+20140??? 3.3
+ - Fix to SCSI Reset handling to avoid lockups
+ - Bug fixes to improve standards compatibility
+ - Bug fix for Unit Attention Condition, which is now enabled by default.
+ - scsi2sd-config can be used to disable it for those systems that
+ truely require it (eg. Mac Plus).
+
20140214 3.2
- Remove hacks around ATN handling, and implement proper select-with-atn
support. This fix is essential for communicating with some SCSI hosts.
/* bEndpointAddress */ 0x82u,\r
/* bmAttributes */ 0x03u,\r
/* wMaxPacketSize */ 0x40u, 0x00u,\r
-/* bInterval */ 0x80u\r
+/* bInterval */ 0x40u\r
};\r
\r
/*********************************************************************\r
#define SCSI_RST_ISR__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
\r
/* SDCard_BSPIM */\r
-#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB06_07_ACTL\r
-#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B1_UDB06_07_ST\r
-#define SDCard_BSPIM_BitCounter_ST__MASK_REG CYREG_B1_UDB06_MSK\r
-#define SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL\r
-#define SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL\r
-#define SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B1_UDB06_ACTL\r
-#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B1_UDB06_ST_CTL\r
-#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B1_UDB06_ST_CTL\r
-#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B1_UDB06_ST\r
-#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB06_07_ACTL\r
-#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB06_07_CTL\r
-#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB06_07_CTL\r
-#define SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB06_07_CTL\r
-#define SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B1_UDB06_07_CTL\r
-#define SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B1_UDB06_07_MSK\r
-#define SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B1_UDB06_07_MSK\r
-#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B1_UDB06_07_MSK\r
-#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB06_07_MSK\r
-#define SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B1_UDB06_ACTL\r
-#define SDCard_BSPIM_BitCounter__CONTROL_REG CYREG_B1_UDB06_CTL\r
-#define SDCard_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B1_UDB06_ST_CTL\r
-#define SDCard_BSPIM_BitCounter__COUNT_REG CYREG_B1_UDB06_CTL\r
-#define SDCard_BSPIM_BitCounter__COUNT_ST_REG CYREG_B1_UDB06_ST_CTL\r
-#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL\r
-#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B1_UDB06_MSK\r
-#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL\r
-#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB06_07_ACTL\r
-#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B0_UDB06_07_ST\r
+#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB06_07_ACTL\r
+#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B0_UDB06_07_ST\r
+#define SDCard_BSPIM_BitCounter_ST__MASK_REG CYREG_B0_UDB06_MSK\r
+#define SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL\r
+#define SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL\r
+#define SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B0_UDB06_ACTL\r
+#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B0_UDB06_ST_CTL\r
+#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B0_UDB06_ST_CTL\r
+#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B0_UDB06_ST\r
+#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB06_07_ACTL\r
+#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB06_07_CTL\r
+#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB06_07_CTL\r
+#define SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB06_07_CTL\r
+#define SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B0_UDB06_07_CTL\r
+#define SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B0_UDB06_07_MSK\r
+#define SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B0_UDB06_07_MSK\r
+#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B0_UDB06_07_MSK\r
+#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB06_07_MSK\r
+#define SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B0_UDB06_ACTL\r
+#define SDCard_BSPIM_BitCounter__CONTROL_REG CYREG_B0_UDB06_CTL\r
+#define SDCard_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B0_UDB06_ST_CTL\r
+#define SDCard_BSPIM_BitCounter__COUNT_REG CYREG_B0_UDB06_CTL\r
+#define SDCard_BSPIM_BitCounter__COUNT_ST_REG CYREG_B0_UDB06_ST_CTL\r
+#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL\r
+#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B0_UDB06_MSK\r
+#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL\r
+#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB07_08_ACTL\r
+#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B0_UDB07_08_ST\r
#define SDCard_BSPIM_RxStsReg__4__MASK 0x10u\r
#define SDCard_BSPIM_RxStsReg__4__POS 4\r
#define SDCard_BSPIM_RxStsReg__5__MASK 0x20u\r
#define SDCard_BSPIM_RxStsReg__6__MASK 0x40u\r
#define SDCard_BSPIM_RxStsReg__6__POS 6\r
#define SDCard_BSPIM_RxStsReg__MASK 0x70u\r
-#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B0_UDB06_MSK\r
-#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB06_ACTL\r
-#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B0_UDB06_ST\r
+#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B0_UDB07_MSK\r
+#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB07_ACTL\r
+#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B0_UDB07_ST\r
#define SDCard_BSPIM_TxStsReg__0__MASK 0x01u\r
#define SDCard_BSPIM_TxStsReg__0__POS 0\r
#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB05_06_ACTL\r
#define SDCard_BSPIM_TxStsReg__4__POS 4\r
#define SDCard_BSPIM_TxStsReg__MASK 0x1Fu\r
#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B0_UDB05_MSK\r
-#define SDCard_BSPIM_TxStsReg__MASK_ST_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL\r
-#define SDCard_BSPIM_TxStsReg__PER_ST_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL\r
#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB05_ACTL\r
-#define SDCard_BSPIM_TxStsReg__STATUS_CNT_REG CYREG_B0_UDB05_ST_CTL\r
-#define SDCard_BSPIM_TxStsReg__STATUS_CONTROL_REG CYREG_B0_UDB05_ST_CTL\r
#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B0_UDB05_ST\r
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B1_UDB06_07_A0\r
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B1_UDB06_07_A1\r
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG CYREG_B1_UDB06_07_D0\r
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG CYREG_B1_UDB06_07_D1\r
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG CYREG_B1_UDB06_07_ACTL\r
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG CYREG_B1_UDB06_07_F0\r
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG CYREG_B1_UDB06_07_F1\r
-#define SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG CYREG_B1_UDB06_A0_A1\r
-#define SDCard_BSPIM_sR8_Dp_u0__A0_REG CYREG_B1_UDB06_A0\r
-#define SDCard_BSPIM_sR8_Dp_u0__A1_REG CYREG_B1_UDB06_A1\r
-#define SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG CYREG_B1_UDB06_D0_D1\r
-#define SDCard_BSPIM_sR8_Dp_u0__D0_REG CYREG_B1_UDB06_D0\r
-#define SDCard_BSPIM_sR8_Dp_u0__D1_REG CYREG_B1_UDB06_D1\r
-#define SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG CYREG_B1_UDB06_ACTL\r
-#define SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG CYREG_B1_UDB06_F0_F1\r
-#define SDCard_BSPIM_sR8_Dp_u0__F0_REG CYREG_B1_UDB06_F0\r
-#define SDCard_BSPIM_sR8_Dp_u0__F1_REG CYREG_B1_UDB06_F1\r
-#define SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL\r
-#define SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL\r
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B0_UDB06_07_A0\r
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B0_UDB06_07_A1\r
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG CYREG_B0_UDB06_07_D0\r
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG CYREG_B0_UDB06_07_D1\r
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG CYREG_B0_UDB06_07_ACTL\r
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG CYREG_B0_UDB06_07_F0\r
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG CYREG_B0_UDB06_07_F1\r
+#define SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG CYREG_B0_UDB06_A0_A1\r
+#define SDCard_BSPIM_sR8_Dp_u0__A0_REG CYREG_B0_UDB06_A0\r
+#define SDCard_BSPIM_sR8_Dp_u0__A1_REG CYREG_B0_UDB06_A1\r
+#define SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG CYREG_B0_UDB06_D0_D1\r
+#define SDCard_BSPIM_sR8_Dp_u0__D0_REG CYREG_B0_UDB06_D0\r
+#define SDCard_BSPIM_sR8_Dp_u0__D1_REG CYREG_B0_UDB06_D1\r
+#define SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG CYREG_B0_UDB06_ACTL\r
+#define SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG CYREG_B0_UDB06_F0_F1\r
+#define SDCard_BSPIM_sR8_Dp_u0__F0_REG CYREG_B0_UDB06_F0\r
+#define SDCard_BSPIM_sR8_Dp_u0__F1_REG CYREG_B0_UDB06_F1\r
+#define SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL\r
+#define SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL\r
\r
/* USBFS_dp_int */\r
#define USBFS_dp_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
/* SCSI_CTL_IO */\r
#define SCSI_CTL_IO_Sync_ctrl_reg__0__MASK 0x01u\r
#define SCSI_CTL_IO_Sync_ctrl_reg__0__POS 0\r
-#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB00_01_ACTL\r
-#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB00_01_CTL\r
-#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB00_01_CTL\r
-#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB00_01_CTL\r
-#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB00_01_CTL\r
-#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB00_01_MSK\r
-#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB00_01_MSK\r
-#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB00_01_MSK\r
-#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB00_01_MSK\r
-#define SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB00_ACTL\r
-#define SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB00_CTL\r
-#define SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB00_ST_CTL\r
-#define SCSI_CTL_IO_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB00_CTL\r
-#define SCSI_CTL_IO_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB00_ST_CTL\r
+#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB11_12_ACTL\r
+#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB11_12_CTL\r
+#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB11_12_CTL\r
+#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB11_12_CTL\r
+#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB11_12_CTL\r
+#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB11_12_MSK\r
+#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB11_12_MSK\r
+#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB11_12_MSK\r
+#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB11_12_MSK\r
+#define SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB11_ACTL\r
+#define SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB11_CTL\r
+#define SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB11_ST_CTL\r
+#define SCSI_CTL_IO_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB11_CTL\r
+#define SCSI_CTL_IO_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB11_ST_CTL\r
#define SCSI_CTL_IO_Sync_ctrl_reg__MASK 0x01u\r
-#define SCSI_CTL_IO_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB00_MSK_ACTL\r
-#define SCSI_CTL_IO_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB00_MSK\r
-#define SCSI_CTL_IO_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB00_MSK_ACTL\r
+#define SCSI_CTL_IO_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL\r
+#define SCSI_CTL_IO_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB11_MSK\r
+#define SCSI_CTL_IO_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL\r
\r
/* SCSI_In_DBx */\r
#define SCSI_In_DBx__0__AG CYREG_PRT12_AG\r
/* scsiTarget */\r
#define scsiTarget_StatusReg__0__MASK 0x01u\r
#define scsiTarget_StatusReg__0__POS 0\r
-#define scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB11_12_ACTL\r
-#define scsiTarget_StatusReg__16BIT_STATUS_REG CYREG_B0_UDB11_12_ST\r
+#define scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB14_15_ACTL\r
+#define scsiTarget_StatusReg__16BIT_STATUS_REG CYREG_B0_UDB14_15_ST\r
#define scsiTarget_StatusReg__1__MASK 0x02u\r
#define scsiTarget_StatusReg__1__POS 1\r
#define scsiTarget_StatusReg__2__MASK 0x04u\r
#define scsiTarget_StatusReg__3__MASK 0x08u\r
#define scsiTarget_StatusReg__3__POS 3\r
#define scsiTarget_StatusReg__MASK 0x0Fu\r
-#define scsiTarget_StatusReg__MASK_REG CYREG_B0_UDB11_MSK\r
-#define scsiTarget_StatusReg__STATUS_AUX_CTL_REG CYREG_B0_UDB11_ACTL\r
-#define scsiTarget_StatusReg__STATUS_REG CYREG_B0_UDB11_ST\r
-#define scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB03_04_ACTL\r
-#define scsiTarget_datapath_PI__16BIT_STATUS_REG CYREG_B0_UDB03_04_ST\r
-#define scsiTarget_datapath_PI__MASK_REG CYREG_B0_UDB03_MSK\r
-#define scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL\r
-#define scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL\r
-#define scsiTarget_datapath_PI__STATUS_AUX_CTL_REG CYREG_B0_UDB03_ACTL\r
-#define scsiTarget_datapath_PI__STATUS_CNT_REG CYREG_B0_UDB03_ST_CTL\r
-#define scsiTarget_datapath_PI__STATUS_CONTROL_REG CYREG_B0_UDB03_ST_CTL\r
-#define scsiTarget_datapath_PI__STATUS_REG CYREG_B0_UDB03_ST\r
-#define scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB03_04_ACTL\r
-#define scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB03_04_CTL\r
-#define scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB03_04_CTL\r
-#define scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB03_04_CTL\r
-#define scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG CYREG_B0_UDB03_04_CTL\r
-#define scsiTarget_datapath_PO__16BIT_MASK_MASK_REG CYREG_B0_UDB03_04_MSK\r
-#define scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG CYREG_B0_UDB03_04_MSK\r
-#define scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG CYREG_B0_UDB03_04_MSK\r
-#define scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB03_04_MSK\r
-#define scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG CYREG_B0_UDB03_ACTL\r
-#define scsiTarget_datapath_PO__CONTROL_REG CYREG_B0_UDB03_CTL\r
-#define scsiTarget_datapath_PO__CONTROL_ST_REG CYREG_B0_UDB03_ST_CTL\r
-#define scsiTarget_datapath_PO__COUNT_REG CYREG_B0_UDB03_CTL\r
-#define scsiTarget_datapath_PO__COUNT_ST_REG CYREG_B0_UDB03_ST_CTL\r
-#define scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL\r
-#define scsiTarget_datapath_PO__PERIOD_REG CYREG_B0_UDB03_MSK\r
-#define scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL\r
-#define scsiTarget_datapath__16BIT_A0_REG CYREG_B0_UDB03_04_A0\r
-#define scsiTarget_datapath__16BIT_A1_REG CYREG_B0_UDB03_04_A1\r
-#define scsiTarget_datapath__16BIT_D0_REG CYREG_B0_UDB03_04_D0\r
-#define scsiTarget_datapath__16BIT_D1_REG CYREG_B0_UDB03_04_D1\r
-#define scsiTarget_datapath__16BIT_DP_AUX_CTL_REG CYREG_B0_UDB03_04_ACTL\r
-#define scsiTarget_datapath__16BIT_F0_REG CYREG_B0_UDB03_04_F0\r
-#define scsiTarget_datapath__16BIT_F1_REG CYREG_B0_UDB03_04_F1\r
-#define scsiTarget_datapath__A0_A1_REG CYREG_B0_UDB03_A0_A1\r
-#define scsiTarget_datapath__A0_REG CYREG_B0_UDB03_A0\r
-#define scsiTarget_datapath__A1_REG CYREG_B0_UDB03_A1\r
-#define scsiTarget_datapath__D0_D1_REG CYREG_B0_UDB03_D0_D1\r
-#define scsiTarget_datapath__D0_REG CYREG_B0_UDB03_D0\r
-#define scsiTarget_datapath__D1_REG CYREG_B0_UDB03_D1\r
-#define scsiTarget_datapath__DP_AUX_CTL_REG CYREG_B0_UDB03_ACTL\r
-#define scsiTarget_datapath__F0_F1_REG CYREG_B0_UDB03_F0_F1\r
-#define scsiTarget_datapath__F0_REG CYREG_B0_UDB03_F0\r
-#define scsiTarget_datapath__F1_REG CYREG_B0_UDB03_F1\r
-#define scsiTarget_datapath__MSK_DP_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL\r
-#define scsiTarget_datapath__PER_DP_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL\r
+#define scsiTarget_StatusReg__MASK_REG CYREG_B0_UDB14_MSK\r
+#define scsiTarget_StatusReg__STATUS_AUX_CTL_REG CYREG_B0_UDB14_ACTL\r
+#define scsiTarget_StatusReg__STATUS_REG CYREG_B0_UDB14_ST\r
+#define scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB13_14_ACTL\r
+#define scsiTarget_datapath_PI__16BIT_STATUS_REG CYREG_B0_UDB13_14_ST\r
+#define scsiTarget_datapath_PI__MASK_REG CYREG_B0_UDB13_MSK\r
+#define scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG CYREG_B0_UDB13_MSK_ACTL\r
+#define scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG CYREG_B0_UDB13_MSK_ACTL\r
+#define scsiTarget_datapath_PI__STATUS_AUX_CTL_REG CYREG_B0_UDB13_ACTL\r
+#define scsiTarget_datapath_PI__STATUS_CNT_REG CYREG_B0_UDB13_ST_CTL\r
+#define scsiTarget_datapath_PI__STATUS_CONTROL_REG CYREG_B0_UDB13_ST_CTL\r
+#define scsiTarget_datapath_PI__STATUS_REG CYREG_B0_UDB13_ST\r
+#define scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB13_14_ACTL\r
+#define scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB13_14_CTL\r
+#define scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB13_14_CTL\r
+#define scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB13_14_CTL\r
+#define scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG CYREG_B0_UDB13_14_CTL\r
+#define scsiTarget_datapath_PO__16BIT_MASK_MASK_REG CYREG_B0_UDB13_14_MSK\r
+#define scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG CYREG_B0_UDB13_14_MSK\r
+#define scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG CYREG_B0_UDB13_14_MSK\r
+#define scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB13_14_MSK\r
+#define scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG CYREG_B0_UDB13_ACTL\r
+#define scsiTarget_datapath_PO__CONTROL_REG CYREG_B0_UDB13_CTL\r
+#define scsiTarget_datapath_PO__CONTROL_ST_REG CYREG_B0_UDB13_ST_CTL\r
+#define scsiTarget_datapath_PO__COUNT_REG CYREG_B0_UDB13_CTL\r
+#define scsiTarget_datapath_PO__COUNT_ST_REG CYREG_B0_UDB13_ST_CTL\r
+#define scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB13_MSK_ACTL\r
+#define scsiTarget_datapath_PO__PERIOD_REG CYREG_B0_UDB13_MSK\r
+#define scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG CYREG_B0_UDB13_MSK_ACTL\r
+#define scsiTarget_datapath__16BIT_A0_REG CYREG_B0_UDB13_14_A0\r
+#define scsiTarget_datapath__16BIT_A1_REG CYREG_B0_UDB13_14_A1\r
+#define scsiTarget_datapath__16BIT_D0_REG CYREG_B0_UDB13_14_D0\r
+#define scsiTarget_datapath__16BIT_D1_REG CYREG_B0_UDB13_14_D1\r
+#define scsiTarget_datapath__16BIT_DP_AUX_CTL_REG CYREG_B0_UDB13_14_ACTL\r
+#define scsiTarget_datapath__16BIT_F0_REG CYREG_B0_UDB13_14_F0\r
+#define scsiTarget_datapath__16BIT_F1_REG CYREG_B0_UDB13_14_F1\r
+#define scsiTarget_datapath__A0_A1_REG CYREG_B0_UDB13_A0_A1\r
+#define scsiTarget_datapath__A0_REG CYREG_B0_UDB13_A0\r
+#define scsiTarget_datapath__A1_REG CYREG_B0_UDB13_A1\r
+#define scsiTarget_datapath__D0_D1_REG CYREG_B0_UDB13_D0_D1\r
+#define scsiTarget_datapath__D0_REG CYREG_B0_UDB13_D0\r
+#define scsiTarget_datapath__D1_REG CYREG_B0_UDB13_D1\r
+#define scsiTarget_datapath__DP_AUX_CTL_REG CYREG_B0_UDB13_ACTL\r
+#define scsiTarget_datapath__F0_F1_REG CYREG_B0_UDB13_F0_F1\r
+#define scsiTarget_datapath__F0_REG CYREG_B0_UDB13_F0\r
+#define scsiTarget_datapath__F1_REG CYREG_B0_UDB13_F1\r
+#define scsiTarget_datapath__MSK_DP_AUX_CTL_REG CYREG_B0_UDB13_MSK_ACTL\r
+#define scsiTarget_datapath__PER_DP_AUX_CTL_REG CYREG_B0_UDB13_MSK_ACTL\r
\r
/* SD_Clk_Ctl */\r
#define SD_Clk_Ctl_Sync_ctrl_reg__0__MASK 0x01u\r
#define SD_Clk_Ctl_Sync_ctrl_reg__0__POS 0\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB05_06_ACTL\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB05_06_CTL\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB05_06_CTL\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB05_06_CTL\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB05_06_CTL\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB05_06_MSK\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB05_06_MSK\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB05_06_MSK\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB05_06_MSK\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB05_ACTL\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB05_CTL\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB05_ST_CTL\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB05_CTL\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB05_ST_CTL\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB10_11_ACTL\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB10_11_CTL\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB10_11_CTL\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB10_11_CTL\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB10_11_CTL\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB10_11_MSK\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB10_11_MSK\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB10_11_MSK\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB10_11_MSK\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB10_ACTL\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB10_CTL\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB10_ST_CTL\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB10_CTL\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB10_ST_CTL\r
#define SD_Clk_Ctl_Sync_ctrl_reg__MASK 0x01u\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB05_MSK\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB10_MSK_ACTL\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB10_MSK\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB10_MSK_ACTL\r
\r
/* USBFS_ep_0 */\r
#define USBFS_ep_0__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
}\r
#endif\r
\r
-#define CY_CFG_BASE_ADDR_COUNT 34u\r
+#define CY_CFG_BASE_ADDR_COUNT 33u\r
CYPACKED typedef struct\r
{\r
uint8 offset;\r
static const uint32 CYCODE cy_cfg_addr_table[] = {\r
0x40004502u, /* Base address: 0x40004500 Count: 2 */\r
0x4000520Au, /* Base address: 0x40005200 Count: 10 */\r
- 0x40006401u, /* Base address: 0x40006400 Count: 1 */\r
- 0x40006501u, /* Base address: 0x40006500 Count: 1 */\r
- 0x40010043u, /* Base address: 0x40010000 Count: 67 */\r
- 0x40010130u, /* Base address: 0x40010100 Count: 48 */\r
- 0x4001023Au, /* Base address: 0x40010200 Count: 58 */\r
- 0x4001034Cu, /* Base address: 0x40010300 Count: 76 */\r
- 0x40010447u, /* Base address: 0x40010400 Count: 71 */\r
- 0x4001054Du, /* Base address: 0x40010500 Count: 77 */\r
- 0x40010649u, /* Base address: 0x40010600 Count: 73 */\r
- 0x40010746u, /* Base address: 0x40010700 Count: 70 */\r
- 0x4001090Du, /* Base address: 0x40010900 Count: 13 */\r
- 0x40010A33u, /* Base address: 0x40010A00 Count: 51 */\r
- 0x40010B38u, /* Base address: 0x40010B00 Count: 56 */\r
- 0x40010D06u, /* Base address: 0x40010D00 Count: 6 */\r
- 0x40010F03u, /* Base address: 0x40010F00 Count: 3 */\r
- 0x40011503u, /* Base address: 0x40011500 Count: 3 */\r
- 0x40011736u, /* Base address: 0x40011700 Count: 54 */\r
- 0x40011902u, /* Base address: 0x40011900 Count: 2 */\r
- 0x40011B02u, /* Base address: 0x40011B00 Count: 2 */\r
- 0x4001400Du, /* Base address: 0x40014000 Count: 13 */\r
+ 0x40006402u, /* Base address: 0x40006400 Count: 2 */\r
+ 0x40010101u, /* Base address: 0x40010100 Count: 1 */\r
+ 0x40010308u, /* Base address: 0x40010300 Count: 8 */\r
+ 0x40010442u, /* Base address: 0x40010400 Count: 66 */\r
+ 0x4001053Cu, /* Base address: 0x40010500 Count: 60 */\r
+ 0x40010604u, /* Base address: 0x40010600 Count: 4 */\r
+ 0x40010747u, /* Base address: 0x40010700 Count: 71 */\r
+ 0x40010908u, /* Base address: 0x40010900 Count: 8 */\r
+ 0x40010A44u, /* Base address: 0x40010A00 Count: 68 */\r
+ 0x40010B40u, /* Base address: 0x40010B00 Count: 64 */\r
+ 0x40010C35u, /* Base address: 0x40010C00 Count: 53 */\r
+ 0x40010D49u, /* Base address: 0x40010D00 Count: 73 */\r
+ 0x40010E43u, /* Base address: 0x40010E00 Count: 67 */\r
+ 0x40010F2Fu, /* Base address: 0x40010F00 Count: 47 */\r
+ 0x40011504u, /* Base address: 0x40011500 Count: 4 */\r
+ 0x40011648u, /* Base address: 0x40011600 Count: 72 */\r
+ 0x40011740u, /* Base address: 0x40011700 Count: 64 */\r
+ 0x40011904u, /* Base address: 0x40011900 Count: 4 */\r
+ 0x4001400Bu, /* Base address: 0x40014000 Count: 11 */\r
0x4001410Fu, /* Base address: 0x40014100 Count: 15 */\r
- 0x4001420Au, /* Base address: 0x40014200 Count: 10 */\r
- 0x40014308u, /* Base address: 0x40014300 Count: 8 */\r
- 0x4001440Bu, /* Base address: 0x40014400 Count: 11 */\r
- 0x40014512u, /* Base address: 0x40014500 Count: 18 */\r
- 0x4001460Cu, /* Base address: 0x40014600 Count: 12 */\r
- 0x40014706u, /* Base address: 0x40014700 Count: 6 */\r
+ 0x40014207u, /* Base address: 0x40014200 Count: 7 */\r
+ 0x40014303u, /* Base address: 0x40014300 Count: 3 */\r
+ 0x4001440Cu, /* Base address: 0x40014400 Count: 12 */\r
+ 0x40014516u, /* Base address: 0x40014500 Count: 22 */\r
+ 0x40014608u, /* Base address: 0x40014600 Count: 8 */\r
+ 0x40014708u, /* Base address: 0x40014700 Count: 8 */\r
0x4001480Au, /* Base address: 0x40014800 Count: 10 */\r
- 0x40014909u, /* Base address: 0x40014900 Count: 9 */\r
- 0x40014C02u, /* Base address: 0x40014C00 Count: 2 */\r
+ 0x4001490Bu, /* Base address: 0x40014900 Count: 11 */\r
+ 0x40014C01u, /* Base address: 0x40014C00 Count: 1 */\r
0x40015006u, /* Base address: 0x40015000 Count: 6 */\r
0x40015101u, /* Base address: 0x40015100 Count: 1 */\r
};\r
{0x36u, 0x02u},\r
{0x7Eu, 0x02u},\r
{0x00u, 0x01u},\r
- {0x01u, 0x01u},\r
- {0x18u, 0x08u},\r
- {0x19u, 0x04u},\r
+ {0x01u, 0x03u},\r
+ {0x18u, 0x04u},\r
+ {0x19u, 0x0Cu},\r
{0x1Cu, 0x61u},\r
{0x20u, 0x98u},\r
- {0x21u, 0x50u},\r
+ {0x21u, 0x38u},\r
{0x30u, 0x03u},\r
- {0x31u, 0x06u},\r
+ {0x31u, 0x05u},\r
{0x7Cu, 0x40u},\r
- {0x33u, 0x03u},\r
+ {0x3Du, 0x03u},\r
{0x86u, 0x0Fu},\r
- {0x06u, 0x44u},\r
- {0x07u, 0x03u},\r
- {0x09u, 0x10u},\r
- {0x10u, 0x44u},\r
- {0x12u, 0x22u},\r
- {0x16u, 0x03u},\r
- {0x17u, 0x04u},\r
+ {0xE2u, 0x80u},\r
+ {0x81u, 0x40u},\r
+ {0x85u, 0x04u},\r
+ {0xA0u, 0x04u},\r
+ {0xACu, 0x04u},\r
+ {0xE2u, 0x08u},\r
+ {0xE6u, 0x25u},\r
+ {0xEAu, 0x01u},\r
+ {0xEEu, 0x02u},\r
+ {0x07u, 0x04u},\r
+ {0x0Bu, 0x04u},\r
+ {0x0Du, 0x04u},\r
+ {0x0Fu, 0x02u},\r
+ {0x13u, 0x03u},\r
{0x19u, 0x04u},\r
- {0x1Au, 0x30u},\r
{0x1Bu, 0x01u},\r
- {0x1Du, 0x08u},\r
- {0x1Eu, 0x40u},\r
- {0x21u, 0x04u},\r
- {0x23u, 0x02u},\r
+ {0x31u, 0x07u},\r
+ {0x56u, 0x08u},\r
+ {0x59u, 0x04u},\r
+ {0x5Bu, 0x04u},\r
+ {0x5Cu, 0x90u},\r
+ {0x5Du, 0x90u},\r
+ {0x5Fu, 0x01u},\r
+ {0x80u, 0xD6u},\r
+ {0x81u, 0x2Cu},\r
+ {0x84u, 0x17u},\r
+ {0x86u, 0x28u},\r
+ {0x88u, 0xD2u},\r
+ {0x89u, 0x31u},\r
+ {0x8Au, 0x04u},\r
+ {0x8Bu, 0x42u},\r
+ {0x8Cu, 0xD6u},\r
+ {0x8Du, 0x2Cu},\r
+ {0x91u, 0xC0u},\r
+ {0x94u, 0x29u},\r
+ {0x96u, 0x46u},\r
+ {0x97u, 0x2Cu},\r
+ {0x98u, 0x20u},\r
+ {0x99u, 0x40u},\r
+ {0x9Au, 0xD0u},\r
+ {0x9Bu, 0x2Fu},\r
+ {0x9Cu, 0x04u},\r
+ {0x9Du, 0x24u},\r
+ {0xA0u, 0xD6u},\r
+ {0xA1u, 0x08u},\r
+ {0xA3u, 0x10u},\r
+ {0xA4u, 0xD0u},\r
+ {0xA5u, 0x24u},\r
+ {0xA6u, 0x06u},\r
+ {0xA7u, 0x08u},\r
+ {0xA8u, 0x21u},\r
+ {0xA9u, 0x11u},\r
+ {0xAAu, 0x8Eu},\r
+ {0xABu, 0x8Eu},\r
+ {0xACu, 0x02u},\r
+ {0xADu, 0x2Cu},\r
+ {0xB0u, 0x01u},\r
+ {0xB1u, 0xC1u},\r
+ {0xB2u, 0x0Fu},\r
+ {0xB3u, 0x31u},\r
+ {0xB4u, 0xF0u},\r
+ {0xB5u, 0x0Fu},\r
+ {0xB6u, 0x08u},\r
+ {0xB8u, 0x08u},\r
+ {0xB9u, 0x02u},\r
+ {0xBAu, 0x20u},\r
+ {0xBBu, 0x0Cu},\r
+ {0xBEu, 0x41u},\r
+ {0xD4u, 0x09u},\r
+ {0xD8u, 0x0Bu},\r
+ {0xD9u, 0x0Bu},\r
+ {0xDBu, 0x0Bu},\r
+ {0xDCu, 0x99u},\r
+ {0xDDu, 0x90u},\r
+ {0xDFu, 0x01u},\r
+ {0x04u, 0x29u},\r
+ {0x06u, 0x02u},\r
+ {0x0Eu, 0x28u},\r
+ {0x0Fu, 0x02u},\r
+ {0x17u, 0x65u},\r
+ {0x1Cu, 0x10u},\r
+ {0x1Du, 0x48u},\r
+ {0x1Eu, 0x28u},\r
+ {0x1Fu, 0x09u},\r
+ {0x21u, 0x02u},\r
+ {0x23u, 0x40u},\r
{0x24u, 0x08u},\r
- {0x28u, 0x44u},\r
- {0x2Au, 0x11u},\r
- {0x2Bu, 0x04u},\r
- {0x2Eu, 0x04u},\r
- {0x31u, 0x10u},\r
- {0x32u, 0x07u},\r
- {0x33u, 0x07u},\r
- {0x34u, 0x70u},\r
- {0x35u, 0x08u},\r
- {0x36u, 0x08u},\r
+ {0x25u, 0x10u},\r
+ {0x26u, 0x02u},\r
+ {0x27u, 0x38u},\r
+ {0x29u, 0xC0u},\r
+ {0x2Du, 0x02u},\r
+ {0x2Fu, 0x2Au},\r
+ {0x31u, 0x02u},\r
+ {0x32u, 0x10u},\r
+ {0x34u, 0x01u},\r
+ {0x36u, 0x02u},\r
+ {0x37u, 0x54u},\r
+ {0x39u, 0x48u},\r
+ {0x3Au, 0x10u},\r
+ {0x3Cu, 0x81u},\r
+ {0x3Du, 0x20u},\r
+ {0x3Eu, 0x01u},\r
+ {0x58u, 0x80u},\r
+ {0x5Du, 0x98u},\r
+ {0x5Eu, 0x02u},\r
+ {0x60u, 0x02u},\r
+ {0x62u, 0x80u},\r
+ {0x65u, 0x08u},\r
+ {0x66u, 0x04u},\r
+ {0x67u, 0x02u},\r
+ {0x7Eu, 0x80u},\r
+ {0x89u, 0x02u},\r
+ {0x8Cu, 0x20u},\r
+ {0x91u, 0x48u},\r
+ {0x92u, 0x20u},\r
+ {0x9Au, 0x10u},\r
+ {0xA0u, 0x04u},\r
+ {0xA4u, 0x10u},\r
+ {0xAEu, 0x10u},\r
+ {0xB0u, 0x10u},\r
+ {0xB6u, 0x10u},\r
+ {0xC0u, 0xF0u},\r
+ {0xC2u, 0xE0u},\r
+ {0xC4u, 0xF0u},\r
+ {0xCAu, 0xF0u},\r
+ {0xCCu, 0xF5u},\r
+ {0xCEu, 0xBEu},\r
+ {0xD6u, 0xF8u},\r
+ {0xD8u, 0x18u},\r
+ {0xDEu, 0x80u},\r
+ {0xE2u, 0x40u},\r
+ {0xE6u, 0x20u},\r
+ {0xEAu, 0x02u},\r
+ {0xEEu, 0x08u},\r
+ {0xD4u, 0x40u},\r
+ {0xDBu, 0x0Bu},\r
+ {0xDDu, 0x90u},\r
+ {0xDFu, 0x01u},\r
+ {0x04u, 0x20u},\r
+ {0x06u, 0x02u},\r
+ {0x07u, 0x60u},\r
+ {0x0Eu, 0xA1u},\r
+ {0x0Fu, 0x04u},\r
+ {0x15u, 0x14u},\r
+ {0x17u, 0x09u},\r
+ {0x1Fu, 0x08u},\r
+ {0x25u, 0x40u},\r
+ {0x26u, 0x40u},\r
+ {0x27u, 0x80u},\r
+ {0x2Cu, 0x80u},\r
+ {0x2Fu, 0x2Au},\r
+ {0x36u, 0x02u},\r
+ {0x37u, 0xA8u},\r
+ {0x3Cu, 0x10u},\r
+ {0x3Du, 0x80u},\r
+ {0x3Eu, 0x01u},\r
+ {0x3Fu, 0x04u},\r
+ {0x45u, 0x88u},\r
+ {0x46u, 0x40u},\r
+ {0x47u, 0x20u},\r
+ {0x4Cu, 0x04u},\r
+ {0x4Du, 0x0Au},\r
+ {0x4Fu, 0x06u},\r
+ {0x55u, 0x20u},\r
+ {0x56u, 0x84u},\r
+ {0x61u, 0x20u},\r
+ {0x62u, 0x08u},\r
+ {0x63u, 0x01u},\r
+ {0x65u, 0x80u},\r
+ {0x6Cu, 0x10u},\r
+ {0x6Du, 0x11u},\r
+ {0x6Eu, 0x09u},\r
+ {0x6Fu, 0x27u},\r
+ {0x74u, 0xC0u},\r
+ {0x76u, 0x02u},\r
+ {0x78u, 0x02u},\r
+ {0x7Eu, 0x80u},\r
+ {0x81u, 0x48u},\r
+ {0x90u, 0x18u},\r
+ {0x92u, 0x80u},\r
+ {0x93u, 0x40u},\r
+ {0x94u, 0x20u},\r
+ {0x96u, 0x01u},\r
+ {0x98u, 0x23u},\r
+ {0x9Bu, 0x38u},\r
+ {0x9Du, 0x02u},\r
+ {0x9Eu, 0x06u},\r
+ {0x9Fu, 0x45u},\r
+ {0xA0u, 0x04u},\r
+ {0xA1u, 0x08u},\r
+ {0xA2u, 0x90u},\r
+ {0xA4u, 0x50u},\r
+ {0xA6u, 0x01u},\r
+ {0xA7u, 0x23u},\r
+ {0xAAu, 0x40u},\r
+ {0xACu, 0x80u},\r
+ {0xB1u, 0x12u},\r
+ {0xC0u, 0xF0u},\r
+ {0xC2u, 0xF0u},\r
+ {0xC4u, 0x70u},\r
+ {0xCAu, 0xF0u},\r
+ {0xCCu, 0xF0u},\r
+ {0xCEu, 0xF0u},\r
+ {0xD0u, 0xF0u},\r
+ {0xD2u, 0x20u},\r
+ {0xD8u, 0x1Eu},\r
+ {0xDEu, 0x81u},\r
+ {0xE8u, 0x40u},\r
+ {0xEEu, 0x03u},\r
+ {0x9Cu, 0x04u},\r
+ {0xA7u, 0x40u},\r
+ {0xAEu, 0x11u},\r
+ {0xB0u, 0x80u},\r
+ {0xB6u, 0x10u},\r
+ {0xE8u, 0x40u},\r
+ {0xEAu, 0x02u},\r
+ {0xEEu, 0x01u},\r
+ {0x04u, 0x24u},\r
+ {0x06u, 0x12u},\r
+ {0x07u, 0x03u},\r
+ {0x0Au, 0x24u},\r
+ {0x0Bu, 0x04u},\r
+ {0x0Eu, 0x03u},\r
+ {0x10u, 0x40u},\r
+ {0x12u, 0x80u},\r
+ {0x13u, 0x20u},\r
+ {0x16u, 0x80u},\r
+ {0x1Au, 0x18u},\r
+ {0x1Bu, 0x24u},\r
+ {0x1Fu, 0x18u},\r
+ {0x21u, 0x40u},\r
+ {0x22u, 0x20u},\r
+ {0x25u, 0x24u},\r
+ {0x26u, 0x04u},\r
+ {0x27u, 0x12u},\r
+ {0x29u, 0x80u},\r
+ {0x2Au, 0x40u},\r
+ {0x2Cu, 0x24u},\r
+ {0x2Du, 0x24u},\r
+ {0x2Eu, 0x09u},\r
+ {0x2Fu, 0x09u},\r
+ {0x30u, 0x07u},\r
+ {0x31u, 0x80u},\r
+ {0x33u, 0x40u},\r
+ {0x34u, 0x38u},\r
+ {0x35u, 0x07u},\r
+ {0x36u, 0xC0u},\r
+ {0x37u, 0x38u},\r
{0x3Eu, 0x40u},\r
- {0x3Fu, 0x11u},\r
+ {0x3Fu, 0x05u},\r
{0x58u, 0x04u},\r
{0x59u, 0x04u},\r
{0x5Bu, 0x04u},\r
{0x5Cu, 0x99u},\r
{0x5Fu, 0x01u},\r
- {0x84u, 0x18u},\r
- {0x86u, 0x60u},\r
- {0x87u, 0x04u},\r
- {0x88u, 0x07u},\r
- {0x8Bu, 0x08u},\r
- {0x8Du, 0x08u},\r
- {0x8Fu, 0x10u},\r
- {0x90u, 0x28u},\r
- {0x92u, 0x50u},\r
- {0x93u, 0x03u},\r
- {0x98u, 0x04u},\r
- {0x9Bu, 0x04u},\r
- {0xA0u, 0x30u},\r
- {0xA2u, 0x48u},\r
- {0xA3u, 0x10u},\r
- {0xA5u, 0x04u},\r
- {0xA6u, 0x02u},\r
- {0xA7u, 0x01u},\r
- {0xA8u, 0x01u},\r
- {0xADu, 0x04u},\r
- {0xAEu, 0x07u},\r
- {0xAFu, 0x02u},\r
- {0xB1u, 0x18u},\r
- {0xB2u, 0x78u},\r
- {0xB4u, 0x07u},\r
- {0xB7u, 0x07u},\r
- {0xBEu, 0x14u},\r
- {0xBFu, 0x01u},\r
- {0xD6u, 0x08u},\r
+ {0x85u, 0x33u},\r
+ {0x86u, 0xFFu},\r
+ {0x87u, 0xCCu},\r
+ {0x89u, 0xFFu},\r
+ {0x8Du, 0x0Fu},\r
+ {0x8Eu, 0xFFu},\r
+ {0x8Fu, 0xF0u},\r
+ {0x90u, 0x96u},\r
+ {0x92u, 0x69u},\r
+ {0x93u, 0xFFu},\r
+ {0x94u, 0xFFu},\r
+ {0x98u, 0x33u},\r
+ {0x9Au, 0xCCu},\r
+ {0x9Du, 0x96u},\r
+ {0x9Fu, 0x69u},\r
+ {0xA0u, 0x55u},\r
+ {0xA1u, 0x55u},\r
+ {0xA2u, 0xAAu},\r
+ {0xA3u, 0xAAu},\r
+ {0xA7u, 0xFFu},\r
+ {0xACu, 0x0Fu},\r
+ {0xAEu, 0xF0u},\r
+ {0xB2u, 0xFFu},\r
+ {0xB3u, 0xFFu},\r
+ {0xBEu, 0x04u},\r
+ {0xBFu, 0x04u},\r
{0xD8u, 0x04u},\r
{0xD9u, 0x04u},\r
{0xDBu, 0x04u},\r
- {0xDCu, 0x90u},\r
- {0xDDu, 0x90u},\r
{0xDFu, 0x01u},\r
- {0x00u, 0x04u},\r
- {0x05u, 0x08u},\r
- {0x06u, 0x08u},\r
- {0x09u, 0x80u},\r
- {0x0Au, 0x54u},\r
- {0x0Cu, 0x02u},\r
- {0x0Eu, 0x08u},\r
- {0x12u, 0x08u},\r
- {0x13u, 0x48u},\r
- {0x14u, 0x08u},\r
- {0x16u, 0x01u},\r
- {0x17u, 0x05u},\r
- {0x19u, 0x08u},\r
- {0x1Au, 0x16u},\r
+ {0x00u, 0x50u},\r
+ {0x03u, 0x20u},\r
+ {0x05u, 0x04u},\r
+ {0x06u, 0x20u},\r
+ {0x07u, 0x01u},\r
+ {0x0Au, 0x64u},\r
+ {0x0Eu, 0x80u},\r
+ {0x0Fu, 0xA4u},\r
+ {0x10u, 0xA5u},\r
+ {0x13u, 0x40u},\r
+ {0x14u, 0x40u},\r
+ {0x15u, 0x40u},\r
+ {0x18u, 0x40u},\r
+ {0x1Au, 0x06u},\r
{0x1Bu, 0x10u},\r
- {0x1Du, 0x18u},\r
- {0x21u, 0x04u},\r
- {0x22u, 0x12u},\r
- {0x24u, 0x40u},\r
- {0x27u, 0x01u},\r
- {0x29u, 0x21u},\r
- {0x2Du, 0x02u},\r
- {0x2Eu, 0x40u},\r
- {0x2Fu, 0x20u},\r
- {0x30u, 0x40u},\r
- {0x31u, 0x24u},\r
- {0x33u, 0x20u},\r
- {0x35u, 0x20u},\r
+ {0x1Fu, 0x04u},\r
+ {0x22u, 0x46u},\r
+ {0x23u, 0x04u},\r
+ {0x25u, 0x08u},\r
+ {0x28u, 0x81u},\r
+ {0x2Au, 0x10u},\r
+ {0x2Bu, 0x20u},\r
+ {0x2Cu, 0x40u},\r
+ {0x2Eu, 0x04u},\r
+ {0x30u, 0x42u},\r
+ {0x31u, 0x20u},\r
+ {0x32u, 0x40u},\r
+ {0x36u, 0x40u},\r
{0x37u, 0x01u},\r
- {0x39u, 0x08u},\r
- {0x3Bu, 0x10u},\r
- {0x3Du, 0x80u},\r
+ {0x39u, 0x10u},\r
+ {0x3Bu, 0x04u},\r
+ {0x3Du, 0x40u},\r
{0x3Eu, 0x20u},\r
{0x3Fu, 0x04u},\r
- {0x5Cu, 0x40u},\r
- {0x67u, 0x02u},\r
- {0x69u, 0x80u},\r
- {0x82u, 0x10u},\r
- {0x83u, 0x01u},\r
- {0xC0u, 0x64u},\r
- {0xC2u, 0x5Fu},\r
- {0xC4u, 0xF7u},\r
- {0xCAu, 0xD5u},\r
- {0xCCu, 0xAEu},\r
+ {0x6Au, 0x40u},\r
+ {0x6Fu, 0x01u},\r
+ {0x8Cu, 0x40u},\r
+ {0x90u, 0x10u},\r
+ {0x91u, 0x50u},\r
+ {0x93u, 0x40u},\r
+ {0x96u, 0x08u},\r
+ {0x97u, 0x0Cu},\r
+ {0x99u, 0x04u},\r
+ {0x9Cu, 0x40u},\r
+ {0x9Fu, 0x01u},\r
+ {0xA0u, 0xA2u},\r
+ {0xA1u, 0x20u},\r
+ {0xA3u, 0x20u},\r
+ {0xA5u, 0x08u},\r
+ {0xA6u, 0x02u},\r
+ {0xA7u, 0x50u},\r
+ {0xADu, 0x50u},\r
+ {0xB2u, 0xC0u},\r
+ {0xB3u, 0x08u},\r
+ {0xB4u, 0x42u},\r
+ {0xC0u, 0xA7u},\r
+ {0xC2u, 0x7Eu},\r
+ {0xC4u, 0x9Fu},\r
+ {0xCAu, 0xCFu},\r
+ {0xCCu, 0x9Du},\r
{0xCEu, 0x76u},\r
- {0xD6u, 0x10u},\r
- {0xD8u, 0x10u},\r
- {0xE4u, 0x04u},\r
- {0x82u, 0x40u},\r
- {0x83u, 0x06u},\r
- {0x84u, 0x16u},\r
- {0x85u, 0x10u},\r
- {0x86u, 0x48u},\r
- {0x8Bu, 0x08u},\r
- {0x8Cu, 0x02u},\r
- {0x8Fu, 0x20u},\r
- {0x90u, 0x67u},\r
- {0x92u, 0x18u},\r
- {0x94u, 0x01u},\r
- {0x96u, 0x02u},\r
- {0x98u, 0x10u},\r
- {0x99u, 0x28u},\r
- {0x9Au, 0x2Du},\r
- {0x9Bu, 0x02u},\r
- {0x9Du, 0x01u},\r
- {0xA0u, 0x80u},\r
- {0xA1u, 0x48u},\r
- {0xA3u, 0x04u},\r
- {0xA4u, 0x02u},\r
- {0xA9u, 0x20u},\r
- {0xABu, 0x08u},\r
- {0xB0u, 0x07u},\r
- {0xB1u, 0x0Eu},\r
- {0xB2u, 0x80u},\r
- {0xB3u, 0x10u},\r
- {0xB4u, 0x70u},\r
- {0xB5u, 0x60u},\r
- {0xB6u, 0x08u},\r
- {0xB7u, 0x01u},\r
- {0xBBu, 0x30u},\r
- {0xBEu, 0x44u},\r
+ {0xE2u, 0x40u},\r
+ {0xEAu, 0x40u},\r
+ {0xECu, 0x80u},\r
+ {0x80u, 0x10u},\r
+ {0x84u, 0x0Eu},\r
+ {0x89u, 0x01u},\r
+ {0x8Au, 0x0Eu},\r
+ {0x8Bu, 0x92u},\r
+ {0x8Cu, 0x04u},\r
+ {0x8Du, 0x19u},\r
+ {0x8Fu, 0xA4u},\r
+ {0x90u, 0x0Cu},\r
+ {0x91u, 0x08u},\r
+ {0x92u, 0x01u},\r
+ {0x94u, 0x02u},\r
+ {0x96u, 0x04u},\r
+ {0x97u, 0x3Fu},\r
+ {0x9Au, 0x0Bu},\r
+ {0xA4u, 0x04u},\r
+ {0xA7u, 0x04u},\r
+ {0xA9u, 0x26u},\r
+ {0xABu, 0x99u},\r
+ {0xADu, 0x40u},\r
+ {0xB0u, 0x10u},\r
+ {0xB1u, 0x38u},\r
+ {0xB3u, 0x40u},\r
+ {0xB4u, 0x0Eu},\r
+ {0xB5u, 0x07u},\r
+ {0xB6u, 0x01u},\r
+ {0xB7u, 0x80u},\r
+ {0xBEu, 0x41u},\r
{0xBFu, 0x44u},\r
- {0xC0u, 0x24u},\r
- {0xC1u, 0x06u},\r
+ {0xC0u, 0x26u},\r
+ {0xC1u, 0x04u},\r
{0xC2u, 0x50u},\r
- {0xC5u, 0xCFu},\r
- {0xC6u, 0xD2u},\r
- {0xC7u, 0x0Eu},\r
+ {0xC5u, 0xD2u},\r
+ {0xC6u, 0xCEu},\r
+ {0xC7u, 0x0Fu},\r
{0xC8u, 0x1Fu},\r
{0xC9u, 0xFFu},\r
{0xCAu, 0xFFu},\r
{0xE8u, 0x40u},\r
{0xE9u, 0x40u},\r
{0xEEu, 0x08u},\r
- {0x00u, 0x88u},\r
+ {0x00u, 0x80u},\r
{0x02u, 0x80u},\r
- {0x09u, 0x04u},\r
- {0x0Au, 0x44u},\r
- {0x11u, 0x02u},\r
+ {0x03u, 0x28u},\r
+ {0x04u, 0x08u},\r
+ {0x07u, 0x10u},\r
+ {0x09u, 0x20u},\r
+ {0x0Bu, 0x60u},\r
{0x12u, 0x10u},\r
- {0x18u, 0x14u},\r
- {0x19u, 0xA1u},\r
- {0x1Au, 0x44u},\r
- {0x1Bu, 0x02u},\r
- {0x20u, 0x08u},\r
- {0x21u, 0x21u},\r
- {0x22u, 0x04u},\r
- {0x23u, 0x01u},\r
- {0x29u, 0x21u},\r
- {0x31u, 0x20u},\r
- {0x33u, 0x40u},\r
- {0x39u, 0xA2u},\r
- {0x3Bu, 0x08u},\r
- {0x40u, 0x04u},\r
- {0x42u, 0x40u},\r
- {0x48u, 0x54u},\r
- {0x49u, 0x80u},\r
- {0x4Au, 0x08u},\r
- {0x52u, 0x94u},\r
- {0x53u, 0x10u},\r
- {0x58u, 0x80u},\r
- {0x5Au, 0x2Au},\r
- {0x60u, 0x10u},\r
- {0x62u, 0x02u},\r
- {0x63u, 0x09u},\r
- {0x68u, 0x80u},\r
- {0x69u, 0x24u},\r
- {0x6Au, 0x80u},\r
- {0x71u, 0x84u},\r
- {0x73u, 0x44u},\r
- {0x81u, 0x05u},\r
- {0x82u, 0x04u},\r
- {0x87u, 0x1Cu},\r
- {0x8Du, 0x10u},\r
- {0x91u, 0x80u},\r
- {0x92u, 0x22u},\r
- {0x93u, 0x02u},\r
- {0x94u, 0x04u},\r
- {0x96u, 0x40u},\r
- {0x97u, 0x54u},\r
- {0x99u, 0x10u},\r
- {0x9Cu, 0x48u},\r
- {0x9Du, 0x25u},\r
- {0x9Eu, 0x29u},\r
- {0x9Fu, 0x0Cu},\r
- {0xA1u, 0x08u},\r
- {0xA2u, 0x02u},\r
- {0xA3u, 0x10u},\r
- {0xA5u, 0xE0u},\r
- {0xA6u, 0x0Cu},\r
- {0xABu, 0x10u},\r
- {0xACu, 0x02u},\r
- {0xADu, 0x04u},\r
- {0xAFu, 0x01u},\r
- {0xB5u, 0x02u},\r
- {0xC0u, 0x0Du},\r
+ {0x13u, 0x08u},\r
+ {0x19u, 0x52u},\r
+ {0x1Bu, 0x20u},\r
+ {0x20u, 0x42u},\r
+ {0x21u, 0x31u},\r
+ {0x22u, 0x08u},\r
+ {0x23u, 0x40u},\r
+ {0x28u, 0x02u},\r
+ {0x29u, 0x18u},\r
+ {0x33u, 0x09u},\r
+ {0x38u, 0x50u},\r
+ {0x39u, 0x20u},\r
+ {0x40u, 0x40u},\r
+ {0x41u, 0x10u},\r
+ {0x48u, 0x41u},\r
+ {0x49u, 0x19u},\r
+ {0x50u, 0x04u},\r
+ {0x52u, 0x10u},\r
+ {0x53u, 0x80u},\r
+ {0x59u, 0x02u},\r
+ {0x5Au, 0xA8u},\r
+ {0x60u, 0x04u},\r
+ {0x62u, 0x4Au},\r
+ {0x68u, 0x82u},\r
+ {0x69u, 0x14u},\r
+ {0x70u, 0x20u},\r
+ {0x72u, 0x80u},\r
+ {0x73u, 0x12u},\r
+ {0x81u, 0x10u},\r
+ {0x84u, 0x01u},\r
+ {0x87u, 0x10u},\r
+ {0x8Bu, 0x11u},\r
+ {0x90u, 0x04u},\r
+ {0x91u, 0x40u},\r
+ {0x92u, 0xA0u},\r
+ {0x95u, 0x26u},\r
+ {0x97u, 0x4Cu},\r
+ {0x99u, 0x04u},\r
+ {0x9Cu, 0x41u},\r
+ {0x9Du, 0x11u},\r
+ {0x9Eu, 0x80u},\r
+ {0x9Fu, 0x1Bu},\r
+ {0xA5u, 0x28u},\r
+ {0xA7u, 0xF0u},\r
+ {0xA8u, 0x40u},\r
+ {0xAAu, 0x10u},\r
+ {0xACu, 0x40u},\r
+ {0xAEu, 0x01u},\r
+ {0xAFu, 0x04u},\r
+ {0xB2u, 0x02u},\r
+ {0xB7u, 0x10u},\r
+ {0xC0u, 0x0Fu},\r
{0xC2u, 0x0Eu},\r
- {0xC4u, 0x0Cu},\r
- {0xCAu, 0x05u},\r
- {0xCCu, 0x0Cu},\r
- {0xCEu, 0x0Fu},\r
+ {0xC4u, 0x04u},\r
+ {0xCAu, 0x0Eu},\r
+ {0xCCu, 0x03u},\r
+ {0xCEu, 0x0Cu},\r
{0xD0u, 0x05u},\r
{0xD2u, 0x0Cu},\r
{0xD6u, 0x0Fu},\r
{0xD8u, 0x0Fu},\r
- {0xE0u, 0x01u},\r
- {0xE2u, 0x4Cu},\r
- {0xE4u, 0x02u},\r
- {0xE6u, 0x09u},\r
- {0xE8u, 0x40u},\r
+ {0xE2u, 0x02u},\r
+ {0xE6u, 0x21u},\r
+ {0xE8u, 0x02u},\r
+ {0xECu, 0x0Cu},\r
+ {0x01u, 0x04u},\r
+ {0x03u, 0x01u},\r
{0x04u, 0x24u},\r
- {0x06u, 0x49u},\r
- {0x0Cu, 0x24u},\r
- {0x0Eu, 0x12u},\r
- {0x0Fu, 0xFFu},\r
- {0x11u, 0xFFu},\r
- {0x12u, 0x04u},\r
- {0x15u, 0x96u},\r
+ {0x05u, 0x10u},\r
+ {0x06u, 0x12u},\r
+ {0x0Bu, 0x04u},\r
+ {0x0Eu, 0x18u},\r
+ {0x0Fu, 0x04u},\r
+ {0x10u, 0x40u},\r
+ {0x13u, 0x03u},\r
+ {0x15u, 0x10u},\r
{0x16u, 0x03u},\r
- {0x17u, 0x69u},\r
- {0x19u, 0x55u},\r
- {0x1Au, 0x64u},\r
- {0x1Bu, 0xAAu},\r
- {0x1Du, 0x33u},\r
- {0x1Eu, 0x18u},\r
- {0x1Fu, 0xCCu},\r
- {0x21u, 0x0Fu},\r
- {0x22u, 0x20u},\r
- {0x23u, 0xF0u},\r
- {0x27u, 0xFFu},\r
+ {0x19u, 0x04u},\r
+ {0x1Au, 0x24u},\r
+ {0x1Bu, 0x02u},\r
+ {0x1Du, 0x10u},\r
+ {0x21u, 0x20u},\r
+ {0x22u, 0x04u},\r
+ {0x26u, 0x20u},\r
+ {0x29u, 0x08u},\r
+ {0x2Cu, 0x24u},\r
+ {0x2Du, 0x10u},\r
+ {0x2Eu, 0x09u},\r
+ {0x30u, 0x38u},\r
+ {0x31u, 0x07u},\r
{0x32u, 0x07u},\r
+ {0x33u, 0x10u},\r
{0x34u, 0x40u},\r
- {0x35u, 0xFFu},\r
- {0x36u, 0x38u},\r
+ {0x35u, 0x08u},\r
+ {0x37u, 0x20u},\r
+ {0x39u, 0x08u},\r
{0x3Eu, 0x10u},\r
- {0x3Fu, 0x10u},\r
+ {0x3Fu, 0x54u},\r
{0x58u, 0x04u},\r
{0x59u, 0x04u},\r
- {0x5Cu, 0x09u},\r
- {0x5Fu, 0x01u},\r
- {0x82u, 0x20u},\r
- {0x84u, 0x11u},\r
- {0x85u, 0x06u},\r
- {0x86u, 0x22u},\r
- {0x89u, 0x20u},\r
- {0x8Au, 0x10u},\r
- {0x8Bu, 0x18u},\r
- {0x8Eu, 0xC0u},\r
- {0x90u, 0x02u},\r
- {0x92u, 0x0Du},\r
- {0x94u, 0x0Du},\r
- {0x95u, 0x49u},\r
- {0x97u, 0x32u},\r
- {0x98u, 0x82u},\r
- {0x99u, 0x59u},\r
- {0x9Au, 0x38u},\r
- {0x9Bu, 0x24u},\r
- {0x9Cu, 0x0Du},\r
- {0xA0u, 0x0Du},\r
- {0xA4u, 0x42u},\r
- {0xA5u, 0x6Au},\r
- {0xA6u, 0x34u},\r
- {0xA7u, 0x11u},\r
- {0xA8u, 0x0Du},\r
- {0xACu, 0x0Du},\r
- {0xB0u, 0x0Fu},\r
- {0xB3u, 0x07u},\r
- {0xB5u, 0x38u},\r
- {0xB6u, 0xF0u},\r
- {0xB7u, 0x40u},\r
- {0xB9u, 0x08u},\r
- {0xBAu, 0x02u},\r
- {0xBBu, 0x20u},\r
- {0xBFu, 0x40u},\r
- {0xD4u, 0x09u},\r
- {0xD8u, 0x08u},\r
- {0xD9u, 0x08u},\r
- {0xDBu, 0x08u},\r
- {0xDCu, 0x99u},\r
- {0xDDu, 0x90u},\r
- {0xDFu, 0x01u},\r
- {0x00u, 0x08u},\r
- {0x03u, 0x02u},\r
- {0x05u, 0x54u},\r
- {0x06u, 0x81u},\r
- {0x0Au, 0xA6u},\r
- {0x0Du, 0x02u},\r
- {0x0Eu, 0x19u},\r
- {0x10u, 0x80u},\r
- {0x12u, 0x10u},\r
- {0x13u, 0x08u},\r
- {0x16u, 0x06u},\r
- {0x17u, 0x05u},\r
- {0x18u, 0x08u},\r
- {0x1Au, 0x22u},\r
- {0x1Du, 0x42u},\r
- {0x21u, 0x20u},\r
- {0x24u, 0x02u},\r
- {0x25u, 0x14u},\r
- {0x27u, 0x08u},\r
- {0x29u, 0x02u},\r
- {0x2Bu, 0x10u},\r
- {0x2Cu, 0x20u},\r
- {0x31u, 0x08u},\r
- {0x32u, 0x91u},\r
- {0x34u, 0x08u},\r
- {0x35u, 0x04u},\r
- {0x36u, 0x20u},\r
- {0x39u, 0x80u},\r
- {0x3Du, 0x28u},\r
- {0x3Eu, 0x08u},\r
- {0x4Cu, 0x01u},\r
- {0x4Du, 0x80u},\r
- {0x5Cu, 0x40u},\r
- {0x5Du, 0x08u},\r
- {0x5Eu, 0x02u},\r
- {0x5Fu, 0x20u},\r
- {0x65u, 0x80u},\r
- {0x6Du, 0x80u},\r
- {0x79u, 0x02u},\r
- {0x7Au, 0x80u},\r
- {0x7Fu, 0x01u},\r
- {0x81u, 0x62u},\r
- {0x88u, 0x41u},\r
- {0x89u, 0x01u},\r
- {0x8Eu, 0x30u},\r
- {0x8Fu, 0x10u},\r
- {0x91u, 0x86u},\r
- {0x92u, 0x84u},\r
- {0x93u, 0x02u},\r
- {0x9Cu, 0x88u},\r
- {0x9Eu, 0x29u},\r
- {0x9Fu, 0x04u},\r
- {0xA0u, 0xC4u},\r
- {0xA1u, 0x08u},\r
- {0xA3u, 0x12u},\r
- {0xA5u, 0x40u},\r
- {0xA6u, 0x04u},\r
- {0xA7u, 0x04u},\r
- {0xA9u, 0x40u},\r
- {0xABu, 0x40u},\r
- {0xACu, 0x40u},\r
- {0xAFu, 0x10u},\r
- {0xB0u, 0x10u},\r
- {0xC0u, 0xF5u},\r
- {0xC2u, 0xFFu},\r
- {0xC4u, 0xF8u},\r
- {0xCAu, 0x43u},\r
- {0xCCu, 0x6Fu},\r
- {0xCEu, 0x68u},\r
- {0xD6u, 0xF0u},\r
- {0xD8u, 0x10u},\r
- {0xDEu, 0x10u},\r
- {0xE0u, 0x05u},\r
- {0xE4u, 0x44u},\r
- {0xE6u, 0x02u},\r
- {0xEAu, 0x08u},\r
- {0xEEu, 0x09u},\r
- {0x00u, 0x01u},\r
- {0x01u, 0x86u},\r
- {0x04u, 0x07u},\r
- {0x05u, 0x04u},\r
- {0x06u, 0x18u},\r
- {0x07u, 0x40u},\r
- {0x08u, 0x01u},\r
- {0x0Bu, 0x86u},\r
- {0x0Cu, 0x04u},\r
- {0x0Du, 0x86u},\r
- {0x10u, 0x10u},\r
- {0x11u, 0x82u},\r
- {0x12u, 0x40u},\r
- {0x15u, 0x69u},\r
- {0x17u, 0x06u},\r
- {0x18u, 0x22u},\r
- {0x19u, 0x82u},\r
- {0x1Au, 0x08u},\r
- {0x1Bu, 0x04u},\r
- {0x1Cu, 0x01u},\r
- {0x1Du, 0x10u},\r
- {0x20u, 0x01u},\r
- {0x21u, 0x10u},\r
- {0x24u, 0x08u},\r
- {0x25u, 0x01u},\r
- {0x26u, 0x21u},\r
- {0x27u, 0xAEu},\r
- {0x29u, 0xE7u},\r
- {0x2Bu, 0x08u},\r
- {0x2Cu, 0x01u},\r
- {0x2Du, 0x86u},\r
- {0x30u, 0x08u},\r
- {0x31u, 0x10u},\r
- {0x33u, 0xE0u},\r
- {0x34u, 0x40u},\r
- {0x35u, 0x0Fu},\r
- {0x36u, 0x3Fu},\r
- {0x38u, 0x80u},\r
- {0x39u, 0x22u},\r
- {0x3Bu, 0x0Cu},\r
- {0x3Eu, 0x41u},\r
- {0x54u, 0x40u},\r
- {0x58u, 0x08u},\r
- {0x59u, 0x08u},\r
- {0x5Bu, 0x08u},\r
+ {0x5Bu, 0x04u},\r
{0x5Cu, 0x99u},\r
- {0x5Du, 0x90u},\r
{0x5Fu, 0x01u},\r
- {0x82u, 0x03u},\r
- {0x84u, 0x04u},\r
- {0x86u, 0x01u},\r
- {0x8Cu, 0x04u},\r
- {0x8Eu, 0x02u},\r
- {0x8Fu, 0xFFu},\r
+ {0x85u, 0x33u},\r
+ {0x86u, 0xFFu},\r
+ {0x87u, 0xCCu},\r
+ {0x89u, 0xFFu},\r
+ {0x8Du, 0x0Fu},\r
+ {0x8Eu, 0xFFu},\r
+ {0x8Fu, 0xF0u},\r
+ {0x90u, 0x69u},\r
+ {0x92u, 0x96u},\r
{0x93u, 0xFFu},\r
- {0x95u, 0x69u},\r
- {0x97u, 0x96u},\r
- {0x99u, 0x55u},\r
- {0x9Au, 0x04u},\r
- {0x9Bu, 0xAAu},\r
- {0x9Du, 0x33u},\r
- {0x9Fu, 0xCCu},\r
- {0xA1u, 0x0Fu},\r
- {0xA3u, 0xF0u},\r
- {0xA6u, 0x04u},\r
- {0xA7u, 0xFFu},\r
- {0xB0u, 0x07u},\r
+ {0x96u, 0xFFu},\r
+ {0x98u, 0x33u},\r
+ {0x9Au, 0xCCu},\r
+ {0x9Du, 0x69u},\r
+ {0x9Fu, 0x96u},\r
+ {0xA0u, 0x55u},\r
+ {0xA1u, 0x55u},\r
+ {0xA2u, 0xAAu},\r
+ {0xA3u, 0xAAu},\r
+ {0xA9u, 0xFFu},\r
+ {0xACu, 0x0Fu},\r
+ {0xAEu, 0xF0u},\r
+ {0xB0u, 0xFFu},\r
{0xB7u, 0xFFu},\r
+ {0xBEu, 0x01u},\r
{0xBFu, 0x40u},\r
{0xD8u, 0x04u},\r
{0xD9u, 0x04u},\r
- {0xDCu, 0x09u},\r
{0xDFu, 0x01u},\r
- {0x00u, 0x08u},\r
- {0x01u, 0x02u},\r
- {0x03u, 0x02u},\r
- {0x04u, 0xA0u},\r
- {0x05u, 0x05u},\r
- {0x06u, 0x04u},\r
- {0x0Au, 0x04u},\r
- {0x0Cu, 0x20u},\r
- {0x0Eu, 0x09u},\r
- {0x0Fu, 0x80u},\r
+ {0x00u, 0x40u},\r
+ {0x01u, 0x40u},\r
+ {0x03u, 0x20u},\r
+ {0x05u, 0x04u},\r
+ {0x07u, 0x01u},\r
+ {0x08u, 0x01u},\r
+ {0x09u, 0x20u},\r
+ {0x0Au, 0x10u},\r
+ {0x0Cu, 0x08u},\r
+ {0x0Eu, 0x80u},\r
+ {0x0Fu, 0xA4u},\r
{0x11u, 0x04u},\r
- {0x16u, 0x02u},\r
- {0x17u, 0x05u},\r
- {0x19u, 0x02u},\r
- {0x1Cu, 0x40u},\r
- {0x1Du, 0x10u},\r
- {0x1Fu, 0x40u},\r
- {0x20u, 0x02u},\r
- {0x24u, 0x80u},\r
- {0x25u, 0x20u},\r
- {0x26u, 0x2Eu},\r
- {0x27u, 0x04u},\r
- {0x29u, 0x02u},\r
- {0x2Bu, 0x10u},\r
- {0x2Cu, 0x20u},\r
- {0x2Du, 0x80u},\r
- {0x2Fu, 0x48u},\r
- {0x31u, 0x08u},\r
- {0x32u, 0x91u},\r
- {0x35u, 0x01u},\r
- {0x37u, 0x54u},\r
- {0x39u, 0x80u},\r
- {0x3Du, 0x80u},\r
- {0x3Eu, 0x19u},\r
- {0x46u, 0x08u},\r
- {0x47u, 0x20u},\r
- {0x66u, 0x20u},\r
- {0x67u, 0x21u},\r
- {0x7Fu, 0x01u},\r
- {0x8Eu, 0x24u},\r
- {0x91u, 0x84u},\r
- {0x92u, 0x26u},\r
- {0x93u, 0x02u},\r
- {0x94u, 0x40u},\r
- {0x96u, 0x11u},\r
- {0x9Au, 0x10u},\r
- {0x9Du, 0x1Eu},\r
- {0x9Eu, 0x86u},\r
- {0x9Fu, 0x25u},\r
- {0xA0u, 0x04u},\r
- {0xA1u, 0x08u},\r
- {0xA2u, 0x80u},\r
- {0xA3u, 0x12u},\r
- {0xA4u, 0x21u},\r
- {0xA6u, 0x25u},\r
- {0xA8u, 0x04u},\r
- {0xABu, 0x04u},\r
- {0xACu, 0x80u},\r
- {0xB1u, 0x08u},\r
+ {0x13u, 0x42u},\r
+ {0x14u, 0x40u},\r
+ {0x15u, 0x40u},\r
+ {0x18u, 0x44u},\r
+ {0x19u, 0x04u},\r
+ {0x1Au, 0x10u},\r
+ {0x1Fu, 0x02u},\r
+ {0x22u, 0x55u},\r
+ {0x26u, 0x80u},\r
+ {0x2Au, 0x22u},\r
+ {0x2Bu, 0x02u},\r
+ {0x2Cu, 0x48u},\r
+ {0x31u, 0x18u},\r
+ {0x32u, 0x81u},\r
+ {0x36u, 0x40u},\r
+ {0x37u, 0x01u},\r
+ {0x39u, 0x22u},\r
+ {0x3Au, 0x80u},\r
+ {0x3Bu, 0x08u},\r
+ {0x3Cu, 0x40u},\r
+ {0x3Eu, 0x10u},\r
+ {0x3Fu, 0x04u},\r
+ {0x43u, 0xC0u},\r
+ {0x59u, 0x01u},\r
+ {0x5Bu, 0x58u},\r
+ {0x86u, 0x20u},\r
+ {0x8Au, 0x04u},\r
+ {0xC0u, 0xA5u},\r
+ {0xC2u, 0x7Eu},\r
+ {0xC4u, 0x9Du},\r
+ {0xCAu, 0xADu},\r
+ {0xCCu, 0x9Fu},\r
+ {0xCEu, 0x7Fu},\r
+ {0xD6u, 0x0Fu},\r
+ {0xE2u, 0x88u},\r
+ {0x80u, 0x01u},\r
+ {0x90u, 0x02u},\r
{0xB2u, 0x01u},\r
- {0xC0u, 0xFDu},\r
- {0xC2u, 0xD2u},\r
- {0xC4u, 0xB4u},\r
- {0xCAu, 0xF3u},\r
- {0xCCu, 0xFFu},\r
- {0xCEu, 0xF8u},\r
- {0xD8u, 0x70u},\r
- {0xDEu, 0x10u},\r
- {0xEAu, 0x80u},\r
- {0xEEu, 0x06u},\r
- {0x8Du, 0x08u},\r
- {0x8Fu, 0x02u},\r
- {0x9Du, 0x28u},\r
- {0x9Fu, 0x02u},\r
- {0xA8u, 0x40u},\r
- {0xAEu, 0x28u},\r
- {0xB0u, 0x08u},\r
- {0xB2u, 0x18u},\r
- {0xB3u, 0x10u},\r
- {0xE0u, 0x50u},\r
- {0xE8u, 0x20u},\r
- {0xEAu, 0x88u},\r
- {0xECu, 0x20u},\r
- {0x08u, 0xFFu},\r
- {0x14u, 0xFFu},\r
- {0x15u, 0x02u},\r
- {0x1Au, 0xFFu},\r
- {0x1Cu, 0x33u},\r
- {0x1Eu, 0xCCu},\r
- {0x20u, 0x55u},\r
- {0x21u, 0x01u},\r
- {0x22u, 0xAAu},\r
- {0x28u, 0x69u},\r
- {0x2Au, 0x96u},\r
- {0x2Cu, 0x0Fu},\r
- {0x2Eu, 0xF0u},\r
- {0x31u, 0x02u},\r
- {0x35u, 0x01u},\r
- {0x36u, 0xFFu},\r
+ {0xEAu, 0x20u},\r
+ {0x01u, 0x05u},\r
+ {0x02u, 0x01u},\r
+ {0x05u, 0x09u},\r
+ {0x06u, 0x0Cu},\r
+ {0x07u, 0x02u},\r
+ {0x08u, 0x01u},\r
+ {0x0Au, 0x02u},\r
+ {0x0Bu, 0x38u},\r
+ {0x0Eu, 0x10u},\r
+ {0x0Fu, 0x04u},\r
+ {0x13u, 0x05u},\r
+ {0x14u, 0x04u},\r
+ {0x15u, 0x05u},\r
+ {0x16u, 0x03u},\r
+ {0x18u, 0x10u},\r
+ {0x19u, 0x23u},\r
+ {0x1Cu, 0x10u},\r
+ {0x1Du, 0x02u},\r
+ {0x1Fu, 0x01u},\r
+ {0x20u, 0x10u},\r
+ {0x21u, 0x05u},\r
+ {0x24u, 0x10u},\r
+ {0x25u, 0x05u},\r
+ {0x28u, 0x08u},\r
+ {0x29u, 0x02u},\r
+ {0x2Au, 0x03u},\r
+ {0x2Bu, 0x11u},\r
+ {0x2Du, 0x38u},\r
+ {0x2Eu, 0x22u},\r
+ {0x30u, 0x20u},\r
+ {0x31u, 0x03u},\r
+ {0x32u, 0x0Fu},\r
+ {0x33u, 0x04u},\r
+ {0x36u, 0x10u},\r
+ {0x37u, 0x38u},\r
+ {0x3Bu, 0x02u},\r
{0x3Eu, 0x40u},\r
- {0x3Fu, 0x11u},\r
- {0x58u, 0x04u},\r
- {0x59u, 0x04u},\r
+ {0x3Fu, 0x44u},\r
+ {0x58u, 0x0Bu},\r
+ {0x59u, 0x0Bu},\r
+ {0x5Cu, 0x99u},\r
{0x5Fu, 0x01u},\r
- {0x84u, 0x06u},\r
- {0x85u, 0x0Fu},\r
- {0x87u, 0xF0u},\r
- {0x8Au, 0x03u},\r
- {0x8Bu, 0xFFu},\r
- {0x8Eu, 0x05u},\r
- {0x91u, 0xFFu},\r
- {0x95u, 0x55u},\r
- {0x96u, 0x01u},\r
- {0x97u, 0xAAu},\r
- {0x98u, 0x08u},\r
- {0x99u, 0x33u},\r
- {0x9Bu, 0xCCu},\r
- {0x9Cu, 0x08u},\r
- {0xA0u, 0x08u},\r
- {0xA4u, 0x08u},\r
- {0xA7u, 0xFFu},\r
- {0xA9u, 0x96u},\r
- {0xABu, 0x69u},\r
- {0xB0u, 0x08u},\r
- {0xB2u, 0x07u},\r
- {0xB5u, 0xFFu},\r
- {0xB8u, 0x02u},\r
- {0xBEu, 0x01u},\r
- {0xBFu, 0x10u},\r
+ {0x84u, 0x18u},\r
+ {0x86u, 0x60u},\r
+ {0x87u, 0x06u},\r
+ {0x8Cu, 0x04u},\r
+ {0x8Eu, 0x03u},\r
+ {0x93u, 0x02u},\r
+ {0x94u, 0x03u},\r
+ {0x96u, 0x04u},\r
+ {0x97u, 0x0Au},\r
+ {0x98u, 0x30u},\r
+ {0x99u, 0x0Cu},\r
+ {0x9Au, 0x48u},\r
+ {0x9Du, 0x01u},\r
+ {0xA4u, 0x01u},\r
+ {0xA6u, 0x06u},\r
+ {0xA8u, 0x05u},\r
+ {0xAAu, 0x02u},\r
+ {0xACu, 0x28u},\r
+ {0xAEu, 0x50u},\r
+ {0xB1u, 0x0Eu},\r
+ {0xB3u, 0x01u},\r
+ {0xB4u, 0x78u},\r
+ {0xB6u, 0x07u},\r
+ {0xBAu, 0x80u},\r
+ {0xBEu, 0x10u},\r
+ {0xBFu, 0x04u},\r
{0xD8u, 0x0Bu},\r
- {0xD9u, 0x04u},\r
- {0xDBu, 0x04u},\r
- {0xDCu, 0x09u},\r
+ {0xD9u, 0x0Bu},\r
+ {0xDCu, 0x99u},\r
{0xDFu, 0x01u},\r
- {0x00u, 0x10u},\r
- {0x05u, 0x28u},\r
- {0x07u, 0x02u},\r
- {0x09u, 0x10u},\r
- {0x0Au, 0x02u},\r
- {0x0Bu, 0x20u},\r
- {0x0Du, 0x20u},\r
- {0x0Eu, 0x21u},\r
- {0x10u, 0x08u},\r
- {0x11u, 0x40u},\r
- {0x12u, 0x80u},\r
- {0x14u, 0x40u},\r
- {0x16u, 0x20u},\r
- {0x1Au, 0x01u},\r
- {0x1Eu, 0xA0u},\r
- {0x20u, 0x40u},\r
- {0x22u, 0x20u},\r
- {0x25u, 0x20u},\r
- {0x28u, 0x80u},\r
- {0x2Cu, 0x08u},\r
- {0x2Eu, 0x08u},\r
- {0x32u, 0x08u},\r
- {0x34u, 0x18u},\r
- {0x36u, 0x01u},\r
- {0x3Du, 0x20u},\r
- {0x3Fu, 0x08u},\r
- {0x5Cu, 0x02u},\r
- {0x5Fu, 0x94u},\r
- {0x7Fu, 0x80u},\r
- {0x81u, 0x50u},\r
- {0x82u, 0x20u},\r
- {0x83u, 0x04u},\r
- {0x86u, 0x40u},\r
- {0x88u, 0x50u},\r
- {0x8Au, 0x01u},\r
- {0x8Bu, 0x04u},\r
- {0x8Cu, 0x18u},\r
- {0x8Eu, 0x81u},\r
- {0x93u, 0x10u},\r
- {0x98u, 0x82u},\r
- {0x9Bu, 0x80u},\r
- {0xA3u, 0x80u},\r
- {0xB3u, 0x10u},\r
- {0xC0u, 0xE2u},\r
- {0xC2u, 0xE7u},\r
- {0xC4u, 0x3Bu},\r
- {0xCAu, 0x61u},\r
- {0xCCu, 0xE2u},\r
- {0xCEu, 0x60u},\r
- {0xD6u, 0xF0u},\r
- {0xDEu, 0x80u},\r
- {0xE0u, 0xF0u},\r
- {0xE4u, 0x24u},\r
- {0xEAu, 0x08u},\r
- {0xECu, 0x80u},\r
- {0xEEu, 0x09u},\r
- {0x83u, 0x80u},\r
- {0x84u, 0x02u},\r
- {0x98u, 0x80u},\r
- {0xA3u, 0x80u},\r
- {0xE2u, 0x0Cu},\r
- {0xE6u, 0x09u},\r
- {0x83u, 0x80u},\r
- {0x84u, 0x80u},\r
- {0xE6u, 0x02u},\r
- {0x80u, 0x01u},\r
- {0x94u, 0x02u},\r
- {0xB5u, 0x04u},\r
+ {0x00u, 0x08u},\r
+ {0x01u, 0x80u},\r
{0x05u, 0x05u},\r
- {0x06u, 0x0Au},\r
- {0x0Eu, 0x99u},\r
- {0x15u, 0x01u},\r
+ {0x06u, 0x20u},\r
+ {0x07u, 0x09u},\r
+ {0x08u, 0x20u},\r
+ {0x09u, 0x08u},\r
+ {0x0Cu, 0x80u},\r
+ {0x0Eu, 0x28u},\r
+ {0x11u, 0x04u},\r
+ {0x13u, 0x60u},\r
+ {0x15u, 0x41u},\r
{0x17u, 0x14u},\r
- {0x1Du, 0x8Du},\r
+ {0x18u, 0x04u},\r
+ {0x19u, 0x80u},\r
+ {0x1Du, 0x85u},\r
{0x1Eu, 0x02u},\r
- {0x1Fu, 0x1Au},\r
+ {0x20u, 0x20u},\r
+ {0x22u, 0x01u},\r
+ {0x24u, 0x02u},\r
+ {0x26u, 0x0Au},\r
{0x27u, 0x40u},\r
- {0x2Eu, 0x02u},\r
- {0x2Fu, 0x0Au},\r
- {0x36u, 0x6Au},\r
- {0x3Eu, 0x15u},\r
- {0x3Fu, 0x80u},\r
- {0x45u, 0xA8u},\r
- {0x4Cu, 0x01u},\r
- {0x4Du, 0x09u},\r
- {0x4Eu, 0x08u},\r
- {0x4Fu, 0x01u},\r
- {0x56u, 0xA8u},\r
- {0x57u, 0x40u},\r
- {0x66u, 0x10u},\r
- {0x6Cu, 0x10u},\r
- {0x6Du, 0x80u},\r
- {0x6Eu, 0x95u},\r
- {0x6Fu, 0x11u},\r
- {0x75u, 0x80u},\r
- {0x76u, 0x02u},\r
- {0x7Fu, 0x01u},\r
- {0x93u, 0x02u},\r
- {0x94u, 0x20u},\r
- {0x96u, 0x11u},\r
- {0x97u, 0x21u},\r
- {0x9Au, 0x10u},\r
- {0x9Bu, 0x04u},\r
- {0x9Du, 0x8Du},\r
- {0x9Eu, 0xAAu},\r
- {0x9Fu, 0x51u},\r
- {0xA1u, 0x20u},\r
- {0xA2u, 0x2Eu},\r
- {0xA5u, 0x40u},\r
- {0xA6u, 0x01u},\r
- {0xA7u, 0x48u},\r
- {0xC0u, 0xF0u},\r
- {0xC2u, 0xF0u},\r
- {0xC4u, 0x70u},\r
- {0xCAu, 0xB0u},\r
- {0xCCu, 0xF0u},\r
- {0xCEu, 0xF0u},\r
- {0xD0u, 0x70u},\r
- {0xD2u, 0x30u},\r
- {0xD8u, 0x20u},\r
- {0xDEu, 0x10u},\r
- {0xEEu, 0x0Au},\r
- {0x9Du, 0x20u},\r
- {0xEEu, 0x0Au},\r
- {0xB5u, 0x20u},\r
- {0xE8u, 0x10u},\r
- {0x33u, 0x80u},\r
+ {0x2Cu, 0x81u},\r
+ {0x2Fu, 0x28u},\r
+ {0x31u, 0x08u},\r
+ {0x32u, 0x41u},\r
+ {0x33u, 0x18u},\r
+ {0x37u, 0x65u},\r
+ {0x38u, 0x08u},\r
+ {0x3Du, 0x05u},\r
+ {0x3Eu, 0xA0u},\r
+ {0x78u, 0x02u},\r
+ {0x7Eu, 0x80u},\r
+ {0x90u, 0x08u},\r
+ {0x91u, 0x45u},\r
+ {0x92u, 0x80u},\r
+ {0x93u, 0x40u},\r
+ {0x94u, 0x04u},\r
+ {0x98u, 0x23u},\r
+ {0x9Au, 0x80u},\r
+ {0x9Bu, 0x3Du},\r
+ {0x9Du, 0x80u},\r
+ {0x9Fu, 0x40u},\r
+ {0xA0u, 0x84u},\r
+ {0xA1u, 0x08u},\r
+ {0xA2u, 0x94u},\r
+ {0xA3u, 0x20u},\r
+ {0xA4u, 0x10u},\r
+ {0xA5u, 0x80u},\r
+ {0xA6u, 0x0Bu},\r
+ {0xA8u, 0x04u},\r
+ {0xAEu, 0x40u},\r
+ {0xB6u, 0x80u},\r
+ {0xB7u, 0x01u},\r
+ {0xC0u, 0xF5u},\r
+ {0xC2u, 0xE6u},\r
+ {0xC4u, 0xF7u},\r
+ {0xCAu, 0xF0u},\r
+ {0xCCu, 0xFFu},\r
+ {0xCEu, 0xF2u},\r
+ {0xDEu, 0x81u},\r
+ {0xE8u, 0x04u},\r
+ {0xECu, 0x80u},\r
+ {0xEEu, 0x02u},\r
+ {0xABu, 0x40u},\r
+ {0xB0u, 0x04u},\r
+ {0xECu, 0x80u},\r
+ {0xEEu, 0x02u},\r
+ {0x33u, 0x40u},\r
{0x36u, 0x40u},\r
- {0x56u, 0x08u},\r
- {0x58u, 0x04u},\r
- {0x5Eu, 0x02u},\r
- {0x62u, 0x02u},\r
- {0x66u, 0x04u},\r
- {0x82u, 0x04u},\r
+ {0x58u, 0x08u},\r
+ {0x5Cu, 0x01u},\r
+ {0x5Du, 0x10u},\r
+ {0x61u, 0x08u},\r
+ {0x64u, 0x10u},\r
+ {0x89u, 0x10u},\r
{0xCCu, 0x30u},\r
- {0xD4u, 0x40u},\r
- {0xD6u, 0xC0u},\r
+ {0xD6u, 0xE0u},\r
{0xD8u, 0xC0u},\r
- {0xE2u, 0x80u},\r
- {0x52u, 0x20u},\r
+ {0x59u, 0x40u},\r
{0x5Fu, 0x20u},\r
- {0x8Fu, 0x04u},\r
- {0x94u, 0x02u},\r
- {0x9Eu, 0x08u},\r
+ {0x83u, 0x40u},\r
+ {0x8Bu, 0x20u},\r
+ {0x9Cu, 0x08u},\r
+ {0x9Fu, 0x40u},\r
+ {0xA5u, 0x08u},\r
{0xA6u, 0x40u},\r
- {0xA7u, 0x80u},\r
- {0xAAu, 0x01u},\r
- {0xACu, 0x04u},\r
- {0xAEu, 0x02u},\r
- {0xB4u, 0x01u},\r
- {0xD4u, 0x20u},\r
+ {0xA8u, 0x01u},\r
+ {0xACu, 0x10u},\r
+ {0xD4u, 0x80u},\r
{0xD6u, 0x20u},\r
- {0xEAu, 0x50u},\r
- {0xEEu, 0x80u},\r
- {0x86u, 0x08u},\r
- {0x8Eu, 0x08u},\r
- {0x94u, 0x02u},\r
- {0x9Eu, 0x08u},\r
- {0xA3u, 0x04u},\r
- {0xA6u, 0x60u},\r
- {0xA7u, 0x80u},\r
- {0xABu, 0x20u},\r
- {0xE6u, 0x40u},\r
+ {0xE6u, 0x80u},\r
{0xEAu, 0x80u},\r
+ {0xEEu, 0x40u},\r
+ {0x89u, 0x08u},\r
+ {0x8Cu, 0x08u},\r
+ {0x9Cu, 0x08u},\r
+ {0xA5u, 0x08u},\r
+ {0xA6u, 0x40u},\r
+ {0xADu, 0x40u},\r
+ {0xEEu, 0x10u},\r
{0x94u, 0x02u},\r
- {0x98u, 0x20u},\r
- {0xA3u, 0x04u},\r
- {0xA6u, 0x48u},\r
- {0xA7u, 0x80u},\r
- {0xAAu, 0x20u},\r
- {0xB0u, 0x20u},\r
- {0xEEu, 0x80u},\r
- {0x0Cu, 0x02u},\r
- {0x12u, 0x20u},\r
- {0x53u, 0x80u},\r
- {0x55u, 0x80u},\r
- {0x58u, 0x80u},\r
- {0x5Cu, 0x40u},\r
- {0x86u, 0x20u},\r
- {0xC2u, 0x04u},\r
+ {0xA6u, 0x40u},\r
+ {0xB4u, 0x01u},\r
+ {0x08u, 0x80u},\r
+ {0x0Fu, 0x40u},\r
+ {0x12u, 0x80u},\r
+ {0x53u, 0x04u},\r
+ {0x57u, 0x80u},\r
+ {0x5Bu, 0x20u},\r
+ {0x5Cu, 0x10u},\r
+ {0x84u, 0x80u},\r
+ {0xC2u, 0x06u},\r
{0xC4u, 0x08u},\r
{0xD4u, 0x07u},\r
{0xD6u, 0x04u},\r
{0x01u, 0x20u},\r
- {0x06u, 0x40u},\r
- {0x07u, 0x08u},\r
- {0x08u, 0x02u},\r
- {0x0Bu, 0x08u},\r
- {0x0Du, 0x04u},\r
- {0x0Fu, 0x02u},\r
- {0x80u, 0x02u},\r
- {0x81u, 0x20u},\r
- {0x85u, 0x04u},\r
- {0x87u, 0x04u},\r
- {0x94u, 0x40u},\r
- {0x9Cu, 0x80u},\r
- {0xA0u, 0x02u},\r
- {0xA5u, 0x80u},\r
- {0xA7u, 0x80u},\r
+ {0x06u, 0x80u},\r
+ {0x07u, 0x01u},\r
+ {0x09u, 0x01u},\r
+ {0x0Au, 0x02u},\r
+ {0x0Cu, 0x80u},\r
+ {0x0Eu, 0x20u},\r
+ {0x82u, 0x40u},\r
+ {0x87u, 0x01u},\r
+ {0x8Bu, 0x40u},\r
+ {0x93u, 0x40u},\r
+ {0x98u, 0x80u},\r
+ {0xA4u, 0x80u},\r
+ {0xABu, 0x80u},\r
+ {0xAFu, 0x24u},\r
+ {0xB2u, 0x80u},\r
+ {0xB4u, 0x10u},\r
{0xC0u, 0x07u},\r
{0xC2u, 0x0Fu},\r
- {0x80u, 0x40u},\r
- {0x88u, 0x80u},\r
- {0x8Fu, 0x80u},\r
- {0x94u, 0x40u},\r
- {0x9Bu, 0x08u},\r
- {0x9Cu, 0x80u},\r
- {0xA5u, 0x80u},\r
- {0xA7u, 0x80u},\r
- {0xA8u, 0x02u},\r
- {0xAEu, 0x40u},\r
- {0xAFu, 0x01u},\r
- {0xE0u, 0x06u},\r
- {0x08u, 0x08u},\r
+ {0xE2u, 0x04u},\r
+ {0xE8u, 0x08u},\r
+ {0xEAu, 0x01u},\r
+ {0x92u, 0x02u},\r
+ {0x96u, 0x80u},\r
+ {0x9Au, 0x80u},\r
+ {0xA1u, 0x01u},\r
+ {0xB0u, 0x80u},\r
+ {0xB2u, 0x10u},\r
+ {0xB5u, 0x20u},\r
+ {0xEAu, 0x0Du},\r
+ {0x0Au, 0x80u},\r
{0x0Fu, 0x40u},\r
- {0xAFu, 0x08u},\r
- {0xB1u, 0x80u},\r
+ {0x96u, 0x80u},\r
+ {0xA9u, 0x01u},\r
+ {0xAEu, 0x80u},\r
+ {0xB2u, 0x01u},\r
{0xC2u, 0x0Cu},\r
- {0xE8u, 0x04u},\r
+ {0xEAu, 0x04u},\r
{0x22u, 0x08u},\r
{0x24u, 0x02u},\r
{0x94u, 0x02u},\r
- {0x98u, 0x20u},\r
- {0xA3u, 0x04u},\r
+ {0x9Eu, 0x20u},\r
{0xA6u, 0x08u},\r
- {0xAEu, 0x40u},\r
- {0xAFu, 0x80u},\r
+ {0xAEu, 0x60u},\r
+ {0xB2u, 0x08u},\r
{0xC8u, 0x60u},\r
- {0xEEu, 0x50u},\r
- {0x05u, 0x02u},\r
- {0x57u, 0x04u},\r
- {0x58u, 0x20u},\r
- {0x81u, 0x02u},\r
- {0x98u, 0x20u},\r
- {0xA3u, 0x04u},\r
+ {0xE8u, 0x10u},\r
+ {0xEEu, 0x40u},\r
+ {0x06u, 0x20u},\r
+ {0x53u, 0x01u},\r
+ {0x5Du, 0x20u},\r
+ {0x83u, 0x01u},\r
+ {0x99u, 0x20u},\r
+ {0x9Eu, 0x20u},\r
+ {0xB1u, 0x20u},\r
{0xC0u, 0x20u},\r
- {0xD4u, 0xC0u},\r
- {0xE4u, 0x20u},\r
- {0xACu, 0x08u},\r
+ {0xD4u, 0x80u},\r
+ {0xD6u, 0x20u},\r
+ {0xE6u, 0x20u},\r
{0xAFu, 0x40u},\r
{0x01u, 0x01u},\r
- {0x09u, 0x01u},\r
{0x0Bu, 0x01u},\r
{0x0Du, 0x01u},\r
+ {0x0Fu, 0x01u},\r
{0x11u, 0x01u},\r
{0x1Bu, 0x01u},\r
{0x00u, 0x0Au},\r
static const cfg_memset_t CYCODE cfg_memset_list [] = {\r
/* address, size */\r
{(void CYFAR *)(CYREG_PRT1_DR), 16u},\r
- {(void CYFAR *)(CYDEV_UCFG_B0_P0_U0_BASE), 4096u},\r
- {(void CYFAR *)(CYDEV_UCFG_B1_P2_U0_BASE), 512u},\r
- {(void CYFAR *)(CYDEV_UCFG_B1_P3_U1_BASE), 1408u},\r
+ {(void CYFAR *)(CYDEV_UCFG_B0_P0_U0_BASE), 1536u},\r
+ {(void CYFAR *)(CYDEV_UCFG_B0_P3_U1_BASE), 2432u},\r
+ {(void CYFAR *)(CYDEV_UCFG_B1_P2_U0_BASE), 2048u},\r
{(void CYFAR *)(CYDEV_UCFG_DSI0_BASE), 2560u},\r
{(void CYFAR *)(CYDEV_UCFG_DSI12_BASE), 512u},\r
{(void CYFAR *)(CYREG_BCTL0_MDCLK_EN), 32u},\r
};\r
\r
- /* UDB_1_1_1_CONFIG Address: CYDEV_UCFG_B1_P3_U0_BASE Size (bytes): 128 */\r
- static const uint8 CYCODE BS_UDB_1_1_1_CONFIG_VAL[] = {\r
- 0x24u, 0xC0u, 0x10u, 0x02u, 0x11u, 0xC0u, 0x22u, 0x04u, 0x08u, 0xC0u, 0x00u, 0x08u, 0xDCu, 0x00u, 0x00u, 0x9Fu, \r
- 0x0Cu, 0x00u, 0xD0u, 0x60u, 0xD0u, 0x7Fu, 0x0Cu, 0x80u, 0x30u, 0x00u, 0x0Fu, 0xFFu, 0xDCu, 0x90u, 0x00u, 0x40u, \r
- 0x00u, 0xC0u, 0x80u, 0x01u, 0x21u, 0x00u, 0x1Eu, 0x00u, 0xD4u, 0x1Fu, 0x08u, 0x20u, 0x00u, 0x80u, 0x00u, 0x00u, \r
- 0x30u, 0xFFu, 0x0Fu, 0x00u, 0x80u, 0x00u, 0x40u, 0x00u, 0x00u, 0x00u, 0x02u, 0x00u, 0x00u, 0x00u, 0x50u, 0x01u, \r
- 0x26u, 0x03u, 0x10u, 0x00u, 0x05u, 0xDEu, 0xFBu, 0x0Cu, 0x1Fu, 0xFFu, 0xFFu, 0xFFu, 0x22u, 0x00u, 0xF0u, 0x08u, \r
- 0x04u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x24u, 0x08u, 0x04u, 0x08u, 0x08u, 0x09u, 0x99u, 0x00u, 0x01u, \r
+ /* UDB_1_2_1_CONFIG Address: CYDEV_UCFG_B0_P3_U0_BASE Size (bytes): 128 */\r
+ static const uint8 CYCODE BS_UDB_1_2_1_CONFIG_VAL[] = {\r
+ 0x80u, 0x01u, 0x00u, 0x00u, 0x7Fu, 0x10u, 0x80u, 0x00u, 0xC0u, 0x08u, 0x04u, 0x21u, 0xC0u, 0x04u, 0x01u, 0x00u, \r
+ 0x00u, 0x01u, 0x60u, 0x00u, 0x00u, 0x07u, 0xFFu, 0x18u, 0x00u, 0x22u, 0x9Fu, 0x08u, 0xC0u, 0x40u, 0x02u, 0x00u, \r
+ 0x90u, 0x01u, 0x40u, 0x00u, 0x1Fu, 0x01u, 0x20u, 0x00u, 0xC0u, 0x40u, 0x08u, 0x00u, 0x00u, 0x01u, 0x00u, 0x00u, \r
+ 0x00u, 0x3Fu, 0xFFu, 0x00u, 0x00u, 0x00u, 0x00u, 0x40u, 0x00u, 0x82u, 0x00u, 0x00u, 0x00u, 0x00u, 0x04u, 0x01u, \r
+ 0x32u, 0x06u, 0x10u, 0x00u, 0x04u, 0xCBu, 0xFDu, 0x0Eu, 0x1Fu, 0xFFu, 0xFFu, 0xFFu, 0x22u, 0x00u, 0xF0u, 0x08u, \r
+ 0x04u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x20u, 0x04u, 0x0Bu, 0x0Bu, 0x0Bu, 0x90u, 0x99u, 0x00u, 0x01u, \r
0x00u, 0x00u, 0xC0u, 0x00u, 0x40u, 0x01u, 0x10u, 0x11u, 0xC0u, 0x01u, 0x00u, 0x11u, 0x40u, 0x01u, 0x40u, 0x01u, \r
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u};\r
\r
static const cfg_memcpy_t CYCODE cfg_memcpy_list [] = {\r
/* dest, src, size */\r
- {(void CYFAR *)(CYDEV_UCFG_B1_P3_U0_BASE), BS_UDB_1_1_1_CONFIG_VAL, 128u},\r
+ {(void CYFAR *)(CYDEV_UCFG_B0_P3_U0_BASE), BS_UDB_1_2_1_CONFIG_VAL, 128u},\r
};\r
\r
uint8 CYDATA i;\r
.set SCSI_RST_ISR__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
\r
/* SDCard_BSPIM */\r
-.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB06_07_ACTL\r
-.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B1_UDB06_07_ST\r
-.set SDCard_BSPIM_BitCounter_ST__MASK_REG, CYREG_B1_UDB06_MSK\r
-.set SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B1_UDB06_MSK_ACTL\r
-.set SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B1_UDB06_MSK_ACTL\r
-.set SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B1_UDB06_ACTL\r
-.set SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B1_UDB06_ST_CTL\r
-.set SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B1_UDB06_ST_CTL\r
-.set SDCard_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B1_UDB06_ST\r
-.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB06_07_ACTL\r
-.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB06_07_CTL\r
-.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB06_07_CTL\r
-.set SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB06_07_CTL\r
-.set SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB06_07_CTL\r
-.set SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B1_UDB06_07_MSK\r
-.set SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB06_07_MSK\r
-.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB06_07_MSK\r
-.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB06_07_MSK\r
-.set SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B1_UDB06_ACTL\r
-.set SDCard_BSPIM_BitCounter__CONTROL_REG, CYREG_B1_UDB06_CTL\r
-.set SDCard_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B1_UDB06_ST_CTL\r
-.set SDCard_BSPIM_BitCounter__COUNT_REG, CYREG_B1_UDB06_CTL\r
-.set SDCard_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B1_UDB06_ST_CTL\r
-.set SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB06_MSK_ACTL\r
-.set SDCard_BSPIM_BitCounter__PERIOD_REG, CYREG_B1_UDB06_MSK\r
-.set SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB06_MSK_ACTL\r
-.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB06_07_ACTL\r
-.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB06_07_ST\r
+.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB06_07_ACTL\r
+.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B0_UDB06_07_ST\r
+.set SDCard_BSPIM_BitCounter_ST__MASK_REG, CYREG_B0_UDB06_MSK\r
+.set SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB06_MSK_ACTL\r
+.set SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B0_UDB06_MSK_ACTL\r
+.set SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B0_UDB06_ACTL\r
+.set SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B0_UDB06_ST_CTL\r
+.set SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B0_UDB06_ST_CTL\r
+.set SDCard_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B0_UDB06_ST\r
+.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB06_07_ACTL\r
+.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB06_07_CTL\r
+.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB06_07_CTL\r
+.set SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB06_07_CTL\r
+.set SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB06_07_CTL\r
+.set SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B0_UDB06_07_MSK\r
+.set SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB06_07_MSK\r
+.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB06_07_MSK\r
+.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB06_07_MSK\r
+.set SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B0_UDB06_ACTL\r
+.set SDCard_BSPIM_BitCounter__CONTROL_REG, CYREG_B0_UDB06_CTL\r
+.set SDCard_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B0_UDB06_ST_CTL\r
+.set SDCard_BSPIM_BitCounter__COUNT_REG, CYREG_B0_UDB06_CTL\r
+.set SDCard_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B0_UDB06_ST_CTL\r
+.set SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB06_MSK_ACTL\r
+.set SDCard_BSPIM_BitCounter__PERIOD_REG, CYREG_B0_UDB06_MSK\r
+.set SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB06_MSK_ACTL\r
+.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB07_08_ACTL\r
+.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB07_08_ST\r
.set SDCard_BSPIM_RxStsReg__4__MASK, 0x10\r
.set SDCard_BSPIM_RxStsReg__4__POS, 4\r
.set SDCard_BSPIM_RxStsReg__5__MASK, 0x20\r
.set SDCard_BSPIM_RxStsReg__6__MASK, 0x40\r
.set SDCard_BSPIM_RxStsReg__6__POS, 6\r
.set SDCard_BSPIM_RxStsReg__MASK, 0x70\r
-.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B0_UDB06_MSK\r
-.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB06_ACTL\r
-.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B0_UDB06_ST\r
+.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B0_UDB07_MSK\r
+.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB07_ACTL\r
+.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B0_UDB07_ST\r
.set SDCard_BSPIM_TxStsReg__0__MASK, 0x01\r
.set SDCard_BSPIM_TxStsReg__0__POS, 0\r
.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB05_06_ACTL\r
.set SDCard_BSPIM_TxStsReg__4__POS, 4\r
.set SDCard_BSPIM_TxStsReg__MASK, 0x1F\r
.set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B0_UDB05_MSK\r
-.set SDCard_BSPIM_TxStsReg__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB05_MSK_ACTL\r
-.set SDCard_BSPIM_TxStsReg__PER_ST_AUX_CTL_REG, CYREG_B0_UDB05_MSK_ACTL\r
.set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB05_ACTL\r
-.set SDCard_BSPIM_TxStsReg__STATUS_CNT_REG, CYREG_B0_UDB05_ST_CTL\r
-.set SDCard_BSPIM_TxStsReg__STATUS_CONTROL_REG, CYREG_B0_UDB05_ST_CTL\r
.set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B0_UDB05_ST\r
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG, CYREG_B1_UDB06_07_A0\r
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG, CYREG_B1_UDB06_07_A1\r
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG, CYREG_B1_UDB06_07_D0\r
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG, CYREG_B1_UDB06_07_D1\r
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG, CYREG_B1_UDB06_07_ACTL\r
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG, CYREG_B1_UDB06_07_F0\r
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG, CYREG_B1_UDB06_07_F1\r
-.set SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG, CYREG_B1_UDB06_A0_A1\r
-.set SDCard_BSPIM_sR8_Dp_u0__A0_REG, CYREG_B1_UDB06_A0\r
-.set SDCard_BSPIM_sR8_Dp_u0__A1_REG, CYREG_B1_UDB06_A1\r
-.set SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG, CYREG_B1_UDB06_D0_D1\r
-.set SDCard_BSPIM_sR8_Dp_u0__D0_REG, CYREG_B1_UDB06_D0\r
-.set SDCard_BSPIM_sR8_Dp_u0__D1_REG, CYREG_B1_UDB06_D1\r
-.set SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG, CYREG_B1_UDB06_ACTL\r
-.set SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG, CYREG_B1_UDB06_F0_F1\r
-.set SDCard_BSPIM_sR8_Dp_u0__F0_REG, CYREG_B1_UDB06_F0\r
-.set SDCard_BSPIM_sR8_Dp_u0__F1_REG, CYREG_B1_UDB06_F1\r
-.set SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG, CYREG_B1_UDB06_MSK_ACTL\r
-.set SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG, CYREG_B1_UDB06_MSK_ACTL\r
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG, CYREG_B0_UDB06_07_A0\r
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG, CYREG_B0_UDB06_07_A1\r
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG, CYREG_B0_UDB06_07_D0\r
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG, CYREG_B0_UDB06_07_D1\r
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG, CYREG_B0_UDB06_07_ACTL\r
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG, CYREG_B0_UDB06_07_F0\r
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG, CYREG_B0_UDB06_07_F1\r
+.set SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG, CYREG_B0_UDB06_A0_A1\r
+.set SDCard_BSPIM_sR8_Dp_u0__A0_REG, CYREG_B0_UDB06_A0\r
+.set SDCard_BSPIM_sR8_Dp_u0__A1_REG, CYREG_B0_UDB06_A1\r
+.set SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG, CYREG_B0_UDB06_D0_D1\r
+.set SDCard_BSPIM_sR8_Dp_u0__D0_REG, CYREG_B0_UDB06_D0\r
+.set SDCard_BSPIM_sR8_Dp_u0__D1_REG, CYREG_B0_UDB06_D1\r
+.set SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG, CYREG_B0_UDB06_ACTL\r
+.set SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG, CYREG_B0_UDB06_F0_F1\r
+.set SDCard_BSPIM_sR8_Dp_u0__F0_REG, CYREG_B0_UDB06_F0\r
+.set SDCard_BSPIM_sR8_Dp_u0__F1_REG, CYREG_B0_UDB06_F1\r
+.set SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG, CYREG_B0_UDB06_MSK_ACTL\r
+.set SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG, CYREG_B0_UDB06_MSK_ACTL\r
\r
/* USBFS_dp_int */\r
.set USBFS_dp_int__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
/* SCSI_CTL_IO */\r
.set SCSI_CTL_IO_Sync_ctrl_reg__0__MASK, 0x01\r
.set SCSI_CTL_IO_Sync_ctrl_reg__0__POS, 0\r
-.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB00_01_ACTL\r
-.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB00_01_CTL\r
-.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB00_01_CTL\r
-.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB00_01_CTL\r
-.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB00_01_CTL\r
-.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB00_01_MSK\r
-.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB00_01_MSK\r
-.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB00_01_MSK\r
-.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB00_01_MSK\r
-.set SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB00_ACTL\r
-.set SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB00_CTL\r
-.set SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB00_ST_CTL\r
-.set SCSI_CTL_IO_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB00_CTL\r
-.set SCSI_CTL_IO_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB00_ST_CTL\r
+.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB11_12_ACTL\r
+.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB11_12_CTL\r
+.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB11_12_CTL\r
+.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB11_12_CTL\r
+.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB11_12_CTL\r
+.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB11_12_MSK\r
+.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB11_12_MSK\r
+.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB11_12_MSK\r
+.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB11_12_MSK\r
+.set SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB11_ACTL\r
+.set SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB11_CTL\r
+.set SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB11_ST_CTL\r
+.set SCSI_CTL_IO_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB11_CTL\r
+.set SCSI_CTL_IO_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB11_ST_CTL\r
.set SCSI_CTL_IO_Sync_ctrl_reg__MASK, 0x01\r
-.set SCSI_CTL_IO_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB00_MSK_ACTL\r
-.set SCSI_CTL_IO_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB00_MSK\r
-.set SCSI_CTL_IO_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB00_MSK_ACTL\r
+.set SCSI_CTL_IO_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL\r
+.set SCSI_CTL_IO_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB11_MSK\r
+.set SCSI_CTL_IO_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL\r
\r
/* SCSI_In_DBx */\r
.set SCSI_In_DBx__0__AG, CYREG_PRT12_AG\r
/* scsiTarget */\r
.set scsiTarget_StatusReg__0__MASK, 0x01\r
.set scsiTarget_StatusReg__0__POS, 0\r
-.set scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB11_12_ACTL\r
-.set scsiTarget_StatusReg__16BIT_STATUS_REG, CYREG_B0_UDB11_12_ST\r
+.set scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB14_15_ACTL\r
+.set scsiTarget_StatusReg__16BIT_STATUS_REG, CYREG_B0_UDB14_15_ST\r
.set scsiTarget_StatusReg__1__MASK, 0x02\r
.set scsiTarget_StatusReg__1__POS, 1\r
.set scsiTarget_StatusReg__2__MASK, 0x04\r
.set scsiTarget_StatusReg__3__MASK, 0x08\r
.set scsiTarget_StatusReg__3__POS, 3\r
.set scsiTarget_StatusReg__MASK, 0x0F\r
-.set scsiTarget_StatusReg__MASK_REG, CYREG_B0_UDB11_MSK\r
-.set scsiTarget_StatusReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB11_ACTL\r
-.set scsiTarget_StatusReg__STATUS_REG, CYREG_B0_UDB11_ST\r
-.set scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB03_04_ACTL\r
-.set scsiTarget_datapath_PI__16BIT_STATUS_REG, CYREG_B0_UDB03_04_ST\r
-.set scsiTarget_datapath_PI__MASK_REG, CYREG_B0_UDB03_MSK\r
-.set scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL\r
-.set scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL\r
-.set scsiTarget_datapath_PI__STATUS_AUX_CTL_REG, CYREG_B0_UDB03_ACTL\r
-.set scsiTarget_datapath_PI__STATUS_CNT_REG, CYREG_B0_UDB03_ST_CTL\r
-.set scsiTarget_datapath_PI__STATUS_CONTROL_REG, CYREG_B0_UDB03_ST_CTL\r
-.set scsiTarget_datapath_PI__STATUS_REG, CYREG_B0_UDB03_ST\r
-.set scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB03_04_ACTL\r
-.set scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB03_04_CTL\r
-.set scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB03_04_CTL\r
-.set scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB03_04_CTL\r
-.set scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB03_04_CTL\r
-.set scsiTarget_datapath_PO__16BIT_MASK_MASK_REG, CYREG_B0_UDB03_04_MSK\r
-.set scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB03_04_MSK\r
-.set scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB03_04_MSK\r
-.set scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB03_04_MSK\r
-.set scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG, CYREG_B0_UDB03_ACTL\r
-.set scsiTarget_datapath_PO__CONTROL_REG, CYREG_B0_UDB03_CTL\r
-.set scsiTarget_datapath_PO__CONTROL_ST_REG, CYREG_B0_UDB03_ST_CTL\r
-.set scsiTarget_datapath_PO__COUNT_REG, CYREG_B0_UDB03_CTL\r
-.set scsiTarget_datapath_PO__COUNT_ST_REG, CYREG_B0_UDB03_ST_CTL\r
-.set scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL\r
-.set scsiTarget_datapath_PO__PERIOD_REG, CYREG_B0_UDB03_MSK\r
-.set scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL\r
-.set scsiTarget_datapath__16BIT_A0_REG, CYREG_B0_UDB03_04_A0\r
-.set scsiTarget_datapath__16BIT_A1_REG, CYREG_B0_UDB03_04_A1\r
-.set scsiTarget_datapath__16BIT_D0_REG, CYREG_B0_UDB03_04_D0\r
-.set scsiTarget_datapath__16BIT_D1_REG, CYREG_B0_UDB03_04_D1\r
-.set scsiTarget_datapath__16BIT_DP_AUX_CTL_REG, CYREG_B0_UDB03_04_ACTL\r
-.set scsiTarget_datapath__16BIT_F0_REG, CYREG_B0_UDB03_04_F0\r
-.set scsiTarget_datapath__16BIT_F1_REG, CYREG_B0_UDB03_04_F1\r
-.set scsiTarget_datapath__A0_A1_REG, CYREG_B0_UDB03_A0_A1\r
-.set scsiTarget_datapath__A0_REG, CYREG_B0_UDB03_A0\r
-.set scsiTarget_datapath__A1_REG, CYREG_B0_UDB03_A1\r
-.set scsiTarget_datapath__D0_D1_REG, CYREG_B0_UDB03_D0_D1\r
-.set scsiTarget_datapath__D0_REG, CYREG_B0_UDB03_D0\r
-.set scsiTarget_datapath__D1_REG, CYREG_B0_UDB03_D1\r
-.set scsiTarget_datapath__DP_AUX_CTL_REG, CYREG_B0_UDB03_ACTL\r
-.set scsiTarget_datapath__F0_F1_REG, CYREG_B0_UDB03_F0_F1\r
-.set scsiTarget_datapath__F0_REG, CYREG_B0_UDB03_F0\r
-.set scsiTarget_datapath__F1_REG, CYREG_B0_UDB03_F1\r
-.set scsiTarget_datapath__MSK_DP_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL\r
-.set scsiTarget_datapath__PER_DP_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL\r
+.set scsiTarget_StatusReg__MASK_REG, CYREG_B0_UDB14_MSK\r
+.set scsiTarget_StatusReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB14_ACTL\r
+.set scsiTarget_StatusReg__STATUS_REG, CYREG_B0_UDB14_ST\r
+.set scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB13_14_ACTL\r
+.set scsiTarget_datapath_PI__16BIT_STATUS_REG, CYREG_B0_UDB13_14_ST\r
+.set scsiTarget_datapath_PI__MASK_REG, CYREG_B0_UDB13_MSK\r
+.set scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB13_MSK_ACTL\r
+.set scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG, CYREG_B0_UDB13_MSK_ACTL\r
+.set scsiTarget_datapath_PI__STATUS_AUX_CTL_REG, CYREG_B0_UDB13_ACTL\r
+.set scsiTarget_datapath_PI__STATUS_CNT_REG, CYREG_B0_UDB13_ST_CTL\r
+.set scsiTarget_datapath_PI__STATUS_CONTROL_REG, CYREG_B0_UDB13_ST_CTL\r
+.set scsiTarget_datapath_PI__STATUS_REG, CYREG_B0_UDB13_ST\r
+.set scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB13_14_ACTL\r
+.set scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB13_14_CTL\r
+.set scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB13_14_CTL\r
+.set scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB13_14_CTL\r
+.set scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB13_14_CTL\r
+.set scsiTarget_datapath_PO__16BIT_MASK_MASK_REG, CYREG_B0_UDB13_14_MSK\r
+.set scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB13_14_MSK\r
+.set scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB13_14_MSK\r
+.set scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB13_14_MSK\r
+.set scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG, CYREG_B0_UDB13_ACTL\r
+.set scsiTarget_datapath_PO__CONTROL_REG, CYREG_B0_UDB13_CTL\r
+.set scsiTarget_datapath_PO__CONTROL_ST_REG, CYREG_B0_UDB13_ST_CTL\r
+.set scsiTarget_datapath_PO__COUNT_REG, CYREG_B0_UDB13_CTL\r
+.set scsiTarget_datapath_PO__COUNT_ST_REG, CYREG_B0_UDB13_ST_CTL\r
+.set scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB13_MSK_ACTL\r
+.set scsiTarget_datapath_PO__PERIOD_REG, CYREG_B0_UDB13_MSK\r
+.set scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB13_MSK_ACTL\r
+.set scsiTarget_datapath__16BIT_A0_REG, CYREG_B0_UDB13_14_A0\r
+.set scsiTarget_datapath__16BIT_A1_REG, CYREG_B0_UDB13_14_A1\r
+.set scsiTarget_datapath__16BIT_D0_REG, CYREG_B0_UDB13_14_D0\r
+.set scsiTarget_datapath__16BIT_D1_REG, CYREG_B0_UDB13_14_D1\r
+.set scsiTarget_datapath__16BIT_DP_AUX_CTL_REG, CYREG_B0_UDB13_14_ACTL\r
+.set scsiTarget_datapath__16BIT_F0_REG, CYREG_B0_UDB13_14_F0\r
+.set scsiTarget_datapath__16BIT_F1_REG, CYREG_B0_UDB13_14_F1\r
+.set scsiTarget_datapath__A0_A1_REG, CYREG_B0_UDB13_A0_A1\r
+.set scsiTarget_datapath__A0_REG, CYREG_B0_UDB13_A0\r
+.set scsiTarget_datapath__A1_REG, CYREG_B0_UDB13_A1\r
+.set scsiTarget_datapath__D0_D1_REG, CYREG_B0_UDB13_D0_D1\r
+.set scsiTarget_datapath__D0_REG, CYREG_B0_UDB13_D0\r
+.set scsiTarget_datapath__D1_REG, CYREG_B0_UDB13_D1\r
+.set scsiTarget_datapath__DP_AUX_CTL_REG, CYREG_B0_UDB13_ACTL\r
+.set scsiTarget_datapath__F0_F1_REG, CYREG_B0_UDB13_F0_F1\r
+.set scsiTarget_datapath__F0_REG, CYREG_B0_UDB13_F0\r
+.set scsiTarget_datapath__F1_REG, CYREG_B0_UDB13_F1\r
+.set scsiTarget_datapath__MSK_DP_AUX_CTL_REG, CYREG_B0_UDB13_MSK_ACTL\r
+.set scsiTarget_datapath__PER_DP_AUX_CTL_REG, CYREG_B0_UDB13_MSK_ACTL\r
\r
/* SD_Clk_Ctl */\r
.set SD_Clk_Ctl_Sync_ctrl_reg__0__MASK, 0x01\r
.set SD_Clk_Ctl_Sync_ctrl_reg__0__POS, 0\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB05_06_ACTL\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB05_06_CTL\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB05_06_CTL\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB05_06_CTL\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB05_06_CTL\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB05_06_MSK\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB05_06_MSK\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB05_06_MSK\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB05_06_MSK\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB05_ACTL\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB05_CTL\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB05_ST_CTL\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB05_CTL\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB05_ST_CTL\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB10_11_ACTL\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB10_11_CTL\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB10_11_CTL\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB10_11_CTL\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB10_11_CTL\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB10_11_MSK\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB10_11_MSK\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB10_11_MSK\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB10_11_MSK\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB10_ACTL\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB10_CTL\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB10_ST_CTL\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB10_CTL\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB10_ST_CTL\r
.set SD_Clk_Ctl_Sync_ctrl_reg__MASK, 0x01\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB05_MSK_ACTL\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB05_MSK\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB05_MSK_ACTL\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB10_MSK_ACTL\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB10_MSK\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB10_MSK_ACTL\r
\r
/* USBFS_ep_0 */\r
.set USBFS_ep_0__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
SCSI_RST_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
\r
/* SDCard_BSPIM */\r
-SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL\r
-SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB06_07_ST\r
-SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB06_MSK\r
-SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL\r
-SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB06_ST_CTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB06_ST_CTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB06_ST\r
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL\r
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB06_07_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB06_07_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB06_07_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB06_07_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB06_07_MSK\r
-SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB06_07_MSK\r
-SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB06_07_MSK\r
-SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB06_07_MSK\r
-SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL\r
-SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB06_CTL\r
-SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB06_ST_CTL\r
-SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB06_CTL\r
-SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB06_ST_CTL\r
-SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL\r
-SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB06_MSK\r
-SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL\r
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL\r
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB06_07_ST\r
+SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL\r
+SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B0_UDB06_07_ST\r
+SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B0_UDB06_MSK\r
+SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL\r
+SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B0_UDB06_ST_CTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B0_UDB06_ST_CTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B0_UDB06_ST\r
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL\r
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB06_07_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB06_07_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB06_07_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB06_07_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB06_07_MSK\r
+SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB06_07_MSK\r
+SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB06_07_MSK\r
+SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB06_07_MSK\r
+SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL\r
+SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B0_UDB06_CTL\r
+SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B0_UDB06_ST_CTL\r
+SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B0_UDB06_CTL\r
+SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B0_UDB06_ST_CTL\r
+SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL\r
+SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B0_UDB06_MSK\r
+SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL\r
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL\r
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB07_08_ST\r
SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10\r
SDCard_BSPIM_RxStsReg__4__POS EQU 4\r
SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20\r
SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40\r
SDCard_BSPIM_RxStsReg__6__POS EQU 6\r
SDCard_BSPIM_RxStsReg__MASK EQU 0x70\r
-SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B0_UDB06_MSK\r
-SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL\r
-SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B0_UDB06_ST\r
+SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B0_UDB07_MSK\r
+SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL\r
+SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B0_UDB07_ST\r
SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01\r
SDCard_BSPIM_TxStsReg__0__POS EQU 0\r
SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL\r
SDCard_BSPIM_TxStsReg__4__POS EQU 4\r
SDCard_BSPIM_TxStsReg__MASK EQU 0x1F\r
SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B0_UDB05_MSK\r
-SDCard_BSPIM_TxStsReg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL\r
-SDCard_BSPIM_TxStsReg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL\r
SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL\r
-SDCard_BSPIM_TxStsReg__STATUS_CNT_REG EQU CYREG_B0_UDB05_ST_CTL\r
-SDCard_BSPIM_TxStsReg__STATUS_CONTROL_REG EQU CYREG_B0_UDB05_ST_CTL\r
SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B0_UDB05_ST\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB06_07_A0\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB06_07_A1\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B1_UDB06_07_D0\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B1_UDB06_07_D1\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B1_UDB06_07_F0\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B1_UDB06_07_F1\r
-SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B1_UDB06_A0_A1\r
-SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B1_UDB06_A0\r
-SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B1_UDB06_A1\r
-SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B1_UDB06_D0_D1\r
-SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B1_UDB06_D0\r
-SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B1_UDB06_D1\r
-SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL\r
-SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B1_UDB06_F0_F1\r
-SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B1_UDB06_F0\r
-SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B1_UDB06_F1\r
-SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL\r
-SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B0_UDB06_07_A0\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B0_UDB06_07_A1\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B0_UDB06_07_D0\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B0_UDB06_07_D1\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B0_UDB06_07_F0\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B0_UDB06_07_F1\r
+SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B0_UDB06_A0_A1\r
+SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B0_UDB06_A0\r
+SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B0_UDB06_A1\r
+SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B0_UDB06_D0_D1\r
+SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B0_UDB06_D0\r
+SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B0_UDB06_D1\r
+SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL\r
+SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B0_UDB06_F0_F1\r
+SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B0_UDB06_F0\r
+SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B0_UDB06_F1\r
+SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL\r
+SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL\r
\r
/* USBFS_dp_int */\r
USBFS_dp_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
/* SCSI_CTL_IO */\r
SCSI_CTL_IO_Sync_ctrl_reg__0__MASK EQU 0x01\r
SCSI_CTL_IO_Sync_ctrl_reg__0__POS EQU 0\r
-SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB00_01_ACTL\r
-SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB00_01_CTL\r
-SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB00_01_CTL\r
-SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB00_01_CTL\r
-SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB00_01_CTL\r
-SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB00_01_MSK\r
-SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB00_01_MSK\r
-SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB00_01_MSK\r
-SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB00_01_MSK\r
-SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB00_ACTL\r
-SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB00_CTL\r
-SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB00_ST_CTL\r
-SCSI_CTL_IO_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB00_CTL\r
-SCSI_CTL_IO_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB00_ST_CTL\r
+SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL\r
+SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL\r
+SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB11_12_CTL\r
+SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL\r
+SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB11_12_CTL\r
+SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB11_12_MSK\r
+SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK\r
+SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB11_12_MSK\r
+SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK\r
+SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL\r
+SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB11_CTL\r
+SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB11_ST_CTL\r
+SCSI_CTL_IO_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB11_CTL\r
+SCSI_CTL_IO_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB11_ST_CTL\r
SCSI_CTL_IO_Sync_ctrl_reg__MASK EQU 0x01\r
-SCSI_CTL_IO_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB00_MSK_ACTL\r
-SCSI_CTL_IO_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB00_MSK\r
-SCSI_CTL_IO_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB00_MSK_ACTL\r
+SCSI_CTL_IO_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL\r
+SCSI_CTL_IO_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB11_MSK\r
+SCSI_CTL_IO_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL\r
\r
/* SCSI_In_DBx */\r
SCSI_In_DBx__0__AG EQU CYREG_PRT12_AG\r
/* scsiTarget */\r
scsiTarget_StatusReg__0__MASK EQU 0x01\r
scsiTarget_StatusReg__0__POS EQU 0\r
-scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL\r
-scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB11_12_ST\r
+scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB14_15_ACTL\r
+scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB14_15_ST\r
scsiTarget_StatusReg__1__MASK EQU 0x02\r
scsiTarget_StatusReg__1__POS EQU 1\r
scsiTarget_StatusReg__2__MASK EQU 0x04\r
scsiTarget_StatusReg__3__MASK EQU 0x08\r
scsiTarget_StatusReg__3__POS EQU 3\r
scsiTarget_StatusReg__MASK EQU 0x0F\r
-scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB11_MSK\r
-scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL\r
-scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB11_ST\r
-scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL\r
-scsiTarget_datapath_PI__16BIT_STATUS_REG EQU CYREG_B0_UDB03_04_ST\r
-scsiTarget_datapath_PI__MASK_REG EQU CYREG_B0_UDB03_MSK\r
-scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL\r
-scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL\r
-scsiTarget_datapath_PI__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL\r
-scsiTarget_datapath_PI__STATUS_CNT_REG EQU CYREG_B0_UDB03_ST_CTL\r
-scsiTarget_datapath_PI__STATUS_CONTROL_REG EQU CYREG_B0_UDB03_ST_CTL\r
-scsiTarget_datapath_PI__STATUS_REG EQU CYREG_B0_UDB03_ST\r
-scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL\r
-scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL\r
-scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB03_04_CTL\r
-scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL\r
-scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB03_04_CTL\r
-scsiTarget_datapath_PO__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB03_04_MSK\r
-scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK\r
-scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB03_04_MSK\r
-scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK\r
-scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL\r
-scsiTarget_datapath_PO__CONTROL_REG EQU CYREG_B0_UDB03_CTL\r
-scsiTarget_datapath_PO__CONTROL_ST_REG EQU CYREG_B0_UDB03_ST_CTL\r
-scsiTarget_datapath_PO__COUNT_REG EQU CYREG_B0_UDB03_CTL\r
-scsiTarget_datapath_PO__COUNT_ST_REG EQU CYREG_B0_UDB03_ST_CTL\r
-scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL\r
-scsiTarget_datapath_PO__PERIOD_REG EQU CYREG_B0_UDB03_MSK\r
-scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL\r
-scsiTarget_datapath__16BIT_A0_REG EQU CYREG_B0_UDB03_04_A0\r
-scsiTarget_datapath__16BIT_A1_REG EQU CYREG_B0_UDB03_04_A1\r
-scsiTarget_datapath__16BIT_D0_REG EQU CYREG_B0_UDB03_04_D0\r
-scsiTarget_datapath__16BIT_D1_REG EQU CYREG_B0_UDB03_04_D1\r
-scsiTarget_datapath__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL\r
-scsiTarget_datapath__16BIT_F0_REG EQU CYREG_B0_UDB03_04_F0\r
-scsiTarget_datapath__16BIT_F1_REG EQU CYREG_B0_UDB03_04_F1\r
-scsiTarget_datapath__A0_A1_REG EQU CYREG_B0_UDB03_A0_A1\r
-scsiTarget_datapath__A0_REG EQU CYREG_B0_UDB03_A0\r
-scsiTarget_datapath__A1_REG EQU CYREG_B0_UDB03_A1\r
-scsiTarget_datapath__D0_D1_REG EQU CYREG_B0_UDB03_D0_D1\r
-scsiTarget_datapath__D0_REG EQU CYREG_B0_UDB03_D0\r
-scsiTarget_datapath__D1_REG EQU CYREG_B0_UDB03_D1\r
-scsiTarget_datapath__DP_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL\r
-scsiTarget_datapath__F0_F1_REG EQU CYREG_B0_UDB03_F0_F1\r
-scsiTarget_datapath__F0_REG EQU CYREG_B0_UDB03_F0\r
-scsiTarget_datapath__F1_REG EQU CYREG_B0_UDB03_F1\r
-scsiTarget_datapath__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL\r
-scsiTarget_datapath__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL\r
+scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB14_MSK\r
+scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB14_ACTL\r
+scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB14_ST\r
+scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB13_14_ACTL\r
+scsiTarget_datapath_PI__16BIT_STATUS_REG EQU CYREG_B0_UDB13_14_ST\r
+scsiTarget_datapath_PI__MASK_REG EQU CYREG_B0_UDB13_MSK\r
+scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL\r
+scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL\r
+scsiTarget_datapath_PI__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB13_ACTL\r
+scsiTarget_datapath_PI__STATUS_CNT_REG EQU CYREG_B0_UDB13_ST_CTL\r
+scsiTarget_datapath_PI__STATUS_CONTROL_REG EQU CYREG_B0_UDB13_ST_CTL\r
+scsiTarget_datapath_PI__STATUS_REG EQU CYREG_B0_UDB13_ST\r
+scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB13_14_ACTL\r
+scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB13_14_CTL\r
+scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB13_14_CTL\r
+scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB13_14_CTL\r
+scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB13_14_CTL\r
+scsiTarget_datapath_PO__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB13_14_MSK\r
+scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB13_14_MSK\r
+scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB13_14_MSK\r
+scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB13_14_MSK\r
+scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB13_ACTL\r
+scsiTarget_datapath_PO__CONTROL_REG EQU CYREG_B0_UDB13_CTL\r
+scsiTarget_datapath_PO__CONTROL_ST_REG EQU CYREG_B0_UDB13_ST_CTL\r
+scsiTarget_datapath_PO__COUNT_REG EQU CYREG_B0_UDB13_CTL\r
+scsiTarget_datapath_PO__COUNT_ST_REG EQU CYREG_B0_UDB13_ST_CTL\r
+scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL\r
+scsiTarget_datapath_PO__PERIOD_REG EQU CYREG_B0_UDB13_MSK\r
+scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL\r
+scsiTarget_datapath__16BIT_A0_REG EQU CYREG_B0_UDB13_14_A0\r
+scsiTarget_datapath__16BIT_A1_REG EQU CYREG_B0_UDB13_14_A1\r
+scsiTarget_datapath__16BIT_D0_REG EQU CYREG_B0_UDB13_14_D0\r
+scsiTarget_datapath__16BIT_D1_REG EQU CYREG_B0_UDB13_14_D1\r
+scsiTarget_datapath__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB13_14_ACTL\r
+scsiTarget_datapath__16BIT_F0_REG EQU CYREG_B0_UDB13_14_F0\r
+scsiTarget_datapath__16BIT_F1_REG EQU CYREG_B0_UDB13_14_F1\r
+scsiTarget_datapath__A0_A1_REG EQU CYREG_B0_UDB13_A0_A1\r
+scsiTarget_datapath__A0_REG EQU CYREG_B0_UDB13_A0\r
+scsiTarget_datapath__A1_REG EQU CYREG_B0_UDB13_A1\r
+scsiTarget_datapath__D0_D1_REG EQU CYREG_B0_UDB13_D0_D1\r
+scsiTarget_datapath__D0_REG EQU CYREG_B0_UDB13_D0\r
+scsiTarget_datapath__D1_REG EQU CYREG_B0_UDB13_D1\r
+scsiTarget_datapath__DP_AUX_CTL_REG EQU CYREG_B0_UDB13_ACTL\r
+scsiTarget_datapath__F0_F1_REG EQU CYREG_B0_UDB13_F0_F1\r
+scsiTarget_datapath__F0_REG EQU CYREG_B0_UDB13_F0\r
+scsiTarget_datapath__F1_REG EQU CYREG_B0_UDB13_F1\r
+scsiTarget_datapath__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL\r
+scsiTarget_datapath__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL\r
\r
/* SD_Clk_Ctl */\r
SD_Clk_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01\r
SD_Clk_Ctl_Sync_ctrl_reg__0__POS EQU 0\r
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB05_06_CTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB05_06_CTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB05_06_MSK\r
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK\r
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB05_06_MSK\r
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK\r
-SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB05_CTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB05_ST_CTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB05_CTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB05_ST_CTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB10_11_ACTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB10_11_CTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB10_11_CTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB10_11_CTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB10_11_CTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB10_11_MSK\r
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB10_11_MSK\r
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB10_11_MSK\r
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB10_11_MSK\r
+SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB10_ACTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB10_CTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB10_ST_CTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB10_CTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB10_ST_CTL\r
SD_Clk_Ctl_Sync_ctrl_reg__MASK EQU 0x01\r
-SD_Clk_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB05_MSK\r
-SD_Clk_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB10_MSK\r
+SD_Clk_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL\r
\r
/* USBFS_ep_0 */\r
USBFS_ep_0__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
SCSI_RST_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
\r
; SDCard_BSPIM\r
-SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL\r
-SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB06_07_ST\r
-SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB06_MSK\r
-SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL\r
-SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB06_ST_CTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB06_ST_CTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB06_ST\r
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL\r
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB06_07_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB06_07_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB06_07_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB06_07_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB06_07_MSK\r
-SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB06_07_MSK\r
-SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB06_07_MSK\r
-SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB06_07_MSK\r
-SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL\r
-SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB06_CTL\r
-SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB06_ST_CTL\r
-SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB06_CTL\r
-SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB06_ST_CTL\r
-SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL\r
-SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB06_MSK\r
-SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL\r
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL\r
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB06_07_ST\r
+SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL\r
+SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B0_UDB06_07_ST\r
+SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B0_UDB06_MSK\r
+SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL\r
+SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B0_UDB06_ST_CTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B0_UDB06_ST_CTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B0_UDB06_ST\r
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL\r
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB06_07_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB06_07_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB06_07_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB06_07_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB06_07_MSK\r
+SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB06_07_MSK\r
+SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB06_07_MSK\r
+SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB06_07_MSK\r
+SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL\r
+SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B0_UDB06_CTL\r
+SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B0_UDB06_ST_CTL\r
+SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B0_UDB06_CTL\r
+SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B0_UDB06_ST_CTL\r
+SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL\r
+SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B0_UDB06_MSK\r
+SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL\r
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL\r
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB07_08_ST\r
SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10\r
SDCard_BSPIM_RxStsReg__4__POS EQU 4\r
SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20\r
SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40\r
SDCard_BSPIM_RxStsReg__6__POS EQU 6\r
SDCard_BSPIM_RxStsReg__MASK EQU 0x70\r
-SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B0_UDB06_MSK\r
-SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL\r
-SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B0_UDB06_ST\r
+SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B0_UDB07_MSK\r
+SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL\r
+SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B0_UDB07_ST\r
SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01\r
SDCard_BSPIM_TxStsReg__0__POS EQU 0\r
SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL\r
SDCard_BSPIM_TxStsReg__4__POS EQU 4\r
SDCard_BSPIM_TxStsReg__MASK EQU 0x1F\r
SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B0_UDB05_MSK\r
-SDCard_BSPIM_TxStsReg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL\r
-SDCard_BSPIM_TxStsReg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL\r
SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL\r
-SDCard_BSPIM_TxStsReg__STATUS_CNT_REG EQU CYREG_B0_UDB05_ST_CTL\r
-SDCard_BSPIM_TxStsReg__STATUS_CONTROL_REG EQU CYREG_B0_UDB05_ST_CTL\r
SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B0_UDB05_ST\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB06_07_A0\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB06_07_A1\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B1_UDB06_07_D0\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B1_UDB06_07_D1\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B1_UDB06_07_F0\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B1_UDB06_07_F1\r
-SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B1_UDB06_A0_A1\r
-SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B1_UDB06_A0\r
-SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B1_UDB06_A1\r
-SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B1_UDB06_D0_D1\r
-SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B1_UDB06_D0\r
-SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B1_UDB06_D1\r
-SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL\r
-SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B1_UDB06_F0_F1\r
-SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B1_UDB06_F0\r
-SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B1_UDB06_F1\r
-SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL\r
-SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B0_UDB06_07_A0\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B0_UDB06_07_A1\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B0_UDB06_07_D0\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B0_UDB06_07_D1\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B0_UDB06_07_F0\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B0_UDB06_07_F1\r
+SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B0_UDB06_A0_A1\r
+SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B0_UDB06_A0\r
+SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B0_UDB06_A1\r
+SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B0_UDB06_D0_D1\r
+SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B0_UDB06_D0\r
+SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B0_UDB06_D1\r
+SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL\r
+SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B0_UDB06_F0_F1\r
+SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B0_UDB06_F0\r
+SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B0_UDB06_F1\r
+SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL\r
+SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL\r
\r
; USBFS_dp_int\r
USBFS_dp_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
; SCSI_CTL_IO\r
SCSI_CTL_IO_Sync_ctrl_reg__0__MASK EQU 0x01\r
SCSI_CTL_IO_Sync_ctrl_reg__0__POS EQU 0\r
-SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB00_01_ACTL\r
-SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB00_01_CTL\r
-SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB00_01_CTL\r
-SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB00_01_CTL\r
-SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB00_01_CTL\r
-SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB00_01_MSK\r
-SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB00_01_MSK\r
-SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB00_01_MSK\r
-SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB00_01_MSK\r
-SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB00_ACTL\r
-SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB00_CTL\r
-SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB00_ST_CTL\r
-SCSI_CTL_IO_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB00_CTL\r
-SCSI_CTL_IO_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB00_ST_CTL\r
+SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL\r
+SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL\r
+SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB11_12_CTL\r
+SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL\r
+SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB11_12_CTL\r
+SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB11_12_MSK\r
+SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK\r
+SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB11_12_MSK\r
+SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK\r
+SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL\r
+SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB11_CTL\r
+SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB11_ST_CTL\r
+SCSI_CTL_IO_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB11_CTL\r
+SCSI_CTL_IO_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB11_ST_CTL\r
SCSI_CTL_IO_Sync_ctrl_reg__MASK EQU 0x01\r
-SCSI_CTL_IO_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB00_MSK_ACTL\r
-SCSI_CTL_IO_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB00_MSK\r
-SCSI_CTL_IO_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB00_MSK_ACTL\r
+SCSI_CTL_IO_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL\r
+SCSI_CTL_IO_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB11_MSK\r
+SCSI_CTL_IO_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL\r
\r
; SCSI_In_DBx\r
SCSI_In_DBx__0__AG EQU CYREG_PRT12_AG\r
; scsiTarget\r
scsiTarget_StatusReg__0__MASK EQU 0x01\r
scsiTarget_StatusReg__0__POS EQU 0\r
-scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL\r
-scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB11_12_ST\r
+scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB14_15_ACTL\r
+scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB14_15_ST\r
scsiTarget_StatusReg__1__MASK EQU 0x02\r
scsiTarget_StatusReg__1__POS EQU 1\r
scsiTarget_StatusReg__2__MASK EQU 0x04\r
scsiTarget_StatusReg__3__MASK EQU 0x08\r
scsiTarget_StatusReg__3__POS EQU 3\r
scsiTarget_StatusReg__MASK EQU 0x0F\r
-scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB11_MSK\r
-scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL\r
-scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB11_ST\r
-scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL\r
-scsiTarget_datapath_PI__16BIT_STATUS_REG EQU CYREG_B0_UDB03_04_ST\r
-scsiTarget_datapath_PI__MASK_REG EQU CYREG_B0_UDB03_MSK\r
-scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL\r
-scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL\r
-scsiTarget_datapath_PI__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL\r
-scsiTarget_datapath_PI__STATUS_CNT_REG EQU CYREG_B0_UDB03_ST_CTL\r
-scsiTarget_datapath_PI__STATUS_CONTROL_REG EQU CYREG_B0_UDB03_ST_CTL\r
-scsiTarget_datapath_PI__STATUS_REG EQU CYREG_B0_UDB03_ST\r
-scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL\r
-scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL\r
-scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB03_04_CTL\r
-scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL\r
-scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB03_04_CTL\r
-scsiTarget_datapath_PO__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB03_04_MSK\r
-scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK\r
-scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB03_04_MSK\r
-scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK\r
-scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL\r
-scsiTarget_datapath_PO__CONTROL_REG EQU CYREG_B0_UDB03_CTL\r
-scsiTarget_datapath_PO__CONTROL_ST_REG EQU CYREG_B0_UDB03_ST_CTL\r
-scsiTarget_datapath_PO__COUNT_REG EQU CYREG_B0_UDB03_CTL\r
-scsiTarget_datapath_PO__COUNT_ST_REG EQU CYREG_B0_UDB03_ST_CTL\r
-scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL\r
-scsiTarget_datapath_PO__PERIOD_REG EQU CYREG_B0_UDB03_MSK\r
-scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL\r
-scsiTarget_datapath__16BIT_A0_REG EQU CYREG_B0_UDB03_04_A0\r
-scsiTarget_datapath__16BIT_A1_REG EQU CYREG_B0_UDB03_04_A1\r
-scsiTarget_datapath__16BIT_D0_REG EQU CYREG_B0_UDB03_04_D0\r
-scsiTarget_datapath__16BIT_D1_REG EQU CYREG_B0_UDB03_04_D1\r
-scsiTarget_datapath__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL\r
-scsiTarget_datapath__16BIT_F0_REG EQU CYREG_B0_UDB03_04_F0\r
-scsiTarget_datapath__16BIT_F1_REG EQU CYREG_B0_UDB03_04_F1\r
-scsiTarget_datapath__A0_A1_REG EQU CYREG_B0_UDB03_A0_A1\r
-scsiTarget_datapath__A0_REG EQU CYREG_B0_UDB03_A0\r
-scsiTarget_datapath__A1_REG EQU CYREG_B0_UDB03_A1\r
-scsiTarget_datapath__D0_D1_REG EQU CYREG_B0_UDB03_D0_D1\r
-scsiTarget_datapath__D0_REG EQU CYREG_B0_UDB03_D0\r
-scsiTarget_datapath__D1_REG EQU CYREG_B0_UDB03_D1\r
-scsiTarget_datapath__DP_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL\r
-scsiTarget_datapath__F0_F1_REG EQU CYREG_B0_UDB03_F0_F1\r
-scsiTarget_datapath__F0_REG EQU CYREG_B0_UDB03_F0\r
-scsiTarget_datapath__F1_REG EQU CYREG_B0_UDB03_F1\r
-scsiTarget_datapath__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL\r
-scsiTarget_datapath__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL\r
+scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB14_MSK\r
+scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB14_ACTL\r
+scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB14_ST\r
+scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB13_14_ACTL\r
+scsiTarget_datapath_PI__16BIT_STATUS_REG EQU CYREG_B0_UDB13_14_ST\r
+scsiTarget_datapath_PI__MASK_REG EQU CYREG_B0_UDB13_MSK\r
+scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL\r
+scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL\r
+scsiTarget_datapath_PI__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB13_ACTL\r
+scsiTarget_datapath_PI__STATUS_CNT_REG EQU CYREG_B0_UDB13_ST_CTL\r
+scsiTarget_datapath_PI__STATUS_CONTROL_REG EQU CYREG_B0_UDB13_ST_CTL\r
+scsiTarget_datapath_PI__STATUS_REG EQU CYREG_B0_UDB13_ST\r
+scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB13_14_ACTL\r
+scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB13_14_CTL\r
+scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB13_14_CTL\r
+scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB13_14_CTL\r
+scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB13_14_CTL\r
+scsiTarget_datapath_PO__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB13_14_MSK\r
+scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB13_14_MSK\r
+scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB13_14_MSK\r
+scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB13_14_MSK\r
+scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB13_ACTL\r
+scsiTarget_datapath_PO__CONTROL_REG EQU CYREG_B0_UDB13_CTL\r
+scsiTarget_datapath_PO__CONTROL_ST_REG EQU CYREG_B0_UDB13_ST_CTL\r
+scsiTarget_datapath_PO__COUNT_REG EQU CYREG_B0_UDB13_CTL\r
+scsiTarget_datapath_PO__COUNT_ST_REG EQU CYREG_B0_UDB13_ST_CTL\r
+scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL\r
+scsiTarget_datapath_PO__PERIOD_REG EQU CYREG_B0_UDB13_MSK\r
+scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL\r
+scsiTarget_datapath__16BIT_A0_REG EQU CYREG_B0_UDB13_14_A0\r
+scsiTarget_datapath__16BIT_A1_REG EQU CYREG_B0_UDB13_14_A1\r
+scsiTarget_datapath__16BIT_D0_REG EQU CYREG_B0_UDB13_14_D0\r
+scsiTarget_datapath__16BIT_D1_REG EQU CYREG_B0_UDB13_14_D1\r
+scsiTarget_datapath__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB13_14_ACTL\r
+scsiTarget_datapath__16BIT_F0_REG EQU CYREG_B0_UDB13_14_F0\r
+scsiTarget_datapath__16BIT_F1_REG EQU CYREG_B0_UDB13_14_F1\r
+scsiTarget_datapath__A0_A1_REG EQU CYREG_B0_UDB13_A0_A1\r
+scsiTarget_datapath__A0_REG EQU CYREG_B0_UDB13_A0\r
+scsiTarget_datapath__A1_REG EQU CYREG_B0_UDB13_A1\r
+scsiTarget_datapath__D0_D1_REG EQU CYREG_B0_UDB13_D0_D1\r
+scsiTarget_datapath__D0_REG EQU CYREG_B0_UDB13_D0\r
+scsiTarget_datapath__D1_REG EQU CYREG_B0_UDB13_D1\r
+scsiTarget_datapath__DP_AUX_CTL_REG EQU CYREG_B0_UDB13_ACTL\r
+scsiTarget_datapath__F0_F1_REG EQU CYREG_B0_UDB13_F0_F1\r
+scsiTarget_datapath__F0_REG EQU CYREG_B0_UDB13_F0\r
+scsiTarget_datapath__F1_REG EQU CYREG_B0_UDB13_F1\r
+scsiTarget_datapath__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL\r
+scsiTarget_datapath__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL\r
\r
; SD_Clk_Ctl\r
SD_Clk_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01\r
SD_Clk_Ctl_Sync_ctrl_reg__0__POS EQU 0\r
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB05_06_CTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB05_06_CTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB05_06_MSK\r
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK\r
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB05_06_MSK\r
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK\r
-SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB05_CTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB05_ST_CTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB05_CTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB05_ST_CTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB10_11_ACTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB10_11_CTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB10_11_CTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB10_11_CTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB10_11_CTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB10_11_MSK\r
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB10_11_MSK\r
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB10_11_MSK\r
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB10_11_MSK\r
+SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB10_ACTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB10_CTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB10_ST_CTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB10_CTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB10_ST_CTL\r
SD_Clk_Ctl_Sync_ctrl_reg__MASK EQU 0x01\r
-SD_Clk_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB05_MSK\r
-SD_Clk_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB10_MSK\r
+SD_Clk_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL\r
\r
; USBFS_ep_0\r
USBFS_ep_0__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
<block name="SCSI_In_DBx" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="SCSI_Out_DBx" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="SD_Clk_Ctl" BASE="0x0" SIZE="0x0" desc="" visible="true">\r
- <register name="SD_Clk_Ctl_CONTROL_REG" address="0x40006475" bitWidth="8" desc="" />\r
+ <register name="SD_Clk_Ctl_CONTROL_REG" address="0x4000647A" bitWidth="8" desc="" />\r
</block>\r
<block name="SD_CD" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="OddParityGen_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="SD_DAT2" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="SD_DAT1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="SCSI_CTL_IO" BASE="0x0" SIZE="0x0" desc="" visible="true">\r
- <register name="SCSI_CTL_IO_CONTROL_REG" address="0x40006470" bitWidth="8" desc="" />\r
+ <register name="SCSI_CTL_IO_CONTROL_REG" address="0x4000647B" bitWidth="8" desc="" />\r
</block>\r
</blockRegMap>
\ No newline at end of file
<peripheral>\r
<name>SD_Clk_Ctl</name>\r
<description>No description available</description>\r
- <baseAddress>0x40006475</baseAddress>\r
+ <baseAddress>0x4000647A</baseAddress>\r
<addressBlock>\r
<offset>0</offset>\r
<size>0x1</size>\r
<peripheral>\r
<name>SCSI_CTL_IO</name>\r
<description>No description available</description>\r
- <baseAddress>0x40006470</baseAddress>\r
+ <baseAddress>0x4000647B</baseAddress>\r
<addressBlock>\r
<offset>0</offset>\r
<size>0x1</size>\r
\r
#include "scsi.h"\r
#include "scsiPhy.h"\r
+#include "disk.h"\r
\r
#include <string.h>\r
\r
0, // SCSI ID\r
" codesrc", // vendor (68k Apple Drive Setup: Set to " SEAGATE")\r
" SCSI2SD", //prodId (68k Apple Drive Setup: Set to " ST225N")\r
- " 3.2", // revision (68k Apple Drive Setup: Set to "1.0 ")\r
+ " 3.3", // revision (68k Apple Drive Setup: Set to "1.0 ")\r
1, // enable parity\r
- 0, // disable unit attention,\r
+ 1, // enable unit attention,\r
0 // Max blocks (0 == disabled)\r
// reserved bytes will be initialised to 0.\r
};\r
shadow.reserved[21] = scsiDev.rstCount;\r
shadow.reserved[22] = scsiDev.selCount;\r
shadow.reserved[23] = scsiDev.msgCount;\r
- shadow.reserved[24] = scsiDev.watchdogTick++;\r
+ shadow.reserved[24] = scsiDev.cmdCount;\r
+ shadow.reserved[25] = scsiDev.watchdogTick;\r
+ shadow.reserved[26] = blockDev.state;\r
+ shadow.reserved[27] = scsiReadDBxPins();\r
#endif\r
\r
USBFS_LoadInEP(USB_EP_IN, (uint8 *)&shadow, sizeof(shadow));\r
transfer.currentBlock++;\r
if (transfer.currentBlock >= transfer.blocks)\r
{\r
- int needComplete = transfer.multiBlock;\r
scsiDev.phase = STATUS;\r
scsiDiskReset();\r
- if (needComplete)\r
- {\r
- sdCompleteRead();\r
- }\r
}\r
}\r
}\r
else if (scsiDev.phase == DATA_OUT &&\r
transfer.currentBlock != transfer.blocks)\r
{\r
- int writeOk = sdWriteSector();\r
+ sdWriteSector();\r
// TODO FIX scsiDiskPoll() scsiDev.dataPtr = 0;\r
transfer.currentBlock++;\r
if (transfer.currentBlock >= transfer.blocks)\r
scsiDev.phase = STATUS;\r
\r
scsiDiskReset();\r
-\r
- if (writeOk)\r
- {\r
- sdCompleteWrite();\r
- }\r
}\r
}\r
}\r
\r
void scsiDiskReset()\r
{\r
- // todo if SPI command in progress, cancel it.\r
scsiDev.dataPtr = 0;\r
scsiDev.savedDataPtr = 0;\r
scsiDev.dataLen = 0;\r
- transfer.lba = 0;\r
+ // transfer.lba = 0; // Needed in Request Sense to determine failure\r
transfer.blocks = 0;\r
transfer.currentBlock = 0;\r
+\r
+ // Cancel long running commands!\r
+ if (transfer.inProgress == 1)\r
+ {\r
+ if (transfer.dir == TRANSFER_WRITE)\r
+ {\r
+ sdCompleteWrite();\r
+ }\r
+ else\r
+ {\r
+ sdCompleteRead();\r
+ }\r
+ }\r
+ transfer.inProgress = 0;\r
transfer.multiBlock = 0;\r
}\r
\r
{\r
blockDev.bs = SCSI_BLOCK_SIZE;\r
blockDev.capacity = 0;\r
+ transfer.inProgress = 0;\r
scsiDiskReset();\r
\r
// Don't require the host to send us a START STOP UNIT command\r
{
int dir;
int multiBlock; // True if we're using a multi-block SPI transfer.
+ int inProgress; // True if we need to call sdComplete{Read|Write}
uint32 lba;
uint32 blocks;
sizeof(config->prodId) +\r
sizeof(config->revision);\r
scsiDev.phase = DATA_IN;\r
- \r
- if (!lun) scsiDev.unitAttention = 0;\r
}\r
}\r
else if (pageCode == 0x00)\r
\r
static void enter_BusFree()\r
{\r
- scsiEnterPhase(BUS_FREE);\r
+ // TODO MPC3000 testing.\r
+ // 1,2us: Cannot see SCSI device.\r
+ // 5us: Can see SCSI device, format fails\r
+ // 10us: Format succeeds.\r
+ // 25us: Format fails.\r
+ CyDelayUs(10);\r
+\r
+\r
\r
- ledOff();\r
\r
- scsiDev.phase = BUS_FREE;\r
SCSI_ClearPin(SCSI_Out_BSY);\r
+ // We now have a Bus Clear Delay of 800ns to release remaining signals.\r
+ SCSI_ClearPin(SCSI_Out_MSG);\r
+ SCSI_ClearPin(SCSI_Out_CD);\r
+ SCSI_CTL_IO_Write(0);\r
+\r
+ // Wait for the initiator to cease driving signals\r
+ // Bus settle delay + bus clear delay = 1200ns\r
+ CyDelayUs(2);\r
+\r
+ ledOff();\r
+ scsiDev.phase = BUS_FREE;\r
}\r
\r
static void enter_MessageIn(uint8 message)\r
{\r
scsiDev.status = status;\r
scsiDev.phase = STATUS;\r
+\r
+\r
+ #ifdef MM_DEBUG\r
+ scsiDev.lastStatus = scsiDev.status;\r
+ scsiDev.lastSense = scsiDev.sense.code;\r
+ #endif\r
}\r
\r
static void process_Status()\r
{\r
scsiEnterPhase(STATUS);\r
scsiWriteByte(scsiDev.status);\r
- \r
+\r
#ifdef MM_DEBUG\r
scsiDev.lastStatus = scsiDev.status;\r
scsiDev.lastSense = scsiDev.sense.code;\r
static void process_DataIn()\r
{\r
uint32 len;\r
- \r
+\r
if (scsiDev.dataLen > sizeof(scsiDev.data))\r
{\r
scsiDev.dataLen = sizeof(scsiDev.data);\r
static void process_DataOut()\r
{\r
uint32 len;\r
- \r
+\r
if (scsiDev.dataLen > sizeof(scsiDev.data))\r
{\r
scsiDev.dataLen = sizeof(scsiDev.data);\r
int cmdSize;\r
uint8 command;\r
uint8 lun;\r
- \r
+\r
scsiEnterPhase(COMMAND);\r
scsiDev.parityError = 0;\r
\r
command = scsiDev.cdb[0];\r
lun = scsiDev.cdb[1] >> 5;\r
\r
- if (scsiDev.parityError)\r
+ #ifdef MM_DEBUG\r
+ scsiDev.cmdCount++;\r
+ #endif\r
+\r
+ if (scsiDev.resetFlag)\r
+ {\r
+#ifdef MM_DEBUG\r
+ // Don't log bogus commands\r
+ scsiDev.cmdCount--;\r
+ memset(scsiDev.cdb, 0xff, sizeof(scsiDev.cdb));\r
+#endif\r
+ return;\r
+ }\r
+ else if (scsiDev.parityError)\r
{\r
scsiDev.sense.code = ABORTED_COMMAND;\r
scsiDev.sense.asc = SCSI_PARITY_ERROR;\r
scsiDev.data[0] = 0xF0;\r
scsiDev.data[2] = scsiDev.sense.code & 0x0F;\r
\r
- // TODO populate "information" field with requested LBA.\r
- // TODO support more detailed sense data ?\r
+ scsiDev.data[3] = transfer.lba >> 24;\r
+ scsiDev.data[4] = transfer.lba >> 16;\r
+ scsiDev.data[5] = transfer.lba >> 8;\r
+ scsiDev.data[6] = transfer.lba;\r
\r
- scsiDev.data[12] = scsiDev.sense.asc >> 8;\r
- scsiDev.data[13] = scsiDev.sense.asc;\r
+ // Additional bytes if there are errors to report\r
+ int responseLength;\r
+ if (scsiDev.sense.code == NO_SENSE)\r
+ {\r
+ responseLength = 8;\r
+ }\r
+ else\r
+ {\r
+ responseLength = 18;\r
+ scsiDev.data[7] = 10; // additional length\r
+ scsiDev.data[12] = scsiDev.sense.asc >> 8;\r
+ scsiDev.data[13] = scsiDev.sense.asc;\r
+ }\r
\r
// Silently truncate results. SCSI-2 spec 8.2.14.\r
- enter_DataIn(allocLength < 18 ? allocLength : 18);\r
+ enter_DataIn(\r
+ (allocLength < responseLength) ? allocLength : responseLength\r
+ );\r
\r
// This is a good time to clear out old sense information.\r
scsiDev.sense.code = NO_SENSE;\r
scsiDev.sense.asc = NO_ADDITIONAL_SENSE_INFORMATION;\r
}\r
// Some old SCSI drivers do NOT properly support\r
- // unitAttention. OTOH, Linux seems to require it\r
- // confirmed LCIII with unknown scsi driver fials here.\r
+ // unitAttention. eg. the Mac Plus would trigger a SCSI reset\r
+ // on receiving the unit attention response on boot, thus\r
+ // triggering another unit attention condition.\r
else if (scsiDev.unitAttention && config->enableUnitAttention)\r
{\r
scsiDev.sense.code = UNIT_ATTENTION;\r
scsiDev.sense.asc = scsiDev.unitAttention;\r
+\r
+ // If initiator doesn't do REQUEST SENSE for the next command, then\r
+ // data is lost.\r
+ scsiDev.unitAttention = 0;\r
+\r
enter_Status(CHECK_CONDITION);\r
}\r
else if (lun)\r
{\r
enter_Status(GOOD);\r
}\r
+\r
}\r
\r
static void doReserveRelease()\r
scsiDev.rstCount++;\r
#endif\r
ledOff();\r
- // done in verilog SCSI_Out_DBx_Write(0);\r
- SCSI_CTL_IO_Write(0);\r
- SCSI_ClearPin(SCSI_Out_ATN);\r
- SCSI_ClearPin(SCSI_Out_BSY);\r
- SCSI_ClearPin(SCSI_Out_ACK);\r
- SCSI_ClearPin(SCSI_Out_RST);\r
- SCSI_ClearPin(SCSI_Out_SEL);\r
- SCSI_ClearPin(SCSI_Out_REQ);\r
- SCSI_ClearPin(SCSI_Out_MSG);\r
- SCSI_ClearPin(SCSI_Out_CD);\r
+\r
+ scsiPhyReset();\r
\r
scsiDev.parityError = 0;\r
scsiDev.phase = BUS_FREE;\r
+ scsiDev.atnFlag = 0;\r
+ scsiDev.resetFlag = 0;\r
\r
if (scsiDev.unitAttention != POWER_ON_RESET)\r
{\r
// in which case TERMPWR cannot be supplied, and reset will ALWAYS\r
// be true.\r
CyDelay(10); // 10ms.\r
- scsiDev.resetFlag = SCSI_ReadPin(SCSI_RST_INT);\r
- scsiDev.atnFlag = 0;\r
}\r
\r
static void enter_SelectionPhase()\r
if (scsiDev.resetFlag)\r
{\r
scsiReset();\r
+ if ((scsiDev.resetFlag = SCSI_ReadPin(SCSI_RST_INT)))\r
+ {\r
+ // Still in reset phase. Do not try and process any commands.\r
+ return;\r
+ }\r
}\r
\r
switch (scsiDev.phase)\r
uint8 msgOut;
#ifdef MM_DEBUG
+ uint8 cmdCount;
uint8 selCount;
uint8 rstCount;
uint8 msgCount;
#include "scsiPhy.h"\r
#include "bits.h"\r
\r
+#define scsiTarget_AUX_CTL (* (reg8 *) scsiTarget_datapath__DP_AUX_CTL_REG)\r
+\r
CY_ISR_PROTO(scsiResetISR);\r
CY_ISR(scsiResetISR)\r
{\r
\r
uint8 scsiReadByte(void)\r
{\r
- while (!(CY_GET_REG8(scsiTarget_StatusReg__STATUS_REG) & 1)) {}\r
+ while (!(CY_GET_REG8(scsiTarget_StatusReg__STATUS_REG) & 1) &&\r
+ !scsiDev.resetFlag) {}\r
CY_SET_REG8(scsiTarget_datapath__F0_REG, 0);\r
- while (!(CY_GET_REG8(scsiTarget_StatusReg__STATUS_REG) & 2)) {}\r
+ while (!(CY_GET_REG8(scsiTarget_StatusReg__STATUS_REG) & 2) &&\r
+ !scsiDev.resetFlag) {}\r
return CY_GET_REG8(scsiTarget_datapath__F1_REG);\r
}\r
\r
int prep = 0;\r
int i = 0;\r
\r
- while (i < count)\r
+ while (i < count && !scsiDev.resetFlag)\r
{\r
if (prep < count && (CY_GET_REG8(scsiTarget_StatusReg__STATUS_REG) & 1))\r
{\r
\r
void scsiWriteByte(uint8 value)\r
{\r
- while (!(CY_GET_REG8(scsiTarget_StatusReg__STATUS_REG) & 1)) {}\r
+ while (!(CY_GET_REG8(scsiTarget_StatusReg__STATUS_REG) & 1) &&\r
+ !scsiDev.resetFlag) {}\r
CY_SET_REG8(scsiTarget_datapath__F0_REG, value);\r
\r
// TODO maybe move this TX EMPTY check to scsiEnterPhase ?\r
//while (!(CY_GET_REG8(scsiTarget_StatusReg__STATUS_REG) & 4)) {}\r
- while (!(CY_GET_REG8(scsiTarget_StatusReg__STATUS_REG) & 2)) {}\r
+ while (!(CY_GET_REG8(scsiTarget_StatusReg__STATUS_REG) & 2) &&\r
+ !scsiDev.resetFlag) {}\r
value = CY_GET_REG8(scsiTarget_datapath__F1_REG); \r
}\r
\r
int prep = 0;\r
int i = 0;\r
\r
- while (i < count)\r
+ while (i < count && !scsiDev.resetFlag)\r
{\r
if (prep < count && (CY_GET_REG8(scsiTarget_StatusReg__STATUS_REG) & 1))\r
{\r
busSettleDelay();\r
}\r
\r
+void scsiPhyReset()\r
+{\r
+ // Set the Clear bits for both SCSI device FIFOs\r
+ scsiTarget_AUX_CTL = scsiTarget_AUX_CTL | 0x03;\r
+\r
+ // Trigger RST outselves. It is connected to the datapath and will\r
+ // ensure it returns to the idle state. The datapath runs at the BUS clk\r
+ // speed (ie. same as the CPU), so we can be sure it is active for a sufficient\r
+ // duration.\r
+ SCSI_SetPin(SCSI_Out_RST);\r
+\r
+ SCSI_CTL_IO_Write(0);\r
+ SCSI_ClearPin(SCSI_Out_ATN);\r
+ SCSI_ClearPin(SCSI_Out_BSY);\r
+ SCSI_ClearPin(SCSI_Out_ACK);\r
+ SCSI_ClearPin(SCSI_Out_RST);\r
+ SCSI_ClearPin(SCSI_Out_SEL);\r
+ SCSI_ClearPin(SCSI_Out_REQ);\r
+ SCSI_ClearPin(SCSI_Out_MSG);\r
+ SCSI_ClearPin(SCSI_Out_CD);\r
+\r
+ // Allow the FIFOs to fill up again.\r
+ SCSI_ClearPin(SCSI_Out_RST);\r
+ scsiTarget_AUX_CTL = scsiTarget_AUX_CTL & ~(0x03);\r
+}\r
+\r
void scsiPhyInit()\r
{\r
SCSI_RST_ISR_StartEx(scsiResetISR);\r
// Contains the odd-parity flag for a given 8-bit value.
extern const uint8 Lookup_OddParity[256];
+void scsiPhyReset(void);
void scsiPhyInit(void);
uint8 scsiReadByte(void);
void scsiRead(uint8* data, uint32 count);
// Check that SCSI initiator is ready, and input FIFO is not empty,\r
// and output FIFO is not full.\r
// Note that output FIFO is unused in TX mode.\r
- if (nACK & !f0_blk_stat && !f1_blk_stat)\r
+ if (!nRST) state <= STATE_IDLE;\r
+ else if (nACK & !f0_blk_stat && !f1_blk_stat)\r
state <= STATE_FIFOLOAD;\r
else\r
state <= STATE_IDLE;\r
end\r
\r
STATE_FIFOLOAD:\r
- state <= IO == IO_WRITE ? STATE_TX : STATE_READY;\r
+ if (!nRST) state <= STATE_IDLE;\r
+ else state <= IO == IO_WRITE ? STATE_TX : STATE_READY;\r
\r
STATE_TX:\r
begin\r
- state <= STATE_DESKEW_INIT;\r
+ if (!nRST) state <= STATE_IDLE;\r
+ else state <= STATE_DESKEW_INIT;\r
data <= po;\r
end\r
\r
- STATE_DESKEW_INIT: state <= STATE_DESKEW;\r
+ STATE_DESKEW_INIT:\r
+ if (!nRST) state <= STATE_IDLE;\r
+ else state <= STATE_DESKEW;\r
\r
STATE_DESKEW:\r
- if(deskewComplete) state <= STATE_READY;\r
+ if (!nRST) state <= STATE_IDLE;\r
+ else if(deskewComplete) state <= STATE_READY;\r
else state <= STATE_DESKEW;\r
\r
STATE_READY:\r
- if (~nACK) state <= STATE_RX;\r
+ if (!nRST) state <= STATE_IDLE;\r
+ else if (~nACK) state <= STATE_RX;\r
else state <= STATE_READY;\r
\r
STATE_RX: state <= STATE_IDLE;\r
scsiDev.sense.asc = LOGICAL_UNIT_COMMUNICATION_FAILURE;\r
scsiDev.phase = STATUS;\r
}\r
+ else\r
+ {\r
+ transfer.inProgress = 1;\r
+ }\r
}\r
\r
static void doReadSector()\r
{\r
int prep, i, guard;\r
- \r
+\r
// Wait for a start-block token.\r
// Don't wait more than 100ms, which is the timeout recommended\r
// in the standard.\r
// Don't do a bus settle delay if we're already in the correct phase.\r
if (transfer.currentBlock == 0)\r
{\r
+ //scsiEnterPhase(DATA_OUT);\r
+ //CyDelayUs(200);\r
scsiEnterPhase(DATA_IN);\r
+ //CyDelayUs(200); // TODO BLOODY SLOW INTERLEAVE\r
}\r
\r
// Quickly seed the FIFO\r
// This loop is critically important for performance.\r
// We stream data straight from the SDCard fifos into the SCSI component\r
// FIFO's. If the loop isn't fast enough, the transmit FIFO's will empty,\r
- // and performance will suffer. Every clock cycle counts. \r
- while (i < SCSI_BLOCK_SIZE)\r
+ // and performance will suffer. Every clock cycle counts.\r
+ while (i < SCSI_BLOCK_SIZE && !scsiDev.resetFlag)\r
{\r
uint8_t sdRxStatus = CY_GET_REG8(SDCard_RX_STATUS_PTR);\r
uint8_t scsiStatus = CY_GET_REG8(scsiTarget_StatusReg__STATUS_REG);\r
// Read from the SPIM fifo if there is room to stream the byte to the\r
// SCSI fifos\r
if((sdRxStatus & SDCard_STS_RX_FIFO_NOT_EMPTY) &&\r
- (scsiStatus & 1) // SCSI TX FIFO NOT FULL\r
+ (scsiDev.resetFlag || (scsiStatus & 1)) // SCSI TX FIFO NOT FULL\r
)\r
{\r
uint8_t val = CY_GET_REG8(SDCard_RXDATA_PTR);\r
}\r
\r
// Byte has been sent out the SCSI interface.\r
- if (scsiStatus & 2) // SCSI RX FIFO NOT EMPTY\r
+ if (scsiDev.resetFlag || (scsiStatus & 2)) // SCSI RX FIFO NOT EMPTY\r
{\r
CY_GET_REG8(scsiTarget_datapath__F1_REG);\r
++i;\r
{\r
CY_SET_REG8(SDCard_TXDATA_PTR, 0xFF); // Put a byte in the FIFO\r
prep++;\r
- } \r
+ }\r
}\r
\r
sdSpiByte(0xFF); // CRC\r
\r
void sdCompleteRead()\r
{\r
+ transfer.inProgress = 0;\r
+\r
// We cannot send even a single "padding" byte, as we normally would when\r
// sending a command. If we've just finished reading the very last block\r
// on the card, then reading an additional dummy byte will just trigger\r
\r
int sdWriteSector()\r
{\r
- int prep, i, guard; \r
+ int prep, i, guard;\r
int result, maxWait;\r
uint8 dataToken;\r
\r
// SPIM fifos\r
// See sdReadSector for comment on guard (FIFO size is really 5)\r
if((guard - i < 4) &&\r
- (scsiStatus & 2)) // SCSI RX FIFO NOT EMPTY\r
+ (scsiDev.resetFlag || (scsiStatus & 2))\r
+ ) // SCSI RX FIFO NOT EMPTY\r
{\r
uint8_t val = CY_GET_REG8(scsiTarget_datapath__F1_REG);\r
CY_SET_REG8(SDCard_TXDATA_PTR, val);\r
guard++;\r
}\r
- \r
+\r
// Byte has been sent out the SPIM interface.\r
if (sdRxStatus & SDCard_STS_RX_FIFO_NOT_EMPTY)\r
{\r
}\r
\r
if (prep < SCSI_BLOCK_SIZE &&\r
- (scsiStatus & 1) // SCSI TX FIFO NOT FULL\r
+ (scsiDev.resetFlag || (scsiStatus & 1)) // SCSI TX FIFO NOT FULL\r
)\r
{\r
// Trigger the SCSI component to read a byte\r
CY_SET_REG8(scsiTarget_datapath__F0_REG, 0xFF);\r
prep++;\r
- } \r
+ }\r
}\r
\r
sdSpiByte(0x00); // CRC\r
// Wait for the card to come out of busy.\r
sdWaitWriteBusy();\r
\r
+ transfer.inProgress = 0;\r
scsiDiskReset();\r
sdClearStatus();\r
\r
\r
void sdCompleteWrite()\r
{\r
+ transfer.inProgress = 0;\r
+\r
uint8 r1, r2;\r
- \r
+\r
sdSpiByte(0xFD); // STOP TOKEN\r
// Wait for the card to come out of busy.\r
sdWaitWriteBusy();\r
scsiDev.sense.asc = LOGICAL_UNIT_COMMUNICATION_FAILURE;\r
scsiDev.phase = STATUS;\r
}\r
+ else\r
+ {\r
+ transfer.inProgress = 1;\r
+ }\r
}\r
\r
projects / SCSI2SD-V6.git / commitdiff