As currently implemented:
-Sequential read: 2.5MB/s Sequential write: 900kb/sec
+Transfer size: 512 2048 8192 65536
+-------------------------------------------------------
+read: 2MB/s 2.1MB/s 2.5MB/s 2.6MB/s
+write: 125kB/s 441kB/s 1.5MB/s 2.3MB/s
+-------------------------------------------------------
+
Tested with a 16GB class 10 SD card, via the commands:
# WRITE TEST
- sudo dd bs=8192 count=100 if=/dev/zero of=/dev/sdX oflag=dsync
+ sudo dd bs=${SIZE} count=100 if=/dev/zero of=/dev/sdX oflag=dsync
# READ TEST
- sudo dd bs=8192 count=100 if=/dev/sdX of=/dev/null
+ sudo dd bs=${SIZE} count=100 if=/dev/sdX of=/dev/null
Compatibility
/* SCSI_CTL_PHASE */\r
#define SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK 0x01u\r
#define SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS 0\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB02_03_ACTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB02_03_CTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB02_03_CTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB02_03_CTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB02_03_CTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB02_03_MSK\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB02_03_MSK\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB02_03_MSK\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB02_03_MSK\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB05_06_ACTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB05_06_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB05_06_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB05_06_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB05_06_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB05_06_MSK\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB05_06_MSK\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB05_06_MSK\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB05_06_MSK\r
#define SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK 0x02u\r
#define SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS 1\r
#define SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK 0x04u\r
#define SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS 2\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB02_ACTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB02_CTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB02_ST_CTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB02_CTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB02_ST_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB05_ACTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB05_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB05_ST_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB05_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB05_ST_CTL\r
#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK 0x07u\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB02_MSK_ACTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB02_MSK\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB02_MSK_ACTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB05_MSK\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL\r
\r
/* SCSI_Out_Bits */\r
#define SCSI_Out_Bits_Sync_ctrl_reg__0__MASK 0x01u\r
#define SCSI_RST_ISR__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
\r
/* SDCard_BSPIM */\r
-#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB06_07_ACTL\r
-#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B1_UDB06_07_ST\r
-#define SDCard_BSPIM_BitCounter_ST__MASK_REG CYREG_B1_UDB06_MSK\r
-#define SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL\r
-#define SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL\r
-#define SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B1_UDB06_ACTL\r
-#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B1_UDB06_ST_CTL\r
-#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B1_UDB06_ST_CTL\r
-#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B1_UDB06_ST\r
-#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB06_07_ACTL\r
-#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB06_07_CTL\r
-#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB06_07_CTL\r
-#define SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB06_07_CTL\r
-#define SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B1_UDB06_07_CTL\r
-#define SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B1_UDB06_07_MSK\r
-#define SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B1_UDB06_07_MSK\r
-#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B1_UDB06_07_MSK\r
-#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB06_07_MSK\r
-#define SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B1_UDB06_ACTL\r
-#define SDCard_BSPIM_BitCounter__CONTROL_REG CYREG_B1_UDB06_CTL\r
-#define SDCard_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B1_UDB06_ST_CTL\r
-#define SDCard_BSPIM_BitCounter__COUNT_REG CYREG_B1_UDB06_CTL\r
-#define SDCard_BSPIM_BitCounter__COUNT_ST_REG CYREG_B1_UDB06_ST_CTL\r
-#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL\r
-#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B1_UDB06_MSK\r
-#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL\r
-#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB07_08_ACTL\r
-#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B0_UDB07_08_ST\r
+#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB06_07_ACTL\r
+#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B0_UDB06_07_ST\r
+#define SDCard_BSPIM_BitCounter_ST__MASK_REG CYREG_B0_UDB06_MSK\r
+#define SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL\r
+#define SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL\r
+#define SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B0_UDB06_ACTL\r
+#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B0_UDB06_ST_CTL\r
+#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B0_UDB06_ST_CTL\r
+#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B0_UDB06_ST\r
+#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB06_07_ACTL\r
+#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB06_07_CTL\r
+#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB06_07_CTL\r
+#define SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB06_07_CTL\r
+#define SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B0_UDB06_07_CTL\r
+#define SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B0_UDB06_07_MSK\r
+#define SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B0_UDB06_07_MSK\r
+#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B0_UDB06_07_MSK\r
+#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB06_07_MSK\r
+#define SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B0_UDB06_ACTL\r
+#define SDCard_BSPIM_BitCounter__CONTROL_REG CYREG_B0_UDB06_CTL\r
+#define SDCard_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B0_UDB06_ST_CTL\r
+#define SDCard_BSPIM_BitCounter__COUNT_REG CYREG_B0_UDB06_CTL\r
+#define SDCard_BSPIM_BitCounter__COUNT_ST_REG CYREG_B0_UDB06_ST_CTL\r
+#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL\r
+#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B0_UDB06_MSK\r
+#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL\r
+#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB05_06_ACTL\r
+#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B0_UDB05_06_ST\r
#define SDCard_BSPIM_RxStsReg__4__MASK 0x10u\r
#define SDCard_BSPIM_RxStsReg__4__POS 4\r
#define SDCard_BSPIM_RxStsReg__5__MASK 0x20u\r
#define SDCard_BSPIM_RxStsReg__6__MASK 0x40u\r
#define SDCard_BSPIM_RxStsReg__6__POS 6\r
#define SDCard_BSPIM_RxStsReg__MASK 0x70u\r
-#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B0_UDB07_MSK\r
-#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB07_ACTL\r
-#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B0_UDB07_ST\r
+#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B0_UDB05_MSK\r
+#define SDCard_BSPIM_RxStsReg__MASK_ST_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL\r
+#define SDCard_BSPIM_RxStsReg__PER_ST_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL\r
+#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB05_ACTL\r
+#define SDCard_BSPIM_RxStsReg__STATUS_CNT_REG CYREG_B0_UDB05_ST_CTL\r
+#define SDCard_BSPIM_RxStsReg__STATUS_CONTROL_REG CYREG_B0_UDB05_ST_CTL\r
+#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B0_UDB05_ST\r
#define SDCard_BSPIM_TxStsReg__0__MASK 0x01u\r
#define SDCard_BSPIM_TxStsReg__0__POS 0\r
-#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB07_08_ACTL\r
-#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B1_UDB07_08_ST\r
+#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB06_07_ACTL\r
+#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B1_UDB06_07_ST\r
#define SDCard_BSPIM_TxStsReg__1__MASK 0x02u\r
#define SDCard_BSPIM_TxStsReg__1__POS 1\r
#define SDCard_BSPIM_TxStsReg__2__MASK 0x04u\r
#define SDCard_BSPIM_TxStsReg__4__MASK 0x10u\r
#define SDCard_BSPIM_TxStsReg__4__POS 4\r
#define SDCard_BSPIM_TxStsReg__MASK 0x1Fu\r
-#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B1_UDB07_MSK\r
-#define SDCard_BSPIM_TxStsReg__MASK_ST_AUX_CTL_REG CYREG_B1_UDB07_MSK_ACTL\r
-#define SDCard_BSPIM_TxStsReg__PER_ST_AUX_CTL_REG CYREG_B1_UDB07_MSK_ACTL\r
-#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB07_ACTL\r
-#define SDCard_BSPIM_TxStsReg__STATUS_CNT_REG CYREG_B1_UDB07_ST_CTL\r
-#define SDCard_BSPIM_TxStsReg__STATUS_CONTROL_REG CYREG_B1_UDB07_ST_CTL\r
-#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B1_UDB07_ST\r
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B0_UDB04_05_A0\r
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B0_UDB04_05_A1\r
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG CYREG_B0_UDB04_05_D0\r
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG CYREG_B0_UDB04_05_D1\r
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG CYREG_B0_UDB04_05_ACTL\r
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG CYREG_B0_UDB04_05_F0\r
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG CYREG_B0_UDB04_05_F1\r
-#define SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG CYREG_B0_UDB04_A0_A1\r
-#define SDCard_BSPIM_sR8_Dp_u0__A0_REG CYREG_B0_UDB04_A0\r
-#define SDCard_BSPIM_sR8_Dp_u0__A1_REG CYREG_B0_UDB04_A1\r
-#define SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG CYREG_B0_UDB04_D0_D1\r
-#define SDCard_BSPIM_sR8_Dp_u0__D0_REG CYREG_B0_UDB04_D0\r
-#define SDCard_BSPIM_sR8_Dp_u0__D1_REG CYREG_B0_UDB04_D1\r
-#define SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG CYREG_B0_UDB04_ACTL\r
-#define SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG CYREG_B0_UDB04_F0_F1\r
-#define SDCard_BSPIM_sR8_Dp_u0__F0_REG CYREG_B0_UDB04_F0\r
-#define SDCard_BSPIM_sR8_Dp_u0__F1_REG CYREG_B0_UDB04_F1\r
+#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B1_UDB06_MSK\r
+#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB06_ACTL\r
+#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B1_UDB06_ST\r
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B0_UDB05_06_A0\r
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B0_UDB05_06_A1\r
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG CYREG_B0_UDB05_06_D0\r
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG CYREG_B0_UDB05_06_D1\r
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG CYREG_B0_UDB05_06_ACTL\r
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG CYREG_B0_UDB05_06_F0\r
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG CYREG_B0_UDB05_06_F1\r
+#define SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG CYREG_B0_UDB05_A0_A1\r
+#define SDCard_BSPIM_sR8_Dp_u0__A0_REG CYREG_B0_UDB05_A0\r
+#define SDCard_BSPIM_sR8_Dp_u0__A1_REG CYREG_B0_UDB05_A1\r
+#define SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG CYREG_B0_UDB05_D0_D1\r
+#define SDCard_BSPIM_sR8_Dp_u0__D0_REG CYREG_B0_UDB05_D0\r
+#define SDCard_BSPIM_sR8_Dp_u0__D1_REG CYREG_B0_UDB05_D1\r
+#define SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG CYREG_B0_UDB05_ACTL\r
+#define SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG CYREG_B0_UDB05_F0_F1\r
+#define SDCard_BSPIM_sR8_Dp_u0__F0_REG CYREG_B0_UDB05_F0\r
+#define SDCard_BSPIM_sR8_Dp_u0__F1_REG CYREG_B0_UDB05_F1\r
+#define SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL\r
+#define SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL\r
\r
/* USBFS_dp_int */\r
#define USBFS_dp_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
#define SD_Data_Clk__PM_STBY_CFG CYREG_PM_STBY_CFG2\r
#define SD_Data_Clk__PM_STBY_MSK 0x01u\r
\r
-/* SD_Init_Clk */\r
-#define SD_Init_Clk__CFG0 CYREG_CLKDIST_DCFG3_CFG0\r
-#define SD_Init_Clk__CFG1 CYREG_CLKDIST_DCFG3_CFG1\r
-#define SD_Init_Clk__CFG2 CYREG_CLKDIST_DCFG3_CFG2\r
-#define SD_Init_Clk__CFG2_SRC_SEL_MASK 0x07u\r
-#define SD_Init_Clk__INDEX 0x03u\r
-#define SD_Init_Clk__PM_ACT_CFG CYREG_PM_ACT_CFG2\r
-#define SD_Init_Clk__PM_ACT_MSK 0x08u\r
-#define SD_Init_Clk__PM_STBY_CFG CYREG_PM_STBY_CFG2\r
-#define SD_Init_Clk__PM_STBY_MSK 0x08u\r
-\r
/* timer_clock */\r
#define timer_clock__CFG0 CYREG_CLKDIST_DCFG2_CFG0\r
#define timer_clock__CFG1 CYREG_CLKDIST_DCFG2_CFG1\r
/* scsiTarget */\r
#define scsiTarget_StatusReg__0__MASK 0x01u\r
#define scsiTarget_StatusReg__0__POS 0\r
-#define scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB04_05_ACTL\r
-#define scsiTarget_StatusReg__16BIT_STATUS_REG CYREG_B0_UDB04_05_ST\r
+#define scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB00_01_ACTL\r
+#define scsiTarget_StatusReg__16BIT_STATUS_REG CYREG_B0_UDB00_01_ST\r
#define scsiTarget_StatusReg__1__MASK 0x02u\r
#define scsiTarget_StatusReg__1__POS 1\r
#define scsiTarget_StatusReg__2__MASK 0x04u\r
#define scsiTarget_StatusReg__4__MASK 0x10u\r
#define scsiTarget_StatusReg__4__POS 4\r
#define scsiTarget_StatusReg__MASK 0x1Fu\r
-#define scsiTarget_StatusReg__MASK_REG CYREG_B0_UDB04_MSK\r
-#define scsiTarget_StatusReg__STATUS_AUX_CTL_REG CYREG_B0_UDB04_ACTL\r
-#define scsiTarget_StatusReg__STATUS_REG CYREG_B0_UDB04_ST\r
+#define scsiTarget_StatusReg__MASK_REG CYREG_B0_UDB00_MSK\r
+#define scsiTarget_StatusReg__STATUS_AUX_CTL_REG CYREG_B0_UDB00_ACTL\r
+#define scsiTarget_StatusReg__STATUS_REG CYREG_B0_UDB00_ST\r
#define scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB03_04_ACTL\r
#define scsiTarget_datapath_PI__16BIT_STATUS_REG CYREG_B0_UDB03_04_ST\r
#define scsiTarget_datapath_PI__MASK_REG CYREG_B0_UDB03_MSK\r
#define scsiTarget_datapath__MSK_DP_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL\r
#define scsiTarget_datapath__PER_DP_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL\r
\r
-/* SD_Clk_Ctl */\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__REMOVED 1u\r
-\r
/* USBFS_ep_0 */\r
#define USBFS_ep_0__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
#define USBFS_ep_0__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
}\r
#endif\r
\r
-#define CY_CFG_BASE_ADDR_COUNT 37u\r
+#define CY_CFG_BASE_ADDR_COUNT 36u\r
CYPACKED typedef struct\r
{\r
uint8 offset;\r
CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_DCFG1_CFG0 + 0x2u), 0x58u);\r
CY_SET_XTND_REG16((void CYFAR *)(CYREG_CLKDIST_DCFG2_CFG0), 0x0017u);\r
CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_DCFG2_CFG0 + 0x2u), 0x19u);\r
- CY_SET_XTND_REG16((void CYFAR *)(CYREG_CLKDIST_DCFG3_CFG0), 0x001Du);\r
- CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_DCFG3_CFG0 + 0x2u), 0x19u);\r
\r
/* Configure ILO based on settings from Clock DWR */\r
CY_SET_XTND_REG8((void CYFAR *)(CYREG_SLOWCLK_ILO_CR0), 0x06u);\r
CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_UCFG), 0x00u);\r
CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_LD), 0x02u);\r
\r
- CY_SET_XTND_REG8((void CYFAR *)(CYREG_PM_ACT_CFG2), ((CY_GET_XTND_REG8((void CYFAR *)CYREG_PM_ACT_CFG2) | 0x0Fu)));\r
+ CY_SET_XTND_REG8((void CYFAR *)(CYREG_PM_ACT_CFG2), ((CY_GET_XTND_REG8((void CYFAR *)CYREG_PM_ACT_CFG2) | 0x07u)));\r
}\r
\r
\r
0x40004502u, /* Base address: 0x40004500 Count: 2 */\r
0x40004F02u, /* Base address: 0x40004F00 Count: 2 */\r
0x4000520Au, /* Base address: 0x40005200 Count: 10 */\r
- 0x40006401u, /* Base address: 0x40006400 Count: 1 */\r
- 0x40006501u, /* Base address: 0x40006500 Count: 1 */\r
- 0x40010052u, /* Base address: 0x40010000 Count: 82 */\r
- 0x40010139u, /* Base address: 0x40010100 Count: 57 */\r
- 0x40010241u, /* Base address: 0x40010200 Count: 65 */\r
- 0x4001035Cu, /* Base address: 0x40010300 Count: 92 */\r
- 0x40010417u, /* Base address: 0x40010400 Count: 23 */\r
- 0x40010560u, /* Base address: 0x40010500 Count: 96 */\r
- 0x4001065Du, /* Base address: 0x40010600 Count: 93 */\r
- 0x40010754u, /* Base address: 0x40010700 Count: 84 */\r
- 0x40010804u, /* Base address: 0x40010800 Count: 4 */\r
- 0x4001090Eu, /* Base address: 0x40010900 Count: 14 */\r
- 0x40010B12u, /* Base address: 0x40010B00 Count: 18 */\r
- 0x40010C47u, /* Base address: 0x40010C00 Count: 71 */\r
- 0x40010D45u, /* Base address: 0x40010D00 Count: 69 */\r
- 0x40010F05u, /* Base address: 0x40010F00 Count: 5 */\r
- 0x40011505u, /* Base address: 0x40011500 Count: 5 */\r
- 0x4001164Cu, /* Base address: 0x40011600 Count: 76 */\r
- 0x4001174Bu, /* Base address: 0x40011700 Count: 75 */\r
- 0x4001190Au, /* Base address: 0x40011900 Count: 10 */\r
- 0x40011B03u, /* Base address: 0x40011B00 Count: 3 */\r
- 0x40014019u, /* Base address: 0x40014000 Count: 25 */\r
- 0x40014117u, /* Base address: 0x40014100 Count: 23 */\r
- 0x4001420Fu, /* Base address: 0x40014200 Count: 15 */\r
- 0x4001430Du, /* Base address: 0x40014300 Count: 13 */\r
- 0x4001440Du, /* Base address: 0x40014400 Count: 13 */\r
- 0x40014516u, /* Base address: 0x40014500 Count: 22 */\r
- 0x40014608u, /* Base address: 0x40014600 Count: 8 */\r
- 0x40014705u, /* Base address: 0x40014700 Count: 5 */\r
+ 0x40006402u, /* Base address: 0x40006400 Count: 2 */\r
+ 0x4001004Bu, /* Base address: 0x40010000 Count: 75 */\r
+ 0x40010138u, /* Base address: 0x40010100 Count: 56 */\r
+ 0x40010248u, /* Base address: 0x40010200 Count: 72 */\r
+ 0x4001035Au, /* Base address: 0x40010300 Count: 90 */\r
+ 0x40010462u, /* Base address: 0x40010400 Count: 98 */\r
+ 0x40010551u, /* Base address: 0x40010500 Count: 81 */\r
+ 0x40010657u, /* Base address: 0x40010600 Count: 87 */\r
+ 0x40010752u, /* Base address: 0x40010700 Count: 82 */\r
+ 0x4001090Au, /* Base address: 0x40010900 Count: 10 */\r
+ 0x40010A04u, /* Base address: 0x40010A00 Count: 4 */\r
+ 0x40010B1Au, /* Base address: 0x40010B00 Count: 26 */\r
+ 0x40010C3Eu, /* Base address: 0x40010C00 Count: 62 */\r
+ 0x40010D42u, /* Base address: 0x40010D00 Count: 66 */\r
+ 0x40010F06u, /* Base address: 0x40010F00 Count: 6 */\r
+ 0x40011506u, /* Base address: 0x40011500 Count: 6 */\r
+ 0x40011652u, /* Base address: 0x40011600 Count: 82 */\r
+ 0x4001174Eu, /* Base address: 0x40011700 Count: 78 */\r
+ 0x40011907u, /* Base address: 0x40011900 Count: 7 */\r
+ 0x40011B05u, /* Base address: 0x40011B00 Count: 5 */\r
+ 0x40014017u, /* Base address: 0x40014000 Count: 23 */\r
+ 0x40014116u, /* Base address: 0x40014100 Count: 22 */\r
+ 0x40014210u, /* Base address: 0x40014200 Count: 16 */\r
+ 0x4001430Bu, /* Base address: 0x40014300 Count: 11 */\r
+ 0x4001440Cu, /* Base address: 0x40014400 Count: 12 */\r
+ 0x40014518u, /* Base address: 0x40014500 Count: 24 */\r
+ 0x40014607u, /* Base address: 0x40014600 Count: 7 */\r
+ 0x4001470Au, /* Base address: 0x40014700 Count: 10 */\r
0x40014807u, /* Base address: 0x40014800 Count: 7 */\r
- 0x4001490Au, /* Base address: 0x40014900 Count: 10 */\r
+ 0x40014909u, /* Base address: 0x40014900 Count: 9 */\r
0x40014C01u, /* Base address: 0x40014C00 Count: 1 */\r
- 0x40015005u, /* Base address: 0x40015000 Count: 5 */\r
+ 0x40015006u, /* Base address: 0x40015000 Count: 6 */\r
0x40015104u, /* Base address: 0x40015100 Count: 4 */\r
};\r
\r
{0x36u, 0x02u},\r
{0x7Eu, 0x02u},\r
{0x01u, 0x20u},\r
- {0x0Au, 0x1Bu},\r
- {0x00u, 0x14u},\r
- {0x01u, 0x01u},\r
+ {0x0Au, 0x4Bu},\r
+ {0x00u, 0x05u},\r
+ {0x01u, 0x13u},\r
{0x18u, 0x0Cu},\r
{0x19u, 0x08u},\r
{0x1Cu, 0x61u},\r
- {0x20u, 0x60u},\r
- {0x21u, 0xC0u},\r
+ {0x20u, 0x90u},\r
+ {0x21u, 0x58u},\r
{0x30u, 0x06u},\r
{0x31u, 0x0Cu},\r
{0x7Cu, 0x40u},\r
{0x23u, 0x02u},\r
{0x86u, 0x0Fu},\r
- {0x00u, 0x03u},\r
{0x01u, 0x09u},\r
- {0x02u, 0x0Cu},\r
{0x03u, 0x24u},\r
- {0x04u, 0x09u},\r
- {0x06u, 0x06u},\r
- {0x07u, 0x09u},\r
- {0x08u, 0xFFu},\r
- {0x09u, 0x40u},\r
- {0x0Cu, 0x90u},\r
- {0x0Eu, 0x60u},\r
- {0x0Fu, 0x30u},\r
- {0x10u, 0xFFu},\r
- {0x11u, 0x09u},\r
- {0x13u, 0x12u},\r
- {0x14u, 0x05u},\r
- {0x15u, 0x40u},\r
- {0x16u, 0x0Au},\r
+ {0x05u, 0x09u},\r
+ {0x06u, 0x0Eu},\r
+ {0x07u, 0x12u},\r
+ {0x0Bu, 0x30u},\r
+ {0x0Cu, 0x21u},\r
+ {0x0Eu, 0x84u},\r
+ {0x0Fu, 0x46u},\r
+ {0x12u, 0x21u},\r
+ {0x16u, 0xC0u},\r
+ {0x18u, 0x21u},\r
+ {0x1Au, 0x42u},\r
{0x1Bu, 0x01u},\r
- {0x1Cu, 0x0Fu},\r
- {0x1Eu, 0xF0u},\r
- {0x1Fu, 0x06u},\r
- {0x20u, 0x50u},\r
- {0x22u, 0xA0u},\r
- {0x23u, 0x08u},\r
- {0x25u, 0x80u},\r
- {0x26u, 0xFFu},\r
- {0x29u, 0x40u},\r
- {0x2Cu, 0x30u},\r
- {0x2Du, 0x40u},\r
- {0x2Eu, 0xC0u},\r
- {0x31u, 0x38u},\r
- {0x32u, 0xFFu},\r
- {0x33u, 0x40u},\r
- {0x35u, 0x80u},\r
- {0x37u, 0x07u},\r
- {0x39u, 0x08u},\r
- {0x3Eu, 0x04u},\r
- {0x3Fu, 0x14u},\r
+ {0x1Eu, 0x20u},\r
+ {0x1Fu, 0x08u},\r
+ {0x21u, 0x40u},\r
+ {0x22u, 0x10u},\r
+ {0x23u, 0x80u},\r
+ {0x26u, 0x01u},\r
+ {0x2Bu, 0x80u},\r
+ {0x2Cu, 0x08u},\r
+ {0x2Eu, 0x10u},\r
+ {0x2Fu, 0x09u},\r
+ {0x30u, 0x18u},\r
+ {0x31u, 0x07u},\r
+ {0x32u, 0xE0u},\r
+ {0x33u, 0xC0u},\r
+ {0x34u, 0x07u},\r
+ {0x35u, 0x38u},\r
+ {0x3Eu, 0x01u},\r
+ {0x3Fu, 0x04u},\r
{0x58u, 0x04u},\r
{0x59u, 0x04u},\r
- {0x5Cu, 0x10u},\r
+ {0x5Bu, 0x04u},\r
+ {0x5Cu, 0x11u},\r
{0x5Fu, 0x01u},\r
- {0x81u, 0x10u},\r
- {0x83u, 0x20u},\r
- {0x85u, 0x43u},\r
- {0x86u, 0xC1u},\r
+ {0x80u, 0x30u},\r
+ {0x81u, 0x01u},\r
+ {0x82u, 0xC0u},\r
+ {0x84u, 0x09u},\r
+ {0x85u, 0x02u},\r
+ {0x86u, 0x06u},\r
{0x87u, 0x04u},\r
- {0x89u, 0x45u},\r
- {0x8Au, 0x04u},\r
+ {0x88u, 0xFFu},\r
{0x8Bu, 0x02u},\r
- {0x8Du, 0x08u},\r
- {0x8Eu, 0x02u},\r
- {0x90u, 0x24u},\r
- {0x91u, 0x41u},\r
- {0x92u, 0x90u},\r
- {0x93u, 0x06u},\r
- {0x95u, 0x04u},\r
- {0x96u, 0x24u},\r
- {0x97u, 0x03u},\r
- {0x9Au, 0x18u},\r
- {0x9Fu, 0x10u},\r
- {0xA0u, 0x01u},\r
- {0xA2u, 0x02u},\r
- {0xA6u, 0x20u},\r
- {0xA8u, 0x24u},\r
- {0xAAu, 0x48u},\r
- {0xABu, 0x20u},\r
- {0xB1u, 0x08u},\r
- {0xB2u, 0xE0u},\r
- {0xB3u, 0x07u},\r
- {0xB4u, 0x1Cu},\r
- {0xB5u, 0x30u},\r
- {0xB6u, 0x03u},\r
- {0xB7u, 0x40u},\r
- {0xBBu, 0x08u},\r
+ {0x8Cu, 0x50u},\r
+ {0x8Du, 0x02u},\r
+ {0x8Eu, 0xA0u},\r
+ {0x8Fu, 0x08u},\r
+ {0x91u, 0x01u},\r
+ {0x94u, 0x03u},\r
+ {0x96u, 0x0Cu},\r
+ {0x97u, 0x0Cu},\r
+ {0x98u, 0x90u},\r
+ {0x9Au, 0x60u},\r
+ {0x9Cu, 0xFFu},\r
+ {0x9Fu, 0x02u},\r
+ {0xA4u, 0x05u},\r
+ {0xA5u, 0x01u},\r
+ {0xA6u, 0x0Au},\r
+ {0xA9u, 0x01u},\r
+ {0xAAu, 0xFFu},\r
+ {0xACu, 0x0Fu},\r
+ {0xAEu, 0xF0u},\r
+ {0xB5u, 0x0Eu},\r
+ {0xB6u, 0xFFu},\r
+ {0xB7u, 0x01u},\r
+ {0xB9u, 0x80u},\r
{0xBEu, 0x40u},\r
- {0xBFu, 0x51u},\r
+ {0xBFu, 0x40u},\r
{0xD8u, 0x04u},\r
{0xD9u, 0x04u},\r
- {0xDCu, 0x01u},\r
+ {0xDCu, 0x10u},\r
{0xDFu, 0x01u},\r
- {0x00u, 0x80u},\r
- {0x02u, 0xA0u},\r
- {0x03u, 0x08u},\r
- {0x05u, 0x14u},\r
- {0x07u, 0x01u},\r
- {0x08u, 0x40u},\r
- {0x09u, 0x05u},\r
- {0x0Au, 0x01u},\r
- {0x0Du, 0x25u},\r
- {0x0Fu, 0x08u},\r
- {0x11u, 0x84u},\r
- {0x12u, 0x04u},\r
- {0x13u, 0x22u},\r
- {0x14u, 0x40u},\r
- {0x15u, 0x20u},\r
- {0x16u, 0x20u},\r
- {0x18u, 0x10u},\r
- {0x1Du, 0x24u},\r
- {0x1Eu, 0x20u},\r
- {0x1Fu, 0x80u},\r
- {0x20u, 0x20u},\r
- {0x22u, 0xD0u},\r
- {0x23u, 0xC0u},\r
- {0x24u, 0x40u},\r
- {0x25u, 0x80u},\r
- {0x26u, 0x04u},\r
- {0x27u, 0x28u},\r
- {0x28u, 0x08u},\r
- {0x2Au, 0x02u},\r
- {0x2Bu, 0x22u},\r
- {0x2Cu, 0x04u},\r
- {0x31u, 0x01u},\r
- {0x32u, 0x44u},\r
- {0x33u, 0x10u},\r
- {0x36u, 0x06u},\r
- {0x37u, 0x80u},\r
- {0x38u, 0x10u},\r
- {0x39u, 0x0Au},\r
- {0x3Bu, 0x40u},\r
+ {0x00u, 0x88u},\r
+ {0x03u, 0x20u},\r
+ {0x05u, 0x20u},\r
+ {0x06u, 0x42u},\r
+ {0x07u, 0x60u},\r
+ {0x08u, 0x01u},\r
+ {0x0Au, 0x24u},\r
+ {0x0Bu, 0x01u},\r
+ {0x0Eu, 0x08u},\r
+ {0x0Fu, 0x22u},\r
+ {0x11u, 0x44u},\r
+ {0x12u, 0x40u},\r
+ {0x15u, 0xC0u},\r
+ {0x16u, 0x01u},\r
+ {0x17u, 0x18u},\r
+ {0x19u, 0x02u},\r
+ {0x1Au, 0x20u},\r
+ {0x1Bu, 0x30u},\r
+ {0x1Eu, 0x01u},\r
+ {0x20u, 0x40u},\r
+ {0x21u, 0x18u},\r
+ {0x22u, 0x01u},\r
+ {0x24u, 0x02u},\r
+ {0x27u, 0x08u},\r
+ {0x28u, 0x05u},\r
+ {0x29u, 0x40u},\r
+ {0x2Au, 0x11u},\r
+ {0x2Du, 0x08u},\r
+ {0x2Eu, 0x10u},\r
+ {0x30u, 0xA0u},\r
+ {0x35u, 0x40u},\r
+ {0x36u, 0x02u},\r
+ {0x37u, 0x08u},\r
+ {0x38u, 0x44u},\r
+ {0x39u, 0x22u},\r
+ {0x3Cu, 0x80u},\r
+ {0x3Du, 0x10u},\r
{0x3Eu, 0x05u},\r
- {0x3Fu, 0x90u},\r
- {0x46u, 0x40u},\r
- {0x47u, 0x01u},\r
- {0x86u, 0x20u},\r
- {0x87u, 0x02u},\r
- {0x88u, 0x08u},\r
- {0x8Cu, 0x40u},\r
- {0x8Du, 0x01u},\r
- {0x8Fu, 0x08u},\r
- {0xC0u, 0xEFu},\r
- {0xC2u, 0x7Du},\r
- {0xC4u, 0x7Du},\r
- {0xCAu, 0x2Fu},\r
- {0xCCu, 0xDFu},\r
+ {0x58u, 0x82u},\r
+ {0x59u, 0x14u},\r
+ {0x61u, 0x80u},\r
+ {0x81u, 0x10u},\r
+ {0x82u, 0x80u},\r
+ {0x84u, 0x04u},\r
+ {0x89u, 0x10u},\r
+ {0x8Cu, 0x01u},\r
+ {0xC0u, 0xF5u},\r
+ {0xC2u, 0xEFu},\r
+ {0xC4u, 0xEDu},\r
+ {0xCAu, 0x6Du},\r
+ {0xCCu, 0xDCu},\r
{0xCEu, 0xFFu},\r
- {0xE2u, 0x08u},\r
- {0xE6u, 0x72u},\r
- {0x21u, 0x01u},\r
- {0x35u, 0x01u},\r
- {0x3Fu, 0x10u},\r
+ {0xD6u, 0x0Fu},\r
+ {0xD8u, 0x08u},\r
+ {0xE2u, 0x48u},\r
+ {0xE6u, 0x02u},\r
+ {0x06u, 0xFFu},\r
+ {0x08u, 0xFFu},\r
+ {0x0Cu, 0x50u},\r
+ {0x0Du, 0x04u},\r
+ {0x0Eu, 0xA0u},\r
+ {0x0Fu, 0x03u},\r
+ {0x11u, 0x01u},\r
+ {0x12u, 0xFFu},\r
+ {0x13u, 0x06u},\r
+ {0x14u, 0x03u},\r
+ {0x15u, 0x03u},\r
+ {0x16u, 0x0Cu},\r
+ {0x17u, 0x04u},\r
+ {0x18u, 0x60u},\r
+ {0x19u, 0x05u},\r
+ {0x1Au, 0x90u},\r
+ {0x1Bu, 0x02u},\r
+ {0x1Cu, 0x0Fu},\r
+ {0x1Eu, 0xF0u},\r
+ {0x24u, 0x05u},\r
+ {0x26u, 0x0Au},\r
+ {0x28u, 0x06u},\r
+ {0x2Au, 0x09u},\r
+ {0x2Cu, 0x30u},\r
+ {0x2Eu, 0xC0u},\r
+ {0x32u, 0xFFu},\r
+ {0x37u, 0x07u},\r
+ {0x3Bu, 0x80u},\r
+ {0x3Eu, 0x04u},\r
+ {0x58u, 0x04u},\r
{0x59u, 0x04u},\r
- {0x5Bu, 0x04u},\r
{0x5Fu, 0x01u},\r
- {0x80u, 0x80u},\r
- {0x81u, 0x40u},\r
- {0x84u, 0x02u},\r
- {0x85u, 0x01u},\r
- {0x8Au, 0x1Fu},\r
- {0x8Bu, 0x20u},\r
- {0x8Cu, 0x5Bu},\r
- {0x8Du, 0x80u},\r
- {0x8Eu, 0x24u},\r
- {0x94u, 0x03u},\r
- {0x95u, 0x08u},\r
- {0x96u, 0x0Cu},\r
- {0x97u, 0x12u},\r
- {0x98u, 0x58u},\r
- {0x99u, 0x0Bu},\r
- {0x9Au, 0x24u},\r
- {0x9Bu, 0x24u},\r
- {0xA0u, 0x0Cu},\r
- {0xA1u, 0x34u},\r
- {0xA2u, 0x40u},\r
- {0xA3u, 0x0Bu},\r
- {0xA6u, 0x01u},\r
- {0xA8u, 0x40u},\r
- {0xAAu, 0x37u},\r
- {0xABu, 0x3Fu},\r
- {0xB0u, 0x1Fu},\r
- {0xB1u, 0x80u},\r
- {0xB2u, 0x20u},\r
- {0xB3u, 0x38u},\r
- {0xB4u, 0x80u},\r
- {0xB5u, 0x07u},\r
- {0xB6u, 0x40u},\r
- {0xB7u, 0x40u},\r
- {0xBEu, 0x54u},\r
- {0xBFu, 0x41u},\r
- {0xC0u, 0x64u},\r
+ {0x82u, 0x3Fu},\r
+ {0x84u, 0x01u},\r
+ {0x89u, 0x01u},\r
+ {0x8Cu, 0x34u},\r
+ {0x8Eu, 0x4Bu},\r
+ {0x98u, 0x0Bu},\r
+ {0x9Au, 0x64u},\r
+ {0x9Cu, 0x08u},\r
+ {0x9Eu, 0x52u},\r
+ {0xA6u, 0x20u},\r
+ {0xB2u, 0x40u},\r
+ {0xB4u, 0x07u},\r
+ {0xB6u, 0x38u},\r
+ {0xB7u, 0x01u},\r
+ {0xBEu, 0x04u},\r
+ {0xBFu, 0x40u},\r
+ {0xC0u, 0x54u},\r
{0xC1u, 0x02u},\r
{0xC2u, 0x30u},\r
- {0xC5u, 0xCDu},\r
- {0xC6u, 0x2Eu},\r
- {0xC7u, 0x0Fu},\r
+ {0xC5u, 0xE2u},\r
+ {0xC6u, 0xCFu},\r
+ {0xC7u, 0x0Du},\r
{0xC8u, 0x1Fu},\r
{0xC9u, 0xFFu},\r
{0xCAu, 0xFFu},\r
{0xD9u, 0x04u},\r
{0xDAu, 0x04u},\r
{0xDBu, 0x04u},\r
- {0xDCu, 0x11u},\r
+ {0xDCu, 0x01u},\r
{0xDDu, 0x01u},\r
{0xDFu, 0x01u},\r
{0xE2u, 0xC0u},\r
{0xE8u, 0x40u},\r
{0xE9u, 0x40u},\r
{0xEEu, 0x08u},\r
- {0x00u, 0x02u},\r
- {0x01u, 0x08u},\r
- {0x03u, 0x0Au},\r
- {0x09u, 0x20u},\r
- {0x0Bu, 0x20u},\r
- {0x10u, 0x80u},\r
- {0x11u, 0x04u},\r
- {0x12u, 0x08u},\r
- {0x18u, 0x04u},\r
- {0x19u, 0x42u},\r
- {0x1Au, 0x10u},\r
- {0x1Bu, 0x02u},\r
- {0x21u, 0x34u},\r
- {0x22u, 0x09u},\r
- {0x23u, 0x05u},\r
- {0x27u, 0x04u},\r
- {0x29u, 0x02u},\r
- {0x2Bu, 0x08u},\r
- {0x2Cu, 0x08u},\r
- {0x2Du, 0x20u},\r
- {0x2Fu, 0x80u},\r
- {0x31u, 0x20u},\r
- {0x32u, 0x08u},\r
- {0x38u, 0x20u},\r
- {0x39u, 0x85u},\r
- {0x41u, 0x11u},\r
- {0x42u, 0x10u},\r
- {0x43u, 0x02u},\r
- {0x48u, 0x90u},\r
- {0x49u, 0x08u},\r
- {0x4Au, 0x08u},\r
- {0x50u, 0x58u},\r
- {0x5Au, 0xA2u},\r
- {0x5Bu, 0x04u},\r
- {0x60u, 0x44u},\r
- {0x61u, 0x08u},\r
- {0x63u, 0x01u},\r
- {0x69u, 0x10u},\r
- {0x6Au, 0x40u},\r
- {0x6Bu, 0x50u},\r
- {0x6Du, 0x64u},\r
- {0x71u, 0x10u},\r
- {0x72u, 0x22u},\r
- {0x73u, 0x40u},\r
- {0x81u, 0x40u},\r
- {0x82u, 0x40u},\r
- {0x87u, 0x80u},\r
- {0x89u, 0x05u},\r
- {0x8Au, 0x80u},\r
- {0x8Bu, 0x80u},\r
- {0x8Cu, 0x08u},\r
+ {0x00u, 0x80u},\r
+ {0x02u, 0x40u},\r
+ {0x03u, 0x10u},\r
+ {0x05u, 0x20u},\r
+ {0x06u, 0x02u},\r
+ {0x07u, 0x10u},\r
+ {0x0Au, 0x05u},\r
+ {0x0Cu, 0x01u},\r
+ {0x0Du, 0x40u},\r
+ {0x0Eu, 0x08u},\r
+ {0x0Fu, 0x20u},\r
+ {0x13u, 0x04u},\r
+ {0x14u, 0x08u},\r
+ {0x16u, 0x01u},\r
+ {0x17u, 0x68u},\r
+ {0x18u, 0x14u},\r
+ {0x19u, 0x40u},\r
+ {0x1Au, 0x0Du},\r
+ {0x1Bu, 0x80u},\r
+ {0x1Eu, 0x10u},\r
+ {0x22u, 0x40u},\r
+ {0x25u, 0x40u},\r
+ {0x28u, 0x01u},\r
+ {0x29u, 0x04u},\r
+ {0x2Bu, 0x21u},\r
+ {0x35u, 0x11u},\r
+ {0x36u, 0x08u},\r
+ {0x3Au, 0x20u},\r
+ {0x3Du, 0x80u},\r
+ {0x3Eu, 0x80u},\r
+ {0x40u, 0x14u},\r
+ {0x41u, 0x01u},\r
+ {0x49u, 0x40u},\r
+ {0x4Au, 0x40u},\r
+ {0x4Bu, 0x04u},\r
+ {0x51u, 0x10u},\r
+ {0x52u, 0x80u},\r
+ {0x53u, 0x28u},\r
+ {0x58u, 0x14u},\r
+ {0x59u, 0x02u},\r
+ {0x5Au, 0x80u},\r
+ {0x60u, 0x02u},\r
+ {0x62u, 0x04u},\r
+ {0x63u, 0x88u},\r
+ {0x68u, 0x80u},\r
+ {0x69u, 0x54u},\r
+ {0x70u, 0x20u},\r
+ {0x73u, 0x51u},\r
+ {0x83u, 0x04u},\r
+ {0x84u, 0x80u},\r
+ {0x86u, 0x42u},\r
+ {0x88u, 0x02u},\r
+ {0x89u, 0x02u},\r
+ {0x8Cu, 0x04u},\r
{0x8Du, 0x40u},\r
- {0x8Fu, 0x08u},\r
- {0x90u, 0x40u},\r
- {0x92u, 0x20u},\r
- {0x93u, 0x20u},\r
- {0x94u, 0x80u},\r
- {0x95u, 0x2Eu},\r
- {0x96u, 0x0Du},\r
- {0x97u, 0x10u},\r
- {0x9Au, 0x44u},\r
- {0x9Bu, 0x80u},\r
- {0x9Cu, 0x08u},\r
- {0x9Du, 0x11u},\r
- {0x9Eu, 0x22u},\r
- {0x9Fu, 0x12u},\r
- {0xA1u, 0x80u},\r
- {0xA2u, 0x90u},\r
- {0xA3u, 0x04u},\r
- {0xA4u, 0x48u},\r
- {0xA5u, 0x44u},\r
- {0xA6u, 0x02u},\r
- {0xA7u, 0x20u},\r
- {0xABu, 0x40u},\r
- {0xACu, 0x10u},\r
- {0xAFu, 0x91u},\r
- {0xB0u, 0x04u},\r
- {0xB7u, 0x08u},\r
- {0xC0u, 0x0Fu},\r
- {0xC2u, 0x06u},\r
- {0xC4u, 0x0Eu},\r
- {0xCAu, 0x85u},\r
- {0xCCu, 0x06u},\r
- {0xCEu, 0x0Fu},\r
+ {0x92u, 0x02u},\r
+ {0x94u, 0x04u},\r
+ {0x95u, 0x96u},\r
+ {0x96u, 0x14u},\r
+ {0x97u, 0x81u},\r
+ {0x9Au, 0x30u},\r
+ {0x9Bu, 0x08u},\r
+ {0x9Cu, 0x80u},\r
+ {0x9Du, 0x6Cu},\r
+ {0x9Eu, 0x02u},\r
+ {0x9Fu, 0x70u},\r
+ {0xA0u, 0x04u},\r
+ {0xA3u, 0x10u},\r
+ {0xA4u, 0xE0u},\r
+ {0xA5u, 0x80u},\r
+ {0xA6u, 0x86u},\r
+ {0xA7u, 0x09u},\r
+ {0xAAu, 0x30u},\r
+ {0xAFu, 0x40u},\r
+ {0xB0u, 0x02u},\r
+ {0xB1u, 0x0Au},\r
+ {0xB3u, 0x08u},\r
+ {0xC0u, 0xEDu},\r
+ {0xC2u, 0xF3u},\r
+ {0xC4u, 0xE4u},\r
+ {0xCCu, 0xE0u},\r
+ {0xCEu, 0x14u},\r
{0xD0u, 0x07u},\r
- {0xD2u, 0x04u},\r
+ {0xD2u, 0x08u},\r
{0xD6u, 0x0Fu},\r
{0xD8u, 0x0Fu},\r
- {0xE2u, 0x20u},\r
- {0xE6u, 0x09u},\r
- {0xEAu, 0x06u},\r
- {0xEEu, 0x02u},\r
- {0x85u, 0x02u},\r
- {0x87u, 0x05u},\r
- {0x8Fu, 0x02u},\r
- {0x97u, 0x03u},\r
- {0x9Au, 0x01u},\r
- {0x9Fu, 0x0Cu},\r
- {0xA1u, 0x02u},\r
- {0xA2u, 0x04u},\r
- {0xA3u, 0x08u},\r
- {0xA4u, 0x05u},\r
- {0xA6u, 0x0Au},\r
- {0xAAu, 0x02u},\r
- {0xAEu, 0x08u},\r
- {0xB1u, 0x0Eu},\r
- {0xB4u, 0x0Cu},\r
- {0xB5u, 0x01u},\r
- {0xB6u, 0x03u},\r
- {0xBEu, 0x50u},\r
+ {0xE6u, 0x0Cu},\r
+ {0xEAu, 0x04u},\r
+ {0xECu, 0x04u},\r
+ {0xEEu, 0x21u},\r
+ {0x01u, 0x9Bu},\r
+ {0x03u, 0x04u},\r
+ {0x04u, 0x03u},\r
+ {0x06u, 0x0Cu},\r
+ {0x07u, 0x40u},\r
+ {0x08u, 0x30u},\r
+ {0x09u, 0x0Cu},\r
+ {0x0Au, 0xC0u},\r
+ {0x0Bu, 0x80u},\r
+ {0x0Cu, 0x0Fu},\r
+ {0x0Du, 0x20u},\r
+ {0x0Eu, 0xF0u},\r
+ {0x0Fu, 0x40u},\r
+ {0x10u, 0x50u},\r
+ {0x12u, 0xA0u},\r
+ {0x15u, 0x98u},\r
+ {0x17u, 0x04u},\r
+ {0x1Bu, 0x01u},\r
+ {0x1Cu, 0x06u},\r
+ {0x1Du, 0x80u},\r
+ {0x1Eu, 0x09u},\r
+ {0x1Fu, 0x17u},\r
+ {0x20u, 0x05u},\r
+ {0x22u, 0x0Au},\r
+ {0x23u, 0x20u},\r
+ {0x24u, 0x60u},\r
+ {0x25u, 0x03u},\r
+ {0x26u, 0x90u},\r
+ {0x27u, 0x0Cu},\r
+ {0x29u, 0x02u},\r
+ {0x2Fu, 0x1Fu},\r
+ {0x31u, 0x1Fu},\r
+ {0x34u, 0xFFu},\r
+ {0x35u, 0x60u},\r
+ {0x37u, 0x80u},\r
+ {0x3Eu, 0x10u},\r
+ {0x3Fu, 0x50u},\r
+ {0x58u, 0x04u},\r
+ {0x59u, 0x04u},\r
+ {0x5Cu, 0x10u},\r
+ {0x5Fu, 0x01u},\r
+ {0x81u, 0x35u},\r
+ {0x89u, 0x39u},\r
+ {0x8Bu, 0x42u},\r
+ {0x8Fu, 0x04u},\r
+ {0x91u, 0x20u},\r
+ {0x95u, 0x4Au},\r
+ {0x97u, 0x31u},\r
+ {0x99u, 0x0Bu},\r
+ {0x9Bu, 0x70u},\r
+ {0x9Du, 0x12u},\r
+ {0x9Fu, 0x01u},\r
+ {0xA1u, 0x35u},\r
+ {0xA5u, 0x15u},\r
+ {0xA7u, 0x20u},\r
+ {0xA9u, 0x05u},\r
+ {0xABu, 0x30u},\r
+ {0xADu, 0x30u},\r
+ {0xAFu, 0x05u},\r
+ {0xB3u, 0x78u},\r
+ {0xB5u, 0x04u},\r
+ {0xB7u, 0x03u},\r
+ {0xB9u, 0x08u},\r
+ {0xBBu, 0x80u},\r
{0xBFu, 0x10u},\r
- {0xD8u, 0x04u},\r
+ {0xC0u, 0x62u},\r
+ {0xC1u, 0x04u},\r
+ {0xC2u, 0x10u},\r
+ {0xC4u, 0x05u},\r
+ {0xC5u, 0xCEu},\r
+ {0xC6u, 0xFDu},\r
+ {0xC7u, 0x0Bu},\r
+ {0xC8u, 0x1Fu},\r
+ {0xC9u, 0xFFu},\r
+ {0xCAu, 0xFFu},\r
+ {0xCBu, 0xFFu},\r
+ {0xCCu, 0x22u},\r
+ {0xCEu, 0xF0u},\r
+ {0xCFu, 0x08u},\r
+ {0xD0u, 0x04u},\r
+ {0xD4u, 0x40u},\r
+ {0xD6u, 0x04u},\r
{0xD9u, 0x04u},\r
- {0xDCu, 0x10u},\r
+ {0xDAu, 0x04u},\r
+ {0xDBu, 0x04u},\r
{0xDFu, 0x01u},\r
- {0x01u, 0x41u},\r
- {0x03u, 0x18u},\r
- {0x04u, 0x80u},\r
- {0x05u, 0x80u},\r
- {0x08u, 0x48u},\r
- {0x0Au, 0x86u},\r
- {0x0Du, 0x80u},\r
- {0x0Fu, 0x0Au},\r
- {0x10u, 0x80u},\r
- {0x12u, 0x02u},\r
- {0x13u, 0x10u},\r
- {0x14u, 0x01u},\r
- {0x15u, 0x02u},\r
- {0x17u, 0x28u},\r
- {0x1Au, 0x82u},\r
- {0x1Bu, 0x10u},\r
- {0x1Fu, 0x90u},\r
- {0x20u, 0x40u},\r
+ {0xE2u, 0xC0u},\r
+ {0xE4u, 0x40u},\r
+ {0xE5u, 0x01u},\r
+ {0xE6u, 0x10u},\r
+ {0xE7u, 0x11u},\r
+ {0xE8u, 0xC0u},\r
+ {0xE9u, 0x01u},\r
+ {0xEBu, 0x11u},\r
+ {0xECu, 0x40u},\r
+ {0xEDu, 0x01u},\r
+ {0xEEu, 0x40u},\r
+ {0xEFu, 0x01u},\r
+ {0x00u, 0x64u},\r
+ {0x09u, 0x01u},\r
+ {0x0Au, 0x02u},\r
+ {0x10u, 0x40u},\r
+ {0x12u, 0x10u},\r
+ {0x19u, 0x20u},\r
+ {0x20u, 0x80u},\r
+ {0x21u, 0x81u},\r
{0x22u, 0x10u},\r
- {0x27u, 0x84u},\r
- {0x29u, 0x02u},\r
- {0x2Du, 0x02u},\r
- {0x32u, 0x18u},\r
- {0x33u, 0x40u},\r
- {0x36u, 0x08u},\r
- {0x37u, 0x80u},\r
- {0x38u, 0x40u},\r
- {0x39u, 0x10u},\r
- {0x3Bu, 0x04u},\r
- {0x3Fu, 0x44u},\r
- {0x40u, 0x20u},\r
- {0x42u, 0x04u},\r
- {0x43u, 0x02u},\r
- {0x49u, 0x04u},\r
- {0x4Au, 0x02u},\r
- {0x4Bu, 0x11u},\r
- {0x50u, 0x08u},\r
- {0x51u, 0x60u},\r
- {0x53u, 0x01u},\r
- {0x58u, 0x04u},\r
- {0x59u, 0xA0u},\r
- {0x5Au, 0x01u},\r
- {0x61u, 0x40u},\r
+ {0x24u, 0x02u},\r
+ {0x26u, 0xACu},\r
+ {0x28u, 0xC1u},\r
+ {0x2Au, 0x48u},\r
+ {0x2Bu, 0x08u},\r
+ {0x2Du, 0x40u},\r
+ {0x2Eu, 0x12u},\r
+ {0x2Fu, 0x20u},\r
+ {0x30u, 0x10u},\r
+ {0x32u, 0x04u},\r
+ {0x33u, 0x90u},\r
+ {0x35u, 0x12u},\r
+ {0x36u, 0x88u},\r
+ {0x38u, 0x48u},\r
+ {0x39u, 0xA2u},\r
+ {0x3Du, 0x21u},\r
+ {0x3Fu, 0x80u},\r
+ {0x45u, 0x62u},\r
+ {0x4Du, 0x82u},\r
+ {0x4Eu, 0x08u},\r
+ {0x4Fu, 0x05u},\r
+ {0x55u, 0x04u},\r
+ {0x56u, 0x24u},\r
+ {0x57u, 0x40u},\r
{0x64u, 0x02u},\r
- {0x67u, 0x02u},\r
- {0x79u, 0x02u},\r
- {0x7Au, 0x80u},\r
- {0x7Du, 0x08u},\r
- {0x7Eu, 0x10u},\r
- {0x80u, 0x08u},\r
- {0x83u, 0x05u},\r
- {0x85u, 0x40u},\r
- {0x88u, 0x20u},\r
- {0x8Bu, 0x10u},\r
- {0x8Fu, 0x80u},\r
- {0x90u, 0x80u},\r
- {0x91u, 0x14u},\r
- {0x92u, 0x40u},\r
- {0x93u, 0x44u},\r
- {0x96u, 0x0Cu},\r
- {0x97u, 0x10u},\r
- {0x98u, 0x04u},\r
- {0x99u, 0x62u},\r
- {0x9Au, 0x44u},\r
- {0x9Bu, 0x68u},\r
- {0xA0u, 0x10u},\r
- {0xA1u, 0x80u},\r
- {0xA2u, 0x98u},\r
- {0xA3u, 0x04u},\r
+ {0x66u, 0x20u},\r
+ {0x67u, 0xA0u},\r
+ {0x6Eu, 0x40u},\r
+ {0x6Fu, 0x14u},\r
+ {0x78u, 0x02u},\r
+ {0x7Bu, 0x40u},\r
+ {0x7Eu, 0x20u},\r
+ {0x7Fu, 0x10u},\r
+ {0x82u, 0x40u},\r
+ {0x88u, 0x40u},\r
+ {0x8Eu, 0x19u},\r
+ {0x91u, 0x20u},\r
+ {0x92u, 0x0Eu},\r
+ {0x93u, 0x50u},\r
+ {0x95u, 0x82u},\r
+ {0x97u, 0x80u},\r
+ {0x9Au, 0x90u},\r
+ {0x9Bu, 0x08u},\r
+ {0x9Cu, 0x08u},\r
+ {0x9Du, 0x39u},\r
+ {0x9Eu, 0x41u},\r
+ {0x9Fu, 0x14u},\r
+ {0xA0u, 0x04u},\r
+ {0xA3u, 0x88u},\r
{0xA4u, 0x40u},\r
- {0xA5u, 0x04u},\r
- {0xA6u, 0x02u},\r
- {0xA7u, 0x40u},\r
- {0xA9u, 0x29u},\r
- {0xABu, 0x20u},\r
- {0xACu, 0x84u},\r
- {0xADu, 0x40u},\r
- {0xB0u, 0x01u},\r
- {0xB2u, 0x01u},\r
- {0xB3u, 0x28u},\r
- {0xB5u, 0x10u},\r
- {0xB7u, 0x42u},\r
- {0xC0u, 0x0Fu},\r
- {0xC2u, 0x4Fu},\r
- {0xC4u, 0xFBu},\r
- {0xCAu, 0x81u},\r
- {0xCCu, 0x5Eu},\r
- {0xCEu, 0x5Eu},\r
- {0xD0u, 0x07u},\r
- {0xD2u, 0x0Cu},\r
- {0xD6u, 0x0Fu},\r
- {0xD8u, 0x08u},\r
- {0xE0u, 0x80u},\r
- {0xE2u, 0x40u},\r
- {0xEAu, 0x03u},\r
- {0xEEu, 0x54u},\r
- {0x00u, 0x01u},\r
- {0x03u, 0x9Fu},\r
- {0x04u, 0x01u},\r
- {0x07u, 0xFFu},\r
- {0x08u, 0x04u},\r
- {0x09u, 0x7Fu},\r
- {0x0Bu, 0x80u},\r
- {0x0Cu, 0x01u},\r
- {0x0Du, 0x90u},\r
- {0x0Fu, 0x40u},\r
- {0x11u, 0x1Fu},\r
- {0x12u, 0x40u},\r
- {0x13u, 0x20u},\r
- {0x14u, 0xA2u},\r
- {0x15u, 0x80u},\r
- {0x16u, 0x08u},\r
- {0x18u, 0x08u},\r
- {0x1Au, 0x61u},\r
- {0x1Bu, 0x60u},\r
- {0x1Cu, 0x01u},\r
- {0x1Du, 0xC0u},\r
- {0x1Fu, 0x02u},\r
- {0x20u, 0x07u},\r
- {0x21u, 0xC0u},\r
- {0x22u, 0xD8u},\r
- {0x23u, 0x01u},\r
- {0x25u, 0xC0u},\r
- {0x27u, 0x04u},\r
- {0x28u, 0x01u},\r
- {0x29u, 0xC0u},\r
- {0x2Bu, 0x08u},\r
- {0x2Cu, 0x10u},\r
- {0x30u, 0xE0u},\r
- {0x36u, 0x3Fu},\r
- {0x37u, 0xFFu},\r
- {0x38u, 0x80u},\r
+ {0xA5u, 0x80u},\r
+ {0xA6u, 0x0Au},\r
+ {0xAAu, 0x04u},\r
+ {0xABu, 0x14u},\r
+ {0xACu, 0x15u},\r
+ {0xB1u, 0x40u},\r
+ {0xB3u, 0x08u},\r
+ {0xB5u, 0x40u},\r
+ {0xB6u, 0x04u},\r
+ {0xB7u, 0x40u},\r
+ {0xC0u, 0x07u},\r
+ {0xC2u, 0x09u},\r
+ {0xC4u, 0x0Cu},\r
+ {0xCAu, 0xFFu},\r
+ {0xCCu, 0xFEu},\r
+ {0xCEu, 0xBFu},\r
+ {0xD0u, 0xB0u},\r
+ {0xD2u, 0x30u},\r
+ {0xD8u, 0xF0u},\r
+ {0xE2u, 0x41u},\r
+ {0xEAu, 0x0Au},\r
+ {0xEEu, 0x06u},\r
+ {0x00u, 0x24u},\r
+ {0x01u, 0x01u},\r
+ {0x04u, 0x6Cu},\r
+ {0x05u, 0x10u},\r
+ {0x0Au, 0x2Fu},\r
+ {0x0Bu, 0x40u},\r
+ {0x0Cu, 0x2Cu},\r
+ {0x0Eu, 0x40u},\r
+ {0x10u, 0x31u},\r
+ {0x11u, 0x07u},\r
+ {0x12u, 0x02u},\r
+ {0x13u, 0xD8u},\r
+ {0x14u, 0x40u},\r
+ {0x15u, 0x08u},\r
+ {0x16u, 0x2Cu},\r
+ {0x17u, 0x61u},\r
+ {0x18u, 0x11u},\r
+ {0x19u, 0xA2u},\r
+ {0x1Au, 0x0Eu},\r
+ {0x1Bu, 0x08u},\r
+ {0x1Cu, 0x08u},\r
+ {0x1Du, 0x01u},\r
+ {0x1Eu, 0x10u},\r
+ {0x20u, 0x6Cu},\r
+ {0x21u, 0x01u},\r
+ {0x24u, 0x80u},\r
+ {0x25u, 0x01u},\r
+ {0x28u, 0x64u},\r
+ {0x29u, 0x04u},\r
+ {0x2Au, 0x08u},\r
+ {0x2Cu, 0x80u},\r
+ {0x2Du, 0x01u},\r
+ {0x30u, 0x0Fu},\r
+ {0x31u, 0x3Fu},\r
+ {0x32u, 0x80u},\r
+ {0x34u, 0x31u},\r
+ {0x35u, 0xE0u},\r
+ {0x36u, 0x40u},\r
+ {0x37u, 0x08u},\r
+ {0x38u, 0x08u},\r
+ {0x39u, 0x02u},\r
+ {0x3Au, 0x30u},\r
{0x3Eu, 0x40u},\r
- {0x3Fu, 0x40u},\r
+ {0x3Fu, 0x41u},\r
+ {0x56u, 0x02u},\r
+ {0x57u, 0x20u},\r
{0x58u, 0x04u},\r
{0x59u, 0x04u},\r
+ {0x5Bu, 0x04u},\r
{0x5Fu, 0x01u},\r
- {0x80u, 0x56u},\r
- {0x81u, 0x64u},\r
- {0x84u, 0x52u},\r
- {0x85u, 0x83u},\r
- {0x86u, 0x04u},\r
- {0x87u, 0x70u},\r
- {0x88u, 0x50u},\r
- {0x8Au, 0x06u},\r
- {0x8Bu, 0xF5u},\r
- {0x8Cu, 0x17u},\r
- {0x8Du, 0x64u},\r
- {0x8Eu, 0x28u},\r
- {0x91u, 0x07u},\r
- {0x93u, 0x90u},\r
- {0x94u, 0x31u},\r
- {0x95u, 0x40u},\r
- {0x96u, 0x0Eu},\r
- {0x97u, 0x02u},\r
- {0x98u, 0x29u},\r
- {0x99u, 0x24u},\r
- {0x9Au, 0x16u},\r
- {0x9Bu, 0x40u},\r
- {0x9Du, 0x08u},\r
- {0xA0u, 0x56u},\r
- {0xA1u, 0x64u},\r
- {0xA4u, 0x22u},\r
- {0xA5u, 0x24u},\r
- {0xA6u, 0x10u},\r
- {0xA8u, 0x04u},\r
- {0xABu, 0x64u},\r
- {0xACu, 0x06u},\r
- {0xADu, 0x08u},\r
- {0xAEu, 0x50u},\r
+ {0x81u, 0xC0u},\r
+ {0x82u, 0x49u},\r
+ {0x83u, 0x01u},\r
+ {0x86u, 0x06u},\r
+ {0x87u, 0x9Fu},\r
+ {0x89u, 0xC0u},\r
+ {0x8Bu, 0x08u},\r
+ {0x8Cu, 0x09u},\r
+ {0x8Du, 0xC0u},\r
+ {0x8Eu, 0x24u},\r
+ {0x8Fu, 0x02u},\r
+ {0x91u, 0x90u},\r
+ {0x93u, 0x40u},\r
+ {0x97u, 0xFFu},\r
+ {0x98u, 0x09u},\r
+ {0x99u, 0xC0u},\r
+ {0x9Au, 0x52u},\r
+ {0x9Bu, 0x04u},\r
+ {0x9Du, 0x80u},\r
+ {0x9Eu, 0x30u},\r
+ {0xA1u, 0x1Fu},\r
+ {0xA3u, 0x20u},\r
+ {0xA7u, 0x60u},\r
+ {0xA9u, 0x7Fu},\r
+ {0xAAu, 0x08u},\r
+ {0xABu, 0x80u},\r
+ {0xAEu, 0x01u},\r
{0xB0u, 0x40u},\r
- {0xB1u, 0x71u},\r
- {0xB2u, 0x30u},\r
- {0xB3u, 0x07u},\r
- {0xB4u, 0x0Fu},\r
- {0xB5u, 0x08u},\r
- {0xB7u, 0x80u},\r
- {0xB8u, 0x20u},\r
- {0xB9u, 0x20u},\r
- {0xBAu, 0x08u},\r
- {0xBBu, 0x0Cu},\r
+ {0xB3u, 0xFFu},\r
+ {0xB4u, 0x07u},\r
+ {0xB6u, 0x38u},\r
{0xBEu, 0x01u},\r
- {0xBFu, 0x40u},\r
- {0xD4u, 0x40u},\r
- {0xD6u, 0x04u},\r
+ {0xBFu, 0x04u},\r
{0xD8u, 0x04u},\r
{0xD9u, 0x04u},\r
- {0xDBu, 0x04u},\r
+ {0xDCu, 0x01u},\r
{0xDFu, 0x01u},\r
- {0x01u, 0x01u},\r
- {0x02u, 0x02u},\r
- {0x03u, 0x18u},\r
- {0x05u, 0x08u},\r
- {0x07u, 0x49u},\r
- {0x0Au, 0x04u},\r
- {0x0Bu, 0x10u},\r
- {0x0Cu, 0x80u},\r
- {0x0Eu, 0x84u},\r
- {0x0Fu, 0x10u},\r
- {0x10u, 0x98u},\r
- {0x11u, 0x40u},\r
- {0x15u, 0x82u},\r
- {0x17u, 0x10u},\r
- {0x18u, 0x08u},\r
- {0x19u, 0x09u},\r
- {0x1Au, 0x04u},\r
- {0x1Bu, 0x02u},\r
- {0x1Du, 0x40u},\r
- {0x1Eu, 0x80u},\r
- {0x21u, 0x01u},\r
- {0x22u, 0x62u},\r
- {0x23u, 0x18u},\r
- {0x25u, 0x80u},\r
- {0x28u, 0x10u},\r
- {0x29u, 0x48u},\r
- {0x2Bu, 0x88u},\r
- {0x2Cu, 0xA0u},\r
- {0x2Fu, 0x08u},\r
- {0x30u, 0x28u},\r
- {0x31u, 0x80u},\r
- {0x32u, 0x02u},\r
- {0x35u, 0x08u},\r
- {0x36u, 0x22u},\r
- {0x37u, 0x40u},\r
- {0x38u, 0x08u},\r
- {0x39u, 0x40u},\r
- {0x3Au, 0x02u},\r
- {0x3Bu, 0x10u},\r
- {0x3Du, 0x40u},\r
- {0x3Eu, 0x04u},\r
- {0x3Fu, 0x11u},\r
- {0x48u, 0x08u},\r
- {0x49u, 0x20u},\r
- {0x60u, 0x02u},\r
- {0x61u, 0x20u},\r
- {0x63u, 0xA0u},\r
- {0x86u, 0x40u},\r
- {0x88u, 0x01u},\r
- {0x91u, 0x84u},\r
- {0x92u, 0x60u},\r
- {0x93u, 0x05u},\r
- {0x95u, 0x41u},\r
- {0x96u, 0x0Cu},\r
- {0x97u, 0x10u},\r
- {0x98u, 0x42u},\r
- {0x99u, 0x06u},\r
- {0x9Au, 0xC4u},\r
- {0x9Bu, 0xA0u},\r
- {0x9Cu, 0x01u},\r
- {0x9Fu, 0x10u},\r
- {0xA0u, 0x08u},\r
- {0xA1u, 0x20u},\r
- {0xA2u, 0x98u},\r
- {0xA3u, 0x15u},\r
- {0xA4u, 0x80u},\r
- {0xA5u, 0x40u},\r
+ {0x00u, 0x84u},\r
+ {0x03u, 0x80u},\r
+ {0x04u, 0x02u},\r
+ {0x05u, 0x10u},\r
+ {0x06u, 0x20u},\r
+ {0x07u, 0x01u},\r
+ {0x08u, 0x80u},\r
+ {0x0Au, 0x05u},\r
+ {0x0Du, 0x02u},\r
+ {0x0Eu, 0x18u},\r
+ {0x0Fu, 0x01u},\r
+ {0x13u, 0x50u},\r
+ {0x15u, 0x09u},\r
+ {0x17u, 0x50u},\r
+ {0x18u, 0x04u},\r
+ {0x1Au, 0x01u},\r
+ {0x1Bu, 0x01u},\r
+ {0x1Du, 0xB7u},\r
+ {0x1Eu, 0x02u},\r
+ {0x1Fu, 0x08u},\r
+ {0x21u, 0x04u},\r
+ {0x25u, 0x10u},\r
+ {0x26u, 0x50u},\r
+ {0x27u, 0x40u},\r
+ {0x29u, 0x15u},\r
+ {0x2Du, 0x40u},\r
+ {0x2Eu, 0x02u},\r
+ {0x2Fu, 0x28u},\r
+ {0x32u, 0x88u},\r
+ {0x33u, 0x11u},\r
+ {0x35u, 0x11u},\r
+ {0x36u, 0x88u},\r
+ {0x38u, 0x80u},\r
+ {0x39u, 0x10u},\r
+ {0x3Au, 0x06u},\r
+ {0x3Du, 0x29u},\r
+ {0x45u, 0xC0u},\r
+ {0x66u, 0x80u},\r
+ {0x6Cu, 0x40u},\r
+ {0x6Du, 0x51u},\r
+ {0x6Eu, 0x10u},\r
+ {0x6Fu, 0x31u},\r
+ {0x75u, 0x80u},\r
+ {0x76u, 0x02u},\r
+ {0x81u, 0x80u},\r
+ {0x82u, 0x20u},\r
+ {0x8Bu, 0x01u},\r
+ {0x90u, 0x02u},\r
+ {0x92u, 0x04u},\r
+ {0x93u, 0x55u},\r
+ {0x94u, 0x04u},\r
+ {0x95u, 0xC1u},\r
+ {0x96u, 0x10u},\r
+ {0x98u, 0x10u},\r
+ {0x99u, 0x20u},\r
+ {0x9Au, 0x85u},\r
+ {0x9Bu, 0x08u},\r
+ {0x9Cu, 0x88u},\r
+ {0x9Du, 0x19u},\r
+ {0x9Eu, 0x02u},\r
+ {0xA0u, 0x44u},\r
+ {0xA1u, 0x04u},\r
+ {0xA2u, 0x8Cu},\r
+ {0xA3u, 0x80u},\r
+ {0xA5u, 0x62u},\r
{0xA6u, 0x02u},\r
- {0xA7u, 0x4Au},\r
- {0xAAu, 0x10u},\r
- {0xACu, 0x50u},\r
- {0xAEu, 0x81u},\r
- {0xB4u, 0x40u},\r
- {0xC0u, 0xFFu},\r
- {0xC2u, 0xF6u},\r
- {0xC4u, 0xDFu},\r
- {0xCAu, 0xEFu},\r
+ {0xA7u, 0x20u},\r
+ {0xA8u, 0x04u},\r
+ {0xA9u, 0x93u},\r
+ {0xACu, 0x10u},\r
+ {0xB0u, 0x01u},\r
+ {0xC0u, 0xFDu},\r
+ {0xC2u, 0xF3u},\r
+ {0xC4u, 0xF3u},\r
+ {0xCAu, 0xF7u},\r
{0xCCu, 0xFFu},\r
- {0xCEu, 0xFFu},\r
- {0xD8u, 0x0Fu},\r
- {0xE2u, 0x09u},\r
- {0xE6u, 0x08u},\r
- {0xEAu, 0x02u},\r
- {0xECu, 0x04u},\r
- {0x38u, 0x80u},\r
- {0x3Eu, 0x40u},\r
- {0x58u, 0x04u},\r
- {0x5Fu, 0x01u},\r
- {0x1Fu, 0x80u},\r
- {0x8Au, 0x04u},\r
- {0x92u, 0x0Cu},\r
- {0x97u, 0x01u},\r
- {0x9Bu, 0x80u},\r
- {0x9Cu, 0x02u},\r
- {0x9Du, 0x20u},\r
- {0xA3u, 0x08u},\r
- {0xAAu, 0x04u},\r
- {0xADu, 0x40u},\r
- {0xB5u, 0x08u},\r
- {0xE2u, 0x09u},\r
- {0xE6u, 0x28u},\r
- {0xE8u, 0x40u},\r
- {0x92u, 0x0Cu},\r
- {0x97u, 0x01u},\r
- {0x9Bu, 0x80u},\r
- {0x9Cu, 0x02u},\r
- {0x9Du, 0x28u},\r
- {0xA1u, 0x40u},\r
- {0xA3u, 0x08u},\r
- {0xA6u, 0x04u},\r
- {0xA8u, 0x40u},\r
+ {0xCEu, 0xEFu},\r
+ {0xD8u, 0x10u},\r
+ {0xE2u, 0x89u},\r
+ {0xE6u, 0x20u},\r
+ {0xEAu, 0x08u},\r
+ {0xEEu, 0x01u},\r
+ {0x90u, 0x08u},\r
+ {0x91u, 0x40u},\r
+ {0x9Bu, 0x01u},\r
+ {0x9Eu, 0x20u},\r
+ {0xA2u, 0x10u},\r
{0xA9u, 0x04u},\r
- {0xAEu, 0x04u},\r
- {0xB0u, 0x20u},\r
- {0xB1u, 0x01u},\r
- {0xB6u, 0x08u},\r
- {0xB7u, 0x08u},\r
- {0xE0u, 0x20u},\r
- {0xEAu, 0x94u},\r
- {0xEEu, 0xA4u},\r
- {0x01u, 0x0Fu},\r
- {0x03u, 0xF0u},\r
- {0x04u, 0x50u},\r
- {0x05u, 0x30u},\r
- {0x06u, 0xA0u},\r
- {0x07u, 0xC0u},\r
- {0x08u, 0x06u},\r
- {0x09u, 0x50u},\r
- {0x0Au, 0x09u},\r
- {0x0Bu, 0xA0u},\r
- {0x0Cu, 0x03u},\r
- {0x0Du, 0x60u},\r
- {0x0Eu, 0x0Cu},\r
- {0x0Fu, 0x90u},\r
- {0x11u, 0xFFu},\r
- {0x12u, 0xFFu},\r
- {0x14u, 0xFFu},\r
- {0x15u, 0x05u},\r
- {0x17u, 0x0Au},\r
- {0x18u, 0x05u},\r
- {0x19u, 0x06u},\r
- {0x1Au, 0x0Au},\r
- {0x1Bu, 0x09u},\r
- {0x1Cu, 0x0Fu},\r
- {0x1Eu, 0xF0u},\r
- {0x1Fu, 0xFFu},\r
- {0x21u, 0x03u},\r
- {0x22u, 0xFFu},\r
- {0x23u, 0x0Cu},\r
- {0x24u, 0x30u},\r
- {0x26u, 0xC0u},\r
- {0x27u, 0xFFu},\r
- {0x2Cu, 0x60u},\r
- {0x2Eu, 0x90u},\r
- {0x35u, 0xFFu},\r
- {0x36u, 0xFFu},\r
- {0x3Eu, 0x40u},\r
- {0x3Fu, 0x10u},\r
+ {0xAEu, 0x40u},\r
+ {0xE2u, 0x09u},\r
+ {0xE6u, 0x20u},\r
+ {0xEEu, 0x20u},\r
+ {0xB9u, 0x08u},\r
+ {0xBFu, 0x04u},\r
+ {0xD9u, 0x04u},\r
+ {0xDFu, 0x01u},\r
+ {0x27u, 0x20u},\r
+ {0x83u, 0x20u},\r
+ {0x8Bu, 0x04u},\r
+ {0x8Fu, 0x10u},\r
+ {0x90u, 0x08u},\r
+ {0x91u, 0x40u},\r
+ {0x97u, 0x04u},\r
+ {0x99u, 0x04u},\r
+ {0x9Au, 0x40u},\r
+ {0x9Bu, 0x11u},\r
+ {0x9Eu, 0x20u},\r
+ {0xA2u, 0x10u},\r
+ {0xA9u, 0x54u},\r
+ {0xADu, 0x05u},\r
+ {0xAFu, 0x01u},\r
+ {0xB1u, 0x02u},\r
+ {0xB2u, 0x18u},\r
+ {0xB4u, 0x40u},\r
+ {0xB5u, 0x41u},\r
+ {0xE2u, 0x10u},\r
+ {0xE4u, 0x20u},\r
+ {0xE6u, 0x40u},\r
+ {0xE8u, 0xC4u},\r
+ {0xEAu, 0x01u},\r
+ {0xECu, 0x80u},\r
+ {0xEEu, 0x50u},\r
+ {0x02u, 0x04u},\r
+ {0x06u, 0x20u},\r
+ {0x08u, 0x21u},\r
+ {0x0Au, 0x42u},\r
+ {0x0Eu, 0x04u},\r
+ {0x11u, 0x20u},\r
+ {0x13u, 0x90u},\r
+ {0x15u, 0x04u},\r
+ {0x16u, 0x18u},\r
+ {0x17u, 0x08u},\r
+ {0x18u, 0x04u},\r
+ {0x1Au, 0x10u},\r
+ {0x1Bu, 0x01u},\r
+ {0x1Eu, 0x02u},\r
+ {0x21u, 0x10u},\r
+ {0x22u, 0x40u},\r
+ {0x23u, 0x20u},\r
+ {0x24u, 0x04u},\r
+ {0x25u, 0x08u},\r
+ {0x26u, 0x08u},\r
+ {0x27u, 0x44u},\r
+ {0x29u, 0x4Du},\r
+ {0x2Au, 0x01u},\r
+ {0x2Bu, 0xB2u},\r
+ {0x2Cu, 0x80u},\r
+ {0x2Fu, 0x02u},\r
+ {0x30u, 0x03u},\r
+ {0x31u, 0xC0u},\r
+ {0x32u, 0x1Cu},\r
+ {0x33u, 0x03u},\r
+ {0x34u, 0x80u},\r
+ {0x36u, 0x60u},\r
+ {0x37u, 0x3Cu},\r
+ {0x3Eu, 0x51u},\r
+ {0x3Fu, 0x45u},\r
{0x58u, 0x04u},\r
{0x59u, 0x04u},\r
{0x5Bu, 0x04u},\r
+ {0x5Cu, 0x01u},\r
{0x5Fu, 0x01u},\r
- {0x84u, 0x10u},\r
- {0x86u, 0x09u},\r
- {0x87u, 0x10u},\r
{0x8Bu, 0x08u},\r
- {0x8Du, 0x0Au},\r
- {0x8Fu, 0x14u},\r
- {0x90u, 0x08u},\r
- {0x92u, 0x10u},\r
- {0x93u, 0x04u},\r
- {0x94u, 0x04u},\r
- {0x95u, 0x01u},\r
- {0x9Cu, 0x19u},\r
- {0x9Eu, 0x62u},\r
- {0xA0u, 0x40u},\r
- {0xA2u, 0x22u},\r
- {0xABu, 0x02u},\r
- {0xACu, 0x20u},\r
- {0xAEu, 0x40u},\r
- {0xB0u, 0x04u},\r
- {0xB1u, 0x06u},\r
- {0xB2u, 0x03u},\r
- {0xB3u, 0x18u},\r
- {0xB4u, 0x78u},\r
- {0xB5u, 0x01u},\r
- {0xBEu, 0x15u},\r
- {0xBFu, 0x15u},\r
+ {0x8Cu, 0x01u},\r
+ {0x8Du, 0x10u},\r
+ {0x91u, 0x04u},\r
+ {0x93u, 0x08u},\r
+ {0x97u, 0x04u},\r
+ {0x98u, 0x02u},\r
+ {0xA5u, 0x01u},\r
+ {0xA9u, 0x02u},\r
+ {0xACu, 0x04u},\r
+ {0xB0u, 0x02u},\r
+ {0xB1u, 0x02u},\r
+ {0xB3u, 0x10u},\r
+ {0xB4u, 0x01u},\r
+ {0xB5u, 0x0Cu},\r
+ {0xB6u, 0x04u},\r
+ {0xB7u, 0x01u},\r
+ {0xBEu, 0x51u},\r
+ {0xBFu, 0x55u},\r
{0xD8u, 0x04u},\r
{0xD9u, 0x04u},\r
{0xDFu, 0x01u},\r
- {0x01u, 0x08u},\r
- {0x04u, 0x08u},\r
- {0x05u, 0x20u},\r
- {0x06u, 0x02u},\r
- {0x09u, 0x06u},\r
- {0x0Bu, 0x01u},\r
- {0x0Cu, 0x01u},\r
- {0x0Du, 0x50u},\r
- {0x0Eu, 0x08u},\r
- {0x0Fu, 0x21u},\r
- {0x11u, 0x02u},\r
- {0x12u, 0x01u},\r
- {0x14u, 0x80u},\r
- {0x15u, 0x44u},\r
- {0x18u, 0xA0u},\r
- {0x1Au, 0x08u},\r
- {0x1Bu, 0x30u},\r
- {0x1Fu, 0x80u},\r
- {0x22u, 0x2Au},\r
- {0x27u, 0x08u},\r
- {0x29u, 0x20u},\r
- {0x2Eu, 0x02u},\r
- {0x2Fu, 0x20u},\r
- {0x31u, 0x08u},\r
- {0x33u, 0x02u},\r
- {0x34u, 0x83u},\r
- {0x35u, 0x20u},\r
- {0x36u, 0x04u},\r
- {0x38u, 0x08u},\r
- {0x39u, 0xA0u},\r
- {0x3Du, 0x91u},\r
- {0x3Eu, 0x04u},\r
- {0x3Fu, 0x01u},\r
+ {0x03u, 0x02u},\r
+ {0x04u, 0x40u},\r
+ {0x05u, 0x02u},\r
+ {0x06u, 0x24u},\r
+ {0x09u, 0x10u},\r
+ {0x0Cu, 0x80u},\r
+ {0x0Eu, 0x20u},\r
+ {0x0Fu, 0x04u},\r
+ {0x10u, 0x01u},\r
+ {0x14u, 0x08u},\r
+ {0x16u, 0x40u},\r
+ {0x17u, 0x48u},\r
+ {0x19u, 0x61u},\r
+ {0x1Du, 0x90u},\r
+ {0x1Eu, 0xA0u},\r
+ {0x21u, 0x45u},\r
+ {0x22u, 0x10u},\r
+ {0x24u, 0x80u},\r
+ {0x25u, 0x04u},\r
+ {0x27u, 0x01u},\r
+ {0x2Au, 0x18u},\r
+ {0x2Cu, 0xA8u},\r
+ {0x2Du, 0x40u},\r
+ {0x31u, 0x02u},\r
+ {0x32u, 0x08u},\r
+ {0x34u, 0x08u},\r
+ {0x36u, 0x11u},\r
+ {0x39u, 0x10u},\r
+ {0x3Au, 0x80u},\r
{0x6Cu, 0x04u},\r
- {0x6Du, 0xD6u},\r
- {0x6Eu, 0x04u},\r
- {0x6Fu, 0x0Au},\r
- {0x74u, 0x20u},\r
- {0x75u, 0x80u},\r
- {0x76u, 0x11u},\r
- {0x77u, 0x80u},\r
- {0x82u, 0x20u},\r
- {0x86u, 0x02u},\r
- {0x88u, 0x80u},\r
- {0x89u, 0x02u},\r
- {0x8Au, 0x02u},\r
- {0x8Cu, 0x10u},\r
- {0x8Fu, 0x80u},\r
- {0x9Cu, 0x02u},\r
- {0x9Du, 0xA0u},\r
- {0x9Eu, 0x10u},\r
- {0x9Fu, 0x08u},\r
- {0xA1u, 0x08u},\r
- {0xA7u, 0x10u},\r
- {0xAEu, 0x10u},\r
- {0xB1u, 0x80u},\r
- {0xB7u, 0x10u},\r
- {0xC0u, 0xE4u},\r
- {0xC2u, 0xFDu},\r
- {0xC4u, 0xB9u},\r
- {0xCAu, 0xC4u},\r
- {0xCCu, 0xF3u},\r
- {0xCEu, 0xFEu},\r
- {0xE0u, 0xA2u},\r
- {0xE2u, 0x50u},\r
+ {0x6Du, 0x50u},\r
+ {0x6Eu, 0x02u},\r
+ {0x6Fu, 0x10u},\r
+ {0x74u, 0x90u},\r
+ {0x75u, 0x04u},\r
+ {0x76u, 0x40u},\r
+ {0x81u, 0x10u},\r
+ {0x83u, 0x40u},\r
+ {0x84u, 0x01u},\r
+ {0x85u, 0x10u},\r
+ {0x87u, 0x02u},\r
+ {0x89u, 0x60u},\r
+ {0x8Au, 0x80u},\r
+ {0x8Cu, 0x08u},\r
+ {0x8Du, 0x02u},\r
+ {0x8Eu, 0x1Cu},\r
+ {0x8Fu, 0x08u},\r
+ {0x94u, 0x80u},\r
+ {0x98u, 0x08u},\r
+ {0xA0u, 0x20u},\r
+ {0xA4u, 0x10u},\r
+ {0xA5u, 0x80u},\r
+ {0xA6u, 0x40u},\r
+ {0xA8u, 0x08u},\r
+ {0xA9u, 0x80u},\r
+ {0xC0u, 0xF1u},\r
+ {0xC2u, 0xE2u},\r
+ {0xC4u, 0xF1u},\r
+ {0xCAu, 0xF6u},\r
+ {0xCCu, 0xE3u},\r
+ {0xCEu, 0x0Cu},\r
+ {0xE2u, 0xAAu},\r
+ {0xE4u, 0x50u},\r
+ {0xE6u, 0x01u},\r
+ {0xE8u, 0x80u},\r
+ {0xEAu, 0x04u},\r
+ {0x80u, 0x40u},\r
+ {0x84u, 0x10u},\r
+ {0x86u, 0x40u},\r
+ {0x88u, 0x20u},\r
+ {0xE0u, 0x01u},\r
{0xE4u, 0x20u},\r
- {0xE6u, 0x98u},\r
- {0xEAu, 0x14u},\r
- {0xEEu, 0x82u},\r
- {0x85u, 0x20u},\r
- {0x87u, 0x08u},\r
- {0x8Cu, 0x02u},\r
- {0x8Du, 0x08u},\r
- {0xE2u, 0x10u},\r
- {0xAFu, 0x10u},\r
- {0xB2u, 0x20u},\r
- {0xB4u, 0x40u},\r
- {0xEAu, 0x40u},\r
- {0xECu, 0x02u},\r
- {0x00u, 0x03u},\r
- {0x02u, 0x0Cu},\r
- {0x04u, 0x60u},\r
- {0x05u, 0x01u},\r
- {0x06u, 0x90u},\r
- {0x07u, 0x02u},\r
- {0x0Bu, 0x10u},\r
- {0x0Cu, 0x0Fu},\r
- {0x0Eu, 0xF0u},\r
- {0x11u, 0x08u},\r
- {0x13u, 0x10u},\r
- {0x14u, 0x05u},\r
- {0x16u, 0x0Au},\r
- {0x17u, 0x01u},\r
- {0x18u, 0x06u},\r
- {0x1Au, 0x09u},\r
- {0x1Bu, 0x06u},\r
- {0x1Fu, 0x08u},\r
- {0x20u, 0x50u},\r
- {0x21u, 0x01u},\r
- {0x22u, 0xA0u},\r
- {0x23u, 0x04u},\r
- {0x24u, 0x30u},\r
- {0x26u, 0xC0u},\r
- {0x2Fu, 0x01u},\r
- {0x34u, 0xFFu},\r
- {0x35u, 0x07u},\r
- {0x37u, 0x18u},\r
- {0x3Eu, 0x10u},\r
+ {0xABu, 0x21u},\r
+ {0xAFu, 0x80u},\r
+ {0xB0u, 0x08u},\r
+ {0xB1u, 0x40u},\r
+ {0xB2u, 0x10u},\r
+ {0xB7u, 0x40u},\r
+ {0x00u, 0x21u},\r
+ {0x01u, 0x02u},\r
+ {0x02u, 0x02u},\r
+ {0x03u, 0x0Du},\r
+ {0x04u, 0xE0u},\r
+ {0x05u, 0x60u},\r
+ {0x08u, 0x88u},\r
+ {0x09u, 0x0Du},\r
+ {0x0Au, 0x03u},\r
+ {0x0Eu, 0x01u},\r
+ {0x11u, 0x91u},\r
+ {0x13u, 0x22u},\r
+ {0x15u, 0x92u},\r
+ {0x16u, 0xECu},\r
+ {0x17u, 0x44u},\r
+ {0x18u, 0x04u},\r
+ {0x19u, 0xA2u},\r
+ {0x1Au, 0x43u},\r
+ {0x1Bu, 0x18u},\r
+ {0x1Du, 0x0Du},\r
+ {0x21u, 0x0Du},\r
+ {0x25u, 0x0Du},\r
+ {0x2Au, 0x12u},\r
+ {0x2Du, 0x0Du},\r
+ {0x30u, 0x10u},\r
+ {0x31u, 0x0Fu},\r
+ {0x32u, 0x0Fu},\r
+ {0x35u, 0x70u},\r
+ {0x36u, 0xE0u},\r
+ {0x37u, 0x80u},\r
+ {0x39u, 0x20u},\r
+ {0x3Bu, 0x02u},\r
+ {0x3Eu, 0x40u},\r
{0x3Fu, 0x40u},\r
- {0x56u, 0x02u},\r
- {0x57u, 0x28u},\r
+ {0x54u, 0x09u},\r
+ {0x56u, 0x04u},\r
{0x58u, 0x04u},\r
{0x59u, 0x04u},\r
{0x5Bu, 0x04u},\r
- {0x5Cu, 0x10u},\r
{0x5Fu, 0x01u},\r
- {0x86u, 0xECu},\r
- {0x87u, 0xFFu},\r
- {0x8Bu, 0xFFu},\r
- {0x8Du, 0x0Fu},\r
- {0x8Eu, 0x01u},\r
- {0x8Fu, 0xF0u},\r
- {0x91u, 0x30u},\r
- {0x93u, 0xC0u},\r
- {0x98u, 0x04u},\r
+ {0x80u, 0x50u},\r
+ {0x81u, 0x30u},\r
+ {0x82u, 0xA0u},\r
+ {0x83u, 0xC0u},\r
+ {0x84u, 0x03u},\r
+ {0x85u, 0x06u},\r
+ {0x86u, 0x0Cu},\r
+ {0x87u, 0x09u},\r
+ {0x89u, 0xFFu},\r
+ {0x8Au, 0xFFu},\r
+ {0x8Cu, 0x30u},\r
+ {0x8Eu, 0xC0u},\r
+ {0x90u, 0x0Fu},\r
+ {0x92u, 0xF0u},\r
+ {0x94u, 0x09u},\r
+ {0x95u, 0x03u},\r
+ {0x96u, 0x06u},\r
+ {0x97u, 0x0Cu},\r
{0x99u, 0x05u},\r
- {0x9Au, 0x43u},\r
+ {0x9Au, 0xFFu},\r
{0x9Bu, 0x0Au},\r
- {0x9Du, 0x03u},\r
- {0x9Eu, 0x12u},\r
- {0x9Fu, 0x0Cu},\r
- {0xA0u, 0xE0u},\r
+ {0x9Du, 0x0Fu},\r
+ {0x9Eu, 0xFFu},\r
+ {0x9Fu, 0xF0u},\r
+ {0xA0u, 0x90u},\r
{0xA1u, 0x50u},\r
+ {0xA2u, 0x60u},\r
{0xA3u, 0xA0u},\r
+ {0xA4u, 0x05u},\r
+ {0xA6u, 0x0Au},\r
{0xA7u, 0xFFu},\r
- {0xA8u, 0x88u},\r
- {0xA9u, 0x09u},\r
- {0xAAu, 0x03u},\r
- {0xABu, 0x06u},\r
- {0xACu, 0x21u},\r
- {0xADu, 0x90u},\r
- {0xAEu, 0x02u},\r
- {0xAFu, 0x60u},\r
- {0xB0u, 0xE0u},\r
- {0xB3u, 0xFFu},\r
- {0xB4u, 0x0Fu},\r
- {0xB6u, 0x10u},\r
- {0xBEu, 0x01u},\r
- {0xBFu, 0x04u},\r
- {0xD4u, 0x09u},\r
- {0xD6u, 0x04u},\r
+ {0xABu, 0xFFu},\r
+ {0xADu, 0x60u},\r
+ {0xAFu, 0x90u},\r
+ {0xB1u, 0xFFu},\r
+ {0xB2u, 0xFFu},\r
+ {0xBEu, 0x04u},\r
+ {0xBFu, 0x01u},\r
{0xD8u, 0x04u},\r
{0xD9u, 0x04u},\r
{0xDBu, 0x04u},\r
{0xDFu, 0x01u},\r
- {0x00u, 0x04u},\r
- {0x01u, 0x80u},\r
- {0x07u, 0xA2u},\r
- {0x0Au, 0x04u},\r
- {0x0Bu, 0x01u},\r
- {0x0Eu, 0x20u},\r
- {0x0Fu, 0x08u},\r
- {0x10u, 0x40u},\r
- {0x12u, 0x02u},\r
- {0x13u, 0x10u},\r
- {0x16u, 0x60u},\r
- {0x18u, 0x44u},\r
- {0x19u, 0x80u},\r
- {0x1Fu, 0x10u},\r
- {0x22u, 0x04u},\r
- {0x25u, 0x40u},\r
- {0x26u, 0x20u},\r
- {0x28u, 0xA0u},\r
- {0x29u, 0x10u},\r
- {0x2Au, 0x80u},\r
- {0x2Du, 0x02u},\r
- {0x2Eu, 0x40u},\r
- {0x30u, 0x01u},\r
- {0x32u, 0x90u},\r
- {0x35u, 0x10u},\r
- {0x36u, 0x28u},\r
- {0x37u, 0x82u},\r
- {0x39u, 0x84u},\r
- {0x3Bu, 0x20u},\r
- {0x3Du, 0x20u},\r
- {0x3Eu, 0x20u},\r
- {0x3Fu, 0x04u},\r
- {0x59u, 0x25u},\r
- {0x5Au, 0x80u},\r
- {0x63u, 0x82u},\r
- {0x66u, 0x04u},\r
+ {0x00u, 0x08u},\r
+ {0x01u, 0x22u},\r
+ {0x02u, 0x01u},\r
+ {0x03u, 0x40u},\r
+ {0x04u, 0x44u},\r
+ {0x05u, 0x11u},\r
+ {0x08u, 0x18u},\r
+ {0x09u, 0x40u},\r
+ {0x0Au, 0x80u},\r
+ {0x0Eu, 0x28u},\r
+ {0x10u, 0x20u},\r
+ {0x12u, 0xC0u},\r
+ {0x13u, 0x08u},\r
+ {0x16u, 0x04u},\r
+ {0x19u, 0x08u},\r
+ {0x1Cu, 0x40u},\r
+ {0x1Eu, 0x20u},\r
+ {0x1Fu, 0x80u},\r
+ {0x22u, 0x02u},\r
+ {0x24u, 0x04u},\r
+ {0x25u, 0x01u},\r
+ {0x27u, 0x01u},\r
+ {0x28u, 0x10u},\r
+ {0x29u, 0x22u},\r
+ {0x2Au, 0x40u},\r
+ {0x2Du, 0x41u},\r
+ {0x2Fu, 0x20u},\r
+ {0x30u, 0x20u},\r
+ {0x32u, 0x48u},\r
+ {0x35u, 0x91u},\r
+ {0x36u, 0x04u},\r
+ {0x3Au, 0x11u},\r
+ {0x3Bu, 0x08u},\r
+ {0x3Cu, 0x04u},\r
+ {0x3Du, 0x02u},\r
+ {0x3Eu, 0x10u},\r
+ {0x46u, 0x80u},\r
+ {0x47u, 0x01u},\r
+ {0x48u, 0x04u},\r
+ {0x4Au, 0x08u},\r
+ {0x5Eu, 0x82u},\r
+ {0x5Fu, 0x24u},\r
+ {0x64u, 0x08u},\r
+ {0x66u, 0x82u},\r
+ {0x67u, 0x08u},\r
{0x69u, 0x80u},\r
- {0x6Bu, 0x02u},\r
- {0x6Cu, 0x20u},\r
- {0x6Du, 0x41u},\r
- {0x6Fu, 0xD9u},\r
- {0x74u, 0x80u},\r
- {0x76u, 0x02u},\r
+ {0x6Au, 0x80u},\r
+ {0x82u, 0x80u},\r
+ {0x8Au, 0x02u},\r
+ {0x91u, 0x41u},\r
+ {0x92u, 0x10u},\r
+ {0x93u, 0x05u},\r
+ {0x95u, 0x80u},\r
+ {0x98u, 0x10u},\r
+ {0x99u, 0xB1u},\r
+ {0x9Au, 0x05u},\r
+ {0x9Bu, 0x08u},\r
+ {0x9Cu, 0x08u},\r
+ {0x9Du, 0x08u},\r
+ {0xA0u, 0x04u},\r
+ {0xA2u, 0x45u},\r
+ {0xA3u, 0x20u},\r
+ {0xA6u, 0x02u},\r
+ {0xA8u, 0x04u},\r
+ {0xB2u, 0x10u},\r
+ {0xC0u, 0xFFu},\r
+ {0xC2u, 0x6Fu},\r
+ {0xC4u, 0x4Cu},\r
+ {0xCAu, 0xDFu},\r
+ {0xCCu, 0xFEu},\r
+ {0xCEu, 0xE7u},\r
+ {0xD6u, 0xF0u},\r
+ {0xD8u, 0x90u},\r
+ {0xE2u, 0x80u},\r
+ {0xE6u, 0x04u},\r
+ {0xE8u, 0x04u},\r
+ {0xEAu, 0x80u},\r
+ {0xEEu, 0x02u},\r
{0x81u, 0x40u},\r
- {0x8Fu, 0x40u},\r
- {0x91u, 0x04u},\r
- {0x92u, 0xE4u},\r
- {0x93u, 0x15u},\r
- {0x95u, 0x41u},\r
- {0x96u, 0x08u},\r
- {0x98u, 0xE1u},\r
- {0x99u, 0x27u},\r
- {0x9Au, 0xC4u},\r
- {0x9Bu, 0xA0u},\r
- {0x9Eu, 0x02u},\r
- {0x9Fu, 0x51u},\r
- {0xA1u, 0x10u},\r
- {0xA2u, 0x9Au},\r
- {0xA3u, 0x05u},\r
- {0xA4u, 0xA0u},\r
- {0xA5u, 0x40u},\r
- {0xA7u, 0x88u},\r
- {0xB0u, 0xA0u},\r
- {0xB5u, 0x10u},\r
- {0xC0u, 0xB5u},\r
- {0xC2u, 0x63u},\r
- {0xC4u, 0x3Bu},\r
- {0xCAu, 0x9Fu},\r
- {0xCCu, 0xFDu},\r
- {0xCEu, 0x6Eu},\r
- {0xD6u, 0x0Fu},\r
- {0xD8u, 0x49u},\r
- {0xE0u, 0x01u},\r
- {0xE6u, 0x40u},\r
- {0xEEu, 0x06u},\r
- {0x83u, 0x01u},\r
- {0x97u, 0x01u},\r
- {0x9Cu, 0x02u},\r
- {0x9Du, 0x20u},\r
- {0xABu, 0x80u},\r
- {0xB2u, 0x04u},\r
- {0xB3u, 0x08u},\r
- {0xB7u, 0x80u},\r
- {0xEAu, 0xA0u},\r
- {0xEEu, 0x12u},\r
- {0xACu, 0x02u},\r
- {0xB1u, 0x20u},\r
- {0xE8u, 0x20u},\r
+ {0x90u, 0x08u},\r
+ {0x91u, 0x40u},\r
+ {0x9Bu, 0x01u},\r
+ {0xA2u, 0x10u},\r
+ {0xAAu, 0x20u},\r
+ {0xEEu, 0x02u},\r
+ {0xB2u, 0x10u},\r
+ {0xB3u, 0x01u},\r
+ {0xB4u, 0x04u},\r
+ {0xEAu, 0x90u},\r
+ {0xEEu, 0x20u},\r
{0x12u, 0x08u},\r
{0x15u, 0x80u},\r
{0x17u, 0x01u},\r
{0x33u, 0x01u},\r
{0x36u, 0x88u},\r
- {0x38u, 0x01u},\r
- {0x39u, 0x80u},\r
- {0x3Cu, 0x04u},\r
- {0x3Du, 0x80u},\r
- {0x43u, 0x10u},\r
- {0x50u, 0x80u},\r
- {0x5Au, 0x04u},\r
- {0x5Du, 0x02u},\r
- {0x61u, 0x20u},\r
- {0x64u, 0x08u},\r
- {0x89u, 0x40u},\r
- {0x8Cu, 0x01u},\r
- {0x8Du, 0x20u},\r
+ {0x39u, 0x84u},\r
+ {0x3Du, 0x41u},\r
+ {0x40u, 0x08u},\r
+ {0x59u, 0x12u},\r
+ {0x5Fu, 0x02u},\r
+ {0x61u, 0x02u},\r
+ {0x65u, 0x04u},\r
+ {0x81u, 0x40u},\r
+ {0x87u, 0x02u},\r
+ {0x8Du, 0x10u},\r
{0xC4u, 0xE0u},\r
{0xCCu, 0xE0u},\r
{0xCEu, 0xF0u},\r
{0xD0u, 0x10u},\r
- {0xD4u, 0x20u},\r
+ {0xD4u, 0x80u},\r
{0xD6u, 0xC0u},\r
{0xD8u, 0xC0u},\r
- {0x31u, 0x20u},\r
- {0x32u, 0x04u},\r
+ {0xE6u, 0x60u},\r
+ {0x31u, 0x22u},\r
{0x36u, 0x40u},\r
{0x37u, 0x04u},\r
- {0x50u, 0x08u},\r
- {0x51u, 0x01u},\r
- {0x55u, 0x08u},\r
- {0x5Du, 0x02u},\r
- {0x81u, 0x02u},\r
- {0x89u, 0x01u},\r
- {0x94u, 0x04u},\r
- {0x96u, 0x04u},\r
+ {0x54u, 0x02u},\r
+ {0x56u, 0x80u},\r
+ {0x59u, 0x40u},\r
+ {0x63u, 0x80u},\r
+ {0x85u, 0x04u},\r
+ {0x95u, 0x04u},\r
{0x9Cu, 0x08u},\r
- {0x9Fu, 0x10u},\r
+ {0x9Du, 0x02u},\r
{0xA6u, 0x80u},\r
- {0xACu, 0x80u},\r
- {0xADu, 0x02u},\r
+ {0xA9u, 0x04u},\r
+ {0xADu, 0x01u},\r
+ {0xB1u, 0x02u},\r
{0xCCu, 0xF0u},\r
- {0xD4u, 0xE0u},\r
- {0xD6u, 0x80u},\r
- {0xE6u, 0x20u},\r
+ {0xD4u, 0xC0u},\r
+ {0xD6u, 0x20u},\r
+ {0xD8u, 0x40u},\r
+ {0xE6u, 0x40u},\r
{0xEAu, 0x10u},\r
- {0xEEu, 0x10u},\r
+ {0xEEu, 0x80u},\r
{0x12u, 0x80u},\r
- {0x80u, 0x08u},\r
- {0x86u, 0x04u},\r
- {0x89u, 0x02u},\r
- {0x8Cu, 0x08u},\r
- {0x96u, 0x0Cu},\r
+ {0x63u, 0x01u},\r
+ {0x83u, 0x41u},\r
+ {0x8Du, 0x02u},\r
{0x9Cu, 0x08u},\r
- {0x9Fu, 0x14u},\r
- {0xA4u, 0x08u},\r
- {0xA5u, 0x20u},\r
+ {0x9Du, 0x42u},\r
+ {0x9Fu, 0x04u},\r
+ {0xA5u, 0x22u},\r
{0xA6u, 0xC0u},\r
- {0xB4u, 0x04u},\r
- {0xB5u, 0x08u},\r
+ {0xA7u, 0x40u},\r
+ {0xA8u, 0x02u},\r
+ {0xAAu, 0x80u},\r
{0xC4u, 0x10u},\r
- {0xE2u, 0xC0u},\r
- {0x63u, 0x08u},\r
+ {0xD6u, 0x40u},\r
+ {0xE2u, 0xA0u},\r
+ {0xEAu, 0xA0u},\r
{0x83u, 0x04u},\r
{0x85u, 0x20u},\r
- {0x86u, 0x04u},\r
- {0x87u, 0x08u},\r
- {0x96u, 0x08u},\r
- {0x9Du, 0x02u},\r
- {0x9Fu, 0x14u},\r
- {0xA5u, 0x20u},\r
+ {0x89u, 0x42u},\r
+ {0x9Cu, 0x08u},\r
+ {0x9Du, 0x41u},\r
+ {0x9Fu, 0x04u},\r
+ {0xA5u, 0x22u},\r
{0xA6u, 0x40u},\r
- {0xD8u, 0x40u},\r
+ {0xA9u, 0x01u},\r
{0xE2u, 0x90u},\r
- {0xE6u, 0x50u},\r
- {0x09u, 0x80u},\r
- {0x0Eu, 0x80u},\r
- {0x13u, 0x01u},\r
- {0x50u, 0x80u},\r
- {0x51u, 0x02u},\r
- {0x54u, 0x04u},\r
- {0x56u, 0x01u},\r
- {0x8Fu, 0x01u},\r
+ {0xE8u, 0x20u},\r
+ {0x09u, 0x40u},\r
+ {0x0Fu, 0x20u},\r
+ {0x13u, 0x08u},\r
+ {0x51u, 0x08u},\r
+ {0x53u, 0x02u},\r
+ {0x57u, 0x20u},\r
+ {0x5Cu, 0x40u},\r
+ {0x81u, 0x08u},\r
{0xC2u, 0x06u},\r
{0xC4u, 0x08u},\r
{0xD4u, 0x07u},\r
{0xD6u, 0x04u},\r
- {0xE6u, 0x08u},\r
- {0x02u, 0x08u},\r
- {0x05u, 0x40u},\r
- {0x06u, 0x20u},\r
- {0x08u, 0x24u},\r
- {0x0Du, 0x08u},\r
- {0x0Eu, 0x08u},\r
- {0x84u, 0x20u},\r
- {0x85u, 0x02u},\r
- {0x88u, 0x04u},\r
- {0x8Cu, 0x80u},\r
- {0x8Du, 0x88u},\r
- {0x9Eu, 0x21u},\r
- {0xA1u, 0x80u},\r
- {0xA4u, 0x84u},\r
- {0xA5u, 0x02u},\r
- {0xAAu, 0x20u},\r
- {0xAEu, 0x40u},\r
+ {0x03u, 0x08u},\r
+ {0x06u, 0x08u},\r
+ {0x07u, 0x80u},\r
+ {0x0Bu, 0x84u},\r
+ {0x0Cu, 0x08u},\r
+ {0x0Du, 0x10u},\r
+ {0x82u, 0x08u},\r
+ {0x84u, 0x08u},\r
+ {0x87u, 0x40u},\r
+ {0x8Bu, 0x04u},\r
+ {0x8Cu, 0x40u},\r
+ {0x8Fu, 0x08u},\r
+ {0x94u, 0x40u},\r
+ {0xA1u, 0x40u},\r
+ {0xA3u, 0x10u},\r
+ {0xA7u, 0x02u},\r
+ {0xABu, 0x08u},\r
+ {0xB3u, 0x20u},\r
{0xC0u, 0x07u},\r
{0xC2u, 0x0Fu},\r
+ {0xE0u, 0x02u},\r
{0xE2u, 0x08u},\r
- {0xE4u, 0x02u},\r
- {0xE6u, 0x09u},\r
- {0x88u, 0x04u},\r
- {0xA4u, 0x04u},\r
- {0xAAu, 0x0Cu},\r
- {0xB1u, 0x40u},\r
- {0xB6u, 0x01u},\r
- {0xE0u, 0x04u},\r
- {0xEAu, 0x01u},\r
- {0xECu, 0x02u},\r
- {0x0Bu, 0x88u},\r
+ {0xE6u, 0x04u},\r
+ {0xE8u, 0x01u},\r
+ {0x8Fu, 0x10u},\r
+ {0xA1u, 0x40u},\r
+ {0xA3u, 0x10u},\r
+ {0xABu, 0x82u},\r
+ {0xB1u, 0x10u},\r
+ {0xE2u, 0x08u},\r
+ {0xEEu, 0x04u},\r
+ {0x09u, 0x40u},\r
+ {0x0Bu, 0x80u},\r
{0x0Fu, 0x41u},\r
{0x83u, 0x01u},\r
- {0x87u, 0x44u},\r
+ {0x87u, 0x40u},\r
+ {0x89u, 0x40u},\r
+ {0xB1u, 0x40u},\r
{0xC2u, 0x0Fu},\r
- {0x8Fu, 0x10u},\r
- {0x9Du, 0x02u},\r
- {0x9Fu, 0x10u},\r
- {0xA3u, 0x08u},\r
- {0xABu, 0x04u},\r
+ {0xE6u, 0x04u},\r
+ {0xEEu, 0x04u},\r
+ {0x88u, 0x08u},\r
+ {0x9Cu, 0x08u},\r
+ {0x9Du, 0x01u},\r
+ {0xA3u, 0x20u},\r
{0xAEu, 0x40u},\r
- {0xEEu, 0x60u},\r
- {0x05u, 0x02u},\r
- {0x57u, 0x08u},\r
- {0x5Du, 0x40u},\r
- {0x91u, 0x40u},\r
- {0x9Du, 0x02u},\r
- {0xA3u, 0x08u},\r
- {0xB5u, 0x40u},\r
+ {0xB3u, 0x20u},\r
+ {0xEEu, 0x40u},\r
+ {0x05u, 0x01u},\r
+ {0x57u, 0x21u},\r
+ {0x9Du, 0x01u},\r
+ {0xA3u, 0x21u},\r
+ {0xAFu, 0x01u},\r
{0xC0u, 0x20u},\r
{0xD4u, 0x40u},\r
{0xD6u, 0x20u},\r
+ {0xEEu, 0x10u},\r
{0xAFu, 0x40u},\r
{0x00u, 0x03u},\r
{0x08u, 0x03u},\r
{0x0Au, 0x03u},\r
- {0x10u, 0x03u},\r
- {0x1Au, 0x03u},\r
+ {0x0Eu, 0x02u},\r
+ {0x10u, 0x01u},\r
+ {0x1Au, 0x01u},\r
{0x00u, 0xFDu},\r
{0x01u, 0xABu},\r
{0x02u, 0x02u},\r
uint16 size;\r
} CYPACKED_ATTR cfg_memset_t;\r
\r
-\r
- CYPACKED typedef struct {\r
- void CYFAR *dest;\r
- const void CYCODE *src;\r
- uint16 size;\r
- } CYPACKED_ATTR cfg_memcpy_t;\r
-\r
static const cfg_memset_t CYCODE cfg_memset_list [] = {\r
/* address, size */\r
{(void CYFAR *)(CYREG_TMR0_CFG0), 12u},\r
{(void CYFAR *)(CYREG_PRT1_DR), 16u},\r
- {(void CYFAR *)(CYDEV_UCFG_B0_P0_U0_BASE), 1024u},\r
- {(void CYFAR *)(CYDEV_UCFG_B0_P2_U1_BASE), 2944u},\r
+ {(void CYFAR *)(CYDEV_UCFG_B0_P0_U0_BASE), 4096u},\r
{(void CYFAR *)(CYDEV_UCFG_B1_P2_U0_BASE), 2048u},\r
{(void CYFAR *)(CYDEV_UCFG_DSI0_BASE), 2560u},\r
{(void CYFAR *)(CYDEV_UCFG_DSI12_BASE), 512u},\r
{(void CYFAR *)(CYREG_BCTL0_MDCLK_EN), 32u},\r
};\r
\r
- /* UDB_1_3_0_CONFIG Address: CYDEV_UCFG_B0_P2_U0_BASE Size (bytes): 128 */\r
- static const uint8 CYCODE BS_UDB_1_3_0_CONFIG_VAL[] = {\r
- 0x8Du, 0x00u, 0x00u, 0x00u, 0x8Du, 0x09u, 0x00u, 0x12u, 0x8Du, 0x00u, 0x00u, 0x01u, 0x0Du, 0x00u, 0x80u, 0x30u, \r
- 0x02u, 0x00u, 0x0Du, 0x00u, 0x00u, 0x00u, 0x80u, 0x09u, 0x12u, 0x00u, 0x44u, 0x06u, 0x60u, 0x00u, 0x00u, 0x08u, \r
- 0x8Du, 0x09u, 0x00u, 0x24u, 0x00u, 0x00u, 0x00u, 0x00u, 0x22u, 0x00u, 0x18u, 0x00u, 0x11u, 0x00u, 0x22u, 0x00u, \r
- 0x0Fu, 0x38u, 0x00u, 0x00u, 0x80u, 0x07u, 0x70u, 0x00u, 0x80u, 0x00u, 0x02u, 0x00u, 0x00u, 0x00u, 0x10u, 0x00u, \r
- 0x26u, 0x05u, 0x40u, 0x00u, 0x03u, 0xBEu, 0xFBu, 0xDCu, 0x3Fu, 0xFFu, 0xFFu, 0xFFu, 0x22u, 0x00u, 0xF0u, 0x08u, \r
- 0x04u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x04u, 0x04u, 0x04u, 0x04u, 0x10u, 0x00u, 0x00u, 0x01u, \r
- 0x00u, 0x00u, 0xC0u, 0x00u, 0x40u, 0x01u, 0x10u, 0x11u, 0xC0u, 0x01u, 0x00u, 0x11u, 0x40u, 0x01u, 0x40u, 0x01u, \r
- 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u};\r
-\r
- static const cfg_memcpy_t CYCODE cfg_memcpy_list [] = {\r
- /* dest, src, size */\r
- {(void CYFAR *)(CYDEV_UCFG_B0_P2_U0_BASE), BS_UDB_1_3_0_CONFIG_VAL, 128u},\r
- };\r
-\r
uint8 CYDATA i;\r
\r
/* Zero out critical memory blocks before beginning configuration */\r
CYMEMZERO(ms->address, (uint32)(ms->size));\r
}\r
\r
- /* Copy device configuration data into registers */\r
- for (i = 0u; i < (sizeof(cfg_memcpy_list)/sizeof(cfg_memcpy_list[0])); i++)\r
- {\r
- const cfg_memcpy_t CYCODE * CYDATA mc = &cfg_memcpy_list[i];\r
- void * CYDATA destPtr = mc->dest;\r
- const void CYCODE * CYDATA srcPtr = mc->src;\r
- uint16 CYDATA numBytes = mc->size;\r
- CYCONFIGCPYCODE(destPtr, srcPtr, numBytes);\r
- }\r
-\r
cfg_write_bytes32(cy_cfg_addr_table, cy_cfg_data_table);\r
\r
/* Perform normal device configuration. Order is not critical for these items. */\r
/* SCSI_CTL_PHASE */\r
.set SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK, 0x01\r
.set SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS, 0\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB02_03_ACTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB02_03_CTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB02_03_CTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB02_03_CTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB02_03_CTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB02_03_MSK\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB02_03_MSK\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB02_03_MSK\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB02_03_MSK\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB05_06_ACTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB05_06_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB05_06_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB05_06_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB05_06_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB05_06_MSK\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB05_06_MSK\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB05_06_MSK\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB05_06_MSK\r
.set SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK, 0x02\r
.set SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS, 1\r
.set SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK, 0x04\r
.set SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS, 2\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB02_ACTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB02_CTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB02_ST_CTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB02_CTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB02_ST_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB05_ACTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB05_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB05_ST_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB05_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB05_ST_CTL\r
.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK, 0x07\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB02_MSK_ACTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB02_MSK\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB02_MSK_ACTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB05_MSK_ACTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB05_MSK\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB05_MSK_ACTL\r
\r
/* SCSI_Out_Bits */\r
.set SCSI_Out_Bits_Sync_ctrl_reg__0__MASK, 0x01\r
.set SCSI_RST_ISR__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
\r
/* SDCard_BSPIM */\r
-.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB06_07_ACTL\r
-.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B1_UDB06_07_ST\r
-.set SDCard_BSPIM_BitCounter_ST__MASK_REG, CYREG_B1_UDB06_MSK\r
-.set SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B1_UDB06_MSK_ACTL\r
-.set SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B1_UDB06_MSK_ACTL\r
-.set SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B1_UDB06_ACTL\r
-.set SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B1_UDB06_ST_CTL\r
-.set SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B1_UDB06_ST_CTL\r
-.set SDCard_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B1_UDB06_ST\r
-.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB06_07_ACTL\r
-.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB06_07_CTL\r
-.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB06_07_CTL\r
-.set SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB06_07_CTL\r
-.set SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB06_07_CTL\r
-.set SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B1_UDB06_07_MSK\r
-.set SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB06_07_MSK\r
-.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB06_07_MSK\r
-.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB06_07_MSK\r
-.set SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B1_UDB06_ACTL\r
-.set SDCard_BSPIM_BitCounter__CONTROL_REG, CYREG_B1_UDB06_CTL\r
-.set SDCard_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B1_UDB06_ST_CTL\r
-.set SDCard_BSPIM_BitCounter__COUNT_REG, CYREG_B1_UDB06_CTL\r
-.set SDCard_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B1_UDB06_ST_CTL\r
-.set SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB06_MSK_ACTL\r
-.set SDCard_BSPIM_BitCounter__PERIOD_REG, CYREG_B1_UDB06_MSK\r
-.set SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB06_MSK_ACTL\r
-.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB07_08_ACTL\r
-.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB07_08_ST\r
+.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB06_07_ACTL\r
+.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B0_UDB06_07_ST\r
+.set SDCard_BSPIM_BitCounter_ST__MASK_REG, CYREG_B0_UDB06_MSK\r
+.set SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB06_MSK_ACTL\r
+.set SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B0_UDB06_MSK_ACTL\r
+.set SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B0_UDB06_ACTL\r
+.set SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B0_UDB06_ST_CTL\r
+.set SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B0_UDB06_ST_CTL\r
+.set SDCard_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B0_UDB06_ST\r
+.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB06_07_ACTL\r
+.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB06_07_CTL\r
+.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB06_07_CTL\r
+.set SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB06_07_CTL\r
+.set SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB06_07_CTL\r
+.set SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B0_UDB06_07_MSK\r
+.set SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB06_07_MSK\r
+.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB06_07_MSK\r
+.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB06_07_MSK\r
+.set SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B0_UDB06_ACTL\r
+.set SDCard_BSPIM_BitCounter__CONTROL_REG, CYREG_B0_UDB06_CTL\r
+.set SDCard_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B0_UDB06_ST_CTL\r
+.set SDCard_BSPIM_BitCounter__COUNT_REG, CYREG_B0_UDB06_CTL\r
+.set SDCard_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B0_UDB06_ST_CTL\r
+.set SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB06_MSK_ACTL\r
+.set SDCard_BSPIM_BitCounter__PERIOD_REG, CYREG_B0_UDB06_MSK\r
+.set SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB06_MSK_ACTL\r
+.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB05_06_ACTL\r
+.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB05_06_ST\r
.set SDCard_BSPIM_RxStsReg__4__MASK, 0x10\r
.set SDCard_BSPIM_RxStsReg__4__POS, 4\r
.set SDCard_BSPIM_RxStsReg__5__MASK, 0x20\r
.set SDCard_BSPIM_RxStsReg__6__MASK, 0x40\r
.set SDCard_BSPIM_RxStsReg__6__POS, 6\r
.set SDCard_BSPIM_RxStsReg__MASK, 0x70\r
-.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B0_UDB07_MSK\r
-.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB07_ACTL\r
-.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B0_UDB07_ST\r
+.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B0_UDB05_MSK\r
+.set SDCard_BSPIM_RxStsReg__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB05_MSK_ACTL\r
+.set SDCard_BSPIM_RxStsReg__PER_ST_AUX_CTL_REG, CYREG_B0_UDB05_MSK_ACTL\r
+.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB05_ACTL\r
+.set SDCard_BSPIM_RxStsReg__STATUS_CNT_REG, CYREG_B0_UDB05_ST_CTL\r
+.set SDCard_BSPIM_RxStsReg__STATUS_CONTROL_REG, CYREG_B0_UDB05_ST_CTL\r
+.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B0_UDB05_ST\r
.set SDCard_BSPIM_TxStsReg__0__MASK, 0x01\r
.set SDCard_BSPIM_TxStsReg__0__POS, 0\r
-.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB07_08_ACTL\r
-.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB07_08_ST\r
+.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB06_07_ACTL\r
+.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB06_07_ST\r
.set SDCard_BSPIM_TxStsReg__1__MASK, 0x02\r
.set SDCard_BSPIM_TxStsReg__1__POS, 1\r
.set SDCard_BSPIM_TxStsReg__2__MASK, 0x04\r
.set SDCard_BSPIM_TxStsReg__4__MASK, 0x10\r
.set SDCard_BSPIM_TxStsReg__4__POS, 4\r
.set SDCard_BSPIM_TxStsReg__MASK, 0x1F\r
-.set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B1_UDB07_MSK\r
-.set SDCard_BSPIM_TxStsReg__MASK_ST_AUX_CTL_REG, CYREG_B1_UDB07_MSK_ACTL\r
-.set SDCard_BSPIM_TxStsReg__PER_ST_AUX_CTL_REG, CYREG_B1_UDB07_MSK_ACTL\r
-.set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB07_ACTL\r
-.set SDCard_BSPIM_TxStsReg__STATUS_CNT_REG, CYREG_B1_UDB07_ST_CTL\r
-.set SDCard_BSPIM_TxStsReg__STATUS_CONTROL_REG, CYREG_B1_UDB07_ST_CTL\r
-.set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B1_UDB07_ST\r
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG, CYREG_B0_UDB04_05_A0\r
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG, CYREG_B0_UDB04_05_A1\r
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG, CYREG_B0_UDB04_05_D0\r
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG, CYREG_B0_UDB04_05_D1\r
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG, CYREG_B0_UDB04_05_ACTL\r
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG, CYREG_B0_UDB04_05_F0\r
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG, CYREG_B0_UDB04_05_F1\r
-.set SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG, CYREG_B0_UDB04_A0_A1\r
-.set SDCard_BSPIM_sR8_Dp_u0__A0_REG, CYREG_B0_UDB04_A0\r
-.set SDCard_BSPIM_sR8_Dp_u0__A1_REG, CYREG_B0_UDB04_A1\r
-.set SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG, CYREG_B0_UDB04_D0_D1\r
-.set SDCard_BSPIM_sR8_Dp_u0__D0_REG, CYREG_B0_UDB04_D0\r
-.set SDCard_BSPIM_sR8_Dp_u0__D1_REG, CYREG_B0_UDB04_D1\r
-.set SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG, CYREG_B0_UDB04_ACTL\r
-.set SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG, CYREG_B0_UDB04_F0_F1\r
-.set SDCard_BSPIM_sR8_Dp_u0__F0_REG, CYREG_B0_UDB04_F0\r
-.set SDCard_BSPIM_sR8_Dp_u0__F1_REG, CYREG_B0_UDB04_F1\r
+.set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B1_UDB06_MSK\r
+.set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB06_ACTL\r
+.set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B1_UDB06_ST\r
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG, CYREG_B0_UDB05_06_A0\r
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG, CYREG_B0_UDB05_06_A1\r
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG, CYREG_B0_UDB05_06_D0\r
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG, CYREG_B0_UDB05_06_D1\r
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG, CYREG_B0_UDB05_06_ACTL\r
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG, CYREG_B0_UDB05_06_F0\r
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG, CYREG_B0_UDB05_06_F1\r
+.set SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG, CYREG_B0_UDB05_A0_A1\r
+.set SDCard_BSPIM_sR8_Dp_u0__A0_REG, CYREG_B0_UDB05_A0\r
+.set SDCard_BSPIM_sR8_Dp_u0__A1_REG, CYREG_B0_UDB05_A1\r
+.set SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG, CYREG_B0_UDB05_D0_D1\r
+.set SDCard_BSPIM_sR8_Dp_u0__D0_REG, CYREG_B0_UDB05_D0\r
+.set SDCard_BSPIM_sR8_Dp_u0__D1_REG, CYREG_B0_UDB05_D1\r
+.set SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG, CYREG_B0_UDB05_ACTL\r
+.set SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG, CYREG_B0_UDB05_F0_F1\r
+.set SDCard_BSPIM_sR8_Dp_u0__F0_REG, CYREG_B0_UDB05_F0\r
+.set SDCard_BSPIM_sR8_Dp_u0__F1_REG, CYREG_B0_UDB05_F1\r
+.set SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG, CYREG_B0_UDB05_MSK_ACTL\r
+.set SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG, CYREG_B0_UDB05_MSK_ACTL\r
\r
/* USBFS_dp_int */\r
.set USBFS_dp_int__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
.set SD_Data_Clk__PM_STBY_CFG, CYREG_PM_STBY_CFG2\r
.set SD_Data_Clk__PM_STBY_MSK, 0x01\r
\r
-/* SD_Init_Clk */\r
-.set SD_Init_Clk__CFG0, CYREG_CLKDIST_DCFG3_CFG0\r
-.set SD_Init_Clk__CFG1, CYREG_CLKDIST_DCFG3_CFG1\r
-.set SD_Init_Clk__CFG2, CYREG_CLKDIST_DCFG3_CFG2\r
-.set SD_Init_Clk__CFG2_SRC_SEL_MASK, 0x07\r
-.set SD_Init_Clk__INDEX, 0x03\r
-.set SD_Init_Clk__PM_ACT_CFG, CYREG_PM_ACT_CFG2\r
-.set SD_Init_Clk__PM_ACT_MSK, 0x08\r
-.set SD_Init_Clk__PM_STBY_CFG, CYREG_PM_STBY_CFG2\r
-.set SD_Init_Clk__PM_STBY_MSK, 0x08\r
-\r
/* timer_clock */\r
.set timer_clock__CFG0, CYREG_CLKDIST_DCFG2_CFG0\r
.set timer_clock__CFG1, CYREG_CLKDIST_DCFG2_CFG1\r
/* scsiTarget */\r
.set scsiTarget_StatusReg__0__MASK, 0x01\r
.set scsiTarget_StatusReg__0__POS, 0\r
-.set scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB04_05_ACTL\r
-.set scsiTarget_StatusReg__16BIT_STATUS_REG, CYREG_B0_UDB04_05_ST\r
+.set scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB00_01_ACTL\r
+.set scsiTarget_StatusReg__16BIT_STATUS_REG, CYREG_B0_UDB00_01_ST\r
.set scsiTarget_StatusReg__1__MASK, 0x02\r
.set scsiTarget_StatusReg__1__POS, 1\r
.set scsiTarget_StatusReg__2__MASK, 0x04\r
.set scsiTarget_StatusReg__4__MASK, 0x10\r
.set scsiTarget_StatusReg__4__POS, 4\r
.set scsiTarget_StatusReg__MASK, 0x1F\r
-.set scsiTarget_StatusReg__MASK_REG, CYREG_B0_UDB04_MSK\r
-.set scsiTarget_StatusReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB04_ACTL\r
-.set scsiTarget_StatusReg__STATUS_REG, CYREG_B0_UDB04_ST\r
+.set scsiTarget_StatusReg__MASK_REG, CYREG_B0_UDB00_MSK\r
+.set scsiTarget_StatusReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB00_ACTL\r
+.set scsiTarget_StatusReg__STATUS_REG, CYREG_B0_UDB00_ST\r
.set scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB03_04_ACTL\r
.set scsiTarget_datapath_PI__16BIT_STATUS_REG, CYREG_B0_UDB03_04_ST\r
.set scsiTarget_datapath_PI__MASK_REG, CYREG_B0_UDB03_MSK\r
.set scsiTarget_datapath__MSK_DP_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL\r
.set scsiTarget_datapath__PER_DP_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL\r
\r
-/* SD_Clk_Ctl */\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__REMOVED, 1\r
-\r
/* USBFS_ep_0 */\r
.set USBFS_ep_0__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
.set USBFS_ep_0__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
/* SCSI_CTL_PHASE */\r
SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01\r
SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS EQU 0\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB02_03_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB02_03_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB02_03_MSK\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB02_03_MSK\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB05_06_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB05_06_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB05_06_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB05_06_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK\r
SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK EQU 0x02\r
SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS EQU 1\r
SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK EQU 0x04\r
SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS EQU 2\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB02_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB02_ST_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB02_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB02_ST_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB05_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB05_ST_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB05_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB05_ST_CTL\r
SCSI_CTL_PHASE_Sync_ctrl_reg__MASK EQU 0x07\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB02_MSK\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB05_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL\r
\r
/* SCSI_Out_Bits */\r
SCSI_Out_Bits_Sync_ctrl_reg__0__MASK EQU 0x01\r
SCSI_RST_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
\r
/* SDCard_BSPIM */\r
-SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL\r
-SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB06_07_ST\r
-SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB06_MSK\r
-SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL\r
-SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB06_ST_CTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB06_ST_CTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB06_ST\r
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL\r
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB06_07_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB06_07_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB06_07_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB06_07_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB06_07_MSK\r
-SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB06_07_MSK\r
-SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB06_07_MSK\r
-SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB06_07_MSK\r
-SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL\r
-SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB06_CTL\r
-SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB06_ST_CTL\r
-SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB06_CTL\r
-SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB06_ST_CTL\r
-SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL\r
-SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB06_MSK\r
-SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL\r
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL\r
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB07_08_ST\r
+SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL\r
+SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B0_UDB06_07_ST\r
+SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B0_UDB06_MSK\r
+SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL\r
+SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B0_UDB06_ST_CTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B0_UDB06_ST_CTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B0_UDB06_ST\r
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL\r
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB06_07_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB06_07_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB06_07_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB06_07_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB06_07_MSK\r
+SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB06_07_MSK\r
+SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB06_07_MSK\r
+SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB06_07_MSK\r
+SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL\r
+SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B0_UDB06_CTL\r
+SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B0_UDB06_ST_CTL\r
+SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B0_UDB06_CTL\r
+SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B0_UDB06_ST_CTL\r
+SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL\r
+SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B0_UDB06_MSK\r
+SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL\r
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL\r
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB05_06_ST\r
SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10\r
SDCard_BSPIM_RxStsReg__4__POS EQU 4\r
SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20\r
SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40\r
SDCard_BSPIM_RxStsReg__6__POS EQU 6\r
SDCard_BSPIM_RxStsReg__MASK EQU 0x70\r
-SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B0_UDB07_MSK\r
-SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL\r
-SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B0_UDB07_ST\r
+SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B0_UDB05_MSK\r
+SDCard_BSPIM_RxStsReg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL\r
+SDCard_BSPIM_RxStsReg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL\r
+SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL\r
+SDCard_BSPIM_RxStsReg__STATUS_CNT_REG EQU CYREG_B0_UDB05_ST_CTL\r
+SDCard_BSPIM_RxStsReg__STATUS_CONTROL_REG EQU CYREG_B0_UDB05_ST_CTL\r
+SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B0_UDB05_ST\r
SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01\r
SDCard_BSPIM_TxStsReg__0__POS EQU 0\r
-SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL\r
-SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST\r
+SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL\r
+SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB06_07_ST\r
SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02\r
SDCard_BSPIM_TxStsReg__1__POS EQU 1\r
SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04\r
SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10\r
SDCard_BSPIM_TxStsReg__4__POS EQU 4\r
SDCard_BSPIM_TxStsReg__MASK EQU 0x1F\r
-SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB07_MSK\r
-SDCard_BSPIM_TxStsReg__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL\r
-SDCard_BSPIM_TxStsReg__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL\r
-SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL\r
-SDCard_BSPIM_TxStsReg__STATUS_CNT_REG EQU CYREG_B1_UDB07_ST_CTL\r
-SDCard_BSPIM_TxStsReg__STATUS_CONTROL_REG EQU CYREG_B1_UDB07_ST_CTL\r
-SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB07_ST\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B0_UDB04_05_A0\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B0_UDB04_05_A1\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B0_UDB04_05_D0\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B0_UDB04_05_D1\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B0_UDB04_05_F0\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B0_UDB04_05_F1\r
-SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B0_UDB04_A0_A1\r
-SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B0_UDB04_A0\r
-SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B0_UDB04_A1\r
-SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B0_UDB04_D0_D1\r
-SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B0_UDB04_D0\r
-SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B0_UDB04_D1\r
-SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL\r
-SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B0_UDB04_F0_F1\r
-SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B0_UDB04_F0\r
-SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B0_UDB04_F1\r
+SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB06_MSK\r
+SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL\r
+SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB06_ST\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B0_UDB05_06_A0\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B0_UDB05_06_A1\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B0_UDB05_06_D0\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B0_UDB05_06_D1\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B0_UDB05_06_F0\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B0_UDB05_06_F1\r
+SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B0_UDB05_A0_A1\r
+SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B0_UDB05_A0\r
+SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B0_UDB05_A1\r
+SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B0_UDB05_D0_D1\r
+SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B0_UDB05_D0\r
+SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B0_UDB05_D1\r
+SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL\r
+SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B0_UDB05_F0_F1\r
+SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B0_UDB05_F0\r
+SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B0_UDB05_F1\r
+SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL\r
+SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL\r
\r
/* USBFS_dp_int */\r
USBFS_dp_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
SD_Data_Clk__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2\r
SD_Data_Clk__PM_STBY_MSK EQU 0x01\r
\r
-/* SD_Init_Clk */\r
-SD_Init_Clk__CFG0 EQU CYREG_CLKDIST_DCFG3_CFG0\r
-SD_Init_Clk__CFG1 EQU CYREG_CLKDIST_DCFG3_CFG1\r
-SD_Init_Clk__CFG2 EQU CYREG_CLKDIST_DCFG3_CFG2\r
-SD_Init_Clk__CFG2_SRC_SEL_MASK EQU 0x07\r
-SD_Init_Clk__INDEX EQU 0x03\r
-SD_Init_Clk__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2\r
-SD_Init_Clk__PM_ACT_MSK EQU 0x08\r
-SD_Init_Clk__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2\r
-SD_Init_Clk__PM_STBY_MSK EQU 0x08\r
-\r
/* timer_clock */\r
timer_clock__CFG0 EQU CYREG_CLKDIST_DCFG2_CFG0\r
timer_clock__CFG1 EQU CYREG_CLKDIST_DCFG2_CFG1\r
/* scsiTarget */\r
scsiTarget_StatusReg__0__MASK EQU 0x01\r
scsiTarget_StatusReg__0__POS EQU 0\r
-scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL\r
-scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB04_05_ST\r
+scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB00_01_ACTL\r
+scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB00_01_ST\r
scsiTarget_StatusReg__1__MASK EQU 0x02\r
scsiTarget_StatusReg__1__POS EQU 1\r
scsiTarget_StatusReg__2__MASK EQU 0x04\r
scsiTarget_StatusReg__4__MASK EQU 0x10\r
scsiTarget_StatusReg__4__POS EQU 4\r
scsiTarget_StatusReg__MASK EQU 0x1F\r
-scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB04_MSK\r
-scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL\r
-scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB04_ST\r
+scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB00_MSK\r
+scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB00_ACTL\r
+scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB00_ST\r
scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL\r
scsiTarget_datapath_PI__16BIT_STATUS_REG EQU CYREG_B0_UDB03_04_ST\r
scsiTarget_datapath_PI__MASK_REG EQU CYREG_B0_UDB03_MSK\r
scsiTarget_datapath__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL\r
scsiTarget_datapath__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL\r
\r
-/* SD_Clk_Ctl */\r
-SD_Clk_Ctl_Sync_ctrl_reg__REMOVED EQU 1\r
-\r
/* USBFS_ep_0 */\r
USBFS_ep_0__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
USBFS_ep_0__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
; SCSI_CTL_PHASE\r
SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01\r
SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS EQU 0\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB02_03_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB02_03_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB02_03_MSK\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB02_03_MSK\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB05_06_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB05_06_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB05_06_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB05_06_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK\r
SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK EQU 0x02\r
SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS EQU 1\r
SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK EQU 0x04\r
SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS EQU 2\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB02_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB02_ST_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB02_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB02_ST_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB05_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB05_ST_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB05_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB05_ST_CTL\r
SCSI_CTL_PHASE_Sync_ctrl_reg__MASK EQU 0x07\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB02_MSK\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB05_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL\r
\r
; SCSI_Out_Bits\r
SCSI_Out_Bits_Sync_ctrl_reg__0__MASK EQU 0x01\r
SCSI_RST_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
\r
; SDCard_BSPIM\r
-SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL\r
-SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB06_07_ST\r
-SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB06_MSK\r
-SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL\r
-SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB06_ST_CTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB06_ST_CTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB06_ST\r
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL\r
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB06_07_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB06_07_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB06_07_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB06_07_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB06_07_MSK\r
-SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB06_07_MSK\r
-SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB06_07_MSK\r
-SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB06_07_MSK\r
-SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL\r
-SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB06_CTL\r
-SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB06_ST_CTL\r
-SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB06_CTL\r
-SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB06_ST_CTL\r
-SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL\r
-SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB06_MSK\r
-SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL\r
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL\r
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB07_08_ST\r
+SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL\r
+SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B0_UDB06_07_ST\r
+SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B0_UDB06_MSK\r
+SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL\r
+SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B0_UDB06_ST_CTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B0_UDB06_ST_CTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B0_UDB06_ST\r
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL\r
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB06_07_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB06_07_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB06_07_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB06_07_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB06_07_MSK\r
+SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB06_07_MSK\r
+SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB06_07_MSK\r
+SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB06_07_MSK\r
+SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL\r
+SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B0_UDB06_CTL\r
+SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B0_UDB06_ST_CTL\r
+SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B0_UDB06_CTL\r
+SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B0_UDB06_ST_CTL\r
+SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL\r
+SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B0_UDB06_MSK\r
+SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL\r
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL\r
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB05_06_ST\r
SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10\r
SDCard_BSPIM_RxStsReg__4__POS EQU 4\r
SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20\r
SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40\r
SDCard_BSPIM_RxStsReg__6__POS EQU 6\r
SDCard_BSPIM_RxStsReg__MASK EQU 0x70\r
-SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B0_UDB07_MSK\r
-SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL\r
-SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B0_UDB07_ST\r
+SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B0_UDB05_MSK\r
+SDCard_BSPIM_RxStsReg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL\r
+SDCard_BSPIM_RxStsReg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL\r
+SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL\r
+SDCard_BSPIM_RxStsReg__STATUS_CNT_REG EQU CYREG_B0_UDB05_ST_CTL\r
+SDCard_BSPIM_RxStsReg__STATUS_CONTROL_REG EQU CYREG_B0_UDB05_ST_CTL\r
+SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B0_UDB05_ST\r
SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01\r
SDCard_BSPIM_TxStsReg__0__POS EQU 0\r
-SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL\r
-SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST\r
+SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL\r
+SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB06_07_ST\r
SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02\r
SDCard_BSPIM_TxStsReg__1__POS EQU 1\r
SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04\r
SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10\r
SDCard_BSPIM_TxStsReg__4__POS EQU 4\r
SDCard_BSPIM_TxStsReg__MASK EQU 0x1F\r
-SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB07_MSK\r
-SDCard_BSPIM_TxStsReg__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL\r
-SDCard_BSPIM_TxStsReg__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL\r
-SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL\r
-SDCard_BSPIM_TxStsReg__STATUS_CNT_REG EQU CYREG_B1_UDB07_ST_CTL\r
-SDCard_BSPIM_TxStsReg__STATUS_CONTROL_REG EQU CYREG_B1_UDB07_ST_CTL\r
-SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB07_ST\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B0_UDB04_05_A0\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B0_UDB04_05_A1\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B0_UDB04_05_D0\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B0_UDB04_05_D1\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B0_UDB04_05_F0\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B0_UDB04_05_F1\r
-SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B0_UDB04_A0_A1\r
-SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B0_UDB04_A0\r
-SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B0_UDB04_A1\r
-SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B0_UDB04_D0_D1\r
-SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B0_UDB04_D0\r
-SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B0_UDB04_D1\r
-SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL\r
-SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B0_UDB04_F0_F1\r
-SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B0_UDB04_F0\r
-SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B0_UDB04_F1\r
+SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB06_MSK\r
+SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL\r
+SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB06_ST\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B0_UDB05_06_A0\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B0_UDB05_06_A1\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B0_UDB05_06_D0\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B0_UDB05_06_D1\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B0_UDB05_06_F0\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B0_UDB05_06_F1\r
+SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B0_UDB05_A0_A1\r
+SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B0_UDB05_A0\r
+SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B0_UDB05_A1\r
+SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B0_UDB05_D0_D1\r
+SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B0_UDB05_D0\r
+SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B0_UDB05_D1\r
+SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL\r
+SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B0_UDB05_F0_F1\r
+SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B0_UDB05_F0\r
+SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B0_UDB05_F1\r
+SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL\r
+SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL\r
\r
; USBFS_dp_int\r
USBFS_dp_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
SD_Data_Clk__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2\r
SD_Data_Clk__PM_STBY_MSK EQU 0x01\r
\r
-; SD_Init_Clk\r
-SD_Init_Clk__CFG0 EQU CYREG_CLKDIST_DCFG3_CFG0\r
-SD_Init_Clk__CFG1 EQU CYREG_CLKDIST_DCFG3_CFG1\r
-SD_Init_Clk__CFG2 EQU CYREG_CLKDIST_DCFG3_CFG2\r
-SD_Init_Clk__CFG2_SRC_SEL_MASK EQU 0x07\r
-SD_Init_Clk__INDEX EQU 0x03\r
-SD_Init_Clk__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2\r
-SD_Init_Clk__PM_ACT_MSK EQU 0x08\r
-SD_Init_Clk__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2\r
-SD_Init_Clk__PM_STBY_MSK EQU 0x08\r
-\r
; timer_clock\r
timer_clock__CFG0 EQU CYREG_CLKDIST_DCFG2_CFG0\r
timer_clock__CFG1 EQU CYREG_CLKDIST_DCFG2_CFG1\r
; scsiTarget\r
scsiTarget_StatusReg__0__MASK EQU 0x01\r
scsiTarget_StatusReg__0__POS EQU 0\r
-scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL\r
-scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB04_05_ST\r
+scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB00_01_ACTL\r
+scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB00_01_ST\r
scsiTarget_StatusReg__1__MASK EQU 0x02\r
scsiTarget_StatusReg__1__POS EQU 1\r
scsiTarget_StatusReg__2__MASK EQU 0x04\r
scsiTarget_StatusReg__4__MASK EQU 0x10\r
scsiTarget_StatusReg__4__POS EQU 4\r
scsiTarget_StatusReg__MASK EQU 0x1F\r
-scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB04_MSK\r
-scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL\r
-scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB04_ST\r
+scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB00_MSK\r
+scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB00_ACTL\r
+scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB00_ST\r
scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL\r
scsiTarget_datapath_PI__16BIT_STATUS_REG EQU CYREG_B0_UDB03_04_ST\r
scsiTarget_datapath_PI__MASK_REG EQU CYREG_B0_UDB03_MSK\r
scsiTarget_datapath__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL\r
scsiTarget_datapath__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL\r
\r
-; SD_Clk_Ctl\r
-SD_Clk_Ctl_Sync_ctrl_reg__REMOVED EQU 1\r
-\r
; USBFS_ep_0\r
USBFS_ep_0__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
USBFS_ep_0__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
#include <cydisabledsheets.h>\r
#include <SCSI_In_DBx_aliases.h>\r
#include <SCSI_Out_DBx_aliases.h>\r
-#include <SD_Clk_Ctl.h>\r
#include <SD_Data_Clk.h>\r
-#include <SD_Init_Clk.h>\r
#include <SD_CD_aliases.h>\r
#include <SD_CD.h>\r
#include <SD_DAT2_aliases.h>\r
<?xml version="1.0" encoding="utf-8"?>\r
<blockRegMap version="1" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://cypress.com/xsd/cyblockregmap cyblockregmap.xsd" xmlns="http://cypress.com/xsd/cyblockregmap">\r
- <block name="SCSI_Out_Mux" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="Bootloadable_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="SCSI_Out_Ctl" BASE="0x0" SIZE="0x0" desc="" visible="true">\r
+ <register name="SCSI_Out_Ctl_CONTROL_REG" address="0x40006577" bitWidth="8" desc="" />\r
+ </block>\r
<block name="SCSI_Out_Bits" BASE="0x0" SIZE="0x0" desc="" visible="true">\r
<register name="SCSI_Out_Bits_CONTROL_REG" address="0x4000647C" bitWidth="8" desc="" />\r
</block>\r
+ <block name="timer_clock" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="Debug_Timer" BASE="0x0" SIZE="0x0" desc="" visible="true">\r
<block name="VirtualMux_2" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<register name="Debug_Timer_PERIOD" address="0x40004F04" bitWidth="16" desc="TMRx.PER0 - Assigned Period" />\r
<register name="Debug_Timer_COUNTER" address="0x40004F06" bitWidth="16" desc="TMRx.CNT_CMP0 - Current Down Counter Value" />\r
</block>\r
- <block name="SCSI_Out_Ctl" BASE="0x0" SIZE="0x0" desc="" visible="true">\r
- <register name="SCSI_Out_Ctl_CONTROL_REG" address="0x40006577" bitWidth="8" desc="" />\r
- </block>\r
- <block name="LED1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="scsiTarget" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="SCSI_Out_Mux" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="SD_MISO" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="SDCard" BASE="0x0" SIZE="0x0" desc="" visible="true">\r
<block name="VirtualMux_3" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="VirtualMux_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="BSPIM" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
</block>\r
+ <block name="Bootloadable_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="USBFS" BASE="0x0" SIZE="0x0" desc="USBFS" visible="true">\r
<block name="bus_reset" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="ep_0" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<register name="USBFS_EP_TYPE" address="0x4000608F" bitWidth="8" desc="Endpoint Type (IN/OUT) Indication" />\r
<register name="USBFS_USB_CLK_EN" address="0x4000609D" bitWidth="8" desc="USB Block Clock Enable Register" />\r
</block>\r
- <block name="SD_MISO" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="timer_clock" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="SD_RX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="SD_TX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="SD_TX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="SD_RX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="SCSI_RX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="SCSI_RX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="Debug_Timer_Interrupt" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="SD_TX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="SCSI_TX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="Debug_Timer_Interrupt" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="SD_RX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="SCSI_TX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="SD_CD" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="SD_Init_Clk" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="SD_DAT2" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="LED1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="SCSI_CTL_PHASE" BASE="0x0" SIZE="0x0" desc="" visible="true">\r
- <register name="SCSI_CTL_PHASE_CONTROL_REG" address="0x40006472" bitWidth="8" desc="" />\r
+ <register name="SCSI_CTL_PHASE_CONTROL_REG" address="0x40006475" bitWidth="8" desc="" />\r
</block>\r
<block name="SD_DAT1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="SCSI_In" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="OddParityGen_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="SD_DAT2" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="SCSI_Out_DBx" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="SCSI_In_DBx" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="SD_Clk_Ctl" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="SD_CD" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="SD_Data_Clk" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="SD_Clk_mux" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="OddParityGen_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="SCSI_CLK" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="SD_MOSI" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="SCSI_Out" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="SCSI_ATN" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="SCSI_RST" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="scsiTarget" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="SCSI_RST_ISR" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="SCSI_ATN" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="SCSI_Out" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="SCSI_In" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="SCSI_CLK" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="SD_CS" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="CFG_EEPROM" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="SD_MOSI" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="SD_SCK" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="SD_CS" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
</blockRegMap>
\ No newline at end of file
<CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFolder" version="2">\r
<CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtBaseContainer" version="1">\r
<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="SD_Init_Clk" persistent="">\r
-<Hidden v="False" />\r
+<Hidden v="True" />\r
</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>\r
<CyGuid_0820c2e7-528d-4137-9a08-97257b946089 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItemList" version="2">\r
<dependencies>\r
<CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFileGenerated" version="1">\r
<CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFile" version="3" xml_contents_version="1">\r
<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="SD_Init_Clk.c" persistent=".\Generated_Source\PSoC5\SD_Init_Clk.c">\r
-<Hidden v="False" />\r
+<Hidden v="True" />\r
</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>\r
<build_action v="ARM_C_FILE" />\r
<PropertyDeltas />\r
<CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFileGenerated" version="1">\r
<CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFile" version="3" xml_contents_version="1">\r
<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="SD_Init_Clk.h" persistent=".\Generated_Source\PSoC5\SD_Init_Clk.h">\r
-<Hidden v="False" />\r
+<Hidden v="True" />\r
</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>\r
<build_action v="NONE" />\r
<PropertyDeltas />\r
<CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFolder" version="2">\r
<CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtBaseContainer" version="1">\r
<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="SD_Clk_Ctl" persistent="">\r
-<Hidden v="False" />\r
+<Hidden v="True" />\r
</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>\r
<CyGuid_0820c2e7-528d-4137-9a08-97257b946089 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItemList" version="2">\r
<dependencies>\r
<CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFileGenerated" version="1">\r
<CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFile" version="3" xml_contents_version="1">\r
<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="SD_Clk_Ctl.c" persistent=".\Generated_Source\PSoC5\SD_Clk_Ctl.c">\r
-<Hidden v="False" />\r
+<Hidden v="True" />\r
</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>\r
<build_action v="ARM_C_FILE" />\r
<PropertyDeltas />\r
<CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFileGenerated" version="1">\r
<CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFile" version="3" xml_contents_version="1">\r
<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="SD_Clk_Ctl.h" persistent=".\Generated_Source\PSoC5\SD_Clk_Ctl.h">\r
-<Hidden v="False" />\r
+<Hidden v="True" />\r
</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>\r
<build_action v="NONE" />\r
<PropertyDeltas />\r
<addressUnitBits>8</addressUnitBits>\r
<width>32</width>\r
<peripherals>\r
+ <peripheral>\r
+ <name>SCSI_Out_Ctl</name>\r
+ <description>No description available</description>\r
+ <baseAddress>0x40006577</baseAddress>\r
+ <addressBlock>\r
+ <offset>0</offset>\r
+ <size>0x1</size>\r
+ <usage>registers</usage>\r
+ </addressBlock>\r
+ <registers>\r
+ <register>\r
+ <name>SCSI_Out_Ctl_CONTROL_REG</name>\r
+ <description>No description available</description>\r
+ <addressOffset>0x0</addressOffset>\r
+ <size>8</size>\r
+ <access>read-write</access>\r
+ <resetValue>0</resetValue>\r
+ <resetMask>0</resetMask>\r
+ </register>\r
+ </registers>\r
+ </peripheral>\r
<peripheral>\r
<name>SCSI_Out_Bits</name>\r
<description>No description available</description>\r
</register>\r
</registers>\r
</peripheral>\r
- <peripheral>\r
- <name>SCSI_Out_Ctl</name>\r
- <description>No description available</description>\r
- <baseAddress>0x40006577</baseAddress>\r
- <addressBlock>\r
- <offset>0</offset>\r
- <size>0x1</size>\r
- <usage>registers</usage>\r
- </addressBlock>\r
- <registers>\r
- <register>\r
- <name>SCSI_Out_Ctl_CONTROL_REG</name>\r
- <description>No description available</description>\r
- <addressOffset>0x0</addressOffset>\r
- <size>8</size>\r
- <access>read-write</access>\r
- <resetValue>0</resetValue>\r
- <resetMask>0</resetMask>\r
- </register>\r
- </registers>\r
- </peripheral>\r
<peripheral>\r
<name>USBFS</name>\r
<description>USBFS</description>\r
<peripheral>\r
<name>SCSI_CTL_PHASE</name>\r
<description>No description available</description>\r
- <baseAddress>0x40006472</baseAddress>\r
+ <baseAddress>0x40006475</baseAddress>\r
<addressBlock>\r
<offset>0</offset>\r
<size>0x1</size>\r
}\r
}\r
\r
+#ifdef MM_DEBUG\r
void debugPoll()\r
{\r
if (!usbReady)\r
debugPoll();\r
CyExitCriticalSection(savedIntrStatus); \r
}\r
+#endif\r
\r
void debugInit()\r
{\r
if (scsiDev.phase == DATA_IN &&\r
transfer.currentBlock != transfer.blocks)\r
{\r
+ scsiEnterPhase(DATA_IN);\r
+\r
int totalSDSectors = transfer.blocks * SDSectorsPerSCSISector();\r
uint32_t sdLBA = SCSISector2SD(transfer.lba);\r
int buffers = sizeof(scsiDev.data) / SD_SECTOR_SIZE;\r
else if (scsiDev.phase == DATA_OUT &&\r
transfer.currentBlock != transfer.blocks)\r
{\r
+ scsiEnterPhase(DATA_OUT);\r
+ \r
int totalSDSectors = transfer.blocks * SDSectorsPerSCSISector();\r
int buffers = sizeof(scsiDev.data) / SD_SECTOR_SIZE;\r
int prep = 0;\r
// Set this to true to log SCSI commands and status information via
// USB HID packets. The can be captured and viewed in wireshark.
// For windows users, capture using USBPcap http://desowin.org/usbpcap/
-#define MM_DEBUG 0
+//#define MM_DEBUG 1
+#undef MM_DEBUG
#include "geometry.h"
#include "sense.h"
\r
// Set the SPI clock for 400kHz transfers\r
// 25MHz / 400kHz approx factor of 63.\r
+ // The register contains (divider - 1)\r
uint16_t clkDiv25MHz = SD_Data_Clk_GetDividerRegister();\r
- SD_Data_Clk_SetDivider(clkDiv25MHz * 63);\r
+ SD_Data_Clk_SetDivider(((clkDiv25MHz + 1) * 63) - 1);\r
// Wait for the clock to settle.\r
CyDelayUs(1);\r
\r
projects / SCSI2SD.git / commitdiff