Fix for multiple devices on the scsi bus.

diff --git a/CHANGELOG b/CHANGELOG
index 02c01c5800b5d25afb43147258f84befca0f56d1..3bd01526226cae1146fae6931fdc946cd22b79b4 100644 (file)
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -1,3 +1,6 @@
+2018XXXX               4.8.1
+       - Fix bug when writing with multiple SCSI devices on the chain
+
 20180416               4.8
        - Fix Unit Serial Number inquiry page to use return configured serial number
        - Apple mode pages now only sent when in Apple mode.

diff --git a/software/SCSI2SD/src/config.c b/software/SCSI2SD/src/config.c
index 70948f7afec817dd61ed8ebef730afa95e88c71b..ce84013bac1279cf831c3b4e7872079685518fa6 100755 (executable)
--- a/software/SCSI2SD/src/config.c
+++ b/software/SCSI2SD/src/config.c
@@ -31,7 +31,7 @@
 \r
 #include <string.h>\r
 \r
-static const uint16_t FIRMWARE_VERSION = 0x0480;\r
+static const uint16_t FIRMWARE_VERSION = 0x0481;\r
 \r
 // 1 flash row\r
 static const uint8_t DEFAULT_CONFIG[256] =\r

diff --git a/software/SCSI2SD/src/disk.c b/software/SCSI2SD/src/disk.c
index b8251645664f8302257c4fb7e0d6ff8192786b27..b8f6c88cd608e4b77746747695cf5a569c6f3821 100755 (executable)
--- a/software/SCSI2SD/src/disk.c
+++ b/software/SCSI2SD/src/disk.c
@@ -637,6 +637,7 @@ void scsiDiskPoll()
                int i = 0;\r
                int scsiDisconnected = 0;\r
                int scsiComplete = 0;\r
+               int clearBSY = 0;\r
                uint32_t lastActivityTime = getTime_ms();\r
                int scsiActive = 0;\r
                int sdActive = 0;\r
@@ -757,16 +758,13 @@ void scsiDiskPoll()
                                scsiComplete = 1;\r
 \r
                                process_Status();\r
-                               process_MessageIn(); // Will go to BUS_FREE state\r
-\r
-                               // Try and prevent anyone else using the SCSI bus while we're not ready.\r
-                               SCSI_SetPin(SCSI_Out_BSY); \r
+                               clearBSY = process_MessageIn(0); // Will go to BUS_FREE state but keeps BSY asserted\r
                        }\r
                }\r
 \r
-               if (scsiComplete)\r
+               if (clearBSY)\r
                {\r
-                       SCSI_ClearPin(SCSI_Out_BSY);\r
+                       enter_BusFree();\r
                }\r
                while (\r
                        !scsiDev.resetFlag &&\r

diff --git a/software/SCSI2SD/src/scsi.c b/software/SCSI2SD/src/scsi.c
index 657868d35ce4b4db9e1c6ea58b356dcd73a80815..db378549251841572592e3608ad2e73e46c74688 100755 (executable)
--- a/software/SCSI2SD/src/scsi.c
+++ b/software/SCSI2SD/src/scsi.c
@@ -40,7 +40,6 @@ ScsiDevice scsiDev;
 \r
 static void enter_SelectionPhase(void);\r
 static void process_SelectionPhase(void);\r
-static void enter_BusFree(void);\r
 static void enter_MessageIn(uint8 message);\r
 static void enter_Status(uint8 status);\r
 static void enter_DataIn(int len);\r
@@ -50,7 +49,7 @@ static void process_Command(void);
 \r
 static void doReserveRelease(void);\r
 \r
-static void enter_BusFree()\r
+void enter_BusFree()\r
 {\r
        // This delay probably isn't needed for most SCSI hosts, but it won't\r
        // hurt either. It's possible some of the samplers needed this delay.\r
@@ -84,7 +83,7 @@ static void enter_MessageIn(uint8 message)
        scsiDev.phase = MESSAGE_IN;\r
 }\r
 \r
-void process_MessageIn()\r
+int process_MessageIn(int releaseBusFree)\r
 {\r
        scsiEnterPhase(MESSAGE_IN);\r
        scsiWriteByte(scsiDev.msgIn);\r
@@ -94,6 +93,7 @@ void process_MessageIn()
                // If there was a parity error, we go\r
                // back to MESSAGE_OUT first, get out parity error message, then come\r
                // back here.\r
+               return 0;\r
        }\r
        else if ((scsiDev.msgIn == MSG_LINKED_COMMAND_COMPLETE) ||\r
                (scsiDev.msgIn == MSG_LINKED_COMMAND_COMPLETE_WITH_FLAG))\r
@@ -107,10 +107,16 @@ void process_MessageIn()
                scsiDev.status = GOOD;\r
                transfer.blocks = 0;\r
                transfer.currentBlock = 0;\r
+               return 0;\r
        }\r
-       else /*if (scsiDev.msgIn == MSG_COMMAND_COMPLETE)*/\r
+       else if (releaseBusFree) /*if (scsiDev.msgIn == MSG_COMMAND_COMPLETE)*/\r
        {\r
                enter_BusFree();\r
+               return 1;\r
+       }\r
+       else\r
+       {\r
+               return 1;\r
        }\r
 }\r
 \r
@@ -1008,7 +1014,7 @@ void scsiPoll(void)
                }\r
                else\r
                {\r
-                       process_MessageIn();\r
+                       process_MessageIn(1);\r
                }\r
 \r
        break;\r

diff --git a/software/SCSI2SD/src/scsi.h b/software/SCSI2SD/src/scsi.h
index 63cc83f31982c966057e51585d336322688dd6df..d1a9f54c25e11391e0a7a14a69201209d25858ac 100755 (executable)
--- a/software/SCSI2SD/src/scsi.h
+++ b/software/SCSI2SD/src/scsi.h
@@ -159,7 +159,8 @@ typedef struct
 extern ScsiDevice scsiDev;
 
 void process_Status(void);
-void process_MessageIn(void);
+int process_MessageIn(int releaseBusFree);
+void enter_BusFree(void);
 
 void scsiInit(void);
 void scsiPoll(void);

diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CTL_PHASE.h b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CTL_PHASE.h
index f9748551151276e172401d2eb196b069693766d5..4db2bae2d67bc7f1f49cde9b264bf6df036ad2b0 100755 (executable)
--- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CTL_PHASE.h
+++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CTL_PHASE.h
@@ -17,7 +17,15 @@
 #if !defined(CY_CONTROL_REG_SCSI_CTL_PHASE_H) /* CY_CONTROL_REG_SCSI_CTL_PHASE_H */
 #define CY_CONTROL_REG_SCSI_CTL_PHASE_H
 
-#include "cytypes.h"
+#include "cyfitter.h"
+
+#if ((CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC3) || \
+     (CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC4) || \
+     (CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC5))
+    #include "cytypes.h"
+#else
+    #include "syslib/cy_syslib.h"
+#endif
 
     
 /***************************************

diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Filtered.h b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Filtered.h
index 87326f5b9c0558d53984d7d43565d6510ee5bdf8..c64ec62a4167a08ccbd95d16c2e4f9e19def34aa 100755 (executable)
--- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Filtered.h
+++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Filtered.h
@@ -17,8 +17,16 @@
 #if !defined(CY_STATUS_REG_SCSI_Filtered_H) /* CY_STATUS_REG_SCSI_Filtered_H */
 #define CY_STATUS_REG_SCSI_Filtered_H
 
-#include "cytypes.h"
-#include "CyLib.h"
+#include "cyfitter.h"
+
+#if ((CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC3) || \
+     (CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC4) || \
+     (CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC5))
+    #include "cytypes.h"
+    #include "CyLib.h"
+#else
+    #include "syslib/cy_syslib.h"
+#endif
 
     
 /***************************************

diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Glitch_Ctl.h b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Glitch_Ctl.h
index d6c0d240f3f5f6986309bf10cc36ae4e4b00bbf8..88e1557e06da80895969e4fbea60768f173f2201 100755 (executable)
--- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Glitch_Ctl.h
+++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Glitch_Ctl.h
@@ -17,7 +17,15 @@
 #if !defined(CY_CONTROL_REG_SCSI_Glitch_Ctl_H) /* CY_CONTROL_REG_SCSI_Glitch_Ctl_H */
 #define CY_CONTROL_REG_SCSI_Glitch_Ctl_H
 
-#include "cytypes.h"
+#include "cyfitter.h"
+
+#if ((CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC3) || \
+     (CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC4) || \
+     (CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC5))
+    #include "cytypes.h"
+#else
+    #include "syslib/cy_syslib.h"
+#endif
 
     
 /***************************************

diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Out_Bits.h b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Out_Bits.h
index 94ea62a85602fa1c20e5c7b7d654b1dab6b40546..1ada4ee13b054306079fe830d6e4caa3e98c29f1 100755 (executable)
--- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Out_Bits.h
+++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Out_Bits.h
@@ -17,7 +17,15 @@
 #if !defined(CY_CONTROL_REG_SCSI_Out_Bits_H) /* CY_CONTROL_REG_SCSI_Out_Bits_H */
 #define CY_CONTROL_REG_SCSI_Out_Bits_H
 
-#include "cytypes.h"
+#include "cyfitter.h"
+
+#if ((CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC3) || \
+     (CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC4) || \
+     (CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC5))
+    #include "cytypes.h"
+#else
+    #include "syslib/cy_syslib.h"
+#endif
 
     
 /***************************************

diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Out_Ctl.h b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Out_Ctl.h
index e473a95f80eddb25f8d1e881fadbebf320ef9918..725873f0df1b011ffe20f96c9ea6043f816fee3f 100755 (executable)
--- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Out_Ctl.h
+++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Out_Ctl.h
@@ -17,7 +17,15 @@
 #if !defined(CY_CONTROL_REG_SCSI_Out_Ctl_H) /* CY_CONTROL_REG_SCSI_Out_Ctl_H */
 #define CY_CONTROL_REG_SCSI_Out_Ctl_H
 
-#include "cytypes.h"
+#include "cyfitter.h"
+
+#if ((CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC3) || \
+     (CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC4) || \
+     (CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC5))
+    #include "cytypes.h"
+#else
+    #include "syslib/cy_syslib.h"
+#endif
 
     
 /***************************************

diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Parity_Error.h b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Parity_Error.h
index 532aff3b0a44489c7b4adbafe7bc145c33f05b20..de1ddc80b54289e90ed11265c478f24012072bc7 100755 (executable)
--- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Parity_Error.h
+++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Parity_Error.h
@@ -17,8 +17,16 @@
 #if !defined(CY_STATUS_REG_SCSI_Parity_Error_H) /* CY_STATUS_REG_SCSI_Parity_Error_H */
 #define CY_STATUS_REG_SCSI_Parity_Error_H
 
-#include "cytypes.h"
-#include "CyLib.h"
+#include "cyfitter.h"
+
+#if ((CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC3) || \
+     (CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC4) || \
+     (CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC5))
+    #include "cytypes.h"
+    #include "CyLib.h"
+#else
+    #include "syslib/cy_syslib.h"
+#endif
 
     
 /***************************************

diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SDCard.h b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SDCard.h
index 6d566df54e7b60e315edc09edf2db4645b781256..6a8ae5daf53c6c9d0b141e64d1a51ec480ea7eca 100755 (executable)
--- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SDCard.h
+++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SDCard.h
@@ -19,15 +19,9 @@
 #if !defined(CY_SPIM_SDCard_H)\r
 #define CY_SPIM_SDCard_H\r
 \r
-#include "cytypes.h"\r
 #include "cyfitter.h"\r
-#include "CyLib.h"\r
-\r
-/* Check to see if required defines such as CY_PSOC5A are available */\r
-/* They are defined starting with cy_boot v3.0 */\r
-#if !defined (CY_PSOC5A)\r
-    #error Component SPI_Master_v2_50 requires cy_boot v3.0 or later\r
-#endif /* (CY_PSOC5A) */\r
+#include "cytypes.h"\r
+#include "CyLib.h" /* For CyEnterCriticalSection() and CyExitCriticalSection() functions */\r
 \r
 \r
 /***************************************\r

diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevice.h b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevice.h
index e9a0eafadd5ee3adf47bf2703d6cf20567a0b8e6..160bd6a0f2d6f6d9d3beea5016670d623e140a77 100755 (executable)
--- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevice.h
+++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevice.h
@@ -1,14 +1,14 @@
 /*******************************************************************************\r
 * File Name: cydevice.h\r
 * OBSOLETE: Do not use this file. Use the _trm version instead.\r
-* PSoC Creator  4.0 Update 1\r
+* PSoC Creator  4.1\r
 *\r
 * Description:\r
 * This file provides all of the address values for the entire PSoC device.\r
 * This file is automatically generated by PSoC Creator.\r
 *\r
 ********************************************************************************\r
-* Copyright (c) 2007-2016 Cypress Semiconductor.  All rights reserved.\r
+* Copyright (c) 2007-2017 Cypress Semiconductor.  All rights reserved.\r
 * You may use this file only in accordance with the license, terms, conditions, \r
 * disclaimers, and limitations in the end user license agreement accompanying \r
 * the software package with which this file was provided.\r

diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevice_trm.h b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevice_trm.h
index b7f270a8da6ebc4a456d739d5811ec091eadb82a..bff26eda9c24eb333a05667c85ee5ee35d29f4b5 100755 (executable)
--- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevice_trm.h
+++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevice_trm.h
@@ -1,14 +1,14 @@
 /*******************************************************************************\r
 * File Name: cydevice_trm.h\r
 * \r
-* PSoC Creator  4.0 Update 1\r
+* PSoC Creator  4.1\r
 *\r
 * Description:\r
 * This file provides all of the address values for the entire PSoC device.\r
 * This file is automatically generated by PSoC Creator.\r
 *\r
 ********************************************************************************\r
-* Copyright (c) 2007-2016 Cypress Semiconductor.  All rights reserved.\r
+* Copyright (c) 2007-2017 Cypress Semiconductor.  All rights reserved.\r
 * You may use this file only in accordance with the license, terms, conditions, \r
 * disclaimers, and limitations in the end user license agreement accompanying \r
 * the software package with which this file was provided.\r

diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicegnu.inc b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicegnu.inc
index bacd4b70cd28cf30edf5f535c3a164268031dfae..5db8be3b4f2d5a57857b84a30e7b3cecfac6ef2f 100755 (executable)
--- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicegnu.inc
+++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicegnu.inc
@@ -1,14 +1,14 @@
 /*******************************************************************************\r
 * File Name: cydevicegnu.inc\r
 * OBSOLETE: Do not use this file. Use the _trm version instead.\r
-* PSoC Creator  4.0 Update 1\r
+* PSoC Creator  4.1\r
 *\r
 * Description:\r
 * This file provides all of the address values for the entire PSoC device.\r
 * This file is automatically generated by PSoC Creator.\r
 *\r
 ********************************************************************************\r
-* Copyright (c) 2007-2016 Cypress Semiconductor.  All rights reserved.\r
+* Copyright (c) 2007-2017 Cypress Semiconductor.  All rights reserved.\r
 * You may use this file only in accordance with the license, terms, conditions, \r
 * disclaimers, and limitations in the end user license agreement accompanying \r
 * the software package with which this file was provided.\r

diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicegnu_trm.inc b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicegnu_trm.inc
index 22e50615cd0cdc7ebe17b59c8d429ae0ac5346b4..e0ed758a0d60ac3b3aff6d4cac325a5729a9d25d 100755 (executable)
--- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicegnu_trm.inc
+++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicegnu_trm.inc
@@ -1,14 +1,14 @@
 /*******************************************************************************\r
 * File Name: cydevicegnu_trm.inc\r
 * \r
-* PSoC Creator  4.0 Update 1\r
+* PSoC Creator  4.1\r
 *\r
 * Description:\r
 * This file provides all of the address values for the entire PSoC device.\r
 * This file is automatically generated by PSoC Creator.\r
 *\r
 ********************************************************************************\r
-* Copyright (c) 2007-2016 Cypress Semiconductor.  All rights reserved.\r
+* Copyright (c) 2007-2017 Cypress Semiconductor.  All rights reserved.\r
 * You may use this file only in accordance with the license, terms, conditions, \r
 * disclaimers, and limitations in the end user license agreement accompanying \r
 * the software package with which this file was provided.\r

diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cydeviceiar.inc b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cydeviceiar.inc
index 019dd7c8a21483794027157430a7819012b4f5d1..6b49c4845bc4bce4984ecb7f91d5789cdeaf22bf 100755 (executable)
--- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cydeviceiar.inc
+++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cydeviceiar.inc
@@ -1,13 +1,13 @@
 ;\r
 ; File Name: cydeviceiar.inc\r
 ; OBSOLETE: Do not use this file. Use the _trm version instead.\r
-; PSoC Creator  4.0 Update 1\r
+; PSoC Creator  4.1\r
 ;\r
 ; Description:\r
 ; This file provides all of the address values for the entire PSoC device.\r
 ;\r
 ;-------------------------------------------------------------------------------\r
-; Copyright (c) 2007-2016 Cypress Semiconductor.  All rights reserved.\r
+; Copyright (c) 2007-2017 Cypress Semiconductor.  All rights reserved.\r
 ; You may use this file only in accordance with the license, terms, conditions, \r
 ; disclaimers, and limitations in the end user license agreement accompanying \r
 ; the software package with which this file was provided.\r

diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cydeviceiar_trm.inc b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cydeviceiar_trm.inc
index 0e2c8a3884422dc62a76eda285faa2d007286789..c7c07d0bddf32e70910d289f2fca9b055af2242f 100755 (executable)
--- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cydeviceiar_trm.inc
+++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cydeviceiar_trm.inc
@@ -1,13 +1,13 @@
 ;\r
 ; File Name: cydeviceiar_trm.inc\r
 ; \r
-; PSoC Creator  4.0 Update 1\r
+; PSoC Creator  4.1\r
 ;\r
 ; Description:\r
 ; This file provides all of the address values for the entire PSoC device.\r
 ;\r
 ;-------------------------------------------------------------------------------\r
-; Copyright (c) 2007-2016 Cypress Semiconductor.  All rights reserved.\r
+; Copyright (c) 2007-2017 Cypress Semiconductor.  All rights reserved.\r
 ; You may use this file only in accordance with the license, terms, conditions, \r
 ; disclaimers, and limitations in the end user license agreement accompanying \r
 ; the software package with which this file was provided.\r

diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicerv.inc b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicerv.inc
index 228aba9db62b0a572ee483d0cc4ef041edbcdd2c..e9f2b7879d09fa2de7cfe811674d43a2196e5275 100755 (executable)
--- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicerv.inc
+++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicerv.inc
@@ -1,13 +1,13 @@
 ;\r
 ; File Name: cydevicerv.inc\r
 ; OBSOLETE: Do not use this file. Use the _trm version instead.\r
-; PSoC Creator  4.0 Update 1\r
+; PSoC Creator  4.1\r
 ;\r
 ; Description:\r
 ; This file provides all of the address values for the entire PSoC device.\r
 ;\r
 ;-------------------------------------------------------------------------------\r
-; Copyright (c) 2007-2016 Cypress Semiconductor.  All rights reserved.\r
+; Copyright (c) 2007-2017 Cypress Semiconductor.  All rights reserved.\r
 ; You may use this file only in accordance with the license, terms, conditions, \r
 ; disclaimers, and limitations in the end user license agreement accompanying \r
 ; the software package with which this file was provided.\r

diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicerv_trm.inc b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicerv_trm.inc
index 473b655a82f5143440c2a2f4168bbcae2c6c2027..4a32cab37d619636c0e6e0654992509eba7646fa 100755 (executable)
--- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicerv_trm.inc
+++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicerv_trm.inc
@@ -1,13 +1,13 @@
 ;\r
 ; File Name: cydevicerv_trm.inc\r
 ; \r
-; PSoC Creator  4.0 Update 1\r
+; PSoC Creator  4.1\r
 ;\r
 ; Description:\r
 ; This file provides all of the address values for the entire PSoC device.\r
 ;\r
 ;-------------------------------------------------------------------------------\r
-; Copyright (c) 2007-2016 Cypress Semiconductor.  All rights reserved.\r
+; Copyright (c) 2007-2017 Cypress Semiconductor.  All rights reserved.\r
 ; You may use this file only in accordance with the license, terms, conditions, \r
 ; disclaimers, and limitations in the end user license agreement accompanying \r
 ; the software package with which this file was provided.\r

diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter.h b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter.h
index 81204e3759b75c91f0dc217e42782e7839f8261c..e5a6d7b05ce760f1fad47bcfeaded54376562a65 100755 (executable)
--- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter.h
+++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter.h
@@ -1,8 +1,52 @@
+/*******************************************************************************\r
+* File Name: cyfitter.h\r
+* \r
+* PSoC Creator  4.1\r
+*\r
+* Description:\r
+* \r
+* This file is automatically generated by PSoC Creator.\r
+*\r
+********************************************************************************\r
+* Copyright (c) 2007-2017 Cypress Semiconductor.  All rights reserved.\r
+* You may use this file only in accordance with the license, terms, conditions, \r
+* disclaimers, and limitations in the end user license agreement accompanying \r
+* the software package with which this file was provided.\r
+********************************************************************************/\r
+\r
 #ifndef INCLUDED_CYFITTER_H\r
 #define INCLUDED_CYFITTER_H\r
 #include "cydevice.h"\r
 #include "cydevice_trm.h"\r
 \r
+/* Debug_Timer_Interrupt */\r
+#define Debug_Timer_Interrupt__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
+#define Debug_Timer_Interrupt__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
+#define Debug_Timer_Interrupt__INTC_MASK 0x01u\r
+#define Debug_Timer_Interrupt__INTC_NUMBER 0u\r
+#define Debug_Timer_Interrupt__INTC_PRIOR_NUM 7u\r
+#define Debug_Timer_Interrupt__INTC_PRIOR_REG CYREG_NVIC_PRI_0\r
+#define Debug_Timer_Interrupt__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
+#define Debug_Timer_Interrupt__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
+\r
+/* Debug_Timer_TimerHW */\r
+#define Debug_Timer_TimerHW__CAP0 CYREG_TMR0_CAP0\r
+#define Debug_Timer_TimerHW__CAP1 CYREG_TMR0_CAP1\r
+#define Debug_Timer_TimerHW__CFG0 CYREG_TMR0_CFG0\r
+#define Debug_Timer_TimerHW__CFG1 CYREG_TMR0_CFG1\r
+#define Debug_Timer_TimerHW__CFG2 CYREG_TMR0_CFG2\r
+#define Debug_Timer_TimerHW__CNT_CMP0 CYREG_TMR0_CNT_CMP0\r
+#define Debug_Timer_TimerHW__CNT_CMP1 CYREG_TMR0_CNT_CMP1\r
+#define Debug_Timer_TimerHW__PER0 CYREG_TMR0_PER0\r
+#define Debug_Timer_TimerHW__PER1 CYREG_TMR0_PER1\r
+#define Debug_Timer_TimerHW__PM_ACT_CFG CYREG_PM_ACT_CFG3\r
+#define Debug_Timer_TimerHW__PM_ACT_MSK 0x01u\r
+#define Debug_Timer_TimerHW__PM_STBY_CFG CYREG_PM_STBY_CFG3\r
+#define Debug_Timer_TimerHW__PM_STBY_MSK 0x01u\r
+#define Debug_Timer_TimerHW__RT0 CYREG_TMR0_RT0\r
+#define Debug_Timer_TimerHW__RT1 CYREG_TMR0_RT1\r
+#define Debug_Timer_TimerHW__SR0 CYREG_TMR0_SR0\r
+\r
 /* LED1 */\r
 #define LED1__0__INTTYPE CYREG_PICU12_INTTYPE3\r
 #define LED1__0__MASK 0x08u\r
@@ -36,2463 +80,810 @@
 #define LED1__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ\r
 #define LED1__SLW CYREG_PRT12_SLW\r
 \r
-/* SD_CD */\r
-#define SD_CD__0__INTTYPE CYREG_PICU3_INTTYPE6\r
-#define SD_CD__0__MASK 0x40u\r
-#define SD_CD__0__PC CYREG_PRT3_PC6\r
-#define SD_CD__0__PORT 3u\r
-#define SD_CD__0__SHIFT 6u\r
-#define SD_CD__AG CYREG_PRT3_AG\r
-#define SD_CD__AMUX CYREG_PRT3_AMUX\r
-#define SD_CD__BIE CYREG_PRT3_BIE\r
-#define SD_CD__BIT_MASK CYREG_PRT3_BIT_MASK\r
-#define SD_CD__BYP CYREG_PRT3_BYP\r
-#define SD_CD__CTL CYREG_PRT3_CTL\r
-#define SD_CD__DM0 CYREG_PRT3_DM0\r
-#define SD_CD__DM1 CYREG_PRT3_DM1\r
-#define SD_CD__DM2 CYREG_PRT3_DM2\r
-#define SD_CD__DR CYREG_PRT3_DR\r
-#define SD_CD__INP_DIS CYREG_PRT3_INP_DIS\r
-#define SD_CD__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU3_BASE\r
-#define SD_CD__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG\r
-#define SD_CD__LCD_EN CYREG_PRT3_LCD_EN\r
-#define SD_CD__MASK 0x40u\r
-#define SD_CD__PORT 3u\r
-#define SD_CD__PRT CYREG_PRT3_PRT\r
-#define SD_CD__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL\r
-#define SD_CD__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN\r
-#define SD_CD__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0\r
-#define SD_CD__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1\r
-#define SD_CD__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0\r
-#define SD_CD__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1\r
-#define SD_CD__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT\r
-#define SD_CD__PS CYREG_PRT3_PS\r
-#define SD_CD__SHIFT 6u\r
-#define SD_CD__SLW CYREG_PRT3_SLW\r
-\r
-/* SD_CS */\r
-#define SD_CS__0__INTTYPE CYREG_PICU3_INTTYPE4\r
-#define SD_CS__0__MASK 0x10u\r
-#define SD_CS__0__PC CYREG_PRT3_PC4\r
-#define SD_CS__0__PORT 3u\r
-#define SD_CS__0__SHIFT 4u\r
-#define SD_CS__AG CYREG_PRT3_AG\r
-#define SD_CS__AMUX CYREG_PRT3_AMUX\r
-#define SD_CS__BIE CYREG_PRT3_BIE\r
-#define SD_CS__BIT_MASK CYREG_PRT3_BIT_MASK\r
-#define SD_CS__BYP CYREG_PRT3_BYP\r
-#define SD_CS__CTL CYREG_PRT3_CTL\r
-#define SD_CS__DM0 CYREG_PRT3_DM0\r
-#define SD_CS__DM1 CYREG_PRT3_DM1\r
-#define SD_CS__DM2 CYREG_PRT3_DM2\r
-#define SD_CS__DR CYREG_PRT3_DR\r
-#define SD_CS__INP_DIS CYREG_PRT3_INP_DIS\r
-#define SD_CS__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU3_BASE\r
-#define SD_CS__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG\r
-#define SD_CS__LCD_EN CYREG_PRT3_LCD_EN\r
-#define SD_CS__MASK 0x10u\r
-#define SD_CS__PORT 3u\r
-#define SD_CS__PRT CYREG_PRT3_PRT\r
-#define SD_CS__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL\r
-#define SD_CS__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN\r
-#define SD_CS__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0\r
-#define SD_CS__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1\r
-#define SD_CS__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0\r
-#define SD_CS__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1\r
-#define SD_CS__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT\r
-#define SD_CS__PS CYREG_PRT3_PS\r
-#define SD_CS__SHIFT 4u\r
-#define SD_CS__SLW CYREG_PRT3_SLW\r
-\r
-/* USBFS_arb_int */\r
-#define USBFS_arb_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
-#define USBFS_arb_int__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
-#define USBFS_arb_int__INTC_MASK 0x400000u\r
-#define USBFS_arb_int__INTC_NUMBER 22u\r
-#define USBFS_arb_int__INTC_PRIOR_NUM 6u\r
-#define USBFS_arb_int__INTC_PRIOR_REG CYREG_NVIC_PRI_22\r
-#define USBFS_arb_int__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
-#define USBFS_arb_int__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
+/* SCSI_CLK */\r
+#define SCSI_CLK__CFG0 CYREG_CLKDIST_DCFG1_CFG0\r
+#define SCSI_CLK__CFG1 CYREG_CLKDIST_DCFG1_CFG1\r
+#define SCSI_CLK__CFG2 CYREG_CLKDIST_DCFG1_CFG2\r
+#define SCSI_CLK__CFG2_SRC_SEL_MASK 0x07u\r
+#define SCSI_CLK__INDEX 0x01u\r
+#define SCSI_CLK__PM_ACT_CFG CYREG_PM_ACT_CFG2\r
+#define SCSI_CLK__PM_ACT_MSK 0x02u\r
+#define SCSI_CLK__PM_STBY_CFG CYREG_PM_STBY_CFG2\r
+#define SCSI_CLK__PM_STBY_MSK 0x02u\r
 \r
-/* USBFS_bus_reset */\r
-#define USBFS_bus_reset__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
-#define USBFS_bus_reset__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
-#define USBFS_bus_reset__INTC_MASK 0x800000u\r
-#define USBFS_bus_reset__INTC_NUMBER 23u\r
-#define USBFS_bus_reset__INTC_PRIOR_NUM 7u\r
-#define USBFS_bus_reset__INTC_PRIOR_REG CYREG_NVIC_PRI_23\r
-#define USBFS_bus_reset__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
-#define USBFS_bus_reset__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
+/* SCSI_CTL_PHASE */\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK 0x01u\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS 0\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK 0x02u\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS 1\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB05_06_ACTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB05_06_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB05_06_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB05_06_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB05_06_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB05_06_MSK\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB05_06_MSK\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB05_06_MSK\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB05_06_MSK\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK 0x04u\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS 2\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB05_ACTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB05_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB05_ST_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB05_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB05_ST_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK 0x07u\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB05_MSK\r
 \r
-/* USBFS_Dm */\r
-#define USBFS_Dm__0__INTTYPE CYREG_PICU15_INTTYPE7\r
-#define USBFS_Dm__0__MASK 0x80u\r
-#define USBFS_Dm__0__PC CYREG_IO_PC_PRT15_7_6_PC1\r
-#define USBFS_Dm__0__PORT 15u\r
-#define USBFS_Dm__0__SHIFT 7u\r
-#define USBFS_Dm__AG CYREG_PRT15_AG\r
-#define USBFS_Dm__AMUX CYREG_PRT15_AMUX\r
-#define USBFS_Dm__BIE CYREG_PRT15_BIE\r
-#define USBFS_Dm__BIT_MASK CYREG_PRT15_BIT_MASK\r
-#define USBFS_Dm__BYP CYREG_PRT15_BYP\r
-#define USBFS_Dm__CTL CYREG_PRT15_CTL\r
-#define USBFS_Dm__DM0 CYREG_PRT15_DM0\r
-#define USBFS_Dm__DM1 CYREG_PRT15_DM1\r
-#define USBFS_Dm__DM2 CYREG_PRT15_DM2\r
-#define USBFS_Dm__DR CYREG_PRT15_DR\r
-#define USBFS_Dm__INP_DIS CYREG_PRT15_INP_DIS\r
-#define USBFS_Dm__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU15_BASE\r
-#define USBFS_Dm__LCD_COM_SEG CYREG_PRT15_LCD_COM_SEG\r
-#define USBFS_Dm__LCD_EN CYREG_PRT15_LCD_EN\r
-#define USBFS_Dm__MASK 0x80u\r
-#define USBFS_Dm__PORT 15u\r
-#define USBFS_Dm__PRT CYREG_PRT15_PRT\r
-#define USBFS_Dm__PRTDSI__CAPS_SEL CYREG_PRT15_CAPS_SEL\r
-#define USBFS_Dm__PRTDSI__DBL_SYNC_IN CYREG_PRT15_DBL_SYNC_IN\r
-#define USBFS_Dm__PRTDSI__OE_SEL0 CYREG_PRT15_OE_SEL0\r
-#define USBFS_Dm__PRTDSI__OE_SEL1 CYREG_PRT15_OE_SEL1\r
-#define USBFS_Dm__PRTDSI__OUT_SEL0 CYREG_PRT15_OUT_SEL0\r
-#define USBFS_Dm__PRTDSI__OUT_SEL1 CYREG_PRT15_OUT_SEL1\r
-#define USBFS_Dm__PRTDSI__SYNC_OUT CYREG_PRT15_SYNC_OUT\r
-#define USBFS_Dm__PS CYREG_PRT15_PS\r
-#define USBFS_Dm__SHIFT 7u\r
-#define USBFS_Dm__SLW CYREG_PRT15_SLW\r
+/* SCSI_Filtered */\r
+#define SCSI_Filtered_sts_sts_reg__0__MASK 0x01u\r
+#define SCSI_Filtered_sts_sts_reg__0__POS 0\r
+#define SCSI_Filtered_sts_sts_reg__1__MASK 0x02u\r
+#define SCSI_Filtered_sts_sts_reg__1__POS 1\r
+#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB02_03_ACTL\r
+#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB02_03_ST\r
+#define SCSI_Filtered_sts_sts_reg__2__MASK 0x04u\r
+#define SCSI_Filtered_sts_sts_reg__2__POS 2\r
+#define SCSI_Filtered_sts_sts_reg__3__MASK 0x08u\r
+#define SCSI_Filtered_sts_sts_reg__3__POS 3\r
+#define SCSI_Filtered_sts_sts_reg__4__MASK 0x10u\r
+#define SCSI_Filtered_sts_sts_reg__4__POS 4\r
+#define SCSI_Filtered_sts_sts_reg__MASK 0x1Fu\r
+#define SCSI_Filtered_sts_sts_reg__MASK_REG CYREG_B0_UDB02_MSK\r
+#define SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB02_ACTL\r
+#define SCSI_Filtered_sts_sts_reg__STATUS_REG CYREG_B0_UDB02_ST\r
 \r
-/* USBFS_Dp */\r
-#define USBFS_Dp__0__INTTYPE CYREG_PICU15_INTTYPE6\r
-#define USBFS_Dp__0__MASK 0x40u\r
-#define USBFS_Dp__0__PC CYREG_IO_PC_PRT15_7_6_PC0\r
-#define USBFS_Dp__0__PORT 15u\r
-#define USBFS_Dp__0__SHIFT 6u\r
-#define USBFS_Dp__AG CYREG_PRT15_AG\r
-#define USBFS_Dp__AMUX CYREG_PRT15_AMUX\r
-#define USBFS_Dp__BIE CYREG_PRT15_BIE\r
-#define USBFS_Dp__BIT_MASK CYREG_PRT15_BIT_MASK\r
-#define USBFS_Dp__BYP CYREG_PRT15_BYP\r
-#define USBFS_Dp__CTL CYREG_PRT15_CTL\r
-#define USBFS_Dp__DM0 CYREG_PRT15_DM0\r
-#define USBFS_Dp__DM1 CYREG_PRT15_DM1\r
-#define USBFS_Dp__DM2 CYREG_PRT15_DM2\r
-#define USBFS_Dp__DR CYREG_PRT15_DR\r
-#define USBFS_Dp__INP_DIS CYREG_PRT15_INP_DIS\r
-#define USBFS_Dp__INTSTAT CYREG_PICU15_INTSTAT\r
-#define USBFS_Dp__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU15_BASE\r
-#define USBFS_Dp__LCD_COM_SEG CYREG_PRT15_LCD_COM_SEG\r
-#define USBFS_Dp__LCD_EN CYREG_PRT15_LCD_EN\r
-#define USBFS_Dp__MASK 0x40u\r
-#define USBFS_Dp__PORT 15u\r
-#define USBFS_Dp__PRT CYREG_PRT15_PRT\r
-#define USBFS_Dp__PRTDSI__CAPS_SEL CYREG_PRT15_CAPS_SEL\r
-#define USBFS_Dp__PRTDSI__DBL_SYNC_IN CYREG_PRT15_DBL_SYNC_IN\r
-#define USBFS_Dp__PRTDSI__OE_SEL0 CYREG_PRT15_OE_SEL0\r
-#define USBFS_Dp__PRTDSI__OE_SEL1 CYREG_PRT15_OE_SEL1\r
-#define USBFS_Dp__PRTDSI__OUT_SEL0 CYREG_PRT15_OUT_SEL0\r
-#define USBFS_Dp__PRTDSI__OUT_SEL1 CYREG_PRT15_OUT_SEL1\r
-#define USBFS_Dp__PRTDSI__SYNC_OUT CYREG_PRT15_SYNC_OUT\r
-#define USBFS_Dp__PS CYREG_PRT15_PS\r
-#define USBFS_Dp__SHIFT 6u\r
-#define USBFS_Dp__SLW CYREG_PRT15_SLW\r
-#define USBFS_Dp__SNAP CYREG_PICU_15_SNAP_15\r
+/* SCSI_Glitch_Ctl */\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK 0x01u\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS 0\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB07_08_ACTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB07_08_CTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB07_08_CTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB07_08_CTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB07_08_CTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB07_08_MSK\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB07_08_MSK\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB07_08_MSK\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB07_08_MSK\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB07_ACTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB07_CTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB07_ST_CTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB07_CTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB07_ST_CTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK 0x01u\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB07_MSK_ACTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB07_MSK_ACTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB07_MSK\r
 \r
-/* USBFS_dp_int */\r
-#define USBFS_dp_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
-#define USBFS_dp_int__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
-#define USBFS_dp_int__INTC_MASK 0x1000u\r
-#define USBFS_dp_int__INTC_NUMBER 12u\r
-#define USBFS_dp_int__INTC_PRIOR_NUM 7u\r
-#define USBFS_dp_int__INTC_PRIOR_REG CYREG_NVIC_PRI_12\r
-#define USBFS_dp_int__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
-#define USBFS_dp_int__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
-\r
-/* USBFS_ep_0 */\r
-#define USBFS_ep_0__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
-#define USBFS_ep_0__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
-#define USBFS_ep_0__INTC_MASK 0x1000000u\r
-#define USBFS_ep_0__INTC_NUMBER 24u\r
-#define USBFS_ep_0__INTC_PRIOR_NUM 7u\r
-#define USBFS_ep_0__INTC_PRIOR_REG CYREG_NVIC_PRI_24\r
-#define USBFS_ep_0__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
-#define USBFS_ep_0__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
-\r
-/* USBFS_ep_1 */\r
-#define USBFS_ep_1__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
-#define USBFS_ep_1__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
-#define USBFS_ep_1__INTC_MASK 0x80u\r
-#define USBFS_ep_1__INTC_NUMBER 7u\r
-#define USBFS_ep_1__INTC_PRIOR_NUM 7u\r
-#define USBFS_ep_1__INTC_PRIOR_REG CYREG_NVIC_PRI_7\r
-#define USBFS_ep_1__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
-#define USBFS_ep_1__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
-\r
-/* USBFS_ep_2 */\r
-#define USBFS_ep_2__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
-#define USBFS_ep_2__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
-#define USBFS_ep_2__INTC_MASK 0x100u\r
-#define USBFS_ep_2__INTC_NUMBER 8u\r
-#define USBFS_ep_2__INTC_PRIOR_NUM 7u\r
-#define USBFS_ep_2__INTC_PRIOR_REG CYREG_NVIC_PRI_8\r
-#define USBFS_ep_2__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
-#define USBFS_ep_2__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
-\r
-/* USBFS_ep_3 */\r
-#define USBFS_ep_3__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
-#define USBFS_ep_3__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
-#define USBFS_ep_3__INTC_MASK 0x200u\r
-#define USBFS_ep_3__INTC_NUMBER 9u\r
-#define USBFS_ep_3__INTC_PRIOR_NUM 7u\r
-#define USBFS_ep_3__INTC_PRIOR_REG CYREG_NVIC_PRI_9\r
-#define USBFS_ep_3__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
-#define USBFS_ep_3__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
-\r
-/* USBFS_ep_4 */\r
-#define USBFS_ep_4__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
-#define USBFS_ep_4__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
-#define USBFS_ep_4__INTC_MASK 0x400u\r
-#define USBFS_ep_4__INTC_NUMBER 10u\r
-#define USBFS_ep_4__INTC_PRIOR_NUM 7u\r
-#define USBFS_ep_4__INTC_PRIOR_REG CYREG_NVIC_PRI_10\r
-#define USBFS_ep_4__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
-#define USBFS_ep_4__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
-\r
-/* USBFS_sof_int */\r
-#define USBFS_sof_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
-#define USBFS_sof_int__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
-#define USBFS_sof_int__INTC_MASK 0x200000u\r
-#define USBFS_sof_int__INTC_NUMBER 21u\r
-#define USBFS_sof_int__INTC_PRIOR_NUM 7u\r
-#define USBFS_sof_int__INTC_PRIOR_REG CYREG_NVIC_PRI_21\r
-#define USBFS_sof_int__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
-#define USBFS_sof_int__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
-\r
-/* USBFS_USB */\r
-#define USBFS_USB__ARB_CFG CYREG_USB_ARB_CFG\r
-#define USBFS_USB__ARB_EP1_CFG CYREG_USB_ARB_EP1_CFG\r
-#define USBFS_USB__ARB_EP1_INT_EN CYREG_USB_ARB_EP1_INT_EN\r
-#define USBFS_USB__ARB_EP1_SR CYREG_USB_ARB_EP1_SR\r
-#define USBFS_USB__ARB_EP2_CFG CYREG_USB_ARB_EP2_CFG\r
-#define USBFS_USB__ARB_EP2_INT_EN CYREG_USB_ARB_EP2_INT_EN\r
-#define USBFS_USB__ARB_EP2_SR CYREG_USB_ARB_EP2_SR\r
-#define USBFS_USB__ARB_EP3_CFG CYREG_USB_ARB_EP3_CFG\r
-#define USBFS_USB__ARB_EP3_INT_EN CYREG_USB_ARB_EP3_INT_EN\r
-#define USBFS_USB__ARB_EP3_SR CYREG_USB_ARB_EP3_SR\r
-#define USBFS_USB__ARB_EP4_CFG CYREG_USB_ARB_EP4_CFG\r
-#define USBFS_USB__ARB_EP4_INT_EN CYREG_USB_ARB_EP4_INT_EN\r
-#define USBFS_USB__ARB_EP4_SR CYREG_USB_ARB_EP4_SR\r
-#define USBFS_USB__ARB_EP5_CFG CYREG_USB_ARB_EP5_CFG\r
-#define USBFS_USB__ARB_EP5_INT_EN CYREG_USB_ARB_EP5_INT_EN\r
-#define USBFS_USB__ARB_EP5_SR CYREG_USB_ARB_EP5_SR\r
-#define USBFS_USB__ARB_EP6_CFG CYREG_USB_ARB_EP6_CFG\r
-#define USBFS_USB__ARB_EP6_INT_EN CYREG_USB_ARB_EP6_INT_EN\r
-#define USBFS_USB__ARB_EP6_SR CYREG_USB_ARB_EP6_SR\r
-#define USBFS_USB__ARB_EP7_CFG CYREG_USB_ARB_EP7_CFG\r
-#define USBFS_USB__ARB_EP7_INT_EN CYREG_USB_ARB_EP7_INT_EN\r
-#define USBFS_USB__ARB_EP7_SR CYREG_USB_ARB_EP7_SR\r
-#define USBFS_USB__ARB_EP8_CFG CYREG_USB_ARB_EP8_CFG\r
-#define USBFS_USB__ARB_EP8_INT_EN CYREG_USB_ARB_EP8_INT_EN\r
-#define USBFS_USB__ARB_EP8_SR CYREG_USB_ARB_EP8_SR\r
-#define USBFS_USB__ARB_INT_EN CYREG_USB_ARB_INT_EN\r
-#define USBFS_USB__ARB_INT_SR CYREG_USB_ARB_INT_SR\r
-#define USBFS_USB__ARB_RW1_DR CYREG_USB_ARB_RW1_DR\r
-#define USBFS_USB__ARB_RW1_RA CYREG_USB_ARB_RW1_RA\r
-#define USBFS_USB__ARB_RW1_RA_MSB CYREG_USB_ARB_RW1_RA_MSB\r
-#define USBFS_USB__ARB_RW1_WA CYREG_USB_ARB_RW1_WA\r
-#define USBFS_USB__ARB_RW1_WA_MSB CYREG_USB_ARB_RW1_WA_MSB\r
-#define USBFS_USB__ARB_RW2_DR CYREG_USB_ARB_RW2_DR\r
-#define USBFS_USB__ARB_RW2_RA CYREG_USB_ARB_RW2_RA\r
-#define USBFS_USB__ARB_RW2_RA_MSB CYREG_USB_ARB_RW2_RA_MSB\r
-#define USBFS_USB__ARB_RW2_WA CYREG_USB_ARB_RW2_WA\r
-#define USBFS_USB__ARB_RW2_WA_MSB CYREG_USB_ARB_RW2_WA_MSB\r
-#define USBFS_USB__ARB_RW3_DR CYREG_USB_ARB_RW3_DR\r
-#define USBFS_USB__ARB_RW3_RA CYREG_USB_ARB_RW3_RA\r
-#define USBFS_USB__ARB_RW3_RA_MSB CYREG_USB_ARB_RW3_RA_MSB\r
-#define USBFS_USB__ARB_RW3_WA CYREG_USB_ARB_RW3_WA\r
-#define USBFS_USB__ARB_RW3_WA_MSB CYREG_USB_ARB_RW3_WA_MSB\r
-#define USBFS_USB__ARB_RW4_DR CYREG_USB_ARB_RW4_DR\r
-#define USBFS_USB__ARB_RW4_RA CYREG_USB_ARB_RW4_RA\r
-#define USBFS_USB__ARB_RW4_RA_MSB CYREG_USB_ARB_RW4_RA_MSB\r
-#define USBFS_USB__ARB_RW4_WA CYREG_USB_ARB_RW4_WA\r
-#define USBFS_USB__ARB_RW4_WA_MSB CYREG_USB_ARB_RW4_WA_MSB\r
-#define USBFS_USB__ARB_RW5_DR CYREG_USB_ARB_RW5_DR\r
-#define USBFS_USB__ARB_RW5_RA CYREG_USB_ARB_RW5_RA\r
-#define USBFS_USB__ARB_RW5_RA_MSB CYREG_USB_ARB_RW5_RA_MSB\r
-#define USBFS_USB__ARB_RW5_WA CYREG_USB_ARB_RW5_WA\r
-#define USBFS_USB__ARB_RW5_WA_MSB CYREG_USB_ARB_RW5_WA_MSB\r
-#define USBFS_USB__ARB_RW6_DR CYREG_USB_ARB_RW6_DR\r
-#define USBFS_USB__ARB_RW6_RA CYREG_USB_ARB_RW6_RA\r
-#define USBFS_USB__ARB_RW6_RA_MSB CYREG_USB_ARB_RW6_RA_MSB\r
-#define USBFS_USB__ARB_RW6_WA CYREG_USB_ARB_RW6_WA\r
-#define USBFS_USB__ARB_RW6_WA_MSB CYREG_USB_ARB_RW6_WA_MSB\r
-#define USBFS_USB__ARB_RW7_DR CYREG_USB_ARB_RW7_DR\r
-#define USBFS_USB__ARB_RW7_RA CYREG_USB_ARB_RW7_RA\r
-#define USBFS_USB__ARB_RW7_RA_MSB CYREG_USB_ARB_RW7_RA_MSB\r
-#define USBFS_USB__ARB_RW7_WA CYREG_USB_ARB_RW7_WA\r
-#define USBFS_USB__ARB_RW7_WA_MSB CYREG_USB_ARB_RW7_WA_MSB\r
-#define USBFS_USB__ARB_RW8_DR CYREG_USB_ARB_RW8_DR\r
-#define USBFS_USB__ARB_RW8_RA CYREG_USB_ARB_RW8_RA\r
-#define USBFS_USB__ARB_RW8_RA_MSB CYREG_USB_ARB_RW8_RA_MSB\r
-#define USBFS_USB__ARB_RW8_WA CYREG_USB_ARB_RW8_WA\r
-#define USBFS_USB__ARB_RW8_WA_MSB CYREG_USB_ARB_RW8_WA_MSB\r
-#define USBFS_USB__BUF_SIZE CYREG_USB_BUF_SIZE\r
-#define USBFS_USB__BUS_RST_CNT CYREG_USB_BUS_RST_CNT\r
-#define USBFS_USB__CR0 CYREG_USB_CR0\r
-#define USBFS_USB__CR1 CYREG_USB_CR1\r
-#define USBFS_USB__CWA CYREG_USB_CWA\r
-#define USBFS_USB__CWA_MSB CYREG_USB_CWA_MSB\r
-#define USBFS_USB__DMA_THRES CYREG_USB_DMA_THRES\r
-#define USBFS_USB__DMA_THRES_MSB CYREG_USB_DMA_THRES_MSB\r
-#define USBFS_USB__DYN_RECONFIG CYREG_USB_DYN_RECONFIG\r
-#define USBFS_USB__EP_ACTIVE CYREG_USB_EP_ACTIVE\r
-#define USBFS_USB__EP_TYPE CYREG_USB_EP_TYPE\r
-#define USBFS_USB__EP0_CNT CYREG_USB_EP0_CNT\r
-#define USBFS_USB__EP0_CR CYREG_USB_EP0_CR\r
-#define USBFS_USB__EP0_DR0 CYREG_USB_EP0_DR0\r
-#define USBFS_USB__EP0_DR1 CYREG_USB_EP0_DR1\r
-#define USBFS_USB__EP0_DR2 CYREG_USB_EP0_DR2\r
-#define USBFS_USB__EP0_DR3 CYREG_USB_EP0_DR3\r
-#define USBFS_USB__EP0_DR4 CYREG_USB_EP0_DR4\r
-#define USBFS_USB__EP0_DR5 CYREG_USB_EP0_DR5\r
-#define USBFS_USB__EP0_DR6 CYREG_USB_EP0_DR6\r
-#define USBFS_USB__EP0_DR7 CYREG_USB_EP0_DR7\r
-#define USBFS_USB__MEM_DATA CYREG_USB_MEM_DATA_MBASE\r
-#define USBFS_USB__PM_ACT_CFG CYREG_PM_ACT_CFG5\r
-#define USBFS_USB__PM_ACT_MSK 0x01u\r
-#define USBFS_USB__PM_STBY_CFG CYREG_PM_STBY_CFG5\r
-#define USBFS_USB__PM_STBY_MSK 0x01u\r
-#define USBFS_USB__SIE_EP_INT_EN CYREG_USB_SIE_EP_INT_EN\r
-#define USBFS_USB__SIE_EP_INT_SR CYREG_USB_SIE_EP_INT_SR\r
-#define USBFS_USB__SIE_EP1_CNT0 CYREG_USB_SIE_EP1_CNT0\r
-#define USBFS_USB__SIE_EP1_CNT1 CYREG_USB_SIE_EP1_CNT1\r
-#define USBFS_USB__SIE_EP1_CR0 CYREG_USB_SIE_EP1_CR0\r
-#define USBFS_USB__SIE_EP2_CNT0 CYREG_USB_SIE_EP2_CNT0\r
-#define USBFS_USB__SIE_EP2_CNT1 CYREG_USB_SIE_EP2_CNT1\r
-#define USBFS_USB__SIE_EP2_CR0 CYREG_USB_SIE_EP2_CR0\r
-#define USBFS_USB__SIE_EP3_CNT0 CYREG_USB_SIE_EP3_CNT0\r
-#define USBFS_USB__SIE_EP3_CNT1 CYREG_USB_SIE_EP3_CNT1\r
-#define USBFS_USB__SIE_EP3_CR0 CYREG_USB_SIE_EP3_CR0\r
-#define USBFS_USB__SIE_EP4_CNT0 CYREG_USB_SIE_EP4_CNT0\r
-#define USBFS_USB__SIE_EP4_CNT1 CYREG_USB_SIE_EP4_CNT1\r
-#define USBFS_USB__SIE_EP4_CR0 CYREG_USB_SIE_EP4_CR0\r
-#define USBFS_USB__SIE_EP5_CNT0 CYREG_USB_SIE_EP5_CNT0\r
-#define USBFS_USB__SIE_EP5_CNT1 CYREG_USB_SIE_EP5_CNT1\r
-#define USBFS_USB__SIE_EP5_CR0 CYREG_USB_SIE_EP5_CR0\r
-#define USBFS_USB__SIE_EP6_CNT0 CYREG_USB_SIE_EP6_CNT0\r
-#define USBFS_USB__SIE_EP6_CNT1 CYREG_USB_SIE_EP6_CNT1\r
-#define USBFS_USB__SIE_EP6_CR0 CYREG_USB_SIE_EP6_CR0\r
-#define USBFS_USB__SIE_EP7_CNT0 CYREG_USB_SIE_EP7_CNT0\r
-#define USBFS_USB__SIE_EP7_CNT1 CYREG_USB_SIE_EP7_CNT1\r
-#define USBFS_USB__SIE_EP7_CR0 CYREG_USB_SIE_EP7_CR0\r
-#define USBFS_USB__SIE_EP8_CNT0 CYREG_USB_SIE_EP8_CNT0\r
-#define USBFS_USB__SIE_EP8_CNT1 CYREG_USB_SIE_EP8_CNT1\r
-#define USBFS_USB__SIE_EP8_CR0 CYREG_USB_SIE_EP8_CR0\r
-#define USBFS_USB__SOF0 CYREG_USB_SOF0\r
-#define USBFS_USB__SOF1 CYREG_USB_SOF1\r
-#define USBFS_USB__USB_CLK_EN CYREG_USB_USB_CLK_EN\r
-#define USBFS_USB__USBIO_CR0 CYREG_USB_USBIO_CR0\r
-#define USBFS_USB__USBIO_CR1 CYREG_USB_USBIO_CR1\r
-\r
-/* SDCard_BSPIM */\r
-#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB04_05_ACTL\r
-#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB04_05_CTL\r
-#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB04_05_CTL\r
-#define SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB04_05_CTL\r
-#define SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B1_UDB04_05_CTL\r
-#define SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B1_UDB04_05_MSK\r
-#define SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B1_UDB04_05_MSK\r
-#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B1_UDB04_05_MSK\r
-#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB04_05_MSK\r
-#define SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B1_UDB04_ACTL\r
-#define SDCard_BSPIM_BitCounter__CONTROL_REG CYREG_B1_UDB04_CTL\r
-#define SDCard_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B1_UDB04_ST_CTL\r
-#define SDCard_BSPIM_BitCounter__COUNT_REG CYREG_B1_UDB04_CTL\r
-#define SDCard_BSPIM_BitCounter__COUNT_ST_REG CYREG_B1_UDB04_ST_CTL\r
-#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL\r
-#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL\r
-#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B1_UDB04_MSK\r
-#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB04_05_ACTL\r
-#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B1_UDB04_05_ST\r
-#define SDCard_BSPIM_BitCounter_ST__MASK_REG CYREG_B1_UDB04_MSK\r
-#define SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL\r
-#define SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL\r
-#define SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B1_UDB04_ACTL\r
-#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B1_UDB04_ST_CTL\r
-#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B1_UDB04_ST_CTL\r
-#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B1_UDB04_ST\r
-#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB08_09_ACTL\r
-#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B1_UDB08_09_ST\r
-#define SDCard_BSPIM_RxStsReg__4__MASK 0x10u\r
-#define SDCard_BSPIM_RxStsReg__4__POS 4\r
-#define SDCard_BSPIM_RxStsReg__5__MASK 0x20u\r
-#define SDCard_BSPIM_RxStsReg__5__POS 5\r
-#define SDCard_BSPIM_RxStsReg__6__MASK 0x40u\r
-#define SDCard_BSPIM_RxStsReg__6__POS 6\r
-#define SDCard_BSPIM_RxStsReg__MASK 0x70u\r
-#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B1_UDB08_MSK\r
-#define SDCard_BSPIM_RxStsReg__MASK_ST_AUX_CTL_REG CYREG_B1_UDB08_MSK_ACTL\r
-#define SDCard_BSPIM_RxStsReg__PER_ST_AUX_CTL_REG CYREG_B1_UDB08_MSK_ACTL\r
-#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB08_ACTL\r
-#define SDCard_BSPIM_RxStsReg__STATUS_CNT_REG CYREG_B1_UDB08_ST_CTL\r
-#define SDCard_BSPIM_RxStsReg__STATUS_CONTROL_REG CYREG_B1_UDB08_ST_CTL\r
-#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B1_UDB08_ST\r
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B1_UDB04_05_A0\r
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B1_UDB04_05_A1\r
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG CYREG_B1_UDB04_05_D0\r
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG CYREG_B1_UDB04_05_D1\r
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG CYREG_B1_UDB04_05_ACTL\r
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG CYREG_B1_UDB04_05_F0\r
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG CYREG_B1_UDB04_05_F1\r
-#define SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG CYREG_B1_UDB04_A0_A1\r
-#define SDCard_BSPIM_sR8_Dp_u0__A0_REG CYREG_B1_UDB04_A0\r
-#define SDCard_BSPIM_sR8_Dp_u0__A1_REG CYREG_B1_UDB04_A1\r
-#define SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG CYREG_B1_UDB04_D0_D1\r
-#define SDCard_BSPIM_sR8_Dp_u0__D0_REG CYREG_B1_UDB04_D0\r
-#define SDCard_BSPIM_sR8_Dp_u0__D1_REG CYREG_B1_UDB04_D1\r
-#define SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG CYREG_B1_UDB04_ACTL\r
-#define SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG CYREG_B1_UDB04_F0_F1\r
-#define SDCard_BSPIM_sR8_Dp_u0__F0_REG CYREG_B1_UDB04_F0\r
-#define SDCard_BSPIM_sR8_Dp_u0__F1_REG CYREG_B1_UDB04_F1\r
-#define SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL\r
-#define SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL\r
-#define SDCard_BSPIM_TxStsReg__0__MASK 0x01u\r
-#define SDCard_BSPIM_TxStsReg__0__POS 0\r
-#define SDCard_BSPIM_TxStsReg__1__MASK 0x02u\r
-#define SDCard_BSPIM_TxStsReg__1__POS 1\r
-#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB07_08_ACTL\r
-#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B1_UDB07_08_ST\r
-#define SDCard_BSPIM_TxStsReg__2__MASK 0x04u\r
-#define SDCard_BSPIM_TxStsReg__2__POS 2\r
-#define SDCard_BSPIM_TxStsReg__3__MASK 0x08u\r
-#define SDCard_BSPIM_TxStsReg__3__POS 3\r
-#define SDCard_BSPIM_TxStsReg__4__MASK 0x10u\r
-#define SDCard_BSPIM_TxStsReg__4__POS 4\r
-#define SDCard_BSPIM_TxStsReg__MASK 0x1Fu\r
-#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B1_UDB07_MSK\r
-#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB07_ACTL\r
-#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B1_UDB07_ST\r
-\r
-/* SD_SCK */\r
-#define SD_SCK__0__INTTYPE CYREG_PICU3_INTTYPE2\r
-#define SD_SCK__0__MASK 0x04u\r
-#define SD_SCK__0__PC CYREG_PRT3_PC2\r
-#define SD_SCK__0__PORT 3u\r
-#define SD_SCK__0__SHIFT 2u\r
-#define SD_SCK__AG CYREG_PRT3_AG\r
-#define SD_SCK__AMUX CYREG_PRT3_AMUX\r
-#define SD_SCK__BIE CYREG_PRT3_BIE\r
-#define SD_SCK__BIT_MASK CYREG_PRT3_BIT_MASK\r
-#define SD_SCK__BYP CYREG_PRT3_BYP\r
-#define SD_SCK__CTL CYREG_PRT3_CTL\r
-#define SD_SCK__DM0 CYREG_PRT3_DM0\r
-#define SD_SCK__DM1 CYREG_PRT3_DM1\r
-#define SD_SCK__DM2 CYREG_PRT3_DM2\r
-#define SD_SCK__DR CYREG_PRT3_DR\r
-#define SD_SCK__INP_DIS CYREG_PRT3_INP_DIS\r
-#define SD_SCK__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU3_BASE\r
-#define SD_SCK__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG\r
-#define SD_SCK__LCD_EN CYREG_PRT3_LCD_EN\r
-#define SD_SCK__MASK 0x04u\r
-#define SD_SCK__PORT 3u\r
-#define SD_SCK__PRT CYREG_PRT3_PRT\r
-#define SD_SCK__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL\r
-#define SD_SCK__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN\r
-#define SD_SCK__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0\r
-#define SD_SCK__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1\r
-#define SD_SCK__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0\r
-#define SD_SCK__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1\r
-#define SD_SCK__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT\r
-#define SD_SCK__PS CYREG_PRT3_PS\r
-#define SD_SCK__SHIFT 2u\r
-#define SD_SCK__SLW CYREG_PRT3_SLW\r
-\r
-/* SCSI_In */\r
-#define SCSI_In__0__AG CYREG_PRT2_AG\r
-#define SCSI_In__0__AMUX CYREG_PRT2_AMUX\r
-#define SCSI_In__0__BIE CYREG_PRT2_BIE\r
-#define SCSI_In__0__BIT_MASK CYREG_PRT2_BIT_MASK\r
-#define SCSI_In__0__BYP CYREG_PRT2_BYP\r
-#define SCSI_In__0__CTL CYREG_PRT2_CTL\r
-#define SCSI_In__0__DM0 CYREG_PRT2_DM0\r
-#define SCSI_In__0__DM1 CYREG_PRT2_DM1\r
-#define SCSI_In__0__DM2 CYREG_PRT2_DM2\r
-#define SCSI_In__0__DR CYREG_PRT2_DR\r
-#define SCSI_In__0__INP_DIS CYREG_PRT2_INP_DIS\r
-#define SCSI_In__0__INTTYPE CYREG_PICU2_INTTYPE0\r
-#define SCSI_In__0__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG\r
-#define SCSI_In__0__LCD_EN CYREG_PRT2_LCD_EN\r
-#define SCSI_In__0__MASK 0x01u\r
-#define SCSI_In__0__PC CYREG_PRT2_PC0\r
-#define SCSI_In__0__PORT 2u\r
-#define SCSI_In__0__PRT CYREG_PRT2_PRT\r
-#define SCSI_In__0__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL\r
-#define SCSI_In__0__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN\r
-#define SCSI_In__0__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0\r
-#define SCSI_In__0__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1\r
-#define SCSI_In__0__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0\r
-#define SCSI_In__0__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1\r
-#define SCSI_In__0__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT\r
-#define SCSI_In__0__PS CYREG_PRT2_PS\r
-#define SCSI_In__0__SHIFT 0u\r
-#define SCSI_In__0__SLW CYREG_PRT2_SLW\r
-#define SCSI_In__1__AG CYREG_PRT6_AG\r
-#define SCSI_In__1__AMUX CYREG_PRT6_AMUX\r
-#define SCSI_In__1__BIE CYREG_PRT6_BIE\r
-#define SCSI_In__1__BIT_MASK CYREG_PRT6_BIT_MASK\r
-#define SCSI_In__1__BYP CYREG_PRT6_BYP\r
-#define SCSI_In__1__CTL CYREG_PRT6_CTL\r
-#define SCSI_In__1__DM0 CYREG_PRT6_DM0\r
-#define SCSI_In__1__DM1 CYREG_PRT6_DM1\r
-#define SCSI_In__1__DM2 CYREG_PRT6_DM2\r
-#define SCSI_In__1__DR CYREG_PRT6_DR\r
-#define SCSI_In__1__INP_DIS CYREG_PRT6_INP_DIS\r
-#define SCSI_In__1__INTTYPE CYREG_PICU6_INTTYPE7\r
-#define SCSI_In__1__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
-#define SCSI_In__1__LCD_EN CYREG_PRT6_LCD_EN\r
-#define SCSI_In__1__MASK 0x80u\r
-#define SCSI_In__1__PC CYREG_PRT6_PC7\r
-#define SCSI_In__1__PORT 6u\r
-#define SCSI_In__1__PRT CYREG_PRT6_PRT\r
-#define SCSI_In__1__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
-#define SCSI_In__1__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
-#define SCSI_In__1__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
-#define SCSI_In__1__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
-#define SCSI_In__1__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
-#define SCSI_In__1__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
-#define SCSI_In__1__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
-#define SCSI_In__1__PS CYREG_PRT6_PS\r
-#define SCSI_In__1__SHIFT 7u\r
-#define SCSI_In__1__SLW CYREG_PRT6_SLW\r
-#define SCSI_In__2__AG CYREG_PRT5_AG\r
-#define SCSI_In__2__AMUX CYREG_PRT5_AMUX\r
-#define SCSI_In__2__BIE CYREG_PRT5_BIE\r
-#define SCSI_In__2__BIT_MASK CYREG_PRT5_BIT_MASK\r
-#define SCSI_In__2__BYP CYREG_PRT5_BYP\r
-#define SCSI_In__2__CTL CYREG_PRT5_CTL\r
-#define SCSI_In__2__DM0 CYREG_PRT5_DM0\r
-#define SCSI_In__2__DM1 CYREG_PRT5_DM1\r
-#define SCSI_In__2__DM2 CYREG_PRT5_DM2\r
-#define SCSI_In__2__DR CYREG_PRT5_DR\r
-#define SCSI_In__2__INP_DIS CYREG_PRT5_INP_DIS\r
-#define SCSI_In__2__INTTYPE CYREG_PICU5_INTTYPE1\r
-#define SCSI_In__2__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG\r
-#define SCSI_In__2__LCD_EN CYREG_PRT5_LCD_EN\r
-#define SCSI_In__2__MASK 0x02u\r
-#define SCSI_In__2__PC CYREG_PRT5_PC1\r
-#define SCSI_In__2__PORT 5u\r
-#define SCSI_In__2__PRT CYREG_PRT5_PRT\r
-#define SCSI_In__2__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL\r
-#define SCSI_In__2__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN\r
-#define SCSI_In__2__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0\r
-#define SCSI_In__2__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1\r
-#define SCSI_In__2__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0\r
-#define SCSI_In__2__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1\r
-#define SCSI_In__2__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT\r
-#define SCSI_In__2__PS CYREG_PRT5_PS\r
-#define SCSI_In__2__SHIFT 1u\r
-#define SCSI_In__2__SLW CYREG_PRT5_SLW\r
-#define SCSI_In__3__AG CYREG_PRT5_AG\r
-#define SCSI_In__3__AMUX CYREG_PRT5_AMUX\r
-#define SCSI_In__3__BIE CYREG_PRT5_BIE\r
-#define SCSI_In__3__BIT_MASK CYREG_PRT5_BIT_MASK\r
-#define SCSI_In__3__BYP CYREG_PRT5_BYP\r
-#define SCSI_In__3__CTL CYREG_PRT5_CTL\r
-#define SCSI_In__3__DM0 CYREG_PRT5_DM0\r
-#define SCSI_In__3__DM1 CYREG_PRT5_DM1\r
-#define SCSI_In__3__DM2 CYREG_PRT5_DM2\r
-#define SCSI_In__3__DR CYREG_PRT5_DR\r
-#define SCSI_In__3__INP_DIS CYREG_PRT5_INP_DIS\r
-#define SCSI_In__3__INTTYPE CYREG_PICU5_INTTYPE2\r
-#define SCSI_In__3__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG\r
-#define SCSI_In__3__LCD_EN CYREG_PRT5_LCD_EN\r
-#define SCSI_In__3__MASK 0x04u\r
-#define SCSI_In__3__PC CYREG_PRT5_PC2\r
-#define SCSI_In__3__PORT 5u\r
-#define SCSI_In__3__PRT CYREG_PRT5_PRT\r
-#define SCSI_In__3__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL\r
-#define SCSI_In__3__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN\r
-#define SCSI_In__3__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0\r
-#define SCSI_In__3__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1\r
-#define SCSI_In__3__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0\r
-#define SCSI_In__3__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1\r
-#define SCSI_In__3__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT\r
-#define SCSI_In__3__PS CYREG_PRT5_PS\r
-#define SCSI_In__3__SHIFT 2u\r
-#define SCSI_In__3__SLW CYREG_PRT5_SLW\r
-#define SCSI_In__4__AG CYREG_PRT5_AG\r
-#define SCSI_In__4__AMUX CYREG_PRT5_AMUX\r
-#define SCSI_In__4__BIE CYREG_PRT5_BIE\r
-#define SCSI_In__4__BIT_MASK CYREG_PRT5_BIT_MASK\r
-#define SCSI_In__4__BYP CYREG_PRT5_BYP\r
-#define SCSI_In__4__CTL CYREG_PRT5_CTL\r
-#define SCSI_In__4__DM0 CYREG_PRT5_DM0\r
-#define SCSI_In__4__DM1 CYREG_PRT5_DM1\r
-#define SCSI_In__4__DM2 CYREG_PRT5_DM2\r
-#define SCSI_In__4__DR CYREG_PRT5_DR\r
-#define SCSI_In__4__INP_DIS CYREG_PRT5_INP_DIS\r
-#define SCSI_In__4__INTTYPE CYREG_PICU5_INTTYPE3\r
-#define SCSI_In__4__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG\r
-#define SCSI_In__4__LCD_EN CYREG_PRT5_LCD_EN\r
-#define SCSI_In__4__MASK 0x08u\r
-#define SCSI_In__4__PC CYREG_PRT5_PC3\r
-#define SCSI_In__4__PORT 5u\r
-#define SCSI_In__4__PRT CYREG_PRT5_PRT\r
-#define SCSI_In__4__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL\r
-#define SCSI_In__4__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN\r
-#define SCSI_In__4__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0\r
-#define SCSI_In__4__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1\r
-#define SCSI_In__4__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0\r
-#define SCSI_In__4__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1\r
-#define SCSI_In__4__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT\r
-#define SCSI_In__4__PS CYREG_PRT5_PS\r
-#define SCSI_In__4__SHIFT 3u\r
-#define SCSI_In__4__SLW CYREG_PRT5_SLW\r
-#define SCSI_In__CD__AG CYREG_PRT5_AG\r
-#define SCSI_In__CD__AMUX CYREG_PRT5_AMUX\r
-#define SCSI_In__CD__BIE CYREG_PRT5_BIE\r
-#define SCSI_In__CD__BIT_MASK CYREG_PRT5_BIT_MASK\r
-#define SCSI_In__CD__BYP CYREG_PRT5_BYP\r
-#define SCSI_In__CD__CTL CYREG_PRT5_CTL\r
-#define SCSI_In__CD__DM0 CYREG_PRT5_DM0\r
-#define SCSI_In__CD__DM1 CYREG_PRT5_DM1\r
-#define SCSI_In__CD__DM2 CYREG_PRT5_DM2\r
-#define SCSI_In__CD__DR CYREG_PRT5_DR\r
-#define SCSI_In__CD__INP_DIS CYREG_PRT5_INP_DIS\r
-#define SCSI_In__CD__INTTYPE CYREG_PICU5_INTTYPE1\r
-#define SCSI_In__CD__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG\r
-#define SCSI_In__CD__LCD_EN CYREG_PRT5_LCD_EN\r
-#define SCSI_In__CD__MASK 0x02u\r
-#define SCSI_In__CD__PC CYREG_PRT5_PC1\r
-#define SCSI_In__CD__PORT 5u\r
-#define SCSI_In__CD__PRT CYREG_PRT5_PRT\r
-#define SCSI_In__CD__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL\r
-#define SCSI_In__CD__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN\r
-#define SCSI_In__CD__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0\r
-#define SCSI_In__CD__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1\r
-#define SCSI_In__CD__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0\r
-#define SCSI_In__CD__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1\r
-#define SCSI_In__CD__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT\r
-#define SCSI_In__CD__PS CYREG_PRT5_PS\r
-#define SCSI_In__CD__SHIFT 1u\r
-#define SCSI_In__CD__SLW CYREG_PRT5_SLW\r
-#define SCSI_In__DBP__AG CYREG_PRT2_AG\r
-#define SCSI_In__DBP__AMUX CYREG_PRT2_AMUX\r
-#define SCSI_In__DBP__BIE CYREG_PRT2_BIE\r
-#define SCSI_In__DBP__BIT_MASK CYREG_PRT2_BIT_MASK\r
-#define SCSI_In__DBP__BYP CYREG_PRT2_BYP\r
-#define SCSI_In__DBP__CTL CYREG_PRT2_CTL\r
-#define SCSI_In__DBP__DM0 CYREG_PRT2_DM0\r
-#define SCSI_In__DBP__DM1 CYREG_PRT2_DM1\r
-#define SCSI_In__DBP__DM2 CYREG_PRT2_DM2\r
-#define SCSI_In__DBP__DR CYREG_PRT2_DR\r
-#define SCSI_In__DBP__INP_DIS CYREG_PRT2_INP_DIS\r
-#define SCSI_In__DBP__INTTYPE CYREG_PICU2_INTTYPE0\r
-#define SCSI_In__DBP__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG\r
-#define SCSI_In__DBP__LCD_EN CYREG_PRT2_LCD_EN\r
-#define SCSI_In__DBP__MASK 0x01u\r
-#define SCSI_In__DBP__PC CYREG_PRT2_PC0\r
-#define SCSI_In__DBP__PORT 2u\r
-#define SCSI_In__DBP__PRT CYREG_PRT2_PRT\r
-#define SCSI_In__DBP__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL\r
-#define SCSI_In__DBP__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN\r
-#define SCSI_In__DBP__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0\r
-#define SCSI_In__DBP__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1\r
-#define SCSI_In__DBP__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0\r
-#define SCSI_In__DBP__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1\r
-#define SCSI_In__DBP__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT\r
-#define SCSI_In__DBP__PS CYREG_PRT2_PS\r
-#define SCSI_In__DBP__SHIFT 0u\r
-#define SCSI_In__DBP__SLW CYREG_PRT2_SLW\r
-#define SCSI_In__IO__AG CYREG_PRT5_AG\r
-#define SCSI_In__IO__AMUX CYREG_PRT5_AMUX\r
-#define SCSI_In__IO__BIE CYREG_PRT5_BIE\r
-#define SCSI_In__IO__BIT_MASK CYREG_PRT5_BIT_MASK\r
-#define SCSI_In__IO__BYP CYREG_PRT5_BYP\r
-#define SCSI_In__IO__CTL CYREG_PRT5_CTL\r
-#define SCSI_In__IO__DM0 CYREG_PRT5_DM0\r
-#define SCSI_In__IO__DM1 CYREG_PRT5_DM1\r
-#define SCSI_In__IO__DM2 CYREG_PRT5_DM2\r
-#define SCSI_In__IO__DR CYREG_PRT5_DR\r
-#define SCSI_In__IO__INP_DIS CYREG_PRT5_INP_DIS\r
-#define SCSI_In__IO__INTTYPE CYREG_PICU5_INTTYPE3\r
-#define SCSI_In__IO__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG\r
-#define SCSI_In__IO__LCD_EN CYREG_PRT5_LCD_EN\r
-#define SCSI_In__IO__MASK 0x08u\r
-#define SCSI_In__IO__PC CYREG_PRT5_PC3\r
-#define SCSI_In__IO__PORT 5u\r
-#define SCSI_In__IO__PRT CYREG_PRT5_PRT\r
-#define SCSI_In__IO__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL\r
-#define SCSI_In__IO__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN\r
-#define SCSI_In__IO__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0\r
-#define SCSI_In__IO__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1\r
-#define SCSI_In__IO__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0\r
-#define SCSI_In__IO__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1\r
-#define SCSI_In__IO__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT\r
-#define SCSI_In__IO__PS CYREG_PRT5_PS\r
-#define SCSI_In__IO__SHIFT 3u\r
-#define SCSI_In__IO__SLW CYREG_PRT5_SLW\r
-#define SCSI_In__MSG__AG CYREG_PRT6_AG\r
-#define SCSI_In__MSG__AMUX CYREG_PRT6_AMUX\r
-#define SCSI_In__MSG__BIE CYREG_PRT6_BIE\r
-#define SCSI_In__MSG__BIT_MASK CYREG_PRT6_BIT_MASK\r
-#define SCSI_In__MSG__BYP CYREG_PRT6_BYP\r
-#define SCSI_In__MSG__CTL CYREG_PRT6_CTL\r
-#define SCSI_In__MSG__DM0 CYREG_PRT6_DM0\r
-#define SCSI_In__MSG__DM1 CYREG_PRT6_DM1\r
-#define SCSI_In__MSG__DM2 CYREG_PRT6_DM2\r
-#define SCSI_In__MSG__DR CYREG_PRT6_DR\r
-#define SCSI_In__MSG__INP_DIS CYREG_PRT6_INP_DIS\r
-#define SCSI_In__MSG__INTTYPE CYREG_PICU6_INTTYPE7\r
-#define SCSI_In__MSG__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
-#define SCSI_In__MSG__LCD_EN CYREG_PRT6_LCD_EN\r
-#define SCSI_In__MSG__MASK 0x80u\r
-#define SCSI_In__MSG__PC CYREG_PRT6_PC7\r
-#define SCSI_In__MSG__PORT 6u\r
-#define SCSI_In__MSG__PRT CYREG_PRT6_PRT\r
-#define SCSI_In__MSG__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
-#define SCSI_In__MSG__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
-#define SCSI_In__MSG__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
-#define SCSI_In__MSG__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
-#define SCSI_In__MSG__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
-#define SCSI_In__MSG__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
-#define SCSI_In__MSG__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
-#define SCSI_In__MSG__PS CYREG_PRT6_PS\r
-#define SCSI_In__MSG__SHIFT 7u\r
-#define SCSI_In__MSG__SLW CYREG_PRT6_SLW\r
-#define SCSI_In__REQ__AG CYREG_PRT5_AG\r
-#define SCSI_In__REQ__AMUX CYREG_PRT5_AMUX\r
-#define SCSI_In__REQ__BIE CYREG_PRT5_BIE\r
-#define SCSI_In__REQ__BIT_MASK CYREG_PRT5_BIT_MASK\r
-#define SCSI_In__REQ__BYP CYREG_PRT5_BYP\r
-#define SCSI_In__REQ__CTL CYREG_PRT5_CTL\r
-#define SCSI_In__REQ__DM0 CYREG_PRT5_DM0\r
-#define SCSI_In__REQ__DM1 CYREG_PRT5_DM1\r
-#define SCSI_In__REQ__DM2 CYREG_PRT5_DM2\r
-#define SCSI_In__REQ__DR CYREG_PRT5_DR\r
-#define SCSI_In__REQ__INP_DIS CYREG_PRT5_INP_DIS\r
-#define SCSI_In__REQ__INTTYPE CYREG_PICU5_INTTYPE2\r
-#define SCSI_In__REQ__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG\r
-#define SCSI_In__REQ__LCD_EN CYREG_PRT5_LCD_EN\r
-#define SCSI_In__REQ__MASK 0x04u\r
-#define SCSI_In__REQ__PC CYREG_PRT5_PC2\r
-#define SCSI_In__REQ__PORT 5u\r
-#define SCSI_In__REQ__PRT CYREG_PRT5_PRT\r
-#define SCSI_In__REQ__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL\r
-#define SCSI_In__REQ__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN\r
-#define SCSI_In__REQ__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0\r
-#define SCSI_In__REQ__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1\r
-#define SCSI_In__REQ__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0\r
-#define SCSI_In__REQ__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1\r
-#define SCSI_In__REQ__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT\r
-#define SCSI_In__REQ__PS CYREG_PRT5_PS\r
-#define SCSI_In__REQ__SHIFT 2u\r
-#define SCSI_In__REQ__SLW CYREG_PRT5_SLW\r
-\r
-/* SCSI_In_DBx */\r
-#define SCSI_In_DBx__0__AG CYREG_PRT12_AG\r
-#define SCSI_In_DBx__0__BIE CYREG_PRT12_BIE\r
-#define SCSI_In_DBx__0__BIT_MASK CYREG_PRT12_BIT_MASK\r
-#define SCSI_In_DBx__0__BYP CYREG_PRT12_BYP\r
-#define SCSI_In_DBx__0__DM0 CYREG_PRT12_DM0\r
-#define SCSI_In_DBx__0__DM1 CYREG_PRT12_DM1\r
-#define SCSI_In_DBx__0__DM2 CYREG_PRT12_DM2\r
-#define SCSI_In_DBx__0__DR CYREG_PRT12_DR\r
-#define SCSI_In_DBx__0__INP_DIS CYREG_PRT12_INP_DIS\r
-#define SCSI_In_DBx__0__INTTYPE CYREG_PICU12_INTTYPE4\r
-#define SCSI_In_DBx__0__MASK 0x10u\r
-#define SCSI_In_DBx__0__PC CYREG_PRT12_PC4\r
-#define SCSI_In_DBx__0__PORT 12u\r
-#define SCSI_In_DBx__0__PRT CYREG_PRT12_PRT\r
-#define SCSI_In_DBx__0__PRTDSI__DBL_SYNC_IN CYREG_PRT12_DBL_SYNC_IN\r
-#define SCSI_In_DBx__0__PRTDSI__OE_SEL0 CYREG_PRT12_OE_SEL0\r
-#define SCSI_In_DBx__0__PRTDSI__OE_SEL1 CYREG_PRT12_OE_SEL1\r
-#define SCSI_In_DBx__0__PRTDSI__OUT_SEL0 CYREG_PRT12_OUT_SEL0\r
-#define SCSI_In_DBx__0__PRTDSI__OUT_SEL1 CYREG_PRT12_OUT_SEL1\r
-#define SCSI_In_DBx__0__PRTDSI__SYNC_OUT CYREG_PRT12_SYNC_OUT\r
-#define SCSI_In_DBx__0__PS CYREG_PRT12_PS\r
-#define SCSI_In_DBx__0__SHIFT 4u\r
-#define SCSI_In_DBx__0__SIO_CFG CYREG_PRT12_SIO_CFG\r
-#define SCSI_In_DBx__0__SIO_DIFF CYREG_PRT12_SIO_DIFF\r
-#define SCSI_In_DBx__0__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN\r
-#define SCSI_In_DBx__0__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ\r
-#define SCSI_In_DBx__0__SLW CYREG_PRT12_SLW\r
-#define SCSI_In_DBx__1__AG CYREG_PRT2_AG\r
-#define SCSI_In_DBx__1__AMUX CYREG_PRT2_AMUX\r
-#define SCSI_In_DBx__1__BIE CYREG_PRT2_BIE\r
-#define SCSI_In_DBx__1__BIT_MASK CYREG_PRT2_BIT_MASK\r
-#define SCSI_In_DBx__1__BYP CYREG_PRT2_BYP\r
-#define SCSI_In_DBx__1__CTL CYREG_PRT2_CTL\r
-#define SCSI_In_DBx__1__DM0 CYREG_PRT2_DM0\r
-#define SCSI_In_DBx__1__DM1 CYREG_PRT2_DM1\r
-#define SCSI_In_DBx__1__DM2 CYREG_PRT2_DM2\r
-#define SCSI_In_DBx__1__DR CYREG_PRT2_DR\r
-#define SCSI_In_DBx__1__INP_DIS CYREG_PRT2_INP_DIS\r
-#define SCSI_In_DBx__1__INTTYPE CYREG_PICU2_INTTYPE7\r
-#define SCSI_In_DBx__1__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG\r
-#define SCSI_In_DBx__1__LCD_EN CYREG_PRT2_LCD_EN\r
-#define SCSI_In_DBx__1__MASK 0x80u\r
-#define SCSI_In_DBx__1__PC CYREG_PRT2_PC7\r
-#define SCSI_In_DBx__1__PORT 2u\r
-#define SCSI_In_DBx__1__PRT CYREG_PRT2_PRT\r
-#define SCSI_In_DBx__1__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL\r
-#define SCSI_In_DBx__1__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN\r
-#define SCSI_In_DBx__1__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0\r
-#define SCSI_In_DBx__1__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1\r
-#define SCSI_In_DBx__1__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0\r
-#define SCSI_In_DBx__1__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1\r
-#define SCSI_In_DBx__1__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT\r
-#define SCSI_In_DBx__1__PS CYREG_PRT2_PS\r
-#define SCSI_In_DBx__1__SHIFT 7u\r
-#define SCSI_In_DBx__1__SLW CYREG_PRT2_SLW\r
-#define SCSI_In_DBx__2__AG CYREG_PRT2_AG\r
-#define SCSI_In_DBx__2__AMUX CYREG_PRT2_AMUX\r
-#define SCSI_In_DBx__2__BIE CYREG_PRT2_BIE\r
-#define SCSI_In_DBx__2__BIT_MASK CYREG_PRT2_BIT_MASK\r
-#define SCSI_In_DBx__2__BYP CYREG_PRT2_BYP\r
-#define SCSI_In_DBx__2__CTL CYREG_PRT2_CTL\r
-#define SCSI_In_DBx__2__DM0 CYREG_PRT2_DM0\r
-#define SCSI_In_DBx__2__DM1 CYREG_PRT2_DM1\r
-#define SCSI_In_DBx__2__DM2 CYREG_PRT2_DM2\r
-#define SCSI_In_DBx__2__DR CYREG_PRT2_DR\r
-#define SCSI_In_DBx__2__INP_DIS CYREG_PRT2_INP_DIS\r
-#define SCSI_In_DBx__2__INTTYPE CYREG_PICU2_INTTYPE6\r
-#define SCSI_In_DBx__2__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG\r
-#define SCSI_In_DBx__2__LCD_EN CYREG_PRT2_LCD_EN\r
-#define SCSI_In_DBx__2__MASK 0x40u\r
-#define SCSI_In_DBx__2__PC CYREG_PRT2_PC6\r
-#define SCSI_In_DBx__2__PORT 2u\r
-#define SCSI_In_DBx__2__PRT CYREG_PRT2_PRT\r
-#define SCSI_In_DBx__2__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL\r
-#define SCSI_In_DBx__2__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN\r
-#define SCSI_In_DBx__2__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0\r
-#define SCSI_In_DBx__2__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1\r
-#define SCSI_In_DBx__2__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0\r
-#define SCSI_In_DBx__2__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1\r
-#define SCSI_In_DBx__2__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT\r
-#define SCSI_In_DBx__2__PS CYREG_PRT2_PS\r
-#define SCSI_In_DBx__2__SHIFT 6u\r
-#define SCSI_In_DBx__2__SLW CYREG_PRT2_SLW\r
-#define SCSI_In_DBx__3__AG CYREG_PRT2_AG\r
-#define SCSI_In_DBx__3__AMUX CYREG_PRT2_AMUX\r
-#define SCSI_In_DBx__3__BIE CYREG_PRT2_BIE\r
-#define SCSI_In_DBx__3__BIT_MASK CYREG_PRT2_BIT_MASK\r
-#define SCSI_In_DBx__3__BYP CYREG_PRT2_BYP\r
-#define SCSI_In_DBx__3__CTL CYREG_PRT2_CTL\r
-#define SCSI_In_DBx__3__DM0 CYREG_PRT2_DM0\r
-#define SCSI_In_DBx__3__DM1 CYREG_PRT2_DM1\r
-#define SCSI_In_DBx__3__DM2 CYREG_PRT2_DM2\r
-#define SCSI_In_DBx__3__DR CYREG_PRT2_DR\r
-#define SCSI_In_DBx__3__INP_DIS CYREG_PRT2_INP_DIS\r
-#define SCSI_In_DBx__3__INTTYPE CYREG_PICU2_INTTYPE5\r
-#define SCSI_In_DBx__3__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG\r
-#define SCSI_In_DBx__3__LCD_EN CYREG_PRT2_LCD_EN\r
-#define SCSI_In_DBx__3__MASK 0x20u\r
-#define SCSI_In_DBx__3__PC CYREG_PRT2_PC5\r
-#define SCSI_In_DBx__3__PORT 2u\r
-#define SCSI_In_DBx__3__PRT CYREG_PRT2_PRT\r
-#define SCSI_In_DBx__3__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL\r
-#define SCSI_In_DBx__3__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN\r
-#define SCSI_In_DBx__3__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0\r
-#define SCSI_In_DBx__3__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1\r
-#define SCSI_In_DBx__3__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0\r
-#define SCSI_In_DBx__3__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1\r
-#define SCSI_In_DBx__3__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT\r
-#define SCSI_In_DBx__3__PS CYREG_PRT2_PS\r
-#define SCSI_In_DBx__3__SHIFT 5u\r
-#define SCSI_In_DBx__3__SLW CYREG_PRT2_SLW\r
-#define SCSI_In_DBx__4__AG CYREG_PRT2_AG\r
-#define SCSI_In_DBx__4__AMUX CYREG_PRT2_AMUX\r
-#define SCSI_In_DBx__4__BIE CYREG_PRT2_BIE\r
-#define SCSI_In_DBx__4__BIT_MASK CYREG_PRT2_BIT_MASK\r
-#define SCSI_In_DBx__4__BYP CYREG_PRT2_BYP\r
-#define SCSI_In_DBx__4__CTL CYREG_PRT2_CTL\r
-#define SCSI_In_DBx__4__DM0 CYREG_PRT2_DM0\r
-#define SCSI_In_DBx__4__DM1 CYREG_PRT2_DM1\r
-#define SCSI_In_DBx__4__DM2 CYREG_PRT2_DM2\r
-#define SCSI_In_DBx__4__DR CYREG_PRT2_DR\r
-#define SCSI_In_DBx__4__INP_DIS CYREG_PRT2_INP_DIS\r
-#define SCSI_In_DBx__4__INTTYPE CYREG_PICU2_INTTYPE4\r
-#define SCSI_In_DBx__4__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG\r
-#define SCSI_In_DBx__4__LCD_EN CYREG_PRT2_LCD_EN\r
-#define SCSI_In_DBx__4__MASK 0x10u\r
-#define SCSI_In_DBx__4__PC CYREG_PRT2_PC4\r
-#define SCSI_In_DBx__4__PORT 2u\r
-#define SCSI_In_DBx__4__PRT CYREG_PRT2_PRT\r
-#define SCSI_In_DBx__4__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL\r
-#define SCSI_In_DBx__4__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN\r
-#define SCSI_In_DBx__4__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0\r
-#define SCSI_In_DBx__4__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1\r
-#define SCSI_In_DBx__4__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0\r
-#define SCSI_In_DBx__4__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1\r
-#define SCSI_In_DBx__4__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT\r
-#define SCSI_In_DBx__4__PS CYREG_PRT2_PS\r
-#define SCSI_In_DBx__4__SHIFT 4u\r
-#define SCSI_In_DBx__4__SLW CYREG_PRT2_SLW\r
-#define SCSI_In_DBx__5__AG CYREG_PRT2_AG\r
-#define SCSI_In_DBx__5__AMUX CYREG_PRT2_AMUX\r
-#define SCSI_In_DBx__5__BIE CYREG_PRT2_BIE\r
-#define SCSI_In_DBx__5__BIT_MASK CYREG_PRT2_BIT_MASK\r
-#define SCSI_In_DBx__5__BYP CYREG_PRT2_BYP\r
-#define SCSI_In_DBx__5__CTL CYREG_PRT2_CTL\r
-#define SCSI_In_DBx__5__DM0 CYREG_PRT2_DM0\r
-#define SCSI_In_DBx__5__DM1 CYREG_PRT2_DM1\r
-#define SCSI_In_DBx__5__DM2 CYREG_PRT2_DM2\r
-#define SCSI_In_DBx__5__DR CYREG_PRT2_DR\r
-#define SCSI_In_DBx__5__INP_DIS CYREG_PRT2_INP_DIS\r
-#define SCSI_In_DBx__5__INTTYPE CYREG_PICU2_INTTYPE3\r
-#define SCSI_In_DBx__5__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG\r
-#define SCSI_In_DBx__5__LCD_EN CYREG_PRT2_LCD_EN\r
-#define SCSI_In_DBx__5__MASK 0x08u\r
-#define SCSI_In_DBx__5__PC CYREG_PRT2_PC3\r
-#define SCSI_In_DBx__5__PORT 2u\r
-#define SCSI_In_DBx__5__PRT CYREG_PRT2_PRT\r
-#define SCSI_In_DBx__5__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL\r
-#define SCSI_In_DBx__5__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN\r
-#define SCSI_In_DBx__5__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0\r
-#define SCSI_In_DBx__5__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1\r
-#define SCSI_In_DBx__5__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0\r
-#define SCSI_In_DBx__5__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1\r
-#define SCSI_In_DBx__5__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT\r
-#define SCSI_In_DBx__5__PS CYREG_PRT2_PS\r
-#define SCSI_In_DBx__5__SHIFT 3u\r
-#define SCSI_In_DBx__5__SLW CYREG_PRT2_SLW\r
-#define SCSI_In_DBx__6__AG CYREG_PRT2_AG\r
-#define SCSI_In_DBx__6__AMUX CYREG_PRT2_AMUX\r
-#define SCSI_In_DBx__6__BIE CYREG_PRT2_BIE\r
-#define SCSI_In_DBx__6__BIT_MASK CYREG_PRT2_BIT_MASK\r
-#define SCSI_In_DBx__6__BYP CYREG_PRT2_BYP\r
-#define SCSI_In_DBx__6__CTL CYREG_PRT2_CTL\r
-#define SCSI_In_DBx__6__DM0 CYREG_PRT2_DM0\r
-#define SCSI_In_DBx__6__DM1 CYREG_PRT2_DM1\r
-#define SCSI_In_DBx__6__DM2 CYREG_PRT2_DM2\r
-#define SCSI_In_DBx__6__DR CYREG_PRT2_DR\r
-#define SCSI_In_DBx__6__INP_DIS CYREG_PRT2_INP_DIS\r
-#define SCSI_In_DBx__6__INTTYPE CYREG_PICU2_INTTYPE2\r
-#define SCSI_In_DBx__6__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG\r
-#define SCSI_In_DBx__6__LCD_EN CYREG_PRT2_LCD_EN\r
-#define SCSI_In_DBx__6__MASK 0x04u\r
-#define SCSI_In_DBx__6__PC CYREG_PRT2_PC2\r
-#define SCSI_In_DBx__6__PORT 2u\r
-#define SCSI_In_DBx__6__PRT CYREG_PRT2_PRT\r
-#define SCSI_In_DBx__6__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL\r
-#define SCSI_In_DBx__6__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN\r
-#define SCSI_In_DBx__6__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0\r
-#define SCSI_In_DBx__6__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1\r
-#define SCSI_In_DBx__6__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0\r
-#define SCSI_In_DBx__6__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1\r
-#define SCSI_In_DBx__6__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT\r
-#define SCSI_In_DBx__6__PS CYREG_PRT2_PS\r
-#define SCSI_In_DBx__6__SHIFT 2u\r
-#define SCSI_In_DBx__6__SLW CYREG_PRT2_SLW\r
-#define SCSI_In_DBx__7__AG CYREG_PRT2_AG\r
-#define SCSI_In_DBx__7__AMUX CYREG_PRT2_AMUX\r
-#define SCSI_In_DBx__7__BIE CYREG_PRT2_BIE\r
-#define SCSI_In_DBx__7__BIT_MASK CYREG_PRT2_BIT_MASK\r
-#define SCSI_In_DBx__7__BYP CYREG_PRT2_BYP\r
-#define SCSI_In_DBx__7__CTL CYREG_PRT2_CTL\r
-#define SCSI_In_DBx__7__DM0 CYREG_PRT2_DM0\r
-#define SCSI_In_DBx__7__DM1 CYREG_PRT2_DM1\r
-#define SCSI_In_DBx__7__DM2 CYREG_PRT2_DM2\r
-#define SCSI_In_DBx__7__DR CYREG_PRT2_DR\r
-#define SCSI_In_DBx__7__INP_DIS CYREG_PRT2_INP_DIS\r
-#define SCSI_In_DBx__7__INTTYPE CYREG_PICU2_INTTYPE1\r
-#define SCSI_In_DBx__7__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG\r
-#define SCSI_In_DBx__7__LCD_EN CYREG_PRT2_LCD_EN\r
-#define SCSI_In_DBx__7__MASK 0x02u\r
-#define SCSI_In_DBx__7__PC CYREG_PRT2_PC1\r
-#define SCSI_In_DBx__7__PORT 2u\r
-#define SCSI_In_DBx__7__PRT CYREG_PRT2_PRT\r
-#define SCSI_In_DBx__7__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL\r
-#define SCSI_In_DBx__7__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN\r
-#define SCSI_In_DBx__7__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0\r
-#define SCSI_In_DBx__7__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1\r
-#define SCSI_In_DBx__7__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0\r
-#define SCSI_In_DBx__7__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1\r
-#define SCSI_In_DBx__7__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT\r
-#define SCSI_In_DBx__7__PS CYREG_PRT2_PS\r
-#define SCSI_In_DBx__7__SHIFT 1u\r
-#define SCSI_In_DBx__7__SLW CYREG_PRT2_SLW\r
-#define SCSI_In_DBx__DB0__AG CYREG_PRT12_AG\r
-#define SCSI_In_DBx__DB0__BIE CYREG_PRT12_BIE\r
-#define SCSI_In_DBx__DB0__BIT_MASK CYREG_PRT12_BIT_MASK\r
-#define SCSI_In_DBx__DB0__BYP CYREG_PRT12_BYP\r
-#define SCSI_In_DBx__DB0__DM0 CYREG_PRT12_DM0\r
-#define SCSI_In_DBx__DB0__DM1 CYREG_PRT12_DM1\r
-#define SCSI_In_DBx__DB0__DM2 CYREG_PRT12_DM2\r
-#define SCSI_In_DBx__DB0__DR CYREG_PRT12_DR\r
-#define SCSI_In_DBx__DB0__INP_DIS CYREG_PRT12_INP_DIS\r
-#define SCSI_In_DBx__DB0__INTTYPE CYREG_PICU12_INTTYPE4\r
-#define SCSI_In_DBx__DB0__MASK 0x10u\r
-#define SCSI_In_DBx__DB0__PC CYREG_PRT12_PC4\r
-#define SCSI_In_DBx__DB0__PORT 12u\r
-#define SCSI_In_DBx__DB0__PRT CYREG_PRT12_PRT\r
-#define SCSI_In_DBx__DB0__PRTDSI__DBL_SYNC_IN CYREG_PRT12_DBL_SYNC_IN\r
-#define SCSI_In_DBx__DB0__PRTDSI__OE_SEL0 CYREG_PRT12_OE_SEL0\r
-#define SCSI_In_DBx__DB0__PRTDSI__OE_SEL1 CYREG_PRT12_OE_SEL1\r
-#define SCSI_In_DBx__DB0__PRTDSI__OUT_SEL0 CYREG_PRT12_OUT_SEL0\r
-#define SCSI_In_DBx__DB0__PRTDSI__OUT_SEL1 CYREG_PRT12_OUT_SEL1\r
-#define SCSI_In_DBx__DB0__PRTDSI__SYNC_OUT CYREG_PRT12_SYNC_OUT\r
-#define SCSI_In_DBx__DB0__PS CYREG_PRT12_PS\r
-#define SCSI_In_DBx__DB0__SHIFT 4u\r
-#define SCSI_In_DBx__DB0__SIO_CFG CYREG_PRT12_SIO_CFG\r
-#define SCSI_In_DBx__DB0__SIO_DIFF CYREG_PRT12_SIO_DIFF\r
-#define SCSI_In_DBx__DB0__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN\r
-#define SCSI_In_DBx__DB0__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ\r
-#define SCSI_In_DBx__DB0__SLW CYREG_PRT12_SLW\r
-#define SCSI_In_DBx__DB1__AG CYREG_PRT2_AG\r
-#define SCSI_In_DBx__DB1__AMUX CYREG_PRT2_AMUX\r
-#define SCSI_In_DBx__DB1__BIE CYREG_PRT2_BIE\r
-#define SCSI_In_DBx__DB1__BIT_MASK CYREG_PRT2_BIT_MASK\r
-#define SCSI_In_DBx__DB1__BYP CYREG_PRT2_BYP\r
-#define SCSI_In_DBx__DB1__CTL CYREG_PRT2_CTL\r
-#define SCSI_In_DBx__DB1__DM0 CYREG_PRT2_DM0\r
-#define SCSI_In_DBx__DB1__DM1 CYREG_PRT2_DM1\r
-#define SCSI_In_DBx__DB1__DM2 CYREG_PRT2_DM2\r
-#define SCSI_In_DBx__DB1__DR CYREG_PRT2_DR\r
-#define SCSI_In_DBx__DB1__INP_DIS CYREG_PRT2_INP_DIS\r
-#define SCSI_In_DBx__DB1__INTTYPE CYREG_PICU2_INTTYPE7\r
-#define SCSI_In_DBx__DB1__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG\r
-#define SCSI_In_DBx__DB1__LCD_EN CYREG_PRT2_LCD_EN\r
-#define SCSI_In_DBx__DB1__MASK 0x80u\r
-#define SCSI_In_DBx__DB1__PC CYREG_PRT2_PC7\r
-#define SCSI_In_DBx__DB1__PORT 2u\r
-#define SCSI_In_DBx__DB1__PRT CYREG_PRT2_PRT\r
-#define SCSI_In_DBx__DB1__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL\r
-#define SCSI_In_DBx__DB1__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN\r
-#define SCSI_In_DBx__DB1__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0\r
-#define SCSI_In_DBx__DB1__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1\r
-#define SCSI_In_DBx__DB1__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0\r
-#define SCSI_In_DBx__DB1__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1\r
-#define SCSI_In_DBx__DB1__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT\r
-#define SCSI_In_DBx__DB1__PS CYREG_PRT2_PS\r
-#define SCSI_In_DBx__DB1__SHIFT 7u\r
-#define SCSI_In_DBx__DB1__SLW CYREG_PRT2_SLW\r
-#define SCSI_In_DBx__DB2__AG CYREG_PRT2_AG\r
-#define SCSI_In_DBx__DB2__AMUX CYREG_PRT2_AMUX\r
-#define SCSI_In_DBx__DB2__BIE CYREG_PRT2_BIE\r
-#define SCSI_In_DBx__DB2__BIT_MASK CYREG_PRT2_BIT_MASK\r
-#define SCSI_In_DBx__DB2__BYP CYREG_PRT2_BYP\r
-#define SCSI_In_DBx__DB2__CTL CYREG_PRT2_CTL\r
-#define SCSI_In_DBx__DB2__DM0 CYREG_PRT2_DM0\r
-#define SCSI_In_DBx__DB2__DM1 CYREG_PRT2_DM1\r
-#define SCSI_In_DBx__DB2__DM2 CYREG_PRT2_DM2\r
-#define SCSI_In_DBx__DB2__DR CYREG_PRT2_DR\r
-#define SCSI_In_DBx__DB2__INP_DIS CYREG_PRT2_INP_DIS\r
-#define SCSI_In_DBx__DB2__INTTYPE CYREG_PICU2_INTTYPE6\r
-#define SCSI_In_DBx__DB2__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG\r
-#define SCSI_In_DBx__DB2__LCD_EN CYREG_PRT2_LCD_EN\r
-#define SCSI_In_DBx__DB2__MASK 0x40u\r
-#define SCSI_In_DBx__DB2__PC CYREG_PRT2_PC6\r
-#define SCSI_In_DBx__DB2__PORT 2u\r
-#define SCSI_In_DBx__DB2__PRT CYREG_PRT2_PRT\r
-#define SCSI_In_DBx__DB2__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL\r
-#define SCSI_In_DBx__DB2__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN\r
-#define SCSI_In_DBx__DB2__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0\r
-#define SCSI_In_DBx__DB2__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1\r
-#define SCSI_In_DBx__DB2__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0\r
-#define SCSI_In_DBx__DB2__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1\r
-#define SCSI_In_DBx__DB2__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT\r
-#define SCSI_In_DBx__DB2__PS CYREG_PRT2_PS\r
-#define SCSI_In_DBx__DB2__SHIFT 6u\r
-#define SCSI_In_DBx__DB2__SLW CYREG_PRT2_SLW\r
-#define SCSI_In_DBx__DB3__AG CYREG_PRT2_AG\r
-#define SCSI_In_DBx__DB3__AMUX CYREG_PRT2_AMUX\r
-#define SCSI_In_DBx__DB3__BIE CYREG_PRT2_BIE\r
-#define SCSI_In_DBx__DB3__BIT_MASK CYREG_PRT2_BIT_MASK\r
-#define SCSI_In_DBx__DB3__BYP CYREG_PRT2_BYP\r
-#define SCSI_In_DBx__DB3__CTL CYREG_PRT2_CTL\r
-#define SCSI_In_DBx__DB3__DM0 CYREG_PRT2_DM0\r
-#define SCSI_In_DBx__DB3__DM1 CYREG_PRT2_DM1\r
-#define SCSI_In_DBx__DB3__DM2 CYREG_PRT2_DM2\r
-#define SCSI_In_DBx__DB3__DR CYREG_PRT2_DR\r
-#define SCSI_In_DBx__DB3__INP_DIS CYREG_PRT2_INP_DIS\r
-#define SCSI_In_DBx__DB3__INTTYPE CYREG_PICU2_INTTYPE5\r
-#define SCSI_In_DBx__DB3__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG\r
-#define SCSI_In_DBx__DB3__LCD_EN CYREG_PRT2_LCD_EN\r
-#define SCSI_In_DBx__DB3__MASK 0x20u\r
-#define SCSI_In_DBx__DB3__PC CYREG_PRT2_PC5\r
-#define SCSI_In_DBx__DB3__PORT 2u\r
-#define SCSI_In_DBx__DB3__PRT CYREG_PRT2_PRT\r
-#define SCSI_In_DBx__DB3__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL\r
-#define SCSI_In_DBx__DB3__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN\r
-#define SCSI_In_DBx__DB3__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0\r
-#define SCSI_In_DBx__DB3__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1\r
-#define SCSI_In_DBx__DB3__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0\r
-#define SCSI_In_DBx__DB3__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1\r
-#define SCSI_In_DBx__DB3__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT\r
-#define SCSI_In_DBx__DB3__PS CYREG_PRT2_PS\r
-#define SCSI_In_DBx__DB3__SHIFT 5u\r
-#define SCSI_In_DBx__DB3__SLW CYREG_PRT2_SLW\r
-#define SCSI_In_DBx__DB4__AG CYREG_PRT2_AG\r
-#define SCSI_In_DBx__DB4__AMUX CYREG_PRT2_AMUX\r
-#define SCSI_In_DBx__DB4__BIE CYREG_PRT2_BIE\r
-#define SCSI_In_DBx__DB4__BIT_MASK CYREG_PRT2_BIT_MASK\r
-#define SCSI_In_DBx__DB4__BYP CYREG_PRT2_BYP\r
-#define SCSI_In_DBx__DB4__CTL CYREG_PRT2_CTL\r
-#define SCSI_In_DBx__DB4__DM0 CYREG_PRT2_DM0\r
-#define SCSI_In_DBx__DB4__DM1 CYREG_PRT2_DM1\r
-#define SCSI_In_DBx__DB4__DM2 CYREG_PRT2_DM2\r
-#define SCSI_In_DBx__DB4__DR CYREG_PRT2_DR\r
-#define SCSI_In_DBx__DB4__INP_DIS CYREG_PRT2_INP_DIS\r
-#define SCSI_In_DBx__DB4__INTTYPE CYREG_PICU2_INTTYPE4\r
-#define SCSI_In_DBx__DB4__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG\r
-#define SCSI_In_DBx__DB4__LCD_EN CYREG_PRT2_LCD_EN\r
-#define SCSI_In_DBx__DB4__MASK 0x10u\r
-#define SCSI_In_DBx__DB4__PC CYREG_PRT2_PC4\r
-#define SCSI_In_DBx__DB4__PORT 2u\r
-#define SCSI_In_DBx__DB4__PRT CYREG_PRT2_PRT\r
-#define SCSI_In_DBx__DB4__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL\r
-#define SCSI_In_DBx__DB4__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN\r
-#define SCSI_In_DBx__DB4__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0\r
-#define SCSI_In_DBx__DB4__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1\r
-#define SCSI_In_DBx__DB4__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0\r
-#define SCSI_In_DBx__DB4__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1\r
-#define SCSI_In_DBx__DB4__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT\r
-#define SCSI_In_DBx__DB4__PS CYREG_PRT2_PS\r
-#define SCSI_In_DBx__DB4__SHIFT 4u\r
-#define SCSI_In_DBx__DB4__SLW CYREG_PRT2_SLW\r
-#define SCSI_In_DBx__DB5__AG CYREG_PRT2_AG\r
-#define SCSI_In_DBx__DB5__AMUX CYREG_PRT2_AMUX\r
-#define SCSI_In_DBx__DB5__BIE CYREG_PRT2_BIE\r
-#define SCSI_In_DBx__DB5__BIT_MASK CYREG_PRT2_BIT_MASK\r
-#define SCSI_In_DBx__DB5__BYP CYREG_PRT2_BYP\r
-#define SCSI_In_DBx__DB5__CTL CYREG_PRT2_CTL\r
-#define SCSI_In_DBx__DB5__DM0 CYREG_PRT2_DM0\r
-#define SCSI_In_DBx__DB5__DM1 CYREG_PRT2_DM1\r
-#define SCSI_In_DBx__DB5__DM2 CYREG_PRT2_DM2\r
-#define SCSI_In_DBx__DB5__DR CYREG_PRT2_DR\r
-#define SCSI_In_DBx__DB5__INP_DIS CYREG_PRT2_INP_DIS\r
-#define SCSI_In_DBx__DB5__INTTYPE CYREG_PICU2_INTTYPE3\r
-#define SCSI_In_DBx__DB5__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG\r
-#define SCSI_In_DBx__DB5__LCD_EN CYREG_PRT2_LCD_EN\r
-#define SCSI_In_DBx__DB5__MASK 0x08u\r
-#define SCSI_In_DBx__DB5__PC CYREG_PRT2_PC3\r
-#define SCSI_In_DBx__DB5__PORT 2u\r
-#define SCSI_In_DBx__DB5__PRT CYREG_PRT2_PRT\r
-#define SCSI_In_DBx__DB5__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL\r
-#define SCSI_In_DBx__DB5__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN\r
-#define SCSI_In_DBx__DB5__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0\r
-#define SCSI_In_DBx__DB5__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1\r
-#define SCSI_In_DBx__DB5__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0\r
-#define SCSI_In_DBx__DB5__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1\r
-#define SCSI_In_DBx__DB5__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT\r
-#define SCSI_In_DBx__DB5__PS CYREG_PRT2_PS\r
-#define SCSI_In_DBx__DB5__SHIFT 3u\r
-#define SCSI_In_DBx__DB5__SLW CYREG_PRT2_SLW\r
-#define SCSI_In_DBx__DB6__AG CYREG_PRT2_AG\r
-#define SCSI_In_DBx__DB6__AMUX CYREG_PRT2_AMUX\r
-#define SCSI_In_DBx__DB6__BIE CYREG_PRT2_BIE\r
-#define SCSI_In_DBx__DB6__BIT_MASK CYREG_PRT2_BIT_MASK\r
-#define SCSI_In_DBx__DB6__BYP CYREG_PRT2_BYP\r
-#define SCSI_In_DBx__DB6__CTL CYREG_PRT2_CTL\r
-#define SCSI_In_DBx__DB6__DM0 CYREG_PRT2_DM0\r
-#define SCSI_In_DBx__DB6__DM1 CYREG_PRT2_DM1\r
-#define SCSI_In_DBx__DB6__DM2 CYREG_PRT2_DM2\r
-#define SCSI_In_DBx__DB6__DR CYREG_PRT2_DR\r
-#define SCSI_In_DBx__DB6__INP_DIS CYREG_PRT2_INP_DIS\r
-#define SCSI_In_DBx__DB6__INTTYPE CYREG_PICU2_INTTYPE2\r
-#define SCSI_In_DBx__DB6__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG\r
-#define SCSI_In_DBx__DB6__LCD_EN CYREG_PRT2_LCD_EN\r
-#define SCSI_In_DBx__DB6__MASK 0x04u\r
-#define SCSI_In_DBx__DB6__PC CYREG_PRT2_PC2\r
-#define SCSI_In_DBx__DB6__PORT 2u\r
-#define SCSI_In_DBx__DB6__PRT CYREG_PRT2_PRT\r
-#define SCSI_In_DBx__DB6__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL\r
-#define SCSI_In_DBx__DB6__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN\r
-#define SCSI_In_DBx__DB6__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0\r
-#define SCSI_In_DBx__DB6__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1\r
-#define SCSI_In_DBx__DB6__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0\r
-#define SCSI_In_DBx__DB6__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1\r
-#define SCSI_In_DBx__DB6__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT\r
-#define SCSI_In_DBx__DB6__PS CYREG_PRT2_PS\r
-#define SCSI_In_DBx__DB6__SHIFT 2u\r
-#define SCSI_In_DBx__DB6__SLW CYREG_PRT2_SLW\r
-#define SCSI_In_DBx__DB7__AG CYREG_PRT2_AG\r
-#define SCSI_In_DBx__DB7__AMUX CYREG_PRT2_AMUX\r
-#define SCSI_In_DBx__DB7__BIE CYREG_PRT2_BIE\r
-#define SCSI_In_DBx__DB7__BIT_MASK CYREG_PRT2_BIT_MASK\r
-#define SCSI_In_DBx__DB7__BYP CYREG_PRT2_BYP\r
-#define SCSI_In_DBx__DB7__CTL CYREG_PRT2_CTL\r
-#define SCSI_In_DBx__DB7__DM0 CYREG_PRT2_DM0\r
-#define SCSI_In_DBx__DB7__DM1 CYREG_PRT2_DM1\r
-#define SCSI_In_DBx__DB7__DM2 CYREG_PRT2_DM2\r
-#define SCSI_In_DBx__DB7__DR CYREG_PRT2_DR\r
-#define SCSI_In_DBx__DB7__INP_DIS CYREG_PRT2_INP_DIS\r
-#define SCSI_In_DBx__DB7__INTTYPE CYREG_PICU2_INTTYPE1\r
-#define SCSI_In_DBx__DB7__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG\r
-#define SCSI_In_DBx__DB7__LCD_EN CYREG_PRT2_LCD_EN\r
-#define SCSI_In_DBx__DB7__MASK 0x02u\r
-#define SCSI_In_DBx__DB7__PC CYREG_PRT2_PC1\r
-#define SCSI_In_DBx__DB7__PORT 2u\r
-#define SCSI_In_DBx__DB7__PRT CYREG_PRT2_PRT\r
-#define SCSI_In_DBx__DB7__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL\r
-#define SCSI_In_DBx__DB7__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN\r
-#define SCSI_In_DBx__DB7__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0\r
-#define SCSI_In_DBx__DB7__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1\r
-#define SCSI_In_DBx__DB7__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0\r
-#define SCSI_In_DBx__DB7__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1\r
-#define SCSI_In_DBx__DB7__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT\r
-#define SCSI_In_DBx__DB7__PS CYREG_PRT2_PS\r
-#define SCSI_In_DBx__DB7__SHIFT 1u\r
-#define SCSI_In_DBx__DB7__SLW CYREG_PRT2_SLW\r
-\r
-/* SD_DAT1 */\r
-#define SD_DAT1__0__INTTYPE CYREG_PICU3_INTTYPE0\r
-#define SD_DAT1__0__MASK 0x01u\r
-#define SD_DAT1__0__PC CYREG_PRT3_PC0\r
-#define SD_DAT1__0__PORT 3u\r
-#define SD_DAT1__0__SHIFT 0u\r
-#define SD_DAT1__AG CYREG_PRT3_AG\r
-#define SD_DAT1__AMUX CYREG_PRT3_AMUX\r
-#define SD_DAT1__BIE CYREG_PRT3_BIE\r
-#define SD_DAT1__BIT_MASK CYREG_PRT3_BIT_MASK\r
-#define SD_DAT1__BYP CYREG_PRT3_BYP\r
-#define SD_DAT1__CTL CYREG_PRT3_CTL\r
-#define SD_DAT1__DM0 CYREG_PRT3_DM0\r
-#define SD_DAT1__DM1 CYREG_PRT3_DM1\r
-#define SD_DAT1__DM2 CYREG_PRT3_DM2\r
-#define SD_DAT1__DR CYREG_PRT3_DR\r
-#define SD_DAT1__INP_DIS CYREG_PRT3_INP_DIS\r
-#define SD_DAT1__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU3_BASE\r
-#define SD_DAT1__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG\r
-#define SD_DAT1__LCD_EN CYREG_PRT3_LCD_EN\r
-#define SD_DAT1__MASK 0x01u\r
-#define SD_DAT1__PORT 3u\r
-#define SD_DAT1__PRT CYREG_PRT3_PRT\r
-#define SD_DAT1__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL\r
-#define SD_DAT1__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN\r
-#define SD_DAT1__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0\r
-#define SD_DAT1__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1\r
-#define SD_DAT1__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0\r
-#define SD_DAT1__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1\r
-#define SD_DAT1__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT\r
-#define SD_DAT1__PS CYREG_PRT3_PS\r
-#define SD_DAT1__SHIFT 0u\r
-#define SD_DAT1__SLW CYREG_PRT3_SLW\r
-\r
-/* SD_DAT2 */\r
-#define SD_DAT2__0__INTTYPE CYREG_PICU3_INTTYPE5\r
-#define SD_DAT2__0__MASK 0x20u\r
-#define SD_DAT2__0__PC CYREG_PRT3_PC5\r
-#define SD_DAT2__0__PORT 3u\r
-#define SD_DAT2__0__SHIFT 5u\r
-#define SD_DAT2__AG CYREG_PRT3_AG\r
-#define SD_DAT2__AMUX CYREG_PRT3_AMUX\r
-#define SD_DAT2__BIE CYREG_PRT3_BIE\r
-#define SD_DAT2__BIT_MASK CYREG_PRT3_BIT_MASK\r
-#define SD_DAT2__BYP CYREG_PRT3_BYP\r
-#define SD_DAT2__CTL CYREG_PRT3_CTL\r
-#define SD_DAT2__DM0 CYREG_PRT3_DM0\r
-#define SD_DAT2__DM1 CYREG_PRT3_DM1\r
-#define SD_DAT2__DM2 CYREG_PRT3_DM2\r
-#define SD_DAT2__DR CYREG_PRT3_DR\r
-#define SD_DAT2__INP_DIS CYREG_PRT3_INP_DIS\r
-#define SD_DAT2__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU3_BASE\r
-#define SD_DAT2__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG\r
-#define SD_DAT2__LCD_EN CYREG_PRT3_LCD_EN\r
-#define SD_DAT2__MASK 0x20u\r
-#define SD_DAT2__PORT 3u\r
-#define SD_DAT2__PRT CYREG_PRT3_PRT\r
-#define SD_DAT2__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL\r
-#define SD_DAT2__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN\r
-#define SD_DAT2__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0\r
-#define SD_DAT2__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1\r
-#define SD_DAT2__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0\r
-#define SD_DAT2__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1\r
-#define SD_DAT2__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT\r
-#define SD_DAT2__PS CYREG_PRT3_PS\r
-#define SD_DAT2__SHIFT 5u\r
-#define SD_DAT2__SLW CYREG_PRT3_SLW\r
-\r
-/* SD_MISO */\r
-#define SD_MISO__0__INTTYPE CYREG_PICU3_INTTYPE1\r
-#define SD_MISO__0__MASK 0x02u\r
-#define SD_MISO__0__PC CYREG_PRT3_PC1\r
-#define SD_MISO__0__PORT 3u\r
-#define SD_MISO__0__SHIFT 1u\r
-#define SD_MISO__AG CYREG_PRT3_AG\r
-#define SD_MISO__AMUX CYREG_PRT3_AMUX\r
-#define SD_MISO__BIE CYREG_PRT3_BIE\r
-#define SD_MISO__BIT_MASK CYREG_PRT3_BIT_MASK\r
-#define SD_MISO__BYP CYREG_PRT3_BYP\r
-#define SD_MISO__CTL CYREG_PRT3_CTL\r
-#define SD_MISO__DM0 CYREG_PRT3_DM0\r
-#define SD_MISO__DM1 CYREG_PRT3_DM1\r
-#define SD_MISO__DM2 CYREG_PRT3_DM2\r
-#define SD_MISO__DR CYREG_PRT3_DR\r
-#define SD_MISO__INP_DIS CYREG_PRT3_INP_DIS\r
-#define SD_MISO__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU3_BASE\r
-#define SD_MISO__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG\r
-#define SD_MISO__LCD_EN CYREG_PRT3_LCD_EN\r
-#define SD_MISO__MASK 0x02u\r
-#define SD_MISO__PORT 3u\r
-#define SD_MISO__PRT CYREG_PRT3_PRT\r
-#define SD_MISO__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL\r
-#define SD_MISO__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN\r
-#define SD_MISO__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0\r
-#define SD_MISO__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1\r
-#define SD_MISO__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0\r
-#define SD_MISO__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1\r
-#define SD_MISO__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT\r
-#define SD_MISO__PS CYREG_PRT3_PS\r
-#define SD_MISO__SHIFT 1u\r
-#define SD_MISO__SLW CYREG_PRT3_SLW\r
-\r
-/* SD_MOSI */\r
-#define SD_MOSI__0__INTTYPE CYREG_PICU3_INTTYPE3\r
-#define SD_MOSI__0__MASK 0x08u\r
-#define SD_MOSI__0__PC CYREG_PRT3_PC3\r
-#define SD_MOSI__0__PORT 3u\r
-#define SD_MOSI__0__SHIFT 3u\r
-#define SD_MOSI__AG CYREG_PRT3_AG\r
-#define SD_MOSI__AMUX CYREG_PRT3_AMUX\r
-#define SD_MOSI__BIE CYREG_PRT3_BIE\r
-#define SD_MOSI__BIT_MASK CYREG_PRT3_BIT_MASK\r
-#define SD_MOSI__BYP CYREG_PRT3_BYP\r
-#define SD_MOSI__CTL CYREG_PRT3_CTL\r
-#define SD_MOSI__DM0 CYREG_PRT3_DM0\r
-#define SD_MOSI__DM1 CYREG_PRT3_DM1\r
-#define SD_MOSI__DM2 CYREG_PRT3_DM2\r
-#define SD_MOSI__DR CYREG_PRT3_DR\r
-#define SD_MOSI__INP_DIS CYREG_PRT3_INP_DIS\r
-#define SD_MOSI__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU3_BASE\r
-#define SD_MOSI__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG\r
-#define SD_MOSI__LCD_EN CYREG_PRT3_LCD_EN\r
-#define SD_MOSI__MASK 0x08u\r
-#define SD_MOSI__PORT 3u\r
-#define SD_MOSI__PRT CYREG_PRT3_PRT\r
-#define SD_MOSI__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL\r
-#define SD_MOSI__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN\r
-#define SD_MOSI__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0\r
-#define SD_MOSI__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1\r
-#define SD_MOSI__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0\r
-#define SD_MOSI__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1\r
-#define SD_MOSI__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT\r
-#define SD_MOSI__PS CYREG_PRT3_PS\r
-#define SD_MOSI__SHIFT 3u\r
-#define SD_MOSI__SLW CYREG_PRT3_SLW\r
-\r
-/* SCSI_CLK */\r
-#define SCSI_CLK__CFG0 CYREG_CLKDIST_DCFG1_CFG0\r
-#define SCSI_CLK__CFG1 CYREG_CLKDIST_DCFG1_CFG1\r
-#define SCSI_CLK__CFG2 CYREG_CLKDIST_DCFG1_CFG2\r
-#define SCSI_CLK__CFG2_SRC_SEL_MASK 0x07u\r
-#define SCSI_CLK__INDEX 0x01u\r
-#define SCSI_CLK__PM_ACT_CFG CYREG_PM_ACT_CFG2\r
-#define SCSI_CLK__PM_ACT_MSK 0x02u\r
-#define SCSI_CLK__PM_STBY_CFG CYREG_PM_STBY_CFG2\r
-#define SCSI_CLK__PM_STBY_MSK 0x02u\r
-\r
-/* SCSI_Out */\r
-#define SCSI_Out__0__AG CYREG_PRT4_AG\r
-#define SCSI_Out__0__AMUX CYREG_PRT4_AMUX\r
-#define SCSI_Out__0__BIE CYREG_PRT4_BIE\r
-#define SCSI_Out__0__BIT_MASK CYREG_PRT4_BIT_MASK\r
-#define SCSI_Out__0__BYP CYREG_PRT4_BYP\r
-#define SCSI_Out__0__CTL CYREG_PRT4_CTL\r
-#define SCSI_Out__0__DM0 CYREG_PRT4_DM0\r
-#define SCSI_Out__0__DM1 CYREG_PRT4_DM1\r
-#define SCSI_Out__0__DM2 CYREG_PRT4_DM2\r
-#define SCSI_Out__0__DR CYREG_PRT4_DR\r
-#define SCSI_Out__0__INP_DIS CYREG_PRT4_INP_DIS\r
-#define SCSI_Out__0__INTTYPE CYREG_PICU4_INTTYPE3\r
-#define SCSI_Out__0__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG\r
-#define SCSI_Out__0__LCD_EN CYREG_PRT4_LCD_EN\r
-#define SCSI_Out__0__MASK 0x08u\r
-#define SCSI_Out__0__PC CYREG_PRT4_PC3\r
-#define SCSI_Out__0__PORT 4u\r
-#define SCSI_Out__0__PRT CYREG_PRT4_PRT\r
-#define SCSI_Out__0__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL\r
-#define SCSI_Out__0__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN\r
-#define SCSI_Out__0__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0\r
-#define SCSI_Out__0__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1\r
-#define SCSI_Out__0__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0\r
-#define SCSI_Out__0__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1\r
-#define SCSI_Out__0__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT\r
-#define SCSI_Out__0__PS CYREG_PRT4_PS\r
-#define SCSI_Out__0__SHIFT 3u\r
-#define SCSI_Out__0__SLW CYREG_PRT4_SLW\r
-#define SCSI_Out__1__AG CYREG_PRT4_AG\r
-#define SCSI_Out__1__AMUX CYREG_PRT4_AMUX\r
-#define SCSI_Out__1__BIE CYREG_PRT4_BIE\r
-#define SCSI_Out__1__BIT_MASK CYREG_PRT4_BIT_MASK\r
-#define SCSI_Out__1__BYP CYREG_PRT4_BYP\r
-#define SCSI_Out__1__CTL CYREG_PRT4_CTL\r
-#define SCSI_Out__1__DM0 CYREG_PRT4_DM0\r
-#define SCSI_Out__1__DM1 CYREG_PRT4_DM1\r
-#define SCSI_Out__1__DM2 CYREG_PRT4_DM2\r
-#define SCSI_Out__1__DR CYREG_PRT4_DR\r
-#define SCSI_Out__1__INP_DIS CYREG_PRT4_INP_DIS\r
-#define SCSI_Out__1__INTTYPE CYREG_PICU4_INTTYPE2\r
-#define SCSI_Out__1__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG\r
-#define SCSI_Out__1__LCD_EN CYREG_PRT4_LCD_EN\r
-#define SCSI_Out__1__MASK 0x04u\r
-#define SCSI_Out__1__PC CYREG_PRT4_PC2\r
-#define SCSI_Out__1__PORT 4u\r
-#define SCSI_Out__1__PRT CYREG_PRT4_PRT\r
-#define SCSI_Out__1__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL\r
-#define SCSI_Out__1__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN\r
-#define SCSI_Out__1__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0\r
-#define SCSI_Out__1__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1\r
-#define SCSI_Out__1__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0\r
-#define SCSI_Out__1__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1\r
-#define SCSI_Out__1__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT\r
-#define SCSI_Out__1__PS CYREG_PRT4_PS\r
-#define SCSI_Out__1__SHIFT 2u\r
-#define SCSI_Out__1__SLW CYREG_PRT4_SLW\r
-#define SCSI_Out__2__AG CYREG_PRT0_AG\r
-#define SCSI_Out__2__AMUX CYREG_PRT0_AMUX\r
-#define SCSI_Out__2__BIE CYREG_PRT0_BIE\r
-#define SCSI_Out__2__BIT_MASK CYREG_PRT0_BIT_MASK\r
-#define SCSI_Out__2__BYP CYREG_PRT0_BYP\r
-#define SCSI_Out__2__CTL CYREG_PRT0_CTL\r
-#define SCSI_Out__2__DM0 CYREG_PRT0_DM0\r
-#define SCSI_Out__2__DM1 CYREG_PRT0_DM1\r
-#define SCSI_Out__2__DM2 CYREG_PRT0_DM2\r
-#define SCSI_Out__2__DR CYREG_PRT0_DR\r
-#define SCSI_Out__2__INP_DIS CYREG_PRT0_INP_DIS\r
-#define SCSI_Out__2__INTTYPE CYREG_PICU0_INTTYPE7\r
-#define SCSI_Out__2__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG\r
-#define SCSI_Out__2__LCD_EN CYREG_PRT0_LCD_EN\r
-#define SCSI_Out__2__MASK 0x80u\r
-#define SCSI_Out__2__PC CYREG_PRT0_PC7\r
-#define SCSI_Out__2__PORT 0u\r
-#define SCSI_Out__2__PRT CYREG_PRT0_PRT\r
-#define SCSI_Out__2__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL\r
-#define SCSI_Out__2__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN\r
-#define SCSI_Out__2__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0\r
-#define SCSI_Out__2__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1\r
-#define SCSI_Out__2__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0\r
-#define SCSI_Out__2__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1\r
-#define SCSI_Out__2__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT\r
-#define SCSI_Out__2__PS CYREG_PRT0_PS\r
-#define SCSI_Out__2__SHIFT 7u\r
-#define SCSI_Out__2__SLW CYREG_PRT0_SLW\r
-#define SCSI_Out__3__AG CYREG_PRT0_AG\r
-#define SCSI_Out__3__AMUX CYREG_PRT0_AMUX\r
-#define SCSI_Out__3__BIE CYREG_PRT0_BIE\r
-#define SCSI_Out__3__BIT_MASK CYREG_PRT0_BIT_MASK\r
-#define SCSI_Out__3__BYP CYREG_PRT0_BYP\r
-#define SCSI_Out__3__CTL CYREG_PRT0_CTL\r
-#define SCSI_Out__3__DM0 CYREG_PRT0_DM0\r
-#define SCSI_Out__3__DM1 CYREG_PRT0_DM1\r
-#define SCSI_Out__3__DM2 CYREG_PRT0_DM2\r
-#define SCSI_Out__3__DR CYREG_PRT0_DR\r
-#define SCSI_Out__3__INP_DIS CYREG_PRT0_INP_DIS\r
-#define SCSI_Out__3__INTTYPE CYREG_PICU0_INTTYPE6\r
-#define SCSI_Out__3__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG\r
-#define SCSI_Out__3__LCD_EN CYREG_PRT0_LCD_EN\r
-#define SCSI_Out__3__MASK 0x40u\r
-#define SCSI_Out__3__PC CYREG_PRT0_PC6\r
-#define SCSI_Out__3__PORT 0u\r
-#define SCSI_Out__3__PRT CYREG_PRT0_PRT\r
-#define SCSI_Out__3__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL\r
-#define SCSI_Out__3__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN\r
-#define SCSI_Out__3__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0\r
-#define SCSI_Out__3__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1\r
-#define SCSI_Out__3__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0\r
-#define SCSI_Out__3__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1\r
-#define SCSI_Out__3__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT\r
-#define SCSI_Out__3__PS CYREG_PRT0_PS\r
-#define SCSI_Out__3__SHIFT 6u\r
-#define SCSI_Out__3__SLW CYREG_PRT0_SLW\r
-#define SCSI_Out__4__AG CYREG_PRT0_AG\r
-#define SCSI_Out__4__AMUX CYREG_PRT0_AMUX\r
-#define SCSI_Out__4__BIE CYREG_PRT0_BIE\r
-#define SCSI_Out__4__BIT_MASK CYREG_PRT0_BIT_MASK\r
-#define SCSI_Out__4__BYP CYREG_PRT0_BYP\r
-#define SCSI_Out__4__CTL CYREG_PRT0_CTL\r
-#define SCSI_Out__4__DM0 CYREG_PRT0_DM0\r
-#define SCSI_Out__4__DM1 CYREG_PRT0_DM1\r
-#define SCSI_Out__4__DM2 CYREG_PRT0_DM2\r
-#define SCSI_Out__4__DR CYREG_PRT0_DR\r
-#define SCSI_Out__4__INP_DIS CYREG_PRT0_INP_DIS\r
-#define SCSI_Out__4__INTTYPE CYREG_PICU0_INTTYPE5\r
-#define SCSI_Out__4__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG\r
-#define SCSI_Out__4__LCD_EN CYREG_PRT0_LCD_EN\r
-#define SCSI_Out__4__MASK 0x20u\r
-#define SCSI_Out__4__PC CYREG_PRT0_PC5\r
-#define SCSI_Out__4__PORT 0u\r
-#define SCSI_Out__4__PRT CYREG_PRT0_PRT\r
-#define SCSI_Out__4__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL\r
-#define SCSI_Out__4__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN\r
-#define SCSI_Out__4__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0\r
-#define SCSI_Out__4__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1\r
-#define SCSI_Out__4__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0\r
-#define SCSI_Out__4__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1\r
-#define SCSI_Out__4__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT\r
-#define SCSI_Out__4__PS CYREG_PRT0_PS\r
-#define SCSI_Out__4__SHIFT 5u\r
-#define SCSI_Out__4__SLW CYREG_PRT0_SLW\r
-#define SCSI_Out__5__AG CYREG_PRT0_AG\r
-#define SCSI_Out__5__AMUX CYREG_PRT0_AMUX\r
-#define SCSI_Out__5__BIE CYREG_PRT0_BIE\r
-#define SCSI_Out__5__BIT_MASK CYREG_PRT0_BIT_MASK\r
-#define SCSI_Out__5__BYP CYREG_PRT0_BYP\r
-#define SCSI_Out__5__CTL CYREG_PRT0_CTL\r
-#define SCSI_Out__5__DM0 CYREG_PRT0_DM0\r
-#define SCSI_Out__5__DM1 CYREG_PRT0_DM1\r
-#define SCSI_Out__5__DM2 CYREG_PRT0_DM2\r
-#define SCSI_Out__5__DR CYREG_PRT0_DR\r
-#define SCSI_Out__5__INP_DIS CYREG_PRT0_INP_DIS\r
-#define SCSI_Out__5__INTTYPE CYREG_PICU0_INTTYPE4\r
-#define SCSI_Out__5__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG\r
-#define SCSI_Out__5__LCD_EN CYREG_PRT0_LCD_EN\r
-#define SCSI_Out__5__MASK 0x10u\r
-#define SCSI_Out__5__PC CYREG_PRT0_PC4\r
-#define SCSI_Out__5__PORT 0u\r
-#define SCSI_Out__5__PRT CYREG_PRT0_PRT\r
-#define SCSI_Out__5__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL\r
-#define SCSI_Out__5__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN\r
-#define SCSI_Out__5__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0\r
-#define SCSI_Out__5__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1\r
-#define SCSI_Out__5__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0\r
-#define SCSI_Out__5__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1\r
-#define SCSI_Out__5__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT\r
-#define SCSI_Out__5__PS CYREG_PRT0_PS\r
-#define SCSI_Out__5__SHIFT 4u\r
-#define SCSI_Out__5__SLW CYREG_PRT0_SLW\r
-#define SCSI_Out__6__AG CYREG_PRT0_AG\r
-#define SCSI_Out__6__AMUX CYREG_PRT0_AMUX\r
-#define SCSI_Out__6__BIE CYREG_PRT0_BIE\r
-#define SCSI_Out__6__BIT_MASK CYREG_PRT0_BIT_MASK\r
-#define SCSI_Out__6__BYP CYREG_PRT0_BYP\r
-#define SCSI_Out__6__CTL CYREG_PRT0_CTL\r
-#define SCSI_Out__6__DM0 CYREG_PRT0_DM0\r
-#define SCSI_Out__6__DM1 CYREG_PRT0_DM1\r
-#define SCSI_Out__6__DM2 CYREG_PRT0_DM2\r
-#define SCSI_Out__6__DR CYREG_PRT0_DR\r
-#define SCSI_Out__6__INP_DIS CYREG_PRT0_INP_DIS\r
-#define SCSI_Out__6__INTTYPE CYREG_PICU0_INTTYPE3\r
-#define SCSI_Out__6__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG\r
-#define SCSI_Out__6__LCD_EN CYREG_PRT0_LCD_EN\r
-#define SCSI_Out__6__MASK 0x08u\r
-#define SCSI_Out__6__PC CYREG_PRT0_PC3\r
-#define SCSI_Out__6__PORT 0u\r
-#define SCSI_Out__6__PRT CYREG_PRT0_PRT\r
-#define SCSI_Out__6__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL\r
-#define SCSI_Out__6__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN\r
-#define SCSI_Out__6__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0\r
-#define SCSI_Out__6__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1\r
-#define SCSI_Out__6__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0\r
-#define SCSI_Out__6__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1\r
-#define SCSI_Out__6__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT\r
-#define SCSI_Out__6__PS CYREG_PRT0_PS\r
-#define SCSI_Out__6__SHIFT 3u\r
-#define SCSI_Out__6__SLW CYREG_PRT0_SLW\r
-#define SCSI_Out__7__AG CYREG_PRT0_AG\r
-#define SCSI_Out__7__AMUX CYREG_PRT0_AMUX\r
-#define SCSI_Out__7__BIE CYREG_PRT0_BIE\r
-#define SCSI_Out__7__BIT_MASK CYREG_PRT0_BIT_MASK\r
-#define SCSI_Out__7__BYP CYREG_PRT0_BYP\r
-#define SCSI_Out__7__CTL CYREG_PRT0_CTL\r
-#define SCSI_Out__7__DM0 CYREG_PRT0_DM0\r
-#define SCSI_Out__7__DM1 CYREG_PRT0_DM1\r
-#define SCSI_Out__7__DM2 CYREG_PRT0_DM2\r
-#define SCSI_Out__7__DR CYREG_PRT0_DR\r
-#define SCSI_Out__7__INP_DIS CYREG_PRT0_INP_DIS\r
-#define SCSI_Out__7__INTTYPE CYREG_PICU0_INTTYPE2\r
-#define SCSI_Out__7__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG\r
-#define SCSI_Out__7__LCD_EN CYREG_PRT0_LCD_EN\r
-#define SCSI_Out__7__MASK 0x04u\r
-#define SCSI_Out__7__PC CYREG_PRT0_PC2\r
-#define SCSI_Out__7__PORT 0u\r
-#define SCSI_Out__7__PRT CYREG_PRT0_PRT\r
-#define SCSI_Out__7__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL\r
-#define SCSI_Out__7__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN\r
-#define SCSI_Out__7__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0\r
-#define SCSI_Out__7__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1\r
-#define SCSI_Out__7__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0\r
-#define SCSI_Out__7__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1\r
-#define SCSI_Out__7__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT\r
-#define SCSI_Out__7__PS CYREG_PRT0_PS\r
-#define SCSI_Out__7__SHIFT 2u\r
-#define SCSI_Out__7__SLW CYREG_PRT0_SLW\r
-#define SCSI_Out__8__AG CYREG_PRT0_AG\r
-#define SCSI_Out__8__AMUX CYREG_PRT0_AMUX\r
-#define SCSI_Out__8__BIE CYREG_PRT0_BIE\r
-#define SCSI_Out__8__BIT_MASK CYREG_PRT0_BIT_MASK\r
-#define SCSI_Out__8__BYP CYREG_PRT0_BYP\r
-#define SCSI_Out__8__CTL CYREG_PRT0_CTL\r
-#define SCSI_Out__8__DM0 CYREG_PRT0_DM0\r
-#define SCSI_Out__8__DM1 CYREG_PRT0_DM1\r
-#define SCSI_Out__8__DM2 CYREG_PRT0_DM2\r
-#define SCSI_Out__8__DR CYREG_PRT0_DR\r
-#define SCSI_Out__8__INP_DIS CYREG_PRT0_INP_DIS\r
-#define SCSI_Out__8__INTTYPE CYREG_PICU0_INTTYPE1\r
-#define SCSI_Out__8__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG\r
-#define SCSI_Out__8__LCD_EN CYREG_PRT0_LCD_EN\r
-#define SCSI_Out__8__MASK 0x02u\r
-#define SCSI_Out__8__PC CYREG_PRT0_PC1\r
-#define SCSI_Out__8__PORT 0u\r
-#define SCSI_Out__8__PRT CYREG_PRT0_PRT\r
-#define SCSI_Out__8__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL\r
-#define SCSI_Out__8__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN\r
-#define SCSI_Out__8__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0\r
-#define SCSI_Out__8__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1\r
-#define SCSI_Out__8__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0\r
-#define SCSI_Out__8__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1\r
-#define SCSI_Out__8__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT\r
-#define SCSI_Out__8__PS CYREG_PRT0_PS\r
-#define SCSI_Out__8__SHIFT 1u\r
-#define SCSI_Out__8__SLW CYREG_PRT0_SLW\r
-#define SCSI_Out__9__AG CYREG_PRT0_AG\r
-#define SCSI_Out__9__AMUX CYREG_PRT0_AMUX\r
-#define SCSI_Out__9__BIE CYREG_PRT0_BIE\r
-#define SCSI_Out__9__BIT_MASK CYREG_PRT0_BIT_MASK\r
-#define SCSI_Out__9__BYP CYREG_PRT0_BYP\r
-#define SCSI_Out__9__CTL CYREG_PRT0_CTL\r
-#define SCSI_Out__9__DM0 CYREG_PRT0_DM0\r
-#define SCSI_Out__9__DM1 CYREG_PRT0_DM1\r
-#define SCSI_Out__9__DM2 CYREG_PRT0_DM2\r
-#define SCSI_Out__9__DR CYREG_PRT0_DR\r
-#define SCSI_Out__9__INP_DIS CYREG_PRT0_INP_DIS\r
-#define SCSI_Out__9__INTTYPE CYREG_PICU0_INTTYPE0\r
-#define SCSI_Out__9__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG\r
-#define SCSI_Out__9__LCD_EN CYREG_PRT0_LCD_EN\r
-#define SCSI_Out__9__MASK 0x01u\r
-#define SCSI_Out__9__PC CYREG_PRT0_PC0\r
-#define SCSI_Out__9__PORT 0u\r
-#define SCSI_Out__9__PRT CYREG_PRT0_PRT\r
-#define SCSI_Out__9__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL\r
-#define SCSI_Out__9__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN\r
-#define SCSI_Out__9__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0\r
-#define SCSI_Out__9__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1\r
-#define SCSI_Out__9__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0\r
-#define SCSI_Out__9__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1\r
-#define SCSI_Out__9__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT\r
-#define SCSI_Out__9__PS CYREG_PRT0_PS\r
-#define SCSI_Out__9__SHIFT 0u\r
-#define SCSI_Out__9__SLW CYREG_PRT0_SLW\r
-#define SCSI_Out__ACK__AG CYREG_PRT0_AG\r
-#define SCSI_Out__ACK__AMUX CYREG_PRT0_AMUX\r
-#define SCSI_Out__ACK__BIE CYREG_PRT0_BIE\r
-#define SCSI_Out__ACK__BIT_MASK CYREG_PRT0_BIT_MASK\r
-#define SCSI_Out__ACK__BYP CYREG_PRT0_BYP\r
-#define SCSI_Out__ACK__CTL CYREG_PRT0_CTL\r
-#define SCSI_Out__ACK__DM0 CYREG_PRT0_DM0\r
-#define SCSI_Out__ACK__DM1 CYREG_PRT0_DM1\r
-#define SCSI_Out__ACK__DM2 CYREG_PRT0_DM2\r
-#define SCSI_Out__ACK__DR CYREG_PRT0_DR\r
-#define SCSI_Out__ACK__INP_DIS CYREG_PRT0_INP_DIS\r
-#define SCSI_Out__ACK__INTTYPE CYREG_PICU0_INTTYPE6\r
-#define SCSI_Out__ACK__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG\r
-#define SCSI_Out__ACK__LCD_EN CYREG_PRT0_LCD_EN\r
-#define SCSI_Out__ACK__MASK 0x40u\r
-#define SCSI_Out__ACK__PC CYREG_PRT0_PC6\r
-#define SCSI_Out__ACK__PORT 0u\r
-#define SCSI_Out__ACK__PRT CYREG_PRT0_PRT\r
-#define SCSI_Out__ACK__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL\r
-#define SCSI_Out__ACK__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN\r
-#define SCSI_Out__ACK__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0\r
-#define SCSI_Out__ACK__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1\r
-#define SCSI_Out__ACK__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0\r
-#define SCSI_Out__ACK__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1\r
-#define SCSI_Out__ACK__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT\r
-#define SCSI_Out__ACK__PS CYREG_PRT0_PS\r
-#define SCSI_Out__ACK__SHIFT 6u\r
-#define SCSI_Out__ACK__SLW CYREG_PRT0_SLW\r
-#define SCSI_Out__ATN__AG CYREG_PRT4_AG\r
-#define SCSI_Out__ATN__AMUX CYREG_PRT4_AMUX\r
-#define SCSI_Out__ATN__BIE CYREG_PRT4_BIE\r
-#define SCSI_Out__ATN__BIT_MASK CYREG_PRT4_BIT_MASK\r
-#define SCSI_Out__ATN__BYP CYREG_PRT4_BYP\r
-#define SCSI_Out__ATN__CTL CYREG_PRT4_CTL\r
-#define SCSI_Out__ATN__DM0 CYREG_PRT4_DM0\r
-#define SCSI_Out__ATN__DM1 CYREG_PRT4_DM1\r
-#define SCSI_Out__ATN__DM2 CYREG_PRT4_DM2\r
-#define SCSI_Out__ATN__DR CYREG_PRT4_DR\r
-#define SCSI_Out__ATN__INP_DIS CYREG_PRT4_INP_DIS\r
-#define SCSI_Out__ATN__INTTYPE CYREG_PICU4_INTTYPE2\r
-#define SCSI_Out__ATN__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG\r
-#define SCSI_Out__ATN__LCD_EN CYREG_PRT4_LCD_EN\r
-#define SCSI_Out__ATN__MASK 0x04u\r
-#define SCSI_Out__ATN__PC CYREG_PRT4_PC2\r
-#define SCSI_Out__ATN__PORT 4u\r
-#define SCSI_Out__ATN__PRT CYREG_PRT4_PRT\r
-#define SCSI_Out__ATN__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL\r
-#define SCSI_Out__ATN__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN\r
-#define SCSI_Out__ATN__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0\r
-#define SCSI_Out__ATN__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1\r
-#define SCSI_Out__ATN__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0\r
-#define SCSI_Out__ATN__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1\r
-#define SCSI_Out__ATN__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT\r
-#define SCSI_Out__ATN__PS CYREG_PRT4_PS\r
-#define SCSI_Out__ATN__SHIFT 2u\r
-#define SCSI_Out__ATN__SLW CYREG_PRT4_SLW\r
-#define SCSI_Out__BSY__AG CYREG_PRT0_AG\r
-#define SCSI_Out__BSY__AMUX CYREG_PRT0_AMUX\r
-#define SCSI_Out__BSY__BIE CYREG_PRT0_BIE\r
-#define SCSI_Out__BSY__BIT_MASK CYREG_PRT0_BIT_MASK\r
-#define SCSI_Out__BSY__BYP CYREG_PRT0_BYP\r
-#define SCSI_Out__BSY__CTL CYREG_PRT0_CTL\r
-#define SCSI_Out__BSY__DM0 CYREG_PRT0_DM0\r
-#define SCSI_Out__BSY__DM1 CYREG_PRT0_DM1\r
-#define SCSI_Out__BSY__DM2 CYREG_PRT0_DM2\r
-#define SCSI_Out__BSY__DR CYREG_PRT0_DR\r
-#define SCSI_Out__BSY__INP_DIS CYREG_PRT0_INP_DIS\r
-#define SCSI_Out__BSY__INTTYPE CYREG_PICU0_INTTYPE7\r
-#define SCSI_Out__BSY__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG\r
-#define SCSI_Out__BSY__LCD_EN CYREG_PRT0_LCD_EN\r
-#define SCSI_Out__BSY__MASK 0x80u\r
-#define SCSI_Out__BSY__PC CYREG_PRT0_PC7\r
-#define SCSI_Out__BSY__PORT 0u\r
-#define SCSI_Out__BSY__PRT CYREG_PRT0_PRT\r
-#define SCSI_Out__BSY__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL\r
-#define SCSI_Out__BSY__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN\r
-#define SCSI_Out__BSY__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0\r
-#define SCSI_Out__BSY__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1\r
-#define SCSI_Out__BSY__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0\r
-#define SCSI_Out__BSY__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1\r
-#define SCSI_Out__BSY__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT\r
-#define SCSI_Out__BSY__PS CYREG_PRT0_PS\r
-#define SCSI_Out__BSY__SHIFT 7u\r
-#define SCSI_Out__BSY__SLW CYREG_PRT0_SLW\r
-#define SCSI_Out__CD_raw__AG CYREG_PRT0_AG\r
-#define SCSI_Out__CD_raw__AMUX CYREG_PRT0_AMUX\r
-#define SCSI_Out__CD_raw__BIE CYREG_PRT0_BIE\r
-#define SCSI_Out__CD_raw__BIT_MASK CYREG_PRT0_BIT_MASK\r
-#define SCSI_Out__CD_raw__BYP CYREG_PRT0_BYP\r
-#define SCSI_Out__CD_raw__CTL CYREG_PRT0_CTL\r
-#define SCSI_Out__CD_raw__DM0 CYREG_PRT0_DM0\r
-#define SCSI_Out__CD_raw__DM1 CYREG_PRT0_DM1\r
-#define SCSI_Out__CD_raw__DM2 CYREG_PRT0_DM2\r
-#define SCSI_Out__CD_raw__DR CYREG_PRT0_DR\r
-#define SCSI_Out__CD_raw__INP_DIS CYREG_PRT0_INP_DIS\r
-#define SCSI_Out__CD_raw__INTTYPE CYREG_PICU0_INTTYPE2\r
-#define SCSI_Out__CD_raw__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG\r
-#define SCSI_Out__CD_raw__LCD_EN CYREG_PRT0_LCD_EN\r
-#define SCSI_Out__CD_raw__MASK 0x04u\r
-#define SCSI_Out__CD_raw__PC CYREG_PRT0_PC2\r
-#define SCSI_Out__CD_raw__PORT 0u\r
-#define SCSI_Out__CD_raw__PRT CYREG_PRT0_PRT\r
-#define SCSI_Out__CD_raw__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL\r
-#define SCSI_Out__CD_raw__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN\r
-#define SCSI_Out__CD_raw__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0\r
-#define SCSI_Out__CD_raw__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1\r
-#define SCSI_Out__CD_raw__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0\r
-#define SCSI_Out__CD_raw__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1\r
-#define SCSI_Out__CD_raw__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT\r
-#define SCSI_Out__CD_raw__PS CYREG_PRT0_PS\r
-#define SCSI_Out__CD_raw__SHIFT 2u\r
-#define SCSI_Out__CD_raw__SLW CYREG_PRT0_SLW\r
-#define SCSI_Out__DBP_raw__AG CYREG_PRT4_AG\r
-#define SCSI_Out__DBP_raw__AMUX CYREG_PRT4_AMUX\r
-#define SCSI_Out__DBP_raw__BIE CYREG_PRT4_BIE\r
-#define SCSI_Out__DBP_raw__BIT_MASK CYREG_PRT4_BIT_MASK\r
-#define SCSI_Out__DBP_raw__BYP CYREG_PRT4_BYP\r
-#define SCSI_Out__DBP_raw__CTL CYREG_PRT4_CTL\r
-#define SCSI_Out__DBP_raw__DM0 CYREG_PRT4_DM0\r
-#define SCSI_Out__DBP_raw__DM1 CYREG_PRT4_DM1\r
-#define SCSI_Out__DBP_raw__DM2 CYREG_PRT4_DM2\r
-#define SCSI_Out__DBP_raw__DR CYREG_PRT4_DR\r
-#define SCSI_Out__DBP_raw__INP_DIS CYREG_PRT4_INP_DIS\r
-#define SCSI_Out__DBP_raw__INTTYPE CYREG_PICU4_INTTYPE3\r
-#define SCSI_Out__DBP_raw__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG\r
-#define SCSI_Out__DBP_raw__LCD_EN CYREG_PRT4_LCD_EN\r
-#define SCSI_Out__DBP_raw__MASK 0x08u\r
-#define SCSI_Out__DBP_raw__PC CYREG_PRT4_PC3\r
-#define SCSI_Out__DBP_raw__PORT 4u\r
-#define SCSI_Out__DBP_raw__PRT CYREG_PRT4_PRT\r
-#define SCSI_Out__DBP_raw__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL\r
-#define SCSI_Out__DBP_raw__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN\r
-#define SCSI_Out__DBP_raw__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0\r
-#define SCSI_Out__DBP_raw__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1\r
-#define SCSI_Out__DBP_raw__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0\r
-#define SCSI_Out__DBP_raw__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1\r
-#define SCSI_Out__DBP_raw__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT\r
-#define SCSI_Out__DBP_raw__PS CYREG_PRT4_PS\r
-#define SCSI_Out__DBP_raw__SHIFT 3u\r
-#define SCSI_Out__DBP_raw__SLW CYREG_PRT4_SLW\r
-#define SCSI_Out__IO_raw__AG CYREG_PRT0_AG\r
-#define SCSI_Out__IO_raw__AMUX CYREG_PRT0_AMUX\r
-#define SCSI_Out__IO_raw__BIE CYREG_PRT0_BIE\r
-#define SCSI_Out__IO_raw__BIT_MASK CYREG_PRT0_BIT_MASK\r
-#define SCSI_Out__IO_raw__BYP CYREG_PRT0_BYP\r
-#define SCSI_Out__IO_raw__CTL CYREG_PRT0_CTL\r
-#define SCSI_Out__IO_raw__DM0 CYREG_PRT0_DM0\r
-#define SCSI_Out__IO_raw__DM1 CYREG_PRT0_DM1\r
-#define SCSI_Out__IO_raw__DM2 CYREG_PRT0_DM2\r
-#define SCSI_Out__IO_raw__DR CYREG_PRT0_DR\r
-#define SCSI_Out__IO_raw__INP_DIS CYREG_PRT0_INP_DIS\r
-#define SCSI_Out__IO_raw__INTTYPE CYREG_PICU0_INTTYPE0\r
-#define SCSI_Out__IO_raw__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG\r
-#define SCSI_Out__IO_raw__LCD_EN CYREG_PRT0_LCD_EN\r
-#define SCSI_Out__IO_raw__MASK 0x01u\r
-#define SCSI_Out__IO_raw__PC CYREG_PRT0_PC0\r
-#define SCSI_Out__IO_raw__PORT 0u\r
-#define SCSI_Out__IO_raw__PRT CYREG_PRT0_PRT\r
-#define SCSI_Out__IO_raw__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL\r
-#define SCSI_Out__IO_raw__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN\r
-#define SCSI_Out__IO_raw__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0\r
-#define SCSI_Out__IO_raw__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1\r
-#define SCSI_Out__IO_raw__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0\r
-#define SCSI_Out__IO_raw__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1\r
-#define SCSI_Out__IO_raw__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT\r
-#define SCSI_Out__IO_raw__PS CYREG_PRT0_PS\r
-#define SCSI_Out__IO_raw__SHIFT 0u\r
-#define SCSI_Out__IO_raw__SLW CYREG_PRT0_SLW\r
-#define SCSI_Out__MSG_raw__AG CYREG_PRT0_AG\r
-#define SCSI_Out__MSG_raw__AMUX CYREG_PRT0_AMUX\r
-#define SCSI_Out__MSG_raw__BIE CYREG_PRT0_BIE\r
-#define SCSI_Out__MSG_raw__BIT_MASK CYREG_PRT0_BIT_MASK\r
-#define SCSI_Out__MSG_raw__BYP CYREG_PRT0_BYP\r
-#define SCSI_Out__MSG_raw__CTL CYREG_PRT0_CTL\r
-#define SCSI_Out__MSG_raw__DM0 CYREG_PRT0_DM0\r
-#define SCSI_Out__MSG_raw__DM1 CYREG_PRT0_DM1\r
-#define SCSI_Out__MSG_raw__DM2 CYREG_PRT0_DM2\r
-#define SCSI_Out__MSG_raw__DR CYREG_PRT0_DR\r
-#define SCSI_Out__MSG_raw__INP_DIS CYREG_PRT0_INP_DIS\r
-#define SCSI_Out__MSG_raw__INTTYPE CYREG_PICU0_INTTYPE4\r
-#define SCSI_Out__MSG_raw__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG\r
-#define SCSI_Out__MSG_raw__LCD_EN CYREG_PRT0_LCD_EN\r
-#define SCSI_Out__MSG_raw__MASK 0x10u\r
-#define SCSI_Out__MSG_raw__PC CYREG_PRT0_PC4\r
-#define SCSI_Out__MSG_raw__PORT 0u\r
-#define SCSI_Out__MSG_raw__PRT CYREG_PRT0_PRT\r
-#define SCSI_Out__MSG_raw__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL\r
-#define SCSI_Out__MSG_raw__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN\r
-#define SCSI_Out__MSG_raw__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0\r
-#define SCSI_Out__MSG_raw__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1\r
-#define SCSI_Out__MSG_raw__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0\r
-#define SCSI_Out__MSG_raw__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1\r
-#define SCSI_Out__MSG_raw__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT\r
-#define SCSI_Out__MSG_raw__PS CYREG_PRT0_PS\r
-#define SCSI_Out__MSG_raw__SHIFT 4u\r
-#define SCSI_Out__MSG_raw__SLW CYREG_PRT0_SLW\r
-#define SCSI_Out__REQ__AG CYREG_PRT0_AG\r
-#define SCSI_Out__REQ__AMUX CYREG_PRT0_AMUX\r
-#define SCSI_Out__REQ__BIE CYREG_PRT0_BIE\r
-#define SCSI_Out__REQ__BIT_MASK CYREG_PRT0_BIT_MASK\r
-#define SCSI_Out__REQ__BYP CYREG_PRT0_BYP\r
-#define SCSI_Out__REQ__CTL CYREG_PRT0_CTL\r
-#define SCSI_Out__REQ__DM0 CYREG_PRT0_DM0\r
-#define SCSI_Out__REQ__DM1 CYREG_PRT0_DM1\r
-#define SCSI_Out__REQ__DM2 CYREG_PRT0_DM2\r
-#define SCSI_Out__REQ__DR CYREG_PRT0_DR\r
-#define SCSI_Out__REQ__INP_DIS CYREG_PRT0_INP_DIS\r
-#define SCSI_Out__REQ__INTTYPE CYREG_PICU0_INTTYPE1\r
-#define SCSI_Out__REQ__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG\r
-#define SCSI_Out__REQ__LCD_EN CYREG_PRT0_LCD_EN\r
-#define SCSI_Out__REQ__MASK 0x02u\r
-#define SCSI_Out__REQ__PC CYREG_PRT0_PC1\r
-#define SCSI_Out__REQ__PORT 0u\r
-#define SCSI_Out__REQ__PRT CYREG_PRT0_PRT\r
-#define SCSI_Out__REQ__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL\r
-#define SCSI_Out__REQ__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN\r
-#define SCSI_Out__REQ__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0\r
-#define SCSI_Out__REQ__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1\r
-#define SCSI_Out__REQ__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0\r
-#define SCSI_Out__REQ__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1\r
-#define SCSI_Out__REQ__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT\r
-#define SCSI_Out__REQ__PS CYREG_PRT0_PS\r
-#define SCSI_Out__REQ__SHIFT 1u\r
-#define SCSI_Out__REQ__SLW CYREG_PRT0_SLW\r
-#define SCSI_Out__RST__AG CYREG_PRT0_AG\r
-#define SCSI_Out__RST__AMUX CYREG_PRT0_AMUX\r
-#define SCSI_Out__RST__BIE CYREG_PRT0_BIE\r
-#define SCSI_Out__RST__BIT_MASK CYREG_PRT0_BIT_MASK\r
-#define SCSI_Out__RST__BYP CYREG_PRT0_BYP\r
-#define SCSI_Out__RST__CTL CYREG_PRT0_CTL\r
-#define SCSI_Out__RST__DM0 CYREG_PRT0_DM0\r
-#define SCSI_Out__RST__DM1 CYREG_PRT0_DM1\r
-#define SCSI_Out__RST__DM2 CYREG_PRT0_DM2\r
-#define SCSI_Out__RST__DR CYREG_PRT0_DR\r
-#define SCSI_Out__RST__INP_DIS CYREG_PRT0_INP_DIS\r
-#define SCSI_Out__RST__INTTYPE CYREG_PICU0_INTTYPE5\r
-#define SCSI_Out__RST__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG\r
-#define SCSI_Out__RST__LCD_EN CYREG_PRT0_LCD_EN\r
-#define SCSI_Out__RST__MASK 0x20u\r
-#define SCSI_Out__RST__PC CYREG_PRT0_PC5\r
-#define SCSI_Out__RST__PORT 0u\r
-#define SCSI_Out__RST__PRT CYREG_PRT0_PRT\r
-#define SCSI_Out__RST__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL\r
-#define SCSI_Out__RST__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN\r
-#define SCSI_Out__RST__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0\r
-#define SCSI_Out__RST__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1\r
-#define SCSI_Out__RST__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0\r
-#define SCSI_Out__RST__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1\r
-#define SCSI_Out__RST__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT\r
-#define SCSI_Out__RST__PS CYREG_PRT0_PS\r
-#define SCSI_Out__RST__SHIFT 5u\r
-#define SCSI_Out__RST__SLW CYREG_PRT0_SLW\r
-#define SCSI_Out__SEL__AG CYREG_PRT0_AG\r
-#define SCSI_Out__SEL__AMUX CYREG_PRT0_AMUX\r
-#define SCSI_Out__SEL__BIE CYREG_PRT0_BIE\r
-#define SCSI_Out__SEL__BIT_MASK CYREG_PRT0_BIT_MASK\r
-#define SCSI_Out__SEL__BYP CYREG_PRT0_BYP\r
-#define SCSI_Out__SEL__CTL CYREG_PRT0_CTL\r
-#define SCSI_Out__SEL__DM0 CYREG_PRT0_DM0\r
-#define SCSI_Out__SEL__DM1 CYREG_PRT0_DM1\r
-#define SCSI_Out__SEL__DM2 CYREG_PRT0_DM2\r
-#define SCSI_Out__SEL__DR CYREG_PRT0_DR\r
-#define SCSI_Out__SEL__INP_DIS CYREG_PRT0_INP_DIS\r
-#define SCSI_Out__SEL__INTTYPE CYREG_PICU0_INTTYPE3\r
-#define SCSI_Out__SEL__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG\r
-#define SCSI_Out__SEL__LCD_EN CYREG_PRT0_LCD_EN\r
-#define SCSI_Out__SEL__MASK 0x08u\r
-#define SCSI_Out__SEL__PC CYREG_PRT0_PC3\r
-#define SCSI_Out__SEL__PORT 0u\r
-#define SCSI_Out__SEL__PRT CYREG_PRT0_PRT\r
-#define SCSI_Out__SEL__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL\r
-#define SCSI_Out__SEL__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN\r
-#define SCSI_Out__SEL__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0\r
-#define SCSI_Out__SEL__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1\r
-#define SCSI_Out__SEL__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0\r
-#define SCSI_Out__SEL__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1\r
-#define SCSI_Out__SEL__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT\r
-#define SCSI_Out__SEL__PS CYREG_PRT0_PS\r
-#define SCSI_Out__SEL__SHIFT 3u\r
-#define SCSI_Out__SEL__SLW CYREG_PRT0_SLW\r
-\r
-/* SCSI_Out_Bits */\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__0__MASK 0x01u\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__0__POS 0\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__1__MASK 0x02u\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__1__POS 1\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB08_09_ACTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB08_09_CTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB08_09_CTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB08_09_CTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B1_UDB08_09_CTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B1_UDB08_09_MSK\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B1_UDB08_09_MSK\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B1_UDB08_09_MSK\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB08_09_MSK\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__2__MASK 0x04u\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__2__POS 2\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__3__MASK 0x08u\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__3__POS 3\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__4__MASK 0x10u\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__4__POS 4\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__5__MASK 0x20u\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__5__POS 5\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__6__MASK 0x40u\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__6__POS 6\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__7__MASK 0x80u\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__7__POS 7\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B1_UDB08_ACTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG CYREG_B1_UDB08_CTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B1_UDB08_ST_CTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG CYREG_B1_UDB08_CTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG CYREG_B1_UDB08_ST_CTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__MASK 0xFFu\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB08_MSK_ACTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B1_UDB08_MSK_ACTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG CYREG_B1_UDB08_MSK\r
-\r
-/* SCSI_Out_Ctl */\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK 0x01u\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__0__POS 0\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB08_09_ACTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB08_09_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB08_09_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB08_09_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB08_09_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB08_09_MSK\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB08_09_MSK\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB08_09_MSK\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB08_09_MSK\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB08_ACTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB08_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB08_ST_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB08_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB08_ST_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK 0x01u\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB08_MSK\r
-\r
-/* SCSI_Out_DBx */\r
-#define SCSI_Out_DBx__0__AG CYREG_PRT6_AG\r
-#define SCSI_Out_DBx__0__AMUX CYREG_PRT6_AMUX\r
-#define SCSI_Out_DBx__0__BIE CYREG_PRT6_BIE\r
-#define SCSI_Out_DBx__0__BIT_MASK CYREG_PRT6_BIT_MASK\r
-#define SCSI_Out_DBx__0__BYP CYREG_PRT6_BYP\r
-#define SCSI_Out_DBx__0__CTL CYREG_PRT6_CTL\r
-#define SCSI_Out_DBx__0__DM0 CYREG_PRT6_DM0\r
-#define SCSI_Out_DBx__0__DM1 CYREG_PRT6_DM1\r
-#define SCSI_Out_DBx__0__DM2 CYREG_PRT6_DM2\r
-#define SCSI_Out_DBx__0__DR CYREG_PRT6_DR\r
-#define SCSI_Out_DBx__0__INP_DIS CYREG_PRT6_INP_DIS\r
-#define SCSI_Out_DBx__0__INTTYPE CYREG_PICU6_INTTYPE3\r
-#define SCSI_Out_DBx__0__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
-#define SCSI_Out_DBx__0__LCD_EN CYREG_PRT6_LCD_EN\r
-#define SCSI_Out_DBx__0__MASK 0x08u\r
-#define SCSI_Out_DBx__0__PC CYREG_PRT6_PC3\r
-#define SCSI_Out_DBx__0__PORT 6u\r
-#define SCSI_Out_DBx__0__PRT CYREG_PRT6_PRT\r
-#define SCSI_Out_DBx__0__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
-#define SCSI_Out_DBx__0__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
-#define SCSI_Out_DBx__0__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
-#define SCSI_Out_DBx__0__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
-#define SCSI_Out_DBx__0__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
-#define SCSI_Out_DBx__0__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
-#define SCSI_Out_DBx__0__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
-#define SCSI_Out_DBx__0__PS CYREG_PRT6_PS\r
-#define SCSI_Out_DBx__0__SHIFT 3u\r
-#define SCSI_Out_DBx__0__SLW CYREG_PRT6_SLW\r
-#define SCSI_Out_DBx__1__AG CYREG_PRT6_AG\r
-#define SCSI_Out_DBx__1__AMUX CYREG_PRT6_AMUX\r
-#define SCSI_Out_DBx__1__BIE CYREG_PRT6_BIE\r
-#define SCSI_Out_DBx__1__BIT_MASK CYREG_PRT6_BIT_MASK\r
-#define SCSI_Out_DBx__1__BYP CYREG_PRT6_BYP\r
-#define SCSI_Out_DBx__1__CTL CYREG_PRT6_CTL\r
-#define SCSI_Out_DBx__1__DM0 CYREG_PRT6_DM0\r
-#define SCSI_Out_DBx__1__DM1 CYREG_PRT6_DM1\r
-#define SCSI_Out_DBx__1__DM2 CYREG_PRT6_DM2\r
-#define SCSI_Out_DBx__1__DR CYREG_PRT6_DR\r
-#define SCSI_Out_DBx__1__INP_DIS CYREG_PRT6_INP_DIS\r
-#define SCSI_Out_DBx__1__INTTYPE CYREG_PICU6_INTTYPE2\r
-#define SCSI_Out_DBx__1__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
-#define SCSI_Out_DBx__1__LCD_EN CYREG_PRT6_LCD_EN\r
-#define SCSI_Out_DBx__1__MASK 0x04u\r
-#define SCSI_Out_DBx__1__PC CYREG_PRT6_PC2\r
-#define SCSI_Out_DBx__1__PORT 6u\r
-#define SCSI_Out_DBx__1__PRT CYREG_PRT6_PRT\r
-#define SCSI_Out_DBx__1__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
-#define SCSI_Out_DBx__1__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
-#define SCSI_Out_DBx__1__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
-#define SCSI_Out_DBx__1__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
-#define SCSI_Out_DBx__1__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
-#define SCSI_Out_DBx__1__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
-#define SCSI_Out_DBx__1__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
-#define SCSI_Out_DBx__1__PS CYREG_PRT6_PS\r
-#define SCSI_Out_DBx__1__SHIFT 2u\r
-#define SCSI_Out_DBx__1__SLW CYREG_PRT6_SLW\r
-#define SCSI_Out_DBx__2__AG CYREG_PRT6_AG\r
-#define SCSI_Out_DBx__2__AMUX CYREG_PRT6_AMUX\r
-#define SCSI_Out_DBx__2__BIE CYREG_PRT6_BIE\r
-#define SCSI_Out_DBx__2__BIT_MASK CYREG_PRT6_BIT_MASK\r
-#define SCSI_Out_DBx__2__BYP CYREG_PRT6_BYP\r
-#define SCSI_Out_DBx__2__CTL CYREG_PRT6_CTL\r
-#define SCSI_Out_DBx__2__DM0 CYREG_PRT6_DM0\r
-#define SCSI_Out_DBx__2__DM1 CYREG_PRT6_DM1\r
-#define SCSI_Out_DBx__2__DM2 CYREG_PRT6_DM2\r
-#define SCSI_Out_DBx__2__DR CYREG_PRT6_DR\r
-#define SCSI_Out_DBx__2__INP_DIS CYREG_PRT6_INP_DIS\r
-#define SCSI_Out_DBx__2__INTTYPE CYREG_PICU6_INTTYPE1\r
-#define SCSI_Out_DBx__2__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
-#define SCSI_Out_DBx__2__LCD_EN CYREG_PRT6_LCD_EN\r
-#define SCSI_Out_DBx__2__MASK 0x02u\r
-#define SCSI_Out_DBx__2__PC CYREG_PRT6_PC1\r
-#define SCSI_Out_DBx__2__PORT 6u\r
-#define SCSI_Out_DBx__2__PRT CYREG_PRT6_PRT\r
-#define SCSI_Out_DBx__2__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
-#define SCSI_Out_DBx__2__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
-#define SCSI_Out_DBx__2__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
-#define SCSI_Out_DBx__2__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
-#define SCSI_Out_DBx__2__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
-#define SCSI_Out_DBx__2__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
-#define SCSI_Out_DBx__2__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
-#define SCSI_Out_DBx__2__PS CYREG_PRT6_PS\r
-#define SCSI_Out_DBx__2__SHIFT 1u\r
-#define SCSI_Out_DBx__2__SLW CYREG_PRT6_SLW\r
-#define SCSI_Out_DBx__3__AG CYREG_PRT6_AG\r
-#define SCSI_Out_DBx__3__AMUX CYREG_PRT6_AMUX\r
-#define SCSI_Out_DBx__3__BIE CYREG_PRT6_BIE\r
-#define SCSI_Out_DBx__3__BIT_MASK CYREG_PRT6_BIT_MASK\r
-#define SCSI_Out_DBx__3__BYP CYREG_PRT6_BYP\r
-#define SCSI_Out_DBx__3__CTL CYREG_PRT6_CTL\r
-#define SCSI_Out_DBx__3__DM0 CYREG_PRT6_DM0\r
-#define SCSI_Out_DBx__3__DM1 CYREG_PRT6_DM1\r
-#define SCSI_Out_DBx__3__DM2 CYREG_PRT6_DM2\r
-#define SCSI_Out_DBx__3__DR CYREG_PRT6_DR\r
-#define SCSI_Out_DBx__3__INP_DIS CYREG_PRT6_INP_DIS\r
-#define SCSI_Out_DBx__3__INTTYPE CYREG_PICU6_INTTYPE0\r
-#define SCSI_Out_DBx__3__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
-#define SCSI_Out_DBx__3__LCD_EN CYREG_PRT6_LCD_EN\r
-#define SCSI_Out_DBx__3__MASK 0x01u\r
-#define SCSI_Out_DBx__3__PC CYREG_PRT6_PC0\r
-#define SCSI_Out_DBx__3__PORT 6u\r
-#define SCSI_Out_DBx__3__PRT CYREG_PRT6_PRT\r
-#define SCSI_Out_DBx__3__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
-#define SCSI_Out_DBx__3__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
-#define SCSI_Out_DBx__3__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
-#define SCSI_Out_DBx__3__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
-#define SCSI_Out_DBx__3__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
-#define SCSI_Out_DBx__3__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
-#define SCSI_Out_DBx__3__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
-#define SCSI_Out_DBx__3__PS CYREG_PRT6_PS\r
-#define SCSI_Out_DBx__3__SHIFT 0u\r
-#define SCSI_Out_DBx__3__SLW CYREG_PRT6_SLW\r
-#define SCSI_Out_DBx__4__AG CYREG_PRT4_AG\r
-#define SCSI_Out_DBx__4__AMUX CYREG_PRT4_AMUX\r
-#define SCSI_Out_DBx__4__BIE CYREG_PRT4_BIE\r
-#define SCSI_Out_DBx__4__BIT_MASK CYREG_PRT4_BIT_MASK\r
-#define SCSI_Out_DBx__4__BYP CYREG_PRT4_BYP\r
-#define SCSI_Out_DBx__4__CTL CYREG_PRT4_CTL\r
-#define SCSI_Out_DBx__4__DM0 CYREG_PRT4_DM0\r
-#define SCSI_Out_DBx__4__DM1 CYREG_PRT4_DM1\r
-#define SCSI_Out_DBx__4__DM2 CYREG_PRT4_DM2\r
-#define SCSI_Out_DBx__4__DR CYREG_PRT4_DR\r
-#define SCSI_Out_DBx__4__INP_DIS CYREG_PRT4_INP_DIS\r
-#define SCSI_Out_DBx__4__INTTYPE CYREG_PICU4_INTTYPE7\r
-#define SCSI_Out_DBx__4__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG\r
-#define SCSI_Out_DBx__4__LCD_EN CYREG_PRT4_LCD_EN\r
-#define SCSI_Out_DBx__4__MASK 0x80u\r
-#define SCSI_Out_DBx__4__PC CYREG_PRT4_PC7\r
-#define SCSI_Out_DBx__4__PORT 4u\r
-#define SCSI_Out_DBx__4__PRT CYREG_PRT4_PRT\r
-#define SCSI_Out_DBx__4__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL\r
-#define SCSI_Out_DBx__4__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN\r
-#define SCSI_Out_DBx__4__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0\r
-#define SCSI_Out_DBx__4__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1\r
-#define SCSI_Out_DBx__4__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0\r
-#define SCSI_Out_DBx__4__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1\r
-#define SCSI_Out_DBx__4__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT\r
-#define SCSI_Out_DBx__4__PS CYREG_PRT4_PS\r
-#define SCSI_Out_DBx__4__SHIFT 7u\r
-#define SCSI_Out_DBx__4__SLW CYREG_PRT4_SLW\r
-#define SCSI_Out_DBx__5__AG CYREG_PRT4_AG\r
-#define SCSI_Out_DBx__5__AMUX CYREG_PRT4_AMUX\r
-#define SCSI_Out_DBx__5__BIE CYREG_PRT4_BIE\r
-#define SCSI_Out_DBx__5__BIT_MASK CYREG_PRT4_BIT_MASK\r
-#define SCSI_Out_DBx__5__BYP CYREG_PRT4_BYP\r
-#define SCSI_Out_DBx__5__CTL CYREG_PRT4_CTL\r
-#define SCSI_Out_DBx__5__DM0 CYREG_PRT4_DM0\r
-#define SCSI_Out_DBx__5__DM1 CYREG_PRT4_DM1\r
-#define SCSI_Out_DBx__5__DM2 CYREG_PRT4_DM2\r
-#define SCSI_Out_DBx__5__DR CYREG_PRT4_DR\r
-#define SCSI_Out_DBx__5__INP_DIS CYREG_PRT4_INP_DIS\r
-#define SCSI_Out_DBx__5__INTTYPE CYREG_PICU4_INTTYPE6\r
-#define SCSI_Out_DBx__5__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG\r
-#define SCSI_Out_DBx__5__LCD_EN CYREG_PRT4_LCD_EN\r
-#define SCSI_Out_DBx__5__MASK 0x40u\r
-#define SCSI_Out_DBx__5__PC CYREG_PRT4_PC6\r
-#define SCSI_Out_DBx__5__PORT 4u\r
-#define SCSI_Out_DBx__5__PRT CYREG_PRT4_PRT\r
-#define SCSI_Out_DBx__5__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL\r
-#define SCSI_Out_DBx__5__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN\r
-#define SCSI_Out_DBx__5__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0\r
-#define SCSI_Out_DBx__5__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1\r
-#define SCSI_Out_DBx__5__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0\r
-#define SCSI_Out_DBx__5__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1\r
-#define SCSI_Out_DBx__5__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT\r
-#define SCSI_Out_DBx__5__PS CYREG_PRT4_PS\r
-#define SCSI_Out_DBx__5__SHIFT 6u\r
-#define SCSI_Out_DBx__5__SLW CYREG_PRT4_SLW\r
-#define SCSI_Out_DBx__6__AG CYREG_PRT4_AG\r
-#define SCSI_Out_DBx__6__AMUX CYREG_PRT4_AMUX\r
-#define SCSI_Out_DBx__6__BIE CYREG_PRT4_BIE\r
-#define SCSI_Out_DBx__6__BIT_MASK CYREG_PRT4_BIT_MASK\r
-#define SCSI_Out_DBx__6__BYP CYREG_PRT4_BYP\r
-#define SCSI_Out_DBx__6__CTL CYREG_PRT4_CTL\r
-#define SCSI_Out_DBx__6__DM0 CYREG_PRT4_DM0\r
-#define SCSI_Out_DBx__6__DM1 CYREG_PRT4_DM1\r
-#define SCSI_Out_DBx__6__DM2 CYREG_PRT4_DM2\r
-#define SCSI_Out_DBx__6__DR CYREG_PRT4_DR\r
-#define SCSI_Out_DBx__6__INP_DIS CYREG_PRT4_INP_DIS\r
-#define SCSI_Out_DBx__6__INTTYPE CYREG_PICU4_INTTYPE5\r
-#define SCSI_Out_DBx__6__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG\r
-#define SCSI_Out_DBx__6__LCD_EN CYREG_PRT4_LCD_EN\r
-#define SCSI_Out_DBx__6__MASK 0x20u\r
-#define SCSI_Out_DBx__6__PC CYREG_PRT4_PC5\r
-#define SCSI_Out_DBx__6__PORT 4u\r
-#define SCSI_Out_DBx__6__PRT CYREG_PRT4_PRT\r
-#define SCSI_Out_DBx__6__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL\r
-#define SCSI_Out_DBx__6__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN\r
-#define SCSI_Out_DBx__6__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0\r
-#define SCSI_Out_DBx__6__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1\r
-#define SCSI_Out_DBx__6__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0\r
-#define SCSI_Out_DBx__6__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1\r
-#define SCSI_Out_DBx__6__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT\r
-#define SCSI_Out_DBx__6__PS CYREG_PRT4_PS\r
-#define SCSI_Out_DBx__6__SHIFT 5u\r
-#define SCSI_Out_DBx__6__SLW CYREG_PRT4_SLW\r
-#define SCSI_Out_DBx__7__AG CYREG_PRT4_AG\r
-#define SCSI_Out_DBx__7__AMUX CYREG_PRT4_AMUX\r
-#define SCSI_Out_DBx__7__BIE CYREG_PRT4_BIE\r
-#define SCSI_Out_DBx__7__BIT_MASK CYREG_PRT4_BIT_MASK\r
-#define SCSI_Out_DBx__7__BYP CYREG_PRT4_BYP\r
-#define SCSI_Out_DBx__7__CTL CYREG_PRT4_CTL\r
-#define SCSI_Out_DBx__7__DM0 CYREG_PRT4_DM0\r
-#define SCSI_Out_DBx__7__DM1 CYREG_PRT4_DM1\r
-#define SCSI_Out_DBx__7__DM2 CYREG_PRT4_DM2\r
-#define SCSI_Out_DBx__7__DR CYREG_PRT4_DR\r
-#define SCSI_Out_DBx__7__INP_DIS CYREG_PRT4_INP_DIS\r
-#define SCSI_Out_DBx__7__INTTYPE CYREG_PICU4_INTTYPE4\r
-#define SCSI_Out_DBx__7__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG\r
-#define SCSI_Out_DBx__7__LCD_EN CYREG_PRT4_LCD_EN\r
-#define SCSI_Out_DBx__7__MASK 0x10u\r
-#define SCSI_Out_DBx__7__PC CYREG_PRT4_PC4\r
-#define SCSI_Out_DBx__7__PORT 4u\r
-#define SCSI_Out_DBx__7__PRT CYREG_PRT4_PRT\r
-#define SCSI_Out_DBx__7__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL\r
-#define SCSI_Out_DBx__7__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN\r
-#define SCSI_Out_DBx__7__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0\r
-#define SCSI_Out_DBx__7__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1\r
-#define SCSI_Out_DBx__7__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0\r
-#define SCSI_Out_DBx__7__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1\r
-#define SCSI_Out_DBx__7__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT\r
-#define SCSI_Out_DBx__7__PS CYREG_PRT4_PS\r
-#define SCSI_Out_DBx__7__SHIFT 4u\r
-#define SCSI_Out_DBx__7__SLW CYREG_PRT4_SLW\r
-#define SCSI_Out_DBx__DB0__AG CYREG_PRT6_AG\r
-#define SCSI_Out_DBx__DB0__AMUX CYREG_PRT6_AMUX\r
-#define SCSI_Out_DBx__DB0__BIE CYREG_PRT6_BIE\r
-#define SCSI_Out_DBx__DB0__BIT_MASK CYREG_PRT6_BIT_MASK\r
-#define SCSI_Out_DBx__DB0__BYP CYREG_PRT6_BYP\r
-#define SCSI_Out_DBx__DB0__CTL CYREG_PRT6_CTL\r
-#define SCSI_Out_DBx__DB0__DM0 CYREG_PRT6_DM0\r
-#define SCSI_Out_DBx__DB0__DM1 CYREG_PRT6_DM1\r
-#define SCSI_Out_DBx__DB0__DM2 CYREG_PRT6_DM2\r
-#define SCSI_Out_DBx__DB0__DR CYREG_PRT6_DR\r
-#define SCSI_Out_DBx__DB0__INP_DIS CYREG_PRT6_INP_DIS\r
-#define SCSI_Out_DBx__DB0__INTTYPE CYREG_PICU6_INTTYPE3\r
-#define SCSI_Out_DBx__DB0__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
-#define SCSI_Out_DBx__DB0__LCD_EN CYREG_PRT6_LCD_EN\r
-#define SCSI_Out_DBx__DB0__MASK 0x08u\r
-#define SCSI_Out_DBx__DB0__PC CYREG_PRT6_PC3\r
-#define SCSI_Out_DBx__DB0__PORT 6u\r
-#define SCSI_Out_DBx__DB0__PRT CYREG_PRT6_PRT\r
-#define SCSI_Out_DBx__DB0__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
-#define SCSI_Out_DBx__DB0__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
-#define SCSI_Out_DBx__DB0__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
-#define SCSI_Out_DBx__DB0__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
-#define SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
-#define SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
-#define SCSI_Out_DBx__DB0__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
-#define SCSI_Out_DBx__DB0__PS CYREG_PRT6_PS\r
-#define SCSI_Out_DBx__DB0__SHIFT 3u\r
-#define SCSI_Out_DBx__DB0__SLW CYREG_PRT6_SLW\r
-#define SCSI_Out_DBx__DB1__AG CYREG_PRT6_AG\r
-#define SCSI_Out_DBx__DB1__AMUX CYREG_PRT6_AMUX\r
-#define SCSI_Out_DBx__DB1__BIE CYREG_PRT6_BIE\r
-#define SCSI_Out_DBx__DB1__BIT_MASK CYREG_PRT6_BIT_MASK\r
-#define SCSI_Out_DBx__DB1__BYP CYREG_PRT6_BYP\r
-#define SCSI_Out_DBx__DB1__CTL CYREG_PRT6_CTL\r
-#define SCSI_Out_DBx__DB1__DM0 CYREG_PRT6_DM0\r
-#define SCSI_Out_DBx__DB1__DM1 CYREG_PRT6_DM1\r
-#define SCSI_Out_DBx__DB1__DM2 CYREG_PRT6_DM2\r
-#define SCSI_Out_DBx__DB1__DR CYREG_PRT6_DR\r
-#define SCSI_Out_DBx__DB1__INP_DIS CYREG_PRT6_INP_DIS\r
-#define SCSI_Out_DBx__DB1__INTTYPE CYREG_PICU6_INTTYPE2\r
-#define SCSI_Out_DBx__DB1__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
-#define SCSI_Out_DBx__DB1__LCD_EN CYREG_PRT6_LCD_EN\r
-#define SCSI_Out_DBx__DB1__MASK 0x04u\r
-#define SCSI_Out_DBx__DB1__PC CYREG_PRT6_PC2\r
-#define SCSI_Out_DBx__DB1__PORT 6u\r
-#define SCSI_Out_DBx__DB1__PRT CYREG_PRT6_PRT\r
-#define SCSI_Out_DBx__DB1__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
-#define SCSI_Out_DBx__DB1__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
-#define SCSI_Out_DBx__DB1__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
-#define SCSI_Out_DBx__DB1__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
-#define SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
-#define SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
-#define SCSI_Out_DBx__DB1__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
-#define SCSI_Out_DBx__DB1__PS CYREG_PRT6_PS\r
-#define SCSI_Out_DBx__DB1__SHIFT 2u\r
-#define SCSI_Out_DBx__DB1__SLW CYREG_PRT6_SLW\r
-#define SCSI_Out_DBx__DB2__AG CYREG_PRT6_AG\r
-#define SCSI_Out_DBx__DB2__AMUX CYREG_PRT6_AMUX\r
-#define SCSI_Out_DBx__DB2__BIE CYREG_PRT6_BIE\r
-#define SCSI_Out_DBx__DB2__BIT_MASK CYREG_PRT6_BIT_MASK\r
-#define SCSI_Out_DBx__DB2__BYP CYREG_PRT6_BYP\r
-#define SCSI_Out_DBx__DB2__CTL CYREG_PRT6_CTL\r
-#define SCSI_Out_DBx__DB2__DM0 CYREG_PRT6_DM0\r
-#define SCSI_Out_DBx__DB2__DM1 CYREG_PRT6_DM1\r
-#define SCSI_Out_DBx__DB2__DM2 CYREG_PRT6_DM2\r
-#define SCSI_Out_DBx__DB2__DR CYREG_PRT6_DR\r
-#define SCSI_Out_DBx__DB2__INP_DIS CYREG_PRT6_INP_DIS\r
-#define SCSI_Out_DBx__DB2__INTTYPE CYREG_PICU6_INTTYPE1\r
-#define SCSI_Out_DBx__DB2__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
-#define SCSI_Out_DBx__DB2__LCD_EN CYREG_PRT6_LCD_EN\r
-#define SCSI_Out_DBx__DB2__MASK 0x02u\r
-#define SCSI_Out_DBx__DB2__PC CYREG_PRT6_PC1\r
-#define SCSI_Out_DBx__DB2__PORT 6u\r
-#define SCSI_Out_DBx__DB2__PRT CYREG_PRT6_PRT\r
-#define SCSI_Out_DBx__DB2__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
-#define SCSI_Out_DBx__DB2__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
-#define SCSI_Out_DBx__DB2__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
-#define SCSI_Out_DBx__DB2__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
-#define SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
-#define SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
-#define SCSI_Out_DBx__DB2__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
-#define SCSI_Out_DBx__DB2__PS CYREG_PRT6_PS\r
-#define SCSI_Out_DBx__DB2__SHIFT 1u\r
-#define SCSI_Out_DBx__DB2__SLW CYREG_PRT6_SLW\r
-#define SCSI_Out_DBx__DB3__AG CYREG_PRT6_AG\r
-#define SCSI_Out_DBx__DB3__AMUX CYREG_PRT6_AMUX\r
-#define SCSI_Out_DBx__DB3__BIE CYREG_PRT6_BIE\r
-#define SCSI_Out_DBx__DB3__BIT_MASK CYREG_PRT6_BIT_MASK\r
-#define SCSI_Out_DBx__DB3__BYP CYREG_PRT6_BYP\r
-#define SCSI_Out_DBx__DB3__CTL CYREG_PRT6_CTL\r
-#define SCSI_Out_DBx__DB3__DM0 CYREG_PRT6_DM0\r
-#define SCSI_Out_DBx__DB3__DM1 CYREG_PRT6_DM1\r
-#define SCSI_Out_DBx__DB3__DM2 CYREG_PRT6_DM2\r
-#define SCSI_Out_DBx__DB3__DR CYREG_PRT6_DR\r
-#define SCSI_Out_DBx__DB3__INP_DIS CYREG_PRT6_INP_DIS\r
-#define SCSI_Out_DBx__DB3__INTTYPE CYREG_PICU6_INTTYPE0\r
-#define SCSI_Out_DBx__DB3__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
-#define SCSI_Out_DBx__DB3__LCD_EN CYREG_PRT6_LCD_EN\r
-#define SCSI_Out_DBx__DB3__MASK 0x01u\r
-#define SCSI_Out_DBx__DB3__PC CYREG_PRT6_PC0\r
-#define SCSI_Out_DBx__DB3__PORT 6u\r
-#define SCSI_Out_DBx__DB3__PRT CYREG_PRT6_PRT\r
-#define SCSI_Out_DBx__DB3__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
-#define SCSI_Out_DBx__DB3__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
-#define SCSI_Out_DBx__DB3__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
-#define SCSI_Out_DBx__DB3__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
-#define SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
-#define SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
-#define SCSI_Out_DBx__DB3__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
-#define SCSI_Out_DBx__DB3__PS CYREG_PRT6_PS\r
-#define SCSI_Out_DBx__DB3__SHIFT 0u\r
-#define SCSI_Out_DBx__DB3__SLW CYREG_PRT6_SLW\r
-#define SCSI_Out_DBx__DB4__AG CYREG_PRT4_AG\r
-#define SCSI_Out_DBx__DB4__AMUX CYREG_PRT4_AMUX\r
-#define SCSI_Out_DBx__DB4__BIE CYREG_PRT4_BIE\r
-#define SCSI_Out_DBx__DB4__BIT_MASK CYREG_PRT4_BIT_MASK\r
-#define SCSI_Out_DBx__DB4__BYP CYREG_PRT4_BYP\r
-#define SCSI_Out_DBx__DB4__CTL CYREG_PRT4_CTL\r
-#define SCSI_Out_DBx__DB4__DM0 CYREG_PRT4_DM0\r
-#define SCSI_Out_DBx__DB4__DM1 CYREG_PRT4_DM1\r
-#define SCSI_Out_DBx__DB4__DM2 CYREG_PRT4_DM2\r
-#define SCSI_Out_DBx__DB4__DR CYREG_PRT4_DR\r
-#define SCSI_Out_DBx__DB4__INP_DIS CYREG_PRT4_INP_DIS\r
-#define SCSI_Out_DBx__DB4__INTTYPE CYREG_PICU4_INTTYPE7\r
-#define SCSI_Out_DBx__DB4__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG\r
-#define SCSI_Out_DBx__DB4__LCD_EN CYREG_PRT4_LCD_EN\r
-#define SCSI_Out_DBx__DB4__MASK 0x80u\r
-#define SCSI_Out_DBx__DB4__PC CYREG_PRT4_PC7\r
-#define SCSI_Out_DBx__DB4__PORT 4u\r
-#define SCSI_Out_DBx__DB4__PRT CYREG_PRT4_PRT\r
-#define SCSI_Out_DBx__DB4__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL\r
-#define SCSI_Out_DBx__DB4__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN\r
-#define SCSI_Out_DBx__DB4__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0\r
-#define SCSI_Out_DBx__DB4__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1\r
-#define SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0\r
-#define SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1\r
-#define SCSI_Out_DBx__DB4__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT\r
-#define SCSI_Out_DBx__DB4__PS CYREG_PRT4_PS\r
-#define SCSI_Out_DBx__DB4__SHIFT 7u\r
-#define SCSI_Out_DBx__DB4__SLW CYREG_PRT4_SLW\r
-#define SCSI_Out_DBx__DB5__AG CYREG_PRT4_AG\r
-#define SCSI_Out_DBx__DB5__AMUX CYREG_PRT4_AMUX\r
-#define SCSI_Out_DBx__DB5__BIE CYREG_PRT4_BIE\r
-#define SCSI_Out_DBx__DB5__BIT_MASK CYREG_PRT4_BIT_MASK\r
-#define SCSI_Out_DBx__DB5__BYP CYREG_PRT4_BYP\r
-#define SCSI_Out_DBx__DB5__CTL CYREG_PRT4_CTL\r
-#define SCSI_Out_DBx__DB5__DM0 CYREG_PRT4_DM0\r
-#define SCSI_Out_DBx__DB5__DM1 CYREG_PRT4_DM1\r
-#define SCSI_Out_DBx__DB5__DM2 CYREG_PRT4_DM2\r
-#define SCSI_Out_DBx__DB5__DR CYREG_PRT4_DR\r
-#define SCSI_Out_DBx__DB5__INP_DIS CYREG_PRT4_INP_DIS\r
-#define SCSI_Out_DBx__DB5__INTTYPE CYREG_PICU4_INTTYPE6\r
-#define SCSI_Out_DBx__DB5__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG\r
-#define SCSI_Out_DBx__DB5__LCD_EN CYREG_PRT4_LCD_EN\r
-#define SCSI_Out_DBx__DB5__MASK 0x40u\r
-#define SCSI_Out_DBx__DB5__PC CYREG_PRT4_PC6\r
-#define SCSI_Out_DBx__DB5__PORT 4u\r
-#define SCSI_Out_DBx__DB5__PRT CYREG_PRT4_PRT\r
-#define SCSI_Out_DBx__DB5__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL\r
-#define SCSI_Out_DBx__DB5__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN\r
-#define SCSI_Out_DBx__DB5__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0\r
-#define SCSI_Out_DBx__DB5__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1\r
-#define SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0\r
-#define SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1\r
-#define SCSI_Out_DBx__DB5__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT\r
-#define SCSI_Out_DBx__DB5__PS CYREG_PRT4_PS\r
-#define SCSI_Out_DBx__DB5__SHIFT 6u\r
-#define SCSI_Out_DBx__DB5__SLW CYREG_PRT4_SLW\r
-#define SCSI_Out_DBx__DB6__AG CYREG_PRT4_AG\r
-#define SCSI_Out_DBx__DB6__AMUX CYREG_PRT4_AMUX\r
-#define SCSI_Out_DBx__DB6__BIE CYREG_PRT4_BIE\r
-#define SCSI_Out_DBx__DB6__BIT_MASK CYREG_PRT4_BIT_MASK\r
-#define SCSI_Out_DBx__DB6__BYP CYREG_PRT4_BYP\r
-#define SCSI_Out_DBx__DB6__CTL CYREG_PRT4_CTL\r
-#define SCSI_Out_DBx__DB6__DM0 CYREG_PRT4_DM0\r
-#define SCSI_Out_DBx__DB6__DM1 CYREG_PRT4_DM1\r
-#define SCSI_Out_DBx__DB6__DM2 CYREG_PRT4_DM2\r
-#define SCSI_Out_DBx__DB6__DR CYREG_PRT4_DR\r
-#define SCSI_Out_DBx__DB6__INP_DIS CYREG_PRT4_INP_DIS\r
-#define SCSI_Out_DBx__DB6__INTTYPE CYREG_PICU4_INTTYPE5\r
-#define SCSI_Out_DBx__DB6__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG\r
-#define SCSI_Out_DBx__DB6__LCD_EN CYREG_PRT4_LCD_EN\r
-#define SCSI_Out_DBx__DB6__MASK 0x20u\r
-#define SCSI_Out_DBx__DB6__PC CYREG_PRT4_PC5\r
-#define SCSI_Out_DBx__DB6__PORT 4u\r
-#define SCSI_Out_DBx__DB6__PRT CYREG_PRT4_PRT\r
-#define SCSI_Out_DBx__DB6__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL\r
-#define SCSI_Out_DBx__DB6__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN\r
-#define SCSI_Out_DBx__DB6__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0\r
-#define SCSI_Out_DBx__DB6__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1\r
-#define SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0\r
-#define SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1\r
-#define SCSI_Out_DBx__DB6__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT\r
-#define SCSI_Out_DBx__DB6__PS CYREG_PRT4_PS\r
-#define SCSI_Out_DBx__DB6__SHIFT 5u\r
-#define SCSI_Out_DBx__DB6__SLW CYREG_PRT4_SLW\r
-#define SCSI_Out_DBx__DB7__AG CYREG_PRT4_AG\r
-#define SCSI_Out_DBx__DB7__AMUX CYREG_PRT4_AMUX\r
-#define SCSI_Out_DBx__DB7__BIE CYREG_PRT4_BIE\r
-#define SCSI_Out_DBx__DB7__BIT_MASK CYREG_PRT4_BIT_MASK\r
-#define SCSI_Out_DBx__DB7__BYP CYREG_PRT4_BYP\r
-#define SCSI_Out_DBx__DB7__CTL CYREG_PRT4_CTL\r
-#define SCSI_Out_DBx__DB7__DM0 CYREG_PRT4_DM0\r
-#define SCSI_Out_DBx__DB7__DM1 CYREG_PRT4_DM1\r
-#define SCSI_Out_DBx__DB7__DM2 CYREG_PRT4_DM2\r
-#define SCSI_Out_DBx__DB7__DR CYREG_PRT4_DR\r
-#define SCSI_Out_DBx__DB7__INP_DIS CYREG_PRT4_INP_DIS\r
-#define SCSI_Out_DBx__DB7__INTTYPE CYREG_PICU4_INTTYPE4\r
-#define SCSI_Out_DBx__DB7__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG\r
-#define SCSI_Out_DBx__DB7__LCD_EN CYREG_PRT4_LCD_EN\r
-#define SCSI_Out_DBx__DB7__MASK 0x10u\r
-#define SCSI_Out_DBx__DB7__PC CYREG_PRT4_PC4\r
-#define SCSI_Out_DBx__DB7__PORT 4u\r
-#define SCSI_Out_DBx__DB7__PRT CYREG_PRT4_PRT\r
-#define SCSI_Out_DBx__DB7__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL\r
-#define SCSI_Out_DBx__DB7__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN\r
-#define SCSI_Out_DBx__DB7__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0\r
-#define SCSI_Out_DBx__DB7__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1\r
-#define SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0\r
-#define SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1\r
-#define SCSI_Out_DBx__DB7__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT\r
-#define SCSI_Out_DBx__DB7__PS CYREG_PRT4_PS\r
-#define SCSI_Out_DBx__DB7__SHIFT 4u\r
-#define SCSI_Out_DBx__DB7__SLW CYREG_PRT4_SLW\r
-\r
-/* SD_RX_DMA */\r
-#define SD_RX_DMA__DRQ_CTL CYREG_IDMUX_DRQ_CTL0\r
-#define SD_RX_DMA__DRQ_NUMBER 2u\r
-#define SD_RX_DMA__NUMBEROF_TDS 0u\r
-#define SD_RX_DMA__PRIORITY 0u\r
-#define SD_RX_DMA__TERMIN_EN 0u\r
-#define SD_RX_DMA__TERMIN_SEL 0u\r
-#define SD_RX_DMA__TERMOUT0_EN 1u\r
-#define SD_RX_DMA__TERMOUT0_SEL 2u\r
-#define SD_RX_DMA__TERMOUT1_EN 0u\r
-#define SD_RX_DMA__TERMOUT1_SEL 0u\r
-\r
-/* SD_RX_DMA_COMPLETE */\r
-#define SD_RX_DMA_COMPLETE__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
-#define SD_RX_DMA_COMPLETE__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
-#define SD_RX_DMA_COMPLETE__INTC_MASK 0x20u\r
-#define SD_RX_DMA_COMPLETE__INTC_NUMBER 5u\r
-#define SD_RX_DMA_COMPLETE__INTC_PRIOR_NUM 7u\r
-#define SD_RX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_5\r
-#define SD_RX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
-#define SD_RX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
-\r
-/* SD_TX_DMA */\r
-#define SD_TX_DMA__DRQ_CTL CYREG_IDMUX_DRQ_CTL0\r
-#define SD_TX_DMA__DRQ_NUMBER 3u\r
-#define SD_TX_DMA__NUMBEROF_TDS 0u\r
-#define SD_TX_DMA__PRIORITY 1u\r
-#define SD_TX_DMA__TERMIN_EN 0u\r
-#define SD_TX_DMA__TERMIN_SEL 0u\r
-#define SD_TX_DMA__TERMOUT0_EN 1u\r
-#define SD_TX_DMA__TERMOUT0_SEL 3u\r
-#define SD_TX_DMA__TERMOUT1_EN 0u\r
-#define SD_TX_DMA__TERMOUT1_SEL 0u\r
-\r
-/* SD_TX_DMA_COMPLETE */\r
-#define SD_TX_DMA_COMPLETE__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
-#define SD_TX_DMA_COMPLETE__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
-#define SD_TX_DMA_COMPLETE__INTC_MASK 0x40u\r
-#define SD_TX_DMA_COMPLETE__INTC_NUMBER 6u\r
-#define SD_TX_DMA_COMPLETE__INTC_PRIOR_NUM 7u\r
-#define SD_TX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_6\r
-#define SD_TX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
-#define SD_TX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
+/* SCSI_In */\r
+#define SCSI_In__0__AG CYREG_PRT2_AG\r
+#define SCSI_In__0__AMUX CYREG_PRT2_AMUX\r
+#define SCSI_In__0__BIE CYREG_PRT2_BIE\r
+#define SCSI_In__0__BIT_MASK CYREG_PRT2_BIT_MASK\r
+#define SCSI_In__0__BYP CYREG_PRT2_BYP\r
+#define SCSI_In__0__CTL CYREG_PRT2_CTL\r
+#define SCSI_In__0__DM0 CYREG_PRT2_DM0\r
+#define SCSI_In__0__DM1 CYREG_PRT2_DM1\r
+#define SCSI_In__0__DM2 CYREG_PRT2_DM2\r
+#define SCSI_In__0__DR CYREG_PRT2_DR\r
+#define SCSI_In__0__INP_DIS CYREG_PRT2_INP_DIS\r
+#define SCSI_In__0__INTTYPE CYREG_PICU2_INTTYPE0\r
+#define SCSI_In__0__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG\r
+#define SCSI_In__0__LCD_EN CYREG_PRT2_LCD_EN\r
+#define SCSI_In__0__MASK 0x01u\r
+#define SCSI_In__0__PC CYREG_PRT2_PC0\r
+#define SCSI_In__0__PORT 2u\r
+#define SCSI_In__0__PRT CYREG_PRT2_PRT\r
+#define SCSI_In__0__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL\r
+#define SCSI_In__0__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN\r
+#define SCSI_In__0__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0\r
+#define SCSI_In__0__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1\r
+#define SCSI_In__0__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0\r
+#define SCSI_In__0__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1\r
+#define SCSI_In__0__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT\r
+#define SCSI_In__0__PS CYREG_PRT2_PS\r
+#define SCSI_In__0__SHIFT 0u\r
+#define SCSI_In__0__SLW CYREG_PRT2_SLW\r
+#define SCSI_In__1__AG CYREG_PRT6_AG\r
+#define SCSI_In__1__AMUX CYREG_PRT6_AMUX\r
+#define SCSI_In__1__BIE CYREG_PRT6_BIE\r
+#define SCSI_In__1__BIT_MASK CYREG_PRT6_BIT_MASK\r
+#define SCSI_In__1__BYP CYREG_PRT6_BYP\r
+#define SCSI_In__1__CTL CYREG_PRT6_CTL\r
+#define SCSI_In__1__DM0 CYREG_PRT6_DM0\r
+#define SCSI_In__1__DM1 CYREG_PRT6_DM1\r
+#define SCSI_In__1__DM2 CYREG_PRT6_DM2\r
+#define SCSI_In__1__DR CYREG_PRT6_DR\r
+#define SCSI_In__1__INP_DIS CYREG_PRT6_INP_DIS\r
+#define SCSI_In__1__INTTYPE CYREG_PICU6_INTTYPE7\r
+#define SCSI_In__1__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
+#define SCSI_In__1__LCD_EN CYREG_PRT6_LCD_EN\r
+#define SCSI_In__1__MASK 0x80u\r
+#define SCSI_In__1__PC CYREG_PRT6_PC7\r
+#define SCSI_In__1__PORT 6u\r
+#define SCSI_In__1__PRT CYREG_PRT6_PRT\r
+#define SCSI_In__1__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
+#define SCSI_In__1__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
+#define SCSI_In__1__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
+#define SCSI_In__1__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
+#define SCSI_In__1__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
+#define SCSI_In__1__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
+#define SCSI_In__1__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
+#define SCSI_In__1__PS CYREG_PRT6_PS\r
+#define SCSI_In__1__SHIFT 7u\r
+#define SCSI_In__1__SLW CYREG_PRT6_SLW\r
+#define SCSI_In__2__AG CYREG_PRT5_AG\r
+#define SCSI_In__2__AMUX CYREG_PRT5_AMUX\r
+#define SCSI_In__2__BIE CYREG_PRT5_BIE\r
+#define SCSI_In__2__BIT_MASK CYREG_PRT5_BIT_MASK\r
+#define SCSI_In__2__BYP CYREG_PRT5_BYP\r
+#define SCSI_In__2__CTL CYREG_PRT5_CTL\r
+#define SCSI_In__2__DM0 CYREG_PRT5_DM0\r
+#define SCSI_In__2__DM1 CYREG_PRT5_DM1\r
+#define SCSI_In__2__DM2 CYREG_PRT5_DM2\r
+#define SCSI_In__2__DR CYREG_PRT5_DR\r
+#define SCSI_In__2__INP_DIS CYREG_PRT5_INP_DIS\r
+#define SCSI_In__2__INTTYPE CYREG_PICU5_INTTYPE1\r
+#define SCSI_In__2__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG\r
+#define SCSI_In__2__LCD_EN CYREG_PRT5_LCD_EN\r
+#define SCSI_In__2__MASK 0x02u\r
+#define SCSI_In__2__PC CYREG_PRT5_PC1\r
+#define SCSI_In__2__PORT 5u\r
+#define SCSI_In__2__PRT CYREG_PRT5_PRT\r
+#define SCSI_In__2__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL\r
+#define SCSI_In__2__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN\r
+#define SCSI_In__2__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0\r
+#define SCSI_In__2__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1\r
+#define SCSI_In__2__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0\r
+#define SCSI_In__2__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1\r
+#define SCSI_In__2__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT\r
+#define SCSI_In__2__PS CYREG_PRT5_PS\r
+#define SCSI_In__2__SHIFT 1u\r
+#define SCSI_In__2__SLW CYREG_PRT5_SLW\r
+#define SCSI_In__3__AG CYREG_PRT5_AG\r
+#define SCSI_In__3__AMUX CYREG_PRT5_AMUX\r
+#define SCSI_In__3__BIE CYREG_PRT5_BIE\r
+#define SCSI_In__3__BIT_MASK CYREG_PRT5_BIT_MASK\r
+#define SCSI_In__3__BYP CYREG_PRT5_BYP\r
+#define SCSI_In__3__CTL CYREG_PRT5_CTL\r
+#define SCSI_In__3__DM0 CYREG_PRT5_DM0\r
+#define SCSI_In__3__DM1 CYREG_PRT5_DM1\r
+#define SCSI_In__3__DM2 CYREG_PRT5_DM2\r
+#define SCSI_In__3__DR CYREG_PRT5_DR\r
+#define SCSI_In__3__INP_DIS CYREG_PRT5_INP_DIS\r
+#define SCSI_In__3__INTTYPE CYREG_PICU5_INTTYPE2\r
+#define SCSI_In__3__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG\r
+#define SCSI_In__3__LCD_EN CYREG_PRT5_LCD_EN\r
+#define SCSI_In__3__MASK 0x04u\r
+#define SCSI_In__3__PC CYREG_PRT5_PC2\r
+#define SCSI_In__3__PORT 5u\r
+#define SCSI_In__3__PRT CYREG_PRT5_PRT\r
+#define SCSI_In__3__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL\r
+#define SCSI_In__3__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN\r
+#define SCSI_In__3__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0\r
+#define SCSI_In__3__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1\r
+#define SCSI_In__3__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0\r
+#define SCSI_In__3__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1\r
+#define SCSI_In__3__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT\r
+#define SCSI_In__3__PS CYREG_PRT5_PS\r
+#define SCSI_In__3__SHIFT 2u\r
+#define SCSI_In__3__SLW CYREG_PRT5_SLW\r
+#define SCSI_In__4__AG CYREG_PRT5_AG\r
+#define SCSI_In__4__AMUX CYREG_PRT5_AMUX\r
+#define SCSI_In__4__BIE CYREG_PRT5_BIE\r
+#define SCSI_In__4__BIT_MASK CYREG_PRT5_BIT_MASK\r
+#define SCSI_In__4__BYP CYREG_PRT5_BYP\r
+#define SCSI_In__4__CTL CYREG_PRT5_CTL\r
+#define SCSI_In__4__DM0 CYREG_PRT5_DM0\r
+#define SCSI_In__4__DM1 CYREG_PRT5_DM1\r
+#define SCSI_In__4__DM2 CYREG_PRT5_DM2\r
+#define SCSI_In__4__DR CYREG_PRT5_DR\r
+#define SCSI_In__4__INP_DIS CYREG_PRT5_INP_DIS\r
+#define SCSI_In__4__INTTYPE CYREG_PICU5_INTTYPE3\r
+#define SCSI_In__4__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG\r
+#define SCSI_In__4__LCD_EN CYREG_PRT5_LCD_EN\r
+#define SCSI_In__4__MASK 0x08u\r
+#define SCSI_In__4__PC CYREG_PRT5_PC3\r
+#define SCSI_In__4__PORT 5u\r
+#define SCSI_In__4__PRT CYREG_PRT5_PRT\r
+#define SCSI_In__4__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL\r
+#define SCSI_In__4__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN\r
+#define SCSI_In__4__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0\r
+#define SCSI_In__4__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1\r
+#define SCSI_In__4__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0\r
+#define SCSI_In__4__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1\r
+#define SCSI_In__4__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT\r
+#define SCSI_In__4__PS CYREG_PRT5_PS\r
+#define SCSI_In__4__SHIFT 3u\r
+#define SCSI_In__4__SLW CYREG_PRT5_SLW\r
+#define SCSI_In__CD__AG CYREG_PRT5_AG\r
+#define SCSI_In__CD__AMUX CYREG_PRT5_AMUX\r
+#define SCSI_In__CD__BIE CYREG_PRT5_BIE\r
+#define SCSI_In__CD__BIT_MASK CYREG_PRT5_BIT_MASK\r
+#define SCSI_In__CD__BYP CYREG_PRT5_BYP\r
+#define SCSI_In__CD__CTL CYREG_PRT5_CTL\r
+#define SCSI_In__CD__DM0 CYREG_PRT5_DM0\r
+#define SCSI_In__CD__DM1 CYREG_PRT5_DM1\r
+#define SCSI_In__CD__DM2 CYREG_PRT5_DM2\r
+#define SCSI_In__CD__DR CYREG_PRT5_DR\r
+#define SCSI_In__CD__INP_DIS CYREG_PRT5_INP_DIS\r
+#define SCSI_In__CD__INTTYPE CYREG_PICU5_INTTYPE1\r
+#define SCSI_In__CD__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG\r
+#define SCSI_In__CD__LCD_EN CYREG_PRT5_LCD_EN\r
+#define SCSI_In__CD__MASK 0x02u\r
+#define SCSI_In__CD__PC CYREG_PRT5_PC1\r
+#define SCSI_In__CD__PORT 5u\r
+#define SCSI_In__CD__PRT CYREG_PRT5_PRT\r
+#define SCSI_In__CD__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL\r
+#define SCSI_In__CD__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN\r
+#define SCSI_In__CD__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0\r
+#define SCSI_In__CD__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1\r
+#define SCSI_In__CD__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0\r
+#define SCSI_In__CD__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1\r
+#define SCSI_In__CD__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT\r
+#define SCSI_In__CD__PS CYREG_PRT5_PS\r
+#define SCSI_In__CD__SHIFT 1u\r
+#define SCSI_In__CD__SLW CYREG_PRT5_SLW\r
+#define SCSI_In__DBP__AG CYREG_PRT2_AG\r
+#define SCSI_In__DBP__AMUX CYREG_PRT2_AMUX\r
+#define SCSI_In__DBP__BIE CYREG_PRT2_BIE\r
+#define SCSI_In__DBP__BIT_MASK CYREG_PRT2_BIT_MASK\r
+#define SCSI_In__DBP__BYP CYREG_PRT2_BYP\r
+#define SCSI_In__DBP__CTL CYREG_PRT2_CTL\r
+#define SCSI_In__DBP__DM0 CYREG_PRT2_DM0\r
+#define SCSI_In__DBP__DM1 CYREG_PRT2_DM1\r
+#define SCSI_In__DBP__DM2 CYREG_PRT2_DM2\r
+#define SCSI_In__DBP__DR CYREG_PRT2_DR\r
+#define SCSI_In__DBP__INP_DIS CYREG_PRT2_INP_DIS\r
+#define SCSI_In__DBP__INTTYPE CYREG_PICU2_INTTYPE0\r
+#define SCSI_In__DBP__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG\r
+#define SCSI_In__DBP__LCD_EN CYREG_PRT2_LCD_EN\r
+#define SCSI_In__DBP__MASK 0x01u\r
+#define SCSI_In__DBP__PC CYREG_PRT2_PC0\r
+#define SCSI_In__DBP__PORT 2u\r
+#define SCSI_In__DBP__PRT CYREG_PRT2_PRT\r
+#define SCSI_In__DBP__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL\r
+#define SCSI_In__DBP__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN\r
+#define SCSI_In__DBP__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0\r
+#define SCSI_In__DBP__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1\r
+#define SCSI_In__DBP__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0\r
+#define SCSI_In__DBP__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1\r
+#define SCSI_In__DBP__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT\r
+#define SCSI_In__DBP__PS CYREG_PRT2_PS\r
+#define SCSI_In__DBP__SHIFT 0u\r
+#define SCSI_In__DBP__SLW CYREG_PRT2_SLW\r
+#define SCSI_In__IO__AG CYREG_PRT5_AG\r
+#define SCSI_In__IO__AMUX CYREG_PRT5_AMUX\r
+#define SCSI_In__IO__BIE CYREG_PRT5_BIE\r
+#define SCSI_In__IO__BIT_MASK CYREG_PRT5_BIT_MASK\r
+#define SCSI_In__IO__BYP CYREG_PRT5_BYP\r
+#define SCSI_In__IO__CTL CYREG_PRT5_CTL\r
+#define SCSI_In__IO__DM0 CYREG_PRT5_DM0\r
+#define SCSI_In__IO__DM1 CYREG_PRT5_DM1\r
+#define SCSI_In__IO__DM2 CYREG_PRT5_DM2\r
+#define SCSI_In__IO__DR CYREG_PRT5_DR\r
+#define SCSI_In__IO__INP_DIS CYREG_PRT5_INP_DIS\r
+#define SCSI_In__IO__INTTYPE CYREG_PICU5_INTTYPE3\r
+#define SCSI_In__IO__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG\r
+#define SCSI_In__IO__LCD_EN CYREG_PRT5_LCD_EN\r
+#define SCSI_In__IO__MASK 0x08u\r
+#define SCSI_In__IO__PC CYREG_PRT5_PC3\r
+#define SCSI_In__IO__PORT 5u\r
+#define SCSI_In__IO__PRT CYREG_PRT5_PRT\r
+#define SCSI_In__IO__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL\r
+#define SCSI_In__IO__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN\r
+#define SCSI_In__IO__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0\r
+#define SCSI_In__IO__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1\r
+#define SCSI_In__IO__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0\r
+#define SCSI_In__IO__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1\r
+#define SCSI_In__IO__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT\r
+#define SCSI_In__IO__PS CYREG_PRT5_PS\r
+#define SCSI_In__IO__SHIFT 3u\r
+#define SCSI_In__IO__SLW CYREG_PRT5_SLW\r
+#define SCSI_In__MSG__AG CYREG_PRT6_AG\r
+#define SCSI_In__MSG__AMUX CYREG_PRT6_AMUX\r
+#define SCSI_In__MSG__BIE CYREG_PRT6_BIE\r
+#define SCSI_In__MSG__BIT_MASK CYREG_PRT6_BIT_MASK\r
+#define SCSI_In__MSG__BYP CYREG_PRT6_BYP\r
+#define SCSI_In__MSG__CTL CYREG_PRT6_CTL\r
+#define SCSI_In__MSG__DM0 CYREG_PRT6_DM0\r
+#define SCSI_In__MSG__DM1 CYREG_PRT6_DM1\r
+#define SCSI_In__MSG__DM2 CYREG_PRT6_DM2\r
+#define SCSI_In__MSG__DR CYREG_PRT6_DR\r
+#define SCSI_In__MSG__INP_DIS CYREG_PRT6_INP_DIS\r
+#define SCSI_In__MSG__INTTYPE CYREG_PICU6_INTTYPE7\r
+#define SCSI_In__MSG__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
+#define SCSI_In__MSG__LCD_EN CYREG_PRT6_LCD_EN\r
+#define SCSI_In__MSG__MASK 0x80u\r
+#define SCSI_In__MSG__PC CYREG_PRT6_PC7\r
+#define SCSI_In__MSG__PORT 6u\r
+#define SCSI_In__MSG__PRT CYREG_PRT6_PRT\r
+#define SCSI_In__MSG__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
+#define SCSI_In__MSG__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
+#define SCSI_In__MSG__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
+#define SCSI_In__MSG__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
+#define SCSI_In__MSG__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
+#define SCSI_In__MSG__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
+#define SCSI_In__MSG__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
+#define SCSI_In__MSG__PS CYREG_PRT6_PS\r
+#define SCSI_In__MSG__SHIFT 7u\r
+#define SCSI_In__MSG__SLW CYREG_PRT6_SLW\r
+#define SCSI_In__REQ__AG CYREG_PRT5_AG\r
+#define SCSI_In__REQ__AMUX CYREG_PRT5_AMUX\r
+#define SCSI_In__REQ__BIE CYREG_PRT5_BIE\r
+#define SCSI_In__REQ__BIT_MASK CYREG_PRT5_BIT_MASK\r
+#define SCSI_In__REQ__BYP CYREG_PRT5_BYP\r
+#define SCSI_In__REQ__CTL CYREG_PRT5_CTL\r
+#define SCSI_In__REQ__DM0 CYREG_PRT5_DM0\r
+#define SCSI_In__REQ__DM1 CYREG_PRT5_DM1\r
+#define SCSI_In__REQ__DM2 CYREG_PRT5_DM2\r
+#define SCSI_In__REQ__DR CYREG_PRT5_DR\r
+#define SCSI_In__REQ__INP_DIS CYREG_PRT5_INP_DIS\r
+#define SCSI_In__REQ__INTTYPE CYREG_PICU5_INTTYPE2\r
+#define SCSI_In__REQ__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG\r
+#define SCSI_In__REQ__LCD_EN CYREG_PRT5_LCD_EN\r
+#define SCSI_In__REQ__MASK 0x04u\r
+#define SCSI_In__REQ__PC CYREG_PRT5_PC2\r
+#define SCSI_In__REQ__PORT 5u\r
+#define SCSI_In__REQ__PRT CYREG_PRT5_PRT\r
+#define SCSI_In__REQ__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL\r
+#define SCSI_In__REQ__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN\r
+#define SCSI_In__REQ__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0\r
+#define SCSI_In__REQ__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1\r
+#define SCSI_In__REQ__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0\r
+#define SCSI_In__REQ__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1\r
+#define SCSI_In__REQ__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT\r
+#define SCSI_In__REQ__PS CYREG_PRT5_PS\r
+#define SCSI_In__REQ__SHIFT 2u\r
+#define SCSI_In__REQ__SLW CYREG_PRT5_SLW\r
+#define SCSI_In_DBx__0__AG CYREG_PRT12_AG\r
+#define SCSI_In_DBx__0__BIE CYREG_PRT12_BIE\r
+#define SCSI_In_DBx__0__BIT_MASK CYREG_PRT12_BIT_MASK\r
+#define SCSI_In_DBx__0__BYP CYREG_PRT12_BYP\r
+#define SCSI_In_DBx__0__DM0 CYREG_PRT12_DM0\r
+#define SCSI_In_DBx__0__DM1 CYREG_PRT12_DM1\r
+#define SCSI_In_DBx__0__DM2 CYREG_PRT12_DM2\r
+#define SCSI_In_DBx__0__DR CYREG_PRT12_DR\r
+#define SCSI_In_DBx__0__INP_DIS CYREG_PRT12_INP_DIS\r
+#define SCSI_In_DBx__0__INTTYPE CYREG_PICU12_INTTYPE4\r
+#define SCSI_In_DBx__0__MASK 0x10u\r
+#define SCSI_In_DBx__0__PC CYREG_PRT12_PC4\r
+#define SCSI_In_DBx__0__PORT 12u\r
+#define SCSI_In_DBx__0__PRT CYREG_PRT12_PRT\r
+#define SCSI_In_DBx__0__PRTDSI__DBL_SYNC_IN CYREG_PRT12_DBL_SYNC_IN\r
+#define SCSI_In_DBx__0__PRTDSI__OE_SEL0 CYREG_PRT12_OE_SEL0\r
+#define SCSI_In_DBx__0__PRTDSI__OE_SEL1 CYREG_PRT12_OE_SEL1\r
+#define SCSI_In_DBx__0__PRTDSI__OUT_SEL0 CYREG_PRT12_OUT_SEL0\r
+#define SCSI_In_DBx__0__PRTDSI__OUT_SEL1 CYREG_PRT12_OUT_SEL1\r
+#define SCSI_In_DBx__0__PRTDSI__SYNC_OUT CYREG_PRT12_SYNC_OUT\r
+#define SCSI_In_DBx__0__PS CYREG_PRT12_PS\r
+#define SCSI_In_DBx__0__SHIFT 4u\r
+#define SCSI_In_DBx__0__SIO_CFG CYREG_PRT12_SIO_CFG\r
+#define SCSI_In_DBx__0__SIO_DIFF CYREG_PRT12_SIO_DIFF\r
+#define SCSI_In_DBx__0__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN\r
+#define SCSI_In_DBx__0__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ\r
+#define SCSI_In_DBx__0__SLW CYREG_PRT12_SLW\r
+#define SCSI_In_DBx__1__AG CYREG_PRT2_AG\r
+#define SCSI_In_DBx__1__AMUX CYREG_PRT2_AMUX\r
+#define SCSI_In_DBx__1__BIE CYREG_PRT2_BIE\r
+#define SCSI_In_DBx__1__BIT_MASK CYREG_PRT2_BIT_MASK\r
+#define SCSI_In_DBx__1__BYP CYREG_PRT2_BYP\r
+#define SCSI_In_DBx__1__CTL CYREG_PRT2_CTL\r
+#define SCSI_In_DBx__1__DM0 CYREG_PRT2_DM0\r
+#define SCSI_In_DBx__1__DM1 CYREG_PRT2_DM1\r
+#define SCSI_In_DBx__1__DM2 CYREG_PRT2_DM2\r
+#define SCSI_In_DBx__1__DR CYREG_PRT2_DR\r
+#define SCSI_In_DBx__1__INP_DIS CYREG_PRT2_INP_DIS\r
+#define SCSI_In_DBx__1__INTTYPE CYREG_PICU2_INTTYPE7\r
+#define SCSI_In_DBx__1__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG\r
+#define SCSI_In_DBx__1__LCD_EN CYREG_PRT2_LCD_EN\r
+#define SCSI_In_DBx__1__MASK 0x80u\r
+#define SCSI_In_DBx__1__PC CYREG_PRT2_PC7\r
+#define SCSI_In_DBx__1__PORT 2u\r
+#define SCSI_In_DBx__1__PRT CYREG_PRT2_PRT\r
+#define SCSI_In_DBx__1__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL\r
+#define SCSI_In_DBx__1__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN\r
+#define SCSI_In_DBx__1__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0\r
+#define SCSI_In_DBx__1__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1\r
+#define SCSI_In_DBx__1__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0\r
+#define SCSI_In_DBx__1__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1\r
+#define SCSI_In_DBx__1__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT\r
+#define SCSI_In_DBx__1__PS CYREG_PRT2_PS\r
+#define SCSI_In_DBx__1__SHIFT 7u\r
+#define SCSI_In_DBx__1__SLW CYREG_PRT2_SLW\r
+#define SCSI_In_DBx__2__AG CYREG_PRT2_AG\r
+#define SCSI_In_DBx__2__AMUX CYREG_PRT2_AMUX\r
+#define SCSI_In_DBx__2__BIE CYREG_PRT2_BIE\r
+#define SCSI_In_DBx__2__BIT_MASK CYREG_PRT2_BIT_MASK\r
+#define SCSI_In_DBx__2__BYP CYREG_PRT2_BYP\r
+#define SCSI_In_DBx__2__CTL CYREG_PRT2_CTL\r
+#define SCSI_In_DBx__2__DM0 CYREG_PRT2_DM0\r
+#define SCSI_In_DBx__2__DM1 CYREG_PRT2_DM1\r
+#define SCSI_In_DBx__2__DM2 CYREG_PRT2_DM2\r
+#define SCSI_In_DBx__2__DR CYREG_PRT2_DR\r
+#define SCSI_In_DBx__2__INP_DIS CYREG_PRT2_INP_DIS\r
+#define SCSI_In_DBx__2__INTTYPE CYREG_PICU2_INTTYPE6\r
+#define SCSI_In_DBx__2__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG\r
+#define SCSI_In_DBx__2__LCD_EN CYREG_PRT2_LCD_EN\r
+#define SCSI_In_DBx__2__MASK 0x40u\r
+#define SCSI_In_DBx__2__PC CYREG_PRT2_PC6\r
+#define SCSI_In_DBx__2__PORT 2u\r
+#define SCSI_In_DBx__2__PRT CYREG_PRT2_PRT\r
+#define SCSI_In_DBx__2__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL\r
+#define SCSI_In_DBx__2__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN\r
+#define SCSI_In_DBx__2__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0\r
+#define SCSI_In_DBx__2__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1\r
+#define SCSI_In_DBx__2__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0\r
+#define SCSI_In_DBx__2__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1\r
+#define SCSI_In_DBx__2__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT\r
+#define SCSI_In_DBx__2__PS CYREG_PRT2_PS\r
+#define SCSI_In_DBx__2__SHIFT 6u\r
+#define SCSI_In_DBx__2__SLW CYREG_PRT2_SLW\r
+#define SCSI_In_DBx__3__AG CYREG_PRT2_AG\r
+#define SCSI_In_DBx__3__AMUX CYREG_PRT2_AMUX\r
+#define SCSI_In_DBx__3__BIE CYREG_PRT2_BIE\r
+#define SCSI_In_DBx__3__BIT_MASK CYREG_PRT2_BIT_MASK\r
+#define SCSI_In_DBx__3__BYP CYREG_PRT2_BYP\r
+#define SCSI_In_DBx__3__CTL CYREG_PRT2_CTL\r
+#define SCSI_In_DBx__3__DM0 CYREG_PRT2_DM0\r
+#define SCSI_In_DBx__3__DM1 CYREG_PRT2_DM1\r
+#define SCSI_In_DBx__3__DM2 CYREG_PRT2_DM2\r
+#define SCSI_In_DBx__3__DR CYREG_PRT2_DR\r
+#define SCSI_In_DBx__3__INP_DIS CYREG_PRT2_INP_DIS\r
+#define SCSI_In_DBx__3__INTTYPE CYREG_PICU2_INTTYPE5\r
+#define SCSI_In_DBx__3__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG\r
+#define SCSI_In_DBx__3__LCD_EN CYREG_PRT2_LCD_EN\r
+#define SCSI_In_DBx__3__MASK 0x20u\r
+#define SCSI_In_DBx__3__PC CYREG_PRT2_PC5\r
+#define SCSI_In_DBx__3__PORT 2u\r
+#define SCSI_In_DBx__3__PRT CYREG_PRT2_PRT\r
+#define SCSI_In_DBx__3__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL\r
+#define SCSI_In_DBx__3__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN\r
+#define SCSI_In_DBx__3__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0\r
+#define SCSI_In_DBx__3__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1\r
+#define SCSI_In_DBx__3__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0\r
+#define SCSI_In_DBx__3__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1\r
+#define SCSI_In_DBx__3__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT\r
+#define SCSI_In_DBx__3__PS CYREG_PRT2_PS\r
+#define SCSI_In_DBx__3__SHIFT 5u\r
+#define SCSI_In_DBx__3__SLW CYREG_PRT2_SLW\r
+#define SCSI_In_DBx__4__AG CYREG_PRT2_AG\r
+#define SCSI_In_DBx__4__AMUX CYREG_PRT2_AMUX\r
+#define SCSI_In_DBx__4__BIE CYREG_PRT2_BIE\r
+#define SCSI_In_DBx__4__BIT_MASK CYREG_PRT2_BIT_MASK\r
+#define SCSI_In_DBx__4__BYP CYREG_PRT2_BYP\r
+#define SCSI_In_DBx__4__CTL CYREG_PRT2_CTL\r
+#define SCSI_In_DBx__4__DM0 CYREG_PRT2_DM0\r
+#define SCSI_In_DBx__4__DM1 CYREG_PRT2_DM1\r
+#define SCSI_In_DBx__4__DM2 CYREG_PRT2_DM2\r
+#define SCSI_In_DBx__4__DR CYREG_PRT2_DR\r
+#define SCSI_In_DBx__4__INP_DIS CYREG_PRT2_INP_DIS\r
+#define SCSI_In_DBx__4__INTTYPE CYREG_PICU2_INTTYPE4\r
+#define SCSI_In_DBx__4__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG\r
+#define SCSI_In_DBx__4__LCD_EN CYREG_PRT2_LCD_EN\r
+#define SCSI_In_DBx__4__MASK 0x10u\r
+#define SCSI_In_DBx__4__PC CYREG_PRT2_PC4\r
+#define SCSI_In_DBx__4__PORT 2u\r
+#define SCSI_In_DBx__4__PRT CYREG_PRT2_PRT\r
+#define SCSI_In_DBx__4__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL\r
+#define SCSI_In_DBx__4__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN\r
+#define SCSI_In_DBx__4__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0\r
+#define SCSI_In_DBx__4__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1\r
+#define SCSI_In_DBx__4__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0\r
+#define SCSI_In_DBx__4__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1\r
+#define SCSI_In_DBx__4__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT\r
+#define SCSI_In_DBx__4__PS CYREG_PRT2_PS\r
+#define SCSI_In_DBx__4__SHIFT 4u\r
+#define SCSI_In_DBx__4__SLW CYREG_PRT2_SLW\r
+#define SCSI_In_DBx__5__AG CYREG_PRT2_AG\r
+#define SCSI_In_DBx__5__AMUX CYREG_PRT2_AMUX\r
+#define SCSI_In_DBx__5__BIE CYREG_PRT2_BIE\r
+#define SCSI_In_DBx__5__BIT_MASK CYREG_PRT2_BIT_MASK\r
+#define SCSI_In_DBx__5__BYP CYREG_PRT2_BYP\r
+#define SCSI_In_DBx__5__CTL CYREG_PRT2_CTL\r
+#define SCSI_In_DBx__5__DM0 CYREG_PRT2_DM0\r
+#define SCSI_In_DBx__5__DM1 CYREG_PRT2_DM1\r
+#define SCSI_In_DBx__5__DM2 CYREG_PRT2_DM2\r
+#define SCSI_In_DBx__5__DR CYREG_PRT2_DR\r
+#define SCSI_In_DBx__5__INP_DIS CYREG_PRT2_INP_DIS\r
+#define SCSI_In_DBx__5__INTTYPE CYREG_PICU2_INTTYPE3\r
+#define SCSI_In_DBx__5__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG\r
+#define SCSI_In_DBx__5__LCD_EN CYREG_PRT2_LCD_EN\r
+#define SCSI_In_DBx__5__MASK 0x08u\r
+#define SCSI_In_DBx__5__PC CYREG_PRT2_PC3\r
+#define SCSI_In_DBx__5__PORT 2u\r
+#define SCSI_In_DBx__5__PRT CYREG_PRT2_PRT\r
+#define SCSI_In_DBx__5__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL\r
+#define SCSI_In_DBx__5__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN\r
+#define SCSI_In_DBx__5__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0\r
+#define SCSI_In_DBx__5__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1\r
+#define SCSI_In_DBx__5__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0\r
+#define SCSI_In_DBx__5__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1\r
+#define SCSI_In_DBx__5__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT\r
+#define SCSI_In_DBx__5__PS CYREG_PRT2_PS\r
+#define SCSI_In_DBx__5__SHIFT 3u\r
+#define SCSI_In_DBx__5__SLW CYREG_PRT2_SLW\r
+#define SCSI_In_DBx__6__AG CYREG_PRT2_AG\r
+#define SCSI_In_DBx__6__AMUX CYREG_PRT2_AMUX\r
+#define SCSI_In_DBx__6__BIE CYREG_PRT2_BIE\r
+#define SCSI_In_DBx__6__BIT_MASK CYREG_PRT2_BIT_MASK\r
+#define SCSI_In_DBx__6__BYP CYREG_PRT2_BYP\r
+#define SCSI_In_DBx__6__CTL CYREG_PRT2_CTL\r
+#define SCSI_In_DBx__6__DM0 CYREG_PRT2_DM0\r
+#define SCSI_In_DBx__6__DM1 CYREG_PRT2_DM1\r
+#define SCSI_In_DBx__6__DM2 CYREG_PRT2_DM2\r
+#define SCSI_In_DBx__6__DR CYREG_PRT2_DR\r
+#define SCSI_In_DBx__6__INP_DIS CYREG_PRT2_INP_DIS\r
+#define SCSI_In_DBx__6__INTTYPE CYREG_PICU2_INTTYPE2\r
+#define SCSI_In_DBx__6__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG\r
+#define SCSI_In_DBx__6__LCD_EN CYREG_PRT2_LCD_EN\r
+#define SCSI_In_DBx__6__MASK 0x04u\r
+#define SCSI_In_DBx__6__PC CYREG_PRT2_PC2\r
+#define SCSI_In_DBx__6__PORT 2u\r
+#define SCSI_In_DBx__6__PRT CYREG_PRT2_PRT\r
+#define SCSI_In_DBx__6__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL\r
+#define SCSI_In_DBx__6__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN\r
+#define SCSI_In_DBx__6__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0\r
+#define SCSI_In_DBx__6__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1\r
+#define SCSI_In_DBx__6__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0\r
+#define SCSI_In_DBx__6__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1\r
+#define SCSI_In_DBx__6__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT\r
+#define SCSI_In_DBx__6__PS CYREG_PRT2_PS\r
+#define SCSI_In_DBx__6__SHIFT 2u\r
+#define SCSI_In_DBx__6__SLW CYREG_PRT2_SLW\r
+#define SCSI_In_DBx__7__AG CYREG_PRT2_AG\r
+#define SCSI_In_DBx__7__AMUX CYREG_PRT2_AMUX\r
+#define SCSI_In_DBx__7__BIE CYREG_PRT2_BIE\r
+#define SCSI_In_DBx__7__BIT_MASK CYREG_PRT2_BIT_MASK\r
+#define SCSI_In_DBx__7__BYP CYREG_PRT2_BYP\r
+#define SCSI_In_DBx__7__CTL CYREG_PRT2_CTL\r
+#define SCSI_In_DBx__7__DM0 CYREG_PRT2_DM0\r
+#define SCSI_In_DBx__7__DM1 CYREG_PRT2_DM1\r
+#define SCSI_In_DBx__7__DM2 CYREG_PRT2_DM2\r
+#define SCSI_In_DBx__7__DR CYREG_PRT2_DR\r
+#define SCSI_In_DBx__7__INP_DIS CYREG_PRT2_INP_DIS\r
+#define SCSI_In_DBx__7__INTTYPE CYREG_PICU2_INTTYPE1\r
+#define SCSI_In_DBx__7__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG\r
+#define SCSI_In_DBx__7__LCD_EN CYREG_PRT2_LCD_EN\r
+#define SCSI_In_DBx__7__MASK 0x02u\r
+#define SCSI_In_DBx__7__PC CYREG_PRT2_PC1\r
+#define SCSI_In_DBx__7__PORT 2u\r
+#define SCSI_In_DBx__7__PRT CYREG_PRT2_PRT\r
+#define SCSI_In_DBx__7__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL\r
+#define SCSI_In_DBx__7__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN\r
+#define SCSI_In_DBx__7__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0\r
+#define SCSI_In_DBx__7__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1\r
+#define SCSI_In_DBx__7__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0\r
+#define SCSI_In_DBx__7__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1\r
+#define SCSI_In_DBx__7__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT\r
+#define SCSI_In_DBx__7__PS CYREG_PRT2_PS\r
+#define SCSI_In_DBx__7__SHIFT 1u\r
+#define SCSI_In_DBx__7__SLW CYREG_PRT2_SLW\r
+#define SCSI_In_DBx__DB0__AG CYREG_PRT12_AG\r
+#define SCSI_In_DBx__DB0__BIE CYREG_PRT12_BIE\r
+#define SCSI_In_DBx__DB0__BIT_MASK CYREG_PRT12_BIT_MASK\r
+#define SCSI_In_DBx__DB0__BYP CYREG_PRT12_BYP\r
+#define SCSI_In_DBx__DB0__DM0 CYREG_PRT12_DM0\r
+#define SCSI_In_DBx__DB0__DM1 CYREG_PRT12_DM1\r
+#define SCSI_In_DBx__DB0__DM2 CYREG_PRT12_DM2\r
+#define SCSI_In_DBx__DB0__DR CYREG_PRT12_DR\r
+#define SCSI_In_DBx__DB0__INP_DIS CYREG_PRT12_INP_DIS\r
+#define SCSI_In_DBx__DB0__INTTYPE CYREG_PICU12_INTTYPE4\r
+#define SCSI_In_DBx__DB0__MASK 0x10u\r
+#define SCSI_In_DBx__DB0__PC CYREG_PRT12_PC4\r
+#define SCSI_In_DBx__DB0__PORT 12u\r
+#define SCSI_In_DBx__DB0__PRT CYREG_PRT12_PRT\r
+#define SCSI_In_DBx__DB0__PRTDSI__DBL_SYNC_IN CYREG_PRT12_DBL_SYNC_IN\r
+#define SCSI_In_DBx__DB0__PRTDSI__OE_SEL0 CYREG_PRT12_OE_SEL0\r
+#define SCSI_In_DBx__DB0__PRTDSI__OE_SEL1 CYREG_PRT12_OE_SEL1\r
+#define SCSI_In_DBx__DB0__PRTDSI__OUT_SEL0 CYREG_PRT12_OUT_SEL0\r
+#define SCSI_In_DBx__DB0__PRTDSI__OUT_SEL1 CYREG_PRT12_OUT_SEL1\r
+#define SCSI_In_DBx__DB0__PRTDSI__SYNC_OUT CYREG_PRT12_SYNC_OUT\r
+#define SCSI_In_DBx__DB0__PS CYREG_PRT12_PS\r
+#define SCSI_In_DBx__DB0__SHIFT 4u\r
+#define SCSI_In_DBx__DB0__SIO_CFG CYREG_PRT12_SIO_CFG\r
+#define SCSI_In_DBx__DB0__SIO_DIFF CYREG_PRT12_SIO_DIFF\r
+#define SCSI_In_DBx__DB0__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN\r
+#define SCSI_In_DBx__DB0__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ\r
+#define SCSI_In_DBx__DB0__SLW CYREG_PRT12_SLW\r
+#define SCSI_In_DBx__DB1__AG CYREG_PRT2_AG\r
+#define SCSI_In_DBx__DB1__AMUX CYREG_PRT2_AMUX\r
+#define SCSI_In_DBx__DB1__BIE CYREG_PRT2_BIE\r
+#define SCSI_In_DBx__DB1__BIT_MASK CYREG_PRT2_BIT_MASK\r
+#define SCSI_In_DBx__DB1__BYP CYREG_PRT2_BYP\r
+#define SCSI_In_DBx__DB1__CTL CYREG_PRT2_CTL\r
+#define SCSI_In_DBx__DB1__DM0 CYREG_PRT2_DM0\r
+#define SCSI_In_DBx__DB1__DM1 CYREG_PRT2_DM1\r
+#define SCSI_In_DBx__DB1__DM2 CYREG_PRT2_DM2\r
+#define SCSI_In_DBx__DB1__DR CYREG_PRT2_DR\r
+#define SCSI_In_DBx__DB1__INP_DIS CYREG_PRT2_INP_DIS\r
+#define SCSI_In_DBx__DB1__INTTYPE CYREG_PICU2_INTTYPE7\r
+#define SCSI_In_DBx__DB1__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG\r
+#define SCSI_In_DBx__DB1__LCD_EN CYREG_PRT2_LCD_EN\r
+#define SCSI_In_DBx__DB1__MASK 0x80u\r
+#define SCSI_In_DBx__DB1__PC CYREG_PRT2_PC7\r
+#define SCSI_In_DBx__DB1__PORT 2u\r
+#define SCSI_In_DBx__DB1__PRT CYREG_PRT2_PRT\r
+#define SCSI_In_DBx__DB1__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL\r
+#define SCSI_In_DBx__DB1__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN\r
+#define SCSI_In_DBx__DB1__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0\r
+#define SCSI_In_DBx__DB1__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1\r
+#define SCSI_In_DBx__DB1__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0\r
+#define SCSI_In_DBx__DB1__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1\r
+#define SCSI_In_DBx__DB1__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT\r
+#define SCSI_In_DBx__DB1__PS CYREG_PRT2_PS\r
+#define SCSI_In_DBx__DB1__SHIFT 7u\r
+#define SCSI_In_DBx__DB1__SLW CYREG_PRT2_SLW\r
+#define SCSI_In_DBx__DB2__AG CYREG_PRT2_AG\r
+#define SCSI_In_DBx__DB2__AMUX CYREG_PRT2_AMUX\r
+#define SCSI_In_DBx__DB2__BIE CYREG_PRT2_BIE\r
+#define SCSI_In_DBx__DB2__BIT_MASK CYREG_PRT2_BIT_MASK\r
+#define SCSI_In_DBx__DB2__BYP CYREG_PRT2_BYP\r
+#define SCSI_In_DBx__DB2__CTL CYREG_PRT2_CTL\r
+#define SCSI_In_DBx__DB2__DM0 CYREG_PRT2_DM0\r
+#define SCSI_In_DBx__DB2__DM1 CYREG_PRT2_DM1\r
+#define SCSI_In_DBx__DB2__DM2 CYREG_PRT2_DM2\r
+#define SCSI_In_DBx__DB2__DR CYREG_PRT2_DR\r
+#define SCSI_In_DBx__DB2__INP_DIS CYREG_PRT2_INP_DIS\r
+#define SCSI_In_DBx__DB2__INTTYPE CYREG_PICU2_INTTYPE6\r
+#define SCSI_In_DBx__DB2__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG\r
+#define SCSI_In_DBx__DB2__LCD_EN CYREG_PRT2_LCD_EN\r
+#define SCSI_In_DBx__DB2__MASK 0x40u\r
+#define SCSI_In_DBx__DB2__PC CYREG_PRT2_PC6\r
+#define SCSI_In_DBx__DB2__PORT 2u\r
+#define SCSI_In_DBx__DB2__PRT CYREG_PRT2_PRT\r
+#define SCSI_In_DBx__DB2__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL\r
+#define SCSI_In_DBx__DB2__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN\r
+#define SCSI_In_DBx__DB2__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0\r
+#define SCSI_In_DBx__DB2__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1\r
+#define SCSI_In_DBx__DB2__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0\r
+#define SCSI_In_DBx__DB2__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1\r
+#define SCSI_In_DBx__DB2__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT\r
+#define SCSI_In_DBx__DB2__PS CYREG_PRT2_PS\r
+#define SCSI_In_DBx__DB2__SHIFT 6u\r
+#define SCSI_In_DBx__DB2__SLW CYREG_PRT2_SLW\r
+#define SCSI_In_DBx__DB3__AG CYREG_PRT2_AG\r
+#define SCSI_In_DBx__DB3__AMUX CYREG_PRT2_AMUX\r
+#define SCSI_In_DBx__DB3__BIE CYREG_PRT2_BIE\r
+#define SCSI_In_DBx__DB3__BIT_MASK CYREG_PRT2_BIT_MASK\r
+#define SCSI_In_DBx__DB3__BYP CYREG_PRT2_BYP\r
+#define SCSI_In_DBx__DB3__CTL CYREG_PRT2_CTL\r
+#define SCSI_In_DBx__DB3__DM0 CYREG_PRT2_DM0\r
+#define SCSI_In_DBx__DB3__DM1 CYREG_PRT2_DM1\r
+#define SCSI_In_DBx__DB3__DM2 CYREG_PRT2_DM2\r
+#define SCSI_In_DBx__DB3__DR CYREG_PRT2_DR\r
+#define SCSI_In_DBx__DB3__INP_DIS CYREG_PRT2_INP_DIS\r
+#define SCSI_In_DBx__DB3__INTTYPE CYREG_PICU2_INTTYPE5\r
+#define SCSI_In_DBx__DB3__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG\r
+#define SCSI_In_DBx__DB3__LCD_EN CYREG_PRT2_LCD_EN\r
+#define SCSI_In_DBx__DB3__MASK 0x20u\r
+#define SCSI_In_DBx__DB3__PC CYREG_PRT2_PC5\r
+#define SCSI_In_DBx__DB3__PORT 2u\r
+#define SCSI_In_DBx__DB3__PRT CYREG_PRT2_PRT\r
+#define SCSI_In_DBx__DB3__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL\r
+#define SCSI_In_DBx__DB3__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN\r
+#define SCSI_In_DBx__DB3__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0\r
+#define SCSI_In_DBx__DB3__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1\r
+#define SCSI_In_DBx__DB3__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0\r
+#define SCSI_In_DBx__DB3__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1\r
+#define SCSI_In_DBx__DB3__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT\r
+#define SCSI_In_DBx__DB3__PS CYREG_PRT2_PS\r
+#define SCSI_In_DBx__DB3__SHIFT 5u\r
+#define SCSI_In_DBx__DB3__SLW CYREG_PRT2_SLW\r
+#define SCSI_In_DBx__DB4__AG CYREG_PRT2_AG\r
+#define SCSI_In_DBx__DB4__AMUX CYREG_PRT2_AMUX\r
+#define SCSI_In_DBx__DB4__BIE CYREG_PRT2_BIE\r
+#define SCSI_In_DBx__DB4__BIT_MASK CYREG_PRT2_BIT_MASK\r
+#define SCSI_In_DBx__DB4__BYP CYREG_PRT2_BYP\r
+#define SCSI_In_DBx__DB4__CTL CYREG_PRT2_CTL\r
+#define SCSI_In_DBx__DB4__DM0 CYREG_PRT2_DM0\r
+#define SCSI_In_DBx__DB4__DM1 CYREG_PRT2_DM1\r
+#define SCSI_In_DBx__DB4__DM2 CYREG_PRT2_DM2\r
+#define SCSI_In_DBx__DB4__DR CYREG_PRT2_DR\r
+#define SCSI_In_DBx__DB4__INP_DIS CYREG_PRT2_INP_DIS\r
+#define SCSI_In_DBx__DB4__INTTYPE CYREG_PICU2_INTTYPE4\r
+#define SCSI_In_DBx__DB4__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG\r
+#define SCSI_In_DBx__DB4__LCD_EN CYREG_PRT2_LCD_EN\r
+#define SCSI_In_DBx__DB4__MASK 0x10u\r
+#define SCSI_In_DBx__DB4__PC CYREG_PRT2_PC4\r
+#define SCSI_In_DBx__DB4__PORT 2u\r
+#define SCSI_In_DBx__DB4__PRT CYREG_PRT2_PRT\r
+#define SCSI_In_DBx__DB4__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL\r
+#define SCSI_In_DBx__DB4__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN\r
+#define SCSI_In_DBx__DB4__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0\r
+#define SCSI_In_DBx__DB4__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1\r
+#define SCSI_In_DBx__DB4__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0\r
+#define SCSI_In_DBx__DB4__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1\r
+#define SCSI_In_DBx__DB4__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT\r
+#define SCSI_In_DBx__DB4__PS CYREG_PRT2_PS\r
+#define SCSI_In_DBx__DB4__SHIFT 4u\r
+#define SCSI_In_DBx__DB4__SLW CYREG_PRT2_SLW\r
+#define SCSI_In_DBx__DB5__AG CYREG_PRT2_AG\r
+#define SCSI_In_DBx__DB5__AMUX CYREG_PRT2_AMUX\r
+#define SCSI_In_DBx__DB5__BIE CYREG_PRT2_BIE\r
+#define SCSI_In_DBx__DB5__BIT_MASK CYREG_PRT2_BIT_MASK\r
+#define SCSI_In_DBx__DB5__BYP CYREG_PRT2_BYP\r
+#define SCSI_In_DBx__DB5__CTL CYREG_PRT2_CTL\r
+#define SCSI_In_DBx__DB5__DM0 CYREG_PRT2_DM0\r
+#define SCSI_In_DBx__DB5__DM1 CYREG_PRT2_DM1\r
+#define SCSI_In_DBx__DB5__DM2 CYREG_PRT2_DM2\r
+#define SCSI_In_DBx__DB5__DR CYREG_PRT2_DR\r
+#define SCSI_In_DBx__DB5__INP_DIS CYREG_PRT2_INP_DIS\r
+#define SCSI_In_DBx__DB5__INTTYPE CYREG_PICU2_INTTYPE3\r
+#define SCSI_In_DBx__DB5__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG\r
+#define SCSI_In_DBx__DB5__LCD_EN CYREG_PRT2_LCD_EN\r
+#define SCSI_In_DBx__DB5__MASK 0x08u\r
+#define SCSI_In_DBx__DB5__PC CYREG_PRT2_PC3\r
+#define SCSI_In_DBx__DB5__PORT 2u\r
+#define SCSI_In_DBx__DB5__PRT CYREG_PRT2_PRT\r
+#define SCSI_In_DBx__DB5__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL\r
+#define SCSI_In_DBx__DB5__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN\r
+#define SCSI_In_DBx__DB5__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0\r
+#define SCSI_In_DBx__DB5__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1\r
+#define SCSI_In_DBx__DB5__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0\r
+#define SCSI_In_DBx__DB5__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1\r
+#define SCSI_In_DBx__DB5__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT\r
+#define SCSI_In_DBx__DB5__PS CYREG_PRT2_PS\r
+#define SCSI_In_DBx__DB5__SHIFT 3u\r
+#define SCSI_In_DBx__DB5__SLW CYREG_PRT2_SLW\r
+#define SCSI_In_DBx__DB6__AG CYREG_PRT2_AG\r
+#define SCSI_In_DBx__DB6__AMUX CYREG_PRT2_AMUX\r
+#define SCSI_In_DBx__DB6__BIE CYREG_PRT2_BIE\r
+#define SCSI_In_DBx__DB6__BIT_MASK CYREG_PRT2_BIT_MASK\r
+#define SCSI_In_DBx__DB6__BYP CYREG_PRT2_BYP\r
+#define SCSI_In_DBx__DB6__CTL CYREG_PRT2_CTL\r
+#define SCSI_In_DBx__DB6__DM0 CYREG_PRT2_DM0\r
+#define SCSI_In_DBx__DB6__DM1 CYREG_PRT2_DM1\r
+#define SCSI_In_DBx__DB6__DM2 CYREG_PRT2_DM2\r
+#define SCSI_In_DBx__DB6__DR CYREG_PRT2_DR\r
+#define SCSI_In_DBx__DB6__INP_DIS CYREG_PRT2_INP_DIS\r
+#define SCSI_In_DBx__DB6__INTTYPE CYREG_PICU2_INTTYPE2\r
+#define SCSI_In_DBx__DB6__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG\r
+#define SCSI_In_DBx__DB6__LCD_EN CYREG_PRT2_LCD_EN\r
+#define SCSI_In_DBx__DB6__MASK 0x04u\r
+#define SCSI_In_DBx__DB6__PC CYREG_PRT2_PC2\r
+#define SCSI_In_DBx__DB6__PORT 2u\r
+#define SCSI_In_DBx__DB6__PRT CYREG_PRT2_PRT\r
+#define SCSI_In_DBx__DB6__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL\r
+#define SCSI_In_DBx__DB6__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN\r
+#define SCSI_In_DBx__DB6__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0\r
+#define SCSI_In_DBx__DB6__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1\r
+#define SCSI_In_DBx__DB6__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0\r
+#define SCSI_In_DBx__DB6__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1\r
+#define SCSI_In_DBx__DB6__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT\r
+#define SCSI_In_DBx__DB6__PS CYREG_PRT2_PS\r
+#define SCSI_In_DBx__DB6__SHIFT 2u\r
+#define SCSI_In_DBx__DB6__SLW CYREG_PRT2_SLW\r
+#define SCSI_In_DBx__DB7__AG CYREG_PRT2_AG\r
+#define SCSI_In_DBx__DB7__AMUX CYREG_PRT2_AMUX\r
+#define SCSI_In_DBx__DB7__BIE CYREG_PRT2_BIE\r
+#define SCSI_In_DBx__DB7__BIT_MASK CYREG_PRT2_BIT_MASK\r
+#define SCSI_In_DBx__DB7__BYP CYREG_PRT2_BYP\r
+#define SCSI_In_DBx__DB7__CTL CYREG_PRT2_CTL\r
+#define SCSI_In_DBx__DB7__DM0 CYREG_PRT2_DM0\r
+#define SCSI_In_DBx__DB7__DM1 CYREG_PRT2_DM1\r
+#define SCSI_In_DBx__DB7__DM2 CYREG_PRT2_DM2\r
+#define SCSI_In_DBx__DB7__DR CYREG_PRT2_DR\r
+#define SCSI_In_DBx__DB7__INP_DIS CYREG_PRT2_INP_DIS\r
+#define SCSI_In_DBx__DB7__INTTYPE CYREG_PICU2_INTTYPE1\r
+#define SCSI_In_DBx__DB7__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG\r
+#define SCSI_In_DBx__DB7__LCD_EN CYREG_PRT2_LCD_EN\r
+#define SCSI_In_DBx__DB7__MASK 0x02u\r
+#define SCSI_In_DBx__DB7__PC CYREG_PRT2_PC1\r
+#define SCSI_In_DBx__DB7__PORT 2u\r
+#define SCSI_In_DBx__DB7__PRT CYREG_PRT2_PRT\r
+#define SCSI_In_DBx__DB7__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL\r
+#define SCSI_In_DBx__DB7__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN\r
+#define SCSI_In_DBx__DB7__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0\r
+#define SCSI_In_DBx__DB7__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1\r
+#define SCSI_In_DBx__DB7__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0\r
+#define SCSI_In_DBx__DB7__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1\r
+#define SCSI_In_DBx__DB7__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT\r
+#define SCSI_In_DBx__DB7__PS CYREG_PRT2_PS\r
+#define SCSI_In_DBx__DB7__SHIFT 1u\r
+#define SCSI_In_DBx__DB7__SLW CYREG_PRT2_SLW\r
 \r
 /* SCSI_Noise */\r
 #define SCSI_Noise__0__AG CYREG_PRT12_AG\r
@@ -2774,6 +1165,1772 @@
 #define SCSI_Noise__SEL__SHIFT 0u\r
 #define SCSI_Noise__SEL__SLW CYREG_PRT5_SLW\r
 \r
+/* SCSI_Out */\r
+#define SCSI_Out__0__AG CYREG_PRT4_AG\r
+#define SCSI_Out__0__AMUX CYREG_PRT4_AMUX\r
+#define SCSI_Out__0__BIE CYREG_PRT4_BIE\r
+#define SCSI_Out__0__BIT_MASK CYREG_PRT4_BIT_MASK\r
+#define SCSI_Out__0__BYP CYREG_PRT4_BYP\r
+#define SCSI_Out__0__CTL CYREG_PRT4_CTL\r
+#define SCSI_Out__0__DM0 CYREG_PRT4_DM0\r
+#define SCSI_Out__0__DM1 CYREG_PRT4_DM1\r
+#define SCSI_Out__0__DM2 CYREG_PRT4_DM2\r
+#define SCSI_Out__0__DR CYREG_PRT4_DR\r
+#define SCSI_Out__0__INP_DIS CYREG_PRT4_INP_DIS\r
+#define SCSI_Out__0__INTTYPE CYREG_PICU4_INTTYPE3\r
+#define SCSI_Out__0__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG\r
+#define SCSI_Out__0__LCD_EN CYREG_PRT4_LCD_EN\r
+#define SCSI_Out__0__MASK 0x08u\r
+#define SCSI_Out__0__PC CYREG_PRT4_PC3\r
+#define SCSI_Out__0__PORT 4u\r
+#define SCSI_Out__0__PRT CYREG_PRT4_PRT\r
+#define SCSI_Out__0__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL\r
+#define SCSI_Out__0__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN\r
+#define SCSI_Out__0__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0\r
+#define SCSI_Out__0__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1\r
+#define SCSI_Out__0__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0\r
+#define SCSI_Out__0__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1\r
+#define SCSI_Out__0__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT\r
+#define SCSI_Out__0__PS CYREG_PRT4_PS\r
+#define SCSI_Out__0__SHIFT 3u\r
+#define SCSI_Out__0__SLW CYREG_PRT4_SLW\r
+#define SCSI_Out__1__AG CYREG_PRT4_AG\r
+#define SCSI_Out__1__AMUX CYREG_PRT4_AMUX\r
+#define SCSI_Out__1__BIE CYREG_PRT4_BIE\r
+#define SCSI_Out__1__BIT_MASK CYREG_PRT4_BIT_MASK\r
+#define SCSI_Out__1__BYP CYREG_PRT4_BYP\r
+#define SCSI_Out__1__CTL CYREG_PRT4_CTL\r
+#define SCSI_Out__1__DM0 CYREG_PRT4_DM0\r
+#define SCSI_Out__1__DM1 CYREG_PRT4_DM1\r
+#define SCSI_Out__1__DM2 CYREG_PRT4_DM2\r
+#define SCSI_Out__1__DR CYREG_PRT4_DR\r
+#define SCSI_Out__1__INP_DIS CYREG_PRT4_INP_DIS\r
+#define SCSI_Out__1__INTTYPE CYREG_PICU4_INTTYPE2\r
+#define SCSI_Out__1__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG\r
+#define SCSI_Out__1__LCD_EN CYREG_PRT4_LCD_EN\r
+#define SCSI_Out__1__MASK 0x04u\r
+#define SCSI_Out__1__PC CYREG_PRT4_PC2\r
+#define SCSI_Out__1__PORT 4u\r
+#define SCSI_Out__1__PRT CYREG_PRT4_PRT\r
+#define SCSI_Out__1__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL\r
+#define SCSI_Out__1__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN\r
+#define SCSI_Out__1__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0\r
+#define SCSI_Out__1__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1\r
+#define SCSI_Out__1__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0\r
+#define SCSI_Out__1__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1\r
+#define SCSI_Out__1__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT\r
+#define SCSI_Out__1__PS CYREG_PRT4_PS\r
+#define SCSI_Out__1__SHIFT 2u\r
+#define SCSI_Out__1__SLW CYREG_PRT4_SLW\r
+#define SCSI_Out__2__AG CYREG_PRT0_AG\r
+#define SCSI_Out__2__AMUX CYREG_PRT0_AMUX\r
+#define SCSI_Out__2__BIE CYREG_PRT0_BIE\r
+#define SCSI_Out__2__BIT_MASK CYREG_PRT0_BIT_MASK\r
+#define SCSI_Out__2__BYP CYREG_PRT0_BYP\r
+#define SCSI_Out__2__CTL CYREG_PRT0_CTL\r
+#define SCSI_Out__2__DM0 CYREG_PRT0_DM0\r
+#define SCSI_Out__2__DM1 CYREG_PRT0_DM1\r
+#define SCSI_Out__2__DM2 CYREG_PRT0_DM2\r
+#define SCSI_Out__2__DR CYREG_PRT0_DR\r
+#define SCSI_Out__2__INP_DIS CYREG_PRT0_INP_DIS\r
+#define SCSI_Out__2__INTTYPE CYREG_PICU0_INTTYPE7\r
+#define SCSI_Out__2__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG\r
+#define SCSI_Out__2__LCD_EN CYREG_PRT0_LCD_EN\r
+#define SCSI_Out__2__MASK 0x80u\r
+#define SCSI_Out__2__PC CYREG_PRT0_PC7\r
+#define SCSI_Out__2__PORT 0u\r
+#define SCSI_Out__2__PRT CYREG_PRT0_PRT\r
+#define SCSI_Out__2__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL\r
+#define SCSI_Out__2__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN\r
+#define SCSI_Out__2__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0\r
+#define SCSI_Out__2__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1\r
+#define SCSI_Out__2__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0\r
+#define SCSI_Out__2__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1\r
+#define SCSI_Out__2__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT\r
+#define SCSI_Out__2__PS CYREG_PRT0_PS\r
+#define SCSI_Out__2__SHIFT 7u\r
+#define SCSI_Out__2__SLW CYREG_PRT0_SLW\r
+#define SCSI_Out__3__AG CYREG_PRT0_AG\r
+#define SCSI_Out__3__AMUX CYREG_PRT0_AMUX\r
+#define SCSI_Out__3__BIE CYREG_PRT0_BIE\r
+#define SCSI_Out__3__BIT_MASK CYREG_PRT0_BIT_MASK\r
+#define SCSI_Out__3__BYP CYREG_PRT0_BYP\r
+#define SCSI_Out__3__CTL CYREG_PRT0_CTL\r
+#define SCSI_Out__3__DM0 CYREG_PRT0_DM0\r
+#define SCSI_Out__3__DM1 CYREG_PRT0_DM1\r
+#define SCSI_Out__3__DM2 CYREG_PRT0_DM2\r
+#define SCSI_Out__3__DR CYREG_PRT0_DR\r
+#define SCSI_Out__3__INP_DIS CYREG_PRT0_INP_DIS\r
+#define SCSI_Out__3__INTTYPE CYREG_PICU0_INTTYPE6\r
+#define SCSI_Out__3__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG\r
+#define SCSI_Out__3__LCD_EN CYREG_PRT0_LCD_EN\r
+#define SCSI_Out__3__MASK 0x40u\r
+#define SCSI_Out__3__PC CYREG_PRT0_PC6\r
+#define SCSI_Out__3__PORT 0u\r
+#define SCSI_Out__3__PRT CYREG_PRT0_PRT\r
+#define SCSI_Out__3__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL\r
+#define SCSI_Out__3__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN\r
+#define SCSI_Out__3__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0\r
+#define SCSI_Out__3__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1\r
+#define SCSI_Out__3__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0\r
+#define SCSI_Out__3__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1\r
+#define SCSI_Out__3__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT\r
+#define SCSI_Out__3__PS CYREG_PRT0_PS\r
+#define SCSI_Out__3__SHIFT 6u\r
+#define SCSI_Out__3__SLW CYREG_PRT0_SLW\r
+#define SCSI_Out__4__AG CYREG_PRT0_AG\r
+#define SCSI_Out__4__AMUX CYREG_PRT0_AMUX\r
+#define SCSI_Out__4__BIE CYREG_PRT0_BIE\r
+#define SCSI_Out__4__BIT_MASK CYREG_PRT0_BIT_MASK\r
+#define SCSI_Out__4__BYP CYREG_PRT0_BYP\r
+#define SCSI_Out__4__CTL CYREG_PRT0_CTL\r
+#define SCSI_Out__4__DM0 CYREG_PRT0_DM0\r
+#define SCSI_Out__4__DM1 CYREG_PRT0_DM1\r
+#define SCSI_Out__4__DM2 CYREG_PRT0_DM2\r
+#define SCSI_Out__4__DR CYREG_PRT0_DR\r
+#define SCSI_Out__4__INP_DIS CYREG_PRT0_INP_DIS\r
+#define SCSI_Out__4__INTTYPE CYREG_PICU0_INTTYPE5\r
+#define SCSI_Out__4__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG\r
+#define SCSI_Out__4__LCD_EN CYREG_PRT0_LCD_EN\r
+#define SCSI_Out__4__MASK 0x20u\r
+#define SCSI_Out__4__PC CYREG_PRT0_PC5\r
+#define SCSI_Out__4__PORT 0u\r
+#define SCSI_Out__4__PRT CYREG_PRT0_PRT\r
+#define SCSI_Out__4__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL\r
+#define SCSI_Out__4__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN\r
+#define SCSI_Out__4__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0\r
+#define SCSI_Out__4__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1\r
+#define SCSI_Out__4__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0\r
+#define SCSI_Out__4__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1\r
+#define SCSI_Out__4__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT\r
+#define SCSI_Out__4__PS CYREG_PRT0_PS\r
+#define SCSI_Out__4__SHIFT 5u\r
+#define SCSI_Out__4__SLW CYREG_PRT0_SLW\r
+#define SCSI_Out__5__AG CYREG_PRT0_AG\r
+#define SCSI_Out__5__AMUX CYREG_PRT0_AMUX\r
+#define SCSI_Out__5__BIE CYREG_PRT0_BIE\r
+#define SCSI_Out__5__BIT_MASK CYREG_PRT0_BIT_MASK\r
+#define SCSI_Out__5__BYP CYREG_PRT0_BYP\r
+#define SCSI_Out__5__CTL CYREG_PRT0_CTL\r
+#define SCSI_Out__5__DM0 CYREG_PRT0_DM0\r
+#define SCSI_Out__5__DM1 CYREG_PRT0_DM1\r
+#define SCSI_Out__5__DM2 CYREG_PRT0_DM2\r
+#define SCSI_Out__5__DR CYREG_PRT0_DR\r
+#define SCSI_Out__5__INP_DIS CYREG_PRT0_INP_DIS\r
+#define SCSI_Out__5__INTTYPE CYREG_PICU0_INTTYPE4\r
+#define SCSI_Out__5__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG\r
+#define SCSI_Out__5__LCD_EN CYREG_PRT0_LCD_EN\r
+#define SCSI_Out__5__MASK 0x10u\r
+#define SCSI_Out__5__PC CYREG_PRT0_PC4\r
+#define SCSI_Out__5__PORT 0u\r
+#define SCSI_Out__5__PRT CYREG_PRT0_PRT\r
+#define SCSI_Out__5__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL\r
+#define SCSI_Out__5__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN\r
+#define SCSI_Out__5__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0\r
+#define SCSI_Out__5__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1\r
+#define SCSI_Out__5__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0\r
+#define SCSI_Out__5__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1\r
+#define SCSI_Out__5__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT\r
+#define SCSI_Out__5__PS CYREG_PRT0_PS\r
+#define SCSI_Out__5__SHIFT 4u\r
+#define SCSI_Out__5__SLW CYREG_PRT0_SLW\r
+#define SCSI_Out__6__AG CYREG_PRT0_AG\r
+#define SCSI_Out__6__AMUX CYREG_PRT0_AMUX\r
+#define SCSI_Out__6__BIE CYREG_PRT0_BIE\r
+#define SCSI_Out__6__BIT_MASK CYREG_PRT0_BIT_MASK\r
+#define SCSI_Out__6__BYP CYREG_PRT0_BYP\r
+#define SCSI_Out__6__CTL CYREG_PRT0_CTL\r
+#define SCSI_Out__6__DM0 CYREG_PRT0_DM0\r
+#define SCSI_Out__6__DM1 CYREG_PRT0_DM1\r
+#define SCSI_Out__6__DM2 CYREG_PRT0_DM2\r
+#define SCSI_Out__6__DR CYREG_PRT0_DR\r
+#define SCSI_Out__6__INP_DIS CYREG_PRT0_INP_DIS\r
+#define SCSI_Out__6__INTTYPE CYREG_PICU0_INTTYPE3\r
+#define SCSI_Out__6__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG\r
+#define SCSI_Out__6__LCD_EN CYREG_PRT0_LCD_EN\r
+#define SCSI_Out__6__MASK 0x08u\r
+#define SCSI_Out__6__PC CYREG_PRT0_PC3\r
+#define SCSI_Out__6__PORT 0u\r
+#define SCSI_Out__6__PRT CYREG_PRT0_PRT\r
+#define SCSI_Out__6__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL\r
+#define SCSI_Out__6__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN\r
+#define SCSI_Out__6__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0\r
+#define SCSI_Out__6__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1\r
+#define SCSI_Out__6__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0\r
+#define SCSI_Out__6__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1\r
+#define SCSI_Out__6__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT\r
+#define SCSI_Out__6__PS CYREG_PRT0_PS\r
+#define SCSI_Out__6__SHIFT 3u\r
+#define SCSI_Out__6__SLW CYREG_PRT0_SLW\r
+#define SCSI_Out__7__AG CYREG_PRT0_AG\r
+#define SCSI_Out__7__AMUX CYREG_PRT0_AMUX\r
+#define SCSI_Out__7__BIE CYREG_PRT0_BIE\r
+#define SCSI_Out__7__BIT_MASK CYREG_PRT0_BIT_MASK\r
+#define SCSI_Out__7__BYP CYREG_PRT0_BYP\r
+#define SCSI_Out__7__CTL CYREG_PRT0_CTL\r
+#define SCSI_Out__7__DM0 CYREG_PRT0_DM0\r
+#define SCSI_Out__7__DM1 CYREG_PRT0_DM1\r
+#define SCSI_Out__7__DM2 CYREG_PRT0_DM2\r
+#define SCSI_Out__7__DR CYREG_PRT0_DR\r
+#define SCSI_Out__7__INP_DIS CYREG_PRT0_INP_DIS\r
+#define SCSI_Out__7__INTTYPE CYREG_PICU0_INTTYPE2\r
+#define SCSI_Out__7__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG\r
+#define SCSI_Out__7__LCD_EN CYREG_PRT0_LCD_EN\r
+#define SCSI_Out__7__MASK 0x04u\r
+#define SCSI_Out__7__PC CYREG_PRT0_PC2\r
+#define SCSI_Out__7__PORT 0u\r
+#define SCSI_Out__7__PRT CYREG_PRT0_PRT\r
+#define SCSI_Out__7__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL\r
+#define SCSI_Out__7__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN\r
+#define SCSI_Out__7__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0\r
+#define SCSI_Out__7__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1\r
+#define SCSI_Out__7__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0\r
+#define SCSI_Out__7__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1\r
+#define SCSI_Out__7__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT\r
+#define SCSI_Out__7__PS CYREG_PRT0_PS\r
+#define SCSI_Out__7__SHIFT 2u\r
+#define SCSI_Out__7__SLW CYREG_PRT0_SLW\r
+#define SCSI_Out__8__AG CYREG_PRT0_AG\r
+#define SCSI_Out__8__AMUX CYREG_PRT0_AMUX\r
+#define SCSI_Out__8__BIE CYREG_PRT0_BIE\r
+#define SCSI_Out__8__BIT_MASK CYREG_PRT0_BIT_MASK\r
+#define SCSI_Out__8__BYP CYREG_PRT0_BYP\r
+#define SCSI_Out__8__CTL CYREG_PRT0_CTL\r
+#define SCSI_Out__8__DM0 CYREG_PRT0_DM0\r
+#define SCSI_Out__8__DM1 CYREG_PRT0_DM1\r
+#define SCSI_Out__8__DM2 CYREG_PRT0_DM2\r
+#define SCSI_Out__8__DR CYREG_PRT0_DR\r
+#define SCSI_Out__8__INP_DIS CYREG_PRT0_INP_DIS\r
+#define SCSI_Out__8__INTTYPE CYREG_PICU0_INTTYPE1\r
+#define SCSI_Out__8__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG\r
+#define SCSI_Out__8__LCD_EN CYREG_PRT0_LCD_EN\r
+#define SCSI_Out__8__MASK 0x02u\r
+#define SCSI_Out__8__PC CYREG_PRT0_PC1\r
+#define SCSI_Out__8__PORT 0u\r
+#define SCSI_Out__8__PRT CYREG_PRT0_PRT\r
+#define SCSI_Out__8__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL\r
+#define SCSI_Out__8__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN\r
+#define SCSI_Out__8__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0\r
+#define SCSI_Out__8__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1\r
+#define SCSI_Out__8__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0\r
+#define SCSI_Out__8__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1\r
+#define SCSI_Out__8__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT\r
+#define SCSI_Out__8__PS CYREG_PRT0_PS\r
+#define SCSI_Out__8__SHIFT 1u\r
+#define SCSI_Out__8__SLW CYREG_PRT0_SLW\r
+#define SCSI_Out__9__AG CYREG_PRT0_AG\r
+#define SCSI_Out__9__AMUX CYREG_PRT0_AMUX\r
+#define SCSI_Out__9__BIE CYREG_PRT0_BIE\r
+#define SCSI_Out__9__BIT_MASK CYREG_PRT0_BIT_MASK\r
+#define SCSI_Out__9__BYP CYREG_PRT0_BYP\r
+#define SCSI_Out__9__CTL CYREG_PRT0_CTL\r
+#define SCSI_Out__9__DM0 CYREG_PRT0_DM0\r
+#define SCSI_Out__9__DM1 CYREG_PRT0_DM1\r
+#define SCSI_Out__9__DM2 CYREG_PRT0_DM2\r
+#define SCSI_Out__9__DR CYREG_PRT0_DR\r
+#define SCSI_Out__9__INP_DIS CYREG_PRT0_INP_DIS\r
+#define SCSI_Out__9__INTTYPE CYREG_PICU0_INTTYPE0\r
+#define SCSI_Out__9__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG\r
+#define SCSI_Out__9__LCD_EN CYREG_PRT0_LCD_EN\r
+#define SCSI_Out__9__MASK 0x01u\r
+#define SCSI_Out__9__PC CYREG_PRT0_PC0\r
+#define SCSI_Out__9__PORT 0u\r
+#define SCSI_Out__9__PRT CYREG_PRT0_PRT\r
+#define SCSI_Out__9__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL\r
+#define SCSI_Out__9__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN\r
+#define SCSI_Out__9__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0\r
+#define SCSI_Out__9__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1\r
+#define SCSI_Out__9__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0\r
+#define SCSI_Out__9__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1\r
+#define SCSI_Out__9__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT\r
+#define SCSI_Out__9__PS CYREG_PRT0_PS\r
+#define SCSI_Out__9__SHIFT 0u\r
+#define SCSI_Out__9__SLW CYREG_PRT0_SLW\r
+#define SCSI_Out__ACK__AG CYREG_PRT0_AG\r
+#define SCSI_Out__ACK__AMUX CYREG_PRT0_AMUX\r
+#define SCSI_Out__ACK__BIE CYREG_PRT0_BIE\r
+#define SCSI_Out__ACK__BIT_MASK CYREG_PRT0_BIT_MASK\r
+#define SCSI_Out__ACK__BYP CYREG_PRT0_BYP\r
+#define SCSI_Out__ACK__CTL CYREG_PRT0_CTL\r
+#define SCSI_Out__ACK__DM0 CYREG_PRT0_DM0\r
+#define SCSI_Out__ACK__DM1 CYREG_PRT0_DM1\r
+#define SCSI_Out__ACK__DM2 CYREG_PRT0_DM2\r
+#define SCSI_Out__ACK__DR CYREG_PRT0_DR\r
+#define SCSI_Out__ACK__INP_DIS CYREG_PRT0_INP_DIS\r
+#define SCSI_Out__ACK__INTTYPE CYREG_PICU0_INTTYPE6\r
+#define SCSI_Out__ACK__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG\r
+#define SCSI_Out__ACK__LCD_EN CYREG_PRT0_LCD_EN\r
+#define SCSI_Out__ACK__MASK 0x40u\r
+#define SCSI_Out__ACK__PC CYREG_PRT0_PC6\r
+#define SCSI_Out__ACK__PORT 0u\r
+#define SCSI_Out__ACK__PRT CYREG_PRT0_PRT\r
+#define SCSI_Out__ACK__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL\r
+#define SCSI_Out__ACK__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN\r
+#define SCSI_Out__ACK__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0\r
+#define SCSI_Out__ACK__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1\r
+#define SCSI_Out__ACK__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0\r
+#define SCSI_Out__ACK__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1\r
+#define SCSI_Out__ACK__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT\r
+#define SCSI_Out__ACK__PS CYREG_PRT0_PS\r
+#define SCSI_Out__ACK__SHIFT 6u\r
+#define SCSI_Out__ACK__SLW CYREG_PRT0_SLW\r
+#define SCSI_Out__ATN__AG CYREG_PRT4_AG\r
+#define SCSI_Out__ATN__AMUX CYREG_PRT4_AMUX\r
+#define SCSI_Out__ATN__BIE CYREG_PRT4_BIE\r
+#define SCSI_Out__ATN__BIT_MASK CYREG_PRT4_BIT_MASK\r
+#define SCSI_Out__ATN__BYP CYREG_PRT4_BYP\r
+#define SCSI_Out__ATN__CTL CYREG_PRT4_CTL\r
+#define SCSI_Out__ATN__DM0 CYREG_PRT4_DM0\r
+#define SCSI_Out__ATN__DM1 CYREG_PRT4_DM1\r
+#define SCSI_Out__ATN__DM2 CYREG_PRT4_DM2\r
+#define SCSI_Out__ATN__DR CYREG_PRT4_DR\r
+#define SCSI_Out__ATN__INP_DIS CYREG_PRT4_INP_DIS\r
+#define SCSI_Out__ATN__INTTYPE CYREG_PICU4_INTTYPE2\r
+#define SCSI_Out__ATN__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG\r
+#define SCSI_Out__ATN__LCD_EN CYREG_PRT4_LCD_EN\r
+#define SCSI_Out__ATN__MASK 0x04u\r
+#define SCSI_Out__ATN__PC CYREG_PRT4_PC2\r
+#define SCSI_Out__ATN__PORT 4u\r
+#define SCSI_Out__ATN__PRT CYREG_PRT4_PRT\r
+#define SCSI_Out__ATN__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL\r
+#define SCSI_Out__ATN__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN\r
+#define SCSI_Out__ATN__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0\r
+#define SCSI_Out__ATN__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1\r
+#define SCSI_Out__ATN__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0\r
+#define SCSI_Out__ATN__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1\r
+#define SCSI_Out__ATN__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT\r
+#define SCSI_Out__ATN__PS CYREG_PRT4_PS\r
+#define SCSI_Out__ATN__SHIFT 2u\r
+#define SCSI_Out__ATN__SLW CYREG_PRT4_SLW\r
+#define SCSI_Out__BSY__AG CYREG_PRT0_AG\r
+#define SCSI_Out__BSY__AMUX CYREG_PRT0_AMUX\r
+#define SCSI_Out__BSY__BIE CYREG_PRT0_BIE\r
+#define SCSI_Out__BSY__BIT_MASK CYREG_PRT0_BIT_MASK\r
+#define SCSI_Out__BSY__BYP CYREG_PRT0_BYP\r
+#define SCSI_Out__BSY__CTL CYREG_PRT0_CTL\r
+#define SCSI_Out__BSY__DM0 CYREG_PRT0_DM0\r
+#define SCSI_Out__BSY__DM1 CYREG_PRT0_DM1\r
+#define SCSI_Out__BSY__DM2 CYREG_PRT0_DM2\r
+#define SCSI_Out__BSY__DR CYREG_PRT0_DR\r
+#define SCSI_Out__BSY__INP_DIS CYREG_PRT0_INP_DIS\r
+#define SCSI_Out__BSY__INTTYPE CYREG_PICU0_INTTYPE7\r
+#define SCSI_Out__BSY__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG\r
+#define SCSI_Out__BSY__LCD_EN CYREG_PRT0_LCD_EN\r
+#define SCSI_Out__BSY__MASK 0x80u\r
+#define SCSI_Out__BSY__PC CYREG_PRT0_PC7\r
+#define SCSI_Out__BSY__PORT 0u\r
+#define SCSI_Out__BSY__PRT CYREG_PRT0_PRT\r
+#define SCSI_Out__BSY__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL\r
+#define SCSI_Out__BSY__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN\r
+#define SCSI_Out__BSY__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0\r
+#define SCSI_Out__BSY__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1\r
+#define SCSI_Out__BSY__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0\r
+#define SCSI_Out__BSY__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1\r
+#define SCSI_Out__BSY__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT\r
+#define SCSI_Out__BSY__PS CYREG_PRT0_PS\r
+#define SCSI_Out__BSY__SHIFT 7u\r
+#define SCSI_Out__BSY__SLW CYREG_PRT0_SLW\r
+#define SCSI_Out__CD_raw__AG CYREG_PRT0_AG\r
+#define SCSI_Out__CD_raw__AMUX CYREG_PRT0_AMUX\r
+#define SCSI_Out__CD_raw__BIE CYREG_PRT0_BIE\r
+#define SCSI_Out__CD_raw__BIT_MASK CYREG_PRT0_BIT_MASK\r
+#define SCSI_Out__CD_raw__BYP CYREG_PRT0_BYP\r
+#define SCSI_Out__CD_raw__CTL CYREG_PRT0_CTL\r
+#define SCSI_Out__CD_raw__DM0 CYREG_PRT0_DM0\r
+#define SCSI_Out__CD_raw__DM1 CYREG_PRT0_DM1\r
+#define SCSI_Out__CD_raw__DM2 CYREG_PRT0_DM2\r
+#define SCSI_Out__CD_raw__DR CYREG_PRT0_DR\r
+#define SCSI_Out__CD_raw__INP_DIS CYREG_PRT0_INP_DIS\r
+#define SCSI_Out__CD_raw__INTTYPE CYREG_PICU0_INTTYPE2\r
+#define SCSI_Out__CD_raw__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG\r
+#define SCSI_Out__CD_raw__LCD_EN CYREG_PRT0_LCD_EN\r
+#define SCSI_Out__CD_raw__MASK 0x04u\r
+#define SCSI_Out__CD_raw__PC CYREG_PRT0_PC2\r
+#define SCSI_Out__CD_raw__PORT 0u\r
+#define SCSI_Out__CD_raw__PRT CYREG_PRT0_PRT\r
+#define SCSI_Out__CD_raw__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL\r
+#define SCSI_Out__CD_raw__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN\r
+#define SCSI_Out__CD_raw__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0\r
+#define SCSI_Out__CD_raw__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1\r
+#define SCSI_Out__CD_raw__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0\r
+#define SCSI_Out__CD_raw__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1\r
+#define SCSI_Out__CD_raw__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT\r
+#define SCSI_Out__CD_raw__PS CYREG_PRT0_PS\r
+#define SCSI_Out__CD_raw__SHIFT 2u\r
+#define SCSI_Out__CD_raw__SLW CYREG_PRT0_SLW\r
+#define SCSI_Out__DBP_raw__AG CYREG_PRT4_AG\r
+#define SCSI_Out__DBP_raw__AMUX CYREG_PRT4_AMUX\r
+#define SCSI_Out__DBP_raw__BIE CYREG_PRT4_BIE\r
+#define SCSI_Out__DBP_raw__BIT_MASK CYREG_PRT4_BIT_MASK\r
+#define SCSI_Out__DBP_raw__BYP CYREG_PRT4_BYP\r
+#define SCSI_Out__DBP_raw__CTL CYREG_PRT4_CTL\r
+#define SCSI_Out__DBP_raw__DM0 CYREG_PRT4_DM0\r
+#define SCSI_Out__DBP_raw__DM1 CYREG_PRT4_DM1\r
+#define SCSI_Out__DBP_raw__DM2 CYREG_PRT4_DM2\r
+#define SCSI_Out__DBP_raw__DR CYREG_PRT4_DR\r
+#define SCSI_Out__DBP_raw__INP_DIS CYREG_PRT4_INP_DIS\r
+#define SCSI_Out__DBP_raw__INTTYPE CYREG_PICU4_INTTYPE3\r
+#define SCSI_Out__DBP_raw__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG\r
+#define SCSI_Out__DBP_raw__LCD_EN CYREG_PRT4_LCD_EN\r
+#define SCSI_Out__DBP_raw__MASK 0x08u\r
+#define SCSI_Out__DBP_raw__PC CYREG_PRT4_PC3\r
+#define SCSI_Out__DBP_raw__PORT 4u\r
+#define SCSI_Out__DBP_raw__PRT CYREG_PRT4_PRT\r
+#define SCSI_Out__DBP_raw__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL\r
+#define SCSI_Out__DBP_raw__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN\r
+#define SCSI_Out__DBP_raw__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0\r
+#define SCSI_Out__DBP_raw__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1\r
+#define SCSI_Out__DBP_raw__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0\r
+#define SCSI_Out__DBP_raw__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1\r
+#define SCSI_Out__DBP_raw__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT\r
+#define SCSI_Out__DBP_raw__PS CYREG_PRT4_PS\r
+#define SCSI_Out__DBP_raw__SHIFT 3u\r
+#define SCSI_Out__DBP_raw__SLW CYREG_PRT4_SLW\r
+#define SCSI_Out__IO_raw__AG CYREG_PRT0_AG\r
+#define SCSI_Out__IO_raw__AMUX CYREG_PRT0_AMUX\r
+#define SCSI_Out__IO_raw__BIE CYREG_PRT0_BIE\r
+#define SCSI_Out__IO_raw__BIT_MASK CYREG_PRT0_BIT_MASK\r
+#define SCSI_Out__IO_raw__BYP CYREG_PRT0_BYP\r
+#define SCSI_Out__IO_raw__CTL CYREG_PRT0_CTL\r
+#define SCSI_Out__IO_raw__DM0 CYREG_PRT0_DM0\r
+#define SCSI_Out__IO_raw__DM1 CYREG_PRT0_DM1\r
+#define SCSI_Out__IO_raw__DM2 CYREG_PRT0_DM2\r
+#define SCSI_Out__IO_raw__DR CYREG_PRT0_DR\r
+#define SCSI_Out__IO_raw__INP_DIS CYREG_PRT0_INP_DIS\r
+#define SCSI_Out__IO_raw__INTTYPE CYREG_PICU0_INTTYPE0\r
+#define SCSI_Out__IO_raw__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG\r
+#define SCSI_Out__IO_raw__LCD_EN CYREG_PRT0_LCD_EN\r
+#define SCSI_Out__IO_raw__MASK 0x01u\r
+#define SCSI_Out__IO_raw__PC CYREG_PRT0_PC0\r
+#define SCSI_Out__IO_raw__PORT 0u\r
+#define SCSI_Out__IO_raw__PRT CYREG_PRT0_PRT\r
+#define SCSI_Out__IO_raw__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL\r
+#define SCSI_Out__IO_raw__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN\r
+#define SCSI_Out__IO_raw__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0\r
+#define SCSI_Out__IO_raw__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1\r
+#define SCSI_Out__IO_raw__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0\r
+#define SCSI_Out__IO_raw__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1\r
+#define SCSI_Out__IO_raw__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT\r
+#define SCSI_Out__IO_raw__PS CYREG_PRT0_PS\r
+#define SCSI_Out__IO_raw__SHIFT 0u\r
+#define SCSI_Out__IO_raw__SLW CYREG_PRT0_SLW\r
+#define SCSI_Out__MSG_raw__AG CYREG_PRT0_AG\r
+#define SCSI_Out__MSG_raw__AMUX CYREG_PRT0_AMUX\r
+#define SCSI_Out__MSG_raw__BIE CYREG_PRT0_BIE\r
+#define SCSI_Out__MSG_raw__BIT_MASK CYREG_PRT0_BIT_MASK\r
+#define SCSI_Out__MSG_raw__BYP CYREG_PRT0_BYP\r
+#define SCSI_Out__MSG_raw__CTL CYREG_PRT0_CTL\r
+#define SCSI_Out__MSG_raw__DM0 CYREG_PRT0_DM0\r
+#define SCSI_Out__MSG_raw__DM1 CYREG_PRT0_DM1\r
+#define SCSI_Out__MSG_raw__DM2 CYREG_PRT0_DM2\r
+#define SCSI_Out__MSG_raw__DR CYREG_PRT0_DR\r
+#define SCSI_Out__MSG_raw__INP_DIS CYREG_PRT0_INP_DIS\r
+#define SCSI_Out__MSG_raw__INTTYPE CYREG_PICU0_INTTYPE4\r
+#define SCSI_Out__MSG_raw__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG\r
+#define SCSI_Out__MSG_raw__LCD_EN CYREG_PRT0_LCD_EN\r
+#define SCSI_Out__MSG_raw__MASK 0x10u\r
+#define SCSI_Out__MSG_raw__PC CYREG_PRT0_PC4\r
+#define SCSI_Out__MSG_raw__PORT 0u\r
+#define SCSI_Out__MSG_raw__PRT CYREG_PRT0_PRT\r
+#define SCSI_Out__MSG_raw__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL\r
+#define SCSI_Out__MSG_raw__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN\r
+#define SCSI_Out__MSG_raw__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0\r
+#define SCSI_Out__MSG_raw__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1\r
+#define SCSI_Out__MSG_raw__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0\r
+#define SCSI_Out__MSG_raw__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1\r
+#define SCSI_Out__MSG_raw__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT\r
+#define SCSI_Out__MSG_raw__PS CYREG_PRT0_PS\r
+#define SCSI_Out__MSG_raw__SHIFT 4u\r
+#define SCSI_Out__MSG_raw__SLW CYREG_PRT0_SLW\r
+#define SCSI_Out__REQ__AG CYREG_PRT0_AG\r
+#define SCSI_Out__REQ__AMUX CYREG_PRT0_AMUX\r
+#define SCSI_Out__REQ__BIE CYREG_PRT0_BIE\r
+#define SCSI_Out__REQ__BIT_MASK CYREG_PRT0_BIT_MASK\r
+#define SCSI_Out__REQ__BYP CYREG_PRT0_BYP\r
+#define SCSI_Out__REQ__CTL CYREG_PRT0_CTL\r
+#define SCSI_Out__REQ__DM0 CYREG_PRT0_DM0\r
+#define SCSI_Out__REQ__DM1 CYREG_PRT0_DM1\r
+#define SCSI_Out__REQ__DM2 CYREG_PRT0_DM2\r
+#define SCSI_Out__REQ__DR CYREG_PRT0_DR\r
+#define SCSI_Out__REQ__INP_DIS CYREG_PRT0_INP_DIS\r
+#define SCSI_Out__REQ__INTTYPE CYREG_PICU0_INTTYPE1\r
+#define SCSI_Out__REQ__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG\r
+#define SCSI_Out__REQ__LCD_EN CYREG_PRT0_LCD_EN\r
+#define SCSI_Out__REQ__MASK 0x02u\r
+#define SCSI_Out__REQ__PC CYREG_PRT0_PC1\r
+#define SCSI_Out__REQ__PORT 0u\r
+#define SCSI_Out__REQ__PRT CYREG_PRT0_PRT\r
+#define SCSI_Out__REQ__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL\r
+#define SCSI_Out__REQ__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN\r
+#define SCSI_Out__REQ__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0\r
+#define SCSI_Out__REQ__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1\r
+#define SCSI_Out__REQ__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0\r
+#define SCSI_Out__REQ__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1\r
+#define SCSI_Out__REQ__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT\r
+#define SCSI_Out__REQ__PS CYREG_PRT0_PS\r
+#define SCSI_Out__REQ__SHIFT 1u\r
+#define SCSI_Out__REQ__SLW CYREG_PRT0_SLW\r
+#define SCSI_Out__RST__AG CYREG_PRT0_AG\r
+#define SCSI_Out__RST__AMUX CYREG_PRT0_AMUX\r
+#define SCSI_Out__RST__BIE CYREG_PRT0_BIE\r
+#define SCSI_Out__RST__BIT_MASK CYREG_PRT0_BIT_MASK\r
+#define SCSI_Out__RST__BYP CYREG_PRT0_BYP\r
+#define SCSI_Out__RST__CTL CYREG_PRT0_CTL\r
+#define SCSI_Out__RST__DM0 CYREG_PRT0_DM0\r
+#define SCSI_Out__RST__DM1 CYREG_PRT0_DM1\r
+#define SCSI_Out__RST__DM2 CYREG_PRT0_DM2\r
+#define SCSI_Out__RST__DR CYREG_PRT0_DR\r
+#define SCSI_Out__RST__INP_DIS CYREG_PRT0_INP_DIS\r
+#define SCSI_Out__RST__INTTYPE CYREG_PICU0_INTTYPE5\r
+#define SCSI_Out__RST__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG\r
+#define SCSI_Out__RST__LCD_EN CYREG_PRT0_LCD_EN\r
+#define SCSI_Out__RST__MASK 0x20u\r
+#define SCSI_Out__RST__PC CYREG_PRT0_PC5\r
+#define SCSI_Out__RST__PORT 0u\r
+#define SCSI_Out__RST__PRT CYREG_PRT0_PRT\r
+#define SCSI_Out__RST__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL\r
+#define SCSI_Out__RST__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN\r
+#define SCSI_Out__RST__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0\r
+#define SCSI_Out__RST__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1\r
+#define SCSI_Out__RST__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0\r
+#define SCSI_Out__RST__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1\r
+#define SCSI_Out__RST__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT\r
+#define SCSI_Out__RST__PS CYREG_PRT0_PS\r
+#define SCSI_Out__RST__SHIFT 5u\r
+#define SCSI_Out__RST__SLW CYREG_PRT0_SLW\r
+#define SCSI_Out__SEL__AG CYREG_PRT0_AG\r
+#define SCSI_Out__SEL__AMUX CYREG_PRT0_AMUX\r
+#define SCSI_Out__SEL__BIE CYREG_PRT0_BIE\r
+#define SCSI_Out__SEL__BIT_MASK CYREG_PRT0_BIT_MASK\r
+#define SCSI_Out__SEL__BYP CYREG_PRT0_BYP\r
+#define SCSI_Out__SEL__CTL CYREG_PRT0_CTL\r
+#define SCSI_Out__SEL__DM0 CYREG_PRT0_DM0\r
+#define SCSI_Out__SEL__DM1 CYREG_PRT0_DM1\r
+#define SCSI_Out__SEL__DM2 CYREG_PRT0_DM2\r
+#define SCSI_Out__SEL__DR CYREG_PRT0_DR\r
+#define SCSI_Out__SEL__INP_DIS CYREG_PRT0_INP_DIS\r
+#define SCSI_Out__SEL__INTTYPE CYREG_PICU0_INTTYPE3\r
+#define SCSI_Out__SEL__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG\r
+#define SCSI_Out__SEL__LCD_EN CYREG_PRT0_LCD_EN\r
+#define SCSI_Out__SEL__MASK 0x08u\r
+#define SCSI_Out__SEL__PC CYREG_PRT0_PC3\r
+#define SCSI_Out__SEL__PORT 0u\r
+#define SCSI_Out__SEL__PRT CYREG_PRT0_PRT\r
+#define SCSI_Out__SEL__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL\r
+#define SCSI_Out__SEL__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN\r
+#define SCSI_Out__SEL__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0\r
+#define SCSI_Out__SEL__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1\r
+#define SCSI_Out__SEL__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0\r
+#define SCSI_Out__SEL__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1\r
+#define SCSI_Out__SEL__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT\r
+#define SCSI_Out__SEL__PS CYREG_PRT0_PS\r
+#define SCSI_Out__SEL__SHIFT 3u\r
+#define SCSI_Out__SEL__SLW CYREG_PRT0_SLW\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__0__MASK 0x01u\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__0__POS 0\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__1__MASK 0x02u\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__1__POS 1\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB08_09_ACTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB08_09_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB08_09_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB08_09_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B1_UDB08_09_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B1_UDB08_09_MSK\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B1_UDB08_09_MSK\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B1_UDB08_09_MSK\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB08_09_MSK\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__2__MASK 0x04u\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__2__POS 2\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__3__MASK 0x08u\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__3__POS 3\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__4__MASK 0x10u\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__4__POS 4\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__5__MASK 0x20u\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__5__POS 5\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__6__MASK 0x40u\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__6__POS 6\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__7__MASK 0x80u\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__7__POS 7\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B1_UDB08_ACTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG CYREG_B1_UDB08_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B1_UDB08_ST_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG CYREG_B1_UDB08_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG CYREG_B1_UDB08_ST_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__MASK 0xFFu\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB08_MSK_ACTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B1_UDB08_MSK_ACTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG CYREG_B1_UDB08_MSK\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK 0x01u\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__0__POS 0\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB08_09_ACTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB08_09_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB08_09_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB08_09_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB08_09_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB08_09_MSK\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB08_09_MSK\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB08_09_MSK\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB08_09_MSK\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB08_ACTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB08_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB08_ST_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB08_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB08_ST_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK 0x01u\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB08_MSK\r
+#define SCSI_Out_DBx__0__AG CYREG_PRT6_AG\r
+#define SCSI_Out_DBx__0__AMUX CYREG_PRT6_AMUX\r
+#define SCSI_Out_DBx__0__BIE CYREG_PRT6_BIE\r
+#define SCSI_Out_DBx__0__BIT_MASK CYREG_PRT6_BIT_MASK\r
+#define SCSI_Out_DBx__0__BYP CYREG_PRT6_BYP\r
+#define SCSI_Out_DBx__0__CTL CYREG_PRT6_CTL\r
+#define SCSI_Out_DBx__0__DM0 CYREG_PRT6_DM0\r
+#define SCSI_Out_DBx__0__DM1 CYREG_PRT6_DM1\r
+#define SCSI_Out_DBx__0__DM2 CYREG_PRT6_DM2\r
+#define SCSI_Out_DBx__0__DR CYREG_PRT6_DR\r
+#define SCSI_Out_DBx__0__INP_DIS CYREG_PRT6_INP_DIS\r
+#define SCSI_Out_DBx__0__INTTYPE CYREG_PICU6_INTTYPE3\r
+#define SCSI_Out_DBx__0__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
+#define SCSI_Out_DBx__0__LCD_EN CYREG_PRT6_LCD_EN\r
+#define SCSI_Out_DBx__0__MASK 0x08u\r
+#define SCSI_Out_DBx__0__PC CYREG_PRT6_PC3\r
+#define SCSI_Out_DBx__0__PORT 6u\r
+#define SCSI_Out_DBx__0__PRT CYREG_PRT6_PRT\r
+#define SCSI_Out_DBx__0__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
+#define SCSI_Out_DBx__0__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
+#define SCSI_Out_DBx__0__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
+#define SCSI_Out_DBx__0__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
+#define SCSI_Out_DBx__0__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
+#define SCSI_Out_DBx__0__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
+#define SCSI_Out_DBx__0__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
+#define SCSI_Out_DBx__0__PS CYREG_PRT6_PS\r
+#define SCSI_Out_DBx__0__SHIFT 3u\r
+#define SCSI_Out_DBx__0__SLW CYREG_PRT6_SLW\r
+#define SCSI_Out_DBx__1__AG CYREG_PRT6_AG\r
+#define SCSI_Out_DBx__1__AMUX CYREG_PRT6_AMUX\r
+#define SCSI_Out_DBx__1__BIE CYREG_PRT6_BIE\r
+#define SCSI_Out_DBx__1__BIT_MASK CYREG_PRT6_BIT_MASK\r
+#define SCSI_Out_DBx__1__BYP CYREG_PRT6_BYP\r
+#define SCSI_Out_DBx__1__CTL CYREG_PRT6_CTL\r
+#define SCSI_Out_DBx__1__DM0 CYREG_PRT6_DM0\r
+#define SCSI_Out_DBx__1__DM1 CYREG_PRT6_DM1\r
+#define SCSI_Out_DBx__1__DM2 CYREG_PRT6_DM2\r
+#define SCSI_Out_DBx__1__DR CYREG_PRT6_DR\r
+#define SCSI_Out_DBx__1__INP_DIS CYREG_PRT6_INP_DIS\r
+#define SCSI_Out_DBx__1__INTTYPE CYREG_PICU6_INTTYPE2\r
+#define SCSI_Out_DBx__1__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
+#define SCSI_Out_DBx__1__LCD_EN CYREG_PRT6_LCD_EN\r
+#define SCSI_Out_DBx__1__MASK 0x04u\r
+#define SCSI_Out_DBx__1__PC CYREG_PRT6_PC2\r
+#define SCSI_Out_DBx__1__PORT 6u\r
+#define SCSI_Out_DBx__1__PRT CYREG_PRT6_PRT\r
+#define SCSI_Out_DBx__1__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
+#define SCSI_Out_DBx__1__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
+#define SCSI_Out_DBx__1__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
+#define SCSI_Out_DBx__1__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
+#define SCSI_Out_DBx__1__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
+#define SCSI_Out_DBx__1__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
+#define SCSI_Out_DBx__1__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
+#define SCSI_Out_DBx__1__PS CYREG_PRT6_PS\r
+#define SCSI_Out_DBx__1__SHIFT 2u\r
+#define SCSI_Out_DBx__1__SLW CYREG_PRT6_SLW\r
+#define SCSI_Out_DBx__2__AG CYREG_PRT6_AG\r
+#define SCSI_Out_DBx__2__AMUX CYREG_PRT6_AMUX\r
+#define SCSI_Out_DBx__2__BIE CYREG_PRT6_BIE\r
+#define SCSI_Out_DBx__2__BIT_MASK CYREG_PRT6_BIT_MASK\r
+#define SCSI_Out_DBx__2__BYP CYREG_PRT6_BYP\r
+#define SCSI_Out_DBx__2__CTL CYREG_PRT6_CTL\r
+#define SCSI_Out_DBx__2__DM0 CYREG_PRT6_DM0\r
+#define SCSI_Out_DBx__2__DM1 CYREG_PRT6_DM1\r
+#define SCSI_Out_DBx__2__DM2 CYREG_PRT6_DM2\r
+#define SCSI_Out_DBx__2__DR CYREG_PRT6_DR\r
+#define SCSI_Out_DBx__2__INP_DIS CYREG_PRT6_INP_DIS\r
+#define SCSI_Out_DBx__2__INTTYPE CYREG_PICU6_INTTYPE1\r
+#define SCSI_Out_DBx__2__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
+#define SCSI_Out_DBx__2__LCD_EN CYREG_PRT6_LCD_EN\r
+#define SCSI_Out_DBx__2__MASK 0x02u\r
+#define SCSI_Out_DBx__2__PC CYREG_PRT6_PC1\r
+#define SCSI_Out_DBx__2__PORT 6u\r
+#define SCSI_Out_DBx__2__PRT CYREG_PRT6_PRT\r
+#define SCSI_Out_DBx__2__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
+#define SCSI_Out_DBx__2__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
+#define SCSI_Out_DBx__2__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
+#define SCSI_Out_DBx__2__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
+#define SCSI_Out_DBx__2__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
+#define SCSI_Out_DBx__2__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
+#define SCSI_Out_DBx__2__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
+#define SCSI_Out_DBx__2__PS CYREG_PRT6_PS\r
+#define SCSI_Out_DBx__2__SHIFT 1u\r
+#define SCSI_Out_DBx__2__SLW CYREG_PRT6_SLW\r
+#define SCSI_Out_DBx__3__AG CYREG_PRT6_AG\r
+#define SCSI_Out_DBx__3__AMUX CYREG_PRT6_AMUX\r
+#define SCSI_Out_DBx__3__BIE CYREG_PRT6_BIE\r
+#define SCSI_Out_DBx__3__BIT_MASK CYREG_PRT6_BIT_MASK\r
+#define SCSI_Out_DBx__3__BYP CYREG_PRT6_BYP\r
+#define SCSI_Out_DBx__3__CTL CYREG_PRT6_CTL\r
+#define SCSI_Out_DBx__3__DM0 CYREG_PRT6_DM0\r
+#define SCSI_Out_DBx__3__DM1 CYREG_PRT6_DM1\r
+#define SCSI_Out_DBx__3__DM2 CYREG_PRT6_DM2\r
+#define SCSI_Out_DBx__3__DR CYREG_PRT6_DR\r
+#define SCSI_Out_DBx__3__INP_DIS CYREG_PRT6_INP_DIS\r
+#define SCSI_Out_DBx__3__INTTYPE CYREG_PICU6_INTTYPE0\r
+#define SCSI_Out_DBx__3__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
+#define SCSI_Out_DBx__3__LCD_EN CYREG_PRT6_LCD_EN\r
+#define SCSI_Out_DBx__3__MASK 0x01u\r
+#define SCSI_Out_DBx__3__PC CYREG_PRT6_PC0\r
+#define SCSI_Out_DBx__3__PORT 6u\r
+#define SCSI_Out_DBx__3__PRT CYREG_PRT6_PRT\r
+#define SCSI_Out_DBx__3__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
+#define SCSI_Out_DBx__3__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
+#define SCSI_Out_DBx__3__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
+#define SCSI_Out_DBx__3__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
+#define SCSI_Out_DBx__3__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
+#define SCSI_Out_DBx__3__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
+#define SCSI_Out_DBx__3__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
+#define SCSI_Out_DBx__3__PS CYREG_PRT6_PS\r
+#define SCSI_Out_DBx__3__SHIFT 0u\r
+#define SCSI_Out_DBx__3__SLW CYREG_PRT6_SLW\r
+#define SCSI_Out_DBx__4__AG CYREG_PRT4_AG\r
+#define SCSI_Out_DBx__4__AMUX CYREG_PRT4_AMUX\r
+#define SCSI_Out_DBx__4__BIE CYREG_PRT4_BIE\r
+#define SCSI_Out_DBx__4__BIT_MASK CYREG_PRT4_BIT_MASK\r
+#define SCSI_Out_DBx__4__BYP CYREG_PRT4_BYP\r
+#define SCSI_Out_DBx__4__CTL CYREG_PRT4_CTL\r
+#define SCSI_Out_DBx__4__DM0 CYREG_PRT4_DM0\r
+#define SCSI_Out_DBx__4__DM1 CYREG_PRT4_DM1\r
+#define SCSI_Out_DBx__4__DM2 CYREG_PRT4_DM2\r
+#define SCSI_Out_DBx__4__DR CYREG_PRT4_DR\r
+#define SCSI_Out_DBx__4__INP_DIS CYREG_PRT4_INP_DIS\r
+#define SCSI_Out_DBx__4__INTTYPE CYREG_PICU4_INTTYPE7\r
+#define SCSI_Out_DBx__4__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG\r
+#define SCSI_Out_DBx__4__LCD_EN CYREG_PRT4_LCD_EN\r
+#define SCSI_Out_DBx__4__MASK 0x80u\r
+#define SCSI_Out_DBx__4__PC CYREG_PRT4_PC7\r
+#define SCSI_Out_DBx__4__PORT 4u\r
+#define SCSI_Out_DBx__4__PRT CYREG_PRT4_PRT\r
+#define SCSI_Out_DBx__4__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL\r
+#define SCSI_Out_DBx__4__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN\r
+#define SCSI_Out_DBx__4__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0\r
+#define SCSI_Out_DBx__4__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1\r
+#define SCSI_Out_DBx__4__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0\r
+#define SCSI_Out_DBx__4__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1\r
+#define SCSI_Out_DBx__4__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT\r
+#define SCSI_Out_DBx__4__PS CYREG_PRT4_PS\r
+#define SCSI_Out_DBx__4__SHIFT 7u\r
+#define SCSI_Out_DBx__4__SLW CYREG_PRT4_SLW\r
+#define SCSI_Out_DBx__5__AG CYREG_PRT4_AG\r
+#define SCSI_Out_DBx__5__AMUX CYREG_PRT4_AMUX\r
+#define SCSI_Out_DBx__5__BIE CYREG_PRT4_BIE\r
+#define SCSI_Out_DBx__5__BIT_MASK CYREG_PRT4_BIT_MASK\r
+#define SCSI_Out_DBx__5__BYP CYREG_PRT4_BYP\r
+#define SCSI_Out_DBx__5__CTL CYREG_PRT4_CTL\r
+#define SCSI_Out_DBx__5__DM0 CYREG_PRT4_DM0\r
+#define SCSI_Out_DBx__5__DM1 CYREG_PRT4_DM1\r
+#define SCSI_Out_DBx__5__DM2 CYREG_PRT4_DM2\r
+#define SCSI_Out_DBx__5__DR CYREG_PRT4_DR\r
+#define SCSI_Out_DBx__5__INP_DIS CYREG_PRT4_INP_DIS\r
+#define SCSI_Out_DBx__5__INTTYPE CYREG_PICU4_INTTYPE6\r
+#define SCSI_Out_DBx__5__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG\r
+#define SCSI_Out_DBx__5__LCD_EN CYREG_PRT4_LCD_EN\r
+#define SCSI_Out_DBx__5__MASK 0x40u\r
+#define SCSI_Out_DBx__5__PC CYREG_PRT4_PC6\r
+#define SCSI_Out_DBx__5__PORT 4u\r
+#define SCSI_Out_DBx__5__PRT CYREG_PRT4_PRT\r
+#define SCSI_Out_DBx__5__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL\r
+#define SCSI_Out_DBx__5__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN\r
+#define SCSI_Out_DBx__5__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0\r
+#define SCSI_Out_DBx__5__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1\r
+#define SCSI_Out_DBx__5__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0\r
+#define SCSI_Out_DBx__5__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1\r
+#define SCSI_Out_DBx__5__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT\r
+#define SCSI_Out_DBx__5__PS CYREG_PRT4_PS\r
+#define SCSI_Out_DBx__5__SHIFT 6u\r
+#define SCSI_Out_DBx__5__SLW CYREG_PRT4_SLW\r
+#define SCSI_Out_DBx__6__AG CYREG_PRT4_AG\r
+#define SCSI_Out_DBx__6__AMUX CYREG_PRT4_AMUX\r
+#define SCSI_Out_DBx__6__BIE CYREG_PRT4_BIE\r
+#define SCSI_Out_DBx__6__BIT_MASK CYREG_PRT4_BIT_MASK\r
+#define SCSI_Out_DBx__6__BYP CYREG_PRT4_BYP\r
+#define SCSI_Out_DBx__6__CTL CYREG_PRT4_CTL\r
+#define SCSI_Out_DBx__6__DM0 CYREG_PRT4_DM0\r
+#define SCSI_Out_DBx__6__DM1 CYREG_PRT4_DM1\r
+#define SCSI_Out_DBx__6__DM2 CYREG_PRT4_DM2\r
+#define SCSI_Out_DBx__6__DR CYREG_PRT4_DR\r
+#define SCSI_Out_DBx__6__INP_DIS CYREG_PRT4_INP_DIS\r
+#define SCSI_Out_DBx__6__INTTYPE CYREG_PICU4_INTTYPE5\r
+#define SCSI_Out_DBx__6__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG\r
+#define SCSI_Out_DBx__6__LCD_EN CYREG_PRT4_LCD_EN\r
+#define SCSI_Out_DBx__6__MASK 0x20u\r
+#define SCSI_Out_DBx__6__PC CYREG_PRT4_PC5\r
+#define SCSI_Out_DBx__6__PORT 4u\r
+#define SCSI_Out_DBx__6__PRT CYREG_PRT4_PRT\r
+#define SCSI_Out_DBx__6__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL\r
+#define SCSI_Out_DBx__6__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN\r
+#define SCSI_Out_DBx__6__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0\r
+#define SCSI_Out_DBx__6__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1\r
+#define SCSI_Out_DBx__6__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0\r
+#define SCSI_Out_DBx__6__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1\r
+#define SCSI_Out_DBx__6__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT\r
+#define SCSI_Out_DBx__6__PS CYREG_PRT4_PS\r
+#define SCSI_Out_DBx__6__SHIFT 5u\r
+#define SCSI_Out_DBx__6__SLW CYREG_PRT4_SLW\r
+#define SCSI_Out_DBx__7__AG CYREG_PRT4_AG\r
+#define SCSI_Out_DBx__7__AMUX CYREG_PRT4_AMUX\r
+#define SCSI_Out_DBx__7__BIE CYREG_PRT4_BIE\r
+#define SCSI_Out_DBx__7__BIT_MASK CYREG_PRT4_BIT_MASK\r
+#define SCSI_Out_DBx__7__BYP CYREG_PRT4_BYP\r
+#define SCSI_Out_DBx__7__CTL CYREG_PRT4_CTL\r
+#define SCSI_Out_DBx__7__DM0 CYREG_PRT4_DM0\r
+#define SCSI_Out_DBx__7__DM1 CYREG_PRT4_DM1\r
+#define SCSI_Out_DBx__7__DM2 CYREG_PRT4_DM2\r
+#define SCSI_Out_DBx__7__DR CYREG_PRT4_DR\r
+#define SCSI_Out_DBx__7__INP_DIS CYREG_PRT4_INP_DIS\r
+#define SCSI_Out_DBx__7__INTTYPE CYREG_PICU4_INTTYPE4\r
+#define SCSI_Out_DBx__7__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG\r
+#define SCSI_Out_DBx__7__LCD_EN CYREG_PRT4_LCD_EN\r
+#define SCSI_Out_DBx__7__MASK 0x10u\r
+#define SCSI_Out_DBx__7__PC CYREG_PRT4_PC4\r
+#define SCSI_Out_DBx__7__PORT 4u\r
+#define SCSI_Out_DBx__7__PRT CYREG_PRT4_PRT\r
+#define SCSI_Out_DBx__7__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL\r
+#define SCSI_Out_DBx__7__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN\r
+#define SCSI_Out_DBx__7__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0\r
+#define SCSI_Out_DBx__7__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1\r
+#define SCSI_Out_DBx__7__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0\r
+#define SCSI_Out_DBx__7__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1\r
+#define SCSI_Out_DBx__7__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT\r
+#define SCSI_Out_DBx__7__PS CYREG_PRT4_PS\r
+#define SCSI_Out_DBx__7__SHIFT 4u\r
+#define SCSI_Out_DBx__7__SLW CYREG_PRT4_SLW\r
+#define SCSI_Out_DBx__DB0__AG CYREG_PRT6_AG\r
+#define SCSI_Out_DBx__DB0__AMUX CYREG_PRT6_AMUX\r
+#define SCSI_Out_DBx__DB0__BIE CYREG_PRT6_BIE\r
+#define SCSI_Out_DBx__DB0__BIT_MASK CYREG_PRT6_BIT_MASK\r
+#define SCSI_Out_DBx__DB0__BYP CYREG_PRT6_BYP\r
+#define SCSI_Out_DBx__DB0__CTL CYREG_PRT6_CTL\r
+#define SCSI_Out_DBx__DB0__DM0 CYREG_PRT6_DM0\r
+#define SCSI_Out_DBx__DB0__DM1 CYREG_PRT6_DM1\r
+#define SCSI_Out_DBx__DB0__DM2 CYREG_PRT6_DM2\r
+#define SCSI_Out_DBx__DB0__DR CYREG_PRT6_DR\r
+#define SCSI_Out_DBx__DB0__INP_DIS CYREG_PRT6_INP_DIS\r
+#define SCSI_Out_DBx__DB0__INTTYPE CYREG_PICU6_INTTYPE3\r
+#define SCSI_Out_DBx__DB0__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
+#define SCSI_Out_DBx__DB0__LCD_EN CYREG_PRT6_LCD_EN\r
+#define SCSI_Out_DBx__DB0__MASK 0x08u\r
+#define SCSI_Out_DBx__DB0__PC CYREG_PRT6_PC3\r
+#define SCSI_Out_DBx__DB0__PORT 6u\r
+#define SCSI_Out_DBx__DB0__PRT CYREG_PRT6_PRT\r
+#define SCSI_Out_DBx__DB0__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
+#define SCSI_Out_DBx__DB0__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
+#define SCSI_Out_DBx__DB0__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
+#define SCSI_Out_DBx__DB0__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
+#define SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
+#define SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
+#define SCSI_Out_DBx__DB0__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
+#define SCSI_Out_DBx__DB0__PS CYREG_PRT6_PS\r
+#define SCSI_Out_DBx__DB0__SHIFT 3u\r
+#define SCSI_Out_DBx__DB0__SLW CYREG_PRT6_SLW\r
+#define SCSI_Out_DBx__DB1__AG CYREG_PRT6_AG\r
+#define SCSI_Out_DBx__DB1__AMUX CYREG_PRT6_AMUX\r
+#define SCSI_Out_DBx__DB1__BIE CYREG_PRT6_BIE\r
+#define SCSI_Out_DBx__DB1__BIT_MASK CYREG_PRT6_BIT_MASK\r
+#define SCSI_Out_DBx__DB1__BYP CYREG_PRT6_BYP\r
+#define SCSI_Out_DBx__DB1__CTL CYREG_PRT6_CTL\r
+#define SCSI_Out_DBx__DB1__DM0 CYREG_PRT6_DM0\r
+#define SCSI_Out_DBx__DB1__DM1 CYREG_PRT6_DM1\r
+#define SCSI_Out_DBx__DB1__DM2 CYREG_PRT6_DM2\r
+#define SCSI_Out_DBx__DB1__DR CYREG_PRT6_DR\r
+#define SCSI_Out_DBx__DB1__INP_DIS CYREG_PRT6_INP_DIS\r
+#define SCSI_Out_DBx__DB1__INTTYPE CYREG_PICU6_INTTYPE2\r
+#define SCSI_Out_DBx__DB1__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
+#define SCSI_Out_DBx__DB1__LCD_EN CYREG_PRT6_LCD_EN\r
+#define SCSI_Out_DBx__DB1__MASK 0x04u\r
+#define SCSI_Out_DBx__DB1__PC CYREG_PRT6_PC2\r
+#define SCSI_Out_DBx__DB1__PORT 6u\r
+#define SCSI_Out_DBx__DB1__PRT CYREG_PRT6_PRT\r
+#define SCSI_Out_DBx__DB1__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
+#define SCSI_Out_DBx__DB1__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
+#define SCSI_Out_DBx__DB1__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
+#define SCSI_Out_DBx__DB1__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
+#define SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
+#define SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
+#define SCSI_Out_DBx__DB1__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
+#define SCSI_Out_DBx__DB1__PS CYREG_PRT6_PS\r
+#define SCSI_Out_DBx__DB1__SHIFT 2u\r
+#define SCSI_Out_DBx__DB1__SLW CYREG_PRT6_SLW\r
+#define SCSI_Out_DBx__DB2__AG CYREG_PRT6_AG\r
+#define SCSI_Out_DBx__DB2__AMUX CYREG_PRT6_AMUX\r
+#define SCSI_Out_DBx__DB2__BIE CYREG_PRT6_BIE\r
+#define SCSI_Out_DBx__DB2__BIT_MASK CYREG_PRT6_BIT_MASK\r
+#define SCSI_Out_DBx__DB2__BYP CYREG_PRT6_BYP\r
+#define SCSI_Out_DBx__DB2__CTL CYREG_PRT6_CTL\r
+#define SCSI_Out_DBx__DB2__DM0 CYREG_PRT6_DM0\r
+#define SCSI_Out_DBx__DB2__DM1 CYREG_PRT6_DM1\r
+#define SCSI_Out_DBx__DB2__DM2 CYREG_PRT6_DM2\r
+#define SCSI_Out_DBx__DB2__DR CYREG_PRT6_DR\r
+#define SCSI_Out_DBx__DB2__INP_DIS CYREG_PRT6_INP_DIS\r
+#define SCSI_Out_DBx__DB2__INTTYPE CYREG_PICU6_INTTYPE1\r
+#define SCSI_Out_DBx__DB2__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
+#define SCSI_Out_DBx__DB2__LCD_EN CYREG_PRT6_LCD_EN\r
+#define SCSI_Out_DBx__DB2__MASK 0x02u\r
+#define SCSI_Out_DBx__DB2__PC CYREG_PRT6_PC1\r
+#define SCSI_Out_DBx__DB2__PORT 6u\r
+#define SCSI_Out_DBx__DB2__PRT CYREG_PRT6_PRT\r
+#define SCSI_Out_DBx__DB2__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
+#define SCSI_Out_DBx__DB2__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
+#define SCSI_Out_DBx__DB2__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
+#define SCSI_Out_DBx__DB2__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
+#define SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
+#define SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
+#define SCSI_Out_DBx__DB2__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
+#define SCSI_Out_DBx__DB2__PS CYREG_PRT6_PS\r
+#define SCSI_Out_DBx__DB2__SHIFT 1u\r
+#define SCSI_Out_DBx__DB2__SLW CYREG_PRT6_SLW\r
+#define SCSI_Out_DBx__DB3__AG CYREG_PRT6_AG\r
+#define SCSI_Out_DBx__DB3__AMUX CYREG_PRT6_AMUX\r
+#define SCSI_Out_DBx__DB3__BIE CYREG_PRT6_BIE\r
+#define SCSI_Out_DBx__DB3__BIT_MASK CYREG_PRT6_BIT_MASK\r
+#define SCSI_Out_DBx__DB3__BYP CYREG_PRT6_BYP\r
+#define SCSI_Out_DBx__DB3__CTL CYREG_PRT6_CTL\r
+#define SCSI_Out_DBx__DB3__DM0 CYREG_PRT6_DM0\r
+#define SCSI_Out_DBx__DB3__DM1 CYREG_PRT6_DM1\r
+#define SCSI_Out_DBx__DB3__DM2 CYREG_PRT6_DM2\r
+#define SCSI_Out_DBx__DB3__DR CYREG_PRT6_DR\r
+#define SCSI_Out_DBx__DB3__INP_DIS CYREG_PRT6_INP_DIS\r
+#define SCSI_Out_DBx__DB3__INTTYPE CYREG_PICU6_INTTYPE0\r
+#define SCSI_Out_DBx__DB3__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
+#define SCSI_Out_DBx__DB3__LCD_EN CYREG_PRT6_LCD_EN\r
+#define SCSI_Out_DBx__DB3__MASK 0x01u\r
+#define SCSI_Out_DBx__DB3__PC CYREG_PRT6_PC0\r
+#define SCSI_Out_DBx__DB3__PORT 6u\r
+#define SCSI_Out_DBx__DB3__PRT CYREG_PRT6_PRT\r
+#define SCSI_Out_DBx__DB3__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
+#define SCSI_Out_DBx__DB3__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
+#define SCSI_Out_DBx__DB3__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
+#define SCSI_Out_DBx__DB3__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
+#define SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
+#define SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
+#define SCSI_Out_DBx__DB3__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
+#define SCSI_Out_DBx__DB3__PS CYREG_PRT6_PS\r
+#define SCSI_Out_DBx__DB3__SHIFT 0u\r
+#define SCSI_Out_DBx__DB3__SLW CYREG_PRT6_SLW\r
+#define SCSI_Out_DBx__DB4__AG CYREG_PRT4_AG\r
+#define SCSI_Out_DBx__DB4__AMUX CYREG_PRT4_AMUX\r
+#define SCSI_Out_DBx__DB4__BIE CYREG_PRT4_BIE\r
+#define SCSI_Out_DBx__DB4__BIT_MASK CYREG_PRT4_BIT_MASK\r
+#define SCSI_Out_DBx__DB4__BYP CYREG_PRT4_BYP\r
+#define SCSI_Out_DBx__DB4__CTL CYREG_PRT4_CTL\r
+#define SCSI_Out_DBx__DB4__DM0 CYREG_PRT4_DM0\r
+#define SCSI_Out_DBx__DB4__DM1 CYREG_PRT4_DM1\r
+#define SCSI_Out_DBx__DB4__DM2 CYREG_PRT4_DM2\r
+#define SCSI_Out_DBx__DB4__DR CYREG_PRT4_DR\r
+#define SCSI_Out_DBx__DB4__INP_DIS CYREG_PRT4_INP_DIS\r
+#define SCSI_Out_DBx__DB4__INTTYPE CYREG_PICU4_INTTYPE7\r
+#define SCSI_Out_DBx__DB4__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG\r
+#define SCSI_Out_DBx__DB4__LCD_EN CYREG_PRT4_LCD_EN\r
+#define SCSI_Out_DBx__DB4__MASK 0x80u\r
+#define SCSI_Out_DBx__DB4__PC CYREG_PRT4_PC7\r
+#define SCSI_Out_DBx__DB4__PORT 4u\r
+#define SCSI_Out_DBx__DB4__PRT CYREG_PRT4_PRT\r
+#define SCSI_Out_DBx__DB4__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL\r
+#define SCSI_Out_DBx__DB4__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN\r
+#define SCSI_Out_DBx__DB4__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0\r
+#define SCSI_Out_DBx__DB4__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1\r
+#define SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0\r
+#define SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1\r
+#define SCSI_Out_DBx__DB4__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT\r
+#define SCSI_Out_DBx__DB4__PS CYREG_PRT4_PS\r
+#define SCSI_Out_DBx__DB4__SHIFT 7u\r
+#define SCSI_Out_DBx__DB4__SLW CYREG_PRT4_SLW\r
+#define SCSI_Out_DBx__DB5__AG CYREG_PRT4_AG\r
+#define SCSI_Out_DBx__DB5__AMUX CYREG_PRT4_AMUX\r
+#define SCSI_Out_DBx__DB5__BIE CYREG_PRT4_BIE\r
+#define SCSI_Out_DBx__DB5__BIT_MASK CYREG_PRT4_BIT_MASK\r
+#define SCSI_Out_DBx__DB5__BYP CYREG_PRT4_BYP\r
+#define SCSI_Out_DBx__DB5__CTL CYREG_PRT4_CTL\r
+#define SCSI_Out_DBx__DB5__DM0 CYREG_PRT4_DM0\r
+#define SCSI_Out_DBx__DB5__DM1 CYREG_PRT4_DM1\r
+#define SCSI_Out_DBx__DB5__DM2 CYREG_PRT4_DM2\r
+#define SCSI_Out_DBx__DB5__DR CYREG_PRT4_DR\r
+#define SCSI_Out_DBx__DB5__INP_DIS CYREG_PRT4_INP_DIS\r
+#define SCSI_Out_DBx__DB5__INTTYPE CYREG_PICU4_INTTYPE6\r
+#define SCSI_Out_DBx__DB5__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG\r
+#define SCSI_Out_DBx__DB5__LCD_EN CYREG_PRT4_LCD_EN\r
+#define SCSI_Out_DBx__DB5__MASK 0x40u\r
+#define SCSI_Out_DBx__DB5__PC CYREG_PRT4_PC6\r
+#define SCSI_Out_DBx__DB5__PORT 4u\r
+#define SCSI_Out_DBx__DB5__PRT CYREG_PRT4_PRT\r
+#define SCSI_Out_DBx__DB5__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL\r
+#define SCSI_Out_DBx__DB5__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN\r
+#define SCSI_Out_DBx__DB5__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0\r
+#define SCSI_Out_DBx__DB5__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1\r
+#define SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0\r
+#define SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1\r
+#define SCSI_Out_DBx__DB5__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT\r
+#define SCSI_Out_DBx__DB5__PS CYREG_PRT4_PS\r
+#define SCSI_Out_DBx__DB5__SHIFT 6u\r
+#define SCSI_Out_DBx__DB5__SLW CYREG_PRT4_SLW\r
+#define SCSI_Out_DBx__DB6__AG CYREG_PRT4_AG\r
+#define SCSI_Out_DBx__DB6__AMUX CYREG_PRT4_AMUX\r
+#define SCSI_Out_DBx__DB6__BIE CYREG_PRT4_BIE\r
+#define SCSI_Out_DBx__DB6__BIT_MASK CYREG_PRT4_BIT_MASK\r
+#define SCSI_Out_DBx__DB6__BYP CYREG_PRT4_BYP\r
+#define SCSI_Out_DBx__DB6__CTL CYREG_PRT4_CTL\r
+#define SCSI_Out_DBx__DB6__DM0 CYREG_PRT4_DM0\r
+#define SCSI_Out_DBx__DB6__DM1 CYREG_PRT4_DM1\r
+#define SCSI_Out_DBx__DB6__DM2 CYREG_PRT4_DM2\r
+#define SCSI_Out_DBx__DB6__DR CYREG_PRT4_DR\r
+#define SCSI_Out_DBx__DB6__INP_DIS CYREG_PRT4_INP_DIS\r
+#define SCSI_Out_DBx__DB6__INTTYPE CYREG_PICU4_INTTYPE5\r
+#define SCSI_Out_DBx__DB6__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG\r
+#define SCSI_Out_DBx__DB6__LCD_EN CYREG_PRT4_LCD_EN\r
+#define SCSI_Out_DBx__DB6__MASK 0x20u\r
+#define SCSI_Out_DBx__DB6__PC CYREG_PRT4_PC5\r
+#define SCSI_Out_DBx__DB6__PORT 4u\r
+#define SCSI_Out_DBx__DB6__PRT CYREG_PRT4_PRT\r
+#define SCSI_Out_DBx__DB6__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL\r
+#define SCSI_Out_DBx__DB6__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN\r
+#define SCSI_Out_DBx__DB6__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0\r
+#define SCSI_Out_DBx__DB6__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1\r
+#define SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0\r
+#define SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1\r
+#define SCSI_Out_DBx__DB6__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT\r
+#define SCSI_Out_DBx__DB6__PS CYREG_PRT4_PS\r
+#define SCSI_Out_DBx__DB6__SHIFT 5u\r
+#define SCSI_Out_DBx__DB6__SLW CYREG_PRT4_SLW\r
+#define SCSI_Out_DBx__DB7__AG CYREG_PRT4_AG\r
+#define SCSI_Out_DBx__DB7__AMUX CYREG_PRT4_AMUX\r
+#define SCSI_Out_DBx__DB7__BIE CYREG_PRT4_BIE\r
+#define SCSI_Out_DBx__DB7__BIT_MASK CYREG_PRT4_BIT_MASK\r
+#define SCSI_Out_DBx__DB7__BYP CYREG_PRT4_BYP\r
+#define SCSI_Out_DBx__DB7__CTL CYREG_PRT4_CTL\r
+#define SCSI_Out_DBx__DB7__DM0 CYREG_PRT4_DM0\r
+#define SCSI_Out_DBx__DB7__DM1 CYREG_PRT4_DM1\r
+#define SCSI_Out_DBx__DB7__DM2 CYREG_PRT4_DM2\r
+#define SCSI_Out_DBx__DB7__DR CYREG_PRT4_DR\r
+#define SCSI_Out_DBx__DB7__INP_DIS CYREG_PRT4_INP_DIS\r
+#define SCSI_Out_DBx__DB7__INTTYPE CYREG_PICU4_INTTYPE4\r
+#define SCSI_Out_DBx__DB7__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG\r
+#define SCSI_Out_DBx__DB7__LCD_EN CYREG_PRT4_LCD_EN\r
+#define SCSI_Out_DBx__DB7__MASK 0x10u\r
+#define SCSI_Out_DBx__DB7__PC CYREG_PRT4_PC4\r
+#define SCSI_Out_DBx__DB7__PORT 4u\r
+#define SCSI_Out_DBx__DB7__PRT CYREG_PRT4_PRT\r
+#define SCSI_Out_DBx__DB7__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL\r
+#define SCSI_Out_DBx__DB7__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN\r
+#define SCSI_Out_DBx__DB7__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0\r
+#define SCSI_Out_DBx__DB7__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1\r
+#define SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0\r
+#define SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1\r
+#define SCSI_Out_DBx__DB7__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT\r
+#define SCSI_Out_DBx__DB7__PS CYREG_PRT4_PS\r
+#define SCSI_Out_DBx__DB7__SHIFT 4u\r
+#define SCSI_Out_DBx__DB7__SLW CYREG_PRT4_SLW\r
+\r
+/* SCSI_Parity_Error */\r
+#define SCSI_Parity_Error_sts_sts_reg__0__MASK 0x01u\r
+#define SCSI_Parity_Error_sts_sts_reg__0__POS 0\r
+#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB01_02_ACTL\r
+#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB01_02_ST\r
+#define SCSI_Parity_Error_sts_sts_reg__MASK 0x01u\r
+#define SCSI_Parity_Error_sts_sts_reg__MASK_REG CYREG_B0_UDB01_MSK\r
+#define SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB01_ACTL\r
+#define SCSI_Parity_Error_sts_sts_reg__STATUS_REG CYREG_B0_UDB01_ST\r
+\r
+/* SCSI_RST_ISR */\r
+#define SCSI_RST_ISR__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
+#define SCSI_RST_ISR__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
+#define SCSI_RST_ISR__INTC_MASK 0x02u\r
+#define SCSI_RST_ISR__INTC_NUMBER 1u\r
+#define SCSI_RST_ISR__INTC_PRIOR_NUM 7u\r
+#define SCSI_RST_ISR__INTC_PRIOR_REG CYREG_NVIC_PRI_1\r
+#define SCSI_RST_ISR__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
+#define SCSI_RST_ISR__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
+\r
+/* SCSI_RX_DMA */\r
+#define SCSI_RX_DMA__DRQ_CTL CYREG_IDMUX_DRQ_CTL0\r
+#define SCSI_RX_DMA__DRQ_NUMBER 0u\r
+#define SCSI_RX_DMA__NUMBEROF_TDS 0u\r
+#define SCSI_RX_DMA__PRIORITY 2u\r
+#define SCSI_RX_DMA__TERMIN_EN 0u\r
+#define SCSI_RX_DMA__TERMIN_SEL 0u\r
+#define SCSI_RX_DMA__TERMOUT0_EN 1u\r
+#define SCSI_RX_DMA__TERMOUT0_SEL 0u\r
+#define SCSI_RX_DMA__TERMOUT1_EN 0u\r
+#define SCSI_RX_DMA__TERMOUT1_SEL 0u\r
+#define SCSI_RX_DMA_COMPLETE__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
+#define SCSI_RX_DMA_COMPLETE__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
+#define SCSI_RX_DMA_COMPLETE__INTC_MASK 0x04u\r
+#define SCSI_RX_DMA_COMPLETE__INTC_NUMBER 2u\r
+#define SCSI_RX_DMA_COMPLETE__INTC_PRIOR_NUM 7u\r
+#define SCSI_RX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_2\r
+#define SCSI_RX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
+#define SCSI_RX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
+\r
+/* SCSI_SEL_ISR */\r
+#define SCSI_SEL_ISR__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
+#define SCSI_SEL_ISR__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
+#define SCSI_SEL_ISR__INTC_MASK 0x08u\r
+#define SCSI_SEL_ISR__INTC_NUMBER 3u\r
+#define SCSI_SEL_ISR__INTC_PRIOR_NUM 7u\r
+#define SCSI_SEL_ISR__INTC_PRIOR_REG CYREG_NVIC_PRI_3\r
+#define SCSI_SEL_ISR__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
+#define SCSI_SEL_ISR__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
+\r
+/* SCSI_TX_DMA */\r
+#define SCSI_TX_DMA__DRQ_CTL CYREG_IDMUX_DRQ_CTL0\r
+#define SCSI_TX_DMA__DRQ_NUMBER 1u\r
+#define SCSI_TX_DMA__NUMBEROF_TDS 0u\r
+#define SCSI_TX_DMA__PRIORITY 2u\r
+#define SCSI_TX_DMA__TERMIN_EN 0u\r
+#define SCSI_TX_DMA__TERMIN_SEL 0u\r
+#define SCSI_TX_DMA__TERMOUT0_EN 1u\r
+#define SCSI_TX_DMA__TERMOUT0_SEL 1u\r
+#define SCSI_TX_DMA__TERMOUT1_EN 0u\r
+#define SCSI_TX_DMA__TERMOUT1_SEL 0u\r
+#define SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
+#define SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
+#define SCSI_TX_DMA_COMPLETE__INTC_MASK 0x10u\r
+#define SCSI_TX_DMA_COMPLETE__INTC_NUMBER 4u\r
+#define SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM 7u\r
+#define SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_4\r
+#define SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
+#define SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
+\r
+/* SDCard_BSPIM */\r
+#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB04_05_ACTL\r
+#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB04_05_CTL\r
+#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB04_05_CTL\r
+#define SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB04_05_CTL\r
+#define SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B1_UDB04_05_CTL\r
+#define SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B1_UDB04_05_MSK\r
+#define SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B1_UDB04_05_MSK\r
+#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B1_UDB04_05_MSK\r
+#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB04_05_MSK\r
+#define SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B1_UDB04_ACTL\r
+#define SDCard_BSPIM_BitCounter__CONTROL_REG CYREG_B1_UDB04_CTL\r
+#define SDCard_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B1_UDB04_ST_CTL\r
+#define SDCard_BSPIM_BitCounter__COUNT_REG CYREG_B1_UDB04_CTL\r
+#define SDCard_BSPIM_BitCounter__COUNT_ST_REG CYREG_B1_UDB04_ST_CTL\r
+#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL\r
+#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL\r
+#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B1_UDB04_MSK\r
+#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB04_05_ACTL\r
+#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B1_UDB04_05_ST\r
+#define SDCard_BSPIM_BitCounter_ST__MASK_REG CYREG_B1_UDB04_MSK\r
+#define SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL\r
+#define SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL\r
+#define SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B1_UDB04_ACTL\r
+#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B1_UDB04_ST_CTL\r
+#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B1_UDB04_ST_CTL\r
+#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B1_UDB04_ST\r
+#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB08_09_ACTL\r
+#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B1_UDB08_09_ST\r
+#define SDCard_BSPIM_RxStsReg__4__MASK 0x10u\r
+#define SDCard_BSPIM_RxStsReg__4__POS 4\r
+#define SDCard_BSPIM_RxStsReg__5__MASK 0x20u\r
+#define SDCard_BSPIM_RxStsReg__5__POS 5\r
+#define SDCard_BSPIM_RxStsReg__6__MASK 0x40u\r
+#define SDCard_BSPIM_RxStsReg__6__POS 6\r
+#define SDCard_BSPIM_RxStsReg__MASK 0x70u\r
+#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B1_UDB08_MSK\r
+#define SDCard_BSPIM_RxStsReg__MASK_ST_AUX_CTL_REG CYREG_B1_UDB08_MSK_ACTL\r
+#define SDCard_BSPIM_RxStsReg__PER_ST_AUX_CTL_REG CYREG_B1_UDB08_MSK_ACTL\r
+#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB08_ACTL\r
+#define SDCard_BSPIM_RxStsReg__STATUS_CNT_REG CYREG_B1_UDB08_ST_CTL\r
+#define SDCard_BSPIM_RxStsReg__STATUS_CONTROL_REG CYREG_B1_UDB08_ST_CTL\r
+#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B1_UDB08_ST\r
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B1_UDB04_05_A0\r
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B1_UDB04_05_A1\r
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG CYREG_B1_UDB04_05_D0\r
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG CYREG_B1_UDB04_05_D1\r
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG CYREG_B1_UDB04_05_ACTL\r
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG CYREG_B1_UDB04_05_F0\r
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG CYREG_B1_UDB04_05_F1\r
+#define SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG CYREG_B1_UDB04_A0_A1\r
+#define SDCard_BSPIM_sR8_Dp_u0__A0_REG CYREG_B1_UDB04_A0\r
+#define SDCard_BSPIM_sR8_Dp_u0__A1_REG CYREG_B1_UDB04_A1\r
+#define SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG CYREG_B1_UDB04_D0_D1\r
+#define SDCard_BSPIM_sR8_Dp_u0__D0_REG CYREG_B1_UDB04_D0\r
+#define SDCard_BSPIM_sR8_Dp_u0__D1_REG CYREG_B1_UDB04_D1\r
+#define SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG CYREG_B1_UDB04_ACTL\r
+#define SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG CYREG_B1_UDB04_F0_F1\r
+#define SDCard_BSPIM_sR8_Dp_u0__F0_REG CYREG_B1_UDB04_F0\r
+#define SDCard_BSPIM_sR8_Dp_u0__F1_REG CYREG_B1_UDB04_F1\r
+#define SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL\r
+#define SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL\r
+#define SDCard_BSPIM_TxStsReg__0__MASK 0x01u\r
+#define SDCard_BSPIM_TxStsReg__0__POS 0\r
+#define SDCard_BSPIM_TxStsReg__1__MASK 0x02u\r
+#define SDCard_BSPIM_TxStsReg__1__POS 1\r
+#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB07_08_ACTL\r
+#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B1_UDB07_08_ST\r
+#define SDCard_BSPIM_TxStsReg__2__MASK 0x04u\r
+#define SDCard_BSPIM_TxStsReg__2__POS 2\r
+#define SDCard_BSPIM_TxStsReg__3__MASK 0x08u\r
+#define SDCard_BSPIM_TxStsReg__3__POS 3\r
+#define SDCard_BSPIM_TxStsReg__4__MASK 0x10u\r
+#define SDCard_BSPIM_TxStsReg__4__POS 4\r
+#define SDCard_BSPIM_TxStsReg__MASK 0x1Fu\r
+#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B1_UDB07_MSK\r
+#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB07_ACTL\r
+#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B1_UDB07_ST\r
+\r
+/* SD_CD */\r
+#define SD_CD__0__INTTYPE CYREG_PICU3_INTTYPE6\r
+#define SD_CD__0__MASK 0x40u\r
+#define SD_CD__0__PC CYREG_PRT3_PC6\r
+#define SD_CD__0__PORT 3u\r
+#define SD_CD__0__SHIFT 6u\r
+#define SD_CD__AG CYREG_PRT3_AG\r
+#define SD_CD__AMUX CYREG_PRT3_AMUX\r
+#define SD_CD__BIE CYREG_PRT3_BIE\r
+#define SD_CD__BIT_MASK CYREG_PRT3_BIT_MASK\r
+#define SD_CD__BYP CYREG_PRT3_BYP\r
+#define SD_CD__CTL CYREG_PRT3_CTL\r
+#define SD_CD__DM0 CYREG_PRT3_DM0\r
+#define SD_CD__DM1 CYREG_PRT3_DM1\r
+#define SD_CD__DM2 CYREG_PRT3_DM2\r
+#define SD_CD__DR CYREG_PRT3_DR\r
+#define SD_CD__INP_DIS CYREG_PRT3_INP_DIS\r
+#define SD_CD__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU3_BASE\r
+#define SD_CD__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG\r
+#define SD_CD__LCD_EN CYREG_PRT3_LCD_EN\r
+#define SD_CD__MASK 0x40u\r
+#define SD_CD__PORT 3u\r
+#define SD_CD__PRT CYREG_PRT3_PRT\r
+#define SD_CD__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL\r
+#define SD_CD__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN\r
+#define SD_CD__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0\r
+#define SD_CD__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1\r
+#define SD_CD__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0\r
+#define SD_CD__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1\r
+#define SD_CD__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT\r
+#define SD_CD__PS CYREG_PRT3_PS\r
+#define SD_CD__SHIFT 6u\r
+#define SD_CD__SLW CYREG_PRT3_SLW\r
+\r
+/* SD_CS */\r
+#define SD_CS__0__INTTYPE CYREG_PICU3_INTTYPE4\r
+#define SD_CS__0__MASK 0x10u\r
+#define SD_CS__0__PC CYREG_PRT3_PC4\r
+#define SD_CS__0__PORT 3u\r
+#define SD_CS__0__SHIFT 4u\r
+#define SD_CS__AG CYREG_PRT3_AG\r
+#define SD_CS__AMUX CYREG_PRT3_AMUX\r
+#define SD_CS__BIE CYREG_PRT3_BIE\r
+#define SD_CS__BIT_MASK CYREG_PRT3_BIT_MASK\r
+#define SD_CS__BYP CYREG_PRT3_BYP\r
+#define SD_CS__CTL CYREG_PRT3_CTL\r
+#define SD_CS__DM0 CYREG_PRT3_DM0\r
+#define SD_CS__DM1 CYREG_PRT3_DM1\r
+#define SD_CS__DM2 CYREG_PRT3_DM2\r
+#define SD_CS__DR CYREG_PRT3_DR\r
+#define SD_CS__INP_DIS CYREG_PRT3_INP_DIS\r
+#define SD_CS__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU3_BASE\r
+#define SD_CS__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG\r
+#define SD_CS__LCD_EN CYREG_PRT3_LCD_EN\r
+#define SD_CS__MASK 0x10u\r
+#define SD_CS__PORT 3u\r
+#define SD_CS__PRT CYREG_PRT3_PRT\r
+#define SD_CS__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL\r
+#define SD_CS__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN\r
+#define SD_CS__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0\r
+#define SD_CS__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1\r
+#define SD_CS__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0\r
+#define SD_CS__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1\r
+#define SD_CS__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT\r
+#define SD_CS__PS CYREG_PRT3_PS\r
+#define SD_CS__SHIFT 4u\r
+#define SD_CS__SLW CYREG_PRT3_SLW\r
+\r
+/* SD_DAT1 */\r
+#define SD_DAT1__0__INTTYPE CYREG_PICU3_INTTYPE0\r
+#define SD_DAT1__0__MASK 0x01u\r
+#define SD_DAT1__0__PC CYREG_PRT3_PC0\r
+#define SD_DAT1__0__PORT 3u\r
+#define SD_DAT1__0__SHIFT 0u\r
+#define SD_DAT1__AG CYREG_PRT3_AG\r
+#define SD_DAT1__AMUX CYREG_PRT3_AMUX\r
+#define SD_DAT1__BIE CYREG_PRT3_BIE\r
+#define SD_DAT1__BIT_MASK CYREG_PRT3_BIT_MASK\r
+#define SD_DAT1__BYP CYREG_PRT3_BYP\r
+#define SD_DAT1__CTL CYREG_PRT3_CTL\r
+#define SD_DAT1__DM0 CYREG_PRT3_DM0\r
+#define SD_DAT1__DM1 CYREG_PRT3_DM1\r
+#define SD_DAT1__DM2 CYREG_PRT3_DM2\r
+#define SD_DAT1__DR CYREG_PRT3_DR\r
+#define SD_DAT1__INP_DIS CYREG_PRT3_INP_DIS\r
+#define SD_DAT1__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU3_BASE\r
+#define SD_DAT1__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG\r
+#define SD_DAT1__LCD_EN CYREG_PRT3_LCD_EN\r
+#define SD_DAT1__MASK 0x01u\r
+#define SD_DAT1__PORT 3u\r
+#define SD_DAT1__PRT CYREG_PRT3_PRT\r
+#define SD_DAT1__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL\r
+#define SD_DAT1__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN\r
+#define SD_DAT1__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0\r
+#define SD_DAT1__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1\r
+#define SD_DAT1__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0\r
+#define SD_DAT1__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1\r
+#define SD_DAT1__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT\r
+#define SD_DAT1__PS CYREG_PRT3_PS\r
+#define SD_DAT1__SHIFT 0u\r
+#define SD_DAT1__SLW CYREG_PRT3_SLW\r
+\r
+/* SD_DAT2 */\r
+#define SD_DAT2__0__INTTYPE CYREG_PICU3_INTTYPE5\r
+#define SD_DAT2__0__MASK 0x20u\r
+#define SD_DAT2__0__PC CYREG_PRT3_PC5\r
+#define SD_DAT2__0__PORT 3u\r
+#define SD_DAT2__0__SHIFT 5u\r
+#define SD_DAT2__AG CYREG_PRT3_AG\r
+#define SD_DAT2__AMUX CYREG_PRT3_AMUX\r
+#define SD_DAT2__BIE CYREG_PRT3_BIE\r
+#define SD_DAT2__BIT_MASK CYREG_PRT3_BIT_MASK\r
+#define SD_DAT2__BYP CYREG_PRT3_BYP\r
+#define SD_DAT2__CTL CYREG_PRT3_CTL\r
+#define SD_DAT2__DM0 CYREG_PRT3_DM0\r
+#define SD_DAT2__DM1 CYREG_PRT3_DM1\r
+#define SD_DAT2__DM2 CYREG_PRT3_DM2\r
+#define SD_DAT2__DR CYREG_PRT3_DR\r
+#define SD_DAT2__INP_DIS CYREG_PRT3_INP_DIS\r
+#define SD_DAT2__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU3_BASE\r
+#define SD_DAT2__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG\r
+#define SD_DAT2__LCD_EN CYREG_PRT3_LCD_EN\r
+#define SD_DAT2__MASK 0x20u\r
+#define SD_DAT2__PORT 3u\r
+#define SD_DAT2__PRT CYREG_PRT3_PRT\r
+#define SD_DAT2__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL\r
+#define SD_DAT2__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN\r
+#define SD_DAT2__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0\r
+#define SD_DAT2__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1\r
+#define SD_DAT2__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0\r
+#define SD_DAT2__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1\r
+#define SD_DAT2__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT\r
+#define SD_DAT2__PS CYREG_PRT3_PS\r
+#define SD_DAT2__SHIFT 5u\r
+#define SD_DAT2__SLW CYREG_PRT3_SLW\r
+\r
+/* SD_Data_Clk */\r
+#define SD_Data_Clk__CFG0 CYREG_CLKDIST_DCFG0_CFG0\r
+#define SD_Data_Clk__CFG1 CYREG_CLKDIST_DCFG0_CFG1\r
+#define SD_Data_Clk__CFG2 CYREG_CLKDIST_DCFG0_CFG2\r
+#define SD_Data_Clk__CFG2_SRC_SEL_MASK 0x07u\r
+#define SD_Data_Clk__INDEX 0x00u\r
+#define SD_Data_Clk__PM_ACT_CFG CYREG_PM_ACT_CFG2\r
+#define SD_Data_Clk__PM_ACT_MSK 0x01u\r
+#define SD_Data_Clk__PM_STBY_CFG CYREG_PM_STBY_CFG2\r
+#define SD_Data_Clk__PM_STBY_MSK 0x01u\r
+\r
+/* SD_MISO */\r
+#define SD_MISO__0__INTTYPE CYREG_PICU3_INTTYPE1\r
+#define SD_MISO__0__MASK 0x02u\r
+#define SD_MISO__0__PC CYREG_PRT3_PC1\r
+#define SD_MISO__0__PORT 3u\r
+#define SD_MISO__0__SHIFT 1u\r
+#define SD_MISO__AG CYREG_PRT3_AG\r
+#define SD_MISO__AMUX CYREG_PRT3_AMUX\r
+#define SD_MISO__BIE CYREG_PRT3_BIE\r
+#define SD_MISO__BIT_MASK CYREG_PRT3_BIT_MASK\r
+#define SD_MISO__BYP CYREG_PRT3_BYP\r
+#define SD_MISO__CTL CYREG_PRT3_CTL\r
+#define SD_MISO__DM0 CYREG_PRT3_DM0\r
+#define SD_MISO__DM1 CYREG_PRT3_DM1\r
+#define SD_MISO__DM2 CYREG_PRT3_DM2\r
+#define SD_MISO__DR CYREG_PRT3_DR\r
+#define SD_MISO__INP_DIS CYREG_PRT3_INP_DIS\r
+#define SD_MISO__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU3_BASE\r
+#define SD_MISO__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG\r
+#define SD_MISO__LCD_EN CYREG_PRT3_LCD_EN\r
+#define SD_MISO__MASK 0x02u\r
+#define SD_MISO__PORT 3u\r
+#define SD_MISO__PRT CYREG_PRT3_PRT\r
+#define SD_MISO__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL\r
+#define SD_MISO__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN\r
+#define SD_MISO__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0\r
+#define SD_MISO__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1\r
+#define SD_MISO__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0\r
+#define SD_MISO__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1\r
+#define SD_MISO__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT\r
+#define SD_MISO__PS CYREG_PRT3_PS\r
+#define SD_MISO__SHIFT 1u\r
+#define SD_MISO__SLW CYREG_PRT3_SLW\r
+\r
+/* SD_MOSI */\r
+#define SD_MOSI__0__INTTYPE CYREG_PICU3_INTTYPE3\r
+#define SD_MOSI__0__MASK 0x08u\r
+#define SD_MOSI__0__PC CYREG_PRT3_PC3\r
+#define SD_MOSI__0__PORT 3u\r
+#define SD_MOSI__0__SHIFT 3u\r
+#define SD_MOSI__AG CYREG_PRT3_AG\r
+#define SD_MOSI__AMUX CYREG_PRT3_AMUX\r
+#define SD_MOSI__BIE CYREG_PRT3_BIE\r
+#define SD_MOSI__BIT_MASK CYREG_PRT3_BIT_MASK\r
+#define SD_MOSI__BYP CYREG_PRT3_BYP\r
+#define SD_MOSI__CTL CYREG_PRT3_CTL\r
+#define SD_MOSI__DM0 CYREG_PRT3_DM0\r
+#define SD_MOSI__DM1 CYREG_PRT3_DM1\r
+#define SD_MOSI__DM2 CYREG_PRT3_DM2\r
+#define SD_MOSI__DR CYREG_PRT3_DR\r
+#define SD_MOSI__INP_DIS CYREG_PRT3_INP_DIS\r
+#define SD_MOSI__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU3_BASE\r
+#define SD_MOSI__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG\r
+#define SD_MOSI__LCD_EN CYREG_PRT3_LCD_EN\r
+#define SD_MOSI__MASK 0x08u\r
+#define SD_MOSI__PORT 3u\r
+#define SD_MOSI__PRT CYREG_PRT3_PRT\r
+#define SD_MOSI__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL\r
+#define SD_MOSI__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN\r
+#define SD_MOSI__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0\r
+#define SD_MOSI__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1\r
+#define SD_MOSI__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0\r
+#define SD_MOSI__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1\r
+#define SD_MOSI__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT\r
+#define SD_MOSI__PS CYREG_PRT3_PS\r
+#define SD_MOSI__SHIFT 3u\r
+#define SD_MOSI__SLW CYREG_PRT3_SLW\r
+\r
+/* SD_RX_DMA */\r
+#define SD_RX_DMA__DRQ_CTL CYREG_IDMUX_DRQ_CTL0\r
+#define SD_RX_DMA__DRQ_NUMBER 2u\r
+#define SD_RX_DMA__NUMBEROF_TDS 0u\r
+#define SD_RX_DMA__PRIORITY 0u\r
+#define SD_RX_DMA__TERMIN_EN 0u\r
+#define SD_RX_DMA__TERMIN_SEL 0u\r
+#define SD_RX_DMA__TERMOUT0_EN 1u\r
+#define SD_RX_DMA__TERMOUT0_SEL 2u\r
+#define SD_RX_DMA__TERMOUT1_EN 0u\r
+#define SD_RX_DMA__TERMOUT1_SEL 0u\r
+#define SD_RX_DMA_COMPLETE__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
+#define SD_RX_DMA_COMPLETE__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
+#define SD_RX_DMA_COMPLETE__INTC_MASK 0x20u\r
+#define SD_RX_DMA_COMPLETE__INTC_NUMBER 5u\r
+#define SD_RX_DMA_COMPLETE__INTC_PRIOR_NUM 7u\r
+#define SD_RX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_5\r
+#define SD_RX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
+#define SD_RX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
+\r
+/* SD_SCK */\r
+#define SD_SCK__0__INTTYPE CYREG_PICU3_INTTYPE2\r
+#define SD_SCK__0__MASK 0x04u\r
+#define SD_SCK__0__PC CYREG_PRT3_PC2\r
+#define SD_SCK__0__PORT 3u\r
+#define SD_SCK__0__SHIFT 2u\r
+#define SD_SCK__AG CYREG_PRT3_AG\r
+#define SD_SCK__AMUX CYREG_PRT3_AMUX\r
+#define SD_SCK__BIE CYREG_PRT3_BIE\r
+#define SD_SCK__BIT_MASK CYREG_PRT3_BIT_MASK\r
+#define SD_SCK__BYP CYREG_PRT3_BYP\r
+#define SD_SCK__CTL CYREG_PRT3_CTL\r
+#define SD_SCK__DM0 CYREG_PRT3_DM0\r
+#define SD_SCK__DM1 CYREG_PRT3_DM1\r
+#define SD_SCK__DM2 CYREG_PRT3_DM2\r
+#define SD_SCK__DR CYREG_PRT3_DR\r
+#define SD_SCK__INP_DIS CYREG_PRT3_INP_DIS\r
+#define SD_SCK__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU3_BASE\r
+#define SD_SCK__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG\r
+#define SD_SCK__LCD_EN CYREG_PRT3_LCD_EN\r
+#define SD_SCK__MASK 0x04u\r
+#define SD_SCK__PORT 3u\r
+#define SD_SCK__PRT CYREG_PRT3_PRT\r
+#define SD_SCK__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL\r
+#define SD_SCK__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN\r
+#define SD_SCK__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0\r
+#define SD_SCK__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1\r
+#define SD_SCK__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0\r
+#define SD_SCK__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1\r
+#define SD_SCK__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT\r
+#define SD_SCK__PS CYREG_PRT3_PS\r
+#define SD_SCK__SHIFT 2u\r
+#define SD_SCK__SLW CYREG_PRT3_SLW\r
+\r
+/* SD_TX_DMA */\r
+#define SD_TX_DMA__DRQ_CTL CYREG_IDMUX_DRQ_CTL0\r
+#define SD_TX_DMA__DRQ_NUMBER 3u\r
+#define SD_TX_DMA__NUMBEROF_TDS 0u\r
+#define SD_TX_DMA__PRIORITY 1u\r
+#define SD_TX_DMA__TERMIN_EN 0u\r
+#define SD_TX_DMA__TERMIN_SEL 0u\r
+#define SD_TX_DMA__TERMOUT0_EN 1u\r
+#define SD_TX_DMA__TERMOUT0_SEL 3u\r
+#define SD_TX_DMA__TERMOUT1_EN 0u\r
+#define SD_TX_DMA__TERMOUT1_SEL 0u\r
+#define SD_TX_DMA_COMPLETE__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
+#define SD_TX_DMA_COMPLETE__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
+#define SD_TX_DMA_COMPLETE__INTC_MASK 0x40u\r
+#define SD_TX_DMA_COMPLETE__INTC_NUMBER 6u\r
+#define SD_TX_DMA_COMPLETE__INTC_PRIOR_NUM 7u\r
+#define SD_TX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_6\r
+#define SD_TX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
+#define SD_TX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
+\r
+/* USBFS */\r
+#define USBFS_arb_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
+#define USBFS_arb_int__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
+#define USBFS_arb_int__INTC_MASK 0x400000u\r
+#define USBFS_arb_int__INTC_NUMBER 22u\r
+#define USBFS_arb_int__INTC_PRIOR_NUM 6u\r
+#define USBFS_arb_int__INTC_PRIOR_REG CYREG_NVIC_PRI_22\r
+#define USBFS_arb_int__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
+#define USBFS_arb_int__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
+#define USBFS_bus_reset__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
+#define USBFS_bus_reset__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
+#define USBFS_bus_reset__INTC_MASK 0x800000u\r
+#define USBFS_bus_reset__INTC_NUMBER 23u\r
+#define USBFS_bus_reset__INTC_PRIOR_NUM 7u\r
+#define USBFS_bus_reset__INTC_PRIOR_REG CYREG_NVIC_PRI_23\r
+#define USBFS_bus_reset__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
+#define USBFS_bus_reset__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
+#define USBFS_Dm__0__INTTYPE CYREG_PICU15_INTTYPE7\r
+#define USBFS_Dm__0__MASK 0x80u\r
+#define USBFS_Dm__0__PC CYREG_IO_PC_PRT15_7_6_PC1\r
+#define USBFS_Dm__0__PORT 15u\r
+#define USBFS_Dm__0__SHIFT 7u\r
+#define USBFS_Dm__AG CYREG_PRT15_AG\r
+#define USBFS_Dm__AMUX CYREG_PRT15_AMUX\r
+#define USBFS_Dm__BIE CYREG_PRT15_BIE\r
+#define USBFS_Dm__BIT_MASK CYREG_PRT15_BIT_MASK\r
+#define USBFS_Dm__BYP CYREG_PRT15_BYP\r
+#define USBFS_Dm__CTL CYREG_PRT15_CTL\r
+#define USBFS_Dm__DM0 CYREG_PRT15_DM0\r
+#define USBFS_Dm__DM1 CYREG_PRT15_DM1\r
+#define USBFS_Dm__DM2 CYREG_PRT15_DM2\r
+#define USBFS_Dm__DR CYREG_PRT15_DR\r
+#define USBFS_Dm__INP_DIS CYREG_PRT15_INP_DIS\r
+#define USBFS_Dm__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU15_BASE\r
+#define USBFS_Dm__LCD_COM_SEG CYREG_PRT15_LCD_COM_SEG\r
+#define USBFS_Dm__LCD_EN CYREG_PRT15_LCD_EN\r
+#define USBFS_Dm__MASK 0x80u\r
+#define USBFS_Dm__PORT 15u\r
+#define USBFS_Dm__PRT CYREG_PRT15_PRT\r
+#define USBFS_Dm__PRTDSI__CAPS_SEL CYREG_PRT15_CAPS_SEL\r
+#define USBFS_Dm__PRTDSI__DBL_SYNC_IN CYREG_PRT15_DBL_SYNC_IN\r
+#define USBFS_Dm__PRTDSI__OE_SEL0 CYREG_PRT15_OE_SEL0\r
+#define USBFS_Dm__PRTDSI__OE_SEL1 CYREG_PRT15_OE_SEL1\r
+#define USBFS_Dm__PRTDSI__OUT_SEL0 CYREG_PRT15_OUT_SEL0\r
+#define USBFS_Dm__PRTDSI__OUT_SEL1 CYREG_PRT15_OUT_SEL1\r
+#define USBFS_Dm__PRTDSI__SYNC_OUT CYREG_PRT15_SYNC_OUT\r
+#define USBFS_Dm__PS CYREG_PRT15_PS\r
+#define USBFS_Dm__SHIFT 7u\r
+#define USBFS_Dm__SLW CYREG_PRT15_SLW\r
+#define USBFS_Dp__0__INTTYPE CYREG_PICU15_INTTYPE6\r
+#define USBFS_Dp__0__MASK 0x40u\r
+#define USBFS_Dp__0__PC CYREG_IO_PC_PRT15_7_6_PC0\r
+#define USBFS_Dp__0__PORT 15u\r
+#define USBFS_Dp__0__SHIFT 6u\r
+#define USBFS_Dp__AG CYREG_PRT15_AG\r
+#define USBFS_Dp__AMUX CYREG_PRT15_AMUX\r
+#define USBFS_Dp__BIE CYREG_PRT15_BIE\r
+#define USBFS_Dp__BIT_MASK CYREG_PRT15_BIT_MASK\r
+#define USBFS_Dp__BYP CYREG_PRT15_BYP\r
+#define USBFS_Dp__CTL CYREG_PRT15_CTL\r
+#define USBFS_Dp__DM0 CYREG_PRT15_DM0\r
+#define USBFS_Dp__DM1 CYREG_PRT15_DM1\r
+#define USBFS_Dp__DM2 CYREG_PRT15_DM2\r
+#define USBFS_Dp__DR CYREG_PRT15_DR\r
+#define USBFS_Dp__INP_DIS CYREG_PRT15_INP_DIS\r
+#define USBFS_Dp__INTSTAT CYREG_PICU15_INTSTAT\r
+#define USBFS_Dp__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU15_BASE\r
+#define USBFS_Dp__LCD_COM_SEG CYREG_PRT15_LCD_COM_SEG\r
+#define USBFS_Dp__LCD_EN CYREG_PRT15_LCD_EN\r
+#define USBFS_Dp__MASK 0x40u\r
+#define USBFS_Dp__PORT 15u\r
+#define USBFS_Dp__PRT CYREG_PRT15_PRT\r
+#define USBFS_Dp__PRTDSI__CAPS_SEL CYREG_PRT15_CAPS_SEL\r
+#define USBFS_Dp__PRTDSI__DBL_SYNC_IN CYREG_PRT15_DBL_SYNC_IN\r
+#define USBFS_Dp__PRTDSI__OE_SEL0 CYREG_PRT15_OE_SEL0\r
+#define USBFS_Dp__PRTDSI__OE_SEL1 CYREG_PRT15_OE_SEL1\r
+#define USBFS_Dp__PRTDSI__OUT_SEL0 CYREG_PRT15_OUT_SEL0\r
+#define USBFS_Dp__PRTDSI__OUT_SEL1 CYREG_PRT15_OUT_SEL1\r
+#define USBFS_Dp__PRTDSI__SYNC_OUT CYREG_PRT15_SYNC_OUT\r
+#define USBFS_Dp__PS CYREG_PRT15_PS\r
+#define USBFS_Dp__SHIFT 6u\r
+#define USBFS_Dp__SLW CYREG_PRT15_SLW\r
+#define USBFS_Dp__SNAP CYREG_PICU_15_SNAP_15\r
+#define USBFS_dp_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
+#define USBFS_dp_int__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
+#define USBFS_dp_int__INTC_MASK 0x1000u\r
+#define USBFS_dp_int__INTC_NUMBER 12u\r
+#define USBFS_dp_int__INTC_PRIOR_NUM 7u\r
+#define USBFS_dp_int__INTC_PRIOR_REG CYREG_NVIC_PRI_12\r
+#define USBFS_dp_int__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
+#define USBFS_dp_int__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
+#define USBFS_ep_0__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
+#define USBFS_ep_0__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
+#define USBFS_ep_0__INTC_MASK 0x1000000u\r
+#define USBFS_ep_0__INTC_NUMBER 24u\r
+#define USBFS_ep_0__INTC_PRIOR_NUM 7u\r
+#define USBFS_ep_0__INTC_PRIOR_REG CYREG_NVIC_PRI_24\r
+#define USBFS_ep_0__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
+#define USBFS_ep_0__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
+#define USBFS_ep_1__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
+#define USBFS_ep_1__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
+#define USBFS_ep_1__INTC_MASK 0x80u\r
+#define USBFS_ep_1__INTC_NUMBER 7u\r
+#define USBFS_ep_1__INTC_PRIOR_NUM 7u\r
+#define USBFS_ep_1__INTC_PRIOR_REG CYREG_NVIC_PRI_7\r
+#define USBFS_ep_1__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
+#define USBFS_ep_1__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
+#define USBFS_ep_2__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
+#define USBFS_ep_2__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
+#define USBFS_ep_2__INTC_MASK 0x100u\r
+#define USBFS_ep_2__INTC_NUMBER 8u\r
+#define USBFS_ep_2__INTC_PRIOR_NUM 7u\r
+#define USBFS_ep_2__INTC_PRIOR_REG CYREG_NVIC_PRI_8\r
+#define USBFS_ep_2__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
+#define USBFS_ep_2__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
+#define USBFS_ep_3__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
+#define USBFS_ep_3__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
+#define USBFS_ep_3__INTC_MASK 0x200u\r
+#define USBFS_ep_3__INTC_NUMBER 9u\r
+#define USBFS_ep_3__INTC_PRIOR_NUM 7u\r
+#define USBFS_ep_3__INTC_PRIOR_REG CYREG_NVIC_PRI_9\r
+#define USBFS_ep_3__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
+#define USBFS_ep_3__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
+#define USBFS_ep_4__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
+#define USBFS_ep_4__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
+#define USBFS_ep_4__INTC_MASK 0x400u\r
+#define USBFS_ep_4__INTC_NUMBER 10u\r
+#define USBFS_ep_4__INTC_PRIOR_NUM 7u\r
+#define USBFS_ep_4__INTC_PRIOR_REG CYREG_NVIC_PRI_10\r
+#define USBFS_ep_4__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
+#define USBFS_ep_4__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
+#define USBFS_sof_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
+#define USBFS_sof_int__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
+#define USBFS_sof_int__INTC_MASK 0x200000u\r
+#define USBFS_sof_int__INTC_NUMBER 21u\r
+#define USBFS_sof_int__INTC_PRIOR_NUM 7u\r
+#define USBFS_sof_int__INTC_PRIOR_REG CYREG_NVIC_PRI_21\r
+#define USBFS_sof_int__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
+#define USBFS_sof_int__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
+#define USBFS_USB__ARB_CFG CYREG_USB_ARB_CFG\r
+#define USBFS_USB__ARB_EP1_CFG CYREG_USB_ARB_EP1_CFG\r
+#define USBFS_USB__ARB_EP1_INT_EN CYREG_USB_ARB_EP1_INT_EN\r
+#define USBFS_USB__ARB_EP1_SR CYREG_USB_ARB_EP1_SR\r
+#define USBFS_USB__ARB_EP2_CFG CYREG_USB_ARB_EP2_CFG\r
+#define USBFS_USB__ARB_EP2_INT_EN CYREG_USB_ARB_EP2_INT_EN\r
+#define USBFS_USB__ARB_EP2_SR CYREG_USB_ARB_EP2_SR\r
+#define USBFS_USB__ARB_EP3_CFG CYREG_USB_ARB_EP3_CFG\r
+#define USBFS_USB__ARB_EP3_INT_EN CYREG_USB_ARB_EP3_INT_EN\r
+#define USBFS_USB__ARB_EP3_SR CYREG_USB_ARB_EP3_SR\r
+#define USBFS_USB__ARB_EP4_CFG CYREG_USB_ARB_EP4_CFG\r
+#define USBFS_USB__ARB_EP4_INT_EN CYREG_USB_ARB_EP4_INT_EN\r
+#define USBFS_USB__ARB_EP4_SR CYREG_USB_ARB_EP4_SR\r
+#define USBFS_USB__ARB_EP5_CFG CYREG_USB_ARB_EP5_CFG\r
+#define USBFS_USB__ARB_EP5_INT_EN CYREG_USB_ARB_EP5_INT_EN\r
+#define USBFS_USB__ARB_EP5_SR CYREG_USB_ARB_EP5_SR\r
+#define USBFS_USB__ARB_EP6_CFG CYREG_USB_ARB_EP6_CFG\r
+#define USBFS_USB__ARB_EP6_INT_EN CYREG_USB_ARB_EP6_INT_EN\r
+#define USBFS_USB__ARB_EP6_SR CYREG_USB_ARB_EP6_SR\r
+#define USBFS_USB__ARB_EP7_CFG CYREG_USB_ARB_EP7_CFG\r
+#define USBFS_USB__ARB_EP7_INT_EN CYREG_USB_ARB_EP7_INT_EN\r
+#define USBFS_USB__ARB_EP7_SR CYREG_USB_ARB_EP7_SR\r
+#define USBFS_USB__ARB_EP8_CFG CYREG_USB_ARB_EP8_CFG\r
+#define USBFS_USB__ARB_EP8_INT_EN CYREG_USB_ARB_EP8_INT_EN\r
+#define USBFS_USB__ARB_EP8_SR CYREG_USB_ARB_EP8_SR\r
+#define USBFS_USB__ARB_INT_EN CYREG_USB_ARB_INT_EN\r
+#define USBFS_USB__ARB_INT_SR CYREG_USB_ARB_INT_SR\r
+#define USBFS_USB__ARB_RW1_DR CYREG_USB_ARB_RW1_DR\r
+#define USBFS_USB__ARB_RW1_RA CYREG_USB_ARB_RW1_RA\r
+#define USBFS_USB__ARB_RW1_RA_MSB CYREG_USB_ARB_RW1_RA_MSB\r
+#define USBFS_USB__ARB_RW1_WA CYREG_USB_ARB_RW1_WA\r
+#define USBFS_USB__ARB_RW1_WA_MSB CYREG_USB_ARB_RW1_WA_MSB\r
+#define USBFS_USB__ARB_RW2_DR CYREG_USB_ARB_RW2_DR\r
+#define USBFS_USB__ARB_RW2_RA CYREG_USB_ARB_RW2_RA\r
+#define USBFS_USB__ARB_RW2_RA_MSB CYREG_USB_ARB_RW2_RA_MSB\r
+#define USBFS_USB__ARB_RW2_WA CYREG_USB_ARB_RW2_WA\r
+#define USBFS_USB__ARB_RW2_WA_MSB CYREG_USB_ARB_RW2_WA_MSB\r
+#define USBFS_USB__ARB_RW3_DR CYREG_USB_ARB_RW3_DR\r
+#define USBFS_USB__ARB_RW3_RA CYREG_USB_ARB_RW3_RA\r
+#define USBFS_USB__ARB_RW3_RA_MSB CYREG_USB_ARB_RW3_RA_MSB\r
+#define USBFS_USB__ARB_RW3_WA CYREG_USB_ARB_RW3_WA\r
+#define USBFS_USB__ARB_RW3_WA_MSB CYREG_USB_ARB_RW3_WA_MSB\r
+#define USBFS_USB__ARB_RW4_DR CYREG_USB_ARB_RW4_DR\r
+#define USBFS_USB__ARB_RW4_RA CYREG_USB_ARB_RW4_RA\r
+#define USBFS_USB__ARB_RW4_RA_MSB CYREG_USB_ARB_RW4_RA_MSB\r
+#define USBFS_USB__ARB_RW4_WA CYREG_USB_ARB_RW4_WA\r
+#define USBFS_USB__ARB_RW4_WA_MSB CYREG_USB_ARB_RW4_WA_MSB\r
+#define USBFS_USB__ARB_RW5_DR CYREG_USB_ARB_RW5_DR\r
+#define USBFS_USB__ARB_RW5_RA CYREG_USB_ARB_RW5_RA\r
+#define USBFS_USB__ARB_RW5_RA_MSB CYREG_USB_ARB_RW5_RA_MSB\r
+#define USBFS_USB__ARB_RW5_WA CYREG_USB_ARB_RW5_WA\r
+#define USBFS_USB__ARB_RW5_WA_MSB CYREG_USB_ARB_RW5_WA_MSB\r
+#define USBFS_USB__ARB_RW6_DR CYREG_USB_ARB_RW6_DR\r
+#define USBFS_USB__ARB_RW6_RA CYREG_USB_ARB_RW6_RA\r
+#define USBFS_USB__ARB_RW6_RA_MSB CYREG_USB_ARB_RW6_RA_MSB\r
+#define USBFS_USB__ARB_RW6_WA CYREG_USB_ARB_RW6_WA\r
+#define USBFS_USB__ARB_RW6_WA_MSB CYREG_USB_ARB_RW6_WA_MSB\r
+#define USBFS_USB__ARB_RW7_DR CYREG_USB_ARB_RW7_DR\r
+#define USBFS_USB__ARB_RW7_RA CYREG_USB_ARB_RW7_RA\r
+#define USBFS_USB__ARB_RW7_RA_MSB CYREG_USB_ARB_RW7_RA_MSB\r
+#define USBFS_USB__ARB_RW7_WA CYREG_USB_ARB_RW7_WA\r
+#define USBFS_USB__ARB_RW7_WA_MSB CYREG_USB_ARB_RW7_WA_MSB\r
+#define USBFS_USB__ARB_RW8_DR CYREG_USB_ARB_RW8_DR\r
+#define USBFS_USB__ARB_RW8_RA CYREG_USB_ARB_RW8_RA\r
+#define USBFS_USB__ARB_RW8_RA_MSB CYREG_USB_ARB_RW8_RA_MSB\r
+#define USBFS_USB__ARB_RW8_WA CYREG_USB_ARB_RW8_WA\r
+#define USBFS_USB__ARB_RW8_WA_MSB CYREG_USB_ARB_RW8_WA_MSB\r
+#define USBFS_USB__BUF_SIZE CYREG_USB_BUF_SIZE\r
+#define USBFS_USB__BUS_RST_CNT CYREG_USB_BUS_RST_CNT\r
+#define USBFS_USB__CR0 CYREG_USB_CR0\r
+#define USBFS_USB__CR1 CYREG_USB_CR1\r
+#define USBFS_USB__CWA CYREG_USB_CWA\r
+#define USBFS_USB__CWA_MSB CYREG_USB_CWA_MSB\r
+#define USBFS_USB__DMA_THRES CYREG_USB_DMA_THRES\r
+#define USBFS_USB__DMA_THRES_MSB CYREG_USB_DMA_THRES_MSB\r
+#define USBFS_USB__DYN_RECONFIG CYREG_USB_DYN_RECONFIG\r
+#define USBFS_USB__EP_ACTIVE CYREG_USB_EP_ACTIVE\r
+#define USBFS_USB__EP_TYPE CYREG_USB_EP_TYPE\r
+#define USBFS_USB__EP0_CNT CYREG_USB_EP0_CNT\r
+#define USBFS_USB__EP0_CR CYREG_USB_EP0_CR\r
+#define USBFS_USB__EP0_DR0 CYREG_USB_EP0_DR0\r
+#define USBFS_USB__EP0_DR1 CYREG_USB_EP0_DR1\r
+#define USBFS_USB__EP0_DR2 CYREG_USB_EP0_DR2\r
+#define USBFS_USB__EP0_DR3 CYREG_USB_EP0_DR3\r
+#define USBFS_USB__EP0_DR4 CYREG_USB_EP0_DR4\r
+#define USBFS_USB__EP0_DR5 CYREG_USB_EP0_DR5\r
+#define USBFS_USB__EP0_DR6 CYREG_USB_EP0_DR6\r
+#define USBFS_USB__EP0_DR7 CYREG_USB_EP0_DR7\r
+#define USBFS_USB__MEM_DATA CYREG_USB_MEM_DATA_MBASE\r
+#define USBFS_USB__PM_ACT_CFG CYREG_PM_ACT_CFG5\r
+#define USBFS_USB__PM_ACT_MSK 0x01u\r
+#define USBFS_USB__PM_STBY_CFG CYREG_PM_STBY_CFG5\r
+#define USBFS_USB__PM_STBY_MSK 0x01u\r
+#define USBFS_USB__SIE_EP_INT_EN CYREG_USB_SIE_EP_INT_EN\r
+#define USBFS_USB__SIE_EP_INT_SR CYREG_USB_SIE_EP_INT_SR\r
+#define USBFS_USB__SIE_EP1_CNT0 CYREG_USB_SIE_EP1_CNT0\r
+#define USBFS_USB__SIE_EP1_CNT1 CYREG_USB_SIE_EP1_CNT1\r
+#define USBFS_USB__SIE_EP1_CR0 CYREG_USB_SIE_EP1_CR0\r
+#define USBFS_USB__SIE_EP2_CNT0 CYREG_USB_SIE_EP2_CNT0\r
+#define USBFS_USB__SIE_EP2_CNT1 CYREG_USB_SIE_EP2_CNT1\r
+#define USBFS_USB__SIE_EP2_CR0 CYREG_USB_SIE_EP2_CR0\r
+#define USBFS_USB__SIE_EP3_CNT0 CYREG_USB_SIE_EP3_CNT0\r
+#define USBFS_USB__SIE_EP3_CNT1 CYREG_USB_SIE_EP3_CNT1\r
+#define USBFS_USB__SIE_EP3_CR0 CYREG_USB_SIE_EP3_CR0\r
+#define USBFS_USB__SIE_EP4_CNT0 CYREG_USB_SIE_EP4_CNT0\r
+#define USBFS_USB__SIE_EP4_CNT1 CYREG_USB_SIE_EP4_CNT1\r
+#define USBFS_USB__SIE_EP4_CR0 CYREG_USB_SIE_EP4_CR0\r
+#define USBFS_USB__SIE_EP5_CNT0 CYREG_USB_SIE_EP5_CNT0\r
+#define USBFS_USB__SIE_EP5_CNT1 CYREG_USB_SIE_EP5_CNT1\r
+#define USBFS_USB__SIE_EP5_CR0 CYREG_USB_SIE_EP5_CR0\r
+#define USBFS_USB__SIE_EP6_CNT0 CYREG_USB_SIE_EP6_CNT0\r
+#define USBFS_USB__SIE_EP6_CNT1 CYREG_USB_SIE_EP6_CNT1\r
+#define USBFS_USB__SIE_EP6_CR0 CYREG_USB_SIE_EP6_CR0\r
+#define USBFS_USB__SIE_EP7_CNT0 CYREG_USB_SIE_EP7_CNT0\r
+#define USBFS_USB__SIE_EP7_CNT1 CYREG_USB_SIE_EP7_CNT1\r
+#define USBFS_USB__SIE_EP7_CR0 CYREG_USB_SIE_EP7_CR0\r
+#define USBFS_USB__SIE_EP8_CNT0 CYREG_USB_SIE_EP8_CNT0\r
+#define USBFS_USB__SIE_EP8_CNT1 CYREG_USB_SIE_EP8_CNT1\r
+#define USBFS_USB__SIE_EP8_CR0 CYREG_USB_SIE_EP8_CR0\r
+#define USBFS_USB__SOF0 CYREG_USB_SOF0\r
+#define USBFS_USB__SOF1 CYREG_USB_SOF1\r
+#define USBFS_USB__USB_CLK_EN CYREG_USB_USB_CLK_EN\r
+#define USBFS_USB__USBIO_CR0 CYREG_USB_USBIO_CR0\r
+#define USBFS_USB__USBIO_CR1 CYREG_USB_USBIO_CR1\r
+\r
 /* scsiTarget */\r
 #define scsiTarget_datapath__16BIT_A0_REG CYREG_B0_UDB00_01_A0\r
 #define scsiTarget_datapath__16BIT_A1_REG CYREG_B0_UDB00_01_A1\r
@@ -2841,89 +2998,6 @@
 #define scsiTarget_StatusReg__STATUS_CONTROL_REG CYREG_B0_UDB07_ST_CTL\r
 #define scsiTarget_StatusReg__STATUS_REG CYREG_B0_UDB07_ST\r
 \r
-/* Debug_Timer_Interrupt */\r
-#define Debug_Timer_Interrupt__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
-#define Debug_Timer_Interrupt__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
-#define Debug_Timer_Interrupt__INTC_MASK 0x02u\r
-#define Debug_Timer_Interrupt__INTC_NUMBER 1u\r
-#define Debug_Timer_Interrupt__INTC_PRIOR_NUM 7u\r
-#define Debug_Timer_Interrupt__INTC_PRIOR_REG CYREG_NVIC_PRI_1\r
-#define Debug_Timer_Interrupt__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
-#define Debug_Timer_Interrupt__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
-\r
-/* Debug_Timer_TimerHW */\r
-#define Debug_Timer_TimerHW__CAP0 CYREG_TMR0_CAP0\r
-#define Debug_Timer_TimerHW__CAP1 CYREG_TMR0_CAP1\r
-#define Debug_Timer_TimerHW__CFG0 CYREG_TMR0_CFG0\r
-#define Debug_Timer_TimerHW__CFG1 CYREG_TMR0_CFG1\r
-#define Debug_Timer_TimerHW__CFG2 CYREG_TMR0_CFG2\r
-#define Debug_Timer_TimerHW__CNT_CMP0 CYREG_TMR0_CNT_CMP0\r
-#define Debug_Timer_TimerHW__CNT_CMP1 CYREG_TMR0_CNT_CMP1\r
-#define Debug_Timer_TimerHW__PER0 CYREG_TMR0_PER0\r
-#define Debug_Timer_TimerHW__PER1 CYREG_TMR0_PER1\r
-#define Debug_Timer_TimerHW__PM_ACT_CFG CYREG_PM_ACT_CFG3\r
-#define Debug_Timer_TimerHW__PM_ACT_MSK 0x01u\r
-#define Debug_Timer_TimerHW__PM_STBY_CFG CYREG_PM_STBY_CFG3\r
-#define Debug_Timer_TimerHW__PM_STBY_MSK 0x01u\r
-#define Debug_Timer_TimerHW__RT0 CYREG_TMR0_RT0\r
-#define Debug_Timer_TimerHW__RT1 CYREG_TMR0_RT1\r
-#define Debug_Timer_TimerHW__SR0 CYREG_TMR0_SR0\r
-\r
-/* SCSI_RX_DMA */\r
-#define SCSI_RX_DMA__DRQ_CTL CYREG_IDMUX_DRQ_CTL0\r
-#define SCSI_RX_DMA__DRQ_NUMBER 0u\r
-#define SCSI_RX_DMA__NUMBEROF_TDS 0u\r
-#define SCSI_RX_DMA__PRIORITY 2u\r
-#define SCSI_RX_DMA__TERMIN_EN 0u\r
-#define SCSI_RX_DMA__TERMIN_SEL 0u\r
-#define SCSI_RX_DMA__TERMOUT0_EN 1u\r
-#define SCSI_RX_DMA__TERMOUT0_SEL 0u\r
-#define SCSI_RX_DMA__TERMOUT1_EN 0u\r
-#define SCSI_RX_DMA__TERMOUT1_SEL 0u\r
-\r
-/* SCSI_RX_DMA_COMPLETE */\r
-#define SCSI_RX_DMA_COMPLETE__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
-#define SCSI_RX_DMA_COMPLETE__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
-#define SCSI_RX_DMA_COMPLETE__INTC_MASK 0x01u\r
-#define SCSI_RX_DMA_COMPLETE__INTC_NUMBER 0u\r
-#define SCSI_RX_DMA_COMPLETE__INTC_PRIOR_NUM 7u\r
-#define SCSI_RX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_0\r
-#define SCSI_RX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
-#define SCSI_RX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
-\r
-/* SCSI_TX_DMA */\r
-#define SCSI_TX_DMA__DRQ_CTL CYREG_IDMUX_DRQ_CTL0\r
-#define SCSI_TX_DMA__DRQ_NUMBER 1u\r
-#define SCSI_TX_DMA__NUMBEROF_TDS 0u\r
-#define SCSI_TX_DMA__PRIORITY 2u\r
-#define SCSI_TX_DMA__TERMIN_EN 0u\r
-#define SCSI_TX_DMA__TERMIN_SEL 0u\r
-#define SCSI_TX_DMA__TERMOUT0_EN 1u\r
-#define SCSI_TX_DMA__TERMOUT0_SEL 1u\r
-#define SCSI_TX_DMA__TERMOUT1_EN 0u\r
-#define SCSI_TX_DMA__TERMOUT1_SEL 0u\r
-\r
-/* SCSI_TX_DMA_COMPLETE */\r
-#define SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
-#define SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
-#define SCSI_TX_DMA_COMPLETE__INTC_MASK 0x10u\r
-#define SCSI_TX_DMA_COMPLETE__INTC_NUMBER 4u\r
-#define SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM 7u\r
-#define SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_4\r
-#define SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
-#define SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
-\r
-/* SD_Data_Clk */\r
-#define SD_Data_Clk__CFG0 CYREG_CLKDIST_DCFG0_CFG0\r
-#define SD_Data_Clk__CFG1 CYREG_CLKDIST_DCFG0_CFG1\r
-#define SD_Data_Clk__CFG2 CYREG_CLKDIST_DCFG0_CFG2\r
-#define SD_Data_Clk__CFG2_SRC_SEL_MASK 0x07u\r
-#define SD_Data_Clk__INDEX 0x00u\r
-#define SD_Data_Clk__PM_ACT_CFG CYREG_PM_ACT_CFG2\r
-#define SD_Data_Clk__PM_ACT_MSK 0x01u\r
-#define SD_Data_Clk__PM_STBY_CFG CYREG_PM_STBY_CFG2\r
-#define SD_Data_Clk__PM_STBY_MSK 0x01u\r
-\r
 /* timer_clock */\r
 #define timer_clock__CFG0 CYREG_CLKDIST_DCFG2_CFG0\r
 #define timer_clock__CFG1 CYREG_CLKDIST_DCFG2_CFG1\r
@@ -2935,148 +3009,55 @@
 #define timer_clock__PM_STBY_CFG CYREG_PM_STBY_CFG2\r
 #define timer_clock__PM_STBY_MSK 0x04u\r
 \r
-/* SCSI_RST_ISR */\r
-#define SCSI_RST_ISR__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
-#define SCSI_RST_ISR__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
-#define SCSI_RST_ISR__INTC_MASK 0x04u\r
-#define SCSI_RST_ISR__INTC_NUMBER 2u\r
-#define SCSI_RST_ISR__INTC_PRIOR_NUM 7u\r
-#define SCSI_RST_ISR__INTC_PRIOR_REG CYREG_NVIC_PRI_2\r
-#define SCSI_RST_ISR__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
-#define SCSI_RST_ISR__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
-\r
-/* SCSI_SEL_ISR */\r
-#define SCSI_SEL_ISR__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
-#define SCSI_SEL_ISR__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
-#define SCSI_SEL_ISR__INTC_MASK 0x08u\r
-#define SCSI_SEL_ISR__INTC_NUMBER 3u\r
-#define SCSI_SEL_ISR__INTC_PRIOR_NUM 7u\r
-#define SCSI_SEL_ISR__INTC_PRIOR_REG CYREG_NVIC_PRI_3\r
-#define SCSI_SEL_ISR__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
-#define SCSI_SEL_ISR__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
-\r
-/* SCSI_Filtered */\r
-#define SCSI_Filtered_sts_sts_reg__0__MASK 0x01u\r
-#define SCSI_Filtered_sts_sts_reg__0__POS 0\r
-#define SCSI_Filtered_sts_sts_reg__1__MASK 0x02u\r
-#define SCSI_Filtered_sts_sts_reg__1__POS 1\r
-#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB02_03_ACTL\r
-#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB02_03_ST\r
-#define SCSI_Filtered_sts_sts_reg__2__MASK 0x04u\r
-#define SCSI_Filtered_sts_sts_reg__2__POS 2\r
-#define SCSI_Filtered_sts_sts_reg__3__MASK 0x08u\r
-#define SCSI_Filtered_sts_sts_reg__3__POS 3\r
-#define SCSI_Filtered_sts_sts_reg__4__MASK 0x10u\r
-#define SCSI_Filtered_sts_sts_reg__4__POS 4\r
-#define SCSI_Filtered_sts_sts_reg__MASK 0x1Fu\r
-#define SCSI_Filtered_sts_sts_reg__MASK_REG CYREG_B0_UDB02_MSK\r
-#define SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB02_ACTL\r
-#define SCSI_Filtered_sts_sts_reg__STATUS_REG CYREG_B0_UDB02_ST\r
-\r
-/* SCSI_CTL_PHASE */\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK 0x01u\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS 0\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK 0x02u\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS 1\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB05_06_ACTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB05_06_CTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB05_06_CTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB05_06_CTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB05_06_CTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB05_06_MSK\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB05_06_MSK\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB05_06_MSK\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB05_06_MSK\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK 0x04u\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS 2\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB05_ACTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB05_CTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB05_ST_CTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB05_CTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB05_ST_CTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK 0x07u\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB05_MSK\r
-\r
-/* SCSI_Glitch_Ctl */\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK 0x01u\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS 0\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB07_08_ACTL\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB07_08_CTL\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB07_08_CTL\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB07_08_CTL\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB07_08_CTL\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB07_08_MSK\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB07_08_MSK\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB07_08_MSK\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB07_08_MSK\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB07_ACTL\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB07_CTL\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB07_ST_CTL\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB07_CTL\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB07_ST_CTL\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK 0x01u\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB07_MSK_ACTL\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB07_MSK_ACTL\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB07_MSK\r
-\r
-/* SCSI_Parity_Error */\r
-#define SCSI_Parity_Error_sts_sts_reg__0__MASK 0x01u\r
-#define SCSI_Parity_Error_sts_sts_reg__0__POS 0\r
-#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB01_02_ACTL\r
-#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB01_02_ST\r
-#define SCSI_Parity_Error_sts_sts_reg__MASK 0x01u\r
-#define SCSI_Parity_Error_sts_sts_reg__MASK_REG CYREG_B0_UDB01_MSK\r
-#define SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB01_ACTL\r
-#define SCSI_Parity_Error_sts_sts_reg__STATUS_REG CYREG_B0_UDB01_ST\r
-\r
 /* Miscellaneous */\r
 #define BCLK__BUS_CLK__HZ 50000000U\r
 #define BCLK__BUS_CLK__KHZ 50000U\r
 #define BCLK__BUS_CLK__MHZ 50U\r
 #define CY_PROJECT_NAME "SCSI2SD"\r
-#define CY_VERSION "PSoC Creator  4.0 Update 1"\r
+#define CY_VERSION "PSoC Creator  4.1"\r
 #define CYDEV_CHIP_DIE_LEOPARD 1u\r
-#define CYDEV_CHIP_DIE_PSOC4A 12u\r
-#define CYDEV_CHIP_DIE_PSOC5LP 19u\r
-#define CYDEV_CHIP_DIE_PSOC5TM 20u\r
-#define CYDEV_CHIP_DIE_TMA4 2u\r
+#define CYDEV_CHIP_DIE_PSOC4A 16u\r
+#define CYDEV_CHIP_DIE_PSOC5LP 2u\r
+#define CYDEV_CHIP_DIE_PSOC5TM 3u\r
+#define CYDEV_CHIP_DIE_TMA4 4u\r
 #define CYDEV_CHIP_DIE_UNKNOWN 0u\r
-#define CYDEV_CHIP_FAMILY_FM0P 4u\r
-#define CYDEV_CHIP_FAMILY_FM3 5u\r
-#define CYDEV_CHIP_FAMILY_FM4 6u\r
+#define CYDEV_CHIP_FAMILY_FM0P 5u\r
+#define CYDEV_CHIP_FAMILY_FM3 6u\r
+#define CYDEV_CHIP_FAMILY_FM4 7u\r
 #define CYDEV_CHIP_FAMILY_PSOC3 1u\r
 #define CYDEV_CHIP_FAMILY_PSOC4 2u\r
 #define CYDEV_CHIP_FAMILY_PSOC5 3u\r
+#define CYDEV_CHIP_FAMILY_PSOC6 4u\r
 #define CYDEV_CHIP_FAMILY_UNKNOWN 0u\r
 #define CYDEV_CHIP_FAMILY_USED CYDEV_CHIP_FAMILY_PSOC5\r
 #define CYDEV_CHIP_JTAG_ID 0x2E133069u\r
 #define CYDEV_CHIP_MEMBER_3A 1u\r
-#define CYDEV_CHIP_MEMBER_4A 12u\r
-#define CYDEV_CHIP_MEMBER_4C 18u\r
-#define CYDEV_CHIP_MEMBER_4D 8u\r
-#define CYDEV_CHIP_MEMBER_4E 4u\r
-#define CYDEV_CHIP_MEMBER_4F 13u\r
-#define CYDEV_CHIP_MEMBER_4G 2u\r
-#define CYDEV_CHIP_MEMBER_4H 11u\r
-#define CYDEV_CHIP_MEMBER_4I 17u\r
-#define CYDEV_CHIP_MEMBER_4J 9u\r
-#define CYDEV_CHIP_MEMBER_4K 10u\r
-#define CYDEV_CHIP_MEMBER_4L 16u\r
-#define CYDEV_CHIP_MEMBER_4M 15u\r
-#define CYDEV_CHIP_MEMBER_4N 6u\r
-#define CYDEV_CHIP_MEMBER_4O 5u\r
-#define CYDEV_CHIP_MEMBER_4P 14u\r
-#define CYDEV_CHIP_MEMBER_4Q 7u\r
-#define CYDEV_CHIP_MEMBER_4U 3u\r
-#define CYDEV_CHIP_MEMBER_5A 20u\r
-#define CYDEV_CHIP_MEMBER_5B 19u\r
-#define CYDEV_CHIP_MEMBER_FM3 24u\r
-#define CYDEV_CHIP_MEMBER_FM4 25u\r
-#define CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE1 21u\r
-#define CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE2 22u\r
-#define CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE3 23u\r
+#define CYDEV_CHIP_MEMBER_4A 16u\r
+#define CYDEV_CHIP_MEMBER_4D 12u\r
+#define CYDEV_CHIP_MEMBER_4E 6u\r
+#define CYDEV_CHIP_MEMBER_4F 17u\r
+#define CYDEV_CHIP_MEMBER_4G 4u\r
+#define CYDEV_CHIP_MEMBER_4H 15u\r
+#define CYDEV_CHIP_MEMBER_4I 21u\r
+#define CYDEV_CHIP_MEMBER_4J 13u\r
+#define CYDEV_CHIP_MEMBER_4K 14u\r
+#define CYDEV_CHIP_MEMBER_4L 20u\r
+#define CYDEV_CHIP_MEMBER_4M 19u\r
+#define CYDEV_CHIP_MEMBER_4N 9u\r
+#define CYDEV_CHIP_MEMBER_4O 7u\r
+#define CYDEV_CHIP_MEMBER_4P 18u\r
+#define CYDEV_CHIP_MEMBER_4Q 11u\r
+#define CYDEV_CHIP_MEMBER_4R 8u\r
+#define CYDEV_CHIP_MEMBER_4S 10u\r
+#define CYDEV_CHIP_MEMBER_4U 5u\r
+#define CYDEV_CHIP_MEMBER_5A 3u\r
+#define CYDEV_CHIP_MEMBER_5B 2u\r
+#define CYDEV_CHIP_MEMBER_6A 22u\r
+#define CYDEV_CHIP_MEMBER_FM3 26u\r
+#define CYDEV_CHIP_MEMBER_FM4 27u\r
+#define CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE1 23u\r
+#define CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE2 24u\r
+#define CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE3 25u\r
 #define CYDEV_CHIP_MEMBER_UNKNOWN 0u\r
 #define CYDEV_CHIP_MEMBER_USED CYDEV_CHIP_MEMBER_5B\r
 #define CYDEV_CHIP_DIE_EXPECT CYDEV_CHIP_MEMBER_USED\r
@@ -3101,7 +3082,6 @@
 #define CYDEV_CHIP_REVISION_3A_PRODUCTION 3u\r
 #define CYDEV_CHIP_REVISION_4A_ES0 17u\r
 #define CYDEV_CHIP_REVISION_4A_PRODUCTION 17u\r
-#define CYDEV_CHIP_REVISION_4C_PRODUCTION 0u\r
 #define CYDEV_CHIP_REVISION_4D_PRODUCTION 0u\r
 #define CYDEV_CHIP_REVISION_4E_PRODUCTION 0u\r
 #define CYDEV_CHIP_REVISION_4F_PRODUCTION 0u\r
@@ -3120,12 +3100,16 @@
 #define CYDEV_CHIP_REVISION_4O_PRODUCTION 0u\r
 #define CYDEV_CHIP_REVISION_4P_PRODUCTION 0u\r
 #define CYDEV_CHIP_REVISION_4Q_PRODUCTION 0u\r
+#define CYDEV_CHIP_REVISION_4R_PRODUCTION 0u\r
+#define CYDEV_CHIP_REVISION_4S_PRODUCTION 0u\r
 #define CYDEV_CHIP_REVISION_4U_PRODUCTION 0u\r
 #define CYDEV_CHIP_REVISION_5A_ES0 0u\r
 #define CYDEV_CHIP_REVISION_5A_ES1 1u\r
 #define CYDEV_CHIP_REVISION_5A_PRODUCTION 1u\r
 #define CYDEV_CHIP_REVISION_5B_ES0 0u\r
 #define CYDEV_CHIP_REVISION_5B_PRODUCTION 0u\r
+#define CYDEV_CHIP_REVISION_6A_NO_UDB 0u\r
+#define CYDEV_CHIP_REVISION_6A_PRODUCTION 0u\r
 #define CYDEV_CHIP_REVISION_FM3_PRODUCTION 0u\r
 #define CYDEV_CHIP_REVISION_FM4_PRODUCTION 0u\r
 #define CYDEV_CHIP_REVISION_PDL_FM0P_TYPE1_PRODUCTION 0u\r
@@ -3157,7 +3141,7 @@
 #define CYDEV_ECC_ENABLE 0\r
 #define CYDEV_HEAP_SIZE 0x0400\r
 #define CYDEV_INSTRUCT_CACHE_ENABLED 1\r
-#define CYDEV_INTR_RISING 0x0000007Eu\r
+#define CYDEV_INTR_RISING 0x0000007Fu\r
 #define CYDEV_IS_EXPORTING_CODE 0\r
 #define CYDEV_IS_IMPORTING_CODE 0\r
 #define CYDEV_PROJ_TYPE 2\r

diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c
index 3b157aa787c094fbadbe3702444542bd3c3b0ef6..5800f1e77a4d8e571287d6a28bd861496fbd53ef 100755 (executable)
--- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c
+++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c
@@ -1,7 +1,8 @@
+\r
 /*******************************************************************************\r
 * File Name: cyfitter_cfg.c\r
 * \r
-* PSoC Creator  4.0 Update 1\r
+* PSoC Creator  4.1\r
 *\r
 * Description:\r
 * This file contains device initialization code.\r
@@ -9,7 +10,7 @@
 * This file is automatically generated by PSoC Creator.\r
 *\r
 ********************************************************************************\r
-* Copyright (c) 2007-2016 Cypress Semiconductor.  All rights reserved.\r
+* Copyright (c) 2007-2017 Cypress Semiconductor.  All rights reserved.\r
 * You may use this file only in accordance with the license, terms, conditions, \r
 * disclaimers, and limitations in the end user license agreement accompanying \r
 * the software package with which this file was provided.\r
@@ -55,6 +56,19 @@
     #error Unsupported toolchain\r
 #endif\r
 \r
+#ifndef CYCODE\r
+    #define CYCODE\r
+#endif\r
+#ifndef CYDATA\r
+    #define CYDATA\r
+#endif\r
+#ifndef CYFAR\r
+    #define CYFAR\r
+#endif\r
+#ifndef CYXDATA\r
+    #define CYXDATA\r
+#endif\r
+\r
 \r
 CY_CFG_UNUSED\r
 static void CYMEMZERO(void *s, size_t n);\r
@@ -86,6 +100,7 @@ static void CYCONFIGCPYCODE(void *dest, const void *src, size_t n)
 #define CYCLOCKSTART_XTAL_ERROR  1u\r
 #define CYCLOCKSTART_32KHZ_ERROR 2u\r
 #define CYCLOCKSTART_PLL_ERROR   3u\r
+#define CYCLOCKSTART_FLL_ERROR   4u\r
 \r
 \r
 #ifdef CY_NEED_CYCLOCKSTARTUPERROR\r
@@ -109,17 +124,21 @@ static void CyClockStartupError(uint8 errorCode);
 CY_CFG_UNUSED\r
 static void CyClockStartupError(uint8 errorCode)\r
 {\r
-    /* To remove the compiler warning if errorCode not used.                */\r
+    /* To remove the compiler warning if errorCode not used. */\r
+#if defined(CY_PSOC3) && (CY_PSOC3)\r
     errorCode = errorCode;\r
+#else\r
+    (void)errorCode;\r
+#endif /* CY_PSOC3 */\r
 \r
     /* If we have a clock startup error (bad MHz crystal, PLL lock, etc.),  */\r
     /* we will end up here to allow the customer to implement something to  */\r
     /* deal with the clock condition.                                       */\r
 \r
 #ifdef CY_CFG_CLOCK_STARTUP_ERROR_CALLBACK\r
-       CY_CFG_Clock_Startup_ErrorCallback();\r
+    CY_CFG_Clock_Startup_ErrorCallback();\r
 #else\r
-       /*  If not using CY_CFG_CLOCK_STARTUP_ERROR_CALLBACK, place your clock startup code here. */\r
+    /*  If not using CY_CFG_CLOCK_STARTUP_ERROR_CALLBACK, place your clock startup code here. */\r
     /* `#START CyClockStartupError` */\r
 \r
     /* If we have a clock startup error (bad MHz crystal, PLL lock, etc.),  */\r
@@ -128,10 +147,8 @@ static void CyClockStartupError(uint8 errorCode)
 \r
     /* `#END` */\r
 \r
-    /* If nothing else, stop here since the clocks have not started         */\r
-    /* correctly.                                                           */\r
     while(1) {}\r
-#endif /* CY_CFG_CLOCK_STARTUP_ERROR_CALLBACK */ \r
+#endif /* CY_CFG_CLOCK_STARTUP_ERROR_CALLBACK */\r
 }\r
 #endif\r
 \r
@@ -170,7 +187,7 @@ static void cfg_write_bytes32(const uint32 addr_table[], const cy_cfg_addrvalue_
                baseAddr &= 0xFFFFFF00u;\r
                while (count != 0u)\r
                {\r
-                       CY_SET_XTND_REG8((void CYFAR *)(baseAddr + data_table[j].offset), data_table[j].value);\r
+                       CY_SET_REG8((void *)(baseAddr + data_table[j].offset), data_table[j].value);\r
                        j++;\r
                        count--;\r
                }\r
@@ -205,8 +222,8 @@ static void ClockSetup(void)
        CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_DCFG0_CFG0 + 0x2u), 0x58u);\r
        CY_SET_XTND_REG16((void CYFAR *)(CYREG_CLKDIST_DCFG1_CFG0), 0x0001u);\r
        CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_DCFG1_CFG0 + 0x2u), 0x18u);\r
-       CY_SET_XTND_REG16((void CYFAR *)(CYREG_CLKDIST_DCFG2_CFG0), 0x0017u);\r
-       CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_DCFG2_CFG0 + 0x2u), 0x19u);\r
+       CY_SET_XTND_REG16((void CYFAR *)(CYREG_CLKDIST_DCFG2_CFG0), 0x0031u);\r
+       CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_DCFG2_CFG0 + 0x2u), 0x18u);\r
 \r
        /* Configure ILO based on settings from Clock DWR */\r
        CY_SET_XTND_REG8((void CYFAR *)(CYREG_SLOWCLK_ILO_CR0), 0x06u);\r
@@ -305,7 +322,7 @@ void SetAnalogRoutingPumps(uint8 enabled)
        CY_SET_XTND_REG8((void CYFAR *)CYREG_PUMP_CR0, regValue);\r
 }\r
 \r
-#define CY_AMUX_UNUSED CYREG_BOOST_SR\r
+\r
 \r
 \r
 /*******************************************************************************\r
@@ -317,7 +334,7 @@ void SetAnalogRoutingPumps(uint8 enabled)
 *  settings.  This includes settings from the Design Wide Resources (DWR) such\r
 *  as Clocks and Pins as well as any component configuration that is necessary.\r
 *\r
-* Parameters:  \r
+* Parameters:\r
 *   void\r
 *\r
 * Return:\r
@@ -402,38 +419,38 @@ void cyfitter_cfg(void)
                        0x40006401u, /* Base address: 0x40006400 Count: 1 */\r
                        0x40006501u, /* Base address: 0x40006500 Count: 1 */\r
                        0x4001004Au, /* Base address: 0x40010000 Count: 74 */\r
-                       0x40010142u, /* Base address: 0x40010100 Count: 66 */\r
+                       0x4001013Bu, /* Base address: 0x40010100 Count: 59 */\r
                        0x40010248u, /* Base address: 0x40010200 Count: 72 */\r
-                       0x40010355u, /* Base address: 0x40010300 Count: 85 */\r
+                       0x40010353u, /* Base address: 0x40010300 Count: 83 */\r
                        0x4001045Du, /* Base address: 0x40010400 Count: 93 */\r
-                       0x4001055Au, /* Base address: 0x40010500 Count: 90 */\r
+                       0x40010560u, /* Base address: 0x40010500 Count: 96 */\r
                        0x40010657u, /* Base address: 0x40010600 Count: 87 */\r
-                       0x4001075Au, /* Base address: 0x40010700 Count: 90 */\r
+                       0x40010750u, /* Base address: 0x40010700 Count: 80 */\r
                        0x40010851u, /* Base address: 0x40010800 Count: 81 */\r
-                       0x40010953u, /* Base address: 0x40010900 Count: 83 */\r
+                       0x40010955u, /* Base address: 0x40010900 Count: 85 */\r
                        0x40010A4Au, /* Base address: 0x40010A00 Count: 74 */\r
-                       0x40010B45u, /* Base address: 0x40010B00 Count: 69 */\r
-                       0x40010D13u, /* Base address: 0x40010D00 Count: 19 */\r
+                       0x40010B47u, /* Base address: 0x40010B00 Count: 71 */\r
+                       0x40010D11u, /* Base address: 0x40010D00 Count: 17 */\r
                        0x40010F06u, /* Base address: 0x40010F00 Count: 6 */\r
                        0x4001141Au, /* Base address: 0x40011400 Count: 26 */\r
-                       0x40011550u, /* Base address: 0x40011500 Count: 80 */\r
-                       0x4001164Fu, /* Base address: 0x40011600 Count: 79 */\r
-                       0x40011758u, /* Base address: 0x40011700 Count: 88 */\r
+                       0x40011557u, /* Base address: 0x40011500 Count: 87 */\r
+                       0x4001164Eu, /* Base address: 0x40011600 Count: 78 */\r
+                       0x40011751u, /* Base address: 0x40011700 Count: 81 */\r
                        0x40011849u, /* Base address: 0x40011800 Count: 73 */\r
-                       0x40011955u, /* Base address: 0x40011900 Count: 85 */\r
+                       0x40011950u, /* Base address: 0x40011900 Count: 80 */\r
                        0x40011B09u, /* Base address: 0x40011B00 Count: 9 */\r
-                       0x4001401Cu, /* Base address: 0x40014000 Count: 28 */\r
-                       0x4001411Du, /* Base address: 0x40014100 Count: 29 */\r
+                       0x4001401Bu, /* Base address: 0x40014000 Count: 27 */\r
+                       0x40014120u, /* Base address: 0x40014100 Count: 32 */\r
                        0x40014214u, /* Base address: 0x40014200 Count: 20 */\r
-                       0x40014309u, /* Base address: 0x40014300 Count: 9 */\r
+                       0x4001430Cu, /* Base address: 0x40014300 Count: 12 */\r
                        0x4001440Du, /* Base address: 0x40014400 Count: 13 */\r
-                       0x40014515u, /* Base address: 0x40014500 Count: 21 */\r
-                       0x40014613u, /* Base address: 0x40014600 Count: 19 */\r
-                       0x40014711u, /* Base address: 0x40014700 Count: 17 */\r
-                       0x40014808u, /* Base address: 0x40014800 Count: 8 */\r
-                       0x4001490Au, /* Base address: 0x40014900 Count: 10 */\r
-                       0x40014C06u, /* Base address: 0x40014C00 Count: 6 */\r
-                       0x40014D06u, /* Base address: 0x40014D00 Count: 6 */\r
+                       0x40014517u, /* Base address: 0x40014500 Count: 23 */\r
+                       0x40014614u, /* Base address: 0x40014600 Count: 20 */\r
+                       0x40014713u, /* Base address: 0x40014700 Count: 19 */\r
+                       0x4001480Au, /* Base address: 0x40014800 Count: 10 */\r
+                       0x4001490Bu, /* Base address: 0x40014900 Count: 11 */\r
+                       0x40014C05u, /* Base address: 0x40014C00 Count: 5 */\r
+                       0x40014D05u, /* Base address: 0x40014D00 Count: 5 */\r
                        0x40015006u, /* Base address: 0x40015000 Count: 6 */\r
                        0x40015104u, /* Base address: 0x40015100 Count: 4 */\r
                };\r
@@ -448,10 +465,10 @@ void cyfitter_cfg(void)
                        {0x19u, 0x04u},\r
                        {0x1Cu, 0x71u},\r
                        {0x20u, 0xA0u},\r
-                       {0x21u, 0x98u},\r
+                       {0x21u, 0x90u},\r
                        {0x2Cu, 0x0Eu},\r
-                       {0x30u, 0x05u},\r
-                       {0x31u, 0x09u},\r
+                       {0x30u, 0x09u},\r
+                       {0x31u, 0x05u},\r
                        {0x34u, 0x80u},\r
                        {0x7Cu, 0x40u},\r
                        {0x20u, 0x01u},\r
@@ -464,19 +481,19 @@ void cyfitter_cfg(void)
                        {0x09u, 0x55u},\r
                        {0x0Au, 0x24u},\r
                        {0x0Bu, 0xAAu},\r
-                       {0x0Fu, 0xFFu},\r
-                       {0x10u, 0x24u},\r
                        {0x11u, 0x0Fu},\r
-                       {0x12u, 0x09u},\r
                        {0x13u, 0xF0u},\r
                        {0x17u, 0xFFu},\r
                        {0x18u, 0x24u},\r
                        {0x19u, 0xFFu},\r
                        {0x1Au, 0x12u},\r
                        {0x22u, 0x20u},\r
+                       {0x23u, 0xFFu},\r
                        {0x25u, 0x33u},\r
                        {0x26u, 0x04u},\r
                        {0x27u, 0xCCu},\r
+                       {0x28u, 0x24u},\r
+                       {0x2Au, 0x09u},\r
                        {0x2Bu, 0xFFu},\r
                        {0x30u, 0x07u},\r
                        {0x33u, 0xFFu},\r
@@ -487,10 +504,10 @@ void cyfitter_cfg(void)
                        {0x40u, 0x32u},\r
                        {0x41u, 0x06u},\r
                        {0x42u, 0x10u},\r
-                       {0x45u, 0x0Du},\r
-                       {0x46u, 0x2Eu},\r
-                       {0x47u, 0xCFu},\r
-                       {0x48u, 0x3Du},\r
+                       {0x45u, 0xCEu},\r
+                       {0x46u, 0x2Du},\r
+                       {0x47u, 0x0Fu},\r
+                       {0x48u, 0x1Fu},\r
                        {0x49u, 0xFFu},\r
                        {0x4Au, 0xFFu},\r
                        {0x4Bu, 0xFFu},\r
@@ -511,7 +528,6 @@ void cyfitter_cfg(void)
                        {0x6Eu, 0x08u},\r
                        {0x81u, 0x33u},\r
                        {0x83u, 0xCCu},\r
-                       {0x85u, 0xFFu},\r
                        {0x8Bu, 0xFFu},\r
                        {0x8Du, 0x0Fu},\r
                        {0x8Fu, 0xF0u},\r
@@ -519,7 +535,8 @@ void cyfitter_cfg(void)
                        {0x93u, 0xAAu},\r
                        {0x97u, 0xFFu},\r
                        {0x99u, 0xFFu},\r
-                       {0xABu, 0xFFu},\r
+                       {0xA3u, 0xFFu},\r
+                       {0xA9u, 0xFFu},\r
                        {0xADu, 0x96u},\r
                        {0xAFu, 0x69u},\r
                        {0xB7u, 0xFFu},\r
@@ -531,87 +548,80 @@ void cyfitter_cfg(void)
                        {0xDDu, 0x10u},\r
                        {0xDFu, 0x01u},\r
                        {0x00u, 0x04u},\r
-                       {0x01u, 0x02u},\r
+                       {0x01u, 0x0Au},\r
                        {0x03u, 0x04u},\r
-                       {0x09u, 0x22u},\r
+                       {0x09u, 0x20u},\r
                        {0x10u, 0x80u},\r
-                       {0x13u, 0x08u},\r
+                       {0x13u, 0x18u},\r
                        {0x18u, 0x04u},\r
                        {0x19u, 0x02u},\r
                        {0x23u, 0x22u},\r
                        {0x25u, 0x40u},\r
                        {0x29u, 0x20u},\r
-                       {0x2Au, 0x04u},\r
-                       {0x2Du, 0x60u},\r
+                       {0x2Au, 0x06u},\r
+                       {0x2Du, 0x40u},\r
+                       {0x2Eu, 0x02u},\r
+                       {0x2Fu, 0x04u},\r
                        {0x31u, 0x10u},\r
                        {0x33u, 0x05u},\r
                        {0x34u, 0x02u},\r
                        {0x35u, 0x10u},\r
                        {0x37u, 0x04u},\r
-                       {0x3Au, 0x99u},\r
-                       {0x3Bu, 0x80u},\r
-                       {0x3Cu, 0x20u},\r
+                       {0x3Au, 0x11u},\r
+                       {0x3Bu, 0x08u},\r
                        {0x3Du, 0x80u},\r
-                       {0x3Eu, 0x08u},\r
-                       {0x3Fu, 0x02u},\r
+                       {0x3Fu, 0x12u},\r
                        {0x41u, 0x20u},\r
-                       {0x42u, 0x08u},\r
                        {0x43u, 0x84u},\r
-                       {0x49u, 0x20u},\r
+                       {0x48u, 0x40u},\r
+                       {0x49u, 0x24u},\r
                        {0x4Au, 0x04u},\r
-                       {0x4Bu, 0x08u},\r
-                       {0x51u, 0x44u},\r
-                       {0x52u, 0x02u},\r
-                       {0x53u, 0x10u},\r
+                       {0x4Bu, 0x10u},\r
+                       {0x51u, 0x04u},\r
+                       {0x53u, 0x50u},\r
                        {0x5Au, 0xAAu},\r
                        {0x5Eu, 0x80u},\r
                        {0x61u, 0x08u},\r
                        {0x62u, 0x40u},\r
                        {0x63u, 0x44u},\r
-                       {0x69u, 0x24u},\r
-                       {0x6Au, 0x40u},\r
+                       {0x69u, 0xA4u},\r
                        {0x6Bu, 0x40u},\r
                        {0x70u, 0x8Au},\r
                        {0x73u, 0x08u},\r
-                       {0x80u, 0x04u},\r
-                       {0x81u, 0x40u},\r
+                       {0x81u, 0x42u},\r
                        {0x83u, 0x40u},\r
-                       {0x86u, 0x40u},\r
-                       {0x87u, 0x10u},\r
-                       {0x88u, 0x10u},\r
                        {0x89u, 0x10u},\r
-                       {0x8Bu, 0x40u},\r
+                       {0x8Du, 0x08u},\r
                        {0x8Fu, 0x40u},\r
                        {0xC0u, 0x0Eu},\r
-                       {0xC2u, 0x0Au},\r
-                       {0xC4u, 0x0Cu},\r
-                       {0xCAu, 0x36u},\r
+                       {0xC2u, 0x02u},\r
+                       {0xC4u, 0x0Eu},\r
+                       {0xCAu, 0xB7u},\r
                        {0xCCu, 0xE7u},\r
-                       {0xCEu, 0xFFu},\r
+                       {0xCEu, 0xB7u},\r
                        {0xD0u, 0x0Eu},\r
                        {0xD2u, 0x04u},\r
                        {0xD6u, 0x1Fu},\r
                        {0xD8u, 0x0Fu},\r
-                       {0xE0u, 0x04u},\r
-                       {0xE2u, 0x10u},\r
-                       {0xE4u, 0x01u},\r
-                       {0xE6u, 0x44u},\r
+                       {0xE0u, 0x01u},\r
+                       {0xE4u, 0x05u},\r
+                       {0xE6u, 0x40u},\r
                        {0x01u, 0x40u},\r
                        {0x03u, 0x80u},\r
                        {0x05u, 0x01u},\r
-                       {0x0Du, 0x0Bu},\r
-                       {0x0Fu, 0xF4u},\r
-                       {0x11u, 0x06u},\r
-                       {0x15u, 0x11u},\r
-                       {0x17u, 0xECu},\r
+                       {0x09u, 0x11u},\r
+                       {0x0Bu, 0xECu},\r
+                       {0x0Du, 0x06u},\r
+                       {0x13u, 0xFFu},\r
+                       {0x15u, 0x0Bu},\r
+                       {0x17u, 0xF4u},\r
                        {0x19u, 0xE0u},\r
-                       {0x21u, 0xCAu},\r
-                       {0x22u, 0x01u},\r
-                       {0x23u, 0x15u},\r
+                       {0x23u, 0x10u},\r
                        {0x25u, 0x40u},\r
                        {0x27u, 0x80u},\r
-                       {0x2Bu, 0x10u},\r
-                       {0x2Fu, 0xFFu},\r
+                       {0x29u, 0xCAu},\r
+                       {0x2Bu, 0x15u},\r
+                       {0x2Eu, 0x01u},\r
                        {0x32u, 0x01u},\r
                        {0x33u, 0xC0u},\r
                        {0x35u, 0x3Fu},\r
@@ -624,14 +634,14 @@ void cyfitter_cfg(void)
                        {0x81u, 0x03u},\r
                        {0x82u, 0x02u},\r
                        {0x83u, 0x0Cu},\r
-                       {0x85u, 0x02u},\r
+                       {0x85u, 0x40u},\r
                        {0x86u, 0x0Du},\r
+                       {0x87u, 0x80u},\r
                        {0x8Au, 0x90u},\r
                        {0x8Bu, 0x01u},\r
-                       {0x8Du, 0xF4u},\r
+                       {0x8Du, 0x02u},\r
                        {0x8Eu, 0x60u},\r
                        {0x90u, 0x01u},\r
-                       {0x91u, 0x08u},\r
                        {0x92u, 0x02u},\r
                        {0x93u, 0xF7u},\r
                        {0x95u, 0x0Bu},\r
@@ -640,19 +650,19 @@ void cyfitter_cfg(void)
                        {0x99u, 0x40u},\r
                        {0x9Au, 0x48u},\r
                        {0x9Bu, 0x80u},\r
-                       {0x9Cu, 0x90u},\r
-                       {0x9Du, 0xFDu},\r
-                       {0x9Eu, 0x24u},\r
-                       {0x9Fu, 0x02u},\r
+                       {0x9Du, 0x08u},\r
+                       {0x9Fu, 0xF7u},\r
+                       {0xA0u, 0x90u},\r
                        {0xA1u, 0x10u},\r
+                       {0xA2u, 0x24u},\r
                        {0xA3u, 0x20u},\r
                        {0xA5u, 0x10u},\r
                        {0xA7u, 0x20u},\r
-                       {0xA9u, 0x40u},\r
+                       {0xA9u, 0xF4u},\r
                        {0xAAu, 0x80u},\r
-                       {0xABu, 0x80u},\r
+                       {0xADu, 0xFDu},\r
                        {0xAEu, 0x10u},\r
-                       {0xAFu, 0xF7u},\r
+                       {0xAFu, 0x02u},\r
                        {0xB0u, 0xE0u},\r
                        {0xB3u, 0x30u},\r
                        {0xB4u, 0x1Cu},\r
@@ -670,128 +680,126 @@ void cyfitter_cfg(void)
                        {0xDFu, 0x01u},\r
                        {0x00u, 0x02u},\r
                        {0x03u, 0x26u},\r
-                       {0x05u, 0x02u},\r
-                       {0x06u, 0x80u},\r
-                       {0x08u, 0x81u},\r
-                       {0x09u, 0x10u},\r
+                       {0x08u, 0x01u},\r
+                       {0x09u, 0x20u},\r
+                       {0x0Bu, 0x08u},\r
                        {0x10u, 0x0Au},\r
-                       {0x16u, 0x40u},\r
+                       {0x12u, 0x80u},\r
+                       {0x15u, 0x80u},\r
+                       {0x1Au, 0x04u},\r
                        {0x1Bu, 0x62u},\r
                        {0x1Eu, 0x20u},\r
+                       {0x20u, 0x04u},\r
                        {0x22u, 0x14u},\r
                        {0x23u, 0x01u},\r
-                       {0x25u, 0x38u},\r
-                       {0x2Au, 0x91u},\r
+                       {0x25u, 0x28u},\r
+                       {0x29u, 0x50u},\r
+                       {0x2Au, 0x01u},\r
                        {0x2Bu, 0x10u},\r
-                       {0x2Cu, 0x90u},\r
-                       {0x2Eu, 0x80u},\r
-                       {0x2Fu, 0x04u},\r
-                       {0x30u, 0x80u},\r
-                       {0x31u, 0x02u},\r
-                       {0x32u, 0x10u},\r
+                       {0x2Cu, 0x10u},\r
+                       {0x2Fu, 0x44u},\r
+                       {0x32u, 0xA2u},\r
                        {0x33u, 0x04u},\r
-                       {0x35u, 0x10u},\r
-                       {0x36u, 0x02u},\r
-                       {0x37u, 0x04u},\r
-                       {0x38u, 0x80u},\r
-                       {0x3Bu, 0x29u},\r
-                       {0x3Du, 0x08u},\r
-                       {0x3Eu, 0x40u},\r
+                       {0x35u, 0x12u},\r
+                       {0x36u, 0x06u},\r
+                       {0x38u, 0x04u},\r
+                       {0x3Bu, 0xA1u},\r
+                       {0x3Cu, 0x80u},\r
+                       {0x3Du, 0x28u},\r
+                       {0x3Eu, 0x80u},\r
                        {0x3Fu, 0x02u},\r
-                       {0x40u, 0x80u},\r
-                       {0x41u, 0x02u},\r
-                       {0x42u, 0x40u},\r
                        {0x44u, 0x10u},\r
                        {0x45u, 0x08u},\r
                        {0x4Eu, 0x04u},\r
                        {0x4Fu, 0x20u},\r
-                       {0x58u, 0x44u},\r
+                       {0x58u, 0x04u},\r
                        {0x5Au, 0x11u},\r
+                       {0x5Bu, 0x40u},\r
                        {0x5Du, 0x9Au},\r
                        {0x60u, 0x02u},\r
                        {0x61u, 0x80u},\r
-                       {0x62u, 0x15u},\r
+                       {0x62u, 0x35u},\r
                        {0x67u, 0x02u},\r
                        {0x81u, 0x08u},\r
                        {0x83u, 0x01u},\r
                        {0x84u, 0x01u},\r
                        {0x85u, 0x80u},\r
-                       {0x88u, 0x80u},\r
+                       {0x86u, 0x04u},\r
                        {0x89u, 0x20u},\r
-                       {0x8Fu, 0x20u},\r
-                       {0x91u, 0x8Cu},\r
-                       {0x93u, 0x28u},\r
+                       {0x8Bu, 0x10u},\r
+                       {0x8Fu, 0x42u},\r
+                       {0x91u, 0x0Cu},\r
+                       {0x93u, 0xA0u},\r
                        {0x95u, 0x40u},\r
                        {0x96u, 0xAAu},\r
-                       {0x97u, 0x54u},\r
+                       {0x97u, 0x4Cu},\r
                        {0x98u, 0x04u},\r
-                       {0x9Au, 0x80u},\r
+                       {0x99u, 0x04u},\r
                        {0x9Bu, 0x20u},\r
                        {0x9Cu, 0x02u},\r
                        {0x9Du, 0x10u},\r
-                       {0x9Eu, 0x15u},\r
+                       {0x9Eu, 0x57u},\r
                        {0x9Fu, 0x04u},\r
-                       {0xA0u, 0x0Au},\r
+                       {0xA0u, 0x4Au},\r
                        {0xA1u, 0x40u},\r
-                       {0xA2u, 0x02u},\r
-                       {0xA4u, 0x10u},\r
-                       {0xA5u, 0x2Au},\r
+                       {0xA5u, 0x28u},\r
                        {0xA6u, 0x44u},\r
                        {0xA7u, 0xC1u},\r
                        {0xADu, 0x04u},\r
                        {0xAFu, 0x23u},\r
                        {0xB0u, 0x04u},\r
-                       {0xB5u, 0x02u},\r
-                       {0xB6u, 0x40u},\r
+                       {0xB5u, 0x04u},\r
                        {0xC0u, 0x0Fu},\r
-                       {0xC2u, 0x0Bu},\r
-                       {0xC4u, 0x13u},\r
-                       {0xCAu, 0xFFu},\r
+                       {0xC2u, 0x0Au},\r
+                       {0xC4u, 0x8Bu},\r
+                       {0xCAu, 0xEFu},\r
                        {0xCCu, 0xEFu},\r
-                       {0xCEu, 0xDFu},\r
+                       {0xCEu, 0xFFu},\r
                        {0xD6u, 0xFFu},\r
                        {0xD8u, 0x1Fu},\r
+                       {0xE0u, 0x02u},\r
                        {0xE2u, 0x08u},\r
-                       {0xE6u, 0x0Du},\r
+                       {0xE6u, 0x0Eu},\r
+                       {0xEAu, 0x50u},\r
                        {0x00u, 0x04u},\r
-                       {0x01u, 0x04u},\r
+                       {0x01u, 0x10u},\r
                        {0x02u, 0x08u},\r
-                       {0x03u, 0x08u},\r
+                       {0x03u, 0x20u},\r
                        {0x04u, 0x08u},\r
                        {0x05u, 0x10u},\r
                        {0x06u, 0x37u},\r
                        {0x07u, 0x20u},\r
-                       {0x09u, 0x01u},\r
-                       {0x0Au, 0x40u},\r
-                       {0x0Bu, 0x02u},\r
-                       {0x0Du, 0x40u},\r
-                       {0x0Fu, 0x3Fu},\r
+                       {0x08u, 0x33u},\r
+                       {0x09u, 0x7Fu},\r
+                       {0x0Au, 0x04u},\r
+                       {0x0Eu, 0x37u},\r
+                       {0x0Fu, 0x40u},\r
                        {0x10u, 0x10u},\r
+                       {0x11u, 0x04u},\r
                        {0x12u, 0x20u},\r
-                       {0x13u, 0x40u},\r
-                       {0x14u, 0x01u},\r
-                       {0x15u, 0x40u},\r
-                       {0x16u, 0x02u},\r
-                       {0x17u, 0x3Fu},\r
+                       {0x13u, 0x08u},\r
+                       {0x14u, 0x08u},\r
+                       {0x15u, 0x01u},\r
+                       {0x16u, 0x37u},\r
+                       {0x17u, 0x02u},\r
                        {0x18u, 0x33u},\r
-                       {0x19u, 0x7Fu},\r
+                       {0x19u, 0x3Fu},\r
                        {0x1Au, 0x04u},\r
                        {0x1Cu, 0x01u},\r
                        {0x1Du, 0x01u},\r
                        {0x1Eu, 0x02u},\r
                        {0x1Fu, 0x02u},\r
-                       {0x20u, 0x33u},\r
-                       {0x21u, 0x10u},\r
-                       {0x22u, 0x04u},\r
-                       {0x23u, 0x20u},\r
-                       {0x25u, 0x04u},\r
-                       {0x26u, 0x37u},\r
-                       {0x27u, 0x08u},\r
+                       {0x21u, 0x04u},\r
+                       {0x23u, 0x08u},\r
+                       {0x25u, 0x40u},\r
+                       {0x26u, 0x40u},\r
+                       {0x27u, 0x3Fu},\r
                        {0x28u, 0x10u},\r
-                       {0x29u, 0x3Fu},\r
+                       {0x29u, 0x40u},\r
                        {0x2Au, 0x20u},\r
-                       {0x2Cu, 0x08u},\r
-                       {0x2Eu, 0x37u},\r
+                       {0x2Bu, 0x3Fu},\r
+                       {0x2Cu, 0x01u},\r
+                       {0x2Eu, 0x02u},\r
                        {0x2Fu, 0x3Fu},\r
                        {0x30u, 0x30u},\r
                        {0x31u, 0x0Cu},\r
@@ -812,182 +820,189 @@ void cyfitter_cfg(void)
                        {0x5Du, 0x90u},\r
                        {0x5Fu, 0x01u},\r
                        {0x80u, 0x01u},\r
-                       {0x81u, 0x81u},\r
                        {0x82u, 0x02u},\r
-                       {0x83u, 0x2Eu},\r
+                       {0x83u, 0x60u},\r
                        {0x87u, 0x80u},\r
-                       {0x8Bu, 0x1Fu},\r
-                       {0x93u, 0x60u},\r
+                       {0x89u, 0x03u},\r
+                       {0x8Bu, 0x94u},\r
+                       {0x93u, 0x1Fu},\r
                        {0x94u, 0x02u},\r
-                       {0x95u, 0x03u},\r
+                       {0x95u, 0x81u},\r
                        {0x96u, 0x01u},\r
-                       {0x97u, 0x94u},\r
+                       {0x97u, 0x2Eu},\r
                        {0x98u, 0x02u},\r
+                       {0x99u, 0x04u},\r
                        {0x9Au, 0x11u},\r
-                       {0x9Bu, 0x01u},\r
                        {0x9Cu, 0x02u},\r
                        {0x9Eu, 0x09u},\r
                        {0xA0u, 0x02u},\r
-                       {0xA1u, 0x98u},\r
+                       {0xA1u, 0x02u},\r
                        {0xA2u, 0x05u},\r
-                       {0xA3u, 0x43u},\r
                        {0xA7u, 0x08u},\r
-                       {0xA9u, 0x02u},\r
-                       {0xADu, 0x04u},\r
+                       {0xA9u, 0x98u},\r
+                       {0xABu, 0x43u},\r
+                       {0xAFu, 0x01u},\r
                        {0xB0u, 0x03u},\r
+                       {0xB1u, 0xE0u},\r
                        {0xB2u, 0x10u},\r
                        {0xB4u, 0x08u},\r
                        {0xB5u, 0x1Fu},\r
                        {0xB6u, 0x04u},\r
-                       {0xB7u, 0xE0u},\r
                        {0xBAu, 0x02u},\r
                        {0xD8u, 0x04u},\r
                        {0xD9u, 0x04u},\r
                        {0xDBu, 0x04u},\r
                        {0xDCu, 0x11u},\r
                        {0xDFu, 0x01u},\r
-                       {0x02u, 0x28u},\r
+                       {0x01u, 0x20u},\r
+                       {0x02u, 0x22u},\r
                        {0x03u, 0x80u},\r
                        {0x05u, 0x01u},\r
+                       {0x08u, 0x08u},\r
                        {0x09u, 0x80u},\r
-                       {0x0Au, 0xA8u},\r
-                       {0x0Cu, 0x02u},\r
-                       {0x0Du, 0x0Au},\r
+                       {0x0Au, 0x80u},\r
+                       {0x0Bu, 0x08u},\r
+                       {0x0Du, 0x08u},\r
                        {0x0Eu, 0x06u},\r
-                       {0x10u, 0x82u},\r
+                       {0x10u, 0x10u},\r
                        {0x12u, 0x04u},\r
-                       {0x13u, 0x08u},\r
+                       {0x13u, 0x40u},\r
                        {0x14u, 0x20u},\r
                        {0x15u, 0x08u},\r
-                       {0x17u, 0x02u},\r
-                       {0x1Au, 0xA0u},\r
-                       {0x1Bu, 0xA8u},\r
+                       {0x16u, 0x40u},\r
+                       {0x18u, 0x04u},\r
+                       {0x1Au, 0x80u},\r
+                       {0x1Bu, 0x88u},\r
                        {0x1Cu, 0x80u},\r
                        {0x1Du, 0x09u},\r
                        {0x1Eu, 0x06u},\r
                        {0x1Fu, 0x01u},\r
-                       {0x21u, 0x01u},\r
-                       {0x22u, 0x81u},\r
-                       {0x23u, 0x14u},\r
+                       {0x22u, 0x09u},\r
+                       {0x23u, 0x05u},\r
+                       {0x25u, 0x11u},\r
                        {0x26u, 0x20u},\r
-                       {0x27u, 0x05u},\r
-                       {0x28u, 0x10u},\r
-                       {0x29u, 0x92u},\r
-                       {0x2Cu, 0x80u},\r
-                       {0x2Eu, 0x40u},\r
-                       {0x2Fu, 0x14u},\r
-                       {0x30u, 0x40u},\r
-                       {0x31u, 0x20u},\r
-                       {0x32u, 0x02u},\r
-                       {0x33u, 0x06u},\r
-                       {0x37u, 0x15u},\r
+                       {0x27u, 0x04u},\r
+                       {0x28u, 0x8Au},\r
+                       {0x2Au, 0x08u},\r
+                       {0x2Cu, 0x02u},\r
+                       {0x2Du, 0x02u},\r
+                       {0x2Fu, 0x54u},\r
+                       {0x31u, 0x10u},\r
+                       {0x32u, 0x89u},\r
+                       {0x34u, 0x02u},\r
+                       {0x35u, 0x10u},\r
+                       {0x36u, 0x06u},\r
                        {0x39u, 0x02u},\r
                        {0x3Au, 0x80u},\r
                        {0x3Bu, 0x14u},\r
-                       {0x3Cu, 0x20u},\r
-                       {0x3Du, 0x06u},\r
-                       {0x45u, 0x01u},\r
-                       {0x46u, 0x80u},\r
-                       {0x5Bu, 0x40u},\r
+                       {0x3Du, 0x27u},\r
+                       {0x42u, 0x80u},\r
+                       {0x43u, 0x02u},\r
+                       {0x44u, 0x02u},\r
+                       {0x45u, 0x10u},\r
+                       {0x46u, 0x0Au},\r
+                       {0x59u, 0x80u},\r
                        {0x63u, 0x02u},\r
                        {0x6Cu, 0x09u},\r
                        {0x6Du, 0x08u},\r
-                       {0x6Fu, 0x10u},\r
-                       {0x81u, 0x02u},\r
                        {0x83u, 0x04u},\r
-                       {0x84u, 0x50u},\r
-                       {0x88u, 0x08u},\r
+                       {0x84u, 0x80u},\r
+                       {0x85u, 0x01u},\r
+                       {0x86u, 0x80u},\r
+                       {0x87u, 0x48u},\r
+                       {0x89u, 0x81u},\r
+                       {0x8Cu, 0x08u},\r
                        {0x8Du, 0x40u},\r
                        {0x8Eu, 0x01u},\r
-                       {0x91u, 0x8Cu},\r
-                       {0x93u, 0x28u},\r
-                       {0x94u, 0x80u},\r
-                       {0x95u, 0x50u},\r
+                       {0x91u, 0x0Cu},\r
+                       {0x93u, 0xB8u},\r
+                       {0x95u, 0xC0u},\r
                        {0x96u, 0x82u},\r
-                       {0x97u, 0x16u},\r
-                       {0x9Au, 0x04u},\r
-                       {0x9Bu, 0x60u},\r
+                       {0x97u, 0x46u},\r
+                       {0x99u, 0x04u},\r
+                       {0x9Au, 0x84u},\r
+                       {0x9Bu, 0x20u},\r
                        {0x9Du, 0x10u},\r
-                       {0x9Eu, 0x40u},\r
+                       {0x9Eu, 0x02u},\r
                        {0x9Fu, 0x04u},\r
-                       {0xA0u, 0x80u},\r
-                       {0xA1u, 0xF0u},\r
-                       {0xA2u, 0x12u},\r
-                       {0xA4u, 0x10u},\r
-                       {0xA5u, 0x06u},\r
-                       {0xA6u, 0x44u},\r
-                       {0xA7u, 0x89u},\r
-                       {0xAAu, 0x10u},\r
-                       {0xABu, 0x40u},\r
-                       {0xACu, 0x41u},\r
-                       {0xAFu, 0x4Au},\r
+                       {0xA1u, 0xC0u},\r
+                       {0xA2u, 0x10u},\r
+                       {0xA5u, 0x14u},\r
+                       {0xA6u, 0x4Eu},\r
+                       {0xA7u, 0x81u},\r
+                       {0xAAu, 0x94u},\r
+                       {0xACu, 0x01u},\r
+                       {0xADu, 0x10u},\r
+                       {0xAEu, 0x48u},\r
+                       {0xB1u, 0x40u},\r
                        {0xB2u, 0x01u},\r
-                       {0xB5u, 0x04u},\r
-                       {0xC0u, 0x1Eu},\r
+                       {0xB3u, 0x04u},\r
+                       {0xC0u, 0x1Fu},\r
                        {0xC2u, 0xEFu},\r
-                       {0xC4u, 0x1Fu},\r
+                       {0xC4u, 0x17u},\r
                        {0xCAu, 0xFFu},\r
                        {0xCCu, 0xEFu},\r
                        {0xCEu, 0xEFu},\r
                        {0xD6u, 0x08u},\r
                        {0xD8u, 0x08u},\r
-                       {0xE0u, 0x01u},\r
-                       {0xE6u, 0x6Eu},\r
-                       {0xE8u, 0x08u},\r
+                       {0xE0u, 0x09u},\r
+                       {0xE2u, 0x10u},\r
+                       {0xE6u, 0x58u},\r
                        {0xEAu, 0x03u},\r
-                       {0xEEu, 0x4Du},\r
+                       {0xEEu, 0x08u},\r
                        {0x01u, 0x80u},\r
+                       {0x04u, 0xFFu},\r
                        {0x05u, 0x0Fu},\r
-                       {0x06u, 0xFFu},\r
-                       {0x08u, 0x60u},\r
-                       {0x09u, 0x20u},\r
-                       {0x0Au, 0x90u},\r
-                       {0x0Bu, 0x4Fu},\r
-                       {0x0Cu, 0x05u},\r
+                       {0x08u, 0x0Fu},\r
+                       {0x09u, 0x40u},\r
+                       {0x0Au, 0xF0u},\r
+                       {0x0Bu, 0x1Fu},\r
+                       {0x0Cu, 0x50u},\r
                        {0x0Du, 0x06u},\r
-                       {0x0Eu, 0x0Au},\r
+                       {0x0Eu, 0xA0u},\r
                        {0x0Fu, 0x09u},\r
-                       {0x10u, 0x50u},\r
                        {0x11u, 0x80u},\r
-                       {0x12u, 0xA0u},\r
+                       {0x12u, 0xFFu},\r
                        {0x14u, 0x30u},\r
-                       {0x15u, 0x40u},\r
+                       {0x15u, 0x10u},\r
                        {0x16u, 0xC0u},\r
-                       {0x17u, 0x1Fu},\r
+                       {0x17u, 0x2Fu},\r
                        {0x19u, 0x03u},\r
                        {0x1Au, 0xFFu},\r
                        {0x1Bu, 0x0Cu},\r
-                       {0x1Cu, 0xFFu},\r
+                       {0x1Cu, 0x03u},\r
+                       {0x1Eu, 0x0Cu},\r
                        {0x1Fu, 0x70u},\r
-                       {0x20u, 0x06u},\r
-                       {0x21u, 0x80u},\r
-                       {0x22u, 0x09u},\r
-                       {0x24u, 0x0Fu},\r
+                       {0x20u, 0x60u},\r
+                       {0x21u, 0x05u},\r
+                       {0x22u, 0x90u},\r
+                       {0x23u, 0x0Au},\r
+                       {0x24u, 0x05u},\r
                        {0x25u, 0x80u},\r
-                       {0x26u, 0xF0u},\r
-                       {0x28u, 0x03u},\r
-                       {0x29u, 0x05u},\r
-                       {0x2Au, 0x0Cu},\r
-                       {0x2Bu, 0x0Au},\r
-                       {0x2Du, 0x10u},\r
-                       {0x2Fu, 0x2Fu},\r
-                       {0x33u, 0x80u},\r
-                       {0x36u, 0xFFu},\r
+                       {0x26u, 0x0Au},\r
+                       {0x28u, 0x06u},\r
+                       {0x29u, 0x20u},\r
+                       {0x2Au, 0x09u},\r
+                       {0x2Bu, 0x4Fu},\r
+                       {0x2Du, 0x80u},\r
+                       {0x30u, 0xFFu},\r
+                       {0x35u, 0x80u},\r
                        {0x37u, 0x7Fu},\r
-                       {0x39u, 0x08u},\r
-                       {0x3Eu, 0x40u},\r
-                       {0x3Fu, 0x04u},\r
+                       {0x39u, 0x20u},\r
+                       {0x3Eu, 0x01u},\r
+                       {0x3Fu, 0x10u},\r
                        {0x58u, 0x04u},\r
                        {0x59u, 0x04u},\r
                        {0x5Cu, 0x10u},\r
                        {0x5Fu, 0x01u},\r
                        {0x81u, 0xD6u},\r
                        {0x84u, 0x01u},\r
-                       {0x85u, 0x17u},\r
+                       {0x85u, 0xD2u},\r
                        {0x86u, 0x06u},\r
-                       {0x87u, 0x28u},\r
+                       {0x87u, 0x04u},\r
                        {0x89u, 0xD0u},\r
                        {0x8Bu, 0x06u},\r
+                       {0x8Du, 0xD6u},\r
                        {0x8Eu, 0x08u},\r
                        {0x90u, 0x05u},\r
                        {0x91u, 0xD6u},\r
@@ -997,158 +1012,147 @@ void cyfitter_cfg(void)
                        {0x99u, 0x29u},\r
                        {0x9Bu, 0x46u},\r
                        {0x9Cu, 0x04u},\r
-                       {0x9Du, 0xD6u},\r
+                       {0x9Du, 0x04u},\r
                        {0x9Eu, 0x03u},\r
                        {0xA1u, 0x21u},\r
                        {0xA2u, 0x10u},\r
                        {0xA3u, 0x8Eu},\r
                        {0xA4u, 0x03u},\r
-                       {0xA5u, 0xD2u},\r
+                       {0xA5u, 0x17u},\r
                        {0xA6u, 0x04u},\r
-                       {0xA7u, 0x04u},\r
+                       {0xA7u, 0x28u},\r
                        {0xA9u, 0x02u},\r
                        {0xACu, 0x08u},\r
-                       {0xADu, 0x04u},\r
                        {0xAEu, 0x10u},\r
-                       {0xB0u, 0x18u},\r
+                       {0xB1u, 0x0Fu},\r
                        {0xB3u, 0xF0u},\r
                        {0xB4u, 0x18u},\r
                        {0xB5u, 0x0Fu},\r
                        {0xB6u, 0x07u},\r
-                       {0xB9u, 0x20u},\r
+                       {0xB9u, 0x22u},\r
                        {0xBAu, 0x80u},\r
                        {0xBBu, 0x08u},\r
-                       {0xBEu, 0x11u},\r
+                       {0xBEu, 0x10u},\r
                        {0xD8u, 0x04u},\r
                        {0xD9u, 0x04u},\r
                        {0xDBu, 0x04u},\r
                        {0xDFu, 0x01u},\r
                        {0x00u, 0x84u},\r
-                       {0x05u, 0x40u},\r
-                       {0x06u, 0x04u},\r
-                       {0x07u, 0x10u},\r
+                       {0x04u, 0x20u},\r
+                       {0x05u, 0x08u},\r
+                       {0x06u, 0x02u},\r
                        {0x0Au, 0x82u},\r
-                       {0x0Du, 0x01u},\r
+                       {0x0Cu, 0x89u},\r
                        {0x0Eu, 0x04u},\r
-                       {0x0Fu, 0x22u},\r
+                       {0x0Fu, 0x40u},\r
                        {0x11u, 0x40u},\r
-                       {0x12u, 0x20u},\r
-                       {0x13u, 0x03u},\r
-                       {0x14u, 0x80u},\r
-                       {0x15u, 0x20u},\r
-                       {0x16u, 0x10u},\r
-                       {0x18u, 0x80u},\r
-                       {0x19u, 0x10u},\r
-                       {0x1Au, 0x4Au},\r
+                       {0x12u, 0x60u},\r
+                       {0x16u, 0x90u},\r
+                       {0x17u, 0x10u},\r
+                       {0x18u, 0x08u},\r
+                       {0x19u, 0x30u},\r
+                       {0x1Au, 0x02u},\r
                        {0x1Bu, 0x40u},\r
-                       {0x1Fu, 0x40u},\r
+                       {0x1Eu, 0x40u},\r
+                       {0x20u, 0x48u},\r
                        {0x21u, 0x08u},\r
                        {0x22u, 0x20u},\r
-                       {0x24u, 0x10u},\r
+                       {0x25u, 0x20u},\r
                        {0x26u, 0x40u},\r
                        {0x29u, 0x01u},\r
-                       {0x2Au, 0x08u},\r
-                       {0x2Bu, 0x06u},\r
-                       {0x2Cu, 0x20u},\r
-                       {0x2Eu, 0xA0u},\r
-                       {0x2Fu, 0x40u},\r
-                       {0x31u, 0x88u},\r
-                       {0x32u, 0x20u},\r
+                       {0x2Bu, 0x14u},\r
+                       {0x2Eu, 0x48u},\r
+                       {0x2Fu, 0x44u},\r
+                       {0x31u, 0x08u},\r
+                       {0x32u, 0xA0u},\r
                        {0x33u, 0x01u},\r
-                       {0x35u, 0x02u},\r
-                       {0x36u, 0x40u},\r
-                       {0x37u, 0x24u},\r
-                       {0x38u, 0x04u},\r
-                       {0x39u, 0x11u},\r
+                       {0x36u, 0x45u},\r
+                       {0x37u, 0x20u},\r
+                       {0x38u, 0x80u},\r
+                       {0x39u, 0x19u},\r
                        {0x3Du, 0xA8u},\r
                        {0x3Eu, 0x05u},\r
-                       {0x41u, 0x40u},\r
-                       {0x43u, 0x40u},\r
-                       {0x58u, 0x26u},\r
+                       {0x58u, 0x24u},\r
+                       {0x59u, 0x02u},\r
                        {0x5Bu, 0x40u},\r
-                       {0x62u, 0x80u},\r
+                       {0x63u, 0x01u},\r
                        {0x69u, 0x40u},\r
-                       {0x7Fu, 0x0Cu},\r
-                       {0x82u, 0x04u},\r
-                       {0x83u, 0x10u},\r
-                       {0x84u, 0x80u},\r
-                       {0x88u, 0x40u},\r
+                       {0x80u, 0x90u},\r
+                       {0x81u, 0x08u},\r
+                       {0x84u, 0x08u},\r
+                       {0x86u, 0x02u},\r
+                       {0x87u, 0x40u},\r
+                       {0x89u, 0x20u},\r
                        {0x8Au, 0x10u},\r
-                       {0x8Bu, 0x01u},\r
-                       {0x8Cu, 0x10u},\r
-                       {0x8Du, 0x02u},\r
-                       {0x8Fu, 0x10u},\r
-                       {0x91u, 0xA0u},\r
-                       {0x93u, 0x08u},\r
-                       {0x94u, 0x80u},\r
-                       {0x96u, 0x48u},\r
+                       {0x8Bu, 0x40u},\r
+                       {0x8Cu, 0x08u},\r
+                       {0x8Eu, 0x05u},\r
+                       {0x93u, 0x09u},\r
+                       {0x95u, 0x80u},\r
                        {0x98u, 0x24u},\r
-                       {0x9Bu, 0x24u},\r
-                       {0x9Du, 0x10u},\r
+                       {0x99u, 0x06u},\r
+                       {0x9Bu, 0x20u},\r
+                       {0x9Cu, 0x1Au},\r
+                       {0x9Du, 0x30u},\r
                        {0x9Eu, 0x41u},\r
-                       {0x9Fu, 0x0Au},\r
                        {0xA0u, 0xC0u},\r
                        {0xA1u, 0x54u},\r
-                       {0xA2u, 0x90u},\r
-                       {0xA3u, 0x20u},\r
-                       {0xA4u, 0x10u},\r
-                       {0xA5u, 0x03u},\r
-                       {0xA6u, 0x4Cu},\r
-                       {0xA8u, 0x01u},\r
-                       {0xADu, 0x90u},\r
-                       {0xAFu, 0x09u},\r
+                       {0xA2u, 0x10u},\r
+                       {0xA6u, 0x44u},\r
+                       {0xA8u, 0x03u},\r
+                       {0xA9u, 0x04u},\r
+                       {0xACu, 0x80u},\r
                        {0xB0u, 0x04u},\r
-                       {0xB1u, 0x10u},\r
                        {0xB3u, 0x02u},\r
+                       {0xB4u, 0x04u},\r
                        {0xC0u, 0xE5u},\r
                        {0xC2u, 0xF9u},\r
                        {0xC4u, 0x7Du},\r
-                       {0xCAu, 0xFFu},\r
+                       {0xCAu, 0xF7u},\r
                        {0xCCu, 0xFFu},\r
-                       {0xCEu, 0xF7u},\r
+                       {0xCEu, 0xFFu},\r
                        {0xD6u, 0x0Fu},\r
                        {0xD8u, 0x08u},\r
-                       {0xE2u, 0x11u},\r
-                       {0xE6u, 0x03u},\r
-                       {0xE8u, 0x02u},\r
-                       {0xEAu, 0x20u},\r
-                       {0xEEu, 0x01u},\r
+                       {0xE2u, 0x0Eu},\r
+                       {0xE6u, 0x8Du},\r
+                       {0xEAu, 0x40u},\r
+                       {0xEEu, 0x02u},\r
+                       {0x00u, 0xFFu},\r
                        {0x01u, 0x08u},\r
                        {0x03u, 0x05u},\r
                        {0x04u, 0x55u},\r
-                       {0x05u, 0x40u},\r
                        {0x06u, 0xAAu},\r
-                       {0x07u, 0x10u},\r
+                       {0x07u, 0x30u},\r
                        {0x0Au, 0xFFu},\r
-                       {0x0Bu, 0x30u},\r
-                       {0x0Cu, 0xFFu},\r
-                       {0x0Fu, 0x40u},\r
-                       {0x10u, 0x0Fu},\r
+                       {0x0Bu, 0x40u},\r
                        {0x11u, 0x08u},\r
-                       {0x12u, 0xF0u},\r
                        {0x13u, 0x06u},\r
                        {0x15u, 0x04u},\r
                        {0x16u, 0xFFu},\r
                        {0x17u, 0x08u},\r
+                       {0x18u, 0x0Fu},\r
                        {0x19u, 0x08u},\r
-                       {0x1Au, 0xFFu},\r
+                       {0x1Au, 0xF0u},\r
                        {0x1Bu, 0x04u},\r
-                       {0x1Cu, 0x69u},\r
-                       {0x1Eu, 0x96u},\r
+                       {0x1Cu, 0xFFu},\r
+                       {0x20u, 0x69u},\r
                        {0x21u, 0x40u},\r
+                       {0x22u, 0x96u},\r
                        {0x23u, 0x20u},\r
-                       {0x24u, 0xFFu},\r
+                       {0x24u, 0x33u},\r
                        {0x25u, 0x08u},\r
+                       {0x26u, 0xCCu},\r
                        {0x27u, 0x04u},\r
-                       {0x28u, 0x33u},\r
-                       {0x2Au, 0xCCu},\r
                        {0x2Bu, 0x40u},\r
-                       {0x30u, 0xFFu},\r
+                       {0x2Du, 0x40u},\r
+                       {0x2Eu, 0xFFu},\r
+                       {0x2Fu, 0x10u},\r
                        {0x31u, 0x01u},\r
                        {0x33u, 0x0Cu},\r
+                       {0x34u, 0xFFu},\r
                        {0x35u, 0x70u},\r
                        {0x37u, 0x02u},\r
-                       {0x3Au, 0x02u},\r
+                       {0x3Au, 0x20u},\r
                        {0x3Bu, 0x08u},\r
                        {0x56u, 0x08u},\r
                        {0x58u, 0x04u},\r
@@ -1158,35 +1162,35 @@ void cyfitter_cfg(void)
                        {0x5Du, 0x90u},\r
                        {0x5Fu, 0x01u},\r
                        {0x80u, 0xFFu},\r
+                       {0x83u, 0x02u},\r
                        {0x84u, 0x30u},\r
                        {0x86u, 0xC0u},\r
                        {0x87u, 0x01u},\r
-                       {0x88u, 0x50u},\r
-                       {0x8Au, 0xA0u},\r
                        {0x8Bu, 0x20u},\r
-                       {0x8Cu, 0x90u},\r
-                       {0x8Eu, 0x60u},\r
-                       {0x90u, 0x03u},\r
-                       {0x92u, 0x0Cu},\r
-                       {0x93u, 0x04u},\r
+                       {0x8Cu, 0x03u},\r
+                       {0x8Eu, 0x0Cu},\r
+                       {0x8Fu, 0x04u},\r
                        {0x94u, 0xFFu},\r
-                       {0x97u, 0x10u},\r
                        {0x98u, 0x05u},\r
                        {0x9Au, 0x0Au},\r
-                       {0x9Bu, 0x08u},\r
+                       {0x9Cu, 0x90u},\r
+                       {0x9Eu, 0x60u},\r
                        {0xA2u, 0xFFu},\r
-                       {0xA3u, 0x02u},\r
-                       {0xA8u, 0x09u},\r
-                       {0xAAu, 0x06u},\r
+                       {0xA4u, 0x09u},\r
+                       {0xA6u, 0x06u},\r
+                       {0xA7u, 0x10u},\r
+                       {0xA8u, 0x50u},\r
+                       {0xAAu, 0xA0u},\r
+                       {0xABu, 0x08u},\r
                        {0xACu, 0x0Fu},\r
                        {0xADu, 0x15u},\r
                        {0xAEu, 0xF0u},\r
                        {0xAFu, 0x2Au},\r
-                       {0xB1u, 0x03u},\r
-                       {0xB3u, 0x0Cu},\r
-                       {0xB5u, 0x30u},\r
-                       {0xB6u, 0xFFu},\r
-                       {0xBEu, 0x40u},\r
+                       {0xB1u, 0x0Cu},\r
+                       {0xB3u, 0x30u},\r
+                       {0xB4u, 0xFFu},\r
+                       {0xB5u, 0x03u},\r
+                       {0xBEu, 0x10u},\r
                        {0xBFu, 0x15u},\r
                        {0xD6u, 0x08u},\r
                        {0xD8u, 0x04u},\r
@@ -1194,110 +1198,112 @@ void cyfitter_cfg(void)
                        {0xDBu, 0x04u},\r
                        {0xDDu, 0x90u},\r
                        {0xDFu, 0x01u},\r
-                       {0x01u, 0x10u},\r
-                       {0x02u, 0x23u},\r
-                       {0x03u, 0x88u},\r
-                       {0x05u, 0x80u},\r
+                       {0x00u, 0x40u},\r
+                       {0x01u, 0x02u},\r
+                       {0x02u, 0x10u},\r
+                       {0x03u, 0x80u},\r
                        {0x06u, 0x20u},\r
-                       {0x07u, 0x04u},\r
-                       {0x08u, 0x01u},\r
-                       {0x09u, 0x04u},\r
-                       {0x0Au, 0x08u},\r
-                       {0x0Bu, 0x20u},\r
-                       {0x0Cu, 0x68u},\r
-                       {0x0Eu, 0x40u},\r
-                       {0x0Fu, 0x08u},\r
-                       {0x11u, 0xA0u},\r
-                       {0x13u, 0x02u},\r
-                       {0x16u, 0x08u},\r
-                       {0x17u, 0x08u},\r
-                       {0x18u, 0x02u},\r
-                       {0x1Eu, 0x40u},\r
-                       {0x20u, 0x80u},\r
+                       {0x07u, 0x44u},\r
+                       {0x0Au, 0x04u},\r
+                       {0x0Bu, 0x22u},\r
+                       {0x0Cu, 0x08u},\r
+                       {0x0Du, 0x20u},\r
+                       {0x0Eu, 0x01u},\r
+                       {0x10u, 0x80u},\r
+                       {0x11u, 0x90u},\r
+                       {0x13u, 0x04u},\r
+                       {0x14u, 0x50u},\r
+                       {0x15u, 0x40u},\r
+                       {0x19u, 0x20u},\r
+                       {0x1Du, 0x20u},\r
+                       {0x20u, 0x08u},\r
                        {0x21u, 0x08u},\r
-                       {0x23u, 0x04u},\r
+                       {0x23u, 0x40u},\r
                        {0x24u, 0x04u},\r
-                       {0x25u, 0x10u},\r
                        {0x26u, 0x85u},\r
-                       {0x2Au, 0x01u},\r
-                       {0x2Bu, 0x02u},\r
+                       {0x2Au, 0x10u},\r
+                       {0x2Bu, 0x12u},\r
                        {0x2Cu, 0x08u},\r
-                       {0x2Fu, 0x60u},\r
-                       {0x30u, 0x01u},\r
-                       {0x32u, 0x24u},\r
-                       {0x36u, 0x15u},\r
-                       {0x38u, 0x04u},\r
-                       {0x39u, 0x14u},\r
-                       {0x3Du, 0x20u},\r
-                       {0x3Fu, 0x8Au},\r
+                       {0x2Du, 0x40u},\r
+                       {0x2Eu, 0x01u},\r
+                       {0x2Fu, 0x20u},\r
+                       {0x36u, 0x25u},\r
+                       {0x38u, 0x46u},\r
+                       {0x39u, 0x10u},\r
+                       {0x3Bu, 0x82u},\r
+                       {0x3Cu, 0x04u},\r
+                       {0x3Du, 0x28u},\r
+                       {0x3Fu, 0x06u},\r
                        {0x5Au, 0x80u},\r
                        {0x5Eu, 0x80u},\r
                        {0x63u, 0x02u},\r
                        {0x64u, 0x02u},\r
                        {0x6Du, 0x80u},\r
                        {0x6Fu, 0x03u},\r
-                       {0x82u, 0x22u},\r
-                       {0x85u, 0x0Cu},\r
-                       {0x8Au, 0x40u},\r
-                       {0x8Bu, 0x81u},\r
-                       {0x8Cu, 0x01u},\r
-                       {0x8Du, 0x04u},\r
-                       {0x90u, 0x20u},\r
-                       {0x92u, 0x18u},\r
+                       {0x81u, 0x0Au},\r
+                       {0x83u, 0x02u},\r
+                       {0x85u, 0x30u},\r
+                       {0x86u, 0x10u},\r
+                       {0x87u, 0x40u},\r
+                       {0x8Au, 0x04u},\r
+                       {0x8Bu, 0x10u},\r
+                       {0x8Du, 0x60u},\r
+                       {0x92u, 0x15u},\r
                        {0x93u, 0xA0u},\r
-                       {0x95u, 0x01u},\r
-                       {0x97u, 0x44u},\r
-                       {0x98u, 0x41u},\r
-                       {0x9Au, 0x28u},\r
-                       {0x9Bu, 0x18u},\r
-                       {0x9Du, 0x25u},\r
-                       {0x9Eu, 0x10u},\r
+                       {0x95u, 0x41u},\r
+                       {0x98u, 0x58u},\r
+                       {0x99u, 0x80u},\r
+                       {0x9Au, 0x20u},\r
+                       {0x9Bu, 0x10u},\r
+                       {0x9Du, 0x15u},\r
                        {0x9Fu, 0x01u},\r
                        {0xA0u, 0x08u},\r
-                       {0xA2u, 0x10u},\r
-                       {0xA3u, 0x40u},\r
-                       {0xA4u, 0x65u},\r
+                       {0xA1u, 0x10u},\r
+                       {0xA2u, 0x60u},\r
+                       {0xA3u, 0x10u},\r
+                       {0xA4u, 0x45u},\r
                        {0xA6u, 0x84u},\r
                        {0xA8u, 0x40u},\r
                        {0xAAu, 0x40u},\r
-                       {0xACu, 0x01u},\r
-                       {0xAFu, 0x10u},\r
-                       {0xB0u, 0x05u},\r
-                       {0xB7u, 0x02u},\r
-                       {0xC0u, 0xEFu},\r
-                       {0xC2u, 0xFEu},\r
-                       {0xC4u, 0x6Bu},\r
-                       {0xCAu, 0xE9u},\r
-                       {0xCCu, 0xE7u},\r
-                       {0xCEu, 0xF6u},\r
+                       {0xACu, 0x10u},\r
+                       {0xB2u, 0x40u},\r
+                       {0xB5u, 0xA0u},\r
+                       {0xC0u, 0x7Du},\r
+                       {0xC2u, 0xE7u},\r
+                       {0xC4u, 0xBFu},\r
+                       {0xCAu, 0xFEu},\r
+                       {0xCCu, 0xE0u},\r
+                       {0xCEu, 0xEFu},\r
                        {0xD6u, 0x18u},\r
                        {0xD8u, 0x18u},\r
-                       {0xE0u, 0x02u},\r
-                       {0xE2u, 0xC0u},\r
-                       {0xE6u, 0x60u},\r
-                       {0xEAu, 0xACu},\r
-                       {0xEEu, 0x05u},\r
+                       {0xE0u, 0x41u},\r
+                       {0xE2u, 0x30u},\r
+                       {0xE4u, 0x02u},\r
+                       {0xE6u, 0x21u},\r
+                       {0xEAu, 0x44u},\r
+                       {0xECu, 0x40u},\r
+                       {0xEEu, 0x04u},\r
                        {0x01u, 0x02u},\r
                        {0x02u, 0x02u},\r
                        {0x03u, 0x01u},\r
                        {0x0Cu, 0x01u},\r
                        {0x0Eu, 0x02u},\r
-                       {0x10u, 0x90u},\r
-                       {0x12u, 0x48u},\r
                        {0x15u, 0x02u},\r
                        {0x16u, 0x61u},\r
                        {0x17u, 0x09u},\r
                        {0x19u, 0x01u},\r
                        {0x1Au, 0x0Cu},\r
                        {0x1Bu, 0x02u},\r
+                       {0x1Cu, 0x90u},\r
                        {0x1Du, 0x02u},\r
-                       {0x1Eu, 0x10u},\r
+                       {0x1Eu, 0x48u},\r
                        {0x1Fu, 0x11u},\r
                        {0x22u, 0x80u},\r
-                       {0x24u, 0x90u},\r
-                       {0x26u, 0x24u},\r
+                       {0x26u, 0x10u},\r
                        {0x2Au, 0x90u},\r
+                       {0x2Cu, 0x90u},\r
                        {0x2Du, 0x02u},\r
+                       {0x2Eu, 0x24u},\r
                        {0x2Fu, 0x05u},\r
                        {0x30u, 0x03u},\r
                        {0x31u, 0x10u},\r
@@ -1325,18 +1331,18 @@ void cyfitter_cfg(void)
                        {0x8Cu, 0x0Fu},\r
                        {0x8Eu, 0xF0u},\r
                        {0x8Fu, 0x01u},\r
+                       {0x90u, 0x03u},\r
                        {0x91u, 0x0Au},\r
+                       {0x92u, 0x0Cu},\r
                        {0x93u, 0x14u},\r
-                       {0x97u, 0x04u},\r
+                       {0x97u, 0x02u},\r
                        {0x98u, 0x06u},\r
                        {0x9Au, 0x09u},\r
-                       {0x9Bu, 0x02u},\r
+                       {0x9Bu, 0x10u},\r
                        {0x9Fu, 0x20u},\r
                        {0xA4u, 0x05u},\r
                        {0xA6u, 0x0Au},\r
-                       {0xABu, 0x10u},\r
-                       {0xACu, 0x03u},\r
-                       {0xAEu, 0x0Cu},\r
+                       {0xA7u, 0x04u},\r
                        {0xB1u, 0x06u},\r
                        {0xB3u, 0x01u},\r
                        {0xB4u, 0xFFu},\r
@@ -1353,115 +1359,115 @@ void cyfitter_cfg(void)
                        {0xDFu, 0x01u},\r
                        {0x01u, 0x01u},\r
                        {0x03u, 0x01u},\r
-                       {0x05u, 0x2Bu},\r
-                       {0x06u, 0x10u},\r
+                       {0x05u, 0x1Fu},\r
                        {0x07u, 0x01u},\r
-                       {0x09u, 0x40u},\r
-                       {0x0Au, 0x14u},\r
-                       {0x0Bu, 0x80u},\r
+                       {0x0Au, 0x15u},\r
+                       {0x0Cu, 0x01u},\r
                        {0x0Fu, 0x08u},\r
                        {0x10u, 0x28u},\r
-                       {0x11u, 0x02u},\r
-                       {0x14u, 0x20u},\r
-                       {0x15u, 0x48u},\r
-                       {0x1Au, 0x1Cu},\r
-                       {0x1Bu, 0x02u},\r
+                       {0x11u, 0x42u},\r
+                       {0x17u, 0x08u},\r
+                       {0x1Au, 0x14u},\r
+                       {0x1Bu, 0x12u},\r
                        {0x1Fu, 0x10u},\r
                        {0x21u, 0x29u},\r
                        {0x22u, 0x40u},\r
                        {0x24u, 0x02u},\r
-                       {0x26u, 0x11u},\r
+                       {0x26u, 0x21u},\r
                        {0x27u, 0x10u},\r
                        {0x28u, 0x02u},\r
-                       {0x2Du, 0x20u},\r
+                       {0x2Du, 0x08u},\r
                        {0x31u, 0x28u},\r
                        {0x32u, 0x40u},\r
-                       {0x34u, 0x20u},\r
-                       {0x35u, 0x08u},\r
+                       {0x35u, 0x10u},\r
                        {0x36u, 0x80u},\r
-                       {0x37u, 0x01u},\r
+                       {0x37u, 0x09u},\r
                        {0x39u, 0x02u},\r
-                       {0x3Fu, 0x48u},\r
+                       {0x3Cu, 0x80u},\r
+                       {0x3Fu, 0x08u},\r
                        {0x5Au, 0x40u},\r
                        {0x5Cu, 0x44u},\r
-                       {0x5Fu, 0x12u},\r
+                       {0x5Du, 0x20u},\r
+                       {0x5Fu, 0x02u},\r
                        {0x60u, 0x02u},\r
-                       {0x64u, 0x40u},\r
-                       {0x66u, 0x2Au},\r
-                       {0x67u, 0x0Au},\r
+                       {0x64u, 0x50u},\r
+                       {0x66u, 0x20u},\r
+                       {0x67u, 0x4Au},\r
                        {0x80u, 0x08u},\r
-                       {0x82u, 0x02u},\r
-                       {0x86u, 0x08u},\r
-                       {0x87u, 0x04u},\r
-                       {0x8Bu, 0x04u},\r
+                       {0x84u, 0x04u},\r
+                       {0x87u, 0x44u},\r
+                       {0x8Bu, 0x40u},\r
+                       {0x8Eu, 0x01u},\r
                        {0x8Fu, 0x03u},\r
-                       {0x90u, 0x24u},\r
-                       {0x91u, 0x48u},\r
-                       {0x93u, 0x80u},\r
+                       {0x90u, 0x04u},\r
+                       {0x92u, 0x01u},\r
                        {0x94u, 0x02u},\r
-                       {0x9Bu, 0x08u},\r
-                       {0x9Du, 0x06u},\r
+                       {0x98u, 0x09u},\r
+                       {0x9Bu, 0x0Au},\r
+                       {0x9Du, 0x02u},\r
                        {0x9Fu, 0x01u},\r
-                       {0xA1u, 0x41u},\r
-                       {0xA3u, 0x44u},\r
-                       {0xA4u, 0x40u},\r
+                       {0xA0u, 0x20u},\r
+                       {0xA1u, 0x11u},\r
+                       {0xA3u, 0x04u},\r
+                       {0xA4u, 0x01u},\r
                        {0xA5u, 0x20u},\r
-                       {0xA6u, 0x05u},\r
-                       {0xADu, 0x04u},\r
+                       {0xA6u, 0x04u},\r
+                       {0xABu, 0x02u},\r
+                       {0xACu, 0x01u},\r
                        {0xAFu, 0x01u},\r
                        {0xC0u, 0xF9u},\r
-                       {0xC2u, 0x4Fu},\r
-                       {0xC4u, 0xAEu},\r
-                       {0xCAu, 0x28u},\r
+                       {0xC2u, 0x57u},\r
+                       {0xC4u, 0x2Fu},\r
+                       {0xCAu, 0x48u},\r
                        {0xCCu, 0xFEu},\r
                        {0xCEu, 0x51u},\r
                        {0xD6u, 0xF8u},\r
                        {0xD8u, 0xF8u},\r
-                       {0xE2u, 0x40u},\r
+                       {0xE2u, 0x70u},\r
+                       {0xE4u, 0x02u},\r
+                       {0xE6u, 0x80u},\r
                        {0xEAu, 0x01u},\r
-                       {0xEEu, 0x8Du},\r
+                       {0xEEu, 0x81u},\r
                        {0x80u, 0x04u},\r
-                       {0x81u, 0x04u},\r
                        {0x82u, 0x04u},\r
+                       {0x84u, 0x01u},\r
                        {0x85u, 0x22u},\r
-                       {0x88u, 0x40u},\r
-                       {0x8Bu, 0x48u},\r
-                       {0x8Du, 0x40u},\r
-                       {0x90u, 0x20u},\r
+                       {0x8Au, 0x01u},\r
+                       {0x8Fu, 0x08u},\r
                        {0x94u, 0x02u},\r
-                       {0xA1u, 0x41u},\r
-                       {0xA3u, 0x44u},\r
-                       {0xA6u, 0x01u},\r
-                       {0xB7u, 0x44u},\r
-                       {0xE0u, 0x40u},\r
-                       {0xE2u, 0x04u},\r
-                       {0xE4u, 0x80u},\r
-                       {0xE8u, 0x40u},\r
-                       {0xECu, 0x40u},\r
+                       {0x98u, 0x08u},\r
+                       {0xA0u, 0x20u},\r
+                       {0xA1u, 0x11u},\r
+                       {0xA3u, 0x04u},\r
+                       {0xB4u, 0x01u},\r
+                       {0xE2u, 0x14u},\r
+                       {0xE4u, 0xC0u},\r
+                       {0xE6u, 0x02u},\r
+                       {0xEAu, 0x40u},\r
                        {0xEEu, 0x80u},\r
-                       {0x80u, 0x11u},\r
-                       {0x81u, 0x01u},\r
-                       {0x89u, 0x40u},\r
-                       {0x8Eu, 0x01u},\r
-                       {0xE2u, 0x10u},\r
+                       {0x81u, 0x11u},\r
+                       {0x83u, 0x04u},\r
+                       {0x88u, 0x20u},\r
+                       {0x8Cu, 0x08u},\r
+                       {0xE0u, 0x40u},\r
                        {0xE4u, 0x20u},\r
                        {0x82u, 0x02u},\r
                        {0x83u, 0x07u},\r
+                       {0x87u, 0x2Au},\r
                        {0x88u, 0x11u},\r
                        {0x8Au, 0x22u},\r
-                       {0x8Cu, 0x28u},\r
-                       {0x8Eu, 0x13u},\r
-                       {0x91u, 0x34u},\r
+                       {0x8Cu, 0x14u},\r
+                       {0x8Du, 0x34u},\r
+                       {0x8Eu, 0x43u},\r
+                       {0x90u, 0x28u},\r
+                       {0x92u, 0x13u},\r
                        {0x95u, 0x07u},\r
                        {0x96u, 0x01u},\r
                        {0x98u, 0x60u},\r
-                       {0x9Bu, 0x2Au},\r
+                       {0x99u, 0x01u},\r
+                       {0x9Bu, 0x18u},\r
                        {0x9Eu, 0x0Cu},\r
                        {0x9Fu, 0x08u},\r
-                       {0xA4u, 0x14u},\r
-                       {0xA6u, 0x43u},\r
-                       {0xA9u, 0x01u},\r
-                       {0xABu, 0x18u},\r
                        {0xB1u, 0x38u},\r
                        {0xB4u, 0x70u},\r
                        {0xB6u, 0x0Fu},\r
@@ -1471,116 +1477,122 @@ void cyfitter_cfg(void)
                        {0xD8u, 0x04u},\r
                        {0xD9u, 0x04u},\r
                        {0xDFu, 0x01u},\r
-                       {0x00u, 0x04u},\r
-                       {0x01u, 0x01u},\r
+                       {0x00u, 0x08u},\r
+                       {0x01u, 0x21u},\r
                        {0x03u, 0x01u},\r
                        {0x04u, 0x40u},\r
-                       {0x05u, 0x20u},\r
+                       {0x05u, 0x10u},\r
                        {0x06u, 0x40u},\r
                        {0x09u, 0x80u},\r
-                       {0x0Au, 0x94u},\r
-                       {0x0Eu, 0x2Au},\r
-                       {0x0Fu, 0x01u},\r
+                       {0x0Au, 0x54u},\r
+                       {0x0Eu, 0x6Au},\r
+                       {0x0Fu, 0x02u},\r
                        {0x11u, 0x10u},\r
-                       {0x12u, 0x21u},\r
-                       {0x13u, 0x08u},\r
-                       {0x17u, 0x08u},\r
-                       {0x18u, 0x44u},\r
-                       {0x19u, 0x29u},\r
-                       {0x1Au, 0x90u},\r
-                       {0x1Bu, 0x04u},\r
+                       {0x12u, 0x80u},\r
+                       {0x18u, 0x04u},\r
+                       {0x19u, 0x31u},\r
+                       {0x1Au, 0xF0u},\r
+                       {0x1Bu, 0x14u},\r
                        {0x1Eu, 0x0Au},\r
                        {0x22u, 0x02u},\r
                        {0x27u, 0x82u},\r
-                       {0x29u, 0x29u},\r
+                       {0x29u, 0x11u},\r
                        {0x2Au, 0x40u},\r
-                       {0x2Du, 0x20u},\r
-                       {0x31u, 0x10u},\r
-                       {0x32u, 0x20u},\r
+                       {0x32u, 0x10u},\r
                        {0x33u, 0x49u},\r
-                       {0x35u, 0x01u},\r
-                       {0x36u, 0x24u},\r
+                       {0x35u, 0x10u},\r
+                       {0x36u, 0x04u},\r
                        {0x37u, 0x80u},\r
-                       {0x38u, 0x80u},\r
+                       {0x38u, 0x40u},\r
                        {0x39u, 0x18u},\r
-                       {0x3Fu, 0x01u},\r
-                       {0x40u, 0x64u},\r
-                       {0x49u, 0x14u},\r
+                       {0x3Au, 0x02u},\r
+                       {0x3Cu, 0x08u},\r
+                       {0x3Eu, 0x40u},\r
+                       {0x3Fu, 0x02u},\r
+                       {0x40u, 0x04u},\r
+                       {0x42u, 0x60u},\r
+                       {0x48u, 0x04u},\r
+                       {0x49u, 0x04u},\r
+                       {0x4Au, 0x80u},\r
                        {0x4Bu, 0x40u},\r
                        {0x50u, 0x20u},\r
-                       {0x52u, 0x41u},\r
-                       {0x53u, 0x06u},\r
+                       {0x51u, 0x42u},\r
+                       {0x52u, 0x40u},\r
+                       {0x53u, 0x80u},\r
                        {0x63u, 0x80u},\r
                        {0x69u, 0x19u},\r
                        {0x6Au, 0x04u},\r
                        {0x6Bu, 0x61u},\r
                        {0x70u, 0x40u},\r
                        {0x71u, 0x80u},\r
-                       {0x80u, 0x20u},\r
+                       {0x72u, 0x02u},\r
+                       {0x82u, 0x20u},\r
+                       {0x85u, 0x02u},\r
                        {0x87u, 0x02u},\r
                        {0x8Bu, 0x80u},\r
+                       {0x90u, 0x40u},\r
                        {0x93u, 0x40u},\r
                        {0x94u, 0x84u},\r
-                       {0x95u, 0x19u},\r
+                       {0x95u, 0x99u},\r
                        {0x96u, 0x90u},\r
-                       {0x97u, 0x08u},\r
                        {0x9Du, 0x05u},\r
-                       {0x9Eu, 0x40u},\r
                        {0x9Fu, 0x61u},\r
-                       {0xA2u, 0x30u},\r
+                       {0xA0u, 0x04u},\r
+                       {0xA2u, 0x10u},\r
                        {0xA3u, 0x48u},\r
                        {0xA4u, 0x20u},\r
                        {0xA5u, 0x80u},\r
-                       {0xA6u, 0x02u},\r
-                       {0xA7u, 0x06u},\r
-                       {0xA8u, 0x08u},\r
-                       {0xAEu, 0x60u},\r
-                       {0xB1u, 0x04u},\r
-                       {0xB2u, 0x08u},\r
-                       {0xB3u, 0x20u},\r
+                       {0xA6u, 0x82u},\r
+                       {0xA7u, 0x94u},\r
+                       {0xA9u, 0x04u},\r
+                       {0xABu, 0x01u},\r
+                       {0xAEu, 0x20u},\r
+                       {0xB0u, 0x20u},\r
                        {0xB4u, 0x01u},\r
-                       {0xC0u, 0xDDu},\r
-                       {0xC2u, 0xEFu},\r
-                       {0xC4u, 0x27u},\r
-                       {0xCAu, 0x2Fu},\r
-                       {0xCCu, 0xFFu},\r
-                       {0xCEu, 0x8Eu},\r
+                       {0xB5u, 0x10u},\r
+                       {0xB6u, 0x88u},\r
+                       {0xC0u, 0xDFu},\r
+                       {0xC2u, 0xFFu},\r
+                       {0xC4u, 0x0Au},\r
+                       {0xCAu, 0x0Du},\r
+                       {0xCCu, 0x7Fu},\r
+                       {0xCEu, 0xDFu},\r
                        {0xD0u, 0x07u},\r
                        {0xD2u, 0x0Cu},\r
                        {0xD8u, 0x01u},\r
+                       {0xE0u, 0x02u},\r
                        {0xE6u, 0x20u},\r
-                       {0xEAu, 0x09u},\r
-                       {0xEEu, 0x02u},\r
-                       {0x01u, 0x05u},\r
-                       {0x03u, 0x08u},\r
-                       {0x04u, 0x0Fu},\r
-                       {0x06u, 0xF0u},\r
+                       {0xE8u, 0x04u},\r
+                       {0xEAu, 0x29u},\r
+                       {0x00u, 0x60u},\r
+                       {0x02u, 0x90u},\r
+                       {0x06u, 0xFFu},\r
                        {0x07u, 0x01u},\r
-                       {0x08u, 0x60u},\r
-                       {0x0Au, 0x90u},\r
-                       {0x0Cu, 0x05u},\r
-                       {0x0Eu, 0x0Au},\r
-                       {0x0Fu, 0x08u},\r
-                       {0x10u, 0x50u},\r
-                       {0x12u, 0xA0u},\r
+                       {0x08u, 0x0Fu},\r
+                       {0x09u, 0x01u},\r
+                       {0x0Au, 0xF0u},\r
+                       {0x0Bu, 0x08u},\r
+                       {0x0Cu, 0x50u},\r
+                       {0x0Eu, 0xA0u},\r
+                       {0x10u, 0xFFu},\r
+                       {0x11u, 0x02u},\r
                        {0x14u, 0x30u},\r
-                       {0x15u, 0x01u},\r
+                       {0x15u, 0x05u},\r
                        {0x16u, 0xC0u},\r
                        {0x17u, 0x08u},\r
-                       {0x18u, 0x03u},\r
-                       {0x1Au, 0x0Cu},\r
-                       {0x1Eu, 0xFFu},\r
-                       {0x20u, 0x06u},\r
-                       {0x21u, 0x04u},\r
-                       {0x22u, 0x09u},\r
-                       {0x23u, 0x08u},\r
-                       {0x26u, 0xFFu},\r
-                       {0x28u, 0xFFu},\r
-                       {0x2Du, 0x02u},\r
-                       {0x31u, 0x0Fu},\r
+                       {0x1Au, 0xFFu},\r
+                       {0x1Bu, 0x08u},\r
+                       {0x1Cu, 0x03u},\r
+                       {0x1Eu, 0x0Cu},\r
+                       {0x24u, 0x05u},\r
+                       {0x26u, 0x0Au},\r
+                       {0x28u, 0x06u},\r
+                       {0x29u, 0x04u},\r
+                       {0x2Au, 0x09u},\r
+                       {0x2Bu, 0x08u},\r
                        {0x33u, 0x0Fu},\r
                        {0x36u, 0xFFu},\r
-                       {0x39u, 0x0Au},\r
+                       {0x39u, 0x08u},\r
                        {0x3Eu, 0x40u},\r
                        {0x56u, 0x08u},\r
                        {0x58u, 0x04u},\r
@@ -1590,6 +1602,7 @@ void cyfitter_cfg(void)
                        {0x5Du, 0x90u},\r
                        {0x5Fu, 0x01u},\r
                        {0x80u, 0x10u},\r
+                       {0x83u, 0x04u},\r
                        {0x84u, 0x87u},\r
                        {0x85u, 0x03u},\r
                        {0x86u, 0x18u},\r
@@ -1601,7 +1614,6 @@ void cyfitter_cfg(void)
                        {0x92u, 0x08u},\r
                        {0x93u, 0x03u},\r
                        {0x94u, 0x01u},\r
-                       {0x97u, 0x04u},\r
                        {0x98u, 0x40u},\r
                        {0x9Bu, 0x01u},\r
                        {0x9Cu, 0x01u},\r
@@ -1631,105 +1643,97 @@ void cyfitter_cfg(void)
                        {0xDCu, 0x10u},\r
                        {0xDFu, 0x01u},\r
                        {0x00u, 0x04u},\r
-                       {0x02u, 0x40u},\r
-                       {0x03u, 0x09u},\r
-                       {0x05u, 0x40u},\r
-                       {0x06u, 0x14u},\r
+                       {0x03u, 0x89u},\r
+                       {0x04u, 0x20u},\r
+                       {0x05u, 0x08u},\r
+                       {0x06u, 0x82u},\r
                        {0x09u, 0x80u},\r
                        {0x0Au, 0x98u},\r
-                       {0x0Cu, 0x40u},\r
-                       {0x0Du, 0x11u},\r
-                       {0x0Fu, 0x20u},\r
+                       {0x0Cu, 0x89u},\r
+                       {0x0Eu, 0x04u},\r
                        {0x11u, 0x01u},\r
                        {0x12u, 0x22u},\r
                        {0x13u, 0x20u},\r
-                       {0x14u, 0x80u},\r
-                       {0x15u, 0x04u},\r
+                       {0x16u, 0x10u},\r
                        {0x17u, 0x10u},\r
                        {0x19u, 0x80u},\r
                        {0x1Au, 0x08u},\r
                        {0x1Bu, 0x09u},\r
                        {0x1Eu, 0x01u},\r
-                       {0x20u, 0x09u},\r
+                       {0x20u, 0x01u},\r
                        {0x22u, 0x09u},\r
-                       {0x23u, 0x40u},\r
-                       {0x25u, 0x03u},\r
+                       {0x23u, 0x44u},\r
                        {0x26u, 0x04u},\r
-                       {0x28u, 0x02u},\r
                        {0x2Au, 0x20u},\r
-                       {0x2Bu, 0x02u},\r
-                       {0x2Cu, 0x82u},\r
-                       {0x30u, 0x28u},\r
-                       {0x32u, 0x10u},\r
+                       {0x2Fu, 0x04u},\r
+                       {0x30u, 0x20u},\r
                        {0x33u, 0x41u},\r
-                       {0x37u, 0x04u},\r
+                       {0x34u, 0x02u},\r
+                       {0x35u, 0x20u},\r
+                       {0x36u, 0x04u},\r
                        {0x38u, 0x80u},\r
                        {0x39u, 0x18u},\r
-                       {0x3Au, 0x08u},\r
-                       {0x3Du, 0x0Eu},\r
-                       {0x3Eu, 0x40u},\r
-                       {0x58u, 0x10u},\r
-                       {0x59u, 0x84u},\r
+                       {0x3Bu, 0x01u},\r
+                       {0x3Du, 0x28u},\r
+                       {0x59u, 0x94u},\r
                        {0x5Au, 0x02u},\r
-                       {0x5Eu, 0x80u},\r
+                       {0x5Cu, 0x80u},\r
                        {0x62u, 0x01u},\r
                        {0x63u, 0x02u},\r
-                       {0x67u, 0x01u},\r
-                       {0x84u, 0x12u},\r
-                       {0x88u, 0x16u},\r
-                       {0x8Bu, 0x0Cu},\r
-                       {0x8Eu, 0x10u},\r
-                       {0x91u, 0x22u},\r
-                       {0x92u, 0x40u},\r
-                       {0x94u, 0x04u},\r
-                       {0x95u, 0x11u},\r
+                       {0x66u, 0x40u},\r
+                       {0x78u, 0x10u},\r
+                       {0x7Au, 0x08u},\r
+                       {0x80u, 0x02u},\r
+                       {0x87u, 0x04u},\r
+                       {0x8Au, 0x80u},\r
+                       {0x90u, 0x60u},\r
+                       {0x92u, 0x04u},\r
+                       {0x93u, 0x08u},\r
+                       {0x94u, 0x84u},\r
+                       {0x95u, 0x99u},\r
                        {0x96u, 0x81u},\r
-                       {0x97u, 0x01u},\r
-                       {0x98u, 0xC0u},\r
-                       {0x99u, 0x40u},\r
-                       {0x9Au, 0x14u},\r
-                       {0x9Bu, 0x14u},\r
+                       {0x98u, 0x81u},\r
+                       {0x99u, 0x28u},\r
+                       {0x9Au, 0x12u},\r
+                       {0x9Bu, 0x10u},\r
+                       {0x9Cu, 0x12u},\r
                        {0x9Du, 0x01u},\r
-                       {0x9Eu, 0x49u},\r
-                       {0x9Fu, 0x09u},\r
-                       {0xA0u, 0x80u},\r
-                       {0xA1u, 0x04u},\r
+                       {0x9Eu, 0xC1u},\r
+                       {0x9Fu, 0x01u},\r
+                       {0xA0u, 0x8Cu},\r
+                       {0xA1u, 0x14u},\r
                        {0xA2u, 0x30u},\r
-                       {0xA3u, 0x70u},\r
-                       {0xA4u, 0x10u},\r
-                       {0xA5u, 0x83u},\r
-                       {0xA6u, 0x0Cu},\r
-                       {0xA7u, 0x06u},\r
-                       {0xA8u, 0x22u},\r
-                       {0xAAu, 0x40u},\r
-                       {0xABu, 0x08u},\r
-                       {0xB1u, 0x43u},\r
-                       {0xB2u, 0x80u},\r
-                       {0xB6u, 0x20u},\r
-                       {0xC0u, 0xEFu},\r
+                       {0xA3u, 0x40u},\r
+                       {0xA6u, 0x84u},\r
+                       {0xA7u, 0x14u},\r
+                       {0xA9u, 0x04u},\r
+                       {0xABu, 0x50u},\r
+                       {0xB2u, 0x08u},\r
+                       {0xB4u, 0x04u},\r
+                       {0xC0u, 0xFFu},\r
                        {0xC2u, 0xFFu},\r
-                       {0xC4u, 0x7Fu},\r
-                       {0xCAu, 0x94u},\r
-                       {0xCCu, 0x4Fu},\r
-                       {0xCEu, 0xDEu},\r
+                       {0xC4u, 0x6Fu},\r
+                       {0xCAu, 0x24u},\r
+                       {0xCCu, 0xEDu},\r
+                       {0xCEu, 0x6Fu},\r
                        {0xD6u, 0x1Fu},\r
                        {0xD8u, 0x19u},\r
-                       {0xE6u, 0x44u},\r
-                       {0xE8u, 0x04u},\r
-                       {0xEAu, 0x03u},\r
+                       {0xE0u, 0x02u},\r
+                       {0xE2u, 0x10u},\r
+                       {0xE6u, 0x49u},\r
+                       {0xEAu, 0x06u},\r
                        {0xEEu, 0x08u},\r
                        {0x01u, 0x01u},\r
                        {0x03u, 0x02u},\r
+                       {0x04u, 0x01u},\r
                        {0x05u, 0x02u},\r
                        {0x07u, 0x01u},\r
-                       {0x08u, 0x08u},\r
                        {0x09u, 0x02u},\r
-                       {0x0Au, 0x12u},\r
                        {0x0Bu, 0x01u},\r
-                       {0x0Cu, 0x1Au},\r
+                       {0x0Cu, 0x20u},\r
                        {0x0Du, 0x10u},\r
-                       {0x0Eu, 0x64u},\r
-                       {0x0Fu, 0x08u},\r
+                       {0x0Eu, 0x44u},\r
+                       {0x0Fu, 0x0Cu},\r
                        {0x11u, 0x02u},\r
                        {0x13u, 0x21u},\r
                        {0x14u, 0x10u},\r
@@ -1739,17 +1743,18 @@ void cyfitter_cfg(void)
                        {0x18u, 0x80u},\r
                        {0x19u, 0x10u},\r
                        {0x1Bu, 0x08u},\r
-                       {0x1Cu, 0x20u},\r
-                       {0x1Eu, 0x44u},\r
-                       {0x20u, 0x40u},\r
-                       {0x21u, 0x10u},\r
-                       {0x22u, 0x20u},\r
-                       {0x23u, 0x0Cu},\r
-                       {0x24u, 0x01u},\r
+                       {0x1Cu, 0x40u},\r
+                       {0x1Eu, 0x20u},\r
+                       {0x20u, 0x1Au},\r
+                       {0x22u, 0x64u},\r
                        {0x25u, 0x10u},\r
                        {0x27u, 0x08u},\r
-                       {0x29u, 0x02u},\r
-                       {0x2Bu, 0x01u},\r
+                       {0x28u, 0x08u},\r
+                       {0x29u, 0x10u},\r
+                       {0x2Au, 0x12u},\r
+                       {0x2Bu, 0x08u},\r
+                       {0x2Du, 0x02u},\r
+                       {0x2Fu, 0x01u},\r
                        {0x30u, 0x80u},\r
                        {0x31u, 0x03u},\r
                        {0x32u, 0x01u},\r
@@ -1779,305 +1784,311 @@ void cyfitter_cfg(void)
                        {0x96u, 0xFFu},\r
                        {0x98u, 0x05u},\r
                        {0x9Au, 0x0Au},\r
+                       {0x9Cu, 0x90u},\r
+                       {0x9Eu, 0x60u},\r
                        {0xA2u, 0xFFu},\r
                        {0xA4u, 0x30u},\r
                        {0xA6u, 0xC0u},\r
-                       {0xACu, 0x90u},\r
-                       {0xAEu, 0x60u},\r
-                       {0xB0u, 0xFFu},\r
-                       {0xBEu, 0x01u},\r
+                       {0xB6u, 0xFFu},\r
+                       {0xBEu, 0x40u},\r
                        {0xD6u, 0x08u},\r
                        {0xD8u, 0x04u},\r
                        {0xDBu, 0x04u},\r
                        {0xDDu, 0x90u},\r
                        {0xDFu, 0x01u},\r
-                       {0x00u, 0x44u},\r
+                       {0x00u, 0x04u},\r
                        {0x01u, 0x10u},\r
-                       {0x03u, 0x82u},\r
-                       {0x04u, 0x60u},\r
-                       {0x08u, 0x01u},\r
-                       {0x0Au, 0x08u},\r
-                       {0x0Bu, 0x20u},\r
-                       {0x0Cu, 0x80u},\r
-                       {0x0Eu, 0x18u},\r
-                       {0x11u, 0x84u},\r
-                       {0x12u, 0x21u},\r
-                       {0x13u, 0x02u},\r
-                       {0x15u, 0x01u},\r
-                       {0x17u, 0x08u},\r
-                       {0x18u, 0x80u},\r
-                       {0x1Cu, 0x08u},\r
-                       {0x1Du, 0x04u},\r
+                       {0x03u, 0x83u},\r
+                       {0x04u, 0x08u},\r
+                       {0x05u, 0x40u},\r
+                       {0x09u, 0x40u},\r
+                       {0x0Au, 0x04u},\r
+                       {0x0Bu, 0xA0u},\r
+                       {0x0Eu, 0x19u},\r
+                       {0x10u, 0x80u},\r
+                       {0x11u, 0x04u},\r
+                       {0x12u, 0x10u},\r
+                       {0x14u, 0x08u},\r
+                       {0x17u, 0x01u},\r
+                       {0x1Au, 0x02u},\r
+                       {0x1Cu, 0x18u},\r
                        {0x1Eu, 0x40u},\r
                        {0x1Fu, 0x80u},\r
-                       {0x24u, 0x01u},\r
-                       {0x25u, 0x25u},\r
+                       {0x24u, 0x09u},\r
+                       {0x25u, 0x05u},\r
                        {0x26u, 0x08u},\r
-                       {0x27u, 0x0Cu},\r
-                       {0x2Cu, 0x60u},\r
-                       {0x2Fu, 0x04u},\r
+                       {0x27u, 0x04u},\r
+                       {0x2Cu, 0x28u},\r
+                       {0x2Du, 0x80u},\r
                        {0x34u, 0x02u},\r
                        {0x37u, 0x14u},\r
+                       {0x3Au, 0x40u},\r
+                       {0x3Bu, 0x40u},\r
                        {0x3Cu, 0x02u},\r
                        {0x3Du, 0x0Au},\r
                        {0x3Eu, 0x20u},\r
                        {0x3Fu, 0x40u},\r
-                       {0x44u, 0x40u},\r
-                       {0x46u, 0x40u},\r
-                       {0x59u, 0x80u},\r
+                       {0x5Au, 0x80u},\r
                        {0x62u, 0x40u},\r
-                       {0x64u, 0x08u},\r
-                       {0x66u, 0x06u},\r
-                       {0x67u, 0x02u},\r
+                       {0x66u, 0x86u},\r
+                       {0x67u, 0x04u},\r
+                       {0x6Cu, 0x01u},\r
                        {0x6Du, 0x95u},\r
-                       {0x74u, 0x80u},\r
-                       {0x75u, 0x21u},\r
-                       {0x76u, 0x10u},\r
-                       {0x82u, 0x02u},\r
-                       {0x88u, 0x08u},\r
-                       {0x89u, 0x20u},\r
-                       {0x8Bu, 0x40u},\r
+                       {0x6Eu, 0x01u},\r
+                       {0x75u, 0x55u},\r
+                       {0x80u, 0x04u},\r
+                       {0x84u, 0x48u},\r
+                       {0x86u, 0x02u},\r
+                       {0x89u, 0x40u},\r
+                       {0x8Cu, 0x10u},\r
                        {0x8Eu, 0x40u},\r
-                       {0x8Fu, 0x01u},\r
-                       {0x90u, 0x24u},\r
-                       {0x92u, 0x18u},\r
-                       {0x93u, 0x20u},\r
-                       {0x94u, 0x80u},\r
+                       {0x90u, 0x04u},\r
+                       {0x92u, 0x14u},\r
+                       {0x93u, 0xA0u},\r
+                       {0x94u, 0x02u},\r
                        {0x95u, 0x11u},\r
-                       {0x97u, 0x40u},\r
-                       {0x98u, 0x03u},\r
+                       {0x96u, 0x02u},\r
+                       {0x98u, 0x0Au},\r
+                       {0x99u, 0x80u},\r
                        {0x9Bu, 0x10u},\r
-                       {0x9Du, 0x25u},\r
-                       {0x9Eu, 0x11u},\r
-                       {0x9Fu, 0x06u},\r
+                       {0x9Du, 0x15u},\r
+                       {0x9Eu, 0x10u},\r
+                       {0x9Fu, 0x04u},\r
                        {0xA2u, 0x04u},\r
                        {0xA3u, 0x02u},\r
-                       {0xA4u, 0x05u},\r
-                       {0xA6u, 0x20u},\r
+                       {0xA4u, 0xC1u},\r
                        {0xA7u, 0x80u},\r
-                       {0xA8u, 0x40u},\r
-                       {0xA9u, 0x80u},\r
+                       {0xA9u, 0x04u},\r
                        {0xAAu, 0x40u},\r
-                       {0xB0u, 0x20u},\r
-                       {0xB2u, 0x04u},\r
-                       {0xB3u, 0x08u},\r
-                       {0xB6u, 0xC0u},\r
-                       {0xB7u, 0x20u},\r
-                       {0xC0u, 0xCFu},\r
-                       {0xC2u, 0xEEu},\r
-                       {0xC4u, 0x3Du},\r
-                       {0xCAu, 0xE0u},\r
+                       {0xB2u, 0x01u},\r
+                       {0xB6u, 0x80u},\r
+                       {0xB7u, 0x60u},\r
+                       {0xC0u, 0xAFu},\r
+                       {0xC2u, 0xEFu},\r
+                       {0xC4u, 0x5Cu},\r
+                       {0xCAu, 0x70u},\r
                        {0xCCu, 0xE0u},\r
                        {0xCEu, 0xF0u},\r
                        {0xD6u, 0x08u},\r
                        {0xD8u, 0xF8u},\r
-                       {0xE0u, 0xE0u},\r
-                       {0xE6u, 0xC0u},\r
-                       {0xEAu, 0xA2u},\r
-                       {0xECu, 0x20u},\r
-                       {0xEEu, 0x49u},\r
-                       {0xA8u, 0x21u},\r
+                       {0xE2u, 0x10u},\r
+                       {0xE6u, 0x60u},\r
+                       {0xE8u, 0x10u},\r
+                       {0xEAu, 0x22u},\r
+                       {0xEEu, 0x09u},\r
+                       {0x87u, 0x04u},\r
+                       {0x97u, 0x04u},\r
+                       {0xA8u, 0xA1u},\r
                        {0xAEu, 0x08u},\r
-                       {0xB2u, 0x20u},\r
-                       {0xB3u, 0x06u},\r
-                       {0xB5u, 0x80u},\r
-                       {0xB6u, 0x04u},\r
-                       {0xE8u, 0xA0u},\r
-                       {0xECu, 0x90u},\r
-                       {0xEEu, 0x02u},\r
+                       {0xB0u, 0x04u},\r
+                       {0xB2u, 0x80u},\r
+                       {0xB6u, 0x64u},\r
+                       {0xEAu, 0x20u},\r
+                       {0xECu, 0x70u},\r
                        {0x12u, 0x08u},\r
+                       {0x13u, 0x02u},\r
                        {0x16u, 0x80u},\r
                        {0x17u, 0x80u},\r
-                       {0x33u, 0x08u},\r
+                       {0x30u, 0x10u},\r
+                       {0x33u, 0x01u},\r
                        {0x35u, 0x01u},\r
-                       {0x36u, 0x80u},\r
+                       {0x36u, 0x20u},\r
+                       {0x38u, 0x08u},\r
                        {0x3Au, 0x80u},\r
-                       {0x3Bu, 0x01u},\r
-                       {0x3Fu, 0x18u},\r
+                       {0x3Cu, 0x02u},\r
+                       {0x3Fu, 0x10u},\r
                        {0x40u, 0x04u},\r
+                       {0x53u, 0x40u},\r
                        {0x59u, 0x08u},\r
-                       {0x5Au, 0x80u},\r
                        {0x5Eu, 0x02u},\r
                        {0x61u, 0x20u},\r
                        {0x65u, 0x20u},\r
-                       {0x81u, 0x08u},\r
-                       {0x83u, 0x01u},\r
+                       {0x6Bu, 0x03u},\r
                        {0x8Du, 0x20u},\r
-                       {0x8Eu, 0x01u},\r
-                       {0xC4u, 0xE0u},\r
-                       {0xCCu, 0xE0u},\r
+                       {0xC4u, 0xF0u},\r
+                       {0xCCu, 0xF0u},\r
                        {0xCEu, 0xF0u},\r
                        {0xD0u, 0x10u},\r
-                       {0xD4u, 0x80u},\r
+                       {0xD4u, 0x20u},\r
                        {0xD6u, 0xC0u},\r
                        {0xD8u, 0xC0u},\r
-                       {0xE2u, 0x80u},\r
-                       {0xE6u, 0x20u},\r
                        {0x33u, 0x11u},\r
                        {0x34u, 0x02u},\r
                        {0x37u, 0x80u},\r
                        {0x39u, 0x40u},\r
                        {0x51u, 0x08u},\r
                        {0x52u, 0x02u},\r
+                       {0x57u, 0x02u},\r
                        {0x5Du, 0x02u},\r
-                       {0x5Eu, 0x40u},\r
                        {0x82u, 0x02u},\r
-                       {0x83u, 0x08u},\r
+                       {0x84u, 0x02u},\r
                        {0x92u, 0x02u},\r
                        {0x94u, 0x04u},\r
-                       {0x96u, 0x80u},\r
+                       {0x97u, 0x80u},\r
                        {0x9Bu, 0x90u},\r
+                       {0x9Cu, 0x10u},\r
                        {0x9Du, 0x21u},\r
-                       {0xA6u, 0x80u},\r
-                       {0xA7u, 0x0Cu},\r
+                       {0xA4u, 0x01u},\r
+                       {0xA6u, 0x21u},\r
                        {0xAAu, 0x08u},\r
                        {0xABu, 0x10u},\r
                        {0xAEu, 0x01u},\r
                        {0xAFu, 0x10u},\r
+                       {0xB4u, 0x04u},\r
+                       {0xB5u, 0x08u},\r
                        {0xCCu, 0xF0u},\r
                        {0xCEu, 0x10u},\r
                        {0xD4u, 0xA0u},\r
                        {0xD6u, 0xA0u},\r
                        {0xE2u, 0x80u},\r
-                       {0xE6u, 0x80u},\r
+                       {0xE6u, 0x40u},\r
                        {0xEAu, 0x10u},\r
                        {0xEEu, 0x40u},\r
-                       {0x12u, 0x80u},\r
+                       {0x10u, 0x10u},\r
                        {0x33u, 0x80u},\r
                        {0x5Au, 0x02u},\r
-                       {0x89u, 0x08u},\r
                        {0x8Cu, 0x04u},\r
+                       {0x8Du, 0x08u},\r
+                       {0x8Eu, 0x01u},\r
                        {0x92u, 0x02u},\r
                        {0x94u, 0x04u},\r
-                       {0x96u, 0x80u},\r
-                       {0x9Cu, 0x02u},\r
+                       {0x95u, 0x40u},\r
+                       {0x97u, 0x80u},\r
+                       {0x9Cu, 0x10u},\r
                        {0x9Du, 0x23u},\r
                        {0x9Fu, 0x01u},\r
+                       {0xA4u, 0x01u},\r
                        {0xA5u, 0x08u},\r
-                       {0xA6u, 0x80u},\r
-                       {0xA7u, 0x04u},\r
-                       {0xA9u, 0x40u},\r
-                       {0xB6u, 0x40u},\r
+                       {0xA6u, 0x21u},\r
+                       {0xA7u, 0x02u},\r
                        {0xC4u, 0x10u},\r
                        {0xCCu, 0x10u},\r
                        {0xD6u, 0x40u},\r
-                       {0xEEu, 0x20u},\r
-                       {0x8Eu, 0x40u},\r
-                       {0x96u, 0x80u},\r
-                       {0x9Du, 0x01u},\r
+                       {0x8Bu, 0x40u},\r
+                       {0x97u, 0x80u},\r
+                       {0x9Du, 0x21u},\r
                        {0x9Fu, 0x01u},\r
-                       {0xA7u, 0x84u},\r
-                       {0xA8u, 0x02u},\r
+                       {0xA4u, 0x01u},\r
+                       {0xA6u, 0x20u},\r
+                       {0xA7u, 0x80u},\r
                        {0xA9u, 0x02u},\r
-                       {0xB1u, 0x20u},\r
-                       {0xEEu, 0xA0u},\r
-                       {0x08u, 0x02u},\r
-                       {0x09u, 0x20u},\r
-                       {0x0Du, 0x01u},\r
+                       {0xABu, 0x02u},\r
+                       {0xB5u, 0x40u},\r
+                       {0xEAu, 0x20u},\r
+                       {0xEEu, 0x20u},\r
+                       {0x09u, 0x80u},\r
+                       {0x0Bu, 0x40u},\r
+                       {0x0Fu, 0x20u},\r
                        {0x10u, 0x80u},\r
                        {0x17u, 0x08u},\r
-                       {0x51u, 0x10u},\r
-                       {0x54u, 0x40u},\r
-                       {0x5Bu, 0x80u},\r
+                       {0x51u, 0x02u},\r
+                       {0x53u, 0x10u},\r
+                       {0x57u, 0x08u},\r
                        {0x5Du, 0x80u},\r
                        {0xC2u, 0x0Eu},\r
                        {0xC4u, 0x0Cu},\r
                        {0xD4u, 0x07u},\r
                        {0xD6u, 0x04u},\r
-                       {0x03u, 0x88u},\r
+                       {0x00u, 0x20u},\r
+                       {0x01u, 0x08u},\r
                        {0x04u, 0x10u},\r
-                       {0x05u, 0x02u},\r
+                       {0x07u, 0x40u},\r
+                       {0x08u, 0x02u},\r
                        {0x0Au, 0x01u},\r
-                       {0x0Bu, 0x80u},\r
                        {0x0Cu, 0x22u},\r
                        {0x80u, 0x02u},\r
-                       {0x8Bu, 0x80u},\r
-                       {0x91u, 0x02u},\r
-                       {0x95u, 0x20u},\r
-                       {0x98u, 0x02u},\r
+                       {0x86u, 0x40u},\r
+                       {0x8Fu, 0x40u},\r
+                       {0x93u, 0x40u},\r
+                       {0x97u, 0x20u},\r
                        {0x9Bu, 0x08u},\r
                        {0x9Du, 0x80u},\r
-                       {0x9Fu, 0x80u},\r
-                       {0xA1u, 0x20u},\r
-                       {0xA4u, 0x40u},\r
+                       {0xA1u, 0x80u},\r
+                       {0xA3u, 0x10u},\r
+                       {0xA5u, 0x02u},\r
+                       {0xA7u, 0x08u},\r
                        {0xB0u, 0x80u},\r
                        {0xC0u, 0x0Fu},\r
                        {0xC2u, 0x0Fu},\r
-                       {0xE4u, 0x04u},\r
+                       {0xE2u, 0x08u},\r
                        {0xEEu, 0x01u},\r
-                       {0x88u, 0x40u},\r
+                       {0x87u, 0x08u},\r
+                       {0x88u, 0x10u},\r
                        {0x8Du, 0x80u},\r
-                       {0x90u, 0x10u},\r
-                       {0x91u, 0x02u},\r
-                       {0x93u, 0x80u},\r
-                       {0x95u, 0x20u},\r
-                       {0x97u, 0x02u},\r
+                       {0x93u, 0x40u},\r
+                       {0x97u, 0x20u},\r
                        {0x98u, 0x02u},\r
+                       {0x99u, 0x08u},\r
                        {0x9Bu, 0x08u},\r
                        {0x9Du, 0x80u},\r
-                       {0xA1u, 0x20u},\r
-                       {0xA3u, 0x80u},\r
-                       {0xA4u, 0x40u},\r
-                       {0xA8u, 0x20u},\r
-                       {0xABu, 0x09u},\r
-                       {0xADu, 0x02u},\r
+                       {0xA0u, 0x10u},\r
+                       {0xA1u, 0x80u},\r
+                       {0xA3u, 0x10u},\r
+                       {0xA5u, 0x02u},\r
+                       {0xA6u, 0x40u},\r
+                       {0xA7u, 0x08u},\r
+                       {0xA8u, 0x30u},\r
                        {0xB2u, 0x01u},\r
-                       {0xE4u, 0x06u},\r
+                       {0xE4u, 0x02u},\r
+                       {0xE6u, 0x01u},\r
                        {0xEEu, 0x01u},\r
                        {0x09u, 0x08u},\r
                        {0x0Bu, 0x02u},\r
-                       {0x0Fu, 0x22u},\r
-                       {0x85u, 0x10u},\r
-                       {0x88u, 0x02u},\r
-                       {0x91u, 0x02u},\r
-                       {0x95u, 0x20u},\r
-                       {0x97u, 0x02u},\r
-                       {0x98u, 0x02u},\r
-                       {0xA1u, 0x20u},\r
-                       {0xA7u, 0x10u},\r
-                       {0xABu, 0x98u},\r
-                       {0xAFu, 0x40u},\r
-                       {0xB4u, 0x10u},\r
+                       {0x0Eu, 0x80u},\r
+                       {0x0Fu, 0x02u},\r
+                       {0x81u, 0x02u},\r
+                       {0x83u, 0x10u},\r
+                       {0x87u, 0x10u},\r
+                       {0x97u, 0x22u},\r
+                       {0xA1u, 0x80u},\r
+                       {0xA3u, 0x10u},\r
+                       {0xA5u, 0x02u},\r
+                       {0xA6u, 0x40u},\r
+                       {0xA9u, 0x08u},\r
+                       {0xABu, 0x08u},\r
+                       {0xB3u, 0x40u},\r
+                       {0xB4u, 0x02u},\r
+                       {0xB7u, 0x01u},\r
                        {0xC2u, 0x0Fu},\r
-                       {0xE2u, 0x04u},\r
-                       {0xEAu, 0x08u},\r
-                       {0x83u, 0x04u},\r
+                       {0xEAu, 0x0Eu},\r
+                       {0x84u, 0x01u},\r
                        {0x8Du, 0x01u},\r
-                       {0x9Du, 0x01u},\r
-                       {0xA7u, 0x04u},\r
+                       {0x8Eu, 0x20u},\r
+                       {0x9Du, 0x21u},\r
+                       {0xA4u, 0x01u},\r
+                       {0xA6u, 0x20u},\r
                        {0xAFu, 0x81u},\r
-                       {0xE6u, 0x20u},\r
+                       {0xE6u, 0x10u},\r
                        {0xEAu, 0x40u},\r
                        {0xEEu, 0x10u},\r
-                       {0x05u, 0x02u},\r
+                       {0x07u, 0x10u},\r
                        {0x57u, 0x08u},\r
                        {0x5Bu, 0x20u},\r
-                       {0x81u, 0x02u},\r
+                       {0x83u, 0x10u},\r
                        {0x87u, 0x08u},\r
                        {0x8Bu, 0x20u},\r
+                       {0xB1u, 0x20u},\r
                        {0xC0u, 0x20u},\r
                        {0xD4u, 0xC0u},\r
-                       {0xE4u, 0x20u},\r
+                       {0xE0u, 0x20u},\r
                        {0xE6u, 0x40u},\r
-                       {0x91u, 0x02u},\r
                        {0x9Fu, 0x40u},\r
-                       {0xA1u, 0x20u},\r
+                       {0xA1u, 0x80u},\r
                        {0xABu, 0x40u},\r
                        {0xADu, 0x08u},\r
                        {0xAFu, 0x01u},\r
                        {0x03u, 0x40u},\r
                        {0x9Fu, 0x40u},\r
-                       {0xADu, 0x01u},\r
-                       {0xB5u, 0x20u},\r
+                       {0xB5u, 0x80u},\r
                        {0xC0u, 0x08u},\r
-                       {0xEEu, 0x02u},\r
+                       {0xEAu, 0x08u},\r
                        {0x10u, 0x03u},\r
                        {0x11u, 0x01u},\r
                        {0x1Au, 0x03u},\r
                        {0x1Bu, 0x01u},\r
                        {0x1Cu, 0x03u},\r
                        {0x1Du, 0x01u},\r
-                       {0x00u, 0xFDu},\r
+                       {0x00u, 0xFFu},\r
                        {0x01u, 0xBFu},\r
                        {0x02u, 0x2Au},\r
                        {0x10u, 0x95u},\r
@@ -2097,7 +2108,7 @@ void cyfitter_cfg(void)
                        uint16 size;\r
                } CYPACKED_ATTR cfg_memcpy_t;\r
 \r
-               static const cfg_memset_t CYCODE cfg_memset_list [] = {\r
+               static const cfg_memset_t CYCODE cfg_memset_list[] = {\r
                        /* address, size */\r
                        {(void CYFAR *)(CYREG_TMR0_CFG0), 12u},\r
                        {(void CYFAR *)(CYDEV_UCFG_B0_P0_U0_BASE), 4096u},\r
@@ -2109,11 +2120,11 @@ void cyfitter_cfg(void)
 \r
                /* UDB_1_0_0_CONFIG Address: CYDEV_UCFG_B1_P2_U0_BASE Size (bytes): 128 */\r
                static const uint8 CYCODE BS_UDB_1_0_0_CONFIG_VAL[] = {\r
-                       0x6Cu, 0x00u, 0x00u, 0x00u, 0x71u, 0xC0u, 0x82u, 0x04u, 0x00u, 0xC0u, 0x00u, 0x08u, 0x2Cu, 0xC0u, 0x40u, 0x01u, \r
-                       0xC0u, 0x90u, 0x2Fu, 0x40u, 0xA4u, 0x00u, 0x40u, 0x60u, 0x64u, 0x00u, 0x08u, 0xFFu, 0x6Cu, 0xC0u, 0x00u, 0x02u, \r
-                       0x00u, 0x7Fu, 0x00u, 0x80u, 0x91u, 0x80u, 0x4Eu, 0x00u, 0x40u, 0x1Fu, 0x2Cu, 0x20u, 0x08u, 0x00u, 0x10u, 0x9Fu, \r
+                       0x6Cu, 0xC0u, 0x00u, 0x01u, 0x91u, 0xC0u, 0x4Eu, 0x04u, 0x71u, 0xC0u, 0x82u, 0x08u, 0x2Cu, 0x00u, 0x40u, 0xFFu, \r
+                       0xC0u, 0x90u, 0x2Fu, 0x40u, 0xA4u, 0x00u, 0x40u, 0x60u, 0x64u, 0x80u, 0x08u, 0x00u, 0x6Cu, 0xC0u, 0x00u, 0x02u, \r
+                       0x08u, 0x7Fu, 0x10u, 0x80u, 0x00u, 0x00u, 0x00u, 0x00u, 0x40u, 0x1Fu, 0x2Cu, 0x20u, 0x00u, 0x00u, 0x00u, 0x9Fu, \r
                        0x31u, 0xFFu, 0xC0u, 0x00u, 0x0Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x0Bu, 0x00u, 0x00u, 0x00u, 0x00u, 0x01u, \r
-                       0x64u, 0x02u, 0x50u, 0x00u, 0x03u, 0x0Eu, 0xDBu, 0xCFu, 0x3Du, 0xFFu, 0xFFu, 0xFFu, 0x22u, 0x00u, 0xF0u, 0x08u, \r
+                       0x64u, 0x02u, 0x50u, 0x00u, 0x03u, 0xCEu, 0xDBu, 0xF0u, 0x2Fu, 0xFFu, 0xFFu, 0xFFu, 0x22u, 0x00u, 0xF0u, 0x08u, \r
                        0x04u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x2Cu, 0x04u, 0x04u, 0x04u, 0x04u, 0x00u, 0x00u, 0x00u, 0x01u, \r
                        0x00u, 0x00u, 0xC0u, 0x00u, 0x40u, 0x01u, 0x10u, 0x11u, 0xC0u, 0x01u, 0x00u, 0x11u, 0x40u, 0x01u, 0x40u, 0x01u, \r
                        0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u};\r

diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.h b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.h
index 72521357129e3a5425f7dde53296ab03568cd940..3a40dcb89c8df23cf00f847f24ef27580ddd5c32 100755 (executable)
--- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.h
+++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.h
@@ -1,14 +1,14 @@
 /*******************************************************************************\r
 * File Name: cyfitter_cfg.h\r
 * \r
-* PSoC Creator  4.0 Update 1\r
+* PSoC Creator  4.1\r
 *\r
 * Description:\r
-* This file provides basic startup and mux configration settings\r
+* This file provides basic startup and mux configuration settings\r
 * This file is automatically generated by PSoC Creator.\r
 *\r
 ********************************************************************************\r
-* Copyright (c) 2007-2016 Cypress Semiconductor.  All rights reserved.\r
+* Copyright (c) 2007-2017 Cypress Semiconductor.  All rights reserved.\r
 * You may use this file only in accordance with the license, terms, conditions, \r
 * disclaimers, and limitations in the end user license agreement accompanying \r
 * the software package with which this file was provided.\r

diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfittergnu.inc b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfittergnu.inc
index 4d4b2043a13457199b9010bb96766d5253328b2e..33a4bd884e883d84430ab89558e3953d3ef582a6 100755 (executable)
--- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfittergnu.inc
+++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfittergnu.inc
@@ -1,8 +1,52 @@
+/*******************************************************************************\r
+* File Name: cyfittergnu.inc\r
+* \r
+* PSoC Creator  4.1\r
+*\r
+* Description:\r
+* \r
+* This file is automatically generated by PSoC Creator.\r
+*\r
+********************************************************************************\r
+* Copyright (c) 2007-2017 Cypress Semiconductor.  All rights reserved.\r
+* You may use this file only in accordance with the license, terms, conditions, \r
+* disclaimers, and limitations in the end user license agreement accompanying \r
+* the software package with which this file was provided.\r
+********************************************************************************/\r
+\r
 .ifndef INCLUDED_CYFITTERGNU_INC\r
 .set INCLUDED_CYFITTERGNU_INC, 1\r
 .include "cydevicegnu.inc"\r
 .include "cydevicegnu_trm.inc"\r
 \r
+/* Debug_Timer_Interrupt */\r
+.set Debug_Timer_Interrupt__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
+.set Debug_Timer_Interrupt__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
+.set Debug_Timer_Interrupt__INTC_MASK, 0x01\r
+.set Debug_Timer_Interrupt__INTC_NUMBER, 0\r
+.set Debug_Timer_Interrupt__INTC_PRIOR_NUM, 7\r
+.set Debug_Timer_Interrupt__INTC_PRIOR_REG, CYREG_NVIC_PRI_0\r
+.set Debug_Timer_Interrupt__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
+.set Debug_Timer_Interrupt__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
+\r
+/* Debug_Timer_TimerHW */\r
+.set Debug_Timer_TimerHW__CAP0, CYREG_TMR0_CAP0\r
+.set Debug_Timer_TimerHW__CAP1, CYREG_TMR0_CAP1\r
+.set Debug_Timer_TimerHW__CFG0, CYREG_TMR0_CFG0\r
+.set Debug_Timer_TimerHW__CFG1, CYREG_TMR0_CFG1\r
+.set Debug_Timer_TimerHW__CFG2, CYREG_TMR0_CFG2\r
+.set Debug_Timer_TimerHW__CNT_CMP0, CYREG_TMR0_CNT_CMP0\r
+.set Debug_Timer_TimerHW__CNT_CMP1, CYREG_TMR0_CNT_CMP1\r
+.set Debug_Timer_TimerHW__PER0, CYREG_TMR0_PER0\r
+.set Debug_Timer_TimerHW__PER1, CYREG_TMR0_PER1\r
+.set Debug_Timer_TimerHW__PM_ACT_CFG, CYREG_PM_ACT_CFG3\r
+.set Debug_Timer_TimerHW__PM_ACT_MSK, 0x01\r
+.set Debug_Timer_TimerHW__PM_STBY_CFG, CYREG_PM_STBY_CFG3\r
+.set Debug_Timer_TimerHW__PM_STBY_MSK, 0x01\r
+.set Debug_Timer_TimerHW__RT0, CYREG_TMR0_RT0\r
+.set Debug_Timer_TimerHW__RT1, CYREG_TMR0_RT1\r
+.set Debug_Timer_TimerHW__SR0, CYREG_TMR0_SR0\r
+\r
 /* LED1 */\r
 .set LED1__0__INTTYPE, CYREG_PICU12_INTTYPE3\r
 .set LED1__0__MASK, 0x08\r
@@ -36,2463 +80,810 @@
 .set LED1__SIO_REG_HIFREQ, CYREG_PRT12_SIO_REG_HIFREQ\r
 .set LED1__SLW, CYREG_PRT12_SLW\r
 \r
-/* SD_CD */\r
-.set SD_CD__0__INTTYPE, CYREG_PICU3_INTTYPE6\r
-.set SD_CD__0__MASK, 0x40\r
-.set SD_CD__0__PC, CYREG_PRT3_PC6\r
-.set SD_CD__0__PORT, 3\r
-.set SD_CD__0__SHIFT, 6\r
-.set SD_CD__AG, CYREG_PRT3_AG\r
-.set SD_CD__AMUX, CYREG_PRT3_AMUX\r
-.set SD_CD__BIE, CYREG_PRT3_BIE\r
-.set SD_CD__BIT_MASK, CYREG_PRT3_BIT_MASK\r
-.set SD_CD__BYP, CYREG_PRT3_BYP\r
-.set SD_CD__CTL, CYREG_PRT3_CTL\r
-.set SD_CD__DM0, CYREG_PRT3_DM0\r
-.set SD_CD__DM1, CYREG_PRT3_DM1\r
-.set SD_CD__DM2, CYREG_PRT3_DM2\r
-.set SD_CD__DR, CYREG_PRT3_DR\r
-.set SD_CD__INP_DIS, CYREG_PRT3_INP_DIS\r
-.set SD_CD__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU3_BASE\r
-.set SD_CD__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG\r
-.set SD_CD__LCD_EN, CYREG_PRT3_LCD_EN\r
-.set SD_CD__MASK, 0x40\r
-.set SD_CD__PORT, 3\r
-.set SD_CD__PRT, CYREG_PRT3_PRT\r
-.set SD_CD__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL\r
-.set SD_CD__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN\r
-.set SD_CD__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0\r
-.set SD_CD__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1\r
-.set SD_CD__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0\r
-.set SD_CD__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1\r
-.set SD_CD__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT\r
-.set SD_CD__PS, CYREG_PRT3_PS\r
-.set SD_CD__SHIFT, 6\r
-.set SD_CD__SLW, CYREG_PRT3_SLW\r
-\r
-/* SD_CS */\r
-.set SD_CS__0__INTTYPE, CYREG_PICU3_INTTYPE4\r
-.set SD_CS__0__MASK, 0x10\r
-.set SD_CS__0__PC, CYREG_PRT3_PC4\r
-.set SD_CS__0__PORT, 3\r
-.set SD_CS__0__SHIFT, 4\r
-.set SD_CS__AG, CYREG_PRT3_AG\r
-.set SD_CS__AMUX, CYREG_PRT3_AMUX\r
-.set SD_CS__BIE, CYREG_PRT3_BIE\r
-.set SD_CS__BIT_MASK, CYREG_PRT3_BIT_MASK\r
-.set SD_CS__BYP, CYREG_PRT3_BYP\r
-.set SD_CS__CTL, CYREG_PRT3_CTL\r
-.set SD_CS__DM0, CYREG_PRT3_DM0\r
-.set SD_CS__DM1, CYREG_PRT3_DM1\r
-.set SD_CS__DM2, CYREG_PRT3_DM2\r
-.set SD_CS__DR, CYREG_PRT3_DR\r
-.set SD_CS__INP_DIS, CYREG_PRT3_INP_DIS\r
-.set SD_CS__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU3_BASE\r
-.set SD_CS__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG\r
-.set SD_CS__LCD_EN, CYREG_PRT3_LCD_EN\r
-.set SD_CS__MASK, 0x10\r
-.set SD_CS__PORT, 3\r
-.set SD_CS__PRT, CYREG_PRT3_PRT\r
-.set SD_CS__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL\r
-.set SD_CS__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN\r
-.set SD_CS__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0\r
-.set SD_CS__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1\r
-.set SD_CS__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0\r
-.set SD_CS__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1\r
-.set SD_CS__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT\r
-.set SD_CS__PS, CYREG_PRT3_PS\r
-.set SD_CS__SHIFT, 4\r
-.set SD_CS__SLW, CYREG_PRT3_SLW\r
-\r
-/* USBFS_arb_int */\r
-.set USBFS_arb_int__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
-.set USBFS_arb_int__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
-.set USBFS_arb_int__INTC_MASK, 0x400000\r
-.set USBFS_arb_int__INTC_NUMBER, 22\r
-.set USBFS_arb_int__INTC_PRIOR_NUM, 6\r
-.set USBFS_arb_int__INTC_PRIOR_REG, CYREG_NVIC_PRI_22\r
-.set USBFS_arb_int__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
-.set USBFS_arb_int__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
+/* SCSI_CLK */\r
+.set SCSI_CLK__CFG0, CYREG_CLKDIST_DCFG1_CFG0\r
+.set SCSI_CLK__CFG1, CYREG_CLKDIST_DCFG1_CFG1\r
+.set SCSI_CLK__CFG2, CYREG_CLKDIST_DCFG1_CFG2\r
+.set SCSI_CLK__CFG2_SRC_SEL_MASK, 0x07\r
+.set SCSI_CLK__INDEX, 0x01\r
+.set SCSI_CLK__PM_ACT_CFG, CYREG_PM_ACT_CFG2\r
+.set SCSI_CLK__PM_ACT_MSK, 0x02\r
+.set SCSI_CLK__PM_STBY_CFG, CYREG_PM_STBY_CFG2\r
+.set SCSI_CLK__PM_STBY_MSK, 0x02\r
 \r
-/* USBFS_bus_reset */\r
-.set USBFS_bus_reset__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
-.set USBFS_bus_reset__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
-.set USBFS_bus_reset__INTC_MASK, 0x800000\r
-.set USBFS_bus_reset__INTC_NUMBER, 23\r
-.set USBFS_bus_reset__INTC_PRIOR_NUM, 7\r
-.set USBFS_bus_reset__INTC_PRIOR_REG, CYREG_NVIC_PRI_23\r
-.set USBFS_bus_reset__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
-.set USBFS_bus_reset__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
+/* SCSI_CTL_PHASE */\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK, 0x01\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS, 0\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK, 0x02\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS, 1\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB05_06_ACTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB05_06_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB05_06_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB05_06_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB05_06_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB05_06_MSK\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB05_06_MSK\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB05_06_MSK\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB05_06_MSK\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK, 0x04\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS, 2\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB05_ACTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB05_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB05_ST_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB05_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB05_ST_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK, 0x07\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB05_MSK_ACTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB05_MSK_ACTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB05_MSK\r
 \r
-/* USBFS_Dm */\r
-.set USBFS_Dm__0__INTTYPE, CYREG_PICU15_INTTYPE7\r
-.set USBFS_Dm__0__MASK, 0x80\r
-.set USBFS_Dm__0__PC, CYREG_IO_PC_PRT15_7_6_PC1\r
-.set USBFS_Dm__0__PORT, 15\r
-.set USBFS_Dm__0__SHIFT, 7\r
-.set USBFS_Dm__AG, CYREG_PRT15_AG\r
-.set USBFS_Dm__AMUX, CYREG_PRT15_AMUX\r
-.set USBFS_Dm__BIE, CYREG_PRT15_BIE\r
-.set USBFS_Dm__BIT_MASK, CYREG_PRT15_BIT_MASK\r
-.set USBFS_Dm__BYP, CYREG_PRT15_BYP\r
-.set USBFS_Dm__CTL, CYREG_PRT15_CTL\r
-.set USBFS_Dm__DM0, CYREG_PRT15_DM0\r
-.set USBFS_Dm__DM1, CYREG_PRT15_DM1\r
-.set USBFS_Dm__DM2, CYREG_PRT15_DM2\r
-.set USBFS_Dm__DR, CYREG_PRT15_DR\r
-.set USBFS_Dm__INP_DIS, CYREG_PRT15_INP_DIS\r
-.set USBFS_Dm__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU15_BASE\r
-.set USBFS_Dm__LCD_COM_SEG, CYREG_PRT15_LCD_COM_SEG\r
-.set USBFS_Dm__LCD_EN, CYREG_PRT15_LCD_EN\r
-.set USBFS_Dm__MASK, 0x80\r
-.set USBFS_Dm__PORT, 15\r
-.set USBFS_Dm__PRT, CYREG_PRT15_PRT\r
-.set USBFS_Dm__PRTDSI__CAPS_SEL, CYREG_PRT15_CAPS_SEL\r
-.set USBFS_Dm__PRTDSI__DBL_SYNC_IN, CYREG_PRT15_DBL_SYNC_IN\r
-.set USBFS_Dm__PRTDSI__OE_SEL0, CYREG_PRT15_OE_SEL0\r
-.set USBFS_Dm__PRTDSI__OE_SEL1, CYREG_PRT15_OE_SEL1\r
-.set USBFS_Dm__PRTDSI__OUT_SEL0, CYREG_PRT15_OUT_SEL0\r
-.set USBFS_Dm__PRTDSI__OUT_SEL1, CYREG_PRT15_OUT_SEL1\r
-.set USBFS_Dm__PRTDSI__SYNC_OUT, CYREG_PRT15_SYNC_OUT\r
-.set USBFS_Dm__PS, CYREG_PRT15_PS\r
-.set USBFS_Dm__SHIFT, 7\r
-.set USBFS_Dm__SLW, CYREG_PRT15_SLW\r
+/* SCSI_Filtered */\r
+.set SCSI_Filtered_sts_sts_reg__0__MASK, 0x01\r
+.set SCSI_Filtered_sts_sts_reg__0__POS, 0\r
+.set SCSI_Filtered_sts_sts_reg__1__MASK, 0x02\r
+.set SCSI_Filtered_sts_sts_reg__1__POS, 1\r
+.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB02_03_ACTL\r
+.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB02_03_ST\r
+.set SCSI_Filtered_sts_sts_reg__2__MASK, 0x04\r
+.set SCSI_Filtered_sts_sts_reg__2__POS, 2\r
+.set SCSI_Filtered_sts_sts_reg__3__MASK, 0x08\r
+.set SCSI_Filtered_sts_sts_reg__3__POS, 3\r
+.set SCSI_Filtered_sts_sts_reg__4__MASK, 0x10\r
+.set SCSI_Filtered_sts_sts_reg__4__POS, 4\r
+.set SCSI_Filtered_sts_sts_reg__MASK, 0x1F\r
+.set SCSI_Filtered_sts_sts_reg__MASK_REG, CYREG_B0_UDB02_MSK\r
+.set SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB02_ACTL\r
+.set SCSI_Filtered_sts_sts_reg__STATUS_REG, CYREG_B0_UDB02_ST\r
 \r
-/* USBFS_Dp */\r
-.set USBFS_Dp__0__INTTYPE, CYREG_PICU15_INTTYPE6\r
-.set USBFS_Dp__0__MASK, 0x40\r
-.set USBFS_Dp__0__PC, CYREG_IO_PC_PRT15_7_6_PC0\r
-.set USBFS_Dp__0__PORT, 15\r
-.set USBFS_Dp__0__SHIFT, 6\r
-.set USBFS_Dp__AG, CYREG_PRT15_AG\r
-.set USBFS_Dp__AMUX, CYREG_PRT15_AMUX\r
-.set USBFS_Dp__BIE, CYREG_PRT15_BIE\r
-.set USBFS_Dp__BIT_MASK, CYREG_PRT15_BIT_MASK\r
-.set USBFS_Dp__BYP, CYREG_PRT15_BYP\r
-.set USBFS_Dp__CTL, CYREG_PRT15_CTL\r
-.set USBFS_Dp__DM0, CYREG_PRT15_DM0\r
-.set USBFS_Dp__DM1, CYREG_PRT15_DM1\r
-.set USBFS_Dp__DM2, CYREG_PRT15_DM2\r
-.set USBFS_Dp__DR, CYREG_PRT15_DR\r
-.set USBFS_Dp__INP_DIS, CYREG_PRT15_INP_DIS\r
-.set USBFS_Dp__INTSTAT, CYREG_PICU15_INTSTAT\r
-.set USBFS_Dp__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU15_BASE\r
-.set USBFS_Dp__LCD_COM_SEG, CYREG_PRT15_LCD_COM_SEG\r
-.set USBFS_Dp__LCD_EN, CYREG_PRT15_LCD_EN\r
-.set USBFS_Dp__MASK, 0x40\r
-.set USBFS_Dp__PORT, 15\r
-.set USBFS_Dp__PRT, CYREG_PRT15_PRT\r
-.set USBFS_Dp__PRTDSI__CAPS_SEL, CYREG_PRT15_CAPS_SEL\r
-.set USBFS_Dp__PRTDSI__DBL_SYNC_IN, CYREG_PRT15_DBL_SYNC_IN\r
-.set USBFS_Dp__PRTDSI__OE_SEL0, CYREG_PRT15_OE_SEL0\r
-.set USBFS_Dp__PRTDSI__OE_SEL1, CYREG_PRT15_OE_SEL1\r
-.set USBFS_Dp__PRTDSI__OUT_SEL0, CYREG_PRT15_OUT_SEL0\r
-.set USBFS_Dp__PRTDSI__OUT_SEL1, CYREG_PRT15_OUT_SEL1\r
-.set USBFS_Dp__PRTDSI__SYNC_OUT, CYREG_PRT15_SYNC_OUT\r
-.set USBFS_Dp__PS, CYREG_PRT15_PS\r
-.set USBFS_Dp__SHIFT, 6\r
-.set USBFS_Dp__SLW, CYREG_PRT15_SLW\r
-.set USBFS_Dp__SNAP, CYREG_PICU_15_SNAP_15\r
+/* SCSI_Glitch_Ctl */\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK, 0x01\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS, 0\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB07_08_ACTL\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB07_08_CTL\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB07_08_CTL\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB07_08_CTL\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB07_08_CTL\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB07_08_MSK\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB07_08_MSK\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB07_08_MSK\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB07_08_MSK\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB07_ACTL\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB07_CTL\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB07_ST_CTL\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB07_CTL\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB07_ST_CTL\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK, 0x01\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB07_MSK_ACTL\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB07_MSK_ACTL\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB07_MSK\r
 \r
-/* USBFS_dp_int */\r
-.set USBFS_dp_int__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
-.set USBFS_dp_int__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
-.set USBFS_dp_int__INTC_MASK, 0x1000\r
-.set USBFS_dp_int__INTC_NUMBER, 12\r
-.set USBFS_dp_int__INTC_PRIOR_NUM, 7\r
-.set USBFS_dp_int__INTC_PRIOR_REG, CYREG_NVIC_PRI_12\r
-.set USBFS_dp_int__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
-.set USBFS_dp_int__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
-\r
-/* USBFS_ep_0 */\r
-.set USBFS_ep_0__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
-.set USBFS_ep_0__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
-.set USBFS_ep_0__INTC_MASK, 0x1000000\r
-.set USBFS_ep_0__INTC_NUMBER, 24\r
-.set USBFS_ep_0__INTC_PRIOR_NUM, 7\r
-.set USBFS_ep_0__INTC_PRIOR_REG, CYREG_NVIC_PRI_24\r
-.set USBFS_ep_0__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
-.set USBFS_ep_0__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
-\r
-/* USBFS_ep_1 */\r
-.set USBFS_ep_1__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
-.set USBFS_ep_1__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
-.set USBFS_ep_1__INTC_MASK, 0x80\r
-.set USBFS_ep_1__INTC_NUMBER, 7\r
-.set USBFS_ep_1__INTC_PRIOR_NUM, 7\r
-.set USBFS_ep_1__INTC_PRIOR_REG, CYREG_NVIC_PRI_7\r
-.set USBFS_ep_1__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
-.set USBFS_ep_1__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
-\r
-/* USBFS_ep_2 */\r
-.set USBFS_ep_2__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
-.set USBFS_ep_2__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
-.set USBFS_ep_2__INTC_MASK, 0x100\r
-.set USBFS_ep_2__INTC_NUMBER, 8\r
-.set USBFS_ep_2__INTC_PRIOR_NUM, 7\r
-.set USBFS_ep_2__INTC_PRIOR_REG, CYREG_NVIC_PRI_8\r
-.set USBFS_ep_2__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
-.set USBFS_ep_2__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
-\r
-/* USBFS_ep_3 */\r
-.set USBFS_ep_3__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
-.set USBFS_ep_3__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
-.set USBFS_ep_3__INTC_MASK, 0x200\r
-.set USBFS_ep_3__INTC_NUMBER, 9\r
-.set USBFS_ep_3__INTC_PRIOR_NUM, 7\r
-.set USBFS_ep_3__INTC_PRIOR_REG, CYREG_NVIC_PRI_9\r
-.set USBFS_ep_3__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
-.set USBFS_ep_3__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
-\r
-/* USBFS_ep_4 */\r
-.set USBFS_ep_4__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
-.set USBFS_ep_4__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
-.set USBFS_ep_4__INTC_MASK, 0x400\r
-.set USBFS_ep_4__INTC_NUMBER, 10\r
-.set USBFS_ep_4__INTC_PRIOR_NUM, 7\r
-.set USBFS_ep_4__INTC_PRIOR_REG, CYREG_NVIC_PRI_10\r
-.set USBFS_ep_4__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
-.set USBFS_ep_4__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
-\r
-/* USBFS_sof_int */\r
-.set USBFS_sof_int__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
-.set USBFS_sof_int__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
-.set USBFS_sof_int__INTC_MASK, 0x200000\r
-.set USBFS_sof_int__INTC_NUMBER, 21\r
-.set USBFS_sof_int__INTC_PRIOR_NUM, 7\r
-.set USBFS_sof_int__INTC_PRIOR_REG, CYREG_NVIC_PRI_21\r
-.set USBFS_sof_int__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
-.set USBFS_sof_int__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
-\r
-/* USBFS_USB */\r
-.set USBFS_USB__ARB_CFG, CYREG_USB_ARB_CFG\r
-.set USBFS_USB__ARB_EP1_CFG, CYREG_USB_ARB_EP1_CFG\r
-.set USBFS_USB__ARB_EP1_INT_EN, CYREG_USB_ARB_EP1_INT_EN\r
-.set USBFS_USB__ARB_EP1_SR, CYREG_USB_ARB_EP1_SR\r
-.set USBFS_USB__ARB_EP2_CFG, CYREG_USB_ARB_EP2_CFG\r
-.set USBFS_USB__ARB_EP2_INT_EN, CYREG_USB_ARB_EP2_INT_EN\r
-.set USBFS_USB__ARB_EP2_SR, CYREG_USB_ARB_EP2_SR\r
-.set USBFS_USB__ARB_EP3_CFG, CYREG_USB_ARB_EP3_CFG\r
-.set USBFS_USB__ARB_EP3_INT_EN, CYREG_USB_ARB_EP3_INT_EN\r
-.set USBFS_USB__ARB_EP3_SR, CYREG_USB_ARB_EP3_SR\r
-.set USBFS_USB__ARB_EP4_CFG, CYREG_USB_ARB_EP4_CFG\r
-.set USBFS_USB__ARB_EP4_INT_EN, CYREG_USB_ARB_EP4_INT_EN\r
-.set USBFS_USB__ARB_EP4_SR, CYREG_USB_ARB_EP4_SR\r
-.set USBFS_USB__ARB_EP5_CFG, CYREG_USB_ARB_EP5_CFG\r
-.set USBFS_USB__ARB_EP5_INT_EN, CYREG_USB_ARB_EP5_INT_EN\r
-.set USBFS_USB__ARB_EP5_SR, CYREG_USB_ARB_EP5_SR\r
-.set USBFS_USB__ARB_EP6_CFG, CYREG_USB_ARB_EP6_CFG\r
-.set USBFS_USB__ARB_EP6_INT_EN, CYREG_USB_ARB_EP6_INT_EN\r
-.set USBFS_USB__ARB_EP6_SR, CYREG_USB_ARB_EP6_SR\r
-.set USBFS_USB__ARB_EP7_CFG, CYREG_USB_ARB_EP7_CFG\r
-.set USBFS_USB__ARB_EP7_INT_EN, CYREG_USB_ARB_EP7_INT_EN\r
-.set USBFS_USB__ARB_EP7_SR, CYREG_USB_ARB_EP7_SR\r
-.set USBFS_USB__ARB_EP8_CFG, CYREG_USB_ARB_EP8_CFG\r
-.set USBFS_USB__ARB_EP8_INT_EN, CYREG_USB_ARB_EP8_INT_EN\r
-.set USBFS_USB__ARB_EP8_SR, CYREG_USB_ARB_EP8_SR\r
-.set USBFS_USB__ARB_INT_EN, CYREG_USB_ARB_INT_EN\r
-.set USBFS_USB__ARB_INT_SR, CYREG_USB_ARB_INT_SR\r
-.set USBFS_USB__ARB_RW1_DR, CYREG_USB_ARB_RW1_DR\r
-.set USBFS_USB__ARB_RW1_RA, CYREG_USB_ARB_RW1_RA\r
-.set USBFS_USB__ARB_RW1_RA_MSB, CYREG_USB_ARB_RW1_RA_MSB\r
-.set USBFS_USB__ARB_RW1_WA, CYREG_USB_ARB_RW1_WA\r
-.set USBFS_USB__ARB_RW1_WA_MSB, CYREG_USB_ARB_RW1_WA_MSB\r
-.set USBFS_USB__ARB_RW2_DR, CYREG_USB_ARB_RW2_DR\r
-.set USBFS_USB__ARB_RW2_RA, CYREG_USB_ARB_RW2_RA\r
-.set USBFS_USB__ARB_RW2_RA_MSB, CYREG_USB_ARB_RW2_RA_MSB\r
-.set USBFS_USB__ARB_RW2_WA, CYREG_USB_ARB_RW2_WA\r
-.set USBFS_USB__ARB_RW2_WA_MSB, CYREG_USB_ARB_RW2_WA_MSB\r
-.set USBFS_USB__ARB_RW3_DR, CYREG_USB_ARB_RW3_DR\r
-.set USBFS_USB__ARB_RW3_RA, CYREG_USB_ARB_RW3_RA\r
-.set USBFS_USB__ARB_RW3_RA_MSB, CYREG_USB_ARB_RW3_RA_MSB\r
-.set USBFS_USB__ARB_RW3_WA, CYREG_USB_ARB_RW3_WA\r
-.set USBFS_USB__ARB_RW3_WA_MSB, CYREG_USB_ARB_RW3_WA_MSB\r
-.set USBFS_USB__ARB_RW4_DR, CYREG_USB_ARB_RW4_DR\r
-.set USBFS_USB__ARB_RW4_RA, CYREG_USB_ARB_RW4_RA\r
-.set USBFS_USB__ARB_RW4_RA_MSB, CYREG_USB_ARB_RW4_RA_MSB\r
-.set USBFS_USB__ARB_RW4_WA, CYREG_USB_ARB_RW4_WA\r
-.set USBFS_USB__ARB_RW4_WA_MSB, CYREG_USB_ARB_RW4_WA_MSB\r
-.set USBFS_USB__ARB_RW5_DR, CYREG_USB_ARB_RW5_DR\r
-.set USBFS_USB__ARB_RW5_RA, CYREG_USB_ARB_RW5_RA\r
-.set USBFS_USB__ARB_RW5_RA_MSB, CYREG_USB_ARB_RW5_RA_MSB\r
-.set USBFS_USB__ARB_RW5_WA, CYREG_USB_ARB_RW5_WA\r
-.set USBFS_USB__ARB_RW5_WA_MSB, CYREG_USB_ARB_RW5_WA_MSB\r
-.set USBFS_USB__ARB_RW6_DR, CYREG_USB_ARB_RW6_DR\r
-.set USBFS_USB__ARB_RW6_RA, CYREG_USB_ARB_RW6_RA\r
-.set USBFS_USB__ARB_RW6_RA_MSB, CYREG_USB_ARB_RW6_RA_MSB\r
-.set USBFS_USB__ARB_RW6_WA, CYREG_USB_ARB_RW6_WA\r
-.set USBFS_USB__ARB_RW6_WA_MSB, CYREG_USB_ARB_RW6_WA_MSB\r
-.set USBFS_USB__ARB_RW7_DR, CYREG_USB_ARB_RW7_DR\r
-.set USBFS_USB__ARB_RW7_RA, CYREG_USB_ARB_RW7_RA\r
-.set USBFS_USB__ARB_RW7_RA_MSB, CYREG_USB_ARB_RW7_RA_MSB\r
-.set USBFS_USB__ARB_RW7_WA, CYREG_USB_ARB_RW7_WA\r
-.set USBFS_USB__ARB_RW7_WA_MSB, CYREG_USB_ARB_RW7_WA_MSB\r
-.set USBFS_USB__ARB_RW8_DR, CYREG_USB_ARB_RW8_DR\r
-.set USBFS_USB__ARB_RW8_RA, CYREG_USB_ARB_RW8_RA\r
-.set USBFS_USB__ARB_RW8_RA_MSB, CYREG_USB_ARB_RW8_RA_MSB\r
-.set USBFS_USB__ARB_RW8_WA, CYREG_USB_ARB_RW8_WA\r
-.set USBFS_USB__ARB_RW8_WA_MSB, CYREG_USB_ARB_RW8_WA_MSB\r
-.set USBFS_USB__BUF_SIZE, CYREG_USB_BUF_SIZE\r
-.set USBFS_USB__BUS_RST_CNT, CYREG_USB_BUS_RST_CNT\r
-.set USBFS_USB__CR0, CYREG_USB_CR0\r
-.set USBFS_USB__CR1, CYREG_USB_CR1\r
-.set USBFS_USB__CWA, CYREG_USB_CWA\r
-.set USBFS_USB__CWA_MSB, CYREG_USB_CWA_MSB\r
-.set USBFS_USB__DMA_THRES, CYREG_USB_DMA_THRES\r
-.set USBFS_USB__DMA_THRES_MSB, CYREG_USB_DMA_THRES_MSB\r
-.set USBFS_USB__DYN_RECONFIG, CYREG_USB_DYN_RECONFIG\r
-.set USBFS_USB__EP_ACTIVE, CYREG_USB_EP_ACTIVE\r
-.set USBFS_USB__EP_TYPE, CYREG_USB_EP_TYPE\r
-.set USBFS_USB__EP0_CNT, CYREG_USB_EP0_CNT\r
-.set USBFS_USB__EP0_CR, CYREG_USB_EP0_CR\r
-.set USBFS_USB__EP0_DR0, CYREG_USB_EP0_DR0\r
-.set USBFS_USB__EP0_DR1, CYREG_USB_EP0_DR1\r
-.set USBFS_USB__EP0_DR2, CYREG_USB_EP0_DR2\r
-.set USBFS_USB__EP0_DR3, CYREG_USB_EP0_DR3\r
-.set USBFS_USB__EP0_DR4, CYREG_USB_EP0_DR4\r
-.set USBFS_USB__EP0_DR5, CYREG_USB_EP0_DR5\r
-.set USBFS_USB__EP0_DR6, CYREG_USB_EP0_DR6\r
-.set USBFS_USB__EP0_DR7, CYREG_USB_EP0_DR7\r
-.set USBFS_USB__MEM_DATA, CYREG_USB_MEM_DATA_MBASE\r
-.set USBFS_USB__PM_ACT_CFG, CYREG_PM_ACT_CFG5\r
-.set USBFS_USB__PM_ACT_MSK, 0x01\r
-.set USBFS_USB__PM_STBY_CFG, CYREG_PM_STBY_CFG5\r
-.set USBFS_USB__PM_STBY_MSK, 0x01\r
-.set USBFS_USB__SIE_EP_INT_EN, CYREG_USB_SIE_EP_INT_EN\r
-.set USBFS_USB__SIE_EP_INT_SR, CYREG_USB_SIE_EP_INT_SR\r
-.set USBFS_USB__SIE_EP1_CNT0, CYREG_USB_SIE_EP1_CNT0\r
-.set USBFS_USB__SIE_EP1_CNT1, CYREG_USB_SIE_EP1_CNT1\r
-.set USBFS_USB__SIE_EP1_CR0, CYREG_USB_SIE_EP1_CR0\r
-.set USBFS_USB__SIE_EP2_CNT0, CYREG_USB_SIE_EP2_CNT0\r
-.set USBFS_USB__SIE_EP2_CNT1, CYREG_USB_SIE_EP2_CNT1\r
-.set USBFS_USB__SIE_EP2_CR0, CYREG_USB_SIE_EP2_CR0\r
-.set USBFS_USB__SIE_EP3_CNT0, CYREG_USB_SIE_EP3_CNT0\r
-.set USBFS_USB__SIE_EP3_CNT1, CYREG_USB_SIE_EP3_CNT1\r
-.set USBFS_USB__SIE_EP3_CR0, CYREG_USB_SIE_EP3_CR0\r
-.set USBFS_USB__SIE_EP4_CNT0, CYREG_USB_SIE_EP4_CNT0\r
-.set USBFS_USB__SIE_EP4_CNT1, CYREG_USB_SIE_EP4_CNT1\r
-.set USBFS_USB__SIE_EP4_CR0, CYREG_USB_SIE_EP4_CR0\r
-.set USBFS_USB__SIE_EP5_CNT0, CYREG_USB_SIE_EP5_CNT0\r
-.set USBFS_USB__SIE_EP5_CNT1, CYREG_USB_SIE_EP5_CNT1\r
-.set USBFS_USB__SIE_EP5_CR0, CYREG_USB_SIE_EP5_CR0\r
-.set USBFS_USB__SIE_EP6_CNT0, CYREG_USB_SIE_EP6_CNT0\r
-.set USBFS_USB__SIE_EP6_CNT1, CYREG_USB_SIE_EP6_CNT1\r
-.set USBFS_USB__SIE_EP6_CR0, CYREG_USB_SIE_EP6_CR0\r
-.set USBFS_USB__SIE_EP7_CNT0, CYREG_USB_SIE_EP7_CNT0\r
-.set USBFS_USB__SIE_EP7_CNT1, CYREG_USB_SIE_EP7_CNT1\r
-.set USBFS_USB__SIE_EP7_CR0, CYREG_USB_SIE_EP7_CR0\r
-.set USBFS_USB__SIE_EP8_CNT0, CYREG_USB_SIE_EP8_CNT0\r
-.set USBFS_USB__SIE_EP8_CNT1, CYREG_USB_SIE_EP8_CNT1\r
-.set USBFS_USB__SIE_EP8_CR0, CYREG_USB_SIE_EP8_CR0\r
-.set USBFS_USB__SOF0, CYREG_USB_SOF0\r
-.set USBFS_USB__SOF1, CYREG_USB_SOF1\r
-.set USBFS_USB__USB_CLK_EN, CYREG_USB_USB_CLK_EN\r
-.set USBFS_USB__USBIO_CR0, CYREG_USB_USBIO_CR0\r
-.set USBFS_USB__USBIO_CR1, CYREG_USB_USBIO_CR1\r
-\r
-/* SDCard_BSPIM */\r
-.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB04_05_ACTL\r
-.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB04_05_CTL\r
-.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB04_05_CTL\r
-.set SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB04_05_CTL\r
-.set SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB04_05_CTL\r
-.set SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B1_UDB04_05_MSK\r
-.set SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB04_05_MSK\r
-.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB04_05_MSK\r
-.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB04_05_MSK\r
-.set SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B1_UDB04_ACTL\r
-.set SDCard_BSPIM_BitCounter__CONTROL_REG, CYREG_B1_UDB04_CTL\r
-.set SDCard_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B1_UDB04_ST_CTL\r
-.set SDCard_BSPIM_BitCounter__COUNT_REG, CYREG_B1_UDB04_CTL\r
-.set SDCard_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B1_UDB04_ST_CTL\r
-.set SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL\r
-.set SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL\r
-.set SDCard_BSPIM_BitCounter__PERIOD_REG, CYREG_B1_UDB04_MSK\r
-.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB04_05_ACTL\r
-.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B1_UDB04_05_ST\r
-.set SDCard_BSPIM_BitCounter_ST__MASK_REG, CYREG_B1_UDB04_MSK\r
-.set SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL\r
-.set SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL\r
-.set SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B1_UDB04_ACTL\r
-.set SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B1_UDB04_ST_CTL\r
-.set SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B1_UDB04_ST_CTL\r
-.set SDCard_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B1_UDB04_ST\r
-.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB08_09_ACTL\r
-.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB08_09_ST\r
-.set SDCard_BSPIM_RxStsReg__4__MASK, 0x10\r
-.set SDCard_BSPIM_RxStsReg__4__POS, 4\r
-.set SDCard_BSPIM_RxStsReg__5__MASK, 0x20\r
-.set SDCard_BSPIM_RxStsReg__5__POS, 5\r
-.set SDCard_BSPIM_RxStsReg__6__MASK, 0x40\r
-.set SDCard_BSPIM_RxStsReg__6__POS, 6\r
-.set SDCard_BSPIM_RxStsReg__MASK, 0x70\r
-.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B1_UDB08_MSK\r
-.set SDCard_BSPIM_RxStsReg__MASK_ST_AUX_CTL_REG, CYREG_B1_UDB08_MSK_ACTL\r
-.set SDCard_BSPIM_RxStsReg__PER_ST_AUX_CTL_REG, CYREG_B1_UDB08_MSK_ACTL\r
-.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB08_ACTL\r
-.set SDCard_BSPIM_RxStsReg__STATUS_CNT_REG, CYREG_B1_UDB08_ST_CTL\r
-.set SDCard_BSPIM_RxStsReg__STATUS_CONTROL_REG, CYREG_B1_UDB08_ST_CTL\r
-.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B1_UDB08_ST\r
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG, CYREG_B1_UDB04_05_A0\r
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG, CYREG_B1_UDB04_05_A1\r
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG, CYREG_B1_UDB04_05_D0\r
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG, CYREG_B1_UDB04_05_D1\r
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG, CYREG_B1_UDB04_05_ACTL\r
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG, CYREG_B1_UDB04_05_F0\r
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG, CYREG_B1_UDB04_05_F1\r
-.set SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG, CYREG_B1_UDB04_A0_A1\r
-.set SDCard_BSPIM_sR8_Dp_u0__A0_REG, CYREG_B1_UDB04_A0\r
-.set SDCard_BSPIM_sR8_Dp_u0__A1_REG, CYREG_B1_UDB04_A1\r
-.set SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG, CYREG_B1_UDB04_D0_D1\r
-.set SDCard_BSPIM_sR8_Dp_u0__D0_REG, CYREG_B1_UDB04_D0\r
-.set SDCard_BSPIM_sR8_Dp_u0__D1_REG, CYREG_B1_UDB04_D1\r
-.set SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG, CYREG_B1_UDB04_ACTL\r
-.set SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG, CYREG_B1_UDB04_F0_F1\r
-.set SDCard_BSPIM_sR8_Dp_u0__F0_REG, CYREG_B1_UDB04_F0\r
-.set SDCard_BSPIM_sR8_Dp_u0__F1_REG, CYREG_B1_UDB04_F1\r
-.set SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL\r
-.set SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL\r
-.set SDCard_BSPIM_TxStsReg__0__MASK, 0x01\r
-.set SDCard_BSPIM_TxStsReg__0__POS, 0\r
-.set SDCard_BSPIM_TxStsReg__1__MASK, 0x02\r
-.set SDCard_BSPIM_TxStsReg__1__POS, 1\r
-.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB07_08_ACTL\r
-.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB07_08_ST\r
-.set SDCard_BSPIM_TxStsReg__2__MASK, 0x04\r
-.set SDCard_BSPIM_TxStsReg__2__POS, 2\r
-.set SDCard_BSPIM_TxStsReg__3__MASK, 0x08\r
-.set SDCard_BSPIM_TxStsReg__3__POS, 3\r
-.set SDCard_BSPIM_TxStsReg__4__MASK, 0x10\r
-.set SDCard_BSPIM_TxStsReg__4__POS, 4\r
-.set SDCard_BSPIM_TxStsReg__MASK, 0x1F\r
-.set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B1_UDB07_MSK\r
-.set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB07_ACTL\r
-.set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B1_UDB07_ST\r
-\r
-/* SD_SCK */\r
-.set SD_SCK__0__INTTYPE, CYREG_PICU3_INTTYPE2\r
-.set SD_SCK__0__MASK, 0x04\r
-.set SD_SCK__0__PC, CYREG_PRT3_PC2\r
-.set SD_SCK__0__PORT, 3\r
-.set SD_SCK__0__SHIFT, 2\r
-.set SD_SCK__AG, CYREG_PRT3_AG\r
-.set SD_SCK__AMUX, CYREG_PRT3_AMUX\r
-.set SD_SCK__BIE, CYREG_PRT3_BIE\r
-.set SD_SCK__BIT_MASK, CYREG_PRT3_BIT_MASK\r
-.set SD_SCK__BYP, CYREG_PRT3_BYP\r
-.set SD_SCK__CTL, CYREG_PRT3_CTL\r
-.set SD_SCK__DM0, CYREG_PRT3_DM0\r
-.set SD_SCK__DM1, CYREG_PRT3_DM1\r
-.set SD_SCK__DM2, CYREG_PRT3_DM2\r
-.set SD_SCK__DR, CYREG_PRT3_DR\r
-.set SD_SCK__INP_DIS, CYREG_PRT3_INP_DIS\r
-.set SD_SCK__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU3_BASE\r
-.set SD_SCK__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG\r
-.set SD_SCK__LCD_EN, CYREG_PRT3_LCD_EN\r
-.set SD_SCK__MASK, 0x04\r
-.set SD_SCK__PORT, 3\r
-.set SD_SCK__PRT, CYREG_PRT3_PRT\r
-.set SD_SCK__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL\r
-.set SD_SCK__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN\r
-.set SD_SCK__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0\r
-.set SD_SCK__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1\r
-.set SD_SCK__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0\r
-.set SD_SCK__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1\r
-.set SD_SCK__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT\r
-.set SD_SCK__PS, CYREG_PRT3_PS\r
-.set SD_SCK__SHIFT, 2\r
-.set SD_SCK__SLW, CYREG_PRT3_SLW\r
-\r
-/* SCSI_In */\r
-.set SCSI_In__0__AG, CYREG_PRT2_AG\r
-.set SCSI_In__0__AMUX, CYREG_PRT2_AMUX\r
-.set SCSI_In__0__BIE, CYREG_PRT2_BIE\r
-.set SCSI_In__0__BIT_MASK, CYREG_PRT2_BIT_MASK\r
-.set SCSI_In__0__BYP, CYREG_PRT2_BYP\r
-.set SCSI_In__0__CTL, CYREG_PRT2_CTL\r
-.set SCSI_In__0__DM0, CYREG_PRT2_DM0\r
-.set SCSI_In__0__DM1, CYREG_PRT2_DM1\r
-.set SCSI_In__0__DM2, CYREG_PRT2_DM2\r
-.set SCSI_In__0__DR, CYREG_PRT2_DR\r
-.set SCSI_In__0__INP_DIS, CYREG_PRT2_INP_DIS\r
-.set SCSI_In__0__INTTYPE, CYREG_PICU2_INTTYPE0\r
-.set SCSI_In__0__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG\r
-.set SCSI_In__0__LCD_EN, CYREG_PRT2_LCD_EN\r
-.set SCSI_In__0__MASK, 0x01\r
-.set SCSI_In__0__PC, CYREG_PRT2_PC0\r
-.set SCSI_In__0__PORT, 2\r
-.set SCSI_In__0__PRT, CYREG_PRT2_PRT\r
-.set SCSI_In__0__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL\r
-.set SCSI_In__0__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN\r
-.set SCSI_In__0__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0\r
-.set SCSI_In__0__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1\r
-.set SCSI_In__0__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0\r
-.set SCSI_In__0__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1\r
-.set SCSI_In__0__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT\r
-.set SCSI_In__0__PS, CYREG_PRT2_PS\r
-.set SCSI_In__0__SHIFT, 0\r
-.set SCSI_In__0__SLW, CYREG_PRT2_SLW\r
-.set SCSI_In__1__AG, CYREG_PRT6_AG\r
-.set SCSI_In__1__AMUX, CYREG_PRT6_AMUX\r
-.set SCSI_In__1__BIE, CYREG_PRT6_BIE\r
-.set SCSI_In__1__BIT_MASK, CYREG_PRT6_BIT_MASK\r
-.set SCSI_In__1__BYP, CYREG_PRT6_BYP\r
-.set SCSI_In__1__CTL, CYREG_PRT6_CTL\r
-.set SCSI_In__1__DM0, CYREG_PRT6_DM0\r
-.set SCSI_In__1__DM1, CYREG_PRT6_DM1\r
-.set SCSI_In__1__DM2, CYREG_PRT6_DM2\r
-.set SCSI_In__1__DR, CYREG_PRT6_DR\r
-.set SCSI_In__1__INP_DIS, CYREG_PRT6_INP_DIS\r
-.set SCSI_In__1__INTTYPE, CYREG_PICU6_INTTYPE7\r
-.set SCSI_In__1__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG\r
-.set SCSI_In__1__LCD_EN, CYREG_PRT6_LCD_EN\r
-.set SCSI_In__1__MASK, 0x80\r
-.set SCSI_In__1__PC, CYREG_PRT6_PC7\r
-.set SCSI_In__1__PORT, 6\r
-.set SCSI_In__1__PRT, CYREG_PRT6_PRT\r
-.set SCSI_In__1__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL\r
-.set SCSI_In__1__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN\r
-.set SCSI_In__1__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0\r
-.set SCSI_In__1__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1\r
-.set SCSI_In__1__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0\r
-.set SCSI_In__1__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1\r
-.set SCSI_In__1__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT\r
-.set SCSI_In__1__PS, CYREG_PRT6_PS\r
-.set SCSI_In__1__SHIFT, 7\r
-.set SCSI_In__1__SLW, CYREG_PRT6_SLW\r
-.set SCSI_In__2__AG, CYREG_PRT5_AG\r
-.set SCSI_In__2__AMUX, CYREG_PRT5_AMUX\r
-.set SCSI_In__2__BIE, CYREG_PRT5_BIE\r
-.set SCSI_In__2__BIT_MASK, CYREG_PRT5_BIT_MASK\r
-.set SCSI_In__2__BYP, CYREG_PRT5_BYP\r
-.set SCSI_In__2__CTL, CYREG_PRT5_CTL\r
-.set SCSI_In__2__DM0, CYREG_PRT5_DM0\r
-.set SCSI_In__2__DM1, CYREG_PRT5_DM1\r
-.set SCSI_In__2__DM2, CYREG_PRT5_DM2\r
-.set SCSI_In__2__DR, CYREG_PRT5_DR\r
-.set SCSI_In__2__INP_DIS, CYREG_PRT5_INP_DIS\r
-.set SCSI_In__2__INTTYPE, CYREG_PICU5_INTTYPE1\r
-.set SCSI_In__2__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG\r
-.set SCSI_In__2__LCD_EN, CYREG_PRT5_LCD_EN\r
-.set SCSI_In__2__MASK, 0x02\r
-.set SCSI_In__2__PC, CYREG_PRT5_PC1\r
-.set SCSI_In__2__PORT, 5\r
-.set SCSI_In__2__PRT, CYREG_PRT5_PRT\r
-.set SCSI_In__2__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL\r
-.set SCSI_In__2__PRTDSI__DBL_SYNC_IN, CYREG_PRT5_DBL_SYNC_IN\r
-.set SCSI_In__2__PRTDSI__OE_SEL0, CYREG_PRT5_OE_SEL0\r
-.set SCSI_In__2__PRTDSI__OE_SEL1, CYREG_PRT5_OE_SEL1\r
-.set SCSI_In__2__PRTDSI__OUT_SEL0, CYREG_PRT5_OUT_SEL0\r
-.set SCSI_In__2__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1\r
-.set SCSI_In__2__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT\r
-.set SCSI_In__2__PS, CYREG_PRT5_PS\r
-.set SCSI_In__2__SHIFT, 1\r
-.set SCSI_In__2__SLW, CYREG_PRT5_SLW\r
-.set SCSI_In__3__AG, CYREG_PRT5_AG\r
-.set SCSI_In__3__AMUX, CYREG_PRT5_AMUX\r
-.set SCSI_In__3__BIE, CYREG_PRT5_BIE\r
-.set SCSI_In__3__BIT_MASK, CYREG_PRT5_BIT_MASK\r
-.set SCSI_In__3__BYP, CYREG_PRT5_BYP\r
-.set SCSI_In__3__CTL, CYREG_PRT5_CTL\r
-.set SCSI_In__3__DM0, CYREG_PRT5_DM0\r
-.set SCSI_In__3__DM1, CYREG_PRT5_DM1\r
-.set SCSI_In__3__DM2, CYREG_PRT5_DM2\r
-.set SCSI_In__3__DR, CYREG_PRT5_DR\r
-.set SCSI_In__3__INP_DIS, CYREG_PRT5_INP_DIS\r
-.set SCSI_In__3__INTTYPE, CYREG_PICU5_INTTYPE2\r
-.set SCSI_In__3__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG\r
-.set SCSI_In__3__LCD_EN, CYREG_PRT5_LCD_EN\r
-.set SCSI_In__3__MASK, 0x04\r
-.set SCSI_In__3__PC, CYREG_PRT5_PC2\r
-.set SCSI_In__3__PORT, 5\r
-.set SCSI_In__3__PRT, CYREG_PRT5_PRT\r
-.set SCSI_In__3__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL\r
-.set SCSI_In__3__PRTDSI__DBL_SYNC_IN, CYREG_PRT5_DBL_SYNC_IN\r
-.set SCSI_In__3__PRTDSI__OE_SEL0, CYREG_PRT5_OE_SEL0\r
-.set SCSI_In__3__PRTDSI__OE_SEL1, CYREG_PRT5_OE_SEL1\r
-.set SCSI_In__3__PRTDSI__OUT_SEL0, CYREG_PRT5_OUT_SEL0\r
-.set SCSI_In__3__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1\r
-.set SCSI_In__3__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT\r
-.set SCSI_In__3__PS, CYREG_PRT5_PS\r
-.set SCSI_In__3__SHIFT, 2\r
-.set SCSI_In__3__SLW, CYREG_PRT5_SLW\r
-.set SCSI_In__4__AG, CYREG_PRT5_AG\r
-.set SCSI_In__4__AMUX, CYREG_PRT5_AMUX\r
-.set SCSI_In__4__BIE, CYREG_PRT5_BIE\r
-.set SCSI_In__4__BIT_MASK, CYREG_PRT5_BIT_MASK\r
-.set SCSI_In__4__BYP, CYREG_PRT5_BYP\r
-.set SCSI_In__4__CTL, CYREG_PRT5_CTL\r
-.set SCSI_In__4__DM0, CYREG_PRT5_DM0\r
-.set SCSI_In__4__DM1, CYREG_PRT5_DM1\r
-.set SCSI_In__4__DM2, CYREG_PRT5_DM2\r
-.set SCSI_In__4__DR, CYREG_PRT5_DR\r
-.set SCSI_In__4__INP_DIS, CYREG_PRT5_INP_DIS\r
-.set SCSI_In__4__INTTYPE, CYREG_PICU5_INTTYPE3\r
-.set SCSI_In__4__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG\r
-.set SCSI_In__4__LCD_EN, CYREG_PRT5_LCD_EN\r
-.set SCSI_In__4__MASK, 0x08\r
-.set SCSI_In__4__PC, CYREG_PRT5_PC3\r
-.set SCSI_In__4__PORT, 5\r
-.set SCSI_In__4__PRT, CYREG_PRT5_PRT\r
-.set SCSI_In__4__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL\r
-.set SCSI_In__4__PRTDSI__DBL_SYNC_IN, CYREG_PRT5_DBL_SYNC_IN\r
-.set SCSI_In__4__PRTDSI__OE_SEL0, CYREG_PRT5_OE_SEL0\r
-.set SCSI_In__4__PRTDSI__OE_SEL1, CYREG_PRT5_OE_SEL1\r
-.set SCSI_In__4__PRTDSI__OUT_SEL0, CYREG_PRT5_OUT_SEL0\r
-.set SCSI_In__4__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1\r
-.set SCSI_In__4__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT\r
-.set SCSI_In__4__PS, CYREG_PRT5_PS\r
-.set SCSI_In__4__SHIFT, 3\r
-.set SCSI_In__4__SLW, CYREG_PRT5_SLW\r
-.set SCSI_In__CD__AG, CYREG_PRT5_AG\r
-.set SCSI_In__CD__AMUX, CYREG_PRT5_AMUX\r
-.set SCSI_In__CD__BIE, CYREG_PRT5_BIE\r
-.set SCSI_In__CD__BIT_MASK, CYREG_PRT5_BIT_MASK\r
-.set SCSI_In__CD__BYP, CYREG_PRT5_BYP\r
-.set SCSI_In__CD__CTL, CYREG_PRT5_CTL\r
-.set SCSI_In__CD__DM0, CYREG_PRT5_DM0\r
-.set SCSI_In__CD__DM1, CYREG_PRT5_DM1\r
-.set SCSI_In__CD__DM2, CYREG_PRT5_DM2\r
-.set SCSI_In__CD__DR, CYREG_PRT5_DR\r
-.set SCSI_In__CD__INP_DIS, CYREG_PRT5_INP_DIS\r
-.set SCSI_In__CD__INTTYPE, CYREG_PICU5_INTTYPE1\r
-.set SCSI_In__CD__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG\r
-.set SCSI_In__CD__LCD_EN, CYREG_PRT5_LCD_EN\r
-.set SCSI_In__CD__MASK, 0x02\r
-.set SCSI_In__CD__PC, CYREG_PRT5_PC1\r
-.set SCSI_In__CD__PORT, 5\r
-.set SCSI_In__CD__PRT, CYREG_PRT5_PRT\r
-.set SCSI_In__CD__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL\r
-.set SCSI_In__CD__PRTDSI__DBL_SYNC_IN, CYREG_PRT5_DBL_SYNC_IN\r
-.set SCSI_In__CD__PRTDSI__OE_SEL0, CYREG_PRT5_OE_SEL0\r
-.set SCSI_In__CD__PRTDSI__OE_SEL1, CYREG_PRT5_OE_SEL1\r
-.set SCSI_In__CD__PRTDSI__OUT_SEL0, CYREG_PRT5_OUT_SEL0\r
-.set SCSI_In__CD__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1\r
-.set SCSI_In__CD__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT\r
-.set SCSI_In__CD__PS, CYREG_PRT5_PS\r
-.set SCSI_In__CD__SHIFT, 1\r
-.set SCSI_In__CD__SLW, CYREG_PRT5_SLW\r
-.set SCSI_In__DBP__AG, CYREG_PRT2_AG\r
-.set SCSI_In__DBP__AMUX, CYREG_PRT2_AMUX\r
-.set SCSI_In__DBP__BIE, CYREG_PRT2_BIE\r
-.set SCSI_In__DBP__BIT_MASK, CYREG_PRT2_BIT_MASK\r
-.set SCSI_In__DBP__BYP, CYREG_PRT2_BYP\r
-.set SCSI_In__DBP__CTL, CYREG_PRT2_CTL\r
-.set SCSI_In__DBP__DM0, CYREG_PRT2_DM0\r
-.set SCSI_In__DBP__DM1, CYREG_PRT2_DM1\r
-.set SCSI_In__DBP__DM2, CYREG_PRT2_DM2\r
-.set SCSI_In__DBP__DR, CYREG_PRT2_DR\r
-.set SCSI_In__DBP__INP_DIS, CYREG_PRT2_INP_DIS\r
-.set SCSI_In__DBP__INTTYPE, CYREG_PICU2_INTTYPE0\r
-.set SCSI_In__DBP__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG\r
-.set SCSI_In__DBP__LCD_EN, CYREG_PRT2_LCD_EN\r
-.set SCSI_In__DBP__MASK, 0x01\r
-.set SCSI_In__DBP__PC, CYREG_PRT2_PC0\r
-.set SCSI_In__DBP__PORT, 2\r
-.set SCSI_In__DBP__PRT, CYREG_PRT2_PRT\r
-.set SCSI_In__DBP__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL\r
-.set SCSI_In__DBP__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN\r
-.set SCSI_In__DBP__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0\r
-.set SCSI_In__DBP__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1\r
-.set SCSI_In__DBP__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0\r
-.set SCSI_In__DBP__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1\r
-.set SCSI_In__DBP__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT\r
-.set SCSI_In__DBP__PS, CYREG_PRT2_PS\r
-.set SCSI_In__DBP__SHIFT, 0\r
-.set SCSI_In__DBP__SLW, CYREG_PRT2_SLW\r
-.set SCSI_In__IO__AG, CYREG_PRT5_AG\r
-.set SCSI_In__IO__AMUX, CYREG_PRT5_AMUX\r
-.set SCSI_In__IO__BIE, CYREG_PRT5_BIE\r
-.set SCSI_In__IO__BIT_MASK, CYREG_PRT5_BIT_MASK\r
-.set SCSI_In__IO__BYP, CYREG_PRT5_BYP\r
-.set SCSI_In__IO__CTL, CYREG_PRT5_CTL\r
-.set SCSI_In__IO__DM0, CYREG_PRT5_DM0\r
-.set SCSI_In__IO__DM1, CYREG_PRT5_DM1\r
-.set SCSI_In__IO__DM2, CYREG_PRT5_DM2\r
-.set SCSI_In__IO__DR, CYREG_PRT5_DR\r
-.set SCSI_In__IO__INP_DIS, CYREG_PRT5_INP_DIS\r
-.set SCSI_In__IO__INTTYPE, CYREG_PICU5_INTTYPE3\r
-.set SCSI_In__IO__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG\r
-.set SCSI_In__IO__LCD_EN, CYREG_PRT5_LCD_EN\r
-.set SCSI_In__IO__MASK, 0x08\r
-.set SCSI_In__IO__PC, CYREG_PRT5_PC3\r
-.set SCSI_In__IO__PORT, 5\r
-.set SCSI_In__IO__PRT, CYREG_PRT5_PRT\r
-.set SCSI_In__IO__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL\r
-.set SCSI_In__IO__PRTDSI__DBL_SYNC_IN, CYREG_PRT5_DBL_SYNC_IN\r
-.set SCSI_In__IO__PRTDSI__OE_SEL0, CYREG_PRT5_OE_SEL0\r
-.set SCSI_In__IO__PRTDSI__OE_SEL1, CYREG_PRT5_OE_SEL1\r
-.set SCSI_In__IO__PRTDSI__OUT_SEL0, CYREG_PRT5_OUT_SEL0\r
-.set SCSI_In__IO__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1\r
-.set SCSI_In__IO__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT\r
-.set SCSI_In__IO__PS, CYREG_PRT5_PS\r
-.set SCSI_In__IO__SHIFT, 3\r
-.set SCSI_In__IO__SLW, CYREG_PRT5_SLW\r
-.set SCSI_In__MSG__AG, CYREG_PRT6_AG\r
-.set SCSI_In__MSG__AMUX, CYREG_PRT6_AMUX\r
-.set SCSI_In__MSG__BIE, CYREG_PRT6_BIE\r
-.set SCSI_In__MSG__BIT_MASK, CYREG_PRT6_BIT_MASK\r
-.set SCSI_In__MSG__BYP, CYREG_PRT6_BYP\r
-.set SCSI_In__MSG__CTL, CYREG_PRT6_CTL\r
-.set SCSI_In__MSG__DM0, CYREG_PRT6_DM0\r
-.set SCSI_In__MSG__DM1, CYREG_PRT6_DM1\r
-.set SCSI_In__MSG__DM2, CYREG_PRT6_DM2\r
-.set SCSI_In__MSG__DR, CYREG_PRT6_DR\r
-.set SCSI_In__MSG__INP_DIS, CYREG_PRT6_INP_DIS\r
-.set SCSI_In__MSG__INTTYPE, CYREG_PICU6_INTTYPE7\r
-.set SCSI_In__MSG__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG\r
-.set SCSI_In__MSG__LCD_EN, CYREG_PRT6_LCD_EN\r
-.set SCSI_In__MSG__MASK, 0x80\r
-.set SCSI_In__MSG__PC, CYREG_PRT6_PC7\r
-.set SCSI_In__MSG__PORT, 6\r
-.set SCSI_In__MSG__PRT, CYREG_PRT6_PRT\r
-.set SCSI_In__MSG__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL\r
-.set SCSI_In__MSG__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN\r
-.set SCSI_In__MSG__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0\r
-.set SCSI_In__MSG__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1\r
-.set SCSI_In__MSG__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0\r
-.set SCSI_In__MSG__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1\r
-.set SCSI_In__MSG__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT\r
-.set SCSI_In__MSG__PS, CYREG_PRT6_PS\r
-.set SCSI_In__MSG__SHIFT, 7\r
-.set SCSI_In__MSG__SLW, CYREG_PRT6_SLW\r
-.set SCSI_In__REQ__AG, CYREG_PRT5_AG\r
-.set SCSI_In__REQ__AMUX, CYREG_PRT5_AMUX\r
-.set SCSI_In__REQ__BIE, CYREG_PRT5_BIE\r
-.set SCSI_In__REQ__BIT_MASK, CYREG_PRT5_BIT_MASK\r
-.set SCSI_In__REQ__BYP, CYREG_PRT5_BYP\r
-.set SCSI_In__REQ__CTL, CYREG_PRT5_CTL\r
-.set SCSI_In__REQ__DM0, CYREG_PRT5_DM0\r
-.set SCSI_In__REQ__DM1, CYREG_PRT5_DM1\r
-.set SCSI_In__REQ__DM2, CYREG_PRT5_DM2\r
-.set SCSI_In__REQ__DR, CYREG_PRT5_DR\r
-.set SCSI_In__REQ__INP_DIS, CYREG_PRT5_INP_DIS\r
-.set SCSI_In__REQ__INTTYPE, CYREG_PICU5_INTTYPE2\r
-.set SCSI_In__REQ__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG\r
-.set SCSI_In__REQ__LCD_EN, CYREG_PRT5_LCD_EN\r
-.set SCSI_In__REQ__MASK, 0x04\r
-.set SCSI_In__REQ__PC, CYREG_PRT5_PC2\r
-.set SCSI_In__REQ__PORT, 5\r
-.set SCSI_In__REQ__PRT, CYREG_PRT5_PRT\r
-.set SCSI_In__REQ__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL\r
-.set SCSI_In__REQ__PRTDSI__DBL_SYNC_IN, CYREG_PRT5_DBL_SYNC_IN\r
-.set SCSI_In__REQ__PRTDSI__OE_SEL0, CYREG_PRT5_OE_SEL0\r
-.set SCSI_In__REQ__PRTDSI__OE_SEL1, CYREG_PRT5_OE_SEL1\r
-.set SCSI_In__REQ__PRTDSI__OUT_SEL0, CYREG_PRT5_OUT_SEL0\r
-.set SCSI_In__REQ__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1\r
-.set SCSI_In__REQ__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT\r
-.set SCSI_In__REQ__PS, CYREG_PRT5_PS\r
-.set SCSI_In__REQ__SHIFT, 2\r
-.set SCSI_In__REQ__SLW, CYREG_PRT5_SLW\r
-\r
-/* SCSI_In_DBx */\r
-.set SCSI_In_DBx__0__AG, CYREG_PRT12_AG\r
-.set SCSI_In_DBx__0__BIE, CYREG_PRT12_BIE\r
-.set SCSI_In_DBx__0__BIT_MASK, CYREG_PRT12_BIT_MASK\r
-.set SCSI_In_DBx__0__BYP, CYREG_PRT12_BYP\r
-.set SCSI_In_DBx__0__DM0, CYREG_PRT12_DM0\r
-.set SCSI_In_DBx__0__DM1, CYREG_PRT12_DM1\r
-.set SCSI_In_DBx__0__DM2, CYREG_PRT12_DM2\r
-.set SCSI_In_DBx__0__DR, CYREG_PRT12_DR\r
-.set SCSI_In_DBx__0__INP_DIS, CYREG_PRT12_INP_DIS\r
-.set SCSI_In_DBx__0__INTTYPE, CYREG_PICU12_INTTYPE4\r
-.set SCSI_In_DBx__0__MASK, 0x10\r
-.set SCSI_In_DBx__0__PC, CYREG_PRT12_PC4\r
-.set SCSI_In_DBx__0__PORT, 12\r
-.set SCSI_In_DBx__0__PRT, CYREG_PRT12_PRT\r
-.set SCSI_In_DBx__0__PRTDSI__DBL_SYNC_IN, CYREG_PRT12_DBL_SYNC_IN\r
-.set SCSI_In_DBx__0__PRTDSI__OE_SEL0, CYREG_PRT12_OE_SEL0\r
-.set SCSI_In_DBx__0__PRTDSI__OE_SEL1, CYREG_PRT12_OE_SEL1\r
-.set SCSI_In_DBx__0__PRTDSI__OUT_SEL0, CYREG_PRT12_OUT_SEL0\r
-.set SCSI_In_DBx__0__PRTDSI__OUT_SEL1, CYREG_PRT12_OUT_SEL1\r
-.set SCSI_In_DBx__0__PRTDSI__SYNC_OUT, CYREG_PRT12_SYNC_OUT\r
-.set SCSI_In_DBx__0__PS, CYREG_PRT12_PS\r
-.set SCSI_In_DBx__0__SHIFT, 4\r
-.set SCSI_In_DBx__0__SIO_CFG, CYREG_PRT12_SIO_CFG\r
-.set SCSI_In_DBx__0__SIO_DIFF, CYREG_PRT12_SIO_DIFF\r
-.set SCSI_In_DBx__0__SIO_HYST_EN, CYREG_PRT12_SIO_HYST_EN\r
-.set SCSI_In_DBx__0__SIO_REG_HIFREQ, CYREG_PRT12_SIO_REG_HIFREQ\r
-.set SCSI_In_DBx__0__SLW, CYREG_PRT12_SLW\r
-.set SCSI_In_DBx__1__AG, CYREG_PRT2_AG\r
-.set SCSI_In_DBx__1__AMUX, CYREG_PRT2_AMUX\r
-.set SCSI_In_DBx__1__BIE, CYREG_PRT2_BIE\r
-.set SCSI_In_DBx__1__BIT_MASK, CYREG_PRT2_BIT_MASK\r
-.set SCSI_In_DBx__1__BYP, CYREG_PRT2_BYP\r
-.set SCSI_In_DBx__1__CTL, CYREG_PRT2_CTL\r
-.set SCSI_In_DBx__1__DM0, CYREG_PRT2_DM0\r
-.set SCSI_In_DBx__1__DM1, CYREG_PRT2_DM1\r
-.set SCSI_In_DBx__1__DM2, CYREG_PRT2_DM2\r
-.set SCSI_In_DBx__1__DR, CYREG_PRT2_DR\r
-.set SCSI_In_DBx__1__INP_DIS, CYREG_PRT2_INP_DIS\r
-.set SCSI_In_DBx__1__INTTYPE, CYREG_PICU2_INTTYPE7\r
-.set SCSI_In_DBx__1__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG\r
-.set SCSI_In_DBx__1__LCD_EN, CYREG_PRT2_LCD_EN\r
-.set SCSI_In_DBx__1__MASK, 0x80\r
-.set SCSI_In_DBx__1__PC, CYREG_PRT2_PC7\r
-.set SCSI_In_DBx__1__PORT, 2\r
-.set SCSI_In_DBx__1__PRT, CYREG_PRT2_PRT\r
-.set SCSI_In_DBx__1__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL\r
-.set SCSI_In_DBx__1__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN\r
-.set SCSI_In_DBx__1__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0\r
-.set SCSI_In_DBx__1__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1\r
-.set SCSI_In_DBx__1__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0\r
-.set SCSI_In_DBx__1__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1\r
-.set SCSI_In_DBx__1__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT\r
-.set SCSI_In_DBx__1__PS, CYREG_PRT2_PS\r
-.set SCSI_In_DBx__1__SHIFT, 7\r
-.set SCSI_In_DBx__1__SLW, CYREG_PRT2_SLW\r
-.set SCSI_In_DBx__2__AG, CYREG_PRT2_AG\r
-.set SCSI_In_DBx__2__AMUX, CYREG_PRT2_AMUX\r
-.set SCSI_In_DBx__2__BIE, CYREG_PRT2_BIE\r
-.set SCSI_In_DBx__2__BIT_MASK, CYREG_PRT2_BIT_MASK\r
-.set SCSI_In_DBx__2__BYP, CYREG_PRT2_BYP\r
-.set SCSI_In_DBx__2__CTL, CYREG_PRT2_CTL\r
-.set SCSI_In_DBx__2__DM0, CYREG_PRT2_DM0\r
-.set SCSI_In_DBx__2__DM1, CYREG_PRT2_DM1\r
-.set SCSI_In_DBx__2__DM2, CYREG_PRT2_DM2\r
-.set SCSI_In_DBx__2__DR, CYREG_PRT2_DR\r
-.set SCSI_In_DBx__2__INP_DIS, CYREG_PRT2_INP_DIS\r
-.set SCSI_In_DBx__2__INTTYPE, CYREG_PICU2_INTTYPE6\r
-.set SCSI_In_DBx__2__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG\r
-.set SCSI_In_DBx__2__LCD_EN, CYREG_PRT2_LCD_EN\r
-.set SCSI_In_DBx__2__MASK, 0x40\r
-.set SCSI_In_DBx__2__PC, CYREG_PRT2_PC6\r
-.set SCSI_In_DBx__2__PORT, 2\r
-.set SCSI_In_DBx__2__PRT, CYREG_PRT2_PRT\r
-.set SCSI_In_DBx__2__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL\r
-.set SCSI_In_DBx__2__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN\r
-.set SCSI_In_DBx__2__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0\r
-.set SCSI_In_DBx__2__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1\r
-.set SCSI_In_DBx__2__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0\r
-.set SCSI_In_DBx__2__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1\r
-.set SCSI_In_DBx__2__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT\r
-.set SCSI_In_DBx__2__PS, CYREG_PRT2_PS\r
-.set SCSI_In_DBx__2__SHIFT, 6\r
-.set SCSI_In_DBx__2__SLW, CYREG_PRT2_SLW\r
-.set SCSI_In_DBx__3__AG, CYREG_PRT2_AG\r
-.set SCSI_In_DBx__3__AMUX, CYREG_PRT2_AMUX\r
-.set SCSI_In_DBx__3__BIE, CYREG_PRT2_BIE\r
-.set SCSI_In_DBx__3__BIT_MASK, CYREG_PRT2_BIT_MASK\r
-.set SCSI_In_DBx__3__BYP, CYREG_PRT2_BYP\r
-.set SCSI_In_DBx__3__CTL, CYREG_PRT2_CTL\r
-.set SCSI_In_DBx__3__DM0, CYREG_PRT2_DM0\r
-.set SCSI_In_DBx__3__DM1, CYREG_PRT2_DM1\r
-.set SCSI_In_DBx__3__DM2, CYREG_PRT2_DM2\r
-.set SCSI_In_DBx__3__DR, CYREG_PRT2_DR\r
-.set SCSI_In_DBx__3__INP_DIS, CYREG_PRT2_INP_DIS\r
-.set SCSI_In_DBx__3__INTTYPE, CYREG_PICU2_INTTYPE5\r
-.set SCSI_In_DBx__3__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG\r
-.set SCSI_In_DBx__3__LCD_EN, CYREG_PRT2_LCD_EN\r
-.set SCSI_In_DBx__3__MASK, 0x20\r
-.set SCSI_In_DBx__3__PC, CYREG_PRT2_PC5\r
-.set SCSI_In_DBx__3__PORT, 2\r
-.set SCSI_In_DBx__3__PRT, CYREG_PRT2_PRT\r
-.set SCSI_In_DBx__3__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL\r
-.set SCSI_In_DBx__3__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN\r
-.set SCSI_In_DBx__3__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0\r
-.set SCSI_In_DBx__3__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1\r
-.set SCSI_In_DBx__3__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0\r
-.set SCSI_In_DBx__3__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1\r
-.set SCSI_In_DBx__3__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT\r
-.set SCSI_In_DBx__3__PS, CYREG_PRT2_PS\r
-.set SCSI_In_DBx__3__SHIFT, 5\r
-.set SCSI_In_DBx__3__SLW, CYREG_PRT2_SLW\r
-.set SCSI_In_DBx__4__AG, CYREG_PRT2_AG\r
-.set SCSI_In_DBx__4__AMUX, CYREG_PRT2_AMUX\r
-.set SCSI_In_DBx__4__BIE, CYREG_PRT2_BIE\r
-.set SCSI_In_DBx__4__BIT_MASK, CYREG_PRT2_BIT_MASK\r
-.set SCSI_In_DBx__4__BYP, CYREG_PRT2_BYP\r
-.set SCSI_In_DBx__4__CTL, CYREG_PRT2_CTL\r
-.set SCSI_In_DBx__4__DM0, CYREG_PRT2_DM0\r
-.set SCSI_In_DBx__4__DM1, CYREG_PRT2_DM1\r
-.set SCSI_In_DBx__4__DM2, CYREG_PRT2_DM2\r
-.set SCSI_In_DBx__4__DR, CYREG_PRT2_DR\r
-.set SCSI_In_DBx__4__INP_DIS, CYREG_PRT2_INP_DIS\r
-.set SCSI_In_DBx__4__INTTYPE, CYREG_PICU2_INTTYPE4\r
-.set SCSI_In_DBx__4__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG\r
-.set SCSI_In_DBx__4__LCD_EN, CYREG_PRT2_LCD_EN\r
-.set SCSI_In_DBx__4__MASK, 0x10\r
-.set SCSI_In_DBx__4__PC, CYREG_PRT2_PC4\r
-.set SCSI_In_DBx__4__PORT, 2\r
-.set SCSI_In_DBx__4__PRT, CYREG_PRT2_PRT\r
-.set SCSI_In_DBx__4__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL\r
-.set SCSI_In_DBx__4__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN\r
-.set SCSI_In_DBx__4__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0\r
-.set SCSI_In_DBx__4__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1\r
-.set SCSI_In_DBx__4__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0\r
-.set SCSI_In_DBx__4__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1\r
-.set SCSI_In_DBx__4__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT\r
-.set SCSI_In_DBx__4__PS, CYREG_PRT2_PS\r
-.set SCSI_In_DBx__4__SHIFT, 4\r
-.set SCSI_In_DBx__4__SLW, CYREG_PRT2_SLW\r
-.set SCSI_In_DBx__5__AG, CYREG_PRT2_AG\r
-.set SCSI_In_DBx__5__AMUX, CYREG_PRT2_AMUX\r
-.set SCSI_In_DBx__5__BIE, CYREG_PRT2_BIE\r
-.set SCSI_In_DBx__5__BIT_MASK, CYREG_PRT2_BIT_MASK\r
-.set SCSI_In_DBx__5__BYP, CYREG_PRT2_BYP\r
-.set SCSI_In_DBx__5__CTL, CYREG_PRT2_CTL\r
-.set SCSI_In_DBx__5__DM0, CYREG_PRT2_DM0\r
-.set SCSI_In_DBx__5__DM1, CYREG_PRT2_DM1\r
-.set SCSI_In_DBx__5__DM2, CYREG_PRT2_DM2\r
-.set SCSI_In_DBx__5__DR, CYREG_PRT2_DR\r
-.set SCSI_In_DBx__5__INP_DIS, CYREG_PRT2_INP_DIS\r
-.set SCSI_In_DBx__5__INTTYPE, CYREG_PICU2_INTTYPE3\r
-.set SCSI_In_DBx__5__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG\r
-.set SCSI_In_DBx__5__LCD_EN, CYREG_PRT2_LCD_EN\r
-.set SCSI_In_DBx__5__MASK, 0x08\r
-.set SCSI_In_DBx__5__PC, CYREG_PRT2_PC3\r
-.set SCSI_In_DBx__5__PORT, 2\r
-.set SCSI_In_DBx__5__PRT, CYREG_PRT2_PRT\r
-.set SCSI_In_DBx__5__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL\r
-.set SCSI_In_DBx__5__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN\r
-.set SCSI_In_DBx__5__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0\r
-.set SCSI_In_DBx__5__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1\r
-.set SCSI_In_DBx__5__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0\r
-.set SCSI_In_DBx__5__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1\r
-.set SCSI_In_DBx__5__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT\r
-.set SCSI_In_DBx__5__PS, CYREG_PRT2_PS\r
-.set SCSI_In_DBx__5__SHIFT, 3\r
-.set SCSI_In_DBx__5__SLW, CYREG_PRT2_SLW\r
-.set SCSI_In_DBx__6__AG, CYREG_PRT2_AG\r
-.set SCSI_In_DBx__6__AMUX, CYREG_PRT2_AMUX\r
-.set SCSI_In_DBx__6__BIE, CYREG_PRT2_BIE\r
-.set SCSI_In_DBx__6__BIT_MASK, CYREG_PRT2_BIT_MASK\r
-.set SCSI_In_DBx__6__BYP, CYREG_PRT2_BYP\r
-.set SCSI_In_DBx__6__CTL, CYREG_PRT2_CTL\r
-.set SCSI_In_DBx__6__DM0, CYREG_PRT2_DM0\r
-.set SCSI_In_DBx__6__DM1, CYREG_PRT2_DM1\r
-.set SCSI_In_DBx__6__DM2, CYREG_PRT2_DM2\r
-.set SCSI_In_DBx__6__DR, CYREG_PRT2_DR\r
-.set SCSI_In_DBx__6__INP_DIS, CYREG_PRT2_INP_DIS\r
-.set SCSI_In_DBx__6__INTTYPE, CYREG_PICU2_INTTYPE2\r
-.set SCSI_In_DBx__6__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG\r
-.set SCSI_In_DBx__6__LCD_EN, CYREG_PRT2_LCD_EN\r
-.set SCSI_In_DBx__6__MASK, 0x04\r
-.set SCSI_In_DBx__6__PC, CYREG_PRT2_PC2\r
-.set SCSI_In_DBx__6__PORT, 2\r
-.set SCSI_In_DBx__6__PRT, CYREG_PRT2_PRT\r
-.set SCSI_In_DBx__6__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL\r
-.set SCSI_In_DBx__6__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN\r
-.set SCSI_In_DBx__6__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0\r
-.set SCSI_In_DBx__6__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1\r
-.set SCSI_In_DBx__6__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0\r
-.set SCSI_In_DBx__6__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1\r
-.set SCSI_In_DBx__6__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT\r
-.set SCSI_In_DBx__6__PS, CYREG_PRT2_PS\r
-.set SCSI_In_DBx__6__SHIFT, 2\r
-.set SCSI_In_DBx__6__SLW, CYREG_PRT2_SLW\r
-.set SCSI_In_DBx__7__AG, CYREG_PRT2_AG\r
-.set SCSI_In_DBx__7__AMUX, CYREG_PRT2_AMUX\r
-.set SCSI_In_DBx__7__BIE, CYREG_PRT2_BIE\r
-.set SCSI_In_DBx__7__BIT_MASK, CYREG_PRT2_BIT_MASK\r
-.set SCSI_In_DBx__7__BYP, CYREG_PRT2_BYP\r
-.set SCSI_In_DBx__7__CTL, CYREG_PRT2_CTL\r
-.set SCSI_In_DBx__7__DM0, CYREG_PRT2_DM0\r
-.set SCSI_In_DBx__7__DM1, CYREG_PRT2_DM1\r
-.set SCSI_In_DBx__7__DM2, CYREG_PRT2_DM2\r
-.set SCSI_In_DBx__7__DR, CYREG_PRT2_DR\r
-.set SCSI_In_DBx__7__INP_DIS, CYREG_PRT2_INP_DIS\r
-.set SCSI_In_DBx__7__INTTYPE, CYREG_PICU2_INTTYPE1\r
-.set SCSI_In_DBx__7__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG\r
-.set SCSI_In_DBx__7__LCD_EN, CYREG_PRT2_LCD_EN\r
-.set SCSI_In_DBx__7__MASK, 0x02\r
-.set SCSI_In_DBx__7__PC, CYREG_PRT2_PC1\r
-.set SCSI_In_DBx__7__PORT, 2\r
-.set SCSI_In_DBx__7__PRT, CYREG_PRT2_PRT\r
-.set SCSI_In_DBx__7__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL\r
-.set SCSI_In_DBx__7__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN\r
-.set SCSI_In_DBx__7__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0\r
-.set SCSI_In_DBx__7__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1\r
-.set SCSI_In_DBx__7__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0\r
-.set SCSI_In_DBx__7__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1\r
-.set SCSI_In_DBx__7__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT\r
-.set SCSI_In_DBx__7__PS, CYREG_PRT2_PS\r
-.set SCSI_In_DBx__7__SHIFT, 1\r
-.set SCSI_In_DBx__7__SLW, CYREG_PRT2_SLW\r
-.set SCSI_In_DBx__DB0__AG, CYREG_PRT12_AG\r
-.set SCSI_In_DBx__DB0__BIE, CYREG_PRT12_BIE\r
-.set SCSI_In_DBx__DB0__BIT_MASK, CYREG_PRT12_BIT_MASK\r
-.set SCSI_In_DBx__DB0__BYP, CYREG_PRT12_BYP\r
-.set SCSI_In_DBx__DB0__DM0, CYREG_PRT12_DM0\r
-.set SCSI_In_DBx__DB0__DM1, CYREG_PRT12_DM1\r
-.set SCSI_In_DBx__DB0__DM2, CYREG_PRT12_DM2\r
-.set SCSI_In_DBx__DB0__DR, CYREG_PRT12_DR\r
-.set SCSI_In_DBx__DB0__INP_DIS, CYREG_PRT12_INP_DIS\r
-.set SCSI_In_DBx__DB0__INTTYPE, CYREG_PICU12_INTTYPE4\r
-.set SCSI_In_DBx__DB0__MASK, 0x10\r
-.set SCSI_In_DBx__DB0__PC, CYREG_PRT12_PC4\r
-.set SCSI_In_DBx__DB0__PORT, 12\r
-.set SCSI_In_DBx__DB0__PRT, CYREG_PRT12_PRT\r
-.set SCSI_In_DBx__DB0__PRTDSI__DBL_SYNC_IN, CYREG_PRT12_DBL_SYNC_IN\r
-.set SCSI_In_DBx__DB0__PRTDSI__OE_SEL0, CYREG_PRT12_OE_SEL0\r
-.set SCSI_In_DBx__DB0__PRTDSI__OE_SEL1, CYREG_PRT12_OE_SEL1\r
-.set SCSI_In_DBx__DB0__PRTDSI__OUT_SEL0, CYREG_PRT12_OUT_SEL0\r
-.set SCSI_In_DBx__DB0__PRTDSI__OUT_SEL1, CYREG_PRT12_OUT_SEL1\r
-.set SCSI_In_DBx__DB0__PRTDSI__SYNC_OUT, CYREG_PRT12_SYNC_OUT\r
-.set SCSI_In_DBx__DB0__PS, CYREG_PRT12_PS\r
-.set SCSI_In_DBx__DB0__SHIFT, 4\r
-.set SCSI_In_DBx__DB0__SIO_CFG, CYREG_PRT12_SIO_CFG\r
-.set SCSI_In_DBx__DB0__SIO_DIFF, CYREG_PRT12_SIO_DIFF\r
-.set SCSI_In_DBx__DB0__SIO_HYST_EN, CYREG_PRT12_SIO_HYST_EN\r
-.set SCSI_In_DBx__DB0__SIO_REG_HIFREQ, CYREG_PRT12_SIO_REG_HIFREQ\r
-.set SCSI_In_DBx__DB0__SLW, CYREG_PRT12_SLW\r
-.set SCSI_In_DBx__DB1__AG, CYREG_PRT2_AG\r
-.set SCSI_In_DBx__DB1__AMUX, CYREG_PRT2_AMUX\r
-.set SCSI_In_DBx__DB1__BIE, CYREG_PRT2_BIE\r
-.set SCSI_In_DBx__DB1__BIT_MASK, CYREG_PRT2_BIT_MASK\r
-.set SCSI_In_DBx__DB1__BYP, CYREG_PRT2_BYP\r
-.set SCSI_In_DBx__DB1__CTL, CYREG_PRT2_CTL\r
-.set SCSI_In_DBx__DB1__DM0, CYREG_PRT2_DM0\r
-.set SCSI_In_DBx__DB1__DM1, CYREG_PRT2_DM1\r
-.set SCSI_In_DBx__DB1__DM2, CYREG_PRT2_DM2\r
-.set SCSI_In_DBx__DB1__DR, CYREG_PRT2_DR\r
-.set SCSI_In_DBx__DB1__INP_DIS, CYREG_PRT2_INP_DIS\r
-.set SCSI_In_DBx__DB1__INTTYPE, CYREG_PICU2_INTTYPE7\r
-.set SCSI_In_DBx__DB1__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG\r
-.set SCSI_In_DBx__DB1__LCD_EN, CYREG_PRT2_LCD_EN\r
-.set SCSI_In_DBx__DB1__MASK, 0x80\r
-.set SCSI_In_DBx__DB1__PC, CYREG_PRT2_PC7\r
-.set SCSI_In_DBx__DB1__PORT, 2\r
-.set SCSI_In_DBx__DB1__PRT, CYREG_PRT2_PRT\r
-.set SCSI_In_DBx__DB1__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL\r
-.set SCSI_In_DBx__DB1__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN\r
-.set SCSI_In_DBx__DB1__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0\r
-.set SCSI_In_DBx__DB1__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1\r
-.set SCSI_In_DBx__DB1__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0\r
-.set SCSI_In_DBx__DB1__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1\r
-.set SCSI_In_DBx__DB1__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT\r
-.set SCSI_In_DBx__DB1__PS, CYREG_PRT2_PS\r
-.set SCSI_In_DBx__DB1__SHIFT, 7\r
-.set SCSI_In_DBx__DB1__SLW, CYREG_PRT2_SLW\r
-.set SCSI_In_DBx__DB2__AG, CYREG_PRT2_AG\r
-.set SCSI_In_DBx__DB2__AMUX, CYREG_PRT2_AMUX\r
-.set SCSI_In_DBx__DB2__BIE, CYREG_PRT2_BIE\r
-.set SCSI_In_DBx__DB2__BIT_MASK, CYREG_PRT2_BIT_MASK\r
-.set SCSI_In_DBx__DB2__BYP, CYREG_PRT2_BYP\r
-.set SCSI_In_DBx__DB2__CTL, CYREG_PRT2_CTL\r
-.set SCSI_In_DBx__DB2__DM0, CYREG_PRT2_DM0\r
-.set SCSI_In_DBx__DB2__DM1, CYREG_PRT2_DM1\r
-.set SCSI_In_DBx__DB2__DM2, CYREG_PRT2_DM2\r
-.set SCSI_In_DBx__DB2__DR, CYREG_PRT2_DR\r
-.set SCSI_In_DBx__DB2__INP_DIS, CYREG_PRT2_INP_DIS\r
-.set SCSI_In_DBx__DB2__INTTYPE, CYREG_PICU2_INTTYPE6\r
-.set SCSI_In_DBx__DB2__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG\r
-.set SCSI_In_DBx__DB2__LCD_EN, CYREG_PRT2_LCD_EN\r
-.set SCSI_In_DBx__DB2__MASK, 0x40\r
-.set SCSI_In_DBx__DB2__PC, CYREG_PRT2_PC6\r
-.set SCSI_In_DBx__DB2__PORT, 2\r
-.set SCSI_In_DBx__DB2__PRT, CYREG_PRT2_PRT\r
-.set SCSI_In_DBx__DB2__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL\r
-.set SCSI_In_DBx__DB2__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN\r
-.set SCSI_In_DBx__DB2__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0\r
-.set SCSI_In_DBx__DB2__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1\r
-.set SCSI_In_DBx__DB2__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0\r
-.set SCSI_In_DBx__DB2__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1\r
-.set SCSI_In_DBx__DB2__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT\r
-.set SCSI_In_DBx__DB2__PS, CYREG_PRT2_PS\r
-.set SCSI_In_DBx__DB2__SHIFT, 6\r
-.set SCSI_In_DBx__DB2__SLW, CYREG_PRT2_SLW\r
-.set SCSI_In_DBx__DB3__AG, CYREG_PRT2_AG\r
-.set SCSI_In_DBx__DB3__AMUX, CYREG_PRT2_AMUX\r
-.set SCSI_In_DBx__DB3__BIE, CYREG_PRT2_BIE\r
-.set SCSI_In_DBx__DB3__BIT_MASK, CYREG_PRT2_BIT_MASK\r
-.set SCSI_In_DBx__DB3__BYP, CYREG_PRT2_BYP\r
-.set SCSI_In_DBx__DB3__CTL, CYREG_PRT2_CTL\r
-.set SCSI_In_DBx__DB3__DM0, CYREG_PRT2_DM0\r
-.set SCSI_In_DBx__DB3__DM1, CYREG_PRT2_DM1\r
-.set SCSI_In_DBx__DB3__DM2, CYREG_PRT2_DM2\r
-.set SCSI_In_DBx__DB3__DR, CYREG_PRT2_DR\r
-.set SCSI_In_DBx__DB3__INP_DIS, CYREG_PRT2_INP_DIS\r
-.set SCSI_In_DBx__DB3__INTTYPE, CYREG_PICU2_INTTYPE5\r
-.set SCSI_In_DBx__DB3__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG\r
-.set SCSI_In_DBx__DB3__LCD_EN, CYREG_PRT2_LCD_EN\r
-.set SCSI_In_DBx__DB3__MASK, 0x20\r
-.set SCSI_In_DBx__DB3__PC, CYREG_PRT2_PC5\r
-.set SCSI_In_DBx__DB3__PORT, 2\r
-.set SCSI_In_DBx__DB3__PRT, CYREG_PRT2_PRT\r
-.set SCSI_In_DBx__DB3__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL\r
-.set SCSI_In_DBx__DB3__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN\r
-.set SCSI_In_DBx__DB3__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0\r
-.set SCSI_In_DBx__DB3__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1\r
-.set SCSI_In_DBx__DB3__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0\r
-.set SCSI_In_DBx__DB3__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1\r
-.set SCSI_In_DBx__DB3__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT\r
-.set SCSI_In_DBx__DB3__PS, CYREG_PRT2_PS\r
-.set SCSI_In_DBx__DB3__SHIFT, 5\r
-.set SCSI_In_DBx__DB3__SLW, CYREG_PRT2_SLW\r
-.set SCSI_In_DBx__DB4__AG, CYREG_PRT2_AG\r
-.set SCSI_In_DBx__DB4__AMUX, CYREG_PRT2_AMUX\r
-.set SCSI_In_DBx__DB4__BIE, CYREG_PRT2_BIE\r
-.set SCSI_In_DBx__DB4__BIT_MASK, CYREG_PRT2_BIT_MASK\r
-.set SCSI_In_DBx__DB4__BYP, CYREG_PRT2_BYP\r
-.set SCSI_In_DBx__DB4__CTL, CYREG_PRT2_CTL\r
-.set SCSI_In_DBx__DB4__DM0, CYREG_PRT2_DM0\r
-.set SCSI_In_DBx__DB4__DM1, CYREG_PRT2_DM1\r
-.set SCSI_In_DBx__DB4__DM2, CYREG_PRT2_DM2\r
-.set SCSI_In_DBx__DB4__DR, CYREG_PRT2_DR\r
-.set SCSI_In_DBx__DB4__INP_DIS, CYREG_PRT2_INP_DIS\r
-.set SCSI_In_DBx__DB4__INTTYPE, CYREG_PICU2_INTTYPE4\r
-.set SCSI_In_DBx__DB4__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG\r
-.set SCSI_In_DBx__DB4__LCD_EN, CYREG_PRT2_LCD_EN\r
-.set SCSI_In_DBx__DB4__MASK, 0x10\r
-.set SCSI_In_DBx__DB4__PC, CYREG_PRT2_PC4\r
-.set SCSI_In_DBx__DB4__PORT, 2\r
-.set SCSI_In_DBx__DB4__PRT, CYREG_PRT2_PRT\r
-.set SCSI_In_DBx__DB4__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL\r
-.set SCSI_In_DBx__DB4__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN\r
-.set SCSI_In_DBx__DB4__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0\r
-.set SCSI_In_DBx__DB4__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1\r
-.set SCSI_In_DBx__DB4__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0\r
-.set SCSI_In_DBx__DB4__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1\r
-.set SCSI_In_DBx__DB4__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT\r
-.set SCSI_In_DBx__DB4__PS, CYREG_PRT2_PS\r
-.set SCSI_In_DBx__DB4__SHIFT, 4\r
-.set SCSI_In_DBx__DB4__SLW, CYREG_PRT2_SLW\r
-.set SCSI_In_DBx__DB5__AG, CYREG_PRT2_AG\r
-.set SCSI_In_DBx__DB5__AMUX, CYREG_PRT2_AMUX\r
-.set SCSI_In_DBx__DB5__BIE, CYREG_PRT2_BIE\r
-.set SCSI_In_DBx__DB5__BIT_MASK, CYREG_PRT2_BIT_MASK\r
-.set SCSI_In_DBx__DB5__BYP, CYREG_PRT2_BYP\r
-.set SCSI_In_DBx__DB5__CTL, CYREG_PRT2_CTL\r
-.set SCSI_In_DBx__DB5__DM0, CYREG_PRT2_DM0\r
-.set SCSI_In_DBx__DB5__DM1, CYREG_PRT2_DM1\r
-.set SCSI_In_DBx__DB5__DM2, CYREG_PRT2_DM2\r
-.set SCSI_In_DBx__DB5__DR, CYREG_PRT2_DR\r
-.set SCSI_In_DBx__DB5__INP_DIS, CYREG_PRT2_INP_DIS\r
-.set SCSI_In_DBx__DB5__INTTYPE, CYREG_PICU2_INTTYPE3\r
-.set SCSI_In_DBx__DB5__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG\r
-.set SCSI_In_DBx__DB5__LCD_EN, CYREG_PRT2_LCD_EN\r
-.set SCSI_In_DBx__DB5__MASK, 0x08\r
-.set SCSI_In_DBx__DB5__PC, CYREG_PRT2_PC3\r
-.set SCSI_In_DBx__DB5__PORT, 2\r
-.set SCSI_In_DBx__DB5__PRT, CYREG_PRT2_PRT\r
-.set SCSI_In_DBx__DB5__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL\r
-.set SCSI_In_DBx__DB5__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN\r
-.set SCSI_In_DBx__DB5__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0\r
-.set SCSI_In_DBx__DB5__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1\r
-.set SCSI_In_DBx__DB5__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0\r
-.set SCSI_In_DBx__DB5__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1\r
-.set SCSI_In_DBx__DB5__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT\r
-.set SCSI_In_DBx__DB5__PS, CYREG_PRT2_PS\r
-.set SCSI_In_DBx__DB5__SHIFT, 3\r
-.set SCSI_In_DBx__DB5__SLW, CYREG_PRT2_SLW\r
-.set SCSI_In_DBx__DB6__AG, CYREG_PRT2_AG\r
-.set SCSI_In_DBx__DB6__AMUX, CYREG_PRT2_AMUX\r
-.set SCSI_In_DBx__DB6__BIE, CYREG_PRT2_BIE\r
-.set SCSI_In_DBx__DB6__BIT_MASK, CYREG_PRT2_BIT_MASK\r
-.set SCSI_In_DBx__DB6__BYP, CYREG_PRT2_BYP\r
-.set SCSI_In_DBx__DB6__CTL, CYREG_PRT2_CTL\r
-.set SCSI_In_DBx__DB6__DM0, CYREG_PRT2_DM0\r
-.set SCSI_In_DBx__DB6__DM1, CYREG_PRT2_DM1\r
-.set SCSI_In_DBx__DB6__DM2, CYREG_PRT2_DM2\r
-.set SCSI_In_DBx__DB6__DR, CYREG_PRT2_DR\r
-.set SCSI_In_DBx__DB6__INP_DIS, CYREG_PRT2_INP_DIS\r
-.set SCSI_In_DBx__DB6__INTTYPE, CYREG_PICU2_INTTYPE2\r
-.set SCSI_In_DBx__DB6__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG\r
-.set SCSI_In_DBx__DB6__LCD_EN, CYREG_PRT2_LCD_EN\r
-.set SCSI_In_DBx__DB6__MASK, 0x04\r
-.set SCSI_In_DBx__DB6__PC, CYREG_PRT2_PC2\r
-.set SCSI_In_DBx__DB6__PORT, 2\r
-.set SCSI_In_DBx__DB6__PRT, CYREG_PRT2_PRT\r
-.set SCSI_In_DBx__DB6__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL\r
-.set SCSI_In_DBx__DB6__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN\r
-.set SCSI_In_DBx__DB6__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0\r
-.set SCSI_In_DBx__DB6__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1\r
-.set SCSI_In_DBx__DB6__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0\r
-.set SCSI_In_DBx__DB6__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1\r
-.set SCSI_In_DBx__DB6__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT\r
-.set SCSI_In_DBx__DB6__PS, CYREG_PRT2_PS\r
-.set SCSI_In_DBx__DB6__SHIFT, 2\r
-.set SCSI_In_DBx__DB6__SLW, CYREG_PRT2_SLW\r
-.set SCSI_In_DBx__DB7__AG, CYREG_PRT2_AG\r
-.set SCSI_In_DBx__DB7__AMUX, CYREG_PRT2_AMUX\r
-.set SCSI_In_DBx__DB7__BIE, CYREG_PRT2_BIE\r
-.set SCSI_In_DBx__DB7__BIT_MASK, CYREG_PRT2_BIT_MASK\r
-.set SCSI_In_DBx__DB7__BYP, CYREG_PRT2_BYP\r
-.set SCSI_In_DBx__DB7__CTL, CYREG_PRT2_CTL\r
-.set SCSI_In_DBx__DB7__DM0, CYREG_PRT2_DM0\r
-.set SCSI_In_DBx__DB7__DM1, CYREG_PRT2_DM1\r
-.set SCSI_In_DBx__DB7__DM2, CYREG_PRT2_DM2\r
-.set SCSI_In_DBx__DB7__DR, CYREG_PRT2_DR\r
-.set SCSI_In_DBx__DB7__INP_DIS, CYREG_PRT2_INP_DIS\r
-.set SCSI_In_DBx__DB7__INTTYPE, CYREG_PICU2_INTTYPE1\r
-.set SCSI_In_DBx__DB7__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG\r
-.set SCSI_In_DBx__DB7__LCD_EN, CYREG_PRT2_LCD_EN\r
-.set SCSI_In_DBx__DB7__MASK, 0x02\r
-.set SCSI_In_DBx__DB7__PC, CYREG_PRT2_PC1\r
-.set SCSI_In_DBx__DB7__PORT, 2\r
-.set SCSI_In_DBx__DB7__PRT, CYREG_PRT2_PRT\r
-.set SCSI_In_DBx__DB7__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL\r
-.set SCSI_In_DBx__DB7__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN\r
-.set SCSI_In_DBx__DB7__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0\r
-.set SCSI_In_DBx__DB7__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1\r
-.set SCSI_In_DBx__DB7__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0\r
-.set SCSI_In_DBx__DB7__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1\r
-.set SCSI_In_DBx__DB7__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT\r
-.set SCSI_In_DBx__DB7__PS, CYREG_PRT2_PS\r
-.set SCSI_In_DBx__DB7__SHIFT, 1\r
-.set SCSI_In_DBx__DB7__SLW, CYREG_PRT2_SLW\r
-\r
-/* SD_DAT1 */\r
-.set SD_DAT1__0__INTTYPE, CYREG_PICU3_INTTYPE0\r
-.set SD_DAT1__0__MASK, 0x01\r
-.set SD_DAT1__0__PC, CYREG_PRT3_PC0\r
-.set SD_DAT1__0__PORT, 3\r
-.set SD_DAT1__0__SHIFT, 0\r
-.set SD_DAT1__AG, CYREG_PRT3_AG\r
-.set SD_DAT1__AMUX, CYREG_PRT3_AMUX\r
-.set SD_DAT1__BIE, CYREG_PRT3_BIE\r
-.set SD_DAT1__BIT_MASK, CYREG_PRT3_BIT_MASK\r
-.set SD_DAT1__BYP, CYREG_PRT3_BYP\r
-.set SD_DAT1__CTL, CYREG_PRT3_CTL\r
-.set SD_DAT1__DM0, CYREG_PRT3_DM0\r
-.set SD_DAT1__DM1, CYREG_PRT3_DM1\r
-.set SD_DAT1__DM2, CYREG_PRT3_DM2\r
-.set SD_DAT1__DR, CYREG_PRT3_DR\r
-.set SD_DAT1__INP_DIS, CYREG_PRT3_INP_DIS\r
-.set SD_DAT1__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU3_BASE\r
-.set SD_DAT1__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG\r
-.set SD_DAT1__LCD_EN, CYREG_PRT3_LCD_EN\r
-.set SD_DAT1__MASK, 0x01\r
-.set SD_DAT1__PORT, 3\r
-.set SD_DAT1__PRT, CYREG_PRT3_PRT\r
-.set SD_DAT1__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL\r
-.set SD_DAT1__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN\r
-.set SD_DAT1__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0\r
-.set SD_DAT1__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1\r
-.set SD_DAT1__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0\r
-.set SD_DAT1__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1\r
-.set SD_DAT1__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT\r
-.set SD_DAT1__PS, CYREG_PRT3_PS\r
-.set SD_DAT1__SHIFT, 0\r
-.set SD_DAT1__SLW, CYREG_PRT3_SLW\r
-\r
-/* SD_DAT2 */\r
-.set SD_DAT2__0__INTTYPE, CYREG_PICU3_INTTYPE5\r
-.set SD_DAT2__0__MASK, 0x20\r
-.set SD_DAT2__0__PC, CYREG_PRT3_PC5\r
-.set SD_DAT2__0__PORT, 3\r
-.set SD_DAT2__0__SHIFT, 5\r
-.set SD_DAT2__AG, CYREG_PRT3_AG\r
-.set SD_DAT2__AMUX, CYREG_PRT3_AMUX\r
-.set SD_DAT2__BIE, CYREG_PRT3_BIE\r
-.set SD_DAT2__BIT_MASK, CYREG_PRT3_BIT_MASK\r
-.set SD_DAT2__BYP, CYREG_PRT3_BYP\r
-.set SD_DAT2__CTL, CYREG_PRT3_CTL\r
-.set SD_DAT2__DM0, CYREG_PRT3_DM0\r
-.set SD_DAT2__DM1, CYREG_PRT3_DM1\r
-.set SD_DAT2__DM2, CYREG_PRT3_DM2\r
-.set SD_DAT2__DR, CYREG_PRT3_DR\r
-.set SD_DAT2__INP_DIS, CYREG_PRT3_INP_DIS\r
-.set SD_DAT2__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU3_BASE\r
-.set SD_DAT2__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG\r
-.set SD_DAT2__LCD_EN, CYREG_PRT3_LCD_EN\r
-.set SD_DAT2__MASK, 0x20\r
-.set SD_DAT2__PORT, 3\r
-.set SD_DAT2__PRT, CYREG_PRT3_PRT\r
-.set SD_DAT2__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL\r
-.set SD_DAT2__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN\r
-.set SD_DAT2__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0\r
-.set SD_DAT2__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1\r
-.set SD_DAT2__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0\r
-.set SD_DAT2__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1\r
-.set SD_DAT2__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT\r
-.set SD_DAT2__PS, CYREG_PRT3_PS\r
-.set SD_DAT2__SHIFT, 5\r
-.set SD_DAT2__SLW, CYREG_PRT3_SLW\r
-\r
-/* SD_MISO */\r
-.set SD_MISO__0__INTTYPE, CYREG_PICU3_INTTYPE1\r
-.set SD_MISO__0__MASK, 0x02\r
-.set SD_MISO__0__PC, CYREG_PRT3_PC1\r
-.set SD_MISO__0__PORT, 3\r
-.set SD_MISO__0__SHIFT, 1\r
-.set SD_MISO__AG, CYREG_PRT3_AG\r
-.set SD_MISO__AMUX, CYREG_PRT3_AMUX\r
-.set SD_MISO__BIE, CYREG_PRT3_BIE\r
-.set SD_MISO__BIT_MASK, CYREG_PRT3_BIT_MASK\r
-.set SD_MISO__BYP, CYREG_PRT3_BYP\r
-.set SD_MISO__CTL, CYREG_PRT3_CTL\r
-.set SD_MISO__DM0, CYREG_PRT3_DM0\r
-.set SD_MISO__DM1, CYREG_PRT3_DM1\r
-.set SD_MISO__DM2, CYREG_PRT3_DM2\r
-.set SD_MISO__DR, CYREG_PRT3_DR\r
-.set SD_MISO__INP_DIS, CYREG_PRT3_INP_DIS\r
-.set SD_MISO__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU3_BASE\r
-.set SD_MISO__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG\r
-.set SD_MISO__LCD_EN, CYREG_PRT3_LCD_EN\r
-.set SD_MISO__MASK, 0x02\r
-.set SD_MISO__PORT, 3\r
-.set SD_MISO__PRT, CYREG_PRT3_PRT\r
-.set SD_MISO__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL\r
-.set SD_MISO__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN\r
-.set SD_MISO__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0\r
-.set SD_MISO__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1\r
-.set SD_MISO__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0\r
-.set SD_MISO__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1\r
-.set SD_MISO__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT\r
-.set SD_MISO__PS, CYREG_PRT3_PS\r
-.set SD_MISO__SHIFT, 1\r
-.set SD_MISO__SLW, CYREG_PRT3_SLW\r
-\r
-/* SD_MOSI */\r
-.set SD_MOSI__0__INTTYPE, CYREG_PICU3_INTTYPE3\r
-.set SD_MOSI__0__MASK, 0x08\r
-.set SD_MOSI__0__PC, CYREG_PRT3_PC3\r
-.set SD_MOSI__0__PORT, 3\r
-.set SD_MOSI__0__SHIFT, 3\r
-.set SD_MOSI__AG, CYREG_PRT3_AG\r
-.set SD_MOSI__AMUX, CYREG_PRT3_AMUX\r
-.set SD_MOSI__BIE, CYREG_PRT3_BIE\r
-.set SD_MOSI__BIT_MASK, CYREG_PRT3_BIT_MASK\r
-.set SD_MOSI__BYP, CYREG_PRT3_BYP\r
-.set SD_MOSI__CTL, CYREG_PRT3_CTL\r
-.set SD_MOSI__DM0, CYREG_PRT3_DM0\r
-.set SD_MOSI__DM1, CYREG_PRT3_DM1\r
-.set SD_MOSI__DM2, CYREG_PRT3_DM2\r
-.set SD_MOSI__DR, CYREG_PRT3_DR\r
-.set SD_MOSI__INP_DIS, CYREG_PRT3_INP_DIS\r
-.set SD_MOSI__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU3_BASE\r
-.set SD_MOSI__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG\r
-.set SD_MOSI__LCD_EN, CYREG_PRT3_LCD_EN\r
-.set SD_MOSI__MASK, 0x08\r
-.set SD_MOSI__PORT, 3\r
-.set SD_MOSI__PRT, CYREG_PRT3_PRT\r
-.set SD_MOSI__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL\r
-.set SD_MOSI__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN\r
-.set SD_MOSI__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0\r
-.set SD_MOSI__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1\r
-.set SD_MOSI__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0\r
-.set SD_MOSI__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1\r
-.set SD_MOSI__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT\r
-.set SD_MOSI__PS, CYREG_PRT3_PS\r
-.set SD_MOSI__SHIFT, 3\r
-.set SD_MOSI__SLW, CYREG_PRT3_SLW\r
-\r
-/* SCSI_CLK */\r
-.set SCSI_CLK__CFG0, CYREG_CLKDIST_DCFG1_CFG0\r
-.set SCSI_CLK__CFG1, CYREG_CLKDIST_DCFG1_CFG1\r
-.set SCSI_CLK__CFG2, CYREG_CLKDIST_DCFG1_CFG2\r
-.set SCSI_CLK__CFG2_SRC_SEL_MASK, 0x07\r
-.set SCSI_CLK__INDEX, 0x01\r
-.set SCSI_CLK__PM_ACT_CFG, CYREG_PM_ACT_CFG2\r
-.set SCSI_CLK__PM_ACT_MSK, 0x02\r
-.set SCSI_CLK__PM_STBY_CFG, CYREG_PM_STBY_CFG2\r
-.set SCSI_CLK__PM_STBY_MSK, 0x02\r
-\r
-/* SCSI_Out */\r
-.set SCSI_Out__0__AG, CYREG_PRT4_AG\r
-.set SCSI_Out__0__AMUX, CYREG_PRT4_AMUX\r
-.set SCSI_Out__0__BIE, CYREG_PRT4_BIE\r
-.set SCSI_Out__0__BIT_MASK, CYREG_PRT4_BIT_MASK\r
-.set SCSI_Out__0__BYP, CYREG_PRT4_BYP\r
-.set SCSI_Out__0__CTL, CYREG_PRT4_CTL\r
-.set SCSI_Out__0__DM0, CYREG_PRT4_DM0\r
-.set SCSI_Out__0__DM1, CYREG_PRT4_DM1\r
-.set SCSI_Out__0__DM2, CYREG_PRT4_DM2\r
-.set SCSI_Out__0__DR, CYREG_PRT4_DR\r
-.set SCSI_Out__0__INP_DIS, CYREG_PRT4_INP_DIS\r
-.set SCSI_Out__0__INTTYPE, CYREG_PICU4_INTTYPE3\r
-.set SCSI_Out__0__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG\r
-.set SCSI_Out__0__LCD_EN, CYREG_PRT4_LCD_EN\r
-.set SCSI_Out__0__MASK, 0x08\r
-.set SCSI_Out__0__PC, CYREG_PRT4_PC3\r
-.set SCSI_Out__0__PORT, 4\r
-.set SCSI_Out__0__PRT, CYREG_PRT4_PRT\r
-.set SCSI_Out__0__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL\r
-.set SCSI_Out__0__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN\r
-.set SCSI_Out__0__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0\r
-.set SCSI_Out__0__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1\r
-.set SCSI_Out__0__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0\r
-.set SCSI_Out__0__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1\r
-.set SCSI_Out__0__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT\r
-.set SCSI_Out__0__PS, CYREG_PRT4_PS\r
-.set SCSI_Out__0__SHIFT, 3\r
-.set SCSI_Out__0__SLW, CYREG_PRT4_SLW\r
-.set SCSI_Out__1__AG, CYREG_PRT4_AG\r
-.set SCSI_Out__1__AMUX, CYREG_PRT4_AMUX\r
-.set SCSI_Out__1__BIE, CYREG_PRT4_BIE\r
-.set SCSI_Out__1__BIT_MASK, CYREG_PRT4_BIT_MASK\r
-.set SCSI_Out__1__BYP, CYREG_PRT4_BYP\r
-.set SCSI_Out__1__CTL, CYREG_PRT4_CTL\r
-.set SCSI_Out__1__DM0, CYREG_PRT4_DM0\r
-.set SCSI_Out__1__DM1, CYREG_PRT4_DM1\r
-.set SCSI_Out__1__DM2, CYREG_PRT4_DM2\r
-.set SCSI_Out__1__DR, CYREG_PRT4_DR\r
-.set SCSI_Out__1__INP_DIS, CYREG_PRT4_INP_DIS\r
-.set SCSI_Out__1__INTTYPE, CYREG_PICU4_INTTYPE2\r
-.set SCSI_Out__1__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG\r
-.set SCSI_Out__1__LCD_EN, CYREG_PRT4_LCD_EN\r
-.set SCSI_Out__1__MASK, 0x04\r
-.set SCSI_Out__1__PC, CYREG_PRT4_PC2\r
-.set SCSI_Out__1__PORT, 4\r
-.set SCSI_Out__1__PRT, CYREG_PRT4_PRT\r
-.set SCSI_Out__1__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL\r
-.set SCSI_Out__1__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN\r
-.set SCSI_Out__1__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0\r
-.set SCSI_Out__1__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1\r
-.set SCSI_Out__1__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0\r
-.set SCSI_Out__1__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1\r
-.set SCSI_Out__1__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT\r
-.set SCSI_Out__1__PS, CYREG_PRT4_PS\r
-.set SCSI_Out__1__SHIFT, 2\r
-.set SCSI_Out__1__SLW, CYREG_PRT4_SLW\r
-.set SCSI_Out__2__AG, CYREG_PRT0_AG\r
-.set SCSI_Out__2__AMUX, CYREG_PRT0_AMUX\r
-.set SCSI_Out__2__BIE, CYREG_PRT0_BIE\r
-.set SCSI_Out__2__BIT_MASK, CYREG_PRT0_BIT_MASK\r
-.set SCSI_Out__2__BYP, CYREG_PRT0_BYP\r
-.set SCSI_Out__2__CTL, CYREG_PRT0_CTL\r
-.set SCSI_Out__2__DM0, CYREG_PRT0_DM0\r
-.set SCSI_Out__2__DM1, CYREG_PRT0_DM1\r
-.set SCSI_Out__2__DM2, CYREG_PRT0_DM2\r
-.set SCSI_Out__2__DR, CYREG_PRT0_DR\r
-.set SCSI_Out__2__INP_DIS, CYREG_PRT0_INP_DIS\r
-.set SCSI_Out__2__INTTYPE, CYREG_PICU0_INTTYPE7\r
-.set SCSI_Out__2__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG\r
-.set SCSI_Out__2__LCD_EN, CYREG_PRT0_LCD_EN\r
-.set SCSI_Out__2__MASK, 0x80\r
-.set SCSI_Out__2__PC, CYREG_PRT0_PC7\r
-.set SCSI_Out__2__PORT, 0\r
-.set SCSI_Out__2__PRT, CYREG_PRT0_PRT\r
-.set SCSI_Out__2__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL\r
-.set SCSI_Out__2__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN\r
-.set SCSI_Out__2__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0\r
-.set SCSI_Out__2__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1\r
-.set SCSI_Out__2__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0\r
-.set SCSI_Out__2__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1\r
-.set SCSI_Out__2__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT\r
-.set SCSI_Out__2__PS, CYREG_PRT0_PS\r
-.set SCSI_Out__2__SHIFT, 7\r
-.set SCSI_Out__2__SLW, CYREG_PRT0_SLW\r
-.set SCSI_Out__3__AG, CYREG_PRT0_AG\r
-.set SCSI_Out__3__AMUX, CYREG_PRT0_AMUX\r
-.set SCSI_Out__3__BIE, CYREG_PRT0_BIE\r
-.set SCSI_Out__3__BIT_MASK, CYREG_PRT0_BIT_MASK\r
-.set SCSI_Out__3__BYP, CYREG_PRT0_BYP\r
-.set SCSI_Out__3__CTL, CYREG_PRT0_CTL\r
-.set SCSI_Out__3__DM0, CYREG_PRT0_DM0\r
-.set SCSI_Out__3__DM1, CYREG_PRT0_DM1\r
-.set SCSI_Out__3__DM2, CYREG_PRT0_DM2\r
-.set SCSI_Out__3__DR, CYREG_PRT0_DR\r
-.set SCSI_Out__3__INP_DIS, CYREG_PRT0_INP_DIS\r
-.set SCSI_Out__3__INTTYPE, CYREG_PICU0_INTTYPE6\r
-.set SCSI_Out__3__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG\r
-.set SCSI_Out__3__LCD_EN, CYREG_PRT0_LCD_EN\r
-.set SCSI_Out__3__MASK, 0x40\r
-.set SCSI_Out__3__PC, CYREG_PRT0_PC6\r
-.set SCSI_Out__3__PORT, 0\r
-.set SCSI_Out__3__PRT, CYREG_PRT0_PRT\r
-.set SCSI_Out__3__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL\r
-.set SCSI_Out__3__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN\r
-.set SCSI_Out__3__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0\r
-.set SCSI_Out__3__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1\r
-.set SCSI_Out__3__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0\r
-.set SCSI_Out__3__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1\r
-.set SCSI_Out__3__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT\r
-.set SCSI_Out__3__PS, CYREG_PRT0_PS\r
-.set SCSI_Out__3__SHIFT, 6\r
-.set SCSI_Out__3__SLW, CYREG_PRT0_SLW\r
-.set SCSI_Out__4__AG, CYREG_PRT0_AG\r
-.set SCSI_Out__4__AMUX, CYREG_PRT0_AMUX\r
-.set SCSI_Out__4__BIE, CYREG_PRT0_BIE\r
-.set SCSI_Out__4__BIT_MASK, CYREG_PRT0_BIT_MASK\r
-.set SCSI_Out__4__BYP, CYREG_PRT0_BYP\r
-.set SCSI_Out__4__CTL, CYREG_PRT0_CTL\r
-.set SCSI_Out__4__DM0, CYREG_PRT0_DM0\r
-.set SCSI_Out__4__DM1, CYREG_PRT0_DM1\r
-.set SCSI_Out__4__DM2, CYREG_PRT0_DM2\r
-.set SCSI_Out__4__DR, CYREG_PRT0_DR\r
-.set SCSI_Out__4__INP_DIS, CYREG_PRT0_INP_DIS\r
-.set SCSI_Out__4__INTTYPE, CYREG_PICU0_INTTYPE5\r
-.set SCSI_Out__4__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG\r
-.set SCSI_Out__4__LCD_EN, CYREG_PRT0_LCD_EN\r
-.set SCSI_Out__4__MASK, 0x20\r
-.set SCSI_Out__4__PC, CYREG_PRT0_PC5\r
-.set SCSI_Out__4__PORT, 0\r
-.set SCSI_Out__4__PRT, CYREG_PRT0_PRT\r
-.set SCSI_Out__4__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL\r
-.set SCSI_Out__4__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN\r
-.set SCSI_Out__4__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0\r
-.set SCSI_Out__4__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1\r
-.set SCSI_Out__4__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0\r
-.set SCSI_Out__4__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1\r
-.set SCSI_Out__4__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT\r
-.set SCSI_Out__4__PS, CYREG_PRT0_PS\r
-.set SCSI_Out__4__SHIFT, 5\r
-.set SCSI_Out__4__SLW, CYREG_PRT0_SLW\r
-.set SCSI_Out__5__AG, CYREG_PRT0_AG\r
-.set SCSI_Out__5__AMUX, CYREG_PRT0_AMUX\r
-.set SCSI_Out__5__BIE, CYREG_PRT0_BIE\r
-.set SCSI_Out__5__BIT_MASK, CYREG_PRT0_BIT_MASK\r
-.set SCSI_Out__5__BYP, CYREG_PRT0_BYP\r
-.set SCSI_Out__5__CTL, CYREG_PRT0_CTL\r
-.set SCSI_Out__5__DM0, CYREG_PRT0_DM0\r
-.set SCSI_Out__5__DM1, CYREG_PRT0_DM1\r
-.set SCSI_Out__5__DM2, CYREG_PRT0_DM2\r
-.set SCSI_Out__5__DR, CYREG_PRT0_DR\r
-.set SCSI_Out__5__INP_DIS, CYREG_PRT0_INP_DIS\r
-.set SCSI_Out__5__INTTYPE, CYREG_PICU0_INTTYPE4\r
-.set SCSI_Out__5__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG\r
-.set SCSI_Out__5__LCD_EN, CYREG_PRT0_LCD_EN\r
-.set SCSI_Out__5__MASK, 0x10\r
-.set SCSI_Out__5__PC, CYREG_PRT0_PC4\r
-.set SCSI_Out__5__PORT, 0\r
-.set SCSI_Out__5__PRT, CYREG_PRT0_PRT\r
-.set SCSI_Out__5__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL\r
-.set SCSI_Out__5__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN\r
-.set SCSI_Out__5__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0\r
-.set SCSI_Out__5__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1\r
-.set SCSI_Out__5__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0\r
-.set SCSI_Out__5__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1\r
-.set SCSI_Out__5__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT\r
-.set SCSI_Out__5__PS, CYREG_PRT0_PS\r
-.set SCSI_Out__5__SHIFT, 4\r
-.set SCSI_Out__5__SLW, CYREG_PRT0_SLW\r
-.set SCSI_Out__6__AG, CYREG_PRT0_AG\r
-.set SCSI_Out__6__AMUX, CYREG_PRT0_AMUX\r
-.set SCSI_Out__6__BIE, CYREG_PRT0_BIE\r
-.set SCSI_Out__6__BIT_MASK, CYREG_PRT0_BIT_MASK\r
-.set SCSI_Out__6__BYP, CYREG_PRT0_BYP\r
-.set SCSI_Out__6__CTL, CYREG_PRT0_CTL\r
-.set SCSI_Out__6__DM0, CYREG_PRT0_DM0\r
-.set SCSI_Out__6__DM1, CYREG_PRT0_DM1\r
-.set SCSI_Out__6__DM2, CYREG_PRT0_DM2\r
-.set SCSI_Out__6__DR, CYREG_PRT0_DR\r
-.set SCSI_Out__6__INP_DIS, CYREG_PRT0_INP_DIS\r
-.set SCSI_Out__6__INTTYPE, CYREG_PICU0_INTTYPE3\r
-.set SCSI_Out__6__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG\r
-.set SCSI_Out__6__LCD_EN, CYREG_PRT0_LCD_EN\r
-.set SCSI_Out__6__MASK, 0x08\r
-.set SCSI_Out__6__PC, CYREG_PRT0_PC3\r
-.set SCSI_Out__6__PORT, 0\r
-.set SCSI_Out__6__PRT, CYREG_PRT0_PRT\r
-.set SCSI_Out__6__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL\r
-.set SCSI_Out__6__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN\r
-.set SCSI_Out__6__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0\r
-.set SCSI_Out__6__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1\r
-.set SCSI_Out__6__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0\r
-.set SCSI_Out__6__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1\r
-.set SCSI_Out__6__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT\r
-.set SCSI_Out__6__PS, CYREG_PRT0_PS\r
-.set SCSI_Out__6__SHIFT, 3\r
-.set SCSI_Out__6__SLW, CYREG_PRT0_SLW\r
-.set SCSI_Out__7__AG, CYREG_PRT0_AG\r
-.set SCSI_Out__7__AMUX, CYREG_PRT0_AMUX\r
-.set SCSI_Out__7__BIE, CYREG_PRT0_BIE\r
-.set SCSI_Out__7__BIT_MASK, CYREG_PRT0_BIT_MASK\r
-.set SCSI_Out__7__BYP, CYREG_PRT0_BYP\r
-.set SCSI_Out__7__CTL, CYREG_PRT0_CTL\r
-.set SCSI_Out__7__DM0, CYREG_PRT0_DM0\r
-.set SCSI_Out__7__DM1, CYREG_PRT0_DM1\r
-.set SCSI_Out__7__DM2, CYREG_PRT0_DM2\r
-.set SCSI_Out__7__DR, CYREG_PRT0_DR\r
-.set SCSI_Out__7__INP_DIS, CYREG_PRT0_INP_DIS\r
-.set SCSI_Out__7__INTTYPE, CYREG_PICU0_INTTYPE2\r
-.set SCSI_Out__7__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG\r
-.set SCSI_Out__7__LCD_EN, CYREG_PRT0_LCD_EN\r
-.set SCSI_Out__7__MASK, 0x04\r
-.set SCSI_Out__7__PC, CYREG_PRT0_PC2\r
-.set SCSI_Out__7__PORT, 0\r
-.set SCSI_Out__7__PRT, CYREG_PRT0_PRT\r
-.set SCSI_Out__7__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL\r
-.set SCSI_Out__7__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN\r
-.set SCSI_Out__7__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0\r
-.set SCSI_Out__7__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1\r
-.set SCSI_Out__7__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0\r
-.set SCSI_Out__7__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1\r
-.set SCSI_Out__7__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT\r
-.set SCSI_Out__7__PS, CYREG_PRT0_PS\r
-.set SCSI_Out__7__SHIFT, 2\r
-.set SCSI_Out__7__SLW, CYREG_PRT0_SLW\r
-.set SCSI_Out__8__AG, CYREG_PRT0_AG\r
-.set SCSI_Out__8__AMUX, CYREG_PRT0_AMUX\r
-.set SCSI_Out__8__BIE, CYREG_PRT0_BIE\r
-.set SCSI_Out__8__BIT_MASK, CYREG_PRT0_BIT_MASK\r
-.set SCSI_Out__8__BYP, CYREG_PRT0_BYP\r
-.set SCSI_Out__8__CTL, CYREG_PRT0_CTL\r
-.set SCSI_Out__8__DM0, CYREG_PRT0_DM0\r
-.set SCSI_Out__8__DM1, CYREG_PRT0_DM1\r
-.set SCSI_Out__8__DM2, CYREG_PRT0_DM2\r
-.set SCSI_Out__8__DR, CYREG_PRT0_DR\r
-.set SCSI_Out__8__INP_DIS, CYREG_PRT0_INP_DIS\r
-.set SCSI_Out__8__INTTYPE, CYREG_PICU0_INTTYPE1\r
-.set SCSI_Out__8__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG\r
-.set SCSI_Out__8__LCD_EN, CYREG_PRT0_LCD_EN\r
-.set SCSI_Out__8__MASK, 0x02\r
-.set SCSI_Out__8__PC, CYREG_PRT0_PC1\r
-.set SCSI_Out__8__PORT, 0\r
-.set SCSI_Out__8__PRT, CYREG_PRT0_PRT\r
-.set SCSI_Out__8__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL\r
-.set SCSI_Out__8__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN\r
-.set SCSI_Out__8__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0\r
-.set SCSI_Out__8__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1\r
-.set SCSI_Out__8__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0\r
-.set SCSI_Out__8__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1\r
-.set SCSI_Out__8__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT\r
-.set SCSI_Out__8__PS, CYREG_PRT0_PS\r
-.set SCSI_Out__8__SHIFT, 1\r
-.set SCSI_Out__8__SLW, CYREG_PRT0_SLW\r
-.set SCSI_Out__9__AG, CYREG_PRT0_AG\r
-.set SCSI_Out__9__AMUX, CYREG_PRT0_AMUX\r
-.set SCSI_Out__9__BIE, CYREG_PRT0_BIE\r
-.set SCSI_Out__9__BIT_MASK, CYREG_PRT0_BIT_MASK\r
-.set SCSI_Out__9__BYP, CYREG_PRT0_BYP\r
-.set SCSI_Out__9__CTL, CYREG_PRT0_CTL\r
-.set SCSI_Out__9__DM0, CYREG_PRT0_DM0\r
-.set SCSI_Out__9__DM1, CYREG_PRT0_DM1\r
-.set SCSI_Out__9__DM2, CYREG_PRT0_DM2\r
-.set SCSI_Out__9__DR, CYREG_PRT0_DR\r
-.set SCSI_Out__9__INP_DIS, CYREG_PRT0_INP_DIS\r
-.set SCSI_Out__9__INTTYPE, CYREG_PICU0_INTTYPE0\r
-.set SCSI_Out__9__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG\r
-.set SCSI_Out__9__LCD_EN, CYREG_PRT0_LCD_EN\r
-.set SCSI_Out__9__MASK, 0x01\r
-.set SCSI_Out__9__PC, CYREG_PRT0_PC0\r
-.set SCSI_Out__9__PORT, 0\r
-.set SCSI_Out__9__PRT, CYREG_PRT0_PRT\r
-.set SCSI_Out__9__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL\r
-.set SCSI_Out__9__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN\r
-.set SCSI_Out__9__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0\r
-.set SCSI_Out__9__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1\r
-.set SCSI_Out__9__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0\r
-.set SCSI_Out__9__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1\r
-.set SCSI_Out__9__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT\r
-.set SCSI_Out__9__PS, CYREG_PRT0_PS\r
-.set SCSI_Out__9__SHIFT, 0\r
-.set SCSI_Out__9__SLW, CYREG_PRT0_SLW\r
-.set SCSI_Out__ACK__AG, CYREG_PRT0_AG\r
-.set SCSI_Out__ACK__AMUX, CYREG_PRT0_AMUX\r
-.set SCSI_Out__ACK__BIE, CYREG_PRT0_BIE\r
-.set SCSI_Out__ACK__BIT_MASK, CYREG_PRT0_BIT_MASK\r
-.set SCSI_Out__ACK__BYP, CYREG_PRT0_BYP\r
-.set SCSI_Out__ACK__CTL, CYREG_PRT0_CTL\r
-.set SCSI_Out__ACK__DM0, CYREG_PRT0_DM0\r
-.set SCSI_Out__ACK__DM1, CYREG_PRT0_DM1\r
-.set SCSI_Out__ACK__DM2, CYREG_PRT0_DM2\r
-.set SCSI_Out__ACK__DR, CYREG_PRT0_DR\r
-.set SCSI_Out__ACK__INP_DIS, CYREG_PRT0_INP_DIS\r
-.set SCSI_Out__ACK__INTTYPE, CYREG_PICU0_INTTYPE6\r
-.set SCSI_Out__ACK__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG\r
-.set SCSI_Out__ACK__LCD_EN, CYREG_PRT0_LCD_EN\r
-.set SCSI_Out__ACK__MASK, 0x40\r
-.set SCSI_Out__ACK__PC, CYREG_PRT0_PC6\r
-.set SCSI_Out__ACK__PORT, 0\r
-.set SCSI_Out__ACK__PRT, CYREG_PRT0_PRT\r
-.set SCSI_Out__ACK__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL\r
-.set SCSI_Out__ACK__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN\r
-.set SCSI_Out__ACK__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0\r
-.set SCSI_Out__ACK__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1\r
-.set SCSI_Out__ACK__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0\r
-.set SCSI_Out__ACK__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1\r
-.set SCSI_Out__ACK__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT\r
-.set SCSI_Out__ACK__PS, CYREG_PRT0_PS\r
-.set SCSI_Out__ACK__SHIFT, 6\r
-.set SCSI_Out__ACK__SLW, CYREG_PRT0_SLW\r
-.set SCSI_Out__ATN__AG, CYREG_PRT4_AG\r
-.set SCSI_Out__ATN__AMUX, CYREG_PRT4_AMUX\r
-.set SCSI_Out__ATN__BIE, CYREG_PRT4_BIE\r
-.set SCSI_Out__ATN__BIT_MASK, CYREG_PRT4_BIT_MASK\r
-.set SCSI_Out__ATN__BYP, CYREG_PRT4_BYP\r
-.set SCSI_Out__ATN__CTL, CYREG_PRT4_CTL\r
-.set SCSI_Out__ATN__DM0, CYREG_PRT4_DM0\r
-.set SCSI_Out__ATN__DM1, CYREG_PRT4_DM1\r
-.set SCSI_Out__ATN__DM2, CYREG_PRT4_DM2\r
-.set SCSI_Out__ATN__DR, CYREG_PRT4_DR\r
-.set SCSI_Out__ATN__INP_DIS, CYREG_PRT4_INP_DIS\r
-.set SCSI_Out__ATN__INTTYPE, CYREG_PICU4_INTTYPE2\r
-.set SCSI_Out__ATN__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG\r
-.set SCSI_Out__ATN__LCD_EN, CYREG_PRT4_LCD_EN\r
-.set SCSI_Out__ATN__MASK, 0x04\r
-.set SCSI_Out__ATN__PC, CYREG_PRT4_PC2\r
-.set SCSI_Out__ATN__PORT, 4\r
-.set SCSI_Out__ATN__PRT, CYREG_PRT4_PRT\r
-.set SCSI_Out__ATN__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL\r
-.set SCSI_Out__ATN__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN\r
-.set SCSI_Out__ATN__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0\r
-.set SCSI_Out__ATN__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1\r
-.set SCSI_Out__ATN__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0\r
-.set SCSI_Out__ATN__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1\r
-.set SCSI_Out__ATN__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT\r
-.set SCSI_Out__ATN__PS, CYREG_PRT4_PS\r
-.set SCSI_Out__ATN__SHIFT, 2\r
-.set SCSI_Out__ATN__SLW, CYREG_PRT4_SLW\r
-.set SCSI_Out__BSY__AG, CYREG_PRT0_AG\r
-.set SCSI_Out__BSY__AMUX, CYREG_PRT0_AMUX\r
-.set SCSI_Out__BSY__BIE, CYREG_PRT0_BIE\r
-.set SCSI_Out__BSY__BIT_MASK, CYREG_PRT0_BIT_MASK\r
-.set SCSI_Out__BSY__BYP, CYREG_PRT0_BYP\r
-.set SCSI_Out__BSY__CTL, CYREG_PRT0_CTL\r
-.set SCSI_Out__BSY__DM0, CYREG_PRT0_DM0\r
-.set SCSI_Out__BSY__DM1, CYREG_PRT0_DM1\r
-.set SCSI_Out__BSY__DM2, CYREG_PRT0_DM2\r
-.set SCSI_Out__BSY__DR, CYREG_PRT0_DR\r
-.set SCSI_Out__BSY__INP_DIS, CYREG_PRT0_INP_DIS\r
-.set SCSI_Out__BSY__INTTYPE, CYREG_PICU0_INTTYPE7\r
-.set SCSI_Out__BSY__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG\r
-.set SCSI_Out__BSY__LCD_EN, CYREG_PRT0_LCD_EN\r
-.set SCSI_Out__BSY__MASK, 0x80\r
-.set SCSI_Out__BSY__PC, CYREG_PRT0_PC7\r
-.set SCSI_Out__BSY__PORT, 0\r
-.set SCSI_Out__BSY__PRT, CYREG_PRT0_PRT\r
-.set SCSI_Out__BSY__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL\r
-.set SCSI_Out__BSY__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN\r
-.set SCSI_Out__BSY__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0\r
-.set SCSI_Out__BSY__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1\r
-.set SCSI_Out__BSY__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0\r
-.set SCSI_Out__BSY__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1\r
-.set SCSI_Out__BSY__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT\r
-.set SCSI_Out__BSY__PS, CYREG_PRT0_PS\r
-.set SCSI_Out__BSY__SHIFT, 7\r
-.set SCSI_Out__BSY__SLW, CYREG_PRT0_SLW\r
-.set SCSI_Out__CD_raw__AG, CYREG_PRT0_AG\r
-.set SCSI_Out__CD_raw__AMUX, CYREG_PRT0_AMUX\r
-.set SCSI_Out__CD_raw__BIE, CYREG_PRT0_BIE\r
-.set SCSI_Out__CD_raw__BIT_MASK, CYREG_PRT0_BIT_MASK\r
-.set SCSI_Out__CD_raw__BYP, CYREG_PRT0_BYP\r
-.set SCSI_Out__CD_raw__CTL, CYREG_PRT0_CTL\r
-.set SCSI_Out__CD_raw__DM0, CYREG_PRT0_DM0\r
-.set SCSI_Out__CD_raw__DM1, CYREG_PRT0_DM1\r
-.set SCSI_Out__CD_raw__DM2, CYREG_PRT0_DM2\r
-.set SCSI_Out__CD_raw__DR, CYREG_PRT0_DR\r
-.set SCSI_Out__CD_raw__INP_DIS, CYREG_PRT0_INP_DIS\r
-.set SCSI_Out__CD_raw__INTTYPE, CYREG_PICU0_INTTYPE2\r
-.set SCSI_Out__CD_raw__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG\r
-.set SCSI_Out__CD_raw__LCD_EN, CYREG_PRT0_LCD_EN\r
-.set SCSI_Out__CD_raw__MASK, 0x04\r
-.set SCSI_Out__CD_raw__PC, CYREG_PRT0_PC2\r
-.set SCSI_Out__CD_raw__PORT, 0\r
-.set SCSI_Out__CD_raw__PRT, CYREG_PRT0_PRT\r
-.set SCSI_Out__CD_raw__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL\r
-.set SCSI_Out__CD_raw__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN\r
-.set SCSI_Out__CD_raw__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0\r
-.set SCSI_Out__CD_raw__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1\r
-.set SCSI_Out__CD_raw__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0\r
-.set SCSI_Out__CD_raw__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1\r
-.set SCSI_Out__CD_raw__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT\r
-.set SCSI_Out__CD_raw__PS, CYREG_PRT0_PS\r
-.set SCSI_Out__CD_raw__SHIFT, 2\r
-.set SCSI_Out__CD_raw__SLW, CYREG_PRT0_SLW\r
-.set SCSI_Out__DBP_raw__AG, CYREG_PRT4_AG\r
-.set SCSI_Out__DBP_raw__AMUX, CYREG_PRT4_AMUX\r
-.set SCSI_Out__DBP_raw__BIE, CYREG_PRT4_BIE\r
-.set SCSI_Out__DBP_raw__BIT_MASK, CYREG_PRT4_BIT_MASK\r
-.set SCSI_Out__DBP_raw__BYP, CYREG_PRT4_BYP\r
-.set SCSI_Out__DBP_raw__CTL, CYREG_PRT4_CTL\r
-.set SCSI_Out__DBP_raw__DM0, CYREG_PRT4_DM0\r
-.set SCSI_Out__DBP_raw__DM1, CYREG_PRT4_DM1\r
-.set SCSI_Out__DBP_raw__DM2, CYREG_PRT4_DM2\r
-.set SCSI_Out__DBP_raw__DR, CYREG_PRT4_DR\r
-.set SCSI_Out__DBP_raw__INP_DIS, CYREG_PRT4_INP_DIS\r
-.set SCSI_Out__DBP_raw__INTTYPE, CYREG_PICU4_INTTYPE3\r
-.set SCSI_Out__DBP_raw__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG\r
-.set SCSI_Out__DBP_raw__LCD_EN, CYREG_PRT4_LCD_EN\r
-.set SCSI_Out__DBP_raw__MASK, 0x08\r
-.set SCSI_Out__DBP_raw__PC, CYREG_PRT4_PC3\r
-.set SCSI_Out__DBP_raw__PORT, 4\r
-.set SCSI_Out__DBP_raw__PRT, CYREG_PRT4_PRT\r
-.set SCSI_Out__DBP_raw__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL\r
-.set SCSI_Out__DBP_raw__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN\r
-.set SCSI_Out__DBP_raw__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0\r
-.set SCSI_Out__DBP_raw__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1\r
-.set SCSI_Out__DBP_raw__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0\r
-.set SCSI_Out__DBP_raw__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1\r
-.set SCSI_Out__DBP_raw__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT\r
-.set SCSI_Out__DBP_raw__PS, CYREG_PRT4_PS\r
-.set SCSI_Out__DBP_raw__SHIFT, 3\r
-.set SCSI_Out__DBP_raw__SLW, CYREG_PRT4_SLW\r
-.set SCSI_Out__IO_raw__AG, CYREG_PRT0_AG\r
-.set SCSI_Out__IO_raw__AMUX, CYREG_PRT0_AMUX\r
-.set SCSI_Out__IO_raw__BIE, CYREG_PRT0_BIE\r
-.set SCSI_Out__IO_raw__BIT_MASK, CYREG_PRT0_BIT_MASK\r
-.set SCSI_Out__IO_raw__BYP, CYREG_PRT0_BYP\r
-.set SCSI_Out__IO_raw__CTL, CYREG_PRT0_CTL\r
-.set SCSI_Out__IO_raw__DM0, CYREG_PRT0_DM0\r
-.set SCSI_Out__IO_raw__DM1, CYREG_PRT0_DM1\r
-.set SCSI_Out__IO_raw__DM2, CYREG_PRT0_DM2\r
-.set SCSI_Out__IO_raw__DR, CYREG_PRT0_DR\r
-.set SCSI_Out__IO_raw__INP_DIS, CYREG_PRT0_INP_DIS\r
-.set SCSI_Out__IO_raw__INTTYPE, CYREG_PICU0_INTTYPE0\r
-.set SCSI_Out__IO_raw__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG\r
-.set SCSI_Out__IO_raw__LCD_EN, CYREG_PRT0_LCD_EN\r
-.set SCSI_Out__IO_raw__MASK, 0x01\r
-.set SCSI_Out__IO_raw__PC, CYREG_PRT0_PC0\r
-.set SCSI_Out__IO_raw__PORT, 0\r
-.set SCSI_Out__IO_raw__PRT, CYREG_PRT0_PRT\r
-.set SCSI_Out__IO_raw__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL\r
-.set SCSI_Out__IO_raw__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN\r
-.set SCSI_Out__IO_raw__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0\r
-.set SCSI_Out__IO_raw__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1\r
-.set SCSI_Out__IO_raw__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0\r
-.set SCSI_Out__IO_raw__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1\r
-.set SCSI_Out__IO_raw__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT\r
-.set SCSI_Out__IO_raw__PS, CYREG_PRT0_PS\r
-.set SCSI_Out__IO_raw__SHIFT, 0\r
-.set SCSI_Out__IO_raw__SLW, CYREG_PRT0_SLW\r
-.set SCSI_Out__MSG_raw__AG, CYREG_PRT0_AG\r
-.set SCSI_Out__MSG_raw__AMUX, CYREG_PRT0_AMUX\r
-.set SCSI_Out__MSG_raw__BIE, CYREG_PRT0_BIE\r
-.set SCSI_Out__MSG_raw__BIT_MASK, CYREG_PRT0_BIT_MASK\r
-.set SCSI_Out__MSG_raw__BYP, CYREG_PRT0_BYP\r
-.set SCSI_Out__MSG_raw__CTL, CYREG_PRT0_CTL\r
-.set SCSI_Out__MSG_raw__DM0, CYREG_PRT0_DM0\r
-.set SCSI_Out__MSG_raw__DM1, CYREG_PRT0_DM1\r
-.set SCSI_Out__MSG_raw__DM2, CYREG_PRT0_DM2\r
-.set SCSI_Out__MSG_raw__DR, CYREG_PRT0_DR\r
-.set SCSI_Out__MSG_raw__INP_DIS, CYREG_PRT0_INP_DIS\r
-.set SCSI_Out__MSG_raw__INTTYPE, CYREG_PICU0_INTTYPE4\r
-.set SCSI_Out__MSG_raw__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG\r
-.set SCSI_Out__MSG_raw__LCD_EN, CYREG_PRT0_LCD_EN\r
-.set SCSI_Out__MSG_raw__MASK, 0x10\r
-.set SCSI_Out__MSG_raw__PC, CYREG_PRT0_PC4\r
-.set SCSI_Out__MSG_raw__PORT, 0\r
-.set SCSI_Out__MSG_raw__PRT, CYREG_PRT0_PRT\r
-.set SCSI_Out__MSG_raw__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL\r
-.set SCSI_Out__MSG_raw__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN\r
-.set SCSI_Out__MSG_raw__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0\r
-.set SCSI_Out__MSG_raw__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1\r
-.set SCSI_Out__MSG_raw__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0\r
-.set SCSI_Out__MSG_raw__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1\r
-.set SCSI_Out__MSG_raw__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT\r
-.set SCSI_Out__MSG_raw__PS, CYREG_PRT0_PS\r
-.set SCSI_Out__MSG_raw__SHIFT, 4\r
-.set SCSI_Out__MSG_raw__SLW, CYREG_PRT0_SLW\r
-.set SCSI_Out__REQ__AG, CYREG_PRT0_AG\r
-.set SCSI_Out__REQ__AMUX, CYREG_PRT0_AMUX\r
-.set SCSI_Out__REQ__BIE, CYREG_PRT0_BIE\r
-.set SCSI_Out__REQ__BIT_MASK, CYREG_PRT0_BIT_MASK\r
-.set SCSI_Out__REQ__BYP, CYREG_PRT0_BYP\r
-.set SCSI_Out__REQ__CTL, CYREG_PRT0_CTL\r
-.set SCSI_Out__REQ__DM0, CYREG_PRT0_DM0\r
-.set SCSI_Out__REQ__DM1, CYREG_PRT0_DM1\r
-.set SCSI_Out__REQ__DM2, CYREG_PRT0_DM2\r
-.set SCSI_Out__REQ__DR, CYREG_PRT0_DR\r
-.set SCSI_Out__REQ__INP_DIS, CYREG_PRT0_INP_DIS\r
-.set SCSI_Out__REQ__INTTYPE, CYREG_PICU0_INTTYPE1\r
-.set SCSI_Out__REQ__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG\r
-.set SCSI_Out__REQ__LCD_EN, CYREG_PRT0_LCD_EN\r
-.set SCSI_Out__REQ__MASK, 0x02\r
-.set SCSI_Out__REQ__PC, CYREG_PRT0_PC1\r
-.set SCSI_Out__REQ__PORT, 0\r
-.set SCSI_Out__REQ__PRT, CYREG_PRT0_PRT\r
-.set SCSI_Out__REQ__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL\r
-.set SCSI_Out__REQ__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN\r
-.set SCSI_Out__REQ__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0\r
-.set SCSI_Out__REQ__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1\r
-.set SCSI_Out__REQ__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0\r
-.set SCSI_Out__REQ__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1\r
-.set SCSI_Out__REQ__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT\r
-.set SCSI_Out__REQ__PS, CYREG_PRT0_PS\r
-.set SCSI_Out__REQ__SHIFT, 1\r
-.set SCSI_Out__REQ__SLW, CYREG_PRT0_SLW\r
-.set SCSI_Out__RST__AG, CYREG_PRT0_AG\r
-.set SCSI_Out__RST__AMUX, CYREG_PRT0_AMUX\r
-.set SCSI_Out__RST__BIE, CYREG_PRT0_BIE\r
-.set SCSI_Out__RST__BIT_MASK, CYREG_PRT0_BIT_MASK\r
-.set SCSI_Out__RST__BYP, CYREG_PRT0_BYP\r
-.set SCSI_Out__RST__CTL, CYREG_PRT0_CTL\r
-.set SCSI_Out__RST__DM0, CYREG_PRT0_DM0\r
-.set SCSI_Out__RST__DM1, CYREG_PRT0_DM1\r
-.set SCSI_Out__RST__DM2, CYREG_PRT0_DM2\r
-.set SCSI_Out__RST__DR, CYREG_PRT0_DR\r
-.set SCSI_Out__RST__INP_DIS, CYREG_PRT0_INP_DIS\r
-.set SCSI_Out__RST__INTTYPE, CYREG_PICU0_INTTYPE5\r
-.set SCSI_Out__RST__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG\r
-.set SCSI_Out__RST__LCD_EN, CYREG_PRT0_LCD_EN\r
-.set SCSI_Out__RST__MASK, 0x20\r
-.set SCSI_Out__RST__PC, CYREG_PRT0_PC5\r
-.set SCSI_Out__RST__PORT, 0\r
-.set SCSI_Out__RST__PRT, CYREG_PRT0_PRT\r
-.set SCSI_Out__RST__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL\r
-.set SCSI_Out__RST__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN\r
-.set SCSI_Out__RST__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0\r
-.set SCSI_Out__RST__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1\r
-.set SCSI_Out__RST__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0\r
-.set SCSI_Out__RST__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1\r
-.set SCSI_Out__RST__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT\r
-.set SCSI_Out__RST__PS, CYREG_PRT0_PS\r
-.set SCSI_Out__RST__SHIFT, 5\r
-.set SCSI_Out__RST__SLW, CYREG_PRT0_SLW\r
-.set SCSI_Out__SEL__AG, CYREG_PRT0_AG\r
-.set SCSI_Out__SEL__AMUX, CYREG_PRT0_AMUX\r
-.set SCSI_Out__SEL__BIE, CYREG_PRT0_BIE\r
-.set SCSI_Out__SEL__BIT_MASK, CYREG_PRT0_BIT_MASK\r
-.set SCSI_Out__SEL__BYP, CYREG_PRT0_BYP\r
-.set SCSI_Out__SEL__CTL, CYREG_PRT0_CTL\r
-.set SCSI_Out__SEL__DM0, CYREG_PRT0_DM0\r
-.set SCSI_Out__SEL__DM1, CYREG_PRT0_DM1\r
-.set SCSI_Out__SEL__DM2, CYREG_PRT0_DM2\r
-.set SCSI_Out__SEL__DR, CYREG_PRT0_DR\r
-.set SCSI_Out__SEL__INP_DIS, CYREG_PRT0_INP_DIS\r
-.set SCSI_Out__SEL__INTTYPE, CYREG_PICU0_INTTYPE3\r
-.set SCSI_Out__SEL__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG\r
-.set SCSI_Out__SEL__LCD_EN, CYREG_PRT0_LCD_EN\r
-.set SCSI_Out__SEL__MASK, 0x08\r
-.set SCSI_Out__SEL__PC, CYREG_PRT0_PC3\r
-.set SCSI_Out__SEL__PORT, 0\r
-.set SCSI_Out__SEL__PRT, CYREG_PRT0_PRT\r
-.set SCSI_Out__SEL__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL\r
-.set SCSI_Out__SEL__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN\r
-.set SCSI_Out__SEL__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0\r
-.set SCSI_Out__SEL__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1\r
-.set SCSI_Out__SEL__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0\r
-.set SCSI_Out__SEL__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1\r
-.set SCSI_Out__SEL__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT\r
-.set SCSI_Out__SEL__PS, CYREG_PRT0_PS\r
-.set SCSI_Out__SEL__SHIFT, 3\r
-.set SCSI_Out__SEL__SLW, CYREG_PRT0_SLW\r
-\r
-/* SCSI_Out_Bits */\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__0__MASK, 0x01\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__0__POS, 0\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__1__MASK, 0x02\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__1__POS, 1\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB08_09_ACTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB08_09_CTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB08_09_CTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB08_09_CTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB08_09_CTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B1_UDB08_09_MSK\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB08_09_MSK\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB08_09_MSK\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB08_09_MSK\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__2__MASK, 0x04\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__2__POS, 2\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__3__MASK, 0x08\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__3__POS, 3\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__4__MASK, 0x10\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__4__POS, 4\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__5__MASK, 0x20\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__5__POS, 5\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__6__MASK, 0x40\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__6__POS, 6\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__7__MASK, 0x80\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__7__POS, 7\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B1_UDB08_ACTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG, CYREG_B1_UDB08_CTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B1_UDB08_ST_CTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG, CYREG_B1_UDB08_CTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B1_UDB08_ST_CTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__MASK, 0xFF\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB08_MSK_ACTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB08_MSK_ACTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG, CYREG_B1_UDB08_MSK\r
-\r
-/* SCSI_Out_Ctl */\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK, 0x01\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__0__POS, 0\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB08_09_ACTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB08_09_CTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB08_09_CTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB08_09_CTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB08_09_CTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB08_09_MSK\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB08_09_MSK\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB08_09_MSK\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB08_09_MSK\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB08_ACTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB08_CTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB08_ST_CTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB08_CTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB08_ST_CTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK, 0x01\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB08_MSK_ACTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB08_MSK_ACTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB08_MSK\r
-\r
-/* SCSI_Out_DBx */\r
-.set SCSI_Out_DBx__0__AG, CYREG_PRT6_AG\r
-.set SCSI_Out_DBx__0__AMUX, CYREG_PRT6_AMUX\r
-.set SCSI_Out_DBx__0__BIE, CYREG_PRT6_BIE\r
-.set SCSI_Out_DBx__0__BIT_MASK, CYREG_PRT6_BIT_MASK\r
-.set SCSI_Out_DBx__0__BYP, CYREG_PRT6_BYP\r
-.set SCSI_Out_DBx__0__CTL, CYREG_PRT6_CTL\r
-.set SCSI_Out_DBx__0__DM0, CYREG_PRT6_DM0\r
-.set SCSI_Out_DBx__0__DM1, CYREG_PRT6_DM1\r
-.set SCSI_Out_DBx__0__DM2, CYREG_PRT6_DM2\r
-.set SCSI_Out_DBx__0__DR, CYREG_PRT6_DR\r
-.set SCSI_Out_DBx__0__INP_DIS, CYREG_PRT6_INP_DIS\r
-.set SCSI_Out_DBx__0__INTTYPE, CYREG_PICU6_INTTYPE3\r
-.set SCSI_Out_DBx__0__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG\r
-.set SCSI_Out_DBx__0__LCD_EN, CYREG_PRT6_LCD_EN\r
-.set SCSI_Out_DBx__0__MASK, 0x08\r
-.set SCSI_Out_DBx__0__PC, CYREG_PRT6_PC3\r
-.set SCSI_Out_DBx__0__PORT, 6\r
-.set SCSI_Out_DBx__0__PRT, CYREG_PRT6_PRT\r
-.set SCSI_Out_DBx__0__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL\r
-.set SCSI_Out_DBx__0__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN\r
-.set SCSI_Out_DBx__0__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0\r
-.set SCSI_Out_DBx__0__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1\r
-.set SCSI_Out_DBx__0__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0\r
-.set SCSI_Out_DBx__0__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1\r
-.set SCSI_Out_DBx__0__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT\r
-.set SCSI_Out_DBx__0__PS, CYREG_PRT6_PS\r
-.set SCSI_Out_DBx__0__SHIFT, 3\r
-.set SCSI_Out_DBx__0__SLW, CYREG_PRT6_SLW\r
-.set SCSI_Out_DBx__1__AG, CYREG_PRT6_AG\r
-.set SCSI_Out_DBx__1__AMUX, CYREG_PRT6_AMUX\r
-.set SCSI_Out_DBx__1__BIE, CYREG_PRT6_BIE\r
-.set SCSI_Out_DBx__1__BIT_MASK, CYREG_PRT6_BIT_MASK\r
-.set SCSI_Out_DBx__1__BYP, CYREG_PRT6_BYP\r
-.set SCSI_Out_DBx__1__CTL, CYREG_PRT6_CTL\r
-.set SCSI_Out_DBx__1__DM0, CYREG_PRT6_DM0\r
-.set SCSI_Out_DBx__1__DM1, CYREG_PRT6_DM1\r
-.set SCSI_Out_DBx__1__DM2, CYREG_PRT6_DM2\r
-.set SCSI_Out_DBx__1__DR, CYREG_PRT6_DR\r
-.set SCSI_Out_DBx__1__INP_DIS, CYREG_PRT6_INP_DIS\r
-.set SCSI_Out_DBx__1__INTTYPE, CYREG_PICU6_INTTYPE2\r
-.set SCSI_Out_DBx__1__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG\r
-.set SCSI_Out_DBx__1__LCD_EN, CYREG_PRT6_LCD_EN\r
-.set SCSI_Out_DBx__1__MASK, 0x04\r
-.set SCSI_Out_DBx__1__PC, CYREG_PRT6_PC2\r
-.set SCSI_Out_DBx__1__PORT, 6\r
-.set SCSI_Out_DBx__1__PRT, CYREG_PRT6_PRT\r
-.set SCSI_Out_DBx__1__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL\r
-.set SCSI_Out_DBx__1__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN\r
-.set SCSI_Out_DBx__1__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0\r
-.set SCSI_Out_DBx__1__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1\r
-.set SCSI_Out_DBx__1__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0\r
-.set SCSI_Out_DBx__1__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1\r
-.set SCSI_Out_DBx__1__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT\r
-.set SCSI_Out_DBx__1__PS, CYREG_PRT6_PS\r
-.set SCSI_Out_DBx__1__SHIFT, 2\r
-.set SCSI_Out_DBx__1__SLW, CYREG_PRT6_SLW\r
-.set SCSI_Out_DBx__2__AG, CYREG_PRT6_AG\r
-.set SCSI_Out_DBx__2__AMUX, CYREG_PRT6_AMUX\r
-.set SCSI_Out_DBx__2__BIE, CYREG_PRT6_BIE\r
-.set SCSI_Out_DBx__2__BIT_MASK, CYREG_PRT6_BIT_MASK\r
-.set SCSI_Out_DBx__2__BYP, CYREG_PRT6_BYP\r
-.set SCSI_Out_DBx__2__CTL, CYREG_PRT6_CTL\r
-.set SCSI_Out_DBx__2__DM0, CYREG_PRT6_DM0\r
-.set SCSI_Out_DBx__2__DM1, CYREG_PRT6_DM1\r
-.set SCSI_Out_DBx__2__DM2, CYREG_PRT6_DM2\r
-.set SCSI_Out_DBx__2__DR, CYREG_PRT6_DR\r
-.set SCSI_Out_DBx__2__INP_DIS, CYREG_PRT6_INP_DIS\r
-.set SCSI_Out_DBx__2__INTTYPE, CYREG_PICU6_INTTYPE1\r
-.set SCSI_Out_DBx__2__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG\r
-.set SCSI_Out_DBx__2__LCD_EN, CYREG_PRT6_LCD_EN\r
-.set SCSI_Out_DBx__2__MASK, 0x02\r
-.set SCSI_Out_DBx__2__PC, CYREG_PRT6_PC1\r
-.set SCSI_Out_DBx__2__PORT, 6\r
-.set SCSI_Out_DBx__2__PRT, CYREG_PRT6_PRT\r
-.set SCSI_Out_DBx__2__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL\r
-.set SCSI_Out_DBx__2__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN\r
-.set SCSI_Out_DBx__2__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0\r
-.set SCSI_Out_DBx__2__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1\r
-.set SCSI_Out_DBx__2__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0\r
-.set SCSI_Out_DBx__2__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1\r
-.set SCSI_Out_DBx__2__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT\r
-.set SCSI_Out_DBx__2__PS, CYREG_PRT6_PS\r
-.set SCSI_Out_DBx__2__SHIFT, 1\r
-.set SCSI_Out_DBx__2__SLW, CYREG_PRT6_SLW\r
-.set SCSI_Out_DBx__3__AG, CYREG_PRT6_AG\r
-.set SCSI_Out_DBx__3__AMUX, CYREG_PRT6_AMUX\r
-.set SCSI_Out_DBx__3__BIE, CYREG_PRT6_BIE\r
-.set SCSI_Out_DBx__3__BIT_MASK, CYREG_PRT6_BIT_MASK\r
-.set SCSI_Out_DBx__3__BYP, CYREG_PRT6_BYP\r
-.set SCSI_Out_DBx__3__CTL, CYREG_PRT6_CTL\r
-.set SCSI_Out_DBx__3__DM0, CYREG_PRT6_DM0\r
-.set SCSI_Out_DBx__3__DM1, CYREG_PRT6_DM1\r
-.set SCSI_Out_DBx__3__DM2, CYREG_PRT6_DM2\r
-.set SCSI_Out_DBx__3__DR, CYREG_PRT6_DR\r
-.set SCSI_Out_DBx__3__INP_DIS, CYREG_PRT6_INP_DIS\r
-.set SCSI_Out_DBx__3__INTTYPE, CYREG_PICU6_INTTYPE0\r
-.set SCSI_Out_DBx__3__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG\r
-.set SCSI_Out_DBx__3__LCD_EN, CYREG_PRT6_LCD_EN\r
-.set SCSI_Out_DBx__3__MASK, 0x01\r
-.set SCSI_Out_DBx__3__PC, CYREG_PRT6_PC0\r
-.set SCSI_Out_DBx__3__PORT, 6\r
-.set SCSI_Out_DBx__3__PRT, CYREG_PRT6_PRT\r
-.set SCSI_Out_DBx__3__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL\r
-.set SCSI_Out_DBx__3__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN\r
-.set SCSI_Out_DBx__3__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0\r
-.set SCSI_Out_DBx__3__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1\r
-.set SCSI_Out_DBx__3__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0\r
-.set SCSI_Out_DBx__3__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1\r
-.set SCSI_Out_DBx__3__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT\r
-.set SCSI_Out_DBx__3__PS, CYREG_PRT6_PS\r
-.set SCSI_Out_DBx__3__SHIFT, 0\r
-.set SCSI_Out_DBx__3__SLW, CYREG_PRT6_SLW\r
-.set SCSI_Out_DBx__4__AG, CYREG_PRT4_AG\r
-.set SCSI_Out_DBx__4__AMUX, CYREG_PRT4_AMUX\r
-.set SCSI_Out_DBx__4__BIE, CYREG_PRT4_BIE\r
-.set SCSI_Out_DBx__4__BIT_MASK, CYREG_PRT4_BIT_MASK\r
-.set SCSI_Out_DBx__4__BYP, CYREG_PRT4_BYP\r
-.set SCSI_Out_DBx__4__CTL, CYREG_PRT4_CTL\r
-.set SCSI_Out_DBx__4__DM0, CYREG_PRT4_DM0\r
-.set SCSI_Out_DBx__4__DM1, CYREG_PRT4_DM1\r
-.set SCSI_Out_DBx__4__DM2, CYREG_PRT4_DM2\r
-.set SCSI_Out_DBx__4__DR, CYREG_PRT4_DR\r
-.set SCSI_Out_DBx__4__INP_DIS, CYREG_PRT4_INP_DIS\r
-.set SCSI_Out_DBx__4__INTTYPE, CYREG_PICU4_INTTYPE7\r
-.set SCSI_Out_DBx__4__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG\r
-.set SCSI_Out_DBx__4__LCD_EN, CYREG_PRT4_LCD_EN\r
-.set SCSI_Out_DBx__4__MASK, 0x80\r
-.set SCSI_Out_DBx__4__PC, CYREG_PRT4_PC7\r
-.set SCSI_Out_DBx__4__PORT, 4\r
-.set SCSI_Out_DBx__4__PRT, CYREG_PRT4_PRT\r
-.set SCSI_Out_DBx__4__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL\r
-.set SCSI_Out_DBx__4__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN\r
-.set SCSI_Out_DBx__4__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0\r
-.set SCSI_Out_DBx__4__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1\r
-.set SCSI_Out_DBx__4__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0\r
-.set SCSI_Out_DBx__4__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1\r
-.set SCSI_Out_DBx__4__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT\r
-.set SCSI_Out_DBx__4__PS, CYREG_PRT4_PS\r
-.set SCSI_Out_DBx__4__SHIFT, 7\r
-.set SCSI_Out_DBx__4__SLW, CYREG_PRT4_SLW\r
-.set SCSI_Out_DBx__5__AG, CYREG_PRT4_AG\r
-.set SCSI_Out_DBx__5__AMUX, CYREG_PRT4_AMUX\r
-.set SCSI_Out_DBx__5__BIE, CYREG_PRT4_BIE\r
-.set SCSI_Out_DBx__5__BIT_MASK, CYREG_PRT4_BIT_MASK\r
-.set SCSI_Out_DBx__5__BYP, CYREG_PRT4_BYP\r
-.set SCSI_Out_DBx__5__CTL, CYREG_PRT4_CTL\r
-.set SCSI_Out_DBx__5__DM0, CYREG_PRT4_DM0\r
-.set SCSI_Out_DBx__5__DM1, CYREG_PRT4_DM1\r
-.set SCSI_Out_DBx__5__DM2, CYREG_PRT4_DM2\r
-.set SCSI_Out_DBx__5__DR, CYREG_PRT4_DR\r
-.set SCSI_Out_DBx__5__INP_DIS, CYREG_PRT4_INP_DIS\r
-.set SCSI_Out_DBx__5__INTTYPE, CYREG_PICU4_INTTYPE6\r
-.set SCSI_Out_DBx__5__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG\r
-.set SCSI_Out_DBx__5__LCD_EN, CYREG_PRT4_LCD_EN\r
-.set SCSI_Out_DBx__5__MASK, 0x40\r
-.set SCSI_Out_DBx__5__PC, CYREG_PRT4_PC6\r
-.set SCSI_Out_DBx__5__PORT, 4\r
-.set SCSI_Out_DBx__5__PRT, CYREG_PRT4_PRT\r
-.set SCSI_Out_DBx__5__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL\r
-.set SCSI_Out_DBx__5__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN\r
-.set SCSI_Out_DBx__5__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0\r
-.set SCSI_Out_DBx__5__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1\r
-.set SCSI_Out_DBx__5__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0\r
-.set SCSI_Out_DBx__5__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1\r
-.set SCSI_Out_DBx__5__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT\r
-.set SCSI_Out_DBx__5__PS, CYREG_PRT4_PS\r
-.set SCSI_Out_DBx__5__SHIFT, 6\r
-.set SCSI_Out_DBx__5__SLW, CYREG_PRT4_SLW\r
-.set SCSI_Out_DBx__6__AG, CYREG_PRT4_AG\r
-.set SCSI_Out_DBx__6__AMUX, CYREG_PRT4_AMUX\r
-.set SCSI_Out_DBx__6__BIE, CYREG_PRT4_BIE\r
-.set SCSI_Out_DBx__6__BIT_MASK, CYREG_PRT4_BIT_MASK\r
-.set SCSI_Out_DBx__6__BYP, CYREG_PRT4_BYP\r
-.set SCSI_Out_DBx__6__CTL, CYREG_PRT4_CTL\r
-.set SCSI_Out_DBx__6__DM0, CYREG_PRT4_DM0\r
-.set SCSI_Out_DBx__6__DM1, CYREG_PRT4_DM1\r
-.set SCSI_Out_DBx__6__DM2, CYREG_PRT4_DM2\r
-.set SCSI_Out_DBx__6__DR, CYREG_PRT4_DR\r
-.set SCSI_Out_DBx__6__INP_DIS, CYREG_PRT4_INP_DIS\r
-.set SCSI_Out_DBx__6__INTTYPE, CYREG_PICU4_INTTYPE5\r
-.set SCSI_Out_DBx__6__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG\r
-.set SCSI_Out_DBx__6__LCD_EN, CYREG_PRT4_LCD_EN\r
-.set SCSI_Out_DBx__6__MASK, 0x20\r
-.set SCSI_Out_DBx__6__PC, CYREG_PRT4_PC5\r
-.set SCSI_Out_DBx__6__PORT, 4\r
-.set SCSI_Out_DBx__6__PRT, CYREG_PRT4_PRT\r
-.set SCSI_Out_DBx__6__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL\r
-.set SCSI_Out_DBx__6__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN\r
-.set SCSI_Out_DBx__6__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0\r
-.set SCSI_Out_DBx__6__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1\r
-.set SCSI_Out_DBx__6__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0\r
-.set SCSI_Out_DBx__6__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1\r
-.set SCSI_Out_DBx__6__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT\r
-.set SCSI_Out_DBx__6__PS, CYREG_PRT4_PS\r
-.set SCSI_Out_DBx__6__SHIFT, 5\r
-.set SCSI_Out_DBx__6__SLW, CYREG_PRT4_SLW\r
-.set SCSI_Out_DBx__7__AG, CYREG_PRT4_AG\r
-.set SCSI_Out_DBx__7__AMUX, CYREG_PRT4_AMUX\r
-.set SCSI_Out_DBx__7__BIE, CYREG_PRT4_BIE\r
-.set SCSI_Out_DBx__7__BIT_MASK, CYREG_PRT4_BIT_MASK\r
-.set SCSI_Out_DBx__7__BYP, CYREG_PRT4_BYP\r
-.set SCSI_Out_DBx__7__CTL, CYREG_PRT4_CTL\r
-.set SCSI_Out_DBx__7__DM0, CYREG_PRT4_DM0\r
-.set SCSI_Out_DBx__7__DM1, CYREG_PRT4_DM1\r
-.set SCSI_Out_DBx__7__DM2, CYREG_PRT4_DM2\r
-.set SCSI_Out_DBx__7__DR, CYREG_PRT4_DR\r
-.set SCSI_Out_DBx__7__INP_DIS, CYREG_PRT4_INP_DIS\r
-.set SCSI_Out_DBx__7__INTTYPE, CYREG_PICU4_INTTYPE4\r
-.set SCSI_Out_DBx__7__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG\r
-.set SCSI_Out_DBx__7__LCD_EN, CYREG_PRT4_LCD_EN\r
-.set SCSI_Out_DBx__7__MASK, 0x10\r
-.set SCSI_Out_DBx__7__PC, CYREG_PRT4_PC4\r
-.set SCSI_Out_DBx__7__PORT, 4\r
-.set SCSI_Out_DBx__7__PRT, CYREG_PRT4_PRT\r
-.set SCSI_Out_DBx__7__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL\r
-.set SCSI_Out_DBx__7__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN\r
-.set SCSI_Out_DBx__7__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0\r
-.set SCSI_Out_DBx__7__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1\r
-.set SCSI_Out_DBx__7__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0\r
-.set SCSI_Out_DBx__7__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1\r
-.set SCSI_Out_DBx__7__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT\r
-.set SCSI_Out_DBx__7__PS, CYREG_PRT4_PS\r
-.set SCSI_Out_DBx__7__SHIFT, 4\r
-.set SCSI_Out_DBx__7__SLW, CYREG_PRT4_SLW\r
-.set SCSI_Out_DBx__DB0__AG, CYREG_PRT6_AG\r
-.set SCSI_Out_DBx__DB0__AMUX, CYREG_PRT6_AMUX\r
-.set SCSI_Out_DBx__DB0__BIE, CYREG_PRT6_BIE\r
-.set SCSI_Out_DBx__DB0__BIT_MASK, CYREG_PRT6_BIT_MASK\r
-.set SCSI_Out_DBx__DB0__BYP, CYREG_PRT6_BYP\r
-.set SCSI_Out_DBx__DB0__CTL, CYREG_PRT6_CTL\r
-.set SCSI_Out_DBx__DB0__DM0, CYREG_PRT6_DM0\r
-.set SCSI_Out_DBx__DB0__DM1, CYREG_PRT6_DM1\r
-.set SCSI_Out_DBx__DB0__DM2, CYREG_PRT6_DM2\r
-.set SCSI_Out_DBx__DB0__DR, CYREG_PRT6_DR\r
-.set SCSI_Out_DBx__DB0__INP_DIS, CYREG_PRT6_INP_DIS\r
-.set SCSI_Out_DBx__DB0__INTTYPE, CYREG_PICU6_INTTYPE3\r
-.set SCSI_Out_DBx__DB0__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG\r
-.set SCSI_Out_DBx__DB0__LCD_EN, CYREG_PRT6_LCD_EN\r
-.set SCSI_Out_DBx__DB0__MASK, 0x08\r
-.set SCSI_Out_DBx__DB0__PC, CYREG_PRT6_PC3\r
-.set SCSI_Out_DBx__DB0__PORT, 6\r
-.set SCSI_Out_DBx__DB0__PRT, CYREG_PRT6_PRT\r
-.set SCSI_Out_DBx__DB0__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL\r
-.set SCSI_Out_DBx__DB0__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN\r
-.set SCSI_Out_DBx__DB0__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0\r
-.set SCSI_Out_DBx__DB0__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1\r
-.set SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0\r
-.set SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1\r
-.set SCSI_Out_DBx__DB0__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT\r
-.set SCSI_Out_DBx__DB0__PS, CYREG_PRT6_PS\r
-.set SCSI_Out_DBx__DB0__SHIFT, 3\r
-.set SCSI_Out_DBx__DB0__SLW, CYREG_PRT6_SLW\r
-.set SCSI_Out_DBx__DB1__AG, CYREG_PRT6_AG\r
-.set SCSI_Out_DBx__DB1__AMUX, CYREG_PRT6_AMUX\r
-.set SCSI_Out_DBx__DB1__BIE, CYREG_PRT6_BIE\r
-.set SCSI_Out_DBx__DB1__BIT_MASK, CYREG_PRT6_BIT_MASK\r
-.set SCSI_Out_DBx__DB1__BYP, CYREG_PRT6_BYP\r
-.set SCSI_Out_DBx__DB1__CTL, CYREG_PRT6_CTL\r
-.set SCSI_Out_DBx__DB1__DM0, CYREG_PRT6_DM0\r
-.set SCSI_Out_DBx__DB1__DM1, CYREG_PRT6_DM1\r
-.set SCSI_Out_DBx__DB1__DM2, CYREG_PRT6_DM2\r
-.set SCSI_Out_DBx__DB1__DR, CYREG_PRT6_DR\r
-.set SCSI_Out_DBx__DB1__INP_DIS, CYREG_PRT6_INP_DIS\r
-.set SCSI_Out_DBx__DB1__INTTYPE, CYREG_PICU6_INTTYPE2\r
-.set SCSI_Out_DBx__DB1__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG\r
-.set SCSI_Out_DBx__DB1__LCD_EN, CYREG_PRT6_LCD_EN\r
-.set SCSI_Out_DBx__DB1__MASK, 0x04\r
-.set SCSI_Out_DBx__DB1__PC, CYREG_PRT6_PC2\r
-.set SCSI_Out_DBx__DB1__PORT, 6\r
-.set SCSI_Out_DBx__DB1__PRT, CYREG_PRT6_PRT\r
-.set SCSI_Out_DBx__DB1__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL\r
-.set SCSI_Out_DBx__DB1__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN\r
-.set SCSI_Out_DBx__DB1__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0\r
-.set SCSI_Out_DBx__DB1__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1\r
-.set SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0\r
-.set SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1\r
-.set SCSI_Out_DBx__DB1__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT\r
-.set SCSI_Out_DBx__DB1__PS, CYREG_PRT6_PS\r
-.set SCSI_Out_DBx__DB1__SHIFT, 2\r
-.set SCSI_Out_DBx__DB1__SLW, CYREG_PRT6_SLW\r
-.set SCSI_Out_DBx__DB2__AG, CYREG_PRT6_AG\r
-.set SCSI_Out_DBx__DB2__AMUX, CYREG_PRT6_AMUX\r
-.set SCSI_Out_DBx__DB2__BIE, CYREG_PRT6_BIE\r
-.set SCSI_Out_DBx__DB2__BIT_MASK, CYREG_PRT6_BIT_MASK\r
-.set SCSI_Out_DBx__DB2__BYP, CYREG_PRT6_BYP\r
-.set SCSI_Out_DBx__DB2__CTL, CYREG_PRT6_CTL\r
-.set SCSI_Out_DBx__DB2__DM0, CYREG_PRT6_DM0\r
-.set SCSI_Out_DBx__DB2__DM1, CYREG_PRT6_DM1\r
-.set SCSI_Out_DBx__DB2__DM2, CYREG_PRT6_DM2\r
-.set SCSI_Out_DBx__DB2__DR, CYREG_PRT6_DR\r
-.set SCSI_Out_DBx__DB2__INP_DIS, CYREG_PRT6_INP_DIS\r
-.set SCSI_Out_DBx__DB2__INTTYPE, CYREG_PICU6_INTTYPE1\r
-.set SCSI_Out_DBx__DB2__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG\r
-.set SCSI_Out_DBx__DB2__LCD_EN, CYREG_PRT6_LCD_EN\r
-.set SCSI_Out_DBx__DB2__MASK, 0x02\r
-.set SCSI_Out_DBx__DB2__PC, CYREG_PRT6_PC1\r
-.set SCSI_Out_DBx__DB2__PORT, 6\r
-.set SCSI_Out_DBx__DB2__PRT, CYREG_PRT6_PRT\r
-.set SCSI_Out_DBx__DB2__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL\r
-.set SCSI_Out_DBx__DB2__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN\r
-.set SCSI_Out_DBx__DB2__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0\r
-.set SCSI_Out_DBx__DB2__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1\r
-.set SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0\r
-.set SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1\r
-.set SCSI_Out_DBx__DB2__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT\r
-.set SCSI_Out_DBx__DB2__PS, CYREG_PRT6_PS\r
-.set SCSI_Out_DBx__DB2__SHIFT, 1\r
-.set SCSI_Out_DBx__DB2__SLW, CYREG_PRT6_SLW\r
-.set SCSI_Out_DBx__DB3__AG, CYREG_PRT6_AG\r
-.set SCSI_Out_DBx__DB3__AMUX, CYREG_PRT6_AMUX\r
-.set SCSI_Out_DBx__DB3__BIE, CYREG_PRT6_BIE\r
-.set SCSI_Out_DBx__DB3__BIT_MASK, CYREG_PRT6_BIT_MASK\r
-.set SCSI_Out_DBx__DB3__BYP, CYREG_PRT6_BYP\r
-.set SCSI_Out_DBx__DB3__CTL, CYREG_PRT6_CTL\r
-.set SCSI_Out_DBx__DB3__DM0, CYREG_PRT6_DM0\r
-.set SCSI_Out_DBx__DB3__DM1, CYREG_PRT6_DM1\r
-.set SCSI_Out_DBx__DB3__DM2, CYREG_PRT6_DM2\r
-.set SCSI_Out_DBx__DB3__DR, CYREG_PRT6_DR\r
-.set SCSI_Out_DBx__DB3__INP_DIS, CYREG_PRT6_INP_DIS\r
-.set SCSI_Out_DBx__DB3__INTTYPE, CYREG_PICU6_INTTYPE0\r
-.set SCSI_Out_DBx__DB3__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG\r
-.set SCSI_Out_DBx__DB3__LCD_EN, CYREG_PRT6_LCD_EN\r
-.set SCSI_Out_DBx__DB3__MASK, 0x01\r
-.set SCSI_Out_DBx__DB3__PC, CYREG_PRT6_PC0\r
-.set SCSI_Out_DBx__DB3__PORT, 6\r
-.set SCSI_Out_DBx__DB3__PRT, CYREG_PRT6_PRT\r
-.set SCSI_Out_DBx__DB3__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL\r
-.set SCSI_Out_DBx__DB3__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN\r
-.set SCSI_Out_DBx__DB3__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0\r
-.set SCSI_Out_DBx__DB3__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1\r
-.set SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0\r
-.set SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1\r
-.set SCSI_Out_DBx__DB3__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT\r
-.set SCSI_Out_DBx__DB3__PS, CYREG_PRT6_PS\r
-.set SCSI_Out_DBx__DB3__SHIFT, 0\r
-.set SCSI_Out_DBx__DB3__SLW, CYREG_PRT6_SLW\r
-.set SCSI_Out_DBx__DB4__AG, CYREG_PRT4_AG\r
-.set SCSI_Out_DBx__DB4__AMUX, CYREG_PRT4_AMUX\r
-.set SCSI_Out_DBx__DB4__BIE, CYREG_PRT4_BIE\r
-.set SCSI_Out_DBx__DB4__BIT_MASK, CYREG_PRT4_BIT_MASK\r
-.set SCSI_Out_DBx__DB4__BYP, CYREG_PRT4_BYP\r
-.set SCSI_Out_DBx__DB4__CTL, CYREG_PRT4_CTL\r
-.set SCSI_Out_DBx__DB4__DM0, CYREG_PRT4_DM0\r
-.set SCSI_Out_DBx__DB4__DM1, CYREG_PRT4_DM1\r
-.set SCSI_Out_DBx__DB4__DM2, CYREG_PRT4_DM2\r
-.set SCSI_Out_DBx__DB4__DR, CYREG_PRT4_DR\r
-.set SCSI_Out_DBx__DB4__INP_DIS, CYREG_PRT4_INP_DIS\r
-.set SCSI_Out_DBx__DB4__INTTYPE, CYREG_PICU4_INTTYPE7\r
-.set SCSI_Out_DBx__DB4__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG\r
-.set SCSI_Out_DBx__DB4__LCD_EN, CYREG_PRT4_LCD_EN\r
-.set SCSI_Out_DBx__DB4__MASK, 0x80\r
-.set SCSI_Out_DBx__DB4__PC, CYREG_PRT4_PC7\r
-.set SCSI_Out_DBx__DB4__PORT, 4\r
-.set SCSI_Out_DBx__DB4__PRT, CYREG_PRT4_PRT\r
-.set SCSI_Out_DBx__DB4__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL\r
-.set SCSI_Out_DBx__DB4__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN\r
-.set SCSI_Out_DBx__DB4__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0\r
-.set SCSI_Out_DBx__DB4__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1\r
-.set SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0\r
-.set SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1\r
-.set SCSI_Out_DBx__DB4__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT\r
-.set SCSI_Out_DBx__DB4__PS, CYREG_PRT4_PS\r
-.set SCSI_Out_DBx__DB4__SHIFT, 7\r
-.set SCSI_Out_DBx__DB4__SLW, CYREG_PRT4_SLW\r
-.set SCSI_Out_DBx__DB5__AG, CYREG_PRT4_AG\r
-.set SCSI_Out_DBx__DB5__AMUX, CYREG_PRT4_AMUX\r
-.set SCSI_Out_DBx__DB5__BIE, CYREG_PRT4_BIE\r
-.set SCSI_Out_DBx__DB5__BIT_MASK, CYREG_PRT4_BIT_MASK\r
-.set SCSI_Out_DBx__DB5__BYP, CYREG_PRT4_BYP\r
-.set SCSI_Out_DBx__DB5__CTL, CYREG_PRT4_CTL\r
-.set SCSI_Out_DBx__DB5__DM0, CYREG_PRT4_DM0\r
-.set SCSI_Out_DBx__DB5__DM1, CYREG_PRT4_DM1\r
-.set SCSI_Out_DBx__DB5__DM2, CYREG_PRT4_DM2\r
-.set SCSI_Out_DBx__DB5__DR, CYREG_PRT4_DR\r
-.set SCSI_Out_DBx__DB5__INP_DIS, CYREG_PRT4_INP_DIS\r
-.set SCSI_Out_DBx__DB5__INTTYPE, CYREG_PICU4_INTTYPE6\r
-.set SCSI_Out_DBx__DB5__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG\r
-.set SCSI_Out_DBx__DB5__LCD_EN, CYREG_PRT4_LCD_EN\r
-.set SCSI_Out_DBx__DB5__MASK, 0x40\r
-.set SCSI_Out_DBx__DB5__PC, CYREG_PRT4_PC6\r
-.set SCSI_Out_DBx__DB5__PORT, 4\r
-.set SCSI_Out_DBx__DB5__PRT, CYREG_PRT4_PRT\r
-.set SCSI_Out_DBx__DB5__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL\r
-.set SCSI_Out_DBx__DB5__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN\r
-.set SCSI_Out_DBx__DB5__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0\r
-.set SCSI_Out_DBx__DB5__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1\r
-.set SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0\r
-.set SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1\r
-.set SCSI_Out_DBx__DB5__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT\r
-.set SCSI_Out_DBx__DB5__PS, CYREG_PRT4_PS\r
-.set SCSI_Out_DBx__DB5__SHIFT, 6\r
-.set SCSI_Out_DBx__DB5__SLW, CYREG_PRT4_SLW\r
-.set SCSI_Out_DBx__DB6__AG, CYREG_PRT4_AG\r
-.set SCSI_Out_DBx__DB6__AMUX, CYREG_PRT4_AMUX\r
-.set SCSI_Out_DBx__DB6__BIE, CYREG_PRT4_BIE\r
-.set SCSI_Out_DBx__DB6__BIT_MASK, CYREG_PRT4_BIT_MASK\r
-.set SCSI_Out_DBx__DB6__BYP, CYREG_PRT4_BYP\r
-.set SCSI_Out_DBx__DB6__CTL, CYREG_PRT4_CTL\r
-.set SCSI_Out_DBx__DB6__DM0, CYREG_PRT4_DM0\r
-.set SCSI_Out_DBx__DB6__DM1, CYREG_PRT4_DM1\r
-.set SCSI_Out_DBx__DB6__DM2, CYREG_PRT4_DM2\r
-.set SCSI_Out_DBx__DB6__DR, CYREG_PRT4_DR\r
-.set SCSI_Out_DBx__DB6__INP_DIS, CYREG_PRT4_INP_DIS\r
-.set SCSI_Out_DBx__DB6__INTTYPE, CYREG_PICU4_INTTYPE5\r
-.set SCSI_Out_DBx__DB6__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG\r
-.set SCSI_Out_DBx__DB6__LCD_EN, CYREG_PRT4_LCD_EN\r
-.set SCSI_Out_DBx__DB6__MASK, 0x20\r
-.set SCSI_Out_DBx__DB6__PC, CYREG_PRT4_PC5\r
-.set SCSI_Out_DBx__DB6__PORT, 4\r
-.set SCSI_Out_DBx__DB6__PRT, CYREG_PRT4_PRT\r
-.set SCSI_Out_DBx__DB6__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL\r
-.set SCSI_Out_DBx__DB6__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN\r
-.set SCSI_Out_DBx__DB6__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0\r
-.set SCSI_Out_DBx__DB6__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1\r
-.set SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0\r
-.set SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1\r
-.set SCSI_Out_DBx__DB6__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT\r
-.set SCSI_Out_DBx__DB6__PS, CYREG_PRT4_PS\r
-.set SCSI_Out_DBx__DB6__SHIFT, 5\r
-.set SCSI_Out_DBx__DB6__SLW, CYREG_PRT4_SLW\r
-.set SCSI_Out_DBx__DB7__AG, CYREG_PRT4_AG\r
-.set SCSI_Out_DBx__DB7__AMUX, CYREG_PRT4_AMUX\r
-.set SCSI_Out_DBx__DB7__BIE, CYREG_PRT4_BIE\r
-.set SCSI_Out_DBx__DB7__BIT_MASK, CYREG_PRT4_BIT_MASK\r
-.set SCSI_Out_DBx__DB7__BYP, CYREG_PRT4_BYP\r
-.set SCSI_Out_DBx__DB7__CTL, CYREG_PRT4_CTL\r
-.set SCSI_Out_DBx__DB7__DM0, CYREG_PRT4_DM0\r
-.set SCSI_Out_DBx__DB7__DM1, CYREG_PRT4_DM1\r
-.set SCSI_Out_DBx__DB7__DM2, CYREG_PRT4_DM2\r
-.set SCSI_Out_DBx__DB7__DR, CYREG_PRT4_DR\r
-.set SCSI_Out_DBx__DB7__INP_DIS, CYREG_PRT4_INP_DIS\r
-.set SCSI_Out_DBx__DB7__INTTYPE, CYREG_PICU4_INTTYPE4\r
-.set SCSI_Out_DBx__DB7__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG\r
-.set SCSI_Out_DBx__DB7__LCD_EN, CYREG_PRT4_LCD_EN\r
-.set SCSI_Out_DBx__DB7__MASK, 0x10\r
-.set SCSI_Out_DBx__DB7__PC, CYREG_PRT4_PC4\r
-.set SCSI_Out_DBx__DB7__PORT, 4\r
-.set SCSI_Out_DBx__DB7__PRT, CYREG_PRT4_PRT\r
-.set SCSI_Out_DBx__DB7__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL\r
-.set SCSI_Out_DBx__DB7__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN\r
-.set SCSI_Out_DBx__DB7__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0\r
-.set SCSI_Out_DBx__DB7__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1\r
-.set SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0\r
-.set SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1\r
-.set SCSI_Out_DBx__DB7__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT\r
-.set SCSI_Out_DBx__DB7__PS, CYREG_PRT4_PS\r
-.set SCSI_Out_DBx__DB7__SHIFT, 4\r
-.set SCSI_Out_DBx__DB7__SLW, CYREG_PRT4_SLW\r
-\r
-/* SD_RX_DMA */\r
-.set SD_RX_DMA__DRQ_CTL, CYREG_IDMUX_DRQ_CTL0\r
-.set SD_RX_DMA__DRQ_NUMBER, 2\r
-.set SD_RX_DMA__NUMBEROF_TDS, 0\r
-.set SD_RX_DMA__PRIORITY, 0\r
-.set SD_RX_DMA__TERMIN_EN, 0\r
-.set SD_RX_DMA__TERMIN_SEL, 0\r
-.set SD_RX_DMA__TERMOUT0_EN, 1\r
-.set SD_RX_DMA__TERMOUT0_SEL, 2\r
-.set SD_RX_DMA__TERMOUT1_EN, 0\r
-.set SD_RX_DMA__TERMOUT1_SEL, 0\r
-\r
-/* SD_RX_DMA_COMPLETE */\r
-.set SD_RX_DMA_COMPLETE__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
-.set SD_RX_DMA_COMPLETE__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
-.set SD_RX_DMA_COMPLETE__INTC_MASK, 0x20\r
-.set SD_RX_DMA_COMPLETE__INTC_NUMBER, 5\r
-.set SD_RX_DMA_COMPLETE__INTC_PRIOR_NUM, 7\r
-.set SD_RX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_5\r
-.set SD_RX_DMA_COMPLETE__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
-.set SD_RX_DMA_COMPLETE__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
-\r
-/* SD_TX_DMA */\r
-.set SD_TX_DMA__DRQ_CTL, CYREG_IDMUX_DRQ_CTL0\r
-.set SD_TX_DMA__DRQ_NUMBER, 3\r
-.set SD_TX_DMA__NUMBEROF_TDS, 0\r
-.set SD_TX_DMA__PRIORITY, 1\r
-.set SD_TX_DMA__TERMIN_EN, 0\r
-.set SD_TX_DMA__TERMIN_SEL, 0\r
-.set SD_TX_DMA__TERMOUT0_EN, 1\r
-.set SD_TX_DMA__TERMOUT0_SEL, 3\r
-.set SD_TX_DMA__TERMOUT1_EN, 0\r
-.set SD_TX_DMA__TERMOUT1_SEL, 0\r
-\r
-/* SD_TX_DMA_COMPLETE */\r
-.set SD_TX_DMA_COMPLETE__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
-.set SD_TX_DMA_COMPLETE__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
-.set SD_TX_DMA_COMPLETE__INTC_MASK, 0x40\r
-.set SD_TX_DMA_COMPLETE__INTC_NUMBER, 6\r
-.set SD_TX_DMA_COMPLETE__INTC_PRIOR_NUM, 7\r
-.set SD_TX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_6\r
-.set SD_TX_DMA_COMPLETE__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
-.set SD_TX_DMA_COMPLETE__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
+/* SCSI_In */\r
+.set SCSI_In__0__AG, CYREG_PRT2_AG\r
+.set SCSI_In__0__AMUX, CYREG_PRT2_AMUX\r
+.set SCSI_In__0__BIE, CYREG_PRT2_BIE\r
+.set SCSI_In__0__BIT_MASK, CYREG_PRT2_BIT_MASK\r
+.set SCSI_In__0__BYP, CYREG_PRT2_BYP\r
+.set SCSI_In__0__CTL, CYREG_PRT2_CTL\r
+.set SCSI_In__0__DM0, CYREG_PRT2_DM0\r
+.set SCSI_In__0__DM1, CYREG_PRT2_DM1\r
+.set SCSI_In__0__DM2, CYREG_PRT2_DM2\r
+.set SCSI_In__0__DR, CYREG_PRT2_DR\r
+.set SCSI_In__0__INP_DIS, CYREG_PRT2_INP_DIS\r
+.set SCSI_In__0__INTTYPE, CYREG_PICU2_INTTYPE0\r
+.set SCSI_In__0__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG\r
+.set SCSI_In__0__LCD_EN, CYREG_PRT2_LCD_EN\r
+.set SCSI_In__0__MASK, 0x01\r
+.set SCSI_In__0__PC, CYREG_PRT2_PC0\r
+.set SCSI_In__0__PORT, 2\r
+.set SCSI_In__0__PRT, CYREG_PRT2_PRT\r
+.set SCSI_In__0__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL\r
+.set SCSI_In__0__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN\r
+.set SCSI_In__0__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0\r
+.set SCSI_In__0__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1\r
+.set SCSI_In__0__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0\r
+.set SCSI_In__0__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1\r
+.set SCSI_In__0__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT\r
+.set SCSI_In__0__PS, CYREG_PRT2_PS\r
+.set SCSI_In__0__SHIFT, 0\r
+.set SCSI_In__0__SLW, CYREG_PRT2_SLW\r
+.set SCSI_In__1__AG, CYREG_PRT6_AG\r
+.set SCSI_In__1__AMUX, CYREG_PRT6_AMUX\r
+.set SCSI_In__1__BIE, CYREG_PRT6_BIE\r
+.set SCSI_In__1__BIT_MASK, CYREG_PRT6_BIT_MASK\r
+.set SCSI_In__1__BYP, CYREG_PRT6_BYP\r
+.set SCSI_In__1__CTL, CYREG_PRT6_CTL\r
+.set SCSI_In__1__DM0, CYREG_PRT6_DM0\r
+.set SCSI_In__1__DM1, CYREG_PRT6_DM1\r
+.set SCSI_In__1__DM2, CYREG_PRT6_DM2\r
+.set SCSI_In__1__DR, CYREG_PRT6_DR\r
+.set SCSI_In__1__INP_DIS, CYREG_PRT6_INP_DIS\r
+.set SCSI_In__1__INTTYPE, CYREG_PICU6_INTTYPE7\r
+.set SCSI_In__1__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG\r
+.set SCSI_In__1__LCD_EN, CYREG_PRT6_LCD_EN\r
+.set SCSI_In__1__MASK, 0x80\r
+.set SCSI_In__1__PC, CYREG_PRT6_PC7\r
+.set SCSI_In__1__PORT, 6\r
+.set SCSI_In__1__PRT, CYREG_PRT6_PRT\r
+.set SCSI_In__1__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL\r
+.set SCSI_In__1__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN\r
+.set SCSI_In__1__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0\r
+.set SCSI_In__1__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1\r
+.set SCSI_In__1__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0\r
+.set SCSI_In__1__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1\r
+.set SCSI_In__1__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT\r
+.set SCSI_In__1__PS, CYREG_PRT6_PS\r
+.set SCSI_In__1__SHIFT, 7\r
+.set SCSI_In__1__SLW, CYREG_PRT6_SLW\r
+.set SCSI_In__2__AG, CYREG_PRT5_AG\r
+.set SCSI_In__2__AMUX, CYREG_PRT5_AMUX\r
+.set SCSI_In__2__BIE, CYREG_PRT5_BIE\r
+.set SCSI_In__2__BIT_MASK, CYREG_PRT5_BIT_MASK\r
+.set SCSI_In__2__BYP, CYREG_PRT5_BYP\r
+.set SCSI_In__2__CTL, CYREG_PRT5_CTL\r
+.set SCSI_In__2__DM0, CYREG_PRT5_DM0\r
+.set SCSI_In__2__DM1, CYREG_PRT5_DM1\r
+.set SCSI_In__2__DM2, CYREG_PRT5_DM2\r
+.set SCSI_In__2__DR, CYREG_PRT5_DR\r
+.set SCSI_In__2__INP_DIS, CYREG_PRT5_INP_DIS\r
+.set SCSI_In__2__INTTYPE, CYREG_PICU5_INTTYPE1\r
+.set SCSI_In__2__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG\r
+.set SCSI_In__2__LCD_EN, CYREG_PRT5_LCD_EN\r
+.set SCSI_In__2__MASK, 0x02\r
+.set SCSI_In__2__PC, CYREG_PRT5_PC1\r
+.set SCSI_In__2__PORT, 5\r
+.set SCSI_In__2__PRT, CYREG_PRT5_PRT\r
+.set SCSI_In__2__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL\r
+.set SCSI_In__2__PRTDSI__DBL_SYNC_IN, CYREG_PRT5_DBL_SYNC_IN\r
+.set SCSI_In__2__PRTDSI__OE_SEL0, CYREG_PRT5_OE_SEL0\r
+.set SCSI_In__2__PRTDSI__OE_SEL1, CYREG_PRT5_OE_SEL1\r
+.set SCSI_In__2__PRTDSI__OUT_SEL0, CYREG_PRT5_OUT_SEL0\r
+.set SCSI_In__2__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1\r
+.set SCSI_In__2__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT\r
+.set SCSI_In__2__PS, CYREG_PRT5_PS\r
+.set SCSI_In__2__SHIFT, 1\r
+.set SCSI_In__2__SLW, CYREG_PRT5_SLW\r
+.set SCSI_In__3__AG, CYREG_PRT5_AG\r
+.set SCSI_In__3__AMUX, CYREG_PRT5_AMUX\r
+.set SCSI_In__3__BIE, CYREG_PRT5_BIE\r
+.set SCSI_In__3__BIT_MASK, CYREG_PRT5_BIT_MASK\r
+.set SCSI_In__3__BYP, CYREG_PRT5_BYP\r
+.set SCSI_In__3__CTL, CYREG_PRT5_CTL\r
+.set SCSI_In__3__DM0, CYREG_PRT5_DM0\r
+.set SCSI_In__3__DM1, CYREG_PRT5_DM1\r
+.set SCSI_In__3__DM2, CYREG_PRT5_DM2\r
+.set SCSI_In__3__DR, CYREG_PRT5_DR\r
+.set SCSI_In__3__INP_DIS, CYREG_PRT5_INP_DIS\r
+.set SCSI_In__3__INTTYPE, CYREG_PICU5_INTTYPE2\r
+.set SCSI_In__3__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG\r
+.set SCSI_In__3__LCD_EN, CYREG_PRT5_LCD_EN\r
+.set SCSI_In__3__MASK, 0x04\r
+.set SCSI_In__3__PC, CYREG_PRT5_PC2\r
+.set SCSI_In__3__PORT, 5\r
+.set SCSI_In__3__PRT, CYREG_PRT5_PRT\r
+.set SCSI_In__3__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL\r
+.set SCSI_In__3__PRTDSI__DBL_SYNC_IN, CYREG_PRT5_DBL_SYNC_IN\r
+.set SCSI_In__3__PRTDSI__OE_SEL0, CYREG_PRT5_OE_SEL0\r
+.set SCSI_In__3__PRTDSI__OE_SEL1, CYREG_PRT5_OE_SEL1\r
+.set SCSI_In__3__PRTDSI__OUT_SEL0, CYREG_PRT5_OUT_SEL0\r
+.set SCSI_In__3__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1\r
+.set SCSI_In__3__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT\r
+.set SCSI_In__3__PS, CYREG_PRT5_PS\r
+.set SCSI_In__3__SHIFT, 2\r
+.set SCSI_In__3__SLW, CYREG_PRT5_SLW\r
+.set SCSI_In__4__AG, CYREG_PRT5_AG\r
+.set SCSI_In__4__AMUX, CYREG_PRT5_AMUX\r
+.set SCSI_In__4__BIE, CYREG_PRT5_BIE\r
+.set SCSI_In__4__BIT_MASK, CYREG_PRT5_BIT_MASK\r
+.set SCSI_In__4__BYP, CYREG_PRT5_BYP\r
+.set SCSI_In__4__CTL, CYREG_PRT5_CTL\r
+.set SCSI_In__4__DM0, CYREG_PRT5_DM0\r
+.set SCSI_In__4__DM1, CYREG_PRT5_DM1\r
+.set SCSI_In__4__DM2, CYREG_PRT5_DM2\r
+.set SCSI_In__4__DR, CYREG_PRT5_DR\r
+.set SCSI_In__4__INP_DIS, CYREG_PRT5_INP_DIS\r
+.set SCSI_In__4__INTTYPE, CYREG_PICU5_INTTYPE3\r
+.set SCSI_In__4__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG\r
+.set SCSI_In__4__LCD_EN, CYREG_PRT5_LCD_EN\r
+.set SCSI_In__4__MASK, 0x08\r
+.set SCSI_In__4__PC, CYREG_PRT5_PC3\r
+.set SCSI_In__4__PORT, 5\r
+.set SCSI_In__4__PRT, CYREG_PRT5_PRT\r
+.set SCSI_In__4__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL\r
+.set SCSI_In__4__PRTDSI__DBL_SYNC_IN, CYREG_PRT5_DBL_SYNC_IN\r
+.set SCSI_In__4__PRTDSI__OE_SEL0, CYREG_PRT5_OE_SEL0\r
+.set SCSI_In__4__PRTDSI__OE_SEL1, CYREG_PRT5_OE_SEL1\r
+.set SCSI_In__4__PRTDSI__OUT_SEL0, CYREG_PRT5_OUT_SEL0\r
+.set SCSI_In__4__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1\r
+.set SCSI_In__4__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT\r
+.set SCSI_In__4__PS, CYREG_PRT5_PS\r
+.set SCSI_In__4__SHIFT, 3\r
+.set SCSI_In__4__SLW, CYREG_PRT5_SLW\r
+.set SCSI_In__CD__AG, CYREG_PRT5_AG\r
+.set SCSI_In__CD__AMUX, CYREG_PRT5_AMUX\r
+.set SCSI_In__CD__BIE, CYREG_PRT5_BIE\r
+.set SCSI_In__CD__BIT_MASK, CYREG_PRT5_BIT_MASK\r
+.set SCSI_In__CD__BYP, CYREG_PRT5_BYP\r
+.set SCSI_In__CD__CTL, CYREG_PRT5_CTL\r
+.set SCSI_In__CD__DM0, CYREG_PRT5_DM0\r
+.set SCSI_In__CD__DM1, CYREG_PRT5_DM1\r
+.set SCSI_In__CD__DM2, CYREG_PRT5_DM2\r
+.set SCSI_In__CD__DR, CYREG_PRT5_DR\r
+.set SCSI_In__CD__INP_DIS, CYREG_PRT5_INP_DIS\r
+.set SCSI_In__CD__INTTYPE, CYREG_PICU5_INTTYPE1\r
+.set SCSI_In__CD__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG\r
+.set SCSI_In__CD__LCD_EN, CYREG_PRT5_LCD_EN\r
+.set SCSI_In__CD__MASK, 0x02\r
+.set SCSI_In__CD__PC, CYREG_PRT5_PC1\r
+.set SCSI_In__CD__PORT, 5\r
+.set SCSI_In__CD__PRT, CYREG_PRT5_PRT\r
+.set SCSI_In__CD__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL\r
+.set SCSI_In__CD__PRTDSI__DBL_SYNC_IN, CYREG_PRT5_DBL_SYNC_IN\r
+.set SCSI_In__CD__PRTDSI__OE_SEL0, CYREG_PRT5_OE_SEL0\r
+.set SCSI_In__CD__PRTDSI__OE_SEL1, CYREG_PRT5_OE_SEL1\r
+.set SCSI_In__CD__PRTDSI__OUT_SEL0, CYREG_PRT5_OUT_SEL0\r
+.set SCSI_In__CD__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1\r
+.set SCSI_In__CD__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT\r
+.set SCSI_In__CD__PS, CYREG_PRT5_PS\r
+.set SCSI_In__CD__SHIFT, 1\r
+.set SCSI_In__CD__SLW, CYREG_PRT5_SLW\r
+.set SCSI_In__DBP__AG, CYREG_PRT2_AG\r
+.set SCSI_In__DBP__AMUX, CYREG_PRT2_AMUX\r
+.set SCSI_In__DBP__BIE, CYREG_PRT2_BIE\r
+.set SCSI_In__DBP__BIT_MASK, CYREG_PRT2_BIT_MASK\r
+.set SCSI_In__DBP__BYP, CYREG_PRT2_BYP\r
+.set SCSI_In__DBP__CTL, CYREG_PRT2_CTL\r
+.set SCSI_In__DBP__DM0, CYREG_PRT2_DM0\r
+.set SCSI_In__DBP__DM1, CYREG_PRT2_DM1\r
+.set SCSI_In__DBP__DM2, CYREG_PRT2_DM2\r
+.set SCSI_In__DBP__DR, CYREG_PRT2_DR\r
+.set SCSI_In__DBP__INP_DIS, CYREG_PRT2_INP_DIS\r
+.set SCSI_In__DBP__INTTYPE, CYREG_PICU2_INTTYPE0\r
+.set SCSI_In__DBP__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG\r
+.set SCSI_In__DBP__LCD_EN, CYREG_PRT2_LCD_EN\r
+.set SCSI_In__DBP__MASK, 0x01\r
+.set SCSI_In__DBP__PC, CYREG_PRT2_PC0\r
+.set SCSI_In__DBP__PORT, 2\r
+.set SCSI_In__DBP__PRT, CYREG_PRT2_PRT\r
+.set SCSI_In__DBP__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL\r
+.set SCSI_In__DBP__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN\r
+.set SCSI_In__DBP__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0\r
+.set SCSI_In__DBP__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1\r
+.set SCSI_In__DBP__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0\r
+.set SCSI_In__DBP__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1\r
+.set SCSI_In__DBP__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT\r
+.set SCSI_In__DBP__PS, CYREG_PRT2_PS\r
+.set SCSI_In__DBP__SHIFT, 0\r
+.set SCSI_In__DBP__SLW, CYREG_PRT2_SLW\r
+.set SCSI_In__IO__AG, CYREG_PRT5_AG\r
+.set SCSI_In__IO__AMUX, CYREG_PRT5_AMUX\r
+.set SCSI_In__IO__BIE, CYREG_PRT5_BIE\r
+.set SCSI_In__IO__BIT_MASK, CYREG_PRT5_BIT_MASK\r
+.set SCSI_In__IO__BYP, CYREG_PRT5_BYP\r
+.set SCSI_In__IO__CTL, CYREG_PRT5_CTL\r
+.set SCSI_In__IO__DM0, CYREG_PRT5_DM0\r
+.set SCSI_In__IO__DM1, CYREG_PRT5_DM1\r
+.set SCSI_In__IO__DM2, CYREG_PRT5_DM2\r
+.set SCSI_In__IO__DR, CYREG_PRT5_DR\r
+.set SCSI_In__IO__INP_DIS, CYREG_PRT5_INP_DIS\r
+.set SCSI_In__IO__INTTYPE, CYREG_PICU5_INTTYPE3\r
+.set SCSI_In__IO__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG\r
+.set SCSI_In__IO__LCD_EN, CYREG_PRT5_LCD_EN\r
+.set SCSI_In__IO__MASK, 0x08\r
+.set SCSI_In__IO__PC, CYREG_PRT5_PC3\r
+.set SCSI_In__IO__PORT, 5\r
+.set SCSI_In__IO__PRT, CYREG_PRT5_PRT\r
+.set SCSI_In__IO__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL\r
+.set SCSI_In__IO__PRTDSI__DBL_SYNC_IN, CYREG_PRT5_DBL_SYNC_IN\r
+.set SCSI_In__IO__PRTDSI__OE_SEL0, CYREG_PRT5_OE_SEL0\r
+.set SCSI_In__IO__PRTDSI__OE_SEL1, CYREG_PRT5_OE_SEL1\r
+.set SCSI_In__IO__PRTDSI__OUT_SEL0, CYREG_PRT5_OUT_SEL0\r
+.set SCSI_In__IO__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1\r
+.set SCSI_In__IO__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT\r
+.set SCSI_In__IO__PS, CYREG_PRT5_PS\r
+.set SCSI_In__IO__SHIFT, 3\r
+.set SCSI_In__IO__SLW, CYREG_PRT5_SLW\r
+.set SCSI_In__MSG__AG, CYREG_PRT6_AG\r
+.set SCSI_In__MSG__AMUX, CYREG_PRT6_AMUX\r
+.set SCSI_In__MSG__BIE, CYREG_PRT6_BIE\r
+.set SCSI_In__MSG__BIT_MASK, CYREG_PRT6_BIT_MASK\r
+.set SCSI_In__MSG__BYP, CYREG_PRT6_BYP\r
+.set SCSI_In__MSG__CTL, CYREG_PRT6_CTL\r
+.set SCSI_In__MSG__DM0, CYREG_PRT6_DM0\r
+.set SCSI_In__MSG__DM1, CYREG_PRT6_DM1\r
+.set SCSI_In__MSG__DM2, CYREG_PRT6_DM2\r
+.set SCSI_In__MSG__DR, CYREG_PRT6_DR\r
+.set SCSI_In__MSG__INP_DIS, CYREG_PRT6_INP_DIS\r
+.set SCSI_In__MSG__INTTYPE, CYREG_PICU6_INTTYPE7\r
+.set SCSI_In__MSG__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG\r
+.set SCSI_In__MSG__LCD_EN, CYREG_PRT6_LCD_EN\r
+.set SCSI_In__MSG__MASK, 0x80\r
+.set SCSI_In__MSG__PC, CYREG_PRT6_PC7\r
+.set SCSI_In__MSG__PORT, 6\r
+.set SCSI_In__MSG__PRT, CYREG_PRT6_PRT\r
+.set SCSI_In__MSG__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL\r
+.set SCSI_In__MSG__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN\r
+.set SCSI_In__MSG__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0\r
+.set SCSI_In__MSG__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1\r
+.set SCSI_In__MSG__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0\r
+.set SCSI_In__MSG__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1\r
+.set SCSI_In__MSG__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT\r
+.set SCSI_In__MSG__PS, CYREG_PRT6_PS\r
+.set SCSI_In__MSG__SHIFT, 7\r
+.set SCSI_In__MSG__SLW, CYREG_PRT6_SLW\r
+.set SCSI_In__REQ__AG, CYREG_PRT5_AG\r
+.set SCSI_In__REQ__AMUX, CYREG_PRT5_AMUX\r
+.set SCSI_In__REQ__BIE, CYREG_PRT5_BIE\r
+.set SCSI_In__REQ__BIT_MASK, CYREG_PRT5_BIT_MASK\r
+.set SCSI_In__REQ__BYP, CYREG_PRT5_BYP\r
+.set SCSI_In__REQ__CTL, CYREG_PRT5_CTL\r
+.set SCSI_In__REQ__DM0, CYREG_PRT5_DM0\r
+.set SCSI_In__REQ__DM1, CYREG_PRT5_DM1\r
+.set SCSI_In__REQ__DM2, CYREG_PRT5_DM2\r
+.set SCSI_In__REQ__DR, CYREG_PRT5_DR\r
+.set SCSI_In__REQ__INP_DIS, CYREG_PRT5_INP_DIS\r
+.set SCSI_In__REQ__INTTYPE, CYREG_PICU5_INTTYPE2\r
+.set SCSI_In__REQ__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG\r
+.set SCSI_In__REQ__LCD_EN, CYREG_PRT5_LCD_EN\r
+.set SCSI_In__REQ__MASK, 0x04\r
+.set SCSI_In__REQ__PC, CYREG_PRT5_PC2\r
+.set SCSI_In__REQ__PORT, 5\r
+.set SCSI_In__REQ__PRT, CYREG_PRT5_PRT\r
+.set SCSI_In__REQ__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL\r
+.set SCSI_In__REQ__PRTDSI__DBL_SYNC_IN, CYREG_PRT5_DBL_SYNC_IN\r
+.set SCSI_In__REQ__PRTDSI__OE_SEL0, CYREG_PRT5_OE_SEL0\r
+.set SCSI_In__REQ__PRTDSI__OE_SEL1, CYREG_PRT5_OE_SEL1\r
+.set SCSI_In__REQ__PRTDSI__OUT_SEL0, CYREG_PRT5_OUT_SEL0\r
+.set SCSI_In__REQ__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1\r
+.set SCSI_In__REQ__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT\r
+.set SCSI_In__REQ__PS, CYREG_PRT5_PS\r
+.set SCSI_In__REQ__SHIFT, 2\r
+.set SCSI_In__REQ__SLW, CYREG_PRT5_SLW\r
+.set SCSI_In_DBx__0__AG, CYREG_PRT12_AG\r
+.set SCSI_In_DBx__0__BIE, CYREG_PRT12_BIE\r
+.set SCSI_In_DBx__0__BIT_MASK, CYREG_PRT12_BIT_MASK\r
+.set SCSI_In_DBx__0__BYP, CYREG_PRT12_BYP\r
+.set SCSI_In_DBx__0__DM0, CYREG_PRT12_DM0\r
+.set SCSI_In_DBx__0__DM1, CYREG_PRT12_DM1\r
+.set SCSI_In_DBx__0__DM2, CYREG_PRT12_DM2\r
+.set SCSI_In_DBx__0__DR, CYREG_PRT12_DR\r
+.set SCSI_In_DBx__0__INP_DIS, CYREG_PRT12_INP_DIS\r
+.set SCSI_In_DBx__0__INTTYPE, CYREG_PICU12_INTTYPE4\r
+.set SCSI_In_DBx__0__MASK, 0x10\r
+.set SCSI_In_DBx__0__PC, CYREG_PRT12_PC4\r
+.set SCSI_In_DBx__0__PORT, 12\r
+.set SCSI_In_DBx__0__PRT, CYREG_PRT12_PRT\r
+.set SCSI_In_DBx__0__PRTDSI__DBL_SYNC_IN, CYREG_PRT12_DBL_SYNC_IN\r
+.set SCSI_In_DBx__0__PRTDSI__OE_SEL0, CYREG_PRT12_OE_SEL0\r
+.set SCSI_In_DBx__0__PRTDSI__OE_SEL1, CYREG_PRT12_OE_SEL1\r
+.set SCSI_In_DBx__0__PRTDSI__OUT_SEL0, CYREG_PRT12_OUT_SEL0\r
+.set SCSI_In_DBx__0__PRTDSI__OUT_SEL1, CYREG_PRT12_OUT_SEL1\r
+.set SCSI_In_DBx__0__PRTDSI__SYNC_OUT, CYREG_PRT12_SYNC_OUT\r
+.set SCSI_In_DBx__0__PS, CYREG_PRT12_PS\r
+.set SCSI_In_DBx__0__SHIFT, 4\r
+.set SCSI_In_DBx__0__SIO_CFG, CYREG_PRT12_SIO_CFG\r
+.set SCSI_In_DBx__0__SIO_DIFF, CYREG_PRT12_SIO_DIFF\r
+.set SCSI_In_DBx__0__SIO_HYST_EN, CYREG_PRT12_SIO_HYST_EN\r
+.set SCSI_In_DBx__0__SIO_REG_HIFREQ, CYREG_PRT12_SIO_REG_HIFREQ\r
+.set SCSI_In_DBx__0__SLW, CYREG_PRT12_SLW\r
+.set SCSI_In_DBx__1__AG, CYREG_PRT2_AG\r
+.set SCSI_In_DBx__1__AMUX, CYREG_PRT2_AMUX\r
+.set SCSI_In_DBx__1__BIE, CYREG_PRT2_BIE\r
+.set SCSI_In_DBx__1__BIT_MASK, CYREG_PRT2_BIT_MASK\r
+.set SCSI_In_DBx__1__BYP, CYREG_PRT2_BYP\r
+.set SCSI_In_DBx__1__CTL, CYREG_PRT2_CTL\r
+.set SCSI_In_DBx__1__DM0, CYREG_PRT2_DM0\r
+.set SCSI_In_DBx__1__DM1, CYREG_PRT2_DM1\r
+.set SCSI_In_DBx__1__DM2, CYREG_PRT2_DM2\r
+.set SCSI_In_DBx__1__DR, CYREG_PRT2_DR\r
+.set SCSI_In_DBx__1__INP_DIS, CYREG_PRT2_INP_DIS\r
+.set SCSI_In_DBx__1__INTTYPE, CYREG_PICU2_INTTYPE7\r
+.set SCSI_In_DBx__1__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG\r
+.set SCSI_In_DBx__1__LCD_EN, CYREG_PRT2_LCD_EN\r
+.set SCSI_In_DBx__1__MASK, 0x80\r
+.set SCSI_In_DBx__1__PC, CYREG_PRT2_PC7\r
+.set SCSI_In_DBx__1__PORT, 2\r
+.set SCSI_In_DBx__1__PRT, CYREG_PRT2_PRT\r
+.set SCSI_In_DBx__1__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL\r
+.set SCSI_In_DBx__1__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN\r
+.set SCSI_In_DBx__1__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0\r
+.set SCSI_In_DBx__1__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1\r
+.set SCSI_In_DBx__1__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0\r
+.set SCSI_In_DBx__1__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1\r
+.set SCSI_In_DBx__1__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT\r
+.set SCSI_In_DBx__1__PS, CYREG_PRT2_PS\r
+.set SCSI_In_DBx__1__SHIFT, 7\r
+.set SCSI_In_DBx__1__SLW, CYREG_PRT2_SLW\r
+.set SCSI_In_DBx__2__AG, CYREG_PRT2_AG\r
+.set SCSI_In_DBx__2__AMUX, CYREG_PRT2_AMUX\r
+.set SCSI_In_DBx__2__BIE, CYREG_PRT2_BIE\r
+.set SCSI_In_DBx__2__BIT_MASK, CYREG_PRT2_BIT_MASK\r
+.set SCSI_In_DBx__2__BYP, CYREG_PRT2_BYP\r
+.set SCSI_In_DBx__2__CTL, CYREG_PRT2_CTL\r
+.set SCSI_In_DBx__2__DM0, CYREG_PRT2_DM0\r
+.set SCSI_In_DBx__2__DM1, CYREG_PRT2_DM1\r
+.set SCSI_In_DBx__2__DM2, CYREG_PRT2_DM2\r
+.set SCSI_In_DBx__2__DR, CYREG_PRT2_DR\r
+.set SCSI_In_DBx__2__INP_DIS, CYREG_PRT2_INP_DIS\r
+.set SCSI_In_DBx__2__INTTYPE, CYREG_PICU2_INTTYPE6\r
+.set SCSI_In_DBx__2__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG\r
+.set SCSI_In_DBx__2__LCD_EN, CYREG_PRT2_LCD_EN\r
+.set SCSI_In_DBx__2__MASK, 0x40\r
+.set SCSI_In_DBx__2__PC, CYREG_PRT2_PC6\r
+.set SCSI_In_DBx__2__PORT, 2\r
+.set SCSI_In_DBx__2__PRT, CYREG_PRT2_PRT\r
+.set SCSI_In_DBx__2__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL\r
+.set SCSI_In_DBx__2__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN\r
+.set SCSI_In_DBx__2__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0\r
+.set SCSI_In_DBx__2__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1\r
+.set SCSI_In_DBx__2__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0\r
+.set SCSI_In_DBx__2__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1\r
+.set SCSI_In_DBx__2__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT\r
+.set SCSI_In_DBx__2__PS, CYREG_PRT2_PS\r
+.set SCSI_In_DBx__2__SHIFT, 6\r
+.set SCSI_In_DBx__2__SLW, CYREG_PRT2_SLW\r
+.set SCSI_In_DBx__3__AG, CYREG_PRT2_AG\r
+.set SCSI_In_DBx__3__AMUX, CYREG_PRT2_AMUX\r
+.set SCSI_In_DBx__3__BIE, CYREG_PRT2_BIE\r
+.set SCSI_In_DBx__3__BIT_MASK, CYREG_PRT2_BIT_MASK\r
+.set SCSI_In_DBx__3__BYP, CYREG_PRT2_BYP\r
+.set SCSI_In_DBx__3__CTL, CYREG_PRT2_CTL\r
+.set SCSI_In_DBx__3__DM0, CYREG_PRT2_DM0\r
+.set SCSI_In_DBx__3__DM1, CYREG_PRT2_DM1\r
+.set SCSI_In_DBx__3__DM2, CYREG_PRT2_DM2\r
+.set SCSI_In_DBx__3__DR, CYREG_PRT2_DR\r
+.set SCSI_In_DBx__3__INP_DIS, CYREG_PRT2_INP_DIS\r
+.set SCSI_In_DBx__3__INTTYPE, CYREG_PICU2_INTTYPE5\r
+.set SCSI_In_DBx__3__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG\r
+.set SCSI_In_DBx__3__LCD_EN, CYREG_PRT2_LCD_EN\r
+.set SCSI_In_DBx__3__MASK, 0x20\r
+.set SCSI_In_DBx__3__PC, CYREG_PRT2_PC5\r
+.set SCSI_In_DBx__3__PORT, 2\r
+.set SCSI_In_DBx__3__PRT, CYREG_PRT2_PRT\r
+.set SCSI_In_DBx__3__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL\r
+.set SCSI_In_DBx__3__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN\r
+.set SCSI_In_DBx__3__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0\r
+.set SCSI_In_DBx__3__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1\r
+.set SCSI_In_DBx__3__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0\r
+.set SCSI_In_DBx__3__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1\r
+.set SCSI_In_DBx__3__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT\r
+.set SCSI_In_DBx__3__PS, CYREG_PRT2_PS\r
+.set SCSI_In_DBx__3__SHIFT, 5\r
+.set SCSI_In_DBx__3__SLW, CYREG_PRT2_SLW\r
+.set SCSI_In_DBx__4__AG, CYREG_PRT2_AG\r
+.set SCSI_In_DBx__4__AMUX, CYREG_PRT2_AMUX\r
+.set SCSI_In_DBx__4__BIE, CYREG_PRT2_BIE\r
+.set SCSI_In_DBx__4__BIT_MASK, CYREG_PRT2_BIT_MASK\r
+.set SCSI_In_DBx__4__BYP, CYREG_PRT2_BYP\r
+.set SCSI_In_DBx__4__CTL, CYREG_PRT2_CTL\r
+.set SCSI_In_DBx__4__DM0, CYREG_PRT2_DM0\r
+.set SCSI_In_DBx__4__DM1, CYREG_PRT2_DM1\r
+.set SCSI_In_DBx__4__DM2, CYREG_PRT2_DM2\r
+.set SCSI_In_DBx__4__DR, CYREG_PRT2_DR\r
+.set SCSI_In_DBx__4__INP_DIS, CYREG_PRT2_INP_DIS\r
+.set SCSI_In_DBx__4__INTTYPE, CYREG_PICU2_INTTYPE4\r
+.set SCSI_In_DBx__4__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG\r
+.set SCSI_In_DBx__4__LCD_EN, CYREG_PRT2_LCD_EN\r
+.set SCSI_In_DBx__4__MASK, 0x10\r
+.set SCSI_In_DBx__4__PC, CYREG_PRT2_PC4\r
+.set SCSI_In_DBx__4__PORT, 2\r
+.set SCSI_In_DBx__4__PRT, CYREG_PRT2_PRT\r
+.set SCSI_In_DBx__4__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL\r
+.set SCSI_In_DBx__4__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN\r
+.set SCSI_In_DBx__4__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0\r
+.set SCSI_In_DBx__4__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1\r
+.set SCSI_In_DBx__4__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0\r
+.set SCSI_In_DBx__4__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1\r
+.set SCSI_In_DBx__4__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT\r
+.set SCSI_In_DBx__4__PS, CYREG_PRT2_PS\r
+.set SCSI_In_DBx__4__SHIFT, 4\r
+.set SCSI_In_DBx__4__SLW, CYREG_PRT2_SLW\r
+.set SCSI_In_DBx__5__AG, CYREG_PRT2_AG\r
+.set SCSI_In_DBx__5__AMUX, CYREG_PRT2_AMUX\r
+.set SCSI_In_DBx__5__BIE, CYREG_PRT2_BIE\r
+.set SCSI_In_DBx__5__BIT_MASK, CYREG_PRT2_BIT_MASK\r
+.set SCSI_In_DBx__5__BYP, CYREG_PRT2_BYP\r
+.set SCSI_In_DBx__5__CTL, CYREG_PRT2_CTL\r
+.set SCSI_In_DBx__5__DM0, CYREG_PRT2_DM0\r
+.set SCSI_In_DBx__5__DM1, CYREG_PRT2_DM1\r
+.set SCSI_In_DBx__5__DM2, CYREG_PRT2_DM2\r
+.set SCSI_In_DBx__5__DR, CYREG_PRT2_DR\r
+.set SCSI_In_DBx__5__INP_DIS, CYREG_PRT2_INP_DIS\r
+.set SCSI_In_DBx__5__INTTYPE, CYREG_PICU2_INTTYPE3\r
+.set SCSI_In_DBx__5__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG\r
+.set SCSI_In_DBx__5__LCD_EN, CYREG_PRT2_LCD_EN\r
+.set SCSI_In_DBx__5__MASK, 0x08\r
+.set SCSI_In_DBx__5__PC, CYREG_PRT2_PC3\r
+.set SCSI_In_DBx__5__PORT, 2\r
+.set SCSI_In_DBx__5__PRT, CYREG_PRT2_PRT\r
+.set SCSI_In_DBx__5__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL\r
+.set SCSI_In_DBx__5__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN\r
+.set SCSI_In_DBx__5__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0\r
+.set SCSI_In_DBx__5__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1\r
+.set SCSI_In_DBx__5__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0\r
+.set SCSI_In_DBx__5__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1\r
+.set SCSI_In_DBx__5__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT\r
+.set SCSI_In_DBx__5__PS, CYREG_PRT2_PS\r
+.set SCSI_In_DBx__5__SHIFT, 3\r
+.set SCSI_In_DBx__5__SLW, CYREG_PRT2_SLW\r
+.set SCSI_In_DBx__6__AG, CYREG_PRT2_AG\r
+.set SCSI_In_DBx__6__AMUX, CYREG_PRT2_AMUX\r
+.set SCSI_In_DBx__6__BIE, CYREG_PRT2_BIE\r
+.set SCSI_In_DBx__6__BIT_MASK, CYREG_PRT2_BIT_MASK\r
+.set SCSI_In_DBx__6__BYP, CYREG_PRT2_BYP\r
+.set SCSI_In_DBx__6__CTL, CYREG_PRT2_CTL\r
+.set SCSI_In_DBx__6__DM0, CYREG_PRT2_DM0\r
+.set SCSI_In_DBx__6__DM1, CYREG_PRT2_DM1\r
+.set SCSI_In_DBx__6__DM2, CYREG_PRT2_DM2\r
+.set SCSI_In_DBx__6__DR, CYREG_PRT2_DR\r
+.set SCSI_In_DBx__6__INP_DIS, CYREG_PRT2_INP_DIS\r
+.set SCSI_In_DBx__6__INTTYPE, CYREG_PICU2_INTTYPE2\r
+.set SCSI_In_DBx__6__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG\r
+.set SCSI_In_DBx__6__LCD_EN, CYREG_PRT2_LCD_EN\r
+.set SCSI_In_DBx__6__MASK, 0x04\r
+.set SCSI_In_DBx__6__PC, CYREG_PRT2_PC2\r
+.set SCSI_In_DBx__6__PORT, 2\r
+.set SCSI_In_DBx__6__PRT, CYREG_PRT2_PRT\r
+.set SCSI_In_DBx__6__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL\r
+.set SCSI_In_DBx__6__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN\r
+.set SCSI_In_DBx__6__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0\r
+.set SCSI_In_DBx__6__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1\r
+.set SCSI_In_DBx__6__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0\r
+.set SCSI_In_DBx__6__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1\r
+.set SCSI_In_DBx__6__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT\r
+.set SCSI_In_DBx__6__PS, CYREG_PRT2_PS\r
+.set SCSI_In_DBx__6__SHIFT, 2\r
+.set SCSI_In_DBx__6__SLW, CYREG_PRT2_SLW\r
+.set SCSI_In_DBx__7__AG, CYREG_PRT2_AG\r
+.set SCSI_In_DBx__7__AMUX, CYREG_PRT2_AMUX\r
+.set SCSI_In_DBx__7__BIE, CYREG_PRT2_BIE\r
+.set SCSI_In_DBx__7__BIT_MASK, CYREG_PRT2_BIT_MASK\r
+.set SCSI_In_DBx__7__BYP, CYREG_PRT2_BYP\r
+.set SCSI_In_DBx__7__CTL, CYREG_PRT2_CTL\r
+.set SCSI_In_DBx__7__DM0, CYREG_PRT2_DM0\r
+.set SCSI_In_DBx__7__DM1, CYREG_PRT2_DM1\r
+.set SCSI_In_DBx__7__DM2, CYREG_PRT2_DM2\r
+.set SCSI_In_DBx__7__DR, CYREG_PRT2_DR\r
+.set SCSI_In_DBx__7__INP_DIS, CYREG_PRT2_INP_DIS\r
+.set SCSI_In_DBx__7__INTTYPE, CYREG_PICU2_INTTYPE1\r
+.set SCSI_In_DBx__7__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG\r
+.set SCSI_In_DBx__7__LCD_EN, CYREG_PRT2_LCD_EN\r
+.set SCSI_In_DBx__7__MASK, 0x02\r
+.set SCSI_In_DBx__7__PC, CYREG_PRT2_PC1\r
+.set SCSI_In_DBx__7__PORT, 2\r
+.set SCSI_In_DBx__7__PRT, CYREG_PRT2_PRT\r
+.set SCSI_In_DBx__7__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL\r
+.set SCSI_In_DBx__7__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN\r
+.set SCSI_In_DBx__7__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0\r
+.set SCSI_In_DBx__7__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1\r
+.set SCSI_In_DBx__7__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0\r
+.set SCSI_In_DBx__7__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1\r
+.set SCSI_In_DBx__7__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT\r
+.set SCSI_In_DBx__7__PS, CYREG_PRT2_PS\r
+.set SCSI_In_DBx__7__SHIFT, 1\r
+.set SCSI_In_DBx__7__SLW, CYREG_PRT2_SLW\r
+.set SCSI_In_DBx__DB0__AG, CYREG_PRT12_AG\r
+.set SCSI_In_DBx__DB0__BIE, CYREG_PRT12_BIE\r
+.set SCSI_In_DBx__DB0__BIT_MASK, CYREG_PRT12_BIT_MASK\r
+.set SCSI_In_DBx__DB0__BYP, CYREG_PRT12_BYP\r
+.set SCSI_In_DBx__DB0__DM0, CYREG_PRT12_DM0\r
+.set SCSI_In_DBx__DB0__DM1, CYREG_PRT12_DM1\r
+.set SCSI_In_DBx__DB0__DM2, CYREG_PRT12_DM2\r
+.set SCSI_In_DBx__DB0__DR, CYREG_PRT12_DR\r
+.set SCSI_In_DBx__DB0__INP_DIS, CYREG_PRT12_INP_DIS\r
+.set SCSI_In_DBx__DB0__INTTYPE, CYREG_PICU12_INTTYPE4\r
+.set SCSI_In_DBx__DB0__MASK, 0x10\r
+.set SCSI_In_DBx__DB0__PC, CYREG_PRT12_PC4\r
+.set SCSI_In_DBx__DB0__PORT, 12\r
+.set SCSI_In_DBx__DB0__PRT, CYREG_PRT12_PRT\r
+.set SCSI_In_DBx__DB0__PRTDSI__DBL_SYNC_IN, CYREG_PRT12_DBL_SYNC_IN\r
+.set SCSI_In_DBx__DB0__PRTDSI__OE_SEL0, CYREG_PRT12_OE_SEL0\r
+.set SCSI_In_DBx__DB0__PRTDSI__OE_SEL1, CYREG_PRT12_OE_SEL1\r
+.set SCSI_In_DBx__DB0__PRTDSI__OUT_SEL0, CYREG_PRT12_OUT_SEL0\r
+.set SCSI_In_DBx__DB0__PRTDSI__OUT_SEL1, CYREG_PRT12_OUT_SEL1\r
+.set SCSI_In_DBx__DB0__PRTDSI__SYNC_OUT, CYREG_PRT12_SYNC_OUT\r
+.set SCSI_In_DBx__DB0__PS, CYREG_PRT12_PS\r
+.set SCSI_In_DBx__DB0__SHIFT, 4\r
+.set SCSI_In_DBx__DB0__SIO_CFG, CYREG_PRT12_SIO_CFG\r
+.set SCSI_In_DBx__DB0__SIO_DIFF, CYREG_PRT12_SIO_DIFF\r
+.set SCSI_In_DBx__DB0__SIO_HYST_EN, CYREG_PRT12_SIO_HYST_EN\r
+.set SCSI_In_DBx__DB0__SIO_REG_HIFREQ, CYREG_PRT12_SIO_REG_HIFREQ\r
+.set SCSI_In_DBx__DB0__SLW, CYREG_PRT12_SLW\r
+.set SCSI_In_DBx__DB1__AG, CYREG_PRT2_AG\r
+.set SCSI_In_DBx__DB1__AMUX, CYREG_PRT2_AMUX\r
+.set SCSI_In_DBx__DB1__BIE, CYREG_PRT2_BIE\r
+.set SCSI_In_DBx__DB1__BIT_MASK, CYREG_PRT2_BIT_MASK\r
+.set SCSI_In_DBx__DB1__BYP, CYREG_PRT2_BYP\r
+.set SCSI_In_DBx__DB1__CTL, CYREG_PRT2_CTL\r
+.set SCSI_In_DBx__DB1__DM0, CYREG_PRT2_DM0\r
+.set SCSI_In_DBx__DB1__DM1, CYREG_PRT2_DM1\r
+.set SCSI_In_DBx__DB1__DM2, CYREG_PRT2_DM2\r
+.set SCSI_In_DBx__DB1__DR, CYREG_PRT2_DR\r
+.set SCSI_In_DBx__DB1__INP_DIS, CYREG_PRT2_INP_DIS\r
+.set SCSI_In_DBx__DB1__INTTYPE, CYREG_PICU2_INTTYPE7\r
+.set SCSI_In_DBx__DB1__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG\r
+.set SCSI_In_DBx__DB1__LCD_EN, CYREG_PRT2_LCD_EN\r
+.set SCSI_In_DBx__DB1__MASK, 0x80\r
+.set SCSI_In_DBx__DB1__PC, CYREG_PRT2_PC7\r
+.set SCSI_In_DBx__DB1__PORT, 2\r
+.set SCSI_In_DBx__DB1__PRT, CYREG_PRT2_PRT\r
+.set SCSI_In_DBx__DB1__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL\r
+.set SCSI_In_DBx__DB1__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN\r
+.set SCSI_In_DBx__DB1__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0\r
+.set SCSI_In_DBx__DB1__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1\r
+.set SCSI_In_DBx__DB1__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0\r
+.set SCSI_In_DBx__DB1__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1\r
+.set SCSI_In_DBx__DB1__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT\r
+.set SCSI_In_DBx__DB1__PS, CYREG_PRT2_PS\r
+.set SCSI_In_DBx__DB1__SHIFT, 7\r
+.set SCSI_In_DBx__DB1__SLW, CYREG_PRT2_SLW\r
+.set SCSI_In_DBx__DB2__AG, CYREG_PRT2_AG\r
+.set SCSI_In_DBx__DB2__AMUX, CYREG_PRT2_AMUX\r
+.set SCSI_In_DBx__DB2__BIE, CYREG_PRT2_BIE\r
+.set SCSI_In_DBx__DB2__BIT_MASK, CYREG_PRT2_BIT_MASK\r
+.set SCSI_In_DBx__DB2__BYP, CYREG_PRT2_BYP\r
+.set SCSI_In_DBx__DB2__CTL, CYREG_PRT2_CTL\r
+.set SCSI_In_DBx__DB2__DM0, CYREG_PRT2_DM0\r
+.set SCSI_In_DBx__DB2__DM1, CYREG_PRT2_DM1\r
+.set SCSI_In_DBx__DB2__DM2, CYREG_PRT2_DM2\r
+.set SCSI_In_DBx__DB2__DR, CYREG_PRT2_DR\r
+.set SCSI_In_DBx__DB2__INP_DIS, CYREG_PRT2_INP_DIS\r
+.set SCSI_In_DBx__DB2__INTTYPE, CYREG_PICU2_INTTYPE6\r
+.set SCSI_In_DBx__DB2__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG\r
+.set SCSI_In_DBx__DB2__LCD_EN, CYREG_PRT2_LCD_EN\r
+.set SCSI_In_DBx__DB2__MASK, 0x40\r
+.set SCSI_In_DBx__DB2__PC, CYREG_PRT2_PC6\r
+.set SCSI_In_DBx__DB2__PORT, 2\r
+.set SCSI_In_DBx__DB2__PRT, CYREG_PRT2_PRT\r
+.set SCSI_In_DBx__DB2__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL\r
+.set SCSI_In_DBx__DB2__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN\r
+.set SCSI_In_DBx__DB2__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0\r
+.set SCSI_In_DBx__DB2__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1\r
+.set SCSI_In_DBx__DB2__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0\r
+.set SCSI_In_DBx__DB2__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1\r
+.set SCSI_In_DBx__DB2__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT\r
+.set SCSI_In_DBx__DB2__PS, CYREG_PRT2_PS\r
+.set SCSI_In_DBx__DB2__SHIFT, 6\r
+.set SCSI_In_DBx__DB2__SLW, CYREG_PRT2_SLW\r
+.set SCSI_In_DBx__DB3__AG, CYREG_PRT2_AG\r
+.set SCSI_In_DBx__DB3__AMUX, CYREG_PRT2_AMUX\r
+.set SCSI_In_DBx__DB3__BIE, CYREG_PRT2_BIE\r
+.set SCSI_In_DBx__DB3__BIT_MASK, CYREG_PRT2_BIT_MASK\r
+.set SCSI_In_DBx__DB3__BYP, CYREG_PRT2_BYP\r
+.set SCSI_In_DBx__DB3__CTL, CYREG_PRT2_CTL\r
+.set SCSI_In_DBx__DB3__DM0, CYREG_PRT2_DM0\r
+.set SCSI_In_DBx__DB3__DM1, CYREG_PRT2_DM1\r
+.set SCSI_In_DBx__DB3__DM2, CYREG_PRT2_DM2\r
+.set SCSI_In_DBx__DB3__DR, CYREG_PRT2_DR\r
+.set SCSI_In_DBx__DB3__INP_DIS, CYREG_PRT2_INP_DIS\r
+.set SCSI_In_DBx__DB3__INTTYPE, CYREG_PICU2_INTTYPE5\r
+.set SCSI_In_DBx__DB3__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG\r
+.set SCSI_In_DBx__DB3__LCD_EN, CYREG_PRT2_LCD_EN\r
+.set SCSI_In_DBx__DB3__MASK, 0x20\r
+.set SCSI_In_DBx__DB3__PC, CYREG_PRT2_PC5\r
+.set SCSI_In_DBx__DB3__PORT, 2\r
+.set SCSI_In_DBx__DB3__PRT, CYREG_PRT2_PRT\r
+.set SCSI_In_DBx__DB3__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL\r
+.set SCSI_In_DBx__DB3__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN\r
+.set SCSI_In_DBx__DB3__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0\r
+.set SCSI_In_DBx__DB3__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1\r
+.set SCSI_In_DBx__DB3__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0\r
+.set SCSI_In_DBx__DB3__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1\r
+.set SCSI_In_DBx__DB3__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT\r
+.set SCSI_In_DBx__DB3__PS, CYREG_PRT2_PS\r
+.set SCSI_In_DBx__DB3__SHIFT, 5\r
+.set SCSI_In_DBx__DB3__SLW, CYREG_PRT2_SLW\r
+.set SCSI_In_DBx__DB4__AG, CYREG_PRT2_AG\r
+.set SCSI_In_DBx__DB4__AMUX, CYREG_PRT2_AMUX\r
+.set SCSI_In_DBx__DB4__BIE, CYREG_PRT2_BIE\r
+.set SCSI_In_DBx__DB4__BIT_MASK, CYREG_PRT2_BIT_MASK\r
+.set SCSI_In_DBx__DB4__BYP, CYREG_PRT2_BYP\r
+.set SCSI_In_DBx__DB4__CTL, CYREG_PRT2_CTL\r
+.set SCSI_In_DBx__DB4__DM0, CYREG_PRT2_DM0\r
+.set SCSI_In_DBx__DB4__DM1, CYREG_PRT2_DM1\r
+.set SCSI_In_DBx__DB4__DM2, CYREG_PRT2_DM2\r
+.set SCSI_In_DBx__DB4__DR, CYREG_PRT2_DR\r
+.set SCSI_In_DBx__DB4__INP_DIS, CYREG_PRT2_INP_DIS\r
+.set SCSI_In_DBx__DB4__INTTYPE, CYREG_PICU2_INTTYPE4\r
+.set SCSI_In_DBx__DB4__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG\r
+.set SCSI_In_DBx__DB4__LCD_EN, CYREG_PRT2_LCD_EN\r
+.set SCSI_In_DBx__DB4__MASK, 0x10\r
+.set SCSI_In_DBx__DB4__PC, CYREG_PRT2_PC4\r
+.set SCSI_In_DBx__DB4__PORT, 2\r
+.set SCSI_In_DBx__DB4__PRT, CYREG_PRT2_PRT\r
+.set SCSI_In_DBx__DB4__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL\r
+.set SCSI_In_DBx__DB4__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN\r
+.set SCSI_In_DBx__DB4__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0\r
+.set SCSI_In_DBx__DB4__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1\r
+.set SCSI_In_DBx__DB4__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0\r
+.set SCSI_In_DBx__DB4__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1\r
+.set SCSI_In_DBx__DB4__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT\r
+.set SCSI_In_DBx__DB4__PS, CYREG_PRT2_PS\r
+.set SCSI_In_DBx__DB4__SHIFT, 4\r
+.set SCSI_In_DBx__DB4__SLW, CYREG_PRT2_SLW\r
+.set SCSI_In_DBx__DB5__AG, CYREG_PRT2_AG\r
+.set SCSI_In_DBx__DB5__AMUX, CYREG_PRT2_AMUX\r
+.set SCSI_In_DBx__DB5__BIE, CYREG_PRT2_BIE\r
+.set SCSI_In_DBx__DB5__BIT_MASK, CYREG_PRT2_BIT_MASK\r
+.set SCSI_In_DBx__DB5__BYP, CYREG_PRT2_BYP\r
+.set SCSI_In_DBx__DB5__CTL, CYREG_PRT2_CTL\r
+.set SCSI_In_DBx__DB5__DM0, CYREG_PRT2_DM0\r
+.set SCSI_In_DBx__DB5__DM1, CYREG_PRT2_DM1\r
+.set SCSI_In_DBx__DB5__DM2, CYREG_PRT2_DM2\r
+.set SCSI_In_DBx__DB5__DR, CYREG_PRT2_DR\r
+.set SCSI_In_DBx__DB5__INP_DIS, CYREG_PRT2_INP_DIS\r
+.set SCSI_In_DBx__DB5__INTTYPE, CYREG_PICU2_INTTYPE3\r
+.set SCSI_In_DBx__DB5__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG\r
+.set SCSI_In_DBx__DB5__LCD_EN, CYREG_PRT2_LCD_EN\r
+.set SCSI_In_DBx__DB5__MASK, 0x08\r
+.set SCSI_In_DBx__DB5__PC, CYREG_PRT2_PC3\r
+.set SCSI_In_DBx__DB5__PORT, 2\r
+.set SCSI_In_DBx__DB5__PRT, CYREG_PRT2_PRT\r
+.set SCSI_In_DBx__DB5__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL\r
+.set SCSI_In_DBx__DB5__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN\r
+.set SCSI_In_DBx__DB5__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0\r
+.set SCSI_In_DBx__DB5__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1\r
+.set SCSI_In_DBx__DB5__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0\r
+.set SCSI_In_DBx__DB5__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1\r
+.set SCSI_In_DBx__DB5__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT\r
+.set SCSI_In_DBx__DB5__PS, CYREG_PRT2_PS\r
+.set SCSI_In_DBx__DB5__SHIFT, 3\r
+.set SCSI_In_DBx__DB5__SLW, CYREG_PRT2_SLW\r
+.set SCSI_In_DBx__DB6__AG, CYREG_PRT2_AG\r
+.set SCSI_In_DBx__DB6__AMUX, CYREG_PRT2_AMUX\r
+.set SCSI_In_DBx__DB6__BIE, CYREG_PRT2_BIE\r
+.set SCSI_In_DBx__DB6__BIT_MASK, CYREG_PRT2_BIT_MASK\r
+.set SCSI_In_DBx__DB6__BYP, CYREG_PRT2_BYP\r
+.set SCSI_In_DBx__DB6__CTL, CYREG_PRT2_CTL\r
+.set SCSI_In_DBx__DB6__DM0, CYREG_PRT2_DM0\r
+.set SCSI_In_DBx__DB6__DM1, CYREG_PRT2_DM1\r
+.set SCSI_In_DBx__DB6__DM2, CYREG_PRT2_DM2\r
+.set SCSI_In_DBx__DB6__DR, CYREG_PRT2_DR\r
+.set SCSI_In_DBx__DB6__INP_DIS, CYREG_PRT2_INP_DIS\r
+.set SCSI_In_DBx__DB6__INTTYPE, CYREG_PICU2_INTTYPE2\r
+.set SCSI_In_DBx__DB6__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG\r
+.set SCSI_In_DBx__DB6__LCD_EN, CYREG_PRT2_LCD_EN\r
+.set SCSI_In_DBx__DB6__MASK, 0x04\r
+.set SCSI_In_DBx__DB6__PC, CYREG_PRT2_PC2\r
+.set SCSI_In_DBx__DB6__PORT, 2\r
+.set SCSI_In_DBx__DB6__PRT, CYREG_PRT2_PRT\r
+.set SCSI_In_DBx__DB6__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL\r
+.set SCSI_In_DBx__DB6__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN\r
+.set SCSI_In_DBx__DB6__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0\r
+.set SCSI_In_DBx__DB6__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1\r
+.set SCSI_In_DBx__DB6__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0\r
+.set SCSI_In_DBx__DB6__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1\r
+.set SCSI_In_DBx__DB6__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT\r
+.set SCSI_In_DBx__DB6__PS, CYREG_PRT2_PS\r
+.set SCSI_In_DBx__DB6__SHIFT, 2\r
+.set SCSI_In_DBx__DB6__SLW, CYREG_PRT2_SLW\r
+.set SCSI_In_DBx__DB7__AG, CYREG_PRT2_AG\r
+.set SCSI_In_DBx__DB7__AMUX, CYREG_PRT2_AMUX\r
+.set SCSI_In_DBx__DB7__BIE, CYREG_PRT2_BIE\r
+.set SCSI_In_DBx__DB7__BIT_MASK, CYREG_PRT2_BIT_MASK\r
+.set SCSI_In_DBx__DB7__BYP, CYREG_PRT2_BYP\r
+.set SCSI_In_DBx__DB7__CTL, CYREG_PRT2_CTL\r
+.set SCSI_In_DBx__DB7__DM0, CYREG_PRT2_DM0\r
+.set SCSI_In_DBx__DB7__DM1, CYREG_PRT2_DM1\r
+.set SCSI_In_DBx__DB7__DM2, CYREG_PRT2_DM2\r
+.set SCSI_In_DBx__DB7__DR, CYREG_PRT2_DR\r
+.set SCSI_In_DBx__DB7__INP_DIS, CYREG_PRT2_INP_DIS\r
+.set SCSI_In_DBx__DB7__INTTYPE, CYREG_PICU2_INTTYPE1\r
+.set SCSI_In_DBx__DB7__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG\r
+.set SCSI_In_DBx__DB7__LCD_EN, CYREG_PRT2_LCD_EN\r
+.set SCSI_In_DBx__DB7__MASK, 0x02\r
+.set SCSI_In_DBx__DB7__PC, CYREG_PRT2_PC1\r
+.set SCSI_In_DBx__DB7__PORT, 2\r
+.set SCSI_In_DBx__DB7__PRT, CYREG_PRT2_PRT\r
+.set SCSI_In_DBx__DB7__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL\r
+.set SCSI_In_DBx__DB7__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN\r
+.set SCSI_In_DBx__DB7__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0\r
+.set SCSI_In_DBx__DB7__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1\r
+.set SCSI_In_DBx__DB7__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0\r
+.set SCSI_In_DBx__DB7__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1\r
+.set SCSI_In_DBx__DB7__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT\r
+.set SCSI_In_DBx__DB7__PS, CYREG_PRT2_PS\r
+.set SCSI_In_DBx__DB7__SHIFT, 1\r
+.set SCSI_In_DBx__DB7__SLW, CYREG_PRT2_SLW\r
 \r
 /* SCSI_Noise */\r
 .set SCSI_Noise__0__AG, CYREG_PRT12_AG\r
@@ -2774,6 +1165,1772 @@
 .set SCSI_Noise__SEL__SHIFT, 0\r
 .set SCSI_Noise__SEL__SLW, CYREG_PRT5_SLW\r
 \r
+/* SCSI_Out */\r
+.set SCSI_Out__0__AG, CYREG_PRT4_AG\r
+.set SCSI_Out__0__AMUX, CYREG_PRT4_AMUX\r
+.set SCSI_Out__0__BIE, CYREG_PRT4_BIE\r
+.set SCSI_Out__0__BIT_MASK, CYREG_PRT4_BIT_MASK\r
+.set SCSI_Out__0__BYP, CYREG_PRT4_BYP\r
+.set SCSI_Out__0__CTL, CYREG_PRT4_CTL\r
+.set SCSI_Out__0__DM0, CYREG_PRT4_DM0\r
+.set SCSI_Out__0__DM1, CYREG_PRT4_DM1\r
+.set SCSI_Out__0__DM2, CYREG_PRT4_DM2\r
+.set SCSI_Out__0__DR, CYREG_PRT4_DR\r
+.set SCSI_Out__0__INP_DIS, CYREG_PRT4_INP_DIS\r
+.set SCSI_Out__0__INTTYPE, CYREG_PICU4_INTTYPE3\r
+.set SCSI_Out__0__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG\r
+.set SCSI_Out__0__LCD_EN, CYREG_PRT4_LCD_EN\r
+.set SCSI_Out__0__MASK, 0x08\r
+.set SCSI_Out__0__PC, CYREG_PRT4_PC3\r
+.set SCSI_Out__0__PORT, 4\r
+.set SCSI_Out__0__PRT, CYREG_PRT4_PRT\r
+.set SCSI_Out__0__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL\r
+.set SCSI_Out__0__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN\r
+.set SCSI_Out__0__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0\r
+.set SCSI_Out__0__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1\r
+.set SCSI_Out__0__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0\r
+.set SCSI_Out__0__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1\r
+.set SCSI_Out__0__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT\r
+.set SCSI_Out__0__PS, CYREG_PRT4_PS\r
+.set SCSI_Out__0__SHIFT, 3\r
+.set SCSI_Out__0__SLW, CYREG_PRT4_SLW\r
+.set SCSI_Out__1__AG, CYREG_PRT4_AG\r
+.set SCSI_Out__1__AMUX, CYREG_PRT4_AMUX\r
+.set SCSI_Out__1__BIE, CYREG_PRT4_BIE\r
+.set SCSI_Out__1__BIT_MASK, CYREG_PRT4_BIT_MASK\r
+.set SCSI_Out__1__BYP, CYREG_PRT4_BYP\r
+.set SCSI_Out__1__CTL, CYREG_PRT4_CTL\r
+.set SCSI_Out__1__DM0, CYREG_PRT4_DM0\r
+.set SCSI_Out__1__DM1, CYREG_PRT4_DM1\r
+.set SCSI_Out__1__DM2, CYREG_PRT4_DM2\r
+.set SCSI_Out__1__DR, CYREG_PRT4_DR\r
+.set SCSI_Out__1__INP_DIS, CYREG_PRT4_INP_DIS\r
+.set SCSI_Out__1__INTTYPE, CYREG_PICU4_INTTYPE2\r
+.set SCSI_Out__1__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG\r
+.set SCSI_Out__1__LCD_EN, CYREG_PRT4_LCD_EN\r
+.set SCSI_Out__1__MASK, 0x04\r
+.set SCSI_Out__1__PC, CYREG_PRT4_PC2\r
+.set SCSI_Out__1__PORT, 4\r
+.set SCSI_Out__1__PRT, CYREG_PRT4_PRT\r
+.set SCSI_Out__1__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL\r
+.set SCSI_Out__1__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN\r
+.set SCSI_Out__1__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0\r
+.set SCSI_Out__1__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1\r
+.set SCSI_Out__1__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0\r
+.set SCSI_Out__1__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1\r
+.set SCSI_Out__1__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT\r
+.set SCSI_Out__1__PS, CYREG_PRT4_PS\r
+.set SCSI_Out__1__SHIFT, 2\r
+.set SCSI_Out__1__SLW, CYREG_PRT4_SLW\r
+.set SCSI_Out__2__AG, CYREG_PRT0_AG\r
+.set SCSI_Out__2__AMUX, CYREG_PRT0_AMUX\r
+.set SCSI_Out__2__BIE, CYREG_PRT0_BIE\r
+.set SCSI_Out__2__BIT_MASK, CYREG_PRT0_BIT_MASK\r
+.set SCSI_Out__2__BYP, CYREG_PRT0_BYP\r
+.set SCSI_Out__2__CTL, CYREG_PRT0_CTL\r
+.set SCSI_Out__2__DM0, CYREG_PRT0_DM0\r
+.set SCSI_Out__2__DM1, CYREG_PRT0_DM1\r
+.set SCSI_Out__2__DM2, CYREG_PRT0_DM2\r
+.set SCSI_Out__2__DR, CYREG_PRT0_DR\r
+.set SCSI_Out__2__INP_DIS, CYREG_PRT0_INP_DIS\r
+.set SCSI_Out__2__INTTYPE, CYREG_PICU0_INTTYPE7\r
+.set SCSI_Out__2__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG\r
+.set SCSI_Out__2__LCD_EN, CYREG_PRT0_LCD_EN\r
+.set SCSI_Out__2__MASK, 0x80\r
+.set SCSI_Out__2__PC, CYREG_PRT0_PC7\r
+.set SCSI_Out__2__PORT, 0\r
+.set SCSI_Out__2__PRT, CYREG_PRT0_PRT\r
+.set SCSI_Out__2__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL\r
+.set SCSI_Out__2__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN\r
+.set SCSI_Out__2__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0\r
+.set SCSI_Out__2__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1\r
+.set SCSI_Out__2__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0\r
+.set SCSI_Out__2__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1\r
+.set SCSI_Out__2__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT\r
+.set SCSI_Out__2__PS, CYREG_PRT0_PS\r
+.set SCSI_Out__2__SHIFT, 7\r
+.set SCSI_Out__2__SLW, CYREG_PRT0_SLW\r
+.set SCSI_Out__3__AG, CYREG_PRT0_AG\r
+.set SCSI_Out__3__AMUX, CYREG_PRT0_AMUX\r
+.set SCSI_Out__3__BIE, CYREG_PRT0_BIE\r
+.set SCSI_Out__3__BIT_MASK, CYREG_PRT0_BIT_MASK\r
+.set SCSI_Out__3__BYP, CYREG_PRT0_BYP\r
+.set SCSI_Out__3__CTL, CYREG_PRT0_CTL\r
+.set SCSI_Out__3__DM0, CYREG_PRT0_DM0\r
+.set SCSI_Out__3__DM1, CYREG_PRT0_DM1\r
+.set SCSI_Out__3__DM2, CYREG_PRT0_DM2\r
+.set SCSI_Out__3__DR, CYREG_PRT0_DR\r
+.set SCSI_Out__3__INP_DIS, CYREG_PRT0_INP_DIS\r
+.set SCSI_Out__3__INTTYPE, CYREG_PICU0_INTTYPE6\r
+.set SCSI_Out__3__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG\r
+.set SCSI_Out__3__LCD_EN, CYREG_PRT0_LCD_EN\r
+.set SCSI_Out__3__MASK, 0x40\r
+.set SCSI_Out__3__PC, CYREG_PRT0_PC6\r
+.set SCSI_Out__3__PORT, 0\r
+.set SCSI_Out__3__PRT, CYREG_PRT0_PRT\r
+.set SCSI_Out__3__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL\r
+.set SCSI_Out__3__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN\r
+.set SCSI_Out__3__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0\r
+.set SCSI_Out__3__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1\r
+.set SCSI_Out__3__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0\r
+.set SCSI_Out__3__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1\r
+.set SCSI_Out__3__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT\r
+.set SCSI_Out__3__PS, CYREG_PRT0_PS\r
+.set SCSI_Out__3__SHIFT, 6\r
+.set SCSI_Out__3__SLW, CYREG_PRT0_SLW\r
+.set SCSI_Out__4__AG, CYREG_PRT0_AG\r
+.set SCSI_Out__4__AMUX, CYREG_PRT0_AMUX\r
+.set SCSI_Out__4__BIE, CYREG_PRT0_BIE\r
+.set SCSI_Out__4__BIT_MASK, CYREG_PRT0_BIT_MASK\r
+.set SCSI_Out__4__BYP, CYREG_PRT0_BYP\r
+.set SCSI_Out__4__CTL, CYREG_PRT0_CTL\r
+.set SCSI_Out__4__DM0, CYREG_PRT0_DM0\r
+.set SCSI_Out__4__DM1, CYREG_PRT0_DM1\r
+.set SCSI_Out__4__DM2, CYREG_PRT0_DM2\r
+.set SCSI_Out__4__DR, CYREG_PRT0_DR\r
+.set SCSI_Out__4__INP_DIS, CYREG_PRT0_INP_DIS\r
+.set SCSI_Out__4__INTTYPE, CYREG_PICU0_INTTYPE5\r
+.set SCSI_Out__4__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG\r
+.set SCSI_Out__4__LCD_EN, CYREG_PRT0_LCD_EN\r
+.set SCSI_Out__4__MASK, 0x20\r
+.set SCSI_Out__4__PC, CYREG_PRT0_PC5\r
+.set SCSI_Out__4__PORT, 0\r
+.set SCSI_Out__4__PRT, CYREG_PRT0_PRT\r
+.set SCSI_Out__4__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL\r
+.set SCSI_Out__4__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN\r
+.set SCSI_Out__4__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0\r
+.set SCSI_Out__4__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1\r
+.set SCSI_Out__4__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0\r
+.set SCSI_Out__4__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1\r
+.set SCSI_Out__4__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT\r
+.set SCSI_Out__4__PS, CYREG_PRT0_PS\r
+.set SCSI_Out__4__SHIFT, 5\r
+.set SCSI_Out__4__SLW, CYREG_PRT0_SLW\r
+.set SCSI_Out__5__AG, CYREG_PRT0_AG\r
+.set SCSI_Out__5__AMUX, CYREG_PRT0_AMUX\r
+.set SCSI_Out__5__BIE, CYREG_PRT0_BIE\r
+.set SCSI_Out__5__BIT_MASK, CYREG_PRT0_BIT_MASK\r
+.set SCSI_Out__5__BYP, CYREG_PRT0_BYP\r
+.set SCSI_Out__5__CTL, CYREG_PRT0_CTL\r
+.set SCSI_Out__5__DM0, CYREG_PRT0_DM0\r
+.set SCSI_Out__5__DM1, CYREG_PRT0_DM1\r
+.set SCSI_Out__5__DM2, CYREG_PRT0_DM2\r
+.set SCSI_Out__5__DR, CYREG_PRT0_DR\r
+.set SCSI_Out__5__INP_DIS, CYREG_PRT0_INP_DIS\r
+.set SCSI_Out__5__INTTYPE, CYREG_PICU0_INTTYPE4\r
+.set SCSI_Out__5__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG\r
+.set SCSI_Out__5__LCD_EN, CYREG_PRT0_LCD_EN\r
+.set SCSI_Out__5__MASK, 0x10\r
+.set SCSI_Out__5__PC, CYREG_PRT0_PC4\r
+.set SCSI_Out__5__PORT, 0\r
+.set SCSI_Out__5__PRT, CYREG_PRT0_PRT\r
+.set SCSI_Out__5__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL\r
+.set SCSI_Out__5__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN\r
+.set SCSI_Out__5__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0\r
+.set SCSI_Out__5__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1\r
+.set SCSI_Out__5__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0\r
+.set SCSI_Out__5__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1\r
+.set SCSI_Out__5__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT\r
+.set SCSI_Out__5__PS, CYREG_PRT0_PS\r
+.set SCSI_Out__5__SHIFT, 4\r
+.set SCSI_Out__5__SLW, CYREG_PRT0_SLW\r
+.set SCSI_Out__6__AG, CYREG_PRT0_AG\r
+.set SCSI_Out__6__AMUX, CYREG_PRT0_AMUX\r
+.set SCSI_Out__6__BIE, CYREG_PRT0_BIE\r
+.set SCSI_Out__6__BIT_MASK, CYREG_PRT0_BIT_MASK\r
+.set SCSI_Out__6__BYP, CYREG_PRT0_BYP\r
+.set SCSI_Out__6__CTL, CYREG_PRT0_CTL\r
+.set SCSI_Out__6__DM0, CYREG_PRT0_DM0\r
+.set SCSI_Out__6__DM1, CYREG_PRT0_DM1\r
+.set SCSI_Out__6__DM2, CYREG_PRT0_DM2\r
+.set SCSI_Out__6__DR, CYREG_PRT0_DR\r
+.set SCSI_Out__6__INP_DIS, CYREG_PRT0_INP_DIS\r
+.set SCSI_Out__6__INTTYPE, CYREG_PICU0_INTTYPE3\r
+.set SCSI_Out__6__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG\r
+.set SCSI_Out__6__LCD_EN, CYREG_PRT0_LCD_EN\r
+.set SCSI_Out__6__MASK, 0x08\r
+.set SCSI_Out__6__PC, CYREG_PRT0_PC3\r
+.set SCSI_Out__6__PORT, 0\r
+.set SCSI_Out__6__PRT, CYREG_PRT0_PRT\r
+.set SCSI_Out__6__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL\r
+.set SCSI_Out__6__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN\r
+.set SCSI_Out__6__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0\r
+.set SCSI_Out__6__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1\r
+.set SCSI_Out__6__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0\r
+.set SCSI_Out__6__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1\r
+.set SCSI_Out__6__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT\r
+.set SCSI_Out__6__PS, CYREG_PRT0_PS\r
+.set SCSI_Out__6__SHIFT, 3\r
+.set SCSI_Out__6__SLW, CYREG_PRT0_SLW\r
+.set SCSI_Out__7__AG, CYREG_PRT0_AG\r
+.set SCSI_Out__7__AMUX, CYREG_PRT0_AMUX\r
+.set SCSI_Out__7__BIE, CYREG_PRT0_BIE\r
+.set SCSI_Out__7__BIT_MASK, CYREG_PRT0_BIT_MASK\r
+.set SCSI_Out__7__BYP, CYREG_PRT0_BYP\r
+.set SCSI_Out__7__CTL, CYREG_PRT0_CTL\r
+.set SCSI_Out__7__DM0, CYREG_PRT0_DM0\r
+.set SCSI_Out__7__DM1, CYREG_PRT0_DM1\r
+.set SCSI_Out__7__DM2, CYREG_PRT0_DM2\r
+.set SCSI_Out__7__DR, CYREG_PRT0_DR\r
+.set SCSI_Out__7__INP_DIS, CYREG_PRT0_INP_DIS\r
+.set SCSI_Out__7__INTTYPE, CYREG_PICU0_INTTYPE2\r
+.set SCSI_Out__7__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG\r
+.set SCSI_Out__7__LCD_EN, CYREG_PRT0_LCD_EN\r
+.set SCSI_Out__7__MASK, 0x04\r
+.set SCSI_Out__7__PC, CYREG_PRT0_PC2\r
+.set SCSI_Out__7__PORT, 0\r
+.set SCSI_Out__7__PRT, CYREG_PRT0_PRT\r
+.set SCSI_Out__7__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL\r
+.set SCSI_Out__7__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN\r
+.set SCSI_Out__7__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0\r
+.set SCSI_Out__7__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1\r
+.set SCSI_Out__7__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0\r
+.set SCSI_Out__7__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1\r
+.set SCSI_Out__7__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT\r
+.set SCSI_Out__7__PS, CYREG_PRT0_PS\r
+.set SCSI_Out__7__SHIFT, 2\r
+.set SCSI_Out__7__SLW, CYREG_PRT0_SLW\r
+.set SCSI_Out__8__AG, CYREG_PRT0_AG\r
+.set SCSI_Out__8__AMUX, CYREG_PRT0_AMUX\r
+.set SCSI_Out__8__BIE, CYREG_PRT0_BIE\r
+.set SCSI_Out__8__BIT_MASK, CYREG_PRT0_BIT_MASK\r
+.set SCSI_Out__8__BYP, CYREG_PRT0_BYP\r
+.set SCSI_Out__8__CTL, CYREG_PRT0_CTL\r
+.set SCSI_Out__8__DM0, CYREG_PRT0_DM0\r
+.set SCSI_Out__8__DM1, CYREG_PRT0_DM1\r
+.set SCSI_Out__8__DM2, CYREG_PRT0_DM2\r
+.set SCSI_Out__8__DR, CYREG_PRT0_DR\r
+.set SCSI_Out__8__INP_DIS, CYREG_PRT0_INP_DIS\r
+.set SCSI_Out__8__INTTYPE, CYREG_PICU0_INTTYPE1\r
+.set SCSI_Out__8__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG\r
+.set SCSI_Out__8__LCD_EN, CYREG_PRT0_LCD_EN\r
+.set SCSI_Out__8__MASK, 0x02\r
+.set SCSI_Out__8__PC, CYREG_PRT0_PC1\r
+.set SCSI_Out__8__PORT, 0\r
+.set SCSI_Out__8__PRT, CYREG_PRT0_PRT\r
+.set SCSI_Out__8__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL\r
+.set SCSI_Out__8__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN\r
+.set SCSI_Out__8__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0\r
+.set SCSI_Out__8__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1\r
+.set SCSI_Out__8__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0\r
+.set SCSI_Out__8__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1\r
+.set SCSI_Out__8__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT\r
+.set SCSI_Out__8__PS, CYREG_PRT0_PS\r
+.set SCSI_Out__8__SHIFT, 1\r
+.set SCSI_Out__8__SLW, CYREG_PRT0_SLW\r
+.set SCSI_Out__9__AG, CYREG_PRT0_AG\r
+.set SCSI_Out__9__AMUX, CYREG_PRT0_AMUX\r
+.set SCSI_Out__9__BIE, CYREG_PRT0_BIE\r
+.set SCSI_Out__9__BIT_MASK, CYREG_PRT0_BIT_MASK\r
+.set SCSI_Out__9__BYP, CYREG_PRT0_BYP\r
+.set SCSI_Out__9__CTL, CYREG_PRT0_CTL\r
+.set SCSI_Out__9__DM0, CYREG_PRT0_DM0\r
+.set SCSI_Out__9__DM1, CYREG_PRT0_DM1\r
+.set SCSI_Out__9__DM2, CYREG_PRT0_DM2\r
+.set SCSI_Out__9__DR, CYREG_PRT0_DR\r
+.set SCSI_Out__9__INP_DIS, CYREG_PRT0_INP_DIS\r
+.set SCSI_Out__9__INTTYPE, CYREG_PICU0_INTTYPE0\r
+.set SCSI_Out__9__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG\r
+.set SCSI_Out__9__LCD_EN, CYREG_PRT0_LCD_EN\r
+.set SCSI_Out__9__MASK, 0x01\r
+.set SCSI_Out__9__PC, CYREG_PRT0_PC0\r
+.set SCSI_Out__9__PORT, 0\r
+.set SCSI_Out__9__PRT, CYREG_PRT0_PRT\r
+.set SCSI_Out__9__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL\r
+.set SCSI_Out__9__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN\r
+.set SCSI_Out__9__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0\r
+.set SCSI_Out__9__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1\r
+.set SCSI_Out__9__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0\r
+.set SCSI_Out__9__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1\r
+.set SCSI_Out__9__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT\r
+.set SCSI_Out__9__PS, CYREG_PRT0_PS\r
+.set SCSI_Out__9__SHIFT, 0\r
+.set SCSI_Out__9__SLW, CYREG_PRT0_SLW\r
+.set SCSI_Out__ACK__AG, CYREG_PRT0_AG\r
+.set SCSI_Out__ACK__AMUX, CYREG_PRT0_AMUX\r
+.set SCSI_Out__ACK__BIE, CYREG_PRT0_BIE\r
+.set SCSI_Out__ACK__BIT_MASK, CYREG_PRT0_BIT_MASK\r
+.set SCSI_Out__ACK__BYP, CYREG_PRT0_BYP\r
+.set SCSI_Out__ACK__CTL, CYREG_PRT0_CTL\r
+.set SCSI_Out__ACK__DM0, CYREG_PRT0_DM0\r
+.set SCSI_Out__ACK__DM1, CYREG_PRT0_DM1\r
+.set SCSI_Out__ACK__DM2, CYREG_PRT0_DM2\r
+.set SCSI_Out__ACK__DR, CYREG_PRT0_DR\r
+.set SCSI_Out__ACK__INP_DIS, CYREG_PRT0_INP_DIS\r
+.set SCSI_Out__ACK__INTTYPE, CYREG_PICU0_INTTYPE6\r
+.set SCSI_Out__ACK__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG\r
+.set SCSI_Out__ACK__LCD_EN, CYREG_PRT0_LCD_EN\r
+.set SCSI_Out__ACK__MASK, 0x40\r
+.set SCSI_Out__ACK__PC, CYREG_PRT0_PC6\r
+.set SCSI_Out__ACK__PORT, 0\r
+.set SCSI_Out__ACK__PRT, CYREG_PRT0_PRT\r
+.set SCSI_Out__ACK__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL\r
+.set SCSI_Out__ACK__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN\r
+.set SCSI_Out__ACK__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0\r
+.set SCSI_Out__ACK__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1\r
+.set SCSI_Out__ACK__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0\r
+.set SCSI_Out__ACK__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1\r
+.set SCSI_Out__ACK__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT\r
+.set SCSI_Out__ACK__PS, CYREG_PRT0_PS\r
+.set SCSI_Out__ACK__SHIFT, 6\r
+.set SCSI_Out__ACK__SLW, CYREG_PRT0_SLW\r
+.set SCSI_Out__ATN__AG, CYREG_PRT4_AG\r
+.set SCSI_Out__ATN__AMUX, CYREG_PRT4_AMUX\r
+.set SCSI_Out__ATN__BIE, CYREG_PRT4_BIE\r
+.set SCSI_Out__ATN__BIT_MASK, CYREG_PRT4_BIT_MASK\r
+.set SCSI_Out__ATN__BYP, CYREG_PRT4_BYP\r
+.set SCSI_Out__ATN__CTL, CYREG_PRT4_CTL\r
+.set SCSI_Out__ATN__DM0, CYREG_PRT4_DM0\r
+.set SCSI_Out__ATN__DM1, CYREG_PRT4_DM1\r
+.set SCSI_Out__ATN__DM2, CYREG_PRT4_DM2\r
+.set SCSI_Out__ATN__DR, CYREG_PRT4_DR\r
+.set SCSI_Out__ATN__INP_DIS, CYREG_PRT4_INP_DIS\r
+.set SCSI_Out__ATN__INTTYPE, CYREG_PICU4_INTTYPE2\r
+.set SCSI_Out__ATN__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG\r
+.set SCSI_Out__ATN__LCD_EN, CYREG_PRT4_LCD_EN\r
+.set SCSI_Out__ATN__MASK, 0x04\r
+.set SCSI_Out__ATN__PC, CYREG_PRT4_PC2\r
+.set SCSI_Out__ATN__PORT, 4\r
+.set SCSI_Out__ATN__PRT, CYREG_PRT4_PRT\r
+.set SCSI_Out__ATN__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL\r
+.set SCSI_Out__ATN__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN\r
+.set SCSI_Out__ATN__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0\r
+.set SCSI_Out__ATN__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1\r
+.set SCSI_Out__ATN__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0\r
+.set SCSI_Out__ATN__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1\r
+.set SCSI_Out__ATN__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT\r
+.set SCSI_Out__ATN__PS, CYREG_PRT4_PS\r
+.set SCSI_Out__ATN__SHIFT, 2\r
+.set SCSI_Out__ATN__SLW, CYREG_PRT4_SLW\r
+.set SCSI_Out__BSY__AG, CYREG_PRT0_AG\r
+.set SCSI_Out__BSY__AMUX, CYREG_PRT0_AMUX\r
+.set SCSI_Out__BSY__BIE, CYREG_PRT0_BIE\r
+.set SCSI_Out__BSY__BIT_MASK, CYREG_PRT0_BIT_MASK\r
+.set SCSI_Out__BSY__BYP, CYREG_PRT0_BYP\r
+.set SCSI_Out__BSY__CTL, CYREG_PRT0_CTL\r
+.set SCSI_Out__BSY__DM0, CYREG_PRT0_DM0\r
+.set SCSI_Out__BSY__DM1, CYREG_PRT0_DM1\r
+.set SCSI_Out__BSY__DM2, CYREG_PRT0_DM2\r
+.set SCSI_Out__BSY__DR, CYREG_PRT0_DR\r
+.set SCSI_Out__BSY__INP_DIS, CYREG_PRT0_INP_DIS\r
+.set SCSI_Out__BSY__INTTYPE, CYREG_PICU0_INTTYPE7\r
+.set SCSI_Out__BSY__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG\r
+.set SCSI_Out__BSY__LCD_EN, CYREG_PRT0_LCD_EN\r
+.set SCSI_Out__BSY__MASK, 0x80\r
+.set SCSI_Out__BSY__PC, CYREG_PRT0_PC7\r
+.set SCSI_Out__BSY__PORT, 0\r
+.set SCSI_Out__BSY__PRT, CYREG_PRT0_PRT\r
+.set SCSI_Out__BSY__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL\r
+.set SCSI_Out__BSY__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN\r
+.set SCSI_Out__BSY__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0\r
+.set SCSI_Out__BSY__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1\r
+.set SCSI_Out__BSY__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0\r
+.set SCSI_Out__BSY__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1\r
+.set SCSI_Out__BSY__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT\r
+.set SCSI_Out__BSY__PS, CYREG_PRT0_PS\r
+.set SCSI_Out__BSY__SHIFT, 7\r
+.set SCSI_Out__BSY__SLW, CYREG_PRT0_SLW\r
+.set SCSI_Out__CD_raw__AG, CYREG_PRT0_AG\r
+.set SCSI_Out__CD_raw__AMUX, CYREG_PRT0_AMUX\r
+.set SCSI_Out__CD_raw__BIE, CYREG_PRT0_BIE\r
+.set SCSI_Out__CD_raw__BIT_MASK, CYREG_PRT0_BIT_MASK\r
+.set SCSI_Out__CD_raw__BYP, CYREG_PRT0_BYP\r
+.set SCSI_Out__CD_raw__CTL, CYREG_PRT0_CTL\r
+.set SCSI_Out__CD_raw__DM0, CYREG_PRT0_DM0\r
+.set SCSI_Out__CD_raw__DM1, CYREG_PRT0_DM1\r
+.set SCSI_Out__CD_raw__DM2, CYREG_PRT0_DM2\r
+.set SCSI_Out__CD_raw__DR, CYREG_PRT0_DR\r
+.set SCSI_Out__CD_raw__INP_DIS, CYREG_PRT0_INP_DIS\r
+.set SCSI_Out__CD_raw__INTTYPE, CYREG_PICU0_INTTYPE2\r
+.set SCSI_Out__CD_raw__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG\r
+.set SCSI_Out__CD_raw__LCD_EN, CYREG_PRT0_LCD_EN\r
+.set SCSI_Out__CD_raw__MASK, 0x04\r
+.set SCSI_Out__CD_raw__PC, CYREG_PRT0_PC2\r
+.set SCSI_Out__CD_raw__PORT, 0\r
+.set SCSI_Out__CD_raw__PRT, CYREG_PRT0_PRT\r
+.set SCSI_Out__CD_raw__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL\r
+.set SCSI_Out__CD_raw__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN\r
+.set SCSI_Out__CD_raw__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0\r
+.set SCSI_Out__CD_raw__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1\r
+.set SCSI_Out__CD_raw__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0\r
+.set SCSI_Out__CD_raw__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1\r
+.set SCSI_Out__CD_raw__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT\r
+.set SCSI_Out__CD_raw__PS, CYREG_PRT0_PS\r
+.set SCSI_Out__CD_raw__SHIFT, 2\r
+.set SCSI_Out__CD_raw__SLW, CYREG_PRT0_SLW\r
+.set SCSI_Out__DBP_raw__AG, CYREG_PRT4_AG\r
+.set SCSI_Out__DBP_raw__AMUX, CYREG_PRT4_AMUX\r
+.set SCSI_Out__DBP_raw__BIE, CYREG_PRT4_BIE\r
+.set SCSI_Out__DBP_raw__BIT_MASK, CYREG_PRT4_BIT_MASK\r
+.set SCSI_Out__DBP_raw__BYP, CYREG_PRT4_BYP\r
+.set SCSI_Out__DBP_raw__CTL, CYREG_PRT4_CTL\r
+.set SCSI_Out__DBP_raw__DM0, CYREG_PRT4_DM0\r
+.set SCSI_Out__DBP_raw__DM1, CYREG_PRT4_DM1\r
+.set SCSI_Out__DBP_raw__DM2, CYREG_PRT4_DM2\r
+.set SCSI_Out__DBP_raw__DR, CYREG_PRT4_DR\r
+.set SCSI_Out__DBP_raw__INP_DIS, CYREG_PRT4_INP_DIS\r
+.set SCSI_Out__DBP_raw__INTTYPE, CYREG_PICU4_INTTYPE3\r
+.set SCSI_Out__DBP_raw__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG\r
+.set SCSI_Out__DBP_raw__LCD_EN, CYREG_PRT4_LCD_EN\r
+.set SCSI_Out__DBP_raw__MASK, 0x08\r
+.set SCSI_Out__DBP_raw__PC, CYREG_PRT4_PC3\r
+.set SCSI_Out__DBP_raw__PORT, 4\r
+.set SCSI_Out__DBP_raw__PRT, CYREG_PRT4_PRT\r
+.set SCSI_Out__DBP_raw__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL\r
+.set SCSI_Out__DBP_raw__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN\r
+.set SCSI_Out__DBP_raw__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0\r
+.set SCSI_Out__DBP_raw__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1\r
+.set SCSI_Out__DBP_raw__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0\r
+.set SCSI_Out__DBP_raw__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1\r
+.set SCSI_Out__DBP_raw__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT\r
+.set SCSI_Out__DBP_raw__PS, CYREG_PRT4_PS\r
+.set SCSI_Out__DBP_raw__SHIFT, 3\r
+.set SCSI_Out__DBP_raw__SLW, CYREG_PRT4_SLW\r
+.set SCSI_Out__IO_raw__AG, CYREG_PRT0_AG\r
+.set SCSI_Out__IO_raw__AMUX, CYREG_PRT0_AMUX\r
+.set SCSI_Out__IO_raw__BIE, CYREG_PRT0_BIE\r
+.set SCSI_Out__IO_raw__BIT_MASK, CYREG_PRT0_BIT_MASK\r
+.set SCSI_Out__IO_raw__BYP, CYREG_PRT0_BYP\r
+.set SCSI_Out__IO_raw__CTL, CYREG_PRT0_CTL\r
+.set SCSI_Out__IO_raw__DM0, CYREG_PRT0_DM0\r
+.set SCSI_Out__IO_raw__DM1, CYREG_PRT0_DM1\r
+.set SCSI_Out__IO_raw__DM2, CYREG_PRT0_DM2\r
+.set SCSI_Out__IO_raw__DR, CYREG_PRT0_DR\r
+.set SCSI_Out__IO_raw__INP_DIS, CYREG_PRT0_INP_DIS\r
+.set SCSI_Out__IO_raw__INTTYPE, CYREG_PICU0_INTTYPE0\r
+.set SCSI_Out__IO_raw__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG\r
+.set SCSI_Out__IO_raw__LCD_EN, CYREG_PRT0_LCD_EN\r
+.set SCSI_Out__IO_raw__MASK, 0x01\r
+.set SCSI_Out__IO_raw__PC, CYREG_PRT0_PC0\r
+.set SCSI_Out__IO_raw__PORT, 0\r
+.set SCSI_Out__IO_raw__PRT, CYREG_PRT0_PRT\r
+.set SCSI_Out__IO_raw__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL\r
+.set SCSI_Out__IO_raw__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN\r
+.set SCSI_Out__IO_raw__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0\r
+.set SCSI_Out__IO_raw__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1\r
+.set SCSI_Out__IO_raw__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0\r
+.set SCSI_Out__IO_raw__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1\r
+.set SCSI_Out__IO_raw__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT\r
+.set SCSI_Out__IO_raw__PS, CYREG_PRT0_PS\r
+.set SCSI_Out__IO_raw__SHIFT, 0\r
+.set SCSI_Out__IO_raw__SLW, CYREG_PRT0_SLW\r
+.set SCSI_Out__MSG_raw__AG, CYREG_PRT0_AG\r
+.set SCSI_Out__MSG_raw__AMUX, CYREG_PRT0_AMUX\r
+.set SCSI_Out__MSG_raw__BIE, CYREG_PRT0_BIE\r
+.set SCSI_Out__MSG_raw__BIT_MASK, CYREG_PRT0_BIT_MASK\r
+.set SCSI_Out__MSG_raw__BYP, CYREG_PRT0_BYP\r
+.set SCSI_Out__MSG_raw__CTL, CYREG_PRT0_CTL\r
+.set SCSI_Out__MSG_raw__DM0, CYREG_PRT0_DM0\r
+.set SCSI_Out__MSG_raw__DM1, CYREG_PRT0_DM1\r
+.set SCSI_Out__MSG_raw__DM2, CYREG_PRT0_DM2\r
+.set SCSI_Out__MSG_raw__DR, CYREG_PRT0_DR\r
+.set SCSI_Out__MSG_raw__INP_DIS, CYREG_PRT0_INP_DIS\r
+.set SCSI_Out__MSG_raw__INTTYPE, CYREG_PICU0_INTTYPE4\r
+.set SCSI_Out__MSG_raw__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG\r
+.set SCSI_Out__MSG_raw__LCD_EN, CYREG_PRT0_LCD_EN\r
+.set SCSI_Out__MSG_raw__MASK, 0x10\r
+.set SCSI_Out__MSG_raw__PC, CYREG_PRT0_PC4\r
+.set SCSI_Out__MSG_raw__PORT, 0\r
+.set SCSI_Out__MSG_raw__PRT, CYREG_PRT0_PRT\r
+.set SCSI_Out__MSG_raw__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL\r
+.set SCSI_Out__MSG_raw__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN\r
+.set SCSI_Out__MSG_raw__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0\r
+.set SCSI_Out__MSG_raw__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1\r
+.set SCSI_Out__MSG_raw__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0\r
+.set SCSI_Out__MSG_raw__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1\r
+.set SCSI_Out__MSG_raw__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT\r
+.set SCSI_Out__MSG_raw__PS, CYREG_PRT0_PS\r
+.set SCSI_Out__MSG_raw__SHIFT, 4\r
+.set SCSI_Out__MSG_raw__SLW, CYREG_PRT0_SLW\r
+.set SCSI_Out__REQ__AG, CYREG_PRT0_AG\r
+.set SCSI_Out__REQ__AMUX, CYREG_PRT0_AMUX\r
+.set SCSI_Out__REQ__BIE, CYREG_PRT0_BIE\r
+.set SCSI_Out__REQ__BIT_MASK, CYREG_PRT0_BIT_MASK\r
+.set SCSI_Out__REQ__BYP, CYREG_PRT0_BYP\r
+.set SCSI_Out__REQ__CTL, CYREG_PRT0_CTL\r
+.set SCSI_Out__REQ__DM0, CYREG_PRT0_DM0\r
+.set SCSI_Out__REQ__DM1, CYREG_PRT0_DM1\r
+.set SCSI_Out__REQ__DM2, CYREG_PRT0_DM2\r
+.set SCSI_Out__REQ__DR, CYREG_PRT0_DR\r
+.set SCSI_Out__REQ__INP_DIS, CYREG_PRT0_INP_DIS\r
+.set SCSI_Out__REQ__INTTYPE, CYREG_PICU0_INTTYPE1\r
+.set SCSI_Out__REQ__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG\r
+.set SCSI_Out__REQ__LCD_EN, CYREG_PRT0_LCD_EN\r
+.set SCSI_Out__REQ__MASK, 0x02\r
+.set SCSI_Out__REQ__PC, CYREG_PRT0_PC1\r
+.set SCSI_Out__REQ__PORT, 0\r
+.set SCSI_Out__REQ__PRT, CYREG_PRT0_PRT\r
+.set SCSI_Out__REQ__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL\r
+.set SCSI_Out__REQ__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN\r
+.set SCSI_Out__REQ__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0\r
+.set SCSI_Out__REQ__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1\r
+.set SCSI_Out__REQ__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0\r
+.set SCSI_Out__REQ__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1\r
+.set SCSI_Out__REQ__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT\r
+.set SCSI_Out__REQ__PS, CYREG_PRT0_PS\r
+.set SCSI_Out__REQ__SHIFT, 1\r
+.set SCSI_Out__REQ__SLW, CYREG_PRT0_SLW\r
+.set SCSI_Out__RST__AG, CYREG_PRT0_AG\r
+.set SCSI_Out__RST__AMUX, CYREG_PRT0_AMUX\r
+.set SCSI_Out__RST__BIE, CYREG_PRT0_BIE\r
+.set SCSI_Out__RST__BIT_MASK, CYREG_PRT0_BIT_MASK\r
+.set SCSI_Out__RST__BYP, CYREG_PRT0_BYP\r
+.set SCSI_Out__RST__CTL, CYREG_PRT0_CTL\r
+.set SCSI_Out__RST__DM0, CYREG_PRT0_DM0\r
+.set SCSI_Out__RST__DM1, CYREG_PRT0_DM1\r
+.set SCSI_Out__RST__DM2, CYREG_PRT0_DM2\r
+.set SCSI_Out__RST__DR, CYREG_PRT0_DR\r
+.set SCSI_Out__RST__INP_DIS, CYREG_PRT0_INP_DIS\r
+.set SCSI_Out__RST__INTTYPE, CYREG_PICU0_INTTYPE5\r
+.set SCSI_Out__RST__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG\r
+.set SCSI_Out__RST__LCD_EN, CYREG_PRT0_LCD_EN\r
+.set SCSI_Out__RST__MASK, 0x20\r
+.set SCSI_Out__RST__PC, CYREG_PRT0_PC5\r
+.set SCSI_Out__RST__PORT, 0\r
+.set SCSI_Out__RST__PRT, CYREG_PRT0_PRT\r
+.set SCSI_Out__RST__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL\r
+.set SCSI_Out__RST__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN\r
+.set SCSI_Out__RST__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0\r
+.set SCSI_Out__RST__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1\r
+.set SCSI_Out__RST__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0\r
+.set SCSI_Out__RST__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1\r
+.set SCSI_Out__RST__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT\r
+.set SCSI_Out__RST__PS, CYREG_PRT0_PS\r
+.set SCSI_Out__RST__SHIFT, 5\r
+.set SCSI_Out__RST__SLW, CYREG_PRT0_SLW\r
+.set SCSI_Out__SEL__AG, CYREG_PRT0_AG\r
+.set SCSI_Out__SEL__AMUX, CYREG_PRT0_AMUX\r
+.set SCSI_Out__SEL__BIE, CYREG_PRT0_BIE\r
+.set SCSI_Out__SEL__BIT_MASK, CYREG_PRT0_BIT_MASK\r
+.set SCSI_Out__SEL__BYP, CYREG_PRT0_BYP\r
+.set SCSI_Out__SEL__CTL, CYREG_PRT0_CTL\r
+.set SCSI_Out__SEL__DM0, CYREG_PRT0_DM0\r
+.set SCSI_Out__SEL__DM1, CYREG_PRT0_DM1\r
+.set SCSI_Out__SEL__DM2, CYREG_PRT0_DM2\r
+.set SCSI_Out__SEL__DR, CYREG_PRT0_DR\r
+.set SCSI_Out__SEL__INP_DIS, CYREG_PRT0_INP_DIS\r
+.set SCSI_Out__SEL__INTTYPE, CYREG_PICU0_INTTYPE3\r
+.set SCSI_Out__SEL__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG\r
+.set SCSI_Out__SEL__LCD_EN, CYREG_PRT0_LCD_EN\r
+.set SCSI_Out__SEL__MASK, 0x08\r
+.set SCSI_Out__SEL__PC, CYREG_PRT0_PC3\r
+.set SCSI_Out__SEL__PORT, 0\r
+.set SCSI_Out__SEL__PRT, CYREG_PRT0_PRT\r
+.set SCSI_Out__SEL__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL\r
+.set SCSI_Out__SEL__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN\r
+.set SCSI_Out__SEL__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0\r
+.set SCSI_Out__SEL__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1\r
+.set SCSI_Out__SEL__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0\r
+.set SCSI_Out__SEL__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1\r
+.set SCSI_Out__SEL__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT\r
+.set SCSI_Out__SEL__PS, CYREG_PRT0_PS\r
+.set SCSI_Out__SEL__SHIFT, 3\r
+.set SCSI_Out__SEL__SLW, CYREG_PRT0_SLW\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__0__MASK, 0x01\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__0__POS, 0\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__1__MASK, 0x02\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__1__POS, 1\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB08_09_ACTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB08_09_CTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB08_09_CTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB08_09_CTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB08_09_CTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B1_UDB08_09_MSK\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB08_09_MSK\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB08_09_MSK\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB08_09_MSK\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__2__MASK, 0x04\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__2__POS, 2\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__3__MASK, 0x08\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__3__POS, 3\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__4__MASK, 0x10\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__4__POS, 4\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__5__MASK, 0x20\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__5__POS, 5\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__6__MASK, 0x40\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__6__POS, 6\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__7__MASK, 0x80\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__7__POS, 7\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B1_UDB08_ACTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG, CYREG_B1_UDB08_CTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B1_UDB08_ST_CTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG, CYREG_B1_UDB08_CTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B1_UDB08_ST_CTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__MASK, 0xFF\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB08_MSK_ACTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB08_MSK_ACTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG, CYREG_B1_UDB08_MSK\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK, 0x01\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__0__POS, 0\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB08_09_ACTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB08_09_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB08_09_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB08_09_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB08_09_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB08_09_MSK\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB08_09_MSK\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB08_09_MSK\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB08_09_MSK\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB08_ACTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB08_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB08_ST_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB08_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB08_ST_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK, 0x01\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB08_MSK_ACTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB08_MSK_ACTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB08_MSK\r
+.set SCSI_Out_DBx__0__AG, CYREG_PRT6_AG\r
+.set SCSI_Out_DBx__0__AMUX, CYREG_PRT6_AMUX\r
+.set SCSI_Out_DBx__0__BIE, CYREG_PRT6_BIE\r
+.set SCSI_Out_DBx__0__BIT_MASK, CYREG_PRT6_BIT_MASK\r
+.set SCSI_Out_DBx__0__BYP, CYREG_PRT6_BYP\r
+.set SCSI_Out_DBx__0__CTL, CYREG_PRT6_CTL\r
+.set SCSI_Out_DBx__0__DM0, CYREG_PRT6_DM0\r
+.set SCSI_Out_DBx__0__DM1, CYREG_PRT6_DM1\r
+.set SCSI_Out_DBx__0__DM2, CYREG_PRT6_DM2\r
+.set SCSI_Out_DBx__0__DR, CYREG_PRT6_DR\r
+.set SCSI_Out_DBx__0__INP_DIS, CYREG_PRT6_INP_DIS\r
+.set SCSI_Out_DBx__0__INTTYPE, CYREG_PICU6_INTTYPE3\r
+.set SCSI_Out_DBx__0__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG\r
+.set SCSI_Out_DBx__0__LCD_EN, CYREG_PRT6_LCD_EN\r
+.set SCSI_Out_DBx__0__MASK, 0x08\r
+.set SCSI_Out_DBx__0__PC, CYREG_PRT6_PC3\r
+.set SCSI_Out_DBx__0__PORT, 6\r
+.set SCSI_Out_DBx__0__PRT, CYREG_PRT6_PRT\r
+.set SCSI_Out_DBx__0__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL\r
+.set SCSI_Out_DBx__0__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN\r
+.set SCSI_Out_DBx__0__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0\r
+.set SCSI_Out_DBx__0__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1\r
+.set SCSI_Out_DBx__0__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0\r
+.set SCSI_Out_DBx__0__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1\r
+.set SCSI_Out_DBx__0__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT\r
+.set SCSI_Out_DBx__0__PS, CYREG_PRT6_PS\r
+.set SCSI_Out_DBx__0__SHIFT, 3\r
+.set SCSI_Out_DBx__0__SLW, CYREG_PRT6_SLW\r
+.set SCSI_Out_DBx__1__AG, CYREG_PRT6_AG\r
+.set SCSI_Out_DBx__1__AMUX, CYREG_PRT6_AMUX\r
+.set SCSI_Out_DBx__1__BIE, CYREG_PRT6_BIE\r
+.set SCSI_Out_DBx__1__BIT_MASK, CYREG_PRT6_BIT_MASK\r
+.set SCSI_Out_DBx__1__BYP, CYREG_PRT6_BYP\r
+.set SCSI_Out_DBx__1__CTL, CYREG_PRT6_CTL\r
+.set SCSI_Out_DBx__1__DM0, CYREG_PRT6_DM0\r
+.set SCSI_Out_DBx__1__DM1, CYREG_PRT6_DM1\r
+.set SCSI_Out_DBx__1__DM2, CYREG_PRT6_DM2\r
+.set SCSI_Out_DBx__1__DR, CYREG_PRT6_DR\r
+.set SCSI_Out_DBx__1__INP_DIS, CYREG_PRT6_INP_DIS\r
+.set SCSI_Out_DBx__1__INTTYPE, CYREG_PICU6_INTTYPE2\r
+.set SCSI_Out_DBx__1__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG\r
+.set SCSI_Out_DBx__1__LCD_EN, CYREG_PRT6_LCD_EN\r
+.set SCSI_Out_DBx__1__MASK, 0x04\r
+.set SCSI_Out_DBx__1__PC, CYREG_PRT6_PC2\r
+.set SCSI_Out_DBx__1__PORT, 6\r
+.set SCSI_Out_DBx__1__PRT, CYREG_PRT6_PRT\r
+.set SCSI_Out_DBx__1__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL\r
+.set SCSI_Out_DBx__1__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN\r
+.set SCSI_Out_DBx__1__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0\r
+.set SCSI_Out_DBx__1__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1\r
+.set SCSI_Out_DBx__1__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0\r
+.set SCSI_Out_DBx__1__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1\r
+.set SCSI_Out_DBx__1__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT\r
+.set SCSI_Out_DBx__1__PS, CYREG_PRT6_PS\r
+.set SCSI_Out_DBx__1__SHIFT, 2\r
+.set SCSI_Out_DBx__1__SLW, CYREG_PRT6_SLW\r
+.set SCSI_Out_DBx__2__AG, CYREG_PRT6_AG\r
+.set SCSI_Out_DBx__2__AMUX, CYREG_PRT6_AMUX\r
+.set SCSI_Out_DBx__2__BIE, CYREG_PRT6_BIE\r
+.set SCSI_Out_DBx__2__BIT_MASK, CYREG_PRT6_BIT_MASK\r
+.set SCSI_Out_DBx__2__BYP, CYREG_PRT6_BYP\r
+.set SCSI_Out_DBx__2__CTL, CYREG_PRT6_CTL\r
+.set SCSI_Out_DBx__2__DM0, CYREG_PRT6_DM0\r
+.set SCSI_Out_DBx__2__DM1, CYREG_PRT6_DM1\r
+.set SCSI_Out_DBx__2__DM2, CYREG_PRT6_DM2\r
+.set SCSI_Out_DBx__2__DR, CYREG_PRT6_DR\r
+.set SCSI_Out_DBx__2__INP_DIS, CYREG_PRT6_INP_DIS\r
+.set SCSI_Out_DBx__2__INTTYPE, CYREG_PICU6_INTTYPE1\r
+.set SCSI_Out_DBx__2__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG\r
+.set SCSI_Out_DBx__2__LCD_EN, CYREG_PRT6_LCD_EN\r
+.set SCSI_Out_DBx__2__MASK, 0x02\r
+.set SCSI_Out_DBx__2__PC, CYREG_PRT6_PC1\r
+.set SCSI_Out_DBx__2__PORT, 6\r
+.set SCSI_Out_DBx__2__PRT, CYREG_PRT6_PRT\r
+.set SCSI_Out_DBx__2__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL\r
+.set SCSI_Out_DBx__2__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN\r
+.set SCSI_Out_DBx__2__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0\r
+.set SCSI_Out_DBx__2__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1\r
+.set SCSI_Out_DBx__2__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0\r
+.set SCSI_Out_DBx__2__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1\r
+.set SCSI_Out_DBx__2__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT\r
+.set SCSI_Out_DBx__2__PS, CYREG_PRT6_PS\r
+.set SCSI_Out_DBx__2__SHIFT, 1\r
+.set SCSI_Out_DBx__2__SLW, CYREG_PRT6_SLW\r
+.set SCSI_Out_DBx__3__AG, CYREG_PRT6_AG\r
+.set SCSI_Out_DBx__3__AMUX, CYREG_PRT6_AMUX\r
+.set SCSI_Out_DBx__3__BIE, CYREG_PRT6_BIE\r
+.set SCSI_Out_DBx__3__BIT_MASK, CYREG_PRT6_BIT_MASK\r
+.set SCSI_Out_DBx__3__BYP, CYREG_PRT6_BYP\r
+.set SCSI_Out_DBx__3__CTL, CYREG_PRT6_CTL\r
+.set SCSI_Out_DBx__3__DM0, CYREG_PRT6_DM0\r
+.set SCSI_Out_DBx__3__DM1, CYREG_PRT6_DM1\r
+.set SCSI_Out_DBx__3__DM2, CYREG_PRT6_DM2\r
+.set SCSI_Out_DBx__3__DR, CYREG_PRT6_DR\r
+.set SCSI_Out_DBx__3__INP_DIS, CYREG_PRT6_INP_DIS\r
+.set SCSI_Out_DBx__3__INTTYPE, CYREG_PICU6_INTTYPE0\r
+.set SCSI_Out_DBx__3__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG\r
+.set SCSI_Out_DBx__3__LCD_EN, CYREG_PRT6_LCD_EN\r
+.set SCSI_Out_DBx__3__MASK, 0x01\r
+.set SCSI_Out_DBx__3__PC, CYREG_PRT6_PC0\r
+.set SCSI_Out_DBx__3__PORT, 6\r
+.set SCSI_Out_DBx__3__PRT, CYREG_PRT6_PRT\r
+.set SCSI_Out_DBx__3__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL\r
+.set SCSI_Out_DBx__3__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN\r
+.set SCSI_Out_DBx__3__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0\r
+.set SCSI_Out_DBx__3__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1\r
+.set SCSI_Out_DBx__3__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0\r
+.set SCSI_Out_DBx__3__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1\r
+.set SCSI_Out_DBx__3__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT\r
+.set SCSI_Out_DBx__3__PS, CYREG_PRT6_PS\r
+.set SCSI_Out_DBx__3__SHIFT, 0\r
+.set SCSI_Out_DBx__3__SLW, CYREG_PRT6_SLW\r
+.set SCSI_Out_DBx__4__AG, CYREG_PRT4_AG\r
+.set SCSI_Out_DBx__4__AMUX, CYREG_PRT4_AMUX\r
+.set SCSI_Out_DBx__4__BIE, CYREG_PRT4_BIE\r
+.set SCSI_Out_DBx__4__BIT_MASK, CYREG_PRT4_BIT_MASK\r
+.set SCSI_Out_DBx__4__BYP, CYREG_PRT4_BYP\r
+.set SCSI_Out_DBx__4__CTL, CYREG_PRT4_CTL\r
+.set SCSI_Out_DBx__4__DM0, CYREG_PRT4_DM0\r
+.set SCSI_Out_DBx__4__DM1, CYREG_PRT4_DM1\r
+.set SCSI_Out_DBx__4__DM2, CYREG_PRT4_DM2\r
+.set SCSI_Out_DBx__4__DR, CYREG_PRT4_DR\r
+.set SCSI_Out_DBx__4__INP_DIS, CYREG_PRT4_INP_DIS\r
+.set SCSI_Out_DBx__4__INTTYPE, CYREG_PICU4_INTTYPE7\r
+.set SCSI_Out_DBx__4__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG\r
+.set SCSI_Out_DBx__4__LCD_EN, CYREG_PRT4_LCD_EN\r
+.set SCSI_Out_DBx__4__MASK, 0x80\r
+.set SCSI_Out_DBx__4__PC, CYREG_PRT4_PC7\r
+.set SCSI_Out_DBx__4__PORT, 4\r
+.set SCSI_Out_DBx__4__PRT, CYREG_PRT4_PRT\r
+.set SCSI_Out_DBx__4__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL\r
+.set SCSI_Out_DBx__4__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN\r
+.set SCSI_Out_DBx__4__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0\r
+.set SCSI_Out_DBx__4__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1\r
+.set SCSI_Out_DBx__4__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0\r
+.set SCSI_Out_DBx__4__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1\r
+.set SCSI_Out_DBx__4__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT\r
+.set SCSI_Out_DBx__4__PS, CYREG_PRT4_PS\r
+.set SCSI_Out_DBx__4__SHIFT, 7\r
+.set SCSI_Out_DBx__4__SLW, CYREG_PRT4_SLW\r
+.set SCSI_Out_DBx__5__AG, CYREG_PRT4_AG\r
+.set SCSI_Out_DBx__5__AMUX, CYREG_PRT4_AMUX\r
+.set SCSI_Out_DBx__5__BIE, CYREG_PRT4_BIE\r
+.set SCSI_Out_DBx__5__BIT_MASK, CYREG_PRT4_BIT_MASK\r
+.set SCSI_Out_DBx__5__BYP, CYREG_PRT4_BYP\r
+.set SCSI_Out_DBx__5__CTL, CYREG_PRT4_CTL\r
+.set SCSI_Out_DBx__5__DM0, CYREG_PRT4_DM0\r
+.set SCSI_Out_DBx__5__DM1, CYREG_PRT4_DM1\r
+.set SCSI_Out_DBx__5__DM2, CYREG_PRT4_DM2\r
+.set SCSI_Out_DBx__5__DR, CYREG_PRT4_DR\r
+.set SCSI_Out_DBx__5__INP_DIS, CYREG_PRT4_INP_DIS\r
+.set SCSI_Out_DBx__5__INTTYPE, CYREG_PICU4_INTTYPE6\r
+.set SCSI_Out_DBx__5__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG\r
+.set SCSI_Out_DBx__5__LCD_EN, CYREG_PRT4_LCD_EN\r
+.set SCSI_Out_DBx__5__MASK, 0x40\r
+.set SCSI_Out_DBx__5__PC, CYREG_PRT4_PC6\r
+.set SCSI_Out_DBx__5__PORT, 4\r
+.set SCSI_Out_DBx__5__PRT, CYREG_PRT4_PRT\r
+.set SCSI_Out_DBx__5__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL\r
+.set SCSI_Out_DBx__5__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN\r
+.set SCSI_Out_DBx__5__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0\r
+.set SCSI_Out_DBx__5__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1\r
+.set SCSI_Out_DBx__5__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0\r
+.set SCSI_Out_DBx__5__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1\r
+.set SCSI_Out_DBx__5__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT\r
+.set SCSI_Out_DBx__5__PS, CYREG_PRT4_PS\r
+.set SCSI_Out_DBx__5__SHIFT, 6\r
+.set SCSI_Out_DBx__5__SLW, CYREG_PRT4_SLW\r
+.set SCSI_Out_DBx__6__AG, CYREG_PRT4_AG\r
+.set SCSI_Out_DBx__6__AMUX, CYREG_PRT4_AMUX\r
+.set SCSI_Out_DBx__6__BIE, CYREG_PRT4_BIE\r
+.set SCSI_Out_DBx__6__BIT_MASK, CYREG_PRT4_BIT_MASK\r
+.set SCSI_Out_DBx__6__BYP, CYREG_PRT4_BYP\r
+.set SCSI_Out_DBx__6__CTL, CYREG_PRT4_CTL\r
+.set SCSI_Out_DBx__6__DM0, CYREG_PRT4_DM0\r
+.set SCSI_Out_DBx__6__DM1, CYREG_PRT4_DM1\r
+.set SCSI_Out_DBx__6__DM2, CYREG_PRT4_DM2\r
+.set SCSI_Out_DBx__6__DR, CYREG_PRT4_DR\r
+.set SCSI_Out_DBx__6__INP_DIS, CYREG_PRT4_INP_DIS\r
+.set SCSI_Out_DBx__6__INTTYPE, CYREG_PICU4_INTTYPE5\r
+.set SCSI_Out_DBx__6__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG\r
+.set SCSI_Out_DBx__6__LCD_EN, CYREG_PRT4_LCD_EN\r
+.set SCSI_Out_DBx__6__MASK, 0x20\r
+.set SCSI_Out_DBx__6__PC, CYREG_PRT4_PC5\r
+.set SCSI_Out_DBx__6__PORT, 4\r
+.set SCSI_Out_DBx__6__PRT, CYREG_PRT4_PRT\r
+.set SCSI_Out_DBx__6__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL\r
+.set SCSI_Out_DBx__6__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN\r
+.set SCSI_Out_DBx__6__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0\r
+.set SCSI_Out_DBx__6__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1\r
+.set SCSI_Out_DBx__6__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0\r
+.set SCSI_Out_DBx__6__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1\r
+.set SCSI_Out_DBx__6__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT\r
+.set SCSI_Out_DBx__6__PS, CYREG_PRT4_PS\r
+.set SCSI_Out_DBx__6__SHIFT, 5\r
+.set SCSI_Out_DBx__6__SLW, CYREG_PRT4_SLW\r
+.set SCSI_Out_DBx__7__AG, CYREG_PRT4_AG\r
+.set SCSI_Out_DBx__7__AMUX, CYREG_PRT4_AMUX\r
+.set SCSI_Out_DBx__7__BIE, CYREG_PRT4_BIE\r
+.set SCSI_Out_DBx__7__BIT_MASK, CYREG_PRT4_BIT_MASK\r
+.set SCSI_Out_DBx__7__BYP, CYREG_PRT4_BYP\r
+.set SCSI_Out_DBx__7__CTL, CYREG_PRT4_CTL\r
+.set SCSI_Out_DBx__7__DM0, CYREG_PRT4_DM0\r
+.set SCSI_Out_DBx__7__DM1, CYREG_PRT4_DM1\r
+.set SCSI_Out_DBx__7__DM2, CYREG_PRT4_DM2\r
+.set SCSI_Out_DBx__7__DR, CYREG_PRT4_DR\r
+.set SCSI_Out_DBx__7__INP_DIS, CYREG_PRT4_INP_DIS\r
+.set SCSI_Out_DBx__7__INTTYPE, CYREG_PICU4_INTTYPE4\r
+.set SCSI_Out_DBx__7__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG\r
+.set SCSI_Out_DBx__7__LCD_EN, CYREG_PRT4_LCD_EN\r
+.set SCSI_Out_DBx__7__MASK, 0x10\r
+.set SCSI_Out_DBx__7__PC, CYREG_PRT4_PC4\r
+.set SCSI_Out_DBx__7__PORT, 4\r
+.set SCSI_Out_DBx__7__PRT, CYREG_PRT4_PRT\r
+.set SCSI_Out_DBx__7__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL\r
+.set SCSI_Out_DBx__7__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN\r
+.set SCSI_Out_DBx__7__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0\r
+.set SCSI_Out_DBx__7__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1\r
+.set SCSI_Out_DBx__7__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0\r
+.set SCSI_Out_DBx__7__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1\r
+.set SCSI_Out_DBx__7__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT\r
+.set SCSI_Out_DBx__7__PS, CYREG_PRT4_PS\r
+.set SCSI_Out_DBx__7__SHIFT, 4\r
+.set SCSI_Out_DBx__7__SLW, CYREG_PRT4_SLW\r
+.set SCSI_Out_DBx__DB0__AG, CYREG_PRT6_AG\r
+.set SCSI_Out_DBx__DB0__AMUX, CYREG_PRT6_AMUX\r
+.set SCSI_Out_DBx__DB0__BIE, CYREG_PRT6_BIE\r
+.set SCSI_Out_DBx__DB0__BIT_MASK, CYREG_PRT6_BIT_MASK\r
+.set SCSI_Out_DBx__DB0__BYP, CYREG_PRT6_BYP\r
+.set SCSI_Out_DBx__DB0__CTL, CYREG_PRT6_CTL\r
+.set SCSI_Out_DBx__DB0__DM0, CYREG_PRT6_DM0\r
+.set SCSI_Out_DBx__DB0__DM1, CYREG_PRT6_DM1\r
+.set SCSI_Out_DBx__DB0__DM2, CYREG_PRT6_DM2\r
+.set SCSI_Out_DBx__DB0__DR, CYREG_PRT6_DR\r
+.set SCSI_Out_DBx__DB0__INP_DIS, CYREG_PRT6_INP_DIS\r
+.set SCSI_Out_DBx__DB0__INTTYPE, CYREG_PICU6_INTTYPE3\r
+.set SCSI_Out_DBx__DB0__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG\r
+.set SCSI_Out_DBx__DB0__LCD_EN, CYREG_PRT6_LCD_EN\r
+.set SCSI_Out_DBx__DB0__MASK, 0x08\r
+.set SCSI_Out_DBx__DB0__PC, CYREG_PRT6_PC3\r
+.set SCSI_Out_DBx__DB0__PORT, 6\r
+.set SCSI_Out_DBx__DB0__PRT, CYREG_PRT6_PRT\r
+.set SCSI_Out_DBx__DB0__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL\r
+.set SCSI_Out_DBx__DB0__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN\r
+.set SCSI_Out_DBx__DB0__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0\r
+.set SCSI_Out_DBx__DB0__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1\r
+.set SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0\r
+.set SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1\r
+.set SCSI_Out_DBx__DB0__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT\r
+.set SCSI_Out_DBx__DB0__PS, CYREG_PRT6_PS\r
+.set SCSI_Out_DBx__DB0__SHIFT, 3\r
+.set SCSI_Out_DBx__DB0__SLW, CYREG_PRT6_SLW\r
+.set SCSI_Out_DBx__DB1__AG, CYREG_PRT6_AG\r
+.set SCSI_Out_DBx__DB1__AMUX, CYREG_PRT6_AMUX\r
+.set SCSI_Out_DBx__DB1__BIE, CYREG_PRT6_BIE\r
+.set SCSI_Out_DBx__DB1__BIT_MASK, CYREG_PRT6_BIT_MASK\r
+.set SCSI_Out_DBx__DB1__BYP, CYREG_PRT6_BYP\r
+.set SCSI_Out_DBx__DB1__CTL, CYREG_PRT6_CTL\r
+.set SCSI_Out_DBx__DB1__DM0, CYREG_PRT6_DM0\r
+.set SCSI_Out_DBx__DB1__DM1, CYREG_PRT6_DM1\r
+.set SCSI_Out_DBx__DB1__DM2, CYREG_PRT6_DM2\r
+.set SCSI_Out_DBx__DB1__DR, CYREG_PRT6_DR\r
+.set SCSI_Out_DBx__DB1__INP_DIS, CYREG_PRT6_INP_DIS\r
+.set SCSI_Out_DBx__DB1__INTTYPE, CYREG_PICU6_INTTYPE2\r
+.set SCSI_Out_DBx__DB1__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG\r
+.set SCSI_Out_DBx__DB1__LCD_EN, CYREG_PRT6_LCD_EN\r
+.set SCSI_Out_DBx__DB1__MASK, 0x04\r
+.set SCSI_Out_DBx__DB1__PC, CYREG_PRT6_PC2\r
+.set SCSI_Out_DBx__DB1__PORT, 6\r
+.set SCSI_Out_DBx__DB1__PRT, CYREG_PRT6_PRT\r
+.set SCSI_Out_DBx__DB1__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL\r
+.set SCSI_Out_DBx__DB1__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN\r
+.set SCSI_Out_DBx__DB1__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0\r
+.set SCSI_Out_DBx__DB1__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1\r
+.set SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0\r
+.set SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1\r
+.set SCSI_Out_DBx__DB1__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT\r
+.set SCSI_Out_DBx__DB1__PS, CYREG_PRT6_PS\r
+.set SCSI_Out_DBx__DB1__SHIFT, 2\r
+.set SCSI_Out_DBx__DB1__SLW, CYREG_PRT6_SLW\r
+.set SCSI_Out_DBx__DB2__AG, CYREG_PRT6_AG\r
+.set SCSI_Out_DBx__DB2__AMUX, CYREG_PRT6_AMUX\r
+.set SCSI_Out_DBx__DB2__BIE, CYREG_PRT6_BIE\r
+.set SCSI_Out_DBx__DB2__BIT_MASK, CYREG_PRT6_BIT_MASK\r
+.set SCSI_Out_DBx__DB2__BYP, CYREG_PRT6_BYP\r
+.set SCSI_Out_DBx__DB2__CTL, CYREG_PRT6_CTL\r
+.set SCSI_Out_DBx__DB2__DM0, CYREG_PRT6_DM0\r
+.set SCSI_Out_DBx__DB2__DM1, CYREG_PRT6_DM1\r
+.set SCSI_Out_DBx__DB2__DM2, CYREG_PRT6_DM2\r
+.set SCSI_Out_DBx__DB2__DR, CYREG_PRT6_DR\r
+.set SCSI_Out_DBx__DB2__INP_DIS, CYREG_PRT6_INP_DIS\r
+.set SCSI_Out_DBx__DB2__INTTYPE, CYREG_PICU6_INTTYPE1\r
+.set SCSI_Out_DBx__DB2__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG\r
+.set SCSI_Out_DBx__DB2__LCD_EN, CYREG_PRT6_LCD_EN\r
+.set SCSI_Out_DBx__DB2__MASK, 0x02\r
+.set SCSI_Out_DBx__DB2__PC, CYREG_PRT6_PC1\r
+.set SCSI_Out_DBx__DB2__PORT, 6\r
+.set SCSI_Out_DBx__DB2__PRT, CYREG_PRT6_PRT\r
+.set SCSI_Out_DBx__DB2__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL\r
+.set SCSI_Out_DBx__DB2__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN\r
+.set SCSI_Out_DBx__DB2__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0\r
+.set SCSI_Out_DBx__DB2__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1\r
+.set SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0\r
+.set SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1\r
+.set SCSI_Out_DBx__DB2__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT\r
+.set SCSI_Out_DBx__DB2__PS, CYREG_PRT6_PS\r
+.set SCSI_Out_DBx__DB2__SHIFT, 1\r
+.set SCSI_Out_DBx__DB2__SLW, CYREG_PRT6_SLW\r
+.set SCSI_Out_DBx__DB3__AG, CYREG_PRT6_AG\r
+.set SCSI_Out_DBx__DB3__AMUX, CYREG_PRT6_AMUX\r
+.set SCSI_Out_DBx__DB3__BIE, CYREG_PRT6_BIE\r
+.set SCSI_Out_DBx__DB3__BIT_MASK, CYREG_PRT6_BIT_MASK\r
+.set SCSI_Out_DBx__DB3__BYP, CYREG_PRT6_BYP\r
+.set SCSI_Out_DBx__DB3__CTL, CYREG_PRT6_CTL\r
+.set SCSI_Out_DBx__DB3__DM0, CYREG_PRT6_DM0\r
+.set SCSI_Out_DBx__DB3__DM1, CYREG_PRT6_DM1\r
+.set SCSI_Out_DBx__DB3__DM2, CYREG_PRT6_DM2\r
+.set SCSI_Out_DBx__DB3__DR, CYREG_PRT6_DR\r
+.set SCSI_Out_DBx__DB3__INP_DIS, CYREG_PRT6_INP_DIS\r
+.set SCSI_Out_DBx__DB3__INTTYPE, CYREG_PICU6_INTTYPE0\r
+.set SCSI_Out_DBx__DB3__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG\r
+.set SCSI_Out_DBx__DB3__LCD_EN, CYREG_PRT6_LCD_EN\r
+.set SCSI_Out_DBx__DB3__MASK, 0x01\r
+.set SCSI_Out_DBx__DB3__PC, CYREG_PRT6_PC0\r
+.set SCSI_Out_DBx__DB3__PORT, 6\r
+.set SCSI_Out_DBx__DB3__PRT, CYREG_PRT6_PRT\r
+.set SCSI_Out_DBx__DB3__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL\r
+.set SCSI_Out_DBx__DB3__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN\r
+.set SCSI_Out_DBx__DB3__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0\r
+.set SCSI_Out_DBx__DB3__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1\r
+.set SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0\r
+.set SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1\r
+.set SCSI_Out_DBx__DB3__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT\r
+.set SCSI_Out_DBx__DB3__PS, CYREG_PRT6_PS\r
+.set SCSI_Out_DBx__DB3__SHIFT, 0\r
+.set SCSI_Out_DBx__DB3__SLW, CYREG_PRT6_SLW\r
+.set SCSI_Out_DBx__DB4__AG, CYREG_PRT4_AG\r
+.set SCSI_Out_DBx__DB4__AMUX, CYREG_PRT4_AMUX\r
+.set SCSI_Out_DBx__DB4__BIE, CYREG_PRT4_BIE\r
+.set SCSI_Out_DBx__DB4__BIT_MASK, CYREG_PRT4_BIT_MASK\r
+.set SCSI_Out_DBx__DB4__BYP, CYREG_PRT4_BYP\r
+.set SCSI_Out_DBx__DB4__CTL, CYREG_PRT4_CTL\r
+.set SCSI_Out_DBx__DB4__DM0, CYREG_PRT4_DM0\r
+.set SCSI_Out_DBx__DB4__DM1, CYREG_PRT4_DM1\r
+.set SCSI_Out_DBx__DB4__DM2, CYREG_PRT4_DM2\r
+.set SCSI_Out_DBx__DB4__DR, CYREG_PRT4_DR\r
+.set SCSI_Out_DBx__DB4__INP_DIS, CYREG_PRT4_INP_DIS\r
+.set SCSI_Out_DBx__DB4__INTTYPE, CYREG_PICU4_INTTYPE7\r
+.set SCSI_Out_DBx__DB4__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG\r
+.set SCSI_Out_DBx__DB4__LCD_EN, CYREG_PRT4_LCD_EN\r
+.set SCSI_Out_DBx__DB4__MASK, 0x80\r
+.set SCSI_Out_DBx__DB4__PC, CYREG_PRT4_PC7\r
+.set SCSI_Out_DBx__DB4__PORT, 4\r
+.set SCSI_Out_DBx__DB4__PRT, CYREG_PRT4_PRT\r
+.set SCSI_Out_DBx__DB4__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL\r
+.set SCSI_Out_DBx__DB4__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN\r
+.set SCSI_Out_DBx__DB4__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0\r
+.set SCSI_Out_DBx__DB4__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1\r
+.set SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0\r
+.set SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1\r
+.set SCSI_Out_DBx__DB4__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT\r
+.set SCSI_Out_DBx__DB4__PS, CYREG_PRT4_PS\r
+.set SCSI_Out_DBx__DB4__SHIFT, 7\r
+.set SCSI_Out_DBx__DB4__SLW, CYREG_PRT4_SLW\r
+.set SCSI_Out_DBx__DB5__AG, CYREG_PRT4_AG\r
+.set SCSI_Out_DBx__DB5__AMUX, CYREG_PRT4_AMUX\r
+.set SCSI_Out_DBx__DB5__BIE, CYREG_PRT4_BIE\r
+.set SCSI_Out_DBx__DB5__BIT_MASK, CYREG_PRT4_BIT_MASK\r
+.set SCSI_Out_DBx__DB5__BYP, CYREG_PRT4_BYP\r
+.set SCSI_Out_DBx__DB5__CTL, CYREG_PRT4_CTL\r
+.set SCSI_Out_DBx__DB5__DM0, CYREG_PRT4_DM0\r
+.set SCSI_Out_DBx__DB5__DM1, CYREG_PRT4_DM1\r
+.set SCSI_Out_DBx__DB5__DM2, CYREG_PRT4_DM2\r
+.set SCSI_Out_DBx__DB5__DR, CYREG_PRT4_DR\r
+.set SCSI_Out_DBx__DB5__INP_DIS, CYREG_PRT4_INP_DIS\r
+.set SCSI_Out_DBx__DB5__INTTYPE, CYREG_PICU4_INTTYPE6\r
+.set SCSI_Out_DBx__DB5__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG\r
+.set SCSI_Out_DBx__DB5__LCD_EN, CYREG_PRT4_LCD_EN\r
+.set SCSI_Out_DBx__DB5__MASK, 0x40\r
+.set SCSI_Out_DBx__DB5__PC, CYREG_PRT4_PC6\r
+.set SCSI_Out_DBx__DB5__PORT, 4\r
+.set SCSI_Out_DBx__DB5__PRT, CYREG_PRT4_PRT\r
+.set SCSI_Out_DBx__DB5__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL\r
+.set SCSI_Out_DBx__DB5__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN\r
+.set SCSI_Out_DBx__DB5__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0\r
+.set SCSI_Out_DBx__DB5__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1\r
+.set SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0\r
+.set SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1\r
+.set SCSI_Out_DBx__DB5__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT\r
+.set SCSI_Out_DBx__DB5__PS, CYREG_PRT4_PS\r
+.set SCSI_Out_DBx__DB5__SHIFT, 6\r
+.set SCSI_Out_DBx__DB5__SLW, CYREG_PRT4_SLW\r
+.set SCSI_Out_DBx__DB6__AG, CYREG_PRT4_AG\r
+.set SCSI_Out_DBx__DB6__AMUX, CYREG_PRT4_AMUX\r
+.set SCSI_Out_DBx__DB6__BIE, CYREG_PRT4_BIE\r
+.set SCSI_Out_DBx__DB6__BIT_MASK, CYREG_PRT4_BIT_MASK\r
+.set SCSI_Out_DBx__DB6__BYP, CYREG_PRT4_BYP\r
+.set SCSI_Out_DBx__DB6__CTL, CYREG_PRT4_CTL\r
+.set SCSI_Out_DBx__DB6__DM0, CYREG_PRT4_DM0\r
+.set SCSI_Out_DBx__DB6__DM1, CYREG_PRT4_DM1\r
+.set SCSI_Out_DBx__DB6__DM2, CYREG_PRT4_DM2\r
+.set SCSI_Out_DBx__DB6__DR, CYREG_PRT4_DR\r
+.set SCSI_Out_DBx__DB6__INP_DIS, CYREG_PRT4_INP_DIS\r
+.set SCSI_Out_DBx__DB6__INTTYPE, CYREG_PICU4_INTTYPE5\r
+.set SCSI_Out_DBx__DB6__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG\r
+.set SCSI_Out_DBx__DB6__LCD_EN, CYREG_PRT4_LCD_EN\r
+.set SCSI_Out_DBx__DB6__MASK, 0x20\r
+.set SCSI_Out_DBx__DB6__PC, CYREG_PRT4_PC5\r
+.set SCSI_Out_DBx__DB6__PORT, 4\r
+.set SCSI_Out_DBx__DB6__PRT, CYREG_PRT4_PRT\r
+.set SCSI_Out_DBx__DB6__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL\r
+.set SCSI_Out_DBx__DB6__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN\r
+.set SCSI_Out_DBx__DB6__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0\r
+.set SCSI_Out_DBx__DB6__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1\r
+.set SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0\r
+.set SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1\r
+.set SCSI_Out_DBx__DB6__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT\r
+.set SCSI_Out_DBx__DB6__PS, CYREG_PRT4_PS\r
+.set SCSI_Out_DBx__DB6__SHIFT, 5\r
+.set SCSI_Out_DBx__DB6__SLW, CYREG_PRT4_SLW\r
+.set SCSI_Out_DBx__DB7__AG, CYREG_PRT4_AG\r
+.set SCSI_Out_DBx__DB7__AMUX, CYREG_PRT4_AMUX\r
+.set SCSI_Out_DBx__DB7__BIE, CYREG_PRT4_BIE\r
+.set SCSI_Out_DBx__DB7__BIT_MASK, CYREG_PRT4_BIT_MASK\r
+.set SCSI_Out_DBx__DB7__BYP, CYREG_PRT4_BYP\r
+.set SCSI_Out_DBx__DB7__CTL, CYREG_PRT4_CTL\r
+.set SCSI_Out_DBx__DB7__DM0, CYREG_PRT4_DM0\r
+.set SCSI_Out_DBx__DB7__DM1, CYREG_PRT4_DM1\r
+.set SCSI_Out_DBx__DB7__DM2, CYREG_PRT4_DM2\r
+.set SCSI_Out_DBx__DB7__DR, CYREG_PRT4_DR\r
+.set SCSI_Out_DBx__DB7__INP_DIS, CYREG_PRT4_INP_DIS\r
+.set SCSI_Out_DBx__DB7__INTTYPE, CYREG_PICU4_INTTYPE4\r
+.set SCSI_Out_DBx__DB7__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG\r
+.set SCSI_Out_DBx__DB7__LCD_EN, CYREG_PRT4_LCD_EN\r
+.set SCSI_Out_DBx__DB7__MASK, 0x10\r
+.set SCSI_Out_DBx__DB7__PC, CYREG_PRT4_PC4\r
+.set SCSI_Out_DBx__DB7__PORT, 4\r
+.set SCSI_Out_DBx__DB7__PRT, CYREG_PRT4_PRT\r
+.set SCSI_Out_DBx__DB7__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL\r
+.set SCSI_Out_DBx__DB7__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN\r
+.set SCSI_Out_DBx__DB7__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0\r
+.set SCSI_Out_DBx__DB7__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1\r
+.set SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0\r
+.set SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1\r
+.set SCSI_Out_DBx__DB7__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT\r
+.set SCSI_Out_DBx__DB7__PS, CYREG_PRT4_PS\r
+.set SCSI_Out_DBx__DB7__SHIFT, 4\r
+.set SCSI_Out_DBx__DB7__SLW, CYREG_PRT4_SLW\r
+\r
+/* SCSI_Parity_Error */\r
+.set SCSI_Parity_Error_sts_sts_reg__0__MASK, 0x01\r
+.set SCSI_Parity_Error_sts_sts_reg__0__POS, 0\r
+.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB01_02_ACTL\r
+.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB01_02_ST\r
+.set SCSI_Parity_Error_sts_sts_reg__MASK, 0x01\r
+.set SCSI_Parity_Error_sts_sts_reg__MASK_REG, CYREG_B0_UDB01_MSK\r
+.set SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB01_ACTL\r
+.set SCSI_Parity_Error_sts_sts_reg__STATUS_REG, CYREG_B0_UDB01_ST\r
+\r
+/* SCSI_RST_ISR */\r
+.set SCSI_RST_ISR__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
+.set SCSI_RST_ISR__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
+.set SCSI_RST_ISR__INTC_MASK, 0x02\r
+.set SCSI_RST_ISR__INTC_NUMBER, 1\r
+.set SCSI_RST_ISR__INTC_PRIOR_NUM, 7\r
+.set SCSI_RST_ISR__INTC_PRIOR_REG, CYREG_NVIC_PRI_1\r
+.set SCSI_RST_ISR__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
+.set SCSI_RST_ISR__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
+\r
+/* SCSI_RX_DMA */\r
+.set SCSI_RX_DMA__DRQ_CTL, CYREG_IDMUX_DRQ_CTL0\r
+.set SCSI_RX_DMA__DRQ_NUMBER, 0\r
+.set SCSI_RX_DMA__NUMBEROF_TDS, 0\r
+.set SCSI_RX_DMA__PRIORITY, 2\r
+.set SCSI_RX_DMA__TERMIN_EN, 0\r
+.set SCSI_RX_DMA__TERMIN_SEL, 0\r
+.set SCSI_RX_DMA__TERMOUT0_EN, 1\r
+.set SCSI_RX_DMA__TERMOUT0_SEL, 0\r
+.set SCSI_RX_DMA__TERMOUT1_EN, 0\r
+.set SCSI_RX_DMA__TERMOUT1_SEL, 0\r
+.set SCSI_RX_DMA_COMPLETE__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
+.set SCSI_RX_DMA_COMPLETE__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
+.set SCSI_RX_DMA_COMPLETE__INTC_MASK, 0x04\r
+.set SCSI_RX_DMA_COMPLETE__INTC_NUMBER, 2\r
+.set SCSI_RX_DMA_COMPLETE__INTC_PRIOR_NUM, 7\r
+.set SCSI_RX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_2\r
+.set SCSI_RX_DMA_COMPLETE__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
+.set SCSI_RX_DMA_COMPLETE__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
+\r
+/* SCSI_SEL_ISR */\r
+.set SCSI_SEL_ISR__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
+.set SCSI_SEL_ISR__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
+.set SCSI_SEL_ISR__INTC_MASK, 0x08\r
+.set SCSI_SEL_ISR__INTC_NUMBER, 3\r
+.set SCSI_SEL_ISR__INTC_PRIOR_NUM, 7\r
+.set SCSI_SEL_ISR__INTC_PRIOR_REG, CYREG_NVIC_PRI_3\r
+.set SCSI_SEL_ISR__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
+.set SCSI_SEL_ISR__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
+\r
+/* SCSI_TX_DMA */\r
+.set SCSI_TX_DMA__DRQ_CTL, CYREG_IDMUX_DRQ_CTL0\r
+.set SCSI_TX_DMA__DRQ_NUMBER, 1\r
+.set SCSI_TX_DMA__NUMBEROF_TDS, 0\r
+.set SCSI_TX_DMA__PRIORITY, 2\r
+.set SCSI_TX_DMA__TERMIN_EN, 0\r
+.set SCSI_TX_DMA__TERMIN_SEL, 0\r
+.set SCSI_TX_DMA__TERMOUT0_EN, 1\r
+.set SCSI_TX_DMA__TERMOUT0_SEL, 1\r
+.set SCSI_TX_DMA__TERMOUT1_EN, 0\r
+.set SCSI_TX_DMA__TERMOUT1_SEL, 0\r
+.set SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
+.set SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
+.set SCSI_TX_DMA_COMPLETE__INTC_MASK, 0x10\r
+.set SCSI_TX_DMA_COMPLETE__INTC_NUMBER, 4\r
+.set SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM, 7\r
+.set SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_4\r
+.set SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
+.set SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
+\r
+/* SDCard_BSPIM */\r
+.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB04_05_ACTL\r
+.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB04_05_CTL\r
+.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB04_05_CTL\r
+.set SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB04_05_CTL\r
+.set SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB04_05_CTL\r
+.set SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B1_UDB04_05_MSK\r
+.set SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB04_05_MSK\r
+.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB04_05_MSK\r
+.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB04_05_MSK\r
+.set SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B1_UDB04_ACTL\r
+.set SDCard_BSPIM_BitCounter__CONTROL_REG, CYREG_B1_UDB04_CTL\r
+.set SDCard_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B1_UDB04_ST_CTL\r
+.set SDCard_BSPIM_BitCounter__COUNT_REG, CYREG_B1_UDB04_CTL\r
+.set SDCard_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B1_UDB04_ST_CTL\r
+.set SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL\r
+.set SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL\r
+.set SDCard_BSPIM_BitCounter__PERIOD_REG, CYREG_B1_UDB04_MSK\r
+.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB04_05_ACTL\r
+.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B1_UDB04_05_ST\r
+.set SDCard_BSPIM_BitCounter_ST__MASK_REG, CYREG_B1_UDB04_MSK\r
+.set SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL\r
+.set SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL\r
+.set SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B1_UDB04_ACTL\r
+.set SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B1_UDB04_ST_CTL\r
+.set SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B1_UDB04_ST_CTL\r
+.set SDCard_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B1_UDB04_ST\r
+.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB08_09_ACTL\r
+.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB08_09_ST\r
+.set SDCard_BSPIM_RxStsReg__4__MASK, 0x10\r
+.set SDCard_BSPIM_RxStsReg__4__POS, 4\r
+.set SDCard_BSPIM_RxStsReg__5__MASK, 0x20\r
+.set SDCard_BSPIM_RxStsReg__5__POS, 5\r
+.set SDCard_BSPIM_RxStsReg__6__MASK, 0x40\r
+.set SDCard_BSPIM_RxStsReg__6__POS, 6\r
+.set SDCard_BSPIM_RxStsReg__MASK, 0x70\r
+.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B1_UDB08_MSK\r
+.set SDCard_BSPIM_RxStsReg__MASK_ST_AUX_CTL_REG, CYREG_B1_UDB08_MSK_ACTL\r
+.set SDCard_BSPIM_RxStsReg__PER_ST_AUX_CTL_REG, CYREG_B1_UDB08_MSK_ACTL\r
+.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB08_ACTL\r
+.set SDCard_BSPIM_RxStsReg__STATUS_CNT_REG, CYREG_B1_UDB08_ST_CTL\r
+.set SDCard_BSPIM_RxStsReg__STATUS_CONTROL_REG, CYREG_B1_UDB08_ST_CTL\r
+.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B1_UDB08_ST\r
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG, CYREG_B1_UDB04_05_A0\r
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG, CYREG_B1_UDB04_05_A1\r
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG, CYREG_B1_UDB04_05_D0\r
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG, CYREG_B1_UDB04_05_D1\r
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG, CYREG_B1_UDB04_05_ACTL\r
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG, CYREG_B1_UDB04_05_F0\r
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG, CYREG_B1_UDB04_05_F1\r
+.set SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG, CYREG_B1_UDB04_A0_A1\r
+.set SDCard_BSPIM_sR8_Dp_u0__A0_REG, CYREG_B1_UDB04_A0\r
+.set SDCard_BSPIM_sR8_Dp_u0__A1_REG, CYREG_B1_UDB04_A1\r
+.set SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG, CYREG_B1_UDB04_D0_D1\r
+.set SDCard_BSPIM_sR8_Dp_u0__D0_REG, CYREG_B1_UDB04_D0\r
+.set SDCard_BSPIM_sR8_Dp_u0__D1_REG, CYREG_B1_UDB04_D1\r
+.set SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG, CYREG_B1_UDB04_ACTL\r
+.set SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG, CYREG_B1_UDB04_F0_F1\r
+.set SDCard_BSPIM_sR8_Dp_u0__F0_REG, CYREG_B1_UDB04_F0\r
+.set SDCard_BSPIM_sR8_Dp_u0__F1_REG, CYREG_B1_UDB04_F1\r
+.set SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL\r
+.set SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL\r
+.set SDCard_BSPIM_TxStsReg__0__MASK, 0x01\r
+.set SDCard_BSPIM_TxStsReg__0__POS, 0\r
+.set SDCard_BSPIM_TxStsReg__1__MASK, 0x02\r
+.set SDCard_BSPIM_TxStsReg__1__POS, 1\r
+.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB07_08_ACTL\r
+.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB07_08_ST\r
+.set SDCard_BSPIM_TxStsReg__2__MASK, 0x04\r
+.set SDCard_BSPIM_TxStsReg__2__POS, 2\r
+.set SDCard_BSPIM_TxStsReg__3__MASK, 0x08\r
+.set SDCard_BSPIM_TxStsReg__3__POS, 3\r
+.set SDCard_BSPIM_TxStsReg__4__MASK, 0x10\r
+.set SDCard_BSPIM_TxStsReg__4__POS, 4\r
+.set SDCard_BSPIM_TxStsReg__MASK, 0x1F\r
+.set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B1_UDB07_MSK\r
+.set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB07_ACTL\r
+.set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B1_UDB07_ST\r
+\r
+/* SD_CD */\r
+.set SD_CD__0__INTTYPE, CYREG_PICU3_INTTYPE6\r
+.set SD_CD__0__MASK, 0x40\r
+.set SD_CD__0__PC, CYREG_PRT3_PC6\r
+.set SD_CD__0__PORT, 3\r
+.set SD_CD__0__SHIFT, 6\r
+.set SD_CD__AG, CYREG_PRT3_AG\r
+.set SD_CD__AMUX, CYREG_PRT3_AMUX\r
+.set SD_CD__BIE, CYREG_PRT3_BIE\r
+.set SD_CD__BIT_MASK, CYREG_PRT3_BIT_MASK\r
+.set SD_CD__BYP, CYREG_PRT3_BYP\r
+.set SD_CD__CTL, CYREG_PRT3_CTL\r
+.set SD_CD__DM0, CYREG_PRT3_DM0\r
+.set SD_CD__DM1, CYREG_PRT3_DM1\r
+.set SD_CD__DM2, CYREG_PRT3_DM2\r
+.set SD_CD__DR, CYREG_PRT3_DR\r
+.set SD_CD__INP_DIS, CYREG_PRT3_INP_DIS\r
+.set SD_CD__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU3_BASE\r
+.set SD_CD__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG\r
+.set SD_CD__LCD_EN, CYREG_PRT3_LCD_EN\r
+.set SD_CD__MASK, 0x40\r
+.set SD_CD__PORT, 3\r
+.set SD_CD__PRT, CYREG_PRT3_PRT\r
+.set SD_CD__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL\r
+.set SD_CD__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN\r
+.set SD_CD__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0\r
+.set SD_CD__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1\r
+.set SD_CD__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0\r
+.set SD_CD__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1\r
+.set SD_CD__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT\r
+.set SD_CD__PS, CYREG_PRT3_PS\r
+.set SD_CD__SHIFT, 6\r
+.set SD_CD__SLW, CYREG_PRT3_SLW\r
+\r
+/* SD_CS */\r
+.set SD_CS__0__INTTYPE, CYREG_PICU3_INTTYPE4\r
+.set SD_CS__0__MASK, 0x10\r
+.set SD_CS__0__PC, CYREG_PRT3_PC4\r
+.set SD_CS__0__PORT, 3\r
+.set SD_CS__0__SHIFT, 4\r
+.set SD_CS__AG, CYREG_PRT3_AG\r
+.set SD_CS__AMUX, CYREG_PRT3_AMUX\r
+.set SD_CS__BIE, CYREG_PRT3_BIE\r
+.set SD_CS__BIT_MASK, CYREG_PRT3_BIT_MASK\r
+.set SD_CS__BYP, CYREG_PRT3_BYP\r
+.set SD_CS__CTL, CYREG_PRT3_CTL\r
+.set SD_CS__DM0, CYREG_PRT3_DM0\r
+.set SD_CS__DM1, CYREG_PRT3_DM1\r
+.set SD_CS__DM2, CYREG_PRT3_DM2\r
+.set SD_CS__DR, CYREG_PRT3_DR\r
+.set SD_CS__INP_DIS, CYREG_PRT3_INP_DIS\r
+.set SD_CS__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU3_BASE\r
+.set SD_CS__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG\r
+.set SD_CS__LCD_EN, CYREG_PRT3_LCD_EN\r
+.set SD_CS__MASK, 0x10\r
+.set SD_CS__PORT, 3\r
+.set SD_CS__PRT, CYREG_PRT3_PRT\r
+.set SD_CS__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL\r
+.set SD_CS__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN\r
+.set SD_CS__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0\r
+.set SD_CS__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1\r
+.set SD_CS__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0\r
+.set SD_CS__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1\r
+.set SD_CS__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT\r
+.set SD_CS__PS, CYREG_PRT3_PS\r
+.set SD_CS__SHIFT, 4\r
+.set SD_CS__SLW, CYREG_PRT3_SLW\r
+\r
+/* SD_DAT1 */\r
+.set SD_DAT1__0__INTTYPE, CYREG_PICU3_INTTYPE0\r
+.set SD_DAT1__0__MASK, 0x01\r
+.set SD_DAT1__0__PC, CYREG_PRT3_PC0\r
+.set SD_DAT1__0__PORT, 3\r
+.set SD_DAT1__0__SHIFT, 0\r
+.set SD_DAT1__AG, CYREG_PRT3_AG\r
+.set SD_DAT1__AMUX, CYREG_PRT3_AMUX\r
+.set SD_DAT1__BIE, CYREG_PRT3_BIE\r
+.set SD_DAT1__BIT_MASK, CYREG_PRT3_BIT_MASK\r
+.set SD_DAT1__BYP, CYREG_PRT3_BYP\r
+.set SD_DAT1__CTL, CYREG_PRT3_CTL\r
+.set SD_DAT1__DM0, CYREG_PRT3_DM0\r
+.set SD_DAT1__DM1, CYREG_PRT3_DM1\r
+.set SD_DAT1__DM2, CYREG_PRT3_DM2\r
+.set SD_DAT1__DR, CYREG_PRT3_DR\r
+.set SD_DAT1__INP_DIS, CYREG_PRT3_INP_DIS\r
+.set SD_DAT1__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU3_BASE\r
+.set SD_DAT1__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG\r
+.set SD_DAT1__LCD_EN, CYREG_PRT3_LCD_EN\r
+.set SD_DAT1__MASK, 0x01\r
+.set SD_DAT1__PORT, 3\r
+.set SD_DAT1__PRT, CYREG_PRT3_PRT\r
+.set SD_DAT1__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL\r
+.set SD_DAT1__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN\r
+.set SD_DAT1__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0\r
+.set SD_DAT1__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1\r
+.set SD_DAT1__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0\r
+.set SD_DAT1__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1\r
+.set SD_DAT1__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT\r
+.set SD_DAT1__PS, CYREG_PRT3_PS\r
+.set SD_DAT1__SHIFT, 0\r
+.set SD_DAT1__SLW, CYREG_PRT3_SLW\r
+\r
+/* SD_DAT2 */\r
+.set SD_DAT2__0__INTTYPE, CYREG_PICU3_INTTYPE5\r
+.set SD_DAT2__0__MASK, 0x20\r
+.set SD_DAT2__0__PC, CYREG_PRT3_PC5\r
+.set SD_DAT2__0__PORT, 3\r
+.set SD_DAT2__0__SHIFT, 5\r
+.set SD_DAT2__AG, CYREG_PRT3_AG\r
+.set SD_DAT2__AMUX, CYREG_PRT3_AMUX\r
+.set SD_DAT2__BIE, CYREG_PRT3_BIE\r
+.set SD_DAT2__BIT_MASK, CYREG_PRT3_BIT_MASK\r
+.set SD_DAT2__BYP, CYREG_PRT3_BYP\r
+.set SD_DAT2__CTL, CYREG_PRT3_CTL\r
+.set SD_DAT2__DM0, CYREG_PRT3_DM0\r
+.set SD_DAT2__DM1, CYREG_PRT3_DM1\r
+.set SD_DAT2__DM2, CYREG_PRT3_DM2\r
+.set SD_DAT2__DR, CYREG_PRT3_DR\r
+.set SD_DAT2__INP_DIS, CYREG_PRT3_INP_DIS\r
+.set SD_DAT2__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU3_BASE\r
+.set SD_DAT2__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG\r
+.set SD_DAT2__LCD_EN, CYREG_PRT3_LCD_EN\r
+.set SD_DAT2__MASK, 0x20\r
+.set SD_DAT2__PORT, 3\r
+.set SD_DAT2__PRT, CYREG_PRT3_PRT\r
+.set SD_DAT2__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL\r
+.set SD_DAT2__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN\r
+.set SD_DAT2__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0\r
+.set SD_DAT2__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1\r
+.set SD_DAT2__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0\r
+.set SD_DAT2__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1\r
+.set SD_DAT2__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT\r
+.set SD_DAT2__PS, CYREG_PRT3_PS\r
+.set SD_DAT2__SHIFT, 5\r
+.set SD_DAT2__SLW, CYREG_PRT3_SLW\r
+\r
+/* SD_Data_Clk */\r
+.set SD_Data_Clk__CFG0, CYREG_CLKDIST_DCFG0_CFG0\r
+.set SD_Data_Clk__CFG1, CYREG_CLKDIST_DCFG0_CFG1\r
+.set SD_Data_Clk__CFG2, CYREG_CLKDIST_DCFG0_CFG2\r
+.set SD_Data_Clk__CFG2_SRC_SEL_MASK, 0x07\r
+.set SD_Data_Clk__INDEX, 0x00\r
+.set SD_Data_Clk__PM_ACT_CFG, CYREG_PM_ACT_CFG2\r
+.set SD_Data_Clk__PM_ACT_MSK, 0x01\r
+.set SD_Data_Clk__PM_STBY_CFG, CYREG_PM_STBY_CFG2\r
+.set SD_Data_Clk__PM_STBY_MSK, 0x01\r
+\r
+/* SD_MISO */\r
+.set SD_MISO__0__INTTYPE, CYREG_PICU3_INTTYPE1\r
+.set SD_MISO__0__MASK, 0x02\r
+.set SD_MISO__0__PC, CYREG_PRT3_PC1\r
+.set SD_MISO__0__PORT, 3\r
+.set SD_MISO__0__SHIFT, 1\r
+.set SD_MISO__AG, CYREG_PRT3_AG\r
+.set SD_MISO__AMUX, CYREG_PRT3_AMUX\r
+.set SD_MISO__BIE, CYREG_PRT3_BIE\r
+.set SD_MISO__BIT_MASK, CYREG_PRT3_BIT_MASK\r
+.set SD_MISO__BYP, CYREG_PRT3_BYP\r
+.set SD_MISO__CTL, CYREG_PRT3_CTL\r
+.set SD_MISO__DM0, CYREG_PRT3_DM0\r
+.set SD_MISO__DM1, CYREG_PRT3_DM1\r
+.set SD_MISO__DM2, CYREG_PRT3_DM2\r
+.set SD_MISO__DR, CYREG_PRT3_DR\r
+.set SD_MISO__INP_DIS, CYREG_PRT3_INP_DIS\r
+.set SD_MISO__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU3_BASE\r
+.set SD_MISO__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG\r
+.set SD_MISO__LCD_EN, CYREG_PRT3_LCD_EN\r
+.set SD_MISO__MASK, 0x02\r
+.set SD_MISO__PORT, 3\r
+.set SD_MISO__PRT, CYREG_PRT3_PRT\r
+.set SD_MISO__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL\r
+.set SD_MISO__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN\r
+.set SD_MISO__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0\r
+.set SD_MISO__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1\r
+.set SD_MISO__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0\r
+.set SD_MISO__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1\r
+.set SD_MISO__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT\r
+.set SD_MISO__PS, CYREG_PRT3_PS\r
+.set SD_MISO__SHIFT, 1\r
+.set SD_MISO__SLW, CYREG_PRT3_SLW\r
+\r
+/* SD_MOSI */\r
+.set SD_MOSI__0__INTTYPE, CYREG_PICU3_INTTYPE3\r
+.set SD_MOSI__0__MASK, 0x08\r
+.set SD_MOSI__0__PC, CYREG_PRT3_PC3\r
+.set SD_MOSI__0__PORT, 3\r
+.set SD_MOSI__0__SHIFT, 3\r
+.set SD_MOSI__AG, CYREG_PRT3_AG\r
+.set SD_MOSI__AMUX, CYREG_PRT3_AMUX\r
+.set SD_MOSI__BIE, CYREG_PRT3_BIE\r
+.set SD_MOSI__BIT_MASK, CYREG_PRT3_BIT_MASK\r
+.set SD_MOSI__BYP, CYREG_PRT3_BYP\r
+.set SD_MOSI__CTL, CYREG_PRT3_CTL\r
+.set SD_MOSI__DM0, CYREG_PRT3_DM0\r
+.set SD_MOSI__DM1, CYREG_PRT3_DM1\r
+.set SD_MOSI__DM2, CYREG_PRT3_DM2\r
+.set SD_MOSI__DR, CYREG_PRT3_DR\r
+.set SD_MOSI__INP_DIS, CYREG_PRT3_INP_DIS\r
+.set SD_MOSI__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU3_BASE\r
+.set SD_MOSI__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG\r
+.set SD_MOSI__LCD_EN, CYREG_PRT3_LCD_EN\r
+.set SD_MOSI__MASK, 0x08\r
+.set SD_MOSI__PORT, 3\r
+.set SD_MOSI__PRT, CYREG_PRT3_PRT\r
+.set SD_MOSI__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL\r
+.set SD_MOSI__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN\r
+.set SD_MOSI__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0\r
+.set SD_MOSI__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1\r
+.set SD_MOSI__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0\r
+.set SD_MOSI__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1\r
+.set SD_MOSI__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT\r
+.set SD_MOSI__PS, CYREG_PRT3_PS\r
+.set SD_MOSI__SHIFT, 3\r
+.set SD_MOSI__SLW, CYREG_PRT3_SLW\r
+\r
+/* SD_RX_DMA */\r
+.set SD_RX_DMA__DRQ_CTL, CYREG_IDMUX_DRQ_CTL0\r
+.set SD_RX_DMA__DRQ_NUMBER, 2\r
+.set SD_RX_DMA__NUMBEROF_TDS, 0\r
+.set SD_RX_DMA__PRIORITY, 0\r
+.set SD_RX_DMA__TERMIN_EN, 0\r
+.set SD_RX_DMA__TERMIN_SEL, 0\r
+.set SD_RX_DMA__TERMOUT0_EN, 1\r
+.set SD_RX_DMA__TERMOUT0_SEL, 2\r
+.set SD_RX_DMA__TERMOUT1_EN, 0\r
+.set SD_RX_DMA__TERMOUT1_SEL, 0\r
+.set SD_RX_DMA_COMPLETE__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
+.set SD_RX_DMA_COMPLETE__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
+.set SD_RX_DMA_COMPLETE__INTC_MASK, 0x20\r
+.set SD_RX_DMA_COMPLETE__INTC_NUMBER, 5\r
+.set SD_RX_DMA_COMPLETE__INTC_PRIOR_NUM, 7\r
+.set SD_RX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_5\r
+.set SD_RX_DMA_COMPLETE__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
+.set SD_RX_DMA_COMPLETE__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
+\r
+/* SD_SCK */\r
+.set SD_SCK__0__INTTYPE, CYREG_PICU3_INTTYPE2\r
+.set SD_SCK__0__MASK, 0x04\r
+.set SD_SCK__0__PC, CYREG_PRT3_PC2\r
+.set SD_SCK__0__PORT, 3\r
+.set SD_SCK__0__SHIFT, 2\r
+.set SD_SCK__AG, CYREG_PRT3_AG\r
+.set SD_SCK__AMUX, CYREG_PRT3_AMUX\r
+.set SD_SCK__BIE, CYREG_PRT3_BIE\r
+.set SD_SCK__BIT_MASK, CYREG_PRT3_BIT_MASK\r
+.set SD_SCK__BYP, CYREG_PRT3_BYP\r
+.set SD_SCK__CTL, CYREG_PRT3_CTL\r
+.set SD_SCK__DM0, CYREG_PRT3_DM0\r
+.set SD_SCK__DM1, CYREG_PRT3_DM1\r
+.set SD_SCK__DM2, CYREG_PRT3_DM2\r
+.set SD_SCK__DR, CYREG_PRT3_DR\r
+.set SD_SCK__INP_DIS, CYREG_PRT3_INP_DIS\r
+.set SD_SCK__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU3_BASE\r
+.set SD_SCK__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG\r
+.set SD_SCK__LCD_EN, CYREG_PRT3_LCD_EN\r
+.set SD_SCK__MASK, 0x04\r
+.set SD_SCK__PORT, 3\r
+.set SD_SCK__PRT, CYREG_PRT3_PRT\r
+.set SD_SCK__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL\r
+.set SD_SCK__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN\r
+.set SD_SCK__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0\r
+.set SD_SCK__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1\r
+.set SD_SCK__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0\r
+.set SD_SCK__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1\r
+.set SD_SCK__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT\r
+.set SD_SCK__PS, CYREG_PRT3_PS\r
+.set SD_SCK__SHIFT, 2\r
+.set SD_SCK__SLW, CYREG_PRT3_SLW\r
+\r
+/* SD_TX_DMA */\r
+.set SD_TX_DMA__DRQ_CTL, CYREG_IDMUX_DRQ_CTL0\r
+.set SD_TX_DMA__DRQ_NUMBER, 3\r
+.set SD_TX_DMA__NUMBEROF_TDS, 0\r
+.set SD_TX_DMA__PRIORITY, 1\r
+.set SD_TX_DMA__TERMIN_EN, 0\r
+.set SD_TX_DMA__TERMIN_SEL, 0\r
+.set SD_TX_DMA__TERMOUT0_EN, 1\r
+.set SD_TX_DMA__TERMOUT0_SEL, 3\r
+.set SD_TX_DMA__TERMOUT1_EN, 0\r
+.set SD_TX_DMA__TERMOUT1_SEL, 0\r
+.set SD_TX_DMA_COMPLETE__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
+.set SD_TX_DMA_COMPLETE__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
+.set SD_TX_DMA_COMPLETE__INTC_MASK, 0x40\r
+.set SD_TX_DMA_COMPLETE__INTC_NUMBER, 6\r
+.set SD_TX_DMA_COMPLETE__INTC_PRIOR_NUM, 7\r
+.set SD_TX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_6\r
+.set SD_TX_DMA_COMPLETE__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
+.set SD_TX_DMA_COMPLETE__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
+\r
+/* USBFS */\r
+.set USBFS_arb_int__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
+.set USBFS_arb_int__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
+.set USBFS_arb_int__INTC_MASK, 0x400000\r
+.set USBFS_arb_int__INTC_NUMBER, 22\r
+.set USBFS_arb_int__INTC_PRIOR_NUM, 6\r
+.set USBFS_arb_int__INTC_PRIOR_REG, CYREG_NVIC_PRI_22\r
+.set USBFS_arb_int__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
+.set USBFS_arb_int__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
+.set USBFS_bus_reset__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
+.set USBFS_bus_reset__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
+.set USBFS_bus_reset__INTC_MASK, 0x800000\r
+.set USBFS_bus_reset__INTC_NUMBER, 23\r
+.set USBFS_bus_reset__INTC_PRIOR_NUM, 7\r
+.set USBFS_bus_reset__INTC_PRIOR_REG, CYREG_NVIC_PRI_23\r
+.set USBFS_bus_reset__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
+.set USBFS_bus_reset__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
+.set USBFS_Dm__0__INTTYPE, CYREG_PICU15_INTTYPE7\r
+.set USBFS_Dm__0__MASK, 0x80\r
+.set USBFS_Dm__0__PC, CYREG_IO_PC_PRT15_7_6_PC1\r
+.set USBFS_Dm__0__PORT, 15\r
+.set USBFS_Dm__0__SHIFT, 7\r
+.set USBFS_Dm__AG, CYREG_PRT15_AG\r
+.set USBFS_Dm__AMUX, CYREG_PRT15_AMUX\r
+.set USBFS_Dm__BIE, CYREG_PRT15_BIE\r
+.set USBFS_Dm__BIT_MASK, CYREG_PRT15_BIT_MASK\r
+.set USBFS_Dm__BYP, CYREG_PRT15_BYP\r
+.set USBFS_Dm__CTL, CYREG_PRT15_CTL\r
+.set USBFS_Dm__DM0, CYREG_PRT15_DM0\r
+.set USBFS_Dm__DM1, CYREG_PRT15_DM1\r
+.set USBFS_Dm__DM2, CYREG_PRT15_DM2\r
+.set USBFS_Dm__DR, CYREG_PRT15_DR\r
+.set USBFS_Dm__INP_DIS, CYREG_PRT15_INP_DIS\r
+.set USBFS_Dm__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU15_BASE\r
+.set USBFS_Dm__LCD_COM_SEG, CYREG_PRT15_LCD_COM_SEG\r
+.set USBFS_Dm__LCD_EN, CYREG_PRT15_LCD_EN\r
+.set USBFS_Dm__MASK, 0x80\r
+.set USBFS_Dm__PORT, 15\r
+.set USBFS_Dm__PRT, CYREG_PRT15_PRT\r
+.set USBFS_Dm__PRTDSI__CAPS_SEL, CYREG_PRT15_CAPS_SEL\r
+.set USBFS_Dm__PRTDSI__DBL_SYNC_IN, CYREG_PRT15_DBL_SYNC_IN\r
+.set USBFS_Dm__PRTDSI__OE_SEL0, CYREG_PRT15_OE_SEL0\r
+.set USBFS_Dm__PRTDSI__OE_SEL1, CYREG_PRT15_OE_SEL1\r
+.set USBFS_Dm__PRTDSI__OUT_SEL0, CYREG_PRT15_OUT_SEL0\r
+.set USBFS_Dm__PRTDSI__OUT_SEL1, CYREG_PRT15_OUT_SEL1\r
+.set USBFS_Dm__PRTDSI__SYNC_OUT, CYREG_PRT15_SYNC_OUT\r
+.set USBFS_Dm__PS, CYREG_PRT15_PS\r
+.set USBFS_Dm__SHIFT, 7\r
+.set USBFS_Dm__SLW, CYREG_PRT15_SLW\r
+.set USBFS_Dp__0__INTTYPE, CYREG_PICU15_INTTYPE6\r
+.set USBFS_Dp__0__MASK, 0x40\r
+.set USBFS_Dp__0__PC, CYREG_IO_PC_PRT15_7_6_PC0\r
+.set USBFS_Dp__0__PORT, 15\r
+.set USBFS_Dp__0__SHIFT, 6\r
+.set USBFS_Dp__AG, CYREG_PRT15_AG\r
+.set USBFS_Dp__AMUX, CYREG_PRT15_AMUX\r
+.set USBFS_Dp__BIE, CYREG_PRT15_BIE\r
+.set USBFS_Dp__BIT_MASK, CYREG_PRT15_BIT_MASK\r
+.set USBFS_Dp__BYP, CYREG_PRT15_BYP\r
+.set USBFS_Dp__CTL, CYREG_PRT15_CTL\r
+.set USBFS_Dp__DM0, CYREG_PRT15_DM0\r
+.set USBFS_Dp__DM1, CYREG_PRT15_DM1\r
+.set USBFS_Dp__DM2, CYREG_PRT15_DM2\r
+.set USBFS_Dp__DR, CYREG_PRT15_DR\r
+.set USBFS_Dp__INP_DIS, CYREG_PRT15_INP_DIS\r
+.set USBFS_Dp__INTSTAT, CYREG_PICU15_INTSTAT\r
+.set USBFS_Dp__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU15_BASE\r
+.set USBFS_Dp__LCD_COM_SEG, CYREG_PRT15_LCD_COM_SEG\r
+.set USBFS_Dp__LCD_EN, CYREG_PRT15_LCD_EN\r
+.set USBFS_Dp__MASK, 0x40\r
+.set USBFS_Dp__PORT, 15\r
+.set USBFS_Dp__PRT, CYREG_PRT15_PRT\r
+.set USBFS_Dp__PRTDSI__CAPS_SEL, CYREG_PRT15_CAPS_SEL\r
+.set USBFS_Dp__PRTDSI__DBL_SYNC_IN, CYREG_PRT15_DBL_SYNC_IN\r
+.set USBFS_Dp__PRTDSI__OE_SEL0, CYREG_PRT15_OE_SEL0\r
+.set USBFS_Dp__PRTDSI__OE_SEL1, CYREG_PRT15_OE_SEL1\r
+.set USBFS_Dp__PRTDSI__OUT_SEL0, CYREG_PRT15_OUT_SEL0\r
+.set USBFS_Dp__PRTDSI__OUT_SEL1, CYREG_PRT15_OUT_SEL1\r
+.set USBFS_Dp__PRTDSI__SYNC_OUT, CYREG_PRT15_SYNC_OUT\r
+.set USBFS_Dp__PS, CYREG_PRT15_PS\r
+.set USBFS_Dp__SHIFT, 6\r
+.set USBFS_Dp__SLW, CYREG_PRT15_SLW\r
+.set USBFS_Dp__SNAP, CYREG_PICU_15_SNAP_15\r
+.set USBFS_dp_int__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
+.set USBFS_dp_int__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
+.set USBFS_dp_int__INTC_MASK, 0x1000\r
+.set USBFS_dp_int__INTC_NUMBER, 12\r
+.set USBFS_dp_int__INTC_PRIOR_NUM, 7\r
+.set USBFS_dp_int__INTC_PRIOR_REG, CYREG_NVIC_PRI_12\r
+.set USBFS_dp_int__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
+.set USBFS_dp_int__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
+.set USBFS_ep_0__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
+.set USBFS_ep_0__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
+.set USBFS_ep_0__INTC_MASK, 0x1000000\r
+.set USBFS_ep_0__INTC_NUMBER, 24\r
+.set USBFS_ep_0__INTC_PRIOR_NUM, 7\r
+.set USBFS_ep_0__INTC_PRIOR_REG, CYREG_NVIC_PRI_24\r
+.set USBFS_ep_0__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
+.set USBFS_ep_0__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
+.set USBFS_ep_1__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
+.set USBFS_ep_1__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
+.set USBFS_ep_1__INTC_MASK, 0x80\r
+.set USBFS_ep_1__INTC_NUMBER, 7\r
+.set USBFS_ep_1__INTC_PRIOR_NUM, 7\r
+.set USBFS_ep_1__INTC_PRIOR_REG, CYREG_NVIC_PRI_7\r
+.set USBFS_ep_1__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
+.set USBFS_ep_1__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
+.set USBFS_ep_2__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
+.set USBFS_ep_2__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
+.set USBFS_ep_2__INTC_MASK, 0x100\r
+.set USBFS_ep_2__INTC_NUMBER, 8\r
+.set USBFS_ep_2__INTC_PRIOR_NUM, 7\r
+.set USBFS_ep_2__INTC_PRIOR_REG, CYREG_NVIC_PRI_8\r
+.set USBFS_ep_2__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
+.set USBFS_ep_2__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
+.set USBFS_ep_3__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
+.set USBFS_ep_3__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
+.set USBFS_ep_3__INTC_MASK, 0x200\r
+.set USBFS_ep_3__INTC_NUMBER, 9\r
+.set USBFS_ep_3__INTC_PRIOR_NUM, 7\r
+.set USBFS_ep_3__INTC_PRIOR_REG, CYREG_NVIC_PRI_9\r
+.set USBFS_ep_3__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
+.set USBFS_ep_3__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
+.set USBFS_ep_4__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
+.set USBFS_ep_4__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
+.set USBFS_ep_4__INTC_MASK, 0x400\r
+.set USBFS_ep_4__INTC_NUMBER, 10\r
+.set USBFS_ep_4__INTC_PRIOR_NUM, 7\r
+.set USBFS_ep_4__INTC_PRIOR_REG, CYREG_NVIC_PRI_10\r
+.set USBFS_ep_4__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
+.set USBFS_ep_4__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
+.set USBFS_sof_int__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
+.set USBFS_sof_int__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
+.set USBFS_sof_int__INTC_MASK, 0x200000\r
+.set USBFS_sof_int__INTC_NUMBER, 21\r
+.set USBFS_sof_int__INTC_PRIOR_NUM, 7\r
+.set USBFS_sof_int__INTC_PRIOR_REG, CYREG_NVIC_PRI_21\r
+.set USBFS_sof_int__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
+.set USBFS_sof_int__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
+.set USBFS_USB__ARB_CFG, CYREG_USB_ARB_CFG\r
+.set USBFS_USB__ARB_EP1_CFG, CYREG_USB_ARB_EP1_CFG\r
+.set USBFS_USB__ARB_EP1_INT_EN, CYREG_USB_ARB_EP1_INT_EN\r
+.set USBFS_USB__ARB_EP1_SR, CYREG_USB_ARB_EP1_SR\r
+.set USBFS_USB__ARB_EP2_CFG, CYREG_USB_ARB_EP2_CFG\r
+.set USBFS_USB__ARB_EP2_INT_EN, CYREG_USB_ARB_EP2_INT_EN\r
+.set USBFS_USB__ARB_EP2_SR, CYREG_USB_ARB_EP2_SR\r
+.set USBFS_USB__ARB_EP3_CFG, CYREG_USB_ARB_EP3_CFG\r
+.set USBFS_USB__ARB_EP3_INT_EN, CYREG_USB_ARB_EP3_INT_EN\r
+.set USBFS_USB__ARB_EP3_SR, CYREG_USB_ARB_EP3_SR\r
+.set USBFS_USB__ARB_EP4_CFG, CYREG_USB_ARB_EP4_CFG\r
+.set USBFS_USB__ARB_EP4_INT_EN, CYREG_USB_ARB_EP4_INT_EN\r
+.set USBFS_USB__ARB_EP4_SR, CYREG_USB_ARB_EP4_SR\r
+.set USBFS_USB__ARB_EP5_CFG, CYREG_USB_ARB_EP5_CFG\r
+.set USBFS_USB__ARB_EP5_INT_EN, CYREG_USB_ARB_EP5_INT_EN\r
+.set USBFS_USB__ARB_EP5_SR, CYREG_USB_ARB_EP5_SR\r
+.set USBFS_USB__ARB_EP6_CFG, CYREG_USB_ARB_EP6_CFG\r
+.set USBFS_USB__ARB_EP6_INT_EN, CYREG_USB_ARB_EP6_INT_EN\r
+.set USBFS_USB__ARB_EP6_SR, CYREG_USB_ARB_EP6_SR\r
+.set USBFS_USB__ARB_EP7_CFG, CYREG_USB_ARB_EP7_CFG\r
+.set USBFS_USB__ARB_EP7_INT_EN, CYREG_USB_ARB_EP7_INT_EN\r
+.set USBFS_USB__ARB_EP7_SR, CYREG_USB_ARB_EP7_SR\r
+.set USBFS_USB__ARB_EP8_CFG, CYREG_USB_ARB_EP8_CFG\r
+.set USBFS_USB__ARB_EP8_INT_EN, CYREG_USB_ARB_EP8_INT_EN\r
+.set USBFS_USB__ARB_EP8_SR, CYREG_USB_ARB_EP8_SR\r
+.set USBFS_USB__ARB_INT_EN, CYREG_USB_ARB_INT_EN\r
+.set USBFS_USB__ARB_INT_SR, CYREG_USB_ARB_INT_SR\r
+.set USBFS_USB__ARB_RW1_DR, CYREG_USB_ARB_RW1_DR\r
+.set USBFS_USB__ARB_RW1_RA, CYREG_USB_ARB_RW1_RA\r
+.set USBFS_USB__ARB_RW1_RA_MSB, CYREG_USB_ARB_RW1_RA_MSB\r
+.set USBFS_USB__ARB_RW1_WA, CYREG_USB_ARB_RW1_WA\r
+.set USBFS_USB__ARB_RW1_WA_MSB, CYREG_USB_ARB_RW1_WA_MSB\r
+.set USBFS_USB__ARB_RW2_DR, CYREG_USB_ARB_RW2_DR\r
+.set USBFS_USB__ARB_RW2_RA, CYREG_USB_ARB_RW2_RA\r
+.set USBFS_USB__ARB_RW2_RA_MSB, CYREG_USB_ARB_RW2_RA_MSB\r
+.set USBFS_USB__ARB_RW2_WA, CYREG_USB_ARB_RW2_WA\r
+.set USBFS_USB__ARB_RW2_WA_MSB, CYREG_USB_ARB_RW2_WA_MSB\r
+.set USBFS_USB__ARB_RW3_DR, CYREG_USB_ARB_RW3_DR\r
+.set USBFS_USB__ARB_RW3_RA, CYREG_USB_ARB_RW3_RA\r
+.set USBFS_USB__ARB_RW3_RA_MSB, CYREG_USB_ARB_RW3_RA_MSB\r
+.set USBFS_USB__ARB_RW3_WA, CYREG_USB_ARB_RW3_WA\r
+.set USBFS_USB__ARB_RW3_WA_MSB, CYREG_USB_ARB_RW3_WA_MSB\r
+.set USBFS_USB__ARB_RW4_DR, CYREG_USB_ARB_RW4_DR\r
+.set USBFS_USB__ARB_RW4_RA, CYREG_USB_ARB_RW4_RA\r
+.set USBFS_USB__ARB_RW4_RA_MSB, CYREG_USB_ARB_RW4_RA_MSB\r
+.set USBFS_USB__ARB_RW4_WA, CYREG_USB_ARB_RW4_WA\r
+.set USBFS_USB__ARB_RW4_WA_MSB, CYREG_USB_ARB_RW4_WA_MSB\r
+.set USBFS_USB__ARB_RW5_DR, CYREG_USB_ARB_RW5_DR\r
+.set USBFS_USB__ARB_RW5_RA, CYREG_USB_ARB_RW5_RA\r
+.set USBFS_USB__ARB_RW5_RA_MSB, CYREG_USB_ARB_RW5_RA_MSB\r
+.set USBFS_USB__ARB_RW5_WA, CYREG_USB_ARB_RW5_WA\r
+.set USBFS_USB__ARB_RW5_WA_MSB, CYREG_USB_ARB_RW5_WA_MSB\r
+.set USBFS_USB__ARB_RW6_DR, CYREG_USB_ARB_RW6_DR\r
+.set USBFS_USB__ARB_RW6_RA, CYREG_USB_ARB_RW6_RA\r
+.set USBFS_USB__ARB_RW6_RA_MSB, CYREG_USB_ARB_RW6_RA_MSB\r
+.set USBFS_USB__ARB_RW6_WA, CYREG_USB_ARB_RW6_WA\r
+.set USBFS_USB__ARB_RW6_WA_MSB, CYREG_USB_ARB_RW6_WA_MSB\r
+.set USBFS_USB__ARB_RW7_DR, CYREG_USB_ARB_RW7_DR\r
+.set USBFS_USB__ARB_RW7_RA, CYREG_USB_ARB_RW7_RA\r
+.set USBFS_USB__ARB_RW7_RA_MSB, CYREG_USB_ARB_RW7_RA_MSB\r
+.set USBFS_USB__ARB_RW7_WA, CYREG_USB_ARB_RW7_WA\r
+.set USBFS_USB__ARB_RW7_WA_MSB, CYREG_USB_ARB_RW7_WA_MSB\r
+.set USBFS_USB__ARB_RW8_DR, CYREG_USB_ARB_RW8_DR\r
+.set USBFS_USB__ARB_RW8_RA, CYREG_USB_ARB_RW8_RA\r
+.set USBFS_USB__ARB_RW8_RA_MSB, CYREG_USB_ARB_RW8_RA_MSB\r
+.set USBFS_USB__ARB_RW8_WA, CYREG_USB_ARB_RW8_WA\r
+.set USBFS_USB__ARB_RW8_WA_MSB, CYREG_USB_ARB_RW8_WA_MSB\r
+.set USBFS_USB__BUF_SIZE, CYREG_USB_BUF_SIZE\r
+.set USBFS_USB__BUS_RST_CNT, CYREG_USB_BUS_RST_CNT\r
+.set USBFS_USB__CR0, CYREG_USB_CR0\r
+.set USBFS_USB__CR1, CYREG_USB_CR1\r
+.set USBFS_USB__CWA, CYREG_USB_CWA\r
+.set USBFS_USB__CWA_MSB, CYREG_USB_CWA_MSB\r
+.set USBFS_USB__DMA_THRES, CYREG_USB_DMA_THRES\r
+.set USBFS_USB__DMA_THRES_MSB, CYREG_USB_DMA_THRES_MSB\r
+.set USBFS_USB__DYN_RECONFIG, CYREG_USB_DYN_RECONFIG\r
+.set USBFS_USB__EP_ACTIVE, CYREG_USB_EP_ACTIVE\r
+.set USBFS_USB__EP_TYPE, CYREG_USB_EP_TYPE\r
+.set USBFS_USB__EP0_CNT, CYREG_USB_EP0_CNT\r
+.set USBFS_USB__EP0_CR, CYREG_USB_EP0_CR\r
+.set USBFS_USB__EP0_DR0, CYREG_USB_EP0_DR0\r
+.set USBFS_USB__EP0_DR1, CYREG_USB_EP0_DR1\r
+.set USBFS_USB__EP0_DR2, CYREG_USB_EP0_DR2\r
+.set USBFS_USB__EP0_DR3, CYREG_USB_EP0_DR3\r
+.set USBFS_USB__EP0_DR4, CYREG_USB_EP0_DR4\r
+.set USBFS_USB__EP0_DR5, CYREG_USB_EP0_DR5\r
+.set USBFS_USB__EP0_DR6, CYREG_USB_EP0_DR6\r
+.set USBFS_USB__EP0_DR7, CYREG_USB_EP0_DR7\r
+.set USBFS_USB__MEM_DATA, CYREG_USB_MEM_DATA_MBASE\r
+.set USBFS_USB__PM_ACT_CFG, CYREG_PM_ACT_CFG5\r
+.set USBFS_USB__PM_ACT_MSK, 0x01\r
+.set USBFS_USB__PM_STBY_CFG, CYREG_PM_STBY_CFG5\r
+.set USBFS_USB__PM_STBY_MSK, 0x01\r
+.set USBFS_USB__SIE_EP_INT_EN, CYREG_USB_SIE_EP_INT_EN\r
+.set USBFS_USB__SIE_EP_INT_SR, CYREG_USB_SIE_EP_INT_SR\r
+.set USBFS_USB__SIE_EP1_CNT0, CYREG_USB_SIE_EP1_CNT0\r
+.set USBFS_USB__SIE_EP1_CNT1, CYREG_USB_SIE_EP1_CNT1\r
+.set USBFS_USB__SIE_EP1_CR0, CYREG_USB_SIE_EP1_CR0\r
+.set USBFS_USB__SIE_EP2_CNT0, CYREG_USB_SIE_EP2_CNT0\r
+.set USBFS_USB__SIE_EP2_CNT1, CYREG_USB_SIE_EP2_CNT1\r
+.set USBFS_USB__SIE_EP2_CR0, CYREG_USB_SIE_EP2_CR0\r
+.set USBFS_USB__SIE_EP3_CNT0, CYREG_USB_SIE_EP3_CNT0\r
+.set USBFS_USB__SIE_EP3_CNT1, CYREG_USB_SIE_EP3_CNT1\r
+.set USBFS_USB__SIE_EP3_CR0, CYREG_USB_SIE_EP3_CR0\r
+.set USBFS_USB__SIE_EP4_CNT0, CYREG_USB_SIE_EP4_CNT0\r
+.set USBFS_USB__SIE_EP4_CNT1, CYREG_USB_SIE_EP4_CNT1\r
+.set USBFS_USB__SIE_EP4_CR0, CYREG_USB_SIE_EP4_CR0\r
+.set USBFS_USB__SIE_EP5_CNT0, CYREG_USB_SIE_EP5_CNT0\r
+.set USBFS_USB__SIE_EP5_CNT1, CYREG_USB_SIE_EP5_CNT1\r
+.set USBFS_USB__SIE_EP5_CR0, CYREG_USB_SIE_EP5_CR0\r
+.set USBFS_USB__SIE_EP6_CNT0, CYREG_USB_SIE_EP6_CNT0\r
+.set USBFS_USB__SIE_EP6_CNT1, CYREG_USB_SIE_EP6_CNT1\r
+.set USBFS_USB__SIE_EP6_CR0, CYREG_USB_SIE_EP6_CR0\r
+.set USBFS_USB__SIE_EP7_CNT0, CYREG_USB_SIE_EP7_CNT0\r
+.set USBFS_USB__SIE_EP7_CNT1, CYREG_USB_SIE_EP7_CNT1\r
+.set USBFS_USB__SIE_EP7_CR0, CYREG_USB_SIE_EP7_CR0\r
+.set USBFS_USB__SIE_EP8_CNT0, CYREG_USB_SIE_EP8_CNT0\r
+.set USBFS_USB__SIE_EP8_CNT1, CYREG_USB_SIE_EP8_CNT1\r
+.set USBFS_USB__SIE_EP8_CR0, CYREG_USB_SIE_EP8_CR0\r
+.set USBFS_USB__SOF0, CYREG_USB_SOF0\r
+.set USBFS_USB__SOF1, CYREG_USB_SOF1\r
+.set USBFS_USB__USB_CLK_EN, CYREG_USB_USB_CLK_EN\r
+.set USBFS_USB__USBIO_CR0, CYREG_USB_USBIO_CR0\r
+.set USBFS_USB__USBIO_CR1, CYREG_USB_USBIO_CR1\r
+\r
 /* scsiTarget */\r
 .set scsiTarget_datapath__16BIT_A0_REG, CYREG_B0_UDB00_01_A0\r
 .set scsiTarget_datapath__16BIT_A1_REG, CYREG_B0_UDB00_01_A1\r
@@ -2841,89 +2998,6 @@
 .set scsiTarget_StatusReg__STATUS_CONTROL_REG, CYREG_B0_UDB07_ST_CTL\r
 .set scsiTarget_StatusReg__STATUS_REG, CYREG_B0_UDB07_ST\r
 \r
-/* Debug_Timer_Interrupt */\r
-.set Debug_Timer_Interrupt__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
-.set Debug_Timer_Interrupt__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
-.set Debug_Timer_Interrupt__INTC_MASK, 0x02\r
-.set Debug_Timer_Interrupt__INTC_NUMBER, 1\r
-.set Debug_Timer_Interrupt__INTC_PRIOR_NUM, 7\r
-.set Debug_Timer_Interrupt__INTC_PRIOR_REG, CYREG_NVIC_PRI_1\r
-.set Debug_Timer_Interrupt__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
-.set Debug_Timer_Interrupt__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
-\r
-/* Debug_Timer_TimerHW */\r
-.set Debug_Timer_TimerHW__CAP0, CYREG_TMR0_CAP0\r
-.set Debug_Timer_TimerHW__CAP1, CYREG_TMR0_CAP1\r
-.set Debug_Timer_TimerHW__CFG0, CYREG_TMR0_CFG0\r
-.set Debug_Timer_TimerHW__CFG1, CYREG_TMR0_CFG1\r
-.set Debug_Timer_TimerHW__CFG2, CYREG_TMR0_CFG2\r
-.set Debug_Timer_TimerHW__CNT_CMP0, CYREG_TMR0_CNT_CMP0\r
-.set Debug_Timer_TimerHW__CNT_CMP1, CYREG_TMR0_CNT_CMP1\r
-.set Debug_Timer_TimerHW__PER0, CYREG_TMR0_PER0\r
-.set Debug_Timer_TimerHW__PER1, CYREG_TMR0_PER1\r
-.set Debug_Timer_TimerHW__PM_ACT_CFG, CYREG_PM_ACT_CFG3\r
-.set Debug_Timer_TimerHW__PM_ACT_MSK, 0x01\r
-.set Debug_Timer_TimerHW__PM_STBY_CFG, CYREG_PM_STBY_CFG3\r
-.set Debug_Timer_TimerHW__PM_STBY_MSK, 0x01\r
-.set Debug_Timer_TimerHW__RT0, CYREG_TMR0_RT0\r
-.set Debug_Timer_TimerHW__RT1, CYREG_TMR0_RT1\r
-.set Debug_Timer_TimerHW__SR0, CYREG_TMR0_SR0\r
-\r
-/* SCSI_RX_DMA */\r
-.set SCSI_RX_DMA__DRQ_CTL, CYREG_IDMUX_DRQ_CTL0\r
-.set SCSI_RX_DMA__DRQ_NUMBER, 0\r
-.set SCSI_RX_DMA__NUMBEROF_TDS, 0\r
-.set SCSI_RX_DMA__PRIORITY, 2\r
-.set SCSI_RX_DMA__TERMIN_EN, 0\r
-.set SCSI_RX_DMA__TERMIN_SEL, 0\r
-.set SCSI_RX_DMA__TERMOUT0_EN, 1\r
-.set SCSI_RX_DMA__TERMOUT0_SEL, 0\r
-.set SCSI_RX_DMA__TERMOUT1_EN, 0\r
-.set SCSI_RX_DMA__TERMOUT1_SEL, 0\r
-\r
-/* SCSI_RX_DMA_COMPLETE */\r
-.set SCSI_RX_DMA_COMPLETE__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
-.set SCSI_RX_DMA_COMPLETE__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
-.set SCSI_RX_DMA_COMPLETE__INTC_MASK, 0x01\r
-.set SCSI_RX_DMA_COMPLETE__INTC_NUMBER, 0\r
-.set SCSI_RX_DMA_COMPLETE__INTC_PRIOR_NUM, 7\r
-.set SCSI_RX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_0\r
-.set SCSI_RX_DMA_COMPLETE__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
-.set SCSI_RX_DMA_COMPLETE__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
-\r
-/* SCSI_TX_DMA */\r
-.set SCSI_TX_DMA__DRQ_CTL, CYREG_IDMUX_DRQ_CTL0\r
-.set SCSI_TX_DMA__DRQ_NUMBER, 1\r
-.set SCSI_TX_DMA__NUMBEROF_TDS, 0\r
-.set SCSI_TX_DMA__PRIORITY, 2\r
-.set SCSI_TX_DMA__TERMIN_EN, 0\r
-.set SCSI_TX_DMA__TERMIN_SEL, 0\r
-.set SCSI_TX_DMA__TERMOUT0_EN, 1\r
-.set SCSI_TX_DMA__TERMOUT0_SEL, 1\r
-.set SCSI_TX_DMA__TERMOUT1_EN, 0\r
-.set SCSI_TX_DMA__TERMOUT1_SEL, 0\r
-\r
-/* SCSI_TX_DMA_COMPLETE */\r
-.set SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
-.set SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
-.set SCSI_TX_DMA_COMPLETE__INTC_MASK, 0x10\r
-.set SCSI_TX_DMA_COMPLETE__INTC_NUMBER, 4\r
-.set SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM, 7\r
-.set SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_4\r
-.set SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
-.set SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
-\r
-/* SD_Data_Clk */\r
-.set SD_Data_Clk__CFG0, CYREG_CLKDIST_DCFG0_CFG0\r
-.set SD_Data_Clk__CFG1, CYREG_CLKDIST_DCFG0_CFG1\r
-.set SD_Data_Clk__CFG2, CYREG_CLKDIST_DCFG0_CFG2\r
-.set SD_Data_Clk__CFG2_SRC_SEL_MASK, 0x07\r
-.set SD_Data_Clk__INDEX, 0x00\r
-.set SD_Data_Clk__PM_ACT_CFG, CYREG_PM_ACT_CFG2\r
-.set SD_Data_Clk__PM_ACT_MSK, 0x01\r
-.set SD_Data_Clk__PM_STBY_CFG, CYREG_PM_STBY_CFG2\r
-.set SD_Data_Clk__PM_STBY_MSK, 0x01\r
-\r
 /* timer_clock */\r
 .set timer_clock__CFG0, CYREG_CLKDIST_DCFG2_CFG0\r
 .set timer_clock__CFG1, CYREG_CLKDIST_DCFG2_CFG1\r
@@ -2935,146 +3009,53 @@
 .set timer_clock__PM_STBY_CFG, CYREG_PM_STBY_CFG2\r
 .set timer_clock__PM_STBY_MSK, 0x04\r
 \r
-/* SCSI_RST_ISR */\r
-.set SCSI_RST_ISR__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
-.set SCSI_RST_ISR__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
-.set SCSI_RST_ISR__INTC_MASK, 0x04\r
-.set SCSI_RST_ISR__INTC_NUMBER, 2\r
-.set SCSI_RST_ISR__INTC_PRIOR_NUM, 7\r
-.set SCSI_RST_ISR__INTC_PRIOR_REG, CYREG_NVIC_PRI_2\r
-.set SCSI_RST_ISR__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
-.set SCSI_RST_ISR__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
-\r
-/* SCSI_SEL_ISR */\r
-.set SCSI_SEL_ISR__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
-.set SCSI_SEL_ISR__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
-.set SCSI_SEL_ISR__INTC_MASK, 0x08\r
-.set SCSI_SEL_ISR__INTC_NUMBER, 3\r
-.set SCSI_SEL_ISR__INTC_PRIOR_NUM, 7\r
-.set SCSI_SEL_ISR__INTC_PRIOR_REG, CYREG_NVIC_PRI_3\r
-.set SCSI_SEL_ISR__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
-.set SCSI_SEL_ISR__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
-\r
-/* SCSI_Filtered */\r
-.set SCSI_Filtered_sts_sts_reg__0__MASK, 0x01\r
-.set SCSI_Filtered_sts_sts_reg__0__POS, 0\r
-.set SCSI_Filtered_sts_sts_reg__1__MASK, 0x02\r
-.set SCSI_Filtered_sts_sts_reg__1__POS, 1\r
-.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB02_03_ACTL\r
-.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB02_03_ST\r
-.set SCSI_Filtered_sts_sts_reg__2__MASK, 0x04\r
-.set SCSI_Filtered_sts_sts_reg__2__POS, 2\r
-.set SCSI_Filtered_sts_sts_reg__3__MASK, 0x08\r
-.set SCSI_Filtered_sts_sts_reg__3__POS, 3\r
-.set SCSI_Filtered_sts_sts_reg__4__MASK, 0x10\r
-.set SCSI_Filtered_sts_sts_reg__4__POS, 4\r
-.set SCSI_Filtered_sts_sts_reg__MASK, 0x1F\r
-.set SCSI_Filtered_sts_sts_reg__MASK_REG, CYREG_B0_UDB02_MSK\r
-.set SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB02_ACTL\r
-.set SCSI_Filtered_sts_sts_reg__STATUS_REG, CYREG_B0_UDB02_ST\r
-\r
-/* SCSI_CTL_PHASE */\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK, 0x01\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS, 0\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK, 0x02\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS, 1\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB05_06_ACTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB05_06_CTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB05_06_CTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB05_06_CTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB05_06_CTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB05_06_MSK\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB05_06_MSK\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB05_06_MSK\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB05_06_MSK\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK, 0x04\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS, 2\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB05_ACTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB05_CTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB05_ST_CTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB05_CTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB05_ST_CTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK, 0x07\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB05_MSK_ACTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB05_MSK_ACTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB05_MSK\r
-\r
-/* SCSI_Glitch_Ctl */\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK, 0x01\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS, 0\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB07_08_ACTL\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB07_08_CTL\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB07_08_CTL\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB07_08_CTL\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB07_08_CTL\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB07_08_MSK\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB07_08_MSK\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB07_08_MSK\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB07_08_MSK\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB07_ACTL\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB07_CTL\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB07_ST_CTL\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB07_CTL\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB07_ST_CTL\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK, 0x01\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB07_MSK_ACTL\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB07_MSK_ACTL\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB07_MSK\r
-\r
-/* SCSI_Parity_Error */\r
-.set SCSI_Parity_Error_sts_sts_reg__0__MASK, 0x01\r
-.set SCSI_Parity_Error_sts_sts_reg__0__POS, 0\r
-.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB01_02_ACTL\r
-.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB01_02_ST\r
-.set SCSI_Parity_Error_sts_sts_reg__MASK, 0x01\r
-.set SCSI_Parity_Error_sts_sts_reg__MASK_REG, CYREG_B0_UDB01_MSK\r
-.set SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB01_ACTL\r
-.set SCSI_Parity_Error_sts_sts_reg__STATUS_REG, CYREG_B0_UDB01_ST\r
-\r
 /* Miscellaneous */\r
 .set BCLK__BUS_CLK__HZ, 50000000\r
 .set BCLK__BUS_CLK__KHZ, 50000\r
 .set BCLK__BUS_CLK__MHZ, 50\r
 .set CYDEV_CHIP_DIE_LEOPARD, 1\r
-.set CYDEV_CHIP_DIE_PSOC4A, 12\r
-.set CYDEV_CHIP_DIE_PSOC5LP, 19\r
-.set CYDEV_CHIP_DIE_PSOC5TM, 20\r
-.set CYDEV_CHIP_DIE_TMA4, 2\r
+.set CYDEV_CHIP_DIE_PSOC4A, 16\r
+.set CYDEV_CHIP_DIE_PSOC5LP, 2\r
+.set CYDEV_CHIP_DIE_PSOC5TM, 3\r
+.set CYDEV_CHIP_DIE_TMA4, 4\r
 .set CYDEV_CHIP_DIE_UNKNOWN, 0\r
-.set CYDEV_CHIP_FAMILY_FM0P, 4\r
-.set CYDEV_CHIP_FAMILY_FM3, 5\r
-.set CYDEV_CHIP_FAMILY_FM4, 6\r
+.set CYDEV_CHIP_FAMILY_FM0P, 5\r
+.set CYDEV_CHIP_FAMILY_FM3, 6\r
+.set CYDEV_CHIP_FAMILY_FM4, 7\r
 .set CYDEV_CHIP_FAMILY_PSOC3, 1\r
 .set CYDEV_CHIP_FAMILY_PSOC4, 2\r
 .set CYDEV_CHIP_FAMILY_PSOC5, 3\r
+.set CYDEV_CHIP_FAMILY_PSOC6, 4\r
 .set CYDEV_CHIP_FAMILY_UNKNOWN, 0\r
 .set CYDEV_CHIP_FAMILY_USED, CYDEV_CHIP_FAMILY_PSOC5\r
 .set CYDEV_CHIP_JTAG_ID, 0x2E133069\r
 .set CYDEV_CHIP_MEMBER_3A, 1\r
-.set CYDEV_CHIP_MEMBER_4A, 12\r
-.set CYDEV_CHIP_MEMBER_4C, 18\r
-.set CYDEV_CHIP_MEMBER_4D, 8\r
-.set CYDEV_CHIP_MEMBER_4E, 4\r
-.set CYDEV_CHIP_MEMBER_4F, 13\r
-.set CYDEV_CHIP_MEMBER_4G, 2\r
-.set CYDEV_CHIP_MEMBER_4H, 11\r
-.set CYDEV_CHIP_MEMBER_4I, 17\r
-.set CYDEV_CHIP_MEMBER_4J, 9\r
-.set CYDEV_CHIP_MEMBER_4K, 10\r
-.set CYDEV_CHIP_MEMBER_4L, 16\r
-.set CYDEV_CHIP_MEMBER_4M, 15\r
-.set CYDEV_CHIP_MEMBER_4N, 6\r
-.set CYDEV_CHIP_MEMBER_4O, 5\r
-.set CYDEV_CHIP_MEMBER_4P, 14\r
-.set CYDEV_CHIP_MEMBER_4Q, 7\r
-.set CYDEV_CHIP_MEMBER_4U, 3\r
-.set CYDEV_CHIP_MEMBER_5A, 20\r
-.set CYDEV_CHIP_MEMBER_5B, 19\r
-.set CYDEV_CHIP_MEMBER_FM3, 24\r
-.set CYDEV_CHIP_MEMBER_FM4, 25\r
-.set CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE1, 21\r
-.set CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE2, 22\r
-.set CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE3, 23\r
+.set CYDEV_CHIP_MEMBER_4A, 16\r
+.set CYDEV_CHIP_MEMBER_4D, 12\r
+.set CYDEV_CHIP_MEMBER_4E, 6\r
+.set CYDEV_CHIP_MEMBER_4F, 17\r
+.set CYDEV_CHIP_MEMBER_4G, 4\r
+.set CYDEV_CHIP_MEMBER_4H, 15\r
+.set CYDEV_CHIP_MEMBER_4I, 21\r
+.set CYDEV_CHIP_MEMBER_4J, 13\r
+.set CYDEV_CHIP_MEMBER_4K, 14\r
+.set CYDEV_CHIP_MEMBER_4L, 20\r
+.set CYDEV_CHIP_MEMBER_4M, 19\r
+.set CYDEV_CHIP_MEMBER_4N, 9\r
+.set CYDEV_CHIP_MEMBER_4O, 7\r
+.set CYDEV_CHIP_MEMBER_4P, 18\r
+.set CYDEV_CHIP_MEMBER_4Q, 11\r
+.set CYDEV_CHIP_MEMBER_4R, 8\r
+.set CYDEV_CHIP_MEMBER_4S, 10\r
+.set CYDEV_CHIP_MEMBER_4U, 5\r
+.set CYDEV_CHIP_MEMBER_5A, 3\r
+.set CYDEV_CHIP_MEMBER_5B, 2\r
+.set CYDEV_CHIP_MEMBER_6A, 22\r
+.set CYDEV_CHIP_MEMBER_FM3, 26\r
+.set CYDEV_CHIP_MEMBER_FM4, 27\r
+.set CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE1, 23\r
+.set CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE2, 24\r
+.set CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE3, 25\r
 .set CYDEV_CHIP_MEMBER_UNKNOWN, 0\r
 .set CYDEV_CHIP_MEMBER_USED, CYDEV_CHIP_MEMBER_5B\r
 .set CYDEV_CHIP_DIE_EXPECT, CYDEV_CHIP_MEMBER_USED\r
@@ -3099,7 +3080,6 @@
 .set CYDEV_CHIP_REVISION_3A_PRODUCTION, 3\r
 .set CYDEV_CHIP_REVISION_4A_ES0, 17\r
 .set CYDEV_CHIP_REVISION_4A_PRODUCTION, 17\r
-.set CYDEV_CHIP_REVISION_4C_PRODUCTION, 0\r
 .set CYDEV_CHIP_REVISION_4D_PRODUCTION, 0\r
 .set CYDEV_CHIP_REVISION_4E_PRODUCTION, 0\r
 .set CYDEV_CHIP_REVISION_4F_PRODUCTION, 0\r
@@ -3118,12 +3098,16 @@
 .set CYDEV_CHIP_REVISION_4O_PRODUCTION, 0\r
 .set CYDEV_CHIP_REVISION_4P_PRODUCTION, 0\r
 .set CYDEV_CHIP_REVISION_4Q_PRODUCTION, 0\r
+.set CYDEV_CHIP_REVISION_4R_PRODUCTION, 0\r
+.set CYDEV_CHIP_REVISION_4S_PRODUCTION, 0\r
 .set CYDEV_CHIP_REVISION_4U_PRODUCTION, 0\r
 .set CYDEV_CHIP_REVISION_5A_ES0, 0\r
 .set CYDEV_CHIP_REVISION_5A_ES1, 1\r
 .set CYDEV_CHIP_REVISION_5A_PRODUCTION, 1\r
 .set CYDEV_CHIP_REVISION_5B_ES0, 0\r
 .set CYDEV_CHIP_REVISION_5B_PRODUCTION, 0\r
+.set CYDEV_CHIP_REVISION_6A_NO_UDB, 0\r
+.set CYDEV_CHIP_REVISION_6A_PRODUCTION, 0\r
 .set CYDEV_CHIP_REVISION_FM3_PRODUCTION, 0\r
 .set CYDEV_CHIP_REVISION_FM4_PRODUCTION, 0\r
 .set CYDEV_CHIP_REVISION_PDL_FM0P_TYPE1_PRODUCTION, 0\r
@@ -3155,7 +3139,7 @@
 .set CYDEV_ECC_ENABLE, 0\r
 .set CYDEV_HEAP_SIZE, 0x0400\r
 .set CYDEV_INSTRUCT_CACHE_ENABLED, 1\r
-.set CYDEV_INTR_RISING, 0x0000007E\r
+.set CYDEV_INTR_RISING, 0x0000007F\r
 .set CYDEV_IS_EXPORTING_CODE, 0\r
 .set CYDEV_IS_IMPORTING_CODE, 0\r
 .set CYDEV_PROJ_TYPE, 2\r

diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitteriar.inc b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitteriar.inc
index 1dae0891aa14620ef86bebd309682e7daaa6a2b9..f222dd3e861f167b0c00e8d7644cfbf58b93997c 100755 (executable)
--- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitteriar.inc
+++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitteriar.inc
@@ -1,8 +1,51 @@
+;\r
+; File Name: cyfitteriar.inc\r
+; \r
+; PSoC Creator  4.1\r
+;\r
+; Description:\r
+; \r
+;\r
+;-------------------------------------------------------------------------------\r
+; Copyright (c) 2007-2017 Cypress Semiconductor.  All rights reserved.\r
+; You may use this file only in accordance with the license, terms, conditions, \r
+; disclaimers, and limitations in the end user license agreement accompanying \r
+; the software package with which this file was provided.\r
+;-------------------------------------------------------------------------------\r
+\r
 #ifndef INCLUDED_CYFITTERIAR_INC\r
 #define INCLUDED_CYFITTERIAR_INC\r
     INCLUDE cydeviceiar.inc\r
     INCLUDE cydeviceiar_trm.inc\r
 \r
+/* Debug_Timer_Interrupt */\r
+Debug_Timer_Interrupt__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
+Debug_Timer_Interrupt__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
+Debug_Timer_Interrupt__INTC_MASK EQU 0x01\r
+Debug_Timer_Interrupt__INTC_NUMBER EQU 0\r
+Debug_Timer_Interrupt__INTC_PRIOR_NUM EQU 7\r
+Debug_Timer_Interrupt__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_0\r
+Debug_Timer_Interrupt__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
+Debug_Timer_Interrupt__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
+\r
+/* Debug_Timer_TimerHW */\r
+Debug_Timer_TimerHW__CAP0 EQU CYREG_TMR0_CAP0\r
+Debug_Timer_TimerHW__CAP1 EQU CYREG_TMR0_CAP1\r
+Debug_Timer_TimerHW__CFG0 EQU CYREG_TMR0_CFG0\r
+Debug_Timer_TimerHW__CFG1 EQU CYREG_TMR0_CFG1\r
+Debug_Timer_TimerHW__CFG2 EQU CYREG_TMR0_CFG2\r
+Debug_Timer_TimerHW__CNT_CMP0 EQU CYREG_TMR0_CNT_CMP0\r
+Debug_Timer_TimerHW__CNT_CMP1 EQU CYREG_TMR0_CNT_CMP1\r
+Debug_Timer_TimerHW__PER0 EQU CYREG_TMR0_PER0\r
+Debug_Timer_TimerHW__PER1 EQU CYREG_TMR0_PER1\r
+Debug_Timer_TimerHW__PM_ACT_CFG EQU CYREG_PM_ACT_CFG3\r
+Debug_Timer_TimerHW__PM_ACT_MSK EQU 0x01\r
+Debug_Timer_TimerHW__PM_STBY_CFG EQU CYREG_PM_STBY_CFG3\r
+Debug_Timer_TimerHW__PM_STBY_MSK EQU 0x01\r
+Debug_Timer_TimerHW__RT0 EQU CYREG_TMR0_RT0\r
+Debug_Timer_TimerHW__RT1 EQU CYREG_TMR0_RT1\r
+Debug_Timer_TimerHW__SR0 EQU CYREG_TMR0_SR0\r
+\r
 /* LED1 */\r
 LED1__0__INTTYPE EQU CYREG_PICU12_INTTYPE3\r
 LED1__0__MASK EQU 0x08\r
@@ -36,2463 +79,810 @@ LED1__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN
 LED1__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ\r
 LED1__SLW EQU CYREG_PRT12_SLW\r
 \r
-/* SD_CD */\r
-SD_CD__0__INTTYPE EQU CYREG_PICU3_INTTYPE6\r
-SD_CD__0__MASK EQU 0x40\r
-SD_CD__0__PC EQU CYREG_PRT3_PC6\r
-SD_CD__0__PORT EQU 3\r
-SD_CD__0__SHIFT EQU 6\r
-SD_CD__AG EQU CYREG_PRT3_AG\r
-SD_CD__AMUX EQU CYREG_PRT3_AMUX\r
-SD_CD__BIE EQU CYREG_PRT3_BIE\r
-SD_CD__BIT_MASK EQU CYREG_PRT3_BIT_MASK\r
-SD_CD__BYP EQU CYREG_PRT3_BYP\r
-SD_CD__CTL EQU CYREG_PRT3_CTL\r
-SD_CD__DM0 EQU CYREG_PRT3_DM0\r
-SD_CD__DM1 EQU CYREG_PRT3_DM1\r
-SD_CD__DM2 EQU CYREG_PRT3_DM2\r
-SD_CD__DR EQU CYREG_PRT3_DR\r
-SD_CD__INP_DIS EQU CYREG_PRT3_INP_DIS\r
-SD_CD__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE\r
-SD_CD__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG\r
-SD_CD__LCD_EN EQU CYREG_PRT3_LCD_EN\r
-SD_CD__MASK EQU 0x40\r
-SD_CD__PORT EQU 3\r
-SD_CD__PRT EQU CYREG_PRT3_PRT\r
-SD_CD__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL\r
-SD_CD__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN\r
-SD_CD__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0\r
-SD_CD__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1\r
-SD_CD__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0\r
-SD_CD__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1\r
-SD_CD__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT\r
-SD_CD__PS EQU CYREG_PRT3_PS\r
-SD_CD__SHIFT EQU 6\r
-SD_CD__SLW EQU CYREG_PRT3_SLW\r
-\r
-/* SD_CS */\r
-SD_CS__0__INTTYPE EQU CYREG_PICU3_INTTYPE4\r
-SD_CS__0__MASK EQU 0x10\r
-SD_CS__0__PC EQU CYREG_PRT3_PC4\r
-SD_CS__0__PORT EQU 3\r
-SD_CS__0__SHIFT EQU 4\r
-SD_CS__AG EQU CYREG_PRT3_AG\r
-SD_CS__AMUX EQU CYREG_PRT3_AMUX\r
-SD_CS__BIE EQU CYREG_PRT3_BIE\r
-SD_CS__BIT_MASK EQU CYREG_PRT3_BIT_MASK\r
-SD_CS__BYP EQU CYREG_PRT3_BYP\r
-SD_CS__CTL EQU CYREG_PRT3_CTL\r
-SD_CS__DM0 EQU CYREG_PRT3_DM0\r
-SD_CS__DM1 EQU CYREG_PRT3_DM1\r
-SD_CS__DM2 EQU CYREG_PRT3_DM2\r
-SD_CS__DR EQU CYREG_PRT3_DR\r
-SD_CS__INP_DIS EQU CYREG_PRT3_INP_DIS\r
-SD_CS__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE\r
-SD_CS__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG\r
-SD_CS__LCD_EN EQU CYREG_PRT3_LCD_EN\r
-SD_CS__MASK EQU 0x10\r
-SD_CS__PORT EQU 3\r
-SD_CS__PRT EQU CYREG_PRT3_PRT\r
-SD_CS__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL\r
-SD_CS__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN\r
-SD_CS__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0\r
-SD_CS__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1\r
-SD_CS__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0\r
-SD_CS__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1\r
-SD_CS__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT\r
-SD_CS__PS EQU CYREG_PRT3_PS\r
-SD_CS__SHIFT EQU 4\r
-SD_CS__SLW EQU CYREG_PRT3_SLW\r
-\r
-/* USBFS_arb_int */\r
-USBFS_arb_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
-USBFS_arb_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
-USBFS_arb_int__INTC_MASK EQU 0x400000\r
-USBFS_arb_int__INTC_NUMBER EQU 22\r
-USBFS_arb_int__INTC_PRIOR_NUM EQU 6\r
-USBFS_arb_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_22\r
-USBFS_arb_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
-USBFS_arb_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
+/* SCSI_CLK */\r
+SCSI_CLK__CFG0 EQU CYREG_CLKDIST_DCFG1_CFG0\r
+SCSI_CLK__CFG1 EQU CYREG_CLKDIST_DCFG1_CFG1\r
+SCSI_CLK__CFG2 EQU CYREG_CLKDIST_DCFG1_CFG2\r
+SCSI_CLK__CFG2_SRC_SEL_MASK EQU 0x07\r
+SCSI_CLK__INDEX EQU 0x01\r
+SCSI_CLK__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2\r
+SCSI_CLK__PM_ACT_MSK EQU 0x02\r
+SCSI_CLK__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2\r
+SCSI_CLK__PM_STBY_MSK EQU 0x02\r
 \r
-/* USBFS_bus_reset */\r
-USBFS_bus_reset__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
-USBFS_bus_reset__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
-USBFS_bus_reset__INTC_MASK EQU 0x800000\r
-USBFS_bus_reset__INTC_NUMBER EQU 23\r
-USBFS_bus_reset__INTC_PRIOR_NUM EQU 7\r
-USBFS_bus_reset__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_23\r
-USBFS_bus_reset__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
-USBFS_bus_reset__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
+/* SCSI_CTL_PHASE */\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS EQU 0\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK EQU 0x02\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS EQU 1\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB05_06_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB05_06_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB05_06_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB05_06_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK EQU 0x04\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS EQU 2\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB05_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB05_ST_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB05_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB05_ST_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__MASK EQU 0x07\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB05_MSK\r
 \r
-/* USBFS_Dm */\r
-USBFS_Dm__0__INTTYPE EQU CYREG_PICU15_INTTYPE7\r
-USBFS_Dm__0__MASK EQU 0x80\r
-USBFS_Dm__0__PC EQU CYREG_IO_PC_PRT15_7_6_PC1\r
-USBFS_Dm__0__PORT EQU 15\r
-USBFS_Dm__0__SHIFT EQU 7\r
-USBFS_Dm__AG EQU CYREG_PRT15_AG\r
-USBFS_Dm__AMUX EQU CYREG_PRT15_AMUX\r
-USBFS_Dm__BIE EQU CYREG_PRT15_BIE\r
-USBFS_Dm__BIT_MASK EQU CYREG_PRT15_BIT_MASK\r
-USBFS_Dm__BYP EQU CYREG_PRT15_BYP\r
-USBFS_Dm__CTL EQU CYREG_PRT15_CTL\r
-USBFS_Dm__DM0 EQU CYREG_PRT15_DM0\r
-USBFS_Dm__DM1 EQU CYREG_PRT15_DM1\r
-USBFS_Dm__DM2 EQU CYREG_PRT15_DM2\r
-USBFS_Dm__DR EQU CYREG_PRT15_DR\r
-USBFS_Dm__INP_DIS EQU CYREG_PRT15_INP_DIS\r
-USBFS_Dm__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU15_BASE\r
-USBFS_Dm__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG\r
-USBFS_Dm__LCD_EN EQU CYREG_PRT15_LCD_EN\r
-USBFS_Dm__MASK EQU 0x80\r
-USBFS_Dm__PORT EQU 15\r
-USBFS_Dm__PRT EQU CYREG_PRT15_PRT\r
-USBFS_Dm__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL\r
-USBFS_Dm__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN\r
-USBFS_Dm__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0\r
-USBFS_Dm__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1\r
-USBFS_Dm__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0\r
-USBFS_Dm__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1\r
-USBFS_Dm__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT\r
-USBFS_Dm__PS EQU CYREG_PRT15_PS\r
-USBFS_Dm__SHIFT EQU 7\r
-USBFS_Dm__SLW EQU CYREG_PRT15_SLW\r
+/* SCSI_Filtered */\r
+SCSI_Filtered_sts_sts_reg__0__MASK EQU 0x01\r
+SCSI_Filtered_sts_sts_reg__0__POS EQU 0\r
+SCSI_Filtered_sts_sts_reg__1__MASK EQU 0x02\r
+SCSI_Filtered_sts_sts_reg__1__POS EQU 1\r
+SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL\r
+SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB02_03_ST\r
+SCSI_Filtered_sts_sts_reg__2__MASK EQU 0x04\r
+SCSI_Filtered_sts_sts_reg__2__POS EQU 2\r
+SCSI_Filtered_sts_sts_reg__3__MASK EQU 0x08\r
+SCSI_Filtered_sts_sts_reg__3__POS EQU 3\r
+SCSI_Filtered_sts_sts_reg__4__MASK EQU 0x10\r
+SCSI_Filtered_sts_sts_reg__4__POS EQU 4\r
+SCSI_Filtered_sts_sts_reg__MASK EQU 0x1F\r
+SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB02_MSK\r
+SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL\r
+SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB02_ST\r
 \r
-/* USBFS_Dp */\r
-USBFS_Dp__0__INTTYPE EQU CYREG_PICU15_INTTYPE6\r
-USBFS_Dp__0__MASK EQU 0x40\r
-USBFS_Dp__0__PC EQU CYREG_IO_PC_PRT15_7_6_PC0\r
-USBFS_Dp__0__PORT EQU 15\r
-USBFS_Dp__0__SHIFT EQU 6\r
-USBFS_Dp__AG EQU CYREG_PRT15_AG\r
-USBFS_Dp__AMUX EQU CYREG_PRT15_AMUX\r
-USBFS_Dp__BIE EQU CYREG_PRT15_BIE\r
-USBFS_Dp__BIT_MASK EQU CYREG_PRT15_BIT_MASK\r
-USBFS_Dp__BYP EQU CYREG_PRT15_BYP\r
-USBFS_Dp__CTL EQU CYREG_PRT15_CTL\r
-USBFS_Dp__DM0 EQU CYREG_PRT15_DM0\r
-USBFS_Dp__DM1 EQU CYREG_PRT15_DM1\r
-USBFS_Dp__DM2 EQU CYREG_PRT15_DM2\r
-USBFS_Dp__DR EQU CYREG_PRT15_DR\r
-USBFS_Dp__INP_DIS EQU CYREG_PRT15_INP_DIS\r
-USBFS_Dp__INTSTAT EQU CYREG_PICU15_INTSTAT\r
-USBFS_Dp__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU15_BASE\r
-USBFS_Dp__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG\r
-USBFS_Dp__LCD_EN EQU CYREG_PRT15_LCD_EN\r
-USBFS_Dp__MASK EQU 0x40\r
-USBFS_Dp__PORT EQU 15\r
-USBFS_Dp__PRT EQU CYREG_PRT15_PRT\r
-USBFS_Dp__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL\r
-USBFS_Dp__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN\r
-USBFS_Dp__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0\r
-USBFS_Dp__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1\r
-USBFS_Dp__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0\r
-USBFS_Dp__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1\r
-USBFS_Dp__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT\r
-USBFS_Dp__PS EQU CYREG_PRT15_PS\r
-USBFS_Dp__SHIFT EQU 6\r
-USBFS_Dp__SLW EQU CYREG_PRT15_SLW\r
-USBFS_Dp__SNAP EQU CYREG_PICU_15_SNAP_15\r
+/* SCSI_Glitch_Ctl */\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS EQU 0\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB07_08_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB07_08_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB07_08_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB07_08_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB07_08_MSK\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB07_08_MSK\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB07_08_MSK\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB07_08_MSK\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB07_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB07_ST_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB07_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB07_ST_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK EQU 0x01\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB07_MSK\r
 \r
-/* USBFS_dp_int */\r
-USBFS_dp_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
-USBFS_dp_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
-USBFS_dp_int__INTC_MASK EQU 0x1000\r
-USBFS_dp_int__INTC_NUMBER EQU 12\r
-USBFS_dp_int__INTC_PRIOR_NUM EQU 7\r
-USBFS_dp_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_12\r
-USBFS_dp_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
-USBFS_dp_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
-\r
-/* USBFS_ep_0 */\r
-USBFS_ep_0__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
-USBFS_ep_0__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
-USBFS_ep_0__INTC_MASK EQU 0x1000000\r
-USBFS_ep_0__INTC_NUMBER EQU 24\r
-USBFS_ep_0__INTC_PRIOR_NUM EQU 7\r
-USBFS_ep_0__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_24\r
-USBFS_ep_0__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
-USBFS_ep_0__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
-\r
-/* USBFS_ep_1 */\r
-USBFS_ep_1__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
-USBFS_ep_1__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
-USBFS_ep_1__INTC_MASK EQU 0x80\r
-USBFS_ep_1__INTC_NUMBER EQU 7\r
-USBFS_ep_1__INTC_PRIOR_NUM EQU 7\r
-USBFS_ep_1__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_7\r
-USBFS_ep_1__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
-USBFS_ep_1__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
-\r
-/* USBFS_ep_2 */\r
-USBFS_ep_2__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
-USBFS_ep_2__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
-USBFS_ep_2__INTC_MASK EQU 0x100\r
-USBFS_ep_2__INTC_NUMBER EQU 8\r
-USBFS_ep_2__INTC_PRIOR_NUM EQU 7\r
-USBFS_ep_2__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_8\r
-USBFS_ep_2__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
-USBFS_ep_2__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
-\r
-/* USBFS_ep_3 */\r
-USBFS_ep_3__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
-USBFS_ep_3__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
-USBFS_ep_3__INTC_MASK EQU 0x200\r
-USBFS_ep_3__INTC_NUMBER EQU 9\r
-USBFS_ep_3__INTC_PRIOR_NUM EQU 7\r
-USBFS_ep_3__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_9\r
-USBFS_ep_3__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
-USBFS_ep_3__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
-\r
-/* USBFS_ep_4 */\r
-USBFS_ep_4__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
-USBFS_ep_4__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
-USBFS_ep_4__INTC_MASK EQU 0x400\r
-USBFS_ep_4__INTC_NUMBER EQU 10\r
-USBFS_ep_4__INTC_PRIOR_NUM EQU 7\r
-USBFS_ep_4__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_10\r
-USBFS_ep_4__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
-USBFS_ep_4__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
-\r
-/* USBFS_sof_int */\r
-USBFS_sof_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
-USBFS_sof_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
-USBFS_sof_int__INTC_MASK EQU 0x200000\r
-USBFS_sof_int__INTC_NUMBER EQU 21\r
-USBFS_sof_int__INTC_PRIOR_NUM EQU 7\r
-USBFS_sof_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_21\r
-USBFS_sof_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
-USBFS_sof_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
-\r
-/* USBFS_USB */\r
-USBFS_USB__ARB_CFG EQU CYREG_USB_ARB_CFG\r
-USBFS_USB__ARB_EP1_CFG EQU CYREG_USB_ARB_EP1_CFG\r
-USBFS_USB__ARB_EP1_INT_EN EQU CYREG_USB_ARB_EP1_INT_EN\r
-USBFS_USB__ARB_EP1_SR EQU CYREG_USB_ARB_EP1_SR\r
-USBFS_USB__ARB_EP2_CFG EQU CYREG_USB_ARB_EP2_CFG\r
-USBFS_USB__ARB_EP2_INT_EN EQU CYREG_USB_ARB_EP2_INT_EN\r
-USBFS_USB__ARB_EP2_SR EQU CYREG_USB_ARB_EP2_SR\r
-USBFS_USB__ARB_EP3_CFG EQU CYREG_USB_ARB_EP3_CFG\r
-USBFS_USB__ARB_EP3_INT_EN EQU CYREG_USB_ARB_EP3_INT_EN\r
-USBFS_USB__ARB_EP3_SR EQU CYREG_USB_ARB_EP3_SR\r
-USBFS_USB__ARB_EP4_CFG EQU CYREG_USB_ARB_EP4_CFG\r
-USBFS_USB__ARB_EP4_INT_EN EQU CYREG_USB_ARB_EP4_INT_EN\r
-USBFS_USB__ARB_EP4_SR EQU CYREG_USB_ARB_EP4_SR\r
-USBFS_USB__ARB_EP5_CFG EQU CYREG_USB_ARB_EP5_CFG\r
-USBFS_USB__ARB_EP5_INT_EN EQU CYREG_USB_ARB_EP5_INT_EN\r
-USBFS_USB__ARB_EP5_SR EQU CYREG_USB_ARB_EP5_SR\r
-USBFS_USB__ARB_EP6_CFG EQU CYREG_USB_ARB_EP6_CFG\r
-USBFS_USB__ARB_EP6_INT_EN EQU CYREG_USB_ARB_EP6_INT_EN\r
-USBFS_USB__ARB_EP6_SR EQU CYREG_USB_ARB_EP6_SR\r
-USBFS_USB__ARB_EP7_CFG EQU CYREG_USB_ARB_EP7_CFG\r
-USBFS_USB__ARB_EP7_INT_EN EQU CYREG_USB_ARB_EP7_INT_EN\r
-USBFS_USB__ARB_EP7_SR EQU CYREG_USB_ARB_EP7_SR\r
-USBFS_USB__ARB_EP8_CFG EQU CYREG_USB_ARB_EP8_CFG\r
-USBFS_USB__ARB_EP8_INT_EN EQU CYREG_USB_ARB_EP8_INT_EN\r
-USBFS_USB__ARB_EP8_SR EQU CYREG_USB_ARB_EP8_SR\r
-USBFS_USB__ARB_INT_EN EQU CYREG_USB_ARB_INT_EN\r
-USBFS_USB__ARB_INT_SR EQU CYREG_USB_ARB_INT_SR\r
-USBFS_USB__ARB_RW1_DR EQU CYREG_USB_ARB_RW1_DR\r
-USBFS_USB__ARB_RW1_RA EQU CYREG_USB_ARB_RW1_RA\r
-USBFS_USB__ARB_RW1_RA_MSB EQU CYREG_USB_ARB_RW1_RA_MSB\r
-USBFS_USB__ARB_RW1_WA EQU CYREG_USB_ARB_RW1_WA\r
-USBFS_USB__ARB_RW1_WA_MSB EQU CYREG_USB_ARB_RW1_WA_MSB\r
-USBFS_USB__ARB_RW2_DR EQU CYREG_USB_ARB_RW2_DR\r
-USBFS_USB__ARB_RW2_RA EQU CYREG_USB_ARB_RW2_RA\r
-USBFS_USB__ARB_RW2_RA_MSB EQU CYREG_USB_ARB_RW2_RA_MSB\r
-USBFS_USB__ARB_RW2_WA EQU CYREG_USB_ARB_RW2_WA\r
-USBFS_USB__ARB_RW2_WA_MSB EQU CYREG_USB_ARB_RW2_WA_MSB\r
-USBFS_USB__ARB_RW3_DR EQU CYREG_USB_ARB_RW3_DR\r
-USBFS_USB__ARB_RW3_RA EQU CYREG_USB_ARB_RW3_RA\r
-USBFS_USB__ARB_RW3_RA_MSB EQU CYREG_USB_ARB_RW3_RA_MSB\r
-USBFS_USB__ARB_RW3_WA EQU CYREG_USB_ARB_RW3_WA\r
-USBFS_USB__ARB_RW3_WA_MSB EQU CYREG_USB_ARB_RW3_WA_MSB\r
-USBFS_USB__ARB_RW4_DR EQU CYREG_USB_ARB_RW4_DR\r
-USBFS_USB__ARB_RW4_RA EQU CYREG_USB_ARB_RW4_RA\r
-USBFS_USB__ARB_RW4_RA_MSB EQU CYREG_USB_ARB_RW4_RA_MSB\r
-USBFS_USB__ARB_RW4_WA EQU CYREG_USB_ARB_RW4_WA\r
-USBFS_USB__ARB_RW4_WA_MSB EQU CYREG_USB_ARB_RW4_WA_MSB\r
-USBFS_USB__ARB_RW5_DR EQU CYREG_USB_ARB_RW5_DR\r
-USBFS_USB__ARB_RW5_RA EQU CYREG_USB_ARB_RW5_RA\r
-USBFS_USB__ARB_RW5_RA_MSB EQU CYREG_USB_ARB_RW5_RA_MSB\r
-USBFS_USB__ARB_RW5_WA EQU CYREG_USB_ARB_RW5_WA\r
-USBFS_USB__ARB_RW5_WA_MSB EQU CYREG_USB_ARB_RW5_WA_MSB\r
-USBFS_USB__ARB_RW6_DR EQU CYREG_USB_ARB_RW6_DR\r
-USBFS_USB__ARB_RW6_RA EQU CYREG_USB_ARB_RW6_RA\r
-USBFS_USB__ARB_RW6_RA_MSB EQU CYREG_USB_ARB_RW6_RA_MSB\r
-USBFS_USB__ARB_RW6_WA EQU CYREG_USB_ARB_RW6_WA\r
-USBFS_USB__ARB_RW6_WA_MSB EQU CYREG_USB_ARB_RW6_WA_MSB\r
-USBFS_USB__ARB_RW7_DR EQU CYREG_USB_ARB_RW7_DR\r
-USBFS_USB__ARB_RW7_RA EQU CYREG_USB_ARB_RW7_RA\r
-USBFS_USB__ARB_RW7_RA_MSB EQU CYREG_USB_ARB_RW7_RA_MSB\r
-USBFS_USB__ARB_RW7_WA EQU CYREG_USB_ARB_RW7_WA\r
-USBFS_USB__ARB_RW7_WA_MSB EQU CYREG_USB_ARB_RW7_WA_MSB\r
-USBFS_USB__ARB_RW8_DR EQU CYREG_USB_ARB_RW8_DR\r
-USBFS_USB__ARB_RW8_RA EQU CYREG_USB_ARB_RW8_RA\r
-USBFS_USB__ARB_RW8_RA_MSB EQU CYREG_USB_ARB_RW8_RA_MSB\r
-USBFS_USB__ARB_RW8_WA EQU CYREG_USB_ARB_RW8_WA\r
-USBFS_USB__ARB_RW8_WA_MSB EQU CYREG_USB_ARB_RW8_WA_MSB\r
-USBFS_USB__BUF_SIZE EQU CYREG_USB_BUF_SIZE\r
-USBFS_USB__BUS_RST_CNT EQU CYREG_USB_BUS_RST_CNT\r
-USBFS_USB__CR0 EQU CYREG_USB_CR0\r
-USBFS_USB__CR1 EQU CYREG_USB_CR1\r
-USBFS_USB__CWA EQU CYREG_USB_CWA\r
-USBFS_USB__CWA_MSB EQU CYREG_USB_CWA_MSB\r
-USBFS_USB__DMA_THRES EQU CYREG_USB_DMA_THRES\r
-USBFS_USB__DMA_THRES_MSB EQU CYREG_USB_DMA_THRES_MSB\r
-USBFS_USB__DYN_RECONFIG EQU CYREG_USB_DYN_RECONFIG\r
-USBFS_USB__EP_ACTIVE EQU CYREG_USB_EP_ACTIVE\r
-USBFS_USB__EP_TYPE EQU CYREG_USB_EP_TYPE\r
-USBFS_USB__EP0_CNT EQU CYREG_USB_EP0_CNT\r
-USBFS_USB__EP0_CR EQU CYREG_USB_EP0_CR\r
-USBFS_USB__EP0_DR0 EQU CYREG_USB_EP0_DR0\r
-USBFS_USB__EP0_DR1 EQU CYREG_USB_EP0_DR1\r
-USBFS_USB__EP0_DR2 EQU CYREG_USB_EP0_DR2\r
-USBFS_USB__EP0_DR3 EQU CYREG_USB_EP0_DR3\r
-USBFS_USB__EP0_DR4 EQU CYREG_USB_EP0_DR4\r
-USBFS_USB__EP0_DR5 EQU CYREG_USB_EP0_DR5\r
-USBFS_USB__EP0_DR6 EQU CYREG_USB_EP0_DR6\r
-USBFS_USB__EP0_DR7 EQU CYREG_USB_EP0_DR7\r
-USBFS_USB__MEM_DATA EQU CYREG_USB_MEM_DATA_MBASE\r
-USBFS_USB__PM_ACT_CFG EQU CYREG_PM_ACT_CFG5\r
-USBFS_USB__PM_ACT_MSK EQU 0x01\r
-USBFS_USB__PM_STBY_CFG EQU CYREG_PM_STBY_CFG5\r
-USBFS_USB__PM_STBY_MSK EQU 0x01\r
-USBFS_USB__SIE_EP_INT_EN EQU CYREG_USB_SIE_EP_INT_EN\r
-USBFS_USB__SIE_EP_INT_SR EQU CYREG_USB_SIE_EP_INT_SR\r
-USBFS_USB__SIE_EP1_CNT0 EQU CYREG_USB_SIE_EP1_CNT0\r
-USBFS_USB__SIE_EP1_CNT1 EQU CYREG_USB_SIE_EP1_CNT1\r
-USBFS_USB__SIE_EP1_CR0 EQU CYREG_USB_SIE_EP1_CR0\r
-USBFS_USB__SIE_EP2_CNT0 EQU CYREG_USB_SIE_EP2_CNT0\r
-USBFS_USB__SIE_EP2_CNT1 EQU CYREG_USB_SIE_EP2_CNT1\r
-USBFS_USB__SIE_EP2_CR0 EQU CYREG_USB_SIE_EP2_CR0\r
-USBFS_USB__SIE_EP3_CNT0 EQU CYREG_USB_SIE_EP3_CNT0\r
-USBFS_USB__SIE_EP3_CNT1 EQU CYREG_USB_SIE_EP3_CNT1\r
-USBFS_USB__SIE_EP3_CR0 EQU CYREG_USB_SIE_EP3_CR0\r
-USBFS_USB__SIE_EP4_CNT0 EQU CYREG_USB_SIE_EP4_CNT0\r
-USBFS_USB__SIE_EP4_CNT1 EQU CYREG_USB_SIE_EP4_CNT1\r
-USBFS_USB__SIE_EP4_CR0 EQU CYREG_USB_SIE_EP4_CR0\r
-USBFS_USB__SIE_EP5_CNT0 EQU CYREG_USB_SIE_EP5_CNT0\r
-USBFS_USB__SIE_EP5_CNT1 EQU CYREG_USB_SIE_EP5_CNT1\r
-USBFS_USB__SIE_EP5_CR0 EQU CYREG_USB_SIE_EP5_CR0\r
-USBFS_USB__SIE_EP6_CNT0 EQU CYREG_USB_SIE_EP6_CNT0\r
-USBFS_USB__SIE_EP6_CNT1 EQU CYREG_USB_SIE_EP6_CNT1\r
-USBFS_USB__SIE_EP6_CR0 EQU CYREG_USB_SIE_EP6_CR0\r
-USBFS_USB__SIE_EP7_CNT0 EQU CYREG_USB_SIE_EP7_CNT0\r
-USBFS_USB__SIE_EP7_CNT1 EQU CYREG_USB_SIE_EP7_CNT1\r
-USBFS_USB__SIE_EP7_CR0 EQU CYREG_USB_SIE_EP7_CR0\r
-USBFS_USB__SIE_EP8_CNT0 EQU CYREG_USB_SIE_EP8_CNT0\r
-USBFS_USB__SIE_EP8_CNT1 EQU CYREG_USB_SIE_EP8_CNT1\r
-USBFS_USB__SIE_EP8_CR0 EQU CYREG_USB_SIE_EP8_CR0\r
-USBFS_USB__SOF0 EQU CYREG_USB_SOF0\r
-USBFS_USB__SOF1 EQU CYREG_USB_SOF1\r
-USBFS_USB__USB_CLK_EN EQU CYREG_USB_USB_CLK_EN\r
-USBFS_USB__USBIO_CR0 EQU CYREG_USB_USBIO_CR0\r
-USBFS_USB__USBIO_CR1 EQU CYREG_USB_USBIO_CR1\r
-\r
-/* SDCard_BSPIM */\r
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL\r
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB04_05_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB04_05_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB04_05_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB04_05_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB04_05_MSK\r
-SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB04_05_MSK\r
-SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB04_05_MSK\r
-SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB04_05_MSK\r
-SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL\r
-SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB04_CTL\r
-SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB04_ST_CTL\r
-SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB04_CTL\r
-SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB04_ST_CTL\r
-SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL\r
-SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL\r
-SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB04_MSK\r
-SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL\r
-SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB04_05_ST\r
-SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB04_MSK\r
-SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL\r
-SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB04_ST_CTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB04_ST_CTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB04_ST\r
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB08_09_ACTL\r
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB08_09_ST\r
-SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10\r
-SDCard_BSPIM_RxStsReg__4__POS EQU 4\r
-SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20\r
-SDCard_BSPIM_RxStsReg__5__POS EQU 5\r
-SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40\r
-SDCard_BSPIM_RxStsReg__6__POS EQU 6\r
-SDCard_BSPIM_RxStsReg__MASK EQU 0x70\r
-SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB08_MSK\r
-SDCard_BSPIM_RxStsReg__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB08_MSK_ACTL\r
-SDCard_BSPIM_RxStsReg__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB08_MSK_ACTL\r
-SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB08_ACTL\r
-SDCard_BSPIM_RxStsReg__STATUS_CNT_REG EQU CYREG_B1_UDB08_ST_CTL\r
-SDCard_BSPIM_RxStsReg__STATUS_CONTROL_REG EQU CYREG_B1_UDB08_ST_CTL\r
-SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB08_ST\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB04_05_A0\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB04_05_A1\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B1_UDB04_05_D0\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B1_UDB04_05_D1\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B1_UDB04_05_F0\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B1_UDB04_05_F1\r
-SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B1_UDB04_A0_A1\r
-SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B1_UDB04_A0\r
-SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B1_UDB04_A1\r
-SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B1_UDB04_D0_D1\r
-SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B1_UDB04_D0\r
-SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B1_UDB04_D1\r
-SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL\r
-SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B1_UDB04_F0_F1\r
-SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B1_UDB04_F0\r
-SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B1_UDB04_F1\r
-SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL\r
-SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL\r
-SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01\r
-SDCard_BSPIM_TxStsReg__0__POS EQU 0\r
-SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02\r
-SDCard_BSPIM_TxStsReg__1__POS EQU 1\r
-SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL\r
-SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST\r
-SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04\r
-SDCard_BSPIM_TxStsReg__2__POS EQU 2\r
-SDCard_BSPIM_TxStsReg__3__MASK EQU 0x08\r
-SDCard_BSPIM_TxStsReg__3__POS EQU 3\r
-SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10\r
-SDCard_BSPIM_TxStsReg__4__POS EQU 4\r
-SDCard_BSPIM_TxStsReg__MASK EQU 0x1F\r
-SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB07_MSK\r
-SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL\r
-SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB07_ST\r
-\r
-/* SD_SCK */\r
-SD_SCK__0__INTTYPE EQU CYREG_PICU3_INTTYPE2\r
-SD_SCK__0__MASK EQU 0x04\r
-SD_SCK__0__PC EQU CYREG_PRT3_PC2\r
-SD_SCK__0__PORT EQU 3\r
-SD_SCK__0__SHIFT EQU 2\r
-SD_SCK__AG EQU CYREG_PRT3_AG\r
-SD_SCK__AMUX EQU CYREG_PRT3_AMUX\r
-SD_SCK__BIE EQU CYREG_PRT3_BIE\r
-SD_SCK__BIT_MASK EQU CYREG_PRT3_BIT_MASK\r
-SD_SCK__BYP EQU CYREG_PRT3_BYP\r
-SD_SCK__CTL EQU CYREG_PRT3_CTL\r
-SD_SCK__DM0 EQU CYREG_PRT3_DM0\r
-SD_SCK__DM1 EQU CYREG_PRT3_DM1\r
-SD_SCK__DM2 EQU CYREG_PRT3_DM2\r
-SD_SCK__DR EQU CYREG_PRT3_DR\r
-SD_SCK__INP_DIS EQU CYREG_PRT3_INP_DIS\r
-SD_SCK__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE\r
-SD_SCK__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG\r
-SD_SCK__LCD_EN EQU CYREG_PRT3_LCD_EN\r
-SD_SCK__MASK EQU 0x04\r
-SD_SCK__PORT EQU 3\r
-SD_SCK__PRT EQU CYREG_PRT3_PRT\r
-SD_SCK__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL\r
-SD_SCK__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN\r
-SD_SCK__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0\r
-SD_SCK__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1\r
-SD_SCK__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0\r
-SD_SCK__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1\r
-SD_SCK__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT\r
-SD_SCK__PS EQU CYREG_PRT3_PS\r
-SD_SCK__SHIFT EQU 2\r
-SD_SCK__SLW EQU CYREG_PRT3_SLW\r
-\r
-/* SCSI_In */\r
-SCSI_In__0__AG EQU CYREG_PRT2_AG\r
-SCSI_In__0__AMUX EQU CYREG_PRT2_AMUX\r
-SCSI_In__0__BIE EQU CYREG_PRT2_BIE\r
-SCSI_In__0__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
-SCSI_In__0__BYP EQU CYREG_PRT2_BYP\r
-SCSI_In__0__CTL EQU CYREG_PRT2_CTL\r
-SCSI_In__0__DM0 EQU CYREG_PRT2_DM0\r
-SCSI_In__0__DM1 EQU CYREG_PRT2_DM1\r
-SCSI_In__0__DM2 EQU CYREG_PRT2_DM2\r
-SCSI_In__0__DR EQU CYREG_PRT2_DR\r
-SCSI_In__0__INP_DIS EQU CYREG_PRT2_INP_DIS\r
-SCSI_In__0__INTTYPE EQU CYREG_PICU2_INTTYPE0\r
-SCSI_In__0__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
-SCSI_In__0__LCD_EN EQU CYREG_PRT2_LCD_EN\r
-SCSI_In__0__MASK EQU 0x01\r
-SCSI_In__0__PC EQU CYREG_PRT2_PC0\r
-SCSI_In__0__PORT EQU 2\r
-SCSI_In__0__PRT EQU CYREG_PRT2_PRT\r
-SCSI_In__0__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
-SCSI_In__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
-SCSI_In__0__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
-SCSI_In__0__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
-SCSI_In__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
-SCSI_In__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
-SCSI_In__0__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
-SCSI_In__0__PS EQU CYREG_PRT2_PS\r
-SCSI_In__0__SHIFT EQU 0\r
-SCSI_In__0__SLW EQU CYREG_PRT2_SLW\r
-SCSI_In__1__AG EQU CYREG_PRT6_AG\r
-SCSI_In__1__AMUX EQU CYREG_PRT6_AMUX\r
-SCSI_In__1__BIE EQU CYREG_PRT6_BIE\r
-SCSI_In__1__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
-SCSI_In__1__BYP EQU CYREG_PRT6_BYP\r
-SCSI_In__1__CTL EQU CYREG_PRT6_CTL\r
-SCSI_In__1__DM0 EQU CYREG_PRT6_DM0\r
-SCSI_In__1__DM1 EQU CYREG_PRT6_DM1\r
-SCSI_In__1__DM2 EQU CYREG_PRT6_DM2\r
-SCSI_In__1__DR EQU CYREG_PRT6_DR\r
-SCSI_In__1__INP_DIS EQU CYREG_PRT6_INP_DIS\r
-SCSI_In__1__INTTYPE EQU CYREG_PICU6_INTTYPE7\r
-SCSI_In__1__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
-SCSI_In__1__LCD_EN EQU CYREG_PRT6_LCD_EN\r
-SCSI_In__1__MASK EQU 0x80\r
-SCSI_In__1__PC EQU CYREG_PRT6_PC7\r
-SCSI_In__1__PORT EQU 6\r
-SCSI_In__1__PRT EQU CYREG_PRT6_PRT\r
-SCSI_In__1__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
-SCSI_In__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
-SCSI_In__1__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
-SCSI_In__1__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
-SCSI_In__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
-SCSI_In__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
-SCSI_In__1__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
-SCSI_In__1__PS EQU CYREG_PRT6_PS\r
-SCSI_In__1__SHIFT EQU 7\r
-SCSI_In__1__SLW EQU CYREG_PRT6_SLW\r
-SCSI_In__2__AG EQU CYREG_PRT5_AG\r
-SCSI_In__2__AMUX EQU CYREG_PRT5_AMUX\r
-SCSI_In__2__BIE EQU CYREG_PRT5_BIE\r
-SCSI_In__2__BIT_MASK EQU CYREG_PRT5_BIT_MASK\r
-SCSI_In__2__BYP EQU CYREG_PRT5_BYP\r
-SCSI_In__2__CTL EQU CYREG_PRT5_CTL\r
-SCSI_In__2__DM0 EQU CYREG_PRT5_DM0\r
-SCSI_In__2__DM1 EQU CYREG_PRT5_DM1\r
-SCSI_In__2__DM2 EQU CYREG_PRT5_DM2\r
-SCSI_In__2__DR EQU CYREG_PRT5_DR\r
-SCSI_In__2__INP_DIS EQU CYREG_PRT5_INP_DIS\r
-SCSI_In__2__INTTYPE EQU CYREG_PICU5_INTTYPE1\r
-SCSI_In__2__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG\r
-SCSI_In__2__LCD_EN EQU CYREG_PRT5_LCD_EN\r
-SCSI_In__2__MASK EQU 0x02\r
-SCSI_In__2__PC EQU CYREG_PRT5_PC1\r
-SCSI_In__2__PORT EQU 5\r
-SCSI_In__2__PRT EQU CYREG_PRT5_PRT\r
-SCSI_In__2__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL\r
-SCSI_In__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN\r
-SCSI_In__2__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0\r
-SCSI_In__2__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1\r
-SCSI_In__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0\r
-SCSI_In__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1\r
-SCSI_In__2__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT\r
-SCSI_In__2__PS EQU CYREG_PRT5_PS\r
-SCSI_In__2__SHIFT EQU 1\r
-SCSI_In__2__SLW EQU CYREG_PRT5_SLW\r
-SCSI_In__3__AG EQU CYREG_PRT5_AG\r
-SCSI_In__3__AMUX EQU CYREG_PRT5_AMUX\r
-SCSI_In__3__BIE EQU CYREG_PRT5_BIE\r
-SCSI_In__3__BIT_MASK EQU CYREG_PRT5_BIT_MASK\r
-SCSI_In__3__BYP EQU CYREG_PRT5_BYP\r
-SCSI_In__3__CTL EQU CYREG_PRT5_CTL\r
-SCSI_In__3__DM0 EQU CYREG_PRT5_DM0\r
-SCSI_In__3__DM1 EQU CYREG_PRT5_DM1\r
-SCSI_In__3__DM2 EQU CYREG_PRT5_DM2\r
-SCSI_In__3__DR EQU CYREG_PRT5_DR\r
-SCSI_In__3__INP_DIS EQU CYREG_PRT5_INP_DIS\r
-SCSI_In__3__INTTYPE EQU CYREG_PICU5_INTTYPE2\r
-SCSI_In__3__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG\r
-SCSI_In__3__LCD_EN EQU CYREG_PRT5_LCD_EN\r
-SCSI_In__3__MASK EQU 0x04\r
-SCSI_In__3__PC EQU CYREG_PRT5_PC2\r
-SCSI_In__3__PORT EQU 5\r
-SCSI_In__3__PRT EQU CYREG_PRT5_PRT\r
-SCSI_In__3__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL\r
-SCSI_In__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN\r
-SCSI_In__3__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0\r
-SCSI_In__3__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1\r
-SCSI_In__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0\r
-SCSI_In__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1\r
-SCSI_In__3__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT\r
-SCSI_In__3__PS EQU CYREG_PRT5_PS\r
-SCSI_In__3__SHIFT EQU 2\r
-SCSI_In__3__SLW EQU CYREG_PRT5_SLW\r
-SCSI_In__4__AG EQU CYREG_PRT5_AG\r
-SCSI_In__4__AMUX EQU CYREG_PRT5_AMUX\r
-SCSI_In__4__BIE EQU CYREG_PRT5_BIE\r
-SCSI_In__4__BIT_MASK EQU CYREG_PRT5_BIT_MASK\r
-SCSI_In__4__BYP EQU CYREG_PRT5_BYP\r
-SCSI_In__4__CTL EQU CYREG_PRT5_CTL\r
-SCSI_In__4__DM0 EQU CYREG_PRT5_DM0\r
-SCSI_In__4__DM1 EQU CYREG_PRT5_DM1\r
-SCSI_In__4__DM2 EQU CYREG_PRT5_DM2\r
-SCSI_In__4__DR EQU CYREG_PRT5_DR\r
-SCSI_In__4__INP_DIS EQU CYREG_PRT5_INP_DIS\r
-SCSI_In__4__INTTYPE EQU CYREG_PICU5_INTTYPE3\r
-SCSI_In__4__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG\r
-SCSI_In__4__LCD_EN EQU CYREG_PRT5_LCD_EN\r
-SCSI_In__4__MASK EQU 0x08\r
-SCSI_In__4__PC EQU CYREG_PRT5_PC3\r
-SCSI_In__4__PORT EQU 5\r
-SCSI_In__4__PRT EQU CYREG_PRT5_PRT\r
-SCSI_In__4__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL\r
-SCSI_In__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN\r
-SCSI_In__4__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0\r
-SCSI_In__4__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1\r
-SCSI_In__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0\r
-SCSI_In__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1\r
-SCSI_In__4__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT\r
-SCSI_In__4__PS EQU CYREG_PRT5_PS\r
-SCSI_In__4__SHIFT EQU 3\r
-SCSI_In__4__SLW EQU CYREG_PRT5_SLW\r
-SCSI_In__CD__AG EQU CYREG_PRT5_AG\r
-SCSI_In__CD__AMUX EQU CYREG_PRT5_AMUX\r
-SCSI_In__CD__BIE EQU CYREG_PRT5_BIE\r
-SCSI_In__CD__BIT_MASK EQU CYREG_PRT5_BIT_MASK\r
-SCSI_In__CD__BYP EQU CYREG_PRT5_BYP\r
-SCSI_In__CD__CTL EQU CYREG_PRT5_CTL\r
-SCSI_In__CD__DM0 EQU CYREG_PRT5_DM0\r
-SCSI_In__CD__DM1 EQU CYREG_PRT5_DM1\r
-SCSI_In__CD__DM2 EQU CYREG_PRT5_DM2\r
-SCSI_In__CD__DR EQU CYREG_PRT5_DR\r
-SCSI_In__CD__INP_DIS EQU CYREG_PRT5_INP_DIS\r
-SCSI_In__CD__INTTYPE EQU CYREG_PICU5_INTTYPE1\r
-SCSI_In__CD__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG\r
-SCSI_In__CD__LCD_EN EQU CYREG_PRT5_LCD_EN\r
-SCSI_In__CD__MASK EQU 0x02\r
-SCSI_In__CD__PC EQU CYREG_PRT5_PC1\r
-SCSI_In__CD__PORT EQU 5\r
-SCSI_In__CD__PRT EQU CYREG_PRT5_PRT\r
-SCSI_In__CD__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL\r
-SCSI_In__CD__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN\r
-SCSI_In__CD__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0\r
-SCSI_In__CD__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1\r
-SCSI_In__CD__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0\r
-SCSI_In__CD__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1\r
-SCSI_In__CD__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT\r
-SCSI_In__CD__PS EQU CYREG_PRT5_PS\r
-SCSI_In__CD__SHIFT EQU 1\r
-SCSI_In__CD__SLW EQU CYREG_PRT5_SLW\r
-SCSI_In__DBP__AG EQU CYREG_PRT2_AG\r
-SCSI_In__DBP__AMUX EQU CYREG_PRT2_AMUX\r
-SCSI_In__DBP__BIE EQU CYREG_PRT2_BIE\r
-SCSI_In__DBP__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
-SCSI_In__DBP__BYP EQU CYREG_PRT2_BYP\r
-SCSI_In__DBP__CTL EQU CYREG_PRT2_CTL\r
-SCSI_In__DBP__DM0 EQU CYREG_PRT2_DM0\r
-SCSI_In__DBP__DM1 EQU CYREG_PRT2_DM1\r
-SCSI_In__DBP__DM2 EQU CYREG_PRT2_DM2\r
-SCSI_In__DBP__DR EQU CYREG_PRT2_DR\r
-SCSI_In__DBP__INP_DIS EQU CYREG_PRT2_INP_DIS\r
-SCSI_In__DBP__INTTYPE EQU CYREG_PICU2_INTTYPE0\r
-SCSI_In__DBP__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
-SCSI_In__DBP__LCD_EN EQU CYREG_PRT2_LCD_EN\r
-SCSI_In__DBP__MASK EQU 0x01\r
-SCSI_In__DBP__PC EQU CYREG_PRT2_PC0\r
-SCSI_In__DBP__PORT EQU 2\r
-SCSI_In__DBP__PRT EQU CYREG_PRT2_PRT\r
-SCSI_In__DBP__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
-SCSI_In__DBP__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
-SCSI_In__DBP__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
-SCSI_In__DBP__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
-SCSI_In__DBP__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
-SCSI_In__DBP__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
-SCSI_In__DBP__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
-SCSI_In__DBP__PS EQU CYREG_PRT2_PS\r
-SCSI_In__DBP__SHIFT EQU 0\r
-SCSI_In__DBP__SLW EQU CYREG_PRT2_SLW\r
-SCSI_In__IO__AG EQU CYREG_PRT5_AG\r
-SCSI_In__IO__AMUX EQU CYREG_PRT5_AMUX\r
-SCSI_In__IO__BIE EQU CYREG_PRT5_BIE\r
-SCSI_In__IO__BIT_MASK EQU CYREG_PRT5_BIT_MASK\r
-SCSI_In__IO__BYP EQU CYREG_PRT5_BYP\r
-SCSI_In__IO__CTL EQU CYREG_PRT5_CTL\r
-SCSI_In__IO__DM0 EQU CYREG_PRT5_DM0\r
-SCSI_In__IO__DM1 EQU CYREG_PRT5_DM1\r
-SCSI_In__IO__DM2 EQU CYREG_PRT5_DM2\r
-SCSI_In__IO__DR EQU CYREG_PRT5_DR\r
-SCSI_In__IO__INP_DIS EQU CYREG_PRT5_INP_DIS\r
-SCSI_In__IO__INTTYPE EQU CYREG_PICU5_INTTYPE3\r
-SCSI_In__IO__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG\r
-SCSI_In__IO__LCD_EN EQU CYREG_PRT5_LCD_EN\r
-SCSI_In__IO__MASK EQU 0x08\r
-SCSI_In__IO__PC EQU CYREG_PRT5_PC3\r
-SCSI_In__IO__PORT EQU 5\r
-SCSI_In__IO__PRT EQU CYREG_PRT5_PRT\r
-SCSI_In__IO__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL\r
-SCSI_In__IO__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN\r
-SCSI_In__IO__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0\r
-SCSI_In__IO__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1\r
-SCSI_In__IO__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0\r
-SCSI_In__IO__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1\r
-SCSI_In__IO__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT\r
-SCSI_In__IO__PS EQU CYREG_PRT5_PS\r
-SCSI_In__IO__SHIFT EQU 3\r
-SCSI_In__IO__SLW EQU CYREG_PRT5_SLW\r
-SCSI_In__MSG__AG EQU CYREG_PRT6_AG\r
-SCSI_In__MSG__AMUX EQU CYREG_PRT6_AMUX\r
-SCSI_In__MSG__BIE EQU CYREG_PRT6_BIE\r
-SCSI_In__MSG__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
-SCSI_In__MSG__BYP EQU CYREG_PRT6_BYP\r
-SCSI_In__MSG__CTL EQU CYREG_PRT6_CTL\r
-SCSI_In__MSG__DM0 EQU CYREG_PRT6_DM0\r
-SCSI_In__MSG__DM1 EQU CYREG_PRT6_DM1\r
-SCSI_In__MSG__DM2 EQU CYREG_PRT6_DM2\r
-SCSI_In__MSG__DR EQU CYREG_PRT6_DR\r
-SCSI_In__MSG__INP_DIS EQU CYREG_PRT6_INP_DIS\r
-SCSI_In__MSG__INTTYPE EQU CYREG_PICU6_INTTYPE7\r
-SCSI_In__MSG__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
-SCSI_In__MSG__LCD_EN EQU CYREG_PRT6_LCD_EN\r
-SCSI_In__MSG__MASK EQU 0x80\r
-SCSI_In__MSG__PC EQU CYREG_PRT6_PC7\r
-SCSI_In__MSG__PORT EQU 6\r
-SCSI_In__MSG__PRT EQU CYREG_PRT6_PRT\r
-SCSI_In__MSG__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
-SCSI_In__MSG__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
-SCSI_In__MSG__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
-SCSI_In__MSG__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
-SCSI_In__MSG__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
-SCSI_In__MSG__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
-SCSI_In__MSG__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
-SCSI_In__MSG__PS EQU CYREG_PRT6_PS\r
-SCSI_In__MSG__SHIFT EQU 7\r
-SCSI_In__MSG__SLW EQU CYREG_PRT6_SLW\r
-SCSI_In__REQ__AG EQU CYREG_PRT5_AG\r
-SCSI_In__REQ__AMUX EQU CYREG_PRT5_AMUX\r
-SCSI_In__REQ__BIE EQU CYREG_PRT5_BIE\r
-SCSI_In__REQ__BIT_MASK EQU CYREG_PRT5_BIT_MASK\r
-SCSI_In__REQ__BYP EQU CYREG_PRT5_BYP\r
-SCSI_In__REQ__CTL EQU CYREG_PRT5_CTL\r
-SCSI_In__REQ__DM0 EQU CYREG_PRT5_DM0\r
-SCSI_In__REQ__DM1 EQU CYREG_PRT5_DM1\r
-SCSI_In__REQ__DM2 EQU CYREG_PRT5_DM2\r
-SCSI_In__REQ__DR EQU CYREG_PRT5_DR\r
-SCSI_In__REQ__INP_DIS EQU CYREG_PRT5_INP_DIS\r
-SCSI_In__REQ__INTTYPE EQU CYREG_PICU5_INTTYPE2\r
-SCSI_In__REQ__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG\r
-SCSI_In__REQ__LCD_EN EQU CYREG_PRT5_LCD_EN\r
-SCSI_In__REQ__MASK EQU 0x04\r
-SCSI_In__REQ__PC EQU CYREG_PRT5_PC2\r
-SCSI_In__REQ__PORT EQU 5\r
-SCSI_In__REQ__PRT EQU CYREG_PRT5_PRT\r
-SCSI_In__REQ__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL\r
-SCSI_In__REQ__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN\r
-SCSI_In__REQ__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0\r
-SCSI_In__REQ__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1\r
-SCSI_In__REQ__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0\r
-SCSI_In__REQ__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1\r
-SCSI_In__REQ__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT\r
-SCSI_In__REQ__PS EQU CYREG_PRT5_PS\r
-SCSI_In__REQ__SHIFT EQU 2\r
-SCSI_In__REQ__SLW EQU CYREG_PRT5_SLW\r
-\r
-/* SCSI_In_DBx */\r
-SCSI_In_DBx__0__AG EQU CYREG_PRT12_AG\r
-SCSI_In_DBx__0__BIE EQU CYREG_PRT12_BIE\r
-SCSI_In_DBx__0__BIT_MASK EQU CYREG_PRT12_BIT_MASK\r
-SCSI_In_DBx__0__BYP EQU CYREG_PRT12_BYP\r
-SCSI_In_DBx__0__DM0 EQU CYREG_PRT12_DM0\r
-SCSI_In_DBx__0__DM1 EQU CYREG_PRT12_DM1\r
-SCSI_In_DBx__0__DM2 EQU CYREG_PRT12_DM2\r
-SCSI_In_DBx__0__DR EQU CYREG_PRT12_DR\r
-SCSI_In_DBx__0__INP_DIS EQU CYREG_PRT12_INP_DIS\r
-SCSI_In_DBx__0__INTTYPE EQU CYREG_PICU12_INTTYPE4\r
-SCSI_In_DBx__0__MASK EQU 0x10\r
-SCSI_In_DBx__0__PC EQU CYREG_PRT12_PC4\r
-SCSI_In_DBx__0__PORT EQU 12\r
-SCSI_In_DBx__0__PRT EQU CYREG_PRT12_PRT\r
-SCSI_In_DBx__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN\r
-SCSI_In_DBx__0__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0\r
-SCSI_In_DBx__0__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1\r
-SCSI_In_DBx__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0\r
-SCSI_In_DBx__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1\r
-SCSI_In_DBx__0__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT\r
-SCSI_In_DBx__0__PS EQU CYREG_PRT12_PS\r
-SCSI_In_DBx__0__SHIFT EQU 4\r
-SCSI_In_DBx__0__SIO_CFG EQU CYREG_PRT12_SIO_CFG\r
-SCSI_In_DBx__0__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF\r
-SCSI_In_DBx__0__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN\r
-SCSI_In_DBx__0__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ\r
-SCSI_In_DBx__0__SLW EQU CYREG_PRT12_SLW\r
-SCSI_In_DBx__1__AG EQU CYREG_PRT2_AG\r
-SCSI_In_DBx__1__AMUX EQU CYREG_PRT2_AMUX\r
-SCSI_In_DBx__1__BIE EQU CYREG_PRT2_BIE\r
-SCSI_In_DBx__1__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
-SCSI_In_DBx__1__BYP EQU CYREG_PRT2_BYP\r
-SCSI_In_DBx__1__CTL EQU CYREG_PRT2_CTL\r
-SCSI_In_DBx__1__DM0 EQU CYREG_PRT2_DM0\r
-SCSI_In_DBx__1__DM1 EQU CYREG_PRT2_DM1\r
-SCSI_In_DBx__1__DM2 EQU CYREG_PRT2_DM2\r
-SCSI_In_DBx__1__DR EQU CYREG_PRT2_DR\r
-SCSI_In_DBx__1__INP_DIS EQU CYREG_PRT2_INP_DIS\r
-SCSI_In_DBx__1__INTTYPE EQU CYREG_PICU2_INTTYPE7\r
-SCSI_In_DBx__1__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
-SCSI_In_DBx__1__LCD_EN EQU CYREG_PRT2_LCD_EN\r
-SCSI_In_DBx__1__MASK EQU 0x80\r
-SCSI_In_DBx__1__PC EQU CYREG_PRT2_PC7\r
-SCSI_In_DBx__1__PORT EQU 2\r
-SCSI_In_DBx__1__PRT EQU CYREG_PRT2_PRT\r
-SCSI_In_DBx__1__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
-SCSI_In_DBx__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
-SCSI_In_DBx__1__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
-SCSI_In_DBx__1__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
-SCSI_In_DBx__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
-SCSI_In_DBx__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
-SCSI_In_DBx__1__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
-SCSI_In_DBx__1__PS EQU CYREG_PRT2_PS\r
-SCSI_In_DBx__1__SHIFT EQU 7\r
-SCSI_In_DBx__1__SLW EQU CYREG_PRT2_SLW\r
-SCSI_In_DBx__2__AG EQU CYREG_PRT2_AG\r
-SCSI_In_DBx__2__AMUX EQU CYREG_PRT2_AMUX\r
-SCSI_In_DBx__2__BIE EQU CYREG_PRT2_BIE\r
-SCSI_In_DBx__2__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
-SCSI_In_DBx__2__BYP EQU CYREG_PRT2_BYP\r
-SCSI_In_DBx__2__CTL EQU CYREG_PRT2_CTL\r
-SCSI_In_DBx__2__DM0 EQU CYREG_PRT2_DM0\r
-SCSI_In_DBx__2__DM1 EQU CYREG_PRT2_DM1\r
-SCSI_In_DBx__2__DM2 EQU CYREG_PRT2_DM2\r
-SCSI_In_DBx__2__DR EQU CYREG_PRT2_DR\r
-SCSI_In_DBx__2__INP_DIS EQU CYREG_PRT2_INP_DIS\r
-SCSI_In_DBx__2__INTTYPE EQU CYREG_PICU2_INTTYPE6\r
-SCSI_In_DBx__2__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
-SCSI_In_DBx__2__LCD_EN EQU CYREG_PRT2_LCD_EN\r
-SCSI_In_DBx__2__MASK EQU 0x40\r
-SCSI_In_DBx__2__PC EQU CYREG_PRT2_PC6\r
-SCSI_In_DBx__2__PORT EQU 2\r
-SCSI_In_DBx__2__PRT EQU CYREG_PRT2_PRT\r
-SCSI_In_DBx__2__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
-SCSI_In_DBx__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
-SCSI_In_DBx__2__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
-SCSI_In_DBx__2__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
-SCSI_In_DBx__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
-SCSI_In_DBx__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
-SCSI_In_DBx__2__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
-SCSI_In_DBx__2__PS EQU CYREG_PRT2_PS\r
-SCSI_In_DBx__2__SHIFT EQU 6\r
-SCSI_In_DBx__2__SLW EQU CYREG_PRT2_SLW\r
-SCSI_In_DBx__3__AG EQU CYREG_PRT2_AG\r
-SCSI_In_DBx__3__AMUX EQU CYREG_PRT2_AMUX\r
-SCSI_In_DBx__3__BIE EQU CYREG_PRT2_BIE\r
-SCSI_In_DBx__3__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
-SCSI_In_DBx__3__BYP EQU CYREG_PRT2_BYP\r
-SCSI_In_DBx__3__CTL EQU CYREG_PRT2_CTL\r
-SCSI_In_DBx__3__DM0 EQU CYREG_PRT2_DM0\r
-SCSI_In_DBx__3__DM1 EQU CYREG_PRT2_DM1\r
-SCSI_In_DBx__3__DM2 EQU CYREG_PRT2_DM2\r
-SCSI_In_DBx__3__DR EQU CYREG_PRT2_DR\r
-SCSI_In_DBx__3__INP_DIS EQU CYREG_PRT2_INP_DIS\r
-SCSI_In_DBx__3__INTTYPE EQU CYREG_PICU2_INTTYPE5\r
-SCSI_In_DBx__3__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
-SCSI_In_DBx__3__LCD_EN EQU CYREG_PRT2_LCD_EN\r
-SCSI_In_DBx__3__MASK EQU 0x20\r
-SCSI_In_DBx__3__PC EQU CYREG_PRT2_PC5\r
-SCSI_In_DBx__3__PORT EQU 2\r
-SCSI_In_DBx__3__PRT EQU CYREG_PRT2_PRT\r
-SCSI_In_DBx__3__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
-SCSI_In_DBx__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
-SCSI_In_DBx__3__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
-SCSI_In_DBx__3__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
-SCSI_In_DBx__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
-SCSI_In_DBx__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
-SCSI_In_DBx__3__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
-SCSI_In_DBx__3__PS EQU CYREG_PRT2_PS\r
-SCSI_In_DBx__3__SHIFT EQU 5\r
-SCSI_In_DBx__3__SLW EQU CYREG_PRT2_SLW\r
-SCSI_In_DBx__4__AG EQU CYREG_PRT2_AG\r
-SCSI_In_DBx__4__AMUX EQU CYREG_PRT2_AMUX\r
-SCSI_In_DBx__4__BIE EQU CYREG_PRT2_BIE\r
-SCSI_In_DBx__4__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
-SCSI_In_DBx__4__BYP EQU CYREG_PRT2_BYP\r
-SCSI_In_DBx__4__CTL EQU CYREG_PRT2_CTL\r
-SCSI_In_DBx__4__DM0 EQU CYREG_PRT2_DM0\r
-SCSI_In_DBx__4__DM1 EQU CYREG_PRT2_DM1\r
-SCSI_In_DBx__4__DM2 EQU CYREG_PRT2_DM2\r
-SCSI_In_DBx__4__DR EQU CYREG_PRT2_DR\r
-SCSI_In_DBx__4__INP_DIS EQU CYREG_PRT2_INP_DIS\r
-SCSI_In_DBx__4__INTTYPE EQU CYREG_PICU2_INTTYPE4\r
-SCSI_In_DBx__4__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
-SCSI_In_DBx__4__LCD_EN EQU CYREG_PRT2_LCD_EN\r
-SCSI_In_DBx__4__MASK EQU 0x10\r
-SCSI_In_DBx__4__PC EQU CYREG_PRT2_PC4\r
-SCSI_In_DBx__4__PORT EQU 2\r
-SCSI_In_DBx__4__PRT EQU CYREG_PRT2_PRT\r
-SCSI_In_DBx__4__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
-SCSI_In_DBx__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
-SCSI_In_DBx__4__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
-SCSI_In_DBx__4__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
-SCSI_In_DBx__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
-SCSI_In_DBx__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
-SCSI_In_DBx__4__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
-SCSI_In_DBx__4__PS EQU CYREG_PRT2_PS\r
-SCSI_In_DBx__4__SHIFT EQU 4\r
-SCSI_In_DBx__4__SLW EQU CYREG_PRT2_SLW\r
-SCSI_In_DBx__5__AG EQU CYREG_PRT2_AG\r
-SCSI_In_DBx__5__AMUX EQU CYREG_PRT2_AMUX\r
-SCSI_In_DBx__5__BIE EQU CYREG_PRT2_BIE\r
-SCSI_In_DBx__5__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
-SCSI_In_DBx__5__BYP EQU CYREG_PRT2_BYP\r
-SCSI_In_DBx__5__CTL EQU CYREG_PRT2_CTL\r
-SCSI_In_DBx__5__DM0 EQU CYREG_PRT2_DM0\r
-SCSI_In_DBx__5__DM1 EQU CYREG_PRT2_DM1\r
-SCSI_In_DBx__5__DM2 EQU CYREG_PRT2_DM2\r
-SCSI_In_DBx__5__DR EQU CYREG_PRT2_DR\r
-SCSI_In_DBx__5__INP_DIS EQU CYREG_PRT2_INP_DIS\r
-SCSI_In_DBx__5__INTTYPE EQU CYREG_PICU2_INTTYPE3\r
-SCSI_In_DBx__5__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
-SCSI_In_DBx__5__LCD_EN EQU CYREG_PRT2_LCD_EN\r
-SCSI_In_DBx__5__MASK EQU 0x08\r
-SCSI_In_DBx__5__PC EQU CYREG_PRT2_PC3\r
-SCSI_In_DBx__5__PORT EQU 2\r
-SCSI_In_DBx__5__PRT EQU CYREG_PRT2_PRT\r
-SCSI_In_DBx__5__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
-SCSI_In_DBx__5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
-SCSI_In_DBx__5__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
-SCSI_In_DBx__5__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
-SCSI_In_DBx__5__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
-SCSI_In_DBx__5__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
-SCSI_In_DBx__5__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
-SCSI_In_DBx__5__PS EQU CYREG_PRT2_PS\r
-SCSI_In_DBx__5__SHIFT EQU 3\r
-SCSI_In_DBx__5__SLW EQU CYREG_PRT2_SLW\r
-SCSI_In_DBx__6__AG EQU CYREG_PRT2_AG\r
-SCSI_In_DBx__6__AMUX EQU CYREG_PRT2_AMUX\r
-SCSI_In_DBx__6__BIE EQU CYREG_PRT2_BIE\r
-SCSI_In_DBx__6__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
-SCSI_In_DBx__6__BYP EQU CYREG_PRT2_BYP\r
-SCSI_In_DBx__6__CTL EQU CYREG_PRT2_CTL\r
-SCSI_In_DBx__6__DM0 EQU CYREG_PRT2_DM0\r
-SCSI_In_DBx__6__DM1 EQU CYREG_PRT2_DM1\r
-SCSI_In_DBx__6__DM2 EQU CYREG_PRT2_DM2\r
-SCSI_In_DBx__6__DR EQU CYREG_PRT2_DR\r
-SCSI_In_DBx__6__INP_DIS EQU CYREG_PRT2_INP_DIS\r
-SCSI_In_DBx__6__INTTYPE EQU CYREG_PICU2_INTTYPE2\r
-SCSI_In_DBx__6__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
-SCSI_In_DBx__6__LCD_EN EQU CYREG_PRT2_LCD_EN\r
-SCSI_In_DBx__6__MASK EQU 0x04\r
-SCSI_In_DBx__6__PC EQU CYREG_PRT2_PC2\r
-SCSI_In_DBx__6__PORT EQU 2\r
-SCSI_In_DBx__6__PRT EQU CYREG_PRT2_PRT\r
-SCSI_In_DBx__6__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
-SCSI_In_DBx__6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
-SCSI_In_DBx__6__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
-SCSI_In_DBx__6__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
-SCSI_In_DBx__6__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
-SCSI_In_DBx__6__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
-SCSI_In_DBx__6__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
-SCSI_In_DBx__6__PS EQU CYREG_PRT2_PS\r
-SCSI_In_DBx__6__SHIFT EQU 2\r
-SCSI_In_DBx__6__SLW EQU CYREG_PRT2_SLW\r
-SCSI_In_DBx__7__AG EQU CYREG_PRT2_AG\r
-SCSI_In_DBx__7__AMUX EQU CYREG_PRT2_AMUX\r
-SCSI_In_DBx__7__BIE EQU CYREG_PRT2_BIE\r
-SCSI_In_DBx__7__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
-SCSI_In_DBx__7__BYP EQU CYREG_PRT2_BYP\r
-SCSI_In_DBx__7__CTL EQU CYREG_PRT2_CTL\r
-SCSI_In_DBx__7__DM0 EQU CYREG_PRT2_DM0\r
-SCSI_In_DBx__7__DM1 EQU CYREG_PRT2_DM1\r
-SCSI_In_DBx__7__DM2 EQU CYREG_PRT2_DM2\r
-SCSI_In_DBx__7__DR EQU CYREG_PRT2_DR\r
-SCSI_In_DBx__7__INP_DIS EQU CYREG_PRT2_INP_DIS\r
-SCSI_In_DBx__7__INTTYPE EQU CYREG_PICU2_INTTYPE1\r
-SCSI_In_DBx__7__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
-SCSI_In_DBx__7__LCD_EN EQU CYREG_PRT2_LCD_EN\r
-SCSI_In_DBx__7__MASK EQU 0x02\r
-SCSI_In_DBx__7__PC EQU CYREG_PRT2_PC1\r
-SCSI_In_DBx__7__PORT EQU 2\r
-SCSI_In_DBx__7__PRT EQU CYREG_PRT2_PRT\r
-SCSI_In_DBx__7__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
-SCSI_In_DBx__7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
-SCSI_In_DBx__7__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
-SCSI_In_DBx__7__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
-SCSI_In_DBx__7__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
-SCSI_In_DBx__7__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
-SCSI_In_DBx__7__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
-SCSI_In_DBx__7__PS EQU CYREG_PRT2_PS\r
-SCSI_In_DBx__7__SHIFT EQU 1\r
-SCSI_In_DBx__7__SLW EQU CYREG_PRT2_SLW\r
-SCSI_In_DBx__DB0__AG EQU CYREG_PRT12_AG\r
-SCSI_In_DBx__DB0__BIE EQU CYREG_PRT12_BIE\r
-SCSI_In_DBx__DB0__BIT_MASK EQU CYREG_PRT12_BIT_MASK\r
-SCSI_In_DBx__DB0__BYP EQU CYREG_PRT12_BYP\r
-SCSI_In_DBx__DB0__DM0 EQU CYREG_PRT12_DM0\r
-SCSI_In_DBx__DB0__DM1 EQU CYREG_PRT12_DM1\r
-SCSI_In_DBx__DB0__DM2 EQU CYREG_PRT12_DM2\r
-SCSI_In_DBx__DB0__DR EQU CYREG_PRT12_DR\r
-SCSI_In_DBx__DB0__INP_DIS EQU CYREG_PRT12_INP_DIS\r
-SCSI_In_DBx__DB0__INTTYPE EQU CYREG_PICU12_INTTYPE4\r
-SCSI_In_DBx__DB0__MASK EQU 0x10\r
-SCSI_In_DBx__DB0__PC EQU CYREG_PRT12_PC4\r
-SCSI_In_DBx__DB0__PORT EQU 12\r
-SCSI_In_DBx__DB0__PRT EQU CYREG_PRT12_PRT\r
-SCSI_In_DBx__DB0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN\r
-SCSI_In_DBx__DB0__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0\r
-SCSI_In_DBx__DB0__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1\r
-SCSI_In_DBx__DB0__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0\r
-SCSI_In_DBx__DB0__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1\r
-SCSI_In_DBx__DB0__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT\r
-SCSI_In_DBx__DB0__PS EQU CYREG_PRT12_PS\r
-SCSI_In_DBx__DB0__SHIFT EQU 4\r
-SCSI_In_DBx__DB0__SIO_CFG EQU CYREG_PRT12_SIO_CFG\r
-SCSI_In_DBx__DB0__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF\r
-SCSI_In_DBx__DB0__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN\r
-SCSI_In_DBx__DB0__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ\r
-SCSI_In_DBx__DB0__SLW EQU CYREG_PRT12_SLW\r
-SCSI_In_DBx__DB1__AG EQU CYREG_PRT2_AG\r
-SCSI_In_DBx__DB1__AMUX EQU CYREG_PRT2_AMUX\r
-SCSI_In_DBx__DB1__BIE EQU CYREG_PRT2_BIE\r
-SCSI_In_DBx__DB1__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
-SCSI_In_DBx__DB1__BYP EQU CYREG_PRT2_BYP\r
-SCSI_In_DBx__DB1__CTL EQU CYREG_PRT2_CTL\r
-SCSI_In_DBx__DB1__DM0 EQU CYREG_PRT2_DM0\r
-SCSI_In_DBx__DB1__DM1 EQU CYREG_PRT2_DM1\r
-SCSI_In_DBx__DB1__DM2 EQU CYREG_PRT2_DM2\r
-SCSI_In_DBx__DB1__DR EQU CYREG_PRT2_DR\r
-SCSI_In_DBx__DB1__INP_DIS EQU CYREG_PRT2_INP_DIS\r
-SCSI_In_DBx__DB1__INTTYPE EQU CYREG_PICU2_INTTYPE7\r
-SCSI_In_DBx__DB1__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
-SCSI_In_DBx__DB1__LCD_EN EQU CYREG_PRT2_LCD_EN\r
-SCSI_In_DBx__DB1__MASK EQU 0x80\r
-SCSI_In_DBx__DB1__PC EQU CYREG_PRT2_PC7\r
-SCSI_In_DBx__DB1__PORT EQU 2\r
-SCSI_In_DBx__DB1__PRT EQU CYREG_PRT2_PRT\r
-SCSI_In_DBx__DB1__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
-SCSI_In_DBx__DB1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
-SCSI_In_DBx__DB1__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
-SCSI_In_DBx__DB1__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
-SCSI_In_DBx__DB1__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
-SCSI_In_DBx__DB1__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
-SCSI_In_DBx__DB1__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
-SCSI_In_DBx__DB1__PS EQU CYREG_PRT2_PS\r
-SCSI_In_DBx__DB1__SHIFT EQU 7\r
-SCSI_In_DBx__DB1__SLW EQU CYREG_PRT2_SLW\r
-SCSI_In_DBx__DB2__AG EQU CYREG_PRT2_AG\r
-SCSI_In_DBx__DB2__AMUX EQU CYREG_PRT2_AMUX\r
-SCSI_In_DBx__DB2__BIE EQU CYREG_PRT2_BIE\r
-SCSI_In_DBx__DB2__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
-SCSI_In_DBx__DB2__BYP EQU CYREG_PRT2_BYP\r
-SCSI_In_DBx__DB2__CTL EQU CYREG_PRT2_CTL\r
-SCSI_In_DBx__DB2__DM0 EQU CYREG_PRT2_DM0\r
-SCSI_In_DBx__DB2__DM1 EQU CYREG_PRT2_DM1\r
-SCSI_In_DBx__DB2__DM2 EQU CYREG_PRT2_DM2\r
-SCSI_In_DBx__DB2__DR EQU CYREG_PRT2_DR\r
-SCSI_In_DBx__DB2__INP_DIS EQU CYREG_PRT2_INP_DIS\r
-SCSI_In_DBx__DB2__INTTYPE EQU CYREG_PICU2_INTTYPE6\r
-SCSI_In_DBx__DB2__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
-SCSI_In_DBx__DB2__LCD_EN EQU CYREG_PRT2_LCD_EN\r
-SCSI_In_DBx__DB2__MASK EQU 0x40\r
-SCSI_In_DBx__DB2__PC EQU CYREG_PRT2_PC6\r
-SCSI_In_DBx__DB2__PORT EQU 2\r
-SCSI_In_DBx__DB2__PRT EQU CYREG_PRT2_PRT\r
-SCSI_In_DBx__DB2__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
-SCSI_In_DBx__DB2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
-SCSI_In_DBx__DB2__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
-SCSI_In_DBx__DB2__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
-SCSI_In_DBx__DB2__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
-SCSI_In_DBx__DB2__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
-SCSI_In_DBx__DB2__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
-SCSI_In_DBx__DB2__PS EQU CYREG_PRT2_PS\r
-SCSI_In_DBx__DB2__SHIFT EQU 6\r
-SCSI_In_DBx__DB2__SLW EQU CYREG_PRT2_SLW\r
-SCSI_In_DBx__DB3__AG EQU CYREG_PRT2_AG\r
-SCSI_In_DBx__DB3__AMUX EQU CYREG_PRT2_AMUX\r
-SCSI_In_DBx__DB3__BIE EQU CYREG_PRT2_BIE\r
-SCSI_In_DBx__DB3__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
-SCSI_In_DBx__DB3__BYP EQU CYREG_PRT2_BYP\r
-SCSI_In_DBx__DB3__CTL EQU CYREG_PRT2_CTL\r
-SCSI_In_DBx__DB3__DM0 EQU CYREG_PRT2_DM0\r
-SCSI_In_DBx__DB3__DM1 EQU CYREG_PRT2_DM1\r
-SCSI_In_DBx__DB3__DM2 EQU CYREG_PRT2_DM2\r
-SCSI_In_DBx__DB3__DR EQU CYREG_PRT2_DR\r
-SCSI_In_DBx__DB3__INP_DIS EQU CYREG_PRT2_INP_DIS\r
-SCSI_In_DBx__DB3__INTTYPE EQU CYREG_PICU2_INTTYPE5\r
-SCSI_In_DBx__DB3__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
-SCSI_In_DBx__DB3__LCD_EN EQU CYREG_PRT2_LCD_EN\r
-SCSI_In_DBx__DB3__MASK EQU 0x20\r
-SCSI_In_DBx__DB3__PC EQU CYREG_PRT2_PC5\r
-SCSI_In_DBx__DB3__PORT EQU 2\r
-SCSI_In_DBx__DB3__PRT EQU CYREG_PRT2_PRT\r
-SCSI_In_DBx__DB3__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
-SCSI_In_DBx__DB3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
-SCSI_In_DBx__DB3__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
-SCSI_In_DBx__DB3__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
-SCSI_In_DBx__DB3__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
-SCSI_In_DBx__DB3__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
-SCSI_In_DBx__DB3__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
-SCSI_In_DBx__DB3__PS EQU CYREG_PRT2_PS\r
-SCSI_In_DBx__DB3__SHIFT EQU 5\r
-SCSI_In_DBx__DB3__SLW EQU CYREG_PRT2_SLW\r
-SCSI_In_DBx__DB4__AG EQU CYREG_PRT2_AG\r
-SCSI_In_DBx__DB4__AMUX EQU CYREG_PRT2_AMUX\r
-SCSI_In_DBx__DB4__BIE EQU CYREG_PRT2_BIE\r
-SCSI_In_DBx__DB4__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
-SCSI_In_DBx__DB4__BYP EQU CYREG_PRT2_BYP\r
-SCSI_In_DBx__DB4__CTL EQU CYREG_PRT2_CTL\r
-SCSI_In_DBx__DB4__DM0 EQU CYREG_PRT2_DM0\r
-SCSI_In_DBx__DB4__DM1 EQU CYREG_PRT2_DM1\r
-SCSI_In_DBx__DB4__DM2 EQU CYREG_PRT2_DM2\r
-SCSI_In_DBx__DB4__DR EQU CYREG_PRT2_DR\r
-SCSI_In_DBx__DB4__INP_DIS EQU CYREG_PRT2_INP_DIS\r
-SCSI_In_DBx__DB4__INTTYPE EQU CYREG_PICU2_INTTYPE4\r
-SCSI_In_DBx__DB4__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
-SCSI_In_DBx__DB4__LCD_EN EQU CYREG_PRT2_LCD_EN\r
-SCSI_In_DBx__DB4__MASK EQU 0x10\r
-SCSI_In_DBx__DB4__PC EQU CYREG_PRT2_PC4\r
-SCSI_In_DBx__DB4__PORT EQU 2\r
-SCSI_In_DBx__DB4__PRT EQU CYREG_PRT2_PRT\r
-SCSI_In_DBx__DB4__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
-SCSI_In_DBx__DB4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
-SCSI_In_DBx__DB4__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
-SCSI_In_DBx__DB4__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
-SCSI_In_DBx__DB4__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
-SCSI_In_DBx__DB4__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
-SCSI_In_DBx__DB4__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
-SCSI_In_DBx__DB4__PS EQU CYREG_PRT2_PS\r
-SCSI_In_DBx__DB4__SHIFT EQU 4\r
-SCSI_In_DBx__DB4__SLW EQU CYREG_PRT2_SLW\r
-SCSI_In_DBx__DB5__AG EQU CYREG_PRT2_AG\r
-SCSI_In_DBx__DB5__AMUX EQU CYREG_PRT2_AMUX\r
-SCSI_In_DBx__DB5__BIE EQU CYREG_PRT2_BIE\r
-SCSI_In_DBx__DB5__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
-SCSI_In_DBx__DB5__BYP EQU CYREG_PRT2_BYP\r
-SCSI_In_DBx__DB5__CTL EQU CYREG_PRT2_CTL\r
-SCSI_In_DBx__DB5__DM0 EQU CYREG_PRT2_DM0\r
-SCSI_In_DBx__DB5__DM1 EQU CYREG_PRT2_DM1\r
-SCSI_In_DBx__DB5__DM2 EQU CYREG_PRT2_DM2\r
-SCSI_In_DBx__DB5__DR EQU CYREG_PRT2_DR\r
-SCSI_In_DBx__DB5__INP_DIS EQU CYREG_PRT2_INP_DIS\r
-SCSI_In_DBx__DB5__INTTYPE EQU CYREG_PICU2_INTTYPE3\r
-SCSI_In_DBx__DB5__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
-SCSI_In_DBx__DB5__LCD_EN EQU CYREG_PRT2_LCD_EN\r
-SCSI_In_DBx__DB5__MASK EQU 0x08\r
-SCSI_In_DBx__DB5__PC EQU CYREG_PRT2_PC3\r
-SCSI_In_DBx__DB5__PORT EQU 2\r
-SCSI_In_DBx__DB5__PRT EQU CYREG_PRT2_PRT\r
-SCSI_In_DBx__DB5__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
-SCSI_In_DBx__DB5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
-SCSI_In_DBx__DB5__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
-SCSI_In_DBx__DB5__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
-SCSI_In_DBx__DB5__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
-SCSI_In_DBx__DB5__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
-SCSI_In_DBx__DB5__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
-SCSI_In_DBx__DB5__PS EQU CYREG_PRT2_PS\r
-SCSI_In_DBx__DB5__SHIFT EQU 3\r
-SCSI_In_DBx__DB5__SLW EQU CYREG_PRT2_SLW\r
-SCSI_In_DBx__DB6__AG EQU CYREG_PRT2_AG\r
-SCSI_In_DBx__DB6__AMUX EQU CYREG_PRT2_AMUX\r
-SCSI_In_DBx__DB6__BIE EQU CYREG_PRT2_BIE\r
-SCSI_In_DBx__DB6__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
-SCSI_In_DBx__DB6__BYP EQU CYREG_PRT2_BYP\r
-SCSI_In_DBx__DB6__CTL EQU CYREG_PRT2_CTL\r
-SCSI_In_DBx__DB6__DM0 EQU CYREG_PRT2_DM0\r
-SCSI_In_DBx__DB6__DM1 EQU CYREG_PRT2_DM1\r
-SCSI_In_DBx__DB6__DM2 EQU CYREG_PRT2_DM2\r
-SCSI_In_DBx__DB6__DR EQU CYREG_PRT2_DR\r
-SCSI_In_DBx__DB6__INP_DIS EQU CYREG_PRT2_INP_DIS\r
-SCSI_In_DBx__DB6__INTTYPE EQU CYREG_PICU2_INTTYPE2\r
-SCSI_In_DBx__DB6__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
-SCSI_In_DBx__DB6__LCD_EN EQU CYREG_PRT2_LCD_EN\r
-SCSI_In_DBx__DB6__MASK EQU 0x04\r
-SCSI_In_DBx__DB6__PC EQU CYREG_PRT2_PC2\r
-SCSI_In_DBx__DB6__PORT EQU 2\r
-SCSI_In_DBx__DB6__PRT EQU CYREG_PRT2_PRT\r
-SCSI_In_DBx__DB6__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
-SCSI_In_DBx__DB6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
-SCSI_In_DBx__DB6__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
-SCSI_In_DBx__DB6__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
-SCSI_In_DBx__DB6__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
-SCSI_In_DBx__DB6__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
-SCSI_In_DBx__DB6__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
-SCSI_In_DBx__DB6__PS EQU CYREG_PRT2_PS\r
-SCSI_In_DBx__DB6__SHIFT EQU 2\r
-SCSI_In_DBx__DB6__SLW EQU CYREG_PRT2_SLW\r
-SCSI_In_DBx__DB7__AG EQU CYREG_PRT2_AG\r
-SCSI_In_DBx__DB7__AMUX EQU CYREG_PRT2_AMUX\r
-SCSI_In_DBx__DB7__BIE EQU CYREG_PRT2_BIE\r
-SCSI_In_DBx__DB7__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
-SCSI_In_DBx__DB7__BYP EQU CYREG_PRT2_BYP\r
-SCSI_In_DBx__DB7__CTL EQU CYREG_PRT2_CTL\r
-SCSI_In_DBx__DB7__DM0 EQU CYREG_PRT2_DM0\r
-SCSI_In_DBx__DB7__DM1 EQU CYREG_PRT2_DM1\r
-SCSI_In_DBx__DB7__DM2 EQU CYREG_PRT2_DM2\r
-SCSI_In_DBx__DB7__DR EQU CYREG_PRT2_DR\r
-SCSI_In_DBx__DB7__INP_DIS EQU CYREG_PRT2_INP_DIS\r
-SCSI_In_DBx__DB7__INTTYPE EQU CYREG_PICU2_INTTYPE1\r
-SCSI_In_DBx__DB7__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
-SCSI_In_DBx__DB7__LCD_EN EQU CYREG_PRT2_LCD_EN\r
-SCSI_In_DBx__DB7__MASK EQU 0x02\r
-SCSI_In_DBx__DB7__PC EQU CYREG_PRT2_PC1\r
-SCSI_In_DBx__DB7__PORT EQU 2\r
-SCSI_In_DBx__DB7__PRT EQU CYREG_PRT2_PRT\r
-SCSI_In_DBx__DB7__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
-SCSI_In_DBx__DB7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
-SCSI_In_DBx__DB7__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
-SCSI_In_DBx__DB7__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
-SCSI_In_DBx__DB7__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
-SCSI_In_DBx__DB7__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
-SCSI_In_DBx__DB7__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
-SCSI_In_DBx__DB7__PS EQU CYREG_PRT2_PS\r
-SCSI_In_DBx__DB7__SHIFT EQU 1\r
-SCSI_In_DBx__DB7__SLW EQU CYREG_PRT2_SLW\r
-\r
-/* SD_DAT1 */\r
-SD_DAT1__0__INTTYPE EQU CYREG_PICU3_INTTYPE0\r
-SD_DAT1__0__MASK EQU 0x01\r
-SD_DAT1__0__PC EQU CYREG_PRT3_PC0\r
-SD_DAT1__0__PORT EQU 3\r
-SD_DAT1__0__SHIFT EQU 0\r
-SD_DAT1__AG EQU CYREG_PRT3_AG\r
-SD_DAT1__AMUX EQU CYREG_PRT3_AMUX\r
-SD_DAT1__BIE EQU CYREG_PRT3_BIE\r
-SD_DAT1__BIT_MASK EQU CYREG_PRT3_BIT_MASK\r
-SD_DAT1__BYP EQU CYREG_PRT3_BYP\r
-SD_DAT1__CTL EQU CYREG_PRT3_CTL\r
-SD_DAT1__DM0 EQU CYREG_PRT3_DM0\r
-SD_DAT1__DM1 EQU CYREG_PRT3_DM1\r
-SD_DAT1__DM2 EQU CYREG_PRT3_DM2\r
-SD_DAT1__DR EQU CYREG_PRT3_DR\r
-SD_DAT1__INP_DIS EQU CYREG_PRT3_INP_DIS\r
-SD_DAT1__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE\r
-SD_DAT1__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG\r
-SD_DAT1__LCD_EN EQU CYREG_PRT3_LCD_EN\r
-SD_DAT1__MASK EQU 0x01\r
-SD_DAT1__PORT EQU 3\r
-SD_DAT1__PRT EQU CYREG_PRT3_PRT\r
-SD_DAT1__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL\r
-SD_DAT1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN\r
-SD_DAT1__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0\r
-SD_DAT1__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1\r
-SD_DAT1__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0\r
-SD_DAT1__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1\r
-SD_DAT1__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT\r
-SD_DAT1__PS EQU CYREG_PRT3_PS\r
-SD_DAT1__SHIFT EQU 0\r
-SD_DAT1__SLW EQU CYREG_PRT3_SLW\r
-\r
-/* SD_DAT2 */\r
-SD_DAT2__0__INTTYPE EQU CYREG_PICU3_INTTYPE5\r
-SD_DAT2__0__MASK EQU 0x20\r
-SD_DAT2__0__PC EQU CYREG_PRT3_PC5\r
-SD_DAT2__0__PORT EQU 3\r
-SD_DAT2__0__SHIFT EQU 5\r
-SD_DAT2__AG EQU CYREG_PRT3_AG\r
-SD_DAT2__AMUX EQU CYREG_PRT3_AMUX\r
-SD_DAT2__BIE EQU CYREG_PRT3_BIE\r
-SD_DAT2__BIT_MASK EQU CYREG_PRT3_BIT_MASK\r
-SD_DAT2__BYP EQU CYREG_PRT3_BYP\r
-SD_DAT2__CTL EQU CYREG_PRT3_CTL\r
-SD_DAT2__DM0 EQU CYREG_PRT3_DM0\r
-SD_DAT2__DM1 EQU CYREG_PRT3_DM1\r
-SD_DAT2__DM2 EQU CYREG_PRT3_DM2\r
-SD_DAT2__DR EQU CYREG_PRT3_DR\r
-SD_DAT2__INP_DIS EQU CYREG_PRT3_INP_DIS\r
-SD_DAT2__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE\r
-SD_DAT2__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG\r
-SD_DAT2__LCD_EN EQU CYREG_PRT3_LCD_EN\r
-SD_DAT2__MASK EQU 0x20\r
-SD_DAT2__PORT EQU 3\r
-SD_DAT2__PRT EQU CYREG_PRT3_PRT\r
-SD_DAT2__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL\r
-SD_DAT2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN\r
-SD_DAT2__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0\r
-SD_DAT2__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1\r
-SD_DAT2__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0\r
-SD_DAT2__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1\r
-SD_DAT2__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT\r
-SD_DAT2__PS EQU CYREG_PRT3_PS\r
-SD_DAT2__SHIFT EQU 5\r
-SD_DAT2__SLW EQU CYREG_PRT3_SLW\r
-\r
-/* SD_MISO */\r
-SD_MISO__0__INTTYPE EQU CYREG_PICU3_INTTYPE1\r
-SD_MISO__0__MASK EQU 0x02\r
-SD_MISO__0__PC EQU CYREG_PRT3_PC1\r
-SD_MISO__0__PORT EQU 3\r
-SD_MISO__0__SHIFT EQU 1\r
-SD_MISO__AG EQU CYREG_PRT3_AG\r
-SD_MISO__AMUX EQU CYREG_PRT3_AMUX\r
-SD_MISO__BIE EQU CYREG_PRT3_BIE\r
-SD_MISO__BIT_MASK EQU CYREG_PRT3_BIT_MASK\r
-SD_MISO__BYP EQU CYREG_PRT3_BYP\r
-SD_MISO__CTL EQU CYREG_PRT3_CTL\r
-SD_MISO__DM0 EQU CYREG_PRT3_DM0\r
-SD_MISO__DM1 EQU CYREG_PRT3_DM1\r
-SD_MISO__DM2 EQU CYREG_PRT3_DM2\r
-SD_MISO__DR EQU CYREG_PRT3_DR\r
-SD_MISO__INP_DIS EQU CYREG_PRT3_INP_DIS\r
-SD_MISO__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE\r
-SD_MISO__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG\r
-SD_MISO__LCD_EN EQU CYREG_PRT3_LCD_EN\r
-SD_MISO__MASK EQU 0x02\r
-SD_MISO__PORT EQU 3\r
-SD_MISO__PRT EQU CYREG_PRT3_PRT\r
-SD_MISO__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL\r
-SD_MISO__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN\r
-SD_MISO__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0\r
-SD_MISO__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1\r
-SD_MISO__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0\r
-SD_MISO__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1\r
-SD_MISO__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT\r
-SD_MISO__PS EQU CYREG_PRT3_PS\r
-SD_MISO__SHIFT EQU 1\r
-SD_MISO__SLW EQU CYREG_PRT3_SLW\r
-\r
-/* SD_MOSI */\r
-SD_MOSI__0__INTTYPE EQU CYREG_PICU3_INTTYPE3\r
-SD_MOSI__0__MASK EQU 0x08\r
-SD_MOSI__0__PC EQU CYREG_PRT3_PC3\r
-SD_MOSI__0__PORT EQU 3\r
-SD_MOSI__0__SHIFT EQU 3\r
-SD_MOSI__AG EQU CYREG_PRT3_AG\r
-SD_MOSI__AMUX EQU CYREG_PRT3_AMUX\r
-SD_MOSI__BIE EQU CYREG_PRT3_BIE\r
-SD_MOSI__BIT_MASK EQU CYREG_PRT3_BIT_MASK\r
-SD_MOSI__BYP EQU CYREG_PRT3_BYP\r
-SD_MOSI__CTL EQU CYREG_PRT3_CTL\r
-SD_MOSI__DM0 EQU CYREG_PRT3_DM0\r
-SD_MOSI__DM1 EQU CYREG_PRT3_DM1\r
-SD_MOSI__DM2 EQU CYREG_PRT3_DM2\r
-SD_MOSI__DR EQU CYREG_PRT3_DR\r
-SD_MOSI__INP_DIS EQU CYREG_PRT3_INP_DIS\r
-SD_MOSI__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE\r
-SD_MOSI__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG\r
-SD_MOSI__LCD_EN EQU CYREG_PRT3_LCD_EN\r
-SD_MOSI__MASK EQU 0x08\r
-SD_MOSI__PORT EQU 3\r
-SD_MOSI__PRT EQU CYREG_PRT3_PRT\r
-SD_MOSI__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL\r
-SD_MOSI__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN\r
-SD_MOSI__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0\r
-SD_MOSI__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1\r
-SD_MOSI__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0\r
-SD_MOSI__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1\r
-SD_MOSI__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT\r
-SD_MOSI__PS EQU CYREG_PRT3_PS\r
-SD_MOSI__SHIFT EQU 3\r
-SD_MOSI__SLW EQU CYREG_PRT3_SLW\r
-\r
-/* SCSI_CLK */\r
-SCSI_CLK__CFG0 EQU CYREG_CLKDIST_DCFG1_CFG0\r
-SCSI_CLK__CFG1 EQU CYREG_CLKDIST_DCFG1_CFG1\r
-SCSI_CLK__CFG2 EQU CYREG_CLKDIST_DCFG1_CFG2\r
-SCSI_CLK__CFG2_SRC_SEL_MASK EQU 0x07\r
-SCSI_CLK__INDEX EQU 0x01\r
-SCSI_CLK__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2\r
-SCSI_CLK__PM_ACT_MSK EQU 0x02\r
-SCSI_CLK__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2\r
-SCSI_CLK__PM_STBY_MSK EQU 0x02\r
-\r
-/* SCSI_Out */\r
-SCSI_Out__0__AG EQU CYREG_PRT4_AG\r
-SCSI_Out__0__AMUX EQU CYREG_PRT4_AMUX\r
-SCSI_Out__0__BIE EQU CYREG_PRT4_BIE\r
-SCSI_Out__0__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
-SCSI_Out__0__BYP EQU CYREG_PRT4_BYP\r
-SCSI_Out__0__CTL EQU CYREG_PRT4_CTL\r
-SCSI_Out__0__DM0 EQU CYREG_PRT4_DM0\r
-SCSI_Out__0__DM1 EQU CYREG_PRT4_DM1\r
-SCSI_Out__0__DM2 EQU CYREG_PRT4_DM2\r
-SCSI_Out__0__DR EQU CYREG_PRT4_DR\r
-SCSI_Out__0__INP_DIS EQU CYREG_PRT4_INP_DIS\r
-SCSI_Out__0__INTTYPE EQU CYREG_PICU4_INTTYPE3\r
-SCSI_Out__0__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
-SCSI_Out__0__LCD_EN EQU CYREG_PRT4_LCD_EN\r
-SCSI_Out__0__MASK EQU 0x08\r
-SCSI_Out__0__PC EQU CYREG_PRT4_PC3\r
-SCSI_Out__0__PORT EQU 4\r
-SCSI_Out__0__PRT EQU CYREG_PRT4_PRT\r
-SCSI_Out__0__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
-SCSI_Out__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
-SCSI_Out__0__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
-SCSI_Out__0__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
-SCSI_Out__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
-SCSI_Out__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
-SCSI_Out__0__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
-SCSI_Out__0__PS EQU CYREG_PRT4_PS\r
-SCSI_Out__0__SHIFT EQU 3\r
-SCSI_Out__0__SLW EQU CYREG_PRT4_SLW\r
-SCSI_Out__1__AG EQU CYREG_PRT4_AG\r
-SCSI_Out__1__AMUX EQU CYREG_PRT4_AMUX\r
-SCSI_Out__1__BIE EQU CYREG_PRT4_BIE\r
-SCSI_Out__1__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
-SCSI_Out__1__BYP EQU CYREG_PRT4_BYP\r
-SCSI_Out__1__CTL EQU CYREG_PRT4_CTL\r
-SCSI_Out__1__DM0 EQU CYREG_PRT4_DM0\r
-SCSI_Out__1__DM1 EQU CYREG_PRT4_DM1\r
-SCSI_Out__1__DM2 EQU CYREG_PRT4_DM2\r
-SCSI_Out__1__DR EQU CYREG_PRT4_DR\r
-SCSI_Out__1__INP_DIS EQU CYREG_PRT4_INP_DIS\r
-SCSI_Out__1__INTTYPE EQU CYREG_PICU4_INTTYPE2\r
-SCSI_Out__1__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
-SCSI_Out__1__LCD_EN EQU CYREG_PRT4_LCD_EN\r
-SCSI_Out__1__MASK EQU 0x04\r
-SCSI_Out__1__PC EQU CYREG_PRT4_PC2\r
-SCSI_Out__1__PORT EQU 4\r
-SCSI_Out__1__PRT EQU CYREG_PRT4_PRT\r
-SCSI_Out__1__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
-SCSI_Out__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
-SCSI_Out__1__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
-SCSI_Out__1__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
-SCSI_Out__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
-SCSI_Out__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
-SCSI_Out__1__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
-SCSI_Out__1__PS EQU CYREG_PRT4_PS\r
-SCSI_Out__1__SHIFT EQU 2\r
-SCSI_Out__1__SLW EQU CYREG_PRT4_SLW\r
-SCSI_Out__2__AG EQU CYREG_PRT0_AG\r
-SCSI_Out__2__AMUX EQU CYREG_PRT0_AMUX\r
-SCSI_Out__2__BIE EQU CYREG_PRT0_BIE\r
-SCSI_Out__2__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
-SCSI_Out__2__BYP EQU CYREG_PRT0_BYP\r
-SCSI_Out__2__CTL EQU CYREG_PRT0_CTL\r
-SCSI_Out__2__DM0 EQU CYREG_PRT0_DM0\r
-SCSI_Out__2__DM1 EQU CYREG_PRT0_DM1\r
-SCSI_Out__2__DM2 EQU CYREG_PRT0_DM2\r
-SCSI_Out__2__DR EQU CYREG_PRT0_DR\r
-SCSI_Out__2__INP_DIS EQU CYREG_PRT0_INP_DIS\r
-SCSI_Out__2__INTTYPE EQU CYREG_PICU0_INTTYPE7\r
-SCSI_Out__2__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
-SCSI_Out__2__LCD_EN EQU CYREG_PRT0_LCD_EN\r
-SCSI_Out__2__MASK EQU 0x80\r
-SCSI_Out__2__PC EQU CYREG_PRT0_PC7\r
-SCSI_Out__2__PORT EQU 0\r
-SCSI_Out__2__PRT EQU CYREG_PRT0_PRT\r
-SCSI_Out__2__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
-SCSI_Out__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
-SCSI_Out__2__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
-SCSI_Out__2__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
-SCSI_Out__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
-SCSI_Out__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
-SCSI_Out__2__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
-SCSI_Out__2__PS EQU CYREG_PRT0_PS\r
-SCSI_Out__2__SHIFT EQU 7\r
-SCSI_Out__2__SLW EQU CYREG_PRT0_SLW\r
-SCSI_Out__3__AG EQU CYREG_PRT0_AG\r
-SCSI_Out__3__AMUX EQU CYREG_PRT0_AMUX\r
-SCSI_Out__3__BIE EQU CYREG_PRT0_BIE\r
-SCSI_Out__3__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
-SCSI_Out__3__BYP EQU CYREG_PRT0_BYP\r
-SCSI_Out__3__CTL EQU CYREG_PRT0_CTL\r
-SCSI_Out__3__DM0 EQU CYREG_PRT0_DM0\r
-SCSI_Out__3__DM1 EQU CYREG_PRT0_DM1\r
-SCSI_Out__3__DM2 EQU CYREG_PRT0_DM2\r
-SCSI_Out__3__DR EQU CYREG_PRT0_DR\r
-SCSI_Out__3__INP_DIS EQU CYREG_PRT0_INP_DIS\r
-SCSI_Out__3__INTTYPE EQU CYREG_PICU0_INTTYPE6\r
-SCSI_Out__3__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
-SCSI_Out__3__LCD_EN EQU CYREG_PRT0_LCD_EN\r
-SCSI_Out__3__MASK EQU 0x40\r
-SCSI_Out__3__PC EQU CYREG_PRT0_PC6\r
-SCSI_Out__3__PORT EQU 0\r
-SCSI_Out__3__PRT EQU CYREG_PRT0_PRT\r
-SCSI_Out__3__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
-SCSI_Out__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
-SCSI_Out__3__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
-SCSI_Out__3__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
-SCSI_Out__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
-SCSI_Out__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
-SCSI_Out__3__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
-SCSI_Out__3__PS EQU CYREG_PRT0_PS\r
-SCSI_Out__3__SHIFT EQU 6\r
-SCSI_Out__3__SLW EQU CYREG_PRT0_SLW\r
-SCSI_Out__4__AG EQU CYREG_PRT0_AG\r
-SCSI_Out__4__AMUX EQU CYREG_PRT0_AMUX\r
-SCSI_Out__4__BIE EQU CYREG_PRT0_BIE\r
-SCSI_Out__4__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
-SCSI_Out__4__BYP EQU CYREG_PRT0_BYP\r
-SCSI_Out__4__CTL EQU CYREG_PRT0_CTL\r
-SCSI_Out__4__DM0 EQU CYREG_PRT0_DM0\r
-SCSI_Out__4__DM1 EQU CYREG_PRT0_DM1\r
-SCSI_Out__4__DM2 EQU CYREG_PRT0_DM2\r
-SCSI_Out__4__DR EQU CYREG_PRT0_DR\r
-SCSI_Out__4__INP_DIS EQU CYREG_PRT0_INP_DIS\r
-SCSI_Out__4__INTTYPE EQU CYREG_PICU0_INTTYPE5\r
-SCSI_Out__4__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
-SCSI_Out__4__LCD_EN EQU CYREG_PRT0_LCD_EN\r
-SCSI_Out__4__MASK EQU 0x20\r
-SCSI_Out__4__PC EQU CYREG_PRT0_PC5\r
-SCSI_Out__4__PORT EQU 0\r
-SCSI_Out__4__PRT EQU CYREG_PRT0_PRT\r
-SCSI_Out__4__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
-SCSI_Out__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
-SCSI_Out__4__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
-SCSI_Out__4__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
-SCSI_Out__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
-SCSI_Out__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
-SCSI_Out__4__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
-SCSI_Out__4__PS EQU CYREG_PRT0_PS\r
-SCSI_Out__4__SHIFT EQU 5\r
-SCSI_Out__4__SLW EQU CYREG_PRT0_SLW\r
-SCSI_Out__5__AG EQU CYREG_PRT0_AG\r
-SCSI_Out__5__AMUX EQU CYREG_PRT0_AMUX\r
-SCSI_Out__5__BIE EQU CYREG_PRT0_BIE\r
-SCSI_Out__5__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
-SCSI_Out__5__BYP EQU CYREG_PRT0_BYP\r
-SCSI_Out__5__CTL EQU CYREG_PRT0_CTL\r
-SCSI_Out__5__DM0 EQU CYREG_PRT0_DM0\r
-SCSI_Out__5__DM1 EQU CYREG_PRT0_DM1\r
-SCSI_Out__5__DM2 EQU CYREG_PRT0_DM2\r
-SCSI_Out__5__DR EQU CYREG_PRT0_DR\r
-SCSI_Out__5__INP_DIS EQU CYREG_PRT0_INP_DIS\r
-SCSI_Out__5__INTTYPE EQU CYREG_PICU0_INTTYPE4\r
-SCSI_Out__5__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
-SCSI_Out__5__LCD_EN EQU CYREG_PRT0_LCD_EN\r
-SCSI_Out__5__MASK EQU 0x10\r
-SCSI_Out__5__PC EQU CYREG_PRT0_PC4\r
-SCSI_Out__5__PORT EQU 0\r
-SCSI_Out__5__PRT EQU CYREG_PRT0_PRT\r
-SCSI_Out__5__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
-SCSI_Out__5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
-SCSI_Out__5__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
-SCSI_Out__5__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
-SCSI_Out__5__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
-SCSI_Out__5__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
-SCSI_Out__5__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
-SCSI_Out__5__PS EQU CYREG_PRT0_PS\r
-SCSI_Out__5__SHIFT EQU 4\r
-SCSI_Out__5__SLW EQU CYREG_PRT0_SLW\r
-SCSI_Out__6__AG EQU CYREG_PRT0_AG\r
-SCSI_Out__6__AMUX EQU CYREG_PRT0_AMUX\r
-SCSI_Out__6__BIE EQU CYREG_PRT0_BIE\r
-SCSI_Out__6__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
-SCSI_Out__6__BYP EQU CYREG_PRT0_BYP\r
-SCSI_Out__6__CTL EQU CYREG_PRT0_CTL\r
-SCSI_Out__6__DM0 EQU CYREG_PRT0_DM0\r
-SCSI_Out__6__DM1 EQU CYREG_PRT0_DM1\r
-SCSI_Out__6__DM2 EQU CYREG_PRT0_DM2\r
-SCSI_Out__6__DR EQU CYREG_PRT0_DR\r
-SCSI_Out__6__INP_DIS EQU CYREG_PRT0_INP_DIS\r
-SCSI_Out__6__INTTYPE EQU CYREG_PICU0_INTTYPE3\r
-SCSI_Out__6__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
-SCSI_Out__6__LCD_EN EQU CYREG_PRT0_LCD_EN\r
-SCSI_Out__6__MASK EQU 0x08\r
-SCSI_Out__6__PC EQU CYREG_PRT0_PC3\r
-SCSI_Out__6__PORT EQU 0\r
-SCSI_Out__6__PRT EQU CYREG_PRT0_PRT\r
-SCSI_Out__6__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
-SCSI_Out__6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
-SCSI_Out__6__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
-SCSI_Out__6__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
-SCSI_Out__6__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
-SCSI_Out__6__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
-SCSI_Out__6__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
-SCSI_Out__6__PS EQU CYREG_PRT0_PS\r
-SCSI_Out__6__SHIFT EQU 3\r
-SCSI_Out__6__SLW EQU CYREG_PRT0_SLW\r
-SCSI_Out__7__AG EQU CYREG_PRT0_AG\r
-SCSI_Out__7__AMUX EQU CYREG_PRT0_AMUX\r
-SCSI_Out__7__BIE EQU CYREG_PRT0_BIE\r
-SCSI_Out__7__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
-SCSI_Out__7__BYP EQU CYREG_PRT0_BYP\r
-SCSI_Out__7__CTL EQU CYREG_PRT0_CTL\r
-SCSI_Out__7__DM0 EQU CYREG_PRT0_DM0\r
-SCSI_Out__7__DM1 EQU CYREG_PRT0_DM1\r
-SCSI_Out__7__DM2 EQU CYREG_PRT0_DM2\r
-SCSI_Out__7__DR EQU CYREG_PRT0_DR\r
-SCSI_Out__7__INP_DIS EQU CYREG_PRT0_INP_DIS\r
-SCSI_Out__7__INTTYPE EQU CYREG_PICU0_INTTYPE2\r
-SCSI_Out__7__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
-SCSI_Out__7__LCD_EN EQU CYREG_PRT0_LCD_EN\r
-SCSI_Out__7__MASK EQU 0x04\r
-SCSI_Out__7__PC EQU CYREG_PRT0_PC2\r
-SCSI_Out__7__PORT EQU 0\r
-SCSI_Out__7__PRT EQU CYREG_PRT0_PRT\r
-SCSI_Out__7__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
-SCSI_Out__7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
-SCSI_Out__7__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
-SCSI_Out__7__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
-SCSI_Out__7__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
-SCSI_Out__7__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
-SCSI_Out__7__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
-SCSI_Out__7__PS EQU CYREG_PRT0_PS\r
-SCSI_Out__7__SHIFT EQU 2\r
-SCSI_Out__7__SLW EQU CYREG_PRT0_SLW\r
-SCSI_Out__8__AG EQU CYREG_PRT0_AG\r
-SCSI_Out__8__AMUX EQU CYREG_PRT0_AMUX\r
-SCSI_Out__8__BIE EQU CYREG_PRT0_BIE\r
-SCSI_Out__8__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
-SCSI_Out__8__BYP EQU CYREG_PRT0_BYP\r
-SCSI_Out__8__CTL EQU CYREG_PRT0_CTL\r
-SCSI_Out__8__DM0 EQU CYREG_PRT0_DM0\r
-SCSI_Out__8__DM1 EQU CYREG_PRT0_DM1\r
-SCSI_Out__8__DM2 EQU CYREG_PRT0_DM2\r
-SCSI_Out__8__DR EQU CYREG_PRT0_DR\r
-SCSI_Out__8__INP_DIS EQU CYREG_PRT0_INP_DIS\r
-SCSI_Out__8__INTTYPE EQU CYREG_PICU0_INTTYPE1\r
-SCSI_Out__8__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
-SCSI_Out__8__LCD_EN EQU CYREG_PRT0_LCD_EN\r
-SCSI_Out__8__MASK EQU 0x02\r
-SCSI_Out__8__PC EQU CYREG_PRT0_PC1\r
-SCSI_Out__8__PORT EQU 0\r
-SCSI_Out__8__PRT EQU CYREG_PRT0_PRT\r
-SCSI_Out__8__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
-SCSI_Out__8__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
-SCSI_Out__8__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
-SCSI_Out__8__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
-SCSI_Out__8__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
-SCSI_Out__8__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
-SCSI_Out__8__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
-SCSI_Out__8__PS EQU CYREG_PRT0_PS\r
-SCSI_Out__8__SHIFT EQU 1\r
-SCSI_Out__8__SLW EQU CYREG_PRT0_SLW\r
-SCSI_Out__9__AG EQU CYREG_PRT0_AG\r
-SCSI_Out__9__AMUX EQU CYREG_PRT0_AMUX\r
-SCSI_Out__9__BIE EQU CYREG_PRT0_BIE\r
-SCSI_Out__9__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
-SCSI_Out__9__BYP EQU CYREG_PRT0_BYP\r
-SCSI_Out__9__CTL EQU CYREG_PRT0_CTL\r
-SCSI_Out__9__DM0 EQU CYREG_PRT0_DM0\r
-SCSI_Out__9__DM1 EQU CYREG_PRT0_DM1\r
-SCSI_Out__9__DM2 EQU CYREG_PRT0_DM2\r
-SCSI_Out__9__DR EQU CYREG_PRT0_DR\r
-SCSI_Out__9__INP_DIS EQU CYREG_PRT0_INP_DIS\r
-SCSI_Out__9__INTTYPE EQU CYREG_PICU0_INTTYPE0\r
-SCSI_Out__9__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
-SCSI_Out__9__LCD_EN EQU CYREG_PRT0_LCD_EN\r
-SCSI_Out__9__MASK EQU 0x01\r
-SCSI_Out__9__PC EQU CYREG_PRT0_PC0\r
-SCSI_Out__9__PORT EQU 0\r
-SCSI_Out__9__PRT EQU CYREG_PRT0_PRT\r
-SCSI_Out__9__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
-SCSI_Out__9__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
-SCSI_Out__9__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
-SCSI_Out__9__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
-SCSI_Out__9__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
-SCSI_Out__9__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
-SCSI_Out__9__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
-SCSI_Out__9__PS EQU CYREG_PRT0_PS\r
-SCSI_Out__9__SHIFT EQU 0\r
-SCSI_Out__9__SLW EQU CYREG_PRT0_SLW\r
-SCSI_Out__ACK__AG EQU CYREG_PRT0_AG\r
-SCSI_Out__ACK__AMUX EQU CYREG_PRT0_AMUX\r
-SCSI_Out__ACK__BIE EQU CYREG_PRT0_BIE\r
-SCSI_Out__ACK__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
-SCSI_Out__ACK__BYP EQU CYREG_PRT0_BYP\r
-SCSI_Out__ACK__CTL EQU CYREG_PRT0_CTL\r
-SCSI_Out__ACK__DM0 EQU CYREG_PRT0_DM0\r
-SCSI_Out__ACK__DM1 EQU CYREG_PRT0_DM1\r
-SCSI_Out__ACK__DM2 EQU CYREG_PRT0_DM2\r
-SCSI_Out__ACK__DR EQU CYREG_PRT0_DR\r
-SCSI_Out__ACK__INP_DIS EQU CYREG_PRT0_INP_DIS\r
-SCSI_Out__ACK__INTTYPE EQU CYREG_PICU0_INTTYPE6\r
-SCSI_Out__ACK__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
-SCSI_Out__ACK__LCD_EN EQU CYREG_PRT0_LCD_EN\r
-SCSI_Out__ACK__MASK EQU 0x40\r
-SCSI_Out__ACK__PC EQU CYREG_PRT0_PC6\r
-SCSI_Out__ACK__PORT EQU 0\r
-SCSI_Out__ACK__PRT EQU CYREG_PRT0_PRT\r
-SCSI_Out__ACK__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
-SCSI_Out__ACK__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
-SCSI_Out__ACK__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
-SCSI_Out__ACK__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
-SCSI_Out__ACK__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
-SCSI_Out__ACK__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
-SCSI_Out__ACK__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
-SCSI_Out__ACK__PS EQU CYREG_PRT0_PS\r
-SCSI_Out__ACK__SHIFT EQU 6\r
-SCSI_Out__ACK__SLW EQU CYREG_PRT0_SLW\r
-SCSI_Out__ATN__AG EQU CYREG_PRT4_AG\r
-SCSI_Out__ATN__AMUX EQU CYREG_PRT4_AMUX\r
-SCSI_Out__ATN__BIE EQU CYREG_PRT4_BIE\r
-SCSI_Out__ATN__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
-SCSI_Out__ATN__BYP EQU CYREG_PRT4_BYP\r
-SCSI_Out__ATN__CTL EQU CYREG_PRT4_CTL\r
-SCSI_Out__ATN__DM0 EQU CYREG_PRT4_DM0\r
-SCSI_Out__ATN__DM1 EQU CYREG_PRT4_DM1\r
-SCSI_Out__ATN__DM2 EQU CYREG_PRT4_DM2\r
-SCSI_Out__ATN__DR EQU CYREG_PRT4_DR\r
-SCSI_Out__ATN__INP_DIS EQU CYREG_PRT4_INP_DIS\r
-SCSI_Out__ATN__INTTYPE EQU CYREG_PICU4_INTTYPE2\r
-SCSI_Out__ATN__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
-SCSI_Out__ATN__LCD_EN EQU CYREG_PRT4_LCD_EN\r
-SCSI_Out__ATN__MASK EQU 0x04\r
-SCSI_Out__ATN__PC EQU CYREG_PRT4_PC2\r
-SCSI_Out__ATN__PORT EQU 4\r
-SCSI_Out__ATN__PRT EQU CYREG_PRT4_PRT\r
-SCSI_Out__ATN__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
-SCSI_Out__ATN__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
-SCSI_Out__ATN__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
-SCSI_Out__ATN__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
-SCSI_Out__ATN__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
-SCSI_Out__ATN__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
-SCSI_Out__ATN__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
-SCSI_Out__ATN__PS EQU CYREG_PRT4_PS\r
-SCSI_Out__ATN__SHIFT EQU 2\r
-SCSI_Out__ATN__SLW EQU CYREG_PRT4_SLW\r
-SCSI_Out__BSY__AG EQU CYREG_PRT0_AG\r
-SCSI_Out__BSY__AMUX EQU CYREG_PRT0_AMUX\r
-SCSI_Out__BSY__BIE EQU CYREG_PRT0_BIE\r
-SCSI_Out__BSY__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
-SCSI_Out__BSY__BYP EQU CYREG_PRT0_BYP\r
-SCSI_Out__BSY__CTL EQU CYREG_PRT0_CTL\r
-SCSI_Out__BSY__DM0 EQU CYREG_PRT0_DM0\r
-SCSI_Out__BSY__DM1 EQU CYREG_PRT0_DM1\r
-SCSI_Out__BSY__DM2 EQU CYREG_PRT0_DM2\r
-SCSI_Out__BSY__DR EQU CYREG_PRT0_DR\r
-SCSI_Out__BSY__INP_DIS EQU CYREG_PRT0_INP_DIS\r
-SCSI_Out__BSY__INTTYPE EQU CYREG_PICU0_INTTYPE7\r
-SCSI_Out__BSY__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
-SCSI_Out__BSY__LCD_EN EQU CYREG_PRT0_LCD_EN\r
-SCSI_Out__BSY__MASK EQU 0x80\r
-SCSI_Out__BSY__PC EQU CYREG_PRT0_PC7\r
-SCSI_Out__BSY__PORT EQU 0\r
-SCSI_Out__BSY__PRT EQU CYREG_PRT0_PRT\r
-SCSI_Out__BSY__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
-SCSI_Out__BSY__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
-SCSI_Out__BSY__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
-SCSI_Out__BSY__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
-SCSI_Out__BSY__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
-SCSI_Out__BSY__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
-SCSI_Out__BSY__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
-SCSI_Out__BSY__PS EQU CYREG_PRT0_PS\r
-SCSI_Out__BSY__SHIFT EQU 7\r
-SCSI_Out__BSY__SLW EQU CYREG_PRT0_SLW\r
-SCSI_Out__CD_raw__AG EQU CYREG_PRT0_AG\r
-SCSI_Out__CD_raw__AMUX EQU CYREG_PRT0_AMUX\r
-SCSI_Out__CD_raw__BIE EQU CYREG_PRT0_BIE\r
-SCSI_Out__CD_raw__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
-SCSI_Out__CD_raw__BYP EQU CYREG_PRT0_BYP\r
-SCSI_Out__CD_raw__CTL EQU CYREG_PRT0_CTL\r
-SCSI_Out__CD_raw__DM0 EQU CYREG_PRT0_DM0\r
-SCSI_Out__CD_raw__DM1 EQU CYREG_PRT0_DM1\r
-SCSI_Out__CD_raw__DM2 EQU CYREG_PRT0_DM2\r
-SCSI_Out__CD_raw__DR EQU CYREG_PRT0_DR\r
-SCSI_Out__CD_raw__INP_DIS EQU CYREG_PRT0_INP_DIS\r
-SCSI_Out__CD_raw__INTTYPE EQU CYREG_PICU0_INTTYPE2\r
-SCSI_Out__CD_raw__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
-SCSI_Out__CD_raw__LCD_EN EQU CYREG_PRT0_LCD_EN\r
-SCSI_Out__CD_raw__MASK EQU 0x04\r
-SCSI_Out__CD_raw__PC EQU CYREG_PRT0_PC2\r
-SCSI_Out__CD_raw__PORT EQU 0\r
-SCSI_Out__CD_raw__PRT EQU CYREG_PRT0_PRT\r
-SCSI_Out__CD_raw__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
-SCSI_Out__CD_raw__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
-SCSI_Out__CD_raw__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
-SCSI_Out__CD_raw__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
-SCSI_Out__CD_raw__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
-SCSI_Out__CD_raw__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
-SCSI_Out__CD_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
-SCSI_Out__CD_raw__PS EQU CYREG_PRT0_PS\r
-SCSI_Out__CD_raw__SHIFT EQU 2\r
-SCSI_Out__CD_raw__SLW EQU CYREG_PRT0_SLW\r
-SCSI_Out__DBP_raw__AG EQU CYREG_PRT4_AG\r
-SCSI_Out__DBP_raw__AMUX EQU CYREG_PRT4_AMUX\r
-SCSI_Out__DBP_raw__BIE EQU CYREG_PRT4_BIE\r
-SCSI_Out__DBP_raw__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
-SCSI_Out__DBP_raw__BYP EQU CYREG_PRT4_BYP\r
-SCSI_Out__DBP_raw__CTL EQU CYREG_PRT4_CTL\r
-SCSI_Out__DBP_raw__DM0 EQU CYREG_PRT4_DM0\r
-SCSI_Out__DBP_raw__DM1 EQU CYREG_PRT4_DM1\r
-SCSI_Out__DBP_raw__DM2 EQU CYREG_PRT4_DM2\r
-SCSI_Out__DBP_raw__DR EQU CYREG_PRT4_DR\r
-SCSI_Out__DBP_raw__INP_DIS EQU CYREG_PRT4_INP_DIS\r
-SCSI_Out__DBP_raw__INTTYPE EQU CYREG_PICU4_INTTYPE3\r
-SCSI_Out__DBP_raw__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
-SCSI_Out__DBP_raw__LCD_EN EQU CYREG_PRT4_LCD_EN\r
-SCSI_Out__DBP_raw__MASK EQU 0x08\r
-SCSI_Out__DBP_raw__PC EQU CYREG_PRT4_PC3\r
-SCSI_Out__DBP_raw__PORT EQU 4\r
-SCSI_Out__DBP_raw__PRT EQU CYREG_PRT4_PRT\r
-SCSI_Out__DBP_raw__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
-SCSI_Out__DBP_raw__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
-SCSI_Out__DBP_raw__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
-SCSI_Out__DBP_raw__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
-SCSI_Out__DBP_raw__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
-SCSI_Out__DBP_raw__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
-SCSI_Out__DBP_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
-SCSI_Out__DBP_raw__PS EQU CYREG_PRT4_PS\r
-SCSI_Out__DBP_raw__SHIFT EQU 3\r
-SCSI_Out__DBP_raw__SLW EQU CYREG_PRT4_SLW\r
-SCSI_Out__IO_raw__AG EQU CYREG_PRT0_AG\r
-SCSI_Out__IO_raw__AMUX EQU CYREG_PRT0_AMUX\r
-SCSI_Out__IO_raw__BIE EQU CYREG_PRT0_BIE\r
-SCSI_Out__IO_raw__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
-SCSI_Out__IO_raw__BYP EQU CYREG_PRT0_BYP\r
-SCSI_Out__IO_raw__CTL EQU CYREG_PRT0_CTL\r
-SCSI_Out__IO_raw__DM0 EQU CYREG_PRT0_DM0\r
-SCSI_Out__IO_raw__DM1 EQU CYREG_PRT0_DM1\r
-SCSI_Out__IO_raw__DM2 EQU CYREG_PRT0_DM2\r
-SCSI_Out__IO_raw__DR EQU CYREG_PRT0_DR\r
-SCSI_Out__IO_raw__INP_DIS EQU CYREG_PRT0_INP_DIS\r
-SCSI_Out__IO_raw__INTTYPE EQU CYREG_PICU0_INTTYPE0\r
-SCSI_Out__IO_raw__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
-SCSI_Out__IO_raw__LCD_EN EQU CYREG_PRT0_LCD_EN\r
-SCSI_Out__IO_raw__MASK EQU 0x01\r
-SCSI_Out__IO_raw__PC EQU CYREG_PRT0_PC0\r
-SCSI_Out__IO_raw__PORT EQU 0\r
-SCSI_Out__IO_raw__PRT EQU CYREG_PRT0_PRT\r
-SCSI_Out__IO_raw__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
-SCSI_Out__IO_raw__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
-SCSI_Out__IO_raw__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
-SCSI_Out__IO_raw__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
-SCSI_Out__IO_raw__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
-SCSI_Out__IO_raw__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
-SCSI_Out__IO_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
-SCSI_Out__IO_raw__PS EQU CYREG_PRT0_PS\r
-SCSI_Out__IO_raw__SHIFT EQU 0\r
-SCSI_Out__IO_raw__SLW EQU CYREG_PRT0_SLW\r
-SCSI_Out__MSG_raw__AG EQU CYREG_PRT0_AG\r
-SCSI_Out__MSG_raw__AMUX EQU CYREG_PRT0_AMUX\r
-SCSI_Out__MSG_raw__BIE EQU CYREG_PRT0_BIE\r
-SCSI_Out__MSG_raw__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
-SCSI_Out__MSG_raw__BYP EQU CYREG_PRT0_BYP\r
-SCSI_Out__MSG_raw__CTL EQU CYREG_PRT0_CTL\r
-SCSI_Out__MSG_raw__DM0 EQU CYREG_PRT0_DM0\r
-SCSI_Out__MSG_raw__DM1 EQU CYREG_PRT0_DM1\r
-SCSI_Out__MSG_raw__DM2 EQU CYREG_PRT0_DM2\r
-SCSI_Out__MSG_raw__DR EQU CYREG_PRT0_DR\r
-SCSI_Out__MSG_raw__INP_DIS EQU CYREG_PRT0_INP_DIS\r
-SCSI_Out__MSG_raw__INTTYPE EQU CYREG_PICU0_INTTYPE4\r
-SCSI_Out__MSG_raw__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
-SCSI_Out__MSG_raw__LCD_EN EQU CYREG_PRT0_LCD_EN\r
-SCSI_Out__MSG_raw__MASK EQU 0x10\r
-SCSI_Out__MSG_raw__PC EQU CYREG_PRT0_PC4\r
-SCSI_Out__MSG_raw__PORT EQU 0\r
-SCSI_Out__MSG_raw__PRT EQU CYREG_PRT0_PRT\r
-SCSI_Out__MSG_raw__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
-SCSI_Out__MSG_raw__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
-SCSI_Out__MSG_raw__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
-SCSI_Out__MSG_raw__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
-SCSI_Out__MSG_raw__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
-SCSI_Out__MSG_raw__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
-SCSI_Out__MSG_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
-SCSI_Out__MSG_raw__PS EQU CYREG_PRT0_PS\r
-SCSI_Out__MSG_raw__SHIFT EQU 4\r
-SCSI_Out__MSG_raw__SLW EQU CYREG_PRT0_SLW\r
-SCSI_Out__REQ__AG EQU CYREG_PRT0_AG\r
-SCSI_Out__REQ__AMUX EQU CYREG_PRT0_AMUX\r
-SCSI_Out__REQ__BIE EQU CYREG_PRT0_BIE\r
-SCSI_Out__REQ__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
-SCSI_Out__REQ__BYP EQU CYREG_PRT0_BYP\r
-SCSI_Out__REQ__CTL EQU CYREG_PRT0_CTL\r
-SCSI_Out__REQ__DM0 EQU CYREG_PRT0_DM0\r
-SCSI_Out__REQ__DM1 EQU CYREG_PRT0_DM1\r
-SCSI_Out__REQ__DM2 EQU CYREG_PRT0_DM2\r
-SCSI_Out__REQ__DR EQU CYREG_PRT0_DR\r
-SCSI_Out__REQ__INP_DIS EQU CYREG_PRT0_INP_DIS\r
-SCSI_Out__REQ__INTTYPE EQU CYREG_PICU0_INTTYPE1\r
-SCSI_Out__REQ__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
-SCSI_Out__REQ__LCD_EN EQU CYREG_PRT0_LCD_EN\r
-SCSI_Out__REQ__MASK EQU 0x02\r
-SCSI_Out__REQ__PC EQU CYREG_PRT0_PC1\r
-SCSI_Out__REQ__PORT EQU 0\r
-SCSI_Out__REQ__PRT EQU CYREG_PRT0_PRT\r
-SCSI_Out__REQ__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
-SCSI_Out__REQ__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
-SCSI_Out__REQ__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
-SCSI_Out__REQ__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
-SCSI_Out__REQ__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
-SCSI_Out__REQ__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
-SCSI_Out__REQ__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
-SCSI_Out__REQ__PS EQU CYREG_PRT0_PS\r
-SCSI_Out__REQ__SHIFT EQU 1\r
-SCSI_Out__REQ__SLW EQU CYREG_PRT0_SLW\r
-SCSI_Out__RST__AG EQU CYREG_PRT0_AG\r
-SCSI_Out__RST__AMUX EQU CYREG_PRT0_AMUX\r
-SCSI_Out__RST__BIE EQU CYREG_PRT0_BIE\r
-SCSI_Out__RST__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
-SCSI_Out__RST__BYP EQU CYREG_PRT0_BYP\r
-SCSI_Out__RST__CTL EQU CYREG_PRT0_CTL\r
-SCSI_Out__RST__DM0 EQU CYREG_PRT0_DM0\r
-SCSI_Out__RST__DM1 EQU CYREG_PRT0_DM1\r
-SCSI_Out__RST__DM2 EQU CYREG_PRT0_DM2\r
-SCSI_Out__RST__DR EQU CYREG_PRT0_DR\r
-SCSI_Out__RST__INP_DIS EQU CYREG_PRT0_INP_DIS\r
-SCSI_Out__RST__INTTYPE EQU CYREG_PICU0_INTTYPE5\r
-SCSI_Out__RST__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
-SCSI_Out__RST__LCD_EN EQU CYREG_PRT0_LCD_EN\r
-SCSI_Out__RST__MASK EQU 0x20\r
-SCSI_Out__RST__PC EQU CYREG_PRT0_PC5\r
-SCSI_Out__RST__PORT EQU 0\r
-SCSI_Out__RST__PRT EQU CYREG_PRT0_PRT\r
-SCSI_Out__RST__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
-SCSI_Out__RST__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
-SCSI_Out__RST__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
-SCSI_Out__RST__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
-SCSI_Out__RST__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
-SCSI_Out__RST__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
-SCSI_Out__RST__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
-SCSI_Out__RST__PS EQU CYREG_PRT0_PS\r
-SCSI_Out__RST__SHIFT EQU 5\r
-SCSI_Out__RST__SLW EQU CYREG_PRT0_SLW\r
-SCSI_Out__SEL__AG EQU CYREG_PRT0_AG\r
-SCSI_Out__SEL__AMUX EQU CYREG_PRT0_AMUX\r
-SCSI_Out__SEL__BIE EQU CYREG_PRT0_BIE\r
-SCSI_Out__SEL__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
-SCSI_Out__SEL__BYP EQU CYREG_PRT0_BYP\r
-SCSI_Out__SEL__CTL EQU CYREG_PRT0_CTL\r
-SCSI_Out__SEL__DM0 EQU CYREG_PRT0_DM0\r
-SCSI_Out__SEL__DM1 EQU CYREG_PRT0_DM1\r
-SCSI_Out__SEL__DM2 EQU CYREG_PRT0_DM2\r
-SCSI_Out__SEL__DR EQU CYREG_PRT0_DR\r
-SCSI_Out__SEL__INP_DIS EQU CYREG_PRT0_INP_DIS\r
-SCSI_Out__SEL__INTTYPE EQU CYREG_PICU0_INTTYPE3\r
-SCSI_Out__SEL__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
-SCSI_Out__SEL__LCD_EN EQU CYREG_PRT0_LCD_EN\r
-SCSI_Out__SEL__MASK EQU 0x08\r
-SCSI_Out__SEL__PC EQU CYREG_PRT0_PC3\r
-SCSI_Out__SEL__PORT EQU 0\r
-SCSI_Out__SEL__PRT EQU CYREG_PRT0_PRT\r
-SCSI_Out__SEL__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
-SCSI_Out__SEL__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
-SCSI_Out__SEL__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
-SCSI_Out__SEL__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
-SCSI_Out__SEL__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
-SCSI_Out__SEL__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
-SCSI_Out__SEL__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
-SCSI_Out__SEL__PS EQU CYREG_PRT0_PS\r
-SCSI_Out__SEL__SHIFT EQU 3\r
-SCSI_Out__SEL__SLW EQU CYREG_PRT0_SLW\r
-\r
-/* SCSI_Out_Bits */\r
-SCSI_Out_Bits_Sync_ctrl_reg__0__MASK EQU 0x01\r
-SCSI_Out_Bits_Sync_ctrl_reg__0__POS EQU 0\r
-SCSI_Out_Bits_Sync_ctrl_reg__1__MASK EQU 0x02\r
-SCSI_Out_Bits_Sync_ctrl_reg__1__POS EQU 1\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB08_09_ACTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB08_09_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB08_09_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB08_09_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB08_09_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB08_09_MSK\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB08_09_MSK\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB08_09_MSK\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB08_09_MSK\r
-SCSI_Out_Bits_Sync_ctrl_reg__2__MASK EQU 0x04\r
-SCSI_Out_Bits_Sync_ctrl_reg__2__POS EQU 2\r
-SCSI_Out_Bits_Sync_ctrl_reg__3__MASK EQU 0x08\r
-SCSI_Out_Bits_Sync_ctrl_reg__3__POS EQU 3\r
-SCSI_Out_Bits_Sync_ctrl_reg__4__MASK EQU 0x10\r
-SCSI_Out_Bits_Sync_ctrl_reg__4__POS EQU 4\r
-SCSI_Out_Bits_Sync_ctrl_reg__5__MASK EQU 0x20\r
-SCSI_Out_Bits_Sync_ctrl_reg__5__POS EQU 5\r
-SCSI_Out_Bits_Sync_ctrl_reg__6__MASK EQU 0x40\r
-SCSI_Out_Bits_Sync_ctrl_reg__6__POS EQU 6\r
-SCSI_Out_Bits_Sync_ctrl_reg__7__MASK EQU 0x80\r
-SCSI_Out_Bits_Sync_ctrl_reg__7__POS EQU 7\r
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB08_ACTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B1_UDB08_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B1_UDB08_ST_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B1_UDB08_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B1_UDB08_ST_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__MASK EQU 0xFF\r
-SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB08_MSK_ACTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB08_MSK_ACTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B1_UDB08_MSK\r
-\r
-/* SCSI_Out_Ctl */\r
-SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01\r
-SCSI_Out_Ctl_Sync_ctrl_reg__0__POS EQU 0\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB08_09_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB08_09_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB08_09_MSK\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB08_09_MSK\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK\r
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB08_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB08_ST_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB08_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB08_ST_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__MASK EQU 0x01\r
-SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB08_MSK\r
-\r
-/* SCSI_Out_DBx */\r
-SCSI_Out_DBx__0__AG EQU CYREG_PRT6_AG\r
-SCSI_Out_DBx__0__AMUX EQU CYREG_PRT6_AMUX\r
-SCSI_Out_DBx__0__BIE EQU CYREG_PRT6_BIE\r
-SCSI_Out_DBx__0__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
-SCSI_Out_DBx__0__BYP EQU CYREG_PRT6_BYP\r
-SCSI_Out_DBx__0__CTL EQU CYREG_PRT6_CTL\r
-SCSI_Out_DBx__0__DM0 EQU CYREG_PRT6_DM0\r
-SCSI_Out_DBx__0__DM1 EQU CYREG_PRT6_DM1\r
-SCSI_Out_DBx__0__DM2 EQU CYREG_PRT6_DM2\r
-SCSI_Out_DBx__0__DR EQU CYREG_PRT6_DR\r
-SCSI_Out_DBx__0__INP_DIS EQU CYREG_PRT6_INP_DIS\r
-SCSI_Out_DBx__0__INTTYPE EQU CYREG_PICU6_INTTYPE3\r
-SCSI_Out_DBx__0__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
-SCSI_Out_DBx__0__LCD_EN EQU CYREG_PRT6_LCD_EN\r
-SCSI_Out_DBx__0__MASK EQU 0x08\r
-SCSI_Out_DBx__0__PC EQU CYREG_PRT6_PC3\r
-SCSI_Out_DBx__0__PORT EQU 6\r
-SCSI_Out_DBx__0__PRT EQU CYREG_PRT6_PRT\r
-SCSI_Out_DBx__0__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
-SCSI_Out_DBx__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
-SCSI_Out_DBx__0__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
-SCSI_Out_DBx__0__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
-SCSI_Out_DBx__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
-SCSI_Out_DBx__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
-SCSI_Out_DBx__0__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
-SCSI_Out_DBx__0__PS EQU CYREG_PRT6_PS\r
-SCSI_Out_DBx__0__SHIFT EQU 3\r
-SCSI_Out_DBx__0__SLW EQU CYREG_PRT6_SLW\r
-SCSI_Out_DBx__1__AG EQU CYREG_PRT6_AG\r
-SCSI_Out_DBx__1__AMUX EQU CYREG_PRT6_AMUX\r
-SCSI_Out_DBx__1__BIE EQU CYREG_PRT6_BIE\r
-SCSI_Out_DBx__1__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
-SCSI_Out_DBx__1__BYP EQU CYREG_PRT6_BYP\r
-SCSI_Out_DBx__1__CTL EQU CYREG_PRT6_CTL\r
-SCSI_Out_DBx__1__DM0 EQU CYREG_PRT6_DM0\r
-SCSI_Out_DBx__1__DM1 EQU CYREG_PRT6_DM1\r
-SCSI_Out_DBx__1__DM2 EQU CYREG_PRT6_DM2\r
-SCSI_Out_DBx__1__DR EQU CYREG_PRT6_DR\r
-SCSI_Out_DBx__1__INP_DIS EQU CYREG_PRT6_INP_DIS\r
-SCSI_Out_DBx__1__INTTYPE EQU CYREG_PICU6_INTTYPE2\r
-SCSI_Out_DBx__1__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
-SCSI_Out_DBx__1__LCD_EN EQU CYREG_PRT6_LCD_EN\r
-SCSI_Out_DBx__1__MASK EQU 0x04\r
-SCSI_Out_DBx__1__PC EQU CYREG_PRT6_PC2\r
-SCSI_Out_DBx__1__PORT EQU 6\r
-SCSI_Out_DBx__1__PRT EQU CYREG_PRT6_PRT\r
-SCSI_Out_DBx__1__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
-SCSI_Out_DBx__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
-SCSI_Out_DBx__1__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
-SCSI_Out_DBx__1__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
-SCSI_Out_DBx__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
-SCSI_Out_DBx__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
-SCSI_Out_DBx__1__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
-SCSI_Out_DBx__1__PS EQU CYREG_PRT6_PS\r
-SCSI_Out_DBx__1__SHIFT EQU 2\r
-SCSI_Out_DBx__1__SLW EQU CYREG_PRT6_SLW\r
-SCSI_Out_DBx__2__AG EQU CYREG_PRT6_AG\r
-SCSI_Out_DBx__2__AMUX EQU CYREG_PRT6_AMUX\r
-SCSI_Out_DBx__2__BIE EQU CYREG_PRT6_BIE\r
-SCSI_Out_DBx__2__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
-SCSI_Out_DBx__2__BYP EQU CYREG_PRT6_BYP\r
-SCSI_Out_DBx__2__CTL EQU CYREG_PRT6_CTL\r
-SCSI_Out_DBx__2__DM0 EQU CYREG_PRT6_DM0\r
-SCSI_Out_DBx__2__DM1 EQU CYREG_PRT6_DM1\r
-SCSI_Out_DBx__2__DM2 EQU CYREG_PRT6_DM2\r
-SCSI_Out_DBx__2__DR EQU CYREG_PRT6_DR\r
-SCSI_Out_DBx__2__INP_DIS EQU CYREG_PRT6_INP_DIS\r
-SCSI_Out_DBx__2__INTTYPE EQU CYREG_PICU6_INTTYPE1\r
-SCSI_Out_DBx__2__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
-SCSI_Out_DBx__2__LCD_EN EQU CYREG_PRT6_LCD_EN\r
-SCSI_Out_DBx__2__MASK EQU 0x02\r
-SCSI_Out_DBx__2__PC EQU CYREG_PRT6_PC1\r
-SCSI_Out_DBx__2__PORT EQU 6\r
-SCSI_Out_DBx__2__PRT EQU CYREG_PRT6_PRT\r
-SCSI_Out_DBx__2__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
-SCSI_Out_DBx__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
-SCSI_Out_DBx__2__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
-SCSI_Out_DBx__2__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
-SCSI_Out_DBx__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
-SCSI_Out_DBx__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
-SCSI_Out_DBx__2__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
-SCSI_Out_DBx__2__PS EQU CYREG_PRT6_PS\r
-SCSI_Out_DBx__2__SHIFT EQU 1\r
-SCSI_Out_DBx__2__SLW EQU CYREG_PRT6_SLW\r
-SCSI_Out_DBx__3__AG EQU CYREG_PRT6_AG\r
-SCSI_Out_DBx__3__AMUX EQU CYREG_PRT6_AMUX\r
-SCSI_Out_DBx__3__BIE EQU CYREG_PRT6_BIE\r
-SCSI_Out_DBx__3__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
-SCSI_Out_DBx__3__BYP EQU CYREG_PRT6_BYP\r
-SCSI_Out_DBx__3__CTL EQU CYREG_PRT6_CTL\r
-SCSI_Out_DBx__3__DM0 EQU CYREG_PRT6_DM0\r
-SCSI_Out_DBx__3__DM1 EQU CYREG_PRT6_DM1\r
-SCSI_Out_DBx__3__DM2 EQU CYREG_PRT6_DM2\r
-SCSI_Out_DBx__3__DR EQU CYREG_PRT6_DR\r
-SCSI_Out_DBx__3__INP_DIS EQU CYREG_PRT6_INP_DIS\r
-SCSI_Out_DBx__3__INTTYPE EQU CYREG_PICU6_INTTYPE0\r
-SCSI_Out_DBx__3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
-SCSI_Out_DBx__3__LCD_EN EQU CYREG_PRT6_LCD_EN\r
-SCSI_Out_DBx__3__MASK EQU 0x01\r
-SCSI_Out_DBx__3__PC EQU CYREG_PRT6_PC0\r
-SCSI_Out_DBx__3__PORT EQU 6\r
-SCSI_Out_DBx__3__PRT EQU CYREG_PRT6_PRT\r
-SCSI_Out_DBx__3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
-SCSI_Out_DBx__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
-SCSI_Out_DBx__3__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
-SCSI_Out_DBx__3__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
-SCSI_Out_DBx__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
-SCSI_Out_DBx__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
-SCSI_Out_DBx__3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
-SCSI_Out_DBx__3__PS EQU CYREG_PRT6_PS\r
-SCSI_Out_DBx__3__SHIFT EQU 0\r
-SCSI_Out_DBx__3__SLW EQU CYREG_PRT6_SLW\r
-SCSI_Out_DBx__4__AG EQU CYREG_PRT4_AG\r
-SCSI_Out_DBx__4__AMUX EQU CYREG_PRT4_AMUX\r
-SCSI_Out_DBx__4__BIE EQU CYREG_PRT4_BIE\r
-SCSI_Out_DBx__4__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
-SCSI_Out_DBx__4__BYP EQU CYREG_PRT4_BYP\r
-SCSI_Out_DBx__4__CTL EQU CYREG_PRT4_CTL\r
-SCSI_Out_DBx__4__DM0 EQU CYREG_PRT4_DM0\r
-SCSI_Out_DBx__4__DM1 EQU CYREG_PRT4_DM1\r
-SCSI_Out_DBx__4__DM2 EQU CYREG_PRT4_DM2\r
-SCSI_Out_DBx__4__DR EQU CYREG_PRT4_DR\r
-SCSI_Out_DBx__4__INP_DIS EQU CYREG_PRT4_INP_DIS\r
-SCSI_Out_DBx__4__INTTYPE EQU CYREG_PICU4_INTTYPE7\r
-SCSI_Out_DBx__4__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
-SCSI_Out_DBx__4__LCD_EN EQU CYREG_PRT4_LCD_EN\r
-SCSI_Out_DBx__4__MASK EQU 0x80\r
-SCSI_Out_DBx__4__PC EQU CYREG_PRT4_PC7\r
-SCSI_Out_DBx__4__PORT EQU 4\r
-SCSI_Out_DBx__4__PRT EQU CYREG_PRT4_PRT\r
-SCSI_Out_DBx__4__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
-SCSI_Out_DBx__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
-SCSI_Out_DBx__4__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
-SCSI_Out_DBx__4__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
-SCSI_Out_DBx__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
-SCSI_Out_DBx__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
-SCSI_Out_DBx__4__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
-SCSI_Out_DBx__4__PS EQU CYREG_PRT4_PS\r
-SCSI_Out_DBx__4__SHIFT EQU 7\r
-SCSI_Out_DBx__4__SLW EQU CYREG_PRT4_SLW\r
-SCSI_Out_DBx__5__AG EQU CYREG_PRT4_AG\r
-SCSI_Out_DBx__5__AMUX EQU CYREG_PRT4_AMUX\r
-SCSI_Out_DBx__5__BIE EQU CYREG_PRT4_BIE\r
-SCSI_Out_DBx__5__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
-SCSI_Out_DBx__5__BYP EQU CYREG_PRT4_BYP\r
-SCSI_Out_DBx__5__CTL EQU CYREG_PRT4_CTL\r
-SCSI_Out_DBx__5__DM0 EQU CYREG_PRT4_DM0\r
-SCSI_Out_DBx__5__DM1 EQU CYREG_PRT4_DM1\r
-SCSI_Out_DBx__5__DM2 EQU CYREG_PRT4_DM2\r
-SCSI_Out_DBx__5__DR EQU CYREG_PRT4_DR\r
-SCSI_Out_DBx__5__INP_DIS EQU CYREG_PRT4_INP_DIS\r
-SCSI_Out_DBx__5__INTTYPE EQU CYREG_PICU4_INTTYPE6\r
-SCSI_Out_DBx__5__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
-SCSI_Out_DBx__5__LCD_EN EQU CYREG_PRT4_LCD_EN\r
-SCSI_Out_DBx__5__MASK EQU 0x40\r
-SCSI_Out_DBx__5__PC EQU CYREG_PRT4_PC6\r
-SCSI_Out_DBx__5__PORT EQU 4\r
-SCSI_Out_DBx__5__PRT EQU CYREG_PRT4_PRT\r
-SCSI_Out_DBx__5__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
-SCSI_Out_DBx__5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
-SCSI_Out_DBx__5__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
-SCSI_Out_DBx__5__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
-SCSI_Out_DBx__5__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
-SCSI_Out_DBx__5__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
-SCSI_Out_DBx__5__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
-SCSI_Out_DBx__5__PS EQU CYREG_PRT4_PS\r
-SCSI_Out_DBx__5__SHIFT EQU 6\r
-SCSI_Out_DBx__5__SLW EQU CYREG_PRT4_SLW\r
-SCSI_Out_DBx__6__AG EQU CYREG_PRT4_AG\r
-SCSI_Out_DBx__6__AMUX EQU CYREG_PRT4_AMUX\r
-SCSI_Out_DBx__6__BIE EQU CYREG_PRT4_BIE\r
-SCSI_Out_DBx__6__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
-SCSI_Out_DBx__6__BYP EQU CYREG_PRT4_BYP\r
-SCSI_Out_DBx__6__CTL EQU CYREG_PRT4_CTL\r
-SCSI_Out_DBx__6__DM0 EQU CYREG_PRT4_DM0\r
-SCSI_Out_DBx__6__DM1 EQU CYREG_PRT4_DM1\r
-SCSI_Out_DBx__6__DM2 EQU CYREG_PRT4_DM2\r
-SCSI_Out_DBx__6__DR EQU CYREG_PRT4_DR\r
-SCSI_Out_DBx__6__INP_DIS EQU CYREG_PRT4_INP_DIS\r
-SCSI_Out_DBx__6__INTTYPE EQU CYREG_PICU4_INTTYPE5\r
-SCSI_Out_DBx__6__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
-SCSI_Out_DBx__6__LCD_EN EQU CYREG_PRT4_LCD_EN\r
-SCSI_Out_DBx__6__MASK EQU 0x20\r
-SCSI_Out_DBx__6__PC EQU CYREG_PRT4_PC5\r
-SCSI_Out_DBx__6__PORT EQU 4\r
-SCSI_Out_DBx__6__PRT EQU CYREG_PRT4_PRT\r
-SCSI_Out_DBx__6__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
-SCSI_Out_DBx__6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
-SCSI_Out_DBx__6__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
-SCSI_Out_DBx__6__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
-SCSI_Out_DBx__6__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
-SCSI_Out_DBx__6__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
-SCSI_Out_DBx__6__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
-SCSI_Out_DBx__6__PS EQU CYREG_PRT4_PS\r
-SCSI_Out_DBx__6__SHIFT EQU 5\r
-SCSI_Out_DBx__6__SLW EQU CYREG_PRT4_SLW\r
-SCSI_Out_DBx__7__AG EQU CYREG_PRT4_AG\r
-SCSI_Out_DBx__7__AMUX EQU CYREG_PRT4_AMUX\r
-SCSI_Out_DBx__7__BIE EQU CYREG_PRT4_BIE\r
-SCSI_Out_DBx__7__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
-SCSI_Out_DBx__7__BYP EQU CYREG_PRT4_BYP\r
-SCSI_Out_DBx__7__CTL EQU CYREG_PRT4_CTL\r
-SCSI_Out_DBx__7__DM0 EQU CYREG_PRT4_DM0\r
-SCSI_Out_DBx__7__DM1 EQU CYREG_PRT4_DM1\r
-SCSI_Out_DBx__7__DM2 EQU CYREG_PRT4_DM2\r
-SCSI_Out_DBx__7__DR EQU CYREG_PRT4_DR\r
-SCSI_Out_DBx__7__INP_DIS EQU CYREG_PRT4_INP_DIS\r
-SCSI_Out_DBx__7__INTTYPE EQU CYREG_PICU4_INTTYPE4\r
-SCSI_Out_DBx__7__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
-SCSI_Out_DBx__7__LCD_EN EQU CYREG_PRT4_LCD_EN\r
-SCSI_Out_DBx__7__MASK EQU 0x10\r
-SCSI_Out_DBx__7__PC EQU CYREG_PRT4_PC4\r
-SCSI_Out_DBx__7__PORT EQU 4\r
-SCSI_Out_DBx__7__PRT EQU CYREG_PRT4_PRT\r
-SCSI_Out_DBx__7__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
-SCSI_Out_DBx__7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
-SCSI_Out_DBx__7__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
-SCSI_Out_DBx__7__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
-SCSI_Out_DBx__7__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
-SCSI_Out_DBx__7__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
-SCSI_Out_DBx__7__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
-SCSI_Out_DBx__7__PS EQU CYREG_PRT4_PS\r
-SCSI_Out_DBx__7__SHIFT EQU 4\r
-SCSI_Out_DBx__7__SLW EQU CYREG_PRT4_SLW\r
-SCSI_Out_DBx__DB0__AG EQU CYREG_PRT6_AG\r
-SCSI_Out_DBx__DB0__AMUX EQU CYREG_PRT6_AMUX\r
-SCSI_Out_DBx__DB0__BIE EQU CYREG_PRT6_BIE\r
-SCSI_Out_DBx__DB0__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
-SCSI_Out_DBx__DB0__BYP EQU CYREG_PRT6_BYP\r
-SCSI_Out_DBx__DB0__CTL EQU CYREG_PRT6_CTL\r
-SCSI_Out_DBx__DB0__DM0 EQU CYREG_PRT6_DM0\r
-SCSI_Out_DBx__DB0__DM1 EQU CYREG_PRT6_DM1\r
-SCSI_Out_DBx__DB0__DM2 EQU CYREG_PRT6_DM2\r
-SCSI_Out_DBx__DB0__DR EQU CYREG_PRT6_DR\r
-SCSI_Out_DBx__DB0__INP_DIS EQU CYREG_PRT6_INP_DIS\r
-SCSI_Out_DBx__DB0__INTTYPE EQU CYREG_PICU6_INTTYPE3\r
-SCSI_Out_DBx__DB0__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
-SCSI_Out_DBx__DB0__LCD_EN EQU CYREG_PRT6_LCD_EN\r
-SCSI_Out_DBx__DB0__MASK EQU 0x08\r
-SCSI_Out_DBx__DB0__PC EQU CYREG_PRT6_PC3\r
-SCSI_Out_DBx__DB0__PORT EQU 6\r
-SCSI_Out_DBx__DB0__PRT EQU CYREG_PRT6_PRT\r
-SCSI_Out_DBx__DB0__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
-SCSI_Out_DBx__DB0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
-SCSI_Out_DBx__DB0__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
-SCSI_Out_DBx__DB0__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
-SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
-SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
-SCSI_Out_DBx__DB0__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
-SCSI_Out_DBx__DB0__PS EQU CYREG_PRT6_PS\r
-SCSI_Out_DBx__DB0__SHIFT EQU 3\r
-SCSI_Out_DBx__DB0__SLW EQU CYREG_PRT6_SLW\r
-SCSI_Out_DBx__DB1__AG EQU CYREG_PRT6_AG\r
-SCSI_Out_DBx__DB1__AMUX EQU CYREG_PRT6_AMUX\r
-SCSI_Out_DBx__DB1__BIE EQU CYREG_PRT6_BIE\r
-SCSI_Out_DBx__DB1__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
-SCSI_Out_DBx__DB1__BYP EQU CYREG_PRT6_BYP\r
-SCSI_Out_DBx__DB1__CTL EQU CYREG_PRT6_CTL\r
-SCSI_Out_DBx__DB1__DM0 EQU CYREG_PRT6_DM0\r
-SCSI_Out_DBx__DB1__DM1 EQU CYREG_PRT6_DM1\r
-SCSI_Out_DBx__DB1__DM2 EQU CYREG_PRT6_DM2\r
-SCSI_Out_DBx__DB1__DR EQU CYREG_PRT6_DR\r
-SCSI_Out_DBx__DB1__INP_DIS EQU CYREG_PRT6_INP_DIS\r
-SCSI_Out_DBx__DB1__INTTYPE EQU CYREG_PICU6_INTTYPE2\r
-SCSI_Out_DBx__DB1__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
-SCSI_Out_DBx__DB1__LCD_EN EQU CYREG_PRT6_LCD_EN\r
-SCSI_Out_DBx__DB1__MASK EQU 0x04\r
-SCSI_Out_DBx__DB1__PC EQU CYREG_PRT6_PC2\r
-SCSI_Out_DBx__DB1__PORT EQU 6\r
-SCSI_Out_DBx__DB1__PRT EQU CYREG_PRT6_PRT\r
-SCSI_Out_DBx__DB1__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
-SCSI_Out_DBx__DB1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
-SCSI_Out_DBx__DB1__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
-SCSI_Out_DBx__DB1__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
-SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
-SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
-SCSI_Out_DBx__DB1__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
-SCSI_Out_DBx__DB1__PS EQU CYREG_PRT6_PS\r
-SCSI_Out_DBx__DB1__SHIFT EQU 2\r
-SCSI_Out_DBx__DB1__SLW EQU CYREG_PRT6_SLW\r
-SCSI_Out_DBx__DB2__AG EQU CYREG_PRT6_AG\r
-SCSI_Out_DBx__DB2__AMUX EQU CYREG_PRT6_AMUX\r
-SCSI_Out_DBx__DB2__BIE EQU CYREG_PRT6_BIE\r
-SCSI_Out_DBx__DB2__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
-SCSI_Out_DBx__DB2__BYP EQU CYREG_PRT6_BYP\r
-SCSI_Out_DBx__DB2__CTL EQU CYREG_PRT6_CTL\r
-SCSI_Out_DBx__DB2__DM0 EQU CYREG_PRT6_DM0\r
-SCSI_Out_DBx__DB2__DM1 EQU CYREG_PRT6_DM1\r
-SCSI_Out_DBx__DB2__DM2 EQU CYREG_PRT6_DM2\r
-SCSI_Out_DBx__DB2__DR EQU CYREG_PRT6_DR\r
-SCSI_Out_DBx__DB2__INP_DIS EQU CYREG_PRT6_INP_DIS\r
-SCSI_Out_DBx__DB2__INTTYPE EQU CYREG_PICU6_INTTYPE1\r
-SCSI_Out_DBx__DB2__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
-SCSI_Out_DBx__DB2__LCD_EN EQU CYREG_PRT6_LCD_EN\r
-SCSI_Out_DBx__DB2__MASK EQU 0x02\r
-SCSI_Out_DBx__DB2__PC EQU CYREG_PRT6_PC1\r
-SCSI_Out_DBx__DB2__PORT EQU 6\r
-SCSI_Out_DBx__DB2__PRT EQU CYREG_PRT6_PRT\r
-SCSI_Out_DBx__DB2__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
-SCSI_Out_DBx__DB2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
-SCSI_Out_DBx__DB2__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
-SCSI_Out_DBx__DB2__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
-SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
-SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
-SCSI_Out_DBx__DB2__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
-SCSI_Out_DBx__DB2__PS EQU CYREG_PRT6_PS\r
-SCSI_Out_DBx__DB2__SHIFT EQU 1\r
-SCSI_Out_DBx__DB2__SLW EQU CYREG_PRT6_SLW\r
-SCSI_Out_DBx__DB3__AG EQU CYREG_PRT6_AG\r
-SCSI_Out_DBx__DB3__AMUX EQU CYREG_PRT6_AMUX\r
-SCSI_Out_DBx__DB3__BIE EQU CYREG_PRT6_BIE\r
-SCSI_Out_DBx__DB3__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
-SCSI_Out_DBx__DB3__BYP EQU CYREG_PRT6_BYP\r
-SCSI_Out_DBx__DB3__CTL EQU CYREG_PRT6_CTL\r
-SCSI_Out_DBx__DB3__DM0 EQU CYREG_PRT6_DM0\r
-SCSI_Out_DBx__DB3__DM1 EQU CYREG_PRT6_DM1\r
-SCSI_Out_DBx__DB3__DM2 EQU CYREG_PRT6_DM2\r
-SCSI_Out_DBx__DB3__DR EQU CYREG_PRT6_DR\r
-SCSI_Out_DBx__DB3__INP_DIS EQU CYREG_PRT6_INP_DIS\r
-SCSI_Out_DBx__DB3__INTTYPE EQU CYREG_PICU6_INTTYPE0\r
-SCSI_Out_DBx__DB3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
-SCSI_Out_DBx__DB3__LCD_EN EQU CYREG_PRT6_LCD_EN\r
-SCSI_Out_DBx__DB3__MASK EQU 0x01\r
-SCSI_Out_DBx__DB3__PC EQU CYREG_PRT6_PC0\r
-SCSI_Out_DBx__DB3__PORT EQU 6\r
-SCSI_Out_DBx__DB3__PRT EQU CYREG_PRT6_PRT\r
-SCSI_Out_DBx__DB3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
-SCSI_Out_DBx__DB3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
-SCSI_Out_DBx__DB3__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
-SCSI_Out_DBx__DB3__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
-SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
-SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
-SCSI_Out_DBx__DB3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
-SCSI_Out_DBx__DB3__PS EQU CYREG_PRT6_PS\r
-SCSI_Out_DBx__DB3__SHIFT EQU 0\r
-SCSI_Out_DBx__DB3__SLW EQU CYREG_PRT6_SLW\r
-SCSI_Out_DBx__DB4__AG EQU CYREG_PRT4_AG\r
-SCSI_Out_DBx__DB4__AMUX EQU CYREG_PRT4_AMUX\r
-SCSI_Out_DBx__DB4__BIE EQU CYREG_PRT4_BIE\r
-SCSI_Out_DBx__DB4__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
-SCSI_Out_DBx__DB4__BYP EQU CYREG_PRT4_BYP\r
-SCSI_Out_DBx__DB4__CTL EQU CYREG_PRT4_CTL\r
-SCSI_Out_DBx__DB4__DM0 EQU CYREG_PRT4_DM0\r
-SCSI_Out_DBx__DB4__DM1 EQU CYREG_PRT4_DM1\r
-SCSI_Out_DBx__DB4__DM2 EQU CYREG_PRT4_DM2\r
-SCSI_Out_DBx__DB4__DR EQU CYREG_PRT4_DR\r
-SCSI_Out_DBx__DB4__INP_DIS EQU CYREG_PRT4_INP_DIS\r
-SCSI_Out_DBx__DB4__INTTYPE EQU CYREG_PICU4_INTTYPE7\r
-SCSI_Out_DBx__DB4__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
-SCSI_Out_DBx__DB4__LCD_EN EQU CYREG_PRT4_LCD_EN\r
-SCSI_Out_DBx__DB4__MASK EQU 0x80\r
-SCSI_Out_DBx__DB4__PC EQU CYREG_PRT4_PC7\r
-SCSI_Out_DBx__DB4__PORT EQU 4\r
-SCSI_Out_DBx__DB4__PRT EQU CYREG_PRT4_PRT\r
-SCSI_Out_DBx__DB4__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
-SCSI_Out_DBx__DB4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
-SCSI_Out_DBx__DB4__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
-SCSI_Out_DBx__DB4__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
-SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
-SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
-SCSI_Out_DBx__DB4__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
-SCSI_Out_DBx__DB4__PS EQU CYREG_PRT4_PS\r
-SCSI_Out_DBx__DB4__SHIFT EQU 7\r
-SCSI_Out_DBx__DB4__SLW EQU CYREG_PRT4_SLW\r
-SCSI_Out_DBx__DB5__AG EQU CYREG_PRT4_AG\r
-SCSI_Out_DBx__DB5__AMUX EQU CYREG_PRT4_AMUX\r
-SCSI_Out_DBx__DB5__BIE EQU CYREG_PRT4_BIE\r
-SCSI_Out_DBx__DB5__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
-SCSI_Out_DBx__DB5__BYP EQU CYREG_PRT4_BYP\r
-SCSI_Out_DBx__DB5__CTL EQU CYREG_PRT4_CTL\r
-SCSI_Out_DBx__DB5__DM0 EQU CYREG_PRT4_DM0\r
-SCSI_Out_DBx__DB5__DM1 EQU CYREG_PRT4_DM1\r
-SCSI_Out_DBx__DB5__DM2 EQU CYREG_PRT4_DM2\r
-SCSI_Out_DBx__DB5__DR EQU CYREG_PRT4_DR\r
-SCSI_Out_DBx__DB5__INP_DIS EQU CYREG_PRT4_INP_DIS\r
-SCSI_Out_DBx__DB5__INTTYPE EQU CYREG_PICU4_INTTYPE6\r
-SCSI_Out_DBx__DB5__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
-SCSI_Out_DBx__DB5__LCD_EN EQU CYREG_PRT4_LCD_EN\r
-SCSI_Out_DBx__DB5__MASK EQU 0x40\r
-SCSI_Out_DBx__DB5__PC EQU CYREG_PRT4_PC6\r
-SCSI_Out_DBx__DB5__PORT EQU 4\r
-SCSI_Out_DBx__DB5__PRT EQU CYREG_PRT4_PRT\r
-SCSI_Out_DBx__DB5__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
-SCSI_Out_DBx__DB5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
-SCSI_Out_DBx__DB5__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
-SCSI_Out_DBx__DB5__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
-SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
-SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
-SCSI_Out_DBx__DB5__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
-SCSI_Out_DBx__DB5__PS EQU CYREG_PRT4_PS\r
-SCSI_Out_DBx__DB5__SHIFT EQU 6\r
-SCSI_Out_DBx__DB5__SLW EQU CYREG_PRT4_SLW\r
-SCSI_Out_DBx__DB6__AG EQU CYREG_PRT4_AG\r
-SCSI_Out_DBx__DB6__AMUX EQU CYREG_PRT4_AMUX\r
-SCSI_Out_DBx__DB6__BIE EQU CYREG_PRT4_BIE\r
-SCSI_Out_DBx__DB6__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
-SCSI_Out_DBx__DB6__BYP EQU CYREG_PRT4_BYP\r
-SCSI_Out_DBx__DB6__CTL EQU CYREG_PRT4_CTL\r
-SCSI_Out_DBx__DB6__DM0 EQU CYREG_PRT4_DM0\r
-SCSI_Out_DBx__DB6__DM1 EQU CYREG_PRT4_DM1\r
-SCSI_Out_DBx__DB6__DM2 EQU CYREG_PRT4_DM2\r
-SCSI_Out_DBx__DB6__DR EQU CYREG_PRT4_DR\r
-SCSI_Out_DBx__DB6__INP_DIS EQU CYREG_PRT4_INP_DIS\r
-SCSI_Out_DBx__DB6__INTTYPE EQU CYREG_PICU4_INTTYPE5\r
-SCSI_Out_DBx__DB6__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
-SCSI_Out_DBx__DB6__LCD_EN EQU CYREG_PRT4_LCD_EN\r
-SCSI_Out_DBx__DB6__MASK EQU 0x20\r
-SCSI_Out_DBx__DB6__PC EQU CYREG_PRT4_PC5\r
-SCSI_Out_DBx__DB6__PORT EQU 4\r
-SCSI_Out_DBx__DB6__PRT EQU CYREG_PRT4_PRT\r
-SCSI_Out_DBx__DB6__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
-SCSI_Out_DBx__DB6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
-SCSI_Out_DBx__DB6__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
-SCSI_Out_DBx__DB6__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
-SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
-SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
-SCSI_Out_DBx__DB6__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
-SCSI_Out_DBx__DB6__PS EQU CYREG_PRT4_PS\r
-SCSI_Out_DBx__DB6__SHIFT EQU 5\r
-SCSI_Out_DBx__DB6__SLW EQU CYREG_PRT4_SLW\r
-SCSI_Out_DBx__DB7__AG EQU CYREG_PRT4_AG\r
-SCSI_Out_DBx__DB7__AMUX EQU CYREG_PRT4_AMUX\r
-SCSI_Out_DBx__DB7__BIE EQU CYREG_PRT4_BIE\r
-SCSI_Out_DBx__DB7__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
-SCSI_Out_DBx__DB7__BYP EQU CYREG_PRT4_BYP\r
-SCSI_Out_DBx__DB7__CTL EQU CYREG_PRT4_CTL\r
-SCSI_Out_DBx__DB7__DM0 EQU CYREG_PRT4_DM0\r
-SCSI_Out_DBx__DB7__DM1 EQU CYREG_PRT4_DM1\r
-SCSI_Out_DBx__DB7__DM2 EQU CYREG_PRT4_DM2\r
-SCSI_Out_DBx__DB7__DR EQU CYREG_PRT4_DR\r
-SCSI_Out_DBx__DB7__INP_DIS EQU CYREG_PRT4_INP_DIS\r
-SCSI_Out_DBx__DB7__INTTYPE EQU CYREG_PICU4_INTTYPE4\r
-SCSI_Out_DBx__DB7__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
-SCSI_Out_DBx__DB7__LCD_EN EQU CYREG_PRT4_LCD_EN\r
-SCSI_Out_DBx__DB7__MASK EQU 0x10\r
-SCSI_Out_DBx__DB7__PC EQU CYREG_PRT4_PC4\r
-SCSI_Out_DBx__DB7__PORT EQU 4\r
-SCSI_Out_DBx__DB7__PRT EQU CYREG_PRT4_PRT\r
-SCSI_Out_DBx__DB7__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
-SCSI_Out_DBx__DB7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
-SCSI_Out_DBx__DB7__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
-SCSI_Out_DBx__DB7__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
-SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
-SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
-SCSI_Out_DBx__DB7__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
-SCSI_Out_DBx__DB7__PS EQU CYREG_PRT4_PS\r
-SCSI_Out_DBx__DB7__SHIFT EQU 4\r
-SCSI_Out_DBx__DB7__SLW EQU CYREG_PRT4_SLW\r
-\r
-/* SD_RX_DMA */\r
-SD_RX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0\r
-SD_RX_DMA__DRQ_NUMBER EQU 2\r
-SD_RX_DMA__NUMBEROF_TDS EQU 0\r
-SD_RX_DMA__PRIORITY EQU 0\r
-SD_RX_DMA__TERMIN_EN EQU 0\r
-SD_RX_DMA__TERMIN_SEL EQU 0\r
-SD_RX_DMA__TERMOUT0_EN EQU 1\r
-SD_RX_DMA__TERMOUT0_SEL EQU 2\r
-SD_RX_DMA__TERMOUT1_EN EQU 0\r
-SD_RX_DMA__TERMOUT1_SEL EQU 0\r
-\r
-/* SD_RX_DMA_COMPLETE */\r
-SD_RX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
-SD_RX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
-SD_RX_DMA_COMPLETE__INTC_MASK EQU 0x20\r
-SD_RX_DMA_COMPLETE__INTC_NUMBER EQU 5\r
-SD_RX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7\r
-SD_RX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_5\r
-SD_RX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
-SD_RX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
-\r
-/* SD_TX_DMA */\r
-SD_TX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0\r
-SD_TX_DMA__DRQ_NUMBER EQU 3\r
-SD_TX_DMA__NUMBEROF_TDS EQU 0\r
-SD_TX_DMA__PRIORITY EQU 1\r
-SD_TX_DMA__TERMIN_EN EQU 0\r
-SD_TX_DMA__TERMIN_SEL EQU 0\r
-SD_TX_DMA__TERMOUT0_EN EQU 1\r
-SD_TX_DMA__TERMOUT0_SEL EQU 3\r
-SD_TX_DMA__TERMOUT1_EN EQU 0\r
-SD_TX_DMA__TERMOUT1_SEL EQU 0\r
-\r
-/* SD_TX_DMA_COMPLETE */\r
-SD_TX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
-SD_TX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
-SD_TX_DMA_COMPLETE__INTC_MASK EQU 0x40\r
-SD_TX_DMA_COMPLETE__INTC_NUMBER EQU 6\r
-SD_TX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7\r
-SD_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_6\r
-SD_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
-SD_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
+/* SCSI_In */\r
+SCSI_In__0__AG EQU CYREG_PRT2_AG\r
+SCSI_In__0__AMUX EQU CYREG_PRT2_AMUX\r
+SCSI_In__0__BIE EQU CYREG_PRT2_BIE\r
+SCSI_In__0__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
+SCSI_In__0__BYP EQU CYREG_PRT2_BYP\r
+SCSI_In__0__CTL EQU CYREG_PRT2_CTL\r
+SCSI_In__0__DM0 EQU CYREG_PRT2_DM0\r
+SCSI_In__0__DM1 EQU CYREG_PRT2_DM1\r
+SCSI_In__0__DM2 EQU CYREG_PRT2_DM2\r
+SCSI_In__0__DR EQU CYREG_PRT2_DR\r
+SCSI_In__0__INP_DIS EQU CYREG_PRT2_INP_DIS\r
+SCSI_In__0__INTTYPE EQU CYREG_PICU2_INTTYPE0\r
+SCSI_In__0__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
+SCSI_In__0__LCD_EN EQU CYREG_PRT2_LCD_EN\r
+SCSI_In__0__MASK EQU 0x01\r
+SCSI_In__0__PC EQU CYREG_PRT2_PC0\r
+SCSI_In__0__PORT EQU 2\r
+SCSI_In__0__PRT EQU CYREG_PRT2_PRT\r
+SCSI_In__0__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
+SCSI_In__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
+SCSI_In__0__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
+SCSI_In__0__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
+SCSI_In__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
+SCSI_In__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
+SCSI_In__0__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
+SCSI_In__0__PS EQU CYREG_PRT2_PS\r
+SCSI_In__0__SHIFT EQU 0\r
+SCSI_In__0__SLW EQU CYREG_PRT2_SLW\r
+SCSI_In__1__AG EQU CYREG_PRT6_AG\r
+SCSI_In__1__AMUX EQU CYREG_PRT6_AMUX\r
+SCSI_In__1__BIE EQU CYREG_PRT6_BIE\r
+SCSI_In__1__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
+SCSI_In__1__BYP EQU CYREG_PRT6_BYP\r
+SCSI_In__1__CTL EQU CYREG_PRT6_CTL\r
+SCSI_In__1__DM0 EQU CYREG_PRT6_DM0\r
+SCSI_In__1__DM1 EQU CYREG_PRT6_DM1\r
+SCSI_In__1__DM2 EQU CYREG_PRT6_DM2\r
+SCSI_In__1__DR EQU CYREG_PRT6_DR\r
+SCSI_In__1__INP_DIS EQU CYREG_PRT6_INP_DIS\r
+SCSI_In__1__INTTYPE EQU CYREG_PICU6_INTTYPE7\r
+SCSI_In__1__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
+SCSI_In__1__LCD_EN EQU CYREG_PRT6_LCD_EN\r
+SCSI_In__1__MASK EQU 0x80\r
+SCSI_In__1__PC EQU CYREG_PRT6_PC7\r
+SCSI_In__1__PORT EQU 6\r
+SCSI_In__1__PRT EQU CYREG_PRT6_PRT\r
+SCSI_In__1__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
+SCSI_In__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
+SCSI_In__1__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
+SCSI_In__1__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
+SCSI_In__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
+SCSI_In__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
+SCSI_In__1__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
+SCSI_In__1__PS EQU CYREG_PRT6_PS\r
+SCSI_In__1__SHIFT EQU 7\r
+SCSI_In__1__SLW EQU CYREG_PRT6_SLW\r
+SCSI_In__2__AG EQU CYREG_PRT5_AG\r
+SCSI_In__2__AMUX EQU CYREG_PRT5_AMUX\r
+SCSI_In__2__BIE EQU CYREG_PRT5_BIE\r
+SCSI_In__2__BIT_MASK EQU CYREG_PRT5_BIT_MASK\r
+SCSI_In__2__BYP EQU CYREG_PRT5_BYP\r
+SCSI_In__2__CTL EQU CYREG_PRT5_CTL\r
+SCSI_In__2__DM0 EQU CYREG_PRT5_DM0\r
+SCSI_In__2__DM1 EQU CYREG_PRT5_DM1\r
+SCSI_In__2__DM2 EQU CYREG_PRT5_DM2\r
+SCSI_In__2__DR EQU CYREG_PRT5_DR\r
+SCSI_In__2__INP_DIS EQU CYREG_PRT5_INP_DIS\r
+SCSI_In__2__INTTYPE EQU CYREG_PICU5_INTTYPE1\r
+SCSI_In__2__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG\r
+SCSI_In__2__LCD_EN EQU CYREG_PRT5_LCD_EN\r
+SCSI_In__2__MASK EQU 0x02\r
+SCSI_In__2__PC EQU CYREG_PRT5_PC1\r
+SCSI_In__2__PORT EQU 5\r
+SCSI_In__2__PRT EQU CYREG_PRT5_PRT\r
+SCSI_In__2__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL\r
+SCSI_In__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN\r
+SCSI_In__2__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0\r
+SCSI_In__2__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1\r
+SCSI_In__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0\r
+SCSI_In__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1\r
+SCSI_In__2__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT\r
+SCSI_In__2__PS EQU CYREG_PRT5_PS\r
+SCSI_In__2__SHIFT EQU 1\r
+SCSI_In__2__SLW EQU CYREG_PRT5_SLW\r
+SCSI_In__3__AG EQU CYREG_PRT5_AG\r
+SCSI_In__3__AMUX EQU CYREG_PRT5_AMUX\r
+SCSI_In__3__BIE EQU CYREG_PRT5_BIE\r
+SCSI_In__3__BIT_MASK EQU CYREG_PRT5_BIT_MASK\r
+SCSI_In__3__BYP EQU CYREG_PRT5_BYP\r
+SCSI_In__3__CTL EQU CYREG_PRT5_CTL\r
+SCSI_In__3__DM0 EQU CYREG_PRT5_DM0\r
+SCSI_In__3__DM1 EQU CYREG_PRT5_DM1\r
+SCSI_In__3__DM2 EQU CYREG_PRT5_DM2\r
+SCSI_In__3__DR EQU CYREG_PRT5_DR\r
+SCSI_In__3__INP_DIS EQU CYREG_PRT5_INP_DIS\r
+SCSI_In__3__INTTYPE EQU CYREG_PICU5_INTTYPE2\r
+SCSI_In__3__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG\r
+SCSI_In__3__LCD_EN EQU CYREG_PRT5_LCD_EN\r
+SCSI_In__3__MASK EQU 0x04\r
+SCSI_In__3__PC EQU CYREG_PRT5_PC2\r
+SCSI_In__3__PORT EQU 5\r
+SCSI_In__3__PRT EQU CYREG_PRT5_PRT\r
+SCSI_In__3__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL\r
+SCSI_In__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN\r
+SCSI_In__3__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0\r
+SCSI_In__3__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1\r
+SCSI_In__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0\r
+SCSI_In__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1\r
+SCSI_In__3__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT\r
+SCSI_In__3__PS EQU CYREG_PRT5_PS\r
+SCSI_In__3__SHIFT EQU 2\r
+SCSI_In__3__SLW EQU CYREG_PRT5_SLW\r
+SCSI_In__4__AG EQU CYREG_PRT5_AG\r
+SCSI_In__4__AMUX EQU CYREG_PRT5_AMUX\r
+SCSI_In__4__BIE EQU CYREG_PRT5_BIE\r
+SCSI_In__4__BIT_MASK EQU CYREG_PRT5_BIT_MASK\r
+SCSI_In__4__BYP EQU CYREG_PRT5_BYP\r
+SCSI_In__4__CTL EQU CYREG_PRT5_CTL\r
+SCSI_In__4__DM0 EQU CYREG_PRT5_DM0\r
+SCSI_In__4__DM1 EQU CYREG_PRT5_DM1\r
+SCSI_In__4__DM2 EQU CYREG_PRT5_DM2\r
+SCSI_In__4__DR EQU CYREG_PRT5_DR\r
+SCSI_In__4__INP_DIS EQU CYREG_PRT5_INP_DIS\r
+SCSI_In__4__INTTYPE EQU CYREG_PICU5_INTTYPE3\r
+SCSI_In__4__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG\r
+SCSI_In__4__LCD_EN EQU CYREG_PRT5_LCD_EN\r
+SCSI_In__4__MASK EQU 0x08\r
+SCSI_In__4__PC EQU CYREG_PRT5_PC3\r
+SCSI_In__4__PORT EQU 5\r
+SCSI_In__4__PRT EQU CYREG_PRT5_PRT\r
+SCSI_In__4__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL\r
+SCSI_In__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN\r
+SCSI_In__4__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0\r
+SCSI_In__4__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1\r
+SCSI_In__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0\r
+SCSI_In__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1\r
+SCSI_In__4__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT\r
+SCSI_In__4__PS EQU CYREG_PRT5_PS\r
+SCSI_In__4__SHIFT EQU 3\r
+SCSI_In__4__SLW EQU CYREG_PRT5_SLW\r
+SCSI_In__CD__AG EQU CYREG_PRT5_AG\r
+SCSI_In__CD__AMUX EQU CYREG_PRT5_AMUX\r
+SCSI_In__CD__BIE EQU CYREG_PRT5_BIE\r
+SCSI_In__CD__BIT_MASK EQU CYREG_PRT5_BIT_MASK\r
+SCSI_In__CD__BYP EQU CYREG_PRT5_BYP\r
+SCSI_In__CD__CTL EQU CYREG_PRT5_CTL\r
+SCSI_In__CD__DM0 EQU CYREG_PRT5_DM0\r
+SCSI_In__CD__DM1 EQU CYREG_PRT5_DM1\r
+SCSI_In__CD__DM2 EQU CYREG_PRT5_DM2\r
+SCSI_In__CD__DR EQU CYREG_PRT5_DR\r
+SCSI_In__CD__INP_DIS EQU CYREG_PRT5_INP_DIS\r
+SCSI_In__CD__INTTYPE EQU CYREG_PICU5_INTTYPE1\r
+SCSI_In__CD__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG\r
+SCSI_In__CD__LCD_EN EQU CYREG_PRT5_LCD_EN\r
+SCSI_In__CD__MASK EQU 0x02\r
+SCSI_In__CD__PC EQU CYREG_PRT5_PC1\r
+SCSI_In__CD__PORT EQU 5\r
+SCSI_In__CD__PRT EQU CYREG_PRT5_PRT\r
+SCSI_In__CD__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL\r
+SCSI_In__CD__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN\r
+SCSI_In__CD__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0\r
+SCSI_In__CD__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1\r
+SCSI_In__CD__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0\r
+SCSI_In__CD__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1\r
+SCSI_In__CD__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT\r
+SCSI_In__CD__PS EQU CYREG_PRT5_PS\r
+SCSI_In__CD__SHIFT EQU 1\r
+SCSI_In__CD__SLW EQU CYREG_PRT5_SLW\r
+SCSI_In__DBP__AG EQU CYREG_PRT2_AG\r
+SCSI_In__DBP__AMUX EQU CYREG_PRT2_AMUX\r
+SCSI_In__DBP__BIE EQU CYREG_PRT2_BIE\r
+SCSI_In__DBP__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
+SCSI_In__DBP__BYP EQU CYREG_PRT2_BYP\r
+SCSI_In__DBP__CTL EQU CYREG_PRT2_CTL\r
+SCSI_In__DBP__DM0 EQU CYREG_PRT2_DM0\r
+SCSI_In__DBP__DM1 EQU CYREG_PRT2_DM1\r
+SCSI_In__DBP__DM2 EQU CYREG_PRT2_DM2\r
+SCSI_In__DBP__DR EQU CYREG_PRT2_DR\r
+SCSI_In__DBP__INP_DIS EQU CYREG_PRT2_INP_DIS\r
+SCSI_In__DBP__INTTYPE EQU CYREG_PICU2_INTTYPE0\r
+SCSI_In__DBP__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
+SCSI_In__DBP__LCD_EN EQU CYREG_PRT2_LCD_EN\r
+SCSI_In__DBP__MASK EQU 0x01\r
+SCSI_In__DBP__PC EQU CYREG_PRT2_PC0\r
+SCSI_In__DBP__PORT EQU 2\r
+SCSI_In__DBP__PRT EQU CYREG_PRT2_PRT\r
+SCSI_In__DBP__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
+SCSI_In__DBP__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
+SCSI_In__DBP__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
+SCSI_In__DBP__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
+SCSI_In__DBP__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
+SCSI_In__DBP__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
+SCSI_In__DBP__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
+SCSI_In__DBP__PS EQU CYREG_PRT2_PS\r
+SCSI_In__DBP__SHIFT EQU 0\r
+SCSI_In__DBP__SLW EQU CYREG_PRT2_SLW\r
+SCSI_In__IO__AG EQU CYREG_PRT5_AG\r
+SCSI_In__IO__AMUX EQU CYREG_PRT5_AMUX\r
+SCSI_In__IO__BIE EQU CYREG_PRT5_BIE\r
+SCSI_In__IO__BIT_MASK EQU CYREG_PRT5_BIT_MASK\r
+SCSI_In__IO__BYP EQU CYREG_PRT5_BYP\r
+SCSI_In__IO__CTL EQU CYREG_PRT5_CTL\r
+SCSI_In__IO__DM0 EQU CYREG_PRT5_DM0\r
+SCSI_In__IO__DM1 EQU CYREG_PRT5_DM1\r
+SCSI_In__IO__DM2 EQU CYREG_PRT5_DM2\r
+SCSI_In__IO__DR EQU CYREG_PRT5_DR\r
+SCSI_In__IO__INP_DIS EQU CYREG_PRT5_INP_DIS\r
+SCSI_In__IO__INTTYPE EQU CYREG_PICU5_INTTYPE3\r
+SCSI_In__IO__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG\r
+SCSI_In__IO__LCD_EN EQU CYREG_PRT5_LCD_EN\r
+SCSI_In__IO__MASK EQU 0x08\r
+SCSI_In__IO__PC EQU CYREG_PRT5_PC3\r
+SCSI_In__IO__PORT EQU 5\r
+SCSI_In__IO__PRT EQU CYREG_PRT5_PRT\r
+SCSI_In__IO__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL\r
+SCSI_In__IO__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN\r
+SCSI_In__IO__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0\r
+SCSI_In__IO__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1\r
+SCSI_In__IO__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0\r
+SCSI_In__IO__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1\r
+SCSI_In__IO__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT\r
+SCSI_In__IO__PS EQU CYREG_PRT5_PS\r
+SCSI_In__IO__SHIFT EQU 3\r
+SCSI_In__IO__SLW EQU CYREG_PRT5_SLW\r
+SCSI_In__MSG__AG EQU CYREG_PRT6_AG\r
+SCSI_In__MSG__AMUX EQU CYREG_PRT6_AMUX\r
+SCSI_In__MSG__BIE EQU CYREG_PRT6_BIE\r
+SCSI_In__MSG__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
+SCSI_In__MSG__BYP EQU CYREG_PRT6_BYP\r
+SCSI_In__MSG__CTL EQU CYREG_PRT6_CTL\r
+SCSI_In__MSG__DM0 EQU CYREG_PRT6_DM0\r
+SCSI_In__MSG__DM1 EQU CYREG_PRT6_DM1\r
+SCSI_In__MSG__DM2 EQU CYREG_PRT6_DM2\r
+SCSI_In__MSG__DR EQU CYREG_PRT6_DR\r
+SCSI_In__MSG__INP_DIS EQU CYREG_PRT6_INP_DIS\r
+SCSI_In__MSG__INTTYPE EQU CYREG_PICU6_INTTYPE7\r
+SCSI_In__MSG__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
+SCSI_In__MSG__LCD_EN EQU CYREG_PRT6_LCD_EN\r
+SCSI_In__MSG__MASK EQU 0x80\r
+SCSI_In__MSG__PC EQU CYREG_PRT6_PC7\r
+SCSI_In__MSG__PORT EQU 6\r
+SCSI_In__MSG__PRT EQU CYREG_PRT6_PRT\r
+SCSI_In__MSG__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
+SCSI_In__MSG__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
+SCSI_In__MSG__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
+SCSI_In__MSG__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
+SCSI_In__MSG__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
+SCSI_In__MSG__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
+SCSI_In__MSG__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
+SCSI_In__MSG__PS EQU CYREG_PRT6_PS\r
+SCSI_In__MSG__SHIFT EQU 7\r
+SCSI_In__MSG__SLW EQU CYREG_PRT6_SLW\r
+SCSI_In__REQ__AG EQU CYREG_PRT5_AG\r
+SCSI_In__REQ__AMUX EQU CYREG_PRT5_AMUX\r
+SCSI_In__REQ__BIE EQU CYREG_PRT5_BIE\r
+SCSI_In__REQ__BIT_MASK EQU CYREG_PRT5_BIT_MASK\r
+SCSI_In__REQ__BYP EQU CYREG_PRT5_BYP\r
+SCSI_In__REQ__CTL EQU CYREG_PRT5_CTL\r
+SCSI_In__REQ__DM0 EQU CYREG_PRT5_DM0\r
+SCSI_In__REQ__DM1 EQU CYREG_PRT5_DM1\r
+SCSI_In__REQ__DM2 EQU CYREG_PRT5_DM2\r
+SCSI_In__REQ__DR EQU CYREG_PRT5_DR\r
+SCSI_In__REQ__INP_DIS EQU CYREG_PRT5_INP_DIS\r
+SCSI_In__REQ__INTTYPE EQU CYREG_PICU5_INTTYPE2\r
+SCSI_In__REQ__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG\r
+SCSI_In__REQ__LCD_EN EQU CYREG_PRT5_LCD_EN\r
+SCSI_In__REQ__MASK EQU 0x04\r
+SCSI_In__REQ__PC EQU CYREG_PRT5_PC2\r
+SCSI_In__REQ__PORT EQU 5\r
+SCSI_In__REQ__PRT EQU CYREG_PRT5_PRT\r
+SCSI_In__REQ__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL\r
+SCSI_In__REQ__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN\r
+SCSI_In__REQ__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0\r
+SCSI_In__REQ__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1\r
+SCSI_In__REQ__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0\r
+SCSI_In__REQ__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1\r
+SCSI_In__REQ__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT\r
+SCSI_In__REQ__PS EQU CYREG_PRT5_PS\r
+SCSI_In__REQ__SHIFT EQU 2\r
+SCSI_In__REQ__SLW EQU CYREG_PRT5_SLW\r
+SCSI_In_DBx__0__AG EQU CYREG_PRT12_AG\r
+SCSI_In_DBx__0__BIE EQU CYREG_PRT12_BIE\r
+SCSI_In_DBx__0__BIT_MASK EQU CYREG_PRT12_BIT_MASK\r
+SCSI_In_DBx__0__BYP EQU CYREG_PRT12_BYP\r
+SCSI_In_DBx__0__DM0 EQU CYREG_PRT12_DM0\r
+SCSI_In_DBx__0__DM1 EQU CYREG_PRT12_DM1\r
+SCSI_In_DBx__0__DM2 EQU CYREG_PRT12_DM2\r
+SCSI_In_DBx__0__DR EQU CYREG_PRT12_DR\r
+SCSI_In_DBx__0__INP_DIS EQU CYREG_PRT12_INP_DIS\r
+SCSI_In_DBx__0__INTTYPE EQU CYREG_PICU12_INTTYPE4\r
+SCSI_In_DBx__0__MASK EQU 0x10\r
+SCSI_In_DBx__0__PC EQU CYREG_PRT12_PC4\r
+SCSI_In_DBx__0__PORT EQU 12\r
+SCSI_In_DBx__0__PRT EQU CYREG_PRT12_PRT\r
+SCSI_In_DBx__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN\r
+SCSI_In_DBx__0__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0\r
+SCSI_In_DBx__0__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1\r
+SCSI_In_DBx__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0\r
+SCSI_In_DBx__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1\r
+SCSI_In_DBx__0__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT\r
+SCSI_In_DBx__0__PS EQU CYREG_PRT12_PS\r
+SCSI_In_DBx__0__SHIFT EQU 4\r
+SCSI_In_DBx__0__SIO_CFG EQU CYREG_PRT12_SIO_CFG\r
+SCSI_In_DBx__0__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF\r
+SCSI_In_DBx__0__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN\r
+SCSI_In_DBx__0__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ\r
+SCSI_In_DBx__0__SLW EQU CYREG_PRT12_SLW\r
+SCSI_In_DBx__1__AG EQU CYREG_PRT2_AG\r
+SCSI_In_DBx__1__AMUX EQU CYREG_PRT2_AMUX\r
+SCSI_In_DBx__1__BIE EQU CYREG_PRT2_BIE\r
+SCSI_In_DBx__1__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
+SCSI_In_DBx__1__BYP EQU CYREG_PRT2_BYP\r
+SCSI_In_DBx__1__CTL EQU CYREG_PRT2_CTL\r
+SCSI_In_DBx__1__DM0 EQU CYREG_PRT2_DM0\r
+SCSI_In_DBx__1__DM1 EQU CYREG_PRT2_DM1\r
+SCSI_In_DBx__1__DM2 EQU CYREG_PRT2_DM2\r
+SCSI_In_DBx__1__DR EQU CYREG_PRT2_DR\r
+SCSI_In_DBx__1__INP_DIS EQU CYREG_PRT2_INP_DIS\r
+SCSI_In_DBx__1__INTTYPE EQU CYREG_PICU2_INTTYPE7\r
+SCSI_In_DBx__1__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
+SCSI_In_DBx__1__LCD_EN EQU CYREG_PRT2_LCD_EN\r
+SCSI_In_DBx__1__MASK EQU 0x80\r
+SCSI_In_DBx__1__PC EQU CYREG_PRT2_PC7\r
+SCSI_In_DBx__1__PORT EQU 2\r
+SCSI_In_DBx__1__PRT EQU CYREG_PRT2_PRT\r
+SCSI_In_DBx__1__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
+SCSI_In_DBx__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
+SCSI_In_DBx__1__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
+SCSI_In_DBx__1__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
+SCSI_In_DBx__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
+SCSI_In_DBx__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
+SCSI_In_DBx__1__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
+SCSI_In_DBx__1__PS EQU CYREG_PRT2_PS\r
+SCSI_In_DBx__1__SHIFT EQU 7\r
+SCSI_In_DBx__1__SLW EQU CYREG_PRT2_SLW\r
+SCSI_In_DBx__2__AG EQU CYREG_PRT2_AG\r
+SCSI_In_DBx__2__AMUX EQU CYREG_PRT2_AMUX\r
+SCSI_In_DBx__2__BIE EQU CYREG_PRT2_BIE\r
+SCSI_In_DBx__2__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
+SCSI_In_DBx__2__BYP EQU CYREG_PRT2_BYP\r
+SCSI_In_DBx__2__CTL EQU CYREG_PRT2_CTL\r
+SCSI_In_DBx__2__DM0 EQU CYREG_PRT2_DM0\r
+SCSI_In_DBx__2__DM1 EQU CYREG_PRT2_DM1\r
+SCSI_In_DBx__2__DM2 EQU CYREG_PRT2_DM2\r
+SCSI_In_DBx__2__DR EQU CYREG_PRT2_DR\r
+SCSI_In_DBx__2__INP_DIS EQU CYREG_PRT2_INP_DIS\r
+SCSI_In_DBx__2__INTTYPE EQU CYREG_PICU2_INTTYPE6\r
+SCSI_In_DBx__2__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
+SCSI_In_DBx__2__LCD_EN EQU CYREG_PRT2_LCD_EN\r
+SCSI_In_DBx__2__MASK EQU 0x40\r
+SCSI_In_DBx__2__PC EQU CYREG_PRT2_PC6\r
+SCSI_In_DBx__2__PORT EQU 2\r
+SCSI_In_DBx__2__PRT EQU CYREG_PRT2_PRT\r
+SCSI_In_DBx__2__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
+SCSI_In_DBx__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
+SCSI_In_DBx__2__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
+SCSI_In_DBx__2__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
+SCSI_In_DBx__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
+SCSI_In_DBx__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
+SCSI_In_DBx__2__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
+SCSI_In_DBx__2__PS EQU CYREG_PRT2_PS\r
+SCSI_In_DBx__2__SHIFT EQU 6\r
+SCSI_In_DBx__2__SLW EQU CYREG_PRT2_SLW\r
+SCSI_In_DBx__3__AG EQU CYREG_PRT2_AG\r
+SCSI_In_DBx__3__AMUX EQU CYREG_PRT2_AMUX\r
+SCSI_In_DBx__3__BIE EQU CYREG_PRT2_BIE\r
+SCSI_In_DBx__3__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
+SCSI_In_DBx__3__BYP EQU CYREG_PRT2_BYP\r
+SCSI_In_DBx__3__CTL EQU CYREG_PRT2_CTL\r
+SCSI_In_DBx__3__DM0 EQU CYREG_PRT2_DM0\r
+SCSI_In_DBx__3__DM1 EQU CYREG_PRT2_DM1\r
+SCSI_In_DBx__3__DM2 EQU CYREG_PRT2_DM2\r
+SCSI_In_DBx__3__DR EQU CYREG_PRT2_DR\r
+SCSI_In_DBx__3__INP_DIS EQU CYREG_PRT2_INP_DIS\r
+SCSI_In_DBx__3__INTTYPE EQU CYREG_PICU2_INTTYPE5\r
+SCSI_In_DBx__3__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
+SCSI_In_DBx__3__LCD_EN EQU CYREG_PRT2_LCD_EN\r
+SCSI_In_DBx__3__MASK EQU 0x20\r
+SCSI_In_DBx__3__PC EQU CYREG_PRT2_PC5\r
+SCSI_In_DBx__3__PORT EQU 2\r
+SCSI_In_DBx__3__PRT EQU CYREG_PRT2_PRT\r
+SCSI_In_DBx__3__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
+SCSI_In_DBx__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
+SCSI_In_DBx__3__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
+SCSI_In_DBx__3__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
+SCSI_In_DBx__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
+SCSI_In_DBx__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
+SCSI_In_DBx__3__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
+SCSI_In_DBx__3__PS EQU CYREG_PRT2_PS\r
+SCSI_In_DBx__3__SHIFT EQU 5\r
+SCSI_In_DBx__3__SLW EQU CYREG_PRT2_SLW\r
+SCSI_In_DBx__4__AG EQU CYREG_PRT2_AG\r
+SCSI_In_DBx__4__AMUX EQU CYREG_PRT2_AMUX\r
+SCSI_In_DBx__4__BIE EQU CYREG_PRT2_BIE\r
+SCSI_In_DBx__4__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
+SCSI_In_DBx__4__BYP EQU CYREG_PRT2_BYP\r
+SCSI_In_DBx__4__CTL EQU CYREG_PRT2_CTL\r
+SCSI_In_DBx__4__DM0 EQU CYREG_PRT2_DM0\r
+SCSI_In_DBx__4__DM1 EQU CYREG_PRT2_DM1\r
+SCSI_In_DBx__4__DM2 EQU CYREG_PRT2_DM2\r
+SCSI_In_DBx__4__DR EQU CYREG_PRT2_DR\r
+SCSI_In_DBx__4__INP_DIS EQU CYREG_PRT2_INP_DIS\r
+SCSI_In_DBx__4__INTTYPE EQU CYREG_PICU2_INTTYPE4\r
+SCSI_In_DBx__4__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
+SCSI_In_DBx__4__LCD_EN EQU CYREG_PRT2_LCD_EN\r
+SCSI_In_DBx__4__MASK EQU 0x10\r
+SCSI_In_DBx__4__PC EQU CYREG_PRT2_PC4\r
+SCSI_In_DBx__4__PORT EQU 2\r
+SCSI_In_DBx__4__PRT EQU CYREG_PRT2_PRT\r
+SCSI_In_DBx__4__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
+SCSI_In_DBx__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
+SCSI_In_DBx__4__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
+SCSI_In_DBx__4__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
+SCSI_In_DBx__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
+SCSI_In_DBx__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
+SCSI_In_DBx__4__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
+SCSI_In_DBx__4__PS EQU CYREG_PRT2_PS\r
+SCSI_In_DBx__4__SHIFT EQU 4\r
+SCSI_In_DBx__4__SLW EQU CYREG_PRT2_SLW\r
+SCSI_In_DBx__5__AG EQU CYREG_PRT2_AG\r
+SCSI_In_DBx__5__AMUX EQU CYREG_PRT2_AMUX\r
+SCSI_In_DBx__5__BIE EQU CYREG_PRT2_BIE\r
+SCSI_In_DBx__5__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
+SCSI_In_DBx__5__BYP EQU CYREG_PRT2_BYP\r
+SCSI_In_DBx__5__CTL EQU CYREG_PRT2_CTL\r
+SCSI_In_DBx__5__DM0 EQU CYREG_PRT2_DM0\r
+SCSI_In_DBx__5__DM1 EQU CYREG_PRT2_DM1\r
+SCSI_In_DBx__5__DM2 EQU CYREG_PRT2_DM2\r
+SCSI_In_DBx__5__DR EQU CYREG_PRT2_DR\r
+SCSI_In_DBx__5__INP_DIS EQU CYREG_PRT2_INP_DIS\r
+SCSI_In_DBx__5__INTTYPE EQU CYREG_PICU2_INTTYPE3\r
+SCSI_In_DBx__5__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
+SCSI_In_DBx__5__LCD_EN EQU CYREG_PRT2_LCD_EN\r
+SCSI_In_DBx__5__MASK EQU 0x08\r
+SCSI_In_DBx__5__PC EQU CYREG_PRT2_PC3\r
+SCSI_In_DBx__5__PORT EQU 2\r
+SCSI_In_DBx__5__PRT EQU CYREG_PRT2_PRT\r
+SCSI_In_DBx__5__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
+SCSI_In_DBx__5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
+SCSI_In_DBx__5__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
+SCSI_In_DBx__5__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
+SCSI_In_DBx__5__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
+SCSI_In_DBx__5__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
+SCSI_In_DBx__5__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
+SCSI_In_DBx__5__PS EQU CYREG_PRT2_PS\r
+SCSI_In_DBx__5__SHIFT EQU 3\r
+SCSI_In_DBx__5__SLW EQU CYREG_PRT2_SLW\r
+SCSI_In_DBx__6__AG EQU CYREG_PRT2_AG\r
+SCSI_In_DBx__6__AMUX EQU CYREG_PRT2_AMUX\r
+SCSI_In_DBx__6__BIE EQU CYREG_PRT2_BIE\r
+SCSI_In_DBx__6__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
+SCSI_In_DBx__6__BYP EQU CYREG_PRT2_BYP\r
+SCSI_In_DBx__6__CTL EQU CYREG_PRT2_CTL\r
+SCSI_In_DBx__6__DM0 EQU CYREG_PRT2_DM0\r
+SCSI_In_DBx__6__DM1 EQU CYREG_PRT2_DM1\r
+SCSI_In_DBx__6__DM2 EQU CYREG_PRT2_DM2\r
+SCSI_In_DBx__6__DR EQU CYREG_PRT2_DR\r
+SCSI_In_DBx__6__INP_DIS EQU CYREG_PRT2_INP_DIS\r
+SCSI_In_DBx__6__INTTYPE EQU CYREG_PICU2_INTTYPE2\r
+SCSI_In_DBx__6__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
+SCSI_In_DBx__6__LCD_EN EQU CYREG_PRT2_LCD_EN\r
+SCSI_In_DBx__6__MASK EQU 0x04\r
+SCSI_In_DBx__6__PC EQU CYREG_PRT2_PC2\r
+SCSI_In_DBx__6__PORT EQU 2\r
+SCSI_In_DBx__6__PRT EQU CYREG_PRT2_PRT\r
+SCSI_In_DBx__6__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
+SCSI_In_DBx__6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
+SCSI_In_DBx__6__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
+SCSI_In_DBx__6__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
+SCSI_In_DBx__6__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
+SCSI_In_DBx__6__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
+SCSI_In_DBx__6__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
+SCSI_In_DBx__6__PS EQU CYREG_PRT2_PS\r
+SCSI_In_DBx__6__SHIFT EQU 2\r
+SCSI_In_DBx__6__SLW EQU CYREG_PRT2_SLW\r
+SCSI_In_DBx__7__AG EQU CYREG_PRT2_AG\r
+SCSI_In_DBx__7__AMUX EQU CYREG_PRT2_AMUX\r
+SCSI_In_DBx__7__BIE EQU CYREG_PRT2_BIE\r
+SCSI_In_DBx__7__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
+SCSI_In_DBx__7__BYP EQU CYREG_PRT2_BYP\r
+SCSI_In_DBx__7__CTL EQU CYREG_PRT2_CTL\r
+SCSI_In_DBx__7__DM0 EQU CYREG_PRT2_DM0\r
+SCSI_In_DBx__7__DM1 EQU CYREG_PRT2_DM1\r
+SCSI_In_DBx__7__DM2 EQU CYREG_PRT2_DM2\r
+SCSI_In_DBx__7__DR EQU CYREG_PRT2_DR\r
+SCSI_In_DBx__7__INP_DIS EQU CYREG_PRT2_INP_DIS\r
+SCSI_In_DBx__7__INTTYPE EQU CYREG_PICU2_INTTYPE1\r
+SCSI_In_DBx__7__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
+SCSI_In_DBx__7__LCD_EN EQU CYREG_PRT2_LCD_EN\r
+SCSI_In_DBx__7__MASK EQU 0x02\r
+SCSI_In_DBx__7__PC EQU CYREG_PRT2_PC1\r
+SCSI_In_DBx__7__PORT EQU 2\r
+SCSI_In_DBx__7__PRT EQU CYREG_PRT2_PRT\r
+SCSI_In_DBx__7__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
+SCSI_In_DBx__7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
+SCSI_In_DBx__7__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
+SCSI_In_DBx__7__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
+SCSI_In_DBx__7__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
+SCSI_In_DBx__7__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
+SCSI_In_DBx__7__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
+SCSI_In_DBx__7__PS EQU CYREG_PRT2_PS\r
+SCSI_In_DBx__7__SHIFT EQU 1\r
+SCSI_In_DBx__7__SLW EQU CYREG_PRT2_SLW\r
+SCSI_In_DBx__DB0__AG EQU CYREG_PRT12_AG\r
+SCSI_In_DBx__DB0__BIE EQU CYREG_PRT12_BIE\r
+SCSI_In_DBx__DB0__BIT_MASK EQU CYREG_PRT12_BIT_MASK\r
+SCSI_In_DBx__DB0__BYP EQU CYREG_PRT12_BYP\r
+SCSI_In_DBx__DB0__DM0 EQU CYREG_PRT12_DM0\r
+SCSI_In_DBx__DB0__DM1 EQU CYREG_PRT12_DM1\r
+SCSI_In_DBx__DB0__DM2 EQU CYREG_PRT12_DM2\r
+SCSI_In_DBx__DB0__DR EQU CYREG_PRT12_DR\r
+SCSI_In_DBx__DB0__INP_DIS EQU CYREG_PRT12_INP_DIS\r
+SCSI_In_DBx__DB0__INTTYPE EQU CYREG_PICU12_INTTYPE4\r
+SCSI_In_DBx__DB0__MASK EQU 0x10\r
+SCSI_In_DBx__DB0__PC EQU CYREG_PRT12_PC4\r
+SCSI_In_DBx__DB0__PORT EQU 12\r
+SCSI_In_DBx__DB0__PRT EQU CYREG_PRT12_PRT\r
+SCSI_In_DBx__DB0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN\r
+SCSI_In_DBx__DB0__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0\r
+SCSI_In_DBx__DB0__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1\r
+SCSI_In_DBx__DB0__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0\r
+SCSI_In_DBx__DB0__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1\r
+SCSI_In_DBx__DB0__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT\r
+SCSI_In_DBx__DB0__PS EQU CYREG_PRT12_PS\r
+SCSI_In_DBx__DB0__SHIFT EQU 4\r
+SCSI_In_DBx__DB0__SIO_CFG EQU CYREG_PRT12_SIO_CFG\r
+SCSI_In_DBx__DB0__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF\r
+SCSI_In_DBx__DB0__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN\r
+SCSI_In_DBx__DB0__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ\r
+SCSI_In_DBx__DB0__SLW EQU CYREG_PRT12_SLW\r
+SCSI_In_DBx__DB1__AG EQU CYREG_PRT2_AG\r
+SCSI_In_DBx__DB1__AMUX EQU CYREG_PRT2_AMUX\r
+SCSI_In_DBx__DB1__BIE EQU CYREG_PRT2_BIE\r
+SCSI_In_DBx__DB1__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
+SCSI_In_DBx__DB1__BYP EQU CYREG_PRT2_BYP\r
+SCSI_In_DBx__DB1__CTL EQU CYREG_PRT2_CTL\r
+SCSI_In_DBx__DB1__DM0 EQU CYREG_PRT2_DM0\r
+SCSI_In_DBx__DB1__DM1 EQU CYREG_PRT2_DM1\r
+SCSI_In_DBx__DB1__DM2 EQU CYREG_PRT2_DM2\r
+SCSI_In_DBx__DB1__DR EQU CYREG_PRT2_DR\r
+SCSI_In_DBx__DB1__INP_DIS EQU CYREG_PRT2_INP_DIS\r
+SCSI_In_DBx__DB1__INTTYPE EQU CYREG_PICU2_INTTYPE7\r
+SCSI_In_DBx__DB1__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
+SCSI_In_DBx__DB1__LCD_EN EQU CYREG_PRT2_LCD_EN\r
+SCSI_In_DBx__DB1__MASK EQU 0x80\r
+SCSI_In_DBx__DB1__PC EQU CYREG_PRT2_PC7\r
+SCSI_In_DBx__DB1__PORT EQU 2\r
+SCSI_In_DBx__DB1__PRT EQU CYREG_PRT2_PRT\r
+SCSI_In_DBx__DB1__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
+SCSI_In_DBx__DB1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
+SCSI_In_DBx__DB1__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
+SCSI_In_DBx__DB1__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
+SCSI_In_DBx__DB1__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
+SCSI_In_DBx__DB1__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
+SCSI_In_DBx__DB1__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
+SCSI_In_DBx__DB1__PS EQU CYREG_PRT2_PS\r
+SCSI_In_DBx__DB1__SHIFT EQU 7\r
+SCSI_In_DBx__DB1__SLW EQU CYREG_PRT2_SLW\r
+SCSI_In_DBx__DB2__AG EQU CYREG_PRT2_AG\r
+SCSI_In_DBx__DB2__AMUX EQU CYREG_PRT2_AMUX\r
+SCSI_In_DBx__DB2__BIE EQU CYREG_PRT2_BIE\r
+SCSI_In_DBx__DB2__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
+SCSI_In_DBx__DB2__BYP EQU CYREG_PRT2_BYP\r
+SCSI_In_DBx__DB2__CTL EQU CYREG_PRT2_CTL\r
+SCSI_In_DBx__DB2__DM0 EQU CYREG_PRT2_DM0\r
+SCSI_In_DBx__DB2__DM1 EQU CYREG_PRT2_DM1\r
+SCSI_In_DBx__DB2__DM2 EQU CYREG_PRT2_DM2\r
+SCSI_In_DBx__DB2__DR EQU CYREG_PRT2_DR\r
+SCSI_In_DBx__DB2__INP_DIS EQU CYREG_PRT2_INP_DIS\r
+SCSI_In_DBx__DB2__INTTYPE EQU CYREG_PICU2_INTTYPE6\r
+SCSI_In_DBx__DB2__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
+SCSI_In_DBx__DB2__LCD_EN EQU CYREG_PRT2_LCD_EN\r
+SCSI_In_DBx__DB2__MASK EQU 0x40\r
+SCSI_In_DBx__DB2__PC EQU CYREG_PRT2_PC6\r
+SCSI_In_DBx__DB2__PORT EQU 2\r
+SCSI_In_DBx__DB2__PRT EQU CYREG_PRT2_PRT\r
+SCSI_In_DBx__DB2__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
+SCSI_In_DBx__DB2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
+SCSI_In_DBx__DB2__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
+SCSI_In_DBx__DB2__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
+SCSI_In_DBx__DB2__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
+SCSI_In_DBx__DB2__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
+SCSI_In_DBx__DB2__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
+SCSI_In_DBx__DB2__PS EQU CYREG_PRT2_PS\r
+SCSI_In_DBx__DB2__SHIFT EQU 6\r
+SCSI_In_DBx__DB2__SLW EQU CYREG_PRT2_SLW\r
+SCSI_In_DBx__DB3__AG EQU CYREG_PRT2_AG\r
+SCSI_In_DBx__DB3__AMUX EQU CYREG_PRT2_AMUX\r
+SCSI_In_DBx__DB3__BIE EQU CYREG_PRT2_BIE\r
+SCSI_In_DBx__DB3__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
+SCSI_In_DBx__DB3__BYP EQU CYREG_PRT2_BYP\r
+SCSI_In_DBx__DB3__CTL EQU CYREG_PRT2_CTL\r
+SCSI_In_DBx__DB3__DM0 EQU CYREG_PRT2_DM0\r
+SCSI_In_DBx__DB3__DM1 EQU CYREG_PRT2_DM1\r
+SCSI_In_DBx__DB3__DM2 EQU CYREG_PRT2_DM2\r
+SCSI_In_DBx__DB3__DR EQU CYREG_PRT2_DR\r
+SCSI_In_DBx__DB3__INP_DIS EQU CYREG_PRT2_INP_DIS\r
+SCSI_In_DBx__DB3__INTTYPE EQU CYREG_PICU2_INTTYPE5\r
+SCSI_In_DBx__DB3__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
+SCSI_In_DBx__DB3__LCD_EN EQU CYREG_PRT2_LCD_EN\r
+SCSI_In_DBx__DB3__MASK EQU 0x20\r
+SCSI_In_DBx__DB3__PC EQU CYREG_PRT2_PC5\r
+SCSI_In_DBx__DB3__PORT EQU 2\r
+SCSI_In_DBx__DB3__PRT EQU CYREG_PRT2_PRT\r
+SCSI_In_DBx__DB3__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
+SCSI_In_DBx__DB3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
+SCSI_In_DBx__DB3__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
+SCSI_In_DBx__DB3__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
+SCSI_In_DBx__DB3__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
+SCSI_In_DBx__DB3__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
+SCSI_In_DBx__DB3__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
+SCSI_In_DBx__DB3__PS EQU CYREG_PRT2_PS\r
+SCSI_In_DBx__DB3__SHIFT EQU 5\r
+SCSI_In_DBx__DB3__SLW EQU CYREG_PRT2_SLW\r
+SCSI_In_DBx__DB4__AG EQU CYREG_PRT2_AG\r
+SCSI_In_DBx__DB4__AMUX EQU CYREG_PRT2_AMUX\r
+SCSI_In_DBx__DB4__BIE EQU CYREG_PRT2_BIE\r
+SCSI_In_DBx__DB4__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
+SCSI_In_DBx__DB4__BYP EQU CYREG_PRT2_BYP\r
+SCSI_In_DBx__DB4__CTL EQU CYREG_PRT2_CTL\r
+SCSI_In_DBx__DB4__DM0 EQU CYREG_PRT2_DM0\r
+SCSI_In_DBx__DB4__DM1 EQU CYREG_PRT2_DM1\r
+SCSI_In_DBx__DB4__DM2 EQU CYREG_PRT2_DM2\r
+SCSI_In_DBx__DB4__DR EQU CYREG_PRT2_DR\r
+SCSI_In_DBx__DB4__INP_DIS EQU CYREG_PRT2_INP_DIS\r
+SCSI_In_DBx__DB4__INTTYPE EQU CYREG_PICU2_INTTYPE4\r
+SCSI_In_DBx__DB4__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
+SCSI_In_DBx__DB4__LCD_EN EQU CYREG_PRT2_LCD_EN\r
+SCSI_In_DBx__DB4__MASK EQU 0x10\r
+SCSI_In_DBx__DB4__PC EQU CYREG_PRT2_PC4\r
+SCSI_In_DBx__DB4__PORT EQU 2\r
+SCSI_In_DBx__DB4__PRT EQU CYREG_PRT2_PRT\r
+SCSI_In_DBx__DB4__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
+SCSI_In_DBx__DB4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
+SCSI_In_DBx__DB4__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
+SCSI_In_DBx__DB4__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
+SCSI_In_DBx__DB4__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
+SCSI_In_DBx__DB4__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
+SCSI_In_DBx__DB4__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
+SCSI_In_DBx__DB4__PS EQU CYREG_PRT2_PS\r
+SCSI_In_DBx__DB4__SHIFT EQU 4\r
+SCSI_In_DBx__DB4__SLW EQU CYREG_PRT2_SLW\r
+SCSI_In_DBx__DB5__AG EQU CYREG_PRT2_AG\r
+SCSI_In_DBx__DB5__AMUX EQU CYREG_PRT2_AMUX\r
+SCSI_In_DBx__DB5__BIE EQU CYREG_PRT2_BIE\r
+SCSI_In_DBx__DB5__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
+SCSI_In_DBx__DB5__BYP EQU CYREG_PRT2_BYP\r
+SCSI_In_DBx__DB5__CTL EQU CYREG_PRT2_CTL\r
+SCSI_In_DBx__DB5__DM0 EQU CYREG_PRT2_DM0\r
+SCSI_In_DBx__DB5__DM1 EQU CYREG_PRT2_DM1\r
+SCSI_In_DBx__DB5__DM2 EQU CYREG_PRT2_DM2\r
+SCSI_In_DBx__DB5__DR EQU CYREG_PRT2_DR\r
+SCSI_In_DBx__DB5__INP_DIS EQU CYREG_PRT2_INP_DIS\r
+SCSI_In_DBx__DB5__INTTYPE EQU CYREG_PICU2_INTTYPE3\r
+SCSI_In_DBx__DB5__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
+SCSI_In_DBx__DB5__LCD_EN EQU CYREG_PRT2_LCD_EN\r
+SCSI_In_DBx__DB5__MASK EQU 0x08\r
+SCSI_In_DBx__DB5__PC EQU CYREG_PRT2_PC3\r
+SCSI_In_DBx__DB5__PORT EQU 2\r
+SCSI_In_DBx__DB5__PRT EQU CYREG_PRT2_PRT\r
+SCSI_In_DBx__DB5__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
+SCSI_In_DBx__DB5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
+SCSI_In_DBx__DB5__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
+SCSI_In_DBx__DB5__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
+SCSI_In_DBx__DB5__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
+SCSI_In_DBx__DB5__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
+SCSI_In_DBx__DB5__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
+SCSI_In_DBx__DB5__PS EQU CYREG_PRT2_PS\r
+SCSI_In_DBx__DB5__SHIFT EQU 3\r
+SCSI_In_DBx__DB5__SLW EQU CYREG_PRT2_SLW\r
+SCSI_In_DBx__DB6__AG EQU CYREG_PRT2_AG\r
+SCSI_In_DBx__DB6__AMUX EQU CYREG_PRT2_AMUX\r
+SCSI_In_DBx__DB6__BIE EQU CYREG_PRT2_BIE\r
+SCSI_In_DBx__DB6__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
+SCSI_In_DBx__DB6__BYP EQU CYREG_PRT2_BYP\r
+SCSI_In_DBx__DB6__CTL EQU CYREG_PRT2_CTL\r
+SCSI_In_DBx__DB6__DM0 EQU CYREG_PRT2_DM0\r
+SCSI_In_DBx__DB6__DM1 EQU CYREG_PRT2_DM1\r
+SCSI_In_DBx__DB6__DM2 EQU CYREG_PRT2_DM2\r
+SCSI_In_DBx__DB6__DR EQU CYREG_PRT2_DR\r
+SCSI_In_DBx__DB6__INP_DIS EQU CYREG_PRT2_INP_DIS\r
+SCSI_In_DBx__DB6__INTTYPE EQU CYREG_PICU2_INTTYPE2\r
+SCSI_In_DBx__DB6__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
+SCSI_In_DBx__DB6__LCD_EN EQU CYREG_PRT2_LCD_EN\r
+SCSI_In_DBx__DB6__MASK EQU 0x04\r
+SCSI_In_DBx__DB6__PC EQU CYREG_PRT2_PC2\r
+SCSI_In_DBx__DB6__PORT EQU 2\r
+SCSI_In_DBx__DB6__PRT EQU CYREG_PRT2_PRT\r
+SCSI_In_DBx__DB6__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
+SCSI_In_DBx__DB6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
+SCSI_In_DBx__DB6__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
+SCSI_In_DBx__DB6__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
+SCSI_In_DBx__DB6__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
+SCSI_In_DBx__DB6__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
+SCSI_In_DBx__DB6__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
+SCSI_In_DBx__DB6__PS EQU CYREG_PRT2_PS\r
+SCSI_In_DBx__DB6__SHIFT EQU 2\r
+SCSI_In_DBx__DB6__SLW EQU CYREG_PRT2_SLW\r
+SCSI_In_DBx__DB7__AG EQU CYREG_PRT2_AG\r
+SCSI_In_DBx__DB7__AMUX EQU CYREG_PRT2_AMUX\r
+SCSI_In_DBx__DB7__BIE EQU CYREG_PRT2_BIE\r
+SCSI_In_DBx__DB7__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
+SCSI_In_DBx__DB7__BYP EQU CYREG_PRT2_BYP\r
+SCSI_In_DBx__DB7__CTL EQU CYREG_PRT2_CTL\r
+SCSI_In_DBx__DB7__DM0 EQU CYREG_PRT2_DM0\r
+SCSI_In_DBx__DB7__DM1 EQU CYREG_PRT2_DM1\r
+SCSI_In_DBx__DB7__DM2 EQU CYREG_PRT2_DM2\r
+SCSI_In_DBx__DB7__DR EQU CYREG_PRT2_DR\r
+SCSI_In_DBx__DB7__INP_DIS EQU CYREG_PRT2_INP_DIS\r
+SCSI_In_DBx__DB7__INTTYPE EQU CYREG_PICU2_INTTYPE1\r
+SCSI_In_DBx__DB7__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
+SCSI_In_DBx__DB7__LCD_EN EQU CYREG_PRT2_LCD_EN\r
+SCSI_In_DBx__DB7__MASK EQU 0x02\r
+SCSI_In_DBx__DB7__PC EQU CYREG_PRT2_PC1\r
+SCSI_In_DBx__DB7__PORT EQU 2\r
+SCSI_In_DBx__DB7__PRT EQU CYREG_PRT2_PRT\r
+SCSI_In_DBx__DB7__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
+SCSI_In_DBx__DB7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
+SCSI_In_DBx__DB7__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
+SCSI_In_DBx__DB7__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
+SCSI_In_DBx__DB7__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
+SCSI_In_DBx__DB7__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
+SCSI_In_DBx__DB7__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
+SCSI_In_DBx__DB7__PS EQU CYREG_PRT2_PS\r
+SCSI_In_DBx__DB7__SHIFT EQU 1\r
+SCSI_In_DBx__DB7__SLW EQU CYREG_PRT2_SLW\r
 \r
 /* SCSI_Noise */\r
 SCSI_Noise__0__AG EQU CYREG_PRT12_AG\r
@@ -2774,6 +1164,1772 @@ SCSI_Noise__SEL__PS EQU CYREG_PRT5_PS
 SCSI_Noise__SEL__SHIFT EQU 0\r
 SCSI_Noise__SEL__SLW EQU CYREG_PRT5_SLW\r
 \r
+/* SCSI_Out */\r
+SCSI_Out__0__AG EQU CYREG_PRT4_AG\r
+SCSI_Out__0__AMUX EQU CYREG_PRT4_AMUX\r
+SCSI_Out__0__BIE EQU CYREG_PRT4_BIE\r
+SCSI_Out__0__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
+SCSI_Out__0__BYP EQU CYREG_PRT4_BYP\r
+SCSI_Out__0__CTL EQU CYREG_PRT4_CTL\r
+SCSI_Out__0__DM0 EQU CYREG_PRT4_DM0\r
+SCSI_Out__0__DM1 EQU CYREG_PRT4_DM1\r
+SCSI_Out__0__DM2 EQU CYREG_PRT4_DM2\r
+SCSI_Out__0__DR EQU CYREG_PRT4_DR\r
+SCSI_Out__0__INP_DIS EQU CYREG_PRT4_INP_DIS\r
+SCSI_Out__0__INTTYPE EQU CYREG_PICU4_INTTYPE3\r
+SCSI_Out__0__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
+SCSI_Out__0__LCD_EN EQU CYREG_PRT4_LCD_EN\r
+SCSI_Out__0__MASK EQU 0x08\r
+SCSI_Out__0__PC EQU CYREG_PRT4_PC3\r
+SCSI_Out__0__PORT EQU 4\r
+SCSI_Out__0__PRT EQU CYREG_PRT4_PRT\r
+SCSI_Out__0__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
+SCSI_Out__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
+SCSI_Out__0__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
+SCSI_Out__0__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
+SCSI_Out__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
+SCSI_Out__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
+SCSI_Out__0__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
+SCSI_Out__0__PS EQU CYREG_PRT4_PS\r
+SCSI_Out__0__SHIFT EQU 3\r
+SCSI_Out__0__SLW EQU CYREG_PRT4_SLW\r
+SCSI_Out__1__AG EQU CYREG_PRT4_AG\r
+SCSI_Out__1__AMUX EQU CYREG_PRT4_AMUX\r
+SCSI_Out__1__BIE EQU CYREG_PRT4_BIE\r
+SCSI_Out__1__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
+SCSI_Out__1__BYP EQU CYREG_PRT4_BYP\r
+SCSI_Out__1__CTL EQU CYREG_PRT4_CTL\r
+SCSI_Out__1__DM0 EQU CYREG_PRT4_DM0\r
+SCSI_Out__1__DM1 EQU CYREG_PRT4_DM1\r
+SCSI_Out__1__DM2 EQU CYREG_PRT4_DM2\r
+SCSI_Out__1__DR EQU CYREG_PRT4_DR\r
+SCSI_Out__1__INP_DIS EQU CYREG_PRT4_INP_DIS\r
+SCSI_Out__1__INTTYPE EQU CYREG_PICU4_INTTYPE2\r
+SCSI_Out__1__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
+SCSI_Out__1__LCD_EN EQU CYREG_PRT4_LCD_EN\r
+SCSI_Out__1__MASK EQU 0x04\r
+SCSI_Out__1__PC EQU CYREG_PRT4_PC2\r
+SCSI_Out__1__PORT EQU 4\r
+SCSI_Out__1__PRT EQU CYREG_PRT4_PRT\r
+SCSI_Out__1__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
+SCSI_Out__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
+SCSI_Out__1__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
+SCSI_Out__1__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
+SCSI_Out__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
+SCSI_Out__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
+SCSI_Out__1__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
+SCSI_Out__1__PS EQU CYREG_PRT4_PS\r
+SCSI_Out__1__SHIFT EQU 2\r
+SCSI_Out__1__SLW EQU CYREG_PRT4_SLW\r
+SCSI_Out__2__AG EQU CYREG_PRT0_AG\r
+SCSI_Out__2__AMUX EQU CYREG_PRT0_AMUX\r
+SCSI_Out__2__BIE EQU CYREG_PRT0_BIE\r
+SCSI_Out__2__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
+SCSI_Out__2__BYP EQU CYREG_PRT0_BYP\r
+SCSI_Out__2__CTL EQU CYREG_PRT0_CTL\r
+SCSI_Out__2__DM0 EQU CYREG_PRT0_DM0\r
+SCSI_Out__2__DM1 EQU CYREG_PRT0_DM1\r
+SCSI_Out__2__DM2 EQU CYREG_PRT0_DM2\r
+SCSI_Out__2__DR EQU CYREG_PRT0_DR\r
+SCSI_Out__2__INP_DIS EQU CYREG_PRT0_INP_DIS\r
+SCSI_Out__2__INTTYPE EQU CYREG_PICU0_INTTYPE7\r
+SCSI_Out__2__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
+SCSI_Out__2__LCD_EN EQU CYREG_PRT0_LCD_EN\r
+SCSI_Out__2__MASK EQU 0x80\r
+SCSI_Out__2__PC EQU CYREG_PRT0_PC7\r
+SCSI_Out__2__PORT EQU 0\r
+SCSI_Out__2__PRT EQU CYREG_PRT0_PRT\r
+SCSI_Out__2__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
+SCSI_Out__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
+SCSI_Out__2__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
+SCSI_Out__2__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
+SCSI_Out__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
+SCSI_Out__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
+SCSI_Out__2__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
+SCSI_Out__2__PS EQU CYREG_PRT0_PS\r
+SCSI_Out__2__SHIFT EQU 7\r
+SCSI_Out__2__SLW EQU CYREG_PRT0_SLW\r
+SCSI_Out__3__AG EQU CYREG_PRT0_AG\r
+SCSI_Out__3__AMUX EQU CYREG_PRT0_AMUX\r
+SCSI_Out__3__BIE EQU CYREG_PRT0_BIE\r
+SCSI_Out__3__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
+SCSI_Out__3__BYP EQU CYREG_PRT0_BYP\r
+SCSI_Out__3__CTL EQU CYREG_PRT0_CTL\r
+SCSI_Out__3__DM0 EQU CYREG_PRT0_DM0\r
+SCSI_Out__3__DM1 EQU CYREG_PRT0_DM1\r
+SCSI_Out__3__DM2 EQU CYREG_PRT0_DM2\r
+SCSI_Out__3__DR EQU CYREG_PRT0_DR\r
+SCSI_Out__3__INP_DIS EQU CYREG_PRT0_INP_DIS\r
+SCSI_Out__3__INTTYPE EQU CYREG_PICU0_INTTYPE6\r
+SCSI_Out__3__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
+SCSI_Out__3__LCD_EN EQU CYREG_PRT0_LCD_EN\r
+SCSI_Out__3__MASK EQU 0x40\r
+SCSI_Out__3__PC EQU CYREG_PRT0_PC6\r
+SCSI_Out__3__PORT EQU 0\r
+SCSI_Out__3__PRT EQU CYREG_PRT0_PRT\r
+SCSI_Out__3__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
+SCSI_Out__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
+SCSI_Out__3__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
+SCSI_Out__3__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
+SCSI_Out__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
+SCSI_Out__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
+SCSI_Out__3__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
+SCSI_Out__3__PS EQU CYREG_PRT0_PS\r
+SCSI_Out__3__SHIFT EQU 6\r
+SCSI_Out__3__SLW EQU CYREG_PRT0_SLW\r
+SCSI_Out__4__AG EQU CYREG_PRT0_AG\r
+SCSI_Out__4__AMUX EQU CYREG_PRT0_AMUX\r
+SCSI_Out__4__BIE EQU CYREG_PRT0_BIE\r
+SCSI_Out__4__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
+SCSI_Out__4__BYP EQU CYREG_PRT0_BYP\r
+SCSI_Out__4__CTL EQU CYREG_PRT0_CTL\r
+SCSI_Out__4__DM0 EQU CYREG_PRT0_DM0\r
+SCSI_Out__4__DM1 EQU CYREG_PRT0_DM1\r
+SCSI_Out__4__DM2 EQU CYREG_PRT0_DM2\r
+SCSI_Out__4__DR EQU CYREG_PRT0_DR\r
+SCSI_Out__4__INP_DIS EQU CYREG_PRT0_INP_DIS\r
+SCSI_Out__4__INTTYPE EQU CYREG_PICU0_INTTYPE5\r
+SCSI_Out__4__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
+SCSI_Out__4__LCD_EN EQU CYREG_PRT0_LCD_EN\r
+SCSI_Out__4__MASK EQU 0x20\r
+SCSI_Out__4__PC EQU CYREG_PRT0_PC5\r
+SCSI_Out__4__PORT EQU 0\r
+SCSI_Out__4__PRT EQU CYREG_PRT0_PRT\r
+SCSI_Out__4__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
+SCSI_Out__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
+SCSI_Out__4__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
+SCSI_Out__4__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
+SCSI_Out__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
+SCSI_Out__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
+SCSI_Out__4__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
+SCSI_Out__4__PS EQU CYREG_PRT0_PS\r
+SCSI_Out__4__SHIFT EQU 5\r
+SCSI_Out__4__SLW EQU CYREG_PRT0_SLW\r
+SCSI_Out__5__AG EQU CYREG_PRT0_AG\r
+SCSI_Out__5__AMUX EQU CYREG_PRT0_AMUX\r
+SCSI_Out__5__BIE EQU CYREG_PRT0_BIE\r
+SCSI_Out__5__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
+SCSI_Out__5__BYP EQU CYREG_PRT0_BYP\r
+SCSI_Out__5__CTL EQU CYREG_PRT0_CTL\r
+SCSI_Out__5__DM0 EQU CYREG_PRT0_DM0\r
+SCSI_Out__5__DM1 EQU CYREG_PRT0_DM1\r
+SCSI_Out__5__DM2 EQU CYREG_PRT0_DM2\r
+SCSI_Out__5__DR EQU CYREG_PRT0_DR\r
+SCSI_Out__5__INP_DIS EQU CYREG_PRT0_INP_DIS\r
+SCSI_Out__5__INTTYPE EQU CYREG_PICU0_INTTYPE4\r
+SCSI_Out__5__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
+SCSI_Out__5__LCD_EN EQU CYREG_PRT0_LCD_EN\r
+SCSI_Out__5__MASK EQU 0x10\r
+SCSI_Out__5__PC EQU CYREG_PRT0_PC4\r
+SCSI_Out__5__PORT EQU 0\r
+SCSI_Out__5__PRT EQU CYREG_PRT0_PRT\r
+SCSI_Out__5__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
+SCSI_Out__5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
+SCSI_Out__5__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
+SCSI_Out__5__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
+SCSI_Out__5__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
+SCSI_Out__5__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
+SCSI_Out__5__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
+SCSI_Out__5__PS EQU CYREG_PRT0_PS\r
+SCSI_Out__5__SHIFT EQU 4\r
+SCSI_Out__5__SLW EQU CYREG_PRT0_SLW\r
+SCSI_Out__6__AG EQU CYREG_PRT0_AG\r
+SCSI_Out__6__AMUX EQU CYREG_PRT0_AMUX\r
+SCSI_Out__6__BIE EQU CYREG_PRT0_BIE\r
+SCSI_Out__6__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
+SCSI_Out__6__BYP EQU CYREG_PRT0_BYP\r
+SCSI_Out__6__CTL EQU CYREG_PRT0_CTL\r
+SCSI_Out__6__DM0 EQU CYREG_PRT0_DM0\r
+SCSI_Out__6__DM1 EQU CYREG_PRT0_DM1\r
+SCSI_Out__6__DM2 EQU CYREG_PRT0_DM2\r
+SCSI_Out__6__DR EQU CYREG_PRT0_DR\r
+SCSI_Out__6__INP_DIS EQU CYREG_PRT0_INP_DIS\r
+SCSI_Out__6__INTTYPE EQU CYREG_PICU0_INTTYPE3\r
+SCSI_Out__6__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
+SCSI_Out__6__LCD_EN EQU CYREG_PRT0_LCD_EN\r
+SCSI_Out__6__MASK EQU 0x08\r
+SCSI_Out__6__PC EQU CYREG_PRT0_PC3\r
+SCSI_Out__6__PORT EQU 0\r
+SCSI_Out__6__PRT EQU CYREG_PRT0_PRT\r
+SCSI_Out__6__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
+SCSI_Out__6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
+SCSI_Out__6__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
+SCSI_Out__6__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
+SCSI_Out__6__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
+SCSI_Out__6__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
+SCSI_Out__6__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
+SCSI_Out__6__PS EQU CYREG_PRT0_PS\r
+SCSI_Out__6__SHIFT EQU 3\r
+SCSI_Out__6__SLW EQU CYREG_PRT0_SLW\r
+SCSI_Out__7__AG EQU CYREG_PRT0_AG\r
+SCSI_Out__7__AMUX EQU CYREG_PRT0_AMUX\r
+SCSI_Out__7__BIE EQU CYREG_PRT0_BIE\r
+SCSI_Out__7__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
+SCSI_Out__7__BYP EQU CYREG_PRT0_BYP\r
+SCSI_Out__7__CTL EQU CYREG_PRT0_CTL\r
+SCSI_Out__7__DM0 EQU CYREG_PRT0_DM0\r
+SCSI_Out__7__DM1 EQU CYREG_PRT0_DM1\r
+SCSI_Out__7__DM2 EQU CYREG_PRT0_DM2\r
+SCSI_Out__7__DR EQU CYREG_PRT0_DR\r
+SCSI_Out__7__INP_DIS EQU CYREG_PRT0_INP_DIS\r
+SCSI_Out__7__INTTYPE EQU CYREG_PICU0_INTTYPE2\r
+SCSI_Out__7__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
+SCSI_Out__7__LCD_EN EQU CYREG_PRT0_LCD_EN\r
+SCSI_Out__7__MASK EQU 0x04\r
+SCSI_Out__7__PC EQU CYREG_PRT0_PC2\r
+SCSI_Out__7__PORT EQU 0\r
+SCSI_Out__7__PRT EQU CYREG_PRT0_PRT\r
+SCSI_Out__7__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
+SCSI_Out__7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
+SCSI_Out__7__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
+SCSI_Out__7__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
+SCSI_Out__7__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
+SCSI_Out__7__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
+SCSI_Out__7__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
+SCSI_Out__7__PS EQU CYREG_PRT0_PS\r
+SCSI_Out__7__SHIFT EQU 2\r
+SCSI_Out__7__SLW EQU CYREG_PRT0_SLW\r
+SCSI_Out__8__AG EQU CYREG_PRT0_AG\r
+SCSI_Out__8__AMUX EQU CYREG_PRT0_AMUX\r
+SCSI_Out__8__BIE EQU CYREG_PRT0_BIE\r
+SCSI_Out__8__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
+SCSI_Out__8__BYP EQU CYREG_PRT0_BYP\r
+SCSI_Out__8__CTL EQU CYREG_PRT0_CTL\r
+SCSI_Out__8__DM0 EQU CYREG_PRT0_DM0\r
+SCSI_Out__8__DM1 EQU CYREG_PRT0_DM1\r
+SCSI_Out__8__DM2 EQU CYREG_PRT0_DM2\r
+SCSI_Out__8__DR EQU CYREG_PRT0_DR\r
+SCSI_Out__8__INP_DIS EQU CYREG_PRT0_INP_DIS\r
+SCSI_Out__8__INTTYPE EQU CYREG_PICU0_INTTYPE1\r
+SCSI_Out__8__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
+SCSI_Out__8__LCD_EN EQU CYREG_PRT0_LCD_EN\r
+SCSI_Out__8__MASK EQU 0x02\r
+SCSI_Out__8__PC EQU CYREG_PRT0_PC1\r
+SCSI_Out__8__PORT EQU 0\r
+SCSI_Out__8__PRT EQU CYREG_PRT0_PRT\r
+SCSI_Out__8__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
+SCSI_Out__8__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
+SCSI_Out__8__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
+SCSI_Out__8__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
+SCSI_Out__8__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
+SCSI_Out__8__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
+SCSI_Out__8__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
+SCSI_Out__8__PS EQU CYREG_PRT0_PS\r
+SCSI_Out__8__SHIFT EQU 1\r
+SCSI_Out__8__SLW EQU CYREG_PRT0_SLW\r
+SCSI_Out__9__AG EQU CYREG_PRT0_AG\r
+SCSI_Out__9__AMUX EQU CYREG_PRT0_AMUX\r
+SCSI_Out__9__BIE EQU CYREG_PRT0_BIE\r
+SCSI_Out__9__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
+SCSI_Out__9__BYP EQU CYREG_PRT0_BYP\r
+SCSI_Out__9__CTL EQU CYREG_PRT0_CTL\r
+SCSI_Out__9__DM0 EQU CYREG_PRT0_DM0\r
+SCSI_Out__9__DM1 EQU CYREG_PRT0_DM1\r
+SCSI_Out__9__DM2 EQU CYREG_PRT0_DM2\r
+SCSI_Out__9__DR EQU CYREG_PRT0_DR\r
+SCSI_Out__9__INP_DIS EQU CYREG_PRT0_INP_DIS\r
+SCSI_Out__9__INTTYPE EQU CYREG_PICU0_INTTYPE0\r
+SCSI_Out__9__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
+SCSI_Out__9__LCD_EN EQU CYREG_PRT0_LCD_EN\r
+SCSI_Out__9__MASK EQU 0x01\r
+SCSI_Out__9__PC EQU CYREG_PRT0_PC0\r
+SCSI_Out__9__PORT EQU 0\r
+SCSI_Out__9__PRT EQU CYREG_PRT0_PRT\r
+SCSI_Out__9__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
+SCSI_Out__9__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
+SCSI_Out__9__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
+SCSI_Out__9__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
+SCSI_Out__9__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
+SCSI_Out__9__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
+SCSI_Out__9__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
+SCSI_Out__9__PS EQU CYREG_PRT0_PS\r
+SCSI_Out__9__SHIFT EQU 0\r
+SCSI_Out__9__SLW EQU CYREG_PRT0_SLW\r
+SCSI_Out__ACK__AG EQU CYREG_PRT0_AG\r
+SCSI_Out__ACK__AMUX EQU CYREG_PRT0_AMUX\r
+SCSI_Out__ACK__BIE EQU CYREG_PRT0_BIE\r
+SCSI_Out__ACK__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
+SCSI_Out__ACK__BYP EQU CYREG_PRT0_BYP\r
+SCSI_Out__ACK__CTL EQU CYREG_PRT0_CTL\r
+SCSI_Out__ACK__DM0 EQU CYREG_PRT0_DM0\r
+SCSI_Out__ACK__DM1 EQU CYREG_PRT0_DM1\r
+SCSI_Out__ACK__DM2 EQU CYREG_PRT0_DM2\r
+SCSI_Out__ACK__DR EQU CYREG_PRT0_DR\r
+SCSI_Out__ACK__INP_DIS EQU CYREG_PRT0_INP_DIS\r
+SCSI_Out__ACK__INTTYPE EQU CYREG_PICU0_INTTYPE6\r
+SCSI_Out__ACK__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
+SCSI_Out__ACK__LCD_EN EQU CYREG_PRT0_LCD_EN\r
+SCSI_Out__ACK__MASK EQU 0x40\r
+SCSI_Out__ACK__PC EQU CYREG_PRT0_PC6\r
+SCSI_Out__ACK__PORT EQU 0\r
+SCSI_Out__ACK__PRT EQU CYREG_PRT0_PRT\r
+SCSI_Out__ACK__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
+SCSI_Out__ACK__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
+SCSI_Out__ACK__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
+SCSI_Out__ACK__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
+SCSI_Out__ACK__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
+SCSI_Out__ACK__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
+SCSI_Out__ACK__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
+SCSI_Out__ACK__PS EQU CYREG_PRT0_PS\r
+SCSI_Out__ACK__SHIFT EQU 6\r
+SCSI_Out__ACK__SLW EQU CYREG_PRT0_SLW\r
+SCSI_Out__ATN__AG EQU CYREG_PRT4_AG\r
+SCSI_Out__ATN__AMUX EQU CYREG_PRT4_AMUX\r
+SCSI_Out__ATN__BIE EQU CYREG_PRT4_BIE\r
+SCSI_Out__ATN__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
+SCSI_Out__ATN__BYP EQU CYREG_PRT4_BYP\r
+SCSI_Out__ATN__CTL EQU CYREG_PRT4_CTL\r
+SCSI_Out__ATN__DM0 EQU CYREG_PRT4_DM0\r
+SCSI_Out__ATN__DM1 EQU CYREG_PRT4_DM1\r
+SCSI_Out__ATN__DM2 EQU CYREG_PRT4_DM2\r
+SCSI_Out__ATN__DR EQU CYREG_PRT4_DR\r
+SCSI_Out__ATN__INP_DIS EQU CYREG_PRT4_INP_DIS\r
+SCSI_Out__ATN__INTTYPE EQU CYREG_PICU4_INTTYPE2\r
+SCSI_Out__ATN__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
+SCSI_Out__ATN__LCD_EN EQU CYREG_PRT4_LCD_EN\r
+SCSI_Out__ATN__MASK EQU 0x04\r
+SCSI_Out__ATN__PC EQU CYREG_PRT4_PC2\r
+SCSI_Out__ATN__PORT EQU 4\r
+SCSI_Out__ATN__PRT EQU CYREG_PRT4_PRT\r
+SCSI_Out__ATN__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
+SCSI_Out__ATN__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
+SCSI_Out__ATN__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
+SCSI_Out__ATN__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
+SCSI_Out__ATN__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
+SCSI_Out__ATN__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
+SCSI_Out__ATN__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
+SCSI_Out__ATN__PS EQU CYREG_PRT4_PS\r
+SCSI_Out__ATN__SHIFT EQU 2\r
+SCSI_Out__ATN__SLW EQU CYREG_PRT4_SLW\r
+SCSI_Out__BSY__AG EQU CYREG_PRT0_AG\r
+SCSI_Out__BSY__AMUX EQU CYREG_PRT0_AMUX\r
+SCSI_Out__BSY__BIE EQU CYREG_PRT0_BIE\r
+SCSI_Out__BSY__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
+SCSI_Out__BSY__BYP EQU CYREG_PRT0_BYP\r
+SCSI_Out__BSY__CTL EQU CYREG_PRT0_CTL\r
+SCSI_Out__BSY__DM0 EQU CYREG_PRT0_DM0\r
+SCSI_Out__BSY__DM1 EQU CYREG_PRT0_DM1\r
+SCSI_Out__BSY__DM2 EQU CYREG_PRT0_DM2\r
+SCSI_Out__BSY__DR EQU CYREG_PRT0_DR\r
+SCSI_Out__BSY__INP_DIS EQU CYREG_PRT0_INP_DIS\r
+SCSI_Out__BSY__INTTYPE EQU CYREG_PICU0_INTTYPE7\r
+SCSI_Out__BSY__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
+SCSI_Out__BSY__LCD_EN EQU CYREG_PRT0_LCD_EN\r
+SCSI_Out__BSY__MASK EQU 0x80\r
+SCSI_Out__BSY__PC EQU CYREG_PRT0_PC7\r
+SCSI_Out__BSY__PORT EQU 0\r
+SCSI_Out__BSY__PRT EQU CYREG_PRT0_PRT\r
+SCSI_Out__BSY__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
+SCSI_Out__BSY__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
+SCSI_Out__BSY__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
+SCSI_Out__BSY__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
+SCSI_Out__BSY__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
+SCSI_Out__BSY__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
+SCSI_Out__BSY__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
+SCSI_Out__BSY__PS EQU CYREG_PRT0_PS\r
+SCSI_Out__BSY__SHIFT EQU 7\r
+SCSI_Out__BSY__SLW EQU CYREG_PRT0_SLW\r
+SCSI_Out__CD_raw__AG EQU CYREG_PRT0_AG\r
+SCSI_Out__CD_raw__AMUX EQU CYREG_PRT0_AMUX\r
+SCSI_Out__CD_raw__BIE EQU CYREG_PRT0_BIE\r
+SCSI_Out__CD_raw__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
+SCSI_Out__CD_raw__BYP EQU CYREG_PRT0_BYP\r
+SCSI_Out__CD_raw__CTL EQU CYREG_PRT0_CTL\r
+SCSI_Out__CD_raw__DM0 EQU CYREG_PRT0_DM0\r
+SCSI_Out__CD_raw__DM1 EQU CYREG_PRT0_DM1\r
+SCSI_Out__CD_raw__DM2 EQU CYREG_PRT0_DM2\r
+SCSI_Out__CD_raw__DR EQU CYREG_PRT0_DR\r
+SCSI_Out__CD_raw__INP_DIS EQU CYREG_PRT0_INP_DIS\r
+SCSI_Out__CD_raw__INTTYPE EQU CYREG_PICU0_INTTYPE2\r
+SCSI_Out__CD_raw__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
+SCSI_Out__CD_raw__LCD_EN EQU CYREG_PRT0_LCD_EN\r
+SCSI_Out__CD_raw__MASK EQU 0x04\r
+SCSI_Out__CD_raw__PC EQU CYREG_PRT0_PC2\r
+SCSI_Out__CD_raw__PORT EQU 0\r
+SCSI_Out__CD_raw__PRT EQU CYREG_PRT0_PRT\r
+SCSI_Out__CD_raw__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
+SCSI_Out__CD_raw__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
+SCSI_Out__CD_raw__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
+SCSI_Out__CD_raw__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
+SCSI_Out__CD_raw__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
+SCSI_Out__CD_raw__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
+SCSI_Out__CD_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
+SCSI_Out__CD_raw__PS EQU CYREG_PRT0_PS\r
+SCSI_Out__CD_raw__SHIFT EQU 2\r
+SCSI_Out__CD_raw__SLW EQU CYREG_PRT0_SLW\r
+SCSI_Out__DBP_raw__AG EQU CYREG_PRT4_AG\r
+SCSI_Out__DBP_raw__AMUX EQU CYREG_PRT4_AMUX\r
+SCSI_Out__DBP_raw__BIE EQU CYREG_PRT4_BIE\r
+SCSI_Out__DBP_raw__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
+SCSI_Out__DBP_raw__BYP EQU CYREG_PRT4_BYP\r
+SCSI_Out__DBP_raw__CTL EQU CYREG_PRT4_CTL\r
+SCSI_Out__DBP_raw__DM0 EQU CYREG_PRT4_DM0\r
+SCSI_Out__DBP_raw__DM1 EQU CYREG_PRT4_DM1\r
+SCSI_Out__DBP_raw__DM2 EQU CYREG_PRT4_DM2\r
+SCSI_Out__DBP_raw__DR EQU CYREG_PRT4_DR\r
+SCSI_Out__DBP_raw__INP_DIS EQU CYREG_PRT4_INP_DIS\r
+SCSI_Out__DBP_raw__INTTYPE EQU CYREG_PICU4_INTTYPE3\r
+SCSI_Out__DBP_raw__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
+SCSI_Out__DBP_raw__LCD_EN EQU CYREG_PRT4_LCD_EN\r
+SCSI_Out__DBP_raw__MASK EQU 0x08\r
+SCSI_Out__DBP_raw__PC EQU CYREG_PRT4_PC3\r
+SCSI_Out__DBP_raw__PORT EQU 4\r
+SCSI_Out__DBP_raw__PRT EQU CYREG_PRT4_PRT\r
+SCSI_Out__DBP_raw__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
+SCSI_Out__DBP_raw__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
+SCSI_Out__DBP_raw__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
+SCSI_Out__DBP_raw__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
+SCSI_Out__DBP_raw__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
+SCSI_Out__DBP_raw__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
+SCSI_Out__DBP_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
+SCSI_Out__DBP_raw__PS EQU CYREG_PRT4_PS\r
+SCSI_Out__DBP_raw__SHIFT EQU 3\r
+SCSI_Out__DBP_raw__SLW EQU CYREG_PRT4_SLW\r
+SCSI_Out__IO_raw__AG EQU CYREG_PRT0_AG\r
+SCSI_Out__IO_raw__AMUX EQU CYREG_PRT0_AMUX\r
+SCSI_Out__IO_raw__BIE EQU CYREG_PRT0_BIE\r
+SCSI_Out__IO_raw__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
+SCSI_Out__IO_raw__BYP EQU CYREG_PRT0_BYP\r
+SCSI_Out__IO_raw__CTL EQU CYREG_PRT0_CTL\r
+SCSI_Out__IO_raw__DM0 EQU CYREG_PRT0_DM0\r
+SCSI_Out__IO_raw__DM1 EQU CYREG_PRT0_DM1\r
+SCSI_Out__IO_raw__DM2 EQU CYREG_PRT0_DM2\r
+SCSI_Out__IO_raw__DR EQU CYREG_PRT0_DR\r
+SCSI_Out__IO_raw__INP_DIS EQU CYREG_PRT0_INP_DIS\r
+SCSI_Out__IO_raw__INTTYPE EQU CYREG_PICU0_INTTYPE0\r
+SCSI_Out__IO_raw__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
+SCSI_Out__IO_raw__LCD_EN EQU CYREG_PRT0_LCD_EN\r
+SCSI_Out__IO_raw__MASK EQU 0x01\r
+SCSI_Out__IO_raw__PC EQU CYREG_PRT0_PC0\r
+SCSI_Out__IO_raw__PORT EQU 0\r
+SCSI_Out__IO_raw__PRT EQU CYREG_PRT0_PRT\r
+SCSI_Out__IO_raw__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
+SCSI_Out__IO_raw__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
+SCSI_Out__IO_raw__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
+SCSI_Out__IO_raw__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
+SCSI_Out__IO_raw__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
+SCSI_Out__IO_raw__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
+SCSI_Out__IO_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
+SCSI_Out__IO_raw__PS EQU CYREG_PRT0_PS\r
+SCSI_Out__IO_raw__SHIFT EQU 0\r
+SCSI_Out__IO_raw__SLW EQU CYREG_PRT0_SLW\r
+SCSI_Out__MSG_raw__AG EQU CYREG_PRT0_AG\r
+SCSI_Out__MSG_raw__AMUX EQU CYREG_PRT0_AMUX\r
+SCSI_Out__MSG_raw__BIE EQU CYREG_PRT0_BIE\r
+SCSI_Out__MSG_raw__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
+SCSI_Out__MSG_raw__BYP EQU CYREG_PRT0_BYP\r
+SCSI_Out__MSG_raw__CTL EQU CYREG_PRT0_CTL\r
+SCSI_Out__MSG_raw__DM0 EQU CYREG_PRT0_DM0\r
+SCSI_Out__MSG_raw__DM1 EQU CYREG_PRT0_DM1\r
+SCSI_Out__MSG_raw__DM2 EQU CYREG_PRT0_DM2\r
+SCSI_Out__MSG_raw__DR EQU CYREG_PRT0_DR\r
+SCSI_Out__MSG_raw__INP_DIS EQU CYREG_PRT0_INP_DIS\r
+SCSI_Out__MSG_raw__INTTYPE EQU CYREG_PICU0_INTTYPE4\r
+SCSI_Out__MSG_raw__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
+SCSI_Out__MSG_raw__LCD_EN EQU CYREG_PRT0_LCD_EN\r
+SCSI_Out__MSG_raw__MASK EQU 0x10\r
+SCSI_Out__MSG_raw__PC EQU CYREG_PRT0_PC4\r
+SCSI_Out__MSG_raw__PORT EQU 0\r
+SCSI_Out__MSG_raw__PRT EQU CYREG_PRT0_PRT\r
+SCSI_Out__MSG_raw__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
+SCSI_Out__MSG_raw__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
+SCSI_Out__MSG_raw__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
+SCSI_Out__MSG_raw__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
+SCSI_Out__MSG_raw__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
+SCSI_Out__MSG_raw__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
+SCSI_Out__MSG_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
+SCSI_Out__MSG_raw__PS EQU CYREG_PRT0_PS\r
+SCSI_Out__MSG_raw__SHIFT EQU 4\r
+SCSI_Out__MSG_raw__SLW EQU CYREG_PRT0_SLW\r
+SCSI_Out__REQ__AG EQU CYREG_PRT0_AG\r
+SCSI_Out__REQ__AMUX EQU CYREG_PRT0_AMUX\r
+SCSI_Out__REQ__BIE EQU CYREG_PRT0_BIE\r
+SCSI_Out__REQ__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
+SCSI_Out__REQ__BYP EQU CYREG_PRT0_BYP\r
+SCSI_Out__REQ__CTL EQU CYREG_PRT0_CTL\r
+SCSI_Out__REQ__DM0 EQU CYREG_PRT0_DM0\r
+SCSI_Out__REQ__DM1 EQU CYREG_PRT0_DM1\r
+SCSI_Out__REQ__DM2 EQU CYREG_PRT0_DM2\r
+SCSI_Out__REQ__DR EQU CYREG_PRT0_DR\r
+SCSI_Out__REQ__INP_DIS EQU CYREG_PRT0_INP_DIS\r
+SCSI_Out__REQ__INTTYPE EQU CYREG_PICU0_INTTYPE1\r
+SCSI_Out__REQ__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
+SCSI_Out__REQ__LCD_EN EQU CYREG_PRT0_LCD_EN\r
+SCSI_Out__REQ__MASK EQU 0x02\r
+SCSI_Out__REQ__PC EQU CYREG_PRT0_PC1\r
+SCSI_Out__REQ__PORT EQU 0\r
+SCSI_Out__REQ__PRT EQU CYREG_PRT0_PRT\r
+SCSI_Out__REQ__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
+SCSI_Out__REQ__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
+SCSI_Out__REQ__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
+SCSI_Out__REQ__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
+SCSI_Out__REQ__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
+SCSI_Out__REQ__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
+SCSI_Out__REQ__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
+SCSI_Out__REQ__PS EQU CYREG_PRT0_PS\r
+SCSI_Out__REQ__SHIFT EQU 1\r
+SCSI_Out__REQ__SLW EQU CYREG_PRT0_SLW\r
+SCSI_Out__RST__AG EQU CYREG_PRT0_AG\r
+SCSI_Out__RST__AMUX EQU CYREG_PRT0_AMUX\r
+SCSI_Out__RST__BIE EQU CYREG_PRT0_BIE\r
+SCSI_Out__RST__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
+SCSI_Out__RST__BYP EQU CYREG_PRT0_BYP\r
+SCSI_Out__RST__CTL EQU CYREG_PRT0_CTL\r
+SCSI_Out__RST__DM0 EQU CYREG_PRT0_DM0\r
+SCSI_Out__RST__DM1 EQU CYREG_PRT0_DM1\r
+SCSI_Out__RST__DM2 EQU CYREG_PRT0_DM2\r
+SCSI_Out__RST__DR EQU CYREG_PRT0_DR\r
+SCSI_Out__RST__INP_DIS EQU CYREG_PRT0_INP_DIS\r
+SCSI_Out__RST__INTTYPE EQU CYREG_PICU0_INTTYPE5\r
+SCSI_Out__RST__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
+SCSI_Out__RST__LCD_EN EQU CYREG_PRT0_LCD_EN\r
+SCSI_Out__RST__MASK EQU 0x20\r
+SCSI_Out__RST__PC EQU CYREG_PRT0_PC5\r
+SCSI_Out__RST__PORT EQU 0\r
+SCSI_Out__RST__PRT EQU CYREG_PRT0_PRT\r
+SCSI_Out__RST__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
+SCSI_Out__RST__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
+SCSI_Out__RST__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
+SCSI_Out__RST__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
+SCSI_Out__RST__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
+SCSI_Out__RST__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
+SCSI_Out__RST__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
+SCSI_Out__RST__PS EQU CYREG_PRT0_PS\r
+SCSI_Out__RST__SHIFT EQU 5\r
+SCSI_Out__RST__SLW EQU CYREG_PRT0_SLW\r
+SCSI_Out__SEL__AG EQU CYREG_PRT0_AG\r
+SCSI_Out__SEL__AMUX EQU CYREG_PRT0_AMUX\r
+SCSI_Out__SEL__BIE EQU CYREG_PRT0_BIE\r
+SCSI_Out__SEL__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
+SCSI_Out__SEL__BYP EQU CYREG_PRT0_BYP\r
+SCSI_Out__SEL__CTL EQU CYREG_PRT0_CTL\r
+SCSI_Out__SEL__DM0 EQU CYREG_PRT0_DM0\r
+SCSI_Out__SEL__DM1 EQU CYREG_PRT0_DM1\r
+SCSI_Out__SEL__DM2 EQU CYREG_PRT0_DM2\r
+SCSI_Out__SEL__DR EQU CYREG_PRT0_DR\r
+SCSI_Out__SEL__INP_DIS EQU CYREG_PRT0_INP_DIS\r
+SCSI_Out__SEL__INTTYPE EQU CYREG_PICU0_INTTYPE3\r
+SCSI_Out__SEL__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
+SCSI_Out__SEL__LCD_EN EQU CYREG_PRT0_LCD_EN\r
+SCSI_Out__SEL__MASK EQU 0x08\r
+SCSI_Out__SEL__PC EQU CYREG_PRT0_PC3\r
+SCSI_Out__SEL__PORT EQU 0\r
+SCSI_Out__SEL__PRT EQU CYREG_PRT0_PRT\r
+SCSI_Out__SEL__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
+SCSI_Out__SEL__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
+SCSI_Out__SEL__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
+SCSI_Out__SEL__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
+SCSI_Out__SEL__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
+SCSI_Out__SEL__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
+SCSI_Out__SEL__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
+SCSI_Out__SEL__PS EQU CYREG_PRT0_PS\r
+SCSI_Out__SEL__SHIFT EQU 3\r
+SCSI_Out__SEL__SLW EQU CYREG_PRT0_SLW\r
+SCSI_Out_Bits_Sync_ctrl_reg__0__MASK EQU 0x01\r
+SCSI_Out_Bits_Sync_ctrl_reg__0__POS EQU 0\r
+SCSI_Out_Bits_Sync_ctrl_reg__1__MASK EQU 0x02\r
+SCSI_Out_Bits_Sync_ctrl_reg__1__POS EQU 1\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB08_09_ACTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB08_09_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB08_09_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB08_09_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB08_09_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB08_09_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB08_09_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB08_09_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB08_09_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__2__MASK EQU 0x04\r
+SCSI_Out_Bits_Sync_ctrl_reg__2__POS EQU 2\r
+SCSI_Out_Bits_Sync_ctrl_reg__3__MASK EQU 0x08\r
+SCSI_Out_Bits_Sync_ctrl_reg__3__POS EQU 3\r
+SCSI_Out_Bits_Sync_ctrl_reg__4__MASK EQU 0x10\r
+SCSI_Out_Bits_Sync_ctrl_reg__4__POS EQU 4\r
+SCSI_Out_Bits_Sync_ctrl_reg__5__MASK EQU 0x20\r
+SCSI_Out_Bits_Sync_ctrl_reg__5__POS EQU 5\r
+SCSI_Out_Bits_Sync_ctrl_reg__6__MASK EQU 0x40\r
+SCSI_Out_Bits_Sync_ctrl_reg__6__POS EQU 6\r
+SCSI_Out_Bits_Sync_ctrl_reg__7__MASK EQU 0x80\r
+SCSI_Out_Bits_Sync_ctrl_reg__7__POS EQU 7\r
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB08_ACTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B1_UDB08_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B1_UDB08_ST_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B1_UDB08_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B1_UDB08_ST_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__MASK EQU 0xFF\r
+SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB08_MSK_ACTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB08_MSK_ACTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B1_UDB08_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01\r
+SCSI_Out_Ctl_Sync_ctrl_reg__0__POS EQU 0\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB08_09_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB08_09_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB08_09_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB08_09_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB08_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB08_ST_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB08_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB08_ST_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__MASK EQU 0x01\r
+SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB08_MSK\r
+SCSI_Out_DBx__0__AG EQU CYREG_PRT6_AG\r
+SCSI_Out_DBx__0__AMUX EQU CYREG_PRT6_AMUX\r
+SCSI_Out_DBx__0__BIE EQU CYREG_PRT6_BIE\r
+SCSI_Out_DBx__0__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
+SCSI_Out_DBx__0__BYP EQU CYREG_PRT6_BYP\r
+SCSI_Out_DBx__0__CTL EQU CYREG_PRT6_CTL\r
+SCSI_Out_DBx__0__DM0 EQU CYREG_PRT6_DM0\r
+SCSI_Out_DBx__0__DM1 EQU CYREG_PRT6_DM1\r
+SCSI_Out_DBx__0__DM2 EQU CYREG_PRT6_DM2\r
+SCSI_Out_DBx__0__DR EQU CYREG_PRT6_DR\r
+SCSI_Out_DBx__0__INP_DIS EQU CYREG_PRT6_INP_DIS\r
+SCSI_Out_DBx__0__INTTYPE EQU CYREG_PICU6_INTTYPE3\r
+SCSI_Out_DBx__0__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
+SCSI_Out_DBx__0__LCD_EN EQU CYREG_PRT6_LCD_EN\r
+SCSI_Out_DBx__0__MASK EQU 0x08\r
+SCSI_Out_DBx__0__PC EQU CYREG_PRT6_PC3\r
+SCSI_Out_DBx__0__PORT EQU 6\r
+SCSI_Out_DBx__0__PRT EQU CYREG_PRT6_PRT\r
+SCSI_Out_DBx__0__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
+SCSI_Out_DBx__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
+SCSI_Out_DBx__0__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
+SCSI_Out_DBx__0__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
+SCSI_Out_DBx__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
+SCSI_Out_DBx__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
+SCSI_Out_DBx__0__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
+SCSI_Out_DBx__0__PS EQU CYREG_PRT6_PS\r
+SCSI_Out_DBx__0__SHIFT EQU 3\r
+SCSI_Out_DBx__0__SLW EQU CYREG_PRT6_SLW\r
+SCSI_Out_DBx__1__AG EQU CYREG_PRT6_AG\r
+SCSI_Out_DBx__1__AMUX EQU CYREG_PRT6_AMUX\r
+SCSI_Out_DBx__1__BIE EQU CYREG_PRT6_BIE\r
+SCSI_Out_DBx__1__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
+SCSI_Out_DBx__1__BYP EQU CYREG_PRT6_BYP\r
+SCSI_Out_DBx__1__CTL EQU CYREG_PRT6_CTL\r
+SCSI_Out_DBx__1__DM0 EQU CYREG_PRT6_DM0\r
+SCSI_Out_DBx__1__DM1 EQU CYREG_PRT6_DM1\r
+SCSI_Out_DBx__1__DM2 EQU CYREG_PRT6_DM2\r
+SCSI_Out_DBx__1__DR EQU CYREG_PRT6_DR\r
+SCSI_Out_DBx__1__INP_DIS EQU CYREG_PRT6_INP_DIS\r
+SCSI_Out_DBx__1__INTTYPE EQU CYREG_PICU6_INTTYPE2\r
+SCSI_Out_DBx__1__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
+SCSI_Out_DBx__1__LCD_EN EQU CYREG_PRT6_LCD_EN\r
+SCSI_Out_DBx__1__MASK EQU 0x04\r
+SCSI_Out_DBx__1__PC EQU CYREG_PRT6_PC2\r
+SCSI_Out_DBx__1__PORT EQU 6\r
+SCSI_Out_DBx__1__PRT EQU CYREG_PRT6_PRT\r
+SCSI_Out_DBx__1__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
+SCSI_Out_DBx__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
+SCSI_Out_DBx__1__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
+SCSI_Out_DBx__1__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
+SCSI_Out_DBx__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
+SCSI_Out_DBx__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
+SCSI_Out_DBx__1__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
+SCSI_Out_DBx__1__PS EQU CYREG_PRT6_PS\r
+SCSI_Out_DBx__1__SHIFT EQU 2\r
+SCSI_Out_DBx__1__SLW EQU CYREG_PRT6_SLW\r
+SCSI_Out_DBx__2__AG EQU CYREG_PRT6_AG\r
+SCSI_Out_DBx__2__AMUX EQU CYREG_PRT6_AMUX\r
+SCSI_Out_DBx__2__BIE EQU CYREG_PRT6_BIE\r
+SCSI_Out_DBx__2__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
+SCSI_Out_DBx__2__BYP EQU CYREG_PRT6_BYP\r
+SCSI_Out_DBx__2__CTL EQU CYREG_PRT6_CTL\r
+SCSI_Out_DBx__2__DM0 EQU CYREG_PRT6_DM0\r
+SCSI_Out_DBx__2__DM1 EQU CYREG_PRT6_DM1\r
+SCSI_Out_DBx__2__DM2 EQU CYREG_PRT6_DM2\r
+SCSI_Out_DBx__2__DR EQU CYREG_PRT6_DR\r
+SCSI_Out_DBx__2__INP_DIS EQU CYREG_PRT6_INP_DIS\r
+SCSI_Out_DBx__2__INTTYPE EQU CYREG_PICU6_INTTYPE1\r
+SCSI_Out_DBx__2__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
+SCSI_Out_DBx__2__LCD_EN EQU CYREG_PRT6_LCD_EN\r
+SCSI_Out_DBx__2__MASK EQU 0x02\r
+SCSI_Out_DBx__2__PC EQU CYREG_PRT6_PC1\r
+SCSI_Out_DBx__2__PORT EQU 6\r
+SCSI_Out_DBx__2__PRT EQU CYREG_PRT6_PRT\r
+SCSI_Out_DBx__2__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
+SCSI_Out_DBx__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
+SCSI_Out_DBx__2__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
+SCSI_Out_DBx__2__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
+SCSI_Out_DBx__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
+SCSI_Out_DBx__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
+SCSI_Out_DBx__2__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
+SCSI_Out_DBx__2__PS EQU CYREG_PRT6_PS\r
+SCSI_Out_DBx__2__SHIFT EQU 1\r
+SCSI_Out_DBx__2__SLW EQU CYREG_PRT6_SLW\r
+SCSI_Out_DBx__3__AG EQU CYREG_PRT6_AG\r
+SCSI_Out_DBx__3__AMUX EQU CYREG_PRT6_AMUX\r
+SCSI_Out_DBx__3__BIE EQU CYREG_PRT6_BIE\r
+SCSI_Out_DBx__3__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
+SCSI_Out_DBx__3__BYP EQU CYREG_PRT6_BYP\r
+SCSI_Out_DBx__3__CTL EQU CYREG_PRT6_CTL\r
+SCSI_Out_DBx__3__DM0 EQU CYREG_PRT6_DM0\r
+SCSI_Out_DBx__3__DM1 EQU CYREG_PRT6_DM1\r
+SCSI_Out_DBx__3__DM2 EQU CYREG_PRT6_DM2\r
+SCSI_Out_DBx__3__DR EQU CYREG_PRT6_DR\r
+SCSI_Out_DBx__3__INP_DIS EQU CYREG_PRT6_INP_DIS\r
+SCSI_Out_DBx__3__INTTYPE EQU CYREG_PICU6_INTTYPE0\r
+SCSI_Out_DBx__3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
+SCSI_Out_DBx__3__LCD_EN EQU CYREG_PRT6_LCD_EN\r
+SCSI_Out_DBx__3__MASK EQU 0x01\r
+SCSI_Out_DBx__3__PC EQU CYREG_PRT6_PC0\r
+SCSI_Out_DBx__3__PORT EQU 6\r
+SCSI_Out_DBx__3__PRT EQU CYREG_PRT6_PRT\r
+SCSI_Out_DBx__3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
+SCSI_Out_DBx__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
+SCSI_Out_DBx__3__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
+SCSI_Out_DBx__3__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
+SCSI_Out_DBx__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
+SCSI_Out_DBx__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
+SCSI_Out_DBx__3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
+SCSI_Out_DBx__3__PS EQU CYREG_PRT6_PS\r
+SCSI_Out_DBx__3__SHIFT EQU 0\r
+SCSI_Out_DBx__3__SLW EQU CYREG_PRT6_SLW\r
+SCSI_Out_DBx__4__AG EQU CYREG_PRT4_AG\r
+SCSI_Out_DBx__4__AMUX EQU CYREG_PRT4_AMUX\r
+SCSI_Out_DBx__4__BIE EQU CYREG_PRT4_BIE\r
+SCSI_Out_DBx__4__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
+SCSI_Out_DBx__4__BYP EQU CYREG_PRT4_BYP\r
+SCSI_Out_DBx__4__CTL EQU CYREG_PRT4_CTL\r
+SCSI_Out_DBx__4__DM0 EQU CYREG_PRT4_DM0\r
+SCSI_Out_DBx__4__DM1 EQU CYREG_PRT4_DM1\r
+SCSI_Out_DBx__4__DM2 EQU CYREG_PRT4_DM2\r
+SCSI_Out_DBx__4__DR EQU CYREG_PRT4_DR\r
+SCSI_Out_DBx__4__INP_DIS EQU CYREG_PRT4_INP_DIS\r
+SCSI_Out_DBx__4__INTTYPE EQU CYREG_PICU4_INTTYPE7\r
+SCSI_Out_DBx__4__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
+SCSI_Out_DBx__4__LCD_EN EQU CYREG_PRT4_LCD_EN\r
+SCSI_Out_DBx__4__MASK EQU 0x80\r
+SCSI_Out_DBx__4__PC EQU CYREG_PRT4_PC7\r
+SCSI_Out_DBx__4__PORT EQU 4\r
+SCSI_Out_DBx__4__PRT EQU CYREG_PRT4_PRT\r
+SCSI_Out_DBx__4__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
+SCSI_Out_DBx__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
+SCSI_Out_DBx__4__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
+SCSI_Out_DBx__4__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
+SCSI_Out_DBx__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
+SCSI_Out_DBx__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
+SCSI_Out_DBx__4__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
+SCSI_Out_DBx__4__PS EQU CYREG_PRT4_PS\r
+SCSI_Out_DBx__4__SHIFT EQU 7\r
+SCSI_Out_DBx__4__SLW EQU CYREG_PRT4_SLW\r
+SCSI_Out_DBx__5__AG EQU CYREG_PRT4_AG\r
+SCSI_Out_DBx__5__AMUX EQU CYREG_PRT4_AMUX\r
+SCSI_Out_DBx__5__BIE EQU CYREG_PRT4_BIE\r
+SCSI_Out_DBx__5__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
+SCSI_Out_DBx__5__BYP EQU CYREG_PRT4_BYP\r
+SCSI_Out_DBx__5__CTL EQU CYREG_PRT4_CTL\r
+SCSI_Out_DBx__5__DM0 EQU CYREG_PRT4_DM0\r
+SCSI_Out_DBx__5__DM1 EQU CYREG_PRT4_DM1\r
+SCSI_Out_DBx__5__DM2 EQU CYREG_PRT4_DM2\r
+SCSI_Out_DBx__5__DR EQU CYREG_PRT4_DR\r
+SCSI_Out_DBx__5__INP_DIS EQU CYREG_PRT4_INP_DIS\r
+SCSI_Out_DBx__5__INTTYPE EQU CYREG_PICU4_INTTYPE6\r
+SCSI_Out_DBx__5__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
+SCSI_Out_DBx__5__LCD_EN EQU CYREG_PRT4_LCD_EN\r
+SCSI_Out_DBx__5__MASK EQU 0x40\r
+SCSI_Out_DBx__5__PC EQU CYREG_PRT4_PC6\r
+SCSI_Out_DBx__5__PORT EQU 4\r
+SCSI_Out_DBx__5__PRT EQU CYREG_PRT4_PRT\r
+SCSI_Out_DBx__5__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
+SCSI_Out_DBx__5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
+SCSI_Out_DBx__5__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
+SCSI_Out_DBx__5__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
+SCSI_Out_DBx__5__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
+SCSI_Out_DBx__5__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
+SCSI_Out_DBx__5__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
+SCSI_Out_DBx__5__PS EQU CYREG_PRT4_PS\r
+SCSI_Out_DBx__5__SHIFT EQU 6\r
+SCSI_Out_DBx__5__SLW EQU CYREG_PRT4_SLW\r
+SCSI_Out_DBx__6__AG EQU CYREG_PRT4_AG\r
+SCSI_Out_DBx__6__AMUX EQU CYREG_PRT4_AMUX\r
+SCSI_Out_DBx__6__BIE EQU CYREG_PRT4_BIE\r
+SCSI_Out_DBx__6__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
+SCSI_Out_DBx__6__BYP EQU CYREG_PRT4_BYP\r
+SCSI_Out_DBx__6__CTL EQU CYREG_PRT4_CTL\r
+SCSI_Out_DBx__6__DM0 EQU CYREG_PRT4_DM0\r
+SCSI_Out_DBx__6__DM1 EQU CYREG_PRT4_DM1\r
+SCSI_Out_DBx__6__DM2 EQU CYREG_PRT4_DM2\r
+SCSI_Out_DBx__6__DR EQU CYREG_PRT4_DR\r
+SCSI_Out_DBx__6__INP_DIS EQU CYREG_PRT4_INP_DIS\r
+SCSI_Out_DBx__6__INTTYPE EQU CYREG_PICU4_INTTYPE5\r
+SCSI_Out_DBx__6__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
+SCSI_Out_DBx__6__LCD_EN EQU CYREG_PRT4_LCD_EN\r
+SCSI_Out_DBx__6__MASK EQU 0x20\r
+SCSI_Out_DBx__6__PC EQU CYREG_PRT4_PC5\r
+SCSI_Out_DBx__6__PORT EQU 4\r
+SCSI_Out_DBx__6__PRT EQU CYREG_PRT4_PRT\r
+SCSI_Out_DBx__6__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
+SCSI_Out_DBx__6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
+SCSI_Out_DBx__6__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
+SCSI_Out_DBx__6__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
+SCSI_Out_DBx__6__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
+SCSI_Out_DBx__6__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
+SCSI_Out_DBx__6__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
+SCSI_Out_DBx__6__PS EQU CYREG_PRT4_PS\r
+SCSI_Out_DBx__6__SHIFT EQU 5\r
+SCSI_Out_DBx__6__SLW EQU CYREG_PRT4_SLW\r
+SCSI_Out_DBx__7__AG EQU CYREG_PRT4_AG\r
+SCSI_Out_DBx__7__AMUX EQU CYREG_PRT4_AMUX\r
+SCSI_Out_DBx__7__BIE EQU CYREG_PRT4_BIE\r
+SCSI_Out_DBx__7__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
+SCSI_Out_DBx__7__BYP EQU CYREG_PRT4_BYP\r
+SCSI_Out_DBx__7__CTL EQU CYREG_PRT4_CTL\r
+SCSI_Out_DBx__7__DM0 EQU CYREG_PRT4_DM0\r
+SCSI_Out_DBx__7__DM1 EQU CYREG_PRT4_DM1\r
+SCSI_Out_DBx__7__DM2 EQU CYREG_PRT4_DM2\r
+SCSI_Out_DBx__7__DR EQU CYREG_PRT4_DR\r
+SCSI_Out_DBx__7__INP_DIS EQU CYREG_PRT4_INP_DIS\r
+SCSI_Out_DBx__7__INTTYPE EQU CYREG_PICU4_INTTYPE4\r
+SCSI_Out_DBx__7__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
+SCSI_Out_DBx__7__LCD_EN EQU CYREG_PRT4_LCD_EN\r
+SCSI_Out_DBx__7__MASK EQU 0x10\r
+SCSI_Out_DBx__7__PC EQU CYREG_PRT4_PC4\r
+SCSI_Out_DBx__7__PORT EQU 4\r
+SCSI_Out_DBx__7__PRT EQU CYREG_PRT4_PRT\r
+SCSI_Out_DBx__7__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
+SCSI_Out_DBx__7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
+SCSI_Out_DBx__7__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
+SCSI_Out_DBx__7__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
+SCSI_Out_DBx__7__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
+SCSI_Out_DBx__7__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
+SCSI_Out_DBx__7__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
+SCSI_Out_DBx__7__PS EQU CYREG_PRT4_PS\r
+SCSI_Out_DBx__7__SHIFT EQU 4\r
+SCSI_Out_DBx__7__SLW EQU CYREG_PRT4_SLW\r
+SCSI_Out_DBx__DB0__AG EQU CYREG_PRT6_AG\r
+SCSI_Out_DBx__DB0__AMUX EQU CYREG_PRT6_AMUX\r
+SCSI_Out_DBx__DB0__BIE EQU CYREG_PRT6_BIE\r
+SCSI_Out_DBx__DB0__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
+SCSI_Out_DBx__DB0__BYP EQU CYREG_PRT6_BYP\r
+SCSI_Out_DBx__DB0__CTL EQU CYREG_PRT6_CTL\r
+SCSI_Out_DBx__DB0__DM0 EQU CYREG_PRT6_DM0\r
+SCSI_Out_DBx__DB0__DM1 EQU CYREG_PRT6_DM1\r
+SCSI_Out_DBx__DB0__DM2 EQU CYREG_PRT6_DM2\r
+SCSI_Out_DBx__DB0__DR EQU CYREG_PRT6_DR\r
+SCSI_Out_DBx__DB0__INP_DIS EQU CYREG_PRT6_INP_DIS\r
+SCSI_Out_DBx__DB0__INTTYPE EQU CYREG_PICU6_INTTYPE3\r
+SCSI_Out_DBx__DB0__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
+SCSI_Out_DBx__DB0__LCD_EN EQU CYREG_PRT6_LCD_EN\r
+SCSI_Out_DBx__DB0__MASK EQU 0x08\r
+SCSI_Out_DBx__DB0__PC EQU CYREG_PRT6_PC3\r
+SCSI_Out_DBx__DB0__PORT EQU 6\r
+SCSI_Out_DBx__DB0__PRT EQU CYREG_PRT6_PRT\r
+SCSI_Out_DBx__DB0__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
+SCSI_Out_DBx__DB0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
+SCSI_Out_DBx__DB0__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
+SCSI_Out_DBx__DB0__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
+SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
+SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
+SCSI_Out_DBx__DB0__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
+SCSI_Out_DBx__DB0__PS EQU CYREG_PRT6_PS\r
+SCSI_Out_DBx__DB0__SHIFT EQU 3\r
+SCSI_Out_DBx__DB0__SLW EQU CYREG_PRT6_SLW\r
+SCSI_Out_DBx__DB1__AG EQU CYREG_PRT6_AG\r
+SCSI_Out_DBx__DB1__AMUX EQU CYREG_PRT6_AMUX\r
+SCSI_Out_DBx__DB1__BIE EQU CYREG_PRT6_BIE\r
+SCSI_Out_DBx__DB1__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
+SCSI_Out_DBx__DB1__BYP EQU CYREG_PRT6_BYP\r
+SCSI_Out_DBx__DB1__CTL EQU CYREG_PRT6_CTL\r
+SCSI_Out_DBx__DB1__DM0 EQU CYREG_PRT6_DM0\r
+SCSI_Out_DBx__DB1__DM1 EQU CYREG_PRT6_DM1\r
+SCSI_Out_DBx__DB1__DM2 EQU CYREG_PRT6_DM2\r
+SCSI_Out_DBx__DB1__DR EQU CYREG_PRT6_DR\r
+SCSI_Out_DBx__DB1__INP_DIS EQU CYREG_PRT6_INP_DIS\r
+SCSI_Out_DBx__DB1__INTTYPE EQU CYREG_PICU6_INTTYPE2\r
+SCSI_Out_DBx__DB1__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
+SCSI_Out_DBx__DB1__LCD_EN EQU CYREG_PRT6_LCD_EN\r
+SCSI_Out_DBx__DB1__MASK EQU 0x04\r
+SCSI_Out_DBx__DB1__PC EQU CYREG_PRT6_PC2\r
+SCSI_Out_DBx__DB1__PORT EQU 6\r
+SCSI_Out_DBx__DB1__PRT EQU CYREG_PRT6_PRT\r
+SCSI_Out_DBx__DB1__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
+SCSI_Out_DBx__DB1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
+SCSI_Out_DBx__DB1__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
+SCSI_Out_DBx__DB1__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
+SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
+SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
+SCSI_Out_DBx__DB1__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
+SCSI_Out_DBx__DB1__PS EQU CYREG_PRT6_PS\r
+SCSI_Out_DBx__DB1__SHIFT EQU 2\r
+SCSI_Out_DBx__DB1__SLW EQU CYREG_PRT6_SLW\r
+SCSI_Out_DBx__DB2__AG EQU CYREG_PRT6_AG\r
+SCSI_Out_DBx__DB2__AMUX EQU CYREG_PRT6_AMUX\r
+SCSI_Out_DBx__DB2__BIE EQU CYREG_PRT6_BIE\r
+SCSI_Out_DBx__DB2__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
+SCSI_Out_DBx__DB2__BYP EQU CYREG_PRT6_BYP\r
+SCSI_Out_DBx__DB2__CTL EQU CYREG_PRT6_CTL\r
+SCSI_Out_DBx__DB2__DM0 EQU CYREG_PRT6_DM0\r
+SCSI_Out_DBx__DB2__DM1 EQU CYREG_PRT6_DM1\r
+SCSI_Out_DBx__DB2__DM2 EQU CYREG_PRT6_DM2\r
+SCSI_Out_DBx__DB2__DR EQU CYREG_PRT6_DR\r
+SCSI_Out_DBx__DB2__INP_DIS EQU CYREG_PRT6_INP_DIS\r
+SCSI_Out_DBx__DB2__INTTYPE EQU CYREG_PICU6_INTTYPE1\r
+SCSI_Out_DBx__DB2__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
+SCSI_Out_DBx__DB2__LCD_EN EQU CYREG_PRT6_LCD_EN\r
+SCSI_Out_DBx__DB2__MASK EQU 0x02\r
+SCSI_Out_DBx__DB2__PC EQU CYREG_PRT6_PC1\r
+SCSI_Out_DBx__DB2__PORT EQU 6\r
+SCSI_Out_DBx__DB2__PRT EQU CYREG_PRT6_PRT\r
+SCSI_Out_DBx__DB2__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
+SCSI_Out_DBx__DB2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
+SCSI_Out_DBx__DB2__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
+SCSI_Out_DBx__DB2__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
+SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
+SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
+SCSI_Out_DBx__DB2__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
+SCSI_Out_DBx__DB2__PS EQU CYREG_PRT6_PS\r
+SCSI_Out_DBx__DB2__SHIFT EQU 1\r
+SCSI_Out_DBx__DB2__SLW EQU CYREG_PRT6_SLW\r
+SCSI_Out_DBx__DB3__AG EQU CYREG_PRT6_AG\r
+SCSI_Out_DBx__DB3__AMUX EQU CYREG_PRT6_AMUX\r
+SCSI_Out_DBx__DB3__BIE EQU CYREG_PRT6_BIE\r
+SCSI_Out_DBx__DB3__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
+SCSI_Out_DBx__DB3__BYP EQU CYREG_PRT6_BYP\r
+SCSI_Out_DBx__DB3__CTL EQU CYREG_PRT6_CTL\r
+SCSI_Out_DBx__DB3__DM0 EQU CYREG_PRT6_DM0\r
+SCSI_Out_DBx__DB3__DM1 EQU CYREG_PRT6_DM1\r
+SCSI_Out_DBx__DB3__DM2 EQU CYREG_PRT6_DM2\r
+SCSI_Out_DBx__DB3__DR EQU CYREG_PRT6_DR\r
+SCSI_Out_DBx__DB3__INP_DIS EQU CYREG_PRT6_INP_DIS\r
+SCSI_Out_DBx__DB3__INTTYPE EQU CYREG_PICU6_INTTYPE0\r
+SCSI_Out_DBx__DB3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
+SCSI_Out_DBx__DB3__LCD_EN EQU CYREG_PRT6_LCD_EN\r
+SCSI_Out_DBx__DB3__MASK EQU 0x01\r
+SCSI_Out_DBx__DB3__PC EQU CYREG_PRT6_PC0\r
+SCSI_Out_DBx__DB3__PORT EQU 6\r
+SCSI_Out_DBx__DB3__PRT EQU CYREG_PRT6_PRT\r
+SCSI_Out_DBx__DB3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
+SCSI_Out_DBx__DB3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
+SCSI_Out_DBx__DB3__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
+SCSI_Out_DBx__DB3__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
+SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
+SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
+SCSI_Out_DBx__DB3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
+SCSI_Out_DBx__DB3__PS EQU CYREG_PRT6_PS\r
+SCSI_Out_DBx__DB3__SHIFT EQU 0\r
+SCSI_Out_DBx__DB3__SLW EQU CYREG_PRT6_SLW\r
+SCSI_Out_DBx__DB4__AG EQU CYREG_PRT4_AG\r
+SCSI_Out_DBx__DB4__AMUX EQU CYREG_PRT4_AMUX\r
+SCSI_Out_DBx__DB4__BIE EQU CYREG_PRT4_BIE\r
+SCSI_Out_DBx__DB4__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
+SCSI_Out_DBx__DB4__BYP EQU CYREG_PRT4_BYP\r
+SCSI_Out_DBx__DB4__CTL EQU CYREG_PRT4_CTL\r
+SCSI_Out_DBx__DB4__DM0 EQU CYREG_PRT4_DM0\r
+SCSI_Out_DBx__DB4__DM1 EQU CYREG_PRT4_DM1\r
+SCSI_Out_DBx__DB4__DM2 EQU CYREG_PRT4_DM2\r
+SCSI_Out_DBx__DB4__DR EQU CYREG_PRT4_DR\r
+SCSI_Out_DBx__DB4__INP_DIS EQU CYREG_PRT4_INP_DIS\r
+SCSI_Out_DBx__DB4__INTTYPE EQU CYREG_PICU4_INTTYPE7\r
+SCSI_Out_DBx__DB4__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
+SCSI_Out_DBx__DB4__LCD_EN EQU CYREG_PRT4_LCD_EN\r
+SCSI_Out_DBx__DB4__MASK EQU 0x80\r
+SCSI_Out_DBx__DB4__PC EQU CYREG_PRT4_PC7\r
+SCSI_Out_DBx__DB4__PORT EQU 4\r
+SCSI_Out_DBx__DB4__PRT EQU CYREG_PRT4_PRT\r
+SCSI_Out_DBx__DB4__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
+SCSI_Out_DBx__DB4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
+SCSI_Out_DBx__DB4__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
+SCSI_Out_DBx__DB4__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
+SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
+SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
+SCSI_Out_DBx__DB4__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
+SCSI_Out_DBx__DB4__PS EQU CYREG_PRT4_PS\r
+SCSI_Out_DBx__DB4__SHIFT EQU 7\r
+SCSI_Out_DBx__DB4__SLW EQU CYREG_PRT4_SLW\r
+SCSI_Out_DBx__DB5__AG EQU CYREG_PRT4_AG\r
+SCSI_Out_DBx__DB5__AMUX EQU CYREG_PRT4_AMUX\r
+SCSI_Out_DBx__DB5__BIE EQU CYREG_PRT4_BIE\r
+SCSI_Out_DBx__DB5__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
+SCSI_Out_DBx__DB5__BYP EQU CYREG_PRT4_BYP\r
+SCSI_Out_DBx__DB5__CTL EQU CYREG_PRT4_CTL\r
+SCSI_Out_DBx__DB5__DM0 EQU CYREG_PRT4_DM0\r
+SCSI_Out_DBx__DB5__DM1 EQU CYREG_PRT4_DM1\r
+SCSI_Out_DBx__DB5__DM2 EQU CYREG_PRT4_DM2\r
+SCSI_Out_DBx__DB5__DR EQU CYREG_PRT4_DR\r
+SCSI_Out_DBx__DB5__INP_DIS EQU CYREG_PRT4_INP_DIS\r
+SCSI_Out_DBx__DB5__INTTYPE EQU CYREG_PICU4_INTTYPE6\r
+SCSI_Out_DBx__DB5__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
+SCSI_Out_DBx__DB5__LCD_EN EQU CYREG_PRT4_LCD_EN\r
+SCSI_Out_DBx__DB5__MASK EQU 0x40\r
+SCSI_Out_DBx__DB5__PC EQU CYREG_PRT4_PC6\r
+SCSI_Out_DBx__DB5__PORT EQU 4\r
+SCSI_Out_DBx__DB5__PRT EQU CYREG_PRT4_PRT\r
+SCSI_Out_DBx__DB5__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
+SCSI_Out_DBx__DB5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
+SCSI_Out_DBx__DB5__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
+SCSI_Out_DBx__DB5__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
+SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
+SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
+SCSI_Out_DBx__DB5__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
+SCSI_Out_DBx__DB5__PS EQU CYREG_PRT4_PS\r
+SCSI_Out_DBx__DB5__SHIFT EQU 6\r
+SCSI_Out_DBx__DB5__SLW EQU CYREG_PRT4_SLW\r
+SCSI_Out_DBx__DB6__AG EQU CYREG_PRT4_AG\r
+SCSI_Out_DBx__DB6__AMUX EQU CYREG_PRT4_AMUX\r
+SCSI_Out_DBx__DB6__BIE EQU CYREG_PRT4_BIE\r
+SCSI_Out_DBx__DB6__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
+SCSI_Out_DBx__DB6__BYP EQU CYREG_PRT4_BYP\r
+SCSI_Out_DBx__DB6__CTL EQU CYREG_PRT4_CTL\r
+SCSI_Out_DBx__DB6__DM0 EQU CYREG_PRT4_DM0\r
+SCSI_Out_DBx__DB6__DM1 EQU CYREG_PRT4_DM1\r
+SCSI_Out_DBx__DB6__DM2 EQU CYREG_PRT4_DM2\r
+SCSI_Out_DBx__DB6__DR EQU CYREG_PRT4_DR\r
+SCSI_Out_DBx__DB6__INP_DIS EQU CYREG_PRT4_INP_DIS\r
+SCSI_Out_DBx__DB6__INTTYPE EQU CYREG_PICU4_INTTYPE5\r
+SCSI_Out_DBx__DB6__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
+SCSI_Out_DBx__DB6__LCD_EN EQU CYREG_PRT4_LCD_EN\r
+SCSI_Out_DBx__DB6__MASK EQU 0x20\r
+SCSI_Out_DBx__DB6__PC EQU CYREG_PRT4_PC5\r
+SCSI_Out_DBx__DB6__PORT EQU 4\r
+SCSI_Out_DBx__DB6__PRT EQU CYREG_PRT4_PRT\r
+SCSI_Out_DBx__DB6__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
+SCSI_Out_DBx__DB6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
+SCSI_Out_DBx__DB6__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
+SCSI_Out_DBx__DB6__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
+SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
+SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
+SCSI_Out_DBx__DB6__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
+SCSI_Out_DBx__DB6__PS EQU CYREG_PRT4_PS\r
+SCSI_Out_DBx__DB6__SHIFT EQU 5\r
+SCSI_Out_DBx__DB6__SLW EQU CYREG_PRT4_SLW\r
+SCSI_Out_DBx__DB7__AG EQU CYREG_PRT4_AG\r
+SCSI_Out_DBx__DB7__AMUX EQU CYREG_PRT4_AMUX\r
+SCSI_Out_DBx__DB7__BIE EQU CYREG_PRT4_BIE\r
+SCSI_Out_DBx__DB7__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
+SCSI_Out_DBx__DB7__BYP EQU CYREG_PRT4_BYP\r
+SCSI_Out_DBx__DB7__CTL EQU CYREG_PRT4_CTL\r
+SCSI_Out_DBx__DB7__DM0 EQU CYREG_PRT4_DM0\r
+SCSI_Out_DBx__DB7__DM1 EQU CYREG_PRT4_DM1\r
+SCSI_Out_DBx__DB7__DM2 EQU CYREG_PRT4_DM2\r
+SCSI_Out_DBx__DB7__DR EQU CYREG_PRT4_DR\r
+SCSI_Out_DBx__DB7__INP_DIS EQU CYREG_PRT4_INP_DIS\r
+SCSI_Out_DBx__DB7__INTTYPE EQU CYREG_PICU4_INTTYPE4\r
+SCSI_Out_DBx__DB7__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
+SCSI_Out_DBx__DB7__LCD_EN EQU CYREG_PRT4_LCD_EN\r
+SCSI_Out_DBx__DB7__MASK EQU 0x10\r
+SCSI_Out_DBx__DB7__PC EQU CYREG_PRT4_PC4\r
+SCSI_Out_DBx__DB7__PORT EQU 4\r
+SCSI_Out_DBx__DB7__PRT EQU CYREG_PRT4_PRT\r
+SCSI_Out_DBx__DB7__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
+SCSI_Out_DBx__DB7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
+SCSI_Out_DBx__DB7__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
+SCSI_Out_DBx__DB7__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
+SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
+SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
+SCSI_Out_DBx__DB7__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
+SCSI_Out_DBx__DB7__PS EQU CYREG_PRT4_PS\r
+SCSI_Out_DBx__DB7__SHIFT EQU 4\r
+SCSI_Out_DBx__DB7__SLW EQU CYREG_PRT4_SLW\r
+\r
+/* SCSI_Parity_Error */\r
+SCSI_Parity_Error_sts_sts_reg__0__MASK EQU 0x01\r
+SCSI_Parity_Error_sts_sts_reg__0__POS EQU 0\r
+SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB01_02_ACTL\r
+SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB01_02_ST\r
+SCSI_Parity_Error_sts_sts_reg__MASK EQU 0x01\r
+SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB01_MSK\r
+SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB01_ACTL\r
+SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB01_ST\r
+\r
+/* SCSI_RST_ISR */\r
+SCSI_RST_ISR__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
+SCSI_RST_ISR__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
+SCSI_RST_ISR__INTC_MASK EQU 0x02\r
+SCSI_RST_ISR__INTC_NUMBER EQU 1\r
+SCSI_RST_ISR__INTC_PRIOR_NUM EQU 7\r
+SCSI_RST_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_1\r
+SCSI_RST_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
+SCSI_RST_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
+\r
+/* SCSI_RX_DMA */\r
+SCSI_RX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0\r
+SCSI_RX_DMA__DRQ_NUMBER EQU 0\r
+SCSI_RX_DMA__NUMBEROF_TDS EQU 0\r
+SCSI_RX_DMA__PRIORITY EQU 2\r
+SCSI_RX_DMA__TERMIN_EN EQU 0\r
+SCSI_RX_DMA__TERMIN_SEL EQU 0\r
+SCSI_RX_DMA__TERMOUT0_EN EQU 1\r
+SCSI_RX_DMA__TERMOUT0_SEL EQU 0\r
+SCSI_RX_DMA__TERMOUT1_EN EQU 0\r
+SCSI_RX_DMA__TERMOUT1_SEL EQU 0\r
+SCSI_RX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
+SCSI_RX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
+SCSI_RX_DMA_COMPLETE__INTC_MASK EQU 0x04\r
+SCSI_RX_DMA_COMPLETE__INTC_NUMBER EQU 2\r
+SCSI_RX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7\r
+SCSI_RX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_2\r
+SCSI_RX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
+SCSI_RX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
+\r
+/* SCSI_SEL_ISR */\r
+SCSI_SEL_ISR__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
+SCSI_SEL_ISR__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
+SCSI_SEL_ISR__INTC_MASK EQU 0x08\r
+SCSI_SEL_ISR__INTC_NUMBER EQU 3\r
+SCSI_SEL_ISR__INTC_PRIOR_NUM EQU 7\r
+SCSI_SEL_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_3\r
+SCSI_SEL_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
+SCSI_SEL_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
+\r
+/* SCSI_TX_DMA */\r
+SCSI_TX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0\r
+SCSI_TX_DMA__DRQ_NUMBER EQU 1\r
+SCSI_TX_DMA__NUMBEROF_TDS EQU 0\r
+SCSI_TX_DMA__PRIORITY EQU 2\r
+SCSI_TX_DMA__TERMIN_EN EQU 0\r
+SCSI_TX_DMA__TERMIN_SEL EQU 0\r
+SCSI_TX_DMA__TERMOUT0_EN EQU 1\r
+SCSI_TX_DMA__TERMOUT0_SEL EQU 1\r
+SCSI_TX_DMA__TERMOUT1_EN EQU 0\r
+SCSI_TX_DMA__TERMOUT1_SEL EQU 0\r
+SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
+SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
+SCSI_TX_DMA_COMPLETE__INTC_MASK EQU 0x10\r
+SCSI_TX_DMA_COMPLETE__INTC_NUMBER EQU 4\r
+SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7\r
+SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_4\r
+SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
+SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
+\r
+/* SDCard_BSPIM */\r
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL\r
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB04_05_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB04_05_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB04_05_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB04_05_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB04_05_MSK\r
+SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB04_05_MSK\r
+SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB04_05_MSK\r
+SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB04_05_MSK\r
+SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL\r
+SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB04_CTL\r
+SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB04_ST_CTL\r
+SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB04_CTL\r
+SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB04_ST_CTL\r
+SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL\r
+SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL\r
+SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB04_MSK\r
+SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL\r
+SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB04_05_ST\r
+SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB04_MSK\r
+SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL\r
+SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB04_ST_CTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB04_ST_CTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB04_ST\r
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB08_09_ACTL\r
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB08_09_ST\r
+SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10\r
+SDCard_BSPIM_RxStsReg__4__POS EQU 4\r
+SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20\r
+SDCard_BSPIM_RxStsReg__5__POS EQU 5\r
+SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40\r
+SDCard_BSPIM_RxStsReg__6__POS EQU 6\r
+SDCard_BSPIM_RxStsReg__MASK EQU 0x70\r
+SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB08_MSK\r
+SDCard_BSPIM_RxStsReg__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB08_MSK_ACTL\r
+SDCard_BSPIM_RxStsReg__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB08_MSK_ACTL\r
+SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB08_ACTL\r
+SDCard_BSPIM_RxStsReg__STATUS_CNT_REG EQU CYREG_B1_UDB08_ST_CTL\r
+SDCard_BSPIM_RxStsReg__STATUS_CONTROL_REG EQU CYREG_B1_UDB08_ST_CTL\r
+SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB08_ST\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB04_05_A0\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB04_05_A1\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B1_UDB04_05_D0\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B1_UDB04_05_D1\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B1_UDB04_05_F0\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B1_UDB04_05_F1\r
+SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B1_UDB04_A0_A1\r
+SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B1_UDB04_A0\r
+SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B1_UDB04_A1\r
+SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B1_UDB04_D0_D1\r
+SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B1_UDB04_D0\r
+SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B1_UDB04_D1\r
+SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL\r
+SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B1_UDB04_F0_F1\r
+SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B1_UDB04_F0\r
+SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B1_UDB04_F1\r
+SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL\r
+SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL\r
+SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01\r
+SDCard_BSPIM_TxStsReg__0__POS EQU 0\r
+SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02\r
+SDCard_BSPIM_TxStsReg__1__POS EQU 1\r
+SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL\r
+SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST\r
+SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04\r
+SDCard_BSPIM_TxStsReg__2__POS EQU 2\r
+SDCard_BSPIM_TxStsReg__3__MASK EQU 0x08\r
+SDCard_BSPIM_TxStsReg__3__POS EQU 3\r
+SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10\r
+SDCard_BSPIM_TxStsReg__4__POS EQU 4\r
+SDCard_BSPIM_TxStsReg__MASK EQU 0x1F\r
+SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB07_MSK\r
+SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL\r
+SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB07_ST\r
+\r
+/* SD_CD */\r
+SD_CD__0__INTTYPE EQU CYREG_PICU3_INTTYPE6\r
+SD_CD__0__MASK EQU 0x40\r
+SD_CD__0__PC EQU CYREG_PRT3_PC6\r
+SD_CD__0__PORT EQU 3\r
+SD_CD__0__SHIFT EQU 6\r
+SD_CD__AG EQU CYREG_PRT3_AG\r
+SD_CD__AMUX EQU CYREG_PRT3_AMUX\r
+SD_CD__BIE EQU CYREG_PRT3_BIE\r
+SD_CD__BIT_MASK EQU CYREG_PRT3_BIT_MASK\r
+SD_CD__BYP EQU CYREG_PRT3_BYP\r
+SD_CD__CTL EQU CYREG_PRT3_CTL\r
+SD_CD__DM0 EQU CYREG_PRT3_DM0\r
+SD_CD__DM1 EQU CYREG_PRT3_DM1\r
+SD_CD__DM2 EQU CYREG_PRT3_DM2\r
+SD_CD__DR EQU CYREG_PRT3_DR\r
+SD_CD__INP_DIS EQU CYREG_PRT3_INP_DIS\r
+SD_CD__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE\r
+SD_CD__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG\r
+SD_CD__LCD_EN EQU CYREG_PRT3_LCD_EN\r
+SD_CD__MASK EQU 0x40\r
+SD_CD__PORT EQU 3\r
+SD_CD__PRT EQU CYREG_PRT3_PRT\r
+SD_CD__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL\r
+SD_CD__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN\r
+SD_CD__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0\r
+SD_CD__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1\r
+SD_CD__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0\r
+SD_CD__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1\r
+SD_CD__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT\r
+SD_CD__PS EQU CYREG_PRT3_PS\r
+SD_CD__SHIFT EQU 6\r
+SD_CD__SLW EQU CYREG_PRT3_SLW\r
+\r
+/* SD_CS */\r
+SD_CS__0__INTTYPE EQU CYREG_PICU3_INTTYPE4\r
+SD_CS__0__MASK EQU 0x10\r
+SD_CS__0__PC EQU CYREG_PRT3_PC4\r
+SD_CS__0__PORT EQU 3\r
+SD_CS__0__SHIFT EQU 4\r
+SD_CS__AG EQU CYREG_PRT3_AG\r
+SD_CS__AMUX EQU CYREG_PRT3_AMUX\r
+SD_CS__BIE EQU CYREG_PRT3_BIE\r
+SD_CS__BIT_MASK EQU CYREG_PRT3_BIT_MASK\r
+SD_CS__BYP EQU CYREG_PRT3_BYP\r
+SD_CS__CTL EQU CYREG_PRT3_CTL\r
+SD_CS__DM0 EQU CYREG_PRT3_DM0\r
+SD_CS__DM1 EQU CYREG_PRT3_DM1\r
+SD_CS__DM2 EQU CYREG_PRT3_DM2\r
+SD_CS__DR EQU CYREG_PRT3_DR\r
+SD_CS__INP_DIS EQU CYREG_PRT3_INP_DIS\r
+SD_CS__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE\r
+SD_CS__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG\r
+SD_CS__LCD_EN EQU CYREG_PRT3_LCD_EN\r
+SD_CS__MASK EQU 0x10\r
+SD_CS__PORT EQU 3\r
+SD_CS__PRT EQU CYREG_PRT3_PRT\r
+SD_CS__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL\r
+SD_CS__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN\r
+SD_CS__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0\r
+SD_CS__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1\r
+SD_CS__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0\r
+SD_CS__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1\r
+SD_CS__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT\r
+SD_CS__PS EQU CYREG_PRT3_PS\r
+SD_CS__SHIFT EQU 4\r
+SD_CS__SLW EQU CYREG_PRT3_SLW\r
+\r
+/* SD_DAT1 */\r
+SD_DAT1__0__INTTYPE EQU CYREG_PICU3_INTTYPE0\r
+SD_DAT1__0__MASK EQU 0x01\r
+SD_DAT1__0__PC EQU CYREG_PRT3_PC0\r
+SD_DAT1__0__PORT EQU 3\r
+SD_DAT1__0__SHIFT EQU 0\r
+SD_DAT1__AG EQU CYREG_PRT3_AG\r
+SD_DAT1__AMUX EQU CYREG_PRT3_AMUX\r
+SD_DAT1__BIE EQU CYREG_PRT3_BIE\r
+SD_DAT1__BIT_MASK EQU CYREG_PRT3_BIT_MASK\r
+SD_DAT1__BYP EQU CYREG_PRT3_BYP\r
+SD_DAT1__CTL EQU CYREG_PRT3_CTL\r
+SD_DAT1__DM0 EQU CYREG_PRT3_DM0\r
+SD_DAT1__DM1 EQU CYREG_PRT3_DM1\r
+SD_DAT1__DM2 EQU CYREG_PRT3_DM2\r
+SD_DAT1__DR EQU CYREG_PRT3_DR\r
+SD_DAT1__INP_DIS EQU CYREG_PRT3_INP_DIS\r
+SD_DAT1__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE\r
+SD_DAT1__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG\r
+SD_DAT1__LCD_EN EQU CYREG_PRT3_LCD_EN\r
+SD_DAT1__MASK EQU 0x01\r
+SD_DAT1__PORT EQU 3\r
+SD_DAT1__PRT EQU CYREG_PRT3_PRT\r
+SD_DAT1__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL\r
+SD_DAT1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN\r
+SD_DAT1__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0\r
+SD_DAT1__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1\r
+SD_DAT1__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0\r
+SD_DAT1__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1\r
+SD_DAT1__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT\r
+SD_DAT1__PS EQU CYREG_PRT3_PS\r
+SD_DAT1__SHIFT EQU 0\r
+SD_DAT1__SLW EQU CYREG_PRT3_SLW\r
+\r
+/* SD_DAT2 */\r
+SD_DAT2__0__INTTYPE EQU CYREG_PICU3_INTTYPE5\r
+SD_DAT2__0__MASK EQU 0x20\r
+SD_DAT2__0__PC EQU CYREG_PRT3_PC5\r
+SD_DAT2__0__PORT EQU 3\r
+SD_DAT2__0__SHIFT EQU 5\r
+SD_DAT2__AG EQU CYREG_PRT3_AG\r
+SD_DAT2__AMUX EQU CYREG_PRT3_AMUX\r
+SD_DAT2__BIE EQU CYREG_PRT3_BIE\r
+SD_DAT2__BIT_MASK EQU CYREG_PRT3_BIT_MASK\r
+SD_DAT2__BYP EQU CYREG_PRT3_BYP\r
+SD_DAT2__CTL EQU CYREG_PRT3_CTL\r
+SD_DAT2__DM0 EQU CYREG_PRT3_DM0\r
+SD_DAT2__DM1 EQU CYREG_PRT3_DM1\r
+SD_DAT2__DM2 EQU CYREG_PRT3_DM2\r
+SD_DAT2__DR EQU CYREG_PRT3_DR\r
+SD_DAT2__INP_DIS EQU CYREG_PRT3_INP_DIS\r
+SD_DAT2__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE\r
+SD_DAT2__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG\r
+SD_DAT2__LCD_EN EQU CYREG_PRT3_LCD_EN\r
+SD_DAT2__MASK EQU 0x20\r
+SD_DAT2__PORT EQU 3\r
+SD_DAT2__PRT EQU CYREG_PRT3_PRT\r
+SD_DAT2__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL\r
+SD_DAT2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN\r
+SD_DAT2__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0\r
+SD_DAT2__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1\r
+SD_DAT2__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0\r
+SD_DAT2__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1\r
+SD_DAT2__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT\r
+SD_DAT2__PS EQU CYREG_PRT3_PS\r
+SD_DAT2__SHIFT EQU 5\r
+SD_DAT2__SLW EQU CYREG_PRT3_SLW\r
+\r
+/* SD_Data_Clk */\r
+SD_Data_Clk__CFG0 EQU CYREG_CLKDIST_DCFG0_CFG0\r
+SD_Data_Clk__CFG1 EQU CYREG_CLKDIST_DCFG0_CFG1\r
+SD_Data_Clk__CFG2 EQU CYREG_CLKDIST_DCFG0_CFG2\r
+SD_Data_Clk__CFG2_SRC_SEL_MASK EQU 0x07\r
+SD_Data_Clk__INDEX EQU 0x00\r
+SD_Data_Clk__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2\r
+SD_Data_Clk__PM_ACT_MSK EQU 0x01\r
+SD_Data_Clk__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2\r
+SD_Data_Clk__PM_STBY_MSK EQU 0x01\r
+\r
+/* SD_MISO */\r
+SD_MISO__0__INTTYPE EQU CYREG_PICU3_INTTYPE1\r
+SD_MISO__0__MASK EQU 0x02\r
+SD_MISO__0__PC EQU CYREG_PRT3_PC1\r
+SD_MISO__0__PORT EQU 3\r
+SD_MISO__0__SHIFT EQU 1\r
+SD_MISO__AG EQU CYREG_PRT3_AG\r
+SD_MISO__AMUX EQU CYREG_PRT3_AMUX\r
+SD_MISO__BIE EQU CYREG_PRT3_BIE\r
+SD_MISO__BIT_MASK EQU CYREG_PRT3_BIT_MASK\r
+SD_MISO__BYP EQU CYREG_PRT3_BYP\r
+SD_MISO__CTL EQU CYREG_PRT3_CTL\r
+SD_MISO__DM0 EQU CYREG_PRT3_DM0\r
+SD_MISO__DM1 EQU CYREG_PRT3_DM1\r
+SD_MISO__DM2 EQU CYREG_PRT3_DM2\r
+SD_MISO__DR EQU CYREG_PRT3_DR\r
+SD_MISO__INP_DIS EQU CYREG_PRT3_INP_DIS\r
+SD_MISO__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE\r
+SD_MISO__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG\r
+SD_MISO__LCD_EN EQU CYREG_PRT3_LCD_EN\r
+SD_MISO__MASK EQU 0x02\r
+SD_MISO__PORT EQU 3\r
+SD_MISO__PRT EQU CYREG_PRT3_PRT\r
+SD_MISO__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL\r
+SD_MISO__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN\r
+SD_MISO__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0\r
+SD_MISO__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1\r
+SD_MISO__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0\r
+SD_MISO__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1\r
+SD_MISO__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT\r
+SD_MISO__PS EQU CYREG_PRT3_PS\r
+SD_MISO__SHIFT EQU 1\r
+SD_MISO__SLW EQU CYREG_PRT3_SLW\r
+\r
+/* SD_MOSI */\r
+SD_MOSI__0__INTTYPE EQU CYREG_PICU3_INTTYPE3\r
+SD_MOSI__0__MASK EQU 0x08\r
+SD_MOSI__0__PC EQU CYREG_PRT3_PC3\r
+SD_MOSI__0__PORT EQU 3\r
+SD_MOSI__0__SHIFT EQU 3\r
+SD_MOSI__AG EQU CYREG_PRT3_AG\r
+SD_MOSI__AMUX EQU CYREG_PRT3_AMUX\r
+SD_MOSI__BIE EQU CYREG_PRT3_BIE\r
+SD_MOSI__BIT_MASK EQU CYREG_PRT3_BIT_MASK\r
+SD_MOSI__BYP EQU CYREG_PRT3_BYP\r
+SD_MOSI__CTL EQU CYREG_PRT3_CTL\r
+SD_MOSI__DM0 EQU CYREG_PRT3_DM0\r
+SD_MOSI__DM1 EQU CYREG_PRT3_DM1\r
+SD_MOSI__DM2 EQU CYREG_PRT3_DM2\r
+SD_MOSI__DR EQU CYREG_PRT3_DR\r
+SD_MOSI__INP_DIS EQU CYREG_PRT3_INP_DIS\r
+SD_MOSI__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE\r
+SD_MOSI__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG\r
+SD_MOSI__LCD_EN EQU CYREG_PRT3_LCD_EN\r
+SD_MOSI__MASK EQU 0x08\r
+SD_MOSI__PORT EQU 3\r
+SD_MOSI__PRT EQU CYREG_PRT3_PRT\r
+SD_MOSI__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL\r
+SD_MOSI__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN\r
+SD_MOSI__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0\r
+SD_MOSI__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1\r
+SD_MOSI__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0\r
+SD_MOSI__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1\r
+SD_MOSI__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT\r
+SD_MOSI__PS EQU CYREG_PRT3_PS\r
+SD_MOSI__SHIFT EQU 3\r
+SD_MOSI__SLW EQU CYREG_PRT3_SLW\r
+\r
+/* SD_RX_DMA */\r
+SD_RX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0\r
+SD_RX_DMA__DRQ_NUMBER EQU 2\r
+SD_RX_DMA__NUMBEROF_TDS EQU 0\r
+SD_RX_DMA__PRIORITY EQU 0\r
+SD_RX_DMA__TERMIN_EN EQU 0\r
+SD_RX_DMA__TERMIN_SEL EQU 0\r
+SD_RX_DMA__TERMOUT0_EN EQU 1\r
+SD_RX_DMA__TERMOUT0_SEL EQU 2\r
+SD_RX_DMA__TERMOUT1_EN EQU 0\r
+SD_RX_DMA__TERMOUT1_SEL EQU 0\r
+SD_RX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
+SD_RX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
+SD_RX_DMA_COMPLETE__INTC_MASK EQU 0x20\r
+SD_RX_DMA_COMPLETE__INTC_NUMBER EQU 5\r
+SD_RX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7\r
+SD_RX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_5\r
+SD_RX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
+SD_RX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
+\r
+/* SD_SCK */\r
+SD_SCK__0__INTTYPE EQU CYREG_PICU3_INTTYPE2\r
+SD_SCK__0__MASK EQU 0x04\r
+SD_SCK__0__PC EQU CYREG_PRT3_PC2\r
+SD_SCK__0__PORT EQU 3\r
+SD_SCK__0__SHIFT EQU 2\r
+SD_SCK__AG EQU CYREG_PRT3_AG\r
+SD_SCK__AMUX EQU CYREG_PRT3_AMUX\r
+SD_SCK__BIE EQU CYREG_PRT3_BIE\r
+SD_SCK__BIT_MASK EQU CYREG_PRT3_BIT_MASK\r
+SD_SCK__BYP EQU CYREG_PRT3_BYP\r
+SD_SCK__CTL EQU CYREG_PRT3_CTL\r
+SD_SCK__DM0 EQU CYREG_PRT3_DM0\r
+SD_SCK__DM1 EQU CYREG_PRT3_DM1\r
+SD_SCK__DM2 EQU CYREG_PRT3_DM2\r
+SD_SCK__DR EQU CYREG_PRT3_DR\r
+SD_SCK__INP_DIS EQU CYREG_PRT3_INP_DIS\r
+SD_SCK__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE\r
+SD_SCK__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG\r
+SD_SCK__LCD_EN EQU CYREG_PRT3_LCD_EN\r
+SD_SCK__MASK EQU 0x04\r
+SD_SCK__PORT EQU 3\r
+SD_SCK__PRT EQU CYREG_PRT3_PRT\r
+SD_SCK__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL\r
+SD_SCK__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN\r
+SD_SCK__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0\r
+SD_SCK__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1\r
+SD_SCK__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0\r
+SD_SCK__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1\r
+SD_SCK__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT\r
+SD_SCK__PS EQU CYREG_PRT3_PS\r
+SD_SCK__SHIFT EQU 2\r
+SD_SCK__SLW EQU CYREG_PRT3_SLW\r
+\r
+/* SD_TX_DMA */\r
+SD_TX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0\r
+SD_TX_DMA__DRQ_NUMBER EQU 3\r
+SD_TX_DMA__NUMBEROF_TDS EQU 0\r
+SD_TX_DMA__PRIORITY EQU 1\r
+SD_TX_DMA__TERMIN_EN EQU 0\r
+SD_TX_DMA__TERMIN_SEL EQU 0\r
+SD_TX_DMA__TERMOUT0_EN EQU 1\r
+SD_TX_DMA__TERMOUT0_SEL EQU 3\r
+SD_TX_DMA__TERMOUT1_EN EQU 0\r
+SD_TX_DMA__TERMOUT1_SEL EQU 0\r
+SD_TX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
+SD_TX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
+SD_TX_DMA_COMPLETE__INTC_MASK EQU 0x40\r
+SD_TX_DMA_COMPLETE__INTC_NUMBER EQU 6\r
+SD_TX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7\r
+SD_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_6\r
+SD_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
+SD_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
+\r
+/* USBFS */\r
+USBFS_arb_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
+USBFS_arb_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
+USBFS_arb_int__INTC_MASK EQU 0x400000\r
+USBFS_arb_int__INTC_NUMBER EQU 22\r
+USBFS_arb_int__INTC_PRIOR_NUM EQU 6\r
+USBFS_arb_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_22\r
+USBFS_arb_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
+USBFS_arb_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
+USBFS_bus_reset__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
+USBFS_bus_reset__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
+USBFS_bus_reset__INTC_MASK EQU 0x800000\r
+USBFS_bus_reset__INTC_NUMBER EQU 23\r
+USBFS_bus_reset__INTC_PRIOR_NUM EQU 7\r
+USBFS_bus_reset__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_23\r
+USBFS_bus_reset__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
+USBFS_bus_reset__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
+USBFS_Dm__0__INTTYPE EQU CYREG_PICU15_INTTYPE7\r
+USBFS_Dm__0__MASK EQU 0x80\r
+USBFS_Dm__0__PC EQU CYREG_IO_PC_PRT15_7_6_PC1\r
+USBFS_Dm__0__PORT EQU 15\r
+USBFS_Dm__0__SHIFT EQU 7\r
+USBFS_Dm__AG EQU CYREG_PRT15_AG\r
+USBFS_Dm__AMUX EQU CYREG_PRT15_AMUX\r
+USBFS_Dm__BIE EQU CYREG_PRT15_BIE\r
+USBFS_Dm__BIT_MASK EQU CYREG_PRT15_BIT_MASK\r
+USBFS_Dm__BYP EQU CYREG_PRT15_BYP\r
+USBFS_Dm__CTL EQU CYREG_PRT15_CTL\r
+USBFS_Dm__DM0 EQU CYREG_PRT15_DM0\r
+USBFS_Dm__DM1 EQU CYREG_PRT15_DM1\r
+USBFS_Dm__DM2 EQU CYREG_PRT15_DM2\r
+USBFS_Dm__DR EQU CYREG_PRT15_DR\r
+USBFS_Dm__INP_DIS EQU CYREG_PRT15_INP_DIS\r
+USBFS_Dm__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU15_BASE\r
+USBFS_Dm__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG\r
+USBFS_Dm__LCD_EN EQU CYREG_PRT15_LCD_EN\r
+USBFS_Dm__MASK EQU 0x80\r
+USBFS_Dm__PORT EQU 15\r
+USBFS_Dm__PRT EQU CYREG_PRT15_PRT\r
+USBFS_Dm__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL\r
+USBFS_Dm__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN\r
+USBFS_Dm__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0\r
+USBFS_Dm__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1\r
+USBFS_Dm__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0\r
+USBFS_Dm__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1\r
+USBFS_Dm__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT\r
+USBFS_Dm__PS EQU CYREG_PRT15_PS\r
+USBFS_Dm__SHIFT EQU 7\r
+USBFS_Dm__SLW EQU CYREG_PRT15_SLW\r
+USBFS_Dp__0__INTTYPE EQU CYREG_PICU15_INTTYPE6\r
+USBFS_Dp__0__MASK EQU 0x40\r
+USBFS_Dp__0__PC EQU CYREG_IO_PC_PRT15_7_6_PC0\r
+USBFS_Dp__0__PORT EQU 15\r
+USBFS_Dp__0__SHIFT EQU 6\r
+USBFS_Dp__AG EQU CYREG_PRT15_AG\r
+USBFS_Dp__AMUX EQU CYREG_PRT15_AMUX\r
+USBFS_Dp__BIE EQU CYREG_PRT15_BIE\r
+USBFS_Dp__BIT_MASK EQU CYREG_PRT15_BIT_MASK\r
+USBFS_Dp__BYP EQU CYREG_PRT15_BYP\r
+USBFS_Dp__CTL EQU CYREG_PRT15_CTL\r
+USBFS_Dp__DM0 EQU CYREG_PRT15_DM0\r
+USBFS_Dp__DM1 EQU CYREG_PRT15_DM1\r
+USBFS_Dp__DM2 EQU CYREG_PRT15_DM2\r
+USBFS_Dp__DR EQU CYREG_PRT15_DR\r
+USBFS_Dp__INP_DIS EQU CYREG_PRT15_INP_DIS\r
+USBFS_Dp__INTSTAT EQU CYREG_PICU15_INTSTAT\r
+USBFS_Dp__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU15_BASE\r
+USBFS_Dp__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG\r
+USBFS_Dp__LCD_EN EQU CYREG_PRT15_LCD_EN\r
+USBFS_Dp__MASK EQU 0x40\r
+USBFS_Dp__PORT EQU 15\r
+USBFS_Dp__PRT EQU CYREG_PRT15_PRT\r
+USBFS_Dp__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL\r
+USBFS_Dp__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN\r
+USBFS_Dp__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0\r
+USBFS_Dp__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1\r
+USBFS_Dp__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0\r
+USBFS_Dp__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1\r
+USBFS_Dp__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT\r
+USBFS_Dp__PS EQU CYREG_PRT15_PS\r
+USBFS_Dp__SHIFT EQU 6\r
+USBFS_Dp__SLW EQU CYREG_PRT15_SLW\r
+USBFS_Dp__SNAP EQU CYREG_PICU_15_SNAP_15\r
+USBFS_dp_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
+USBFS_dp_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
+USBFS_dp_int__INTC_MASK EQU 0x1000\r
+USBFS_dp_int__INTC_NUMBER EQU 12\r
+USBFS_dp_int__INTC_PRIOR_NUM EQU 7\r
+USBFS_dp_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_12\r
+USBFS_dp_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
+USBFS_dp_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
+USBFS_ep_0__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
+USBFS_ep_0__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
+USBFS_ep_0__INTC_MASK EQU 0x1000000\r
+USBFS_ep_0__INTC_NUMBER EQU 24\r
+USBFS_ep_0__INTC_PRIOR_NUM EQU 7\r
+USBFS_ep_0__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_24\r
+USBFS_ep_0__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
+USBFS_ep_0__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
+USBFS_ep_1__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
+USBFS_ep_1__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
+USBFS_ep_1__INTC_MASK EQU 0x80\r
+USBFS_ep_1__INTC_NUMBER EQU 7\r
+USBFS_ep_1__INTC_PRIOR_NUM EQU 7\r
+USBFS_ep_1__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_7\r
+USBFS_ep_1__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
+USBFS_ep_1__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
+USBFS_ep_2__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
+USBFS_ep_2__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
+USBFS_ep_2__INTC_MASK EQU 0x100\r
+USBFS_ep_2__INTC_NUMBER EQU 8\r
+USBFS_ep_2__INTC_PRIOR_NUM EQU 7\r
+USBFS_ep_2__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_8\r
+USBFS_ep_2__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
+USBFS_ep_2__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
+USBFS_ep_3__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
+USBFS_ep_3__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
+USBFS_ep_3__INTC_MASK EQU 0x200\r
+USBFS_ep_3__INTC_NUMBER EQU 9\r
+USBFS_ep_3__INTC_PRIOR_NUM EQU 7\r
+USBFS_ep_3__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_9\r
+USBFS_ep_3__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
+USBFS_ep_3__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
+USBFS_ep_4__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
+USBFS_ep_4__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
+USBFS_ep_4__INTC_MASK EQU 0x400\r
+USBFS_ep_4__INTC_NUMBER EQU 10\r
+USBFS_ep_4__INTC_PRIOR_NUM EQU 7\r
+USBFS_ep_4__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_10\r
+USBFS_ep_4__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
+USBFS_ep_4__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
+USBFS_sof_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
+USBFS_sof_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
+USBFS_sof_int__INTC_MASK EQU 0x200000\r
+USBFS_sof_int__INTC_NUMBER EQU 21\r
+USBFS_sof_int__INTC_PRIOR_NUM EQU 7\r
+USBFS_sof_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_21\r
+USBFS_sof_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
+USBFS_sof_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
+USBFS_USB__ARB_CFG EQU CYREG_USB_ARB_CFG\r
+USBFS_USB__ARB_EP1_CFG EQU CYREG_USB_ARB_EP1_CFG\r
+USBFS_USB__ARB_EP1_INT_EN EQU CYREG_USB_ARB_EP1_INT_EN\r
+USBFS_USB__ARB_EP1_SR EQU CYREG_USB_ARB_EP1_SR\r
+USBFS_USB__ARB_EP2_CFG EQU CYREG_USB_ARB_EP2_CFG\r
+USBFS_USB__ARB_EP2_INT_EN EQU CYREG_USB_ARB_EP2_INT_EN\r
+USBFS_USB__ARB_EP2_SR EQU CYREG_USB_ARB_EP2_SR\r
+USBFS_USB__ARB_EP3_CFG EQU CYREG_USB_ARB_EP3_CFG\r
+USBFS_USB__ARB_EP3_INT_EN EQU CYREG_USB_ARB_EP3_INT_EN\r
+USBFS_USB__ARB_EP3_SR EQU CYREG_USB_ARB_EP3_SR\r
+USBFS_USB__ARB_EP4_CFG EQU CYREG_USB_ARB_EP4_CFG\r
+USBFS_USB__ARB_EP4_INT_EN EQU CYREG_USB_ARB_EP4_INT_EN\r
+USBFS_USB__ARB_EP4_SR EQU CYREG_USB_ARB_EP4_SR\r
+USBFS_USB__ARB_EP5_CFG EQU CYREG_USB_ARB_EP5_CFG\r
+USBFS_USB__ARB_EP5_INT_EN EQU CYREG_USB_ARB_EP5_INT_EN\r
+USBFS_USB__ARB_EP5_SR EQU CYREG_USB_ARB_EP5_SR\r
+USBFS_USB__ARB_EP6_CFG EQU CYREG_USB_ARB_EP6_CFG\r
+USBFS_USB__ARB_EP6_INT_EN EQU CYREG_USB_ARB_EP6_INT_EN\r
+USBFS_USB__ARB_EP6_SR EQU CYREG_USB_ARB_EP6_SR\r
+USBFS_USB__ARB_EP7_CFG EQU CYREG_USB_ARB_EP7_CFG\r
+USBFS_USB__ARB_EP7_INT_EN EQU CYREG_USB_ARB_EP7_INT_EN\r
+USBFS_USB__ARB_EP7_SR EQU CYREG_USB_ARB_EP7_SR\r
+USBFS_USB__ARB_EP8_CFG EQU CYREG_USB_ARB_EP8_CFG\r
+USBFS_USB__ARB_EP8_INT_EN EQU CYREG_USB_ARB_EP8_INT_EN\r
+USBFS_USB__ARB_EP8_SR EQU CYREG_USB_ARB_EP8_SR\r
+USBFS_USB__ARB_INT_EN EQU CYREG_USB_ARB_INT_EN\r
+USBFS_USB__ARB_INT_SR EQU CYREG_USB_ARB_INT_SR\r
+USBFS_USB__ARB_RW1_DR EQU CYREG_USB_ARB_RW1_DR\r
+USBFS_USB__ARB_RW1_RA EQU CYREG_USB_ARB_RW1_RA\r
+USBFS_USB__ARB_RW1_RA_MSB EQU CYREG_USB_ARB_RW1_RA_MSB\r
+USBFS_USB__ARB_RW1_WA EQU CYREG_USB_ARB_RW1_WA\r
+USBFS_USB__ARB_RW1_WA_MSB EQU CYREG_USB_ARB_RW1_WA_MSB\r
+USBFS_USB__ARB_RW2_DR EQU CYREG_USB_ARB_RW2_DR\r
+USBFS_USB__ARB_RW2_RA EQU CYREG_USB_ARB_RW2_RA\r
+USBFS_USB__ARB_RW2_RA_MSB EQU CYREG_USB_ARB_RW2_RA_MSB\r
+USBFS_USB__ARB_RW2_WA EQU CYREG_USB_ARB_RW2_WA\r
+USBFS_USB__ARB_RW2_WA_MSB EQU CYREG_USB_ARB_RW2_WA_MSB\r
+USBFS_USB__ARB_RW3_DR EQU CYREG_USB_ARB_RW3_DR\r
+USBFS_USB__ARB_RW3_RA EQU CYREG_USB_ARB_RW3_RA\r
+USBFS_USB__ARB_RW3_RA_MSB EQU CYREG_USB_ARB_RW3_RA_MSB\r
+USBFS_USB__ARB_RW3_WA EQU CYREG_USB_ARB_RW3_WA\r
+USBFS_USB__ARB_RW3_WA_MSB EQU CYREG_USB_ARB_RW3_WA_MSB\r
+USBFS_USB__ARB_RW4_DR EQU CYREG_USB_ARB_RW4_DR\r
+USBFS_USB__ARB_RW4_RA EQU CYREG_USB_ARB_RW4_RA\r
+USBFS_USB__ARB_RW4_RA_MSB EQU CYREG_USB_ARB_RW4_RA_MSB\r
+USBFS_USB__ARB_RW4_WA EQU CYREG_USB_ARB_RW4_WA\r
+USBFS_USB__ARB_RW4_WA_MSB EQU CYREG_USB_ARB_RW4_WA_MSB\r
+USBFS_USB__ARB_RW5_DR EQU CYREG_USB_ARB_RW5_DR\r
+USBFS_USB__ARB_RW5_RA EQU CYREG_USB_ARB_RW5_RA\r
+USBFS_USB__ARB_RW5_RA_MSB EQU CYREG_USB_ARB_RW5_RA_MSB\r
+USBFS_USB__ARB_RW5_WA EQU CYREG_USB_ARB_RW5_WA\r
+USBFS_USB__ARB_RW5_WA_MSB EQU CYREG_USB_ARB_RW5_WA_MSB\r
+USBFS_USB__ARB_RW6_DR EQU CYREG_USB_ARB_RW6_DR\r
+USBFS_USB__ARB_RW6_RA EQU CYREG_USB_ARB_RW6_RA\r
+USBFS_USB__ARB_RW6_RA_MSB EQU CYREG_USB_ARB_RW6_RA_MSB\r
+USBFS_USB__ARB_RW6_WA EQU CYREG_USB_ARB_RW6_WA\r
+USBFS_USB__ARB_RW6_WA_MSB EQU CYREG_USB_ARB_RW6_WA_MSB\r
+USBFS_USB__ARB_RW7_DR EQU CYREG_USB_ARB_RW7_DR\r
+USBFS_USB__ARB_RW7_RA EQU CYREG_USB_ARB_RW7_RA\r
+USBFS_USB__ARB_RW7_RA_MSB EQU CYREG_USB_ARB_RW7_RA_MSB\r
+USBFS_USB__ARB_RW7_WA EQU CYREG_USB_ARB_RW7_WA\r
+USBFS_USB__ARB_RW7_WA_MSB EQU CYREG_USB_ARB_RW7_WA_MSB\r
+USBFS_USB__ARB_RW8_DR EQU CYREG_USB_ARB_RW8_DR\r
+USBFS_USB__ARB_RW8_RA EQU CYREG_USB_ARB_RW8_RA\r
+USBFS_USB__ARB_RW8_RA_MSB EQU CYREG_USB_ARB_RW8_RA_MSB\r
+USBFS_USB__ARB_RW8_WA EQU CYREG_USB_ARB_RW8_WA\r
+USBFS_USB__ARB_RW8_WA_MSB EQU CYREG_USB_ARB_RW8_WA_MSB\r
+USBFS_USB__BUF_SIZE EQU CYREG_USB_BUF_SIZE\r
+USBFS_USB__BUS_RST_CNT EQU CYREG_USB_BUS_RST_CNT\r
+USBFS_USB__CR0 EQU CYREG_USB_CR0\r
+USBFS_USB__CR1 EQU CYREG_USB_CR1\r
+USBFS_USB__CWA EQU CYREG_USB_CWA\r
+USBFS_USB__CWA_MSB EQU CYREG_USB_CWA_MSB\r
+USBFS_USB__DMA_THRES EQU CYREG_USB_DMA_THRES\r
+USBFS_USB__DMA_THRES_MSB EQU CYREG_USB_DMA_THRES_MSB\r
+USBFS_USB__DYN_RECONFIG EQU CYREG_USB_DYN_RECONFIG\r
+USBFS_USB__EP_ACTIVE EQU CYREG_USB_EP_ACTIVE\r
+USBFS_USB__EP_TYPE EQU CYREG_USB_EP_TYPE\r
+USBFS_USB__EP0_CNT EQU CYREG_USB_EP0_CNT\r
+USBFS_USB__EP0_CR EQU CYREG_USB_EP0_CR\r
+USBFS_USB__EP0_DR0 EQU CYREG_USB_EP0_DR0\r
+USBFS_USB__EP0_DR1 EQU CYREG_USB_EP0_DR1\r
+USBFS_USB__EP0_DR2 EQU CYREG_USB_EP0_DR2\r
+USBFS_USB__EP0_DR3 EQU CYREG_USB_EP0_DR3\r
+USBFS_USB__EP0_DR4 EQU CYREG_USB_EP0_DR4\r
+USBFS_USB__EP0_DR5 EQU CYREG_USB_EP0_DR5\r
+USBFS_USB__EP0_DR6 EQU CYREG_USB_EP0_DR6\r
+USBFS_USB__EP0_DR7 EQU CYREG_USB_EP0_DR7\r
+USBFS_USB__MEM_DATA EQU CYREG_USB_MEM_DATA_MBASE\r
+USBFS_USB__PM_ACT_CFG EQU CYREG_PM_ACT_CFG5\r
+USBFS_USB__PM_ACT_MSK EQU 0x01\r
+USBFS_USB__PM_STBY_CFG EQU CYREG_PM_STBY_CFG5\r
+USBFS_USB__PM_STBY_MSK EQU 0x01\r
+USBFS_USB__SIE_EP_INT_EN EQU CYREG_USB_SIE_EP_INT_EN\r
+USBFS_USB__SIE_EP_INT_SR EQU CYREG_USB_SIE_EP_INT_SR\r
+USBFS_USB__SIE_EP1_CNT0 EQU CYREG_USB_SIE_EP1_CNT0\r
+USBFS_USB__SIE_EP1_CNT1 EQU CYREG_USB_SIE_EP1_CNT1\r
+USBFS_USB__SIE_EP1_CR0 EQU CYREG_USB_SIE_EP1_CR0\r
+USBFS_USB__SIE_EP2_CNT0 EQU CYREG_USB_SIE_EP2_CNT0\r
+USBFS_USB__SIE_EP2_CNT1 EQU CYREG_USB_SIE_EP2_CNT1\r
+USBFS_USB__SIE_EP2_CR0 EQU CYREG_USB_SIE_EP2_CR0\r
+USBFS_USB__SIE_EP3_CNT0 EQU CYREG_USB_SIE_EP3_CNT0\r
+USBFS_USB__SIE_EP3_CNT1 EQU CYREG_USB_SIE_EP3_CNT1\r
+USBFS_USB__SIE_EP3_CR0 EQU CYREG_USB_SIE_EP3_CR0\r
+USBFS_USB__SIE_EP4_CNT0 EQU CYREG_USB_SIE_EP4_CNT0\r
+USBFS_USB__SIE_EP4_CNT1 EQU CYREG_USB_SIE_EP4_CNT1\r
+USBFS_USB__SIE_EP4_CR0 EQU CYREG_USB_SIE_EP4_CR0\r
+USBFS_USB__SIE_EP5_CNT0 EQU CYREG_USB_SIE_EP5_CNT0\r
+USBFS_USB__SIE_EP5_CNT1 EQU CYREG_USB_SIE_EP5_CNT1\r
+USBFS_USB__SIE_EP5_CR0 EQU CYREG_USB_SIE_EP5_CR0\r
+USBFS_USB__SIE_EP6_CNT0 EQU CYREG_USB_SIE_EP6_CNT0\r
+USBFS_USB__SIE_EP6_CNT1 EQU CYREG_USB_SIE_EP6_CNT1\r
+USBFS_USB__SIE_EP6_CR0 EQU CYREG_USB_SIE_EP6_CR0\r
+USBFS_USB__SIE_EP7_CNT0 EQU CYREG_USB_SIE_EP7_CNT0\r
+USBFS_USB__SIE_EP7_CNT1 EQU CYREG_USB_SIE_EP7_CNT1\r
+USBFS_USB__SIE_EP7_CR0 EQU CYREG_USB_SIE_EP7_CR0\r
+USBFS_USB__SIE_EP8_CNT0 EQU CYREG_USB_SIE_EP8_CNT0\r
+USBFS_USB__SIE_EP8_CNT1 EQU CYREG_USB_SIE_EP8_CNT1\r
+USBFS_USB__SIE_EP8_CR0 EQU CYREG_USB_SIE_EP8_CR0\r
+USBFS_USB__SOF0 EQU CYREG_USB_SOF0\r
+USBFS_USB__SOF1 EQU CYREG_USB_SOF1\r
+USBFS_USB__USB_CLK_EN EQU CYREG_USB_USB_CLK_EN\r
+USBFS_USB__USBIO_CR0 EQU CYREG_USB_USBIO_CR0\r
+USBFS_USB__USBIO_CR1 EQU CYREG_USB_USBIO_CR1\r
+\r
 /* scsiTarget */\r
 scsiTarget_datapath__16BIT_A0_REG EQU CYREG_B0_UDB00_01_A0\r
 scsiTarget_datapath__16BIT_A1_REG EQU CYREG_B0_UDB00_01_A1\r
@@ -2841,89 +2997,6 @@ scsiTarget_StatusReg__STATUS_CNT_REG EQU CYREG_B0_UDB07_ST_CTL
 scsiTarget_StatusReg__STATUS_CONTROL_REG EQU CYREG_B0_UDB07_ST_CTL\r
 scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB07_ST\r
 \r
-/* Debug_Timer_Interrupt */\r
-Debug_Timer_Interrupt__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
-Debug_Timer_Interrupt__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
-Debug_Timer_Interrupt__INTC_MASK EQU 0x02\r
-Debug_Timer_Interrupt__INTC_NUMBER EQU 1\r
-Debug_Timer_Interrupt__INTC_PRIOR_NUM EQU 7\r
-Debug_Timer_Interrupt__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_1\r
-Debug_Timer_Interrupt__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
-Debug_Timer_Interrupt__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
-\r
-/* Debug_Timer_TimerHW */\r
-Debug_Timer_TimerHW__CAP0 EQU CYREG_TMR0_CAP0\r
-Debug_Timer_TimerHW__CAP1 EQU CYREG_TMR0_CAP1\r
-Debug_Timer_TimerHW__CFG0 EQU CYREG_TMR0_CFG0\r
-Debug_Timer_TimerHW__CFG1 EQU CYREG_TMR0_CFG1\r
-Debug_Timer_TimerHW__CFG2 EQU CYREG_TMR0_CFG2\r
-Debug_Timer_TimerHW__CNT_CMP0 EQU CYREG_TMR0_CNT_CMP0\r
-Debug_Timer_TimerHW__CNT_CMP1 EQU CYREG_TMR0_CNT_CMP1\r
-Debug_Timer_TimerHW__PER0 EQU CYREG_TMR0_PER0\r
-Debug_Timer_TimerHW__PER1 EQU CYREG_TMR0_PER1\r
-Debug_Timer_TimerHW__PM_ACT_CFG EQU CYREG_PM_ACT_CFG3\r
-Debug_Timer_TimerHW__PM_ACT_MSK EQU 0x01\r
-Debug_Timer_TimerHW__PM_STBY_CFG EQU CYREG_PM_STBY_CFG3\r
-Debug_Timer_TimerHW__PM_STBY_MSK EQU 0x01\r
-Debug_Timer_TimerHW__RT0 EQU CYREG_TMR0_RT0\r
-Debug_Timer_TimerHW__RT1 EQU CYREG_TMR0_RT1\r
-Debug_Timer_TimerHW__SR0 EQU CYREG_TMR0_SR0\r
-\r
-/* SCSI_RX_DMA */\r
-SCSI_RX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0\r
-SCSI_RX_DMA__DRQ_NUMBER EQU 0\r
-SCSI_RX_DMA__NUMBEROF_TDS EQU 0\r
-SCSI_RX_DMA__PRIORITY EQU 2\r
-SCSI_RX_DMA__TERMIN_EN EQU 0\r
-SCSI_RX_DMA__TERMIN_SEL EQU 0\r
-SCSI_RX_DMA__TERMOUT0_EN EQU 1\r
-SCSI_RX_DMA__TERMOUT0_SEL EQU 0\r
-SCSI_RX_DMA__TERMOUT1_EN EQU 0\r
-SCSI_RX_DMA__TERMOUT1_SEL EQU 0\r
-\r
-/* SCSI_RX_DMA_COMPLETE */\r
-SCSI_RX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
-SCSI_RX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
-SCSI_RX_DMA_COMPLETE__INTC_MASK EQU 0x01\r
-SCSI_RX_DMA_COMPLETE__INTC_NUMBER EQU 0\r
-SCSI_RX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7\r
-SCSI_RX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_0\r
-SCSI_RX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
-SCSI_RX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
-\r
-/* SCSI_TX_DMA */\r
-SCSI_TX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0\r
-SCSI_TX_DMA__DRQ_NUMBER EQU 1\r
-SCSI_TX_DMA__NUMBEROF_TDS EQU 0\r
-SCSI_TX_DMA__PRIORITY EQU 2\r
-SCSI_TX_DMA__TERMIN_EN EQU 0\r
-SCSI_TX_DMA__TERMIN_SEL EQU 0\r
-SCSI_TX_DMA__TERMOUT0_EN EQU 1\r
-SCSI_TX_DMA__TERMOUT0_SEL EQU 1\r
-SCSI_TX_DMA__TERMOUT1_EN EQU 0\r
-SCSI_TX_DMA__TERMOUT1_SEL EQU 0\r
-\r
-/* SCSI_TX_DMA_COMPLETE */\r
-SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
-SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
-SCSI_TX_DMA_COMPLETE__INTC_MASK EQU 0x10\r
-SCSI_TX_DMA_COMPLETE__INTC_NUMBER EQU 4\r
-SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7\r
-SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_4\r
-SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
-SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
-\r
-/* SD_Data_Clk */\r
-SD_Data_Clk__CFG0 EQU CYREG_CLKDIST_DCFG0_CFG0\r
-SD_Data_Clk__CFG1 EQU CYREG_CLKDIST_DCFG0_CFG1\r
-SD_Data_Clk__CFG2 EQU CYREG_CLKDIST_DCFG0_CFG2\r
-SD_Data_Clk__CFG2_SRC_SEL_MASK EQU 0x07\r
-SD_Data_Clk__INDEX EQU 0x00\r
-SD_Data_Clk__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2\r
-SD_Data_Clk__PM_ACT_MSK EQU 0x01\r
-SD_Data_Clk__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2\r
-SD_Data_Clk__PM_STBY_MSK EQU 0x01\r
-\r
 /* timer_clock */\r
 timer_clock__CFG0 EQU CYREG_CLKDIST_DCFG2_CFG0\r
 timer_clock__CFG1 EQU CYREG_CLKDIST_DCFG2_CFG1\r
@@ -2935,146 +3008,53 @@ timer_clock__PM_ACT_MSK EQU 0x04
 timer_clock__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2\r
 timer_clock__PM_STBY_MSK EQU 0x04\r
 \r
-/* SCSI_RST_ISR */\r
-SCSI_RST_ISR__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
-SCSI_RST_ISR__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
-SCSI_RST_ISR__INTC_MASK EQU 0x04\r
-SCSI_RST_ISR__INTC_NUMBER EQU 2\r
-SCSI_RST_ISR__INTC_PRIOR_NUM EQU 7\r
-SCSI_RST_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_2\r
-SCSI_RST_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
-SCSI_RST_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
-\r
-/* SCSI_SEL_ISR */\r
-SCSI_SEL_ISR__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
-SCSI_SEL_ISR__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
-SCSI_SEL_ISR__INTC_MASK EQU 0x08\r
-SCSI_SEL_ISR__INTC_NUMBER EQU 3\r
-SCSI_SEL_ISR__INTC_PRIOR_NUM EQU 7\r
-SCSI_SEL_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_3\r
-SCSI_SEL_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
-SCSI_SEL_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
-\r
-/* SCSI_Filtered */\r
-SCSI_Filtered_sts_sts_reg__0__MASK EQU 0x01\r
-SCSI_Filtered_sts_sts_reg__0__POS EQU 0\r
-SCSI_Filtered_sts_sts_reg__1__MASK EQU 0x02\r
-SCSI_Filtered_sts_sts_reg__1__POS EQU 1\r
-SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL\r
-SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB02_03_ST\r
-SCSI_Filtered_sts_sts_reg__2__MASK EQU 0x04\r
-SCSI_Filtered_sts_sts_reg__2__POS EQU 2\r
-SCSI_Filtered_sts_sts_reg__3__MASK EQU 0x08\r
-SCSI_Filtered_sts_sts_reg__3__POS EQU 3\r
-SCSI_Filtered_sts_sts_reg__4__MASK EQU 0x10\r
-SCSI_Filtered_sts_sts_reg__4__POS EQU 4\r
-SCSI_Filtered_sts_sts_reg__MASK EQU 0x1F\r
-SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB02_MSK\r
-SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL\r
-SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB02_ST\r
-\r
-/* SCSI_CTL_PHASE */\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS EQU 0\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK EQU 0x02\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS EQU 1\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB05_06_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB05_06_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB05_06_MSK\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB05_06_MSK\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK EQU 0x04\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS EQU 2\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB05_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB05_ST_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB05_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB05_ST_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__MASK EQU 0x07\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB05_MSK\r
-\r
-/* SCSI_Glitch_Ctl */\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS EQU 0\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB07_08_CTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB07_08_CTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB07_08_CTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB07_08_CTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB07_08_MSK\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB07_08_MSK\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB07_08_MSK\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB07_08_MSK\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB07_CTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB07_ST_CTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB07_CTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB07_ST_CTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK EQU 0x01\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB07_MSK\r
-\r
-/* SCSI_Parity_Error */\r
-SCSI_Parity_Error_sts_sts_reg__0__MASK EQU 0x01\r
-SCSI_Parity_Error_sts_sts_reg__0__POS EQU 0\r
-SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB01_02_ACTL\r
-SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB01_02_ST\r
-SCSI_Parity_Error_sts_sts_reg__MASK EQU 0x01\r
-SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB01_MSK\r
-SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB01_ACTL\r
-SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB01_ST\r
-\r
 /* Miscellaneous */\r
 BCLK__BUS_CLK__HZ EQU 50000000\r
 BCLK__BUS_CLK__KHZ EQU 50000\r
 BCLK__BUS_CLK__MHZ EQU 50\r
 CYDEV_CHIP_DIE_LEOPARD EQU 1\r
-CYDEV_CHIP_DIE_PSOC4A EQU 12\r
-CYDEV_CHIP_DIE_PSOC5LP EQU 19\r
-CYDEV_CHIP_DIE_PSOC5TM EQU 20\r
-CYDEV_CHIP_DIE_TMA4 EQU 2\r
+CYDEV_CHIP_DIE_PSOC4A EQU 16\r
+CYDEV_CHIP_DIE_PSOC5LP EQU 2\r
+CYDEV_CHIP_DIE_PSOC5TM EQU 3\r
+CYDEV_CHIP_DIE_TMA4 EQU 4\r
 CYDEV_CHIP_DIE_UNKNOWN EQU 0\r
-CYDEV_CHIP_FAMILY_FM0P EQU 4\r
-CYDEV_CHIP_FAMILY_FM3 EQU 5\r
-CYDEV_CHIP_FAMILY_FM4 EQU 6\r
+CYDEV_CHIP_FAMILY_FM0P EQU 5\r
+CYDEV_CHIP_FAMILY_FM3 EQU 6\r
+CYDEV_CHIP_FAMILY_FM4 EQU 7\r
 CYDEV_CHIP_FAMILY_PSOC3 EQU 1\r
 CYDEV_CHIP_FAMILY_PSOC4 EQU 2\r
 CYDEV_CHIP_FAMILY_PSOC5 EQU 3\r
+CYDEV_CHIP_FAMILY_PSOC6 EQU 4\r
 CYDEV_CHIP_FAMILY_UNKNOWN EQU 0\r
 CYDEV_CHIP_FAMILY_USED EQU CYDEV_CHIP_FAMILY_PSOC5\r
 CYDEV_CHIP_JTAG_ID EQU 0x2E133069\r
 CYDEV_CHIP_MEMBER_3A EQU 1\r
-CYDEV_CHIP_MEMBER_4A EQU 12\r
-CYDEV_CHIP_MEMBER_4C EQU 18\r
-CYDEV_CHIP_MEMBER_4D EQU 8\r
-CYDEV_CHIP_MEMBER_4E EQU 4\r
-CYDEV_CHIP_MEMBER_4F EQU 13\r
-CYDEV_CHIP_MEMBER_4G EQU 2\r
-CYDEV_CHIP_MEMBER_4H EQU 11\r
-CYDEV_CHIP_MEMBER_4I EQU 17\r
-CYDEV_CHIP_MEMBER_4J EQU 9\r
-CYDEV_CHIP_MEMBER_4K EQU 10\r
-CYDEV_CHIP_MEMBER_4L EQU 16\r
-CYDEV_CHIP_MEMBER_4M EQU 15\r
-CYDEV_CHIP_MEMBER_4N EQU 6\r
-CYDEV_CHIP_MEMBER_4O EQU 5\r
-CYDEV_CHIP_MEMBER_4P EQU 14\r
-CYDEV_CHIP_MEMBER_4Q EQU 7\r
-CYDEV_CHIP_MEMBER_4U EQU 3\r
-CYDEV_CHIP_MEMBER_5A EQU 20\r
-CYDEV_CHIP_MEMBER_5B EQU 19\r
-CYDEV_CHIP_MEMBER_FM3 EQU 24\r
-CYDEV_CHIP_MEMBER_FM4 EQU 25\r
-CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE1 EQU 21\r
-CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE2 EQU 22\r
-CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE3 EQU 23\r
+CYDEV_CHIP_MEMBER_4A EQU 16\r
+CYDEV_CHIP_MEMBER_4D EQU 12\r
+CYDEV_CHIP_MEMBER_4E EQU 6\r
+CYDEV_CHIP_MEMBER_4F EQU 17\r
+CYDEV_CHIP_MEMBER_4G EQU 4\r
+CYDEV_CHIP_MEMBER_4H EQU 15\r
+CYDEV_CHIP_MEMBER_4I EQU 21\r
+CYDEV_CHIP_MEMBER_4J EQU 13\r
+CYDEV_CHIP_MEMBER_4K EQU 14\r
+CYDEV_CHIP_MEMBER_4L EQU 20\r
+CYDEV_CHIP_MEMBER_4M EQU 19\r
+CYDEV_CHIP_MEMBER_4N EQU 9\r
+CYDEV_CHIP_MEMBER_4O EQU 7\r
+CYDEV_CHIP_MEMBER_4P EQU 18\r
+CYDEV_CHIP_MEMBER_4Q EQU 11\r
+CYDEV_CHIP_MEMBER_4R EQU 8\r
+CYDEV_CHIP_MEMBER_4S EQU 10\r
+CYDEV_CHIP_MEMBER_4U EQU 5\r
+CYDEV_CHIP_MEMBER_5A EQU 3\r
+CYDEV_CHIP_MEMBER_5B EQU 2\r
+CYDEV_CHIP_MEMBER_6A EQU 22\r
+CYDEV_CHIP_MEMBER_FM3 EQU 26\r
+CYDEV_CHIP_MEMBER_FM4 EQU 27\r
+CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE1 EQU 23\r
+CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE2 EQU 24\r
+CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE3 EQU 25\r
 CYDEV_CHIP_MEMBER_UNKNOWN EQU 0\r
 CYDEV_CHIP_MEMBER_USED EQU CYDEV_CHIP_MEMBER_5B\r
 CYDEV_CHIP_DIE_EXPECT EQU CYDEV_CHIP_MEMBER_USED\r
@@ -3099,7 +3079,6 @@ CYDEV_CHIP_REVISION_3A_ES3 EQU 3
 CYDEV_CHIP_REVISION_3A_PRODUCTION EQU 3\r
 CYDEV_CHIP_REVISION_4A_ES0 EQU 17\r
 CYDEV_CHIP_REVISION_4A_PRODUCTION EQU 17\r
-CYDEV_CHIP_REVISION_4C_PRODUCTION EQU 0\r
 CYDEV_CHIP_REVISION_4D_PRODUCTION EQU 0\r
 CYDEV_CHIP_REVISION_4E_PRODUCTION EQU 0\r
 CYDEV_CHIP_REVISION_4F_PRODUCTION EQU 0\r
@@ -3118,12 +3097,16 @@ CYDEV_CHIP_REVISION_4N_PRODUCTION EQU 0
 CYDEV_CHIP_REVISION_4O_PRODUCTION EQU 0\r
 CYDEV_CHIP_REVISION_4P_PRODUCTION EQU 0\r
 CYDEV_CHIP_REVISION_4Q_PRODUCTION EQU 0\r
+CYDEV_CHIP_REVISION_4R_PRODUCTION EQU 0\r
+CYDEV_CHIP_REVISION_4S_PRODUCTION EQU 0\r
 CYDEV_CHIP_REVISION_4U_PRODUCTION EQU 0\r
 CYDEV_CHIP_REVISION_5A_ES0 EQU 0\r
 CYDEV_CHIP_REVISION_5A_ES1 EQU 1\r
 CYDEV_CHIP_REVISION_5A_PRODUCTION EQU 1\r
 CYDEV_CHIP_REVISION_5B_ES0 EQU 0\r
 CYDEV_CHIP_REVISION_5B_PRODUCTION EQU 0\r
+CYDEV_CHIP_REVISION_6A_NO_UDB EQU 0\r
+CYDEV_CHIP_REVISION_6A_PRODUCTION EQU 0\r
 CYDEV_CHIP_REVISION_FM3_PRODUCTION EQU 0\r
 CYDEV_CHIP_REVISION_FM4_PRODUCTION EQU 0\r
 CYDEV_CHIP_REVISION_PDL_FM0P_TYPE1_PRODUCTION EQU 0\r
@@ -3155,7 +3138,7 @@ CYDEV_DMA_CHANNELS_AVAILABLE EQU 24
 CYDEV_ECC_ENABLE EQU 0\r
 CYDEV_HEAP_SIZE EQU 0x0400\r
 CYDEV_INSTRUCT_CACHE_ENABLED EQU 1\r
-CYDEV_INTR_RISING EQU 0x0000007E\r
+CYDEV_INTR_RISING EQU 0x0000007F\r
 CYDEV_IS_EXPORTING_CODE EQU 0\r
 CYDEV_IS_IMPORTING_CODE EQU 0\r
 CYDEV_PROJ_TYPE EQU 2\r

diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitterrv.inc b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitterrv.inc
index 05b03560f4011c2cf166297ac6af5658ce6e9ebc..90a305e40a2ad4bd63d1e8ee6147ba912ad90b9b 100755 (executable)
--- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitterrv.inc
+++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitterrv.inc
@@ -1,8 +1,51 @@
+;\r
+; File Name: cyfitterrv.inc\r
+; \r
+; PSoC Creator  4.1\r
+;\r
+; Description:\r
+; \r
+;\r
+;-------------------------------------------------------------------------------\r
+; Copyright (c) 2007-2017 Cypress Semiconductor.  All rights reserved.\r
+; You may use this file only in accordance with the license, terms, conditions, \r
+; disclaimers, and limitations in the end user license agreement accompanying \r
+; the software package with which this file was provided.\r
+;-------------------------------------------------------------------------------\r
+\r
     IF :LNOT::DEF:INCLUDED_CYFITTERRV_INC\r
 INCLUDED_CYFITTERRV_INC EQU 1\r
     GET cydevicerv.inc\r
     GET cydevicerv_trm.inc\r
 \r
+; Debug_Timer_Interrupt\r
+Debug_Timer_Interrupt__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
+Debug_Timer_Interrupt__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
+Debug_Timer_Interrupt__INTC_MASK EQU 0x01\r
+Debug_Timer_Interrupt__INTC_NUMBER EQU 0\r
+Debug_Timer_Interrupt__INTC_PRIOR_NUM EQU 7\r
+Debug_Timer_Interrupt__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_0\r
+Debug_Timer_Interrupt__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
+Debug_Timer_Interrupt__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
+\r
+; Debug_Timer_TimerHW\r
+Debug_Timer_TimerHW__CAP0 EQU CYREG_TMR0_CAP0\r
+Debug_Timer_TimerHW__CAP1 EQU CYREG_TMR0_CAP1\r
+Debug_Timer_TimerHW__CFG0 EQU CYREG_TMR0_CFG0\r
+Debug_Timer_TimerHW__CFG1 EQU CYREG_TMR0_CFG1\r
+Debug_Timer_TimerHW__CFG2 EQU CYREG_TMR0_CFG2\r
+Debug_Timer_TimerHW__CNT_CMP0 EQU CYREG_TMR0_CNT_CMP0\r
+Debug_Timer_TimerHW__CNT_CMP1 EQU CYREG_TMR0_CNT_CMP1\r
+Debug_Timer_TimerHW__PER0 EQU CYREG_TMR0_PER0\r
+Debug_Timer_TimerHW__PER1 EQU CYREG_TMR0_PER1\r
+Debug_Timer_TimerHW__PM_ACT_CFG EQU CYREG_PM_ACT_CFG3\r
+Debug_Timer_TimerHW__PM_ACT_MSK EQU 0x01\r
+Debug_Timer_TimerHW__PM_STBY_CFG EQU CYREG_PM_STBY_CFG3\r
+Debug_Timer_TimerHW__PM_STBY_MSK EQU 0x01\r
+Debug_Timer_TimerHW__RT0 EQU CYREG_TMR0_RT0\r
+Debug_Timer_TimerHW__RT1 EQU CYREG_TMR0_RT1\r
+Debug_Timer_TimerHW__SR0 EQU CYREG_TMR0_SR0\r
+\r
 ; LED1\r
 LED1__0__INTTYPE EQU CYREG_PICU12_INTTYPE3\r
 LED1__0__MASK EQU 0x08\r
@@ -36,2463 +79,810 @@ LED1__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN
 LED1__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ\r
 LED1__SLW EQU CYREG_PRT12_SLW\r
 \r
-; SD_CD\r
-SD_CD__0__INTTYPE EQU CYREG_PICU3_INTTYPE6\r
-SD_CD__0__MASK EQU 0x40\r
-SD_CD__0__PC EQU CYREG_PRT3_PC6\r
-SD_CD__0__PORT EQU 3\r
-SD_CD__0__SHIFT EQU 6\r
-SD_CD__AG EQU CYREG_PRT3_AG\r
-SD_CD__AMUX EQU CYREG_PRT3_AMUX\r
-SD_CD__BIE EQU CYREG_PRT3_BIE\r
-SD_CD__BIT_MASK EQU CYREG_PRT3_BIT_MASK\r
-SD_CD__BYP EQU CYREG_PRT3_BYP\r
-SD_CD__CTL EQU CYREG_PRT3_CTL\r
-SD_CD__DM0 EQU CYREG_PRT3_DM0\r
-SD_CD__DM1 EQU CYREG_PRT3_DM1\r
-SD_CD__DM2 EQU CYREG_PRT3_DM2\r
-SD_CD__DR EQU CYREG_PRT3_DR\r
-SD_CD__INP_DIS EQU CYREG_PRT3_INP_DIS\r
-SD_CD__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE\r
-SD_CD__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG\r
-SD_CD__LCD_EN EQU CYREG_PRT3_LCD_EN\r
-SD_CD__MASK EQU 0x40\r
-SD_CD__PORT EQU 3\r
-SD_CD__PRT EQU CYREG_PRT3_PRT\r
-SD_CD__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL\r
-SD_CD__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN\r
-SD_CD__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0\r
-SD_CD__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1\r
-SD_CD__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0\r
-SD_CD__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1\r
-SD_CD__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT\r
-SD_CD__PS EQU CYREG_PRT3_PS\r
-SD_CD__SHIFT EQU 6\r
-SD_CD__SLW EQU CYREG_PRT3_SLW\r
-\r
-; SD_CS\r
-SD_CS__0__INTTYPE EQU CYREG_PICU3_INTTYPE4\r
-SD_CS__0__MASK EQU 0x10\r
-SD_CS__0__PC EQU CYREG_PRT3_PC4\r
-SD_CS__0__PORT EQU 3\r
-SD_CS__0__SHIFT EQU 4\r
-SD_CS__AG EQU CYREG_PRT3_AG\r
-SD_CS__AMUX EQU CYREG_PRT3_AMUX\r
-SD_CS__BIE EQU CYREG_PRT3_BIE\r
-SD_CS__BIT_MASK EQU CYREG_PRT3_BIT_MASK\r
-SD_CS__BYP EQU CYREG_PRT3_BYP\r
-SD_CS__CTL EQU CYREG_PRT3_CTL\r
-SD_CS__DM0 EQU CYREG_PRT3_DM0\r
-SD_CS__DM1 EQU CYREG_PRT3_DM1\r
-SD_CS__DM2 EQU CYREG_PRT3_DM2\r
-SD_CS__DR EQU CYREG_PRT3_DR\r
-SD_CS__INP_DIS EQU CYREG_PRT3_INP_DIS\r
-SD_CS__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE\r
-SD_CS__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG\r
-SD_CS__LCD_EN EQU CYREG_PRT3_LCD_EN\r
-SD_CS__MASK EQU 0x10\r
-SD_CS__PORT EQU 3\r
-SD_CS__PRT EQU CYREG_PRT3_PRT\r
-SD_CS__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL\r
-SD_CS__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN\r
-SD_CS__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0\r
-SD_CS__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1\r
-SD_CS__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0\r
-SD_CS__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1\r
-SD_CS__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT\r
-SD_CS__PS EQU CYREG_PRT3_PS\r
-SD_CS__SHIFT EQU 4\r
-SD_CS__SLW EQU CYREG_PRT3_SLW\r
-\r
-; USBFS_arb_int\r
-USBFS_arb_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
-USBFS_arb_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
-USBFS_arb_int__INTC_MASK EQU 0x400000\r
-USBFS_arb_int__INTC_NUMBER EQU 22\r
-USBFS_arb_int__INTC_PRIOR_NUM EQU 6\r
-USBFS_arb_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_22\r
-USBFS_arb_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
-USBFS_arb_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
+; SCSI_CLK\r
+SCSI_CLK__CFG0 EQU CYREG_CLKDIST_DCFG1_CFG0\r
+SCSI_CLK__CFG1 EQU CYREG_CLKDIST_DCFG1_CFG1\r
+SCSI_CLK__CFG2 EQU CYREG_CLKDIST_DCFG1_CFG2\r
+SCSI_CLK__CFG2_SRC_SEL_MASK EQU 0x07\r
+SCSI_CLK__INDEX EQU 0x01\r
+SCSI_CLK__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2\r
+SCSI_CLK__PM_ACT_MSK EQU 0x02\r
+SCSI_CLK__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2\r
+SCSI_CLK__PM_STBY_MSK EQU 0x02\r
 \r
-; USBFS_bus_reset\r
-USBFS_bus_reset__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
-USBFS_bus_reset__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
-USBFS_bus_reset__INTC_MASK EQU 0x800000\r
-USBFS_bus_reset__INTC_NUMBER EQU 23\r
-USBFS_bus_reset__INTC_PRIOR_NUM EQU 7\r
-USBFS_bus_reset__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_23\r
-USBFS_bus_reset__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
-USBFS_bus_reset__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
+; SCSI_CTL_PHASE\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS EQU 0\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK EQU 0x02\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS EQU 1\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB05_06_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB05_06_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB05_06_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB05_06_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK EQU 0x04\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS EQU 2\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB05_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB05_ST_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB05_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB05_ST_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__MASK EQU 0x07\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB05_MSK\r
 \r
-; USBFS_Dm\r
-USBFS_Dm__0__INTTYPE EQU CYREG_PICU15_INTTYPE7\r
-USBFS_Dm__0__MASK EQU 0x80\r
-USBFS_Dm__0__PC EQU CYREG_IO_PC_PRT15_7_6_PC1\r
-USBFS_Dm__0__PORT EQU 15\r
-USBFS_Dm__0__SHIFT EQU 7\r
-USBFS_Dm__AG EQU CYREG_PRT15_AG\r
-USBFS_Dm__AMUX EQU CYREG_PRT15_AMUX\r
-USBFS_Dm__BIE EQU CYREG_PRT15_BIE\r
-USBFS_Dm__BIT_MASK EQU CYREG_PRT15_BIT_MASK\r
-USBFS_Dm__BYP EQU CYREG_PRT15_BYP\r
-USBFS_Dm__CTL EQU CYREG_PRT15_CTL\r
-USBFS_Dm__DM0 EQU CYREG_PRT15_DM0\r
-USBFS_Dm__DM1 EQU CYREG_PRT15_DM1\r
-USBFS_Dm__DM2 EQU CYREG_PRT15_DM2\r
-USBFS_Dm__DR EQU CYREG_PRT15_DR\r
-USBFS_Dm__INP_DIS EQU CYREG_PRT15_INP_DIS\r
-USBFS_Dm__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU15_BASE\r
-USBFS_Dm__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG\r
-USBFS_Dm__LCD_EN EQU CYREG_PRT15_LCD_EN\r
-USBFS_Dm__MASK EQU 0x80\r
-USBFS_Dm__PORT EQU 15\r
-USBFS_Dm__PRT EQU CYREG_PRT15_PRT\r
-USBFS_Dm__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL\r
-USBFS_Dm__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN\r
-USBFS_Dm__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0\r
-USBFS_Dm__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1\r
-USBFS_Dm__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0\r
-USBFS_Dm__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1\r
-USBFS_Dm__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT\r
-USBFS_Dm__PS EQU CYREG_PRT15_PS\r
-USBFS_Dm__SHIFT EQU 7\r
-USBFS_Dm__SLW EQU CYREG_PRT15_SLW\r
+; SCSI_Filtered\r
+SCSI_Filtered_sts_sts_reg__0__MASK EQU 0x01\r
+SCSI_Filtered_sts_sts_reg__0__POS EQU 0\r
+SCSI_Filtered_sts_sts_reg__1__MASK EQU 0x02\r
+SCSI_Filtered_sts_sts_reg__1__POS EQU 1\r
+SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL\r
+SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB02_03_ST\r
+SCSI_Filtered_sts_sts_reg__2__MASK EQU 0x04\r
+SCSI_Filtered_sts_sts_reg__2__POS EQU 2\r
+SCSI_Filtered_sts_sts_reg__3__MASK EQU 0x08\r
+SCSI_Filtered_sts_sts_reg__3__POS EQU 3\r
+SCSI_Filtered_sts_sts_reg__4__MASK EQU 0x10\r
+SCSI_Filtered_sts_sts_reg__4__POS EQU 4\r
+SCSI_Filtered_sts_sts_reg__MASK EQU 0x1F\r
+SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB02_MSK\r
+SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL\r
+SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB02_ST\r
 \r
-; USBFS_Dp\r
-USBFS_Dp__0__INTTYPE EQU CYREG_PICU15_INTTYPE6\r
-USBFS_Dp__0__MASK EQU 0x40\r
-USBFS_Dp__0__PC EQU CYREG_IO_PC_PRT15_7_6_PC0\r
-USBFS_Dp__0__PORT EQU 15\r
-USBFS_Dp__0__SHIFT EQU 6\r
-USBFS_Dp__AG EQU CYREG_PRT15_AG\r
-USBFS_Dp__AMUX EQU CYREG_PRT15_AMUX\r
-USBFS_Dp__BIE EQU CYREG_PRT15_BIE\r
-USBFS_Dp__BIT_MASK EQU CYREG_PRT15_BIT_MASK\r
-USBFS_Dp__BYP EQU CYREG_PRT15_BYP\r
-USBFS_Dp__CTL EQU CYREG_PRT15_CTL\r
-USBFS_Dp__DM0 EQU CYREG_PRT15_DM0\r
-USBFS_Dp__DM1 EQU CYREG_PRT15_DM1\r
-USBFS_Dp__DM2 EQU CYREG_PRT15_DM2\r
-USBFS_Dp__DR EQU CYREG_PRT15_DR\r
-USBFS_Dp__INP_DIS EQU CYREG_PRT15_INP_DIS\r
-USBFS_Dp__INTSTAT EQU CYREG_PICU15_INTSTAT\r
-USBFS_Dp__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU15_BASE\r
-USBFS_Dp__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG\r
-USBFS_Dp__LCD_EN EQU CYREG_PRT15_LCD_EN\r
-USBFS_Dp__MASK EQU 0x40\r
-USBFS_Dp__PORT EQU 15\r
-USBFS_Dp__PRT EQU CYREG_PRT15_PRT\r
-USBFS_Dp__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL\r
-USBFS_Dp__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN\r
-USBFS_Dp__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0\r
-USBFS_Dp__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1\r
-USBFS_Dp__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0\r
-USBFS_Dp__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1\r
-USBFS_Dp__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT\r
-USBFS_Dp__PS EQU CYREG_PRT15_PS\r
-USBFS_Dp__SHIFT EQU 6\r
-USBFS_Dp__SLW EQU CYREG_PRT15_SLW\r
-USBFS_Dp__SNAP EQU CYREG_PICU_15_SNAP_15\r
+; SCSI_Glitch_Ctl\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS EQU 0\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB07_08_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB07_08_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB07_08_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB07_08_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB07_08_MSK\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB07_08_MSK\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB07_08_MSK\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB07_08_MSK\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB07_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB07_ST_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB07_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB07_ST_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK EQU 0x01\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB07_MSK\r
 \r
-; USBFS_dp_int\r
-USBFS_dp_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
-USBFS_dp_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
-USBFS_dp_int__INTC_MASK EQU 0x1000\r
-USBFS_dp_int__INTC_NUMBER EQU 12\r
-USBFS_dp_int__INTC_PRIOR_NUM EQU 7\r
-USBFS_dp_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_12\r
-USBFS_dp_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
-USBFS_dp_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
-\r
-; USBFS_ep_0\r
-USBFS_ep_0__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
-USBFS_ep_0__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
-USBFS_ep_0__INTC_MASK EQU 0x1000000\r
-USBFS_ep_0__INTC_NUMBER EQU 24\r
-USBFS_ep_0__INTC_PRIOR_NUM EQU 7\r
-USBFS_ep_0__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_24\r
-USBFS_ep_0__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
-USBFS_ep_0__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
-\r
-; USBFS_ep_1\r
-USBFS_ep_1__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
-USBFS_ep_1__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
-USBFS_ep_1__INTC_MASK EQU 0x80\r
-USBFS_ep_1__INTC_NUMBER EQU 7\r
-USBFS_ep_1__INTC_PRIOR_NUM EQU 7\r
-USBFS_ep_1__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_7\r
-USBFS_ep_1__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
-USBFS_ep_1__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
-\r
-; USBFS_ep_2\r
-USBFS_ep_2__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
-USBFS_ep_2__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
-USBFS_ep_2__INTC_MASK EQU 0x100\r
-USBFS_ep_2__INTC_NUMBER EQU 8\r
-USBFS_ep_2__INTC_PRIOR_NUM EQU 7\r
-USBFS_ep_2__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_8\r
-USBFS_ep_2__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
-USBFS_ep_2__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
-\r
-; USBFS_ep_3\r
-USBFS_ep_3__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
-USBFS_ep_3__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
-USBFS_ep_3__INTC_MASK EQU 0x200\r
-USBFS_ep_3__INTC_NUMBER EQU 9\r
-USBFS_ep_3__INTC_PRIOR_NUM EQU 7\r
-USBFS_ep_3__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_9\r
-USBFS_ep_3__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
-USBFS_ep_3__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
-\r
-; USBFS_ep_4\r
-USBFS_ep_4__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
-USBFS_ep_4__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
-USBFS_ep_4__INTC_MASK EQU 0x400\r
-USBFS_ep_4__INTC_NUMBER EQU 10\r
-USBFS_ep_4__INTC_PRIOR_NUM EQU 7\r
-USBFS_ep_4__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_10\r
-USBFS_ep_4__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
-USBFS_ep_4__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
-\r
-; USBFS_sof_int\r
-USBFS_sof_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
-USBFS_sof_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
-USBFS_sof_int__INTC_MASK EQU 0x200000\r
-USBFS_sof_int__INTC_NUMBER EQU 21\r
-USBFS_sof_int__INTC_PRIOR_NUM EQU 7\r
-USBFS_sof_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_21\r
-USBFS_sof_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
-USBFS_sof_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
-\r
-; USBFS_USB\r
-USBFS_USB__ARB_CFG EQU CYREG_USB_ARB_CFG\r
-USBFS_USB__ARB_EP1_CFG EQU CYREG_USB_ARB_EP1_CFG\r
-USBFS_USB__ARB_EP1_INT_EN EQU CYREG_USB_ARB_EP1_INT_EN\r
-USBFS_USB__ARB_EP1_SR EQU CYREG_USB_ARB_EP1_SR\r
-USBFS_USB__ARB_EP2_CFG EQU CYREG_USB_ARB_EP2_CFG\r
-USBFS_USB__ARB_EP2_INT_EN EQU CYREG_USB_ARB_EP2_INT_EN\r
-USBFS_USB__ARB_EP2_SR EQU CYREG_USB_ARB_EP2_SR\r
-USBFS_USB__ARB_EP3_CFG EQU CYREG_USB_ARB_EP3_CFG\r
-USBFS_USB__ARB_EP3_INT_EN EQU CYREG_USB_ARB_EP3_INT_EN\r
-USBFS_USB__ARB_EP3_SR EQU CYREG_USB_ARB_EP3_SR\r
-USBFS_USB__ARB_EP4_CFG EQU CYREG_USB_ARB_EP4_CFG\r
-USBFS_USB__ARB_EP4_INT_EN EQU CYREG_USB_ARB_EP4_INT_EN\r
-USBFS_USB__ARB_EP4_SR EQU CYREG_USB_ARB_EP4_SR\r
-USBFS_USB__ARB_EP5_CFG EQU CYREG_USB_ARB_EP5_CFG\r
-USBFS_USB__ARB_EP5_INT_EN EQU CYREG_USB_ARB_EP5_INT_EN\r
-USBFS_USB__ARB_EP5_SR EQU CYREG_USB_ARB_EP5_SR\r
-USBFS_USB__ARB_EP6_CFG EQU CYREG_USB_ARB_EP6_CFG\r
-USBFS_USB__ARB_EP6_INT_EN EQU CYREG_USB_ARB_EP6_INT_EN\r
-USBFS_USB__ARB_EP6_SR EQU CYREG_USB_ARB_EP6_SR\r
-USBFS_USB__ARB_EP7_CFG EQU CYREG_USB_ARB_EP7_CFG\r
-USBFS_USB__ARB_EP7_INT_EN EQU CYREG_USB_ARB_EP7_INT_EN\r
-USBFS_USB__ARB_EP7_SR EQU CYREG_USB_ARB_EP7_SR\r
-USBFS_USB__ARB_EP8_CFG EQU CYREG_USB_ARB_EP8_CFG\r
-USBFS_USB__ARB_EP8_INT_EN EQU CYREG_USB_ARB_EP8_INT_EN\r
-USBFS_USB__ARB_EP8_SR EQU CYREG_USB_ARB_EP8_SR\r
-USBFS_USB__ARB_INT_EN EQU CYREG_USB_ARB_INT_EN\r
-USBFS_USB__ARB_INT_SR EQU CYREG_USB_ARB_INT_SR\r
-USBFS_USB__ARB_RW1_DR EQU CYREG_USB_ARB_RW1_DR\r
-USBFS_USB__ARB_RW1_RA EQU CYREG_USB_ARB_RW1_RA\r
-USBFS_USB__ARB_RW1_RA_MSB EQU CYREG_USB_ARB_RW1_RA_MSB\r
-USBFS_USB__ARB_RW1_WA EQU CYREG_USB_ARB_RW1_WA\r
-USBFS_USB__ARB_RW1_WA_MSB EQU CYREG_USB_ARB_RW1_WA_MSB\r
-USBFS_USB__ARB_RW2_DR EQU CYREG_USB_ARB_RW2_DR\r
-USBFS_USB__ARB_RW2_RA EQU CYREG_USB_ARB_RW2_RA\r
-USBFS_USB__ARB_RW2_RA_MSB EQU CYREG_USB_ARB_RW2_RA_MSB\r
-USBFS_USB__ARB_RW2_WA EQU CYREG_USB_ARB_RW2_WA\r
-USBFS_USB__ARB_RW2_WA_MSB EQU CYREG_USB_ARB_RW2_WA_MSB\r
-USBFS_USB__ARB_RW3_DR EQU CYREG_USB_ARB_RW3_DR\r
-USBFS_USB__ARB_RW3_RA EQU CYREG_USB_ARB_RW3_RA\r
-USBFS_USB__ARB_RW3_RA_MSB EQU CYREG_USB_ARB_RW3_RA_MSB\r
-USBFS_USB__ARB_RW3_WA EQU CYREG_USB_ARB_RW3_WA\r
-USBFS_USB__ARB_RW3_WA_MSB EQU CYREG_USB_ARB_RW3_WA_MSB\r
-USBFS_USB__ARB_RW4_DR EQU CYREG_USB_ARB_RW4_DR\r
-USBFS_USB__ARB_RW4_RA EQU CYREG_USB_ARB_RW4_RA\r
-USBFS_USB__ARB_RW4_RA_MSB EQU CYREG_USB_ARB_RW4_RA_MSB\r
-USBFS_USB__ARB_RW4_WA EQU CYREG_USB_ARB_RW4_WA\r
-USBFS_USB__ARB_RW4_WA_MSB EQU CYREG_USB_ARB_RW4_WA_MSB\r
-USBFS_USB__ARB_RW5_DR EQU CYREG_USB_ARB_RW5_DR\r
-USBFS_USB__ARB_RW5_RA EQU CYREG_USB_ARB_RW5_RA\r
-USBFS_USB__ARB_RW5_RA_MSB EQU CYREG_USB_ARB_RW5_RA_MSB\r
-USBFS_USB__ARB_RW5_WA EQU CYREG_USB_ARB_RW5_WA\r
-USBFS_USB__ARB_RW5_WA_MSB EQU CYREG_USB_ARB_RW5_WA_MSB\r
-USBFS_USB__ARB_RW6_DR EQU CYREG_USB_ARB_RW6_DR\r
-USBFS_USB__ARB_RW6_RA EQU CYREG_USB_ARB_RW6_RA\r
-USBFS_USB__ARB_RW6_RA_MSB EQU CYREG_USB_ARB_RW6_RA_MSB\r
-USBFS_USB__ARB_RW6_WA EQU CYREG_USB_ARB_RW6_WA\r
-USBFS_USB__ARB_RW6_WA_MSB EQU CYREG_USB_ARB_RW6_WA_MSB\r
-USBFS_USB__ARB_RW7_DR EQU CYREG_USB_ARB_RW7_DR\r
-USBFS_USB__ARB_RW7_RA EQU CYREG_USB_ARB_RW7_RA\r
-USBFS_USB__ARB_RW7_RA_MSB EQU CYREG_USB_ARB_RW7_RA_MSB\r
-USBFS_USB__ARB_RW7_WA EQU CYREG_USB_ARB_RW7_WA\r
-USBFS_USB__ARB_RW7_WA_MSB EQU CYREG_USB_ARB_RW7_WA_MSB\r
-USBFS_USB__ARB_RW8_DR EQU CYREG_USB_ARB_RW8_DR\r
-USBFS_USB__ARB_RW8_RA EQU CYREG_USB_ARB_RW8_RA\r
-USBFS_USB__ARB_RW8_RA_MSB EQU CYREG_USB_ARB_RW8_RA_MSB\r
-USBFS_USB__ARB_RW8_WA EQU CYREG_USB_ARB_RW8_WA\r
-USBFS_USB__ARB_RW8_WA_MSB EQU CYREG_USB_ARB_RW8_WA_MSB\r
-USBFS_USB__BUF_SIZE EQU CYREG_USB_BUF_SIZE\r
-USBFS_USB__BUS_RST_CNT EQU CYREG_USB_BUS_RST_CNT\r
-USBFS_USB__CR0 EQU CYREG_USB_CR0\r
-USBFS_USB__CR1 EQU CYREG_USB_CR1\r
-USBFS_USB__CWA EQU CYREG_USB_CWA\r
-USBFS_USB__CWA_MSB EQU CYREG_USB_CWA_MSB\r
-USBFS_USB__DMA_THRES EQU CYREG_USB_DMA_THRES\r
-USBFS_USB__DMA_THRES_MSB EQU CYREG_USB_DMA_THRES_MSB\r
-USBFS_USB__DYN_RECONFIG EQU CYREG_USB_DYN_RECONFIG\r
-USBFS_USB__EP_ACTIVE EQU CYREG_USB_EP_ACTIVE\r
-USBFS_USB__EP_TYPE EQU CYREG_USB_EP_TYPE\r
-USBFS_USB__EP0_CNT EQU CYREG_USB_EP0_CNT\r
-USBFS_USB__EP0_CR EQU CYREG_USB_EP0_CR\r
-USBFS_USB__EP0_DR0 EQU CYREG_USB_EP0_DR0\r
-USBFS_USB__EP0_DR1 EQU CYREG_USB_EP0_DR1\r
-USBFS_USB__EP0_DR2 EQU CYREG_USB_EP0_DR2\r
-USBFS_USB__EP0_DR3 EQU CYREG_USB_EP0_DR3\r
-USBFS_USB__EP0_DR4 EQU CYREG_USB_EP0_DR4\r
-USBFS_USB__EP0_DR5 EQU CYREG_USB_EP0_DR5\r
-USBFS_USB__EP0_DR6 EQU CYREG_USB_EP0_DR6\r
-USBFS_USB__EP0_DR7 EQU CYREG_USB_EP0_DR7\r
-USBFS_USB__MEM_DATA EQU CYREG_USB_MEM_DATA_MBASE\r
-USBFS_USB__PM_ACT_CFG EQU CYREG_PM_ACT_CFG5\r
-USBFS_USB__PM_ACT_MSK EQU 0x01\r
-USBFS_USB__PM_STBY_CFG EQU CYREG_PM_STBY_CFG5\r
-USBFS_USB__PM_STBY_MSK EQU 0x01\r
-USBFS_USB__SIE_EP_INT_EN EQU CYREG_USB_SIE_EP_INT_EN\r
-USBFS_USB__SIE_EP_INT_SR EQU CYREG_USB_SIE_EP_INT_SR\r
-USBFS_USB__SIE_EP1_CNT0 EQU CYREG_USB_SIE_EP1_CNT0\r
-USBFS_USB__SIE_EP1_CNT1 EQU CYREG_USB_SIE_EP1_CNT1\r
-USBFS_USB__SIE_EP1_CR0 EQU CYREG_USB_SIE_EP1_CR0\r
-USBFS_USB__SIE_EP2_CNT0 EQU CYREG_USB_SIE_EP2_CNT0\r
-USBFS_USB__SIE_EP2_CNT1 EQU CYREG_USB_SIE_EP2_CNT1\r
-USBFS_USB__SIE_EP2_CR0 EQU CYREG_USB_SIE_EP2_CR0\r
-USBFS_USB__SIE_EP3_CNT0 EQU CYREG_USB_SIE_EP3_CNT0\r
-USBFS_USB__SIE_EP3_CNT1 EQU CYREG_USB_SIE_EP3_CNT1\r
-USBFS_USB__SIE_EP3_CR0 EQU CYREG_USB_SIE_EP3_CR0\r
-USBFS_USB__SIE_EP4_CNT0 EQU CYREG_USB_SIE_EP4_CNT0\r
-USBFS_USB__SIE_EP4_CNT1 EQU CYREG_USB_SIE_EP4_CNT1\r
-USBFS_USB__SIE_EP4_CR0 EQU CYREG_USB_SIE_EP4_CR0\r
-USBFS_USB__SIE_EP5_CNT0 EQU CYREG_USB_SIE_EP5_CNT0\r
-USBFS_USB__SIE_EP5_CNT1 EQU CYREG_USB_SIE_EP5_CNT1\r
-USBFS_USB__SIE_EP5_CR0 EQU CYREG_USB_SIE_EP5_CR0\r
-USBFS_USB__SIE_EP6_CNT0 EQU CYREG_USB_SIE_EP6_CNT0\r
-USBFS_USB__SIE_EP6_CNT1 EQU CYREG_USB_SIE_EP6_CNT1\r
-USBFS_USB__SIE_EP6_CR0 EQU CYREG_USB_SIE_EP6_CR0\r
-USBFS_USB__SIE_EP7_CNT0 EQU CYREG_USB_SIE_EP7_CNT0\r
-USBFS_USB__SIE_EP7_CNT1 EQU CYREG_USB_SIE_EP7_CNT1\r
-USBFS_USB__SIE_EP7_CR0 EQU CYREG_USB_SIE_EP7_CR0\r
-USBFS_USB__SIE_EP8_CNT0 EQU CYREG_USB_SIE_EP8_CNT0\r
-USBFS_USB__SIE_EP8_CNT1 EQU CYREG_USB_SIE_EP8_CNT1\r
-USBFS_USB__SIE_EP8_CR0 EQU CYREG_USB_SIE_EP8_CR0\r
-USBFS_USB__SOF0 EQU CYREG_USB_SOF0\r
-USBFS_USB__SOF1 EQU CYREG_USB_SOF1\r
-USBFS_USB__USB_CLK_EN EQU CYREG_USB_USB_CLK_EN\r
-USBFS_USB__USBIO_CR0 EQU CYREG_USB_USBIO_CR0\r
-USBFS_USB__USBIO_CR1 EQU CYREG_USB_USBIO_CR1\r
-\r
-; SDCard_BSPIM\r
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL\r
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB04_05_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB04_05_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB04_05_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB04_05_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB04_05_MSK\r
-SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB04_05_MSK\r
-SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB04_05_MSK\r
-SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB04_05_MSK\r
-SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL\r
-SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB04_CTL\r
-SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB04_ST_CTL\r
-SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB04_CTL\r
-SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB04_ST_CTL\r
-SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL\r
-SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL\r
-SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB04_MSK\r
-SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL\r
-SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB04_05_ST\r
-SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB04_MSK\r
-SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL\r
-SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB04_ST_CTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB04_ST_CTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB04_ST\r
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB08_09_ACTL\r
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB08_09_ST\r
-SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10\r
-SDCard_BSPIM_RxStsReg__4__POS EQU 4\r
-SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20\r
-SDCard_BSPIM_RxStsReg__5__POS EQU 5\r
-SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40\r
-SDCard_BSPIM_RxStsReg__6__POS EQU 6\r
-SDCard_BSPIM_RxStsReg__MASK EQU 0x70\r
-SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB08_MSK\r
-SDCard_BSPIM_RxStsReg__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB08_MSK_ACTL\r
-SDCard_BSPIM_RxStsReg__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB08_MSK_ACTL\r
-SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB08_ACTL\r
-SDCard_BSPIM_RxStsReg__STATUS_CNT_REG EQU CYREG_B1_UDB08_ST_CTL\r
-SDCard_BSPIM_RxStsReg__STATUS_CONTROL_REG EQU CYREG_B1_UDB08_ST_CTL\r
-SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB08_ST\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB04_05_A0\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB04_05_A1\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B1_UDB04_05_D0\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B1_UDB04_05_D1\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B1_UDB04_05_F0\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B1_UDB04_05_F1\r
-SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B1_UDB04_A0_A1\r
-SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B1_UDB04_A0\r
-SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B1_UDB04_A1\r
-SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B1_UDB04_D0_D1\r
-SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B1_UDB04_D0\r
-SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B1_UDB04_D1\r
-SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL\r
-SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B1_UDB04_F0_F1\r
-SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B1_UDB04_F0\r
-SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B1_UDB04_F1\r
-SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL\r
-SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL\r
-SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01\r
-SDCard_BSPIM_TxStsReg__0__POS EQU 0\r
-SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02\r
-SDCard_BSPIM_TxStsReg__1__POS EQU 1\r
-SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL\r
-SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST\r
-SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04\r
-SDCard_BSPIM_TxStsReg__2__POS EQU 2\r
-SDCard_BSPIM_TxStsReg__3__MASK EQU 0x08\r
-SDCard_BSPIM_TxStsReg__3__POS EQU 3\r
-SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10\r
-SDCard_BSPIM_TxStsReg__4__POS EQU 4\r
-SDCard_BSPIM_TxStsReg__MASK EQU 0x1F\r
-SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB07_MSK\r
-SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL\r
-SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB07_ST\r
-\r
-; SD_SCK\r
-SD_SCK__0__INTTYPE EQU CYREG_PICU3_INTTYPE2\r
-SD_SCK__0__MASK EQU 0x04\r
-SD_SCK__0__PC EQU CYREG_PRT3_PC2\r
-SD_SCK__0__PORT EQU 3\r
-SD_SCK__0__SHIFT EQU 2\r
-SD_SCK__AG EQU CYREG_PRT3_AG\r
-SD_SCK__AMUX EQU CYREG_PRT3_AMUX\r
-SD_SCK__BIE EQU CYREG_PRT3_BIE\r
-SD_SCK__BIT_MASK EQU CYREG_PRT3_BIT_MASK\r
-SD_SCK__BYP EQU CYREG_PRT3_BYP\r
-SD_SCK__CTL EQU CYREG_PRT3_CTL\r
-SD_SCK__DM0 EQU CYREG_PRT3_DM0\r
-SD_SCK__DM1 EQU CYREG_PRT3_DM1\r
-SD_SCK__DM2 EQU CYREG_PRT3_DM2\r
-SD_SCK__DR EQU CYREG_PRT3_DR\r
-SD_SCK__INP_DIS EQU CYREG_PRT3_INP_DIS\r
-SD_SCK__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE\r
-SD_SCK__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG\r
-SD_SCK__LCD_EN EQU CYREG_PRT3_LCD_EN\r
-SD_SCK__MASK EQU 0x04\r
-SD_SCK__PORT EQU 3\r
-SD_SCK__PRT EQU CYREG_PRT3_PRT\r
-SD_SCK__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL\r
-SD_SCK__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN\r
-SD_SCK__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0\r
-SD_SCK__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1\r
-SD_SCK__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0\r
-SD_SCK__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1\r
-SD_SCK__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT\r
-SD_SCK__PS EQU CYREG_PRT3_PS\r
-SD_SCK__SHIFT EQU 2\r
-SD_SCK__SLW EQU CYREG_PRT3_SLW\r
-\r
-; SCSI_In\r
-SCSI_In__0__AG EQU CYREG_PRT2_AG\r
-SCSI_In__0__AMUX EQU CYREG_PRT2_AMUX\r
-SCSI_In__0__BIE EQU CYREG_PRT2_BIE\r
-SCSI_In__0__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
-SCSI_In__0__BYP EQU CYREG_PRT2_BYP\r
-SCSI_In__0__CTL EQU CYREG_PRT2_CTL\r
-SCSI_In__0__DM0 EQU CYREG_PRT2_DM0\r
-SCSI_In__0__DM1 EQU CYREG_PRT2_DM1\r
-SCSI_In__0__DM2 EQU CYREG_PRT2_DM2\r
-SCSI_In__0__DR EQU CYREG_PRT2_DR\r
-SCSI_In__0__INP_DIS EQU CYREG_PRT2_INP_DIS\r
-SCSI_In__0__INTTYPE EQU CYREG_PICU2_INTTYPE0\r
-SCSI_In__0__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
-SCSI_In__0__LCD_EN EQU CYREG_PRT2_LCD_EN\r
-SCSI_In__0__MASK EQU 0x01\r
-SCSI_In__0__PC EQU CYREG_PRT2_PC0\r
-SCSI_In__0__PORT EQU 2\r
-SCSI_In__0__PRT EQU CYREG_PRT2_PRT\r
-SCSI_In__0__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
-SCSI_In__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
-SCSI_In__0__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
-SCSI_In__0__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
-SCSI_In__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
-SCSI_In__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
-SCSI_In__0__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
-SCSI_In__0__PS EQU CYREG_PRT2_PS\r
-SCSI_In__0__SHIFT EQU 0\r
-SCSI_In__0__SLW EQU CYREG_PRT2_SLW\r
-SCSI_In__1__AG EQU CYREG_PRT6_AG\r
-SCSI_In__1__AMUX EQU CYREG_PRT6_AMUX\r
-SCSI_In__1__BIE EQU CYREG_PRT6_BIE\r
-SCSI_In__1__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
-SCSI_In__1__BYP EQU CYREG_PRT6_BYP\r
-SCSI_In__1__CTL EQU CYREG_PRT6_CTL\r
-SCSI_In__1__DM0 EQU CYREG_PRT6_DM0\r
-SCSI_In__1__DM1 EQU CYREG_PRT6_DM1\r
-SCSI_In__1__DM2 EQU CYREG_PRT6_DM2\r
-SCSI_In__1__DR EQU CYREG_PRT6_DR\r
-SCSI_In__1__INP_DIS EQU CYREG_PRT6_INP_DIS\r
-SCSI_In__1__INTTYPE EQU CYREG_PICU6_INTTYPE7\r
-SCSI_In__1__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
-SCSI_In__1__LCD_EN EQU CYREG_PRT6_LCD_EN\r
-SCSI_In__1__MASK EQU 0x80\r
-SCSI_In__1__PC EQU CYREG_PRT6_PC7\r
-SCSI_In__1__PORT EQU 6\r
-SCSI_In__1__PRT EQU CYREG_PRT6_PRT\r
-SCSI_In__1__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
-SCSI_In__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
-SCSI_In__1__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
-SCSI_In__1__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
-SCSI_In__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
-SCSI_In__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
-SCSI_In__1__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
-SCSI_In__1__PS EQU CYREG_PRT6_PS\r
-SCSI_In__1__SHIFT EQU 7\r
-SCSI_In__1__SLW EQU CYREG_PRT6_SLW\r
-SCSI_In__2__AG EQU CYREG_PRT5_AG\r
-SCSI_In__2__AMUX EQU CYREG_PRT5_AMUX\r
-SCSI_In__2__BIE EQU CYREG_PRT5_BIE\r
-SCSI_In__2__BIT_MASK EQU CYREG_PRT5_BIT_MASK\r
-SCSI_In__2__BYP EQU CYREG_PRT5_BYP\r
-SCSI_In__2__CTL EQU CYREG_PRT5_CTL\r
-SCSI_In__2__DM0 EQU CYREG_PRT5_DM0\r
-SCSI_In__2__DM1 EQU CYREG_PRT5_DM1\r
-SCSI_In__2__DM2 EQU CYREG_PRT5_DM2\r
-SCSI_In__2__DR EQU CYREG_PRT5_DR\r
-SCSI_In__2__INP_DIS EQU CYREG_PRT5_INP_DIS\r
-SCSI_In__2__INTTYPE EQU CYREG_PICU5_INTTYPE1\r
-SCSI_In__2__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG\r
-SCSI_In__2__LCD_EN EQU CYREG_PRT5_LCD_EN\r
-SCSI_In__2__MASK EQU 0x02\r
-SCSI_In__2__PC EQU CYREG_PRT5_PC1\r
-SCSI_In__2__PORT EQU 5\r
-SCSI_In__2__PRT EQU CYREG_PRT5_PRT\r
-SCSI_In__2__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL\r
-SCSI_In__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN\r
-SCSI_In__2__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0\r
-SCSI_In__2__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1\r
-SCSI_In__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0\r
-SCSI_In__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1\r
-SCSI_In__2__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT\r
-SCSI_In__2__PS EQU CYREG_PRT5_PS\r
-SCSI_In__2__SHIFT EQU 1\r
-SCSI_In__2__SLW EQU CYREG_PRT5_SLW\r
-SCSI_In__3__AG EQU CYREG_PRT5_AG\r
-SCSI_In__3__AMUX EQU CYREG_PRT5_AMUX\r
-SCSI_In__3__BIE EQU CYREG_PRT5_BIE\r
-SCSI_In__3__BIT_MASK EQU CYREG_PRT5_BIT_MASK\r
-SCSI_In__3__BYP EQU CYREG_PRT5_BYP\r
-SCSI_In__3__CTL EQU CYREG_PRT5_CTL\r
-SCSI_In__3__DM0 EQU CYREG_PRT5_DM0\r
-SCSI_In__3__DM1 EQU CYREG_PRT5_DM1\r
-SCSI_In__3__DM2 EQU CYREG_PRT5_DM2\r
-SCSI_In__3__DR EQU CYREG_PRT5_DR\r
-SCSI_In__3__INP_DIS EQU CYREG_PRT5_INP_DIS\r
-SCSI_In__3__INTTYPE EQU CYREG_PICU5_INTTYPE2\r
-SCSI_In__3__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG\r
-SCSI_In__3__LCD_EN EQU CYREG_PRT5_LCD_EN\r
-SCSI_In__3__MASK EQU 0x04\r
-SCSI_In__3__PC EQU CYREG_PRT5_PC2\r
-SCSI_In__3__PORT EQU 5\r
-SCSI_In__3__PRT EQU CYREG_PRT5_PRT\r
-SCSI_In__3__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL\r
-SCSI_In__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN\r
-SCSI_In__3__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0\r
-SCSI_In__3__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1\r
-SCSI_In__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0\r
-SCSI_In__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1\r
-SCSI_In__3__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT\r
-SCSI_In__3__PS EQU CYREG_PRT5_PS\r
-SCSI_In__3__SHIFT EQU 2\r
-SCSI_In__3__SLW EQU CYREG_PRT5_SLW\r
-SCSI_In__4__AG EQU CYREG_PRT5_AG\r
-SCSI_In__4__AMUX EQU CYREG_PRT5_AMUX\r
-SCSI_In__4__BIE EQU CYREG_PRT5_BIE\r
-SCSI_In__4__BIT_MASK EQU CYREG_PRT5_BIT_MASK\r
-SCSI_In__4__BYP EQU CYREG_PRT5_BYP\r
-SCSI_In__4__CTL EQU CYREG_PRT5_CTL\r
-SCSI_In__4__DM0 EQU CYREG_PRT5_DM0\r
-SCSI_In__4__DM1 EQU CYREG_PRT5_DM1\r
-SCSI_In__4__DM2 EQU CYREG_PRT5_DM2\r
-SCSI_In__4__DR EQU CYREG_PRT5_DR\r
-SCSI_In__4__INP_DIS EQU CYREG_PRT5_INP_DIS\r
-SCSI_In__4__INTTYPE EQU CYREG_PICU5_INTTYPE3\r
-SCSI_In__4__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG\r
-SCSI_In__4__LCD_EN EQU CYREG_PRT5_LCD_EN\r
-SCSI_In__4__MASK EQU 0x08\r
-SCSI_In__4__PC EQU CYREG_PRT5_PC3\r
-SCSI_In__4__PORT EQU 5\r
-SCSI_In__4__PRT EQU CYREG_PRT5_PRT\r
-SCSI_In__4__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL\r
-SCSI_In__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN\r
-SCSI_In__4__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0\r
-SCSI_In__4__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1\r
-SCSI_In__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0\r
-SCSI_In__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1\r
-SCSI_In__4__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT\r
-SCSI_In__4__PS EQU CYREG_PRT5_PS\r
-SCSI_In__4__SHIFT EQU 3\r
-SCSI_In__4__SLW EQU CYREG_PRT5_SLW\r
-SCSI_In__CD__AG EQU CYREG_PRT5_AG\r
-SCSI_In__CD__AMUX EQU CYREG_PRT5_AMUX\r
-SCSI_In__CD__BIE EQU CYREG_PRT5_BIE\r
-SCSI_In__CD__BIT_MASK EQU CYREG_PRT5_BIT_MASK\r
-SCSI_In__CD__BYP EQU CYREG_PRT5_BYP\r
-SCSI_In__CD__CTL EQU CYREG_PRT5_CTL\r
-SCSI_In__CD__DM0 EQU CYREG_PRT5_DM0\r
-SCSI_In__CD__DM1 EQU CYREG_PRT5_DM1\r
-SCSI_In__CD__DM2 EQU CYREG_PRT5_DM2\r
-SCSI_In__CD__DR EQU CYREG_PRT5_DR\r
-SCSI_In__CD__INP_DIS EQU CYREG_PRT5_INP_DIS\r
-SCSI_In__CD__INTTYPE EQU CYREG_PICU5_INTTYPE1\r
-SCSI_In__CD__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG\r
-SCSI_In__CD__LCD_EN EQU CYREG_PRT5_LCD_EN\r
-SCSI_In__CD__MASK EQU 0x02\r
-SCSI_In__CD__PC EQU CYREG_PRT5_PC1\r
-SCSI_In__CD__PORT EQU 5\r
-SCSI_In__CD__PRT EQU CYREG_PRT5_PRT\r
-SCSI_In__CD__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL\r
-SCSI_In__CD__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN\r
-SCSI_In__CD__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0\r
-SCSI_In__CD__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1\r
-SCSI_In__CD__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0\r
-SCSI_In__CD__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1\r
-SCSI_In__CD__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT\r
-SCSI_In__CD__PS EQU CYREG_PRT5_PS\r
-SCSI_In__CD__SHIFT EQU 1\r
-SCSI_In__CD__SLW EQU CYREG_PRT5_SLW\r
-SCSI_In__DBP__AG EQU CYREG_PRT2_AG\r
-SCSI_In__DBP__AMUX EQU CYREG_PRT2_AMUX\r
-SCSI_In__DBP__BIE EQU CYREG_PRT2_BIE\r
-SCSI_In__DBP__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
-SCSI_In__DBP__BYP EQU CYREG_PRT2_BYP\r
-SCSI_In__DBP__CTL EQU CYREG_PRT2_CTL\r
-SCSI_In__DBP__DM0 EQU CYREG_PRT2_DM0\r
-SCSI_In__DBP__DM1 EQU CYREG_PRT2_DM1\r
-SCSI_In__DBP__DM2 EQU CYREG_PRT2_DM2\r
-SCSI_In__DBP__DR EQU CYREG_PRT2_DR\r
-SCSI_In__DBP__INP_DIS EQU CYREG_PRT2_INP_DIS\r
-SCSI_In__DBP__INTTYPE EQU CYREG_PICU2_INTTYPE0\r
-SCSI_In__DBP__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
-SCSI_In__DBP__LCD_EN EQU CYREG_PRT2_LCD_EN\r
-SCSI_In__DBP__MASK EQU 0x01\r
-SCSI_In__DBP__PC EQU CYREG_PRT2_PC0\r
-SCSI_In__DBP__PORT EQU 2\r
-SCSI_In__DBP__PRT EQU CYREG_PRT2_PRT\r
-SCSI_In__DBP__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
-SCSI_In__DBP__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
-SCSI_In__DBP__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
-SCSI_In__DBP__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
-SCSI_In__DBP__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
-SCSI_In__DBP__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
-SCSI_In__DBP__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
-SCSI_In__DBP__PS EQU CYREG_PRT2_PS\r
-SCSI_In__DBP__SHIFT EQU 0\r
-SCSI_In__DBP__SLW EQU CYREG_PRT2_SLW\r
-SCSI_In__IO__AG EQU CYREG_PRT5_AG\r
-SCSI_In__IO__AMUX EQU CYREG_PRT5_AMUX\r
-SCSI_In__IO__BIE EQU CYREG_PRT5_BIE\r
-SCSI_In__IO__BIT_MASK EQU CYREG_PRT5_BIT_MASK\r
-SCSI_In__IO__BYP EQU CYREG_PRT5_BYP\r
-SCSI_In__IO__CTL EQU CYREG_PRT5_CTL\r
-SCSI_In__IO__DM0 EQU CYREG_PRT5_DM0\r
-SCSI_In__IO__DM1 EQU CYREG_PRT5_DM1\r
-SCSI_In__IO__DM2 EQU CYREG_PRT5_DM2\r
-SCSI_In__IO__DR EQU CYREG_PRT5_DR\r
-SCSI_In__IO__INP_DIS EQU CYREG_PRT5_INP_DIS\r
-SCSI_In__IO__INTTYPE EQU CYREG_PICU5_INTTYPE3\r
-SCSI_In__IO__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG\r
-SCSI_In__IO__LCD_EN EQU CYREG_PRT5_LCD_EN\r
-SCSI_In__IO__MASK EQU 0x08\r
-SCSI_In__IO__PC EQU CYREG_PRT5_PC3\r
-SCSI_In__IO__PORT EQU 5\r
-SCSI_In__IO__PRT EQU CYREG_PRT5_PRT\r
-SCSI_In__IO__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL\r
-SCSI_In__IO__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN\r
-SCSI_In__IO__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0\r
-SCSI_In__IO__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1\r
-SCSI_In__IO__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0\r
-SCSI_In__IO__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1\r
-SCSI_In__IO__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT\r
-SCSI_In__IO__PS EQU CYREG_PRT5_PS\r
-SCSI_In__IO__SHIFT EQU 3\r
-SCSI_In__IO__SLW EQU CYREG_PRT5_SLW\r
-SCSI_In__MSG__AG EQU CYREG_PRT6_AG\r
-SCSI_In__MSG__AMUX EQU CYREG_PRT6_AMUX\r
-SCSI_In__MSG__BIE EQU CYREG_PRT6_BIE\r
-SCSI_In__MSG__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
-SCSI_In__MSG__BYP EQU CYREG_PRT6_BYP\r
-SCSI_In__MSG__CTL EQU CYREG_PRT6_CTL\r
-SCSI_In__MSG__DM0 EQU CYREG_PRT6_DM0\r
-SCSI_In__MSG__DM1 EQU CYREG_PRT6_DM1\r
-SCSI_In__MSG__DM2 EQU CYREG_PRT6_DM2\r
-SCSI_In__MSG__DR EQU CYREG_PRT6_DR\r
-SCSI_In__MSG__INP_DIS EQU CYREG_PRT6_INP_DIS\r
-SCSI_In__MSG__INTTYPE EQU CYREG_PICU6_INTTYPE7\r
-SCSI_In__MSG__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
-SCSI_In__MSG__LCD_EN EQU CYREG_PRT6_LCD_EN\r
-SCSI_In__MSG__MASK EQU 0x80\r
-SCSI_In__MSG__PC EQU CYREG_PRT6_PC7\r
-SCSI_In__MSG__PORT EQU 6\r
-SCSI_In__MSG__PRT EQU CYREG_PRT6_PRT\r
-SCSI_In__MSG__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
-SCSI_In__MSG__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
-SCSI_In__MSG__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
-SCSI_In__MSG__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
-SCSI_In__MSG__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
-SCSI_In__MSG__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
-SCSI_In__MSG__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
-SCSI_In__MSG__PS EQU CYREG_PRT6_PS\r
-SCSI_In__MSG__SHIFT EQU 7\r
-SCSI_In__MSG__SLW EQU CYREG_PRT6_SLW\r
-SCSI_In__REQ__AG EQU CYREG_PRT5_AG\r
-SCSI_In__REQ__AMUX EQU CYREG_PRT5_AMUX\r
-SCSI_In__REQ__BIE EQU CYREG_PRT5_BIE\r
-SCSI_In__REQ__BIT_MASK EQU CYREG_PRT5_BIT_MASK\r
-SCSI_In__REQ__BYP EQU CYREG_PRT5_BYP\r
-SCSI_In__REQ__CTL EQU CYREG_PRT5_CTL\r
-SCSI_In__REQ__DM0 EQU CYREG_PRT5_DM0\r
-SCSI_In__REQ__DM1 EQU CYREG_PRT5_DM1\r
-SCSI_In__REQ__DM2 EQU CYREG_PRT5_DM2\r
-SCSI_In__REQ__DR EQU CYREG_PRT5_DR\r
-SCSI_In__REQ__INP_DIS EQU CYREG_PRT5_INP_DIS\r
-SCSI_In__REQ__INTTYPE EQU CYREG_PICU5_INTTYPE2\r
-SCSI_In__REQ__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG\r
-SCSI_In__REQ__LCD_EN EQU CYREG_PRT5_LCD_EN\r
-SCSI_In__REQ__MASK EQU 0x04\r
-SCSI_In__REQ__PC EQU CYREG_PRT5_PC2\r
-SCSI_In__REQ__PORT EQU 5\r
-SCSI_In__REQ__PRT EQU CYREG_PRT5_PRT\r
-SCSI_In__REQ__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL\r
-SCSI_In__REQ__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN\r
-SCSI_In__REQ__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0\r
-SCSI_In__REQ__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1\r
-SCSI_In__REQ__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0\r
-SCSI_In__REQ__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1\r
-SCSI_In__REQ__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT\r
-SCSI_In__REQ__PS EQU CYREG_PRT5_PS\r
-SCSI_In__REQ__SHIFT EQU 2\r
-SCSI_In__REQ__SLW EQU CYREG_PRT5_SLW\r
-\r
-; SCSI_In_DBx\r
-SCSI_In_DBx__0__AG EQU CYREG_PRT12_AG\r
-SCSI_In_DBx__0__BIE EQU CYREG_PRT12_BIE\r
-SCSI_In_DBx__0__BIT_MASK EQU CYREG_PRT12_BIT_MASK\r
-SCSI_In_DBx__0__BYP EQU CYREG_PRT12_BYP\r
-SCSI_In_DBx__0__DM0 EQU CYREG_PRT12_DM0\r
-SCSI_In_DBx__0__DM1 EQU CYREG_PRT12_DM1\r
-SCSI_In_DBx__0__DM2 EQU CYREG_PRT12_DM2\r
-SCSI_In_DBx__0__DR EQU CYREG_PRT12_DR\r
-SCSI_In_DBx__0__INP_DIS EQU CYREG_PRT12_INP_DIS\r
-SCSI_In_DBx__0__INTTYPE EQU CYREG_PICU12_INTTYPE4\r
-SCSI_In_DBx__0__MASK EQU 0x10\r
-SCSI_In_DBx__0__PC EQU CYREG_PRT12_PC4\r
-SCSI_In_DBx__0__PORT EQU 12\r
-SCSI_In_DBx__0__PRT EQU CYREG_PRT12_PRT\r
-SCSI_In_DBx__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN\r
-SCSI_In_DBx__0__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0\r
-SCSI_In_DBx__0__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1\r
-SCSI_In_DBx__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0\r
-SCSI_In_DBx__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1\r
-SCSI_In_DBx__0__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT\r
-SCSI_In_DBx__0__PS EQU CYREG_PRT12_PS\r
-SCSI_In_DBx__0__SHIFT EQU 4\r
-SCSI_In_DBx__0__SIO_CFG EQU CYREG_PRT12_SIO_CFG\r
-SCSI_In_DBx__0__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF\r
-SCSI_In_DBx__0__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN\r
-SCSI_In_DBx__0__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ\r
-SCSI_In_DBx__0__SLW EQU CYREG_PRT12_SLW\r
-SCSI_In_DBx__1__AG EQU CYREG_PRT2_AG\r
-SCSI_In_DBx__1__AMUX EQU CYREG_PRT2_AMUX\r
-SCSI_In_DBx__1__BIE EQU CYREG_PRT2_BIE\r
-SCSI_In_DBx__1__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
-SCSI_In_DBx__1__BYP EQU CYREG_PRT2_BYP\r
-SCSI_In_DBx__1__CTL EQU CYREG_PRT2_CTL\r
-SCSI_In_DBx__1__DM0 EQU CYREG_PRT2_DM0\r
-SCSI_In_DBx__1__DM1 EQU CYREG_PRT2_DM1\r
-SCSI_In_DBx__1__DM2 EQU CYREG_PRT2_DM2\r
-SCSI_In_DBx__1__DR EQU CYREG_PRT2_DR\r
-SCSI_In_DBx__1__INP_DIS EQU CYREG_PRT2_INP_DIS\r
-SCSI_In_DBx__1__INTTYPE EQU CYREG_PICU2_INTTYPE7\r
-SCSI_In_DBx__1__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
-SCSI_In_DBx__1__LCD_EN EQU CYREG_PRT2_LCD_EN\r
-SCSI_In_DBx__1__MASK EQU 0x80\r
-SCSI_In_DBx__1__PC EQU CYREG_PRT2_PC7\r
-SCSI_In_DBx__1__PORT EQU 2\r
-SCSI_In_DBx__1__PRT EQU CYREG_PRT2_PRT\r
-SCSI_In_DBx__1__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
-SCSI_In_DBx__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
-SCSI_In_DBx__1__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
-SCSI_In_DBx__1__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
-SCSI_In_DBx__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
-SCSI_In_DBx__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
-SCSI_In_DBx__1__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
-SCSI_In_DBx__1__PS EQU CYREG_PRT2_PS\r
-SCSI_In_DBx__1__SHIFT EQU 7\r
-SCSI_In_DBx__1__SLW EQU CYREG_PRT2_SLW\r
-SCSI_In_DBx__2__AG EQU CYREG_PRT2_AG\r
-SCSI_In_DBx__2__AMUX EQU CYREG_PRT2_AMUX\r
-SCSI_In_DBx__2__BIE EQU CYREG_PRT2_BIE\r
-SCSI_In_DBx__2__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
-SCSI_In_DBx__2__BYP EQU CYREG_PRT2_BYP\r
-SCSI_In_DBx__2__CTL EQU CYREG_PRT2_CTL\r
-SCSI_In_DBx__2__DM0 EQU CYREG_PRT2_DM0\r
-SCSI_In_DBx__2__DM1 EQU CYREG_PRT2_DM1\r
-SCSI_In_DBx__2__DM2 EQU CYREG_PRT2_DM2\r
-SCSI_In_DBx__2__DR EQU CYREG_PRT2_DR\r
-SCSI_In_DBx__2__INP_DIS EQU CYREG_PRT2_INP_DIS\r
-SCSI_In_DBx__2__INTTYPE EQU CYREG_PICU2_INTTYPE6\r
-SCSI_In_DBx__2__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
-SCSI_In_DBx__2__LCD_EN EQU CYREG_PRT2_LCD_EN\r
-SCSI_In_DBx__2__MASK EQU 0x40\r
-SCSI_In_DBx__2__PC EQU CYREG_PRT2_PC6\r
-SCSI_In_DBx__2__PORT EQU 2\r
-SCSI_In_DBx__2__PRT EQU CYREG_PRT2_PRT\r
-SCSI_In_DBx__2__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
-SCSI_In_DBx__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
-SCSI_In_DBx__2__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
-SCSI_In_DBx__2__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
-SCSI_In_DBx__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
-SCSI_In_DBx__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
-SCSI_In_DBx__2__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
-SCSI_In_DBx__2__PS EQU CYREG_PRT2_PS\r
-SCSI_In_DBx__2__SHIFT EQU 6\r
-SCSI_In_DBx__2__SLW EQU CYREG_PRT2_SLW\r
-SCSI_In_DBx__3__AG EQU CYREG_PRT2_AG\r
-SCSI_In_DBx__3__AMUX EQU CYREG_PRT2_AMUX\r
-SCSI_In_DBx__3__BIE EQU CYREG_PRT2_BIE\r
-SCSI_In_DBx__3__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
-SCSI_In_DBx__3__BYP EQU CYREG_PRT2_BYP\r
-SCSI_In_DBx__3__CTL EQU CYREG_PRT2_CTL\r
-SCSI_In_DBx__3__DM0 EQU CYREG_PRT2_DM0\r
-SCSI_In_DBx__3__DM1 EQU CYREG_PRT2_DM1\r
-SCSI_In_DBx__3__DM2 EQU CYREG_PRT2_DM2\r
-SCSI_In_DBx__3__DR EQU CYREG_PRT2_DR\r
-SCSI_In_DBx__3__INP_DIS EQU CYREG_PRT2_INP_DIS\r
-SCSI_In_DBx__3__INTTYPE EQU CYREG_PICU2_INTTYPE5\r
-SCSI_In_DBx__3__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
-SCSI_In_DBx__3__LCD_EN EQU CYREG_PRT2_LCD_EN\r
-SCSI_In_DBx__3__MASK EQU 0x20\r
-SCSI_In_DBx__3__PC EQU CYREG_PRT2_PC5\r
-SCSI_In_DBx__3__PORT EQU 2\r
-SCSI_In_DBx__3__PRT EQU CYREG_PRT2_PRT\r
-SCSI_In_DBx__3__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
-SCSI_In_DBx__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
-SCSI_In_DBx__3__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
-SCSI_In_DBx__3__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
-SCSI_In_DBx__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
-SCSI_In_DBx__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
-SCSI_In_DBx__3__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
-SCSI_In_DBx__3__PS EQU CYREG_PRT2_PS\r
-SCSI_In_DBx__3__SHIFT EQU 5\r
-SCSI_In_DBx__3__SLW EQU CYREG_PRT2_SLW\r
-SCSI_In_DBx__4__AG EQU CYREG_PRT2_AG\r
-SCSI_In_DBx__4__AMUX EQU CYREG_PRT2_AMUX\r
-SCSI_In_DBx__4__BIE EQU CYREG_PRT2_BIE\r
-SCSI_In_DBx__4__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
-SCSI_In_DBx__4__BYP EQU CYREG_PRT2_BYP\r
-SCSI_In_DBx__4__CTL EQU CYREG_PRT2_CTL\r
-SCSI_In_DBx__4__DM0 EQU CYREG_PRT2_DM0\r
-SCSI_In_DBx__4__DM1 EQU CYREG_PRT2_DM1\r
-SCSI_In_DBx__4__DM2 EQU CYREG_PRT2_DM2\r
-SCSI_In_DBx__4__DR EQU CYREG_PRT2_DR\r
-SCSI_In_DBx__4__INP_DIS EQU CYREG_PRT2_INP_DIS\r
-SCSI_In_DBx__4__INTTYPE EQU CYREG_PICU2_INTTYPE4\r
-SCSI_In_DBx__4__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
-SCSI_In_DBx__4__LCD_EN EQU CYREG_PRT2_LCD_EN\r
-SCSI_In_DBx__4__MASK EQU 0x10\r
-SCSI_In_DBx__4__PC EQU CYREG_PRT2_PC4\r
-SCSI_In_DBx__4__PORT EQU 2\r
-SCSI_In_DBx__4__PRT EQU CYREG_PRT2_PRT\r
-SCSI_In_DBx__4__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
-SCSI_In_DBx__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
-SCSI_In_DBx__4__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
-SCSI_In_DBx__4__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
-SCSI_In_DBx__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
-SCSI_In_DBx__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
-SCSI_In_DBx__4__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
-SCSI_In_DBx__4__PS EQU CYREG_PRT2_PS\r
-SCSI_In_DBx__4__SHIFT EQU 4\r
-SCSI_In_DBx__4__SLW EQU CYREG_PRT2_SLW\r
-SCSI_In_DBx__5__AG EQU CYREG_PRT2_AG\r
-SCSI_In_DBx__5__AMUX EQU CYREG_PRT2_AMUX\r
-SCSI_In_DBx__5__BIE EQU CYREG_PRT2_BIE\r
-SCSI_In_DBx__5__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
-SCSI_In_DBx__5__BYP EQU CYREG_PRT2_BYP\r
-SCSI_In_DBx__5__CTL EQU CYREG_PRT2_CTL\r
-SCSI_In_DBx__5__DM0 EQU CYREG_PRT2_DM0\r
-SCSI_In_DBx__5__DM1 EQU CYREG_PRT2_DM1\r
-SCSI_In_DBx__5__DM2 EQU CYREG_PRT2_DM2\r
-SCSI_In_DBx__5__DR EQU CYREG_PRT2_DR\r
-SCSI_In_DBx__5__INP_DIS EQU CYREG_PRT2_INP_DIS\r
-SCSI_In_DBx__5__INTTYPE EQU CYREG_PICU2_INTTYPE3\r
-SCSI_In_DBx__5__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
-SCSI_In_DBx__5__LCD_EN EQU CYREG_PRT2_LCD_EN\r
-SCSI_In_DBx__5__MASK EQU 0x08\r
-SCSI_In_DBx__5__PC EQU CYREG_PRT2_PC3\r
-SCSI_In_DBx__5__PORT EQU 2\r
-SCSI_In_DBx__5__PRT EQU CYREG_PRT2_PRT\r
-SCSI_In_DBx__5__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
-SCSI_In_DBx__5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
-SCSI_In_DBx__5__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
-SCSI_In_DBx__5__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
-SCSI_In_DBx__5__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
-SCSI_In_DBx__5__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
-SCSI_In_DBx__5__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
-SCSI_In_DBx__5__PS EQU CYREG_PRT2_PS\r
-SCSI_In_DBx__5__SHIFT EQU 3\r
-SCSI_In_DBx__5__SLW EQU CYREG_PRT2_SLW\r
-SCSI_In_DBx__6__AG EQU CYREG_PRT2_AG\r
-SCSI_In_DBx__6__AMUX EQU CYREG_PRT2_AMUX\r
-SCSI_In_DBx__6__BIE EQU CYREG_PRT2_BIE\r
-SCSI_In_DBx__6__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
-SCSI_In_DBx__6__BYP EQU CYREG_PRT2_BYP\r
-SCSI_In_DBx__6__CTL EQU CYREG_PRT2_CTL\r
-SCSI_In_DBx__6__DM0 EQU CYREG_PRT2_DM0\r
-SCSI_In_DBx__6__DM1 EQU CYREG_PRT2_DM1\r
-SCSI_In_DBx__6__DM2 EQU CYREG_PRT2_DM2\r
-SCSI_In_DBx__6__DR EQU CYREG_PRT2_DR\r
-SCSI_In_DBx__6__INP_DIS EQU CYREG_PRT2_INP_DIS\r
-SCSI_In_DBx__6__INTTYPE EQU CYREG_PICU2_INTTYPE2\r
-SCSI_In_DBx__6__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
-SCSI_In_DBx__6__LCD_EN EQU CYREG_PRT2_LCD_EN\r
-SCSI_In_DBx__6__MASK EQU 0x04\r
-SCSI_In_DBx__6__PC EQU CYREG_PRT2_PC2\r
-SCSI_In_DBx__6__PORT EQU 2\r
-SCSI_In_DBx__6__PRT EQU CYREG_PRT2_PRT\r
-SCSI_In_DBx__6__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
-SCSI_In_DBx__6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
-SCSI_In_DBx__6__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
-SCSI_In_DBx__6__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
-SCSI_In_DBx__6__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
-SCSI_In_DBx__6__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
-SCSI_In_DBx__6__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
-SCSI_In_DBx__6__PS EQU CYREG_PRT2_PS\r
-SCSI_In_DBx__6__SHIFT EQU 2\r
-SCSI_In_DBx__6__SLW EQU CYREG_PRT2_SLW\r
-SCSI_In_DBx__7__AG EQU CYREG_PRT2_AG\r
-SCSI_In_DBx__7__AMUX EQU CYREG_PRT2_AMUX\r
-SCSI_In_DBx__7__BIE EQU CYREG_PRT2_BIE\r
-SCSI_In_DBx__7__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
-SCSI_In_DBx__7__BYP EQU CYREG_PRT2_BYP\r
-SCSI_In_DBx__7__CTL EQU CYREG_PRT2_CTL\r
-SCSI_In_DBx__7__DM0 EQU CYREG_PRT2_DM0\r
-SCSI_In_DBx__7__DM1 EQU CYREG_PRT2_DM1\r
-SCSI_In_DBx__7__DM2 EQU CYREG_PRT2_DM2\r
-SCSI_In_DBx__7__DR EQU CYREG_PRT2_DR\r
-SCSI_In_DBx__7__INP_DIS EQU CYREG_PRT2_INP_DIS\r
-SCSI_In_DBx__7__INTTYPE EQU CYREG_PICU2_INTTYPE1\r
-SCSI_In_DBx__7__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
-SCSI_In_DBx__7__LCD_EN EQU CYREG_PRT2_LCD_EN\r
-SCSI_In_DBx__7__MASK EQU 0x02\r
-SCSI_In_DBx__7__PC EQU CYREG_PRT2_PC1\r
-SCSI_In_DBx__7__PORT EQU 2\r
-SCSI_In_DBx__7__PRT EQU CYREG_PRT2_PRT\r
-SCSI_In_DBx__7__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
-SCSI_In_DBx__7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
-SCSI_In_DBx__7__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
-SCSI_In_DBx__7__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
-SCSI_In_DBx__7__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
-SCSI_In_DBx__7__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
-SCSI_In_DBx__7__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
-SCSI_In_DBx__7__PS EQU CYREG_PRT2_PS\r
-SCSI_In_DBx__7__SHIFT EQU 1\r
-SCSI_In_DBx__7__SLW EQU CYREG_PRT2_SLW\r
-SCSI_In_DBx__DB0__AG EQU CYREG_PRT12_AG\r
-SCSI_In_DBx__DB0__BIE EQU CYREG_PRT12_BIE\r
-SCSI_In_DBx__DB0__BIT_MASK EQU CYREG_PRT12_BIT_MASK\r
-SCSI_In_DBx__DB0__BYP EQU CYREG_PRT12_BYP\r
-SCSI_In_DBx__DB0__DM0 EQU CYREG_PRT12_DM0\r
-SCSI_In_DBx__DB0__DM1 EQU CYREG_PRT12_DM1\r
-SCSI_In_DBx__DB0__DM2 EQU CYREG_PRT12_DM2\r
-SCSI_In_DBx__DB0__DR EQU CYREG_PRT12_DR\r
-SCSI_In_DBx__DB0__INP_DIS EQU CYREG_PRT12_INP_DIS\r
-SCSI_In_DBx__DB0__INTTYPE EQU CYREG_PICU12_INTTYPE4\r
-SCSI_In_DBx__DB0__MASK EQU 0x10\r
-SCSI_In_DBx__DB0__PC EQU CYREG_PRT12_PC4\r
-SCSI_In_DBx__DB0__PORT EQU 12\r
-SCSI_In_DBx__DB0__PRT EQU CYREG_PRT12_PRT\r
-SCSI_In_DBx__DB0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN\r
-SCSI_In_DBx__DB0__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0\r
-SCSI_In_DBx__DB0__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1\r
-SCSI_In_DBx__DB0__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0\r
-SCSI_In_DBx__DB0__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1\r
-SCSI_In_DBx__DB0__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT\r
-SCSI_In_DBx__DB0__PS EQU CYREG_PRT12_PS\r
-SCSI_In_DBx__DB0__SHIFT EQU 4\r
-SCSI_In_DBx__DB0__SIO_CFG EQU CYREG_PRT12_SIO_CFG\r
-SCSI_In_DBx__DB0__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF\r
-SCSI_In_DBx__DB0__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN\r
-SCSI_In_DBx__DB0__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ\r
-SCSI_In_DBx__DB0__SLW EQU CYREG_PRT12_SLW\r
-SCSI_In_DBx__DB1__AG EQU CYREG_PRT2_AG\r
-SCSI_In_DBx__DB1__AMUX EQU CYREG_PRT2_AMUX\r
-SCSI_In_DBx__DB1__BIE EQU CYREG_PRT2_BIE\r
-SCSI_In_DBx__DB1__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
-SCSI_In_DBx__DB1__BYP EQU CYREG_PRT2_BYP\r
-SCSI_In_DBx__DB1__CTL EQU CYREG_PRT2_CTL\r
-SCSI_In_DBx__DB1__DM0 EQU CYREG_PRT2_DM0\r
-SCSI_In_DBx__DB1__DM1 EQU CYREG_PRT2_DM1\r
-SCSI_In_DBx__DB1__DM2 EQU CYREG_PRT2_DM2\r
-SCSI_In_DBx__DB1__DR EQU CYREG_PRT2_DR\r
-SCSI_In_DBx__DB1__INP_DIS EQU CYREG_PRT2_INP_DIS\r
-SCSI_In_DBx__DB1__INTTYPE EQU CYREG_PICU2_INTTYPE7\r
-SCSI_In_DBx__DB1__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
-SCSI_In_DBx__DB1__LCD_EN EQU CYREG_PRT2_LCD_EN\r
-SCSI_In_DBx__DB1__MASK EQU 0x80\r
-SCSI_In_DBx__DB1__PC EQU CYREG_PRT2_PC7\r
-SCSI_In_DBx__DB1__PORT EQU 2\r
-SCSI_In_DBx__DB1__PRT EQU CYREG_PRT2_PRT\r
-SCSI_In_DBx__DB1__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
-SCSI_In_DBx__DB1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
-SCSI_In_DBx__DB1__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
-SCSI_In_DBx__DB1__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
-SCSI_In_DBx__DB1__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
-SCSI_In_DBx__DB1__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
-SCSI_In_DBx__DB1__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
-SCSI_In_DBx__DB1__PS EQU CYREG_PRT2_PS\r
-SCSI_In_DBx__DB1__SHIFT EQU 7\r
-SCSI_In_DBx__DB1__SLW EQU CYREG_PRT2_SLW\r
-SCSI_In_DBx__DB2__AG EQU CYREG_PRT2_AG\r
-SCSI_In_DBx__DB2__AMUX EQU CYREG_PRT2_AMUX\r
-SCSI_In_DBx__DB2__BIE EQU CYREG_PRT2_BIE\r
-SCSI_In_DBx__DB2__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
-SCSI_In_DBx__DB2__BYP EQU CYREG_PRT2_BYP\r
-SCSI_In_DBx__DB2__CTL EQU CYREG_PRT2_CTL\r
-SCSI_In_DBx__DB2__DM0 EQU CYREG_PRT2_DM0\r
-SCSI_In_DBx__DB2__DM1 EQU CYREG_PRT2_DM1\r
-SCSI_In_DBx__DB2__DM2 EQU CYREG_PRT2_DM2\r
-SCSI_In_DBx__DB2__DR EQU CYREG_PRT2_DR\r
-SCSI_In_DBx__DB2__INP_DIS EQU CYREG_PRT2_INP_DIS\r
-SCSI_In_DBx__DB2__INTTYPE EQU CYREG_PICU2_INTTYPE6\r
-SCSI_In_DBx__DB2__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
-SCSI_In_DBx__DB2__LCD_EN EQU CYREG_PRT2_LCD_EN\r
-SCSI_In_DBx__DB2__MASK EQU 0x40\r
-SCSI_In_DBx__DB2__PC EQU CYREG_PRT2_PC6\r
-SCSI_In_DBx__DB2__PORT EQU 2\r
-SCSI_In_DBx__DB2__PRT EQU CYREG_PRT2_PRT\r
-SCSI_In_DBx__DB2__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
-SCSI_In_DBx__DB2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
-SCSI_In_DBx__DB2__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
-SCSI_In_DBx__DB2__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
-SCSI_In_DBx__DB2__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
-SCSI_In_DBx__DB2__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
-SCSI_In_DBx__DB2__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
-SCSI_In_DBx__DB2__PS EQU CYREG_PRT2_PS\r
-SCSI_In_DBx__DB2__SHIFT EQU 6\r
-SCSI_In_DBx__DB2__SLW EQU CYREG_PRT2_SLW\r
-SCSI_In_DBx__DB3__AG EQU CYREG_PRT2_AG\r
-SCSI_In_DBx__DB3__AMUX EQU CYREG_PRT2_AMUX\r
-SCSI_In_DBx__DB3__BIE EQU CYREG_PRT2_BIE\r
-SCSI_In_DBx__DB3__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
-SCSI_In_DBx__DB3__BYP EQU CYREG_PRT2_BYP\r
-SCSI_In_DBx__DB3__CTL EQU CYREG_PRT2_CTL\r
-SCSI_In_DBx__DB3__DM0 EQU CYREG_PRT2_DM0\r
-SCSI_In_DBx__DB3__DM1 EQU CYREG_PRT2_DM1\r
-SCSI_In_DBx__DB3__DM2 EQU CYREG_PRT2_DM2\r
-SCSI_In_DBx__DB3__DR EQU CYREG_PRT2_DR\r
-SCSI_In_DBx__DB3__INP_DIS EQU CYREG_PRT2_INP_DIS\r
-SCSI_In_DBx__DB3__INTTYPE EQU CYREG_PICU2_INTTYPE5\r
-SCSI_In_DBx__DB3__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
-SCSI_In_DBx__DB3__LCD_EN EQU CYREG_PRT2_LCD_EN\r
-SCSI_In_DBx__DB3__MASK EQU 0x20\r
-SCSI_In_DBx__DB3__PC EQU CYREG_PRT2_PC5\r
-SCSI_In_DBx__DB3__PORT EQU 2\r
-SCSI_In_DBx__DB3__PRT EQU CYREG_PRT2_PRT\r
-SCSI_In_DBx__DB3__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
-SCSI_In_DBx__DB3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
-SCSI_In_DBx__DB3__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
-SCSI_In_DBx__DB3__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
-SCSI_In_DBx__DB3__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
-SCSI_In_DBx__DB3__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
-SCSI_In_DBx__DB3__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
-SCSI_In_DBx__DB3__PS EQU CYREG_PRT2_PS\r
-SCSI_In_DBx__DB3__SHIFT EQU 5\r
-SCSI_In_DBx__DB3__SLW EQU CYREG_PRT2_SLW\r
-SCSI_In_DBx__DB4__AG EQU CYREG_PRT2_AG\r
-SCSI_In_DBx__DB4__AMUX EQU CYREG_PRT2_AMUX\r
-SCSI_In_DBx__DB4__BIE EQU CYREG_PRT2_BIE\r
-SCSI_In_DBx__DB4__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
-SCSI_In_DBx__DB4__BYP EQU CYREG_PRT2_BYP\r
-SCSI_In_DBx__DB4__CTL EQU CYREG_PRT2_CTL\r
-SCSI_In_DBx__DB4__DM0 EQU CYREG_PRT2_DM0\r
-SCSI_In_DBx__DB4__DM1 EQU CYREG_PRT2_DM1\r
-SCSI_In_DBx__DB4__DM2 EQU CYREG_PRT2_DM2\r
-SCSI_In_DBx__DB4__DR EQU CYREG_PRT2_DR\r
-SCSI_In_DBx__DB4__INP_DIS EQU CYREG_PRT2_INP_DIS\r
-SCSI_In_DBx__DB4__INTTYPE EQU CYREG_PICU2_INTTYPE4\r
-SCSI_In_DBx__DB4__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
-SCSI_In_DBx__DB4__LCD_EN EQU CYREG_PRT2_LCD_EN\r
-SCSI_In_DBx__DB4__MASK EQU 0x10\r
-SCSI_In_DBx__DB4__PC EQU CYREG_PRT2_PC4\r
-SCSI_In_DBx__DB4__PORT EQU 2\r
-SCSI_In_DBx__DB4__PRT EQU CYREG_PRT2_PRT\r
-SCSI_In_DBx__DB4__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
-SCSI_In_DBx__DB4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
-SCSI_In_DBx__DB4__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
-SCSI_In_DBx__DB4__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
-SCSI_In_DBx__DB4__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
-SCSI_In_DBx__DB4__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
-SCSI_In_DBx__DB4__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
-SCSI_In_DBx__DB4__PS EQU CYREG_PRT2_PS\r
-SCSI_In_DBx__DB4__SHIFT EQU 4\r
-SCSI_In_DBx__DB4__SLW EQU CYREG_PRT2_SLW\r
-SCSI_In_DBx__DB5__AG EQU CYREG_PRT2_AG\r
-SCSI_In_DBx__DB5__AMUX EQU CYREG_PRT2_AMUX\r
-SCSI_In_DBx__DB5__BIE EQU CYREG_PRT2_BIE\r
-SCSI_In_DBx__DB5__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
-SCSI_In_DBx__DB5__BYP EQU CYREG_PRT2_BYP\r
-SCSI_In_DBx__DB5__CTL EQU CYREG_PRT2_CTL\r
-SCSI_In_DBx__DB5__DM0 EQU CYREG_PRT2_DM0\r
-SCSI_In_DBx__DB5__DM1 EQU CYREG_PRT2_DM1\r
-SCSI_In_DBx__DB5__DM2 EQU CYREG_PRT2_DM2\r
-SCSI_In_DBx__DB5__DR EQU CYREG_PRT2_DR\r
-SCSI_In_DBx__DB5__INP_DIS EQU CYREG_PRT2_INP_DIS\r
-SCSI_In_DBx__DB5__INTTYPE EQU CYREG_PICU2_INTTYPE3\r
-SCSI_In_DBx__DB5__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
-SCSI_In_DBx__DB5__LCD_EN EQU CYREG_PRT2_LCD_EN\r
-SCSI_In_DBx__DB5__MASK EQU 0x08\r
-SCSI_In_DBx__DB5__PC EQU CYREG_PRT2_PC3\r
-SCSI_In_DBx__DB5__PORT EQU 2\r
-SCSI_In_DBx__DB5__PRT EQU CYREG_PRT2_PRT\r
-SCSI_In_DBx__DB5__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
-SCSI_In_DBx__DB5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
-SCSI_In_DBx__DB5__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
-SCSI_In_DBx__DB5__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
-SCSI_In_DBx__DB5__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
-SCSI_In_DBx__DB5__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
-SCSI_In_DBx__DB5__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
-SCSI_In_DBx__DB5__PS EQU CYREG_PRT2_PS\r
-SCSI_In_DBx__DB5__SHIFT EQU 3\r
-SCSI_In_DBx__DB5__SLW EQU CYREG_PRT2_SLW\r
-SCSI_In_DBx__DB6__AG EQU CYREG_PRT2_AG\r
-SCSI_In_DBx__DB6__AMUX EQU CYREG_PRT2_AMUX\r
-SCSI_In_DBx__DB6__BIE EQU CYREG_PRT2_BIE\r
-SCSI_In_DBx__DB6__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
-SCSI_In_DBx__DB6__BYP EQU CYREG_PRT2_BYP\r
-SCSI_In_DBx__DB6__CTL EQU CYREG_PRT2_CTL\r
-SCSI_In_DBx__DB6__DM0 EQU CYREG_PRT2_DM0\r
-SCSI_In_DBx__DB6__DM1 EQU CYREG_PRT2_DM1\r
-SCSI_In_DBx__DB6__DM2 EQU CYREG_PRT2_DM2\r
-SCSI_In_DBx__DB6__DR EQU CYREG_PRT2_DR\r
-SCSI_In_DBx__DB6__INP_DIS EQU CYREG_PRT2_INP_DIS\r
-SCSI_In_DBx__DB6__INTTYPE EQU CYREG_PICU2_INTTYPE2\r
-SCSI_In_DBx__DB6__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
-SCSI_In_DBx__DB6__LCD_EN EQU CYREG_PRT2_LCD_EN\r
-SCSI_In_DBx__DB6__MASK EQU 0x04\r
-SCSI_In_DBx__DB6__PC EQU CYREG_PRT2_PC2\r
-SCSI_In_DBx__DB6__PORT EQU 2\r
-SCSI_In_DBx__DB6__PRT EQU CYREG_PRT2_PRT\r
-SCSI_In_DBx__DB6__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
-SCSI_In_DBx__DB6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
-SCSI_In_DBx__DB6__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
-SCSI_In_DBx__DB6__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
-SCSI_In_DBx__DB6__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
-SCSI_In_DBx__DB6__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
-SCSI_In_DBx__DB6__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
-SCSI_In_DBx__DB6__PS EQU CYREG_PRT2_PS\r
-SCSI_In_DBx__DB6__SHIFT EQU 2\r
-SCSI_In_DBx__DB6__SLW EQU CYREG_PRT2_SLW\r
-SCSI_In_DBx__DB7__AG EQU CYREG_PRT2_AG\r
-SCSI_In_DBx__DB7__AMUX EQU CYREG_PRT2_AMUX\r
-SCSI_In_DBx__DB7__BIE EQU CYREG_PRT2_BIE\r
-SCSI_In_DBx__DB7__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
-SCSI_In_DBx__DB7__BYP EQU CYREG_PRT2_BYP\r
-SCSI_In_DBx__DB7__CTL EQU CYREG_PRT2_CTL\r
-SCSI_In_DBx__DB7__DM0 EQU CYREG_PRT2_DM0\r
-SCSI_In_DBx__DB7__DM1 EQU CYREG_PRT2_DM1\r
-SCSI_In_DBx__DB7__DM2 EQU CYREG_PRT2_DM2\r
-SCSI_In_DBx__DB7__DR EQU CYREG_PRT2_DR\r
-SCSI_In_DBx__DB7__INP_DIS EQU CYREG_PRT2_INP_DIS\r
-SCSI_In_DBx__DB7__INTTYPE EQU CYREG_PICU2_INTTYPE1\r
-SCSI_In_DBx__DB7__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
-SCSI_In_DBx__DB7__LCD_EN EQU CYREG_PRT2_LCD_EN\r
-SCSI_In_DBx__DB7__MASK EQU 0x02\r
-SCSI_In_DBx__DB7__PC EQU CYREG_PRT2_PC1\r
-SCSI_In_DBx__DB7__PORT EQU 2\r
-SCSI_In_DBx__DB7__PRT EQU CYREG_PRT2_PRT\r
-SCSI_In_DBx__DB7__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
-SCSI_In_DBx__DB7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
-SCSI_In_DBx__DB7__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
-SCSI_In_DBx__DB7__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
-SCSI_In_DBx__DB7__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
-SCSI_In_DBx__DB7__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
-SCSI_In_DBx__DB7__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
-SCSI_In_DBx__DB7__PS EQU CYREG_PRT2_PS\r
-SCSI_In_DBx__DB7__SHIFT EQU 1\r
-SCSI_In_DBx__DB7__SLW EQU CYREG_PRT2_SLW\r
-\r
-; SD_DAT1\r
-SD_DAT1__0__INTTYPE EQU CYREG_PICU3_INTTYPE0\r
-SD_DAT1__0__MASK EQU 0x01\r
-SD_DAT1__0__PC EQU CYREG_PRT3_PC0\r
-SD_DAT1__0__PORT EQU 3\r
-SD_DAT1__0__SHIFT EQU 0\r
-SD_DAT1__AG EQU CYREG_PRT3_AG\r
-SD_DAT1__AMUX EQU CYREG_PRT3_AMUX\r
-SD_DAT1__BIE EQU CYREG_PRT3_BIE\r
-SD_DAT1__BIT_MASK EQU CYREG_PRT3_BIT_MASK\r
-SD_DAT1__BYP EQU CYREG_PRT3_BYP\r
-SD_DAT1__CTL EQU CYREG_PRT3_CTL\r
-SD_DAT1__DM0 EQU CYREG_PRT3_DM0\r
-SD_DAT1__DM1 EQU CYREG_PRT3_DM1\r
-SD_DAT1__DM2 EQU CYREG_PRT3_DM2\r
-SD_DAT1__DR EQU CYREG_PRT3_DR\r
-SD_DAT1__INP_DIS EQU CYREG_PRT3_INP_DIS\r
-SD_DAT1__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE\r
-SD_DAT1__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG\r
-SD_DAT1__LCD_EN EQU CYREG_PRT3_LCD_EN\r
-SD_DAT1__MASK EQU 0x01\r
-SD_DAT1__PORT EQU 3\r
-SD_DAT1__PRT EQU CYREG_PRT3_PRT\r
-SD_DAT1__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL\r
-SD_DAT1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN\r
-SD_DAT1__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0\r
-SD_DAT1__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1\r
-SD_DAT1__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0\r
-SD_DAT1__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1\r
-SD_DAT1__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT\r
-SD_DAT1__PS EQU CYREG_PRT3_PS\r
-SD_DAT1__SHIFT EQU 0\r
-SD_DAT1__SLW EQU CYREG_PRT3_SLW\r
-\r
-; SD_DAT2\r
-SD_DAT2__0__INTTYPE EQU CYREG_PICU3_INTTYPE5\r
-SD_DAT2__0__MASK EQU 0x20\r
-SD_DAT2__0__PC EQU CYREG_PRT3_PC5\r
-SD_DAT2__0__PORT EQU 3\r
-SD_DAT2__0__SHIFT EQU 5\r
-SD_DAT2__AG EQU CYREG_PRT3_AG\r
-SD_DAT2__AMUX EQU CYREG_PRT3_AMUX\r
-SD_DAT2__BIE EQU CYREG_PRT3_BIE\r
-SD_DAT2__BIT_MASK EQU CYREG_PRT3_BIT_MASK\r
-SD_DAT2__BYP EQU CYREG_PRT3_BYP\r
-SD_DAT2__CTL EQU CYREG_PRT3_CTL\r
-SD_DAT2__DM0 EQU CYREG_PRT3_DM0\r
-SD_DAT2__DM1 EQU CYREG_PRT3_DM1\r
-SD_DAT2__DM2 EQU CYREG_PRT3_DM2\r
-SD_DAT2__DR EQU CYREG_PRT3_DR\r
-SD_DAT2__INP_DIS EQU CYREG_PRT3_INP_DIS\r
-SD_DAT2__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE\r
-SD_DAT2__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG\r
-SD_DAT2__LCD_EN EQU CYREG_PRT3_LCD_EN\r
-SD_DAT2__MASK EQU 0x20\r
-SD_DAT2__PORT EQU 3\r
-SD_DAT2__PRT EQU CYREG_PRT3_PRT\r
-SD_DAT2__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL\r
-SD_DAT2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN\r
-SD_DAT2__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0\r
-SD_DAT2__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1\r
-SD_DAT2__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0\r
-SD_DAT2__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1\r
-SD_DAT2__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT\r
-SD_DAT2__PS EQU CYREG_PRT3_PS\r
-SD_DAT2__SHIFT EQU 5\r
-SD_DAT2__SLW EQU CYREG_PRT3_SLW\r
-\r
-; SD_MISO\r
-SD_MISO__0__INTTYPE EQU CYREG_PICU3_INTTYPE1\r
-SD_MISO__0__MASK EQU 0x02\r
-SD_MISO__0__PC EQU CYREG_PRT3_PC1\r
-SD_MISO__0__PORT EQU 3\r
-SD_MISO__0__SHIFT EQU 1\r
-SD_MISO__AG EQU CYREG_PRT3_AG\r
-SD_MISO__AMUX EQU CYREG_PRT3_AMUX\r
-SD_MISO__BIE EQU CYREG_PRT3_BIE\r
-SD_MISO__BIT_MASK EQU CYREG_PRT3_BIT_MASK\r
-SD_MISO__BYP EQU CYREG_PRT3_BYP\r
-SD_MISO__CTL EQU CYREG_PRT3_CTL\r
-SD_MISO__DM0 EQU CYREG_PRT3_DM0\r
-SD_MISO__DM1 EQU CYREG_PRT3_DM1\r
-SD_MISO__DM2 EQU CYREG_PRT3_DM2\r
-SD_MISO__DR EQU CYREG_PRT3_DR\r
-SD_MISO__INP_DIS EQU CYREG_PRT3_INP_DIS\r
-SD_MISO__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE\r
-SD_MISO__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG\r
-SD_MISO__LCD_EN EQU CYREG_PRT3_LCD_EN\r
-SD_MISO__MASK EQU 0x02\r
-SD_MISO__PORT EQU 3\r
-SD_MISO__PRT EQU CYREG_PRT3_PRT\r
-SD_MISO__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL\r
-SD_MISO__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN\r
-SD_MISO__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0\r
-SD_MISO__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1\r
-SD_MISO__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0\r
-SD_MISO__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1\r
-SD_MISO__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT\r
-SD_MISO__PS EQU CYREG_PRT3_PS\r
-SD_MISO__SHIFT EQU 1\r
-SD_MISO__SLW EQU CYREG_PRT3_SLW\r
-\r
-; SD_MOSI\r
-SD_MOSI__0__INTTYPE EQU CYREG_PICU3_INTTYPE3\r
-SD_MOSI__0__MASK EQU 0x08\r
-SD_MOSI__0__PC EQU CYREG_PRT3_PC3\r
-SD_MOSI__0__PORT EQU 3\r
-SD_MOSI__0__SHIFT EQU 3\r
-SD_MOSI__AG EQU CYREG_PRT3_AG\r
-SD_MOSI__AMUX EQU CYREG_PRT3_AMUX\r
-SD_MOSI__BIE EQU CYREG_PRT3_BIE\r
-SD_MOSI__BIT_MASK EQU CYREG_PRT3_BIT_MASK\r
-SD_MOSI__BYP EQU CYREG_PRT3_BYP\r
-SD_MOSI__CTL EQU CYREG_PRT3_CTL\r
-SD_MOSI__DM0 EQU CYREG_PRT3_DM0\r
-SD_MOSI__DM1 EQU CYREG_PRT3_DM1\r
-SD_MOSI__DM2 EQU CYREG_PRT3_DM2\r
-SD_MOSI__DR EQU CYREG_PRT3_DR\r
-SD_MOSI__INP_DIS EQU CYREG_PRT3_INP_DIS\r
-SD_MOSI__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE\r
-SD_MOSI__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG\r
-SD_MOSI__LCD_EN EQU CYREG_PRT3_LCD_EN\r
-SD_MOSI__MASK EQU 0x08\r
-SD_MOSI__PORT EQU 3\r
-SD_MOSI__PRT EQU CYREG_PRT3_PRT\r
-SD_MOSI__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL\r
-SD_MOSI__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN\r
-SD_MOSI__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0\r
-SD_MOSI__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1\r
-SD_MOSI__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0\r
-SD_MOSI__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1\r
-SD_MOSI__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT\r
-SD_MOSI__PS EQU CYREG_PRT3_PS\r
-SD_MOSI__SHIFT EQU 3\r
-SD_MOSI__SLW EQU CYREG_PRT3_SLW\r
-\r
-; SCSI_CLK\r
-SCSI_CLK__CFG0 EQU CYREG_CLKDIST_DCFG1_CFG0\r
-SCSI_CLK__CFG1 EQU CYREG_CLKDIST_DCFG1_CFG1\r
-SCSI_CLK__CFG2 EQU CYREG_CLKDIST_DCFG1_CFG2\r
-SCSI_CLK__CFG2_SRC_SEL_MASK EQU 0x07\r
-SCSI_CLK__INDEX EQU 0x01\r
-SCSI_CLK__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2\r
-SCSI_CLK__PM_ACT_MSK EQU 0x02\r
-SCSI_CLK__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2\r
-SCSI_CLK__PM_STBY_MSK EQU 0x02\r
-\r
-; SCSI_Out\r
-SCSI_Out__0__AG EQU CYREG_PRT4_AG\r
-SCSI_Out__0__AMUX EQU CYREG_PRT4_AMUX\r
-SCSI_Out__0__BIE EQU CYREG_PRT4_BIE\r
-SCSI_Out__0__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
-SCSI_Out__0__BYP EQU CYREG_PRT4_BYP\r
-SCSI_Out__0__CTL EQU CYREG_PRT4_CTL\r
-SCSI_Out__0__DM0 EQU CYREG_PRT4_DM0\r
-SCSI_Out__0__DM1 EQU CYREG_PRT4_DM1\r
-SCSI_Out__0__DM2 EQU CYREG_PRT4_DM2\r
-SCSI_Out__0__DR EQU CYREG_PRT4_DR\r
-SCSI_Out__0__INP_DIS EQU CYREG_PRT4_INP_DIS\r
-SCSI_Out__0__INTTYPE EQU CYREG_PICU4_INTTYPE3\r
-SCSI_Out__0__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
-SCSI_Out__0__LCD_EN EQU CYREG_PRT4_LCD_EN\r
-SCSI_Out__0__MASK EQU 0x08\r
-SCSI_Out__0__PC EQU CYREG_PRT4_PC3\r
-SCSI_Out__0__PORT EQU 4\r
-SCSI_Out__0__PRT EQU CYREG_PRT4_PRT\r
-SCSI_Out__0__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
-SCSI_Out__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
-SCSI_Out__0__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
-SCSI_Out__0__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
-SCSI_Out__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
-SCSI_Out__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
-SCSI_Out__0__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
-SCSI_Out__0__PS EQU CYREG_PRT4_PS\r
-SCSI_Out__0__SHIFT EQU 3\r
-SCSI_Out__0__SLW EQU CYREG_PRT4_SLW\r
-SCSI_Out__1__AG EQU CYREG_PRT4_AG\r
-SCSI_Out__1__AMUX EQU CYREG_PRT4_AMUX\r
-SCSI_Out__1__BIE EQU CYREG_PRT4_BIE\r
-SCSI_Out__1__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
-SCSI_Out__1__BYP EQU CYREG_PRT4_BYP\r
-SCSI_Out__1__CTL EQU CYREG_PRT4_CTL\r
-SCSI_Out__1__DM0 EQU CYREG_PRT4_DM0\r
-SCSI_Out__1__DM1 EQU CYREG_PRT4_DM1\r
-SCSI_Out__1__DM2 EQU CYREG_PRT4_DM2\r
-SCSI_Out__1__DR EQU CYREG_PRT4_DR\r
-SCSI_Out__1__INP_DIS EQU CYREG_PRT4_INP_DIS\r
-SCSI_Out__1__INTTYPE EQU CYREG_PICU4_INTTYPE2\r
-SCSI_Out__1__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
-SCSI_Out__1__LCD_EN EQU CYREG_PRT4_LCD_EN\r
-SCSI_Out__1__MASK EQU 0x04\r
-SCSI_Out__1__PC EQU CYREG_PRT4_PC2\r
-SCSI_Out__1__PORT EQU 4\r
-SCSI_Out__1__PRT EQU CYREG_PRT4_PRT\r
-SCSI_Out__1__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
-SCSI_Out__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
-SCSI_Out__1__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
-SCSI_Out__1__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
-SCSI_Out__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
-SCSI_Out__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
-SCSI_Out__1__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
-SCSI_Out__1__PS EQU CYREG_PRT4_PS\r
-SCSI_Out__1__SHIFT EQU 2\r
-SCSI_Out__1__SLW EQU CYREG_PRT4_SLW\r
-SCSI_Out__2__AG EQU CYREG_PRT0_AG\r
-SCSI_Out__2__AMUX EQU CYREG_PRT0_AMUX\r
-SCSI_Out__2__BIE EQU CYREG_PRT0_BIE\r
-SCSI_Out__2__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
-SCSI_Out__2__BYP EQU CYREG_PRT0_BYP\r
-SCSI_Out__2__CTL EQU CYREG_PRT0_CTL\r
-SCSI_Out__2__DM0 EQU CYREG_PRT0_DM0\r
-SCSI_Out__2__DM1 EQU CYREG_PRT0_DM1\r
-SCSI_Out__2__DM2 EQU CYREG_PRT0_DM2\r
-SCSI_Out__2__DR EQU CYREG_PRT0_DR\r
-SCSI_Out__2__INP_DIS EQU CYREG_PRT0_INP_DIS\r
-SCSI_Out__2__INTTYPE EQU CYREG_PICU0_INTTYPE7\r
-SCSI_Out__2__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
-SCSI_Out__2__LCD_EN EQU CYREG_PRT0_LCD_EN\r
-SCSI_Out__2__MASK EQU 0x80\r
-SCSI_Out__2__PC EQU CYREG_PRT0_PC7\r
-SCSI_Out__2__PORT EQU 0\r
-SCSI_Out__2__PRT EQU CYREG_PRT0_PRT\r
-SCSI_Out__2__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
-SCSI_Out__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
-SCSI_Out__2__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
-SCSI_Out__2__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
-SCSI_Out__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
-SCSI_Out__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
-SCSI_Out__2__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
-SCSI_Out__2__PS EQU CYREG_PRT0_PS\r
-SCSI_Out__2__SHIFT EQU 7\r
-SCSI_Out__2__SLW EQU CYREG_PRT0_SLW\r
-SCSI_Out__3__AG EQU CYREG_PRT0_AG\r
-SCSI_Out__3__AMUX EQU CYREG_PRT0_AMUX\r
-SCSI_Out__3__BIE EQU CYREG_PRT0_BIE\r
-SCSI_Out__3__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
-SCSI_Out__3__BYP EQU CYREG_PRT0_BYP\r
-SCSI_Out__3__CTL EQU CYREG_PRT0_CTL\r
-SCSI_Out__3__DM0 EQU CYREG_PRT0_DM0\r
-SCSI_Out__3__DM1 EQU CYREG_PRT0_DM1\r
-SCSI_Out__3__DM2 EQU CYREG_PRT0_DM2\r
-SCSI_Out__3__DR EQU CYREG_PRT0_DR\r
-SCSI_Out__3__INP_DIS EQU CYREG_PRT0_INP_DIS\r
-SCSI_Out__3__INTTYPE EQU CYREG_PICU0_INTTYPE6\r
-SCSI_Out__3__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
-SCSI_Out__3__LCD_EN EQU CYREG_PRT0_LCD_EN\r
-SCSI_Out__3__MASK EQU 0x40\r
-SCSI_Out__3__PC EQU CYREG_PRT0_PC6\r
-SCSI_Out__3__PORT EQU 0\r
-SCSI_Out__3__PRT EQU CYREG_PRT0_PRT\r
-SCSI_Out__3__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
-SCSI_Out__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
-SCSI_Out__3__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
-SCSI_Out__3__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
-SCSI_Out__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
-SCSI_Out__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
-SCSI_Out__3__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
-SCSI_Out__3__PS EQU CYREG_PRT0_PS\r
-SCSI_Out__3__SHIFT EQU 6\r
-SCSI_Out__3__SLW EQU CYREG_PRT0_SLW\r
-SCSI_Out__4__AG EQU CYREG_PRT0_AG\r
-SCSI_Out__4__AMUX EQU CYREG_PRT0_AMUX\r
-SCSI_Out__4__BIE EQU CYREG_PRT0_BIE\r
-SCSI_Out__4__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
-SCSI_Out__4__BYP EQU CYREG_PRT0_BYP\r
-SCSI_Out__4__CTL EQU CYREG_PRT0_CTL\r
-SCSI_Out__4__DM0 EQU CYREG_PRT0_DM0\r
-SCSI_Out__4__DM1 EQU CYREG_PRT0_DM1\r
-SCSI_Out__4__DM2 EQU CYREG_PRT0_DM2\r
-SCSI_Out__4__DR EQU CYREG_PRT0_DR\r
-SCSI_Out__4__INP_DIS EQU CYREG_PRT0_INP_DIS\r
-SCSI_Out__4__INTTYPE EQU CYREG_PICU0_INTTYPE5\r
-SCSI_Out__4__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
-SCSI_Out__4__LCD_EN EQU CYREG_PRT0_LCD_EN\r
-SCSI_Out__4__MASK EQU 0x20\r
-SCSI_Out__4__PC EQU CYREG_PRT0_PC5\r
-SCSI_Out__4__PORT EQU 0\r
-SCSI_Out__4__PRT EQU CYREG_PRT0_PRT\r
-SCSI_Out__4__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
-SCSI_Out__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
-SCSI_Out__4__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
-SCSI_Out__4__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
-SCSI_Out__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
-SCSI_Out__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
-SCSI_Out__4__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
-SCSI_Out__4__PS EQU CYREG_PRT0_PS\r
-SCSI_Out__4__SHIFT EQU 5\r
-SCSI_Out__4__SLW EQU CYREG_PRT0_SLW\r
-SCSI_Out__5__AG EQU CYREG_PRT0_AG\r
-SCSI_Out__5__AMUX EQU CYREG_PRT0_AMUX\r
-SCSI_Out__5__BIE EQU CYREG_PRT0_BIE\r
-SCSI_Out__5__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
-SCSI_Out__5__BYP EQU CYREG_PRT0_BYP\r
-SCSI_Out__5__CTL EQU CYREG_PRT0_CTL\r
-SCSI_Out__5__DM0 EQU CYREG_PRT0_DM0\r
-SCSI_Out__5__DM1 EQU CYREG_PRT0_DM1\r
-SCSI_Out__5__DM2 EQU CYREG_PRT0_DM2\r
-SCSI_Out__5__DR EQU CYREG_PRT0_DR\r
-SCSI_Out__5__INP_DIS EQU CYREG_PRT0_INP_DIS\r
-SCSI_Out__5__INTTYPE EQU CYREG_PICU0_INTTYPE4\r
-SCSI_Out__5__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
-SCSI_Out__5__LCD_EN EQU CYREG_PRT0_LCD_EN\r
-SCSI_Out__5__MASK EQU 0x10\r
-SCSI_Out__5__PC EQU CYREG_PRT0_PC4\r
-SCSI_Out__5__PORT EQU 0\r
-SCSI_Out__5__PRT EQU CYREG_PRT0_PRT\r
-SCSI_Out__5__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
-SCSI_Out__5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
-SCSI_Out__5__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
-SCSI_Out__5__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
-SCSI_Out__5__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
-SCSI_Out__5__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
-SCSI_Out__5__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
-SCSI_Out__5__PS EQU CYREG_PRT0_PS\r
-SCSI_Out__5__SHIFT EQU 4\r
-SCSI_Out__5__SLW EQU CYREG_PRT0_SLW\r
-SCSI_Out__6__AG EQU CYREG_PRT0_AG\r
-SCSI_Out__6__AMUX EQU CYREG_PRT0_AMUX\r
-SCSI_Out__6__BIE EQU CYREG_PRT0_BIE\r
-SCSI_Out__6__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
-SCSI_Out__6__BYP EQU CYREG_PRT0_BYP\r
-SCSI_Out__6__CTL EQU CYREG_PRT0_CTL\r
-SCSI_Out__6__DM0 EQU CYREG_PRT0_DM0\r
-SCSI_Out__6__DM1 EQU CYREG_PRT0_DM1\r
-SCSI_Out__6__DM2 EQU CYREG_PRT0_DM2\r
-SCSI_Out__6__DR EQU CYREG_PRT0_DR\r
-SCSI_Out__6__INP_DIS EQU CYREG_PRT0_INP_DIS\r
-SCSI_Out__6__INTTYPE EQU CYREG_PICU0_INTTYPE3\r
-SCSI_Out__6__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
-SCSI_Out__6__LCD_EN EQU CYREG_PRT0_LCD_EN\r
-SCSI_Out__6__MASK EQU 0x08\r
-SCSI_Out__6__PC EQU CYREG_PRT0_PC3\r
-SCSI_Out__6__PORT EQU 0\r
-SCSI_Out__6__PRT EQU CYREG_PRT0_PRT\r
-SCSI_Out__6__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
-SCSI_Out__6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
-SCSI_Out__6__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
-SCSI_Out__6__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
-SCSI_Out__6__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
-SCSI_Out__6__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
-SCSI_Out__6__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
-SCSI_Out__6__PS EQU CYREG_PRT0_PS\r
-SCSI_Out__6__SHIFT EQU 3\r
-SCSI_Out__6__SLW EQU CYREG_PRT0_SLW\r
-SCSI_Out__7__AG EQU CYREG_PRT0_AG\r
-SCSI_Out__7__AMUX EQU CYREG_PRT0_AMUX\r
-SCSI_Out__7__BIE EQU CYREG_PRT0_BIE\r
-SCSI_Out__7__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
-SCSI_Out__7__BYP EQU CYREG_PRT0_BYP\r
-SCSI_Out__7__CTL EQU CYREG_PRT0_CTL\r
-SCSI_Out__7__DM0 EQU CYREG_PRT0_DM0\r
-SCSI_Out__7__DM1 EQU CYREG_PRT0_DM1\r
-SCSI_Out__7__DM2 EQU CYREG_PRT0_DM2\r
-SCSI_Out__7__DR EQU CYREG_PRT0_DR\r
-SCSI_Out__7__INP_DIS EQU CYREG_PRT0_INP_DIS\r
-SCSI_Out__7__INTTYPE EQU CYREG_PICU0_INTTYPE2\r
-SCSI_Out__7__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
-SCSI_Out__7__LCD_EN EQU CYREG_PRT0_LCD_EN\r
-SCSI_Out__7__MASK EQU 0x04\r
-SCSI_Out__7__PC EQU CYREG_PRT0_PC2\r
-SCSI_Out__7__PORT EQU 0\r
-SCSI_Out__7__PRT EQU CYREG_PRT0_PRT\r
-SCSI_Out__7__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
-SCSI_Out__7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
-SCSI_Out__7__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
-SCSI_Out__7__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
-SCSI_Out__7__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
-SCSI_Out__7__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
-SCSI_Out__7__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
-SCSI_Out__7__PS EQU CYREG_PRT0_PS\r
-SCSI_Out__7__SHIFT EQU 2\r
-SCSI_Out__7__SLW EQU CYREG_PRT0_SLW\r
-SCSI_Out__8__AG EQU CYREG_PRT0_AG\r
-SCSI_Out__8__AMUX EQU CYREG_PRT0_AMUX\r
-SCSI_Out__8__BIE EQU CYREG_PRT0_BIE\r
-SCSI_Out__8__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
-SCSI_Out__8__BYP EQU CYREG_PRT0_BYP\r
-SCSI_Out__8__CTL EQU CYREG_PRT0_CTL\r
-SCSI_Out__8__DM0 EQU CYREG_PRT0_DM0\r
-SCSI_Out__8__DM1 EQU CYREG_PRT0_DM1\r
-SCSI_Out__8__DM2 EQU CYREG_PRT0_DM2\r
-SCSI_Out__8__DR EQU CYREG_PRT0_DR\r
-SCSI_Out__8__INP_DIS EQU CYREG_PRT0_INP_DIS\r
-SCSI_Out__8__INTTYPE EQU CYREG_PICU0_INTTYPE1\r
-SCSI_Out__8__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
-SCSI_Out__8__LCD_EN EQU CYREG_PRT0_LCD_EN\r
-SCSI_Out__8__MASK EQU 0x02\r
-SCSI_Out__8__PC EQU CYREG_PRT0_PC1\r
-SCSI_Out__8__PORT EQU 0\r
-SCSI_Out__8__PRT EQU CYREG_PRT0_PRT\r
-SCSI_Out__8__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
-SCSI_Out__8__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
-SCSI_Out__8__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
-SCSI_Out__8__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
-SCSI_Out__8__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
-SCSI_Out__8__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
-SCSI_Out__8__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
-SCSI_Out__8__PS EQU CYREG_PRT0_PS\r
-SCSI_Out__8__SHIFT EQU 1\r
-SCSI_Out__8__SLW EQU CYREG_PRT0_SLW\r
-SCSI_Out__9__AG EQU CYREG_PRT0_AG\r
-SCSI_Out__9__AMUX EQU CYREG_PRT0_AMUX\r
-SCSI_Out__9__BIE EQU CYREG_PRT0_BIE\r
-SCSI_Out__9__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
-SCSI_Out__9__BYP EQU CYREG_PRT0_BYP\r
-SCSI_Out__9__CTL EQU CYREG_PRT0_CTL\r
-SCSI_Out__9__DM0 EQU CYREG_PRT0_DM0\r
-SCSI_Out__9__DM1 EQU CYREG_PRT0_DM1\r
-SCSI_Out__9__DM2 EQU CYREG_PRT0_DM2\r
-SCSI_Out__9__DR EQU CYREG_PRT0_DR\r
-SCSI_Out__9__INP_DIS EQU CYREG_PRT0_INP_DIS\r
-SCSI_Out__9__INTTYPE EQU CYREG_PICU0_INTTYPE0\r
-SCSI_Out__9__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
-SCSI_Out__9__LCD_EN EQU CYREG_PRT0_LCD_EN\r
-SCSI_Out__9__MASK EQU 0x01\r
-SCSI_Out__9__PC EQU CYREG_PRT0_PC0\r
-SCSI_Out__9__PORT EQU 0\r
-SCSI_Out__9__PRT EQU CYREG_PRT0_PRT\r
-SCSI_Out__9__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
-SCSI_Out__9__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
-SCSI_Out__9__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
-SCSI_Out__9__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
-SCSI_Out__9__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
-SCSI_Out__9__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
-SCSI_Out__9__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
-SCSI_Out__9__PS EQU CYREG_PRT0_PS\r
-SCSI_Out__9__SHIFT EQU 0\r
-SCSI_Out__9__SLW EQU CYREG_PRT0_SLW\r
-SCSI_Out__ACK__AG EQU CYREG_PRT0_AG\r
-SCSI_Out__ACK__AMUX EQU CYREG_PRT0_AMUX\r
-SCSI_Out__ACK__BIE EQU CYREG_PRT0_BIE\r
-SCSI_Out__ACK__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
-SCSI_Out__ACK__BYP EQU CYREG_PRT0_BYP\r
-SCSI_Out__ACK__CTL EQU CYREG_PRT0_CTL\r
-SCSI_Out__ACK__DM0 EQU CYREG_PRT0_DM0\r
-SCSI_Out__ACK__DM1 EQU CYREG_PRT0_DM1\r
-SCSI_Out__ACK__DM2 EQU CYREG_PRT0_DM2\r
-SCSI_Out__ACK__DR EQU CYREG_PRT0_DR\r
-SCSI_Out__ACK__INP_DIS EQU CYREG_PRT0_INP_DIS\r
-SCSI_Out__ACK__INTTYPE EQU CYREG_PICU0_INTTYPE6\r
-SCSI_Out__ACK__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
-SCSI_Out__ACK__LCD_EN EQU CYREG_PRT0_LCD_EN\r
-SCSI_Out__ACK__MASK EQU 0x40\r
-SCSI_Out__ACK__PC EQU CYREG_PRT0_PC6\r
-SCSI_Out__ACK__PORT EQU 0\r
-SCSI_Out__ACK__PRT EQU CYREG_PRT0_PRT\r
-SCSI_Out__ACK__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
-SCSI_Out__ACK__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
-SCSI_Out__ACK__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
-SCSI_Out__ACK__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
-SCSI_Out__ACK__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
-SCSI_Out__ACK__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
-SCSI_Out__ACK__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
-SCSI_Out__ACK__PS EQU CYREG_PRT0_PS\r
-SCSI_Out__ACK__SHIFT EQU 6\r
-SCSI_Out__ACK__SLW EQU CYREG_PRT0_SLW\r
-SCSI_Out__ATN__AG EQU CYREG_PRT4_AG\r
-SCSI_Out__ATN__AMUX EQU CYREG_PRT4_AMUX\r
-SCSI_Out__ATN__BIE EQU CYREG_PRT4_BIE\r
-SCSI_Out__ATN__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
-SCSI_Out__ATN__BYP EQU CYREG_PRT4_BYP\r
-SCSI_Out__ATN__CTL EQU CYREG_PRT4_CTL\r
-SCSI_Out__ATN__DM0 EQU CYREG_PRT4_DM0\r
-SCSI_Out__ATN__DM1 EQU CYREG_PRT4_DM1\r
-SCSI_Out__ATN__DM2 EQU CYREG_PRT4_DM2\r
-SCSI_Out__ATN__DR EQU CYREG_PRT4_DR\r
-SCSI_Out__ATN__INP_DIS EQU CYREG_PRT4_INP_DIS\r
-SCSI_Out__ATN__INTTYPE EQU CYREG_PICU4_INTTYPE2\r
-SCSI_Out__ATN__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
-SCSI_Out__ATN__LCD_EN EQU CYREG_PRT4_LCD_EN\r
-SCSI_Out__ATN__MASK EQU 0x04\r
-SCSI_Out__ATN__PC EQU CYREG_PRT4_PC2\r
-SCSI_Out__ATN__PORT EQU 4\r
-SCSI_Out__ATN__PRT EQU CYREG_PRT4_PRT\r
-SCSI_Out__ATN__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
-SCSI_Out__ATN__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
-SCSI_Out__ATN__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
-SCSI_Out__ATN__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
-SCSI_Out__ATN__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
-SCSI_Out__ATN__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
-SCSI_Out__ATN__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
-SCSI_Out__ATN__PS EQU CYREG_PRT4_PS\r
-SCSI_Out__ATN__SHIFT EQU 2\r
-SCSI_Out__ATN__SLW EQU CYREG_PRT4_SLW\r
-SCSI_Out__BSY__AG EQU CYREG_PRT0_AG\r
-SCSI_Out__BSY__AMUX EQU CYREG_PRT0_AMUX\r
-SCSI_Out__BSY__BIE EQU CYREG_PRT0_BIE\r
-SCSI_Out__BSY__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
-SCSI_Out__BSY__BYP EQU CYREG_PRT0_BYP\r
-SCSI_Out__BSY__CTL EQU CYREG_PRT0_CTL\r
-SCSI_Out__BSY__DM0 EQU CYREG_PRT0_DM0\r
-SCSI_Out__BSY__DM1 EQU CYREG_PRT0_DM1\r
-SCSI_Out__BSY__DM2 EQU CYREG_PRT0_DM2\r
-SCSI_Out__BSY__DR EQU CYREG_PRT0_DR\r
-SCSI_Out__BSY__INP_DIS EQU CYREG_PRT0_INP_DIS\r
-SCSI_Out__BSY__INTTYPE EQU CYREG_PICU0_INTTYPE7\r
-SCSI_Out__BSY__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
-SCSI_Out__BSY__LCD_EN EQU CYREG_PRT0_LCD_EN\r
-SCSI_Out__BSY__MASK EQU 0x80\r
-SCSI_Out__BSY__PC EQU CYREG_PRT0_PC7\r
-SCSI_Out__BSY__PORT EQU 0\r
-SCSI_Out__BSY__PRT EQU CYREG_PRT0_PRT\r
-SCSI_Out__BSY__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
-SCSI_Out__BSY__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
-SCSI_Out__BSY__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
-SCSI_Out__BSY__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
-SCSI_Out__BSY__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
-SCSI_Out__BSY__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
-SCSI_Out__BSY__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
-SCSI_Out__BSY__PS EQU CYREG_PRT0_PS\r
-SCSI_Out__BSY__SHIFT EQU 7\r
-SCSI_Out__BSY__SLW EQU CYREG_PRT0_SLW\r
-SCSI_Out__CD_raw__AG EQU CYREG_PRT0_AG\r
-SCSI_Out__CD_raw__AMUX EQU CYREG_PRT0_AMUX\r
-SCSI_Out__CD_raw__BIE EQU CYREG_PRT0_BIE\r
-SCSI_Out__CD_raw__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
-SCSI_Out__CD_raw__BYP EQU CYREG_PRT0_BYP\r
-SCSI_Out__CD_raw__CTL EQU CYREG_PRT0_CTL\r
-SCSI_Out__CD_raw__DM0 EQU CYREG_PRT0_DM0\r
-SCSI_Out__CD_raw__DM1 EQU CYREG_PRT0_DM1\r
-SCSI_Out__CD_raw__DM2 EQU CYREG_PRT0_DM2\r
-SCSI_Out__CD_raw__DR EQU CYREG_PRT0_DR\r
-SCSI_Out__CD_raw__INP_DIS EQU CYREG_PRT0_INP_DIS\r
-SCSI_Out__CD_raw__INTTYPE EQU CYREG_PICU0_INTTYPE2\r
-SCSI_Out__CD_raw__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
-SCSI_Out__CD_raw__LCD_EN EQU CYREG_PRT0_LCD_EN\r
-SCSI_Out__CD_raw__MASK EQU 0x04\r
-SCSI_Out__CD_raw__PC EQU CYREG_PRT0_PC2\r
-SCSI_Out__CD_raw__PORT EQU 0\r
-SCSI_Out__CD_raw__PRT EQU CYREG_PRT0_PRT\r
-SCSI_Out__CD_raw__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
-SCSI_Out__CD_raw__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
-SCSI_Out__CD_raw__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
-SCSI_Out__CD_raw__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
-SCSI_Out__CD_raw__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
-SCSI_Out__CD_raw__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
-SCSI_Out__CD_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
-SCSI_Out__CD_raw__PS EQU CYREG_PRT0_PS\r
-SCSI_Out__CD_raw__SHIFT EQU 2\r
-SCSI_Out__CD_raw__SLW EQU CYREG_PRT0_SLW\r
-SCSI_Out__DBP_raw__AG EQU CYREG_PRT4_AG\r
-SCSI_Out__DBP_raw__AMUX EQU CYREG_PRT4_AMUX\r
-SCSI_Out__DBP_raw__BIE EQU CYREG_PRT4_BIE\r
-SCSI_Out__DBP_raw__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
-SCSI_Out__DBP_raw__BYP EQU CYREG_PRT4_BYP\r
-SCSI_Out__DBP_raw__CTL EQU CYREG_PRT4_CTL\r
-SCSI_Out__DBP_raw__DM0 EQU CYREG_PRT4_DM0\r
-SCSI_Out__DBP_raw__DM1 EQU CYREG_PRT4_DM1\r
-SCSI_Out__DBP_raw__DM2 EQU CYREG_PRT4_DM2\r
-SCSI_Out__DBP_raw__DR EQU CYREG_PRT4_DR\r
-SCSI_Out__DBP_raw__INP_DIS EQU CYREG_PRT4_INP_DIS\r
-SCSI_Out__DBP_raw__INTTYPE EQU CYREG_PICU4_INTTYPE3\r
-SCSI_Out__DBP_raw__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
-SCSI_Out__DBP_raw__LCD_EN EQU CYREG_PRT4_LCD_EN\r
-SCSI_Out__DBP_raw__MASK EQU 0x08\r
-SCSI_Out__DBP_raw__PC EQU CYREG_PRT4_PC3\r
-SCSI_Out__DBP_raw__PORT EQU 4\r
-SCSI_Out__DBP_raw__PRT EQU CYREG_PRT4_PRT\r
-SCSI_Out__DBP_raw__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
-SCSI_Out__DBP_raw__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
-SCSI_Out__DBP_raw__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
-SCSI_Out__DBP_raw__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
-SCSI_Out__DBP_raw__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
-SCSI_Out__DBP_raw__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
-SCSI_Out__DBP_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
-SCSI_Out__DBP_raw__PS EQU CYREG_PRT4_PS\r
-SCSI_Out__DBP_raw__SHIFT EQU 3\r
-SCSI_Out__DBP_raw__SLW EQU CYREG_PRT4_SLW\r
-SCSI_Out__IO_raw__AG EQU CYREG_PRT0_AG\r
-SCSI_Out__IO_raw__AMUX EQU CYREG_PRT0_AMUX\r
-SCSI_Out__IO_raw__BIE EQU CYREG_PRT0_BIE\r
-SCSI_Out__IO_raw__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
-SCSI_Out__IO_raw__BYP EQU CYREG_PRT0_BYP\r
-SCSI_Out__IO_raw__CTL EQU CYREG_PRT0_CTL\r
-SCSI_Out__IO_raw__DM0 EQU CYREG_PRT0_DM0\r
-SCSI_Out__IO_raw__DM1 EQU CYREG_PRT0_DM1\r
-SCSI_Out__IO_raw__DM2 EQU CYREG_PRT0_DM2\r
-SCSI_Out__IO_raw__DR EQU CYREG_PRT0_DR\r
-SCSI_Out__IO_raw__INP_DIS EQU CYREG_PRT0_INP_DIS\r
-SCSI_Out__IO_raw__INTTYPE EQU CYREG_PICU0_INTTYPE0\r
-SCSI_Out__IO_raw__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
-SCSI_Out__IO_raw__LCD_EN EQU CYREG_PRT0_LCD_EN\r
-SCSI_Out__IO_raw__MASK EQU 0x01\r
-SCSI_Out__IO_raw__PC EQU CYREG_PRT0_PC0\r
-SCSI_Out__IO_raw__PORT EQU 0\r
-SCSI_Out__IO_raw__PRT EQU CYREG_PRT0_PRT\r
-SCSI_Out__IO_raw__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
-SCSI_Out__IO_raw__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
-SCSI_Out__IO_raw__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
-SCSI_Out__IO_raw__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
-SCSI_Out__IO_raw__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
-SCSI_Out__IO_raw__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
-SCSI_Out__IO_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
-SCSI_Out__IO_raw__PS EQU CYREG_PRT0_PS\r
-SCSI_Out__IO_raw__SHIFT EQU 0\r
-SCSI_Out__IO_raw__SLW EQU CYREG_PRT0_SLW\r
-SCSI_Out__MSG_raw__AG EQU CYREG_PRT0_AG\r
-SCSI_Out__MSG_raw__AMUX EQU CYREG_PRT0_AMUX\r
-SCSI_Out__MSG_raw__BIE EQU CYREG_PRT0_BIE\r
-SCSI_Out__MSG_raw__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
-SCSI_Out__MSG_raw__BYP EQU CYREG_PRT0_BYP\r
-SCSI_Out__MSG_raw__CTL EQU CYREG_PRT0_CTL\r
-SCSI_Out__MSG_raw__DM0 EQU CYREG_PRT0_DM0\r
-SCSI_Out__MSG_raw__DM1 EQU CYREG_PRT0_DM1\r
-SCSI_Out__MSG_raw__DM2 EQU CYREG_PRT0_DM2\r
-SCSI_Out__MSG_raw__DR EQU CYREG_PRT0_DR\r
-SCSI_Out__MSG_raw__INP_DIS EQU CYREG_PRT0_INP_DIS\r
-SCSI_Out__MSG_raw__INTTYPE EQU CYREG_PICU0_INTTYPE4\r
-SCSI_Out__MSG_raw__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
-SCSI_Out__MSG_raw__LCD_EN EQU CYREG_PRT0_LCD_EN\r
-SCSI_Out__MSG_raw__MASK EQU 0x10\r
-SCSI_Out__MSG_raw__PC EQU CYREG_PRT0_PC4\r
-SCSI_Out__MSG_raw__PORT EQU 0\r
-SCSI_Out__MSG_raw__PRT EQU CYREG_PRT0_PRT\r
-SCSI_Out__MSG_raw__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
-SCSI_Out__MSG_raw__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
-SCSI_Out__MSG_raw__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
-SCSI_Out__MSG_raw__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
-SCSI_Out__MSG_raw__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
-SCSI_Out__MSG_raw__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
-SCSI_Out__MSG_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
-SCSI_Out__MSG_raw__PS EQU CYREG_PRT0_PS\r
-SCSI_Out__MSG_raw__SHIFT EQU 4\r
-SCSI_Out__MSG_raw__SLW EQU CYREG_PRT0_SLW\r
-SCSI_Out__REQ__AG EQU CYREG_PRT0_AG\r
-SCSI_Out__REQ__AMUX EQU CYREG_PRT0_AMUX\r
-SCSI_Out__REQ__BIE EQU CYREG_PRT0_BIE\r
-SCSI_Out__REQ__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
-SCSI_Out__REQ__BYP EQU CYREG_PRT0_BYP\r
-SCSI_Out__REQ__CTL EQU CYREG_PRT0_CTL\r
-SCSI_Out__REQ__DM0 EQU CYREG_PRT0_DM0\r
-SCSI_Out__REQ__DM1 EQU CYREG_PRT0_DM1\r
-SCSI_Out__REQ__DM2 EQU CYREG_PRT0_DM2\r
-SCSI_Out__REQ__DR EQU CYREG_PRT0_DR\r
-SCSI_Out__REQ__INP_DIS EQU CYREG_PRT0_INP_DIS\r
-SCSI_Out__REQ__INTTYPE EQU CYREG_PICU0_INTTYPE1\r
-SCSI_Out__REQ__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
-SCSI_Out__REQ__LCD_EN EQU CYREG_PRT0_LCD_EN\r
-SCSI_Out__REQ__MASK EQU 0x02\r
-SCSI_Out__REQ__PC EQU CYREG_PRT0_PC1\r
-SCSI_Out__REQ__PORT EQU 0\r
-SCSI_Out__REQ__PRT EQU CYREG_PRT0_PRT\r
-SCSI_Out__REQ__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
-SCSI_Out__REQ__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
-SCSI_Out__REQ__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
-SCSI_Out__REQ__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
-SCSI_Out__REQ__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
-SCSI_Out__REQ__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
-SCSI_Out__REQ__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
-SCSI_Out__REQ__PS EQU CYREG_PRT0_PS\r
-SCSI_Out__REQ__SHIFT EQU 1\r
-SCSI_Out__REQ__SLW EQU CYREG_PRT0_SLW\r
-SCSI_Out__RST__AG EQU CYREG_PRT0_AG\r
-SCSI_Out__RST__AMUX EQU CYREG_PRT0_AMUX\r
-SCSI_Out__RST__BIE EQU CYREG_PRT0_BIE\r
-SCSI_Out__RST__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
-SCSI_Out__RST__BYP EQU CYREG_PRT0_BYP\r
-SCSI_Out__RST__CTL EQU CYREG_PRT0_CTL\r
-SCSI_Out__RST__DM0 EQU CYREG_PRT0_DM0\r
-SCSI_Out__RST__DM1 EQU CYREG_PRT0_DM1\r
-SCSI_Out__RST__DM2 EQU CYREG_PRT0_DM2\r
-SCSI_Out__RST__DR EQU CYREG_PRT0_DR\r
-SCSI_Out__RST__INP_DIS EQU CYREG_PRT0_INP_DIS\r
-SCSI_Out__RST__INTTYPE EQU CYREG_PICU0_INTTYPE5\r
-SCSI_Out__RST__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
-SCSI_Out__RST__LCD_EN EQU CYREG_PRT0_LCD_EN\r
-SCSI_Out__RST__MASK EQU 0x20\r
-SCSI_Out__RST__PC EQU CYREG_PRT0_PC5\r
-SCSI_Out__RST__PORT EQU 0\r
-SCSI_Out__RST__PRT EQU CYREG_PRT0_PRT\r
-SCSI_Out__RST__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
-SCSI_Out__RST__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
-SCSI_Out__RST__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
-SCSI_Out__RST__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
-SCSI_Out__RST__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
-SCSI_Out__RST__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
-SCSI_Out__RST__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
-SCSI_Out__RST__PS EQU CYREG_PRT0_PS\r
-SCSI_Out__RST__SHIFT EQU 5\r
-SCSI_Out__RST__SLW EQU CYREG_PRT0_SLW\r
-SCSI_Out__SEL__AG EQU CYREG_PRT0_AG\r
-SCSI_Out__SEL__AMUX EQU CYREG_PRT0_AMUX\r
-SCSI_Out__SEL__BIE EQU CYREG_PRT0_BIE\r
-SCSI_Out__SEL__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
-SCSI_Out__SEL__BYP EQU CYREG_PRT0_BYP\r
-SCSI_Out__SEL__CTL EQU CYREG_PRT0_CTL\r
-SCSI_Out__SEL__DM0 EQU CYREG_PRT0_DM0\r
-SCSI_Out__SEL__DM1 EQU CYREG_PRT0_DM1\r
-SCSI_Out__SEL__DM2 EQU CYREG_PRT0_DM2\r
-SCSI_Out__SEL__DR EQU CYREG_PRT0_DR\r
-SCSI_Out__SEL__INP_DIS EQU CYREG_PRT0_INP_DIS\r
-SCSI_Out__SEL__INTTYPE EQU CYREG_PICU0_INTTYPE3\r
-SCSI_Out__SEL__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
-SCSI_Out__SEL__LCD_EN EQU CYREG_PRT0_LCD_EN\r
-SCSI_Out__SEL__MASK EQU 0x08\r
-SCSI_Out__SEL__PC EQU CYREG_PRT0_PC3\r
-SCSI_Out__SEL__PORT EQU 0\r
-SCSI_Out__SEL__PRT EQU CYREG_PRT0_PRT\r
-SCSI_Out__SEL__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
-SCSI_Out__SEL__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
-SCSI_Out__SEL__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
-SCSI_Out__SEL__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
-SCSI_Out__SEL__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
-SCSI_Out__SEL__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
-SCSI_Out__SEL__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
-SCSI_Out__SEL__PS EQU CYREG_PRT0_PS\r
-SCSI_Out__SEL__SHIFT EQU 3\r
-SCSI_Out__SEL__SLW EQU CYREG_PRT0_SLW\r
-\r
-; SCSI_Out_Bits\r
-SCSI_Out_Bits_Sync_ctrl_reg__0__MASK EQU 0x01\r
-SCSI_Out_Bits_Sync_ctrl_reg__0__POS EQU 0\r
-SCSI_Out_Bits_Sync_ctrl_reg__1__MASK EQU 0x02\r
-SCSI_Out_Bits_Sync_ctrl_reg__1__POS EQU 1\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB08_09_ACTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB08_09_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB08_09_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB08_09_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB08_09_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB08_09_MSK\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB08_09_MSK\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB08_09_MSK\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB08_09_MSK\r
-SCSI_Out_Bits_Sync_ctrl_reg__2__MASK EQU 0x04\r
-SCSI_Out_Bits_Sync_ctrl_reg__2__POS EQU 2\r
-SCSI_Out_Bits_Sync_ctrl_reg__3__MASK EQU 0x08\r
-SCSI_Out_Bits_Sync_ctrl_reg__3__POS EQU 3\r
-SCSI_Out_Bits_Sync_ctrl_reg__4__MASK EQU 0x10\r
-SCSI_Out_Bits_Sync_ctrl_reg__4__POS EQU 4\r
-SCSI_Out_Bits_Sync_ctrl_reg__5__MASK EQU 0x20\r
-SCSI_Out_Bits_Sync_ctrl_reg__5__POS EQU 5\r
-SCSI_Out_Bits_Sync_ctrl_reg__6__MASK EQU 0x40\r
-SCSI_Out_Bits_Sync_ctrl_reg__6__POS EQU 6\r
-SCSI_Out_Bits_Sync_ctrl_reg__7__MASK EQU 0x80\r
-SCSI_Out_Bits_Sync_ctrl_reg__7__POS EQU 7\r
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB08_ACTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B1_UDB08_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B1_UDB08_ST_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B1_UDB08_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B1_UDB08_ST_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__MASK EQU 0xFF\r
-SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB08_MSK_ACTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB08_MSK_ACTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B1_UDB08_MSK\r
-\r
-; SCSI_Out_Ctl\r
-SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01\r
-SCSI_Out_Ctl_Sync_ctrl_reg__0__POS EQU 0\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB08_09_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB08_09_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB08_09_MSK\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB08_09_MSK\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK\r
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB08_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB08_ST_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB08_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB08_ST_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__MASK EQU 0x01\r
-SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB08_MSK\r
-\r
-; SCSI_Out_DBx\r
-SCSI_Out_DBx__0__AG EQU CYREG_PRT6_AG\r
-SCSI_Out_DBx__0__AMUX EQU CYREG_PRT6_AMUX\r
-SCSI_Out_DBx__0__BIE EQU CYREG_PRT6_BIE\r
-SCSI_Out_DBx__0__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
-SCSI_Out_DBx__0__BYP EQU CYREG_PRT6_BYP\r
-SCSI_Out_DBx__0__CTL EQU CYREG_PRT6_CTL\r
-SCSI_Out_DBx__0__DM0 EQU CYREG_PRT6_DM0\r
-SCSI_Out_DBx__0__DM1 EQU CYREG_PRT6_DM1\r
-SCSI_Out_DBx__0__DM2 EQU CYREG_PRT6_DM2\r
-SCSI_Out_DBx__0__DR EQU CYREG_PRT6_DR\r
-SCSI_Out_DBx__0__INP_DIS EQU CYREG_PRT6_INP_DIS\r
-SCSI_Out_DBx__0__INTTYPE EQU CYREG_PICU6_INTTYPE3\r
-SCSI_Out_DBx__0__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
-SCSI_Out_DBx__0__LCD_EN EQU CYREG_PRT6_LCD_EN\r
-SCSI_Out_DBx__0__MASK EQU 0x08\r
-SCSI_Out_DBx__0__PC EQU CYREG_PRT6_PC3\r
-SCSI_Out_DBx__0__PORT EQU 6\r
-SCSI_Out_DBx__0__PRT EQU CYREG_PRT6_PRT\r
-SCSI_Out_DBx__0__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
-SCSI_Out_DBx__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
-SCSI_Out_DBx__0__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
-SCSI_Out_DBx__0__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
-SCSI_Out_DBx__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
-SCSI_Out_DBx__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
-SCSI_Out_DBx__0__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
-SCSI_Out_DBx__0__PS EQU CYREG_PRT6_PS\r
-SCSI_Out_DBx__0__SHIFT EQU 3\r
-SCSI_Out_DBx__0__SLW EQU CYREG_PRT6_SLW\r
-SCSI_Out_DBx__1__AG EQU CYREG_PRT6_AG\r
-SCSI_Out_DBx__1__AMUX EQU CYREG_PRT6_AMUX\r
-SCSI_Out_DBx__1__BIE EQU CYREG_PRT6_BIE\r
-SCSI_Out_DBx__1__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
-SCSI_Out_DBx__1__BYP EQU CYREG_PRT6_BYP\r
-SCSI_Out_DBx__1__CTL EQU CYREG_PRT6_CTL\r
-SCSI_Out_DBx__1__DM0 EQU CYREG_PRT6_DM0\r
-SCSI_Out_DBx__1__DM1 EQU CYREG_PRT6_DM1\r
-SCSI_Out_DBx__1__DM2 EQU CYREG_PRT6_DM2\r
-SCSI_Out_DBx__1__DR EQU CYREG_PRT6_DR\r
-SCSI_Out_DBx__1__INP_DIS EQU CYREG_PRT6_INP_DIS\r
-SCSI_Out_DBx__1__INTTYPE EQU CYREG_PICU6_INTTYPE2\r
-SCSI_Out_DBx__1__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
-SCSI_Out_DBx__1__LCD_EN EQU CYREG_PRT6_LCD_EN\r
-SCSI_Out_DBx__1__MASK EQU 0x04\r
-SCSI_Out_DBx__1__PC EQU CYREG_PRT6_PC2\r
-SCSI_Out_DBx__1__PORT EQU 6\r
-SCSI_Out_DBx__1__PRT EQU CYREG_PRT6_PRT\r
-SCSI_Out_DBx__1__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
-SCSI_Out_DBx__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
-SCSI_Out_DBx__1__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
-SCSI_Out_DBx__1__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
-SCSI_Out_DBx__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
-SCSI_Out_DBx__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
-SCSI_Out_DBx__1__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
-SCSI_Out_DBx__1__PS EQU CYREG_PRT6_PS\r
-SCSI_Out_DBx__1__SHIFT EQU 2\r
-SCSI_Out_DBx__1__SLW EQU CYREG_PRT6_SLW\r
-SCSI_Out_DBx__2__AG EQU CYREG_PRT6_AG\r
-SCSI_Out_DBx__2__AMUX EQU CYREG_PRT6_AMUX\r
-SCSI_Out_DBx__2__BIE EQU CYREG_PRT6_BIE\r
-SCSI_Out_DBx__2__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
-SCSI_Out_DBx__2__BYP EQU CYREG_PRT6_BYP\r
-SCSI_Out_DBx__2__CTL EQU CYREG_PRT6_CTL\r
-SCSI_Out_DBx__2__DM0 EQU CYREG_PRT6_DM0\r
-SCSI_Out_DBx__2__DM1 EQU CYREG_PRT6_DM1\r
-SCSI_Out_DBx__2__DM2 EQU CYREG_PRT6_DM2\r
-SCSI_Out_DBx__2__DR EQU CYREG_PRT6_DR\r
-SCSI_Out_DBx__2__INP_DIS EQU CYREG_PRT6_INP_DIS\r
-SCSI_Out_DBx__2__INTTYPE EQU CYREG_PICU6_INTTYPE1\r
-SCSI_Out_DBx__2__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
-SCSI_Out_DBx__2__LCD_EN EQU CYREG_PRT6_LCD_EN\r
-SCSI_Out_DBx__2__MASK EQU 0x02\r
-SCSI_Out_DBx__2__PC EQU CYREG_PRT6_PC1\r
-SCSI_Out_DBx__2__PORT EQU 6\r
-SCSI_Out_DBx__2__PRT EQU CYREG_PRT6_PRT\r
-SCSI_Out_DBx__2__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
-SCSI_Out_DBx__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
-SCSI_Out_DBx__2__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
-SCSI_Out_DBx__2__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
-SCSI_Out_DBx__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
-SCSI_Out_DBx__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
-SCSI_Out_DBx__2__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
-SCSI_Out_DBx__2__PS EQU CYREG_PRT6_PS\r
-SCSI_Out_DBx__2__SHIFT EQU 1\r
-SCSI_Out_DBx__2__SLW EQU CYREG_PRT6_SLW\r
-SCSI_Out_DBx__3__AG EQU CYREG_PRT6_AG\r
-SCSI_Out_DBx__3__AMUX EQU CYREG_PRT6_AMUX\r
-SCSI_Out_DBx__3__BIE EQU CYREG_PRT6_BIE\r
-SCSI_Out_DBx__3__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
-SCSI_Out_DBx__3__BYP EQU CYREG_PRT6_BYP\r
-SCSI_Out_DBx__3__CTL EQU CYREG_PRT6_CTL\r
-SCSI_Out_DBx__3__DM0 EQU CYREG_PRT6_DM0\r
-SCSI_Out_DBx__3__DM1 EQU CYREG_PRT6_DM1\r
-SCSI_Out_DBx__3__DM2 EQU CYREG_PRT6_DM2\r
-SCSI_Out_DBx__3__DR EQU CYREG_PRT6_DR\r
-SCSI_Out_DBx__3__INP_DIS EQU CYREG_PRT6_INP_DIS\r
-SCSI_Out_DBx__3__INTTYPE EQU CYREG_PICU6_INTTYPE0\r
-SCSI_Out_DBx__3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
-SCSI_Out_DBx__3__LCD_EN EQU CYREG_PRT6_LCD_EN\r
-SCSI_Out_DBx__3__MASK EQU 0x01\r
-SCSI_Out_DBx__3__PC EQU CYREG_PRT6_PC0\r
-SCSI_Out_DBx__3__PORT EQU 6\r
-SCSI_Out_DBx__3__PRT EQU CYREG_PRT6_PRT\r
-SCSI_Out_DBx__3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
-SCSI_Out_DBx__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
-SCSI_Out_DBx__3__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
-SCSI_Out_DBx__3__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
-SCSI_Out_DBx__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
-SCSI_Out_DBx__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
-SCSI_Out_DBx__3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
-SCSI_Out_DBx__3__PS EQU CYREG_PRT6_PS\r
-SCSI_Out_DBx__3__SHIFT EQU 0\r
-SCSI_Out_DBx__3__SLW EQU CYREG_PRT6_SLW\r
-SCSI_Out_DBx__4__AG EQU CYREG_PRT4_AG\r
-SCSI_Out_DBx__4__AMUX EQU CYREG_PRT4_AMUX\r
-SCSI_Out_DBx__4__BIE EQU CYREG_PRT4_BIE\r
-SCSI_Out_DBx__4__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
-SCSI_Out_DBx__4__BYP EQU CYREG_PRT4_BYP\r
-SCSI_Out_DBx__4__CTL EQU CYREG_PRT4_CTL\r
-SCSI_Out_DBx__4__DM0 EQU CYREG_PRT4_DM0\r
-SCSI_Out_DBx__4__DM1 EQU CYREG_PRT4_DM1\r
-SCSI_Out_DBx__4__DM2 EQU CYREG_PRT4_DM2\r
-SCSI_Out_DBx__4__DR EQU CYREG_PRT4_DR\r
-SCSI_Out_DBx__4__INP_DIS EQU CYREG_PRT4_INP_DIS\r
-SCSI_Out_DBx__4__INTTYPE EQU CYREG_PICU4_INTTYPE7\r
-SCSI_Out_DBx__4__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
-SCSI_Out_DBx__4__LCD_EN EQU CYREG_PRT4_LCD_EN\r
-SCSI_Out_DBx__4__MASK EQU 0x80\r
-SCSI_Out_DBx__4__PC EQU CYREG_PRT4_PC7\r
-SCSI_Out_DBx__4__PORT EQU 4\r
-SCSI_Out_DBx__4__PRT EQU CYREG_PRT4_PRT\r
-SCSI_Out_DBx__4__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
-SCSI_Out_DBx__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
-SCSI_Out_DBx__4__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
-SCSI_Out_DBx__4__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
-SCSI_Out_DBx__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
-SCSI_Out_DBx__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
-SCSI_Out_DBx__4__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
-SCSI_Out_DBx__4__PS EQU CYREG_PRT4_PS\r
-SCSI_Out_DBx__4__SHIFT EQU 7\r
-SCSI_Out_DBx__4__SLW EQU CYREG_PRT4_SLW\r
-SCSI_Out_DBx__5__AG EQU CYREG_PRT4_AG\r
-SCSI_Out_DBx__5__AMUX EQU CYREG_PRT4_AMUX\r
-SCSI_Out_DBx__5__BIE EQU CYREG_PRT4_BIE\r
-SCSI_Out_DBx__5__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
-SCSI_Out_DBx__5__BYP EQU CYREG_PRT4_BYP\r
-SCSI_Out_DBx__5__CTL EQU CYREG_PRT4_CTL\r
-SCSI_Out_DBx__5__DM0 EQU CYREG_PRT4_DM0\r
-SCSI_Out_DBx__5__DM1 EQU CYREG_PRT4_DM1\r
-SCSI_Out_DBx__5__DM2 EQU CYREG_PRT4_DM2\r
-SCSI_Out_DBx__5__DR EQU CYREG_PRT4_DR\r
-SCSI_Out_DBx__5__INP_DIS EQU CYREG_PRT4_INP_DIS\r
-SCSI_Out_DBx__5__INTTYPE EQU CYREG_PICU4_INTTYPE6\r
-SCSI_Out_DBx__5__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
-SCSI_Out_DBx__5__LCD_EN EQU CYREG_PRT4_LCD_EN\r
-SCSI_Out_DBx__5__MASK EQU 0x40\r
-SCSI_Out_DBx__5__PC EQU CYREG_PRT4_PC6\r
-SCSI_Out_DBx__5__PORT EQU 4\r
-SCSI_Out_DBx__5__PRT EQU CYREG_PRT4_PRT\r
-SCSI_Out_DBx__5__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
-SCSI_Out_DBx__5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
-SCSI_Out_DBx__5__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
-SCSI_Out_DBx__5__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
-SCSI_Out_DBx__5__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
-SCSI_Out_DBx__5__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
-SCSI_Out_DBx__5__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
-SCSI_Out_DBx__5__PS EQU CYREG_PRT4_PS\r
-SCSI_Out_DBx__5__SHIFT EQU 6\r
-SCSI_Out_DBx__5__SLW EQU CYREG_PRT4_SLW\r
-SCSI_Out_DBx__6__AG EQU CYREG_PRT4_AG\r
-SCSI_Out_DBx__6__AMUX EQU CYREG_PRT4_AMUX\r
-SCSI_Out_DBx__6__BIE EQU CYREG_PRT4_BIE\r
-SCSI_Out_DBx__6__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
-SCSI_Out_DBx__6__BYP EQU CYREG_PRT4_BYP\r
-SCSI_Out_DBx__6__CTL EQU CYREG_PRT4_CTL\r
-SCSI_Out_DBx__6__DM0 EQU CYREG_PRT4_DM0\r
-SCSI_Out_DBx__6__DM1 EQU CYREG_PRT4_DM1\r
-SCSI_Out_DBx__6__DM2 EQU CYREG_PRT4_DM2\r
-SCSI_Out_DBx__6__DR EQU CYREG_PRT4_DR\r
-SCSI_Out_DBx__6__INP_DIS EQU CYREG_PRT4_INP_DIS\r
-SCSI_Out_DBx__6__INTTYPE EQU CYREG_PICU4_INTTYPE5\r
-SCSI_Out_DBx__6__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
-SCSI_Out_DBx__6__LCD_EN EQU CYREG_PRT4_LCD_EN\r
-SCSI_Out_DBx__6__MASK EQU 0x20\r
-SCSI_Out_DBx__6__PC EQU CYREG_PRT4_PC5\r
-SCSI_Out_DBx__6__PORT EQU 4\r
-SCSI_Out_DBx__6__PRT EQU CYREG_PRT4_PRT\r
-SCSI_Out_DBx__6__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
-SCSI_Out_DBx__6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
-SCSI_Out_DBx__6__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
-SCSI_Out_DBx__6__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
-SCSI_Out_DBx__6__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
-SCSI_Out_DBx__6__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
-SCSI_Out_DBx__6__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
-SCSI_Out_DBx__6__PS EQU CYREG_PRT4_PS\r
-SCSI_Out_DBx__6__SHIFT EQU 5\r
-SCSI_Out_DBx__6__SLW EQU CYREG_PRT4_SLW\r
-SCSI_Out_DBx__7__AG EQU CYREG_PRT4_AG\r
-SCSI_Out_DBx__7__AMUX EQU CYREG_PRT4_AMUX\r
-SCSI_Out_DBx__7__BIE EQU CYREG_PRT4_BIE\r
-SCSI_Out_DBx__7__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
-SCSI_Out_DBx__7__BYP EQU CYREG_PRT4_BYP\r
-SCSI_Out_DBx__7__CTL EQU CYREG_PRT4_CTL\r
-SCSI_Out_DBx__7__DM0 EQU CYREG_PRT4_DM0\r
-SCSI_Out_DBx__7__DM1 EQU CYREG_PRT4_DM1\r
-SCSI_Out_DBx__7__DM2 EQU CYREG_PRT4_DM2\r
-SCSI_Out_DBx__7__DR EQU CYREG_PRT4_DR\r
-SCSI_Out_DBx__7__INP_DIS EQU CYREG_PRT4_INP_DIS\r
-SCSI_Out_DBx__7__INTTYPE EQU CYREG_PICU4_INTTYPE4\r
-SCSI_Out_DBx__7__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
-SCSI_Out_DBx__7__LCD_EN EQU CYREG_PRT4_LCD_EN\r
-SCSI_Out_DBx__7__MASK EQU 0x10\r
-SCSI_Out_DBx__7__PC EQU CYREG_PRT4_PC4\r
-SCSI_Out_DBx__7__PORT EQU 4\r
-SCSI_Out_DBx__7__PRT EQU CYREG_PRT4_PRT\r
-SCSI_Out_DBx__7__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
-SCSI_Out_DBx__7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
-SCSI_Out_DBx__7__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
-SCSI_Out_DBx__7__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
-SCSI_Out_DBx__7__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
-SCSI_Out_DBx__7__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
-SCSI_Out_DBx__7__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
-SCSI_Out_DBx__7__PS EQU CYREG_PRT4_PS\r
-SCSI_Out_DBx__7__SHIFT EQU 4\r
-SCSI_Out_DBx__7__SLW EQU CYREG_PRT4_SLW\r
-SCSI_Out_DBx__DB0__AG EQU CYREG_PRT6_AG\r
-SCSI_Out_DBx__DB0__AMUX EQU CYREG_PRT6_AMUX\r
-SCSI_Out_DBx__DB0__BIE EQU CYREG_PRT6_BIE\r
-SCSI_Out_DBx__DB0__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
-SCSI_Out_DBx__DB0__BYP EQU CYREG_PRT6_BYP\r
-SCSI_Out_DBx__DB0__CTL EQU CYREG_PRT6_CTL\r
-SCSI_Out_DBx__DB0__DM0 EQU CYREG_PRT6_DM0\r
-SCSI_Out_DBx__DB0__DM1 EQU CYREG_PRT6_DM1\r
-SCSI_Out_DBx__DB0__DM2 EQU CYREG_PRT6_DM2\r
-SCSI_Out_DBx__DB0__DR EQU CYREG_PRT6_DR\r
-SCSI_Out_DBx__DB0__INP_DIS EQU CYREG_PRT6_INP_DIS\r
-SCSI_Out_DBx__DB0__INTTYPE EQU CYREG_PICU6_INTTYPE3\r
-SCSI_Out_DBx__DB0__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
-SCSI_Out_DBx__DB0__LCD_EN EQU CYREG_PRT6_LCD_EN\r
-SCSI_Out_DBx__DB0__MASK EQU 0x08\r
-SCSI_Out_DBx__DB0__PC EQU CYREG_PRT6_PC3\r
-SCSI_Out_DBx__DB0__PORT EQU 6\r
-SCSI_Out_DBx__DB0__PRT EQU CYREG_PRT6_PRT\r
-SCSI_Out_DBx__DB0__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
-SCSI_Out_DBx__DB0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
-SCSI_Out_DBx__DB0__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
-SCSI_Out_DBx__DB0__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
-SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
-SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
-SCSI_Out_DBx__DB0__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
-SCSI_Out_DBx__DB0__PS EQU CYREG_PRT6_PS\r
-SCSI_Out_DBx__DB0__SHIFT EQU 3\r
-SCSI_Out_DBx__DB0__SLW EQU CYREG_PRT6_SLW\r
-SCSI_Out_DBx__DB1__AG EQU CYREG_PRT6_AG\r
-SCSI_Out_DBx__DB1__AMUX EQU CYREG_PRT6_AMUX\r
-SCSI_Out_DBx__DB1__BIE EQU CYREG_PRT6_BIE\r
-SCSI_Out_DBx__DB1__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
-SCSI_Out_DBx__DB1__BYP EQU CYREG_PRT6_BYP\r
-SCSI_Out_DBx__DB1__CTL EQU CYREG_PRT6_CTL\r
-SCSI_Out_DBx__DB1__DM0 EQU CYREG_PRT6_DM0\r
-SCSI_Out_DBx__DB1__DM1 EQU CYREG_PRT6_DM1\r
-SCSI_Out_DBx__DB1__DM2 EQU CYREG_PRT6_DM2\r
-SCSI_Out_DBx__DB1__DR EQU CYREG_PRT6_DR\r
-SCSI_Out_DBx__DB1__INP_DIS EQU CYREG_PRT6_INP_DIS\r
-SCSI_Out_DBx__DB1__INTTYPE EQU CYREG_PICU6_INTTYPE2\r
-SCSI_Out_DBx__DB1__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
-SCSI_Out_DBx__DB1__LCD_EN EQU CYREG_PRT6_LCD_EN\r
-SCSI_Out_DBx__DB1__MASK EQU 0x04\r
-SCSI_Out_DBx__DB1__PC EQU CYREG_PRT6_PC2\r
-SCSI_Out_DBx__DB1__PORT EQU 6\r
-SCSI_Out_DBx__DB1__PRT EQU CYREG_PRT6_PRT\r
-SCSI_Out_DBx__DB1__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
-SCSI_Out_DBx__DB1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
-SCSI_Out_DBx__DB1__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
-SCSI_Out_DBx__DB1__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
-SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
-SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
-SCSI_Out_DBx__DB1__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
-SCSI_Out_DBx__DB1__PS EQU CYREG_PRT6_PS\r
-SCSI_Out_DBx__DB1__SHIFT EQU 2\r
-SCSI_Out_DBx__DB1__SLW EQU CYREG_PRT6_SLW\r
-SCSI_Out_DBx__DB2__AG EQU CYREG_PRT6_AG\r
-SCSI_Out_DBx__DB2__AMUX EQU CYREG_PRT6_AMUX\r
-SCSI_Out_DBx__DB2__BIE EQU CYREG_PRT6_BIE\r
-SCSI_Out_DBx__DB2__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
-SCSI_Out_DBx__DB2__BYP EQU CYREG_PRT6_BYP\r
-SCSI_Out_DBx__DB2__CTL EQU CYREG_PRT6_CTL\r
-SCSI_Out_DBx__DB2__DM0 EQU CYREG_PRT6_DM0\r
-SCSI_Out_DBx__DB2__DM1 EQU CYREG_PRT6_DM1\r
-SCSI_Out_DBx__DB2__DM2 EQU CYREG_PRT6_DM2\r
-SCSI_Out_DBx__DB2__DR EQU CYREG_PRT6_DR\r
-SCSI_Out_DBx__DB2__INP_DIS EQU CYREG_PRT6_INP_DIS\r
-SCSI_Out_DBx__DB2__INTTYPE EQU CYREG_PICU6_INTTYPE1\r
-SCSI_Out_DBx__DB2__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
-SCSI_Out_DBx__DB2__LCD_EN EQU CYREG_PRT6_LCD_EN\r
-SCSI_Out_DBx__DB2__MASK EQU 0x02\r
-SCSI_Out_DBx__DB2__PC EQU CYREG_PRT6_PC1\r
-SCSI_Out_DBx__DB2__PORT EQU 6\r
-SCSI_Out_DBx__DB2__PRT EQU CYREG_PRT6_PRT\r
-SCSI_Out_DBx__DB2__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
-SCSI_Out_DBx__DB2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
-SCSI_Out_DBx__DB2__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
-SCSI_Out_DBx__DB2__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
-SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
-SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
-SCSI_Out_DBx__DB2__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
-SCSI_Out_DBx__DB2__PS EQU CYREG_PRT6_PS\r
-SCSI_Out_DBx__DB2__SHIFT EQU 1\r
-SCSI_Out_DBx__DB2__SLW EQU CYREG_PRT6_SLW\r
-SCSI_Out_DBx__DB3__AG EQU CYREG_PRT6_AG\r
-SCSI_Out_DBx__DB3__AMUX EQU CYREG_PRT6_AMUX\r
-SCSI_Out_DBx__DB3__BIE EQU CYREG_PRT6_BIE\r
-SCSI_Out_DBx__DB3__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
-SCSI_Out_DBx__DB3__BYP EQU CYREG_PRT6_BYP\r
-SCSI_Out_DBx__DB3__CTL EQU CYREG_PRT6_CTL\r
-SCSI_Out_DBx__DB3__DM0 EQU CYREG_PRT6_DM0\r
-SCSI_Out_DBx__DB3__DM1 EQU CYREG_PRT6_DM1\r
-SCSI_Out_DBx__DB3__DM2 EQU CYREG_PRT6_DM2\r
-SCSI_Out_DBx__DB3__DR EQU CYREG_PRT6_DR\r
-SCSI_Out_DBx__DB3__INP_DIS EQU CYREG_PRT6_INP_DIS\r
-SCSI_Out_DBx__DB3__INTTYPE EQU CYREG_PICU6_INTTYPE0\r
-SCSI_Out_DBx__DB3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
-SCSI_Out_DBx__DB3__LCD_EN EQU CYREG_PRT6_LCD_EN\r
-SCSI_Out_DBx__DB3__MASK EQU 0x01\r
-SCSI_Out_DBx__DB3__PC EQU CYREG_PRT6_PC0\r
-SCSI_Out_DBx__DB3__PORT EQU 6\r
-SCSI_Out_DBx__DB3__PRT EQU CYREG_PRT6_PRT\r
-SCSI_Out_DBx__DB3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
-SCSI_Out_DBx__DB3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
-SCSI_Out_DBx__DB3__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
-SCSI_Out_DBx__DB3__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
-SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
-SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
-SCSI_Out_DBx__DB3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
-SCSI_Out_DBx__DB3__PS EQU CYREG_PRT6_PS\r
-SCSI_Out_DBx__DB3__SHIFT EQU 0\r
-SCSI_Out_DBx__DB3__SLW EQU CYREG_PRT6_SLW\r
-SCSI_Out_DBx__DB4__AG EQU CYREG_PRT4_AG\r
-SCSI_Out_DBx__DB4__AMUX EQU CYREG_PRT4_AMUX\r
-SCSI_Out_DBx__DB4__BIE EQU CYREG_PRT4_BIE\r
-SCSI_Out_DBx__DB4__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
-SCSI_Out_DBx__DB4__BYP EQU CYREG_PRT4_BYP\r
-SCSI_Out_DBx__DB4__CTL EQU CYREG_PRT4_CTL\r
-SCSI_Out_DBx__DB4__DM0 EQU CYREG_PRT4_DM0\r
-SCSI_Out_DBx__DB4__DM1 EQU CYREG_PRT4_DM1\r
-SCSI_Out_DBx__DB4__DM2 EQU CYREG_PRT4_DM2\r
-SCSI_Out_DBx__DB4__DR EQU CYREG_PRT4_DR\r
-SCSI_Out_DBx__DB4__INP_DIS EQU CYREG_PRT4_INP_DIS\r
-SCSI_Out_DBx__DB4__INTTYPE EQU CYREG_PICU4_INTTYPE7\r
-SCSI_Out_DBx__DB4__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
-SCSI_Out_DBx__DB4__LCD_EN EQU CYREG_PRT4_LCD_EN\r
-SCSI_Out_DBx__DB4__MASK EQU 0x80\r
-SCSI_Out_DBx__DB4__PC EQU CYREG_PRT4_PC7\r
-SCSI_Out_DBx__DB4__PORT EQU 4\r
-SCSI_Out_DBx__DB4__PRT EQU CYREG_PRT4_PRT\r
-SCSI_Out_DBx__DB4__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
-SCSI_Out_DBx__DB4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
-SCSI_Out_DBx__DB4__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
-SCSI_Out_DBx__DB4__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
-SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
-SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
-SCSI_Out_DBx__DB4__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
-SCSI_Out_DBx__DB4__PS EQU CYREG_PRT4_PS\r
-SCSI_Out_DBx__DB4__SHIFT EQU 7\r
-SCSI_Out_DBx__DB4__SLW EQU CYREG_PRT4_SLW\r
-SCSI_Out_DBx__DB5__AG EQU CYREG_PRT4_AG\r
-SCSI_Out_DBx__DB5__AMUX EQU CYREG_PRT4_AMUX\r
-SCSI_Out_DBx__DB5__BIE EQU CYREG_PRT4_BIE\r
-SCSI_Out_DBx__DB5__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
-SCSI_Out_DBx__DB5__BYP EQU CYREG_PRT4_BYP\r
-SCSI_Out_DBx__DB5__CTL EQU CYREG_PRT4_CTL\r
-SCSI_Out_DBx__DB5__DM0 EQU CYREG_PRT4_DM0\r
-SCSI_Out_DBx__DB5__DM1 EQU CYREG_PRT4_DM1\r
-SCSI_Out_DBx__DB5__DM2 EQU CYREG_PRT4_DM2\r
-SCSI_Out_DBx__DB5__DR EQU CYREG_PRT4_DR\r
-SCSI_Out_DBx__DB5__INP_DIS EQU CYREG_PRT4_INP_DIS\r
-SCSI_Out_DBx__DB5__INTTYPE EQU CYREG_PICU4_INTTYPE6\r
-SCSI_Out_DBx__DB5__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
-SCSI_Out_DBx__DB5__LCD_EN EQU CYREG_PRT4_LCD_EN\r
-SCSI_Out_DBx__DB5__MASK EQU 0x40\r
-SCSI_Out_DBx__DB5__PC EQU CYREG_PRT4_PC6\r
-SCSI_Out_DBx__DB5__PORT EQU 4\r
-SCSI_Out_DBx__DB5__PRT EQU CYREG_PRT4_PRT\r
-SCSI_Out_DBx__DB5__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
-SCSI_Out_DBx__DB5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
-SCSI_Out_DBx__DB5__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
-SCSI_Out_DBx__DB5__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
-SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
-SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
-SCSI_Out_DBx__DB5__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
-SCSI_Out_DBx__DB5__PS EQU CYREG_PRT4_PS\r
-SCSI_Out_DBx__DB5__SHIFT EQU 6\r
-SCSI_Out_DBx__DB5__SLW EQU CYREG_PRT4_SLW\r
-SCSI_Out_DBx__DB6__AG EQU CYREG_PRT4_AG\r
-SCSI_Out_DBx__DB6__AMUX EQU CYREG_PRT4_AMUX\r
-SCSI_Out_DBx__DB6__BIE EQU CYREG_PRT4_BIE\r
-SCSI_Out_DBx__DB6__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
-SCSI_Out_DBx__DB6__BYP EQU CYREG_PRT4_BYP\r
-SCSI_Out_DBx__DB6__CTL EQU CYREG_PRT4_CTL\r
-SCSI_Out_DBx__DB6__DM0 EQU CYREG_PRT4_DM0\r
-SCSI_Out_DBx__DB6__DM1 EQU CYREG_PRT4_DM1\r
-SCSI_Out_DBx__DB6__DM2 EQU CYREG_PRT4_DM2\r
-SCSI_Out_DBx__DB6__DR EQU CYREG_PRT4_DR\r
-SCSI_Out_DBx__DB6__INP_DIS EQU CYREG_PRT4_INP_DIS\r
-SCSI_Out_DBx__DB6__INTTYPE EQU CYREG_PICU4_INTTYPE5\r
-SCSI_Out_DBx__DB6__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
-SCSI_Out_DBx__DB6__LCD_EN EQU CYREG_PRT4_LCD_EN\r
-SCSI_Out_DBx__DB6__MASK EQU 0x20\r
-SCSI_Out_DBx__DB6__PC EQU CYREG_PRT4_PC5\r
-SCSI_Out_DBx__DB6__PORT EQU 4\r
-SCSI_Out_DBx__DB6__PRT EQU CYREG_PRT4_PRT\r
-SCSI_Out_DBx__DB6__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
-SCSI_Out_DBx__DB6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
-SCSI_Out_DBx__DB6__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
-SCSI_Out_DBx__DB6__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
-SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
-SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
-SCSI_Out_DBx__DB6__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
-SCSI_Out_DBx__DB6__PS EQU CYREG_PRT4_PS\r
-SCSI_Out_DBx__DB6__SHIFT EQU 5\r
-SCSI_Out_DBx__DB6__SLW EQU CYREG_PRT4_SLW\r
-SCSI_Out_DBx__DB7__AG EQU CYREG_PRT4_AG\r
-SCSI_Out_DBx__DB7__AMUX EQU CYREG_PRT4_AMUX\r
-SCSI_Out_DBx__DB7__BIE EQU CYREG_PRT4_BIE\r
-SCSI_Out_DBx__DB7__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
-SCSI_Out_DBx__DB7__BYP EQU CYREG_PRT4_BYP\r
-SCSI_Out_DBx__DB7__CTL EQU CYREG_PRT4_CTL\r
-SCSI_Out_DBx__DB7__DM0 EQU CYREG_PRT4_DM0\r
-SCSI_Out_DBx__DB7__DM1 EQU CYREG_PRT4_DM1\r
-SCSI_Out_DBx__DB7__DM2 EQU CYREG_PRT4_DM2\r
-SCSI_Out_DBx__DB7__DR EQU CYREG_PRT4_DR\r
-SCSI_Out_DBx__DB7__INP_DIS EQU CYREG_PRT4_INP_DIS\r
-SCSI_Out_DBx__DB7__INTTYPE EQU CYREG_PICU4_INTTYPE4\r
-SCSI_Out_DBx__DB7__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
-SCSI_Out_DBx__DB7__LCD_EN EQU CYREG_PRT4_LCD_EN\r
-SCSI_Out_DBx__DB7__MASK EQU 0x10\r
-SCSI_Out_DBx__DB7__PC EQU CYREG_PRT4_PC4\r
-SCSI_Out_DBx__DB7__PORT EQU 4\r
-SCSI_Out_DBx__DB7__PRT EQU CYREG_PRT4_PRT\r
-SCSI_Out_DBx__DB7__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
-SCSI_Out_DBx__DB7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
-SCSI_Out_DBx__DB7__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
-SCSI_Out_DBx__DB7__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
-SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
-SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
-SCSI_Out_DBx__DB7__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
-SCSI_Out_DBx__DB7__PS EQU CYREG_PRT4_PS\r
-SCSI_Out_DBx__DB7__SHIFT EQU 4\r
-SCSI_Out_DBx__DB7__SLW EQU CYREG_PRT4_SLW\r
-\r
-; SD_RX_DMA\r
-SD_RX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0\r
-SD_RX_DMA__DRQ_NUMBER EQU 2\r
-SD_RX_DMA__NUMBEROF_TDS EQU 0\r
-SD_RX_DMA__PRIORITY EQU 0\r
-SD_RX_DMA__TERMIN_EN EQU 0\r
-SD_RX_DMA__TERMIN_SEL EQU 0\r
-SD_RX_DMA__TERMOUT0_EN EQU 1\r
-SD_RX_DMA__TERMOUT0_SEL EQU 2\r
-SD_RX_DMA__TERMOUT1_EN EQU 0\r
-SD_RX_DMA__TERMOUT1_SEL EQU 0\r
-\r
-; SD_RX_DMA_COMPLETE\r
-SD_RX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
-SD_RX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
-SD_RX_DMA_COMPLETE__INTC_MASK EQU 0x20\r
-SD_RX_DMA_COMPLETE__INTC_NUMBER EQU 5\r
-SD_RX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7\r
-SD_RX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_5\r
-SD_RX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
-SD_RX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
-\r
-; SD_TX_DMA\r
-SD_TX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0\r
-SD_TX_DMA__DRQ_NUMBER EQU 3\r
-SD_TX_DMA__NUMBEROF_TDS EQU 0\r
-SD_TX_DMA__PRIORITY EQU 1\r
-SD_TX_DMA__TERMIN_EN EQU 0\r
-SD_TX_DMA__TERMIN_SEL EQU 0\r
-SD_TX_DMA__TERMOUT0_EN EQU 1\r
-SD_TX_DMA__TERMOUT0_SEL EQU 3\r
-SD_TX_DMA__TERMOUT1_EN EQU 0\r
-SD_TX_DMA__TERMOUT1_SEL EQU 0\r
-\r
-; SD_TX_DMA_COMPLETE\r
-SD_TX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
-SD_TX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
-SD_TX_DMA_COMPLETE__INTC_MASK EQU 0x40\r
-SD_TX_DMA_COMPLETE__INTC_NUMBER EQU 6\r
-SD_TX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7\r
-SD_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_6\r
-SD_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
-SD_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
+; SCSI_In\r
+SCSI_In__0__AG EQU CYREG_PRT2_AG\r
+SCSI_In__0__AMUX EQU CYREG_PRT2_AMUX\r
+SCSI_In__0__BIE EQU CYREG_PRT2_BIE\r
+SCSI_In__0__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
+SCSI_In__0__BYP EQU CYREG_PRT2_BYP\r
+SCSI_In__0__CTL EQU CYREG_PRT2_CTL\r
+SCSI_In__0__DM0 EQU CYREG_PRT2_DM0\r
+SCSI_In__0__DM1 EQU CYREG_PRT2_DM1\r
+SCSI_In__0__DM2 EQU CYREG_PRT2_DM2\r
+SCSI_In__0__DR EQU CYREG_PRT2_DR\r
+SCSI_In__0__INP_DIS EQU CYREG_PRT2_INP_DIS\r
+SCSI_In__0__INTTYPE EQU CYREG_PICU2_INTTYPE0\r
+SCSI_In__0__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
+SCSI_In__0__LCD_EN EQU CYREG_PRT2_LCD_EN\r
+SCSI_In__0__MASK EQU 0x01\r
+SCSI_In__0__PC EQU CYREG_PRT2_PC0\r
+SCSI_In__0__PORT EQU 2\r
+SCSI_In__0__PRT EQU CYREG_PRT2_PRT\r
+SCSI_In__0__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
+SCSI_In__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
+SCSI_In__0__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
+SCSI_In__0__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
+SCSI_In__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
+SCSI_In__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
+SCSI_In__0__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
+SCSI_In__0__PS EQU CYREG_PRT2_PS\r
+SCSI_In__0__SHIFT EQU 0\r
+SCSI_In__0__SLW EQU CYREG_PRT2_SLW\r
+SCSI_In__1__AG EQU CYREG_PRT6_AG\r
+SCSI_In__1__AMUX EQU CYREG_PRT6_AMUX\r
+SCSI_In__1__BIE EQU CYREG_PRT6_BIE\r
+SCSI_In__1__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
+SCSI_In__1__BYP EQU CYREG_PRT6_BYP\r
+SCSI_In__1__CTL EQU CYREG_PRT6_CTL\r
+SCSI_In__1__DM0 EQU CYREG_PRT6_DM0\r
+SCSI_In__1__DM1 EQU CYREG_PRT6_DM1\r
+SCSI_In__1__DM2 EQU CYREG_PRT6_DM2\r
+SCSI_In__1__DR EQU CYREG_PRT6_DR\r
+SCSI_In__1__INP_DIS EQU CYREG_PRT6_INP_DIS\r
+SCSI_In__1__INTTYPE EQU CYREG_PICU6_INTTYPE7\r
+SCSI_In__1__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
+SCSI_In__1__LCD_EN EQU CYREG_PRT6_LCD_EN\r
+SCSI_In__1__MASK EQU 0x80\r
+SCSI_In__1__PC EQU CYREG_PRT6_PC7\r
+SCSI_In__1__PORT EQU 6\r
+SCSI_In__1__PRT EQU CYREG_PRT6_PRT\r
+SCSI_In__1__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
+SCSI_In__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
+SCSI_In__1__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
+SCSI_In__1__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
+SCSI_In__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
+SCSI_In__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
+SCSI_In__1__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
+SCSI_In__1__PS EQU CYREG_PRT6_PS\r
+SCSI_In__1__SHIFT EQU 7\r
+SCSI_In__1__SLW EQU CYREG_PRT6_SLW\r
+SCSI_In__2__AG EQU CYREG_PRT5_AG\r
+SCSI_In__2__AMUX EQU CYREG_PRT5_AMUX\r
+SCSI_In__2__BIE EQU CYREG_PRT5_BIE\r
+SCSI_In__2__BIT_MASK EQU CYREG_PRT5_BIT_MASK\r
+SCSI_In__2__BYP EQU CYREG_PRT5_BYP\r
+SCSI_In__2__CTL EQU CYREG_PRT5_CTL\r
+SCSI_In__2__DM0 EQU CYREG_PRT5_DM0\r
+SCSI_In__2__DM1 EQU CYREG_PRT5_DM1\r
+SCSI_In__2__DM2 EQU CYREG_PRT5_DM2\r
+SCSI_In__2__DR EQU CYREG_PRT5_DR\r
+SCSI_In__2__INP_DIS EQU CYREG_PRT5_INP_DIS\r
+SCSI_In__2__INTTYPE EQU CYREG_PICU5_INTTYPE1\r
+SCSI_In__2__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG\r
+SCSI_In__2__LCD_EN EQU CYREG_PRT5_LCD_EN\r
+SCSI_In__2__MASK EQU 0x02\r
+SCSI_In__2__PC EQU CYREG_PRT5_PC1\r
+SCSI_In__2__PORT EQU 5\r
+SCSI_In__2__PRT EQU CYREG_PRT5_PRT\r
+SCSI_In__2__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL\r
+SCSI_In__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN\r
+SCSI_In__2__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0\r
+SCSI_In__2__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1\r
+SCSI_In__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0\r
+SCSI_In__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1\r
+SCSI_In__2__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT\r
+SCSI_In__2__PS EQU CYREG_PRT5_PS\r
+SCSI_In__2__SHIFT EQU 1\r
+SCSI_In__2__SLW EQU CYREG_PRT5_SLW\r
+SCSI_In__3__AG EQU CYREG_PRT5_AG\r
+SCSI_In__3__AMUX EQU CYREG_PRT5_AMUX\r
+SCSI_In__3__BIE EQU CYREG_PRT5_BIE\r
+SCSI_In__3__BIT_MASK EQU CYREG_PRT5_BIT_MASK\r
+SCSI_In__3__BYP EQU CYREG_PRT5_BYP\r
+SCSI_In__3__CTL EQU CYREG_PRT5_CTL\r
+SCSI_In__3__DM0 EQU CYREG_PRT5_DM0\r
+SCSI_In__3__DM1 EQU CYREG_PRT5_DM1\r
+SCSI_In__3__DM2 EQU CYREG_PRT5_DM2\r
+SCSI_In__3__DR EQU CYREG_PRT5_DR\r
+SCSI_In__3__INP_DIS EQU CYREG_PRT5_INP_DIS\r
+SCSI_In__3__INTTYPE EQU CYREG_PICU5_INTTYPE2\r
+SCSI_In__3__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG\r
+SCSI_In__3__LCD_EN EQU CYREG_PRT5_LCD_EN\r
+SCSI_In__3__MASK EQU 0x04\r
+SCSI_In__3__PC EQU CYREG_PRT5_PC2\r
+SCSI_In__3__PORT EQU 5\r
+SCSI_In__3__PRT EQU CYREG_PRT5_PRT\r
+SCSI_In__3__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL\r
+SCSI_In__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN\r
+SCSI_In__3__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0\r
+SCSI_In__3__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1\r
+SCSI_In__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0\r
+SCSI_In__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1\r
+SCSI_In__3__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT\r
+SCSI_In__3__PS EQU CYREG_PRT5_PS\r
+SCSI_In__3__SHIFT EQU 2\r
+SCSI_In__3__SLW EQU CYREG_PRT5_SLW\r
+SCSI_In__4__AG EQU CYREG_PRT5_AG\r
+SCSI_In__4__AMUX EQU CYREG_PRT5_AMUX\r
+SCSI_In__4__BIE EQU CYREG_PRT5_BIE\r
+SCSI_In__4__BIT_MASK EQU CYREG_PRT5_BIT_MASK\r
+SCSI_In__4__BYP EQU CYREG_PRT5_BYP\r
+SCSI_In__4__CTL EQU CYREG_PRT5_CTL\r
+SCSI_In__4__DM0 EQU CYREG_PRT5_DM0\r
+SCSI_In__4__DM1 EQU CYREG_PRT5_DM1\r
+SCSI_In__4__DM2 EQU CYREG_PRT5_DM2\r
+SCSI_In__4__DR EQU CYREG_PRT5_DR\r
+SCSI_In__4__INP_DIS EQU CYREG_PRT5_INP_DIS\r
+SCSI_In__4__INTTYPE EQU CYREG_PICU5_INTTYPE3\r
+SCSI_In__4__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG\r
+SCSI_In__4__LCD_EN EQU CYREG_PRT5_LCD_EN\r
+SCSI_In__4__MASK EQU 0x08\r
+SCSI_In__4__PC EQU CYREG_PRT5_PC3\r
+SCSI_In__4__PORT EQU 5\r
+SCSI_In__4__PRT EQU CYREG_PRT5_PRT\r
+SCSI_In__4__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL\r
+SCSI_In__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN\r
+SCSI_In__4__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0\r
+SCSI_In__4__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1\r
+SCSI_In__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0\r
+SCSI_In__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1\r
+SCSI_In__4__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT\r
+SCSI_In__4__PS EQU CYREG_PRT5_PS\r
+SCSI_In__4__SHIFT EQU 3\r
+SCSI_In__4__SLW EQU CYREG_PRT5_SLW\r
+SCSI_In__CD__AG EQU CYREG_PRT5_AG\r
+SCSI_In__CD__AMUX EQU CYREG_PRT5_AMUX\r
+SCSI_In__CD__BIE EQU CYREG_PRT5_BIE\r
+SCSI_In__CD__BIT_MASK EQU CYREG_PRT5_BIT_MASK\r
+SCSI_In__CD__BYP EQU CYREG_PRT5_BYP\r
+SCSI_In__CD__CTL EQU CYREG_PRT5_CTL\r
+SCSI_In__CD__DM0 EQU CYREG_PRT5_DM0\r
+SCSI_In__CD__DM1 EQU CYREG_PRT5_DM1\r
+SCSI_In__CD__DM2 EQU CYREG_PRT5_DM2\r
+SCSI_In__CD__DR EQU CYREG_PRT5_DR\r
+SCSI_In__CD__INP_DIS EQU CYREG_PRT5_INP_DIS\r
+SCSI_In__CD__INTTYPE EQU CYREG_PICU5_INTTYPE1\r
+SCSI_In__CD__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG\r
+SCSI_In__CD__LCD_EN EQU CYREG_PRT5_LCD_EN\r
+SCSI_In__CD__MASK EQU 0x02\r
+SCSI_In__CD__PC EQU CYREG_PRT5_PC1\r
+SCSI_In__CD__PORT EQU 5\r
+SCSI_In__CD__PRT EQU CYREG_PRT5_PRT\r
+SCSI_In__CD__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL\r
+SCSI_In__CD__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN\r
+SCSI_In__CD__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0\r
+SCSI_In__CD__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1\r
+SCSI_In__CD__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0\r
+SCSI_In__CD__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1\r
+SCSI_In__CD__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT\r
+SCSI_In__CD__PS EQU CYREG_PRT5_PS\r
+SCSI_In__CD__SHIFT EQU 1\r
+SCSI_In__CD__SLW EQU CYREG_PRT5_SLW\r
+SCSI_In__DBP__AG EQU CYREG_PRT2_AG\r
+SCSI_In__DBP__AMUX EQU CYREG_PRT2_AMUX\r
+SCSI_In__DBP__BIE EQU CYREG_PRT2_BIE\r
+SCSI_In__DBP__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
+SCSI_In__DBP__BYP EQU CYREG_PRT2_BYP\r
+SCSI_In__DBP__CTL EQU CYREG_PRT2_CTL\r
+SCSI_In__DBP__DM0 EQU CYREG_PRT2_DM0\r
+SCSI_In__DBP__DM1 EQU CYREG_PRT2_DM1\r
+SCSI_In__DBP__DM2 EQU CYREG_PRT2_DM2\r
+SCSI_In__DBP__DR EQU CYREG_PRT2_DR\r
+SCSI_In__DBP__INP_DIS EQU CYREG_PRT2_INP_DIS\r
+SCSI_In__DBP__INTTYPE EQU CYREG_PICU2_INTTYPE0\r
+SCSI_In__DBP__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
+SCSI_In__DBP__LCD_EN EQU CYREG_PRT2_LCD_EN\r
+SCSI_In__DBP__MASK EQU 0x01\r
+SCSI_In__DBP__PC EQU CYREG_PRT2_PC0\r
+SCSI_In__DBP__PORT EQU 2\r
+SCSI_In__DBP__PRT EQU CYREG_PRT2_PRT\r
+SCSI_In__DBP__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
+SCSI_In__DBP__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
+SCSI_In__DBP__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
+SCSI_In__DBP__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
+SCSI_In__DBP__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
+SCSI_In__DBP__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
+SCSI_In__DBP__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
+SCSI_In__DBP__PS EQU CYREG_PRT2_PS\r
+SCSI_In__DBP__SHIFT EQU 0\r
+SCSI_In__DBP__SLW EQU CYREG_PRT2_SLW\r
+SCSI_In__IO__AG EQU CYREG_PRT5_AG\r
+SCSI_In__IO__AMUX EQU CYREG_PRT5_AMUX\r
+SCSI_In__IO__BIE EQU CYREG_PRT5_BIE\r
+SCSI_In__IO__BIT_MASK EQU CYREG_PRT5_BIT_MASK\r
+SCSI_In__IO__BYP EQU CYREG_PRT5_BYP\r
+SCSI_In__IO__CTL EQU CYREG_PRT5_CTL\r
+SCSI_In__IO__DM0 EQU CYREG_PRT5_DM0\r
+SCSI_In__IO__DM1 EQU CYREG_PRT5_DM1\r
+SCSI_In__IO__DM2 EQU CYREG_PRT5_DM2\r
+SCSI_In__IO__DR EQU CYREG_PRT5_DR\r
+SCSI_In__IO__INP_DIS EQU CYREG_PRT5_INP_DIS\r
+SCSI_In__IO__INTTYPE EQU CYREG_PICU5_INTTYPE3\r
+SCSI_In__IO__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG\r
+SCSI_In__IO__LCD_EN EQU CYREG_PRT5_LCD_EN\r
+SCSI_In__IO__MASK EQU 0x08\r
+SCSI_In__IO__PC EQU CYREG_PRT5_PC3\r
+SCSI_In__IO__PORT EQU 5\r
+SCSI_In__IO__PRT EQU CYREG_PRT5_PRT\r
+SCSI_In__IO__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL\r
+SCSI_In__IO__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN\r
+SCSI_In__IO__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0\r
+SCSI_In__IO__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1\r
+SCSI_In__IO__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0\r
+SCSI_In__IO__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1\r
+SCSI_In__IO__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT\r
+SCSI_In__IO__PS EQU CYREG_PRT5_PS\r
+SCSI_In__IO__SHIFT EQU 3\r
+SCSI_In__IO__SLW EQU CYREG_PRT5_SLW\r
+SCSI_In__MSG__AG EQU CYREG_PRT6_AG\r
+SCSI_In__MSG__AMUX EQU CYREG_PRT6_AMUX\r
+SCSI_In__MSG__BIE EQU CYREG_PRT6_BIE\r
+SCSI_In__MSG__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
+SCSI_In__MSG__BYP EQU CYREG_PRT6_BYP\r
+SCSI_In__MSG__CTL EQU CYREG_PRT6_CTL\r
+SCSI_In__MSG__DM0 EQU CYREG_PRT6_DM0\r
+SCSI_In__MSG__DM1 EQU CYREG_PRT6_DM1\r
+SCSI_In__MSG__DM2 EQU CYREG_PRT6_DM2\r
+SCSI_In__MSG__DR EQU CYREG_PRT6_DR\r
+SCSI_In__MSG__INP_DIS EQU CYREG_PRT6_INP_DIS\r
+SCSI_In__MSG__INTTYPE EQU CYREG_PICU6_INTTYPE7\r
+SCSI_In__MSG__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
+SCSI_In__MSG__LCD_EN EQU CYREG_PRT6_LCD_EN\r
+SCSI_In__MSG__MASK EQU 0x80\r
+SCSI_In__MSG__PC EQU CYREG_PRT6_PC7\r
+SCSI_In__MSG__PORT EQU 6\r
+SCSI_In__MSG__PRT EQU CYREG_PRT6_PRT\r
+SCSI_In__MSG__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
+SCSI_In__MSG__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
+SCSI_In__MSG__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
+SCSI_In__MSG__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
+SCSI_In__MSG__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
+SCSI_In__MSG__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
+SCSI_In__MSG__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
+SCSI_In__MSG__PS EQU CYREG_PRT6_PS\r
+SCSI_In__MSG__SHIFT EQU 7\r
+SCSI_In__MSG__SLW EQU CYREG_PRT6_SLW\r
+SCSI_In__REQ__AG EQU CYREG_PRT5_AG\r
+SCSI_In__REQ__AMUX EQU CYREG_PRT5_AMUX\r
+SCSI_In__REQ__BIE EQU CYREG_PRT5_BIE\r
+SCSI_In__REQ__BIT_MASK EQU CYREG_PRT5_BIT_MASK\r
+SCSI_In__REQ__BYP EQU CYREG_PRT5_BYP\r
+SCSI_In__REQ__CTL EQU CYREG_PRT5_CTL\r
+SCSI_In__REQ__DM0 EQU CYREG_PRT5_DM0\r
+SCSI_In__REQ__DM1 EQU CYREG_PRT5_DM1\r
+SCSI_In__REQ__DM2 EQU CYREG_PRT5_DM2\r
+SCSI_In__REQ__DR EQU CYREG_PRT5_DR\r
+SCSI_In__REQ__INP_DIS EQU CYREG_PRT5_INP_DIS\r
+SCSI_In__REQ__INTTYPE EQU CYREG_PICU5_INTTYPE2\r
+SCSI_In__REQ__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG\r
+SCSI_In__REQ__LCD_EN EQU CYREG_PRT5_LCD_EN\r
+SCSI_In__REQ__MASK EQU 0x04\r
+SCSI_In__REQ__PC EQU CYREG_PRT5_PC2\r
+SCSI_In__REQ__PORT EQU 5\r
+SCSI_In__REQ__PRT EQU CYREG_PRT5_PRT\r
+SCSI_In__REQ__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL\r
+SCSI_In__REQ__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN\r
+SCSI_In__REQ__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0\r
+SCSI_In__REQ__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1\r
+SCSI_In__REQ__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0\r
+SCSI_In__REQ__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1\r
+SCSI_In__REQ__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT\r
+SCSI_In__REQ__PS EQU CYREG_PRT5_PS\r
+SCSI_In__REQ__SHIFT EQU 2\r
+SCSI_In__REQ__SLW EQU CYREG_PRT5_SLW\r
+SCSI_In_DBx__0__AG EQU CYREG_PRT12_AG\r
+SCSI_In_DBx__0__BIE EQU CYREG_PRT12_BIE\r
+SCSI_In_DBx__0__BIT_MASK EQU CYREG_PRT12_BIT_MASK\r
+SCSI_In_DBx__0__BYP EQU CYREG_PRT12_BYP\r
+SCSI_In_DBx__0__DM0 EQU CYREG_PRT12_DM0\r
+SCSI_In_DBx__0__DM1 EQU CYREG_PRT12_DM1\r
+SCSI_In_DBx__0__DM2 EQU CYREG_PRT12_DM2\r
+SCSI_In_DBx__0__DR EQU CYREG_PRT12_DR\r
+SCSI_In_DBx__0__INP_DIS EQU CYREG_PRT12_INP_DIS\r
+SCSI_In_DBx__0__INTTYPE EQU CYREG_PICU12_INTTYPE4\r
+SCSI_In_DBx__0__MASK EQU 0x10\r
+SCSI_In_DBx__0__PC EQU CYREG_PRT12_PC4\r
+SCSI_In_DBx__0__PORT EQU 12\r
+SCSI_In_DBx__0__PRT EQU CYREG_PRT12_PRT\r
+SCSI_In_DBx__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN\r
+SCSI_In_DBx__0__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0\r
+SCSI_In_DBx__0__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1\r
+SCSI_In_DBx__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0\r
+SCSI_In_DBx__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1\r
+SCSI_In_DBx__0__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT\r
+SCSI_In_DBx__0__PS EQU CYREG_PRT12_PS\r
+SCSI_In_DBx__0__SHIFT EQU 4\r
+SCSI_In_DBx__0__SIO_CFG EQU CYREG_PRT12_SIO_CFG\r
+SCSI_In_DBx__0__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF\r
+SCSI_In_DBx__0__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN\r
+SCSI_In_DBx__0__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ\r
+SCSI_In_DBx__0__SLW EQU CYREG_PRT12_SLW\r
+SCSI_In_DBx__1__AG EQU CYREG_PRT2_AG\r
+SCSI_In_DBx__1__AMUX EQU CYREG_PRT2_AMUX\r
+SCSI_In_DBx__1__BIE EQU CYREG_PRT2_BIE\r
+SCSI_In_DBx__1__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
+SCSI_In_DBx__1__BYP EQU CYREG_PRT2_BYP\r
+SCSI_In_DBx__1__CTL EQU CYREG_PRT2_CTL\r
+SCSI_In_DBx__1__DM0 EQU CYREG_PRT2_DM0\r
+SCSI_In_DBx__1__DM1 EQU CYREG_PRT2_DM1\r
+SCSI_In_DBx__1__DM2 EQU CYREG_PRT2_DM2\r
+SCSI_In_DBx__1__DR EQU CYREG_PRT2_DR\r
+SCSI_In_DBx__1__INP_DIS EQU CYREG_PRT2_INP_DIS\r
+SCSI_In_DBx__1__INTTYPE EQU CYREG_PICU2_INTTYPE7\r
+SCSI_In_DBx__1__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
+SCSI_In_DBx__1__LCD_EN EQU CYREG_PRT2_LCD_EN\r
+SCSI_In_DBx__1__MASK EQU 0x80\r
+SCSI_In_DBx__1__PC EQU CYREG_PRT2_PC7\r
+SCSI_In_DBx__1__PORT EQU 2\r
+SCSI_In_DBx__1__PRT EQU CYREG_PRT2_PRT\r
+SCSI_In_DBx__1__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
+SCSI_In_DBx__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
+SCSI_In_DBx__1__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
+SCSI_In_DBx__1__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
+SCSI_In_DBx__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
+SCSI_In_DBx__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
+SCSI_In_DBx__1__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
+SCSI_In_DBx__1__PS EQU CYREG_PRT2_PS\r
+SCSI_In_DBx__1__SHIFT EQU 7\r
+SCSI_In_DBx__1__SLW EQU CYREG_PRT2_SLW\r
+SCSI_In_DBx__2__AG EQU CYREG_PRT2_AG\r
+SCSI_In_DBx__2__AMUX EQU CYREG_PRT2_AMUX\r
+SCSI_In_DBx__2__BIE EQU CYREG_PRT2_BIE\r
+SCSI_In_DBx__2__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
+SCSI_In_DBx__2__BYP EQU CYREG_PRT2_BYP\r
+SCSI_In_DBx__2__CTL EQU CYREG_PRT2_CTL\r
+SCSI_In_DBx__2__DM0 EQU CYREG_PRT2_DM0\r
+SCSI_In_DBx__2__DM1 EQU CYREG_PRT2_DM1\r
+SCSI_In_DBx__2__DM2 EQU CYREG_PRT2_DM2\r
+SCSI_In_DBx__2__DR EQU CYREG_PRT2_DR\r
+SCSI_In_DBx__2__INP_DIS EQU CYREG_PRT2_INP_DIS\r
+SCSI_In_DBx__2__INTTYPE EQU CYREG_PICU2_INTTYPE6\r
+SCSI_In_DBx__2__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
+SCSI_In_DBx__2__LCD_EN EQU CYREG_PRT2_LCD_EN\r
+SCSI_In_DBx__2__MASK EQU 0x40\r
+SCSI_In_DBx__2__PC EQU CYREG_PRT2_PC6\r
+SCSI_In_DBx__2__PORT EQU 2\r
+SCSI_In_DBx__2__PRT EQU CYREG_PRT2_PRT\r
+SCSI_In_DBx__2__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
+SCSI_In_DBx__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
+SCSI_In_DBx__2__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
+SCSI_In_DBx__2__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
+SCSI_In_DBx__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
+SCSI_In_DBx__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
+SCSI_In_DBx__2__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
+SCSI_In_DBx__2__PS EQU CYREG_PRT2_PS\r
+SCSI_In_DBx__2__SHIFT EQU 6\r
+SCSI_In_DBx__2__SLW EQU CYREG_PRT2_SLW\r
+SCSI_In_DBx__3__AG EQU CYREG_PRT2_AG\r
+SCSI_In_DBx__3__AMUX EQU CYREG_PRT2_AMUX\r
+SCSI_In_DBx__3__BIE EQU CYREG_PRT2_BIE\r
+SCSI_In_DBx__3__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
+SCSI_In_DBx__3__BYP EQU CYREG_PRT2_BYP\r
+SCSI_In_DBx__3__CTL EQU CYREG_PRT2_CTL\r
+SCSI_In_DBx__3__DM0 EQU CYREG_PRT2_DM0\r
+SCSI_In_DBx__3__DM1 EQU CYREG_PRT2_DM1\r
+SCSI_In_DBx__3__DM2 EQU CYREG_PRT2_DM2\r
+SCSI_In_DBx__3__DR EQU CYREG_PRT2_DR\r
+SCSI_In_DBx__3__INP_DIS EQU CYREG_PRT2_INP_DIS\r
+SCSI_In_DBx__3__INTTYPE EQU CYREG_PICU2_INTTYPE5\r
+SCSI_In_DBx__3__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
+SCSI_In_DBx__3__LCD_EN EQU CYREG_PRT2_LCD_EN\r
+SCSI_In_DBx__3__MASK EQU 0x20\r
+SCSI_In_DBx__3__PC EQU CYREG_PRT2_PC5\r
+SCSI_In_DBx__3__PORT EQU 2\r
+SCSI_In_DBx__3__PRT EQU CYREG_PRT2_PRT\r
+SCSI_In_DBx__3__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
+SCSI_In_DBx__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
+SCSI_In_DBx__3__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
+SCSI_In_DBx__3__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
+SCSI_In_DBx__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
+SCSI_In_DBx__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
+SCSI_In_DBx__3__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
+SCSI_In_DBx__3__PS EQU CYREG_PRT2_PS\r
+SCSI_In_DBx__3__SHIFT EQU 5\r
+SCSI_In_DBx__3__SLW EQU CYREG_PRT2_SLW\r
+SCSI_In_DBx__4__AG EQU CYREG_PRT2_AG\r
+SCSI_In_DBx__4__AMUX EQU CYREG_PRT2_AMUX\r
+SCSI_In_DBx__4__BIE EQU CYREG_PRT2_BIE\r
+SCSI_In_DBx__4__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
+SCSI_In_DBx__4__BYP EQU CYREG_PRT2_BYP\r
+SCSI_In_DBx__4__CTL EQU CYREG_PRT2_CTL\r
+SCSI_In_DBx__4__DM0 EQU CYREG_PRT2_DM0\r
+SCSI_In_DBx__4__DM1 EQU CYREG_PRT2_DM1\r
+SCSI_In_DBx__4__DM2 EQU CYREG_PRT2_DM2\r
+SCSI_In_DBx__4__DR EQU CYREG_PRT2_DR\r
+SCSI_In_DBx__4__INP_DIS EQU CYREG_PRT2_INP_DIS\r
+SCSI_In_DBx__4__INTTYPE EQU CYREG_PICU2_INTTYPE4\r
+SCSI_In_DBx__4__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
+SCSI_In_DBx__4__LCD_EN EQU CYREG_PRT2_LCD_EN\r
+SCSI_In_DBx__4__MASK EQU 0x10\r
+SCSI_In_DBx__4__PC EQU CYREG_PRT2_PC4\r
+SCSI_In_DBx__4__PORT EQU 2\r
+SCSI_In_DBx__4__PRT EQU CYREG_PRT2_PRT\r
+SCSI_In_DBx__4__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
+SCSI_In_DBx__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
+SCSI_In_DBx__4__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
+SCSI_In_DBx__4__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
+SCSI_In_DBx__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
+SCSI_In_DBx__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
+SCSI_In_DBx__4__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
+SCSI_In_DBx__4__PS EQU CYREG_PRT2_PS\r
+SCSI_In_DBx__4__SHIFT EQU 4\r
+SCSI_In_DBx__4__SLW EQU CYREG_PRT2_SLW\r
+SCSI_In_DBx__5__AG EQU CYREG_PRT2_AG\r
+SCSI_In_DBx__5__AMUX EQU CYREG_PRT2_AMUX\r
+SCSI_In_DBx__5__BIE EQU CYREG_PRT2_BIE\r
+SCSI_In_DBx__5__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
+SCSI_In_DBx__5__BYP EQU CYREG_PRT2_BYP\r
+SCSI_In_DBx__5__CTL EQU CYREG_PRT2_CTL\r
+SCSI_In_DBx__5__DM0 EQU CYREG_PRT2_DM0\r
+SCSI_In_DBx__5__DM1 EQU CYREG_PRT2_DM1\r
+SCSI_In_DBx__5__DM2 EQU CYREG_PRT2_DM2\r
+SCSI_In_DBx__5__DR EQU CYREG_PRT2_DR\r
+SCSI_In_DBx__5__INP_DIS EQU CYREG_PRT2_INP_DIS\r
+SCSI_In_DBx__5__INTTYPE EQU CYREG_PICU2_INTTYPE3\r
+SCSI_In_DBx__5__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
+SCSI_In_DBx__5__LCD_EN EQU CYREG_PRT2_LCD_EN\r
+SCSI_In_DBx__5__MASK EQU 0x08\r
+SCSI_In_DBx__5__PC EQU CYREG_PRT2_PC3\r
+SCSI_In_DBx__5__PORT EQU 2\r
+SCSI_In_DBx__5__PRT EQU CYREG_PRT2_PRT\r
+SCSI_In_DBx__5__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
+SCSI_In_DBx__5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
+SCSI_In_DBx__5__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
+SCSI_In_DBx__5__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
+SCSI_In_DBx__5__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
+SCSI_In_DBx__5__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
+SCSI_In_DBx__5__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
+SCSI_In_DBx__5__PS EQU CYREG_PRT2_PS\r
+SCSI_In_DBx__5__SHIFT EQU 3\r
+SCSI_In_DBx__5__SLW EQU CYREG_PRT2_SLW\r
+SCSI_In_DBx__6__AG EQU CYREG_PRT2_AG\r
+SCSI_In_DBx__6__AMUX EQU CYREG_PRT2_AMUX\r
+SCSI_In_DBx__6__BIE EQU CYREG_PRT2_BIE\r
+SCSI_In_DBx__6__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
+SCSI_In_DBx__6__BYP EQU CYREG_PRT2_BYP\r
+SCSI_In_DBx__6__CTL EQU CYREG_PRT2_CTL\r
+SCSI_In_DBx__6__DM0 EQU CYREG_PRT2_DM0\r
+SCSI_In_DBx__6__DM1 EQU CYREG_PRT2_DM1\r
+SCSI_In_DBx__6__DM2 EQU CYREG_PRT2_DM2\r
+SCSI_In_DBx__6__DR EQU CYREG_PRT2_DR\r
+SCSI_In_DBx__6__INP_DIS EQU CYREG_PRT2_INP_DIS\r
+SCSI_In_DBx__6__INTTYPE EQU CYREG_PICU2_INTTYPE2\r
+SCSI_In_DBx__6__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
+SCSI_In_DBx__6__LCD_EN EQU CYREG_PRT2_LCD_EN\r
+SCSI_In_DBx__6__MASK EQU 0x04\r
+SCSI_In_DBx__6__PC EQU CYREG_PRT2_PC2\r
+SCSI_In_DBx__6__PORT EQU 2\r
+SCSI_In_DBx__6__PRT EQU CYREG_PRT2_PRT\r
+SCSI_In_DBx__6__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
+SCSI_In_DBx__6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
+SCSI_In_DBx__6__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
+SCSI_In_DBx__6__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
+SCSI_In_DBx__6__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
+SCSI_In_DBx__6__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
+SCSI_In_DBx__6__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
+SCSI_In_DBx__6__PS EQU CYREG_PRT2_PS\r
+SCSI_In_DBx__6__SHIFT EQU 2\r
+SCSI_In_DBx__6__SLW EQU CYREG_PRT2_SLW\r
+SCSI_In_DBx__7__AG EQU CYREG_PRT2_AG\r
+SCSI_In_DBx__7__AMUX EQU CYREG_PRT2_AMUX\r
+SCSI_In_DBx__7__BIE EQU CYREG_PRT2_BIE\r
+SCSI_In_DBx__7__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
+SCSI_In_DBx__7__BYP EQU CYREG_PRT2_BYP\r
+SCSI_In_DBx__7__CTL EQU CYREG_PRT2_CTL\r
+SCSI_In_DBx__7__DM0 EQU CYREG_PRT2_DM0\r
+SCSI_In_DBx__7__DM1 EQU CYREG_PRT2_DM1\r
+SCSI_In_DBx__7__DM2 EQU CYREG_PRT2_DM2\r
+SCSI_In_DBx__7__DR EQU CYREG_PRT2_DR\r
+SCSI_In_DBx__7__INP_DIS EQU CYREG_PRT2_INP_DIS\r
+SCSI_In_DBx__7__INTTYPE EQU CYREG_PICU2_INTTYPE1\r
+SCSI_In_DBx__7__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
+SCSI_In_DBx__7__LCD_EN EQU CYREG_PRT2_LCD_EN\r
+SCSI_In_DBx__7__MASK EQU 0x02\r
+SCSI_In_DBx__7__PC EQU CYREG_PRT2_PC1\r
+SCSI_In_DBx__7__PORT EQU 2\r
+SCSI_In_DBx__7__PRT EQU CYREG_PRT2_PRT\r
+SCSI_In_DBx__7__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
+SCSI_In_DBx__7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
+SCSI_In_DBx__7__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
+SCSI_In_DBx__7__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
+SCSI_In_DBx__7__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
+SCSI_In_DBx__7__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
+SCSI_In_DBx__7__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
+SCSI_In_DBx__7__PS EQU CYREG_PRT2_PS\r
+SCSI_In_DBx__7__SHIFT EQU 1\r
+SCSI_In_DBx__7__SLW EQU CYREG_PRT2_SLW\r
+SCSI_In_DBx__DB0__AG EQU CYREG_PRT12_AG\r
+SCSI_In_DBx__DB0__BIE EQU CYREG_PRT12_BIE\r
+SCSI_In_DBx__DB0__BIT_MASK EQU CYREG_PRT12_BIT_MASK\r
+SCSI_In_DBx__DB0__BYP EQU CYREG_PRT12_BYP\r
+SCSI_In_DBx__DB0__DM0 EQU CYREG_PRT12_DM0\r
+SCSI_In_DBx__DB0__DM1 EQU CYREG_PRT12_DM1\r
+SCSI_In_DBx__DB0__DM2 EQU CYREG_PRT12_DM2\r
+SCSI_In_DBx__DB0__DR EQU CYREG_PRT12_DR\r
+SCSI_In_DBx__DB0__INP_DIS EQU CYREG_PRT12_INP_DIS\r
+SCSI_In_DBx__DB0__INTTYPE EQU CYREG_PICU12_INTTYPE4\r
+SCSI_In_DBx__DB0__MASK EQU 0x10\r
+SCSI_In_DBx__DB0__PC EQU CYREG_PRT12_PC4\r
+SCSI_In_DBx__DB0__PORT EQU 12\r
+SCSI_In_DBx__DB0__PRT EQU CYREG_PRT12_PRT\r
+SCSI_In_DBx__DB0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN\r
+SCSI_In_DBx__DB0__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0\r
+SCSI_In_DBx__DB0__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1\r
+SCSI_In_DBx__DB0__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0\r
+SCSI_In_DBx__DB0__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1\r
+SCSI_In_DBx__DB0__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT\r
+SCSI_In_DBx__DB0__PS EQU CYREG_PRT12_PS\r
+SCSI_In_DBx__DB0__SHIFT EQU 4\r
+SCSI_In_DBx__DB0__SIO_CFG EQU CYREG_PRT12_SIO_CFG\r
+SCSI_In_DBx__DB0__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF\r
+SCSI_In_DBx__DB0__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN\r
+SCSI_In_DBx__DB0__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ\r
+SCSI_In_DBx__DB0__SLW EQU CYREG_PRT12_SLW\r
+SCSI_In_DBx__DB1__AG EQU CYREG_PRT2_AG\r
+SCSI_In_DBx__DB1__AMUX EQU CYREG_PRT2_AMUX\r
+SCSI_In_DBx__DB1__BIE EQU CYREG_PRT2_BIE\r
+SCSI_In_DBx__DB1__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
+SCSI_In_DBx__DB1__BYP EQU CYREG_PRT2_BYP\r
+SCSI_In_DBx__DB1__CTL EQU CYREG_PRT2_CTL\r
+SCSI_In_DBx__DB1__DM0 EQU CYREG_PRT2_DM0\r
+SCSI_In_DBx__DB1__DM1 EQU CYREG_PRT2_DM1\r
+SCSI_In_DBx__DB1__DM2 EQU CYREG_PRT2_DM2\r
+SCSI_In_DBx__DB1__DR EQU CYREG_PRT2_DR\r
+SCSI_In_DBx__DB1__INP_DIS EQU CYREG_PRT2_INP_DIS\r
+SCSI_In_DBx__DB1__INTTYPE EQU CYREG_PICU2_INTTYPE7\r
+SCSI_In_DBx__DB1__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
+SCSI_In_DBx__DB1__LCD_EN EQU CYREG_PRT2_LCD_EN\r
+SCSI_In_DBx__DB1__MASK EQU 0x80\r
+SCSI_In_DBx__DB1__PC EQU CYREG_PRT2_PC7\r
+SCSI_In_DBx__DB1__PORT EQU 2\r
+SCSI_In_DBx__DB1__PRT EQU CYREG_PRT2_PRT\r
+SCSI_In_DBx__DB1__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
+SCSI_In_DBx__DB1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
+SCSI_In_DBx__DB1__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
+SCSI_In_DBx__DB1__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
+SCSI_In_DBx__DB1__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
+SCSI_In_DBx__DB1__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
+SCSI_In_DBx__DB1__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
+SCSI_In_DBx__DB1__PS EQU CYREG_PRT2_PS\r
+SCSI_In_DBx__DB1__SHIFT EQU 7\r
+SCSI_In_DBx__DB1__SLW EQU CYREG_PRT2_SLW\r
+SCSI_In_DBx__DB2__AG EQU CYREG_PRT2_AG\r
+SCSI_In_DBx__DB2__AMUX EQU CYREG_PRT2_AMUX\r
+SCSI_In_DBx__DB2__BIE EQU CYREG_PRT2_BIE\r
+SCSI_In_DBx__DB2__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
+SCSI_In_DBx__DB2__BYP EQU CYREG_PRT2_BYP\r
+SCSI_In_DBx__DB2__CTL EQU CYREG_PRT2_CTL\r
+SCSI_In_DBx__DB2__DM0 EQU CYREG_PRT2_DM0\r
+SCSI_In_DBx__DB2__DM1 EQU CYREG_PRT2_DM1\r
+SCSI_In_DBx__DB2__DM2 EQU CYREG_PRT2_DM2\r
+SCSI_In_DBx__DB2__DR EQU CYREG_PRT2_DR\r
+SCSI_In_DBx__DB2__INP_DIS EQU CYREG_PRT2_INP_DIS\r
+SCSI_In_DBx__DB2__INTTYPE EQU CYREG_PICU2_INTTYPE6\r
+SCSI_In_DBx__DB2__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
+SCSI_In_DBx__DB2__LCD_EN EQU CYREG_PRT2_LCD_EN\r
+SCSI_In_DBx__DB2__MASK EQU 0x40\r
+SCSI_In_DBx__DB2__PC EQU CYREG_PRT2_PC6\r
+SCSI_In_DBx__DB2__PORT EQU 2\r
+SCSI_In_DBx__DB2__PRT EQU CYREG_PRT2_PRT\r
+SCSI_In_DBx__DB2__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
+SCSI_In_DBx__DB2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
+SCSI_In_DBx__DB2__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
+SCSI_In_DBx__DB2__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
+SCSI_In_DBx__DB2__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
+SCSI_In_DBx__DB2__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
+SCSI_In_DBx__DB2__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
+SCSI_In_DBx__DB2__PS EQU CYREG_PRT2_PS\r
+SCSI_In_DBx__DB2__SHIFT EQU 6\r
+SCSI_In_DBx__DB2__SLW EQU CYREG_PRT2_SLW\r
+SCSI_In_DBx__DB3__AG EQU CYREG_PRT2_AG\r
+SCSI_In_DBx__DB3__AMUX EQU CYREG_PRT2_AMUX\r
+SCSI_In_DBx__DB3__BIE EQU CYREG_PRT2_BIE\r
+SCSI_In_DBx__DB3__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
+SCSI_In_DBx__DB3__BYP EQU CYREG_PRT2_BYP\r
+SCSI_In_DBx__DB3__CTL EQU CYREG_PRT2_CTL\r
+SCSI_In_DBx__DB3__DM0 EQU CYREG_PRT2_DM0\r
+SCSI_In_DBx__DB3__DM1 EQU CYREG_PRT2_DM1\r
+SCSI_In_DBx__DB3__DM2 EQU CYREG_PRT2_DM2\r
+SCSI_In_DBx__DB3__DR EQU CYREG_PRT2_DR\r
+SCSI_In_DBx__DB3__INP_DIS EQU CYREG_PRT2_INP_DIS\r
+SCSI_In_DBx__DB3__INTTYPE EQU CYREG_PICU2_INTTYPE5\r
+SCSI_In_DBx__DB3__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
+SCSI_In_DBx__DB3__LCD_EN EQU CYREG_PRT2_LCD_EN\r
+SCSI_In_DBx__DB3__MASK EQU 0x20\r
+SCSI_In_DBx__DB3__PC EQU CYREG_PRT2_PC5\r
+SCSI_In_DBx__DB3__PORT EQU 2\r
+SCSI_In_DBx__DB3__PRT EQU CYREG_PRT2_PRT\r
+SCSI_In_DBx__DB3__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
+SCSI_In_DBx__DB3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
+SCSI_In_DBx__DB3__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
+SCSI_In_DBx__DB3__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
+SCSI_In_DBx__DB3__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
+SCSI_In_DBx__DB3__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
+SCSI_In_DBx__DB3__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
+SCSI_In_DBx__DB3__PS EQU CYREG_PRT2_PS\r
+SCSI_In_DBx__DB3__SHIFT EQU 5\r
+SCSI_In_DBx__DB3__SLW EQU CYREG_PRT2_SLW\r
+SCSI_In_DBx__DB4__AG EQU CYREG_PRT2_AG\r
+SCSI_In_DBx__DB4__AMUX EQU CYREG_PRT2_AMUX\r
+SCSI_In_DBx__DB4__BIE EQU CYREG_PRT2_BIE\r
+SCSI_In_DBx__DB4__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
+SCSI_In_DBx__DB4__BYP EQU CYREG_PRT2_BYP\r
+SCSI_In_DBx__DB4__CTL EQU CYREG_PRT2_CTL\r
+SCSI_In_DBx__DB4__DM0 EQU CYREG_PRT2_DM0\r
+SCSI_In_DBx__DB4__DM1 EQU CYREG_PRT2_DM1\r
+SCSI_In_DBx__DB4__DM2 EQU CYREG_PRT2_DM2\r
+SCSI_In_DBx__DB4__DR EQU CYREG_PRT2_DR\r
+SCSI_In_DBx__DB4__INP_DIS EQU CYREG_PRT2_INP_DIS\r
+SCSI_In_DBx__DB4__INTTYPE EQU CYREG_PICU2_INTTYPE4\r
+SCSI_In_DBx__DB4__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
+SCSI_In_DBx__DB4__LCD_EN EQU CYREG_PRT2_LCD_EN\r
+SCSI_In_DBx__DB4__MASK EQU 0x10\r
+SCSI_In_DBx__DB4__PC EQU CYREG_PRT2_PC4\r
+SCSI_In_DBx__DB4__PORT EQU 2\r
+SCSI_In_DBx__DB4__PRT EQU CYREG_PRT2_PRT\r
+SCSI_In_DBx__DB4__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
+SCSI_In_DBx__DB4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
+SCSI_In_DBx__DB4__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
+SCSI_In_DBx__DB4__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
+SCSI_In_DBx__DB4__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
+SCSI_In_DBx__DB4__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
+SCSI_In_DBx__DB4__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
+SCSI_In_DBx__DB4__PS EQU CYREG_PRT2_PS\r
+SCSI_In_DBx__DB4__SHIFT EQU 4\r
+SCSI_In_DBx__DB4__SLW EQU CYREG_PRT2_SLW\r
+SCSI_In_DBx__DB5__AG EQU CYREG_PRT2_AG\r
+SCSI_In_DBx__DB5__AMUX EQU CYREG_PRT2_AMUX\r
+SCSI_In_DBx__DB5__BIE EQU CYREG_PRT2_BIE\r
+SCSI_In_DBx__DB5__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
+SCSI_In_DBx__DB5__BYP EQU CYREG_PRT2_BYP\r
+SCSI_In_DBx__DB5__CTL EQU CYREG_PRT2_CTL\r
+SCSI_In_DBx__DB5__DM0 EQU CYREG_PRT2_DM0\r
+SCSI_In_DBx__DB5__DM1 EQU CYREG_PRT2_DM1\r
+SCSI_In_DBx__DB5__DM2 EQU CYREG_PRT2_DM2\r
+SCSI_In_DBx__DB5__DR EQU CYREG_PRT2_DR\r
+SCSI_In_DBx__DB5__INP_DIS EQU CYREG_PRT2_INP_DIS\r
+SCSI_In_DBx__DB5__INTTYPE EQU CYREG_PICU2_INTTYPE3\r
+SCSI_In_DBx__DB5__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
+SCSI_In_DBx__DB5__LCD_EN EQU CYREG_PRT2_LCD_EN\r
+SCSI_In_DBx__DB5__MASK EQU 0x08\r
+SCSI_In_DBx__DB5__PC EQU CYREG_PRT2_PC3\r
+SCSI_In_DBx__DB5__PORT EQU 2\r
+SCSI_In_DBx__DB5__PRT EQU CYREG_PRT2_PRT\r
+SCSI_In_DBx__DB5__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
+SCSI_In_DBx__DB5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
+SCSI_In_DBx__DB5__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
+SCSI_In_DBx__DB5__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
+SCSI_In_DBx__DB5__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
+SCSI_In_DBx__DB5__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
+SCSI_In_DBx__DB5__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
+SCSI_In_DBx__DB5__PS EQU CYREG_PRT2_PS\r
+SCSI_In_DBx__DB5__SHIFT EQU 3\r
+SCSI_In_DBx__DB5__SLW EQU CYREG_PRT2_SLW\r
+SCSI_In_DBx__DB6__AG EQU CYREG_PRT2_AG\r
+SCSI_In_DBx__DB6__AMUX EQU CYREG_PRT2_AMUX\r
+SCSI_In_DBx__DB6__BIE EQU CYREG_PRT2_BIE\r
+SCSI_In_DBx__DB6__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
+SCSI_In_DBx__DB6__BYP EQU CYREG_PRT2_BYP\r
+SCSI_In_DBx__DB6__CTL EQU CYREG_PRT2_CTL\r
+SCSI_In_DBx__DB6__DM0 EQU CYREG_PRT2_DM0\r
+SCSI_In_DBx__DB6__DM1 EQU CYREG_PRT2_DM1\r
+SCSI_In_DBx__DB6__DM2 EQU CYREG_PRT2_DM2\r
+SCSI_In_DBx__DB6__DR EQU CYREG_PRT2_DR\r
+SCSI_In_DBx__DB6__INP_DIS EQU CYREG_PRT2_INP_DIS\r
+SCSI_In_DBx__DB6__INTTYPE EQU CYREG_PICU2_INTTYPE2\r
+SCSI_In_DBx__DB6__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
+SCSI_In_DBx__DB6__LCD_EN EQU CYREG_PRT2_LCD_EN\r
+SCSI_In_DBx__DB6__MASK EQU 0x04\r
+SCSI_In_DBx__DB6__PC EQU CYREG_PRT2_PC2\r
+SCSI_In_DBx__DB6__PORT EQU 2\r
+SCSI_In_DBx__DB6__PRT EQU CYREG_PRT2_PRT\r
+SCSI_In_DBx__DB6__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
+SCSI_In_DBx__DB6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
+SCSI_In_DBx__DB6__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
+SCSI_In_DBx__DB6__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
+SCSI_In_DBx__DB6__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
+SCSI_In_DBx__DB6__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
+SCSI_In_DBx__DB6__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
+SCSI_In_DBx__DB6__PS EQU CYREG_PRT2_PS\r
+SCSI_In_DBx__DB6__SHIFT EQU 2\r
+SCSI_In_DBx__DB6__SLW EQU CYREG_PRT2_SLW\r
+SCSI_In_DBx__DB7__AG EQU CYREG_PRT2_AG\r
+SCSI_In_DBx__DB7__AMUX EQU CYREG_PRT2_AMUX\r
+SCSI_In_DBx__DB7__BIE EQU CYREG_PRT2_BIE\r
+SCSI_In_DBx__DB7__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
+SCSI_In_DBx__DB7__BYP EQU CYREG_PRT2_BYP\r
+SCSI_In_DBx__DB7__CTL EQU CYREG_PRT2_CTL\r
+SCSI_In_DBx__DB7__DM0 EQU CYREG_PRT2_DM0\r
+SCSI_In_DBx__DB7__DM1 EQU CYREG_PRT2_DM1\r
+SCSI_In_DBx__DB7__DM2 EQU CYREG_PRT2_DM2\r
+SCSI_In_DBx__DB7__DR EQU CYREG_PRT2_DR\r
+SCSI_In_DBx__DB7__INP_DIS EQU CYREG_PRT2_INP_DIS\r
+SCSI_In_DBx__DB7__INTTYPE EQU CYREG_PICU2_INTTYPE1\r
+SCSI_In_DBx__DB7__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
+SCSI_In_DBx__DB7__LCD_EN EQU CYREG_PRT2_LCD_EN\r
+SCSI_In_DBx__DB7__MASK EQU 0x02\r
+SCSI_In_DBx__DB7__PC EQU CYREG_PRT2_PC1\r
+SCSI_In_DBx__DB7__PORT EQU 2\r
+SCSI_In_DBx__DB7__PRT EQU CYREG_PRT2_PRT\r
+SCSI_In_DBx__DB7__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
+SCSI_In_DBx__DB7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
+SCSI_In_DBx__DB7__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
+SCSI_In_DBx__DB7__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
+SCSI_In_DBx__DB7__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
+SCSI_In_DBx__DB7__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
+SCSI_In_DBx__DB7__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
+SCSI_In_DBx__DB7__PS EQU CYREG_PRT2_PS\r
+SCSI_In_DBx__DB7__SHIFT EQU 1\r
+SCSI_In_DBx__DB7__SLW EQU CYREG_PRT2_SLW\r
 \r
 ; SCSI_Noise\r
 SCSI_Noise__0__AG EQU CYREG_PRT12_AG\r
@@ -2774,6 +1164,1772 @@ SCSI_Noise__SEL__PS EQU CYREG_PRT5_PS
 SCSI_Noise__SEL__SHIFT EQU 0\r
 SCSI_Noise__SEL__SLW EQU CYREG_PRT5_SLW\r
 \r
+; SCSI_Out\r
+SCSI_Out__0__AG EQU CYREG_PRT4_AG\r
+SCSI_Out__0__AMUX EQU CYREG_PRT4_AMUX\r
+SCSI_Out__0__BIE EQU CYREG_PRT4_BIE\r
+SCSI_Out__0__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
+SCSI_Out__0__BYP EQU CYREG_PRT4_BYP\r
+SCSI_Out__0__CTL EQU CYREG_PRT4_CTL\r
+SCSI_Out__0__DM0 EQU CYREG_PRT4_DM0\r
+SCSI_Out__0__DM1 EQU CYREG_PRT4_DM1\r
+SCSI_Out__0__DM2 EQU CYREG_PRT4_DM2\r
+SCSI_Out__0__DR EQU CYREG_PRT4_DR\r
+SCSI_Out__0__INP_DIS EQU CYREG_PRT4_INP_DIS\r
+SCSI_Out__0__INTTYPE EQU CYREG_PICU4_INTTYPE3\r
+SCSI_Out__0__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
+SCSI_Out__0__LCD_EN EQU CYREG_PRT4_LCD_EN\r
+SCSI_Out__0__MASK EQU 0x08\r
+SCSI_Out__0__PC EQU CYREG_PRT4_PC3\r
+SCSI_Out__0__PORT EQU 4\r
+SCSI_Out__0__PRT EQU CYREG_PRT4_PRT\r
+SCSI_Out__0__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
+SCSI_Out__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
+SCSI_Out__0__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
+SCSI_Out__0__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
+SCSI_Out__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
+SCSI_Out__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
+SCSI_Out__0__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
+SCSI_Out__0__PS EQU CYREG_PRT4_PS\r
+SCSI_Out__0__SHIFT EQU 3\r
+SCSI_Out__0__SLW EQU CYREG_PRT4_SLW\r
+SCSI_Out__1__AG EQU CYREG_PRT4_AG\r
+SCSI_Out__1__AMUX EQU CYREG_PRT4_AMUX\r
+SCSI_Out__1__BIE EQU CYREG_PRT4_BIE\r
+SCSI_Out__1__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
+SCSI_Out__1__BYP EQU CYREG_PRT4_BYP\r
+SCSI_Out__1__CTL EQU CYREG_PRT4_CTL\r
+SCSI_Out__1__DM0 EQU CYREG_PRT4_DM0\r
+SCSI_Out__1__DM1 EQU CYREG_PRT4_DM1\r
+SCSI_Out__1__DM2 EQU CYREG_PRT4_DM2\r
+SCSI_Out__1__DR EQU CYREG_PRT4_DR\r
+SCSI_Out__1__INP_DIS EQU CYREG_PRT4_INP_DIS\r
+SCSI_Out__1__INTTYPE EQU CYREG_PICU4_INTTYPE2\r
+SCSI_Out__1__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
+SCSI_Out__1__LCD_EN EQU CYREG_PRT4_LCD_EN\r
+SCSI_Out__1__MASK EQU 0x04\r
+SCSI_Out__1__PC EQU CYREG_PRT4_PC2\r
+SCSI_Out__1__PORT EQU 4\r
+SCSI_Out__1__PRT EQU CYREG_PRT4_PRT\r
+SCSI_Out__1__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
+SCSI_Out__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
+SCSI_Out__1__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
+SCSI_Out__1__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
+SCSI_Out__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
+SCSI_Out__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
+SCSI_Out__1__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
+SCSI_Out__1__PS EQU CYREG_PRT4_PS\r
+SCSI_Out__1__SHIFT EQU 2\r
+SCSI_Out__1__SLW EQU CYREG_PRT4_SLW\r
+SCSI_Out__2__AG EQU CYREG_PRT0_AG\r
+SCSI_Out__2__AMUX EQU CYREG_PRT0_AMUX\r
+SCSI_Out__2__BIE EQU CYREG_PRT0_BIE\r
+SCSI_Out__2__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
+SCSI_Out__2__BYP EQU CYREG_PRT0_BYP\r
+SCSI_Out__2__CTL EQU CYREG_PRT0_CTL\r
+SCSI_Out__2__DM0 EQU CYREG_PRT0_DM0\r
+SCSI_Out__2__DM1 EQU CYREG_PRT0_DM1\r
+SCSI_Out__2__DM2 EQU CYREG_PRT0_DM2\r
+SCSI_Out__2__DR EQU CYREG_PRT0_DR\r
+SCSI_Out__2__INP_DIS EQU CYREG_PRT0_INP_DIS\r
+SCSI_Out__2__INTTYPE EQU CYREG_PICU0_INTTYPE7\r
+SCSI_Out__2__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
+SCSI_Out__2__LCD_EN EQU CYREG_PRT0_LCD_EN\r
+SCSI_Out__2__MASK EQU 0x80\r
+SCSI_Out__2__PC EQU CYREG_PRT0_PC7\r
+SCSI_Out__2__PORT EQU 0\r
+SCSI_Out__2__PRT EQU CYREG_PRT0_PRT\r
+SCSI_Out__2__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
+SCSI_Out__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
+SCSI_Out__2__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
+SCSI_Out__2__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
+SCSI_Out__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
+SCSI_Out__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
+SCSI_Out__2__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
+SCSI_Out__2__PS EQU CYREG_PRT0_PS\r
+SCSI_Out__2__SHIFT EQU 7\r
+SCSI_Out__2__SLW EQU CYREG_PRT0_SLW\r
+SCSI_Out__3__AG EQU CYREG_PRT0_AG\r
+SCSI_Out__3__AMUX EQU CYREG_PRT0_AMUX\r
+SCSI_Out__3__BIE EQU CYREG_PRT0_BIE\r
+SCSI_Out__3__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
+SCSI_Out__3__BYP EQU CYREG_PRT0_BYP\r
+SCSI_Out__3__CTL EQU CYREG_PRT0_CTL\r
+SCSI_Out__3__DM0 EQU CYREG_PRT0_DM0\r
+SCSI_Out__3__DM1 EQU CYREG_PRT0_DM1\r
+SCSI_Out__3__DM2 EQU CYREG_PRT0_DM2\r
+SCSI_Out__3__DR EQU CYREG_PRT0_DR\r
+SCSI_Out__3__INP_DIS EQU CYREG_PRT0_INP_DIS\r
+SCSI_Out__3__INTTYPE EQU CYREG_PICU0_INTTYPE6\r
+SCSI_Out__3__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
+SCSI_Out__3__LCD_EN EQU CYREG_PRT0_LCD_EN\r
+SCSI_Out__3__MASK EQU 0x40\r
+SCSI_Out__3__PC EQU CYREG_PRT0_PC6\r
+SCSI_Out__3__PORT EQU 0\r
+SCSI_Out__3__PRT EQU CYREG_PRT0_PRT\r
+SCSI_Out__3__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
+SCSI_Out__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
+SCSI_Out__3__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
+SCSI_Out__3__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
+SCSI_Out__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
+SCSI_Out__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
+SCSI_Out__3__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
+SCSI_Out__3__PS EQU CYREG_PRT0_PS\r
+SCSI_Out__3__SHIFT EQU 6\r
+SCSI_Out__3__SLW EQU CYREG_PRT0_SLW\r
+SCSI_Out__4__AG EQU CYREG_PRT0_AG\r
+SCSI_Out__4__AMUX EQU CYREG_PRT0_AMUX\r
+SCSI_Out__4__BIE EQU CYREG_PRT0_BIE\r
+SCSI_Out__4__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
+SCSI_Out__4__BYP EQU CYREG_PRT0_BYP\r
+SCSI_Out__4__CTL EQU CYREG_PRT0_CTL\r
+SCSI_Out__4__DM0 EQU CYREG_PRT0_DM0\r
+SCSI_Out__4__DM1 EQU CYREG_PRT0_DM1\r
+SCSI_Out__4__DM2 EQU CYREG_PRT0_DM2\r
+SCSI_Out__4__DR EQU CYREG_PRT0_DR\r
+SCSI_Out__4__INP_DIS EQU CYREG_PRT0_INP_DIS\r
+SCSI_Out__4__INTTYPE EQU CYREG_PICU0_INTTYPE5\r
+SCSI_Out__4__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
+SCSI_Out__4__LCD_EN EQU CYREG_PRT0_LCD_EN\r
+SCSI_Out__4__MASK EQU 0x20\r
+SCSI_Out__4__PC EQU CYREG_PRT0_PC5\r
+SCSI_Out__4__PORT EQU 0\r
+SCSI_Out__4__PRT EQU CYREG_PRT0_PRT\r
+SCSI_Out__4__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
+SCSI_Out__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
+SCSI_Out__4__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
+SCSI_Out__4__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
+SCSI_Out__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
+SCSI_Out__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
+SCSI_Out__4__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
+SCSI_Out__4__PS EQU CYREG_PRT0_PS\r
+SCSI_Out__4__SHIFT EQU 5\r
+SCSI_Out__4__SLW EQU CYREG_PRT0_SLW\r
+SCSI_Out__5__AG EQU CYREG_PRT0_AG\r
+SCSI_Out__5__AMUX EQU CYREG_PRT0_AMUX\r
+SCSI_Out__5__BIE EQU CYREG_PRT0_BIE\r
+SCSI_Out__5__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
+SCSI_Out__5__BYP EQU CYREG_PRT0_BYP\r
+SCSI_Out__5__CTL EQU CYREG_PRT0_CTL\r
+SCSI_Out__5__DM0 EQU CYREG_PRT0_DM0\r
+SCSI_Out__5__DM1 EQU CYREG_PRT0_DM1\r
+SCSI_Out__5__DM2 EQU CYREG_PRT0_DM2\r
+SCSI_Out__5__DR EQU CYREG_PRT0_DR\r
+SCSI_Out__5__INP_DIS EQU CYREG_PRT0_INP_DIS\r
+SCSI_Out__5__INTTYPE EQU CYREG_PICU0_INTTYPE4\r
+SCSI_Out__5__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
+SCSI_Out__5__LCD_EN EQU CYREG_PRT0_LCD_EN\r
+SCSI_Out__5__MASK EQU 0x10\r
+SCSI_Out__5__PC EQU CYREG_PRT0_PC4\r
+SCSI_Out__5__PORT EQU 0\r
+SCSI_Out__5__PRT EQU CYREG_PRT0_PRT\r
+SCSI_Out__5__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
+SCSI_Out__5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
+SCSI_Out__5__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
+SCSI_Out__5__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
+SCSI_Out__5__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
+SCSI_Out__5__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
+SCSI_Out__5__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
+SCSI_Out__5__PS EQU CYREG_PRT0_PS\r
+SCSI_Out__5__SHIFT EQU 4\r
+SCSI_Out__5__SLW EQU CYREG_PRT0_SLW\r
+SCSI_Out__6__AG EQU CYREG_PRT0_AG\r
+SCSI_Out__6__AMUX EQU CYREG_PRT0_AMUX\r
+SCSI_Out__6__BIE EQU CYREG_PRT0_BIE\r
+SCSI_Out__6__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
+SCSI_Out__6__BYP EQU CYREG_PRT0_BYP\r
+SCSI_Out__6__CTL EQU CYREG_PRT0_CTL\r
+SCSI_Out__6__DM0 EQU CYREG_PRT0_DM0\r
+SCSI_Out__6__DM1 EQU CYREG_PRT0_DM1\r
+SCSI_Out__6__DM2 EQU CYREG_PRT0_DM2\r
+SCSI_Out__6__DR EQU CYREG_PRT0_DR\r
+SCSI_Out__6__INP_DIS EQU CYREG_PRT0_INP_DIS\r
+SCSI_Out__6__INTTYPE EQU CYREG_PICU0_INTTYPE3\r
+SCSI_Out__6__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
+SCSI_Out__6__LCD_EN EQU CYREG_PRT0_LCD_EN\r
+SCSI_Out__6__MASK EQU 0x08\r
+SCSI_Out__6__PC EQU CYREG_PRT0_PC3\r
+SCSI_Out__6__PORT EQU 0\r
+SCSI_Out__6__PRT EQU CYREG_PRT0_PRT\r
+SCSI_Out__6__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
+SCSI_Out__6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
+SCSI_Out__6__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
+SCSI_Out__6__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
+SCSI_Out__6__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
+SCSI_Out__6__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
+SCSI_Out__6__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
+SCSI_Out__6__PS EQU CYREG_PRT0_PS\r
+SCSI_Out__6__SHIFT EQU 3\r
+SCSI_Out__6__SLW EQU CYREG_PRT0_SLW\r
+SCSI_Out__7__AG EQU CYREG_PRT0_AG\r
+SCSI_Out__7__AMUX EQU CYREG_PRT0_AMUX\r
+SCSI_Out__7__BIE EQU CYREG_PRT0_BIE\r
+SCSI_Out__7__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
+SCSI_Out__7__BYP EQU CYREG_PRT0_BYP\r
+SCSI_Out__7__CTL EQU CYREG_PRT0_CTL\r
+SCSI_Out__7__DM0 EQU CYREG_PRT0_DM0\r
+SCSI_Out__7__DM1 EQU CYREG_PRT0_DM1\r
+SCSI_Out__7__DM2 EQU CYREG_PRT0_DM2\r
+SCSI_Out__7__DR EQU CYREG_PRT0_DR\r
+SCSI_Out__7__INP_DIS EQU CYREG_PRT0_INP_DIS\r
+SCSI_Out__7__INTTYPE EQU CYREG_PICU0_INTTYPE2\r
+SCSI_Out__7__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
+SCSI_Out__7__LCD_EN EQU CYREG_PRT0_LCD_EN\r
+SCSI_Out__7__MASK EQU 0x04\r
+SCSI_Out__7__PC EQU CYREG_PRT0_PC2\r
+SCSI_Out__7__PORT EQU 0\r
+SCSI_Out__7__PRT EQU CYREG_PRT0_PRT\r
+SCSI_Out__7__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
+SCSI_Out__7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
+SCSI_Out__7__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
+SCSI_Out__7__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
+SCSI_Out__7__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
+SCSI_Out__7__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
+SCSI_Out__7__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
+SCSI_Out__7__PS EQU CYREG_PRT0_PS\r
+SCSI_Out__7__SHIFT EQU 2\r
+SCSI_Out__7__SLW EQU CYREG_PRT0_SLW\r
+SCSI_Out__8__AG EQU CYREG_PRT0_AG\r
+SCSI_Out__8__AMUX EQU CYREG_PRT0_AMUX\r
+SCSI_Out__8__BIE EQU CYREG_PRT0_BIE\r
+SCSI_Out__8__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
+SCSI_Out__8__BYP EQU CYREG_PRT0_BYP\r
+SCSI_Out__8__CTL EQU CYREG_PRT0_CTL\r
+SCSI_Out__8__DM0 EQU CYREG_PRT0_DM0\r
+SCSI_Out__8__DM1 EQU CYREG_PRT0_DM1\r
+SCSI_Out__8__DM2 EQU CYREG_PRT0_DM2\r
+SCSI_Out__8__DR EQU CYREG_PRT0_DR\r
+SCSI_Out__8__INP_DIS EQU CYREG_PRT0_INP_DIS\r
+SCSI_Out__8__INTTYPE EQU CYREG_PICU0_INTTYPE1\r
+SCSI_Out__8__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
+SCSI_Out__8__LCD_EN EQU CYREG_PRT0_LCD_EN\r
+SCSI_Out__8__MASK EQU 0x02\r
+SCSI_Out__8__PC EQU CYREG_PRT0_PC1\r
+SCSI_Out__8__PORT EQU 0\r
+SCSI_Out__8__PRT EQU CYREG_PRT0_PRT\r
+SCSI_Out__8__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
+SCSI_Out__8__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
+SCSI_Out__8__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
+SCSI_Out__8__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
+SCSI_Out__8__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
+SCSI_Out__8__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
+SCSI_Out__8__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
+SCSI_Out__8__PS EQU CYREG_PRT0_PS\r
+SCSI_Out__8__SHIFT EQU 1\r
+SCSI_Out__8__SLW EQU CYREG_PRT0_SLW\r
+SCSI_Out__9__AG EQU CYREG_PRT0_AG\r
+SCSI_Out__9__AMUX EQU CYREG_PRT0_AMUX\r
+SCSI_Out__9__BIE EQU CYREG_PRT0_BIE\r
+SCSI_Out__9__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
+SCSI_Out__9__BYP EQU CYREG_PRT0_BYP\r
+SCSI_Out__9__CTL EQU CYREG_PRT0_CTL\r
+SCSI_Out__9__DM0 EQU CYREG_PRT0_DM0\r
+SCSI_Out__9__DM1 EQU CYREG_PRT0_DM1\r
+SCSI_Out__9__DM2 EQU CYREG_PRT0_DM2\r
+SCSI_Out__9__DR EQU CYREG_PRT0_DR\r
+SCSI_Out__9__INP_DIS EQU CYREG_PRT0_INP_DIS\r
+SCSI_Out__9__INTTYPE EQU CYREG_PICU0_INTTYPE0\r
+SCSI_Out__9__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
+SCSI_Out__9__LCD_EN EQU CYREG_PRT0_LCD_EN\r
+SCSI_Out__9__MASK EQU 0x01\r
+SCSI_Out__9__PC EQU CYREG_PRT0_PC0\r
+SCSI_Out__9__PORT EQU 0\r
+SCSI_Out__9__PRT EQU CYREG_PRT0_PRT\r
+SCSI_Out__9__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
+SCSI_Out__9__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
+SCSI_Out__9__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
+SCSI_Out__9__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
+SCSI_Out__9__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
+SCSI_Out__9__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
+SCSI_Out__9__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
+SCSI_Out__9__PS EQU CYREG_PRT0_PS\r
+SCSI_Out__9__SHIFT EQU 0\r
+SCSI_Out__9__SLW EQU CYREG_PRT0_SLW\r
+SCSI_Out__ACK__AG EQU CYREG_PRT0_AG\r
+SCSI_Out__ACK__AMUX EQU CYREG_PRT0_AMUX\r
+SCSI_Out__ACK__BIE EQU CYREG_PRT0_BIE\r
+SCSI_Out__ACK__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
+SCSI_Out__ACK__BYP EQU CYREG_PRT0_BYP\r
+SCSI_Out__ACK__CTL EQU CYREG_PRT0_CTL\r
+SCSI_Out__ACK__DM0 EQU CYREG_PRT0_DM0\r
+SCSI_Out__ACK__DM1 EQU CYREG_PRT0_DM1\r
+SCSI_Out__ACK__DM2 EQU CYREG_PRT0_DM2\r
+SCSI_Out__ACK__DR EQU CYREG_PRT0_DR\r
+SCSI_Out__ACK__INP_DIS EQU CYREG_PRT0_INP_DIS\r
+SCSI_Out__ACK__INTTYPE EQU CYREG_PICU0_INTTYPE6\r
+SCSI_Out__ACK__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
+SCSI_Out__ACK__LCD_EN EQU CYREG_PRT0_LCD_EN\r
+SCSI_Out__ACK__MASK EQU 0x40\r
+SCSI_Out__ACK__PC EQU CYREG_PRT0_PC6\r
+SCSI_Out__ACK__PORT EQU 0\r
+SCSI_Out__ACK__PRT EQU CYREG_PRT0_PRT\r
+SCSI_Out__ACK__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
+SCSI_Out__ACK__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
+SCSI_Out__ACK__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
+SCSI_Out__ACK__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
+SCSI_Out__ACK__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
+SCSI_Out__ACK__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
+SCSI_Out__ACK__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
+SCSI_Out__ACK__PS EQU CYREG_PRT0_PS\r
+SCSI_Out__ACK__SHIFT EQU 6\r
+SCSI_Out__ACK__SLW EQU CYREG_PRT0_SLW\r
+SCSI_Out__ATN__AG EQU CYREG_PRT4_AG\r
+SCSI_Out__ATN__AMUX EQU CYREG_PRT4_AMUX\r
+SCSI_Out__ATN__BIE EQU CYREG_PRT4_BIE\r
+SCSI_Out__ATN__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
+SCSI_Out__ATN__BYP EQU CYREG_PRT4_BYP\r
+SCSI_Out__ATN__CTL EQU CYREG_PRT4_CTL\r
+SCSI_Out__ATN__DM0 EQU CYREG_PRT4_DM0\r
+SCSI_Out__ATN__DM1 EQU CYREG_PRT4_DM1\r
+SCSI_Out__ATN__DM2 EQU CYREG_PRT4_DM2\r
+SCSI_Out__ATN__DR EQU CYREG_PRT4_DR\r
+SCSI_Out__ATN__INP_DIS EQU CYREG_PRT4_INP_DIS\r
+SCSI_Out__ATN__INTTYPE EQU CYREG_PICU4_INTTYPE2\r
+SCSI_Out__ATN__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
+SCSI_Out__ATN__LCD_EN EQU CYREG_PRT4_LCD_EN\r
+SCSI_Out__ATN__MASK EQU 0x04\r
+SCSI_Out__ATN__PC EQU CYREG_PRT4_PC2\r
+SCSI_Out__ATN__PORT EQU 4\r
+SCSI_Out__ATN__PRT EQU CYREG_PRT4_PRT\r
+SCSI_Out__ATN__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
+SCSI_Out__ATN__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
+SCSI_Out__ATN__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
+SCSI_Out__ATN__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
+SCSI_Out__ATN__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
+SCSI_Out__ATN__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
+SCSI_Out__ATN__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
+SCSI_Out__ATN__PS EQU CYREG_PRT4_PS\r
+SCSI_Out__ATN__SHIFT EQU 2\r
+SCSI_Out__ATN__SLW EQU CYREG_PRT4_SLW\r
+SCSI_Out__BSY__AG EQU CYREG_PRT0_AG\r
+SCSI_Out__BSY__AMUX EQU CYREG_PRT0_AMUX\r
+SCSI_Out__BSY__BIE EQU CYREG_PRT0_BIE\r
+SCSI_Out__BSY__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
+SCSI_Out__BSY__BYP EQU CYREG_PRT0_BYP\r
+SCSI_Out__BSY__CTL EQU CYREG_PRT0_CTL\r
+SCSI_Out__BSY__DM0 EQU CYREG_PRT0_DM0\r
+SCSI_Out__BSY__DM1 EQU CYREG_PRT0_DM1\r
+SCSI_Out__BSY__DM2 EQU CYREG_PRT0_DM2\r
+SCSI_Out__BSY__DR EQU CYREG_PRT0_DR\r
+SCSI_Out__BSY__INP_DIS EQU CYREG_PRT0_INP_DIS\r
+SCSI_Out__BSY__INTTYPE EQU CYREG_PICU0_INTTYPE7\r
+SCSI_Out__BSY__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
+SCSI_Out__BSY__LCD_EN EQU CYREG_PRT0_LCD_EN\r
+SCSI_Out__BSY__MASK EQU 0x80\r
+SCSI_Out__BSY__PC EQU CYREG_PRT0_PC7\r
+SCSI_Out__BSY__PORT EQU 0\r
+SCSI_Out__BSY__PRT EQU CYREG_PRT0_PRT\r
+SCSI_Out__BSY__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
+SCSI_Out__BSY__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
+SCSI_Out__BSY__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
+SCSI_Out__BSY__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
+SCSI_Out__BSY__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
+SCSI_Out__BSY__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
+SCSI_Out__BSY__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
+SCSI_Out__BSY__PS EQU CYREG_PRT0_PS\r
+SCSI_Out__BSY__SHIFT EQU 7\r
+SCSI_Out__BSY__SLW EQU CYREG_PRT0_SLW\r
+SCSI_Out__CD_raw__AG EQU CYREG_PRT0_AG\r
+SCSI_Out__CD_raw__AMUX EQU CYREG_PRT0_AMUX\r
+SCSI_Out__CD_raw__BIE EQU CYREG_PRT0_BIE\r
+SCSI_Out__CD_raw__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
+SCSI_Out__CD_raw__BYP EQU CYREG_PRT0_BYP\r
+SCSI_Out__CD_raw__CTL EQU CYREG_PRT0_CTL\r
+SCSI_Out__CD_raw__DM0 EQU CYREG_PRT0_DM0\r
+SCSI_Out__CD_raw__DM1 EQU CYREG_PRT0_DM1\r
+SCSI_Out__CD_raw__DM2 EQU CYREG_PRT0_DM2\r
+SCSI_Out__CD_raw__DR EQU CYREG_PRT0_DR\r
+SCSI_Out__CD_raw__INP_DIS EQU CYREG_PRT0_INP_DIS\r
+SCSI_Out__CD_raw__INTTYPE EQU CYREG_PICU0_INTTYPE2\r
+SCSI_Out__CD_raw__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
+SCSI_Out__CD_raw__LCD_EN EQU CYREG_PRT0_LCD_EN\r
+SCSI_Out__CD_raw__MASK EQU 0x04\r
+SCSI_Out__CD_raw__PC EQU CYREG_PRT0_PC2\r
+SCSI_Out__CD_raw__PORT EQU 0\r
+SCSI_Out__CD_raw__PRT EQU CYREG_PRT0_PRT\r
+SCSI_Out__CD_raw__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
+SCSI_Out__CD_raw__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
+SCSI_Out__CD_raw__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
+SCSI_Out__CD_raw__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
+SCSI_Out__CD_raw__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
+SCSI_Out__CD_raw__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
+SCSI_Out__CD_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
+SCSI_Out__CD_raw__PS EQU CYREG_PRT0_PS\r
+SCSI_Out__CD_raw__SHIFT EQU 2\r
+SCSI_Out__CD_raw__SLW EQU CYREG_PRT0_SLW\r
+SCSI_Out__DBP_raw__AG EQU CYREG_PRT4_AG\r
+SCSI_Out__DBP_raw__AMUX EQU CYREG_PRT4_AMUX\r
+SCSI_Out__DBP_raw__BIE EQU CYREG_PRT4_BIE\r
+SCSI_Out__DBP_raw__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
+SCSI_Out__DBP_raw__BYP EQU CYREG_PRT4_BYP\r
+SCSI_Out__DBP_raw__CTL EQU CYREG_PRT4_CTL\r
+SCSI_Out__DBP_raw__DM0 EQU CYREG_PRT4_DM0\r
+SCSI_Out__DBP_raw__DM1 EQU CYREG_PRT4_DM1\r
+SCSI_Out__DBP_raw__DM2 EQU CYREG_PRT4_DM2\r
+SCSI_Out__DBP_raw__DR EQU CYREG_PRT4_DR\r
+SCSI_Out__DBP_raw__INP_DIS EQU CYREG_PRT4_INP_DIS\r
+SCSI_Out__DBP_raw__INTTYPE EQU CYREG_PICU4_INTTYPE3\r
+SCSI_Out__DBP_raw__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
+SCSI_Out__DBP_raw__LCD_EN EQU CYREG_PRT4_LCD_EN\r
+SCSI_Out__DBP_raw__MASK EQU 0x08\r
+SCSI_Out__DBP_raw__PC EQU CYREG_PRT4_PC3\r
+SCSI_Out__DBP_raw__PORT EQU 4\r
+SCSI_Out__DBP_raw__PRT EQU CYREG_PRT4_PRT\r
+SCSI_Out__DBP_raw__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
+SCSI_Out__DBP_raw__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
+SCSI_Out__DBP_raw__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
+SCSI_Out__DBP_raw__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
+SCSI_Out__DBP_raw__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
+SCSI_Out__DBP_raw__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
+SCSI_Out__DBP_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
+SCSI_Out__DBP_raw__PS EQU CYREG_PRT4_PS\r
+SCSI_Out__DBP_raw__SHIFT EQU 3\r
+SCSI_Out__DBP_raw__SLW EQU CYREG_PRT4_SLW\r
+SCSI_Out__IO_raw__AG EQU CYREG_PRT0_AG\r
+SCSI_Out__IO_raw__AMUX EQU CYREG_PRT0_AMUX\r
+SCSI_Out__IO_raw__BIE EQU CYREG_PRT0_BIE\r
+SCSI_Out__IO_raw__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
+SCSI_Out__IO_raw__BYP EQU CYREG_PRT0_BYP\r
+SCSI_Out__IO_raw__CTL EQU CYREG_PRT0_CTL\r
+SCSI_Out__IO_raw__DM0 EQU CYREG_PRT0_DM0\r
+SCSI_Out__IO_raw__DM1 EQU CYREG_PRT0_DM1\r
+SCSI_Out__IO_raw__DM2 EQU CYREG_PRT0_DM2\r
+SCSI_Out__IO_raw__DR EQU CYREG_PRT0_DR\r
+SCSI_Out__IO_raw__INP_DIS EQU CYREG_PRT0_INP_DIS\r
+SCSI_Out__IO_raw__INTTYPE EQU CYREG_PICU0_INTTYPE0\r
+SCSI_Out__IO_raw__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
+SCSI_Out__IO_raw__LCD_EN EQU CYREG_PRT0_LCD_EN\r
+SCSI_Out__IO_raw__MASK EQU 0x01\r
+SCSI_Out__IO_raw__PC EQU CYREG_PRT0_PC0\r
+SCSI_Out__IO_raw__PORT EQU 0\r
+SCSI_Out__IO_raw__PRT EQU CYREG_PRT0_PRT\r
+SCSI_Out__IO_raw__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
+SCSI_Out__IO_raw__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
+SCSI_Out__IO_raw__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
+SCSI_Out__IO_raw__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
+SCSI_Out__IO_raw__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
+SCSI_Out__IO_raw__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
+SCSI_Out__IO_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
+SCSI_Out__IO_raw__PS EQU CYREG_PRT0_PS\r
+SCSI_Out__IO_raw__SHIFT EQU 0\r
+SCSI_Out__IO_raw__SLW EQU CYREG_PRT0_SLW\r
+SCSI_Out__MSG_raw__AG EQU CYREG_PRT0_AG\r
+SCSI_Out__MSG_raw__AMUX EQU CYREG_PRT0_AMUX\r
+SCSI_Out__MSG_raw__BIE EQU CYREG_PRT0_BIE\r
+SCSI_Out__MSG_raw__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
+SCSI_Out__MSG_raw__BYP EQU CYREG_PRT0_BYP\r
+SCSI_Out__MSG_raw__CTL EQU CYREG_PRT0_CTL\r
+SCSI_Out__MSG_raw__DM0 EQU CYREG_PRT0_DM0\r
+SCSI_Out__MSG_raw__DM1 EQU CYREG_PRT0_DM1\r
+SCSI_Out__MSG_raw__DM2 EQU CYREG_PRT0_DM2\r
+SCSI_Out__MSG_raw__DR EQU CYREG_PRT0_DR\r
+SCSI_Out__MSG_raw__INP_DIS EQU CYREG_PRT0_INP_DIS\r
+SCSI_Out__MSG_raw__INTTYPE EQU CYREG_PICU0_INTTYPE4\r
+SCSI_Out__MSG_raw__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
+SCSI_Out__MSG_raw__LCD_EN EQU CYREG_PRT0_LCD_EN\r
+SCSI_Out__MSG_raw__MASK EQU 0x10\r
+SCSI_Out__MSG_raw__PC EQU CYREG_PRT0_PC4\r
+SCSI_Out__MSG_raw__PORT EQU 0\r
+SCSI_Out__MSG_raw__PRT EQU CYREG_PRT0_PRT\r
+SCSI_Out__MSG_raw__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
+SCSI_Out__MSG_raw__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
+SCSI_Out__MSG_raw__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
+SCSI_Out__MSG_raw__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
+SCSI_Out__MSG_raw__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
+SCSI_Out__MSG_raw__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
+SCSI_Out__MSG_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
+SCSI_Out__MSG_raw__PS EQU CYREG_PRT0_PS\r
+SCSI_Out__MSG_raw__SHIFT EQU 4\r
+SCSI_Out__MSG_raw__SLW EQU CYREG_PRT0_SLW\r
+SCSI_Out__REQ__AG EQU CYREG_PRT0_AG\r
+SCSI_Out__REQ__AMUX EQU CYREG_PRT0_AMUX\r
+SCSI_Out__REQ__BIE EQU CYREG_PRT0_BIE\r
+SCSI_Out__REQ__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
+SCSI_Out__REQ__BYP EQU CYREG_PRT0_BYP\r
+SCSI_Out__REQ__CTL EQU CYREG_PRT0_CTL\r
+SCSI_Out__REQ__DM0 EQU CYREG_PRT0_DM0\r
+SCSI_Out__REQ__DM1 EQU CYREG_PRT0_DM1\r
+SCSI_Out__REQ__DM2 EQU CYREG_PRT0_DM2\r
+SCSI_Out__REQ__DR EQU CYREG_PRT0_DR\r
+SCSI_Out__REQ__INP_DIS EQU CYREG_PRT0_INP_DIS\r
+SCSI_Out__REQ__INTTYPE EQU CYREG_PICU0_INTTYPE1\r
+SCSI_Out__REQ__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
+SCSI_Out__REQ__LCD_EN EQU CYREG_PRT0_LCD_EN\r
+SCSI_Out__REQ__MASK EQU 0x02\r
+SCSI_Out__REQ__PC EQU CYREG_PRT0_PC1\r
+SCSI_Out__REQ__PORT EQU 0\r
+SCSI_Out__REQ__PRT EQU CYREG_PRT0_PRT\r
+SCSI_Out__REQ__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
+SCSI_Out__REQ__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
+SCSI_Out__REQ__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
+SCSI_Out__REQ__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
+SCSI_Out__REQ__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
+SCSI_Out__REQ__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
+SCSI_Out__REQ__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
+SCSI_Out__REQ__PS EQU CYREG_PRT0_PS\r
+SCSI_Out__REQ__SHIFT EQU 1\r
+SCSI_Out__REQ__SLW EQU CYREG_PRT0_SLW\r
+SCSI_Out__RST__AG EQU CYREG_PRT0_AG\r
+SCSI_Out__RST__AMUX EQU CYREG_PRT0_AMUX\r
+SCSI_Out__RST__BIE EQU CYREG_PRT0_BIE\r
+SCSI_Out__RST__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
+SCSI_Out__RST__BYP EQU CYREG_PRT0_BYP\r
+SCSI_Out__RST__CTL EQU CYREG_PRT0_CTL\r
+SCSI_Out__RST__DM0 EQU CYREG_PRT0_DM0\r
+SCSI_Out__RST__DM1 EQU CYREG_PRT0_DM1\r
+SCSI_Out__RST__DM2 EQU CYREG_PRT0_DM2\r
+SCSI_Out__RST__DR EQU CYREG_PRT0_DR\r
+SCSI_Out__RST__INP_DIS EQU CYREG_PRT0_INP_DIS\r
+SCSI_Out__RST__INTTYPE EQU CYREG_PICU0_INTTYPE5\r
+SCSI_Out__RST__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
+SCSI_Out__RST__LCD_EN EQU CYREG_PRT0_LCD_EN\r
+SCSI_Out__RST__MASK EQU 0x20\r
+SCSI_Out__RST__PC EQU CYREG_PRT0_PC5\r
+SCSI_Out__RST__PORT EQU 0\r
+SCSI_Out__RST__PRT EQU CYREG_PRT0_PRT\r
+SCSI_Out__RST__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
+SCSI_Out__RST__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
+SCSI_Out__RST__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
+SCSI_Out__RST__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
+SCSI_Out__RST__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
+SCSI_Out__RST__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
+SCSI_Out__RST__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
+SCSI_Out__RST__PS EQU CYREG_PRT0_PS\r
+SCSI_Out__RST__SHIFT EQU 5\r
+SCSI_Out__RST__SLW EQU CYREG_PRT0_SLW\r
+SCSI_Out__SEL__AG EQU CYREG_PRT0_AG\r
+SCSI_Out__SEL__AMUX EQU CYREG_PRT0_AMUX\r
+SCSI_Out__SEL__BIE EQU CYREG_PRT0_BIE\r
+SCSI_Out__SEL__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
+SCSI_Out__SEL__BYP EQU CYREG_PRT0_BYP\r
+SCSI_Out__SEL__CTL EQU CYREG_PRT0_CTL\r
+SCSI_Out__SEL__DM0 EQU CYREG_PRT0_DM0\r
+SCSI_Out__SEL__DM1 EQU CYREG_PRT0_DM1\r
+SCSI_Out__SEL__DM2 EQU CYREG_PRT0_DM2\r
+SCSI_Out__SEL__DR EQU CYREG_PRT0_DR\r
+SCSI_Out__SEL__INP_DIS EQU CYREG_PRT0_INP_DIS\r
+SCSI_Out__SEL__INTTYPE EQU CYREG_PICU0_INTTYPE3\r
+SCSI_Out__SEL__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
+SCSI_Out__SEL__LCD_EN EQU CYREG_PRT0_LCD_EN\r
+SCSI_Out__SEL__MASK EQU 0x08\r
+SCSI_Out__SEL__PC EQU CYREG_PRT0_PC3\r
+SCSI_Out__SEL__PORT EQU 0\r
+SCSI_Out__SEL__PRT EQU CYREG_PRT0_PRT\r
+SCSI_Out__SEL__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
+SCSI_Out__SEL__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
+SCSI_Out__SEL__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
+SCSI_Out__SEL__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
+SCSI_Out__SEL__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
+SCSI_Out__SEL__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
+SCSI_Out__SEL__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
+SCSI_Out__SEL__PS EQU CYREG_PRT0_PS\r
+SCSI_Out__SEL__SHIFT EQU 3\r
+SCSI_Out__SEL__SLW EQU CYREG_PRT0_SLW\r
+SCSI_Out_Bits_Sync_ctrl_reg__0__MASK EQU 0x01\r
+SCSI_Out_Bits_Sync_ctrl_reg__0__POS EQU 0\r
+SCSI_Out_Bits_Sync_ctrl_reg__1__MASK EQU 0x02\r
+SCSI_Out_Bits_Sync_ctrl_reg__1__POS EQU 1\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB08_09_ACTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB08_09_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB08_09_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB08_09_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB08_09_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB08_09_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB08_09_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB08_09_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB08_09_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__2__MASK EQU 0x04\r
+SCSI_Out_Bits_Sync_ctrl_reg__2__POS EQU 2\r
+SCSI_Out_Bits_Sync_ctrl_reg__3__MASK EQU 0x08\r
+SCSI_Out_Bits_Sync_ctrl_reg__3__POS EQU 3\r
+SCSI_Out_Bits_Sync_ctrl_reg__4__MASK EQU 0x10\r
+SCSI_Out_Bits_Sync_ctrl_reg__4__POS EQU 4\r
+SCSI_Out_Bits_Sync_ctrl_reg__5__MASK EQU 0x20\r
+SCSI_Out_Bits_Sync_ctrl_reg__5__POS EQU 5\r
+SCSI_Out_Bits_Sync_ctrl_reg__6__MASK EQU 0x40\r
+SCSI_Out_Bits_Sync_ctrl_reg__6__POS EQU 6\r
+SCSI_Out_Bits_Sync_ctrl_reg__7__MASK EQU 0x80\r
+SCSI_Out_Bits_Sync_ctrl_reg__7__POS EQU 7\r
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB08_ACTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B1_UDB08_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B1_UDB08_ST_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B1_UDB08_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B1_UDB08_ST_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__MASK EQU 0xFF\r
+SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB08_MSK_ACTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB08_MSK_ACTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B1_UDB08_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01\r
+SCSI_Out_Ctl_Sync_ctrl_reg__0__POS EQU 0\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB08_09_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB08_09_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB08_09_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB08_09_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB08_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB08_ST_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB08_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB08_ST_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__MASK EQU 0x01\r
+SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB08_MSK\r
+SCSI_Out_DBx__0__AG EQU CYREG_PRT6_AG\r
+SCSI_Out_DBx__0__AMUX EQU CYREG_PRT6_AMUX\r
+SCSI_Out_DBx__0__BIE EQU CYREG_PRT6_BIE\r
+SCSI_Out_DBx__0__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
+SCSI_Out_DBx__0__BYP EQU CYREG_PRT6_BYP\r
+SCSI_Out_DBx__0__CTL EQU CYREG_PRT6_CTL\r
+SCSI_Out_DBx__0__DM0 EQU CYREG_PRT6_DM0\r
+SCSI_Out_DBx__0__DM1 EQU CYREG_PRT6_DM1\r
+SCSI_Out_DBx__0__DM2 EQU CYREG_PRT6_DM2\r
+SCSI_Out_DBx__0__DR EQU CYREG_PRT6_DR\r
+SCSI_Out_DBx__0__INP_DIS EQU CYREG_PRT6_INP_DIS\r
+SCSI_Out_DBx__0__INTTYPE EQU CYREG_PICU6_INTTYPE3\r
+SCSI_Out_DBx__0__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
+SCSI_Out_DBx__0__LCD_EN EQU CYREG_PRT6_LCD_EN\r
+SCSI_Out_DBx__0__MASK EQU 0x08\r
+SCSI_Out_DBx__0__PC EQU CYREG_PRT6_PC3\r
+SCSI_Out_DBx__0__PORT EQU 6\r
+SCSI_Out_DBx__0__PRT EQU CYREG_PRT6_PRT\r
+SCSI_Out_DBx__0__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
+SCSI_Out_DBx__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
+SCSI_Out_DBx__0__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
+SCSI_Out_DBx__0__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
+SCSI_Out_DBx__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
+SCSI_Out_DBx__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
+SCSI_Out_DBx__0__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
+SCSI_Out_DBx__0__PS EQU CYREG_PRT6_PS\r
+SCSI_Out_DBx__0__SHIFT EQU 3\r
+SCSI_Out_DBx__0__SLW EQU CYREG_PRT6_SLW\r
+SCSI_Out_DBx__1__AG EQU CYREG_PRT6_AG\r
+SCSI_Out_DBx__1__AMUX EQU CYREG_PRT6_AMUX\r
+SCSI_Out_DBx__1__BIE EQU CYREG_PRT6_BIE\r
+SCSI_Out_DBx__1__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
+SCSI_Out_DBx__1__BYP EQU CYREG_PRT6_BYP\r
+SCSI_Out_DBx__1__CTL EQU CYREG_PRT6_CTL\r
+SCSI_Out_DBx__1__DM0 EQU CYREG_PRT6_DM0\r
+SCSI_Out_DBx__1__DM1 EQU CYREG_PRT6_DM1\r
+SCSI_Out_DBx__1__DM2 EQU CYREG_PRT6_DM2\r
+SCSI_Out_DBx__1__DR EQU CYREG_PRT6_DR\r
+SCSI_Out_DBx__1__INP_DIS EQU CYREG_PRT6_INP_DIS\r
+SCSI_Out_DBx__1__INTTYPE EQU CYREG_PICU6_INTTYPE2\r
+SCSI_Out_DBx__1__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
+SCSI_Out_DBx__1__LCD_EN EQU CYREG_PRT6_LCD_EN\r
+SCSI_Out_DBx__1__MASK EQU 0x04\r
+SCSI_Out_DBx__1__PC EQU CYREG_PRT6_PC2\r
+SCSI_Out_DBx__1__PORT EQU 6\r
+SCSI_Out_DBx__1__PRT EQU CYREG_PRT6_PRT\r
+SCSI_Out_DBx__1__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
+SCSI_Out_DBx__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
+SCSI_Out_DBx__1__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
+SCSI_Out_DBx__1__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
+SCSI_Out_DBx__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
+SCSI_Out_DBx__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
+SCSI_Out_DBx__1__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
+SCSI_Out_DBx__1__PS EQU CYREG_PRT6_PS\r
+SCSI_Out_DBx__1__SHIFT EQU 2\r
+SCSI_Out_DBx__1__SLW EQU CYREG_PRT6_SLW\r
+SCSI_Out_DBx__2__AG EQU CYREG_PRT6_AG\r
+SCSI_Out_DBx__2__AMUX EQU CYREG_PRT6_AMUX\r
+SCSI_Out_DBx__2__BIE EQU CYREG_PRT6_BIE\r
+SCSI_Out_DBx__2__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
+SCSI_Out_DBx__2__BYP EQU CYREG_PRT6_BYP\r
+SCSI_Out_DBx__2__CTL EQU CYREG_PRT6_CTL\r
+SCSI_Out_DBx__2__DM0 EQU CYREG_PRT6_DM0\r
+SCSI_Out_DBx__2__DM1 EQU CYREG_PRT6_DM1\r
+SCSI_Out_DBx__2__DM2 EQU CYREG_PRT6_DM2\r
+SCSI_Out_DBx__2__DR EQU CYREG_PRT6_DR\r
+SCSI_Out_DBx__2__INP_DIS EQU CYREG_PRT6_INP_DIS\r
+SCSI_Out_DBx__2__INTTYPE EQU CYREG_PICU6_INTTYPE1\r
+SCSI_Out_DBx__2__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
+SCSI_Out_DBx__2__LCD_EN EQU CYREG_PRT6_LCD_EN\r
+SCSI_Out_DBx__2__MASK EQU 0x02\r
+SCSI_Out_DBx__2__PC EQU CYREG_PRT6_PC1\r
+SCSI_Out_DBx__2__PORT EQU 6\r
+SCSI_Out_DBx__2__PRT EQU CYREG_PRT6_PRT\r
+SCSI_Out_DBx__2__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
+SCSI_Out_DBx__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
+SCSI_Out_DBx__2__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
+SCSI_Out_DBx__2__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
+SCSI_Out_DBx__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
+SCSI_Out_DBx__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
+SCSI_Out_DBx__2__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
+SCSI_Out_DBx__2__PS EQU CYREG_PRT6_PS\r
+SCSI_Out_DBx__2__SHIFT EQU 1\r
+SCSI_Out_DBx__2__SLW EQU CYREG_PRT6_SLW\r
+SCSI_Out_DBx__3__AG EQU CYREG_PRT6_AG\r
+SCSI_Out_DBx__3__AMUX EQU CYREG_PRT6_AMUX\r
+SCSI_Out_DBx__3__BIE EQU CYREG_PRT6_BIE\r
+SCSI_Out_DBx__3__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
+SCSI_Out_DBx__3__BYP EQU CYREG_PRT6_BYP\r
+SCSI_Out_DBx__3__CTL EQU CYREG_PRT6_CTL\r
+SCSI_Out_DBx__3__DM0 EQU CYREG_PRT6_DM0\r
+SCSI_Out_DBx__3__DM1 EQU CYREG_PRT6_DM1\r
+SCSI_Out_DBx__3__DM2 EQU CYREG_PRT6_DM2\r
+SCSI_Out_DBx__3__DR EQU CYREG_PRT6_DR\r
+SCSI_Out_DBx__3__INP_DIS EQU CYREG_PRT6_INP_DIS\r
+SCSI_Out_DBx__3__INTTYPE EQU CYREG_PICU6_INTTYPE0\r
+SCSI_Out_DBx__3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
+SCSI_Out_DBx__3__LCD_EN EQU CYREG_PRT6_LCD_EN\r
+SCSI_Out_DBx__3__MASK EQU 0x01\r
+SCSI_Out_DBx__3__PC EQU CYREG_PRT6_PC0\r
+SCSI_Out_DBx__3__PORT EQU 6\r
+SCSI_Out_DBx__3__PRT EQU CYREG_PRT6_PRT\r
+SCSI_Out_DBx__3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
+SCSI_Out_DBx__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
+SCSI_Out_DBx__3__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
+SCSI_Out_DBx__3__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
+SCSI_Out_DBx__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
+SCSI_Out_DBx__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
+SCSI_Out_DBx__3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
+SCSI_Out_DBx__3__PS EQU CYREG_PRT6_PS\r
+SCSI_Out_DBx__3__SHIFT EQU 0\r
+SCSI_Out_DBx__3__SLW EQU CYREG_PRT6_SLW\r
+SCSI_Out_DBx__4__AG EQU CYREG_PRT4_AG\r
+SCSI_Out_DBx__4__AMUX EQU CYREG_PRT4_AMUX\r
+SCSI_Out_DBx__4__BIE EQU CYREG_PRT4_BIE\r
+SCSI_Out_DBx__4__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
+SCSI_Out_DBx__4__BYP EQU CYREG_PRT4_BYP\r
+SCSI_Out_DBx__4__CTL EQU CYREG_PRT4_CTL\r
+SCSI_Out_DBx__4__DM0 EQU CYREG_PRT4_DM0\r
+SCSI_Out_DBx__4__DM1 EQU CYREG_PRT4_DM1\r
+SCSI_Out_DBx__4__DM2 EQU CYREG_PRT4_DM2\r
+SCSI_Out_DBx__4__DR EQU CYREG_PRT4_DR\r
+SCSI_Out_DBx__4__INP_DIS EQU CYREG_PRT4_INP_DIS\r
+SCSI_Out_DBx__4__INTTYPE EQU CYREG_PICU4_INTTYPE7\r
+SCSI_Out_DBx__4__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
+SCSI_Out_DBx__4__LCD_EN EQU CYREG_PRT4_LCD_EN\r
+SCSI_Out_DBx__4__MASK EQU 0x80\r
+SCSI_Out_DBx__4__PC EQU CYREG_PRT4_PC7\r
+SCSI_Out_DBx__4__PORT EQU 4\r
+SCSI_Out_DBx__4__PRT EQU CYREG_PRT4_PRT\r
+SCSI_Out_DBx__4__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
+SCSI_Out_DBx__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
+SCSI_Out_DBx__4__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
+SCSI_Out_DBx__4__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
+SCSI_Out_DBx__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
+SCSI_Out_DBx__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
+SCSI_Out_DBx__4__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
+SCSI_Out_DBx__4__PS EQU CYREG_PRT4_PS\r
+SCSI_Out_DBx__4__SHIFT EQU 7\r
+SCSI_Out_DBx__4__SLW EQU CYREG_PRT4_SLW\r
+SCSI_Out_DBx__5__AG EQU CYREG_PRT4_AG\r
+SCSI_Out_DBx__5__AMUX EQU CYREG_PRT4_AMUX\r
+SCSI_Out_DBx__5__BIE EQU CYREG_PRT4_BIE\r
+SCSI_Out_DBx__5__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
+SCSI_Out_DBx__5__BYP EQU CYREG_PRT4_BYP\r
+SCSI_Out_DBx__5__CTL EQU CYREG_PRT4_CTL\r
+SCSI_Out_DBx__5__DM0 EQU CYREG_PRT4_DM0\r
+SCSI_Out_DBx__5__DM1 EQU CYREG_PRT4_DM1\r
+SCSI_Out_DBx__5__DM2 EQU CYREG_PRT4_DM2\r
+SCSI_Out_DBx__5__DR EQU CYREG_PRT4_DR\r
+SCSI_Out_DBx__5__INP_DIS EQU CYREG_PRT4_INP_DIS\r
+SCSI_Out_DBx__5__INTTYPE EQU CYREG_PICU4_INTTYPE6\r
+SCSI_Out_DBx__5__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
+SCSI_Out_DBx__5__LCD_EN EQU CYREG_PRT4_LCD_EN\r
+SCSI_Out_DBx__5__MASK EQU 0x40\r
+SCSI_Out_DBx__5__PC EQU CYREG_PRT4_PC6\r
+SCSI_Out_DBx__5__PORT EQU 4\r
+SCSI_Out_DBx__5__PRT EQU CYREG_PRT4_PRT\r
+SCSI_Out_DBx__5__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
+SCSI_Out_DBx__5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
+SCSI_Out_DBx__5__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
+SCSI_Out_DBx__5__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
+SCSI_Out_DBx__5__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
+SCSI_Out_DBx__5__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
+SCSI_Out_DBx__5__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
+SCSI_Out_DBx__5__PS EQU CYREG_PRT4_PS\r
+SCSI_Out_DBx__5__SHIFT EQU 6\r
+SCSI_Out_DBx__5__SLW EQU CYREG_PRT4_SLW\r
+SCSI_Out_DBx__6__AG EQU CYREG_PRT4_AG\r
+SCSI_Out_DBx__6__AMUX EQU CYREG_PRT4_AMUX\r
+SCSI_Out_DBx__6__BIE EQU CYREG_PRT4_BIE\r
+SCSI_Out_DBx__6__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
+SCSI_Out_DBx__6__BYP EQU CYREG_PRT4_BYP\r
+SCSI_Out_DBx__6__CTL EQU CYREG_PRT4_CTL\r
+SCSI_Out_DBx__6__DM0 EQU CYREG_PRT4_DM0\r
+SCSI_Out_DBx__6__DM1 EQU CYREG_PRT4_DM1\r
+SCSI_Out_DBx__6__DM2 EQU CYREG_PRT4_DM2\r
+SCSI_Out_DBx__6__DR EQU CYREG_PRT4_DR\r
+SCSI_Out_DBx__6__INP_DIS EQU CYREG_PRT4_INP_DIS\r
+SCSI_Out_DBx__6__INTTYPE EQU CYREG_PICU4_INTTYPE5\r
+SCSI_Out_DBx__6__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
+SCSI_Out_DBx__6__LCD_EN EQU CYREG_PRT4_LCD_EN\r
+SCSI_Out_DBx__6__MASK EQU 0x20\r
+SCSI_Out_DBx__6__PC EQU CYREG_PRT4_PC5\r
+SCSI_Out_DBx__6__PORT EQU 4\r
+SCSI_Out_DBx__6__PRT EQU CYREG_PRT4_PRT\r
+SCSI_Out_DBx__6__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
+SCSI_Out_DBx__6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
+SCSI_Out_DBx__6__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
+SCSI_Out_DBx__6__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
+SCSI_Out_DBx__6__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
+SCSI_Out_DBx__6__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
+SCSI_Out_DBx__6__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
+SCSI_Out_DBx__6__PS EQU CYREG_PRT4_PS\r
+SCSI_Out_DBx__6__SHIFT EQU 5\r
+SCSI_Out_DBx__6__SLW EQU CYREG_PRT4_SLW\r
+SCSI_Out_DBx__7__AG EQU CYREG_PRT4_AG\r
+SCSI_Out_DBx__7__AMUX EQU CYREG_PRT4_AMUX\r
+SCSI_Out_DBx__7__BIE EQU CYREG_PRT4_BIE\r
+SCSI_Out_DBx__7__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
+SCSI_Out_DBx__7__BYP EQU CYREG_PRT4_BYP\r
+SCSI_Out_DBx__7__CTL EQU CYREG_PRT4_CTL\r
+SCSI_Out_DBx__7__DM0 EQU CYREG_PRT4_DM0\r
+SCSI_Out_DBx__7__DM1 EQU CYREG_PRT4_DM1\r
+SCSI_Out_DBx__7__DM2 EQU CYREG_PRT4_DM2\r
+SCSI_Out_DBx__7__DR EQU CYREG_PRT4_DR\r
+SCSI_Out_DBx__7__INP_DIS EQU CYREG_PRT4_INP_DIS\r
+SCSI_Out_DBx__7__INTTYPE EQU CYREG_PICU4_INTTYPE4\r
+SCSI_Out_DBx__7__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
+SCSI_Out_DBx__7__LCD_EN EQU CYREG_PRT4_LCD_EN\r
+SCSI_Out_DBx__7__MASK EQU 0x10\r
+SCSI_Out_DBx__7__PC EQU CYREG_PRT4_PC4\r
+SCSI_Out_DBx__7__PORT EQU 4\r
+SCSI_Out_DBx__7__PRT EQU CYREG_PRT4_PRT\r
+SCSI_Out_DBx__7__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
+SCSI_Out_DBx__7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
+SCSI_Out_DBx__7__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
+SCSI_Out_DBx__7__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
+SCSI_Out_DBx__7__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
+SCSI_Out_DBx__7__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
+SCSI_Out_DBx__7__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
+SCSI_Out_DBx__7__PS EQU CYREG_PRT4_PS\r
+SCSI_Out_DBx__7__SHIFT EQU 4\r
+SCSI_Out_DBx__7__SLW EQU CYREG_PRT4_SLW\r
+SCSI_Out_DBx__DB0__AG EQU CYREG_PRT6_AG\r
+SCSI_Out_DBx__DB0__AMUX EQU CYREG_PRT6_AMUX\r
+SCSI_Out_DBx__DB0__BIE EQU CYREG_PRT6_BIE\r
+SCSI_Out_DBx__DB0__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
+SCSI_Out_DBx__DB0__BYP EQU CYREG_PRT6_BYP\r
+SCSI_Out_DBx__DB0__CTL EQU CYREG_PRT6_CTL\r
+SCSI_Out_DBx__DB0__DM0 EQU CYREG_PRT6_DM0\r
+SCSI_Out_DBx__DB0__DM1 EQU CYREG_PRT6_DM1\r
+SCSI_Out_DBx__DB0__DM2 EQU CYREG_PRT6_DM2\r
+SCSI_Out_DBx__DB0__DR EQU CYREG_PRT6_DR\r
+SCSI_Out_DBx__DB0__INP_DIS EQU CYREG_PRT6_INP_DIS\r
+SCSI_Out_DBx__DB0__INTTYPE EQU CYREG_PICU6_INTTYPE3\r
+SCSI_Out_DBx__DB0__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
+SCSI_Out_DBx__DB0__LCD_EN EQU CYREG_PRT6_LCD_EN\r
+SCSI_Out_DBx__DB0__MASK EQU 0x08\r
+SCSI_Out_DBx__DB0__PC EQU CYREG_PRT6_PC3\r
+SCSI_Out_DBx__DB0__PORT EQU 6\r
+SCSI_Out_DBx__DB0__PRT EQU CYREG_PRT6_PRT\r
+SCSI_Out_DBx__DB0__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
+SCSI_Out_DBx__DB0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
+SCSI_Out_DBx__DB0__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
+SCSI_Out_DBx__DB0__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
+SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
+SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
+SCSI_Out_DBx__DB0__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
+SCSI_Out_DBx__DB0__PS EQU CYREG_PRT6_PS\r
+SCSI_Out_DBx__DB0__SHIFT EQU 3\r
+SCSI_Out_DBx__DB0__SLW EQU CYREG_PRT6_SLW\r
+SCSI_Out_DBx__DB1__AG EQU CYREG_PRT6_AG\r
+SCSI_Out_DBx__DB1__AMUX EQU CYREG_PRT6_AMUX\r
+SCSI_Out_DBx__DB1__BIE EQU CYREG_PRT6_BIE\r
+SCSI_Out_DBx__DB1__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
+SCSI_Out_DBx__DB1__BYP EQU CYREG_PRT6_BYP\r
+SCSI_Out_DBx__DB1__CTL EQU CYREG_PRT6_CTL\r
+SCSI_Out_DBx__DB1__DM0 EQU CYREG_PRT6_DM0\r
+SCSI_Out_DBx__DB1__DM1 EQU CYREG_PRT6_DM1\r
+SCSI_Out_DBx__DB1__DM2 EQU CYREG_PRT6_DM2\r
+SCSI_Out_DBx__DB1__DR EQU CYREG_PRT6_DR\r
+SCSI_Out_DBx__DB1__INP_DIS EQU CYREG_PRT6_INP_DIS\r
+SCSI_Out_DBx__DB1__INTTYPE EQU CYREG_PICU6_INTTYPE2\r
+SCSI_Out_DBx__DB1__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
+SCSI_Out_DBx__DB1__LCD_EN EQU CYREG_PRT6_LCD_EN\r
+SCSI_Out_DBx__DB1__MASK EQU 0x04\r
+SCSI_Out_DBx__DB1__PC EQU CYREG_PRT6_PC2\r
+SCSI_Out_DBx__DB1__PORT EQU 6\r
+SCSI_Out_DBx__DB1__PRT EQU CYREG_PRT6_PRT\r
+SCSI_Out_DBx__DB1__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
+SCSI_Out_DBx__DB1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
+SCSI_Out_DBx__DB1__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
+SCSI_Out_DBx__DB1__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
+SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
+SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
+SCSI_Out_DBx__DB1__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
+SCSI_Out_DBx__DB1__PS EQU CYREG_PRT6_PS\r
+SCSI_Out_DBx__DB1__SHIFT EQU 2\r
+SCSI_Out_DBx__DB1__SLW EQU CYREG_PRT6_SLW\r
+SCSI_Out_DBx__DB2__AG EQU CYREG_PRT6_AG\r
+SCSI_Out_DBx__DB2__AMUX EQU CYREG_PRT6_AMUX\r
+SCSI_Out_DBx__DB2__BIE EQU CYREG_PRT6_BIE\r
+SCSI_Out_DBx__DB2__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
+SCSI_Out_DBx__DB2__BYP EQU CYREG_PRT6_BYP\r
+SCSI_Out_DBx__DB2__CTL EQU CYREG_PRT6_CTL\r
+SCSI_Out_DBx__DB2__DM0 EQU CYREG_PRT6_DM0\r
+SCSI_Out_DBx__DB2__DM1 EQU CYREG_PRT6_DM1\r
+SCSI_Out_DBx__DB2__DM2 EQU CYREG_PRT6_DM2\r
+SCSI_Out_DBx__DB2__DR EQU CYREG_PRT6_DR\r
+SCSI_Out_DBx__DB2__INP_DIS EQU CYREG_PRT6_INP_DIS\r
+SCSI_Out_DBx__DB2__INTTYPE EQU CYREG_PICU6_INTTYPE1\r
+SCSI_Out_DBx__DB2__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
+SCSI_Out_DBx__DB2__LCD_EN EQU CYREG_PRT6_LCD_EN\r
+SCSI_Out_DBx__DB2__MASK EQU 0x02\r
+SCSI_Out_DBx__DB2__PC EQU CYREG_PRT6_PC1\r
+SCSI_Out_DBx__DB2__PORT EQU 6\r
+SCSI_Out_DBx__DB2__PRT EQU CYREG_PRT6_PRT\r
+SCSI_Out_DBx__DB2__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
+SCSI_Out_DBx__DB2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
+SCSI_Out_DBx__DB2__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
+SCSI_Out_DBx__DB2__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
+SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
+SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
+SCSI_Out_DBx__DB2__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
+SCSI_Out_DBx__DB2__PS EQU CYREG_PRT6_PS\r
+SCSI_Out_DBx__DB2__SHIFT EQU 1\r
+SCSI_Out_DBx__DB2__SLW EQU CYREG_PRT6_SLW\r
+SCSI_Out_DBx__DB3__AG EQU CYREG_PRT6_AG\r
+SCSI_Out_DBx__DB3__AMUX EQU CYREG_PRT6_AMUX\r
+SCSI_Out_DBx__DB3__BIE EQU CYREG_PRT6_BIE\r
+SCSI_Out_DBx__DB3__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
+SCSI_Out_DBx__DB3__BYP EQU CYREG_PRT6_BYP\r
+SCSI_Out_DBx__DB3__CTL EQU CYREG_PRT6_CTL\r
+SCSI_Out_DBx__DB3__DM0 EQU CYREG_PRT6_DM0\r
+SCSI_Out_DBx__DB3__DM1 EQU CYREG_PRT6_DM1\r
+SCSI_Out_DBx__DB3__DM2 EQU CYREG_PRT6_DM2\r
+SCSI_Out_DBx__DB3__DR EQU CYREG_PRT6_DR\r
+SCSI_Out_DBx__DB3__INP_DIS EQU CYREG_PRT6_INP_DIS\r
+SCSI_Out_DBx__DB3__INTTYPE EQU CYREG_PICU6_INTTYPE0\r
+SCSI_Out_DBx__DB3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
+SCSI_Out_DBx__DB3__LCD_EN EQU CYREG_PRT6_LCD_EN\r
+SCSI_Out_DBx__DB3__MASK EQU 0x01\r
+SCSI_Out_DBx__DB3__PC EQU CYREG_PRT6_PC0\r
+SCSI_Out_DBx__DB3__PORT EQU 6\r
+SCSI_Out_DBx__DB3__PRT EQU CYREG_PRT6_PRT\r
+SCSI_Out_DBx__DB3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
+SCSI_Out_DBx__DB3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
+SCSI_Out_DBx__DB3__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
+SCSI_Out_DBx__DB3__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
+SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
+SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
+SCSI_Out_DBx__DB3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
+SCSI_Out_DBx__DB3__PS EQU CYREG_PRT6_PS\r
+SCSI_Out_DBx__DB3__SHIFT EQU 0\r
+SCSI_Out_DBx__DB3__SLW EQU CYREG_PRT6_SLW\r
+SCSI_Out_DBx__DB4__AG EQU CYREG_PRT4_AG\r
+SCSI_Out_DBx__DB4__AMUX EQU CYREG_PRT4_AMUX\r
+SCSI_Out_DBx__DB4__BIE EQU CYREG_PRT4_BIE\r
+SCSI_Out_DBx__DB4__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
+SCSI_Out_DBx__DB4__BYP EQU CYREG_PRT4_BYP\r
+SCSI_Out_DBx__DB4__CTL EQU CYREG_PRT4_CTL\r
+SCSI_Out_DBx__DB4__DM0 EQU CYREG_PRT4_DM0\r
+SCSI_Out_DBx__DB4__DM1 EQU CYREG_PRT4_DM1\r
+SCSI_Out_DBx__DB4__DM2 EQU CYREG_PRT4_DM2\r
+SCSI_Out_DBx__DB4__DR EQU CYREG_PRT4_DR\r
+SCSI_Out_DBx__DB4__INP_DIS EQU CYREG_PRT4_INP_DIS\r
+SCSI_Out_DBx__DB4__INTTYPE EQU CYREG_PICU4_INTTYPE7\r
+SCSI_Out_DBx__DB4__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
+SCSI_Out_DBx__DB4__LCD_EN EQU CYREG_PRT4_LCD_EN\r
+SCSI_Out_DBx__DB4__MASK EQU 0x80\r
+SCSI_Out_DBx__DB4__PC EQU CYREG_PRT4_PC7\r
+SCSI_Out_DBx__DB4__PORT EQU 4\r
+SCSI_Out_DBx__DB4__PRT EQU CYREG_PRT4_PRT\r
+SCSI_Out_DBx__DB4__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
+SCSI_Out_DBx__DB4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
+SCSI_Out_DBx__DB4__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
+SCSI_Out_DBx__DB4__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
+SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
+SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
+SCSI_Out_DBx__DB4__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
+SCSI_Out_DBx__DB4__PS EQU CYREG_PRT4_PS\r
+SCSI_Out_DBx__DB4__SHIFT EQU 7\r
+SCSI_Out_DBx__DB4__SLW EQU CYREG_PRT4_SLW\r
+SCSI_Out_DBx__DB5__AG EQU CYREG_PRT4_AG\r
+SCSI_Out_DBx__DB5__AMUX EQU CYREG_PRT4_AMUX\r
+SCSI_Out_DBx__DB5__BIE EQU CYREG_PRT4_BIE\r
+SCSI_Out_DBx__DB5__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
+SCSI_Out_DBx__DB5__BYP EQU CYREG_PRT4_BYP\r
+SCSI_Out_DBx__DB5__CTL EQU CYREG_PRT4_CTL\r
+SCSI_Out_DBx__DB5__DM0 EQU CYREG_PRT4_DM0\r
+SCSI_Out_DBx__DB5__DM1 EQU CYREG_PRT4_DM1\r
+SCSI_Out_DBx__DB5__DM2 EQU CYREG_PRT4_DM2\r
+SCSI_Out_DBx__DB5__DR EQU CYREG_PRT4_DR\r
+SCSI_Out_DBx__DB5__INP_DIS EQU CYREG_PRT4_INP_DIS\r
+SCSI_Out_DBx__DB5__INTTYPE EQU CYREG_PICU4_INTTYPE6\r
+SCSI_Out_DBx__DB5__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
+SCSI_Out_DBx__DB5__LCD_EN EQU CYREG_PRT4_LCD_EN\r
+SCSI_Out_DBx__DB5__MASK EQU 0x40\r
+SCSI_Out_DBx__DB5__PC EQU CYREG_PRT4_PC6\r
+SCSI_Out_DBx__DB5__PORT EQU 4\r
+SCSI_Out_DBx__DB5__PRT EQU CYREG_PRT4_PRT\r
+SCSI_Out_DBx__DB5__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
+SCSI_Out_DBx__DB5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
+SCSI_Out_DBx__DB5__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
+SCSI_Out_DBx__DB5__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
+SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
+SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
+SCSI_Out_DBx__DB5__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
+SCSI_Out_DBx__DB5__PS EQU CYREG_PRT4_PS\r
+SCSI_Out_DBx__DB5__SHIFT EQU 6\r
+SCSI_Out_DBx__DB5__SLW EQU CYREG_PRT4_SLW\r
+SCSI_Out_DBx__DB6__AG EQU CYREG_PRT4_AG\r
+SCSI_Out_DBx__DB6__AMUX EQU CYREG_PRT4_AMUX\r
+SCSI_Out_DBx__DB6__BIE EQU CYREG_PRT4_BIE\r
+SCSI_Out_DBx__DB6__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
+SCSI_Out_DBx__DB6__BYP EQU CYREG_PRT4_BYP\r
+SCSI_Out_DBx__DB6__CTL EQU CYREG_PRT4_CTL\r
+SCSI_Out_DBx__DB6__DM0 EQU CYREG_PRT4_DM0\r
+SCSI_Out_DBx__DB6__DM1 EQU CYREG_PRT4_DM1\r
+SCSI_Out_DBx__DB6__DM2 EQU CYREG_PRT4_DM2\r
+SCSI_Out_DBx__DB6__DR EQU CYREG_PRT4_DR\r
+SCSI_Out_DBx__DB6__INP_DIS EQU CYREG_PRT4_INP_DIS\r
+SCSI_Out_DBx__DB6__INTTYPE EQU CYREG_PICU4_INTTYPE5\r
+SCSI_Out_DBx__DB6__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
+SCSI_Out_DBx__DB6__LCD_EN EQU CYREG_PRT4_LCD_EN\r
+SCSI_Out_DBx__DB6__MASK EQU 0x20\r
+SCSI_Out_DBx__DB6__PC EQU CYREG_PRT4_PC5\r
+SCSI_Out_DBx__DB6__PORT EQU 4\r
+SCSI_Out_DBx__DB6__PRT EQU CYREG_PRT4_PRT\r
+SCSI_Out_DBx__DB6__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
+SCSI_Out_DBx__DB6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
+SCSI_Out_DBx__DB6__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
+SCSI_Out_DBx__DB6__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
+SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
+SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
+SCSI_Out_DBx__DB6__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
+SCSI_Out_DBx__DB6__PS EQU CYREG_PRT4_PS\r
+SCSI_Out_DBx__DB6__SHIFT EQU 5\r
+SCSI_Out_DBx__DB6__SLW EQU CYREG_PRT4_SLW\r
+SCSI_Out_DBx__DB7__AG EQU CYREG_PRT4_AG\r
+SCSI_Out_DBx__DB7__AMUX EQU CYREG_PRT4_AMUX\r
+SCSI_Out_DBx__DB7__BIE EQU CYREG_PRT4_BIE\r
+SCSI_Out_DBx__DB7__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
+SCSI_Out_DBx__DB7__BYP EQU CYREG_PRT4_BYP\r
+SCSI_Out_DBx__DB7__CTL EQU CYREG_PRT4_CTL\r
+SCSI_Out_DBx__DB7__DM0 EQU CYREG_PRT4_DM0\r
+SCSI_Out_DBx__DB7__DM1 EQU CYREG_PRT4_DM1\r
+SCSI_Out_DBx__DB7__DM2 EQU CYREG_PRT4_DM2\r
+SCSI_Out_DBx__DB7__DR EQU CYREG_PRT4_DR\r
+SCSI_Out_DBx__DB7__INP_DIS EQU CYREG_PRT4_INP_DIS\r
+SCSI_Out_DBx__DB7__INTTYPE EQU CYREG_PICU4_INTTYPE4\r
+SCSI_Out_DBx__DB7__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
+SCSI_Out_DBx__DB7__LCD_EN EQU CYREG_PRT4_LCD_EN\r
+SCSI_Out_DBx__DB7__MASK EQU 0x10\r
+SCSI_Out_DBx__DB7__PC EQU CYREG_PRT4_PC4\r
+SCSI_Out_DBx__DB7__PORT EQU 4\r
+SCSI_Out_DBx__DB7__PRT EQU CYREG_PRT4_PRT\r
+SCSI_Out_DBx__DB7__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
+SCSI_Out_DBx__DB7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
+SCSI_Out_DBx__DB7__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
+SCSI_Out_DBx__DB7__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
+SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
+SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
+SCSI_Out_DBx__DB7__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
+SCSI_Out_DBx__DB7__PS EQU CYREG_PRT4_PS\r
+SCSI_Out_DBx__DB7__SHIFT EQU 4\r
+SCSI_Out_DBx__DB7__SLW EQU CYREG_PRT4_SLW\r
+\r
+; SCSI_Parity_Error\r
+SCSI_Parity_Error_sts_sts_reg__0__MASK EQU 0x01\r
+SCSI_Parity_Error_sts_sts_reg__0__POS EQU 0\r
+SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB01_02_ACTL\r
+SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB01_02_ST\r
+SCSI_Parity_Error_sts_sts_reg__MASK EQU 0x01\r
+SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB01_MSK\r
+SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB01_ACTL\r
+SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB01_ST\r
+\r
+; SCSI_RST_ISR\r
+SCSI_RST_ISR__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
+SCSI_RST_ISR__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
+SCSI_RST_ISR__INTC_MASK EQU 0x02\r
+SCSI_RST_ISR__INTC_NUMBER EQU 1\r
+SCSI_RST_ISR__INTC_PRIOR_NUM EQU 7\r
+SCSI_RST_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_1\r
+SCSI_RST_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
+SCSI_RST_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
+\r
+; SCSI_RX_DMA\r
+SCSI_RX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0\r
+SCSI_RX_DMA__DRQ_NUMBER EQU 0\r
+SCSI_RX_DMA__NUMBEROF_TDS EQU 0\r
+SCSI_RX_DMA__PRIORITY EQU 2\r
+SCSI_RX_DMA__TERMIN_EN EQU 0\r
+SCSI_RX_DMA__TERMIN_SEL EQU 0\r
+SCSI_RX_DMA__TERMOUT0_EN EQU 1\r
+SCSI_RX_DMA__TERMOUT0_SEL EQU 0\r
+SCSI_RX_DMA__TERMOUT1_EN EQU 0\r
+SCSI_RX_DMA__TERMOUT1_SEL EQU 0\r
+SCSI_RX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
+SCSI_RX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
+SCSI_RX_DMA_COMPLETE__INTC_MASK EQU 0x04\r
+SCSI_RX_DMA_COMPLETE__INTC_NUMBER EQU 2\r
+SCSI_RX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7\r
+SCSI_RX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_2\r
+SCSI_RX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
+SCSI_RX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
+\r
+; SCSI_SEL_ISR\r
+SCSI_SEL_ISR__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
+SCSI_SEL_ISR__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
+SCSI_SEL_ISR__INTC_MASK EQU 0x08\r
+SCSI_SEL_ISR__INTC_NUMBER EQU 3\r
+SCSI_SEL_ISR__INTC_PRIOR_NUM EQU 7\r
+SCSI_SEL_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_3\r
+SCSI_SEL_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
+SCSI_SEL_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
+\r
+; SCSI_TX_DMA\r
+SCSI_TX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0\r
+SCSI_TX_DMA__DRQ_NUMBER EQU 1\r
+SCSI_TX_DMA__NUMBEROF_TDS EQU 0\r
+SCSI_TX_DMA__PRIORITY EQU 2\r
+SCSI_TX_DMA__TERMIN_EN EQU 0\r
+SCSI_TX_DMA__TERMIN_SEL EQU 0\r
+SCSI_TX_DMA__TERMOUT0_EN EQU 1\r
+SCSI_TX_DMA__TERMOUT0_SEL EQU 1\r
+SCSI_TX_DMA__TERMOUT1_EN EQU 0\r
+SCSI_TX_DMA__TERMOUT1_SEL EQU 0\r
+SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
+SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
+SCSI_TX_DMA_COMPLETE__INTC_MASK EQU 0x10\r
+SCSI_TX_DMA_COMPLETE__INTC_NUMBER EQU 4\r
+SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7\r
+SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_4\r
+SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
+SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
+\r
+; SDCard_BSPIM\r
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL\r
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB04_05_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB04_05_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB04_05_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB04_05_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB04_05_MSK\r
+SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB04_05_MSK\r
+SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB04_05_MSK\r
+SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB04_05_MSK\r
+SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL\r
+SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB04_CTL\r
+SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB04_ST_CTL\r
+SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB04_CTL\r
+SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB04_ST_CTL\r
+SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL\r
+SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL\r
+SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB04_MSK\r
+SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL\r
+SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB04_05_ST\r
+SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB04_MSK\r
+SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL\r
+SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB04_ST_CTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB04_ST_CTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB04_ST\r
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB08_09_ACTL\r
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB08_09_ST\r
+SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10\r
+SDCard_BSPIM_RxStsReg__4__POS EQU 4\r
+SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20\r
+SDCard_BSPIM_RxStsReg__5__POS EQU 5\r
+SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40\r
+SDCard_BSPIM_RxStsReg__6__POS EQU 6\r
+SDCard_BSPIM_RxStsReg__MASK EQU 0x70\r
+SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB08_MSK\r
+SDCard_BSPIM_RxStsReg__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB08_MSK_ACTL\r
+SDCard_BSPIM_RxStsReg__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB08_MSK_ACTL\r
+SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB08_ACTL\r
+SDCard_BSPIM_RxStsReg__STATUS_CNT_REG EQU CYREG_B1_UDB08_ST_CTL\r
+SDCard_BSPIM_RxStsReg__STATUS_CONTROL_REG EQU CYREG_B1_UDB08_ST_CTL\r
+SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB08_ST\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB04_05_A0\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB04_05_A1\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B1_UDB04_05_D0\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B1_UDB04_05_D1\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B1_UDB04_05_F0\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B1_UDB04_05_F1\r
+SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B1_UDB04_A0_A1\r
+SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B1_UDB04_A0\r
+SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B1_UDB04_A1\r
+SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B1_UDB04_D0_D1\r
+SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B1_UDB04_D0\r
+SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B1_UDB04_D1\r
+SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL\r
+SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B1_UDB04_F0_F1\r
+SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B1_UDB04_F0\r
+SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B1_UDB04_F1\r
+SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL\r
+SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL\r
+SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01\r
+SDCard_BSPIM_TxStsReg__0__POS EQU 0\r
+SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02\r
+SDCard_BSPIM_TxStsReg__1__POS EQU 1\r
+SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL\r
+SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST\r
+SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04\r
+SDCard_BSPIM_TxStsReg__2__POS EQU 2\r
+SDCard_BSPIM_TxStsReg__3__MASK EQU 0x08\r
+SDCard_BSPIM_TxStsReg__3__POS EQU 3\r
+SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10\r
+SDCard_BSPIM_TxStsReg__4__POS EQU 4\r
+SDCard_BSPIM_TxStsReg__MASK EQU 0x1F\r
+SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB07_MSK\r
+SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL\r
+SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB07_ST\r
+\r
+; SD_CD\r
+SD_CD__0__INTTYPE EQU CYREG_PICU3_INTTYPE6\r
+SD_CD__0__MASK EQU 0x40\r
+SD_CD__0__PC EQU CYREG_PRT3_PC6\r
+SD_CD__0__PORT EQU 3\r
+SD_CD__0__SHIFT EQU 6\r
+SD_CD__AG EQU CYREG_PRT3_AG\r
+SD_CD__AMUX EQU CYREG_PRT3_AMUX\r
+SD_CD__BIE EQU CYREG_PRT3_BIE\r
+SD_CD__BIT_MASK EQU CYREG_PRT3_BIT_MASK\r
+SD_CD__BYP EQU CYREG_PRT3_BYP\r
+SD_CD__CTL EQU CYREG_PRT3_CTL\r
+SD_CD__DM0 EQU CYREG_PRT3_DM0\r
+SD_CD__DM1 EQU CYREG_PRT3_DM1\r
+SD_CD__DM2 EQU CYREG_PRT3_DM2\r
+SD_CD__DR EQU CYREG_PRT3_DR\r
+SD_CD__INP_DIS EQU CYREG_PRT3_INP_DIS\r
+SD_CD__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE\r
+SD_CD__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG\r
+SD_CD__LCD_EN EQU CYREG_PRT3_LCD_EN\r
+SD_CD__MASK EQU 0x40\r
+SD_CD__PORT EQU 3\r
+SD_CD__PRT EQU CYREG_PRT3_PRT\r
+SD_CD__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL\r
+SD_CD__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN\r
+SD_CD__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0\r
+SD_CD__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1\r
+SD_CD__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0\r
+SD_CD__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1\r
+SD_CD__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT\r
+SD_CD__PS EQU CYREG_PRT3_PS\r
+SD_CD__SHIFT EQU 6\r
+SD_CD__SLW EQU CYREG_PRT3_SLW\r
+\r
+; SD_CS\r
+SD_CS__0__INTTYPE EQU CYREG_PICU3_INTTYPE4\r
+SD_CS__0__MASK EQU 0x10\r
+SD_CS__0__PC EQU CYREG_PRT3_PC4\r
+SD_CS__0__PORT EQU 3\r
+SD_CS__0__SHIFT EQU 4\r
+SD_CS__AG EQU CYREG_PRT3_AG\r
+SD_CS__AMUX EQU CYREG_PRT3_AMUX\r
+SD_CS__BIE EQU CYREG_PRT3_BIE\r
+SD_CS__BIT_MASK EQU CYREG_PRT3_BIT_MASK\r
+SD_CS__BYP EQU CYREG_PRT3_BYP\r
+SD_CS__CTL EQU CYREG_PRT3_CTL\r
+SD_CS__DM0 EQU CYREG_PRT3_DM0\r
+SD_CS__DM1 EQU CYREG_PRT3_DM1\r
+SD_CS__DM2 EQU CYREG_PRT3_DM2\r
+SD_CS__DR EQU CYREG_PRT3_DR\r
+SD_CS__INP_DIS EQU CYREG_PRT3_INP_DIS\r
+SD_CS__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE\r
+SD_CS__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG\r
+SD_CS__LCD_EN EQU CYREG_PRT3_LCD_EN\r
+SD_CS__MASK EQU 0x10\r
+SD_CS__PORT EQU 3\r
+SD_CS__PRT EQU CYREG_PRT3_PRT\r
+SD_CS__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL\r
+SD_CS__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN\r
+SD_CS__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0\r
+SD_CS__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1\r
+SD_CS__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0\r
+SD_CS__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1\r
+SD_CS__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT\r
+SD_CS__PS EQU CYREG_PRT3_PS\r
+SD_CS__SHIFT EQU 4\r
+SD_CS__SLW EQU CYREG_PRT3_SLW\r
+\r
+; SD_DAT1\r
+SD_DAT1__0__INTTYPE EQU CYREG_PICU3_INTTYPE0\r
+SD_DAT1__0__MASK EQU 0x01\r
+SD_DAT1__0__PC EQU CYREG_PRT3_PC0\r
+SD_DAT1__0__PORT EQU 3\r
+SD_DAT1__0__SHIFT EQU 0\r
+SD_DAT1__AG EQU CYREG_PRT3_AG\r
+SD_DAT1__AMUX EQU CYREG_PRT3_AMUX\r
+SD_DAT1__BIE EQU CYREG_PRT3_BIE\r
+SD_DAT1__BIT_MASK EQU CYREG_PRT3_BIT_MASK\r
+SD_DAT1__BYP EQU CYREG_PRT3_BYP\r
+SD_DAT1__CTL EQU CYREG_PRT3_CTL\r
+SD_DAT1__DM0 EQU CYREG_PRT3_DM0\r
+SD_DAT1__DM1 EQU CYREG_PRT3_DM1\r
+SD_DAT1__DM2 EQU CYREG_PRT3_DM2\r
+SD_DAT1__DR EQU CYREG_PRT3_DR\r
+SD_DAT1__INP_DIS EQU CYREG_PRT3_INP_DIS\r
+SD_DAT1__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE\r
+SD_DAT1__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG\r
+SD_DAT1__LCD_EN EQU CYREG_PRT3_LCD_EN\r
+SD_DAT1__MASK EQU 0x01\r
+SD_DAT1__PORT EQU 3\r
+SD_DAT1__PRT EQU CYREG_PRT3_PRT\r
+SD_DAT1__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL\r
+SD_DAT1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN\r
+SD_DAT1__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0\r
+SD_DAT1__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1\r
+SD_DAT1__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0\r
+SD_DAT1__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1\r
+SD_DAT1__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT\r
+SD_DAT1__PS EQU CYREG_PRT3_PS\r
+SD_DAT1__SHIFT EQU 0\r
+SD_DAT1__SLW EQU CYREG_PRT3_SLW\r
+\r
+; SD_DAT2\r
+SD_DAT2__0__INTTYPE EQU CYREG_PICU3_INTTYPE5\r
+SD_DAT2__0__MASK EQU 0x20\r
+SD_DAT2__0__PC EQU CYREG_PRT3_PC5\r
+SD_DAT2__0__PORT EQU 3\r
+SD_DAT2__0__SHIFT EQU 5\r
+SD_DAT2__AG EQU CYREG_PRT3_AG\r
+SD_DAT2__AMUX EQU CYREG_PRT3_AMUX\r
+SD_DAT2__BIE EQU CYREG_PRT3_BIE\r
+SD_DAT2__BIT_MASK EQU CYREG_PRT3_BIT_MASK\r
+SD_DAT2__BYP EQU CYREG_PRT3_BYP\r
+SD_DAT2__CTL EQU CYREG_PRT3_CTL\r
+SD_DAT2__DM0 EQU CYREG_PRT3_DM0\r
+SD_DAT2__DM1 EQU CYREG_PRT3_DM1\r
+SD_DAT2__DM2 EQU CYREG_PRT3_DM2\r
+SD_DAT2__DR EQU CYREG_PRT3_DR\r
+SD_DAT2__INP_DIS EQU CYREG_PRT3_INP_DIS\r
+SD_DAT2__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE\r
+SD_DAT2__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG\r
+SD_DAT2__LCD_EN EQU CYREG_PRT3_LCD_EN\r
+SD_DAT2__MASK EQU 0x20\r
+SD_DAT2__PORT EQU 3\r
+SD_DAT2__PRT EQU CYREG_PRT3_PRT\r
+SD_DAT2__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL\r
+SD_DAT2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN\r
+SD_DAT2__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0\r
+SD_DAT2__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1\r
+SD_DAT2__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0\r
+SD_DAT2__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1\r
+SD_DAT2__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT\r
+SD_DAT2__PS EQU CYREG_PRT3_PS\r
+SD_DAT2__SHIFT EQU 5\r
+SD_DAT2__SLW EQU CYREG_PRT3_SLW\r
+\r
+; SD_Data_Clk\r
+SD_Data_Clk__CFG0 EQU CYREG_CLKDIST_DCFG0_CFG0\r
+SD_Data_Clk__CFG1 EQU CYREG_CLKDIST_DCFG0_CFG1\r
+SD_Data_Clk__CFG2 EQU CYREG_CLKDIST_DCFG0_CFG2\r
+SD_Data_Clk__CFG2_SRC_SEL_MASK EQU 0x07\r
+SD_Data_Clk__INDEX EQU 0x00\r
+SD_Data_Clk__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2\r
+SD_Data_Clk__PM_ACT_MSK EQU 0x01\r
+SD_Data_Clk__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2\r
+SD_Data_Clk__PM_STBY_MSK EQU 0x01\r
+\r
+; SD_MISO\r
+SD_MISO__0__INTTYPE EQU CYREG_PICU3_INTTYPE1\r
+SD_MISO__0__MASK EQU 0x02\r
+SD_MISO__0__PC EQU CYREG_PRT3_PC1\r
+SD_MISO__0__PORT EQU 3\r
+SD_MISO__0__SHIFT EQU 1\r
+SD_MISO__AG EQU CYREG_PRT3_AG\r
+SD_MISO__AMUX EQU CYREG_PRT3_AMUX\r
+SD_MISO__BIE EQU CYREG_PRT3_BIE\r
+SD_MISO__BIT_MASK EQU CYREG_PRT3_BIT_MASK\r
+SD_MISO__BYP EQU CYREG_PRT3_BYP\r
+SD_MISO__CTL EQU CYREG_PRT3_CTL\r
+SD_MISO__DM0 EQU CYREG_PRT3_DM0\r
+SD_MISO__DM1 EQU CYREG_PRT3_DM1\r
+SD_MISO__DM2 EQU CYREG_PRT3_DM2\r
+SD_MISO__DR EQU CYREG_PRT3_DR\r
+SD_MISO__INP_DIS EQU CYREG_PRT3_INP_DIS\r
+SD_MISO__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE\r
+SD_MISO__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG\r
+SD_MISO__LCD_EN EQU CYREG_PRT3_LCD_EN\r
+SD_MISO__MASK EQU 0x02\r
+SD_MISO__PORT EQU 3\r
+SD_MISO__PRT EQU CYREG_PRT3_PRT\r
+SD_MISO__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL\r
+SD_MISO__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN\r
+SD_MISO__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0\r
+SD_MISO__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1\r
+SD_MISO__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0\r
+SD_MISO__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1\r
+SD_MISO__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT\r
+SD_MISO__PS EQU CYREG_PRT3_PS\r
+SD_MISO__SHIFT EQU 1\r
+SD_MISO__SLW EQU CYREG_PRT3_SLW\r
+\r
+; SD_MOSI\r
+SD_MOSI__0__INTTYPE EQU CYREG_PICU3_INTTYPE3\r
+SD_MOSI__0__MASK EQU 0x08\r
+SD_MOSI__0__PC EQU CYREG_PRT3_PC3\r
+SD_MOSI__0__PORT EQU 3\r
+SD_MOSI__0__SHIFT EQU 3\r
+SD_MOSI__AG EQU CYREG_PRT3_AG\r
+SD_MOSI__AMUX EQU CYREG_PRT3_AMUX\r
+SD_MOSI__BIE EQU CYREG_PRT3_BIE\r
+SD_MOSI__BIT_MASK EQU CYREG_PRT3_BIT_MASK\r
+SD_MOSI__BYP EQU CYREG_PRT3_BYP\r
+SD_MOSI__CTL EQU CYREG_PRT3_CTL\r
+SD_MOSI__DM0 EQU CYREG_PRT3_DM0\r
+SD_MOSI__DM1 EQU CYREG_PRT3_DM1\r
+SD_MOSI__DM2 EQU CYREG_PRT3_DM2\r
+SD_MOSI__DR EQU CYREG_PRT3_DR\r
+SD_MOSI__INP_DIS EQU CYREG_PRT3_INP_DIS\r
+SD_MOSI__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE\r
+SD_MOSI__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG\r
+SD_MOSI__LCD_EN EQU CYREG_PRT3_LCD_EN\r
+SD_MOSI__MASK EQU 0x08\r
+SD_MOSI__PORT EQU 3\r
+SD_MOSI__PRT EQU CYREG_PRT3_PRT\r
+SD_MOSI__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL\r
+SD_MOSI__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN\r
+SD_MOSI__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0\r
+SD_MOSI__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1\r
+SD_MOSI__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0\r
+SD_MOSI__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1\r
+SD_MOSI__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT\r
+SD_MOSI__PS EQU CYREG_PRT3_PS\r
+SD_MOSI__SHIFT EQU 3\r
+SD_MOSI__SLW EQU CYREG_PRT3_SLW\r
+\r
+; SD_RX_DMA\r
+SD_RX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0\r
+SD_RX_DMA__DRQ_NUMBER EQU 2\r
+SD_RX_DMA__NUMBEROF_TDS EQU 0\r
+SD_RX_DMA__PRIORITY EQU 0\r
+SD_RX_DMA__TERMIN_EN EQU 0\r
+SD_RX_DMA__TERMIN_SEL EQU 0\r
+SD_RX_DMA__TERMOUT0_EN EQU 1\r
+SD_RX_DMA__TERMOUT0_SEL EQU 2\r
+SD_RX_DMA__TERMOUT1_EN EQU 0\r
+SD_RX_DMA__TERMOUT1_SEL EQU 0\r
+SD_RX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
+SD_RX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
+SD_RX_DMA_COMPLETE__INTC_MASK EQU 0x20\r
+SD_RX_DMA_COMPLETE__INTC_NUMBER EQU 5\r
+SD_RX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7\r
+SD_RX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_5\r
+SD_RX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
+SD_RX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
+\r
+; SD_SCK\r
+SD_SCK__0__INTTYPE EQU CYREG_PICU3_INTTYPE2\r
+SD_SCK__0__MASK EQU 0x04\r
+SD_SCK__0__PC EQU CYREG_PRT3_PC2\r
+SD_SCK__0__PORT EQU 3\r
+SD_SCK__0__SHIFT EQU 2\r
+SD_SCK__AG EQU CYREG_PRT3_AG\r
+SD_SCK__AMUX EQU CYREG_PRT3_AMUX\r
+SD_SCK__BIE EQU CYREG_PRT3_BIE\r
+SD_SCK__BIT_MASK EQU CYREG_PRT3_BIT_MASK\r
+SD_SCK__BYP EQU CYREG_PRT3_BYP\r
+SD_SCK__CTL EQU CYREG_PRT3_CTL\r
+SD_SCK__DM0 EQU CYREG_PRT3_DM0\r
+SD_SCK__DM1 EQU CYREG_PRT3_DM1\r
+SD_SCK__DM2 EQU CYREG_PRT3_DM2\r
+SD_SCK__DR EQU CYREG_PRT3_DR\r
+SD_SCK__INP_DIS EQU CYREG_PRT3_INP_DIS\r
+SD_SCK__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE\r
+SD_SCK__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG\r
+SD_SCK__LCD_EN EQU CYREG_PRT3_LCD_EN\r
+SD_SCK__MASK EQU 0x04\r
+SD_SCK__PORT EQU 3\r
+SD_SCK__PRT EQU CYREG_PRT3_PRT\r
+SD_SCK__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL\r
+SD_SCK__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN\r
+SD_SCK__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0\r
+SD_SCK__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1\r
+SD_SCK__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0\r
+SD_SCK__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1\r
+SD_SCK__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT\r
+SD_SCK__PS EQU CYREG_PRT3_PS\r
+SD_SCK__SHIFT EQU 2\r
+SD_SCK__SLW EQU CYREG_PRT3_SLW\r
+\r
+; SD_TX_DMA\r
+SD_TX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0\r
+SD_TX_DMA__DRQ_NUMBER EQU 3\r
+SD_TX_DMA__NUMBEROF_TDS EQU 0\r
+SD_TX_DMA__PRIORITY EQU 1\r
+SD_TX_DMA__TERMIN_EN EQU 0\r
+SD_TX_DMA__TERMIN_SEL EQU 0\r
+SD_TX_DMA__TERMOUT0_EN EQU 1\r
+SD_TX_DMA__TERMOUT0_SEL EQU 3\r
+SD_TX_DMA__TERMOUT1_EN EQU 0\r
+SD_TX_DMA__TERMOUT1_SEL EQU 0\r
+SD_TX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
+SD_TX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
+SD_TX_DMA_COMPLETE__INTC_MASK EQU 0x40\r
+SD_TX_DMA_COMPLETE__INTC_NUMBER EQU 6\r
+SD_TX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7\r
+SD_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_6\r
+SD_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
+SD_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
+\r
+; USBFS\r
+USBFS_arb_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
+USBFS_arb_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
+USBFS_arb_int__INTC_MASK EQU 0x400000\r
+USBFS_arb_int__INTC_NUMBER EQU 22\r
+USBFS_arb_int__INTC_PRIOR_NUM EQU 6\r
+USBFS_arb_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_22\r
+USBFS_arb_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
+USBFS_arb_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
+USBFS_bus_reset__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
+USBFS_bus_reset__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
+USBFS_bus_reset__INTC_MASK EQU 0x800000\r
+USBFS_bus_reset__INTC_NUMBER EQU 23\r
+USBFS_bus_reset__INTC_PRIOR_NUM EQU 7\r
+USBFS_bus_reset__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_23\r
+USBFS_bus_reset__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
+USBFS_bus_reset__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
+USBFS_Dm__0__INTTYPE EQU CYREG_PICU15_INTTYPE7\r
+USBFS_Dm__0__MASK EQU 0x80\r
+USBFS_Dm__0__PC EQU CYREG_IO_PC_PRT15_7_6_PC1\r
+USBFS_Dm__0__PORT EQU 15\r
+USBFS_Dm__0__SHIFT EQU 7\r
+USBFS_Dm__AG EQU CYREG_PRT15_AG\r
+USBFS_Dm__AMUX EQU CYREG_PRT15_AMUX\r
+USBFS_Dm__BIE EQU CYREG_PRT15_BIE\r
+USBFS_Dm__BIT_MASK EQU CYREG_PRT15_BIT_MASK\r
+USBFS_Dm__BYP EQU CYREG_PRT15_BYP\r
+USBFS_Dm__CTL EQU CYREG_PRT15_CTL\r
+USBFS_Dm__DM0 EQU CYREG_PRT15_DM0\r
+USBFS_Dm__DM1 EQU CYREG_PRT15_DM1\r
+USBFS_Dm__DM2 EQU CYREG_PRT15_DM2\r
+USBFS_Dm__DR EQU CYREG_PRT15_DR\r
+USBFS_Dm__INP_DIS EQU CYREG_PRT15_INP_DIS\r
+USBFS_Dm__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU15_BASE\r
+USBFS_Dm__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG\r
+USBFS_Dm__LCD_EN EQU CYREG_PRT15_LCD_EN\r
+USBFS_Dm__MASK EQU 0x80\r
+USBFS_Dm__PORT EQU 15\r
+USBFS_Dm__PRT EQU CYREG_PRT15_PRT\r
+USBFS_Dm__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL\r
+USBFS_Dm__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN\r
+USBFS_Dm__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0\r
+USBFS_Dm__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1\r
+USBFS_Dm__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0\r
+USBFS_Dm__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1\r
+USBFS_Dm__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT\r
+USBFS_Dm__PS EQU CYREG_PRT15_PS\r
+USBFS_Dm__SHIFT EQU 7\r
+USBFS_Dm__SLW EQU CYREG_PRT15_SLW\r
+USBFS_Dp__0__INTTYPE EQU CYREG_PICU15_INTTYPE6\r
+USBFS_Dp__0__MASK EQU 0x40\r
+USBFS_Dp__0__PC EQU CYREG_IO_PC_PRT15_7_6_PC0\r
+USBFS_Dp__0__PORT EQU 15\r
+USBFS_Dp__0__SHIFT EQU 6\r
+USBFS_Dp__AG EQU CYREG_PRT15_AG\r
+USBFS_Dp__AMUX EQU CYREG_PRT15_AMUX\r
+USBFS_Dp__BIE EQU CYREG_PRT15_BIE\r
+USBFS_Dp__BIT_MASK EQU CYREG_PRT15_BIT_MASK\r
+USBFS_Dp__BYP EQU CYREG_PRT15_BYP\r
+USBFS_Dp__CTL EQU CYREG_PRT15_CTL\r
+USBFS_Dp__DM0 EQU CYREG_PRT15_DM0\r
+USBFS_Dp__DM1 EQU CYREG_PRT15_DM1\r
+USBFS_Dp__DM2 EQU CYREG_PRT15_DM2\r
+USBFS_Dp__DR EQU CYREG_PRT15_DR\r
+USBFS_Dp__INP_DIS EQU CYREG_PRT15_INP_DIS\r
+USBFS_Dp__INTSTAT EQU CYREG_PICU15_INTSTAT\r
+USBFS_Dp__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU15_BASE\r
+USBFS_Dp__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG\r
+USBFS_Dp__LCD_EN EQU CYREG_PRT15_LCD_EN\r
+USBFS_Dp__MASK EQU 0x40\r
+USBFS_Dp__PORT EQU 15\r
+USBFS_Dp__PRT EQU CYREG_PRT15_PRT\r
+USBFS_Dp__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL\r
+USBFS_Dp__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN\r
+USBFS_Dp__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0\r
+USBFS_Dp__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1\r
+USBFS_Dp__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0\r
+USBFS_Dp__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1\r
+USBFS_Dp__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT\r
+USBFS_Dp__PS EQU CYREG_PRT15_PS\r
+USBFS_Dp__SHIFT EQU 6\r
+USBFS_Dp__SLW EQU CYREG_PRT15_SLW\r
+USBFS_Dp__SNAP EQU CYREG_PICU_15_SNAP_15\r
+USBFS_dp_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
+USBFS_dp_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
+USBFS_dp_int__INTC_MASK EQU 0x1000\r
+USBFS_dp_int__INTC_NUMBER EQU 12\r
+USBFS_dp_int__INTC_PRIOR_NUM EQU 7\r
+USBFS_dp_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_12\r
+USBFS_dp_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
+USBFS_dp_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
+USBFS_ep_0__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
+USBFS_ep_0__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
+USBFS_ep_0__INTC_MASK EQU 0x1000000\r
+USBFS_ep_0__INTC_NUMBER EQU 24\r
+USBFS_ep_0__INTC_PRIOR_NUM EQU 7\r
+USBFS_ep_0__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_24\r
+USBFS_ep_0__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
+USBFS_ep_0__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
+USBFS_ep_1__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
+USBFS_ep_1__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
+USBFS_ep_1__INTC_MASK EQU 0x80\r
+USBFS_ep_1__INTC_NUMBER EQU 7\r
+USBFS_ep_1__INTC_PRIOR_NUM EQU 7\r
+USBFS_ep_1__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_7\r
+USBFS_ep_1__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
+USBFS_ep_1__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
+USBFS_ep_2__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
+USBFS_ep_2__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
+USBFS_ep_2__INTC_MASK EQU 0x100\r
+USBFS_ep_2__INTC_NUMBER EQU 8\r
+USBFS_ep_2__INTC_PRIOR_NUM EQU 7\r
+USBFS_ep_2__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_8\r
+USBFS_ep_2__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
+USBFS_ep_2__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
+USBFS_ep_3__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
+USBFS_ep_3__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
+USBFS_ep_3__INTC_MASK EQU 0x200\r
+USBFS_ep_3__INTC_NUMBER EQU 9\r
+USBFS_ep_3__INTC_PRIOR_NUM EQU 7\r
+USBFS_ep_3__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_9\r
+USBFS_ep_3__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
+USBFS_ep_3__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
+USBFS_ep_4__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
+USBFS_ep_4__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
+USBFS_ep_4__INTC_MASK EQU 0x400\r
+USBFS_ep_4__INTC_NUMBER EQU 10\r
+USBFS_ep_4__INTC_PRIOR_NUM EQU 7\r
+USBFS_ep_4__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_10\r
+USBFS_ep_4__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
+USBFS_ep_4__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
+USBFS_sof_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
+USBFS_sof_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
+USBFS_sof_int__INTC_MASK EQU 0x200000\r
+USBFS_sof_int__INTC_NUMBER EQU 21\r
+USBFS_sof_int__INTC_PRIOR_NUM EQU 7\r
+USBFS_sof_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_21\r
+USBFS_sof_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
+USBFS_sof_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
+USBFS_USB__ARB_CFG EQU CYREG_USB_ARB_CFG\r
+USBFS_USB__ARB_EP1_CFG EQU CYREG_USB_ARB_EP1_CFG\r
+USBFS_USB__ARB_EP1_INT_EN EQU CYREG_USB_ARB_EP1_INT_EN\r
+USBFS_USB__ARB_EP1_SR EQU CYREG_USB_ARB_EP1_SR\r
+USBFS_USB__ARB_EP2_CFG EQU CYREG_USB_ARB_EP2_CFG\r
+USBFS_USB__ARB_EP2_INT_EN EQU CYREG_USB_ARB_EP2_INT_EN\r
+USBFS_USB__ARB_EP2_SR EQU CYREG_USB_ARB_EP2_SR\r
+USBFS_USB__ARB_EP3_CFG EQU CYREG_USB_ARB_EP3_CFG\r
+USBFS_USB__ARB_EP3_INT_EN EQU CYREG_USB_ARB_EP3_INT_EN\r
+USBFS_USB__ARB_EP3_SR EQU CYREG_USB_ARB_EP3_SR\r
+USBFS_USB__ARB_EP4_CFG EQU CYREG_USB_ARB_EP4_CFG\r
+USBFS_USB__ARB_EP4_INT_EN EQU CYREG_USB_ARB_EP4_INT_EN\r
+USBFS_USB__ARB_EP4_SR EQU CYREG_USB_ARB_EP4_SR\r
+USBFS_USB__ARB_EP5_CFG EQU CYREG_USB_ARB_EP5_CFG\r
+USBFS_USB__ARB_EP5_INT_EN EQU CYREG_USB_ARB_EP5_INT_EN\r
+USBFS_USB__ARB_EP5_SR EQU CYREG_USB_ARB_EP5_SR\r
+USBFS_USB__ARB_EP6_CFG EQU CYREG_USB_ARB_EP6_CFG\r
+USBFS_USB__ARB_EP6_INT_EN EQU CYREG_USB_ARB_EP6_INT_EN\r
+USBFS_USB__ARB_EP6_SR EQU CYREG_USB_ARB_EP6_SR\r
+USBFS_USB__ARB_EP7_CFG EQU CYREG_USB_ARB_EP7_CFG\r
+USBFS_USB__ARB_EP7_INT_EN EQU CYREG_USB_ARB_EP7_INT_EN\r
+USBFS_USB__ARB_EP7_SR EQU CYREG_USB_ARB_EP7_SR\r
+USBFS_USB__ARB_EP8_CFG EQU CYREG_USB_ARB_EP8_CFG\r
+USBFS_USB__ARB_EP8_INT_EN EQU CYREG_USB_ARB_EP8_INT_EN\r
+USBFS_USB__ARB_EP8_SR EQU CYREG_USB_ARB_EP8_SR\r
+USBFS_USB__ARB_INT_EN EQU CYREG_USB_ARB_INT_EN\r
+USBFS_USB__ARB_INT_SR EQU CYREG_USB_ARB_INT_SR\r
+USBFS_USB__ARB_RW1_DR EQU CYREG_USB_ARB_RW1_DR\r
+USBFS_USB__ARB_RW1_RA EQU CYREG_USB_ARB_RW1_RA\r
+USBFS_USB__ARB_RW1_RA_MSB EQU CYREG_USB_ARB_RW1_RA_MSB\r
+USBFS_USB__ARB_RW1_WA EQU CYREG_USB_ARB_RW1_WA\r
+USBFS_USB__ARB_RW1_WA_MSB EQU CYREG_USB_ARB_RW1_WA_MSB\r
+USBFS_USB__ARB_RW2_DR EQU CYREG_USB_ARB_RW2_DR\r
+USBFS_USB__ARB_RW2_RA EQU CYREG_USB_ARB_RW2_RA\r
+USBFS_USB__ARB_RW2_RA_MSB EQU CYREG_USB_ARB_RW2_RA_MSB\r
+USBFS_USB__ARB_RW2_WA EQU CYREG_USB_ARB_RW2_WA\r
+USBFS_USB__ARB_RW2_WA_MSB EQU CYREG_USB_ARB_RW2_WA_MSB\r
+USBFS_USB__ARB_RW3_DR EQU CYREG_USB_ARB_RW3_DR\r
+USBFS_USB__ARB_RW3_RA EQU CYREG_USB_ARB_RW3_RA\r
+USBFS_USB__ARB_RW3_RA_MSB EQU CYREG_USB_ARB_RW3_RA_MSB\r
+USBFS_USB__ARB_RW3_WA EQU CYREG_USB_ARB_RW3_WA\r
+USBFS_USB__ARB_RW3_WA_MSB EQU CYREG_USB_ARB_RW3_WA_MSB\r
+USBFS_USB__ARB_RW4_DR EQU CYREG_USB_ARB_RW4_DR\r
+USBFS_USB__ARB_RW4_RA EQU CYREG_USB_ARB_RW4_RA\r
+USBFS_USB__ARB_RW4_RA_MSB EQU CYREG_USB_ARB_RW4_RA_MSB\r
+USBFS_USB__ARB_RW4_WA EQU CYREG_USB_ARB_RW4_WA\r
+USBFS_USB__ARB_RW4_WA_MSB EQU CYREG_USB_ARB_RW4_WA_MSB\r
+USBFS_USB__ARB_RW5_DR EQU CYREG_USB_ARB_RW5_DR\r
+USBFS_USB__ARB_RW5_RA EQU CYREG_USB_ARB_RW5_RA\r
+USBFS_USB__ARB_RW5_RA_MSB EQU CYREG_USB_ARB_RW5_RA_MSB\r
+USBFS_USB__ARB_RW5_WA EQU CYREG_USB_ARB_RW5_WA\r
+USBFS_USB__ARB_RW5_WA_MSB EQU CYREG_USB_ARB_RW5_WA_MSB\r
+USBFS_USB__ARB_RW6_DR EQU CYREG_USB_ARB_RW6_DR\r
+USBFS_USB__ARB_RW6_RA EQU CYREG_USB_ARB_RW6_RA\r
+USBFS_USB__ARB_RW6_RA_MSB EQU CYREG_USB_ARB_RW6_RA_MSB\r
+USBFS_USB__ARB_RW6_WA EQU CYREG_USB_ARB_RW6_WA\r
+USBFS_USB__ARB_RW6_WA_MSB EQU CYREG_USB_ARB_RW6_WA_MSB\r
+USBFS_USB__ARB_RW7_DR EQU CYREG_USB_ARB_RW7_DR\r
+USBFS_USB__ARB_RW7_RA EQU CYREG_USB_ARB_RW7_RA\r
+USBFS_USB__ARB_RW7_RA_MSB EQU CYREG_USB_ARB_RW7_RA_MSB\r
+USBFS_USB__ARB_RW7_WA EQU CYREG_USB_ARB_RW7_WA\r
+USBFS_USB__ARB_RW7_WA_MSB EQU CYREG_USB_ARB_RW7_WA_MSB\r
+USBFS_USB__ARB_RW8_DR EQU CYREG_USB_ARB_RW8_DR\r
+USBFS_USB__ARB_RW8_RA EQU CYREG_USB_ARB_RW8_RA\r
+USBFS_USB__ARB_RW8_RA_MSB EQU CYREG_USB_ARB_RW8_RA_MSB\r
+USBFS_USB__ARB_RW8_WA EQU CYREG_USB_ARB_RW8_WA\r
+USBFS_USB__ARB_RW8_WA_MSB EQU CYREG_USB_ARB_RW8_WA_MSB\r
+USBFS_USB__BUF_SIZE EQU CYREG_USB_BUF_SIZE\r
+USBFS_USB__BUS_RST_CNT EQU CYREG_USB_BUS_RST_CNT\r
+USBFS_USB__CR0 EQU CYREG_USB_CR0\r
+USBFS_USB__CR1 EQU CYREG_USB_CR1\r
+USBFS_USB__CWA EQU CYREG_USB_CWA\r
+USBFS_USB__CWA_MSB EQU CYREG_USB_CWA_MSB\r
+USBFS_USB__DMA_THRES EQU CYREG_USB_DMA_THRES\r
+USBFS_USB__DMA_THRES_MSB EQU CYREG_USB_DMA_THRES_MSB\r
+USBFS_USB__DYN_RECONFIG EQU CYREG_USB_DYN_RECONFIG\r
+USBFS_USB__EP_ACTIVE EQU CYREG_USB_EP_ACTIVE\r
+USBFS_USB__EP_TYPE EQU CYREG_USB_EP_TYPE\r
+USBFS_USB__EP0_CNT EQU CYREG_USB_EP0_CNT\r
+USBFS_USB__EP0_CR EQU CYREG_USB_EP0_CR\r
+USBFS_USB__EP0_DR0 EQU CYREG_USB_EP0_DR0\r
+USBFS_USB__EP0_DR1 EQU CYREG_USB_EP0_DR1\r
+USBFS_USB__EP0_DR2 EQU CYREG_USB_EP0_DR2\r
+USBFS_USB__EP0_DR3 EQU CYREG_USB_EP0_DR3\r
+USBFS_USB__EP0_DR4 EQU CYREG_USB_EP0_DR4\r
+USBFS_USB__EP0_DR5 EQU CYREG_USB_EP0_DR5\r
+USBFS_USB__EP0_DR6 EQU CYREG_USB_EP0_DR6\r
+USBFS_USB__EP0_DR7 EQU CYREG_USB_EP0_DR7\r
+USBFS_USB__MEM_DATA EQU CYREG_USB_MEM_DATA_MBASE\r
+USBFS_USB__PM_ACT_CFG EQU CYREG_PM_ACT_CFG5\r
+USBFS_USB__PM_ACT_MSK EQU 0x01\r
+USBFS_USB__PM_STBY_CFG EQU CYREG_PM_STBY_CFG5\r
+USBFS_USB__PM_STBY_MSK EQU 0x01\r
+USBFS_USB__SIE_EP_INT_EN EQU CYREG_USB_SIE_EP_INT_EN\r
+USBFS_USB__SIE_EP_INT_SR EQU CYREG_USB_SIE_EP_INT_SR\r
+USBFS_USB__SIE_EP1_CNT0 EQU CYREG_USB_SIE_EP1_CNT0\r
+USBFS_USB__SIE_EP1_CNT1 EQU CYREG_USB_SIE_EP1_CNT1\r
+USBFS_USB__SIE_EP1_CR0 EQU CYREG_USB_SIE_EP1_CR0\r
+USBFS_USB__SIE_EP2_CNT0 EQU CYREG_USB_SIE_EP2_CNT0\r
+USBFS_USB__SIE_EP2_CNT1 EQU CYREG_USB_SIE_EP2_CNT1\r
+USBFS_USB__SIE_EP2_CR0 EQU CYREG_USB_SIE_EP2_CR0\r
+USBFS_USB__SIE_EP3_CNT0 EQU CYREG_USB_SIE_EP3_CNT0\r
+USBFS_USB__SIE_EP3_CNT1 EQU CYREG_USB_SIE_EP3_CNT1\r
+USBFS_USB__SIE_EP3_CR0 EQU CYREG_USB_SIE_EP3_CR0\r
+USBFS_USB__SIE_EP4_CNT0 EQU CYREG_USB_SIE_EP4_CNT0\r
+USBFS_USB__SIE_EP4_CNT1 EQU CYREG_USB_SIE_EP4_CNT1\r
+USBFS_USB__SIE_EP4_CR0 EQU CYREG_USB_SIE_EP4_CR0\r
+USBFS_USB__SIE_EP5_CNT0 EQU CYREG_USB_SIE_EP5_CNT0\r
+USBFS_USB__SIE_EP5_CNT1 EQU CYREG_USB_SIE_EP5_CNT1\r
+USBFS_USB__SIE_EP5_CR0 EQU CYREG_USB_SIE_EP5_CR0\r
+USBFS_USB__SIE_EP6_CNT0 EQU CYREG_USB_SIE_EP6_CNT0\r
+USBFS_USB__SIE_EP6_CNT1 EQU CYREG_USB_SIE_EP6_CNT1\r
+USBFS_USB__SIE_EP6_CR0 EQU CYREG_USB_SIE_EP6_CR0\r
+USBFS_USB__SIE_EP7_CNT0 EQU CYREG_USB_SIE_EP7_CNT0\r
+USBFS_USB__SIE_EP7_CNT1 EQU CYREG_USB_SIE_EP7_CNT1\r
+USBFS_USB__SIE_EP7_CR0 EQU CYREG_USB_SIE_EP7_CR0\r
+USBFS_USB__SIE_EP8_CNT0 EQU CYREG_USB_SIE_EP8_CNT0\r
+USBFS_USB__SIE_EP8_CNT1 EQU CYREG_USB_SIE_EP8_CNT1\r
+USBFS_USB__SIE_EP8_CR0 EQU CYREG_USB_SIE_EP8_CR0\r
+USBFS_USB__SOF0 EQU CYREG_USB_SOF0\r
+USBFS_USB__SOF1 EQU CYREG_USB_SOF1\r
+USBFS_USB__USB_CLK_EN EQU CYREG_USB_USB_CLK_EN\r
+USBFS_USB__USBIO_CR0 EQU CYREG_USB_USBIO_CR0\r
+USBFS_USB__USBIO_CR1 EQU CYREG_USB_USBIO_CR1\r
+\r
 ; scsiTarget\r
 scsiTarget_datapath__16BIT_A0_REG EQU CYREG_B0_UDB00_01_A0\r
 scsiTarget_datapath__16BIT_A1_REG EQU CYREG_B0_UDB00_01_A1\r
@@ -2841,89 +2997,6 @@ scsiTarget_StatusReg__STATUS_CNT_REG EQU CYREG_B0_UDB07_ST_CTL
 scsiTarget_StatusReg__STATUS_CONTROL_REG EQU CYREG_B0_UDB07_ST_CTL\r
 scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB07_ST\r
 \r
-; Debug_Timer_Interrupt\r
-Debug_Timer_Interrupt__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
-Debug_Timer_Interrupt__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
-Debug_Timer_Interrupt__INTC_MASK EQU 0x02\r
-Debug_Timer_Interrupt__INTC_NUMBER EQU 1\r
-Debug_Timer_Interrupt__INTC_PRIOR_NUM EQU 7\r
-Debug_Timer_Interrupt__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_1\r
-Debug_Timer_Interrupt__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
-Debug_Timer_Interrupt__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
-\r
-; Debug_Timer_TimerHW\r
-Debug_Timer_TimerHW__CAP0 EQU CYREG_TMR0_CAP0\r
-Debug_Timer_TimerHW__CAP1 EQU CYREG_TMR0_CAP1\r
-Debug_Timer_TimerHW__CFG0 EQU CYREG_TMR0_CFG0\r
-Debug_Timer_TimerHW__CFG1 EQU CYREG_TMR0_CFG1\r
-Debug_Timer_TimerHW__CFG2 EQU CYREG_TMR0_CFG2\r
-Debug_Timer_TimerHW__CNT_CMP0 EQU CYREG_TMR0_CNT_CMP0\r
-Debug_Timer_TimerHW__CNT_CMP1 EQU CYREG_TMR0_CNT_CMP1\r
-Debug_Timer_TimerHW__PER0 EQU CYREG_TMR0_PER0\r
-Debug_Timer_TimerHW__PER1 EQU CYREG_TMR0_PER1\r
-Debug_Timer_TimerHW__PM_ACT_CFG EQU CYREG_PM_ACT_CFG3\r
-Debug_Timer_TimerHW__PM_ACT_MSK EQU 0x01\r
-Debug_Timer_TimerHW__PM_STBY_CFG EQU CYREG_PM_STBY_CFG3\r
-Debug_Timer_TimerHW__PM_STBY_MSK EQU 0x01\r
-Debug_Timer_TimerHW__RT0 EQU CYREG_TMR0_RT0\r
-Debug_Timer_TimerHW__RT1 EQU CYREG_TMR0_RT1\r
-Debug_Timer_TimerHW__SR0 EQU CYREG_TMR0_SR0\r
-\r
-; SCSI_RX_DMA\r
-SCSI_RX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0\r
-SCSI_RX_DMA__DRQ_NUMBER EQU 0\r
-SCSI_RX_DMA__NUMBEROF_TDS EQU 0\r
-SCSI_RX_DMA__PRIORITY EQU 2\r
-SCSI_RX_DMA__TERMIN_EN EQU 0\r
-SCSI_RX_DMA__TERMIN_SEL EQU 0\r
-SCSI_RX_DMA__TERMOUT0_EN EQU 1\r
-SCSI_RX_DMA__TERMOUT0_SEL EQU 0\r
-SCSI_RX_DMA__TERMOUT1_EN EQU 0\r
-SCSI_RX_DMA__TERMOUT1_SEL EQU 0\r
-\r
-; SCSI_RX_DMA_COMPLETE\r
-SCSI_RX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
-SCSI_RX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
-SCSI_RX_DMA_COMPLETE__INTC_MASK EQU 0x01\r
-SCSI_RX_DMA_COMPLETE__INTC_NUMBER EQU 0\r
-SCSI_RX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7\r
-SCSI_RX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_0\r
-SCSI_RX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
-SCSI_RX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
-\r
-; SCSI_TX_DMA\r
-SCSI_TX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0\r
-SCSI_TX_DMA__DRQ_NUMBER EQU 1\r
-SCSI_TX_DMA__NUMBEROF_TDS EQU 0\r
-SCSI_TX_DMA__PRIORITY EQU 2\r
-SCSI_TX_DMA__TERMIN_EN EQU 0\r
-SCSI_TX_DMA__TERMIN_SEL EQU 0\r
-SCSI_TX_DMA__TERMOUT0_EN EQU 1\r
-SCSI_TX_DMA__TERMOUT0_SEL EQU 1\r
-SCSI_TX_DMA__TERMOUT1_EN EQU 0\r
-SCSI_TX_DMA__TERMOUT1_SEL EQU 0\r
-\r
-; SCSI_TX_DMA_COMPLETE\r
-SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
-SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
-SCSI_TX_DMA_COMPLETE__INTC_MASK EQU 0x10\r
-SCSI_TX_DMA_COMPLETE__INTC_NUMBER EQU 4\r
-SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7\r
-SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_4\r
-SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
-SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
-\r
-; SD_Data_Clk\r
-SD_Data_Clk__CFG0 EQU CYREG_CLKDIST_DCFG0_CFG0\r
-SD_Data_Clk__CFG1 EQU CYREG_CLKDIST_DCFG0_CFG1\r
-SD_Data_Clk__CFG2 EQU CYREG_CLKDIST_DCFG0_CFG2\r
-SD_Data_Clk__CFG2_SRC_SEL_MASK EQU 0x07\r
-SD_Data_Clk__INDEX EQU 0x00\r
-SD_Data_Clk__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2\r
-SD_Data_Clk__PM_ACT_MSK EQU 0x01\r
-SD_Data_Clk__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2\r
-SD_Data_Clk__PM_STBY_MSK EQU 0x01\r
-\r
 ; timer_clock\r
 timer_clock__CFG0 EQU CYREG_CLKDIST_DCFG2_CFG0\r
 timer_clock__CFG1 EQU CYREG_CLKDIST_DCFG2_CFG1\r
@@ -2935,146 +3008,53 @@ timer_clock__PM_ACT_MSK EQU 0x04
 timer_clock__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2\r
 timer_clock__PM_STBY_MSK EQU 0x04\r
 \r
-; SCSI_RST_ISR\r
-SCSI_RST_ISR__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
-SCSI_RST_ISR__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
-SCSI_RST_ISR__INTC_MASK EQU 0x04\r
-SCSI_RST_ISR__INTC_NUMBER EQU 2\r
-SCSI_RST_ISR__INTC_PRIOR_NUM EQU 7\r
-SCSI_RST_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_2\r
-SCSI_RST_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
-SCSI_RST_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
-\r
-; SCSI_SEL_ISR\r
-SCSI_SEL_ISR__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
-SCSI_SEL_ISR__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
-SCSI_SEL_ISR__INTC_MASK EQU 0x08\r
-SCSI_SEL_ISR__INTC_NUMBER EQU 3\r
-SCSI_SEL_ISR__INTC_PRIOR_NUM EQU 7\r
-SCSI_SEL_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_3\r
-SCSI_SEL_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
-SCSI_SEL_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
-\r
-; SCSI_Filtered\r
-SCSI_Filtered_sts_sts_reg__0__MASK EQU 0x01\r
-SCSI_Filtered_sts_sts_reg__0__POS EQU 0\r
-SCSI_Filtered_sts_sts_reg__1__MASK EQU 0x02\r
-SCSI_Filtered_sts_sts_reg__1__POS EQU 1\r
-SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL\r
-SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB02_03_ST\r
-SCSI_Filtered_sts_sts_reg__2__MASK EQU 0x04\r
-SCSI_Filtered_sts_sts_reg__2__POS EQU 2\r
-SCSI_Filtered_sts_sts_reg__3__MASK EQU 0x08\r
-SCSI_Filtered_sts_sts_reg__3__POS EQU 3\r
-SCSI_Filtered_sts_sts_reg__4__MASK EQU 0x10\r
-SCSI_Filtered_sts_sts_reg__4__POS EQU 4\r
-SCSI_Filtered_sts_sts_reg__MASK EQU 0x1F\r
-SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB02_MSK\r
-SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL\r
-SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB02_ST\r
-\r
-; SCSI_CTL_PHASE\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS EQU 0\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK EQU 0x02\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS EQU 1\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB05_06_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB05_06_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB05_06_MSK\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB05_06_MSK\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK EQU 0x04\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS EQU 2\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB05_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB05_ST_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB05_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB05_ST_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__MASK EQU 0x07\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB05_MSK\r
-\r
-; SCSI_Glitch_Ctl\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS EQU 0\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB07_08_CTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB07_08_CTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB07_08_CTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB07_08_CTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB07_08_MSK\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB07_08_MSK\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB07_08_MSK\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB07_08_MSK\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB07_CTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB07_ST_CTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB07_CTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB07_ST_CTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK EQU 0x01\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB07_MSK\r
-\r
-; SCSI_Parity_Error\r
-SCSI_Parity_Error_sts_sts_reg__0__MASK EQU 0x01\r
-SCSI_Parity_Error_sts_sts_reg__0__POS EQU 0\r
-SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB01_02_ACTL\r
-SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB01_02_ST\r
-SCSI_Parity_Error_sts_sts_reg__MASK EQU 0x01\r
-SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB01_MSK\r
-SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB01_ACTL\r
-SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB01_ST\r
-\r
 ; Miscellaneous\r
 BCLK__BUS_CLK__HZ EQU 50000000\r
 BCLK__BUS_CLK__KHZ EQU 50000\r
 BCLK__BUS_CLK__MHZ EQU 50\r
 CYDEV_CHIP_DIE_LEOPARD EQU 1\r
-CYDEV_CHIP_DIE_PSOC4A EQU 12\r
-CYDEV_CHIP_DIE_PSOC5LP EQU 19\r
-CYDEV_CHIP_DIE_PSOC5TM EQU 20\r
-CYDEV_CHIP_DIE_TMA4 EQU 2\r
+CYDEV_CHIP_DIE_PSOC4A EQU 16\r
+CYDEV_CHIP_DIE_PSOC5LP EQU 2\r
+CYDEV_CHIP_DIE_PSOC5TM EQU 3\r
+CYDEV_CHIP_DIE_TMA4 EQU 4\r
 CYDEV_CHIP_DIE_UNKNOWN EQU 0\r
-CYDEV_CHIP_FAMILY_FM0P EQU 4\r
-CYDEV_CHIP_FAMILY_FM3 EQU 5\r
-CYDEV_CHIP_FAMILY_FM4 EQU 6\r
+CYDEV_CHIP_FAMILY_FM0P EQU 5\r
+CYDEV_CHIP_FAMILY_FM3 EQU 6\r
+CYDEV_CHIP_FAMILY_FM4 EQU 7\r
 CYDEV_CHIP_FAMILY_PSOC3 EQU 1\r
 CYDEV_CHIP_FAMILY_PSOC4 EQU 2\r
 CYDEV_CHIP_FAMILY_PSOC5 EQU 3\r
+CYDEV_CHIP_FAMILY_PSOC6 EQU 4\r
 CYDEV_CHIP_FAMILY_UNKNOWN EQU 0\r
 CYDEV_CHIP_FAMILY_USED EQU CYDEV_CHIP_FAMILY_PSOC5\r
 CYDEV_CHIP_JTAG_ID EQU 0x2E133069\r
 CYDEV_CHIP_MEMBER_3A EQU 1\r
-CYDEV_CHIP_MEMBER_4A EQU 12\r
-CYDEV_CHIP_MEMBER_4C EQU 18\r
-CYDEV_CHIP_MEMBER_4D EQU 8\r
-CYDEV_CHIP_MEMBER_4E EQU 4\r
-CYDEV_CHIP_MEMBER_4F EQU 13\r
-CYDEV_CHIP_MEMBER_4G EQU 2\r
-CYDEV_CHIP_MEMBER_4H EQU 11\r
-CYDEV_CHIP_MEMBER_4I EQU 17\r
-CYDEV_CHIP_MEMBER_4J EQU 9\r
-CYDEV_CHIP_MEMBER_4K EQU 10\r
-CYDEV_CHIP_MEMBER_4L EQU 16\r
-CYDEV_CHIP_MEMBER_4M EQU 15\r
-CYDEV_CHIP_MEMBER_4N EQU 6\r
-CYDEV_CHIP_MEMBER_4O EQU 5\r
-CYDEV_CHIP_MEMBER_4P EQU 14\r
-CYDEV_CHIP_MEMBER_4Q EQU 7\r
-CYDEV_CHIP_MEMBER_4U EQU 3\r
-CYDEV_CHIP_MEMBER_5A EQU 20\r
-CYDEV_CHIP_MEMBER_5B EQU 19\r
-CYDEV_CHIP_MEMBER_FM3 EQU 24\r
-CYDEV_CHIP_MEMBER_FM4 EQU 25\r
-CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE1 EQU 21\r
-CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE2 EQU 22\r
-CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE3 EQU 23\r
+CYDEV_CHIP_MEMBER_4A EQU 16\r
+CYDEV_CHIP_MEMBER_4D EQU 12\r
+CYDEV_CHIP_MEMBER_4E EQU 6\r
+CYDEV_CHIP_MEMBER_4F EQU 17\r
+CYDEV_CHIP_MEMBER_4G EQU 4\r
+CYDEV_CHIP_MEMBER_4H EQU 15\r
+CYDEV_CHIP_MEMBER_4I EQU 21\r
+CYDEV_CHIP_MEMBER_4J EQU 13\r
+CYDEV_CHIP_MEMBER_4K EQU 14\r
+CYDEV_CHIP_MEMBER_4L EQU 20\r
+CYDEV_CHIP_MEMBER_4M EQU 19\r
+CYDEV_CHIP_MEMBER_4N EQU 9\r
+CYDEV_CHIP_MEMBER_4O EQU 7\r
+CYDEV_CHIP_MEMBER_4P EQU 18\r
+CYDEV_CHIP_MEMBER_4Q EQU 11\r
+CYDEV_CHIP_MEMBER_4R EQU 8\r
+CYDEV_CHIP_MEMBER_4S EQU 10\r
+CYDEV_CHIP_MEMBER_4U EQU 5\r
+CYDEV_CHIP_MEMBER_5A EQU 3\r
+CYDEV_CHIP_MEMBER_5B EQU 2\r
+CYDEV_CHIP_MEMBER_6A EQU 22\r
+CYDEV_CHIP_MEMBER_FM3 EQU 26\r
+CYDEV_CHIP_MEMBER_FM4 EQU 27\r
+CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE1 EQU 23\r
+CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE2 EQU 24\r
+CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE3 EQU 25\r
 CYDEV_CHIP_MEMBER_UNKNOWN EQU 0\r
 CYDEV_CHIP_MEMBER_USED EQU CYDEV_CHIP_MEMBER_5B\r
 CYDEV_CHIP_DIE_EXPECT EQU CYDEV_CHIP_MEMBER_USED\r
@@ -3099,7 +3079,6 @@ CYDEV_CHIP_REVISION_3A_ES3 EQU 3
 CYDEV_CHIP_REVISION_3A_PRODUCTION EQU 3\r
 CYDEV_CHIP_REVISION_4A_ES0 EQU 17\r
 CYDEV_CHIP_REVISION_4A_PRODUCTION EQU 17\r
-CYDEV_CHIP_REVISION_4C_PRODUCTION EQU 0\r
 CYDEV_CHIP_REVISION_4D_PRODUCTION EQU 0\r
 CYDEV_CHIP_REVISION_4E_PRODUCTION EQU 0\r
 CYDEV_CHIP_REVISION_4F_PRODUCTION EQU 0\r
@@ -3118,12 +3097,16 @@ CYDEV_CHIP_REVISION_4N_PRODUCTION EQU 0
 CYDEV_CHIP_REVISION_4O_PRODUCTION EQU 0\r
 CYDEV_CHIP_REVISION_4P_PRODUCTION EQU 0\r
 CYDEV_CHIP_REVISION_4Q_PRODUCTION EQU 0\r
+CYDEV_CHIP_REVISION_4R_PRODUCTION EQU 0\r
+CYDEV_CHIP_REVISION_4S_PRODUCTION EQU 0\r
 CYDEV_CHIP_REVISION_4U_PRODUCTION EQU 0\r
 CYDEV_CHIP_REVISION_5A_ES0 EQU 0\r
 CYDEV_CHIP_REVISION_5A_ES1 EQU 1\r
 CYDEV_CHIP_REVISION_5A_PRODUCTION EQU 1\r
 CYDEV_CHIP_REVISION_5B_ES0 EQU 0\r
 CYDEV_CHIP_REVISION_5B_PRODUCTION EQU 0\r
+CYDEV_CHIP_REVISION_6A_NO_UDB EQU 0\r
+CYDEV_CHIP_REVISION_6A_PRODUCTION EQU 0\r
 CYDEV_CHIP_REVISION_FM3_PRODUCTION EQU 0\r
 CYDEV_CHIP_REVISION_FM4_PRODUCTION EQU 0\r
 CYDEV_CHIP_REVISION_PDL_FM0P_TYPE1_PRODUCTION EQU 0\r
@@ -3155,7 +3138,7 @@ CYDEV_DMA_CHANNELS_AVAILABLE EQU 24
 CYDEV_ECC_ENABLE EQU 0\r
 CYDEV_HEAP_SIZE EQU 0x0400\r
 CYDEV_INSTRUCT_CACHE_ENABLED EQU 1\r
-CYDEV_INTR_RISING EQU 0x0000007E\r
+CYDEV_INTR_RISING EQU 0x0000007F\r
 CYDEV_IS_EXPORTING_CODE EQU 0\r
 CYDEV_IS_IMPORTING_CODE EQU 0\r
 CYDEV_PROJ_TYPE EQU 2\r

diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cymetadata.c b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cymetadata.c
index 8638ffbb4537e60745ae3609052c798a45935a74..e8e92b1cf9a07ac2bbd7af856de309ca9a17ed7d 100755 (executable)
--- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cymetadata.c
+++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cymetadata.c
@@ -1,21 +1,21 @@
 /*******************************************************************************\r
 * File Name: cymetadata.c\r
 * \r
-* PSoC Creator  4.0 Update 1\r
+* PSoC Creator  4.1\r
 *\r
 * Description:\r
 * This file defines all extra memory spaces that need to be included.\r
 * This file is automatically generated by PSoC Creator.\r
 *\r
 ********************************************************************************\r
-* Copyright (c) 2007-2016 Cypress Semiconductor.  All rights reserved.\r
+* Copyright (c) 2007-2017 Cypress Semiconductor.  All rights reserved.\r
 * You may use this file only in accordance with the license, terms, conditions, \r
 * disclaimers, and limitations in the end user license agreement accompanying \r
 * the software package with which this file was provided.\r
 ********************************************************************************/\r
 \r
 \r
-#include "cytypes.h"\r
+#include "stdint.h"\r
 \r
 \r
 #if defined(__GNUC__) || defined(__ARMCC_VERSION)\r
@@ -28,7 +28,7 @@ CY_LOADABLE_META_SECTION
 #else\r
 #error "Unsupported toolchain"\r
 #endif\r
-const uint8 cy_meta_loadable[] = {\r
+const uint8_t cy_meta_loadable[] = {\r
     0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,\r
     0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,\r
     0x00u, 0x00u, 0x00u, 0x00u, 0x5Cu, 0xD1u, 0x71u, 0x04u,\r
@@ -49,6 +49,6 @@ CY_CONFIG_ECC_SECTION
 #else\r
 #error "Unsupported toolchain"\r
 #endif\r
-const uint8 cy_meta_configecc[] = {\r
+const uint8_t cy_meta_configecc[] = {\r
     0x00u\r
 };\r

diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/project.h b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/project.h
index 83e11bd057f4f42b70b1ed91a8f3abaa8354059c..a6cfaf8daba388f9d1751c5f7236f64c4b4b7866 100755 (executable)
--- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/project.h
+++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/project.h
@@ -1,14 +1,14 @@
 /*******************************************************************************\r
 * File Name: project.h\r
 * \r
-* PSoC Creator  4.0 Update 1\r
+* PSoC Creator  4.1\r
 *\r
 * Description:\r
 * It contains references to all generated header files and should not be modified.\r
 * This file is automatically generated by PSoC Creator.\r
 *\r
 ********************************************************************************\r
-* Copyright (c) 2007-2016 Cypress Semiconductor.  All rights reserved.\r
+* Copyright (c) 2007-2017 Cypress Semiconductor.  All rights reserved.\r
 * You may use this file only in accordance with the license, terms, conditions, \r
 * disclaimers, and limitations in the end user license agreement accompanying \r
 * the software package with which this file was provided.\r

diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.cyfit b/software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.cyfit
index ef48244c929214aede55691e478ebcc3cee8ca52..c8b3326a1ee1cf5b6f77d9753074a2941d99b07c 100644 (file)
Binary files a/software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.cyfit and b/software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.cyfit differ

diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.cyprj b/software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.cyprj
index a6877f0d29e3337f77257892eaec00b243fe36a3..82af2105d2c7559cf7b43b675311d6086cd9ad83 100755 (executable)
--- a/software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.cyprj
+++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.cyprj
@@ -4,14 +4,14 @@
 <!--Due to this, there is no schema for this file.-->\r
 <CyGuid_fec8f9e8-2365-4bdb-96d3-a4380222e01b type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtProjectPSoCExeSerialize" version="4">\r
 <CyGuid_60697ce6-dce2-4816-8680-4de0635742eb type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtProjectExeSerialize" version="3">\r
-<CyGuid_49cfd574-032a-4a64-b7be-d4eeeaf25e43 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtProjectSerialize" version="7" xml_contents_version="1">\r
+<CyGuid_49cfd574-032a-4a64-b7be-d4eeeaf25e43 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtProjectSerialize" version="8" xml_contents_version="1">\r
 <CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtBaseContainerSerialize" version="1">\r
 <CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItemSerialize" version="2" name="SCSI2SD" persistent="SCSI2SD.cyprj">\r
 <Hidden v="False" />\r
 </CyGuid_31768f72-0253-412b-af77-e7dba74d1330>\r
 <CyGuid_0820c2e7-528d-4137-9a08-97257b946089 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItemListSerialize" version="2">\r
 <dependencies>\r
-<CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFolderSerialize" version="2">\r
+<CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFolderSerialize" version="3">\r
 <CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtBaseContainerSerialize" version="1">\r
 <CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItemSerialize" version="2" name="Source Files" persistent="">\r
 <Hidden v="False" />\r
@@ -161,7 +161,7 @@
 <filter v="a51" />\r
 </filters>\r
 </CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0>\r
-<CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFolderSerialize" version="2">\r
+<CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFolderSerialize" version="3">\r
 <CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtBaseContainerSerialize" version="1">\r
 <CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItemSerialize" version="2" name="Header Files" persistent="">\r
 <Hidden v="False" />\r
@@ -331,7 +331,7 @@
 </CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0>\r
 <CyGuid_4429d4ed-fe84-42d0-9e9f-19aee0ff4e7e type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtComponentSerialize" version="1">\r
 <CyGuid_813b8d13-518a-4dc8-91ba-cda6042dfb52 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtPhysicalFolderSerialize" version="1">\r
-<CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFolderSerialize" version="2">\r
+<CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFolderSerialize" version="3">\r
 <CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtBaseContainerSerialize" version="1">\r
 <CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItemSerialize" version="2" name="TopDesign" persistent="TopDesign">\r
 <Hidden v="False" />\r
@@ -363,7 +363,7 @@
 </CyGuid_409391e1-c2a7-4709-8a6b-4622593f7390>\r
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 <CyGuid_813b8d13-518a-4dc8-91ba-cda6042dfb52 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtPhysicalFolderSerialize" version="1">\r
-<CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFolderSerialize" version="2">\r
+<CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFolderSerialize" version="3">\r
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@@ -372,7 +372,7 @@
 <dependencies>\r
 <CyGuid_d8451a8e-a4ea-4e21-aba8-966eaa7ea07d type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFolderGeneratedSerialize" version="1">\r
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-<CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFolderSerialize" version="2">\r
+<CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFolderSerialize" version="3">\r
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@@ -470,7 +470,7 @@
 <build_action v="HEADER;;;;" />\r
 <PropertyDeltas />\r
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-<CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFolderSerialize" version="2">\r
+<CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFolderSerialize" version="3">\r
 <CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtBaseContainerSerialize" version="1">\r
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 <Hidden v="False" />\r
@@ -503,7 +503,7 @@
 </CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8>\r
 <filters />\r
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-<CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFolderSerialize" version="2">\r
+<CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFolderSerialize" version="3">\r
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 <Hidden v="False" />\r
@@ -536,7 +536,7 @@
 </CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8>\r
 <filters />\r
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-<CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFolderSerialize" version="2">\r
+<CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFolderSerialize" version="3">\r
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 <Hidden v="True" />\r
@@ -583,7 +583,7 @@
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 <filters />\r
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-<CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFolderSerialize" version="2">\r
+<CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFolderSerialize" version="3">\r
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 <Hidden v="False" />\r
@@ -616,7 +616,7 @@
 </CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8>\r
 <filters />\r
 </CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0>\r
-<CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFolderSerialize" version="2">\r
+<CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFolderSerialize" version="3">\r
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 <Hidden v="False" />\r
@@ -649,7 +649,7 @@
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 <filters />\r
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-<CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFolderSerialize" version="2">\r
+<CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFolderSerialize" version="3">\r
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@@ -682,7 +682,7 @@
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-<CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFolderSerialize" version="2">\r
+<CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFolderSerialize" version="3">\r
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@@ -715,7 +715,7 @@
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-<CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFolderSerialize" version="2">\r
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@@ -748,7 +748,7 @@
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-<CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFolderSerialize" version="2">\r
+<CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFolderSerialize" version="3">\r
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@@ -781,7 +781,7 @@
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-<CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFolderSerialize" version="2">\r
+<CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFolderSerialize" version="3">\r
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@@ -814,7 +814,7 @@
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-<CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFolderSerialize" version="2">\r
+<CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFolderSerialize" version="3">\r
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@@ -847,7 +847,7 @@
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-<CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFolderSerialize" version="2">\r
+<CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFolderSerialize" version="3">\r
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@@ -866,7 +866,7 @@
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-<CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFolderSerialize" version="2">\r
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@@ -899,7 +899,7 @@
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-<CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFolderSerialize" version="2">\r
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@@ -918,7 +918,7 @@
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-<CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFolderSerialize" version="2">\r
+<CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFolderSerialize" version="3">\r
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@@ -937,7 +937,7 @@
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@@ -2723,7 +2723,7 @@
 </CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8>\r
 <filters />\r
 </CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0>\r
-<CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFolderSerialize" version="2">\r
+<CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFolderSerialize" version="3">\r
 <CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtBaseContainerSerialize" version="1">\r
 <CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItemSerialize" version="2" name="SCSI_Noise" persistent="">\r
 <Hidden v="False" />\r
@@ -2742,7 +2742,7 @@
 </CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8>\r
 <filters />\r
 </CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0>\r
-<CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFolderSerialize" version="2">\r
+<CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFolderSerialize" version="3">\r
 <CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtBaseContainerSerialize" version="1">\r
 <CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItemSerialize" version="2" name="SCSI_Filtered" persistent="">\r
 <Hidden v="False" />\r
@@ -2768,7 +2768,7 @@
 </CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8>\r
 <filters />\r
 </CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0>\r
-<CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFolderSerialize" version="2">\r
+<CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFolderSerialize" version="3">\r
 <CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtBaseContainerSerialize" version="1">\r
 <CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItemSerialize" version="2" name="SCSI_SEL_ISR" persistent="">\r
 <Hidden v="False" />\r
@@ -2794,7 +2794,7 @@
 </CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8>\r
 <filters />\r
 </CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0>\r
-<CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFolderSerialize" version="2">\r
+<CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFolderSerialize" version="3">\r
 <CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtBaseContainerSerialize" version="1">\r
 <CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItemSerialize" version="2" name="SCSI_Glitch_Ctl" persistent="">\r
 <Hidden v="False" />\r
@@ -2864,7 +2864,7 @@
 </CyGuid_d8451a8e-a4ea-4e21-aba8-966eaa7ea07d>\r
 <CyGuid_4429d4ed-fe84-42d0-9e9f-19aee0ff4e7e type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtComponentSerialize" version="1">\r
 <CyGuid_813b8d13-518a-4dc8-91ba-cda6042dfb52 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtPhysicalFolderSerialize" version="1">\r
-<CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFolderSerialize" version="2">\r
+<CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFolderSerialize" version="3">\r
 <CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtBaseContainerSerialize" version="1">\r
 <CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItemSerialize" version="2" name="OddParityGen" persistent="OddParityGen">\r
 <Hidden v="False" />\r
@@ -2894,7 +2894,7 @@
 </CyGuid_4429d4ed-fe84-42d0-9e9f-19aee0ff4e7e>\r
 <CyGuid_4429d4ed-fe84-42d0-9e9f-19aee0ff4e7e type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtComponentSerialize" version="1">\r
 <CyGuid_813b8d13-518a-4dc8-91ba-cda6042dfb52 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtPhysicalFolderSerialize" version="1">\r
-<CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFolderSerialize" version="2">\r
+<CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFolderSerialize" version="3">\r
 <CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtBaseContainerSerialize" version="1">\r
 <CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItemSerialize" version="2" name="scsiTarget" persistent="scsiTarget">\r
 <Hidden v="False" />\r
@@ -2973,10 +2973,10 @@
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@C/C++@General@Struct Return Method" v="System Default" />\r
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@C/C++@General@Verbose Asm" v="False" />\r
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@C/C++@Optimization@Remove Unused Functions" v="True" />\r
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@C/C++@Optimization@Fat LTO objects" v="True" />\r
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@C/C++@Optimization@Inline Functions" v="False" />\r
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@C/C++@Optimization@Optimization Level" v="None" />\r
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@C/C++@Optimization@Link Time Optimization" v="False" />\r
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@C/C++@Optimization@Fat LTO objects" v="True" />\r
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@C/C++@Optimization@Optimization Level" v="None" />\r
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@C/C++@Command Line@Command Line" v="" />\r
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Library Generation@Command Line@Command Line" v="" />\r
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Linker@General@Additional Libraries" v="" />\r
@@ -2989,6 +2989,15 @@
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Linker@General@Enable Float printf" v="False" />\r
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Linker@Optimization@Remove Unused Functions" v="True" />\r
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Linker@Command Line@Command Line" v="" />\r
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Linker@Optimization@SHARED Generate Debugging Information" v="" />\r
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Linker@Optimization@SHARED Struct Return Method" v="" />\r
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Linker@Optimization@SHARED Remove Unused Functions" v="" />\r
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Linker@Optimization@SHARED Inline Functions" v="" />\r
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Linker@Optimization@SHARED Optimization Level" v="" />\r
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Linker@Optimization@SHARED Link Time Optimization" v="" />\r
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Linker@Optimization@SHARED Fat LTO objects" v="" />\r
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@User Commands@General@Pre Build Commands" v="" />\r
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@User Commands@General@Post Build Commands" v="" />\r
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@General@Output Directory" v="${ProjectDir}\${ProcessorType}\${Platform}\${Config}" />\r
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@Assembly@General@Additional Include Directories" v="" />\r
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@Assembly@General@Create Listing File" v="True" />\r
@@ -3007,10 +3016,10 @@
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@C/C++@General@Struct Return Method" v="System Default" />\r
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@C/C++@General@Verbose Asm" v="False" />\r
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@C/C++@Optimization@Remove Unused Functions" v="True" />\r
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@C/C++@Optimization@Fat LTO objects" v="True" />\r
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@C/C++@Optimization@Inline Functions" v="False" />\r
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@C/C++@Optimization@Optimization Level" v="Size" />\r
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@C/C++@Optimization@Link Time Optimization" v="False" />\r
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@C/C++@Optimization@Fat LTO objects" v="True" />\r
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@C/C++@Optimization@Optimization Level" v="Size" />\r
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@C/C++@Command Line@Command Line" v="" />\r
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@Library Generation@Command Line@Command Line" v="" />\r
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@Linker@General@Additional Libraries" v="" />\r
@@ -3023,6 +3032,15 @@
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@Linker@General@Enable Float printf" v="False" />\r
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@Linker@Optimization@Remove Unused Functions" v="True" />\r
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@Linker@Command Line@Command Line" v="" />\r
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@Linker@Optimization@SHARED Generate Debugging Information" v="" />\r
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@Linker@Optimization@SHARED Struct Return Method" v="" />\r
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@Linker@Optimization@SHARED Remove Unused Functions" v="" />\r
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@Linker@Optimization@SHARED Inline Functions" v="" />\r
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@Linker@Optimization@SHARED Optimization Level" v="" />\r
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@Linker@Optimization@SHARED Link Time Optimization" v="" />\r
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@Linker@Optimization@SHARED Fat LTO objects" v="" />\r
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@User Commands@General@Pre Build Commands" v="" />\r
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@User Commands@General@Post Build Commands" v="" />\r
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@General@Output Directory" v="${ProjectDir}\${ProcessorType}\${Platform}\${Config}" />\r
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@Assembly@General@Additional Include Directories" v="" />\r
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@Assembly@General@Create Listing File" v="True" />\r
@@ -3041,10 +3059,10 @@
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@C/C++@General@Struct Return Method" v="System Default" />\r
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@C/C++@General@Verbose Asm" v="False" />\r
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@C/C++@Optimization@Remove Unused Functions" v="True" />\r
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@C/C++@Optimization@Fat LTO objects" v="True" />\r
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@C/C++@Optimization@Inline Functions" v="False" />\r
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@C/C++@Optimization@Optimization Level" v="None" />\r
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@C/C++@Optimization@Link Time Optimization" v="False" />\r
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@C/C++@Optimization@Fat LTO objects" v="True" />\r
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@C/C++@Optimization@Optimization Level" v="None" />\r
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@C/C++@Command Line@Command Line" v="" />\r
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@Library Generation@Command Line@Command Line" v="" />\r
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@Linker@General@Additional Libraries" v="" />\r
@@ -3057,6 +3075,15 @@
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@Linker@General@Enable Float printf" v="False" />\r
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@Linker@Optimization@Remove Unused Functions" v="True" />\r
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@Linker@Command Line@Command Line" v="" />\r
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@Linker@Optimization@SHARED Generate Debugging Information" v="" />\r
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@Linker@Optimization@SHARED Struct Return Method" v="" />\r
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@Linker@Optimization@SHARED Remove Unused Functions" v="" />\r
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@Linker@Optimization@SHARED Inline Functions" v="" />\r
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@Linker@Optimization@SHARED Optimization Level" v="" />\r
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@Linker@Optimization@SHARED Link Time Optimization" v="" />\r
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@Linker@Optimization@SHARED Fat LTO objects" v="" />\r
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@User Commands@General@Pre Build Commands" v="" />\r
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@User Commands@General@Post Build Commands" v="" />\r
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@General@Output Directory" v="${ProjectDir}\${ProcessorType}\${Platform}\${Config}" />\r
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@Assembly@General@Additional Include Directories" v="" />\r
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@Assembly@General@Create Listing File" v="True" />\r
@@ -3075,10 +3102,10 @@
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@C/C++@General@Struct Return Method" v="System Default" />\r
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@C/C++@General@Verbose Asm" v="False" />\r
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@C/C++@Optimization@Remove Unused Functions" v="True" />\r
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@C/C++@Optimization@Fat LTO objects" v="True" />\r
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@C/C++@Optimization@Inline Functions" v="True" />\r
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@C/C++@Optimization@Optimization Level" v="Size" />\r
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@C/C++@Optimization@Link Time Optimization" v="False" />\r
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@C/C++@Optimization@Fat LTO objects" v="True" />\r
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@C/C++@Optimization@Optimization Level" v="Size" />\r
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@C/C++@Command Line@Command Line" v="" />\r
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@Library Generation@Command Line@Command Line" v="" />\r
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@Linker@General@Additional Libraries" v="" />\r
@@ -3091,6 +3118,15 @@
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@Linker@General@Enable Float printf" v="False" />\r
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@Linker@Optimization@Remove Unused Functions" v="True" />\r
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@Linker@Command Line@Command Line" v="" />\r
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@Linker@Optimization@SHARED Generate Debugging Information" v="" />\r
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@Linker@Optimization@SHARED Struct Return Method" v="" />\r
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@Linker@Optimization@SHARED Remove Unused Functions" v="" />\r
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@Linker@Optimization@SHARED Inline Functions" v="" />\r
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@Linker@Optimization@SHARED Optimization Level" v="" />\r
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@Linker@Optimization@SHARED Link Time Optimization" v="" />\r
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@Linker@Optimization@SHARED Fat LTO objects" v="" />\r
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@User Commands@General@Pre Build Commands" v="" />\r
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@User Commands@General@Post Build Commands" v="" />\r
 </name>\r
 </platform>\r
 <platform>\r
@@ -3113,10 +3149,10 @@
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM0@C/C++@General@Struct Return Method" v="System Default" />\r
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM0@C/C++@General@Verbose Asm" v="False" />\r
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM0@C/C++@Optimization@Remove Unused Functions" v="True" />\r
+<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM0@C/C++@Optimization@Fat LTO objects" v="True" />\r
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM0@C/C++@Optimization@Inline Functions" v="False" />\r
-<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM0@C/C++@Optimization@Optimization Level" v="None" />\r
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM0@C/C++@Optimization@Link Time Optimization" v="False" />\r
-<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM0@C/C++@Optimization@Fat LTO objects" v="True" />\r
+<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM0@C/C++@Optimization@Optimization Level" v="None" />\r
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM0@C/C++@Command Line@Command Line" v="" />\r
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM0@Library Generation@Command Line@Command Line" v="" />\r
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM0@Linker@General@Additional Libraries" v="" />\r
@@ -3129,6 +3165,15 @@
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM0@Linker@General@Enable Float printf" v="False" />\r
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM0@Linker@Optimization@Remove Unused Functions" v="True" />\r
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM0@Linker@Command Line@Command Line" v="" />\r
+<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM0@Linker@Optimization@SHARED Generate Debugging Information" v="" />\r
+<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM0@Linker@Optimization@SHARED Struct Return Method" v="" />\r
+<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM0@Linker@Optimization@SHARED Remove Unused Functions" v="" />\r
+<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM0@Linker@Optimization@SHARED Inline Functions" v="" />\r
+<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM0@Linker@Optimization@SHARED Optimization Level" v="" />\r
+<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM0@Linker@Optimization@SHARED Link Time Optimization" v="" />\r
+<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM0@Linker@Optimization@SHARED Fat LTO objects" v="" />\r
+<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM0@User Commands@General@Pre Build Commands" v="" />\r
+<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM0@User Commands@General@Post Build Commands" v="" />\r
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM0@General@Output Directory" v="${ProjectDir}\${ProcessorType}\${Platform}\${Config}" />\r
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM0@Assembly@General@Additional Include Directories" v="" />\r
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM0@Assembly@General@Create Listing File" v="True" />\r
@@ -3147,10 +3192,10 @@
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM0@C/C++@General@Struct Return Method" v="System Default" />\r
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM0@C/C++@General@Verbose Asm" v="False" />\r
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM0@C/C++@Optimization@Remove Unused Functions" v="True" />\r
+<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM0@C/C++@Optimization@Fat LTO objects" v="True" />\r
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM0@C/C++@Optimization@Inline Functions" v="False" />\r
-<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM0@C/C++@Optimization@Optimization Level" v="Size" />\r
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM0@C/C++@Optimization@Link Time Optimization" v="False" />\r
-<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM0@C/C++@Optimization@Fat LTO objects" v="True" />\r
+<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM0@C/C++@Optimization@Optimization Level" v="Size" />\r
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM0@C/C++@Command Line@Command Line" v="" />\r
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM0@Library Generation@Command Line@Command Line" v="" />\r
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM0@Linker@General@Additional Libraries" v="" />\r
@@ -3163,6 +3208,15 @@
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM0@Linker@General@Enable Float printf" v="False" />\r
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM0@Linker@Optimization@Remove Unused Functions" v="True" />\r
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM0@Linker@Command Line@Command Line" v="" />\r
+<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM0@Linker@Optimization@SHARED Generate Debugging Information" v="" />\r
+<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM0@Linker@Optimization@SHARED Struct Return Method" v="" />\r
+<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM0@Linker@Optimization@SHARED Remove Unused Functions" v="" />\r
+<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM0@Linker@Optimization@SHARED Inline Functions" v="" />\r
+<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM0@Linker@Optimization@SHARED Optimization Level" v="" />\r
+<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM0@Linker@Optimization@SHARED Link Time Optimization" v="" />\r
+<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM0@Linker@Optimization@SHARED Fat LTO objects" v="" />\r
+<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM0@User Commands@General@Pre Build Commands" v="" />\r
+<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM0@User Commands@General@Post Build Commands" v="" />\r
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM3@General@Output Directory" v="${ProjectDir}\${ProcessorType}\${Platform}\${Config}" />\r
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM3@Assembly@General@Additional Include Directories" v="" />\r
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM3@Assembly@General@Create Listing File" v="True" />\r
@@ -3181,10 +3235,10 @@
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM3@C/C++@General@Struct Return Method" v="System Default" />\r
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM3@C/C++@General@Verbose Asm" v="False" />\r
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM3@C/C++@Optimization@Remove Unused Functions" v="True" />\r
+<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM3@C/C++@Optimization@Fat LTO objects" v="True" />\r
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM3@C/C++@Optimization@Inline Functions" v="False" />\r
-<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM3@C/C++@Optimization@Optimization Level" v="None" />\r
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM3@C/C++@Optimization@Link Time Optimization" v="False" />\r
-<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM3@C/C++@Optimization@Fat LTO objects" v="True" />\r
+<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM3@C/C++@Optimization@Optimization Level" v="None" />\r
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM3@C/C++@Command Line@Command Line" v="" />\r
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM3@Library Generation@Command Line@Command Line" v="" />\r
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM3@Linker@General@Additional Libraries" v="" />\r
@@ -3197,6 +3251,15 @@
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM3@Linker@General@Enable Float printf" v="False" />\r
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM3@Linker@Optimization@Remove Unused Functions" v="True" />\r
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM3@Linker@Command Line@Command Line" v="" />\r
+<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM3@Linker@Optimization@SHARED Generate Debugging Information" v="" />\r
+<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM3@Linker@Optimization@SHARED Struct Return Method" v="" />\r
+<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM3@Linker@Optimization@SHARED Remove Unused Functions" v="" />\r
+<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM3@Linker@Optimization@SHARED Inline Functions" v="" />\r
+<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM3@Linker@Optimization@SHARED Optimization Level" v="" />\r
+<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM3@Linker@Optimization@SHARED Link Time Optimization" v="" />\r
+<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM3@Linker@Optimization@SHARED Fat LTO objects" v="" />\r
+<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM3@User Commands@General@Pre Build Commands" v="" />\r
+<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM3@User Commands@General@Post Build Commands" v="" />\r
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM3@General@Output Directory" v="${ProjectDir}\${ProcessorType}\${Platform}\${Config}" />\r
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM3@Assembly@General@Additional Include Directories" v="" />\r
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM3@Assembly@General@Create Listing File" v="True" />\r
@@ -3215,10 +3278,10 @@
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM3@C/C++@General@Struct Return Method" v="System Default" />\r
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM3@C/C++@General@Verbose Asm" v="False" />\r
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM3@C/C++@Optimization@Remove Unused Functions" v="True" />\r
+<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM3@C/C++@Optimization@Fat LTO objects" v="True" />\r
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM3@C/C++@Optimization@Inline Functions" v="False" />\r
-<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM3@C/C++@Optimization@Optimization Level" v="Size" />\r
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM3@C/C++@Optimization@Link Time Optimization" v="False" />\r
-<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM3@C/C++@Optimization@Fat LTO objects" v="True" />\r
+<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM3@C/C++@Optimization@Optimization Level" v="Size" />\r
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM3@C/C++@Command Line@Command Line" v="" />\r
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM3@Library Generation@Command Line@Command Line" v="" />\r
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM3@Linker@General@Additional Libraries" v="" />\r
@@ -3231,14 +3294,31 @@
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM3@Linker@General@Enable Float printf" v="False" />\r
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM3@Linker@Optimization@Remove Unused Functions" v="True" />\r
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM3@Linker@Command Line@Command Line" v="" />\r
+<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM3@Linker@Optimization@SHARED Generate Debugging Information" v="" />\r
+<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM3@Linker@Optimization@SHARED Struct Return Method" v="" />\r
+<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM3@Linker@Optimization@SHARED Remove Unused Functions" v="" />\r
+<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM3@Linker@Optimization@SHARED Inline Functions" v="" />\r
+<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM3@Linker@Optimization@SHARED Optimization Level" v="" />\r
+<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM3@Linker@Optimization@SHARED Link Time Optimization" v="" />\r
+<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM3@Linker@Optimization@SHARED Fat LTO objects" v="" />\r
+<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM3@User Commands@General@Pre Build Commands" v="" />\r
+<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM3@User Commands@General@Post Build Commands" v="" />\r
 </name>\r
 </platform>\r
 <platform>\r
 <name v="5bca58cd-5542-421c-b08d-9513dbb687fd">\r
 <name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Debug@CortexM0@General@Output Directory" v="${ProjectDir}\${ProcessorType}\${Platform}\${Config}" />\r
+<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Debug@CortexM0@User Commands@General@Pre Build Commands" v="" />\r
+<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Debug@CortexM0@User Commands@General@Post Build Commands" v="" />\r
 <name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Release@CortexM0@General@Output Directory" v="${ProjectDir}\${ProcessorType}\${Platform}\${Config}" />\r
+<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Release@CortexM0@User Commands@General@Pre Build Commands" v="" />\r
+<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Release@CortexM0@User Commands@General@Post Build Commands" v="" />\r
 <name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Debug@CortexM3@General@Output Directory" v="${ProjectDir}\${ProcessorType}\${Platform}\${Config}" />\r
+<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Debug@CortexM3@User Commands@General@Pre Build Commands" v="" />\r
+<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Debug@CortexM3@User Commands@General@Post Build Commands" v="" />\r
 <name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Release@CortexM3@General@Output Directory" v="${ProjectDir}\${ProcessorType}\${Platform}\${Config}" />\r
+<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Release@CortexM3@User Commands@General@Pre Build Commands" v="" />\r
+<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Release@CortexM3@User Commands@General@Post Build Commands" v="" />\r
 </name>\r
 </platform>\r
 <platform>\r
@@ -3249,6 +3329,7 @@
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM0@Assembly@General@Suppress Warnings" v="False" />\r
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM0@Assembly@General@Generate List Files" v="True" />\r
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM0@Assembly@Command Line@Command Line" v="" />\r
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM0@Assembly@General@SHARED Use MicroLib" v="" />\r
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM0@C/C++@General@Additional Include Directories" v="" />\r
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM0@C/C++@General@Generate List Files" v="True" />\r
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM0@C/C++@General@Default Char Unsigned" v="False" />\r
@@ -3259,6 +3340,7 @@
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM0@C/C++@Optimization@Optimization Level" v="None" />\r
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM0@C/C++@Optimization@Split Sections" v="True" />\r
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM0@C/C++@Command Line@Command Line" v="" />\r
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM0@C/C++@General@SHARED Use MicroLib" v="" />\r
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM0@Library Generation@Command Line@Command Line" v="" />\r
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM0@Linker@General@Additional Libraries" v="" />\r
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM0@Linker@General@Additional Library Directories" v="" />\r
@@ -3268,12 +3350,15 @@
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM0@Linker@General@Generate Debugging Information" v="True" />\r
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM0@Linker@General@Use Default Libs" v="True" />\r
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM0@Linker@Command Line@Command Line" v="" />\r
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM0@User Commands@General@Pre Build Commands" v="" />\r
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM0@User Commands@General@Post Build Commands" v="" />\r
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM0@General@Output Directory" v="${ProjectDir}\${ProcessorType}\${Platform}\${Config}" />\r
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM0@Assembly@General@Additional Include Directories" v="" />\r
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM0@Assembly@General@Generate Debugging Information" v="True" />\r
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM0@Assembly@General@Suppress Warnings" v="False" />\r
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM0@Assembly@General@Generate List Files" v="True" />\r
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM0@Assembly@Command Line@Command Line" v="" />\r
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM0@Assembly@General@SHARED Use MicroLib" v="" />\r
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM0@C/C++@General@Additional Include Directories" v="" />\r
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM0@C/C++@General@Generate List Files" v="True" />\r
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM0@C/C++@General@Default Char Unsigned" v="False" />\r
@@ -3284,6 +3369,7 @@
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM0@C/C++@Optimization@Optimization Level" v="Size" />\r
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM0@C/C++@Optimization@Split Sections" v="True" />\r
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM0@C/C++@Command Line@Command Line" v="" />\r
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM0@C/C++@General@SHARED Use MicroLib" v="" />\r
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM0@Library Generation@Command Line@Command Line" v="" />\r
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM0@Linker@General@Additional Libraries" v="" />\r
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM0@Linker@General@Additional Library Directories" v="" />\r
@@ -3293,12 +3379,15 @@
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM0@Linker@General@Generate Debugging Information" v="True" />\r
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM0@Linker@General@Use Default Libs" v="True" />\r
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM0@Linker@Command Line@Command Line" v="" />\r
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM0@User Commands@General@Pre Build Commands" v="" />\r
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM0@User Commands@General@Post Build Commands" v="" />\r
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM3@General@Output Directory" v="${ProjectDir}\${ProcessorType}\${Platform}\${Config}" />\r
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM3@Assembly@General@Additional Include Directories" v="" />\r
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM3@Assembly@General@Generate Debugging Information" v="True" />\r
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM3@Assembly@General@Suppress Warnings" v="False" />\r
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM3@Assembly@General@Generate List Files" v="True" />\r
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM3@Assembly@Command Line@Command Line" v="" />\r
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM3@Assembly@General@SHARED Use MicroLib" v="" />\r
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM3@C/C++@General@Additional Include Directories" v="" />\r
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM3@C/C++@General@Generate List Files" v="True" />\r
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM3@C/C++@General@Default Char Unsigned" v="False" />\r
@@ -3309,6 +3398,7 @@
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM3@C/C++@Optimization@Optimization Level" v="None" />\r
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM3@C/C++@Optimization@Split Sections" v="True" />\r
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM3@C/C++@Command Line@Command Line" v="" />\r
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM3@C/C++@General@SHARED Use MicroLib" v="" />\r
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM3@Library Generation@Command Line@Command Line" v="" />\r
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM3@Linker@General@Additional Libraries" v="" />\r
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM3@Linker@General@Additional Library Directories" v="" />\r
@@ -3318,12 +3408,15 @@
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM3@Linker@General@Generate Debugging Information" v="True" />\r
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM3@Linker@General@Use Default Libs" v="True" />\r
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM3@Linker@Command Line@Command Line" v="" />\r
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM3@User Commands@General@Pre Build Commands" v="" />\r
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM3@User Commands@General@Post Build Commands" v="" />\r
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@General@Output Directory" v="${ProjectDir}\${ProcessorType}\${Platform}\${Config}" />\r
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@Assembly@General@Additional Include Directories" v="" />\r
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@Assembly@General@Generate Debugging Information" v="True" />\r
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@Assembly@General@Suppress Warnings" v="False" />\r
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@Assembly@General@Generate List Files" v="True" />\r
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@Assembly@Command Line@Command Line" v="" />\r
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@Assembly@General@SHARED Use MicroLib" v="" />\r
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@C/C++@General@Additional Include Directories" v="" />\r
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@C/C++@General@Generate List Files" v="True" />\r
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@C/C++@General@Default Char Unsigned" v="False" />\r
@@ -3334,6 +3427,7 @@
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@C/C++@Optimization@Optimization Level" v="Size" />\r
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@C/C++@Optimization@Split Sections" v="True" />\r
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@C/C++@Command Line@Command Line" v="" />\r
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@C/C++@General@SHARED Use MicroLib" v="" />\r
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@Library Generation@Command Line@Command Line" v="" />\r
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@Linker@General@Additional Libraries" v="" />\r
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@Linker@General@Additional Library Directories" v="" />\r
@@ -3343,31 +3437,33 @@
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@Linker@General@Generate Debugging Information" v="True" />\r
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@Linker@General@Use Default Libs" v="True" />\r
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@Linker@Command Line@Command Line" v="" />\r
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@User Commands@General@Pre Build Commands" v="" />\r
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@User Commands@General@Post Build Commands" v="" />\r
 </name>\r
 </platform>\r
 <platform>\r
 <name v="e9305a93-d091-4da5-bdc7-2813049dcdbf">\r
 <name_val_pair name="e9305a93-d091-4da5-bdc7-2813049dcdbf@Release@CortexM3@General@Output Directory" v="${ProjectDir}\${ProcessorType}\${Platform}\${Config}" />\r
 <name_val_pair name="e9305a93-d091-4da5-bdc7-2813049dcdbf@Release@CortexM3@Assembly@Command Line@Command Line" v="-s+ -M&lt;&gt; -w+ -r -DNDEBUG --fpu None" />\r
+<name_val_pair name="e9305a93-d091-4da5-bdc7-2813049dcdbf@Release@CortexM3@C/C++@General@Preprocessor Definitions" v="-D NDEBUG -D CY_CORE_ID=0" />\r
 <name_val_pair name="e9305a93-d091-4da5-bdc7-2813049dcdbf@Release@CortexM3@C/C++@Command Line@Command Line" v="-D NDEBUG --debug --endian=little -e --fpu=None --no_wrap_diagnostics" />\r
 <name_val_pair name="e9305a93-d091-4da5-bdc7-2813049dcdbf@Release@CortexM3@Library Generation@Command Line@Command Line" v="" />\r
 <name_val_pair name="e9305a93-d091-4da5-bdc7-2813049dcdbf@Release@CortexM3@Linker@Command Line@Command Line" v="--semihosting --entry __iar_program_start --vfe" />\r
+<name_val_pair name="e9305a93-d091-4da5-bdc7-2813049dcdbf@Release@CortexM3@User Commands@General@Pre Build Commands" v="" />\r
+<name_val_pair name="e9305a93-d091-4da5-bdc7-2813049dcdbf@Release@CortexM3@User Commands@General@Post Build Commands" v="" />\r
 </name>\r
 </platform>\r
 </platforms>\r
 <project_current_platform v="c9323d49-d323-40b8-9b59-cc008d68a989" />\r
-<project_current_processor v="CortexM3" />\r
 <last_selected_tab v="Cypress" />\r
-<WriteAppVersionLastSavedWith v="4.0.0.432" />\r
-<WriteAppMarketingVersionLastSavedWith v=" 4.0 Update 1" />\r
+<WriteAppVersionLastSavedWith v="4.1.0.2686" />\r
+<WriteAppMarketingVersionLastSavedWith v=" 4.1" />\r
 <project_id v="6e1f5cbb-a0ca-4f55-a1fa-7b20c5be3a3e" />\r
 <GenerateDescriptionFiles v="False" />\r
 </CyGuid_49cfd574-032a-4a64-b7be-d4eeeaf25e43>\r
 </CyGuid_60697ce6-dce2-4816-8680-4de0635742eb>\r
 <top_block v="TopDesign" />\r
 <selected_device v="CY8C5267AXI-LP051" />\r
-<pdl_path v="" />\r
-<include_paths />\r
 <CyGuid_495451fe-d201-4d01-b22d-5d3f5609ac37 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtComponentMgrSerialize" version="4" xml_contents_version="1">\r
 <library_deps>\r
 <library_dep persistent="${CyRoot}\psoc\content\default\CyAnnotationLibrary\CyAnnotationLibrary.cylib\CyAnnotationLibrary.cyprj" />\r

diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CTL_PHASE.h b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CTL_PHASE.h
index dbb256b687a2068ed20d63fef6332772f397ed45..f3d1b7074d9b3e97377fa4e3d7927d012f9d28ad 100755 (executable)
--- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CTL_PHASE.h
+++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CTL_PHASE.h
@@ -17,7 +17,15 @@
 #if !defined(CY_CONTROL_REG_SCSI_CTL_PHASE_H) /* CY_CONTROL_REG_SCSI_CTL_PHASE_H */\r
 #define CY_CONTROL_REG_SCSI_CTL_PHASE_H\r
 \r
-#include "cytypes.h"\r
+#include "cyfitter.h"\r
+\r
+#if ((CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC3) || \\r
+     (CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC4) || \\r
+     (CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC5))\r
+    #include "cytypes.h"\r
+#else\r
+    #include "syslib/cy_syslib.h"\r
+#endif\r
 \r
     \r
 /***************************************\r

diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Filtered.h b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Filtered.h
index dba521887f1945136aba547392902c5f010f8858..14605f16c47ccefaada41cc5832a9177de2f0813 100755 (executable)
--- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Filtered.h
+++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Filtered.h
@@ -17,8 +17,16 @@
 #if !defined(CY_STATUS_REG_SCSI_Filtered_H) /* CY_STATUS_REG_SCSI_Filtered_H */\r
 #define CY_STATUS_REG_SCSI_Filtered_H\r
 \r
-#include "cytypes.h"\r
-#include "CyLib.h"\r
+#include "cyfitter.h"\r
+\r
+#if ((CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC3) || \\r
+     (CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC4) || \\r
+     (CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC5))\r
+    #include "cytypes.h"\r
+    #include "CyLib.h"\r
+#else\r
+    #include "syslib/cy_syslib.h"\r
+#endif\r
 \r
     \r
 /***************************************\r

diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Glitch_Ctl.h b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Glitch_Ctl.h
index 50da66e8f28e77d999203e74ebac30d0e959ecb7..80cd7ba9bf15d2beeb558c0fa56850273577ee38 100755 (executable)
--- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Glitch_Ctl.h
+++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Glitch_Ctl.h
@@ -17,7 +17,15 @@
 #if !defined(CY_CONTROL_REG_SCSI_Glitch_Ctl_H) /* CY_CONTROL_REG_SCSI_Glitch_Ctl_H */\r
 #define CY_CONTROL_REG_SCSI_Glitch_Ctl_H\r
 \r
-#include "cytypes.h"\r
+#include "cyfitter.h"\r
+\r
+#if ((CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC3) || \\r
+     (CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC4) || \\r
+     (CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC5))\r
+    #include "cytypes.h"\r
+#else\r
+    #include "syslib/cy_syslib.h"\r
+#endif\r
 \r
     \r
 /***************************************\r

diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Out_Bits.h b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Out_Bits.h
index 4431995a6b84034699e58e659c6b6c4b2528c252..dbdc2f3462c5493bd2f755aed1c6137e47c207c2 100755 (executable)
--- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Out_Bits.h
+++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Out_Bits.h
@@ -17,7 +17,15 @@
 #if !defined(CY_CONTROL_REG_SCSI_Out_Bits_H) /* CY_CONTROL_REG_SCSI_Out_Bits_H */\r
 #define CY_CONTROL_REG_SCSI_Out_Bits_H\r
 \r
-#include "cytypes.h"\r
+#include "cyfitter.h"\r
+\r
+#if ((CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC3) || \\r
+     (CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC4) || \\r
+     (CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC5))\r
+    #include "cytypes.h"\r
+#else\r
+    #include "syslib/cy_syslib.h"\r
+#endif\r
 \r
     \r
 /***************************************\r

diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Out_Ctl.h b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Out_Ctl.h
index 6dd3acbd4a0e982a66b528600c728f27c425a340..7419fb73e0968227c73cec9bf8768940c979fe69 100755 (executable)
--- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Out_Ctl.h
+++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Out_Ctl.h
@@ -17,7 +17,15 @@
 #if !defined(CY_CONTROL_REG_SCSI_Out_Ctl_H) /* CY_CONTROL_REG_SCSI_Out_Ctl_H */\r
 #define CY_CONTROL_REG_SCSI_Out_Ctl_H\r
 \r
-#include "cytypes.h"\r
+#include "cyfitter.h"\r
+\r
+#if ((CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC3) || \\r
+     (CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC4) || \\r
+     (CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC5))\r
+    #include "cytypes.h"\r
+#else\r
+    #include "syslib/cy_syslib.h"\r
+#endif\r
 \r
     \r
 /***************************************\r

diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Parity_Error.h b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Parity_Error.h
index 9309c16f949421544a305b00cb0d64574b0ff050..f7ce88751bcf2ff3fa89cb4840e9b78ae01c88d7 100755 (executable)
--- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Parity_Error.h
+++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Parity_Error.h
@@ -17,8 +17,16 @@
 #if !defined(CY_STATUS_REG_SCSI_Parity_Error_H) /* CY_STATUS_REG_SCSI_Parity_Error_H */\r
 #define CY_STATUS_REG_SCSI_Parity_Error_H\r
 \r
-#include "cytypes.h"\r
-#include "CyLib.h"\r
+#include "cyfitter.h"\r
+\r
+#if ((CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC3) || \\r
+     (CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC4) || \\r
+     (CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC5))\r
+    #include "cytypes.h"\r
+    #include "CyLib.h"\r
+#else\r
+    #include "syslib/cy_syslib.h"\r
+#endif\r
 \r
     \r
 /***************************************\r

diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SDCard.h b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SDCard.h
index 6d566df54e7b60e315edc09edf2db4645b781256..6a8ae5daf53c6c9d0b141e64d1a51ec480ea7eca 100755 (executable)
--- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SDCard.h
+++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SDCard.h
@@ -19,15 +19,9 @@
 #if !defined(CY_SPIM_SDCard_H)\r
 #define CY_SPIM_SDCard_H\r
 \r
-#include "cytypes.h"\r
 #include "cyfitter.h"\r
-#include "CyLib.h"\r
-\r
-/* Check to see if required defines such as CY_PSOC5A are available */\r
-/* They are defined starting with cy_boot v3.0 */\r
-#if !defined (CY_PSOC5A)\r
-    #error Component SPI_Master_v2_50 requires cy_boot v3.0 or later\r
-#endif /* (CY_PSOC5A) */\r
+#include "cytypes.h"\r
+#include "CyLib.h" /* For CyEnterCriticalSection() and CyExitCriticalSection() functions */\r
 \r
 \r
 /***************************************\r

diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevice.h b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevice.h
index e9a0eafadd5ee3adf47bf2703d6cf20567a0b8e6..160bd6a0f2d6f6d9d3beea5016670d623e140a77 100755 (executable)
--- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevice.h
+++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevice.h
@@ -1,14 +1,14 @@
 /*******************************************************************************\r
 * File Name: cydevice.h\r
 * OBSOLETE: Do not use this file. Use the _trm version instead.\r
-* PSoC Creator  4.0 Update 1\r
+* PSoC Creator  4.1\r
 *\r
 * Description:\r
 * This file provides all of the address values for the entire PSoC device.\r
 * This file is automatically generated by PSoC Creator.\r
 *\r
 ********************************************************************************\r
-* Copyright (c) 2007-2016 Cypress Semiconductor.  All rights reserved.\r
+* Copyright (c) 2007-2017 Cypress Semiconductor.  All rights reserved.\r
 * You may use this file only in accordance with the license, terms, conditions, \r
 * disclaimers, and limitations in the end user license agreement accompanying \r
 * the software package with which this file was provided.\r

diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevice_trm.h b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevice_trm.h
index b7f270a8da6ebc4a456d739d5811ec091eadb82a..bff26eda9c24eb333a05667c85ee5ee35d29f4b5 100755 (executable)
--- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevice_trm.h
+++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevice_trm.h
@@ -1,14 +1,14 @@
 /*******************************************************************************\r
 * File Name: cydevice_trm.h\r
 * \r
-* PSoC Creator  4.0 Update 1\r
+* PSoC Creator  4.1\r
 *\r
 * Description:\r
 * This file provides all of the address values for the entire PSoC device.\r
 * This file is automatically generated by PSoC Creator.\r
 *\r
 ********************************************************************************\r
-* Copyright (c) 2007-2016 Cypress Semiconductor.  All rights reserved.\r
+* Copyright (c) 2007-2017 Cypress Semiconductor.  All rights reserved.\r
 * You may use this file only in accordance with the license, terms, conditions, \r
 * disclaimers, and limitations in the end user license agreement accompanying \r
 * the software package with which this file was provided.\r

diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicegnu.inc b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicegnu.inc
index bacd4b70cd28cf30edf5f535c3a164268031dfae..5db8be3b4f2d5a57857b84a30e7b3cecfac6ef2f 100755 (executable)
--- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicegnu.inc
+++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicegnu.inc
@@ -1,14 +1,14 @@
 /*******************************************************************************\r
 * File Name: cydevicegnu.inc\r
 * OBSOLETE: Do not use this file. Use the _trm version instead.\r
-* PSoC Creator  4.0 Update 1\r
+* PSoC Creator  4.1\r
 *\r
 * Description:\r
 * This file provides all of the address values for the entire PSoC device.\r
 * This file is automatically generated by PSoC Creator.\r
 *\r
 ********************************************************************************\r
-* Copyright (c) 2007-2016 Cypress Semiconductor.  All rights reserved.\r
+* Copyright (c) 2007-2017 Cypress Semiconductor.  All rights reserved.\r
 * You may use this file only in accordance with the license, terms, conditions, \r
 * disclaimers, and limitations in the end user license agreement accompanying \r
 * the software package with which this file was provided.\r

diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicegnu_trm.inc b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicegnu_trm.inc
index 22e50615cd0cdc7ebe17b59c8d429ae0ac5346b4..e0ed758a0d60ac3b3aff6d4cac325a5729a9d25d 100755 (executable)
--- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicegnu_trm.inc
+++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicegnu_trm.inc
@@ -1,14 +1,14 @@
 /*******************************************************************************\r
 * File Name: cydevicegnu_trm.inc\r
 * \r
-* PSoC Creator  4.0 Update 1\r
+* PSoC Creator  4.1\r
 *\r
 * Description:\r
 * This file provides all of the address values for the entire PSoC device.\r
 * This file is automatically generated by PSoC Creator.\r
 *\r
 ********************************************************************************\r
-* Copyright (c) 2007-2016 Cypress Semiconductor.  All rights reserved.\r
+* Copyright (c) 2007-2017 Cypress Semiconductor.  All rights reserved.\r
 * You may use this file only in accordance with the license, terms, conditions, \r
 * disclaimers, and limitations in the end user license agreement accompanying \r
 * the software package with which this file was provided.\r

diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cydeviceiar.inc b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cydeviceiar.inc
index 019dd7c8a21483794027157430a7819012b4f5d1..6b49c4845bc4bce4984ecb7f91d5789cdeaf22bf 100755 (executable)
--- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cydeviceiar.inc
+++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cydeviceiar.inc
@@ -1,13 +1,13 @@
 ;\r
 ; File Name: cydeviceiar.inc\r
 ; OBSOLETE: Do not use this file. Use the _trm version instead.\r
-; PSoC Creator  4.0 Update 1\r
+; PSoC Creator  4.1\r
 ;\r
 ; Description:\r
 ; This file provides all of the address values for the entire PSoC device.\r
 ;\r
 ;-------------------------------------------------------------------------------\r
-; Copyright (c) 2007-2016 Cypress Semiconductor.  All rights reserved.\r
+; Copyright (c) 2007-2017 Cypress Semiconductor.  All rights reserved.\r
 ; You may use this file only in accordance with the license, terms, conditions, \r
 ; disclaimers, and limitations in the end user license agreement accompanying \r
 ; the software package with which this file was provided.\r

diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cydeviceiar_trm.inc b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cydeviceiar_trm.inc
index 0e2c8a3884422dc62a76eda285faa2d007286789..c7c07d0bddf32e70910d289f2fca9b055af2242f 100755 (executable)
--- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cydeviceiar_trm.inc
+++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cydeviceiar_trm.inc
@@ -1,13 +1,13 @@
 ;\r
 ; File Name: cydeviceiar_trm.inc\r
 ; \r
-; PSoC Creator  4.0 Update 1\r
+; PSoC Creator  4.1\r
 ;\r
 ; Description:\r
 ; This file provides all of the address values for the entire PSoC device.\r
 ;\r
 ;-------------------------------------------------------------------------------\r
-; Copyright (c) 2007-2016 Cypress Semiconductor.  All rights reserved.\r
+; Copyright (c) 2007-2017 Cypress Semiconductor.  All rights reserved.\r
 ; You may use this file only in accordance with the license, terms, conditions, \r
 ; disclaimers, and limitations in the end user license agreement accompanying \r
 ; the software package with which this file was provided.\r

diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicerv.inc b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicerv.inc
index 228aba9db62b0a572ee483d0cc4ef041edbcdd2c..e9f2b7879d09fa2de7cfe811674d43a2196e5275 100755 (executable)
--- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicerv.inc
+++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicerv.inc
@@ -1,13 +1,13 @@
 ;\r
 ; File Name: cydevicerv.inc\r
 ; OBSOLETE: Do not use this file. Use the _trm version instead.\r
-; PSoC Creator  4.0 Update 1\r
+; PSoC Creator  4.1\r
 ;\r
 ; Description:\r
 ; This file provides all of the address values for the entire PSoC device.\r
 ;\r
 ;-------------------------------------------------------------------------------\r
-; Copyright (c) 2007-2016 Cypress Semiconductor.  All rights reserved.\r
+; Copyright (c) 2007-2017 Cypress Semiconductor.  All rights reserved.\r
 ; You may use this file only in accordance with the license, terms, conditions, \r
 ; disclaimers, and limitations in the end user license agreement accompanying \r
 ; the software package with which this file was provided.\r

diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicerv_trm.inc b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicerv_trm.inc
index 473b655a82f5143440c2a2f4168bbcae2c6c2027..4a32cab37d619636c0e6e0654992509eba7646fa 100755 (executable)
--- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicerv_trm.inc
+++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicerv_trm.inc
@@ -1,13 +1,13 @@
 ;\r
 ; File Name: cydevicerv_trm.inc\r
 ; \r
-; PSoC Creator  4.0 Update 1\r
+; PSoC Creator  4.1\r
 ;\r
 ; Description:\r
 ; This file provides all of the address values for the entire PSoC device.\r
 ;\r
 ;-------------------------------------------------------------------------------\r
-; Copyright (c) 2007-2016 Cypress Semiconductor.  All rights reserved.\r
+; Copyright (c) 2007-2017 Cypress Semiconductor.  All rights reserved.\r
 ; You may use this file only in accordance with the license, terms, conditions, \r
 ; disclaimers, and limitations in the end user license agreement accompanying \r
 ; the software package with which this file was provided.\r

diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter.h b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter.h
index 8a9a8f4d99891a62716cbfeb0aa97ff3ba4a9795..a11569b3635be2d45eee2574fa1dd5fd1a9f427f 100755 (executable)
--- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter.h
+++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter.h
@@ -1,8 +1,86 @@
+/*******************************************************************************\r
+* File Name: cyfitter.h\r
+* \r
+* PSoC Creator  4.1\r
+*\r
+* Description:\r
+* \r
+* This file is automatically generated by PSoC Creator.\r
+*\r
+********************************************************************************\r
+* Copyright (c) 2007-2017 Cypress Semiconductor.  All rights reserved.\r
+* You may use this file only in accordance with the license, terms, conditions, \r
+* disclaimers, and limitations in the end user license agreement accompanying \r
+* the software package with which this file was provided.\r
+********************************************************************************/\r
+\r
 #ifndef INCLUDED_CYFITTER_H\r
 #define INCLUDED_CYFITTER_H\r
 #include "cydevice.h"\r
 #include "cydevice_trm.h"\r
 \r
+/* Debug_Timer_Interrupt */\r
+#define Debug_Timer_Interrupt__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
+#define Debug_Timer_Interrupt__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
+#define Debug_Timer_Interrupt__INTC_MASK 0x01u\r
+#define Debug_Timer_Interrupt__INTC_NUMBER 0u\r
+#define Debug_Timer_Interrupt__INTC_PRIOR_NUM 7u\r
+#define Debug_Timer_Interrupt__INTC_PRIOR_REG CYREG_NVIC_PRI_0\r
+#define Debug_Timer_Interrupt__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
+#define Debug_Timer_Interrupt__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
+\r
+/* Debug_Timer_TimerHW */\r
+#define Debug_Timer_TimerHW__CAP0 CYREG_TMR0_CAP0\r
+#define Debug_Timer_TimerHW__CAP1 CYREG_TMR0_CAP1\r
+#define Debug_Timer_TimerHW__CFG0 CYREG_TMR0_CFG0\r
+#define Debug_Timer_TimerHW__CFG1 CYREG_TMR0_CFG1\r
+#define Debug_Timer_TimerHW__CFG2 CYREG_TMR0_CFG2\r
+#define Debug_Timer_TimerHW__CNT_CMP0 CYREG_TMR0_CNT_CMP0\r
+#define Debug_Timer_TimerHW__CNT_CMP1 CYREG_TMR0_CNT_CMP1\r
+#define Debug_Timer_TimerHW__PER0 CYREG_TMR0_PER0\r
+#define Debug_Timer_TimerHW__PER1 CYREG_TMR0_PER1\r
+#define Debug_Timer_TimerHW__PM_ACT_CFG CYREG_PM_ACT_CFG3\r
+#define Debug_Timer_TimerHW__PM_ACT_MSK 0x01u\r
+#define Debug_Timer_TimerHW__PM_STBY_CFG CYREG_PM_STBY_CFG3\r
+#define Debug_Timer_TimerHW__PM_STBY_MSK 0x01u\r
+#define Debug_Timer_TimerHW__RT0 CYREG_TMR0_RT0\r
+#define Debug_Timer_TimerHW__RT1 CYREG_TMR0_RT1\r
+#define Debug_Timer_TimerHW__SR0 CYREG_TMR0_SR0\r
+\r
+/* EXTLED */\r
+#define EXTLED__0__INTTYPE CYREG_PICU0_INTTYPE0\r
+#define EXTLED__0__MASK 0x01u\r
+#define EXTLED__0__PC CYREG_PRT0_PC0\r
+#define EXTLED__0__PORT 0u\r
+#define EXTLED__0__SHIFT 0u\r
+#define EXTLED__AG CYREG_PRT0_AG\r
+#define EXTLED__AMUX CYREG_PRT0_AMUX\r
+#define EXTLED__BIE CYREG_PRT0_BIE\r
+#define EXTLED__BIT_MASK CYREG_PRT0_BIT_MASK\r
+#define EXTLED__BYP CYREG_PRT0_BYP\r
+#define EXTLED__CTL CYREG_PRT0_CTL\r
+#define EXTLED__DM0 CYREG_PRT0_DM0\r
+#define EXTLED__DM1 CYREG_PRT0_DM1\r
+#define EXTLED__DM2 CYREG_PRT0_DM2\r
+#define EXTLED__DR CYREG_PRT0_DR\r
+#define EXTLED__INP_DIS CYREG_PRT0_INP_DIS\r
+#define EXTLED__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU0_BASE\r
+#define EXTLED__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG\r
+#define EXTLED__LCD_EN CYREG_PRT0_LCD_EN\r
+#define EXTLED__MASK 0x01u\r
+#define EXTLED__PORT 0u\r
+#define EXTLED__PRT CYREG_PRT0_PRT\r
+#define EXTLED__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL\r
+#define EXTLED__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN\r
+#define EXTLED__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0\r
+#define EXTLED__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1\r
+#define EXTLED__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0\r
+#define EXTLED__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1\r
+#define EXTLED__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT\r
+#define EXTLED__PS CYREG_PRT0_PS\r
+#define EXTLED__SHIFT 0u\r
+#define EXTLED__SLW CYREG_PRT0_SLW\r
+\r
 /* LED1 */\r
 #define LED1__0__INTTYPE CYREG_PICU0_INTTYPE1\r
 #define LED1__0__MASK 0x02u\r
@@ -37,2421 +115,808 @@
 #define LED1__SHIFT 1u\r
 #define LED1__SLW CYREG_PRT0_SLW\r
 \r
-/* SD_CD */\r
-#define SD_CD__0__INTTYPE CYREG_PICU3_INTTYPE5\r
-#define SD_CD__0__MASK 0x20u\r
-#define SD_CD__0__PC CYREG_PRT3_PC5\r
-#define SD_CD__0__PORT 3u\r
-#define SD_CD__0__SHIFT 5u\r
-#define SD_CD__AG CYREG_PRT3_AG\r
-#define SD_CD__AMUX CYREG_PRT3_AMUX\r
-#define SD_CD__BIE CYREG_PRT3_BIE\r
-#define SD_CD__BIT_MASK CYREG_PRT3_BIT_MASK\r
-#define SD_CD__BYP CYREG_PRT3_BYP\r
-#define SD_CD__CTL CYREG_PRT3_CTL\r
-#define SD_CD__DM0 CYREG_PRT3_DM0\r
-#define SD_CD__DM1 CYREG_PRT3_DM1\r
-#define SD_CD__DM2 CYREG_PRT3_DM2\r
-#define SD_CD__DR CYREG_PRT3_DR\r
-#define SD_CD__INP_DIS CYREG_PRT3_INP_DIS\r
-#define SD_CD__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU3_BASE\r
-#define SD_CD__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG\r
-#define SD_CD__LCD_EN CYREG_PRT3_LCD_EN\r
-#define SD_CD__MASK 0x20u\r
-#define SD_CD__PORT 3u\r
-#define SD_CD__PRT CYREG_PRT3_PRT\r
-#define SD_CD__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL\r
-#define SD_CD__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN\r
-#define SD_CD__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0\r
-#define SD_CD__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1\r
-#define SD_CD__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0\r
-#define SD_CD__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1\r
-#define SD_CD__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT\r
-#define SD_CD__PS CYREG_PRT3_PS\r
-#define SD_CD__SHIFT 5u\r
-#define SD_CD__SLW CYREG_PRT3_SLW\r
-\r
-/* SD_CS */\r
-#define SD_CS__0__INTTYPE CYREG_PICU3_INTTYPE4\r
-#define SD_CS__0__MASK 0x10u\r
-#define SD_CS__0__PC CYREG_PRT3_PC4\r
-#define SD_CS__0__PORT 3u\r
-#define SD_CS__0__SHIFT 4u\r
-#define SD_CS__AG CYREG_PRT3_AG\r
-#define SD_CS__AMUX CYREG_PRT3_AMUX\r
-#define SD_CS__BIE CYREG_PRT3_BIE\r
-#define SD_CS__BIT_MASK CYREG_PRT3_BIT_MASK\r
-#define SD_CS__BYP CYREG_PRT3_BYP\r
-#define SD_CS__CTL CYREG_PRT3_CTL\r
-#define SD_CS__DM0 CYREG_PRT3_DM0\r
-#define SD_CS__DM1 CYREG_PRT3_DM1\r
-#define SD_CS__DM2 CYREG_PRT3_DM2\r
-#define SD_CS__DR CYREG_PRT3_DR\r
-#define SD_CS__INP_DIS CYREG_PRT3_INP_DIS\r
-#define SD_CS__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU3_BASE\r
-#define SD_CS__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG\r
-#define SD_CS__LCD_EN CYREG_PRT3_LCD_EN\r
-#define SD_CS__MASK 0x10u\r
-#define SD_CS__PORT 3u\r
-#define SD_CS__PRT CYREG_PRT3_PRT\r
-#define SD_CS__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL\r
-#define SD_CS__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN\r
-#define SD_CS__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0\r
-#define SD_CS__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1\r
-#define SD_CS__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0\r
-#define SD_CS__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1\r
-#define SD_CS__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT\r
-#define SD_CS__PS CYREG_PRT3_PS\r
-#define SD_CS__SHIFT 4u\r
-#define SD_CS__SLW CYREG_PRT3_SLW\r
+/* SCSI_CLK */\r
+#define SCSI_CLK__CFG0 CYREG_CLKDIST_DCFG1_CFG0\r
+#define SCSI_CLK__CFG1 CYREG_CLKDIST_DCFG1_CFG1\r
+#define SCSI_CLK__CFG2 CYREG_CLKDIST_DCFG1_CFG2\r
+#define SCSI_CLK__CFG2_SRC_SEL_MASK 0x07u\r
+#define SCSI_CLK__INDEX 0x01u\r
+#define SCSI_CLK__PM_ACT_CFG CYREG_PM_ACT_CFG2\r
+#define SCSI_CLK__PM_ACT_MSK 0x02u\r
+#define SCSI_CLK__PM_STBY_CFG CYREG_PM_STBY_CFG2\r
+#define SCSI_CLK__PM_STBY_MSK 0x02u\r
 \r
-/* USBFS_arb_int */\r
-#define USBFS_arb_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
-#define USBFS_arb_int__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
-#define USBFS_arb_int__INTC_MASK 0x400000u\r
-#define USBFS_arb_int__INTC_NUMBER 22u\r
-#define USBFS_arb_int__INTC_PRIOR_NUM 6u\r
-#define USBFS_arb_int__INTC_PRIOR_REG CYREG_NVIC_PRI_22\r
-#define USBFS_arb_int__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
-#define USBFS_arb_int__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
+/* SCSI_CTL_PHASE */\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK 0x01u\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS 0\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK 0x02u\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS 1\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB06_07_ACTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB06_07_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB06_07_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB06_07_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB06_07_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB06_07_MSK\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB06_07_MSK\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB06_07_MSK\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB06_07_MSK\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK 0x04u\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS 2\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB06_ACTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB06_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB06_ST_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB06_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB06_ST_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK 0x07u\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB06_MSK\r
 \r
-/* USBFS_bus_reset */\r
-#define USBFS_bus_reset__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
-#define USBFS_bus_reset__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
-#define USBFS_bus_reset__INTC_MASK 0x800000u\r
-#define USBFS_bus_reset__INTC_NUMBER 23u\r
-#define USBFS_bus_reset__INTC_PRIOR_NUM 7u\r
-#define USBFS_bus_reset__INTC_PRIOR_REG CYREG_NVIC_PRI_23\r
-#define USBFS_bus_reset__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
-#define USBFS_bus_reset__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
+/* SCSI_Filtered */\r
+#define SCSI_Filtered_sts_sts_reg__0__MASK 0x01u\r
+#define SCSI_Filtered_sts_sts_reg__0__POS 0\r
+#define SCSI_Filtered_sts_sts_reg__1__MASK 0x02u\r
+#define SCSI_Filtered_sts_sts_reg__1__POS 1\r
+#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB11_12_ACTL\r
+#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB11_12_ST\r
+#define SCSI_Filtered_sts_sts_reg__2__MASK 0x04u\r
+#define SCSI_Filtered_sts_sts_reg__2__POS 2\r
+#define SCSI_Filtered_sts_sts_reg__3__MASK 0x08u\r
+#define SCSI_Filtered_sts_sts_reg__3__POS 3\r
+#define SCSI_Filtered_sts_sts_reg__4__MASK 0x10u\r
+#define SCSI_Filtered_sts_sts_reg__4__POS 4\r
+#define SCSI_Filtered_sts_sts_reg__MASK 0x1Fu\r
+#define SCSI_Filtered_sts_sts_reg__MASK_REG CYREG_B0_UDB11_MSK\r
+#define SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB11_ACTL\r
+#define SCSI_Filtered_sts_sts_reg__STATUS_REG CYREG_B0_UDB11_ST\r
 \r
-/* USBFS_Dm */\r
-#define USBFS_Dm__0__INTTYPE CYREG_PICU15_INTTYPE7\r
-#define USBFS_Dm__0__MASK 0x80u\r
-#define USBFS_Dm__0__PC CYREG_IO_PC_PRT15_7_6_PC1\r
-#define USBFS_Dm__0__PORT 15u\r
-#define USBFS_Dm__0__SHIFT 7u\r
-#define USBFS_Dm__AG CYREG_PRT15_AG\r
-#define USBFS_Dm__AMUX CYREG_PRT15_AMUX\r
-#define USBFS_Dm__BIE CYREG_PRT15_BIE\r
-#define USBFS_Dm__BIT_MASK CYREG_PRT15_BIT_MASK\r
-#define USBFS_Dm__BYP CYREG_PRT15_BYP\r
-#define USBFS_Dm__CTL CYREG_PRT15_CTL\r
-#define USBFS_Dm__DM0 CYREG_PRT15_DM0\r
-#define USBFS_Dm__DM1 CYREG_PRT15_DM1\r
-#define USBFS_Dm__DM2 CYREG_PRT15_DM2\r
-#define USBFS_Dm__DR CYREG_PRT15_DR\r
-#define USBFS_Dm__INP_DIS CYREG_PRT15_INP_DIS\r
-#define USBFS_Dm__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU15_BASE\r
-#define USBFS_Dm__LCD_COM_SEG CYREG_PRT15_LCD_COM_SEG\r
-#define USBFS_Dm__LCD_EN CYREG_PRT15_LCD_EN\r
-#define USBFS_Dm__MASK 0x80u\r
-#define USBFS_Dm__PORT 15u\r
-#define USBFS_Dm__PRT CYREG_PRT15_PRT\r
-#define USBFS_Dm__PRTDSI__CAPS_SEL CYREG_PRT15_CAPS_SEL\r
-#define USBFS_Dm__PRTDSI__DBL_SYNC_IN CYREG_PRT15_DBL_SYNC_IN\r
-#define USBFS_Dm__PRTDSI__OE_SEL0 CYREG_PRT15_OE_SEL0\r
-#define USBFS_Dm__PRTDSI__OE_SEL1 CYREG_PRT15_OE_SEL1\r
-#define USBFS_Dm__PRTDSI__OUT_SEL0 CYREG_PRT15_OUT_SEL0\r
-#define USBFS_Dm__PRTDSI__OUT_SEL1 CYREG_PRT15_OUT_SEL1\r
-#define USBFS_Dm__PRTDSI__SYNC_OUT CYREG_PRT15_SYNC_OUT\r
-#define USBFS_Dm__PS CYREG_PRT15_PS\r
-#define USBFS_Dm__SHIFT 7u\r
-#define USBFS_Dm__SLW CYREG_PRT15_SLW\r
+/* SCSI_Glitch_Ctl */\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK 0x01u\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS 0\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB04_05_ACTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB04_05_CTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB04_05_CTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB04_05_CTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB04_05_CTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB04_05_MSK\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB04_05_MSK\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB04_05_MSK\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB04_05_MSK\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB04_ACTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB04_CTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB04_ST_CTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB04_CTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB04_ST_CTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK 0x01u\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB04_MSK\r
 \r
-/* USBFS_Dp */\r
-#define USBFS_Dp__0__INTTYPE CYREG_PICU15_INTTYPE6\r
-#define USBFS_Dp__0__MASK 0x40u\r
-#define USBFS_Dp__0__PC CYREG_IO_PC_PRT15_7_6_PC0\r
-#define USBFS_Dp__0__PORT 15u\r
-#define USBFS_Dp__0__SHIFT 6u\r
-#define USBFS_Dp__AG CYREG_PRT15_AG\r
-#define USBFS_Dp__AMUX CYREG_PRT15_AMUX\r
-#define USBFS_Dp__BIE CYREG_PRT15_BIE\r
-#define USBFS_Dp__BIT_MASK CYREG_PRT15_BIT_MASK\r
-#define USBFS_Dp__BYP CYREG_PRT15_BYP\r
-#define USBFS_Dp__CTL CYREG_PRT15_CTL\r
-#define USBFS_Dp__DM0 CYREG_PRT15_DM0\r
-#define USBFS_Dp__DM1 CYREG_PRT15_DM1\r
-#define USBFS_Dp__DM2 CYREG_PRT15_DM2\r
-#define USBFS_Dp__DR CYREG_PRT15_DR\r
-#define USBFS_Dp__INP_DIS CYREG_PRT15_INP_DIS\r
-#define USBFS_Dp__INTSTAT CYREG_PICU15_INTSTAT\r
-#define USBFS_Dp__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU15_BASE\r
-#define USBFS_Dp__LCD_COM_SEG CYREG_PRT15_LCD_COM_SEG\r
-#define USBFS_Dp__LCD_EN CYREG_PRT15_LCD_EN\r
-#define USBFS_Dp__MASK 0x40u\r
-#define USBFS_Dp__PORT 15u\r
-#define USBFS_Dp__PRT CYREG_PRT15_PRT\r
-#define USBFS_Dp__PRTDSI__CAPS_SEL CYREG_PRT15_CAPS_SEL\r
-#define USBFS_Dp__PRTDSI__DBL_SYNC_IN CYREG_PRT15_DBL_SYNC_IN\r
-#define USBFS_Dp__PRTDSI__OE_SEL0 CYREG_PRT15_OE_SEL0\r
-#define USBFS_Dp__PRTDSI__OE_SEL1 CYREG_PRT15_OE_SEL1\r
-#define USBFS_Dp__PRTDSI__OUT_SEL0 CYREG_PRT15_OUT_SEL0\r
-#define USBFS_Dp__PRTDSI__OUT_SEL1 CYREG_PRT15_OUT_SEL1\r
-#define USBFS_Dp__PRTDSI__SYNC_OUT CYREG_PRT15_SYNC_OUT\r
-#define USBFS_Dp__PS CYREG_PRT15_PS\r
-#define USBFS_Dp__SHIFT 6u\r
-#define USBFS_Dp__SLW CYREG_PRT15_SLW\r
-#define USBFS_Dp__SNAP CYREG_PICU_15_SNAP_15\r
-\r
-/* USBFS_dp_int */\r
-#define USBFS_dp_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
-#define USBFS_dp_int__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
-#define USBFS_dp_int__INTC_MASK 0x1000u\r
-#define USBFS_dp_int__INTC_NUMBER 12u\r
-#define USBFS_dp_int__INTC_PRIOR_NUM 7u\r
-#define USBFS_dp_int__INTC_PRIOR_REG CYREG_NVIC_PRI_12\r
-#define USBFS_dp_int__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
-#define USBFS_dp_int__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
-\r
-/* USBFS_ep_0 */\r
-#define USBFS_ep_0__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
-#define USBFS_ep_0__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
-#define USBFS_ep_0__INTC_MASK 0x1000000u\r
-#define USBFS_ep_0__INTC_NUMBER 24u\r
-#define USBFS_ep_0__INTC_PRIOR_NUM 7u\r
-#define USBFS_ep_0__INTC_PRIOR_REG CYREG_NVIC_PRI_24\r
-#define USBFS_ep_0__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
-#define USBFS_ep_0__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
-\r
-/* USBFS_ep_1 */\r
-#define USBFS_ep_1__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
-#define USBFS_ep_1__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
-#define USBFS_ep_1__INTC_MASK 0x80u\r
-#define USBFS_ep_1__INTC_NUMBER 7u\r
-#define USBFS_ep_1__INTC_PRIOR_NUM 7u\r
-#define USBFS_ep_1__INTC_PRIOR_REG CYREG_NVIC_PRI_7\r
-#define USBFS_ep_1__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
-#define USBFS_ep_1__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
-\r
-/* USBFS_ep_2 */\r
-#define USBFS_ep_2__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
-#define USBFS_ep_2__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
-#define USBFS_ep_2__INTC_MASK 0x100u\r
-#define USBFS_ep_2__INTC_NUMBER 8u\r
-#define USBFS_ep_2__INTC_PRIOR_NUM 7u\r
-#define USBFS_ep_2__INTC_PRIOR_REG CYREG_NVIC_PRI_8\r
-#define USBFS_ep_2__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
-#define USBFS_ep_2__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
-\r
-/* USBFS_ep_3 */\r
-#define USBFS_ep_3__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
-#define USBFS_ep_3__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
-#define USBFS_ep_3__INTC_MASK 0x200u\r
-#define USBFS_ep_3__INTC_NUMBER 9u\r
-#define USBFS_ep_3__INTC_PRIOR_NUM 7u\r
-#define USBFS_ep_3__INTC_PRIOR_REG CYREG_NVIC_PRI_9\r
-#define USBFS_ep_3__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
-#define USBFS_ep_3__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
-\r
-/* USBFS_ep_4 */\r
-#define USBFS_ep_4__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
-#define USBFS_ep_4__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
-#define USBFS_ep_4__INTC_MASK 0x400u\r
-#define USBFS_ep_4__INTC_NUMBER 10u\r
-#define USBFS_ep_4__INTC_PRIOR_NUM 7u\r
-#define USBFS_ep_4__INTC_PRIOR_REG CYREG_NVIC_PRI_10\r
-#define USBFS_ep_4__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
-#define USBFS_ep_4__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
-\r
-/* USBFS_sof_int */\r
-#define USBFS_sof_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
-#define USBFS_sof_int__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
-#define USBFS_sof_int__INTC_MASK 0x200000u\r
-#define USBFS_sof_int__INTC_NUMBER 21u\r
-#define USBFS_sof_int__INTC_PRIOR_NUM 7u\r
-#define USBFS_sof_int__INTC_PRIOR_REG CYREG_NVIC_PRI_21\r
-#define USBFS_sof_int__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
-#define USBFS_sof_int__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
-\r
-/* USBFS_USB */\r
-#define USBFS_USB__ARB_CFG CYREG_USB_ARB_CFG\r
-#define USBFS_USB__ARB_EP1_CFG CYREG_USB_ARB_EP1_CFG\r
-#define USBFS_USB__ARB_EP1_INT_EN CYREG_USB_ARB_EP1_INT_EN\r
-#define USBFS_USB__ARB_EP1_SR CYREG_USB_ARB_EP1_SR\r
-#define USBFS_USB__ARB_EP2_CFG CYREG_USB_ARB_EP2_CFG\r
-#define USBFS_USB__ARB_EP2_INT_EN CYREG_USB_ARB_EP2_INT_EN\r
-#define USBFS_USB__ARB_EP2_SR CYREG_USB_ARB_EP2_SR\r
-#define USBFS_USB__ARB_EP3_CFG CYREG_USB_ARB_EP3_CFG\r
-#define USBFS_USB__ARB_EP3_INT_EN CYREG_USB_ARB_EP3_INT_EN\r
-#define USBFS_USB__ARB_EP3_SR CYREG_USB_ARB_EP3_SR\r
-#define USBFS_USB__ARB_EP4_CFG CYREG_USB_ARB_EP4_CFG\r
-#define USBFS_USB__ARB_EP4_INT_EN CYREG_USB_ARB_EP4_INT_EN\r
-#define USBFS_USB__ARB_EP4_SR CYREG_USB_ARB_EP4_SR\r
-#define USBFS_USB__ARB_EP5_CFG CYREG_USB_ARB_EP5_CFG\r
-#define USBFS_USB__ARB_EP5_INT_EN CYREG_USB_ARB_EP5_INT_EN\r
-#define USBFS_USB__ARB_EP5_SR CYREG_USB_ARB_EP5_SR\r
-#define USBFS_USB__ARB_EP6_CFG CYREG_USB_ARB_EP6_CFG\r
-#define USBFS_USB__ARB_EP6_INT_EN CYREG_USB_ARB_EP6_INT_EN\r
-#define USBFS_USB__ARB_EP6_SR CYREG_USB_ARB_EP6_SR\r
-#define USBFS_USB__ARB_EP7_CFG CYREG_USB_ARB_EP7_CFG\r
-#define USBFS_USB__ARB_EP7_INT_EN CYREG_USB_ARB_EP7_INT_EN\r
-#define USBFS_USB__ARB_EP7_SR CYREG_USB_ARB_EP7_SR\r
-#define USBFS_USB__ARB_EP8_CFG CYREG_USB_ARB_EP8_CFG\r
-#define USBFS_USB__ARB_EP8_INT_EN CYREG_USB_ARB_EP8_INT_EN\r
-#define USBFS_USB__ARB_EP8_SR CYREG_USB_ARB_EP8_SR\r
-#define USBFS_USB__ARB_INT_EN CYREG_USB_ARB_INT_EN\r
-#define USBFS_USB__ARB_INT_SR CYREG_USB_ARB_INT_SR\r
-#define USBFS_USB__ARB_RW1_DR CYREG_USB_ARB_RW1_DR\r
-#define USBFS_USB__ARB_RW1_RA CYREG_USB_ARB_RW1_RA\r
-#define USBFS_USB__ARB_RW1_RA_MSB CYREG_USB_ARB_RW1_RA_MSB\r
-#define USBFS_USB__ARB_RW1_WA CYREG_USB_ARB_RW1_WA\r
-#define USBFS_USB__ARB_RW1_WA_MSB CYREG_USB_ARB_RW1_WA_MSB\r
-#define USBFS_USB__ARB_RW2_DR CYREG_USB_ARB_RW2_DR\r
-#define USBFS_USB__ARB_RW2_RA CYREG_USB_ARB_RW2_RA\r
-#define USBFS_USB__ARB_RW2_RA_MSB CYREG_USB_ARB_RW2_RA_MSB\r
-#define USBFS_USB__ARB_RW2_WA CYREG_USB_ARB_RW2_WA\r
-#define USBFS_USB__ARB_RW2_WA_MSB CYREG_USB_ARB_RW2_WA_MSB\r
-#define USBFS_USB__ARB_RW3_DR CYREG_USB_ARB_RW3_DR\r
-#define USBFS_USB__ARB_RW3_RA CYREG_USB_ARB_RW3_RA\r
-#define USBFS_USB__ARB_RW3_RA_MSB CYREG_USB_ARB_RW3_RA_MSB\r
-#define USBFS_USB__ARB_RW3_WA CYREG_USB_ARB_RW3_WA\r
-#define USBFS_USB__ARB_RW3_WA_MSB CYREG_USB_ARB_RW3_WA_MSB\r
-#define USBFS_USB__ARB_RW4_DR CYREG_USB_ARB_RW4_DR\r
-#define USBFS_USB__ARB_RW4_RA CYREG_USB_ARB_RW4_RA\r
-#define USBFS_USB__ARB_RW4_RA_MSB CYREG_USB_ARB_RW4_RA_MSB\r
-#define USBFS_USB__ARB_RW4_WA CYREG_USB_ARB_RW4_WA\r
-#define USBFS_USB__ARB_RW4_WA_MSB CYREG_USB_ARB_RW4_WA_MSB\r
-#define USBFS_USB__ARB_RW5_DR CYREG_USB_ARB_RW5_DR\r
-#define USBFS_USB__ARB_RW5_RA CYREG_USB_ARB_RW5_RA\r
-#define USBFS_USB__ARB_RW5_RA_MSB CYREG_USB_ARB_RW5_RA_MSB\r
-#define USBFS_USB__ARB_RW5_WA CYREG_USB_ARB_RW5_WA\r
-#define USBFS_USB__ARB_RW5_WA_MSB CYREG_USB_ARB_RW5_WA_MSB\r
-#define USBFS_USB__ARB_RW6_DR CYREG_USB_ARB_RW6_DR\r
-#define USBFS_USB__ARB_RW6_RA CYREG_USB_ARB_RW6_RA\r
-#define USBFS_USB__ARB_RW6_RA_MSB CYREG_USB_ARB_RW6_RA_MSB\r
-#define USBFS_USB__ARB_RW6_WA CYREG_USB_ARB_RW6_WA\r
-#define USBFS_USB__ARB_RW6_WA_MSB CYREG_USB_ARB_RW6_WA_MSB\r
-#define USBFS_USB__ARB_RW7_DR CYREG_USB_ARB_RW7_DR\r
-#define USBFS_USB__ARB_RW7_RA CYREG_USB_ARB_RW7_RA\r
-#define USBFS_USB__ARB_RW7_RA_MSB CYREG_USB_ARB_RW7_RA_MSB\r
-#define USBFS_USB__ARB_RW7_WA CYREG_USB_ARB_RW7_WA\r
-#define USBFS_USB__ARB_RW7_WA_MSB CYREG_USB_ARB_RW7_WA_MSB\r
-#define USBFS_USB__ARB_RW8_DR CYREG_USB_ARB_RW8_DR\r
-#define USBFS_USB__ARB_RW8_RA CYREG_USB_ARB_RW8_RA\r
-#define USBFS_USB__ARB_RW8_RA_MSB CYREG_USB_ARB_RW8_RA_MSB\r
-#define USBFS_USB__ARB_RW8_WA CYREG_USB_ARB_RW8_WA\r
-#define USBFS_USB__ARB_RW8_WA_MSB CYREG_USB_ARB_RW8_WA_MSB\r
-#define USBFS_USB__BUF_SIZE CYREG_USB_BUF_SIZE\r
-#define USBFS_USB__BUS_RST_CNT CYREG_USB_BUS_RST_CNT\r
-#define USBFS_USB__CR0 CYREG_USB_CR0\r
-#define USBFS_USB__CR1 CYREG_USB_CR1\r
-#define USBFS_USB__CWA CYREG_USB_CWA\r
-#define USBFS_USB__CWA_MSB CYREG_USB_CWA_MSB\r
-#define USBFS_USB__DMA_THRES CYREG_USB_DMA_THRES\r
-#define USBFS_USB__DMA_THRES_MSB CYREG_USB_DMA_THRES_MSB\r
-#define USBFS_USB__DYN_RECONFIG CYREG_USB_DYN_RECONFIG\r
-#define USBFS_USB__EP_ACTIVE CYREG_USB_EP_ACTIVE\r
-#define USBFS_USB__EP_TYPE CYREG_USB_EP_TYPE\r
-#define USBFS_USB__EP0_CNT CYREG_USB_EP0_CNT\r
-#define USBFS_USB__EP0_CR CYREG_USB_EP0_CR\r
-#define USBFS_USB__EP0_DR0 CYREG_USB_EP0_DR0\r
-#define USBFS_USB__EP0_DR1 CYREG_USB_EP0_DR1\r
-#define USBFS_USB__EP0_DR2 CYREG_USB_EP0_DR2\r
-#define USBFS_USB__EP0_DR3 CYREG_USB_EP0_DR3\r
-#define USBFS_USB__EP0_DR4 CYREG_USB_EP0_DR4\r
-#define USBFS_USB__EP0_DR5 CYREG_USB_EP0_DR5\r
-#define USBFS_USB__EP0_DR6 CYREG_USB_EP0_DR6\r
-#define USBFS_USB__EP0_DR7 CYREG_USB_EP0_DR7\r
-#define USBFS_USB__MEM_DATA CYREG_USB_MEM_DATA_MBASE\r
-#define USBFS_USB__PM_ACT_CFG CYREG_PM_ACT_CFG5\r
-#define USBFS_USB__PM_ACT_MSK 0x01u\r
-#define USBFS_USB__PM_STBY_CFG CYREG_PM_STBY_CFG5\r
-#define USBFS_USB__PM_STBY_MSK 0x01u\r
-#define USBFS_USB__SIE_EP_INT_EN CYREG_USB_SIE_EP_INT_EN\r
-#define USBFS_USB__SIE_EP_INT_SR CYREG_USB_SIE_EP_INT_SR\r
-#define USBFS_USB__SIE_EP1_CNT0 CYREG_USB_SIE_EP1_CNT0\r
-#define USBFS_USB__SIE_EP1_CNT1 CYREG_USB_SIE_EP1_CNT1\r
-#define USBFS_USB__SIE_EP1_CR0 CYREG_USB_SIE_EP1_CR0\r
-#define USBFS_USB__SIE_EP2_CNT0 CYREG_USB_SIE_EP2_CNT0\r
-#define USBFS_USB__SIE_EP2_CNT1 CYREG_USB_SIE_EP2_CNT1\r
-#define USBFS_USB__SIE_EP2_CR0 CYREG_USB_SIE_EP2_CR0\r
-#define USBFS_USB__SIE_EP3_CNT0 CYREG_USB_SIE_EP3_CNT0\r
-#define USBFS_USB__SIE_EP3_CNT1 CYREG_USB_SIE_EP3_CNT1\r
-#define USBFS_USB__SIE_EP3_CR0 CYREG_USB_SIE_EP3_CR0\r
-#define USBFS_USB__SIE_EP4_CNT0 CYREG_USB_SIE_EP4_CNT0\r
-#define USBFS_USB__SIE_EP4_CNT1 CYREG_USB_SIE_EP4_CNT1\r
-#define USBFS_USB__SIE_EP4_CR0 CYREG_USB_SIE_EP4_CR0\r
-#define USBFS_USB__SIE_EP5_CNT0 CYREG_USB_SIE_EP5_CNT0\r
-#define USBFS_USB__SIE_EP5_CNT1 CYREG_USB_SIE_EP5_CNT1\r
-#define USBFS_USB__SIE_EP5_CR0 CYREG_USB_SIE_EP5_CR0\r
-#define USBFS_USB__SIE_EP6_CNT0 CYREG_USB_SIE_EP6_CNT0\r
-#define USBFS_USB__SIE_EP6_CNT1 CYREG_USB_SIE_EP6_CNT1\r
-#define USBFS_USB__SIE_EP6_CR0 CYREG_USB_SIE_EP6_CR0\r
-#define USBFS_USB__SIE_EP7_CNT0 CYREG_USB_SIE_EP7_CNT0\r
-#define USBFS_USB__SIE_EP7_CNT1 CYREG_USB_SIE_EP7_CNT1\r
-#define USBFS_USB__SIE_EP7_CR0 CYREG_USB_SIE_EP7_CR0\r
-#define USBFS_USB__SIE_EP8_CNT0 CYREG_USB_SIE_EP8_CNT0\r
-#define USBFS_USB__SIE_EP8_CNT1 CYREG_USB_SIE_EP8_CNT1\r
-#define USBFS_USB__SIE_EP8_CR0 CYREG_USB_SIE_EP8_CR0\r
-#define USBFS_USB__SOF0 CYREG_USB_SOF0\r
-#define USBFS_USB__SOF1 CYREG_USB_SOF1\r
-#define USBFS_USB__USB_CLK_EN CYREG_USB_USB_CLK_EN\r
-#define USBFS_USB__USBIO_CR0 CYREG_USB_USBIO_CR0\r
-#define USBFS_USB__USBIO_CR1 CYREG_USB_USBIO_CR1\r
-\r
-/* EXTLED */\r
-#define EXTLED__0__INTTYPE CYREG_PICU0_INTTYPE0\r
-#define EXTLED__0__MASK 0x01u\r
-#define EXTLED__0__PC CYREG_PRT0_PC0\r
-#define EXTLED__0__PORT 0u\r
-#define EXTLED__0__SHIFT 0u\r
-#define EXTLED__AG CYREG_PRT0_AG\r
-#define EXTLED__AMUX CYREG_PRT0_AMUX\r
-#define EXTLED__BIE CYREG_PRT0_BIE\r
-#define EXTLED__BIT_MASK CYREG_PRT0_BIT_MASK\r
-#define EXTLED__BYP CYREG_PRT0_BYP\r
-#define EXTLED__CTL CYREG_PRT0_CTL\r
-#define EXTLED__DM0 CYREG_PRT0_DM0\r
-#define EXTLED__DM1 CYREG_PRT0_DM1\r
-#define EXTLED__DM2 CYREG_PRT0_DM2\r
-#define EXTLED__DR CYREG_PRT0_DR\r
-#define EXTLED__INP_DIS CYREG_PRT0_INP_DIS\r
-#define EXTLED__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU0_BASE\r
-#define EXTLED__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG\r
-#define EXTLED__LCD_EN CYREG_PRT0_LCD_EN\r
-#define EXTLED__MASK 0x01u\r
-#define EXTLED__PORT 0u\r
-#define EXTLED__PRT CYREG_PRT0_PRT\r
-#define EXTLED__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL\r
-#define EXTLED__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN\r
-#define EXTLED__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0\r
-#define EXTLED__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1\r
-#define EXTLED__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0\r
-#define EXTLED__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1\r
-#define EXTLED__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT\r
-#define EXTLED__PS CYREG_PRT0_PS\r
-#define EXTLED__SHIFT 0u\r
-#define EXTLED__SLW CYREG_PRT0_SLW\r
-\r
-/* SDCard_BSPIM */\r
-#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB05_06_ACTL\r
-#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB05_06_CTL\r
-#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB05_06_CTL\r
-#define SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB05_06_CTL\r
-#define SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B1_UDB05_06_CTL\r
-#define SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B1_UDB05_06_MSK\r
-#define SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B1_UDB05_06_MSK\r
-#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B1_UDB05_06_MSK\r
-#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB05_06_MSK\r
-#define SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B1_UDB05_ACTL\r
-#define SDCard_BSPIM_BitCounter__CONTROL_REG CYREG_B1_UDB05_CTL\r
-#define SDCard_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B1_UDB05_ST_CTL\r
-#define SDCard_BSPIM_BitCounter__COUNT_REG CYREG_B1_UDB05_CTL\r
-#define SDCard_BSPIM_BitCounter__COUNT_ST_REG CYREG_B1_UDB05_ST_CTL\r
-#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB05_MSK_ACTL\r
-#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B1_UDB05_MSK_ACTL\r
-#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B1_UDB05_MSK\r
-#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB05_06_ACTL\r
-#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B1_UDB05_06_ST\r
-#define SDCard_BSPIM_BitCounter_ST__MASK_REG CYREG_B1_UDB05_MSK\r
-#define SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B1_UDB05_MSK_ACTL\r
-#define SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B1_UDB05_MSK_ACTL\r
-#define SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B1_UDB05_ACTL\r
-#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B1_UDB05_ST_CTL\r
-#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B1_UDB05_ST_CTL\r
-#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B1_UDB05_ST\r
-#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB07_08_ACTL\r
-#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B1_UDB07_08_ST\r
-#define SDCard_BSPIM_RxStsReg__4__MASK 0x10u\r
-#define SDCard_BSPIM_RxStsReg__4__POS 4\r
-#define SDCard_BSPIM_RxStsReg__5__MASK 0x20u\r
-#define SDCard_BSPIM_RxStsReg__5__POS 5\r
-#define SDCard_BSPIM_RxStsReg__6__MASK 0x40u\r
-#define SDCard_BSPIM_RxStsReg__6__POS 6\r
-#define SDCard_BSPIM_RxStsReg__MASK 0x70u\r
-#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B1_UDB07_MSK\r
-#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB07_ACTL\r
-#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B1_UDB07_ST\r
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B1_UDB04_05_A0\r
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B1_UDB04_05_A1\r
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG CYREG_B1_UDB04_05_D0\r
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG CYREG_B1_UDB04_05_D1\r
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG CYREG_B1_UDB04_05_ACTL\r
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG CYREG_B1_UDB04_05_F0\r
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG CYREG_B1_UDB04_05_F1\r
-#define SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG CYREG_B1_UDB04_A0_A1\r
-#define SDCard_BSPIM_sR8_Dp_u0__A0_REG CYREG_B1_UDB04_A0\r
-#define SDCard_BSPIM_sR8_Dp_u0__A1_REG CYREG_B1_UDB04_A1\r
-#define SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG CYREG_B1_UDB04_D0_D1\r
-#define SDCard_BSPIM_sR8_Dp_u0__D0_REG CYREG_B1_UDB04_D0\r
-#define SDCard_BSPIM_sR8_Dp_u0__D1_REG CYREG_B1_UDB04_D1\r
-#define SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG CYREG_B1_UDB04_ACTL\r
-#define SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG CYREG_B1_UDB04_F0_F1\r
-#define SDCard_BSPIM_sR8_Dp_u0__F0_REG CYREG_B1_UDB04_F0\r
-#define SDCard_BSPIM_sR8_Dp_u0__F1_REG CYREG_B1_UDB04_F1\r
-#define SDCard_BSPIM_TxStsReg__0__MASK 0x01u\r
-#define SDCard_BSPIM_TxStsReg__0__POS 0\r
-#define SDCard_BSPIM_TxStsReg__1__MASK 0x02u\r
-#define SDCard_BSPIM_TxStsReg__1__POS 1\r
-#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB06_07_ACTL\r
-#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B1_UDB06_07_ST\r
-#define SDCard_BSPIM_TxStsReg__2__MASK 0x04u\r
-#define SDCard_BSPIM_TxStsReg__2__POS 2\r
-#define SDCard_BSPIM_TxStsReg__3__MASK 0x08u\r
-#define SDCard_BSPIM_TxStsReg__3__POS 3\r
-#define SDCard_BSPIM_TxStsReg__4__MASK 0x10u\r
-#define SDCard_BSPIM_TxStsReg__4__POS 4\r
-#define SDCard_BSPIM_TxStsReg__MASK 0x1Fu\r
-#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B1_UDB06_MSK\r
-#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB06_ACTL\r
-#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B1_UDB06_ST\r
-\r
-/* SD_SCK */\r
-#define SD_SCK__0__INTTYPE CYREG_PICU3_INTTYPE2\r
-#define SD_SCK__0__MASK 0x04u\r
-#define SD_SCK__0__PC CYREG_PRT3_PC2\r
-#define SD_SCK__0__PORT 3u\r
-#define SD_SCK__0__SHIFT 2u\r
-#define SD_SCK__AG CYREG_PRT3_AG\r
-#define SD_SCK__AMUX CYREG_PRT3_AMUX\r
-#define SD_SCK__BIE CYREG_PRT3_BIE\r
-#define SD_SCK__BIT_MASK CYREG_PRT3_BIT_MASK\r
-#define SD_SCK__BYP CYREG_PRT3_BYP\r
-#define SD_SCK__CTL CYREG_PRT3_CTL\r
-#define SD_SCK__DM0 CYREG_PRT3_DM0\r
-#define SD_SCK__DM1 CYREG_PRT3_DM1\r
-#define SD_SCK__DM2 CYREG_PRT3_DM2\r
-#define SD_SCK__DR CYREG_PRT3_DR\r
-#define SD_SCK__INP_DIS CYREG_PRT3_INP_DIS\r
-#define SD_SCK__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU3_BASE\r
-#define SD_SCK__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG\r
-#define SD_SCK__LCD_EN CYREG_PRT3_LCD_EN\r
-#define SD_SCK__MASK 0x04u\r
-#define SD_SCK__PORT 3u\r
-#define SD_SCK__PRT CYREG_PRT3_PRT\r
-#define SD_SCK__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL\r
-#define SD_SCK__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN\r
-#define SD_SCK__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0\r
-#define SD_SCK__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1\r
-#define SD_SCK__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0\r
-#define SD_SCK__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1\r
-#define SD_SCK__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT\r
-#define SD_SCK__PS CYREG_PRT3_PS\r
-#define SD_SCK__SHIFT 2u\r
-#define SD_SCK__SLW CYREG_PRT3_SLW\r
-\r
-/* SCSI_In */\r
-#define SCSI_In__0__AG CYREG_PRT2_AG\r
-#define SCSI_In__0__AMUX CYREG_PRT2_AMUX\r
-#define SCSI_In__0__BIE CYREG_PRT2_BIE\r
-#define SCSI_In__0__BIT_MASK CYREG_PRT2_BIT_MASK\r
-#define SCSI_In__0__BYP CYREG_PRT2_BYP\r
-#define SCSI_In__0__CTL CYREG_PRT2_CTL\r
-#define SCSI_In__0__DM0 CYREG_PRT2_DM0\r
-#define SCSI_In__0__DM1 CYREG_PRT2_DM1\r
-#define SCSI_In__0__DM2 CYREG_PRT2_DM2\r
-#define SCSI_In__0__DR CYREG_PRT2_DR\r
-#define SCSI_In__0__INP_DIS CYREG_PRT2_INP_DIS\r
-#define SCSI_In__0__INTTYPE CYREG_PICU2_INTTYPE1\r
-#define SCSI_In__0__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG\r
-#define SCSI_In__0__LCD_EN CYREG_PRT2_LCD_EN\r
-#define SCSI_In__0__MASK 0x02u\r
-#define SCSI_In__0__PC CYREG_PRT2_PC1\r
-#define SCSI_In__0__PORT 2u\r
-#define SCSI_In__0__PRT CYREG_PRT2_PRT\r
-#define SCSI_In__0__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL\r
-#define SCSI_In__0__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN\r
-#define SCSI_In__0__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0\r
-#define SCSI_In__0__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1\r
-#define SCSI_In__0__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0\r
-#define SCSI_In__0__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1\r
-#define SCSI_In__0__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT\r
-#define SCSI_In__0__PS CYREG_PRT2_PS\r
-#define SCSI_In__0__SHIFT 1u\r
-#define SCSI_In__0__SLW CYREG_PRT2_SLW\r
-#define SCSI_In__1__AG CYREG_PRT4_AG\r
-#define SCSI_In__1__AMUX CYREG_PRT4_AMUX\r
-#define SCSI_In__1__BIE CYREG_PRT4_BIE\r
-#define SCSI_In__1__BIT_MASK CYREG_PRT4_BIT_MASK\r
-#define SCSI_In__1__BYP CYREG_PRT4_BYP\r
-#define SCSI_In__1__CTL CYREG_PRT4_CTL\r
-#define SCSI_In__1__DM0 CYREG_PRT4_DM0\r
-#define SCSI_In__1__DM1 CYREG_PRT4_DM1\r
-#define SCSI_In__1__DM2 CYREG_PRT4_DM2\r
-#define SCSI_In__1__DR CYREG_PRT4_DR\r
-#define SCSI_In__1__INP_DIS CYREG_PRT4_INP_DIS\r
-#define SCSI_In__1__INTTYPE CYREG_PICU4_INTTYPE6\r
-#define SCSI_In__1__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG\r
-#define SCSI_In__1__LCD_EN CYREG_PRT4_LCD_EN\r
-#define SCSI_In__1__MASK 0x40u\r
-#define SCSI_In__1__PC CYREG_PRT4_PC6\r
-#define SCSI_In__1__PORT 4u\r
-#define SCSI_In__1__PRT CYREG_PRT4_PRT\r
-#define SCSI_In__1__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL\r
-#define SCSI_In__1__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN\r
-#define SCSI_In__1__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0\r
-#define SCSI_In__1__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1\r
-#define SCSI_In__1__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0\r
-#define SCSI_In__1__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1\r
-#define SCSI_In__1__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT\r
-#define SCSI_In__1__PS CYREG_PRT4_PS\r
-#define SCSI_In__1__SHIFT 6u\r
-#define SCSI_In__1__SLW CYREG_PRT4_SLW\r
-#define SCSI_In__2__AG CYREG_PRT4_AG\r
-#define SCSI_In__2__AMUX CYREG_PRT4_AMUX\r
-#define SCSI_In__2__BIE CYREG_PRT4_BIE\r
-#define SCSI_In__2__BIT_MASK CYREG_PRT4_BIT_MASK\r
-#define SCSI_In__2__BYP CYREG_PRT4_BYP\r
-#define SCSI_In__2__CTL CYREG_PRT4_CTL\r
-#define SCSI_In__2__DM0 CYREG_PRT4_DM0\r
-#define SCSI_In__2__DM1 CYREG_PRT4_DM1\r
-#define SCSI_In__2__DM2 CYREG_PRT4_DM2\r
-#define SCSI_In__2__DR CYREG_PRT4_DR\r
-#define SCSI_In__2__INP_DIS CYREG_PRT4_INP_DIS\r
-#define SCSI_In__2__INTTYPE CYREG_PICU4_INTTYPE2\r
-#define SCSI_In__2__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG\r
-#define SCSI_In__2__LCD_EN CYREG_PRT4_LCD_EN\r
-#define SCSI_In__2__MASK 0x04u\r
-#define SCSI_In__2__PC CYREG_PRT4_PC2\r
-#define SCSI_In__2__PORT 4u\r
-#define SCSI_In__2__PRT CYREG_PRT4_PRT\r
-#define SCSI_In__2__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL\r
-#define SCSI_In__2__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN\r
-#define SCSI_In__2__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0\r
-#define SCSI_In__2__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1\r
-#define SCSI_In__2__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0\r
-#define SCSI_In__2__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1\r
-#define SCSI_In__2__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT\r
-#define SCSI_In__2__PS CYREG_PRT4_PS\r
-#define SCSI_In__2__SHIFT 2u\r
-#define SCSI_In__2__SLW CYREG_PRT4_SLW\r
-#define SCSI_In__3__AG CYREG_PRT0_AG\r
-#define SCSI_In__3__AMUX CYREG_PRT0_AMUX\r
-#define SCSI_In__3__BIE CYREG_PRT0_BIE\r
-#define SCSI_In__3__BIT_MASK CYREG_PRT0_BIT_MASK\r
-#define SCSI_In__3__BYP CYREG_PRT0_BYP\r
-#define SCSI_In__3__CTL CYREG_PRT0_CTL\r
-#define SCSI_In__3__DM0 CYREG_PRT0_DM0\r
-#define SCSI_In__3__DM1 CYREG_PRT0_DM1\r
-#define SCSI_In__3__DM2 CYREG_PRT0_DM2\r
-#define SCSI_In__3__DR CYREG_PRT0_DR\r
-#define SCSI_In__3__INP_DIS CYREG_PRT0_INP_DIS\r
-#define SCSI_In__3__INTTYPE CYREG_PICU0_INTTYPE5\r
-#define SCSI_In__3__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG\r
-#define SCSI_In__3__LCD_EN CYREG_PRT0_LCD_EN\r
-#define SCSI_In__3__MASK 0x20u\r
-#define SCSI_In__3__PC CYREG_PRT0_PC5\r
-#define SCSI_In__3__PORT 0u\r
-#define SCSI_In__3__PRT CYREG_PRT0_PRT\r
-#define SCSI_In__3__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL\r
-#define SCSI_In__3__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN\r
-#define SCSI_In__3__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0\r
-#define SCSI_In__3__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1\r
-#define SCSI_In__3__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0\r
-#define SCSI_In__3__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1\r
-#define SCSI_In__3__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT\r
-#define SCSI_In__3__PS CYREG_PRT0_PS\r
-#define SCSI_In__3__SHIFT 5u\r
-#define SCSI_In__3__SLW CYREG_PRT0_SLW\r
-#define SCSI_In__4__AG CYREG_PRT0_AG\r
-#define SCSI_In__4__AMUX CYREG_PRT0_AMUX\r
-#define SCSI_In__4__BIE CYREG_PRT0_BIE\r
-#define SCSI_In__4__BIT_MASK CYREG_PRT0_BIT_MASK\r
-#define SCSI_In__4__BYP CYREG_PRT0_BYP\r
-#define SCSI_In__4__CTL CYREG_PRT0_CTL\r
-#define SCSI_In__4__DM0 CYREG_PRT0_DM0\r
-#define SCSI_In__4__DM1 CYREG_PRT0_DM1\r
-#define SCSI_In__4__DM2 CYREG_PRT0_DM2\r
-#define SCSI_In__4__DR CYREG_PRT0_DR\r
-#define SCSI_In__4__INP_DIS CYREG_PRT0_INP_DIS\r
-#define SCSI_In__4__INTTYPE CYREG_PICU0_INTTYPE4\r
-#define SCSI_In__4__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG\r
-#define SCSI_In__4__LCD_EN CYREG_PRT0_LCD_EN\r
-#define SCSI_In__4__MASK 0x10u\r
-#define SCSI_In__4__PC CYREG_PRT0_PC4\r
-#define SCSI_In__4__PORT 0u\r
-#define SCSI_In__4__PRT CYREG_PRT0_PRT\r
-#define SCSI_In__4__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL\r
-#define SCSI_In__4__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN\r
-#define SCSI_In__4__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0\r
-#define SCSI_In__4__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1\r
-#define SCSI_In__4__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0\r
-#define SCSI_In__4__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1\r
-#define SCSI_In__4__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT\r
-#define SCSI_In__4__PS CYREG_PRT0_PS\r
-#define SCSI_In__4__SHIFT 4u\r
-#define SCSI_In__4__SLW CYREG_PRT0_SLW\r
-#define SCSI_In__CD__AG CYREG_PRT4_AG\r
-#define SCSI_In__CD__AMUX CYREG_PRT4_AMUX\r
-#define SCSI_In__CD__BIE CYREG_PRT4_BIE\r
-#define SCSI_In__CD__BIT_MASK CYREG_PRT4_BIT_MASK\r
-#define SCSI_In__CD__BYP CYREG_PRT4_BYP\r
-#define SCSI_In__CD__CTL CYREG_PRT4_CTL\r
-#define SCSI_In__CD__DM0 CYREG_PRT4_DM0\r
-#define SCSI_In__CD__DM1 CYREG_PRT4_DM1\r
-#define SCSI_In__CD__DM2 CYREG_PRT4_DM2\r
-#define SCSI_In__CD__DR CYREG_PRT4_DR\r
-#define SCSI_In__CD__INP_DIS CYREG_PRT4_INP_DIS\r
-#define SCSI_In__CD__INTTYPE CYREG_PICU4_INTTYPE2\r
-#define SCSI_In__CD__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG\r
-#define SCSI_In__CD__LCD_EN CYREG_PRT4_LCD_EN\r
-#define SCSI_In__CD__MASK 0x04u\r
-#define SCSI_In__CD__PC CYREG_PRT4_PC2\r
-#define SCSI_In__CD__PORT 4u\r
-#define SCSI_In__CD__PRT CYREG_PRT4_PRT\r
-#define SCSI_In__CD__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL\r
-#define SCSI_In__CD__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN\r
-#define SCSI_In__CD__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0\r
-#define SCSI_In__CD__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1\r
-#define SCSI_In__CD__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0\r
-#define SCSI_In__CD__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1\r
-#define SCSI_In__CD__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT\r
-#define SCSI_In__CD__PS CYREG_PRT4_PS\r
-#define SCSI_In__CD__SHIFT 2u\r
-#define SCSI_In__CD__SLW CYREG_PRT4_SLW\r
-#define SCSI_In__DBP__AG CYREG_PRT2_AG\r
-#define SCSI_In__DBP__AMUX CYREG_PRT2_AMUX\r
-#define SCSI_In__DBP__BIE CYREG_PRT2_BIE\r
-#define SCSI_In__DBP__BIT_MASK CYREG_PRT2_BIT_MASK\r
-#define SCSI_In__DBP__BYP CYREG_PRT2_BYP\r
-#define SCSI_In__DBP__CTL CYREG_PRT2_CTL\r
-#define SCSI_In__DBP__DM0 CYREG_PRT2_DM0\r
-#define SCSI_In__DBP__DM1 CYREG_PRT2_DM1\r
-#define SCSI_In__DBP__DM2 CYREG_PRT2_DM2\r
-#define SCSI_In__DBP__DR CYREG_PRT2_DR\r
-#define SCSI_In__DBP__INP_DIS CYREG_PRT2_INP_DIS\r
-#define SCSI_In__DBP__INTTYPE CYREG_PICU2_INTTYPE1\r
-#define SCSI_In__DBP__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG\r
-#define SCSI_In__DBP__LCD_EN CYREG_PRT2_LCD_EN\r
-#define SCSI_In__DBP__MASK 0x02u\r
-#define SCSI_In__DBP__PC CYREG_PRT2_PC1\r
-#define SCSI_In__DBP__PORT 2u\r
-#define SCSI_In__DBP__PRT CYREG_PRT2_PRT\r
-#define SCSI_In__DBP__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL\r
-#define SCSI_In__DBP__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN\r
-#define SCSI_In__DBP__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0\r
-#define SCSI_In__DBP__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1\r
-#define SCSI_In__DBP__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0\r
-#define SCSI_In__DBP__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1\r
-#define SCSI_In__DBP__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT\r
-#define SCSI_In__DBP__PS CYREG_PRT2_PS\r
-#define SCSI_In__DBP__SHIFT 1u\r
-#define SCSI_In__DBP__SLW CYREG_PRT2_SLW\r
-#define SCSI_In__IO__AG CYREG_PRT0_AG\r
-#define SCSI_In__IO__AMUX CYREG_PRT0_AMUX\r
-#define SCSI_In__IO__BIE CYREG_PRT0_BIE\r
-#define SCSI_In__IO__BIT_MASK CYREG_PRT0_BIT_MASK\r
-#define SCSI_In__IO__BYP CYREG_PRT0_BYP\r
-#define SCSI_In__IO__CTL CYREG_PRT0_CTL\r
-#define SCSI_In__IO__DM0 CYREG_PRT0_DM0\r
-#define SCSI_In__IO__DM1 CYREG_PRT0_DM1\r
-#define SCSI_In__IO__DM2 CYREG_PRT0_DM2\r
-#define SCSI_In__IO__DR CYREG_PRT0_DR\r
-#define SCSI_In__IO__INP_DIS CYREG_PRT0_INP_DIS\r
-#define SCSI_In__IO__INTTYPE CYREG_PICU0_INTTYPE4\r
-#define SCSI_In__IO__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG\r
-#define SCSI_In__IO__LCD_EN CYREG_PRT0_LCD_EN\r
-#define SCSI_In__IO__MASK 0x10u\r
-#define SCSI_In__IO__PC CYREG_PRT0_PC4\r
-#define SCSI_In__IO__PORT 0u\r
-#define SCSI_In__IO__PRT CYREG_PRT0_PRT\r
-#define SCSI_In__IO__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL\r
-#define SCSI_In__IO__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN\r
-#define SCSI_In__IO__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0\r
-#define SCSI_In__IO__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1\r
-#define SCSI_In__IO__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0\r
-#define SCSI_In__IO__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1\r
-#define SCSI_In__IO__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT\r
-#define SCSI_In__IO__PS CYREG_PRT0_PS\r
-#define SCSI_In__IO__SHIFT 4u\r
-#define SCSI_In__IO__SLW CYREG_PRT0_SLW\r
-#define SCSI_In__MSG__AG CYREG_PRT4_AG\r
-#define SCSI_In__MSG__AMUX CYREG_PRT4_AMUX\r
-#define SCSI_In__MSG__BIE CYREG_PRT4_BIE\r
-#define SCSI_In__MSG__BIT_MASK CYREG_PRT4_BIT_MASK\r
-#define SCSI_In__MSG__BYP CYREG_PRT4_BYP\r
-#define SCSI_In__MSG__CTL CYREG_PRT4_CTL\r
-#define SCSI_In__MSG__DM0 CYREG_PRT4_DM0\r
-#define SCSI_In__MSG__DM1 CYREG_PRT4_DM1\r
-#define SCSI_In__MSG__DM2 CYREG_PRT4_DM2\r
-#define SCSI_In__MSG__DR CYREG_PRT4_DR\r
-#define SCSI_In__MSG__INP_DIS CYREG_PRT4_INP_DIS\r
-#define SCSI_In__MSG__INTTYPE CYREG_PICU4_INTTYPE6\r
-#define SCSI_In__MSG__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG\r
-#define SCSI_In__MSG__LCD_EN CYREG_PRT4_LCD_EN\r
-#define SCSI_In__MSG__MASK 0x40u\r
-#define SCSI_In__MSG__PC CYREG_PRT4_PC6\r
-#define SCSI_In__MSG__PORT 4u\r
-#define SCSI_In__MSG__PRT CYREG_PRT4_PRT\r
-#define SCSI_In__MSG__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL\r
-#define SCSI_In__MSG__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN\r
-#define SCSI_In__MSG__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0\r
-#define SCSI_In__MSG__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1\r
-#define SCSI_In__MSG__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0\r
-#define SCSI_In__MSG__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1\r
-#define SCSI_In__MSG__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT\r
-#define SCSI_In__MSG__PS CYREG_PRT4_PS\r
-#define SCSI_In__MSG__SHIFT 6u\r
-#define SCSI_In__MSG__SLW CYREG_PRT4_SLW\r
-#define SCSI_In__REQ__AG CYREG_PRT0_AG\r
-#define SCSI_In__REQ__AMUX CYREG_PRT0_AMUX\r
-#define SCSI_In__REQ__BIE CYREG_PRT0_BIE\r
-#define SCSI_In__REQ__BIT_MASK CYREG_PRT0_BIT_MASK\r
-#define SCSI_In__REQ__BYP CYREG_PRT0_BYP\r
-#define SCSI_In__REQ__CTL CYREG_PRT0_CTL\r
-#define SCSI_In__REQ__DM0 CYREG_PRT0_DM0\r
-#define SCSI_In__REQ__DM1 CYREG_PRT0_DM1\r
-#define SCSI_In__REQ__DM2 CYREG_PRT0_DM2\r
-#define SCSI_In__REQ__DR CYREG_PRT0_DR\r
-#define SCSI_In__REQ__INP_DIS CYREG_PRT0_INP_DIS\r
-#define SCSI_In__REQ__INTTYPE CYREG_PICU0_INTTYPE5\r
-#define SCSI_In__REQ__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG\r
-#define SCSI_In__REQ__LCD_EN CYREG_PRT0_LCD_EN\r
-#define SCSI_In__REQ__MASK 0x20u\r
-#define SCSI_In__REQ__PC CYREG_PRT0_PC5\r
-#define SCSI_In__REQ__PORT 0u\r
-#define SCSI_In__REQ__PRT CYREG_PRT0_PRT\r
-#define SCSI_In__REQ__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL\r
-#define SCSI_In__REQ__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN\r
-#define SCSI_In__REQ__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0\r
-#define SCSI_In__REQ__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1\r
-#define SCSI_In__REQ__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0\r
-#define SCSI_In__REQ__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1\r
-#define SCSI_In__REQ__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT\r
-#define SCSI_In__REQ__PS CYREG_PRT0_PS\r
-#define SCSI_In__REQ__SHIFT 5u\r
-#define SCSI_In__REQ__SLW CYREG_PRT0_SLW\r
-\r
-/* SCSI_In_DBx */\r
-#define SCSI_In_DBx__0__AG CYREG_PRT5_AG\r
-#define SCSI_In_DBx__0__AMUX CYREG_PRT5_AMUX\r
-#define SCSI_In_DBx__0__BIE CYREG_PRT5_BIE\r
-#define SCSI_In_DBx__0__BIT_MASK CYREG_PRT5_BIT_MASK\r
-#define SCSI_In_DBx__0__BYP CYREG_PRT5_BYP\r
-#define SCSI_In_DBx__0__CTL CYREG_PRT5_CTL\r
-#define SCSI_In_DBx__0__DM0 CYREG_PRT5_DM0\r
-#define SCSI_In_DBx__0__DM1 CYREG_PRT5_DM1\r
-#define SCSI_In_DBx__0__DM2 CYREG_PRT5_DM2\r
-#define SCSI_In_DBx__0__DR CYREG_PRT5_DR\r
-#define SCSI_In_DBx__0__INP_DIS CYREG_PRT5_INP_DIS\r
-#define SCSI_In_DBx__0__INTTYPE CYREG_PICU5_INTTYPE3\r
-#define SCSI_In_DBx__0__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG\r
-#define SCSI_In_DBx__0__LCD_EN CYREG_PRT5_LCD_EN\r
-#define SCSI_In_DBx__0__MASK 0x08u\r
-#define SCSI_In_DBx__0__PC CYREG_PRT5_PC3\r
-#define SCSI_In_DBx__0__PORT 5u\r
-#define SCSI_In_DBx__0__PRT CYREG_PRT5_PRT\r
-#define SCSI_In_DBx__0__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL\r
-#define SCSI_In_DBx__0__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN\r
-#define SCSI_In_DBx__0__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0\r
-#define SCSI_In_DBx__0__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1\r
-#define SCSI_In_DBx__0__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0\r
-#define SCSI_In_DBx__0__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1\r
-#define SCSI_In_DBx__0__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT\r
-#define SCSI_In_DBx__0__PS CYREG_PRT5_PS\r
-#define SCSI_In_DBx__0__SHIFT 3u\r
-#define SCSI_In_DBx__0__SLW CYREG_PRT5_SLW\r
-#define SCSI_In_DBx__1__AG CYREG_PRT5_AG\r
-#define SCSI_In_DBx__1__AMUX CYREG_PRT5_AMUX\r
-#define SCSI_In_DBx__1__BIE CYREG_PRT5_BIE\r
-#define SCSI_In_DBx__1__BIT_MASK CYREG_PRT5_BIT_MASK\r
-#define SCSI_In_DBx__1__BYP CYREG_PRT5_BYP\r
-#define SCSI_In_DBx__1__CTL CYREG_PRT5_CTL\r
-#define SCSI_In_DBx__1__DM0 CYREG_PRT5_DM0\r
-#define SCSI_In_DBx__1__DM1 CYREG_PRT5_DM1\r
-#define SCSI_In_DBx__1__DM2 CYREG_PRT5_DM2\r
-#define SCSI_In_DBx__1__DR CYREG_PRT5_DR\r
-#define SCSI_In_DBx__1__INP_DIS CYREG_PRT5_INP_DIS\r
-#define SCSI_In_DBx__1__INTTYPE CYREG_PICU5_INTTYPE2\r
-#define SCSI_In_DBx__1__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG\r
-#define SCSI_In_DBx__1__LCD_EN CYREG_PRT5_LCD_EN\r
-#define SCSI_In_DBx__1__MASK 0x04u\r
-#define SCSI_In_DBx__1__PC CYREG_PRT5_PC2\r
-#define SCSI_In_DBx__1__PORT 5u\r
-#define SCSI_In_DBx__1__PRT CYREG_PRT5_PRT\r
-#define SCSI_In_DBx__1__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL\r
-#define SCSI_In_DBx__1__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN\r
-#define SCSI_In_DBx__1__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0\r
-#define SCSI_In_DBx__1__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1\r
-#define SCSI_In_DBx__1__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0\r
-#define SCSI_In_DBx__1__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1\r
-#define SCSI_In_DBx__1__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT\r
-#define SCSI_In_DBx__1__PS CYREG_PRT5_PS\r
-#define SCSI_In_DBx__1__SHIFT 2u\r
-#define SCSI_In_DBx__1__SLW CYREG_PRT5_SLW\r
-#define SCSI_In_DBx__2__AG CYREG_PRT6_AG\r
-#define SCSI_In_DBx__2__AMUX CYREG_PRT6_AMUX\r
-#define SCSI_In_DBx__2__BIE CYREG_PRT6_BIE\r
-#define SCSI_In_DBx__2__BIT_MASK CYREG_PRT6_BIT_MASK\r
-#define SCSI_In_DBx__2__BYP CYREG_PRT6_BYP\r
-#define SCSI_In_DBx__2__CTL CYREG_PRT6_CTL\r
-#define SCSI_In_DBx__2__DM0 CYREG_PRT6_DM0\r
-#define SCSI_In_DBx__2__DM1 CYREG_PRT6_DM1\r
-#define SCSI_In_DBx__2__DM2 CYREG_PRT6_DM2\r
-#define SCSI_In_DBx__2__DR CYREG_PRT6_DR\r
-#define SCSI_In_DBx__2__INP_DIS CYREG_PRT6_INP_DIS\r
-#define SCSI_In_DBx__2__INTTYPE CYREG_PICU6_INTTYPE7\r
-#define SCSI_In_DBx__2__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
-#define SCSI_In_DBx__2__LCD_EN CYREG_PRT6_LCD_EN\r
-#define SCSI_In_DBx__2__MASK 0x80u\r
-#define SCSI_In_DBx__2__PC CYREG_PRT6_PC7\r
-#define SCSI_In_DBx__2__PORT 6u\r
-#define SCSI_In_DBx__2__PRT CYREG_PRT6_PRT\r
-#define SCSI_In_DBx__2__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
-#define SCSI_In_DBx__2__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
-#define SCSI_In_DBx__2__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
-#define SCSI_In_DBx__2__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
-#define SCSI_In_DBx__2__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
-#define SCSI_In_DBx__2__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
-#define SCSI_In_DBx__2__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
-#define SCSI_In_DBx__2__PS CYREG_PRT6_PS\r
-#define SCSI_In_DBx__2__SHIFT 7u\r
-#define SCSI_In_DBx__2__SLW CYREG_PRT6_SLW\r
-#define SCSI_In_DBx__3__AG CYREG_PRT6_AG\r
-#define SCSI_In_DBx__3__AMUX CYREG_PRT6_AMUX\r
-#define SCSI_In_DBx__3__BIE CYREG_PRT6_BIE\r
-#define SCSI_In_DBx__3__BIT_MASK CYREG_PRT6_BIT_MASK\r
-#define SCSI_In_DBx__3__BYP CYREG_PRT6_BYP\r
-#define SCSI_In_DBx__3__CTL CYREG_PRT6_CTL\r
-#define SCSI_In_DBx__3__DM0 CYREG_PRT6_DM0\r
-#define SCSI_In_DBx__3__DM1 CYREG_PRT6_DM1\r
-#define SCSI_In_DBx__3__DM2 CYREG_PRT6_DM2\r
-#define SCSI_In_DBx__3__DR CYREG_PRT6_DR\r
-#define SCSI_In_DBx__3__INP_DIS CYREG_PRT6_INP_DIS\r
-#define SCSI_In_DBx__3__INTTYPE CYREG_PICU6_INTTYPE6\r
-#define SCSI_In_DBx__3__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
-#define SCSI_In_DBx__3__LCD_EN CYREG_PRT6_LCD_EN\r
-#define SCSI_In_DBx__3__MASK 0x40u\r
-#define SCSI_In_DBx__3__PC CYREG_PRT6_PC6\r
-#define SCSI_In_DBx__3__PORT 6u\r
-#define SCSI_In_DBx__3__PRT CYREG_PRT6_PRT\r
-#define SCSI_In_DBx__3__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
-#define SCSI_In_DBx__3__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
-#define SCSI_In_DBx__3__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
-#define SCSI_In_DBx__3__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
-#define SCSI_In_DBx__3__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
-#define SCSI_In_DBx__3__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
-#define SCSI_In_DBx__3__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
-#define SCSI_In_DBx__3__PS CYREG_PRT6_PS\r
-#define SCSI_In_DBx__3__SHIFT 6u\r
-#define SCSI_In_DBx__3__SLW CYREG_PRT6_SLW\r
-#define SCSI_In_DBx__4__AG CYREG_PRT12_AG\r
-#define SCSI_In_DBx__4__BIE CYREG_PRT12_BIE\r
-#define SCSI_In_DBx__4__BIT_MASK CYREG_PRT12_BIT_MASK\r
-#define SCSI_In_DBx__4__BYP CYREG_PRT12_BYP\r
-#define SCSI_In_DBx__4__DM0 CYREG_PRT12_DM0\r
-#define SCSI_In_DBx__4__DM1 CYREG_PRT12_DM1\r
-#define SCSI_In_DBx__4__DM2 CYREG_PRT12_DM2\r
-#define SCSI_In_DBx__4__DR CYREG_PRT12_DR\r
-#define SCSI_In_DBx__4__INP_DIS CYREG_PRT12_INP_DIS\r
-#define SCSI_In_DBx__4__INTTYPE CYREG_PICU12_INTTYPE5\r
-#define SCSI_In_DBx__4__MASK 0x20u\r
-#define SCSI_In_DBx__4__PC CYREG_PRT12_PC5\r
-#define SCSI_In_DBx__4__PORT 12u\r
-#define SCSI_In_DBx__4__PRT CYREG_PRT12_PRT\r
-#define SCSI_In_DBx__4__PRTDSI__DBL_SYNC_IN CYREG_PRT12_DBL_SYNC_IN\r
-#define SCSI_In_DBx__4__PRTDSI__OE_SEL0 CYREG_PRT12_OE_SEL0\r
-#define SCSI_In_DBx__4__PRTDSI__OE_SEL1 CYREG_PRT12_OE_SEL1\r
-#define SCSI_In_DBx__4__PRTDSI__OUT_SEL0 CYREG_PRT12_OUT_SEL0\r
-#define SCSI_In_DBx__4__PRTDSI__OUT_SEL1 CYREG_PRT12_OUT_SEL1\r
-#define SCSI_In_DBx__4__PRTDSI__SYNC_OUT CYREG_PRT12_SYNC_OUT\r
-#define SCSI_In_DBx__4__PS CYREG_PRT12_PS\r
-#define SCSI_In_DBx__4__SHIFT 5u\r
-#define SCSI_In_DBx__4__SIO_CFG CYREG_PRT12_SIO_CFG\r
-#define SCSI_In_DBx__4__SIO_DIFF CYREG_PRT12_SIO_DIFF\r
-#define SCSI_In_DBx__4__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN\r
-#define SCSI_In_DBx__4__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ\r
-#define SCSI_In_DBx__4__SLW CYREG_PRT12_SLW\r
-#define SCSI_In_DBx__5__AG CYREG_PRT12_AG\r
-#define SCSI_In_DBx__5__BIE CYREG_PRT12_BIE\r
-#define SCSI_In_DBx__5__BIT_MASK CYREG_PRT12_BIT_MASK\r
-#define SCSI_In_DBx__5__BYP CYREG_PRT12_BYP\r
-#define SCSI_In_DBx__5__DM0 CYREG_PRT12_DM0\r
-#define SCSI_In_DBx__5__DM1 CYREG_PRT12_DM1\r
-#define SCSI_In_DBx__5__DM2 CYREG_PRT12_DM2\r
-#define SCSI_In_DBx__5__DR CYREG_PRT12_DR\r
-#define SCSI_In_DBx__5__INP_DIS CYREG_PRT12_INP_DIS\r
-#define SCSI_In_DBx__5__INTTYPE CYREG_PICU12_INTTYPE4\r
-#define SCSI_In_DBx__5__MASK 0x10u\r
-#define SCSI_In_DBx__5__PC CYREG_PRT12_PC4\r
-#define SCSI_In_DBx__5__PORT 12u\r
-#define SCSI_In_DBx__5__PRT CYREG_PRT12_PRT\r
-#define SCSI_In_DBx__5__PRTDSI__DBL_SYNC_IN CYREG_PRT12_DBL_SYNC_IN\r
-#define SCSI_In_DBx__5__PRTDSI__OE_SEL0 CYREG_PRT12_OE_SEL0\r
-#define SCSI_In_DBx__5__PRTDSI__OE_SEL1 CYREG_PRT12_OE_SEL1\r
-#define SCSI_In_DBx__5__PRTDSI__OUT_SEL0 CYREG_PRT12_OUT_SEL0\r
-#define SCSI_In_DBx__5__PRTDSI__OUT_SEL1 CYREG_PRT12_OUT_SEL1\r
-#define SCSI_In_DBx__5__PRTDSI__SYNC_OUT CYREG_PRT12_SYNC_OUT\r
-#define SCSI_In_DBx__5__PS CYREG_PRT12_PS\r
-#define SCSI_In_DBx__5__SHIFT 4u\r
-#define SCSI_In_DBx__5__SIO_CFG CYREG_PRT12_SIO_CFG\r
-#define SCSI_In_DBx__5__SIO_DIFF CYREG_PRT12_SIO_DIFF\r
-#define SCSI_In_DBx__5__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN\r
-#define SCSI_In_DBx__5__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ\r
-#define SCSI_In_DBx__5__SLW CYREG_PRT12_SLW\r
-#define SCSI_In_DBx__6__AG CYREG_PRT2_AG\r
-#define SCSI_In_DBx__6__AMUX CYREG_PRT2_AMUX\r
-#define SCSI_In_DBx__6__BIE CYREG_PRT2_BIE\r
-#define SCSI_In_DBx__6__BIT_MASK CYREG_PRT2_BIT_MASK\r
-#define SCSI_In_DBx__6__BYP CYREG_PRT2_BYP\r
-#define SCSI_In_DBx__6__CTL CYREG_PRT2_CTL\r
-#define SCSI_In_DBx__6__DM0 CYREG_PRT2_DM0\r
-#define SCSI_In_DBx__6__DM1 CYREG_PRT2_DM1\r
-#define SCSI_In_DBx__6__DM2 CYREG_PRT2_DM2\r
-#define SCSI_In_DBx__6__DR CYREG_PRT2_DR\r
-#define SCSI_In_DBx__6__INP_DIS CYREG_PRT2_INP_DIS\r
-#define SCSI_In_DBx__6__INTTYPE CYREG_PICU2_INTTYPE5\r
-#define SCSI_In_DBx__6__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG\r
-#define SCSI_In_DBx__6__LCD_EN CYREG_PRT2_LCD_EN\r
-#define SCSI_In_DBx__6__MASK 0x20u\r
-#define SCSI_In_DBx__6__PC CYREG_PRT2_PC5\r
-#define SCSI_In_DBx__6__PORT 2u\r
-#define SCSI_In_DBx__6__PRT CYREG_PRT2_PRT\r
-#define SCSI_In_DBx__6__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL\r
-#define SCSI_In_DBx__6__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN\r
-#define SCSI_In_DBx__6__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0\r
-#define SCSI_In_DBx__6__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1\r
-#define SCSI_In_DBx__6__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0\r
-#define SCSI_In_DBx__6__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1\r
-#define SCSI_In_DBx__6__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT\r
-#define SCSI_In_DBx__6__PS CYREG_PRT2_PS\r
-#define SCSI_In_DBx__6__SHIFT 5u\r
-#define SCSI_In_DBx__6__SLW CYREG_PRT2_SLW\r
-#define SCSI_In_DBx__7__AG CYREG_PRT2_AG\r
-#define SCSI_In_DBx__7__AMUX CYREG_PRT2_AMUX\r
-#define SCSI_In_DBx__7__BIE CYREG_PRT2_BIE\r
-#define SCSI_In_DBx__7__BIT_MASK CYREG_PRT2_BIT_MASK\r
-#define SCSI_In_DBx__7__BYP CYREG_PRT2_BYP\r
-#define SCSI_In_DBx__7__CTL CYREG_PRT2_CTL\r
-#define SCSI_In_DBx__7__DM0 CYREG_PRT2_DM0\r
-#define SCSI_In_DBx__7__DM1 CYREG_PRT2_DM1\r
-#define SCSI_In_DBx__7__DM2 CYREG_PRT2_DM2\r
-#define SCSI_In_DBx__7__DR CYREG_PRT2_DR\r
-#define SCSI_In_DBx__7__INP_DIS CYREG_PRT2_INP_DIS\r
-#define SCSI_In_DBx__7__INTTYPE CYREG_PICU2_INTTYPE4\r
-#define SCSI_In_DBx__7__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG\r
-#define SCSI_In_DBx__7__LCD_EN CYREG_PRT2_LCD_EN\r
-#define SCSI_In_DBx__7__MASK 0x10u\r
-#define SCSI_In_DBx__7__PC CYREG_PRT2_PC4\r
-#define SCSI_In_DBx__7__PORT 2u\r
-#define SCSI_In_DBx__7__PRT CYREG_PRT2_PRT\r
-#define SCSI_In_DBx__7__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL\r
-#define SCSI_In_DBx__7__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN\r
-#define SCSI_In_DBx__7__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0\r
-#define SCSI_In_DBx__7__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1\r
-#define SCSI_In_DBx__7__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0\r
-#define SCSI_In_DBx__7__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1\r
-#define SCSI_In_DBx__7__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT\r
-#define SCSI_In_DBx__7__PS CYREG_PRT2_PS\r
-#define SCSI_In_DBx__7__SHIFT 4u\r
-#define SCSI_In_DBx__7__SLW CYREG_PRT2_SLW\r
-#define SCSI_In_DBx__DB0__AG CYREG_PRT5_AG\r
-#define SCSI_In_DBx__DB0__AMUX CYREG_PRT5_AMUX\r
-#define SCSI_In_DBx__DB0__BIE CYREG_PRT5_BIE\r
-#define SCSI_In_DBx__DB0__BIT_MASK CYREG_PRT5_BIT_MASK\r
-#define SCSI_In_DBx__DB0__BYP CYREG_PRT5_BYP\r
-#define SCSI_In_DBx__DB0__CTL CYREG_PRT5_CTL\r
-#define SCSI_In_DBx__DB0__DM0 CYREG_PRT5_DM0\r
-#define SCSI_In_DBx__DB0__DM1 CYREG_PRT5_DM1\r
-#define SCSI_In_DBx__DB0__DM2 CYREG_PRT5_DM2\r
-#define SCSI_In_DBx__DB0__DR CYREG_PRT5_DR\r
-#define SCSI_In_DBx__DB0__INP_DIS CYREG_PRT5_INP_DIS\r
-#define SCSI_In_DBx__DB0__INTTYPE CYREG_PICU5_INTTYPE3\r
-#define SCSI_In_DBx__DB0__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG\r
-#define SCSI_In_DBx__DB0__LCD_EN CYREG_PRT5_LCD_EN\r
-#define SCSI_In_DBx__DB0__MASK 0x08u\r
-#define SCSI_In_DBx__DB0__PC CYREG_PRT5_PC3\r
-#define SCSI_In_DBx__DB0__PORT 5u\r
-#define SCSI_In_DBx__DB0__PRT CYREG_PRT5_PRT\r
-#define SCSI_In_DBx__DB0__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL\r
-#define SCSI_In_DBx__DB0__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN\r
-#define SCSI_In_DBx__DB0__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0\r
-#define SCSI_In_DBx__DB0__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1\r
-#define SCSI_In_DBx__DB0__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0\r
-#define SCSI_In_DBx__DB0__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1\r
-#define SCSI_In_DBx__DB0__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT\r
-#define SCSI_In_DBx__DB0__PS CYREG_PRT5_PS\r
-#define SCSI_In_DBx__DB0__SHIFT 3u\r
-#define SCSI_In_DBx__DB0__SLW CYREG_PRT5_SLW\r
-#define SCSI_In_DBx__DB1__AG CYREG_PRT5_AG\r
-#define SCSI_In_DBx__DB1__AMUX CYREG_PRT5_AMUX\r
-#define SCSI_In_DBx__DB1__BIE CYREG_PRT5_BIE\r
-#define SCSI_In_DBx__DB1__BIT_MASK CYREG_PRT5_BIT_MASK\r
-#define SCSI_In_DBx__DB1__BYP CYREG_PRT5_BYP\r
-#define SCSI_In_DBx__DB1__CTL CYREG_PRT5_CTL\r
-#define SCSI_In_DBx__DB1__DM0 CYREG_PRT5_DM0\r
-#define SCSI_In_DBx__DB1__DM1 CYREG_PRT5_DM1\r
-#define SCSI_In_DBx__DB1__DM2 CYREG_PRT5_DM2\r
-#define SCSI_In_DBx__DB1__DR CYREG_PRT5_DR\r
-#define SCSI_In_DBx__DB1__INP_DIS CYREG_PRT5_INP_DIS\r
-#define SCSI_In_DBx__DB1__INTTYPE CYREG_PICU5_INTTYPE2\r
-#define SCSI_In_DBx__DB1__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG\r
-#define SCSI_In_DBx__DB1__LCD_EN CYREG_PRT5_LCD_EN\r
-#define SCSI_In_DBx__DB1__MASK 0x04u\r
-#define SCSI_In_DBx__DB1__PC CYREG_PRT5_PC2\r
-#define SCSI_In_DBx__DB1__PORT 5u\r
-#define SCSI_In_DBx__DB1__PRT CYREG_PRT5_PRT\r
-#define SCSI_In_DBx__DB1__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL\r
-#define SCSI_In_DBx__DB1__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN\r
-#define SCSI_In_DBx__DB1__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0\r
-#define SCSI_In_DBx__DB1__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1\r
-#define SCSI_In_DBx__DB1__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0\r
-#define SCSI_In_DBx__DB1__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1\r
-#define SCSI_In_DBx__DB1__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT\r
-#define SCSI_In_DBx__DB1__PS CYREG_PRT5_PS\r
-#define SCSI_In_DBx__DB1__SHIFT 2u\r
-#define SCSI_In_DBx__DB1__SLW CYREG_PRT5_SLW\r
-#define SCSI_In_DBx__DB2__AG CYREG_PRT6_AG\r
-#define SCSI_In_DBx__DB2__AMUX CYREG_PRT6_AMUX\r
-#define SCSI_In_DBx__DB2__BIE CYREG_PRT6_BIE\r
-#define SCSI_In_DBx__DB2__BIT_MASK CYREG_PRT6_BIT_MASK\r
-#define SCSI_In_DBx__DB2__BYP CYREG_PRT6_BYP\r
-#define SCSI_In_DBx__DB2__CTL CYREG_PRT6_CTL\r
-#define SCSI_In_DBx__DB2__DM0 CYREG_PRT6_DM0\r
-#define SCSI_In_DBx__DB2__DM1 CYREG_PRT6_DM1\r
-#define SCSI_In_DBx__DB2__DM2 CYREG_PRT6_DM2\r
-#define SCSI_In_DBx__DB2__DR CYREG_PRT6_DR\r
-#define SCSI_In_DBx__DB2__INP_DIS CYREG_PRT6_INP_DIS\r
-#define SCSI_In_DBx__DB2__INTTYPE CYREG_PICU6_INTTYPE7\r
-#define SCSI_In_DBx__DB2__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
-#define SCSI_In_DBx__DB2__LCD_EN CYREG_PRT6_LCD_EN\r
-#define SCSI_In_DBx__DB2__MASK 0x80u\r
-#define SCSI_In_DBx__DB2__PC CYREG_PRT6_PC7\r
-#define SCSI_In_DBx__DB2__PORT 6u\r
-#define SCSI_In_DBx__DB2__PRT CYREG_PRT6_PRT\r
-#define SCSI_In_DBx__DB2__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
-#define SCSI_In_DBx__DB2__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
-#define SCSI_In_DBx__DB2__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
-#define SCSI_In_DBx__DB2__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
-#define SCSI_In_DBx__DB2__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
-#define SCSI_In_DBx__DB2__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
-#define SCSI_In_DBx__DB2__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
-#define SCSI_In_DBx__DB2__PS CYREG_PRT6_PS\r
-#define SCSI_In_DBx__DB2__SHIFT 7u\r
-#define SCSI_In_DBx__DB2__SLW CYREG_PRT6_SLW\r
-#define SCSI_In_DBx__DB3__AG CYREG_PRT6_AG\r
-#define SCSI_In_DBx__DB3__AMUX CYREG_PRT6_AMUX\r
-#define SCSI_In_DBx__DB3__BIE CYREG_PRT6_BIE\r
-#define SCSI_In_DBx__DB3__BIT_MASK CYREG_PRT6_BIT_MASK\r
-#define SCSI_In_DBx__DB3__BYP CYREG_PRT6_BYP\r
-#define SCSI_In_DBx__DB3__CTL CYREG_PRT6_CTL\r
-#define SCSI_In_DBx__DB3__DM0 CYREG_PRT6_DM0\r
-#define SCSI_In_DBx__DB3__DM1 CYREG_PRT6_DM1\r
-#define SCSI_In_DBx__DB3__DM2 CYREG_PRT6_DM2\r
-#define SCSI_In_DBx__DB3__DR CYREG_PRT6_DR\r
-#define SCSI_In_DBx__DB3__INP_DIS CYREG_PRT6_INP_DIS\r
-#define SCSI_In_DBx__DB3__INTTYPE CYREG_PICU6_INTTYPE6\r
-#define SCSI_In_DBx__DB3__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
-#define SCSI_In_DBx__DB3__LCD_EN CYREG_PRT6_LCD_EN\r
-#define SCSI_In_DBx__DB3__MASK 0x40u\r
-#define SCSI_In_DBx__DB3__PC CYREG_PRT6_PC6\r
-#define SCSI_In_DBx__DB3__PORT 6u\r
-#define SCSI_In_DBx__DB3__PRT CYREG_PRT6_PRT\r
-#define SCSI_In_DBx__DB3__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
-#define SCSI_In_DBx__DB3__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
-#define SCSI_In_DBx__DB3__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
-#define SCSI_In_DBx__DB3__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
-#define SCSI_In_DBx__DB3__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
-#define SCSI_In_DBx__DB3__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
-#define SCSI_In_DBx__DB3__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
-#define SCSI_In_DBx__DB3__PS CYREG_PRT6_PS\r
-#define SCSI_In_DBx__DB3__SHIFT 6u\r
-#define SCSI_In_DBx__DB3__SLW CYREG_PRT6_SLW\r
-#define SCSI_In_DBx__DB4__AG CYREG_PRT12_AG\r
-#define SCSI_In_DBx__DB4__BIE CYREG_PRT12_BIE\r
-#define SCSI_In_DBx__DB4__BIT_MASK CYREG_PRT12_BIT_MASK\r
-#define SCSI_In_DBx__DB4__BYP CYREG_PRT12_BYP\r
-#define SCSI_In_DBx__DB4__DM0 CYREG_PRT12_DM0\r
-#define SCSI_In_DBx__DB4__DM1 CYREG_PRT12_DM1\r
-#define SCSI_In_DBx__DB4__DM2 CYREG_PRT12_DM2\r
-#define SCSI_In_DBx__DB4__DR CYREG_PRT12_DR\r
-#define SCSI_In_DBx__DB4__INP_DIS CYREG_PRT12_INP_DIS\r
-#define SCSI_In_DBx__DB4__INTTYPE CYREG_PICU12_INTTYPE5\r
-#define SCSI_In_DBx__DB4__MASK 0x20u\r
-#define SCSI_In_DBx__DB4__PC CYREG_PRT12_PC5\r
-#define SCSI_In_DBx__DB4__PORT 12u\r
-#define SCSI_In_DBx__DB4__PRT CYREG_PRT12_PRT\r
-#define SCSI_In_DBx__DB4__PRTDSI__DBL_SYNC_IN CYREG_PRT12_DBL_SYNC_IN\r
-#define SCSI_In_DBx__DB4__PRTDSI__OE_SEL0 CYREG_PRT12_OE_SEL0\r
-#define SCSI_In_DBx__DB4__PRTDSI__OE_SEL1 CYREG_PRT12_OE_SEL1\r
-#define SCSI_In_DBx__DB4__PRTDSI__OUT_SEL0 CYREG_PRT12_OUT_SEL0\r
-#define SCSI_In_DBx__DB4__PRTDSI__OUT_SEL1 CYREG_PRT12_OUT_SEL1\r
-#define SCSI_In_DBx__DB4__PRTDSI__SYNC_OUT CYREG_PRT12_SYNC_OUT\r
-#define SCSI_In_DBx__DB4__PS CYREG_PRT12_PS\r
-#define SCSI_In_DBx__DB4__SHIFT 5u\r
-#define SCSI_In_DBx__DB4__SIO_CFG CYREG_PRT12_SIO_CFG\r
-#define SCSI_In_DBx__DB4__SIO_DIFF CYREG_PRT12_SIO_DIFF\r
-#define SCSI_In_DBx__DB4__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN\r
-#define SCSI_In_DBx__DB4__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ\r
-#define SCSI_In_DBx__DB4__SLW CYREG_PRT12_SLW\r
-#define SCSI_In_DBx__DB5__AG CYREG_PRT12_AG\r
-#define SCSI_In_DBx__DB5__BIE CYREG_PRT12_BIE\r
-#define SCSI_In_DBx__DB5__BIT_MASK CYREG_PRT12_BIT_MASK\r
-#define SCSI_In_DBx__DB5__BYP CYREG_PRT12_BYP\r
-#define SCSI_In_DBx__DB5__DM0 CYREG_PRT12_DM0\r
-#define SCSI_In_DBx__DB5__DM1 CYREG_PRT12_DM1\r
-#define SCSI_In_DBx__DB5__DM2 CYREG_PRT12_DM2\r
-#define SCSI_In_DBx__DB5__DR CYREG_PRT12_DR\r
-#define SCSI_In_DBx__DB5__INP_DIS CYREG_PRT12_INP_DIS\r
-#define SCSI_In_DBx__DB5__INTTYPE CYREG_PICU12_INTTYPE4\r
-#define SCSI_In_DBx__DB5__MASK 0x10u\r
-#define SCSI_In_DBx__DB5__PC CYREG_PRT12_PC4\r
-#define SCSI_In_DBx__DB5__PORT 12u\r
-#define SCSI_In_DBx__DB5__PRT CYREG_PRT12_PRT\r
-#define SCSI_In_DBx__DB5__PRTDSI__DBL_SYNC_IN CYREG_PRT12_DBL_SYNC_IN\r
-#define SCSI_In_DBx__DB5__PRTDSI__OE_SEL0 CYREG_PRT12_OE_SEL0\r
-#define SCSI_In_DBx__DB5__PRTDSI__OE_SEL1 CYREG_PRT12_OE_SEL1\r
-#define SCSI_In_DBx__DB5__PRTDSI__OUT_SEL0 CYREG_PRT12_OUT_SEL0\r
-#define SCSI_In_DBx__DB5__PRTDSI__OUT_SEL1 CYREG_PRT12_OUT_SEL1\r
-#define SCSI_In_DBx__DB5__PRTDSI__SYNC_OUT CYREG_PRT12_SYNC_OUT\r
-#define SCSI_In_DBx__DB5__PS CYREG_PRT12_PS\r
-#define SCSI_In_DBx__DB5__SHIFT 4u\r
-#define SCSI_In_DBx__DB5__SIO_CFG CYREG_PRT12_SIO_CFG\r
-#define SCSI_In_DBx__DB5__SIO_DIFF CYREG_PRT12_SIO_DIFF\r
-#define SCSI_In_DBx__DB5__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN\r
-#define SCSI_In_DBx__DB5__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ\r
-#define SCSI_In_DBx__DB5__SLW CYREG_PRT12_SLW\r
-#define SCSI_In_DBx__DB6__AG CYREG_PRT2_AG\r
-#define SCSI_In_DBx__DB6__AMUX CYREG_PRT2_AMUX\r
-#define SCSI_In_DBx__DB6__BIE CYREG_PRT2_BIE\r
-#define SCSI_In_DBx__DB6__BIT_MASK CYREG_PRT2_BIT_MASK\r
-#define SCSI_In_DBx__DB6__BYP CYREG_PRT2_BYP\r
-#define SCSI_In_DBx__DB6__CTL CYREG_PRT2_CTL\r
-#define SCSI_In_DBx__DB6__DM0 CYREG_PRT2_DM0\r
-#define SCSI_In_DBx__DB6__DM1 CYREG_PRT2_DM1\r
-#define SCSI_In_DBx__DB6__DM2 CYREG_PRT2_DM2\r
-#define SCSI_In_DBx__DB6__DR CYREG_PRT2_DR\r
-#define SCSI_In_DBx__DB6__INP_DIS CYREG_PRT2_INP_DIS\r
-#define SCSI_In_DBx__DB6__INTTYPE CYREG_PICU2_INTTYPE5\r
-#define SCSI_In_DBx__DB6__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG\r
-#define SCSI_In_DBx__DB6__LCD_EN CYREG_PRT2_LCD_EN\r
-#define SCSI_In_DBx__DB6__MASK 0x20u\r
-#define SCSI_In_DBx__DB6__PC CYREG_PRT2_PC5\r
-#define SCSI_In_DBx__DB6__PORT 2u\r
-#define SCSI_In_DBx__DB6__PRT CYREG_PRT2_PRT\r
-#define SCSI_In_DBx__DB6__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL\r
-#define SCSI_In_DBx__DB6__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN\r
-#define SCSI_In_DBx__DB6__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0\r
-#define SCSI_In_DBx__DB6__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1\r
-#define SCSI_In_DBx__DB6__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0\r
-#define SCSI_In_DBx__DB6__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1\r
-#define SCSI_In_DBx__DB6__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT\r
-#define SCSI_In_DBx__DB6__PS CYREG_PRT2_PS\r
-#define SCSI_In_DBx__DB6__SHIFT 5u\r
-#define SCSI_In_DBx__DB6__SLW CYREG_PRT2_SLW\r
-#define SCSI_In_DBx__DB7__AG CYREG_PRT2_AG\r
-#define SCSI_In_DBx__DB7__AMUX CYREG_PRT2_AMUX\r
-#define SCSI_In_DBx__DB7__BIE CYREG_PRT2_BIE\r
-#define SCSI_In_DBx__DB7__BIT_MASK CYREG_PRT2_BIT_MASK\r
-#define SCSI_In_DBx__DB7__BYP CYREG_PRT2_BYP\r
-#define SCSI_In_DBx__DB7__CTL CYREG_PRT2_CTL\r
-#define SCSI_In_DBx__DB7__DM0 CYREG_PRT2_DM0\r
-#define SCSI_In_DBx__DB7__DM1 CYREG_PRT2_DM1\r
-#define SCSI_In_DBx__DB7__DM2 CYREG_PRT2_DM2\r
-#define SCSI_In_DBx__DB7__DR CYREG_PRT2_DR\r
-#define SCSI_In_DBx__DB7__INP_DIS CYREG_PRT2_INP_DIS\r
-#define SCSI_In_DBx__DB7__INTTYPE CYREG_PICU2_INTTYPE4\r
-#define SCSI_In_DBx__DB7__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG\r
-#define SCSI_In_DBx__DB7__LCD_EN CYREG_PRT2_LCD_EN\r
-#define SCSI_In_DBx__DB7__MASK 0x10u\r
-#define SCSI_In_DBx__DB7__PC CYREG_PRT2_PC4\r
-#define SCSI_In_DBx__DB7__PORT 2u\r
-#define SCSI_In_DBx__DB7__PRT CYREG_PRT2_PRT\r
-#define SCSI_In_DBx__DB7__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL\r
-#define SCSI_In_DBx__DB7__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN\r
-#define SCSI_In_DBx__DB7__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0\r
-#define SCSI_In_DBx__DB7__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1\r
-#define SCSI_In_DBx__DB7__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0\r
-#define SCSI_In_DBx__DB7__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1\r
-#define SCSI_In_DBx__DB7__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT\r
-#define SCSI_In_DBx__DB7__PS CYREG_PRT2_PS\r
-#define SCSI_In_DBx__DB7__SHIFT 4u\r
-#define SCSI_In_DBx__DB7__SLW CYREG_PRT2_SLW\r
-\r
-/* SD_MISO */\r
-#define SD_MISO__0__INTTYPE CYREG_PICU3_INTTYPE1\r
-#define SD_MISO__0__MASK 0x02u\r
-#define SD_MISO__0__PC CYREG_PRT3_PC1\r
-#define SD_MISO__0__PORT 3u\r
-#define SD_MISO__0__SHIFT 1u\r
-#define SD_MISO__AG CYREG_PRT3_AG\r
-#define SD_MISO__AMUX CYREG_PRT3_AMUX\r
-#define SD_MISO__BIE CYREG_PRT3_BIE\r
-#define SD_MISO__BIT_MASK CYREG_PRT3_BIT_MASK\r
-#define SD_MISO__BYP CYREG_PRT3_BYP\r
-#define SD_MISO__CTL CYREG_PRT3_CTL\r
-#define SD_MISO__DM0 CYREG_PRT3_DM0\r
-#define SD_MISO__DM1 CYREG_PRT3_DM1\r
-#define SD_MISO__DM2 CYREG_PRT3_DM2\r
-#define SD_MISO__DR CYREG_PRT3_DR\r
-#define SD_MISO__INP_DIS CYREG_PRT3_INP_DIS\r
-#define SD_MISO__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU3_BASE\r
-#define SD_MISO__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG\r
-#define SD_MISO__LCD_EN CYREG_PRT3_LCD_EN\r
-#define SD_MISO__MASK 0x02u\r
-#define SD_MISO__PORT 3u\r
-#define SD_MISO__PRT CYREG_PRT3_PRT\r
-#define SD_MISO__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL\r
-#define SD_MISO__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN\r
-#define SD_MISO__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0\r
-#define SD_MISO__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1\r
-#define SD_MISO__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0\r
-#define SD_MISO__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1\r
-#define SD_MISO__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT\r
-#define SD_MISO__PS CYREG_PRT3_PS\r
-#define SD_MISO__SHIFT 1u\r
-#define SD_MISO__SLW CYREG_PRT3_SLW\r
-\r
-/* SD_MOSI */\r
-#define SD_MOSI__0__INTTYPE CYREG_PICU3_INTTYPE3\r
-#define SD_MOSI__0__MASK 0x08u\r
-#define SD_MOSI__0__PC CYREG_PRT3_PC3\r
-#define SD_MOSI__0__PORT 3u\r
-#define SD_MOSI__0__SHIFT 3u\r
-#define SD_MOSI__AG CYREG_PRT3_AG\r
-#define SD_MOSI__AMUX CYREG_PRT3_AMUX\r
-#define SD_MOSI__BIE CYREG_PRT3_BIE\r
-#define SD_MOSI__BIT_MASK CYREG_PRT3_BIT_MASK\r
-#define SD_MOSI__BYP CYREG_PRT3_BYP\r
-#define SD_MOSI__CTL CYREG_PRT3_CTL\r
-#define SD_MOSI__DM0 CYREG_PRT3_DM0\r
-#define SD_MOSI__DM1 CYREG_PRT3_DM1\r
-#define SD_MOSI__DM2 CYREG_PRT3_DM2\r
-#define SD_MOSI__DR CYREG_PRT3_DR\r
-#define SD_MOSI__INP_DIS CYREG_PRT3_INP_DIS\r
-#define SD_MOSI__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU3_BASE\r
-#define SD_MOSI__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG\r
-#define SD_MOSI__LCD_EN CYREG_PRT3_LCD_EN\r
-#define SD_MOSI__MASK 0x08u\r
-#define SD_MOSI__PORT 3u\r
-#define SD_MOSI__PRT CYREG_PRT3_PRT\r
-#define SD_MOSI__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL\r
-#define SD_MOSI__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN\r
-#define SD_MOSI__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0\r
-#define SD_MOSI__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1\r
-#define SD_MOSI__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0\r
-#define SD_MOSI__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1\r
-#define SD_MOSI__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT\r
-#define SD_MOSI__PS CYREG_PRT3_PS\r
-#define SD_MOSI__SHIFT 3u\r
-#define SD_MOSI__SLW CYREG_PRT3_SLW\r
-\r
-/* SCSI_CLK */\r
-#define SCSI_CLK__CFG0 CYREG_CLKDIST_DCFG1_CFG0\r
-#define SCSI_CLK__CFG1 CYREG_CLKDIST_DCFG1_CFG1\r
-#define SCSI_CLK__CFG2 CYREG_CLKDIST_DCFG1_CFG2\r
-#define SCSI_CLK__CFG2_SRC_SEL_MASK 0x07u\r
-#define SCSI_CLK__INDEX 0x01u\r
-#define SCSI_CLK__PM_ACT_CFG CYREG_PM_ACT_CFG2\r
-#define SCSI_CLK__PM_ACT_MSK 0x02u\r
-#define SCSI_CLK__PM_STBY_CFG CYREG_PM_STBY_CFG2\r
-#define SCSI_CLK__PM_STBY_MSK 0x02u\r
-\r
-/* SCSI_Out */\r
-#define SCSI_Out__0__AG CYREG_PRT15_AG\r
-#define SCSI_Out__0__AMUX CYREG_PRT15_AMUX\r
-#define SCSI_Out__0__BIE CYREG_PRT15_BIE\r
-#define SCSI_Out__0__BIT_MASK CYREG_PRT15_BIT_MASK\r
-#define SCSI_Out__0__BYP CYREG_PRT15_BYP\r
-#define SCSI_Out__0__CTL CYREG_PRT15_CTL\r
-#define SCSI_Out__0__DM0 CYREG_PRT15_DM0\r
-#define SCSI_Out__0__DM1 CYREG_PRT15_DM1\r
-#define SCSI_Out__0__DM2 CYREG_PRT15_DM2\r
-#define SCSI_Out__0__DR CYREG_PRT15_DR\r
-#define SCSI_Out__0__INP_DIS CYREG_PRT15_INP_DIS\r
-#define SCSI_Out__0__INTTYPE CYREG_PICU15_INTTYPE5\r
-#define SCSI_Out__0__LCD_COM_SEG CYREG_PRT15_LCD_COM_SEG\r
-#define SCSI_Out__0__LCD_EN CYREG_PRT15_LCD_EN\r
-#define SCSI_Out__0__MASK 0x20u\r
-#define SCSI_Out__0__PC CYREG_IO_PC_PRT15_PC5\r
-#define SCSI_Out__0__PORT 15u\r
-#define SCSI_Out__0__PRT CYREG_PRT15_PRT\r
-#define SCSI_Out__0__PRTDSI__CAPS_SEL CYREG_PRT15_CAPS_SEL\r
-#define SCSI_Out__0__PRTDSI__DBL_SYNC_IN CYREG_PRT15_DBL_SYNC_IN\r
-#define SCSI_Out__0__PRTDSI__OE_SEL0 CYREG_PRT15_OE_SEL0\r
-#define SCSI_Out__0__PRTDSI__OE_SEL1 CYREG_PRT15_OE_SEL1\r
-#define SCSI_Out__0__PRTDSI__OUT_SEL0 CYREG_PRT15_OUT_SEL0\r
-#define SCSI_Out__0__PRTDSI__OUT_SEL1 CYREG_PRT15_OUT_SEL1\r
-#define SCSI_Out__0__PRTDSI__SYNC_OUT CYREG_PRT15_SYNC_OUT\r
-#define SCSI_Out__0__PS CYREG_PRT15_PS\r
-#define SCSI_Out__0__SHIFT 5u\r
-#define SCSI_Out__0__SLW CYREG_PRT15_SLW\r
-#define SCSI_Out__1__AG CYREG_PRT15_AG\r
-#define SCSI_Out__1__AMUX CYREG_PRT15_AMUX\r
-#define SCSI_Out__1__BIE CYREG_PRT15_BIE\r
-#define SCSI_Out__1__BIT_MASK CYREG_PRT15_BIT_MASK\r
-#define SCSI_Out__1__BYP CYREG_PRT15_BYP\r
-#define SCSI_Out__1__CTL CYREG_PRT15_CTL\r
-#define SCSI_Out__1__DM0 CYREG_PRT15_DM0\r
-#define SCSI_Out__1__DM1 CYREG_PRT15_DM1\r
-#define SCSI_Out__1__DM2 CYREG_PRT15_DM2\r
-#define SCSI_Out__1__DR CYREG_PRT15_DR\r
-#define SCSI_Out__1__INP_DIS CYREG_PRT15_INP_DIS\r
-#define SCSI_Out__1__INTTYPE CYREG_PICU15_INTTYPE4\r
-#define SCSI_Out__1__LCD_COM_SEG CYREG_PRT15_LCD_COM_SEG\r
-#define SCSI_Out__1__LCD_EN CYREG_PRT15_LCD_EN\r
-#define SCSI_Out__1__MASK 0x10u\r
-#define SCSI_Out__1__PC CYREG_IO_PC_PRT15_PC4\r
-#define SCSI_Out__1__PORT 15u\r
-#define SCSI_Out__1__PRT CYREG_PRT15_PRT\r
-#define SCSI_Out__1__PRTDSI__CAPS_SEL CYREG_PRT15_CAPS_SEL\r
-#define SCSI_Out__1__PRTDSI__DBL_SYNC_IN CYREG_PRT15_DBL_SYNC_IN\r
-#define SCSI_Out__1__PRTDSI__OE_SEL0 CYREG_PRT15_OE_SEL0\r
-#define SCSI_Out__1__PRTDSI__OE_SEL1 CYREG_PRT15_OE_SEL1\r
-#define SCSI_Out__1__PRTDSI__OUT_SEL0 CYREG_PRT15_OUT_SEL0\r
-#define SCSI_Out__1__PRTDSI__OUT_SEL1 CYREG_PRT15_OUT_SEL1\r
-#define SCSI_Out__1__PRTDSI__SYNC_OUT CYREG_PRT15_SYNC_OUT\r
-#define SCSI_Out__1__PS CYREG_PRT15_PS\r
-#define SCSI_Out__1__SHIFT 4u\r
-#define SCSI_Out__1__SLW CYREG_PRT15_SLW\r
-#define SCSI_Out__2__AG CYREG_PRT6_AG\r
-#define SCSI_Out__2__AMUX CYREG_PRT6_AMUX\r
-#define SCSI_Out__2__BIE CYREG_PRT6_BIE\r
-#define SCSI_Out__2__BIT_MASK CYREG_PRT6_BIT_MASK\r
-#define SCSI_Out__2__BYP CYREG_PRT6_BYP\r
-#define SCSI_Out__2__CTL CYREG_PRT6_CTL\r
-#define SCSI_Out__2__DM0 CYREG_PRT6_DM0\r
-#define SCSI_Out__2__DM1 CYREG_PRT6_DM1\r
-#define SCSI_Out__2__DM2 CYREG_PRT6_DM2\r
-#define SCSI_Out__2__DR CYREG_PRT6_DR\r
-#define SCSI_Out__2__INP_DIS CYREG_PRT6_INP_DIS\r
-#define SCSI_Out__2__INTTYPE CYREG_PICU6_INTTYPE1\r
-#define SCSI_Out__2__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
-#define SCSI_Out__2__LCD_EN CYREG_PRT6_LCD_EN\r
-#define SCSI_Out__2__MASK 0x02u\r
-#define SCSI_Out__2__PC CYREG_PRT6_PC1\r
-#define SCSI_Out__2__PORT 6u\r
-#define SCSI_Out__2__PRT CYREG_PRT6_PRT\r
-#define SCSI_Out__2__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
-#define SCSI_Out__2__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
-#define SCSI_Out__2__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
-#define SCSI_Out__2__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
-#define SCSI_Out__2__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
-#define SCSI_Out__2__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
-#define SCSI_Out__2__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
-#define SCSI_Out__2__PS CYREG_PRT6_PS\r
-#define SCSI_Out__2__SHIFT 1u\r
-#define SCSI_Out__2__SLW CYREG_PRT6_SLW\r
-#define SCSI_Out__3__AG CYREG_PRT6_AG\r
-#define SCSI_Out__3__AMUX CYREG_PRT6_AMUX\r
-#define SCSI_Out__3__BIE CYREG_PRT6_BIE\r
-#define SCSI_Out__3__BIT_MASK CYREG_PRT6_BIT_MASK\r
-#define SCSI_Out__3__BYP CYREG_PRT6_BYP\r
-#define SCSI_Out__3__CTL CYREG_PRT6_CTL\r
-#define SCSI_Out__3__DM0 CYREG_PRT6_DM0\r
-#define SCSI_Out__3__DM1 CYREG_PRT6_DM1\r
-#define SCSI_Out__3__DM2 CYREG_PRT6_DM2\r
-#define SCSI_Out__3__DR CYREG_PRT6_DR\r
-#define SCSI_Out__3__INP_DIS CYREG_PRT6_INP_DIS\r
-#define SCSI_Out__3__INTTYPE CYREG_PICU6_INTTYPE0\r
-#define SCSI_Out__3__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
-#define SCSI_Out__3__LCD_EN CYREG_PRT6_LCD_EN\r
-#define SCSI_Out__3__MASK 0x01u\r
-#define SCSI_Out__3__PC CYREG_PRT6_PC0\r
-#define SCSI_Out__3__PORT 6u\r
-#define SCSI_Out__3__PRT CYREG_PRT6_PRT\r
-#define SCSI_Out__3__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
-#define SCSI_Out__3__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
-#define SCSI_Out__3__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
-#define SCSI_Out__3__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
-#define SCSI_Out__3__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
-#define SCSI_Out__3__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
-#define SCSI_Out__3__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
-#define SCSI_Out__3__PS CYREG_PRT6_PS\r
-#define SCSI_Out__3__SHIFT 0u\r
-#define SCSI_Out__3__SLW CYREG_PRT6_SLW\r
-#define SCSI_Out__4__AG CYREG_PRT4_AG\r
-#define SCSI_Out__4__AMUX CYREG_PRT4_AMUX\r
-#define SCSI_Out__4__BIE CYREG_PRT4_BIE\r
-#define SCSI_Out__4__BIT_MASK CYREG_PRT4_BIT_MASK\r
-#define SCSI_Out__4__BYP CYREG_PRT4_BYP\r
-#define SCSI_Out__4__CTL CYREG_PRT4_CTL\r
-#define SCSI_Out__4__DM0 CYREG_PRT4_DM0\r
-#define SCSI_Out__4__DM1 CYREG_PRT4_DM1\r
-#define SCSI_Out__4__DM2 CYREG_PRT4_DM2\r
-#define SCSI_Out__4__DR CYREG_PRT4_DR\r
-#define SCSI_Out__4__INP_DIS CYREG_PRT4_INP_DIS\r
-#define SCSI_Out__4__INTTYPE CYREG_PICU4_INTTYPE5\r
-#define SCSI_Out__4__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG\r
-#define SCSI_Out__4__LCD_EN CYREG_PRT4_LCD_EN\r
-#define SCSI_Out__4__MASK 0x20u\r
-#define SCSI_Out__4__PC CYREG_PRT4_PC5\r
-#define SCSI_Out__4__PORT 4u\r
-#define SCSI_Out__4__PRT CYREG_PRT4_PRT\r
-#define SCSI_Out__4__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL\r
-#define SCSI_Out__4__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN\r
-#define SCSI_Out__4__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0\r
-#define SCSI_Out__4__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1\r
-#define SCSI_Out__4__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0\r
-#define SCSI_Out__4__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1\r
-#define SCSI_Out__4__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT\r
-#define SCSI_Out__4__PS CYREG_PRT4_PS\r
-#define SCSI_Out__4__SHIFT 5u\r
-#define SCSI_Out__4__SLW CYREG_PRT4_SLW\r
-#define SCSI_Out__5__AG CYREG_PRT4_AG\r
-#define SCSI_Out__5__AMUX CYREG_PRT4_AMUX\r
-#define SCSI_Out__5__BIE CYREG_PRT4_BIE\r
-#define SCSI_Out__5__BIT_MASK CYREG_PRT4_BIT_MASK\r
-#define SCSI_Out__5__BYP CYREG_PRT4_BYP\r
-#define SCSI_Out__5__CTL CYREG_PRT4_CTL\r
-#define SCSI_Out__5__DM0 CYREG_PRT4_DM0\r
-#define SCSI_Out__5__DM1 CYREG_PRT4_DM1\r
-#define SCSI_Out__5__DM2 CYREG_PRT4_DM2\r
-#define SCSI_Out__5__DR CYREG_PRT4_DR\r
-#define SCSI_Out__5__INP_DIS CYREG_PRT4_INP_DIS\r
-#define SCSI_Out__5__INTTYPE CYREG_PICU4_INTTYPE4\r
-#define SCSI_Out__5__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG\r
-#define SCSI_Out__5__LCD_EN CYREG_PRT4_LCD_EN\r
-#define SCSI_Out__5__MASK 0x10u\r
-#define SCSI_Out__5__PC CYREG_PRT4_PC4\r
-#define SCSI_Out__5__PORT 4u\r
-#define SCSI_Out__5__PRT CYREG_PRT4_PRT\r
-#define SCSI_Out__5__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL\r
-#define SCSI_Out__5__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN\r
-#define SCSI_Out__5__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0\r
-#define SCSI_Out__5__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1\r
-#define SCSI_Out__5__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0\r
-#define SCSI_Out__5__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1\r
-#define SCSI_Out__5__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT\r
-#define SCSI_Out__5__PS CYREG_PRT4_PS\r
-#define SCSI_Out__5__SHIFT 4u\r
-#define SCSI_Out__5__SLW CYREG_PRT4_SLW\r
-#define SCSI_Out__6__AG CYREG_PRT0_AG\r
-#define SCSI_Out__6__AMUX CYREG_PRT0_AMUX\r
-#define SCSI_Out__6__BIE CYREG_PRT0_BIE\r
-#define SCSI_Out__6__BIT_MASK CYREG_PRT0_BIT_MASK\r
-#define SCSI_Out__6__BYP CYREG_PRT0_BYP\r
-#define SCSI_Out__6__CTL CYREG_PRT0_CTL\r
-#define SCSI_Out__6__DM0 CYREG_PRT0_DM0\r
-#define SCSI_Out__6__DM1 CYREG_PRT0_DM1\r
-#define SCSI_Out__6__DM2 CYREG_PRT0_DM2\r
-#define SCSI_Out__6__DR CYREG_PRT0_DR\r
-#define SCSI_Out__6__INP_DIS CYREG_PRT0_INP_DIS\r
-#define SCSI_Out__6__INTTYPE CYREG_PICU0_INTTYPE7\r
-#define SCSI_Out__6__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG\r
-#define SCSI_Out__6__LCD_EN CYREG_PRT0_LCD_EN\r
-#define SCSI_Out__6__MASK 0x80u\r
-#define SCSI_Out__6__PC CYREG_PRT0_PC7\r
-#define SCSI_Out__6__PORT 0u\r
-#define SCSI_Out__6__PRT CYREG_PRT0_PRT\r
-#define SCSI_Out__6__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL\r
-#define SCSI_Out__6__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN\r
-#define SCSI_Out__6__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0\r
-#define SCSI_Out__6__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1\r
-#define SCSI_Out__6__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0\r
-#define SCSI_Out__6__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1\r
-#define SCSI_Out__6__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT\r
-#define SCSI_Out__6__PS CYREG_PRT0_PS\r
-#define SCSI_Out__6__SHIFT 7u\r
-#define SCSI_Out__6__SLW CYREG_PRT0_SLW\r
-#define SCSI_Out__7__AG CYREG_PRT0_AG\r
-#define SCSI_Out__7__AMUX CYREG_PRT0_AMUX\r
-#define SCSI_Out__7__BIE CYREG_PRT0_BIE\r
-#define SCSI_Out__7__BIT_MASK CYREG_PRT0_BIT_MASK\r
-#define SCSI_Out__7__BYP CYREG_PRT0_BYP\r
-#define SCSI_Out__7__CTL CYREG_PRT0_CTL\r
-#define SCSI_Out__7__DM0 CYREG_PRT0_DM0\r
-#define SCSI_Out__7__DM1 CYREG_PRT0_DM1\r
-#define SCSI_Out__7__DM2 CYREG_PRT0_DM2\r
-#define SCSI_Out__7__DR CYREG_PRT0_DR\r
-#define SCSI_Out__7__INP_DIS CYREG_PRT0_INP_DIS\r
-#define SCSI_Out__7__INTTYPE CYREG_PICU0_INTTYPE6\r
-#define SCSI_Out__7__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG\r
-#define SCSI_Out__7__LCD_EN CYREG_PRT0_LCD_EN\r
-#define SCSI_Out__7__MASK 0x40u\r
-#define SCSI_Out__7__PC CYREG_PRT0_PC6\r
-#define SCSI_Out__7__PORT 0u\r
-#define SCSI_Out__7__PRT CYREG_PRT0_PRT\r
-#define SCSI_Out__7__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL\r
-#define SCSI_Out__7__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN\r
-#define SCSI_Out__7__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0\r
-#define SCSI_Out__7__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1\r
-#define SCSI_Out__7__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0\r
-#define SCSI_Out__7__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1\r
-#define SCSI_Out__7__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT\r
-#define SCSI_Out__7__PS CYREG_PRT0_PS\r
-#define SCSI_Out__7__SHIFT 6u\r
-#define SCSI_Out__7__SLW CYREG_PRT0_SLW\r
-#define SCSI_Out__8__AG CYREG_PRT0_AG\r
-#define SCSI_Out__8__AMUX CYREG_PRT0_AMUX\r
-#define SCSI_Out__8__BIE CYREG_PRT0_BIE\r
-#define SCSI_Out__8__BIT_MASK CYREG_PRT0_BIT_MASK\r
-#define SCSI_Out__8__BYP CYREG_PRT0_BYP\r
-#define SCSI_Out__8__CTL CYREG_PRT0_CTL\r
-#define SCSI_Out__8__DM0 CYREG_PRT0_DM0\r
-#define SCSI_Out__8__DM1 CYREG_PRT0_DM1\r
-#define SCSI_Out__8__DM2 CYREG_PRT0_DM2\r
-#define SCSI_Out__8__DR CYREG_PRT0_DR\r
-#define SCSI_Out__8__INP_DIS CYREG_PRT0_INP_DIS\r
-#define SCSI_Out__8__INTTYPE CYREG_PICU0_INTTYPE3\r
-#define SCSI_Out__8__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG\r
-#define SCSI_Out__8__LCD_EN CYREG_PRT0_LCD_EN\r
-#define SCSI_Out__8__MASK 0x08u\r
-#define SCSI_Out__8__PC CYREG_PRT0_PC3\r
-#define SCSI_Out__8__PORT 0u\r
-#define SCSI_Out__8__PRT CYREG_PRT0_PRT\r
-#define SCSI_Out__8__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL\r
-#define SCSI_Out__8__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN\r
-#define SCSI_Out__8__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0\r
-#define SCSI_Out__8__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1\r
-#define SCSI_Out__8__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0\r
-#define SCSI_Out__8__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1\r
-#define SCSI_Out__8__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT\r
-#define SCSI_Out__8__PS CYREG_PRT0_PS\r
-#define SCSI_Out__8__SHIFT 3u\r
-#define SCSI_Out__8__SLW CYREG_PRT0_SLW\r
-#define SCSI_Out__9__AG CYREG_PRT0_AG\r
-#define SCSI_Out__9__AMUX CYREG_PRT0_AMUX\r
-#define SCSI_Out__9__BIE CYREG_PRT0_BIE\r
-#define SCSI_Out__9__BIT_MASK CYREG_PRT0_BIT_MASK\r
-#define SCSI_Out__9__BYP CYREG_PRT0_BYP\r
-#define SCSI_Out__9__CTL CYREG_PRT0_CTL\r
-#define SCSI_Out__9__DM0 CYREG_PRT0_DM0\r
-#define SCSI_Out__9__DM1 CYREG_PRT0_DM1\r
-#define SCSI_Out__9__DM2 CYREG_PRT0_DM2\r
-#define SCSI_Out__9__DR CYREG_PRT0_DR\r
-#define SCSI_Out__9__INP_DIS CYREG_PRT0_INP_DIS\r
-#define SCSI_Out__9__INTTYPE CYREG_PICU0_INTTYPE2\r
-#define SCSI_Out__9__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG\r
-#define SCSI_Out__9__LCD_EN CYREG_PRT0_LCD_EN\r
-#define SCSI_Out__9__MASK 0x04u\r
-#define SCSI_Out__9__PC CYREG_PRT0_PC2\r
-#define SCSI_Out__9__PORT 0u\r
-#define SCSI_Out__9__PRT CYREG_PRT0_PRT\r
-#define SCSI_Out__9__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL\r
-#define SCSI_Out__9__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN\r
-#define SCSI_Out__9__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0\r
-#define SCSI_Out__9__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1\r
-#define SCSI_Out__9__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0\r
-#define SCSI_Out__9__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1\r
-#define SCSI_Out__9__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT\r
-#define SCSI_Out__9__PS CYREG_PRT0_PS\r
-#define SCSI_Out__9__SHIFT 2u\r
-#define SCSI_Out__9__SLW CYREG_PRT0_SLW\r
-#define SCSI_Out__ACK__AG CYREG_PRT6_AG\r
-#define SCSI_Out__ACK__AMUX CYREG_PRT6_AMUX\r
-#define SCSI_Out__ACK__BIE CYREG_PRT6_BIE\r
-#define SCSI_Out__ACK__BIT_MASK CYREG_PRT6_BIT_MASK\r
-#define SCSI_Out__ACK__BYP CYREG_PRT6_BYP\r
-#define SCSI_Out__ACK__CTL CYREG_PRT6_CTL\r
-#define SCSI_Out__ACK__DM0 CYREG_PRT6_DM0\r
-#define SCSI_Out__ACK__DM1 CYREG_PRT6_DM1\r
-#define SCSI_Out__ACK__DM2 CYREG_PRT6_DM2\r
-#define SCSI_Out__ACK__DR CYREG_PRT6_DR\r
-#define SCSI_Out__ACK__INP_DIS CYREG_PRT6_INP_DIS\r
-#define SCSI_Out__ACK__INTTYPE CYREG_PICU6_INTTYPE0\r
-#define SCSI_Out__ACK__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
-#define SCSI_Out__ACK__LCD_EN CYREG_PRT6_LCD_EN\r
-#define SCSI_Out__ACK__MASK 0x01u\r
-#define SCSI_Out__ACK__PC CYREG_PRT6_PC0\r
-#define SCSI_Out__ACK__PORT 6u\r
-#define SCSI_Out__ACK__PRT CYREG_PRT6_PRT\r
-#define SCSI_Out__ACK__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
-#define SCSI_Out__ACK__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
-#define SCSI_Out__ACK__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
-#define SCSI_Out__ACK__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
-#define SCSI_Out__ACK__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
-#define SCSI_Out__ACK__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
-#define SCSI_Out__ACK__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
-#define SCSI_Out__ACK__PS CYREG_PRT6_PS\r
-#define SCSI_Out__ACK__SHIFT 0u\r
-#define SCSI_Out__ACK__SLW CYREG_PRT6_SLW\r
-#define SCSI_Out__ATN__AG CYREG_PRT15_AG\r
-#define SCSI_Out__ATN__AMUX CYREG_PRT15_AMUX\r
-#define SCSI_Out__ATN__BIE CYREG_PRT15_BIE\r
-#define SCSI_Out__ATN__BIT_MASK CYREG_PRT15_BIT_MASK\r
-#define SCSI_Out__ATN__BYP CYREG_PRT15_BYP\r
-#define SCSI_Out__ATN__CTL CYREG_PRT15_CTL\r
-#define SCSI_Out__ATN__DM0 CYREG_PRT15_DM0\r
-#define SCSI_Out__ATN__DM1 CYREG_PRT15_DM1\r
-#define SCSI_Out__ATN__DM2 CYREG_PRT15_DM2\r
-#define SCSI_Out__ATN__DR CYREG_PRT15_DR\r
-#define SCSI_Out__ATN__INP_DIS CYREG_PRT15_INP_DIS\r
-#define SCSI_Out__ATN__INTTYPE CYREG_PICU15_INTTYPE4\r
-#define SCSI_Out__ATN__LCD_COM_SEG CYREG_PRT15_LCD_COM_SEG\r
-#define SCSI_Out__ATN__LCD_EN CYREG_PRT15_LCD_EN\r
-#define SCSI_Out__ATN__MASK 0x10u\r
-#define SCSI_Out__ATN__PC CYREG_IO_PC_PRT15_PC4\r
-#define SCSI_Out__ATN__PORT 15u\r
-#define SCSI_Out__ATN__PRT CYREG_PRT15_PRT\r
-#define SCSI_Out__ATN__PRTDSI__CAPS_SEL CYREG_PRT15_CAPS_SEL\r
-#define SCSI_Out__ATN__PRTDSI__DBL_SYNC_IN CYREG_PRT15_DBL_SYNC_IN\r
-#define SCSI_Out__ATN__PRTDSI__OE_SEL0 CYREG_PRT15_OE_SEL0\r
-#define SCSI_Out__ATN__PRTDSI__OE_SEL1 CYREG_PRT15_OE_SEL1\r
-#define SCSI_Out__ATN__PRTDSI__OUT_SEL0 CYREG_PRT15_OUT_SEL0\r
-#define SCSI_Out__ATN__PRTDSI__OUT_SEL1 CYREG_PRT15_OUT_SEL1\r
-#define SCSI_Out__ATN__PRTDSI__SYNC_OUT CYREG_PRT15_SYNC_OUT\r
-#define SCSI_Out__ATN__PS CYREG_PRT15_PS\r
-#define SCSI_Out__ATN__SHIFT 4u\r
-#define SCSI_Out__ATN__SLW CYREG_PRT15_SLW\r
-#define SCSI_Out__BSY__AG CYREG_PRT6_AG\r
-#define SCSI_Out__BSY__AMUX CYREG_PRT6_AMUX\r
-#define SCSI_Out__BSY__BIE CYREG_PRT6_BIE\r
-#define SCSI_Out__BSY__BIT_MASK CYREG_PRT6_BIT_MASK\r
-#define SCSI_Out__BSY__BYP CYREG_PRT6_BYP\r
-#define SCSI_Out__BSY__CTL CYREG_PRT6_CTL\r
-#define SCSI_Out__BSY__DM0 CYREG_PRT6_DM0\r
-#define SCSI_Out__BSY__DM1 CYREG_PRT6_DM1\r
-#define SCSI_Out__BSY__DM2 CYREG_PRT6_DM2\r
-#define SCSI_Out__BSY__DR CYREG_PRT6_DR\r
-#define SCSI_Out__BSY__INP_DIS CYREG_PRT6_INP_DIS\r
-#define SCSI_Out__BSY__INTTYPE CYREG_PICU6_INTTYPE1\r
-#define SCSI_Out__BSY__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
-#define SCSI_Out__BSY__LCD_EN CYREG_PRT6_LCD_EN\r
-#define SCSI_Out__BSY__MASK 0x02u\r
-#define SCSI_Out__BSY__PC CYREG_PRT6_PC1\r
-#define SCSI_Out__BSY__PORT 6u\r
-#define SCSI_Out__BSY__PRT CYREG_PRT6_PRT\r
-#define SCSI_Out__BSY__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
-#define SCSI_Out__BSY__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
-#define SCSI_Out__BSY__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
-#define SCSI_Out__BSY__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
-#define SCSI_Out__BSY__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
-#define SCSI_Out__BSY__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
-#define SCSI_Out__BSY__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
-#define SCSI_Out__BSY__PS CYREG_PRT6_PS\r
-#define SCSI_Out__BSY__SHIFT 1u\r
-#define SCSI_Out__BSY__SLW CYREG_PRT6_SLW\r
-#define SCSI_Out__CD_raw__AG CYREG_PRT0_AG\r
-#define SCSI_Out__CD_raw__AMUX CYREG_PRT0_AMUX\r
-#define SCSI_Out__CD_raw__BIE CYREG_PRT0_BIE\r
-#define SCSI_Out__CD_raw__BIT_MASK CYREG_PRT0_BIT_MASK\r
-#define SCSI_Out__CD_raw__BYP CYREG_PRT0_BYP\r
-#define SCSI_Out__CD_raw__CTL CYREG_PRT0_CTL\r
-#define SCSI_Out__CD_raw__DM0 CYREG_PRT0_DM0\r
-#define SCSI_Out__CD_raw__DM1 CYREG_PRT0_DM1\r
-#define SCSI_Out__CD_raw__DM2 CYREG_PRT0_DM2\r
-#define SCSI_Out__CD_raw__DR CYREG_PRT0_DR\r
-#define SCSI_Out__CD_raw__INP_DIS CYREG_PRT0_INP_DIS\r
-#define SCSI_Out__CD_raw__INTTYPE CYREG_PICU0_INTTYPE6\r
-#define SCSI_Out__CD_raw__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG\r
-#define SCSI_Out__CD_raw__LCD_EN CYREG_PRT0_LCD_EN\r
-#define SCSI_Out__CD_raw__MASK 0x40u\r
-#define SCSI_Out__CD_raw__PC CYREG_PRT0_PC6\r
-#define SCSI_Out__CD_raw__PORT 0u\r
-#define SCSI_Out__CD_raw__PRT CYREG_PRT0_PRT\r
-#define SCSI_Out__CD_raw__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL\r
-#define SCSI_Out__CD_raw__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN\r
-#define SCSI_Out__CD_raw__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0\r
-#define SCSI_Out__CD_raw__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1\r
-#define SCSI_Out__CD_raw__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0\r
-#define SCSI_Out__CD_raw__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1\r
-#define SCSI_Out__CD_raw__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT\r
-#define SCSI_Out__CD_raw__PS CYREG_PRT0_PS\r
-#define SCSI_Out__CD_raw__SHIFT 6u\r
-#define SCSI_Out__CD_raw__SLW CYREG_PRT0_SLW\r
-#define SCSI_Out__DBP_raw__AG CYREG_PRT15_AG\r
-#define SCSI_Out__DBP_raw__AMUX CYREG_PRT15_AMUX\r
-#define SCSI_Out__DBP_raw__BIE CYREG_PRT15_BIE\r
-#define SCSI_Out__DBP_raw__BIT_MASK CYREG_PRT15_BIT_MASK\r
-#define SCSI_Out__DBP_raw__BYP CYREG_PRT15_BYP\r
-#define SCSI_Out__DBP_raw__CTL CYREG_PRT15_CTL\r
-#define SCSI_Out__DBP_raw__DM0 CYREG_PRT15_DM0\r
-#define SCSI_Out__DBP_raw__DM1 CYREG_PRT15_DM1\r
-#define SCSI_Out__DBP_raw__DM2 CYREG_PRT15_DM2\r
-#define SCSI_Out__DBP_raw__DR CYREG_PRT15_DR\r
-#define SCSI_Out__DBP_raw__INP_DIS CYREG_PRT15_INP_DIS\r
-#define SCSI_Out__DBP_raw__INTTYPE CYREG_PICU15_INTTYPE5\r
-#define SCSI_Out__DBP_raw__LCD_COM_SEG CYREG_PRT15_LCD_COM_SEG\r
-#define SCSI_Out__DBP_raw__LCD_EN CYREG_PRT15_LCD_EN\r
-#define SCSI_Out__DBP_raw__MASK 0x20u\r
-#define SCSI_Out__DBP_raw__PC CYREG_IO_PC_PRT15_PC5\r
-#define SCSI_Out__DBP_raw__PORT 15u\r
-#define SCSI_Out__DBP_raw__PRT CYREG_PRT15_PRT\r
-#define SCSI_Out__DBP_raw__PRTDSI__CAPS_SEL CYREG_PRT15_CAPS_SEL\r
-#define SCSI_Out__DBP_raw__PRTDSI__DBL_SYNC_IN CYREG_PRT15_DBL_SYNC_IN\r
-#define SCSI_Out__DBP_raw__PRTDSI__OE_SEL0 CYREG_PRT15_OE_SEL0\r
-#define SCSI_Out__DBP_raw__PRTDSI__OE_SEL1 CYREG_PRT15_OE_SEL1\r
-#define SCSI_Out__DBP_raw__PRTDSI__OUT_SEL0 CYREG_PRT15_OUT_SEL0\r
-#define SCSI_Out__DBP_raw__PRTDSI__OUT_SEL1 CYREG_PRT15_OUT_SEL1\r
-#define SCSI_Out__DBP_raw__PRTDSI__SYNC_OUT CYREG_PRT15_SYNC_OUT\r
-#define SCSI_Out__DBP_raw__PS CYREG_PRT15_PS\r
-#define SCSI_Out__DBP_raw__SHIFT 5u\r
-#define SCSI_Out__DBP_raw__SLW CYREG_PRT15_SLW\r
-#define SCSI_Out__IO_raw__AG CYREG_PRT0_AG\r
-#define SCSI_Out__IO_raw__AMUX CYREG_PRT0_AMUX\r
-#define SCSI_Out__IO_raw__BIE CYREG_PRT0_BIE\r
-#define SCSI_Out__IO_raw__BIT_MASK CYREG_PRT0_BIT_MASK\r
-#define SCSI_Out__IO_raw__BYP CYREG_PRT0_BYP\r
-#define SCSI_Out__IO_raw__CTL CYREG_PRT0_CTL\r
-#define SCSI_Out__IO_raw__DM0 CYREG_PRT0_DM0\r
-#define SCSI_Out__IO_raw__DM1 CYREG_PRT0_DM1\r
-#define SCSI_Out__IO_raw__DM2 CYREG_PRT0_DM2\r
-#define SCSI_Out__IO_raw__DR CYREG_PRT0_DR\r
-#define SCSI_Out__IO_raw__INP_DIS CYREG_PRT0_INP_DIS\r
-#define SCSI_Out__IO_raw__INTTYPE CYREG_PICU0_INTTYPE2\r
-#define SCSI_Out__IO_raw__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG\r
-#define SCSI_Out__IO_raw__LCD_EN CYREG_PRT0_LCD_EN\r
-#define SCSI_Out__IO_raw__MASK 0x04u\r
-#define SCSI_Out__IO_raw__PC CYREG_PRT0_PC2\r
-#define SCSI_Out__IO_raw__PORT 0u\r
-#define SCSI_Out__IO_raw__PRT CYREG_PRT0_PRT\r
-#define SCSI_Out__IO_raw__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL\r
-#define SCSI_Out__IO_raw__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN\r
-#define SCSI_Out__IO_raw__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0\r
-#define SCSI_Out__IO_raw__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1\r
-#define SCSI_Out__IO_raw__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0\r
-#define SCSI_Out__IO_raw__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1\r
-#define SCSI_Out__IO_raw__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT\r
-#define SCSI_Out__IO_raw__PS CYREG_PRT0_PS\r
-#define SCSI_Out__IO_raw__SHIFT 2u\r
-#define SCSI_Out__IO_raw__SLW CYREG_PRT0_SLW\r
-#define SCSI_Out__MSG_raw__AG CYREG_PRT4_AG\r
-#define SCSI_Out__MSG_raw__AMUX CYREG_PRT4_AMUX\r
-#define SCSI_Out__MSG_raw__BIE CYREG_PRT4_BIE\r
-#define SCSI_Out__MSG_raw__BIT_MASK CYREG_PRT4_BIT_MASK\r
-#define SCSI_Out__MSG_raw__BYP CYREG_PRT4_BYP\r
-#define SCSI_Out__MSG_raw__CTL CYREG_PRT4_CTL\r
-#define SCSI_Out__MSG_raw__DM0 CYREG_PRT4_DM0\r
-#define SCSI_Out__MSG_raw__DM1 CYREG_PRT4_DM1\r
-#define SCSI_Out__MSG_raw__DM2 CYREG_PRT4_DM2\r
-#define SCSI_Out__MSG_raw__DR CYREG_PRT4_DR\r
-#define SCSI_Out__MSG_raw__INP_DIS CYREG_PRT4_INP_DIS\r
-#define SCSI_Out__MSG_raw__INTTYPE CYREG_PICU4_INTTYPE4\r
-#define SCSI_Out__MSG_raw__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG\r
-#define SCSI_Out__MSG_raw__LCD_EN CYREG_PRT4_LCD_EN\r
-#define SCSI_Out__MSG_raw__MASK 0x10u\r
-#define SCSI_Out__MSG_raw__PC CYREG_PRT4_PC4\r
-#define SCSI_Out__MSG_raw__PORT 4u\r
-#define SCSI_Out__MSG_raw__PRT CYREG_PRT4_PRT\r
-#define SCSI_Out__MSG_raw__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL\r
-#define SCSI_Out__MSG_raw__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN\r
-#define SCSI_Out__MSG_raw__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0\r
-#define SCSI_Out__MSG_raw__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1\r
-#define SCSI_Out__MSG_raw__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0\r
-#define SCSI_Out__MSG_raw__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1\r
-#define SCSI_Out__MSG_raw__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT\r
-#define SCSI_Out__MSG_raw__PS CYREG_PRT4_PS\r
-#define SCSI_Out__MSG_raw__SHIFT 4u\r
-#define SCSI_Out__MSG_raw__SLW CYREG_PRT4_SLW\r
-#define SCSI_Out__REQ__AG CYREG_PRT0_AG\r
-#define SCSI_Out__REQ__AMUX CYREG_PRT0_AMUX\r
-#define SCSI_Out__REQ__BIE CYREG_PRT0_BIE\r
-#define SCSI_Out__REQ__BIT_MASK CYREG_PRT0_BIT_MASK\r
-#define SCSI_Out__REQ__BYP CYREG_PRT0_BYP\r
-#define SCSI_Out__REQ__CTL CYREG_PRT0_CTL\r
-#define SCSI_Out__REQ__DM0 CYREG_PRT0_DM0\r
-#define SCSI_Out__REQ__DM1 CYREG_PRT0_DM1\r
-#define SCSI_Out__REQ__DM2 CYREG_PRT0_DM2\r
-#define SCSI_Out__REQ__DR CYREG_PRT0_DR\r
-#define SCSI_Out__REQ__INP_DIS CYREG_PRT0_INP_DIS\r
-#define SCSI_Out__REQ__INTTYPE CYREG_PICU0_INTTYPE3\r
-#define SCSI_Out__REQ__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG\r
-#define SCSI_Out__REQ__LCD_EN CYREG_PRT0_LCD_EN\r
-#define SCSI_Out__REQ__MASK 0x08u\r
-#define SCSI_Out__REQ__PC CYREG_PRT0_PC3\r
-#define SCSI_Out__REQ__PORT 0u\r
-#define SCSI_Out__REQ__PRT CYREG_PRT0_PRT\r
-#define SCSI_Out__REQ__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL\r
-#define SCSI_Out__REQ__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN\r
-#define SCSI_Out__REQ__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0\r
-#define SCSI_Out__REQ__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1\r
-#define SCSI_Out__REQ__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0\r
-#define SCSI_Out__REQ__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1\r
-#define SCSI_Out__REQ__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT\r
-#define SCSI_Out__REQ__PS CYREG_PRT0_PS\r
-#define SCSI_Out__REQ__SHIFT 3u\r
-#define SCSI_Out__REQ__SLW CYREG_PRT0_SLW\r
-#define SCSI_Out__RST__AG CYREG_PRT4_AG\r
-#define SCSI_Out__RST__AMUX CYREG_PRT4_AMUX\r
-#define SCSI_Out__RST__BIE CYREG_PRT4_BIE\r
-#define SCSI_Out__RST__BIT_MASK CYREG_PRT4_BIT_MASK\r
-#define SCSI_Out__RST__BYP CYREG_PRT4_BYP\r
-#define SCSI_Out__RST__CTL CYREG_PRT4_CTL\r
-#define SCSI_Out__RST__DM0 CYREG_PRT4_DM0\r
-#define SCSI_Out__RST__DM1 CYREG_PRT4_DM1\r
-#define SCSI_Out__RST__DM2 CYREG_PRT4_DM2\r
-#define SCSI_Out__RST__DR CYREG_PRT4_DR\r
-#define SCSI_Out__RST__INP_DIS CYREG_PRT4_INP_DIS\r
-#define SCSI_Out__RST__INTTYPE CYREG_PICU4_INTTYPE5\r
-#define SCSI_Out__RST__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG\r
-#define SCSI_Out__RST__LCD_EN CYREG_PRT4_LCD_EN\r
-#define SCSI_Out__RST__MASK 0x20u\r
-#define SCSI_Out__RST__PC CYREG_PRT4_PC5\r
-#define SCSI_Out__RST__PORT 4u\r
-#define SCSI_Out__RST__PRT CYREG_PRT4_PRT\r
-#define SCSI_Out__RST__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL\r
-#define SCSI_Out__RST__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN\r
-#define SCSI_Out__RST__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0\r
-#define SCSI_Out__RST__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1\r
-#define SCSI_Out__RST__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0\r
-#define SCSI_Out__RST__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1\r
-#define SCSI_Out__RST__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT\r
-#define SCSI_Out__RST__PS CYREG_PRT4_PS\r
-#define SCSI_Out__RST__SHIFT 5u\r
-#define SCSI_Out__RST__SLW CYREG_PRT4_SLW\r
-#define SCSI_Out__SEL__AG CYREG_PRT0_AG\r
-#define SCSI_Out__SEL__AMUX CYREG_PRT0_AMUX\r
-#define SCSI_Out__SEL__BIE CYREG_PRT0_BIE\r
-#define SCSI_Out__SEL__BIT_MASK CYREG_PRT0_BIT_MASK\r
-#define SCSI_Out__SEL__BYP CYREG_PRT0_BYP\r
-#define SCSI_Out__SEL__CTL CYREG_PRT0_CTL\r
-#define SCSI_Out__SEL__DM0 CYREG_PRT0_DM0\r
-#define SCSI_Out__SEL__DM1 CYREG_PRT0_DM1\r
-#define SCSI_Out__SEL__DM2 CYREG_PRT0_DM2\r
-#define SCSI_Out__SEL__DR CYREG_PRT0_DR\r
-#define SCSI_Out__SEL__INP_DIS CYREG_PRT0_INP_DIS\r
-#define SCSI_Out__SEL__INTTYPE CYREG_PICU0_INTTYPE7\r
-#define SCSI_Out__SEL__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG\r
-#define SCSI_Out__SEL__LCD_EN CYREG_PRT0_LCD_EN\r
-#define SCSI_Out__SEL__MASK 0x80u\r
-#define SCSI_Out__SEL__PC CYREG_PRT0_PC7\r
-#define SCSI_Out__SEL__PORT 0u\r
-#define SCSI_Out__SEL__PRT CYREG_PRT0_PRT\r
-#define SCSI_Out__SEL__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL\r
-#define SCSI_Out__SEL__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN\r
-#define SCSI_Out__SEL__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0\r
-#define SCSI_Out__SEL__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1\r
-#define SCSI_Out__SEL__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0\r
-#define SCSI_Out__SEL__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1\r
-#define SCSI_Out__SEL__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT\r
-#define SCSI_Out__SEL__PS CYREG_PRT0_PS\r
-#define SCSI_Out__SEL__SHIFT 7u\r
-#define SCSI_Out__SEL__SLW CYREG_PRT0_SLW\r
-\r
-/* SCSI_Out_Bits */\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__0__MASK 0x01u\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__0__POS 0\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__1__MASK 0x02u\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__1__POS 1\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB14_15_ACTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB14_15_CTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB14_15_CTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB14_15_CTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB14_15_CTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB14_15_MSK\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB14_15_MSK\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB14_15_MSK\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB14_15_MSK\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__2__MASK 0x04u\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__2__POS 2\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__3__MASK 0x08u\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__3__POS 3\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__4__MASK 0x10u\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__4__POS 4\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__5__MASK 0x20u\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__5__POS 5\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__6__MASK 0x40u\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__6__POS 6\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__7__MASK 0x80u\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__7__POS 7\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB14_ACTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB14_CTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB14_ST_CTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB14_CTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB14_ST_CTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__MASK 0xFFu\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB14_MSK_ACTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB14_MSK_ACTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB14_MSK\r
-\r
-/* SCSI_Out_Ctl */\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK 0x01u\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__0__POS 0\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB12_13_ACTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB12_13_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB12_13_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB12_13_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB12_13_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB12_13_MSK\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB12_13_MSK\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB12_13_MSK\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB12_13_MSK\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB12_ACTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB12_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB12_ST_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB12_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB12_ST_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK 0x01u\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB12_MSK\r
-\r
-/* SCSI_Out_DBx */\r
-#define SCSI_Out_DBx__0__AG CYREG_PRT5_AG\r
-#define SCSI_Out_DBx__0__AMUX CYREG_PRT5_AMUX\r
-#define SCSI_Out_DBx__0__BIE CYREG_PRT5_BIE\r
-#define SCSI_Out_DBx__0__BIT_MASK CYREG_PRT5_BIT_MASK\r
-#define SCSI_Out_DBx__0__BYP CYREG_PRT5_BYP\r
-#define SCSI_Out_DBx__0__CTL CYREG_PRT5_CTL\r
-#define SCSI_Out_DBx__0__DM0 CYREG_PRT5_DM0\r
-#define SCSI_Out_DBx__0__DM1 CYREG_PRT5_DM1\r
-#define SCSI_Out_DBx__0__DM2 CYREG_PRT5_DM2\r
-#define SCSI_Out_DBx__0__DR CYREG_PRT5_DR\r
-#define SCSI_Out_DBx__0__INP_DIS CYREG_PRT5_INP_DIS\r
-#define SCSI_Out_DBx__0__INTTYPE CYREG_PICU5_INTTYPE1\r
-#define SCSI_Out_DBx__0__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG\r
-#define SCSI_Out_DBx__0__LCD_EN CYREG_PRT5_LCD_EN\r
-#define SCSI_Out_DBx__0__MASK 0x02u\r
-#define SCSI_Out_DBx__0__PC CYREG_PRT5_PC1\r
-#define SCSI_Out_DBx__0__PORT 5u\r
-#define SCSI_Out_DBx__0__PRT CYREG_PRT5_PRT\r
-#define SCSI_Out_DBx__0__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL\r
-#define SCSI_Out_DBx__0__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN\r
-#define SCSI_Out_DBx__0__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0\r
-#define SCSI_Out_DBx__0__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1\r
-#define SCSI_Out_DBx__0__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0\r
-#define SCSI_Out_DBx__0__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1\r
-#define SCSI_Out_DBx__0__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT\r
-#define SCSI_Out_DBx__0__PS CYREG_PRT5_PS\r
-#define SCSI_Out_DBx__0__SHIFT 1u\r
-#define SCSI_Out_DBx__0__SLW CYREG_PRT5_SLW\r
-#define SCSI_Out_DBx__1__AG CYREG_PRT5_AG\r
-#define SCSI_Out_DBx__1__AMUX CYREG_PRT5_AMUX\r
-#define SCSI_Out_DBx__1__BIE CYREG_PRT5_BIE\r
-#define SCSI_Out_DBx__1__BIT_MASK CYREG_PRT5_BIT_MASK\r
-#define SCSI_Out_DBx__1__BYP CYREG_PRT5_BYP\r
-#define SCSI_Out_DBx__1__CTL CYREG_PRT5_CTL\r
-#define SCSI_Out_DBx__1__DM0 CYREG_PRT5_DM0\r
-#define SCSI_Out_DBx__1__DM1 CYREG_PRT5_DM1\r
-#define SCSI_Out_DBx__1__DM2 CYREG_PRT5_DM2\r
-#define SCSI_Out_DBx__1__DR CYREG_PRT5_DR\r
-#define SCSI_Out_DBx__1__INP_DIS CYREG_PRT5_INP_DIS\r
-#define SCSI_Out_DBx__1__INTTYPE CYREG_PICU5_INTTYPE0\r
-#define SCSI_Out_DBx__1__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG\r
-#define SCSI_Out_DBx__1__LCD_EN CYREG_PRT5_LCD_EN\r
-#define SCSI_Out_DBx__1__MASK 0x01u\r
-#define SCSI_Out_DBx__1__PC CYREG_PRT5_PC0\r
-#define SCSI_Out_DBx__1__PORT 5u\r
-#define SCSI_Out_DBx__1__PRT CYREG_PRT5_PRT\r
-#define SCSI_Out_DBx__1__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL\r
-#define SCSI_Out_DBx__1__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN\r
-#define SCSI_Out_DBx__1__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0\r
-#define SCSI_Out_DBx__1__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1\r
-#define SCSI_Out_DBx__1__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0\r
-#define SCSI_Out_DBx__1__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1\r
-#define SCSI_Out_DBx__1__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT\r
-#define SCSI_Out_DBx__1__PS CYREG_PRT5_PS\r
-#define SCSI_Out_DBx__1__SHIFT 0u\r
-#define SCSI_Out_DBx__1__SLW CYREG_PRT5_SLW\r
-#define SCSI_Out_DBx__2__AG CYREG_PRT6_AG\r
-#define SCSI_Out_DBx__2__AMUX CYREG_PRT6_AMUX\r
-#define SCSI_Out_DBx__2__BIE CYREG_PRT6_BIE\r
-#define SCSI_Out_DBx__2__BIT_MASK CYREG_PRT6_BIT_MASK\r
-#define SCSI_Out_DBx__2__BYP CYREG_PRT6_BYP\r
-#define SCSI_Out_DBx__2__CTL CYREG_PRT6_CTL\r
-#define SCSI_Out_DBx__2__DM0 CYREG_PRT6_DM0\r
-#define SCSI_Out_DBx__2__DM1 CYREG_PRT6_DM1\r
-#define SCSI_Out_DBx__2__DM2 CYREG_PRT6_DM2\r
-#define SCSI_Out_DBx__2__DR CYREG_PRT6_DR\r
-#define SCSI_Out_DBx__2__INP_DIS CYREG_PRT6_INP_DIS\r
-#define SCSI_Out_DBx__2__INTTYPE CYREG_PICU6_INTTYPE5\r
-#define SCSI_Out_DBx__2__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
-#define SCSI_Out_DBx__2__LCD_EN CYREG_PRT6_LCD_EN\r
-#define SCSI_Out_DBx__2__MASK 0x20u\r
-#define SCSI_Out_DBx__2__PC CYREG_PRT6_PC5\r
-#define SCSI_Out_DBx__2__PORT 6u\r
-#define SCSI_Out_DBx__2__PRT CYREG_PRT6_PRT\r
-#define SCSI_Out_DBx__2__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
-#define SCSI_Out_DBx__2__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
-#define SCSI_Out_DBx__2__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
-#define SCSI_Out_DBx__2__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
-#define SCSI_Out_DBx__2__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
-#define SCSI_Out_DBx__2__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
-#define SCSI_Out_DBx__2__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
-#define SCSI_Out_DBx__2__PS CYREG_PRT6_PS\r
-#define SCSI_Out_DBx__2__SHIFT 5u\r
-#define SCSI_Out_DBx__2__SLW CYREG_PRT6_SLW\r
-#define SCSI_Out_DBx__3__AG CYREG_PRT6_AG\r
-#define SCSI_Out_DBx__3__AMUX CYREG_PRT6_AMUX\r
-#define SCSI_Out_DBx__3__BIE CYREG_PRT6_BIE\r
-#define SCSI_Out_DBx__3__BIT_MASK CYREG_PRT6_BIT_MASK\r
-#define SCSI_Out_DBx__3__BYP CYREG_PRT6_BYP\r
-#define SCSI_Out_DBx__3__CTL CYREG_PRT6_CTL\r
-#define SCSI_Out_DBx__3__DM0 CYREG_PRT6_DM0\r
-#define SCSI_Out_DBx__3__DM1 CYREG_PRT6_DM1\r
-#define SCSI_Out_DBx__3__DM2 CYREG_PRT6_DM2\r
-#define SCSI_Out_DBx__3__DR CYREG_PRT6_DR\r
-#define SCSI_Out_DBx__3__INP_DIS CYREG_PRT6_INP_DIS\r
-#define SCSI_Out_DBx__3__INTTYPE CYREG_PICU6_INTTYPE4\r
-#define SCSI_Out_DBx__3__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
-#define SCSI_Out_DBx__3__LCD_EN CYREG_PRT6_LCD_EN\r
-#define SCSI_Out_DBx__3__MASK 0x10u\r
-#define SCSI_Out_DBx__3__PC CYREG_PRT6_PC4\r
-#define SCSI_Out_DBx__3__PORT 6u\r
-#define SCSI_Out_DBx__3__PRT CYREG_PRT6_PRT\r
-#define SCSI_Out_DBx__3__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
-#define SCSI_Out_DBx__3__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
-#define SCSI_Out_DBx__3__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
-#define SCSI_Out_DBx__3__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
-#define SCSI_Out_DBx__3__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
-#define SCSI_Out_DBx__3__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
-#define SCSI_Out_DBx__3__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
-#define SCSI_Out_DBx__3__PS CYREG_PRT6_PS\r
-#define SCSI_Out_DBx__3__SHIFT 4u\r
-#define SCSI_Out_DBx__3__SLW CYREG_PRT6_SLW\r
-#define SCSI_Out_DBx__4__AG CYREG_PRT2_AG\r
-#define SCSI_Out_DBx__4__AMUX CYREG_PRT2_AMUX\r
-#define SCSI_Out_DBx__4__BIE CYREG_PRT2_BIE\r
-#define SCSI_Out_DBx__4__BIT_MASK CYREG_PRT2_BIT_MASK\r
-#define SCSI_Out_DBx__4__BYP CYREG_PRT2_BYP\r
-#define SCSI_Out_DBx__4__CTL CYREG_PRT2_CTL\r
-#define SCSI_Out_DBx__4__DM0 CYREG_PRT2_DM0\r
-#define SCSI_Out_DBx__4__DM1 CYREG_PRT2_DM1\r
-#define SCSI_Out_DBx__4__DM2 CYREG_PRT2_DM2\r
-#define SCSI_Out_DBx__4__DR CYREG_PRT2_DR\r
-#define SCSI_Out_DBx__4__INP_DIS CYREG_PRT2_INP_DIS\r
-#define SCSI_Out_DBx__4__INTTYPE CYREG_PICU2_INTTYPE7\r
-#define SCSI_Out_DBx__4__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG\r
-#define SCSI_Out_DBx__4__LCD_EN CYREG_PRT2_LCD_EN\r
-#define SCSI_Out_DBx__4__MASK 0x80u\r
-#define SCSI_Out_DBx__4__PC CYREG_PRT2_PC7\r
-#define SCSI_Out_DBx__4__PORT 2u\r
-#define SCSI_Out_DBx__4__PRT CYREG_PRT2_PRT\r
-#define SCSI_Out_DBx__4__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL\r
-#define SCSI_Out_DBx__4__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN\r
-#define SCSI_Out_DBx__4__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0\r
-#define SCSI_Out_DBx__4__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1\r
-#define SCSI_Out_DBx__4__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0\r
-#define SCSI_Out_DBx__4__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1\r
-#define SCSI_Out_DBx__4__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT\r
-#define SCSI_Out_DBx__4__PS CYREG_PRT2_PS\r
-#define SCSI_Out_DBx__4__SHIFT 7u\r
-#define SCSI_Out_DBx__4__SLW CYREG_PRT2_SLW\r
-#define SCSI_Out_DBx__5__AG CYREG_PRT2_AG\r
-#define SCSI_Out_DBx__5__AMUX CYREG_PRT2_AMUX\r
-#define SCSI_Out_DBx__5__BIE CYREG_PRT2_BIE\r
-#define SCSI_Out_DBx__5__BIT_MASK CYREG_PRT2_BIT_MASK\r
-#define SCSI_Out_DBx__5__BYP CYREG_PRT2_BYP\r
-#define SCSI_Out_DBx__5__CTL CYREG_PRT2_CTL\r
-#define SCSI_Out_DBx__5__DM0 CYREG_PRT2_DM0\r
-#define SCSI_Out_DBx__5__DM1 CYREG_PRT2_DM1\r
-#define SCSI_Out_DBx__5__DM2 CYREG_PRT2_DM2\r
-#define SCSI_Out_DBx__5__DR CYREG_PRT2_DR\r
-#define SCSI_Out_DBx__5__INP_DIS CYREG_PRT2_INP_DIS\r
-#define SCSI_Out_DBx__5__INTTYPE CYREG_PICU2_INTTYPE6\r
-#define SCSI_Out_DBx__5__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG\r
-#define SCSI_Out_DBx__5__LCD_EN CYREG_PRT2_LCD_EN\r
-#define SCSI_Out_DBx__5__MASK 0x40u\r
-#define SCSI_Out_DBx__5__PC CYREG_PRT2_PC6\r
-#define SCSI_Out_DBx__5__PORT 2u\r
-#define SCSI_Out_DBx__5__PRT CYREG_PRT2_PRT\r
-#define SCSI_Out_DBx__5__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL\r
-#define SCSI_Out_DBx__5__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN\r
-#define SCSI_Out_DBx__5__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0\r
-#define SCSI_Out_DBx__5__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1\r
-#define SCSI_Out_DBx__5__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0\r
-#define SCSI_Out_DBx__5__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1\r
-#define SCSI_Out_DBx__5__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT\r
-#define SCSI_Out_DBx__5__PS CYREG_PRT2_PS\r
-#define SCSI_Out_DBx__5__SHIFT 6u\r
-#define SCSI_Out_DBx__5__SLW CYREG_PRT2_SLW\r
-#define SCSI_Out_DBx__6__AG CYREG_PRT2_AG\r
-#define SCSI_Out_DBx__6__AMUX CYREG_PRT2_AMUX\r
-#define SCSI_Out_DBx__6__BIE CYREG_PRT2_BIE\r
-#define SCSI_Out_DBx__6__BIT_MASK CYREG_PRT2_BIT_MASK\r
-#define SCSI_Out_DBx__6__BYP CYREG_PRT2_BYP\r
-#define SCSI_Out_DBx__6__CTL CYREG_PRT2_CTL\r
-#define SCSI_Out_DBx__6__DM0 CYREG_PRT2_DM0\r
-#define SCSI_Out_DBx__6__DM1 CYREG_PRT2_DM1\r
-#define SCSI_Out_DBx__6__DM2 CYREG_PRT2_DM2\r
-#define SCSI_Out_DBx__6__DR CYREG_PRT2_DR\r
-#define SCSI_Out_DBx__6__INP_DIS CYREG_PRT2_INP_DIS\r
-#define SCSI_Out_DBx__6__INTTYPE CYREG_PICU2_INTTYPE3\r
-#define SCSI_Out_DBx__6__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG\r
-#define SCSI_Out_DBx__6__LCD_EN CYREG_PRT2_LCD_EN\r
-#define SCSI_Out_DBx__6__MASK 0x08u\r
-#define SCSI_Out_DBx__6__PC CYREG_PRT2_PC3\r
-#define SCSI_Out_DBx__6__PORT 2u\r
-#define SCSI_Out_DBx__6__PRT CYREG_PRT2_PRT\r
-#define SCSI_Out_DBx__6__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL\r
-#define SCSI_Out_DBx__6__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN\r
-#define SCSI_Out_DBx__6__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0\r
-#define SCSI_Out_DBx__6__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1\r
-#define SCSI_Out_DBx__6__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0\r
-#define SCSI_Out_DBx__6__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1\r
-#define SCSI_Out_DBx__6__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT\r
-#define SCSI_Out_DBx__6__PS CYREG_PRT2_PS\r
-#define SCSI_Out_DBx__6__SHIFT 3u\r
-#define SCSI_Out_DBx__6__SLW CYREG_PRT2_SLW\r
-#define SCSI_Out_DBx__7__AG CYREG_PRT2_AG\r
-#define SCSI_Out_DBx__7__AMUX CYREG_PRT2_AMUX\r
-#define SCSI_Out_DBx__7__BIE CYREG_PRT2_BIE\r
-#define SCSI_Out_DBx__7__BIT_MASK CYREG_PRT2_BIT_MASK\r
-#define SCSI_Out_DBx__7__BYP CYREG_PRT2_BYP\r
-#define SCSI_Out_DBx__7__CTL CYREG_PRT2_CTL\r
-#define SCSI_Out_DBx__7__DM0 CYREG_PRT2_DM0\r
-#define SCSI_Out_DBx__7__DM1 CYREG_PRT2_DM1\r
-#define SCSI_Out_DBx__7__DM2 CYREG_PRT2_DM2\r
-#define SCSI_Out_DBx__7__DR CYREG_PRT2_DR\r
-#define SCSI_Out_DBx__7__INP_DIS CYREG_PRT2_INP_DIS\r
-#define SCSI_Out_DBx__7__INTTYPE CYREG_PICU2_INTTYPE2\r
-#define SCSI_Out_DBx__7__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG\r
-#define SCSI_Out_DBx__7__LCD_EN CYREG_PRT2_LCD_EN\r
-#define SCSI_Out_DBx__7__MASK 0x04u\r
-#define SCSI_Out_DBx__7__PC CYREG_PRT2_PC2\r
-#define SCSI_Out_DBx__7__PORT 2u\r
-#define SCSI_Out_DBx__7__PRT CYREG_PRT2_PRT\r
-#define SCSI_Out_DBx__7__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL\r
-#define SCSI_Out_DBx__7__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN\r
-#define SCSI_Out_DBx__7__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0\r
-#define SCSI_Out_DBx__7__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1\r
-#define SCSI_Out_DBx__7__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0\r
-#define SCSI_Out_DBx__7__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1\r
-#define SCSI_Out_DBx__7__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT\r
-#define SCSI_Out_DBx__7__PS CYREG_PRT2_PS\r
-#define SCSI_Out_DBx__7__SHIFT 2u\r
-#define SCSI_Out_DBx__7__SLW CYREG_PRT2_SLW\r
-#define SCSI_Out_DBx__DB0__AG CYREG_PRT5_AG\r
-#define SCSI_Out_DBx__DB0__AMUX CYREG_PRT5_AMUX\r
-#define SCSI_Out_DBx__DB0__BIE CYREG_PRT5_BIE\r
-#define SCSI_Out_DBx__DB0__BIT_MASK CYREG_PRT5_BIT_MASK\r
-#define SCSI_Out_DBx__DB0__BYP CYREG_PRT5_BYP\r
-#define SCSI_Out_DBx__DB0__CTL CYREG_PRT5_CTL\r
-#define SCSI_Out_DBx__DB0__DM0 CYREG_PRT5_DM0\r
-#define SCSI_Out_DBx__DB0__DM1 CYREG_PRT5_DM1\r
-#define SCSI_Out_DBx__DB0__DM2 CYREG_PRT5_DM2\r
-#define SCSI_Out_DBx__DB0__DR CYREG_PRT5_DR\r
-#define SCSI_Out_DBx__DB0__INP_DIS CYREG_PRT5_INP_DIS\r
-#define SCSI_Out_DBx__DB0__INTTYPE CYREG_PICU5_INTTYPE1\r
-#define SCSI_Out_DBx__DB0__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG\r
-#define SCSI_Out_DBx__DB0__LCD_EN CYREG_PRT5_LCD_EN\r
-#define SCSI_Out_DBx__DB0__MASK 0x02u\r
-#define SCSI_Out_DBx__DB0__PC CYREG_PRT5_PC1\r
-#define SCSI_Out_DBx__DB0__PORT 5u\r
-#define SCSI_Out_DBx__DB0__PRT CYREG_PRT5_PRT\r
-#define SCSI_Out_DBx__DB0__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL\r
-#define SCSI_Out_DBx__DB0__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN\r
-#define SCSI_Out_DBx__DB0__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0\r
-#define SCSI_Out_DBx__DB0__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1\r
-#define SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0\r
-#define SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1\r
-#define SCSI_Out_DBx__DB0__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT\r
-#define SCSI_Out_DBx__DB0__PS CYREG_PRT5_PS\r
-#define SCSI_Out_DBx__DB0__SHIFT 1u\r
-#define SCSI_Out_DBx__DB0__SLW CYREG_PRT5_SLW\r
-#define SCSI_Out_DBx__DB1__AG CYREG_PRT5_AG\r
-#define SCSI_Out_DBx__DB1__AMUX CYREG_PRT5_AMUX\r
-#define SCSI_Out_DBx__DB1__BIE CYREG_PRT5_BIE\r
-#define SCSI_Out_DBx__DB1__BIT_MASK CYREG_PRT5_BIT_MASK\r
-#define SCSI_Out_DBx__DB1__BYP CYREG_PRT5_BYP\r
-#define SCSI_Out_DBx__DB1__CTL CYREG_PRT5_CTL\r
-#define SCSI_Out_DBx__DB1__DM0 CYREG_PRT5_DM0\r
-#define SCSI_Out_DBx__DB1__DM1 CYREG_PRT5_DM1\r
-#define SCSI_Out_DBx__DB1__DM2 CYREG_PRT5_DM2\r
-#define SCSI_Out_DBx__DB1__DR CYREG_PRT5_DR\r
-#define SCSI_Out_DBx__DB1__INP_DIS CYREG_PRT5_INP_DIS\r
-#define SCSI_Out_DBx__DB1__INTTYPE CYREG_PICU5_INTTYPE0\r
-#define SCSI_Out_DBx__DB1__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG\r
-#define SCSI_Out_DBx__DB1__LCD_EN CYREG_PRT5_LCD_EN\r
-#define SCSI_Out_DBx__DB1__MASK 0x01u\r
-#define SCSI_Out_DBx__DB1__PC CYREG_PRT5_PC0\r
-#define SCSI_Out_DBx__DB1__PORT 5u\r
-#define SCSI_Out_DBx__DB1__PRT CYREG_PRT5_PRT\r
-#define SCSI_Out_DBx__DB1__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL\r
-#define SCSI_Out_DBx__DB1__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN\r
-#define SCSI_Out_DBx__DB1__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0\r
-#define SCSI_Out_DBx__DB1__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1\r
-#define SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0\r
-#define SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1\r
-#define SCSI_Out_DBx__DB1__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT\r
-#define SCSI_Out_DBx__DB1__PS CYREG_PRT5_PS\r
-#define SCSI_Out_DBx__DB1__SHIFT 0u\r
-#define SCSI_Out_DBx__DB1__SLW CYREG_PRT5_SLW\r
-#define SCSI_Out_DBx__DB2__AG CYREG_PRT6_AG\r
-#define SCSI_Out_DBx__DB2__AMUX CYREG_PRT6_AMUX\r
-#define SCSI_Out_DBx__DB2__BIE CYREG_PRT6_BIE\r
-#define SCSI_Out_DBx__DB2__BIT_MASK CYREG_PRT6_BIT_MASK\r
-#define SCSI_Out_DBx__DB2__BYP CYREG_PRT6_BYP\r
-#define SCSI_Out_DBx__DB2__CTL CYREG_PRT6_CTL\r
-#define SCSI_Out_DBx__DB2__DM0 CYREG_PRT6_DM0\r
-#define SCSI_Out_DBx__DB2__DM1 CYREG_PRT6_DM1\r
-#define SCSI_Out_DBx__DB2__DM2 CYREG_PRT6_DM2\r
-#define SCSI_Out_DBx__DB2__DR CYREG_PRT6_DR\r
-#define SCSI_Out_DBx__DB2__INP_DIS CYREG_PRT6_INP_DIS\r
-#define SCSI_Out_DBx__DB2__INTTYPE CYREG_PICU6_INTTYPE5\r
-#define SCSI_Out_DBx__DB2__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
-#define SCSI_Out_DBx__DB2__LCD_EN CYREG_PRT6_LCD_EN\r
-#define SCSI_Out_DBx__DB2__MASK 0x20u\r
-#define SCSI_Out_DBx__DB2__PC CYREG_PRT6_PC5\r
-#define SCSI_Out_DBx__DB2__PORT 6u\r
-#define SCSI_Out_DBx__DB2__PRT CYREG_PRT6_PRT\r
-#define SCSI_Out_DBx__DB2__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
-#define SCSI_Out_DBx__DB2__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
-#define SCSI_Out_DBx__DB2__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
-#define SCSI_Out_DBx__DB2__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
-#define SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
-#define SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
-#define SCSI_Out_DBx__DB2__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
-#define SCSI_Out_DBx__DB2__PS CYREG_PRT6_PS\r
-#define SCSI_Out_DBx__DB2__SHIFT 5u\r
-#define SCSI_Out_DBx__DB2__SLW CYREG_PRT6_SLW\r
-#define SCSI_Out_DBx__DB3__AG CYREG_PRT6_AG\r
-#define SCSI_Out_DBx__DB3__AMUX CYREG_PRT6_AMUX\r
-#define SCSI_Out_DBx__DB3__BIE CYREG_PRT6_BIE\r
-#define SCSI_Out_DBx__DB3__BIT_MASK CYREG_PRT6_BIT_MASK\r
-#define SCSI_Out_DBx__DB3__BYP CYREG_PRT6_BYP\r
-#define SCSI_Out_DBx__DB3__CTL CYREG_PRT6_CTL\r
-#define SCSI_Out_DBx__DB3__DM0 CYREG_PRT6_DM0\r
-#define SCSI_Out_DBx__DB3__DM1 CYREG_PRT6_DM1\r
-#define SCSI_Out_DBx__DB3__DM2 CYREG_PRT6_DM2\r
-#define SCSI_Out_DBx__DB3__DR CYREG_PRT6_DR\r
-#define SCSI_Out_DBx__DB3__INP_DIS CYREG_PRT6_INP_DIS\r
-#define SCSI_Out_DBx__DB3__INTTYPE CYREG_PICU6_INTTYPE4\r
-#define SCSI_Out_DBx__DB3__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
-#define SCSI_Out_DBx__DB3__LCD_EN CYREG_PRT6_LCD_EN\r
-#define SCSI_Out_DBx__DB3__MASK 0x10u\r
-#define SCSI_Out_DBx__DB3__PC CYREG_PRT6_PC4\r
-#define SCSI_Out_DBx__DB3__PORT 6u\r
-#define SCSI_Out_DBx__DB3__PRT CYREG_PRT6_PRT\r
-#define SCSI_Out_DBx__DB3__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
-#define SCSI_Out_DBx__DB3__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
-#define SCSI_Out_DBx__DB3__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
-#define SCSI_Out_DBx__DB3__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
-#define SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
-#define SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
-#define SCSI_Out_DBx__DB3__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
-#define SCSI_Out_DBx__DB3__PS CYREG_PRT6_PS\r
-#define SCSI_Out_DBx__DB3__SHIFT 4u\r
-#define SCSI_Out_DBx__DB3__SLW CYREG_PRT6_SLW\r
-#define SCSI_Out_DBx__DB4__AG CYREG_PRT2_AG\r
-#define SCSI_Out_DBx__DB4__AMUX CYREG_PRT2_AMUX\r
-#define SCSI_Out_DBx__DB4__BIE CYREG_PRT2_BIE\r
-#define SCSI_Out_DBx__DB4__BIT_MASK CYREG_PRT2_BIT_MASK\r
-#define SCSI_Out_DBx__DB4__BYP CYREG_PRT2_BYP\r
-#define SCSI_Out_DBx__DB4__CTL CYREG_PRT2_CTL\r
-#define SCSI_Out_DBx__DB4__DM0 CYREG_PRT2_DM0\r
-#define SCSI_Out_DBx__DB4__DM1 CYREG_PRT2_DM1\r
-#define SCSI_Out_DBx__DB4__DM2 CYREG_PRT2_DM2\r
-#define SCSI_Out_DBx__DB4__DR CYREG_PRT2_DR\r
-#define SCSI_Out_DBx__DB4__INP_DIS CYREG_PRT2_INP_DIS\r
-#define SCSI_Out_DBx__DB4__INTTYPE CYREG_PICU2_INTTYPE7\r
-#define SCSI_Out_DBx__DB4__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG\r
-#define SCSI_Out_DBx__DB4__LCD_EN CYREG_PRT2_LCD_EN\r
-#define SCSI_Out_DBx__DB4__MASK 0x80u\r
-#define SCSI_Out_DBx__DB4__PC CYREG_PRT2_PC7\r
-#define SCSI_Out_DBx__DB4__PORT 2u\r
-#define SCSI_Out_DBx__DB4__PRT CYREG_PRT2_PRT\r
-#define SCSI_Out_DBx__DB4__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL\r
-#define SCSI_Out_DBx__DB4__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN\r
-#define SCSI_Out_DBx__DB4__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0\r
-#define SCSI_Out_DBx__DB4__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1\r
-#define SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0\r
-#define SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1\r
-#define SCSI_Out_DBx__DB4__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT\r
-#define SCSI_Out_DBx__DB4__PS CYREG_PRT2_PS\r
-#define SCSI_Out_DBx__DB4__SHIFT 7u\r
-#define SCSI_Out_DBx__DB4__SLW CYREG_PRT2_SLW\r
-#define SCSI_Out_DBx__DB5__AG CYREG_PRT2_AG\r
-#define SCSI_Out_DBx__DB5__AMUX CYREG_PRT2_AMUX\r
-#define SCSI_Out_DBx__DB5__BIE CYREG_PRT2_BIE\r
-#define SCSI_Out_DBx__DB5__BIT_MASK CYREG_PRT2_BIT_MASK\r
-#define SCSI_Out_DBx__DB5__BYP CYREG_PRT2_BYP\r
-#define SCSI_Out_DBx__DB5__CTL CYREG_PRT2_CTL\r
-#define SCSI_Out_DBx__DB5__DM0 CYREG_PRT2_DM0\r
-#define SCSI_Out_DBx__DB5__DM1 CYREG_PRT2_DM1\r
-#define SCSI_Out_DBx__DB5__DM2 CYREG_PRT2_DM2\r
-#define SCSI_Out_DBx__DB5__DR CYREG_PRT2_DR\r
-#define SCSI_Out_DBx__DB5__INP_DIS CYREG_PRT2_INP_DIS\r
-#define SCSI_Out_DBx__DB5__INTTYPE CYREG_PICU2_INTTYPE6\r
-#define SCSI_Out_DBx__DB5__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG\r
-#define SCSI_Out_DBx__DB5__LCD_EN CYREG_PRT2_LCD_EN\r
-#define SCSI_Out_DBx__DB5__MASK 0x40u\r
-#define SCSI_Out_DBx__DB5__PC CYREG_PRT2_PC6\r
-#define SCSI_Out_DBx__DB5__PORT 2u\r
-#define SCSI_Out_DBx__DB5__PRT CYREG_PRT2_PRT\r
-#define SCSI_Out_DBx__DB5__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL\r
-#define SCSI_Out_DBx__DB5__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN\r
-#define SCSI_Out_DBx__DB5__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0\r
-#define SCSI_Out_DBx__DB5__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1\r
-#define SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0\r
-#define SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1\r
-#define SCSI_Out_DBx__DB5__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT\r
-#define SCSI_Out_DBx__DB5__PS CYREG_PRT2_PS\r
-#define SCSI_Out_DBx__DB5__SHIFT 6u\r
-#define SCSI_Out_DBx__DB5__SLW CYREG_PRT2_SLW\r
-#define SCSI_Out_DBx__DB6__AG CYREG_PRT2_AG\r
-#define SCSI_Out_DBx__DB6__AMUX CYREG_PRT2_AMUX\r
-#define SCSI_Out_DBx__DB6__BIE CYREG_PRT2_BIE\r
-#define SCSI_Out_DBx__DB6__BIT_MASK CYREG_PRT2_BIT_MASK\r
-#define SCSI_Out_DBx__DB6__BYP CYREG_PRT2_BYP\r
-#define SCSI_Out_DBx__DB6__CTL CYREG_PRT2_CTL\r
-#define SCSI_Out_DBx__DB6__DM0 CYREG_PRT2_DM0\r
-#define SCSI_Out_DBx__DB6__DM1 CYREG_PRT2_DM1\r
-#define SCSI_Out_DBx__DB6__DM2 CYREG_PRT2_DM2\r
-#define SCSI_Out_DBx__DB6__DR CYREG_PRT2_DR\r
-#define SCSI_Out_DBx__DB6__INP_DIS CYREG_PRT2_INP_DIS\r
-#define SCSI_Out_DBx__DB6__INTTYPE CYREG_PICU2_INTTYPE3\r
-#define SCSI_Out_DBx__DB6__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG\r
-#define SCSI_Out_DBx__DB6__LCD_EN CYREG_PRT2_LCD_EN\r
-#define SCSI_Out_DBx__DB6__MASK 0x08u\r
-#define SCSI_Out_DBx__DB6__PC CYREG_PRT2_PC3\r
-#define SCSI_Out_DBx__DB6__PORT 2u\r
-#define SCSI_Out_DBx__DB6__PRT CYREG_PRT2_PRT\r
-#define SCSI_Out_DBx__DB6__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL\r
-#define SCSI_Out_DBx__DB6__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN\r
-#define SCSI_Out_DBx__DB6__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0\r
-#define SCSI_Out_DBx__DB6__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1\r
-#define SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0\r
-#define SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1\r
-#define SCSI_Out_DBx__DB6__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT\r
-#define SCSI_Out_DBx__DB6__PS CYREG_PRT2_PS\r
-#define SCSI_Out_DBx__DB6__SHIFT 3u\r
-#define SCSI_Out_DBx__DB6__SLW CYREG_PRT2_SLW\r
-#define SCSI_Out_DBx__DB7__AG CYREG_PRT2_AG\r
-#define SCSI_Out_DBx__DB7__AMUX CYREG_PRT2_AMUX\r
-#define SCSI_Out_DBx__DB7__BIE CYREG_PRT2_BIE\r
-#define SCSI_Out_DBx__DB7__BIT_MASK CYREG_PRT2_BIT_MASK\r
-#define SCSI_Out_DBx__DB7__BYP CYREG_PRT2_BYP\r
-#define SCSI_Out_DBx__DB7__CTL CYREG_PRT2_CTL\r
-#define SCSI_Out_DBx__DB7__DM0 CYREG_PRT2_DM0\r
-#define SCSI_Out_DBx__DB7__DM1 CYREG_PRT2_DM1\r
-#define SCSI_Out_DBx__DB7__DM2 CYREG_PRT2_DM2\r
-#define SCSI_Out_DBx__DB7__DR CYREG_PRT2_DR\r
-#define SCSI_Out_DBx__DB7__INP_DIS CYREG_PRT2_INP_DIS\r
-#define SCSI_Out_DBx__DB7__INTTYPE CYREG_PICU2_INTTYPE2\r
-#define SCSI_Out_DBx__DB7__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG\r
-#define SCSI_Out_DBx__DB7__LCD_EN CYREG_PRT2_LCD_EN\r
-#define SCSI_Out_DBx__DB7__MASK 0x04u\r
-#define SCSI_Out_DBx__DB7__PC CYREG_PRT2_PC2\r
-#define SCSI_Out_DBx__DB7__PORT 2u\r
-#define SCSI_Out_DBx__DB7__PRT CYREG_PRT2_PRT\r
-#define SCSI_Out_DBx__DB7__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL\r
-#define SCSI_Out_DBx__DB7__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN\r
-#define SCSI_Out_DBx__DB7__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0\r
-#define SCSI_Out_DBx__DB7__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1\r
-#define SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0\r
-#define SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1\r
-#define SCSI_Out_DBx__DB7__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT\r
-#define SCSI_Out_DBx__DB7__PS CYREG_PRT2_PS\r
-#define SCSI_Out_DBx__DB7__SHIFT 2u\r
-#define SCSI_Out_DBx__DB7__SLW CYREG_PRT2_SLW\r
-\r
-/* SD_RX_DMA */\r
-#define SD_RX_DMA__DRQ_CTL CYREG_IDMUX_DRQ_CTL0\r
-#define SD_RX_DMA__DRQ_NUMBER 2u\r
-#define SD_RX_DMA__NUMBEROF_TDS 0u\r
-#define SD_RX_DMA__PRIORITY 0u\r
-#define SD_RX_DMA__TERMIN_EN 0u\r
-#define SD_RX_DMA__TERMIN_SEL 0u\r
-#define SD_RX_DMA__TERMOUT0_EN 1u\r
-#define SD_RX_DMA__TERMOUT0_SEL 2u\r
-#define SD_RX_DMA__TERMOUT1_EN 0u\r
-#define SD_RX_DMA__TERMOUT1_SEL 0u\r
-\r
-/* SD_RX_DMA_COMPLETE */\r
-#define SD_RX_DMA_COMPLETE__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
-#define SD_RX_DMA_COMPLETE__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
-#define SD_RX_DMA_COMPLETE__INTC_MASK 0x20u\r
-#define SD_RX_DMA_COMPLETE__INTC_NUMBER 5u\r
-#define SD_RX_DMA_COMPLETE__INTC_PRIOR_NUM 7u\r
-#define SD_RX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_5\r
-#define SD_RX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
-#define SD_RX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
-\r
-/* SD_TX_DMA */\r
-#define SD_TX_DMA__DRQ_CTL CYREG_IDMUX_DRQ_CTL0\r
-#define SD_TX_DMA__DRQ_NUMBER 3u\r
-#define SD_TX_DMA__NUMBEROF_TDS 0u\r
-#define SD_TX_DMA__PRIORITY 1u\r
-#define SD_TX_DMA__TERMIN_EN 0u\r
-#define SD_TX_DMA__TERMIN_SEL 0u\r
-#define SD_TX_DMA__TERMOUT0_EN 1u\r
-#define SD_TX_DMA__TERMOUT0_SEL 3u\r
-#define SD_TX_DMA__TERMOUT1_EN 0u\r
-#define SD_TX_DMA__TERMOUT1_SEL 0u\r
-\r
-/* SD_TX_DMA_COMPLETE */\r
-#define SD_TX_DMA_COMPLETE__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
-#define SD_TX_DMA_COMPLETE__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
-#define SD_TX_DMA_COMPLETE__INTC_MASK 0x40u\r
-#define SD_TX_DMA_COMPLETE__INTC_NUMBER 6u\r
-#define SD_TX_DMA_COMPLETE__INTC_PRIOR_NUM 7u\r
-#define SD_TX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_6\r
-#define SD_TX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
-#define SD_TX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
+/* SCSI_In */\r
+#define SCSI_In__0__AG CYREG_PRT2_AG\r
+#define SCSI_In__0__AMUX CYREG_PRT2_AMUX\r
+#define SCSI_In__0__BIE CYREG_PRT2_BIE\r
+#define SCSI_In__0__BIT_MASK CYREG_PRT2_BIT_MASK\r
+#define SCSI_In__0__BYP CYREG_PRT2_BYP\r
+#define SCSI_In__0__CTL CYREG_PRT2_CTL\r
+#define SCSI_In__0__DM0 CYREG_PRT2_DM0\r
+#define SCSI_In__0__DM1 CYREG_PRT2_DM1\r
+#define SCSI_In__0__DM2 CYREG_PRT2_DM2\r
+#define SCSI_In__0__DR CYREG_PRT2_DR\r
+#define SCSI_In__0__INP_DIS CYREG_PRT2_INP_DIS\r
+#define SCSI_In__0__INTTYPE CYREG_PICU2_INTTYPE1\r
+#define SCSI_In__0__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG\r
+#define SCSI_In__0__LCD_EN CYREG_PRT2_LCD_EN\r
+#define SCSI_In__0__MASK 0x02u\r
+#define SCSI_In__0__PC CYREG_PRT2_PC1\r
+#define SCSI_In__0__PORT 2u\r
+#define SCSI_In__0__PRT CYREG_PRT2_PRT\r
+#define SCSI_In__0__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL\r
+#define SCSI_In__0__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN\r
+#define SCSI_In__0__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0\r
+#define SCSI_In__0__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1\r
+#define SCSI_In__0__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0\r
+#define SCSI_In__0__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1\r
+#define SCSI_In__0__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT\r
+#define SCSI_In__0__PS CYREG_PRT2_PS\r
+#define SCSI_In__0__SHIFT 1u\r
+#define SCSI_In__0__SLW CYREG_PRT2_SLW\r
+#define SCSI_In__1__AG CYREG_PRT4_AG\r
+#define SCSI_In__1__AMUX CYREG_PRT4_AMUX\r
+#define SCSI_In__1__BIE CYREG_PRT4_BIE\r
+#define SCSI_In__1__BIT_MASK CYREG_PRT4_BIT_MASK\r
+#define SCSI_In__1__BYP CYREG_PRT4_BYP\r
+#define SCSI_In__1__CTL CYREG_PRT4_CTL\r
+#define SCSI_In__1__DM0 CYREG_PRT4_DM0\r
+#define SCSI_In__1__DM1 CYREG_PRT4_DM1\r
+#define SCSI_In__1__DM2 CYREG_PRT4_DM2\r
+#define SCSI_In__1__DR CYREG_PRT4_DR\r
+#define SCSI_In__1__INP_DIS CYREG_PRT4_INP_DIS\r
+#define SCSI_In__1__INTTYPE CYREG_PICU4_INTTYPE6\r
+#define SCSI_In__1__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG\r
+#define SCSI_In__1__LCD_EN CYREG_PRT4_LCD_EN\r
+#define SCSI_In__1__MASK 0x40u\r
+#define SCSI_In__1__PC CYREG_PRT4_PC6\r
+#define SCSI_In__1__PORT 4u\r
+#define SCSI_In__1__PRT CYREG_PRT4_PRT\r
+#define SCSI_In__1__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL\r
+#define SCSI_In__1__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN\r
+#define SCSI_In__1__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0\r
+#define SCSI_In__1__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1\r
+#define SCSI_In__1__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0\r
+#define SCSI_In__1__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1\r
+#define SCSI_In__1__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT\r
+#define SCSI_In__1__PS CYREG_PRT4_PS\r
+#define SCSI_In__1__SHIFT 6u\r
+#define SCSI_In__1__SLW CYREG_PRT4_SLW\r
+#define SCSI_In__2__AG CYREG_PRT4_AG\r
+#define SCSI_In__2__AMUX CYREG_PRT4_AMUX\r
+#define SCSI_In__2__BIE CYREG_PRT4_BIE\r
+#define SCSI_In__2__BIT_MASK CYREG_PRT4_BIT_MASK\r
+#define SCSI_In__2__BYP CYREG_PRT4_BYP\r
+#define SCSI_In__2__CTL CYREG_PRT4_CTL\r
+#define SCSI_In__2__DM0 CYREG_PRT4_DM0\r
+#define SCSI_In__2__DM1 CYREG_PRT4_DM1\r
+#define SCSI_In__2__DM2 CYREG_PRT4_DM2\r
+#define SCSI_In__2__DR CYREG_PRT4_DR\r
+#define SCSI_In__2__INP_DIS CYREG_PRT4_INP_DIS\r
+#define SCSI_In__2__INTTYPE CYREG_PICU4_INTTYPE2\r
+#define SCSI_In__2__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG\r
+#define SCSI_In__2__LCD_EN CYREG_PRT4_LCD_EN\r
+#define SCSI_In__2__MASK 0x04u\r
+#define SCSI_In__2__PC CYREG_PRT4_PC2\r
+#define SCSI_In__2__PORT 4u\r
+#define SCSI_In__2__PRT CYREG_PRT4_PRT\r
+#define SCSI_In__2__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL\r
+#define SCSI_In__2__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN\r
+#define SCSI_In__2__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0\r
+#define SCSI_In__2__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1\r
+#define SCSI_In__2__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0\r
+#define SCSI_In__2__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1\r
+#define SCSI_In__2__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT\r
+#define SCSI_In__2__PS CYREG_PRT4_PS\r
+#define SCSI_In__2__SHIFT 2u\r
+#define SCSI_In__2__SLW CYREG_PRT4_SLW\r
+#define SCSI_In__3__AG CYREG_PRT0_AG\r
+#define SCSI_In__3__AMUX CYREG_PRT0_AMUX\r
+#define SCSI_In__3__BIE CYREG_PRT0_BIE\r
+#define SCSI_In__3__BIT_MASK CYREG_PRT0_BIT_MASK\r
+#define SCSI_In__3__BYP CYREG_PRT0_BYP\r
+#define SCSI_In__3__CTL CYREG_PRT0_CTL\r
+#define SCSI_In__3__DM0 CYREG_PRT0_DM0\r
+#define SCSI_In__3__DM1 CYREG_PRT0_DM1\r
+#define SCSI_In__3__DM2 CYREG_PRT0_DM2\r
+#define SCSI_In__3__DR CYREG_PRT0_DR\r
+#define SCSI_In__3__INP_DIS CYREG_PRT0_INP_DIS\r
+#define SCSI_In__3__INTTYPE CYREG_PICU0_INTTYPE5\r
+#define SCSI_In__3__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG\r
+#define SCSI_In__3__LCD_EN CYREG_PRT0_LCD_EN\r
+#define SCSI_In__3__MASK 0x20u\r
+#define SCSI_In__3__PC CYREG_PRT0_PC5\r
+#define SCSI_In__3__PORT 0u\r
+#define SCSI_In__3__PRT CYREG_PRT0_PRT\r
+#define SCSI_In__3__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL\r
+#define SCSI_In__3__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN\r
+#define SCSI_In__3__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0\r
+#define SCSI_In__3__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1\r
+#define SCSI_In__3__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0\r
+#define SCSI_In__3__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1\r
+#define SCSI_In__3__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT\r
+#define SCSI_In__3__PS CYREG_PRT0_PS\r
+#define SCSI_In__3__SHIFT 5u\r
+#define SCSI_In__3__SLW CYREG_PRT0_SLW\r
+#define SCSI_In__4__AG CYREG_PRT0_AG\r
+#define SCSI_In__4__AMUX CYREG_PRT0_AMUX\r
+#define SCSI_In__4__BIE CYREG_PRT0_BIE\r
+#define SCSI_In__4__BIT_MASK CYREG_PRT0_BIT_MASK\r
+#define SCSI_In__4__BYP CYREG_PRT0_BYP\r
+#define SCSI_In__4__CTL CYREG_PRT0_CTL\r
+#define SCSI_In__4__DM0 CYREG_PRT0_DM0\r
+#define SCSI_In__4__DM1 CYREG_PRT0_DM1\r
+#define SCSI_In__4__DM2 CYREG_PRT0_DM2\r
+#define SCSI_In__4__DR CYREG_PRT0_DR\r
+#define SCSI_In__4__INP_DIS CYREG_PRT0_INP_DIS\r
+#define SCSI_In__4__INTTYPE CYREG_PICU0_INTTYPE4\r
+#define SCSI_In__4__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG\r
+#define SCSI_In__4__LCD_EN CYREG_PRT0_LCD_EN\r
+#define SCSI_In__4__MASK 0x10u\r
+#define SCSI_In__4__PC CYREG_PRT0_PC4\r
+#define SCSI_In__4__PORT 0u\r
+#define SCSI_In__4__PRT CYREG_PRT0_PRT\r
+#define SCSI_In__4__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL\r
+#define SCSI_In__4__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN\r
+#define SCSI_In__4__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0\r
+#define SCSI_In__4__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1\r
+#define SCSI_In__4__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0\r
+#define SCSI_In__4__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1\r
+#define SCSI_In__4__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT\r
+#define SCSI_In__4__PS CYREG_PRT0_PS\r
+#define SCSI_In__4__SHIFT 4u\r
+#define SCSI_In__4__SLW CYREG_PRT0_SLW\r
+#define SCSI_In__CD__AG CYREG_PRT4_AG\r
+#define SCSI_In__CD__AMUX CYREG_PRT4_AMUX\r
+#define SCSI_In__CD__BIE CYREG_PRT4_BIE\r
+#define SCSI_In__CD__BIT_MASK CYREG_PRT4_BIT_MASK\r
+#define SCSI_In__CD__BYP CYREG_PRT4_BYP\r
+#define SCSI_In__CD__CTL CYREG_PRT4_CTL\r
+#define SCSI_In__CD__DM0 CYREG_PRT4_DM0\r
+#define SCSI_In__CD__DM1 CYREG_PRT4_DM1\r
+#define SCSI_In__CD__DM2 CYREG_PRT4_DM2\r
+#define SCSI_In__CD__DR CYREG_PRT4_DR\r
+#define SCSI_In__CD__INP_DIS CYREG_PRT4_INP_DIS\r
+#define SCSI_In__CD__INTTYPE CYREG_PICU4_INTTYPE2\r
+#define SCSI_In__CD__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG\r
+#define SCSI_In__CD__LCD_EN CYREG_PRT4_LCD_EN\r
+#define SCSI_In__CD__MASK 0x04u\r
+#define SCSI_In__CD__PC CYREG_PRT4_PC2\r
+#define SCSI_In__CD__PORT 4u\r
+#define SCSI_In__CD__PRT CYREG_PRT4_PRT\r
+#define SCSI_In__CD__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL\r
+#define SCSI_In__CD__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN\r
+#define SCSI_In__CD__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0\r
+#define SCSI_In__CD__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1\r
+#define SCSI_In__CD__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0\r
+#define SCSI_In__CD__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1\r
+#define SCSI_In__CD__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT\r
+#define SCSI_In__CD__PS CYREG_PRT4_PS\r
+#define SCSI_In__CD__SHIFT 2u\r
+#define SCSI_In__CD__SLW CYREG_PRT4_SLW\r
+#define SCSI_In__DBP__AG CYREG_PRT2_AG\r
+#define SCSI_In__DBP__AMUX CYREG_PRT2_AMUX\r
+#define SCSI_In__DBP__BIE CYREG_PRT2_BIE\r
+#define SCSI_In__DBP__BIT_MASK CYREG_PRT2_BIT_MASK\r
+#define SCSI_In__DBP__BYP CYREG_PRT2_BYP\r
+#define SCSI_In__DBP__CTL CYREG_PRT2_CTL\r
+#define SCSI_In__DBP__DM0 CYREG_PRT2_DM0\r
+#define SCSI_In__DBP__DM1 CYREG_PRT2_DM1\r
+#define SCSI_In__DBP__DM2 CYREG_PRT2_DM2\r
+#define SCSI_In__DBP__DR CYREG_PRT2_DR\r
+#define SCSI_In__DBP__INP_DIS CYREG_PRT2_INP_DIS\r
+#define SCSI_In__DBP__INTTYPE CYREG_PICU2_INTTYPE1\r
+#define SCSI_In__DBP__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG\r
+#define SCSI_In__DBP__LCD_EN CYREG_PRT2_LCD_EN\r
+#define SCSI_In__DBP__MASK 0x02u\r
+#define SCSI_In__DBP__PC CYREG_PRT2_PC1\r
+#define SCSI_In__DBP__PORT 2u\r
+#define SCSI_In__DBP__PRT CYREG_PRT2_PRT\r
+#define SCSI_In__DBP__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL\r
+#define SCSI_In__DBP__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN\r
+#define SCSI_In__DBP__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0\r
+#define SCSI_In__DBP__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1\r
+#define SCSI_In__DBP__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0\r
+#define SCSI_In__DBP__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1\r
+#define SCSI_In__DBP__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT\r
+#define SCSI_In__DBP__PS CYREG_PRT2_PS\r
+#define SCSI_In__DBP__SHIFT 1u\r
+#define SCSI_In__DBP__SLW CYREG_PRT2_SLW\r
+#define SCSI_In__IO__AG CYREG_PRT0_AG\r
+#define SCSI_In__IO__AMUX CYREG_PRT0_AMUX\r
+#define SCSI_In__IO__BIE CYREG_PRT0_BIE\r
+#define SCSI_In__IO__BIT_MASK CYREG_PRT0_BIT_MASK\r
+#define SCSI_In__IO__BYP CYREG_PRT0_BYP\r
+#define SCSI_In__IO__CTL CYREG_PRT0_CTL\r
+#define SCSI_In__IO__DM0 CYREG_PRT0_DM0\r
+#define SCSI_In__IO__DM1 CYREG_PRT0_DM1\r
+#define SCSI_In__IO__DM2 CYREG_PRT0_DM2\r
+#define SCSI_In__IO__DR CYREG_PRT0_DR\r
+#define SCSI_In__IO__INP_DIS CYREG_PRT0_INP_DIS\r
+#define SCSI_In__IO__INTTYPE CYREG_PICU0_INTTYPE4\r
+#define SCSI_In__IO__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG\r
+#define SCSI_In__IO__LCD_EN CYREG_PRT0_LCD_EN\r
+#define SCSI_In__IO__MASK 0x10u\r
+#define SCSI_In__IO__PC CYREG_PRT0_PC4\r
+#define SCSI_In__IO__PORT 0u\r
+#define SCSI_In__IO__PRT CYREG_PRT0_PRT\r
+#define SCSI_In__IO__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL\r
+#define SCSI_In__IO__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN\r
+#define SCSI_In__IO__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0\r
+#define SCSI_In__IO__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1\r
+#define SCSI_In__IO__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0\r
+#define SCSI_In__IO__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1\r
+#define SCSI_In__IO__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT\r
+#define SCSI_In__IO__PS CYREG_PRT0_PS\r
+#define SCSI_In__IO__SHIFT 4u\r
+#define SCSI_In__IO__SLW CYREG_PRT0_SLW\r
+#define SCSI_In__MSG__AG CYREG_PRT4_AG\r
+#define SCSI_In__MSG__AMUX CYREG_PRT4_AMUX\r
+#define SCSI_In__MSG__BIE CYREG_PRT4_BIE\r
+#define SCSI_In__MSG__BIT_MASK CYREG_PRT4_BIT_MASK\r
+#define SCSI_In__MSG__BYP CYREG_PRT4_BYP\r
+#define SCSI_In__MSG__CTL CYREG_PRT4_CTL\r
+#define SCSI_In__MSG__DM0 CYREG_PRT4_DM0\r
+#define SCSI_In__MSG__DM1 CYREG_PRT4_DM1\r
+#define SCSI_In__MSG__DM2 CYREG_PRT4_DM2\r
+#define SCSI_In__MSG__DR CYREG_PRT4_DR\r
+#define SCSI_In__MSG__INP_DIS CYREG_PRT4_INP_DIS\r
+#define SCSI_In__MSG__INTTYPE CYREG_PICU4_INTTYPE6\r
+#define SCSI_In__MSG__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG\r
+#define SCSI_In__MSG__LCD_EN CYREG_PRT4_LCD_EN\r
+#define SCSI_In__MSG__MASK 0x40u\r
+#define SCSI_In__MSG__PC CYREG_PRT4_PC6\r
+#define SCSI_In__MSG__PORT 4u\r
+#define SCSI_In__MSG__PRT CYREG_PRT4_PRT\r
+#define SCSI_In__MSG__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL\r
+#define SCSI_In__MSG__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN\r
+#define SCSI_In__MSG__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0\r
+#define SCSI_In__MSG__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1\r
+#define SCSI_In__MSG__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0\r
+#define SCSI_In__MSG__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1\r
+#define SCSI_In__MSG__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT\r
+#define SCSI_In__MSG__PS CYREG_PRT4_PS\r
+#define SCSI_In__MSG__SHIFT 6u\r
+#define SCSI_In__MSG__SLW CYREG_PRT4_SLW\r
+#define SCSI_In__REQ__AG CYREG_PRT0_AG\r
+#define SCSI_In__REQ__AMUX CYREG_PRT0_AMUX\r
+#define SCSI_In__REQ__BIE CYREG_PRT0_BIE\r
+#define SCSI_In__REQ__BIT_MASK CYREG_PRT0_BIT_MASK\r
+#define SCSI_In__REQ__BYP CYREG_PRT0_BYP\r
+#define SCSI_In__REQ__CTL CYREG_PRT0_CTL\r
+#define SCSI_In__REQ__DM0 CYREG_PRT0_DM0\r
+#define SCSI_In__REQ__DM1 CYREG_PRT0_DM1\r
+#define SCSI_In__REQ__DM2 CYREG_PRT0_DM2\r
+#define SCSI_In__REQ__DR CYREG_PRT0_DR\r
+#define SCSI_In__REQ__INP_DIS CYREG_PRT0_INP_DIS\r
+#define SCSI_In__REQ__INTTYPE CYREG_PICU0_INTTYPE5\r
+#define SCSI_In__REQ__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG\r
+#define SCSI_In__REQ__LCD_EN CYREG_PRT0_LCD_EN\r
+#define SCSI_In__REQ__MASK 0x20u\r
+#define SCSI_In__REQ__PC CYREG_PRT0_PC5\r
+#define SCSI_In__REQ__PORT 0u\r
+#define SCSI_In__REQ__PRT CYREG_PRT0_PRT\r
+#define SCSI_In__REQ__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL\r
+#define SCSI_In__REQ__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN\r
+#define SCSI_In__REQ__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0\r
+#define SCSI_In__REQ__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1\r
+#define SCSI_In__REQ__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0\r
+#define SCSI_In__REQ__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1\r
+#define SCSI_In__REQ__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT\r
+#define SCSI_In__REQ__PS CYREG_PRT0_PS\r
+#define SCSI_In__REQ__SHIFT 5u\r
+#define SCSI_In__REQ__SLW CYREG_PRT0_SLW\r
+#define SCSI_In_DBx__0__AG CYREG_PRT5_AG\r
+#define SCSI_In_DBx__0__AMUX CYREG_PRT5_AMUX\r
+#define SCSI_In_DBx__0__BIE CYREG_PRT5_BIE\r
+#define SCSI_In_DBx__0__BIT_MASK CYREG_PRT5_BIT_MASK\r
+#define SCSI_In_DBx__0__BYP CYREG_PRT5_BYP\r
+#define SCSI_In_DBx__0__CTL CYREG_PRT5_CTL\r
+#define SCSI_In_DBx__0__DM0 CYREG_PRT5_DM0\r
+#define SCSI_In_DBx__0__DM1 CYREG_PRT5_DM1\r
+#define SCSI_In_DBx__0__DM2 CYREG_PRT5_DM2\r
+#define SCSI_In_DBx__0__DR CYREG_PRT5_DR\r
+#define SCSI_In_DBx__0__INP_DIS CYREG_PRT5_INP_DIS\r
+#define SCSI_In_DBx__0__INTTYPE CYREG_PICU5_INTTYPE3\r
+#define SCSI_In_DBx__0__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG\r
+#define SCSI_In_DBx__0__LCD_EN CYREG_PRT5_LCD_EN\r
+#define SCSI_In_DBx__0__MASK 0x08u\r
+#define SCSI_In_DBx__0__PC CYREG_PRT5_PC3\r
+#define SCSI_In_DBx__0__PORT 5u\r
+#define SCSI_In_DBx__0__PRT CYREG_PRT5_PRT\r
+#define SCSI_In_DBx__0__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL\r
+#define SCSI_In_DBx__0__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN\r
+#define SCSI_In_DBx__0__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0\r
+#define SCSI_In_DBx__0__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1\r
+#define SCSI_In_DBx__0__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0\r
+#define SCSI_In_DBx__0__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1\r
+#define SCSI_In_DBx__0__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT\r
+#define SCSI_In_DBx__0__PS CYREG_PRT5_PS\r
+#define SCSI_In_DBx__0__SHIFT 3u\r
+#define SCSI_In_DBx__0__SLW CYREG_PRT5_SLW\r
+#define SCSI_In_DBx__1__AG CYREG_PRT5_AG\r
+#define SCSI_In_DBx__1__AMUX CYREG_PRT5_AMUX\r
+#define SCSI_In_DBx__1__BIE CYREG_PRT5_BIE\r
+#define SCSI_In_DBx__1__BIT_MASK CYREG_PRT5_BIT_MASK\r
+#define SCSI_In_DBx__1__BYP CYREG_PRT5_BYP\r
+#define SCSI_In_DBx__1__CTL CYREG_PRT5_CTL\r
+#define SCSI_In_DBx__1__DM0 CYREG_PRT5_DM0\r
+#define SCSI_In_DBx__1__DM1 CYREG_PRT5_DM1\r
+#define SCSI_In_DBx__1__DM2 CYREG_PRT5_DM2\r
+#define SCSI_In_DBx__1__DR CYREG_PRT5_DR\r
+#define SCSI_In_DBx__1__INP_DIS CYREG_PRT5_INP_DIS\r
+#define SCSI_In_DBx__1__INTTYPE CYREG_PICU5_INTTYPE2\r
+#define SCSI_In_DBx__1__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG\r
+#define SCSI_In_DBx__1__LCD_EN CYREG_PRT5_LCD_EN\r
+#define SCSI_In_DBx__1__MASK 0x04u\r
+#define SCSI_In_DBx__1__PC CYREG_PRT5_PC2\r
+#define SCSI_In_DBx__1__PORT 5u\r
+#define SCSI_In_DBx__1__PRT CYREG_PRT5_PRT\r
+#define SCSI_In_DBx__1__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL\r
+#define SCSI_In_DBx__1__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN\r
+#define SCSI_In_DBx__1__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0\r
+#define SCSI_In_DBx__1__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1\r
+#define SCSI_In_DBx__1__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0\r
+#define SCSI_In_DBx__1__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1\r
+#define SCSI_In_DBx__1__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT\r
+#define SCSI_In_DBx__1__PS CYREG_PRT5_PS\r
+#define SCSI_In_DBx__1__SHIFT 2u\r
+#define SCSI_In_DBx__1__SLW CYREG_PRT5_SLW\r
+#define SCSI_In_DBx__2__AG CYREG_PRT6_AG\r
+#define SCSI_In_DBx__2__AMUX CYREG_PRT6_AMUX\r
+#define SCSI_In_DBx__2__BIE CYREG_PRT6_BIE\r
+#define SCSI_In_DBx__2__BIT_MASK CYREG_PRT6_BIT_MASK\r
+#define SCSI_In_DBx__2__BYP CYREG_PRT6_BYP\r
+#define SCSI_In_DBx__2__CTL CYREG_PRT6_CTL\r
+#define SCSI_In_DBx__2__DM0 CYREG_PRT6_DM0\r
+#define SCSI_In_DBx__2__DM1 CYREG_PRT6_DM1\r
+#define SCSI_In_DBx__2__DM2 CYREG_PRT6_DM2\r
+#define SCSI_In_DBx__2__DR CYREG_PRT6_DR\r
+#define SCSI_In_DBx__2__INP_DIS CYREG_PRT6_INP_DIS\r
+#define SCSI_In_DBx__2__INTTYPE CYREG_PICU6_INTTYPE7\r
+#define SCSI_In_DBx__2__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
+#define SCSI_In_DBx__2__LCD_EN CYREG_PRT6_LCD_EN\r
+#define SCSI_In_DBx__2__MASK 0x80u\r
+#define SCSI_In_DBx__2__PC CYREG_PRT6_PC7\r
+#define SCSI_In_DBx__2__PORT 6u\r
+#define SCSI_In_DBx__2__PRT CYREG_PRT6_PRT\r
+#define SCSI_In_DBx__2__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
+#define SCSI_In_DBx__2__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
+#define SCSI_In_DBx__2__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
+#define SCSI_In_DBx__2__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
+#define SCSI_In_DBx__2__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
+#define SCSI_In_DBx__2__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
+#define SCSI_In_DBx__2__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
+#define SCSI_In_DBx__2__PS CYREG_PRT6_PS\r
+#define SCSI_In_DBx__2__SHIFT 7u\r
+#define SCSI_In_DBx__2__SLW CYREG_PRT6_SLW\r
+#define SCSI_In_DBx__3__AG CYREG_PRT6_AG\r
+#define SCSI_In_DBx__3__AMUX CYREG_PRT6_AMUX\r
+#define SCSI_In_DBx__3__BIE CYREG_PRT6_BIE\r
+#define SCSI_In_DBx__3__BIT_MASK CYREG_PRT6_BIT_MASK\r
+#define SCSI_In_DBx__3__BYP CYREG_PRT6_BYP\r
+#define SCSI_In_DBx__3__CTL CYREG_PRT6_CTL\r
+#define SCSI_In_DBx__3__DM0 CYREG_PRT6_DM0\r
+#define SCSI_In_DBx__3__DM1 CYREG_PRT6_DM1\r
+#define SCSI_In_DBx__3__DM2 CYREG_PRT6_DM2\r
+#define SCSI_In_DBx__3__DR CYREG_PRT6_DR\r
+#define SCSI_In_DBx__3__INP_DIS CYREG_PRT6_INP_DIS\r
+#define SCSI_In_DBx__3__INTTYPE CYREG_PICU6_INTTYPE6\r
+#define SCSI_In_DBx__3__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
+#define SCSI_In_DBx__3__LCD_EN CYREG_PRT6_LCD_EN\r
+#define SCSI_In_DBx__3__MASK 0x40u\r
+#define SCSI_In_DBx__3__PC CYREG_PRT6_PC6\r
+#define SCSI_In_DBx__3__PORT 6u\r
+#define SCSI_In_DBx__3__PRT CYREG_PRT6_PRT\r
+#define SCSI_In_DBx__3__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
+#define SCSI_In_DBx__3__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
+#define SCSI_In_DBx__3__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
+#define SCSI_In_DBx__3__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
+#define SCSI_In_DBx__3__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
+#define SCSI_In_DBx__3__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
+#define SCSI_In_DBx__3__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
+#define SCSI_In_DBx__3__PS CYREG_PRT6_PS\r
+#define SCSI_In_DBx__3__SHIFT 6u\r
+#define SCSI_In_DBx__3__SLW CYREG_PRT6_SLW\r
+#define SCSI_In_DBx__4__AG CYREG_PRT12_AG\r
+#define SCSI_In_DBx__4__BIE CYREG_PRT12_BIE\r
+#define SCSI_In_DBx__4__BIT_MASK CYREG_PRT12_BIT_MASK\r
+#define SCSI_In_DBx__4__BYP CYREG_PRT12_BYP\r
+#define SCSI_In_DBx__4__DM0 CYREG_PRT12_DM0\r
+#define SCSI_In_DBx__4__DM1 CYREG_PRT12_DM1\r
+#define SCSI_In_DBx__4__DM2 CYREG_PRT12_DM2\r
+#define SCSI_In_DBx__4__DR CYREG_PRT12_DR\r
+#define SCSI_In_DBx__4__INP_DIS CYREG_PRT12_INP_DIS\r
+#define SCSI_In_DBx__4__INTTYPE CYREG_PICU12_INTTYPE5\r
+#define SCSI_In_DBx__4__MASK 0x20u\r
+#define SCSI_In_DBx__4__PC CYREG_PRT12_PC5\r
+#define SCSI_In_DBx__4__PORT 12u\r
+#define SCSI_In_DBx__4__PRT CYREG_PRT12_PRT\r
+#define SCSI_In_DBx__4__PRTDSI__DBL_SYNC_IN CYREG_PRT12_DBL_SYNC_IN\r
+#define SCSI_In_DBx__4__PRTDSI__OE_SEL0 CYREG_PRT12_OE_SEL0\r
+#define SCSI_In_DBx__4__PRTDSI__OE_SEL1 CYREG_PRT12_OE_SEL1\r
+#define SCSI_In_DBx__4__PRTDSI__OUT_SEL0 CYREG_PRT12_OUT_SEL0\r
+#define SCSI_In_DBx__4__PRTDSI__OUT_SEL1 CYREG_PRT12_OUT_SEL1\r
+#define SCSI_In_DBx__4__PRTDSI__SYNC_OUT CYREG_PRT12_SYNC_OUT\r
+#define SCSI_In_DBx__4__PS CYREG_PRT12_PS\r
+#define SCSI_In_DBx__4__SHIFT 5u\r
+#define SCSI_In_DBx__4__SIO_CFG CYREG_PRT12_SIO_CFG\r
+#define SCSI_In_DBx__4__SIO_DIFF CYREG_PRT12_SIO_DIFF\r
+#define SCSI_In_DBx__4__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN\r
+#define SCSI_In_DBx__4__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ\r
+#define SCSI_In_DBx__4__SLW CYREG_PRT12_SLW\r
+#define SCSI_In_DBx__5__AG CYREG_PRT12_AG\r
+#define SCSI_In_DBx__5__BIE CYREG_PRT12_BIE\r
+#define SCSI_In_DBx__5__BIT_MASK CYREG_PRT12_BIT_MASK\r
+#define SCSI_In_DBx__5__BYP CYREG_PRT12_BYP\r
+#define SCSI_In_DBx__5__DM0 CYREG_PRT12_DM0\r
+#define SCSI_In_DBx__5__DM1 CYREG_PRT12_DM1\r
+#define SCSI_In_DBx__5__DM2 CYREG_PRT12_DM2\r
+#define SCSI_In_DBx__5__DR CYREG_PRT12_DR\r
+#define SCSI_In_DBx__5__INP_DIS CYREG_PRT12_INP_DIS\r
+#define SCSI_In_DBx__5__INTTYPE CYREG_PICU12_INTTYPE4\r
+#define SCSI_In_DBx__5__MASK 0x10u\r
+#define SCSI_In_DBx__5__PC CYREG_PRT12_PC4\r
+#define SCSI_In_DBx__5__PORT 12u\r
+#define SCSI_In_DBx__5__PRT CYREG_PRT12_PRT\r
+#define SCSI_In_DBx__5__PRTDSI__DBL_SYNC_IN CYREG_PRT12_DBL_SYNC_IN\r
+#define SCSI_In_DBx__5__PRTDSI__OE_SEL0 CYREG_PRT12_OE_SEL0\r
+#define SCSI_In_DBx__5__PRTDSI__OE_SEL1 CYREG_PRT12_OE_SEL1\r
+#define SCSI_In_DBx__5__PRTDSI__OUT_SEL0 CYREG_PRT12_OUT_SEL0\r
+#define SCSI_In_DBx__5__PRTDSI__OUT_SEL1 CYREG_PRT12_OUT_SEL1\r
+#define SCSI_In_DBx__5__PRTDSI__SYNC_OUT CYREG_PRT12_SYNC_OUT\r
+#define SCSI_In_DBx__5__PS CYREG_PRT12_PS\r
+#define SCSI_In_DBx__5__SHIFT 4u\r
+#define SCSI_In_DBx__5__SIO_CFG CYREG_PRT12_SIO_CFG\r
+#define SCSI_In_DBx__5__SIO_DIFF CYREG_PRT12_SIO_DIFF\r
+#define SCSI_In_DBx__5__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN\r
+#define SCSI_In_DBx__5__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ\r
+#define SCSI_In_DBx__5__SLW CYREG_PRT12_SLW\r
+#define SCSI_In_DBx__6__AG CYREG_PRT2_AG\r
+#define SCSI_In_DBx__6__AMUX CYREG_PRT2_AMUX\r
+#define SCSI_In_DBx__6__BIE CYREG_PRT2_BIE\r
+#define SCSI_In_DBx__6__BIT_MASK CYREG_PRT2_BIT_MASK\r
+#define SCSI_In_DBx__6__BYP CYREG_PRT2_BYP\r
+#define SCSI_In_DBx__6__CTL CYREG_PRT2_CTL\r
+#define SCSI_In_DBx__6__DM0 CYREG_PRT2_DM0\r
+#define SCSI_In_DBx__6__DM1 CYREG_PRT2_DM1\r
+#define SCSI_In_DBx__6__DM2 CYREG_PRT2_DM2\r
+#define SCSI_In_DBx__6__DR CYREG_PRT2_DR\r
+#define SCSI_In_DBx__6__INP_DIS CYREG_PRT2_INP_DIS\r
+#define SCSI_In_DBx__6__INTTYPE CYREG_PICU2_INTTYPE5\r
+#define SCSI_In_DBx__6__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG\r
+#define SCSI_In_DBx__6__LCD_EN CYREG_PRT2_LCD_EN\r
+#define SCSI_In_DBx__6__MASK 0x20u\r
+#define SCSI_In_DBx__6__PC CYREG_PRT2_PC5\r
+#define SCSI_In_DBx__6__PORT 2u\r
+#define SCSI_In_DBx__6__PRT CYREG_PRT2_PRT\r
+#define SCSI_In_DBx__6__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL\r
+#define SCSI_In_DBx__6__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN\r
+#define SCSI_In_DBx__6__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0\r
+#define SCSI_In_DBx__6__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1\r
+#define SCSI_In_DBx__6__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0\r
+#define SCSI_In_DBx__6__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1\r
+#define SCSI_In_DBx__6__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT\r
+#define SCSI_In_DBx__6__PS CYREG_PRT2_PS\r
+#define SCSI_In_DBx__6__SHIFT 5u\r
+#define SCSI_In_DBx__6__SLW CYREG_PRT2_SLW\r
+#define SCSI_In_DBx__7__AG CYREG_PRT2_AG\r
+#define SCSI_In_DBx__7__AMUX CYREG_PRT2_AMUX\r
+#define SCSI_In_DBx__7__BIE CYREG_PRT2_BIE\r
+#define SCSI_In_DBx__7__BIT_MASK CYREG_PRT2_BIT_MASK\r
+#define SCSI_In_DBx__7__BYP CYREG_PRT2_BYP\r
+#define SCSI_In_DBx__7__CTL CYREG_PRT2_CTL\r
+#define SCSI_In_DBx__7__DM0 CYREG_PRT2_DM0\r
+#define SCSI_In_DBx__7__DM1 CYREG_PRT2_DM1\r
+#define SCSI_In_DBx__7__DM2 CYREG_PRT2_DM2\r
+#define SCSI_In_DBx__7__DR CYREG_PRT2_DR\r
+#define SCSI_In_DBx__7__INP_DIS CYREG_PRT2_INP_DIS\r
+#define SCSI_In_DBx__7__INTTYPE CYREG_PICU2_INTTYPE4\r
+#define SCSI_In_DBx__7__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG\r
+#define SCSI_In_DBx__7__LCD_EN CYREG_PRT2_LCD_EN\r
+#define SCSI_In_DBx__7__MASK 0x10u\r
+#define SCSI_In_DBx__7__PC CYREG_PRT2_PC4\r
+#define SCSI_In_DBx__7__PORT 2u\r
+#define SCSI_In_DBx__7__PRT CYREG_PRT2_PRT\r
+#define SCSI_In_DBx__7__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL\r
+#define SCSI_In_DBx__7__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN\r
+#define SCSI_In_DBx__7__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0\r
+#define SCSI_In_DBx__7__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1\r
+#define SCSI_In_DBx__7__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0\r
+#define SCSI_In_DBx__7__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1\r
+#define SCSI_In_DBx__7__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT\r
+#define SCSI_In_DBx__7__PS CYREG_PRT2_PS\r
+#define SCSI_In_DBx__7__SHIFT 4u\r
+#define SCSI_In_DBx__7__SLW CYREG_PRT2_SLW\r
+#define SCSI_In_DBx__DB0__AG CYREG_PRT5_AG\r
+#define SCSI_In_DBx__DB0__AMUX CYREG_PRT5_AMUX\r
+#define SCSI_In_DBx__DB0__BIE CYREG_PRT5_BIE\r
+#define SCSI_In_DBx__DB0__BIT_MASK CYREG_PRT5_BIT_MASK\r
+#define SCSI_In_DBx__DB0__BYP CYREG_PRT5_BYP\r
+#define SCSI_In_DBx__DB0__CTL CYREG_PRT5_CTL\r
+#define SCSI_In_DBx__DB0__DM0 CYREG_PRT5_DM0\r
+#define SCSI_In_DBx__DB0__DM1 CYREG_PRT5_DM1\r
+#define SCSI_In_DBx__DB0__DM2 CYREG_PRT5_DM2\r
+#define SCSI_In_DBx__DB0__DR CYREG_PRT5_DR\r
+#define SCSI_In_DBx__DB0__INP_DIS CYREG_PRT5_INP_DIS\r
+#define SCSI_In_DBx__DB0__INTTYPE CYREG_PICU5_INTTYPE3\r
+#define SCSI_In_DBx__DB0__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG\r
+#define SCSI_In_DBx__DB0__LCD_EN CYREG_PRT5_LCD_EN\r
+#define SCSI_In_DBx__DB0__MASK 0x08u\r
+#define SCSI_In_DBx__DB0__PC CYREG_PRT5_PC3\r
+#define SCSI_In_DBx__DB0__PORT 5u\r
+#define SCSI_In_DBx__DB0__PRT CYREG_PRT5_PRT\r
+#define SCSI_In_DBx__DB0__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL\r
+#define SCSI_In_DBx__DB0__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN\r
+#define SCSI_In_DBx__DB0__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0\r
+#define SCSI_In_DBx__DB0__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1\r
+#define SCSI_In_DBx__DB0__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0\r
+#define SCSI_In_DBx__DB0__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1\r
+#define SCSI_In_DBx__DB0__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT\r
+#define SCSI_In_DBx__DB0__PS CYREG_PRT5_PS\r
+#define SCSI_In_DBx__DB0__SHIFT 3u\r
+#define SCSI_In_DBx__DB0__SLW CYREG_PRT5_SLW\r
+#define SCSI_In_DBx__DB1__AG CYREG_PRT5_AG\r
+#define SCSI_In_DBx__DB1__AMUX CYREG_PRT5_AMUX\r
+#define SCSI_In_DBx__DB1__BIE CYREG_PRT5_BIE\r
+#define SCSI_In_DBx__DB1__BIT_MASK CYREG_PRT5_BIT_MASK\r
+#define SCSI_In_DBx__DB1__BYP CYREG_PRT5_BYP\r
+#define SCSI_In_DBx__DB1__CTL CYREG_PRT5_CTL\r
+#define SCSI_In_DBx__DB1__DM0 CYREG_PRT5_DM0\r
+#define SCSI_In_DBx__DB1__DM1 CYREG_PRT5_DM1\r
+#define SCSI_In_DBx__DB1__DM2 CYREG_PRT5_DM2\r
+#define SCSI_In_DBx__DB1__DR CYREG_PRT5_DR\r
+#define SCSI_In_DBx__DB1__INP_DIS CYREG_PRT5_INP_DIS\r
+#define SCSI_In_DBx__DB1__INTTYPE CYREG_PICU5_INTTYPE2\r
+#define SCSI_In_DBx__DB1__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG\r
+#define SCSI_In_DBx__DB1__LCD_EN CYREG_PRT5_LCD_EN\r
+#define SCSI_In_DBx__DB1__MASK 0x04u\r
+#define SCSI_In_DBx__DB1__PC CYREG_PRT5_PC2\r
+#define SCSI_In_DBx__DB1__PORT 5u\r
+#define SCSI_In_DBx__DB1__PRT CYREG_PRT5_PRT\r
+#define SCSI_In_DBx__DB1__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL\r
+#define SCSI_In_DBx__DB1__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN\r
+#define SCSI_In_DBx__DB1__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0\r
+#define SCSI_In_DBx__DB1__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1\r
+#define SCSI_In_DBx__DB1__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0\r
+#define SCSI_In_DBx__DB1__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1\r
+#define SCSI_In_DBx__DB1__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT\r
+#define SCSI_In_DBx__DB1__PS CYREG_PRT5_PS\r
+#define SCSI_In_DBx__DB1__SHIFT 2u\r
+#define SCSI_In_DBx__DB1__SLW CYREG_PRT5_SLW\r
+#define SCSI_In_DBx__DB2__AG CYREG_PRT6_AG\r
+#define SCSI_In_DBx__DB2__AMUX CYREG_PRT6_AMUX\r
+#define SCSI_In_DBx__DB2__BIE CYREG_PRT6_BIE\r
+#define SCSI_In_DBx__DB2__BIT_MASK CYREG_PRT6_BIT_MASK\r
+#define SCSI_In_DBx__DB2__BYP CYREG_PRT6_BYP\r
+#define SCSI_In_DBx__DB2__CTL CYREG_PRT6_CTL\r
+#define SCSI_In_DBx__DB2__DM0 CYREG_PRT6_DM0\r
+#define SCSI_In_DBx__DB2__DM1 CYREG_PRT6_DM1\r
+#define SCSI_In_DBx__DB2__DM2 CYREG_PRT6_DM2\r
+#define SCSI_In_DBx__DB2__DR CYREG_PRT6_DR\r
+#define SCSI_In_DBx__DB2__INP_DIS CYREG_PRT6_INP_DIS\r
+#define SCSI_In_DBx__DB2__INTTYPE CYREG_PICU6_INTTYPE7\r
+#define SCSI_In_DBx__DB2__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
+#define SCSI_In_DBx__DB2__LCD_EN CYREG_PRT6_LCD_EN\r
+#define SCSI_In_DBx__DB2__MASK 0x80u\r
+#define SCSI_In_DBx__DB2__PC CYREG_PRT6_PC7\r
+#define SCSI_In_DBx__DB2__PORT 6u\r
+#define SCSI_In_DBx__DB2__PRT CYREG_PRT6_PRT\r
+#define SCSI_In_DBx__DB2__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
+#define SCSI_In_DBx__DB2__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
+#define SCSI_In_DBx__DB2__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
+#define SCSI_In_DBx__DB2__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
+#define SCSI_In_DBx__DB2__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
+#define SCSI_In_DBx__DB2__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
+#define SCSI_In_DBx__DB2__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
+#define SCSI_In_DBx__DB2__PS CYREG_PRT6_PS\r
+#define SCSI_In_DBx__DB2__SHIFT 7u\r
+#define SCSI_In_DBx__DB2__SLW CYREG_PRT6_SLW\r
+#define SCSI_In_DBx__DB3__AG CYREG_PRT6_AG\r
+#define SCSI_In_DBx__DB3__AMUX CYREG_PRT6_AMUX\r
+#define SCSI_In_DBx__DB3__BIE CYREG_PRT6_BIE\r
+#define SCSI_In_DBx__DB3__BIT_MASK CYREG_PRT6_BIT_MASK\r
+#define SCSI_In_DBx__DB3__BYP CYREG_PRT6_BYP\r
+#define SCSI_In_DBx__DB3__CTL CYREG_PRT6_CTL\r
+#define SCSI_In_DBx__DB3__DM0 CYREG_PRT6_DM0\r
+#define SCSI_In_DBx__DB3__DM1 CYREG_PRT6_DM1\r
+#define SCSI_In_DBx__DB3__DM2 CYREG_PRT6_DM2\r
+#define SCSI_In_DBx__DB3__DR CYREG_PRT6_DR\r
+#define SCSI_In_DBx__DB3__INP_DIS CYREG_PRT6_INP_DIS\r
+#define SCSI_In_DBx__DB3__INTTYPE CYREG_PICU6_INTTYPE6\r
+#define SCSI_In_DBx__DB3__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
+#define SCSI_In_DBx__DB3__LCD_EN CYREG_PRT6_LCD_EN\r
+#define SCSI_In_DBx__DB3__MASK 0x40u\r
+#define SCSI_In_DBx__DB3__PC CYREG_PRT6_PC6\r
+#define SCSI_In_DBx__DB3__PORT 6u\r
+#define SCSI_In_DBx__DB3__PRT CYREG_PRT6_PRT\r
+#define SCSI_In_DBx__DB3__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
+#define SCSI_In_DBx__DB3__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
+#define SCSI_In_DBx__DB3__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
+#define SCSI_In_DBx__DB3__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
+#define SCSI_In_DBx__DB3__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
+#define SCSI_In_DBx__DB3__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
+#define SCSI_In_DBx__DB3__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
+#define SCSI_In_DBx__DB3__PS CYREG_PRT6_PS\r
+#define SCSI_In_DBx__DB3__SHIFT 6u\r
+#define SCSI_In_DBx__DB3__SLW CYREG_PRT6_SLW\r
+#define SCSI_In_DBx__DB4__AG CYREG_PRT12_AG\r
+#define SCSI_In_DBx__DB4__BIE CYREG_PRT12_BIE\r
+#define SCSI_In_DBx__DB4__BIT_MASK CYREG_PRT12_BIT_MASK\r
+#define SCSI_In_DBx__DB4__BYP CYREG_PRT12_BYP\r
+#define SCSI_In_DBx__DB4__DM0 CYREG_PRT12_DM0\r
+#define SCSI_In_DBx__DB4__DM1 CYREG_PRT12_DM1\r
+#define SCSI_In_DBx__DB4__DM2 CYREG_PRT12_DM2\r
+#define SCSI_In_DBx__DB4__DR CYREG_PRT12_DR\r
+#define SCSI_In_DBx__DB4__INP_DIS CYREG_PRT12_INP_DIS\r
+#define SCSI_In_DBx__DB4__INTTYPE CYREG_PICU12_INTTYPE5\r
+#define SCSI_In_DBx__DB4__MASK 0x20u\r
+#define SCSI_In_DBx__DB4__PC CYREG_PRT12_PC5\r
+#define SCSI_In_DBx__DB4__PORT 12u\r
+#define SCSI_In_DBx__DB4__PRT CYREG_PRT12_PRT\r
+#define SCSI_In_DBx__DB4__PRTDSI__DBL_SYNC_IN CYREG_PRT12_DBL_SYNC_IN\r
+#define SCSI_In_DBx__DB4__PRTDSI__OE_SEL0 CYREG_PRT12_OE_SEL0\r
+#define SCSI_In_DBx__DB4__PRTDSI__OE_SEL1 CYREG_PRT12_OE_SEL1\r
+#define SCSI_In_DBx__DB4__PRTDSI__OUT_SEL0 CYREG_PRT12_OUT_SEL0\r
+#define SCSI_In_DBx__DB4__PRTDSI__OUT_SEL1 CYREG_PRT12_OUT_SEL1\r
+#define SCSI_In_DBx__DB4__PRTDSI__SYNC_OUT CYREG_PRT12_SYNC_OUT\r
+#define SCSI_In_DBx__DB4__PS CYREG_PRT12_PS\r
+#define SCSI_In_DBx__DB4__SHIFT 5u\r
+#define SCSI_In_DBx__DB4__SIO_CFG CYREG_PRT12_SIO_CFG\r
+#define SCSI_In_DBx__DB4__SIO_DIFF CYREG_PRT12_SIO_DIFF\r
+#define SCSI_In_DBx__DB4__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN\r
+#define SCSI_In_DBx__DB4__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ\r
+#define SCSI_In_DBx__DB4__SLW CYREG_PRT12_SLW\r
+#define SCSI_In_DBx__DB5__AG CYREG_PRT12_AG\r
+#define SCSI_In_DBx__DB5__BIE CYREG_PRT12_BIE\r
+#define SCSI_In_DBx__DB5__BIT_MASK CYREG_PRT12_BIT_MASK\r
+#define SCSI_In_DBx__DB5__BYP CYREG_PRT12_BYP\r
+#define SCSI_In_DBx__DB5__DM0 CYREG_PRT12_DM0\r
+#define SCSI_In_DBx__DB5__DM1 CYREG_PRT12_DM1\r
+#define SCSI_In_DBx__DB5__DM2 CYREG_PRT12_DM2\r
+#define SCSI_In_DBx__DB5__DR CYREG_PRT12_DR\r
+#define SCSI_In_DBx__DB5__INP_DIS CYREG_PRT12_INP_DIS\r
+#define SCSI_In_DBx__DB5__INTTYPE CYREG_PICU12_INTTYPE4\r
+#define SCSI_In_DBx__DB5__MASK 0x10u\r
+#define SCSI_In_DBx__DB5__PC CYREG_PRT12_PC4\r
+#define SCSI_In_DBx__DB5__PORT 12u\r
+#define SCSI_In_DBx__DB5__PRT CYREG_PRT12_PRT\r
+#define SCSI_In_DBx__DB5__PRTDSI__DBL_SYNC_IN CYREG_PRT12_DBL_SYNC_IN\r
+#define SCSI_In_DBx__DB5__PRTDSI__OE_SEL0 CYREG_PRT12_OE_SEL0\r
+#define SCSI_In_DBx__DB5__PRTDSI__OE_SEL1 CYREG_PRT12_OE_SEL1\r
+#define SCSI_In_DBx__DB5__PRTDSI__OUT_SEL0 CYREG_PRT12_OUT_SEL0\r
+#define SCSI_In_DBx__DB5__PRTDSI__OUT_SEL1 CYREG_PRT12_OUT_SEL1\r
+#define SCSI_In_DBx__DB5__PRTDSI__SYNC_OUT CYREG_PRT12_SYNC_OUT\r
+#define SCSI_In_DBx__DB5__PS CYREG_PRT12_PS\r
+#define SCSI_In_DBx__DB5__SHIFT 4u\r
+#define SCSI_In_DBx__DB5__SIO_CFG CYREG_PRT12_SIO_CFG\r
+#define SCSI_In_DBx__DB5__SIO_DIFF CYREG_PRT12_SIO_DIFF\r
+#define SCSI_In_DBx__DB5__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN\r
+#define SCSI_In_DBx__DB5__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ\r
+#define SCSI_In_DBx__DB5__SLW CYREG_PRT12_SLW\r
+#define SCSI_In_DBx__DB6__AG CYREG_PRT2_AG\r
+#define SCSI_In_DBx__DB6__AMUX CYREG_PRT2_AMUX\r
+#define SCSI_In_DBx__DB6__BIE CYREG_PRT2_BIE\r
+#define SCSI_In_DBx__DB6__BIT_MASK CYREG_PRT2_BIT_MASK\r
+#define SCSI_In_DBx__DB6__BYP CYREG_PRT2_BYP\r
+#define SCSI_In_DBx__DB6__CTL CYREG_PRT2_CTL\r
+#define SCSI_In_DBx__DB6__DM0 CYREG_PRT2_DM0\r
+#define SCSI_In_DBx__DB6__DM1 CYREG_PRT2_DM1\r
+#define SCSI_In_DBx__DB6__DM2 CYREG_PRT2_DM2\r
+#define SCSI_In_DBx__DB6__DR CYREG_PRT2_DR\r
+#define SCSI_In_DBx__DB6__INP_DIS CYREG_PRT2_INP_DIS\r
+#define SCSI_In_DBx__DB6__INTTYPE CYREG_PICU2_INTTYPE5\r
+#define SCSI_In_DBx__DB6__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG\r
+#define SCSI_In_DBx__DB6__LCD_EN CYREG_PRT2_LCD_EN\r
+#define SCSI_In_DBx__DB6__MASK 0x20u\r
+#define SCSI_In_DBx__DB6__PC CYREG_PRT2_PC5\r
+#define SCSI_In_DBx__DB6__PORT 2u\r
+#define SCSI_In_DBx__DB6__PRT CYREG_PRT2_PRT\r
+#define SCSI_In_DBx__DB6__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL\r
+#define SCSI_In_DBx__DB6__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN\r
+#define SCSI_In_DBx__DB6__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0\r
+#define SCSI_In_DBx__DB6__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1\r
+#define SCSI_In_DBx__DB6__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0\r
+#define SCSI_In_DBx__DB6__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1\r
+#define SCSI_In_DBx__DB6__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT\r
+#define SCSI_In_DBx__DB6__PS CYREG_PRT2_PS\r
+#define SCSI_In_DBx__DB6__SHIFT 5u\r
+#define SCSI_In_DBx__DB6__SLW CYREG_PRT2_SLW\r
+#define SCSI_In_DBx__DB7__AG CYREG_PRT2_AG\r
+#define SCSI_In_DBx__DB7__AMUX CYREG_PRT2_AMUX\r
+#define SCSI_In_DBx__DB7__BIE CYREG_PRT2_BIE\r
+#define SCSI_In_DBx__DB7__BIT_MASK CYREG_PRT2_BIT_MASK\r
+#define SCSI_In_DBx__DB7__BYP CYREG_PRT2_BYP\r
+#define SCSI_In_DBx__DB7__CTL CYREG_PRT2_CTL\r
+#define SCSI_In_DBx__DB7__DM0 CYREG_PRT2_DM0\r
+#define SCSI_In_DBx__DB7__DM1 CYREG_PRT2_DM1\r
+#define SCSI_In_DBx__DB7__DM2 CYREG_PRT2_DM2\r
+#define SCSI_In_DBx__DB7__DR CYREG_PRT2_DR\r
+#define SCSI_In_DBx__DB7__INP_DIS CYREG_PRT2_INP_DIS\r
+#define SCSI_In_DBx__DB7__INTTYPE CYREG_PICU2_INTTYPE4\r
+#define SCSI_In_DBx__DB7__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG\r
+#define SCSI_In_DBx__DB7__LCD_EN CYREG_PRT2_LCD_EN\r
+#define SCSI_In_DBx__DB7__MASK 0x10u\r
+#define SCSI_In_DBx__DB7__PC CYREG_PRT2_PC4\r
+#define SCSI_In_DBx__DB7__PORT 2u\r
+#define SCSI_In_DBx__DB7__PRT CYREG_PRT2_PRT\r
+#define SCSI_In_DBx__DB7__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL\r
+#define SCSI_In_DBx__DB7__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN\r
+#define SCSI_In_DBx__DB7__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0\r
+#define SCSI_In_DBx__DB7__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1\r
+#define SCSI_In_DBx__DB7__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0\r
+#define SCSI_In_DBx__DB7__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1\r
+#define SCSI_In_DBx__DB7__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT\r
+#define SCSI_In_DBx__DB7__PS CYREG_PRT2_PS\r
+#define SCSI_In_DBx__DB7__SHIFT 4u\r
+#define SCSI_In_DBx__DB7__SLW CYREG_PRT2_SLW\r
 \r
 /* SCSI_Noise */\r
 #define SCSI_Noise__0__AG CYREG_PRT2_AG\r
@@ -2735,6 +1200,1698 @@
 #define SCSI_Noise__SEL__SHIFT 3u\r
 #define SCSI_Noise__SEL__SLW CYREG_PRT4_SLW\r
 \r
+/* SCSI_Out */\r
+#define SCSI_Out__0__AG CYREG_PRT15_AG\r
+#define SCSI_Out__0__AMUX CYREG_PRT15_AMUX\r
+#define SCSI_Out__0__BIE CYREG_PRT15_BIE\r
+#define SCSI_Out__0__BIT_MASK CYREG_PRT15_BIT_MASK\r
+#define SCSI_Out__0__BYP CYREG_PRT15_BYP\r
+#define SCSI_Out__0__CTL CYREG_PRT15_CTL\r
+#define SCSI_Out__0__DM0 CYREG_PRT15_DM0\r
+#define SCSI_Out__0__DM1 CYREG_PRT15_DM1\r
+#define SCSI_Out__0__DM2 CYREG_PRT15_DM2\r
+#define SCSI_Out__0__DR CYREG_PRT15_DR\r
+#define SCSI_Out__0__INP_DIS CYREG_PRT15_INP_DIS\r
+#define SCSI_Out__0__INTTYPE CYREG_PICU15_INTTYPE5\r
+#define SCSI_Out__0__LCD_COM_SEG CYREG_PRT15_LCD_COM_SEG\r
+#define SCSI_Out__0__LCD_EN CYREG_PRT15_LCD_EN\r
+#define SCSI_Out__0__MASK 0x20u\r
+#define SCSI_Out__0__PC CYREG_IO_PC_PRT15_PC5\r
+#define SCSI_Out__0__PORT 15u\r
+#define SCSI_Out__0__PRT CYREG_PRT15_PRT\r
+#define SCSI_Out__0__PRTDSI__CAPS_SEL CYREG_PRT15_CAPS_SEL\r
+#define SCSI_Out__0__PRTDSI__DBL_SYNC_IN CYREG_PRT15_DBL_SYNC_IN\r
+#define SCSI_Out__0__PRTDSI__OE_SEL0 CYREG_PRT15_OE_SEL0\r
+#define SCSI_Out__0__PRTDSI__OE_SEL1 CYREG_PRT15_OE_SEL1\r
+#define SCSI_Out__0__PRTDSI__OUT_SEL0 CYREG_PRT15_OUT_SEL0\r
+#define SCSI_Out__0__PRTDSI__OUT_SEL1 CYREG_PRT15_OUT_SEL1\r
+#define SCSI_Out__0__PRTDSI__SYNC_OUT CYREG_PRT15_SYNC_OUT\r
+#define SCSI_Out__0__PS CYREG_PRT15_PS\r
+#define SCSI_Out__0__SHIFT 5u\r
+#define SCSI_Out__0__SLW CYREG_PRT15_SLW\r
+#define SCSI_Out__1__AG CYREG_PRT15_AG\r
+#define SCSI_Out__1__AMUX CYREG_PRT15_AMUX\r
+#define SCSI_Out__1__BIE CYREG_PRT15_BIE\r
+#define SCSI_Out__1__BIT_MASK CYREG_PRT15_BIT_MASK\r
+#define SCSI_Out__1__BYP CYREG_PRT15_BYP\r
+#define SCSI_Out__1__CTL CYREG_PRT15_CTL\r
+#define SCSI_Out__1__DM0 CYREG_PRT15_DM0\r
+#define SCSI_Out__1__DM1 CYREG_PRT15_DM1\r
+#define SCSI_Out__1__DM2 CYREG_PRT15_DM2\r
+#define SCSI_Out__1__DR CYREG_PRT15_DR\r
+#define SCSI_Out__1__INP_DIS CYREG_PRT15_INP_DIS\r
+#define SCSI_Out__1__INTTYPE CYREG_PICU15_INTTYPE4\r
+#define SCSI_Out__1__LCD_COM_SEG CYREG_PRT15_LCD_COM_SEG\r
+#define SCSI_Out__1__LCD_EN CYREG_PRT15_LCD_EN\r
+#define SCSI_Out__1__MASK 0x10u\r
+#define SCSI_Out__1__PC CYREG_IO_PC_PRT15_PC4\r
+#define SCSI_Out__1__PORT 15u\r
+#define SCSI_Out__1__PRT CYREG_PRT15_PRT\r
+#define SCSI_Out__1__PRTDSI__CAPS_SEL CYREG_PRT15_CAPS_SEL\r
+#define SCSI_Out__1__PRTDSI__DBL_SYNC_IN CYREG_PRT15_DBL_SYNC_IN\r
+#define SCSI_Out__1__PRTDSI__OE_SEL0 CYREG_PRT15_OE_SEL0\r
+#define SCSI_Out__1__PRTDSI__OE_SEL1 CYREG_PRT15_OE_SEL1\r
+#define SCSI_Out__1__PRTDSI__OUT_SEL0 CYREG_PRT15_OUT_SEL0\r
+#define SCSI_Out__1__PRTDSI__OUT_SEL1 CYREG_PRT15_OUT_SEL1\r
+#define SCSI_Out__1__PRTDSI__SYNC_OUT CYREG_PRT15_SYNC_OUT\r
+#define SCSI_Out__1__PS CYREG_PRT15_PS\r
+#define SCSI_Out__1__SHIFT 4u\r
+#define SCSI_Out__1__SLW CYREG_PRT15_SLW\r
+#define SCSI_Out__2__AG CYREG_PRT6_AG\r
+#define SCSI_Out__2__AMUX CYREG_PRT6_AMUX\r
+#define SCSI_Out__2__BIE CYREG_PRT6_BIE\r
+#define SCSI_Out__2__BIT_MASK CYREG_PRT6_BIT_MASK\r
+#define SCSI_Out__2__BYP CYREG_PRT6_BYP\r
+#define SCSI_Out__2__CTL CYREG_PRT6_CTL\r
+#define SCSI_Out__2__DM0 CYREG_PRT6_DM0\r
+#define SCSI_Out__2__DM1 CYREG_PRT6_DM1\r
+#define SCSI_Out__2__DM2 CYREG_PRT6_DM2\r
+#define SCSI_Out__2__DR CYREG_PRT6_DR\r
+#define SCSI_Out__2__INP_DIS CYREG_PRT6_INP_DIS\r
+#define SCSI_Out__2__INTTYPE CYREG_PICU6_INTTYPE1\r
+#define SCSI_Out__2__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
+#define SCSI_Out__2__LCD_EN CYREG_PRT6_LCD_EN\r
+#define SCSI_Out__2__MASK 0x02u\r
+#define SCSI_Out__2__PC CYREG_PRT6_PC1\r
+#define SCSI_Out__2__PORT 6u\r
+#define SCSI_Out__2__PRT CYREG_PRT6_PRT\r
+#define SCSI_Out__2__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
+#define SCSI_Out__2__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
+#define SCSI_Out__2__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
+#define SCSI_Out__2__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
+#define SCSI_Out__2__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
+#define SCSI_Out__2__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
+#define SCSI_Out__2__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
+#define SCSI_Out__2__PS CYREG_PRT6_PS\r
+#define SCSI_Out__2__SHIFT 1u\r
+#define SCSI_Out__2__SLW CYREG_PRT6_SLW\r
+#define SCSI_Out__3__AG CYREG_PRT6_AG\r
+#define SCSI_Out__3__AMUX CYREG_PRT6_AMUX\r
+#define SCSI_Out__3__BIE CYREG_PRT6_BIE\r
+#define SCSI_Out__3__BIT_MASK CYREG_PRT6_BIT_MASK\r
+#define SCSI_Out__3__BYP CYREG_PRT6_BYP\r
+#define SCSI_Out__3__CTL CYREG_PRT6_CTL\r
+#define SCSI_Out__3__DM0 CYREG_PRT6_DM0\r
+#define SCSI_Out__3__DM1 CYREG_PRT6_DM1\r
+#define SCSI_Out__3__DM2 CYREG_PRT6_DM2\r
+#define SCSI_Out__3__DR CYREG_PRT6_DR\r
+#define SCSI_Out__3__INP_DIS CYREG_PRT6_INP_DIS\r
+#define SCSI_Out__3__INTTYPE CYREG_PICU6_INTTYPE0\r
+#define SCSI_Out__3__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
+#define SCSI_Out__3__LCD_EN CYREG_PRT6_LCD_EN\r
+#define SCSI_Out__3__MASK 0x01u\r
+#define SCSI_Out__3__PC CYREG_PRT6_PC0\r
+#define SCSI_Out__3__PORT 6u\r
+#define SCSI_Out__3__PRT CYREG_PRT6_PRT\r
+#define SCSI_Out__3__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
+#define SCSI_Out__3__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
+#define SCSI_Out__3__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
+#define SCSI_Out__3__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
+#define SCSI_Out__3__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
+#define SCSI_Out__3__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
+#define SCSI_Out__3__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
+#define SCSI_Out__3__PS CYREG_PRT6_PS\r
+#define SCSI_Out__3__SHIFT 0u\r
+#define SCSI_Out__3__SLW CYREG_PRT6_SLW\r
+#define SCSI_Out__4__AG CYREG_PRT4_AG\r
+#define SCSI_Out__4__AMUX CYREG_PRT4_AMUX\r
+#define SCSI_Out__4__BIE CYREG_PRT4_BIE\r
+#define SCSI_Out__4__BIT_MASK CYREG_PRT4_BIT_MASK\r
+#define SCSI_Out__4__BYP CYREG_PRT4_BYP\r
+#define SCSI_Out__4__CTL CYREG_PRT4_CTL\r
+#define SCSI_Out__4__DM0 CYREG_PRT4_DM0\r
+#define SCSI_Out__4__DM1 CYREG_PRT4_DM1\r
+#define SCSI_Out__4__DM2 CYREG_PRT4_DM2\r
+#define SCSI_Out__4__DR CYREG_PRT4_DR\r
+#define SCSI_Out__4__INP_DIS CYREG_PRT4_INP_DIS\r
+#define SCSI_Out__4__INTTYPE CYREG_PICU4_INTTYPE5\r
+#define SCSI_Out__4__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG\r
+#define SCSI_Out__4__LCD_EN CYREG_PRT4_LCD_EN\r
+#define SCSI_Out__4__MASK 0x20u\r
+#define SCSI_Out__4__PC CYREG_PRT4_PC5\r
+#define SCSI_Out__4__PORT 4u\r
+#define SCSI_Out__4__PRT CYREG_PRT4_PRT\r
+#define SCSI_Out__4__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL\r
+#define SCSI_Out__4__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN\r
+#define SCSI_Out__4__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0\r
+#define SCSI_Out__4__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1\r
+#define SCSI_Out__4__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0\r
+#define SCSI_Out__4__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1\r
+#define SCSI_Out__4__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT\r
+#define SCSI_Out__4__PS CYREG_PRT4_PS\r
+#define SCSI_Out__4__SHIFT 5u\r
+#define SCSI_Out__4__SLW CYREG_PRT4_SLW\r
+#define SCSI_Out__5__AG CYREG_PRT4_AG\r
+#define SCSI_Out__5__AMUX CYREG_PRT4_AMUX\r
+#define SCSI_Out__5__BIE CYREG_PRT4_BIE\r
+#define SCSI_Out__5__BIT_MASK CYREG_PRT4_BIT_MASK\r
+#define SCSI_Out__5__BYP CYREG_PRT4_BYP\r
+#define SCSI_Out__5__CTL CYREG_PRT4_CTL\r
+#define SCSI_Out__5__DM0 CYREG_PRT4_DM0\r
+#define SCSI_Out__5__DM1 CYREG_PRT4_DM1\r
+#define SCSI_Out__5__DM2 CYREG_PRT4_DM2\r
+#define SCSI_Out__5__DR CYREG_PRT4_DR\r
+#define SCSI_Out__5__INP_DIS CYREG_PRT4_INP_DIS\r
+#define SCSI_Out__5__INTTYPE CYREG_PICU4_INTTYPE4\r
+#define SCSI_Out__5__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG\r
+#define SCSI_Out__5__LCD_EN CYREG_PRT4_LCD_EN\r
+#define SCSI_Out__5__MASK 0x10u\r
+#define SCSI_Out__5__PC CYREG_PRT4_PC4\r
+#define SCSI_Out__5__PORT 4u\r
+#define SCSI_Out__5__PRT CYREG_PRT4_PRT\r
+#define SCSI_Out__5__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL\r
+#define SCSI_Out__5__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN\r
+#define SCSI_Out__5__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0\r
+#define SCSI_Out__5__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1\r
+#define SCSI_Out__5__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0\r
+#define SCSI_Out__5__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1\r
+#define SCSI_Out__5__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT\r
+#define SCSI_Out__5__PS CYREG_PRT4_PS\r
+#define SCSI_Out__5__SHIFT 4u\r
+#define SCSI_Out__5__SLW CYREG_PRT4_SLW\r
+#define SCSI_Out__6__AG CYREG_PRT0_AG\r
+#define SCSI_Out__6__AMUX CYREG_PRT0_AMUX\r
+#define SCSI_Out__6__BIE CYREG_PRT0_BIE\r
+#define SCSI_Out__6__BIT_MASK CYREG_PRT0_BIT_MASK\r
+#define SCSI_Out__6__BYP CYREG_PRT0_BYP\r
+#define SCSI_Out__6__CTL CYREG_PRT0_CTL\r
+#define SCSI_Out__6__DM0 CYREG_PRT0_DM0\r
+#define SCSI_Out__6__DM1 CYREG_PRT0_DM1\r
+#define SCSI_Out__6__DM2 CYREG_PRT0_DM2\r
+#define SCSI_Out__6__DR CYREG_PRT0_DR\r
+#define SCSI_Out__6__INP_DIS CYREG_PRT0_INP_DIS\r
+#define SCSI_Out__6__INTTYPE CYREG_PICU0_INTTYPE7\r
+#define SCSI_Out__6__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG\r
+#define SCSI_Out__6__LCD_EN CYREG_PRT0_LCD_EN\r
+#define SCSI_Out__6__MASK 0x80u\r
+#define SCSI_Out__6__PC CYREG_PRT0_PC7\r
+#define SCSI_Out__6__PORT 0u\r
+#define SCSI_Out__6__PRT CYREG_PRT0_PRT\r
+#define SCSI_Out__6__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL\r
+#define SCSI_Out__6__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN\r
+#define SCSI_Out__6__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0\r
+#define SCSI_Out__6__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1\r
+#define SCSI_Out__6__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0\r
+#define SCSI_Out__6__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1\r
+#define SCSI_Out__6__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT\r
+#define SCSI_Out__6__PS CYREG_PRT0_PS\r
+#define SCSI_Out__6__SHIFT 7u\r
+#define SCSI_Out__6__SLW CYREG_PRT0_SLW\r
+#define SCSI_Out__7__AG CYREG_PRT0_AG\r
+#define SCSI_Out__7__AMUX CYREG_PRT0_AMUX\r
+#define SCSI_Out__7__BIE CYREG_PRT0_BIE\r
+#define SCSI_Out__7__BIT_MASK CYREG_PRT0_BIT_MASK\r
+#define SCSI_Out__7__BYP CYREG_PRT0_BYP\r
+#define SCSI_Out__7__CTL CYREG_PRT0_CTL\r
+#define SCSI_Out__7__DM0 CYREG_PRT0_DM0\r
+#define SCSI_Out__7__DM1 CYREG_PRT0_DM1\r
+#define SCSI_Out__7__DM2 CYREG_PRT0_DM2\r
+#define SCSI_Out__7__DR CYREG_PRT0_DR\r
+#define SCSI_Out__7__INP_DIS CYREG_PRT0_INP_DIS\r
+#define SCSI_Out__7__INTTYPE CYREG_PICU0_INTTYPE6\r
+#define SCSI_Out__7__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG\r
+#define SCSI_Out__7__LCD_EN CYREG_PRT0_LCD_EN\r
+#define SCSI_Out__7__MASK 0x40u\r
+#define SCSI_Out__7__PC CYREG_PRT0_PC6\r
+#define SCSI_Out__7__PORT 0u\r
+#define SCSI_Out__7__PRT CYREG_PRT0_PRT\r
+#define SCSI_Out__7__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL\r
+#define SCSI_Out__7__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN\r
+#define SCSI_Out__7__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0\r
+#define SCSI_Out__7__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1\r
+#define SCSI_Out__7__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0\r
+#define SCSI_Out__7__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1\r
+#define SCSI_Out__7__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT\r
+#define SCSI_Out__7__PS CYREG_PRT0_PS\r
+#define SCSI_Out__7__SHIFT 6u\r
+#define SCSI_Out__7__SLW CYREG_PRT0_SLW\r
+#define SCSI_Out__8__AG CYREG_PRT0_AG\r
+#define SCSI_Out__8__AMUX CYREG_PRT0_AMUX\r
+#define SCSI_Out__8__BIE CYREG_PRT0_BIE\r
+#define SCSI_Out__8__BIT_MASK CYREG_PRT0_BIT_MASK\r
+#define SCSI_Out__8__BYP CYREG_PRT0_BYP\r
+#define SCSI_Out__8__CTL CYREG_PRT0_CTL\r
+#define SCSI_Out__8__DM0 CYREG_PRT0_DM0\r
+#define SCSI_Out__8__DM1 CYREG_PRT0_DM1\r
+#define SCSI_Out__8__DM2 CYREG_PRT0_DM2\r
+#define SCSI_Out__8__DR CYREG_PRT0_DR\r
+#define SCSI_Out__8__INP_DIS CYREG_PRT0_INP_DIS\r
+#define SCSI_Out__8__INTTYPE CYREG_PICU0_INTTYPE3\r
+#define SCSI_Out__8__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG\r
+#define SCSI_Out__8__LCD_EN CYREG_PRT0_LCD_EN\r
+#define SCSI_Out__8__MASK 0x08u\r
+#define SCSI_Out__8__PC CYREG_PRT0_PC3\r
+#define SCSI_Out__8__PORT 0u\r
+#define SCSI_Out__8__PRT CYREG_PRT0_PRT\r
+#define SCSI_Out__8__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL\r
+#define SCSI_Out__8__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN\r
+#define SCSI_Out__8__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0\r
+#define SCSI_Out__8__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1\r
+#define SCSI_Out__8__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0\r
+#define SCSI_Out__8__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1\r
+#define SCSI_Out__8__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT\r
+#define SCSI_Out__8__PS CYREG_PRT0_PS\r
+#define SCSI_Out__8__SHIFT 3u\r
+#define SCSI_Out__8__SLW CYREG_PRT0_SLW\r
+#define SCSI_Out__9__AG CYREG_PRT0_AG\r
+#define SCSI_Out__9__AMUX CYREG_PRT0_AMUX\r
+#define SCSI_Out__9__BIE CYREG_PRT0_BIE\r
+#define SCSI_Out__9__BIT_MASK CYREG_PRT0_BIT_MASK\r
+#define SCSI_Out__9__BYP CYREG_PRT0_BYP\r
+#define SCSI_Out__9__CTL CYREG_PRT0_CTL\r
+#define SCSI_Out__9__DM0 CYREG_PRT0_DM0\r
+#define SCSI_Out__9__DM1 CYREG_PRT0_DM1\r
+#define SCSI_Out__9__DM2 CYREG_PRT0_DM2\r
+#define SCSI_Out__9__DR CYREG_PRT0_DR\r
+#define SCSI_Out__9__INP_DIS CYREG_PRT0_INP_DIS\r
+#define SCSI_Out__9__INTTYPE CYREG_PICU0_INTTYPE2\r
+#define SCSI_Out__9__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG\r
+#define SCSI_Out__9__LCD_EN CYREG_PRT0_LCD_EN\r
+#define SCSI_Out__9__MASK 0x04u\r
+#define SCSI_Out__9__PC CYREG_PRT0_PC2\r
+#define SCSI_Out__9__PORT 0u\r
+#define SCSI_Out__9__PRT CYREG_PRT0_PRT\r
+#define SCSI_Out__9__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL\r
+#define SCSI_Out__9__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN\r
+#define SCSI_Out__9__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0\r
+#define SCSI_Out__9__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1\r
+#define SCSI_Out__9__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0\r
+#define SCSI_Out__9__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1\r
+#define SCSI_Out__9__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT\r
+#define SCSI_Out__9__PS CYREG_PRT0_PS\r
+#define SCSI_Out__9__SHIFT 2u\r
+#define SCSI_Out__9__SLW CYREG_PRT0_SLW\r
+#define SCSI_Out__ACK__AG CYREG_PRT6_AG\r
+#define SCSI_Out__ACK__AMUX CYREG_PRT6_AMUX\r
+#define SCSI_Out__ACK__BIE CYREG_PRT6_BIE\r
+#define SCSI_Out__ACK__BIT_MASK CYREG_PRT6_BIT_MASK\r
+#define SCSI_Out__ACK__BYP CYREG_PRT6_BYP\r
+#define SCSI_Out__ACK__CTL CYREG_PRT6_CTL\r
+#define SCSI_Out__ACK__DM0 CYREG_PRT6_DM0\r
+#define SCSI_Out__ACK__DM1 CYREG_PRT6_DM1\r
+#define SCSI_Out__ACK__DM2 CYREG_PRT6_DM2\r
+#define SCSI_Out__ACK__DR CYREG_PRT6_DR\r
+#define SCSI_Out__ACK__INP_DIS CYREG_PRT6_INP_DIS\r
+#define SCSI_Out__ACK__INTTYPE CYREG_PICU6_INTTYPE0\r
+#define SCSI_Out__ACK__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
+#define SCSI_Out__ACK__LCD_EN CYREG_PRT6_LCD_EN\r
+#define SCSI_Out__ACK__MASK 0x01u\r
+#define SCSI_Out__ACK__PC CYREG_PRT6_PC0\r
+#define SCSI_Out__ACK__PORT 6u\r
+#define SCSI_Out__ACK__PRT CYREG_PRT6_PRT\r
+#define SCSI_Out__ACK__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
+#define SCSI_Out__ACK__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
+#define SCSI_Out__ACK__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
+#define SCSI_Out__ACK__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
+#define SCSI_Out__ACK__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
+#define SCSI_Out__ACK__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
+#define SCSI_Out__ACK__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
+#define SCSI_Out__ACK__PS CYREG_PRT6_PS\r
+#define SCSI_Out__ACK__SHIFT 0u\r
+#define SCSI_Out__ACK__SLW CYREG_PRT6_SLW\r
+#define SCSI_Out__ATN__AG CYREG_PRT15_AG\r
+#define SCSI_Out__ATN__AMUX CYREG_PRT15_AMUX\r
+#define SCSI_Out__ATN__BIE CYREG_PRT15_BIE\r
+#define SCSI_Out__ATN__BIT_MASK CYREG_PRT15_BIT_MASK\r
+#define SCSI_Out__ATN__BYP CYREG_PRT15_BYP\r
+#define SCSI_Out__ATN__CTL CYREG_PRT15_CTL\r
+#define SCSI_Out__ATN__DM0 CYREG_PRT15_DM0\r
+#define SCSI_Out__ATN__DM1 CYREG_PRT15_DM1\r
+#define SCSI_Out__ATN__DM2 CYREG_PRT15_DM2\r
+#define SCSI_Out__ATN__DR CYREG_PRT15_DR\r
+#define SCSI_Out__ATN__INP_DIS CYREG_PRT15_INP_DIS\r
+#define SCSI_Out__ATN__INTTYPE CYREG_PICU15_INTTYPE4\r
+#define SCSI_Out__ATN__LCD_COM_SEG CYREG_PRT15_LCD_COM_SEG\r
+#define SCSI_Out__ATN__LCD_EN CYREG_PRT15_LCD_EN\r
+#define SCSI_Out__ATN__MASK 0x10u\r
+#define SCSI_Out__ATN__PC CYREG_IO_PC_PRT15_PC4\r
+#define SCSI_Out__ATN__PORT 15u\r
+#define SCSI_Out__ATN__PRT CYREG_PRT15_PRT\r
+#define SCSI_Out__ATN__PRTDSI__CAPS_SEL CYREG_PRT15_CAPS_SEL\r
+#define SCSI_Out__ATN__PRTDSI__DBL_SYNC_IN CYREG_PRT15_DBL_SYNC_IN\r
+#define SCSI_Out__ATN__PRTDSI__OE_SEL0 CYREG_PRT15_OE_SEL0\r
+#define SCSI_Out__ATN__PRTDSI__OE_SEL1 CYREG_PRT15_OE_SEL1\r
+#define SCSI_Out__ATN__PRTDSI__OUT_SEL0 CYREG_PRT15_OUT_SEL0\r
+#define SCSI_Out__ATN__PRTDSI__OUT_SEL1 CYREG_PRT15_OUT_SEL1\r
+#define SCSI_Out__ATN__PRTDSI__SYNC_OUT CYREG_PRT15_SYNC_OUT\r
+#define SCSI_Out__ATN__PS CYREG_PRT15_PS\r
+#define SCSI_Out__ATN__SHIFT 4u\r
+#define SCSI_Out__ATN__SLW CYREG_PRT15_SLW\r
+#define SCSI_Out__BSY__AG CYREG_PRT6_AG\r
+#define SCSI_Out__BSY__AMUX CYREG_PRT6_AMUX\r
+#define SCSI_Out__BSY__BIE CYREG_PRT6_BIE\r
+#define SCSI_Out__BSY__BIT_MASK CYREG_PRT6_BIT_MASK\r
+#define SCSI_Out__BSY__BYP CYREG_PRT6_BYP\r
+#define SCSI_Out__BSY__CTL CYREG_PRT6_CTL\r
+#define SCSI_Out__BSY__DM0 CYREG_PRT6_DM0\r
+#define SCSI_Out__BSY__DM1 CYREG_PRT6_DM1\r
+#define SCSI_Out__BSY__DM2 CYREG_PRT6_DM2\r
+#define SCSI_Out__BSY__DR CYREG_PRT6_DR\r
+#define SCSI_Out__BSY__INP_DIS CYREG_PRT6_INP_DIS\r
+#define SCSI_Out__BSY__INTTYPE CYREG_PICU6_INTTYPE1\r
+#define SCSI_Out__BSY__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
+#define SCSI_Out__BSY__LCD_EN CYREG_PRT6_LCD_EN\r
+#define SCSI_Out__BSY__MASK 0x02u\r
+#define SCSI_Out__BSY__PC CYREG_PRT6_PC1\r
+#define SCSI_Out__BSY__PORT 6u\r
+#define SCSI_Out__BSY__PRT CYREG_PRT6_PRT\r
+#define SCSI_Out__BSY__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
+#define SCSI_Out__BSY__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
+#define SCSI_Out__BSY__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
+#define SCSI_Out__BSY__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
+#define SCSI_Out__BSY__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
+#define SCSI_Out__BSY__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
+#define SCSI_Out__BSY__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
+#define SCSI_Out__BSY__PS CYREG_PRT6_PS\r
+#define SCSI_Out__BSY__SHIFT 1u\r
+#define SCSI_Out__BSY__SLW CYREG_PRT6_SLW\r
+#define SCSI_Out__CD_raw__AG CYREG_PRT0_AG\r
+#define SCSI_Out__CD_raw__AMUX CYREG_PRT0_AMUX\r
+#define SCSI_Out__CD_raw__BIE CYREG_PRT0_BIE\r
+#define SCSI_Out__CD_raw__BIT_MASK CYREG_PRT0_BIT_MASK\r
+#define SCSI_Out__CD_raw__BYP CYREG_PRT0_BYP\r
+#define SCSI_Out__CD_raw__CTL CYREG_PRT0_CTL\r
+#define SCSI_Out__CD_raw__DM0 CYREG_PRT0_DM0\r
+#define SCSI_Out__CD_raw__DM1 CYREG_PRT0_DM1\r
+#define SCSI_Out__CD_raw__DM2 CYREG_PRT0_DM2\r
+#define SCSI_Out__CD_raw__DR CYREG_PRT0_DR\r
+#define SCSI_Out__CD_raw__INP_DIS CYREG_PRT0_INP_DIS\r
+#define SCSI_Out__CD_raw__INTTYPE CYREG_PICU0_INTTYPE6\r
+#define SCSI_Out__CD_raw__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG\r
+#define SCSI_Out__CD_raw__LCD_EN CYREG_PRT0_LCD_EN\r
+#define SCSI_Out__CD_raw__MASK 0x40u\r
+#define SCSI_Out__CD_raw__PC CYREG_PRT0_PC6\r
+#define SCSI_Out__CD_raw__PORT 0u\r
+#define SCSI_Out__CD_raw__PRT CYREG_PRT0_PRT\r
+#define SCSI_Out__CD_raw__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL\r
+#define SCSI_Out__CD_raw__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN\r
+#define SCSI_Out__CD_raw__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0\r
+#define SCSI_Out__CD_raw__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1\r
+#define SCSI_Out__CD_raw__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0\r
+#define SCSI_Out__CD_raw__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1\r
+#define SCSI_Out__CD_raw__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT\r
+#define SCSI_Out__CD_raw__PS CYREG_PRT0_PS\r
+#define SCSI_Out__CD_raw__SHIFT 6u\r
+#define SCSI_Out__CD_raw__SLW CYREG_PRT0_SLW\r
+#define SCSI_Out__DBP_raw__AG CYREG_PRT15_AG\r
+#define SCSI_Out__DBP_raw__AMUX CYREG_PRT15_AMUX\r
+#define SCSI_Out__DBP_raw__BIE CYREG_PRT15_BIE\r
+#define SCSI_Out__DBP_raw__BIT_MASK CYREG_PRT15_BIT_MASK\r
+#define SCSI_Out__DBP_raw__BYP CYREG_PRT15_BYP\r
+#define SCSI_Out__DBP_raw__CTL CYREG_PRT15_CTL\r
+#define SCSI_Out__DBP_raw__DM0 CYREG_PRT15_DM0\r
+#define SCSI_Out__DBP_raw__DM1 CYREG_PRT15_DM1\r
+#define SCSI_Out__DBP_raw__DM2 CYREG_PRT15_DM2\r
+#define SCSI_Out__DBP_raw__DR CYREG_PRT15_DR\r
+#define SCSI_Out__DBP_raw__INP_DIS CYREG_PRT15_INP_DIS\r
+#define SCSI_Out__DBP_raw__INTTYPE CYREG_PICU15_INTTYPE5\r
+#define SCSI_Out__DBP_raw__LCD_COM_SEG CYREG_PRT15_LCD_COM_SEG\r
+#define SCSI_Out__DBP_raw__LCD_EN CYREG_PRT15_LCD_EN\r
+#define SCSI_Out__DBP_raw__MASK 0x20u\r
+#define SCSI_Out__DBP_raw__PC CYREG_IO_PC_PRT15_PC5\r
+#define SCSI_Out__DBP_raw__PORT 15u\r
+#define SCSI_Out__DBP_raw__PRT CYREG_PRT15_PRT\r
+#define SCSI_Out__DBP_raw__PRTDSI__CAPS_SEL CYREG_PRT15_CAPS_SEL\r
+#define SCSI_Out__DBP_raw__PRTDSI__DBL_SYNC_IN CYREG_PRT15_DBL_SYNC_IN\r
+#define SCSI_Out__DBP_raw__PRTDSI__OE_SEL0 CYREG_PRT15_OE_SEL0\r
+#define SCSI_Out__DBP_raw__PRTDSI__OE_SEL1 CYREG_PRT15_OE_SEL1\r
+#define SCSI_Out__DBP_raw__PRTDSI__OUT_SEL0 CYREG_PRT15_OUT_SEL0\r
+#define SCSI_Out__DBP_raw__PRTDSI__OUT_SEL1 CYREG_PRT15_OUT_SEL1\r
+#define SCSI_Out__DBP_raw__PRTDSI__SYNC_OUT CYREG_PRT15_SYNC_OUT\r
+#define SCSI_Out__DBP_raw__PS CYREG_PRT15_PS\r
+#define SCSI_Out__DBP_raw__SHIFT 5u\r
+#define SCSI_Out__DBP_raw__SLW CYREG_PRT15_SLW\r
+#define SCSI_Out__IO_raw__AG CYREG_PRT0_AG\r
+#define SCSI_Out__IO_raw__AMUX CYREG_PRT0_AMUX\r
+#define SCSI_Out__IO_raw__BIE CYREG_PRT0_BIE\r
+#define SCSI_Out__IO_raw__BIT_MASK CYREG_PRT0_BIT_MASK\r
+#define SCSI_Out__IO_raw__BYP CYREG_PRT0_BYP\r
+#define SCSI_Out__IO_raw__CTL CYREG_PRT0_CTL\r
+#define SCSI_Out__IO_raw__DM0 CYREG_PRT0_DM0\r
+#define SCSI_Out__IO_raw__DM1 CYREG_PRT0_DM1\r
+#define SCSI_Out__IO_raw__DM2 CYREG_PRT0_DM2\r
+#define SCSI_Out__IO_raw__DR CYREG_PRT0_DR\r
+#define SCSI_Out__IO_raw__INP_DIS CYREG_PRT0_INP_DIS\r
+#define SCSI_Out__IO_raw__INTTYPE CYREG_PICU0_INTTYPE2\r
+#define SCSI_Out__IO_raw__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG\r
+#define SCSI_Out__IO_raw__LCD_EN CYREG_PRT0_LCD_EN\r
+#define SCSI_Out__IO_raw__MASK 0x04u\r
+#define SCSI_Out__IO_raw__PC CYREG_PRT0_PC2\r
+#define SCSI_Out__IO_raw__PORT 0u\r
+#define SCSI_Out__IO_raw__PRT CYREG_PRT0_PRT\r
+#define SCSI_Out__IO_raw__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL\r
+#define SCSI_Out__IO_raw__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN\r
+#define SCSI_Out__IO_raw__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0\r
+#define SCSI_Out__IO_raw__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1\r
+#define SCSI_Out__IO_raw__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0\r
+#define SCSI_Out__IO_raw__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1\r
+#define SCSI_Out__IO_raw__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT\r
+#define SCSI_Out__IO_raw__PS CYREG_PRT0_PS\r
+#define SCSI_Out__IO_raw__SHIFT 2u\r
+#define SCSI_Out__IO_raw__SLW CYREG_PRT0_SLW\r
+#define SCSI_Out__MSG_raw__AG CYREG_PRT4_AG\r
+#define SCSI_Out__MSG_raw__AMUX CYREG_PRT4_AMUX\r
+#define SCSI_Out__MSG_raw__BIE CYREG_PRT4_BIE\r
+#define SCSI_Out__MSG_raw__BIT_MASK CYREG_PRT4_BIT_MASK\r
+#define SCSI_Out__MSG_raw__BYP CYREG_PRT4_BYP\r
+#define SCSI_Out__MSG_raw__CTL CYREG_PRT4_CTL\r
+#define SCSI_Out__MSG_raw__DM0 CYREG_PRT4_DM0\r
+#define SCSI_Out__MSG_raw__DM1 CYREG_PRT4_DM1\r
+#define SCSI_Out__MSG_raw__DM2 CYREG_PRT4_DM2\r
+#define SCSI_Out__MSG_raw__DR CYREG_PRT4_DR\r
+#define SCSI_Out__MSG_raw__INP_DIS CYREG_PRT4_INP_DIS\r
+#define SCSI_Out__MSG_raw__INTTYPE CYREG_PICU4_INTTYPE4\r
+#define SCSI_Out__MSG_raw__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG\r
+#define SCSI_Out__MSG_raw__LCD_EN CYREG_PRT4_LCD_EN\r
+#define SCSI_Out__MSG_raw__MASK 0x10u\r
+#define SCSI_Out__MSG_raw__PC CYREG_PRT4_PC4\r
+#define SCSI_Out__MSG_raw__PORT 4u\r
+#define SCSI_Out__MSG_raw__PRT CYREG_PRT4_PRT\r
+#define SCSI_Out__MSG_raw__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL\r
+#define SCSI_Out__MSG_raw__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN\r
+#define SCSI_Out__MSG_raw__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0\r
+#define SCSI_Out__MSG_raw__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1\r
+#define SCSI_Out__MSG_raw__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0\r
+#define SCSI_Out__MSG_raw__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1\r
+#define SCSI_Out__MSG_raw__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT\r
+#define SCSI_Out__MSG_raw__PS CYREG_PRT4_PS\r
+#define SCSI_Out__MSG_raw__SHIFT 4u\r
+#define SCSI_Out__MSG_raw__SLW CYREG_PRT4_SLW\r
+#define SCSI_Out__REQ__AG CYREG_PRT0_AG\r
+#define SCSI_Out__REQ__AMUX CYREG_PRT0_AMUX\r
+#define SCSI_Out__REQ__BIE CYREG_PRT0_BIE\r
+#define SCSI_Out__REQ__BIT_MASK CYREG_PRT0_BIT_MASK\r
+#define SCSI_Out__REQ__BYP CYREG_PRT0_BYP\r
+#define SCSI_Out__REQ__CTL CYREG_PRT0_CTL\r
+#define SCSI_Out__REQ__DM0 CYREG_PRT0_DM0\r
+#define SCSI_Out__REQ__DM1 CYREG_PRT0_DM1\r
+#define SCSI_Out__REQ__DM2 CYREG_PRT0_DM2\r
+#define SCSI_Out__REQ__DR CYREG_PRT0_DR\r
+#define SCSI_Out__REQ__INP_DIS CYREG_PRT0_INP_DIS\r
+#define SCSI_Out__REQ__INTTYPE CYREG_PICU0_INTTYPE3\r
+#define SCSI_Out__REQ__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG\r
+#define SCSI_Out__REQ__LCD_EN CYREG_PRT0_LCD_EN\r
+#define SCSI_Out__REQ__MASK 0x08u\r
+#define SCSI_Out__REQ__PC CYREG_PRT0_PC3\r
+#define SCSI_Out__REQ__PORT 0u\r
+#define SCSI_Out__REQ__PRT CYREG_PRT0_PRT\r
+#define SCSI_Out__REQ__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL\r
+#define SCSI_Out__REQ__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN\r
+#define SCSI_Out__REQ__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0\r
+#define SCSI_Out__REQ__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1\r
+#define SCSI_Out__REQ__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0\r
+#define SCSI_Out__REQ__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1\r
+#define SCSI_Out__REQ__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT\r
+#define SCSI_Out__REQ__PS CYREG_PRT0_PS\r
+#define SCSI_Out__REQ__SHIFT 3u\r
+#define SCSI_Out__REQ__SLW CYREG_PRT0_SLW\r
+#define SCSI_Out__RST__AG CYREG_PRT4_AG\r
+#define SCSI_Out__RST__AMUX CYREG_PRT4_AMUX\r
+#define SCSI_Out__RST__BIE CYREG_PRT4_BIE\r
+#define SCSI_Out__RST__BIT_MASK CYREG_PRT4_BIT_MASK\r
+#define SCSI_Out__RST__BYP CYREG_PRT4_BYP\r
+#define SCSI_Out__RST__CTL CYREG_PRT4_CTL\r
+#define SCSI_Out__RST__DM0 CYREG_PRT4_DM0\r
+#define SCSI_Out__RST__DM1 CYREG_PRT4_DM1\r
+#define SCSI_Out__RST__DM2 CYREG_PRT4_DM2\r
+#define SCSI_Out__RST__DR CYREG_PRT4_DR\r
+#define SCSI_Out__RST__INP_DIS CYREG_PRT4_INP_DIS\r
+#define SCSI_Out__RST__INTTYPE CYREG_PICU4_INTTYPE5\r
+#define SCSI_Out__RST__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG\r
+#define SCSI_Out__RST__LCD_EN CYREG_PRT4_LCD_EN\r
+#define SCSI_Out__RST__MASK 0x20u\r
+#define SCSI_Out__RST__PC CYREG_PRT4_PC5\r
+#define SCSI_Out__RST__PORT 4u\r
+#define SCSI_Out__RST__PRT CYREG_PRT4_PRT\r
+#define SCSI_Out__RST__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL\r
+#define SCSI_Out__RST__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN\r
+#define SCSI_Out__RST__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0\r
+#define SCSI_Out__RST__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1\r
+#define SCSI_Out__RST__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0\r
+#define SCSI_Out__RST__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1\r
+#define SCSI_Out__RST__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT\r
+#define SCSI_Out__RST__PS CYREG_PRT4_PS\r
+#define SCSI_Out__RST__SHIFT 5u\r
+#define SCSI_Out__RST__SLW CYREG_PRT4_SLW\r
+#define SCSI_Out__SEL__AG CYREG_PRT0_AG\r
+#define SCSI_Out__SEL__AMUX CYREG_PRT0_AMUX\r
+#define SCSI_Out__SEL__BIE CYREG_PRT0_BIE\r
+#define SCSI_Out__SEL__BIT_MASK CYREG_PRT0_BIT_MASK\r
+#define SCSI_Out__SEL__BYP CYREG_PRT0_BYP\r
+#define SCSI_Out__SEL__CTL CYREG_PRT0_CTL\r
+#define SCSI_Out__SEL__DM0 CYREG_PRT0_DM0\r
+#define SCSI_Out__SEL__DM1 CYREG_PRT0_DM1\r
+#define SCSI_Out__SEL__DM2 CYREG_PRT0_DM2\r
+#define SCSI_Out__SEL__DR CYREG_PRT0_DR\r
+#define SCSI_Out__SEL__INP_DIS CYREG_PRT0_INP_DIS\r
+#define SCSI_Out__SEL__INTTYPE CYREG_PICU0_INTTYPE7\r
+#define SCSI_Out__SEL__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG\r
+#define SCSI_Out__SEL__LCD_EN CYREG_PRT0_LCD_EN\r
+#define SCSI_Out__SEL__MASK 0x80u\r
+#define SCSI_Out__SEL__PC CYREG_PRT0_PC7\r
+#define SCSI_Out__SEL__PORT 0u\r
+#define SCSI_Out__SEL__PRT CYREG_PRT0_PRT\r
+#define SCSI_Out__SEL__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL\r
+#define SCSI_Out__SEL__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN\r
+#define SCSI_Out__SEL__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0\r
+#define SCSI_Out__SEL__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1\r
+#define SCSI_Out__SEL__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0\r
+#define SCSI_Out__SEL__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1\r
+#define SCSI_Out__SEL__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT\r
+#define SCSI_Out__SEL__PS CYREG_PRT0_PS\r
+#define SCSI_Out__SEL__SHIFT 7u\r
+#define SCSI_Out__SEL__SLW CYREG_PRT0_SLW\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__0__MASK 0x01u\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__0__POS 0\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__1__MASK 0x02u\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__1__POS 1\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB14_15_ACTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB14_15_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB14_15_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB14_15_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB14_15_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB14_15_MSK\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB14_15_MSK\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB14_15_MSK\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB14_15_MSK\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__2__MASK 0x04u\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__2__POS 2\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__3__MASK 0x08u\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__3__POS 3\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__4__MASK 0x10u\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__4__POS 4\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__5__MASK 0x20u\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__5__POS 5\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__6__MASK 0x40u\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__6__POS 6\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__7__MASK 0x80u\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__7__POS 7\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB14_ACTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB14_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB14_ST_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB14_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB14_ST_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__MASK 0xFFu\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB14_MSK_ACTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB14_MSK_ACTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB14_MSK\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK 0x01u\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__0__POS 0\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB12_13_ACTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB12_13_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB12_13_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB12_13_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB12_13_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB12_13_MSK\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB12_13_MSK\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB12_13_MSK\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB12_13_MSK\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB12_ACTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB12_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB12_ST_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB12_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB12_ST_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK 0x01u\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB12_MSK\r
+#define SCSI_Out_DBx__0__AG CYREG_PRT5_AG\r
+#define SCSI_Out_DBx__0__AMUX CYREG_PRT5_AMUX\r
+#define SCSI_Out_DBx__0__BIE CYREG_PRT5_BIE\r
+#define SCSI_Out_DBx__0__BIT_MASK CYREG_PRT5_BIT_MASK\r
+#define SCSI_Out_DBx__0__BYP CYREG_PRT5_BYP\r
+#define SCSI_Out_DBx__0__CTL CYREG_PRT5_CTL\r
+#define SCSI_Out_DBx__0__DM0 CYREG_PRT5_DM0\r
+#define SCSI_Out_DBx__0__DM1 CYREG_PRT5_DM1\r
+#define SCSI_Out_DBx__0__DM2 CYREG_PRT5_DM2\r
+#define SCSI_Out_DBx__0__DR CYREG_PRT5_DR\r
+#define SCSI_Out_DBx__0__INP_DIS CYREG_PRT5_INP_DIS\r
+#define SCSI_Out_DBx__0__INTTYPE CYREG_PICU5_INTTYPE1\r
+#define SCSI_Out_DBx__0__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG\r
+#define SCSI_Out_DBx__0__LCD_EN CYREG_PRT5_LCD_EN\r
+#define SCSI_Out_DBx__0__MASK 0x02u\r
+#define SCSI_Out_DBx__0__PC CYREG_PRT5_PC1\r
+#define SCSI_Out_DBx__0__PORT 5u\r
+#define SCSI_Out_DBx__0__PRT CYREG_PRT5_PRT\r
+#define SCSI_Out_DBx__0__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL\r
+#define SCSI_Out_DBx__0__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN\r
+#define SCSI_Out_DBx__0__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0\r
+#define SCSI_Out_DBx__0__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1\r
+#define SCSI_Out_DBx__0__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0\r
+#define SCSI_Out_DBx__0__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1\r
+#define SCSI_Out_DBx__0__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT\r
+#define SCSI_Out_DBx__0__PS CYREG_PRT5_PS\r
+#define SCSI_Out_DBx__0__SHIFT 1u\r
+#define SCSI_Out_DBx__0__SLW CYREG_PRT5_SLW\r
+#define SCSI_Out_DBx__1__AG CYREG_PRT5_AG\r
+#define SCSI_Out_DBx__1__AMUX CYREG_PRT5_AMUX\r
+#define SCSI_Out_DBx__1__BIE CYREG_PRT5_BIE\r
+#define SCSI_Out_DBx__1__BIT_MASK CYREG_PRT5_BIT_MASK\r
+#define SCSI_Out_DBx__1__BYP CYREG_PRT5_BYP\r
+#define SCSI_Out_DBx__1__CTL CYREG_PRT5_CTL\r
+#define SCSI_Out_DBx__1__DM0 CYREG_PRT5_DM0\r
+#define SCSI_Out_DBx__1__DM1 CYREG_PRT5_DM1\r
+#define SCSI_Out_DBx__1__DM2 CYREG_PRT5_DM2\r
+#define SCSI_Out_DBx__1__DR CYREG_PRT5_DR\r
+#define SCSI_Out_DBx__1__INP_DIS CYREG_PRT5_INP_DIS\r
+#define SCSI_Out_DBx__1__INTTYPE CYREG_PICU5_INTTYPE0\r
+#define SCSI_Out_DBx__1__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG\r
+#define SCSI_Out_DBx__1__LCD_EN CYREG_PRT5_LCD_EN\r
+#define SCSI_Out_DBx__1__MASK 0x01u\r
+#define SCSI_Out_DBx__1__PC CYREG_PRT5_PC0\r
+#define SCSI_Out_DBx__1__PORT 5u\r
+#define SCSI_Out_DBx__1__PRT CYREG_PRT5_PRT\r
+#define SCSI_Out_DBx__1__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL\r
+#define SCSI_Out_DBx__1__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN\r
+#define SCSI_Out_DBx__1__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0\r
+#define SCSI_Out_DBx__1__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1\r
+#define SCSI_Out_DBx__1__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0\r
+#define SCSI_Out_DBx__1__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1\r
+#define SCSI_Out_DBx__1__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT\r
+#define SCSI_Out_DBx__1__PS CYREG_PRT5_PS\r
+#define SCSI_Out_DBx__1__SHIFT 0u\r
+#define SCSI_Out_DBx__1__SLW CYREG_PRT5_SLW\r
+#define SCSI_Out_DBx__2__AG CYREG_PRT6_AG\r
+#define SCSI_Out_DBx__2__AMUX CYREG_PRT6_AMUX\r
+#define SCSI_Out_DBx__2__BIE CYREG_PRT6_BIE\r
+#define SCSI_Out_DBx__2__BIT_MASK CYREG_PRT6_BIT_MASK\r
+#define SCSI_Out_DBx__2__BYP CYREG_PRT6_BYP\r
+#define SCSI_Out_DBx__2__CTL CYREG_PRT6_CTL\r
+#define SCSI_Out_DBx__2__DM0 CYREG_PRT6_DM0\r
+#define SCSI_Out_DBx__2__DM1 CYREG_PRT6_DM1\r
+#define SCSI_Out_DBx__2__DM2 CYREG_PRT6_DM2\r
+#define SCSI_Out_DBx__2__DR CYREG_PRT6_DR\r
+#define SCSI_Out_DBx__2__INP_DIS CYREG_PRT6_INP_DIS\r
+#define SCSI_Out_DBx__2__INTTYPE CYREG_PICU6_INTTYPE5\r
+#define SCSI_Out_DBx__2__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
+#define SCSI_Out_DBx__2__LCD_EN CYREG_PRT6_LCD_EN\r
+#define SCSI_Out_DBx__2__MASK 0x20u\r
+#define SCSI_Out_DBx__2__PC CYREG_PRT6_PC5\r
+#define SCSI_Out_DBx__2__PORT 6u\r
+#define SCSI_Out_DBx__2__PRT CYREG_PRT6_PRT\r
+#define SCSI_Out_DBx__2__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
+#define SCSI_Out_DBx__2__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
+#define SCSI_Out_DBx__2__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
+#define SCSI_Out_DBx__2__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
+#define SCSI_Out_DBx__2__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
+#define SCSI_Out_DBx__2__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
+#define SCSI_Out_DBx__2__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
+#define SCSI_Out_DBx__2__PS CYREG_PRT6_PS\r
+#define SCSI_Out_DBx__2__SHIFT 5u\r
+#define SCSI_Out_DBx__2__SLW CYREG_PRT6_SLW\r
+#define SCSI_Out_DBx__3__AG CYREG_PRT6_AG\r
+#define SCSI_Out_DBx__3__AMUX CYREG_PRT6_AMUX\r
+#define SCSI_Out_DBx__3__BIE CYREG_PRT6_BIE\r
+#define SCSI_Out_DBx__3__BIT_MASK CYREG_PRT6_BIT_MASK\r
+#define SCSI_Out_DBx__3__BYP CYREG_PRT6_BYP\r
+#define SCSI_Out_DBx__3__CTL CYREG_PRT6_CTL\r
+#define SCSI_Out_DBx__3__DM0 CYREG_PRT6_DM0\r
+#define SCSI_Out_DBx__3__DM1 CYREG_PRT6_DM1\r
+#define SCSI_Out_DBx__3__DM2 CYREG_PRT6_DM2\r
+#define SCSI_Out_DBx__3__DR CYREG_PRT6_DR\r
+#define SCSI_Out_DBx__3__INP_DIS CYREG_PRT6_INP_DIS\r
+#define SCSI_Out_DBx__3__INTTYPE CYREG_PICU6_INTTYPE4\r
+#define SCSI_Out_DBx__3__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
+#define SCSI_Out_DBx__3__LCD_EN CYREG_PRT6_LCD_EN\r
+#define SCSI_Out_DBx__3__MASK 0x10u\r
+#define SCSI_Out_DBx__3__PC CYREG_PRT6_PC4\r
+#define SCSI_Out_DBx__3__PORT 6u\r
+#define SCSI_Out_DBx__3__PRT CYREG_PRT6_PRT\r
+#define SCSI_Out_DBx__3__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
+#define SCSI_Out_DBx__3__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
+#define SCSI_Out_DBx__3__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
+#define SCSI_Out_DBx__3__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
+#define SCSI_Out_DBx__3__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
+#define SCSI_Out_DBx__3__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
+#define SCSI_Out_DBx__3__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
+#define SCSI_Out_DBx__3__PS CYREG_PRT6_PS\r
+#define SCSI_Out_DBx__3__SHIFT 4u\r
+#define SCSI_Out_DBx__3__SLW CYREG_PRT6_SLW\r
+#define SCSI_Out_DBx__4__AG CYREG_PRT2_AG\r
+#define SCSI_Out_DBx__4__AMUX CYREG_PRT2_AMUX\r
+#define SCSI_Out_DBx__4__BIE CYREG_PRT2_BIE\r
+#define SCSI_Out_DBx__4__BIT_MASK CYREG_PRT2_BIT_MASK\r
+#define SCSI_Out_DBx__4__BYP CYREG_PRT2_BYP\r
+#define SCSI_Out_DBx__4__CTL CYREG_PRT2_CTL\r
+#define SCSI_Out_DBx__4__DM0 CYREG_PRT2_DM0\r
+#define SCSI_Out_DBx__4__DM1 CYREG_PRT2_DM1\r
+#define SCSI_Out_DBx__4__DM2 CYREG_PRT2_DM2\r
+#define SCSI_Out_DBx__4__DR CYREG_PRT2_DR\r
+#define SCSI_Out_DBx__4__INP_DIS CYREG_PRT2_INP_DIS\r
+#define SCSI_Out_DBx__4__INTTYPE CYREG_PICU2_INTTYPE7\r
+#define SCSI_Out_DBx__4__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG\r
+#define SCSI_Out_DBx__4__LCD_EN CYREG_PRT2_LCD_EN\r
+#define SCSI_Out_DBx__4__MASK 0x80u\r
+#define SCSI_Out_DBx__4__PC CYREG_PRT2_PC7\r
+#define SCSI_Out_DBx__4__PORT 2u\r
+#define SCSI_Out_DBx__4__PRT CYREG_PRT2_PRT\r
+#define SCSI_Out_DBx__4__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL\r
+#define SCSI_Out_DBx__4__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN\r
+#define SCSI_Out_DBx__4__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0\r
+#define SCSI_Out_DBx__4__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1\r
+#define SCSI_Out_DBx__4__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0\r
+#define SCSI_Out_DBx__4__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1\r
+#define SCSI_Out_DBx__4__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT\r
+#define SCSI_Out_DBx__4__PS CYREG_PRT2_PS\r
+#define SCSI_Out_DBx__4__SHIFT 7u\r
+#define SCSI_Out_DBx__4__SLW CYREG_PRT2_SLW\r
+#define SCSI_Out_DBx__5__AG CYREG_PRT2_AG\r
+#define SCSI_Out_DBx__5__AMUX CYREG_PRT2_AMUX\r
+#define SCSI_Out_DBx__5__BIE CYREG_PRT2_BIE\r
+#define SCSI_Out_DBx__5__BIT_MASK CYREG_PRT2_BIT_MASK\r
+#define SCSI_Out_DBx__5__BYP CYREG_PRT2_BYP\r
+#define SCSI_Out_DBx__5__CTL CYREG_PRT2_CTL\r
+#define SCSI_Out_DBx__5__DM0 CYREG_PRT2_DM0\r
+#define SCSI_Out_DBx__5__DM1 CYREG_PRT2_DM1\r
+#define SCSI_Out_DBx__5__DM2 CYREG_PRT2_DM2\r
+#define SCSI_Out_DBx__5__DR CYREG_PRT2_DR\r
+#define SCSI_Out_DBx__5__INP_DIS CYREG_PRT2_INP_DIS\r
+#define SCSI_Out_DBx__5__INTTYPE CYREG_PICU2_INTTYPE6\r
+#define SCSI_Out_DBx__5__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG\r
+#define SCSI_Out_DBx__5__LCD_EN CYREG_PRT2_LCD_EN\r
+#define SCSI_Out_DBx__5__MASK 0x40u\r
+#define SCSI_Out_DBx__5__PC CYREG_PRT2_PC6\r
+#define SCSI_Out_DBx__5__PORT 2u\r
+#define SCSI_Out_DBx__5__PRT CYREG_PRT2_PRT\r
+#define SCSI_Out_DBx__5__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL\r
+#define SCSI_Out_DBx__5__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN\r
+#define SCSI_Out_DBx__5__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0\r
+#define SCSI_Out_DBx__5__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1\r
+#define SCSI_Out_DBx__5__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0\r
+#define SCSI_Out_DBx__5__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1\r
+#define SCSI_Out_DBx__5__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT\r
+#define SCSI_Out_DBx__5__PS CYREG_PRT2_PS\r
+#define SCSI_Out_DBx__5__SHIFT 6u\r
+#define SCSI_Out_DBx__5__SLW CYREG_PRT2_SLW\r
+#define SCSI_Out_DBx__6__AG CYREG_PRT2_AG\r
+#define SCSI_Out_DBx__6__AMUX CYREG_PRT2_AMUX\r
+#define SCSI_Out_DBx__6__BIE CYREG_PRT2_BIE\r
+#define SCSI_Out_DBx__6__BIT_MASK CYREG_PRT2_BIT_MASK\r
+#define SCSI_Out_DBx__6__BYP CYREG_PRT2_BYP\r
+#define SCSI_Out_DBx__6__CTL CYREG_PRT2_CTL\r
+#define SCSI_Out_DBx__6__DM0 CYREG_PRT2_DM0\r
+#define SCSI_Out_DBx__6__DM1 CYREG_PRT2_DM1\r
+#define SCSI_Out_DBx__6__DM2 CYREG_PRT2_DM2\r
+#define SCSI_Out_DBx__6__DR CYREG_PRT2_DR\r
+#define SCSI_Out_DBx__6__INP_DIS CYREG_PRT2_INP_DIS\r
+#define SCSI_Out_DBx__6__INTTYPE CYREG_PICU2_INTTYPE3\r
+#define SCSI_Out_DBx__6__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG\r
+#define SCSI_Out_DBx__6__LCD_EN CYREG_PRT2_LCD_EN\r
+#define SCSI_Out_DBx__6__MASK 0x08u\r
+#define SCSI_Out_DBx__6__PC CYREG_PRT2_PC3\r
+#define SCSI_Out_DBx__6__PORT 2u\r
+#define SCSI_Out_DBx__6__PRT CYREG_PRT2_PRT\r
+#define SCSI_Out_DBx__6__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL\r
+#define SCSI_Out_DBx__6__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN\r
+#define SCSI_Out_DBx__6__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0\r
+#define SCSI_Out_DBx__6__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1\r
+#define SCSI_Out_DBx__6__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0\r
+#define SCSI_Out_DBx__6__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1\r
+#define SCSI_Out_DBx__6__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT\r
+#define SCSI_Out_DBx__6__PS CYREG_PRT2_PS\r
+#define SCSI_Out_DBx__6__SHIFT 3u\r
+#define SCSI_Out_DBx__6__SLW CYREG_PRT2_SLW\r
+#define SCSI_Out_DBx__7__AG CYREG_PRT2_AG\r
+#define SCSI_Out_DBx__7__AMUX CYREG_PRT2_AMUX\r
+#define SCSI_Out_DBx__7__BIE CYREG_PRT2_BIE\r
+#define SCSI_Out_DBx__7__BIT_MASK CYREG_PRT2_BIT_MASK\r
+#define SCSI_Out_DBx__7__BYP CYREG_PRT2_BYP\r
+#define SCSI_Out_DBx__7__CTL CYREG_PRT2_CTL\r
+#define SCSI_Out_DBx__7__DM0 CYREG_PRT2_DM0\r
+#define SCSI_Out_DBx__7__DM1 CYREG_PRT2_DM1\r
+#define SCSI_Out_DBx__7__DM2 CYREG_PRT2_DM2\r
+#define SCSI_Out_DBx__7__DR CYREG_PRT2_DR\r
+#define SCSI_Out_DBx__7__INP_DIS CYREG_PRT2_INP_DIS\r
+#define SCSI_Out_DBx__7__INTTYPE CYREG_PICU2_INTTYPE2\r
+#define SCSI_Out_DBx__7__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG\r
+#define SCSI_Out_DBx__7__LCD_EN CYREG_PRT2_LCD_EN\r
+#define SCSI_Out_DBx__7__MASK 0x04u\r
+#define SCSI_Out_DBx__7__PC CYREG_PRT2_PC2\r
+#define SCSI_Out_DBx__7__PORT 2u\r
+#define SCSI_Out_DBx__7__PRT CYREG_PRT2_PRT\r
+#define SCSI_Out_DBx__7__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL\r
+#define SCSI_Out_DBx__7__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN\r
+#define SCSI_Out_DBx__7__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0\r
+#define SCSI_Out_DBx__7__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1\r
+#define SCSI_Out_DBx__7__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0\r
+#define SCSI_Out_DBx__7__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1\r
+#define SCSI_Out_DBx__7__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT\r
+#define SCSI_Out_DBx__7__PS CYREG_PRT2_PS\r
+#define SCSI_Out_DBx__7__SHIFT 2u\r
+#define SCSI_Out_DBx__7__SLW CYREG_PRT2_SLW\r
+#define SCSI_Out_DBx__DB0__AG CYREG_PRT5_AG\r
+#define SCSI_Out_DBx__DB0__AMUX CYREG_PRT5_AMUX\r
+#define SCSI_Out_DBx__DB0__BIE CYREG_PRT5_BIE\r
+#define SCSI_Out_DBx__DB0__BIT_MASK CYREG_PRT5_BIT_MASK\r
+#define SCSI_Out_DBx__DB0__BYP CYREG_PRT5_BYP\r
+#define SCSI_Out_DBx__DB0__CTL CYREG_PRT5_CTL\r
+#define SCSI_Out_DBx__DB0__DM0 CYREG_PRT5_DM0\r
+#define SCSI_Out_DBx__DB0__DM1 CYREG_PRT5_DM1\r
+#define SCSI_Out_DBx__DB0__DM2 CYREG_PRT5_DM2\r
+#define SCSI_Out_DBx__DB0__DR CYREG_PRT5_DR\r
+#define SCSI_Out_DBx__DB0__INP_DIS CYREG_PRT5_INP_DIS\r
+#define SCSI_Out_DBx__DB0__INTTYPE CYREG_PICU5_INTTYPE1\r
+#define SCSI_Out_DBx__DB0__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG\r
+#define SCSI_Out_DBx__DB0__LCD_EN CYREG_PRT5_LCD_EN\r
+#define SCSI_Out_DBx__DB0__MASK 0x02u\r
+#define SCSI_Out_DBx__DB0__PC CYREG_PRT5_PC1\r
+#define SCSI_Out_DBx__DB0__PORT 5u\r
+#define SCSI_Out_DBx__DB0__PRT CYREG_PRT5_PRT\r
+#define SCSI_Out_DBx__DB0__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL\r
+#define SCSI_Out_DBx__DB0__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN\r
+#define SCSI_Out_DBx__DB0__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0\r
+#define SCSI_Out_DBx__DB0__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1\r
+#define SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0\r
+#define SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1\r
+#define SCSI_Out_DBx__DB0__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT\r
+#define SCSI_Out_DBx__DB0__PS CYREG_PRT5_PS\r
+#define SCSI_Out_DBx__DB0__SHIFT 1u\r
+#define SCSI_Out_DBx__DB0__SLW CYREG_PRT5_SLW\r
+#define SCSI_Out_DBx__DB1__AG CYREG_PRT5_AG\r
+#define SCSI_Out_DBx__DB1__AMUX CYREG_PRT5_AMUX\r
+#define SCSI_Out_DBx__DB1__BIE CYREG_PRT5_BIE\r
+#define SCSI_Out_DBx__DB1__BIT_MASK CYREG_PRT5_BIT_MASK\r
+#define SCSI_Out_DBx__DB1__BYP CYREG_PRT5_BYP\r
+#define SCSI_Out_DBx__DB1__CTL CYREG_PRT5_CTL\r
+#define SCSI_Out_DBx__DB1__DM0 CYREG_PRT5_DM0\r
+#define SCSI_Out_DBx__DB1__DM1 CYREG_PRT5_DM1\r
+#define SCSI_Out_DBx__DB1__DM2 CYREG_PRT5_DM2\r
+#define SCSI_Out_DBx__DB1__DR CYREG_PRT5_DR\r
+#define SCSI_Out_DBx__DB1__INP_DIS CYREG_PRT5_INP_DIS\r
+#define SCSI_Out_DBx__DB1__INTTYPE CYREG_PICU5_INTTYPE0\r
+#define SCSI_Out_DBx__DB1__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG\r
+#define SCSI_Out_DBx__DB1__LCD_EN CYREG_PRT5_LCD_EN\r
+#define SCSI_Out_DBx__DB1__MASK 0x01u\r
+#define SCSI_Out_DBx__DB1__PC CYREG_PRT5_PC0\r
+#define SCSI_Out_DBx__DB1__PORT 5u\r
+#define SCSI_Out_DBx__DB1__PRT CYREG_PRT5_PRT\r
+#define SCSI_Out_DBx__DB1__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL\r
+#define SCSI_Out_DBx__DB1__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN\r
+#define SCSI_Out_DBx__DB1__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0\r
+#define SCSI_Out_DBx__DB1__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1\r
+#define SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0\r
+#define SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1\r
+#define SCSI_Out_DBx__DB1__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT\r
+#define SCSI_Out_DBx__DB1__PS CYREG_PRT5_PS\r
+#define SCSI_Out_DBx__DB1__SHIFT 0u\r
+#define SCSI_Out_DBx__DB1__SLW CYREG_PRT5_SLW\r
+#define SCSI_Out_DBx__DB2__AG CYREG_PRT6_AG\r
+#define SCSI_Out_DBx__DB2__AMUX CYREG_PRT6_AMUX\r
+#define SCSI_Out_DBx__DB2__BIE CYREG_PRT6_BIE\r
+#define SCSI_Out_DBx__DB2__BIT_MASK CYREG_PRT6_BIT_MASK\r
+#define SCSI_Out_DBx__DB2__BYP CYREG_PRT6_BYP\r
+#define SCSI_Out_DBx__DB2__CTL CYREG_PRT6_CTL\r
+#define SCSI_Out_DBx__DB2__DM0 CYREG_PRT6_DM0\r
+#define SCSI_Out_DBx__DB2__DM1 CYREG_PRT6_DM1\r
+#define SCSI_Out_DBx__DB2__DM2 CYREG_PRT6_DM2\r
+#define SCSI_Out_DBx__DB2__DR CYREG_PRT6_DR\r
+#define SCSI_Out_DBx__DB2__INP_DIS CYREG_PRT6_INP_DIS\r
+#define SCSI_Out_DBx__DB2__INTTYPE CYREG_PICU6_INTTYPE5\r
+#define SCSI_Out_DBx__DB2__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
+#define SCSI_Out_DBx__DB2__LCD_EN CYREG_PRT6_LCD_EN\r
+#define SCSI_Out_DBx__DB2__MASK 0x20u\r
+#define SCSI_Out_DBx__DB2__PC CYREG_PRT6_PC5\r
+#define SCSI_Out_DBx__DB2__PORT 6u\r
+#define SCSI_Out_DBx__DB2__PRT CYREG_PRT6_PRT\r
+#define SCSI_Out_DBx__DB2__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
+#define SCSI_Out_DBx__DB2__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
+#define SCSI_Out_DBx__DB2__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
+#define SCSI_Out_DBx__DB2__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
+#define SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
+#define SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
+#define SCSI_Out_DBx__DB2__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
+#define SCSI_Out_DBx__DB2__PS CYREG_PRT6_PS\r
+#define SCSI_Out_DBx__DB2__SHIFT 5u\r
+#define SCSI_Out_DBx__DB2__SLW CYREG_PRT6_SLW\r
+#define SCSI_Out_DBx__DB3__AG CYREG_PRT6_AG\r
+#define SCSI_Out_DBx__DB3__AMUX CYREG_PRT6_AMUX\r
+#define SCSI_Out_DBx__DB3__BIE CYREG_PRT6_BIE\r
+#define SCSI_Out_DBx__DB3__BIT_MASK CYREG_PRT6_BIT_MASK\r
+#define SCSI_Out_DBx__DB3__BYP CYREG_PRT6_BYP\r
+#define SCSI_Out_DBx__DB3__CTL CYREG_PRT6_CTL\r
+#define SCSI_Out_DBx__DB3__DM0 CYREG_PRT6_DM0\r
+#define SCSI_Out_DBx__DB3__DM1 CYREG_PRT6_DM1\r
+#define SCSI_Out_DBx__DB3__DM2 CYREG_PRT6_DM2\r
+#define SCSI_Out_DBx__DB3__DR CYREG_PRT6_DR\r
+#define SCSI_Out_DBx__DB3__INP_DIS CYREG_PRT6_INP_DIS\r
+#define SCSI_Out_DBx__DB3__INTTYPE CYREG_PICU6_INTTYPE4\r
+#define SCSI_Out_DBx__DB3__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
+#define SCSI_Out_DBx__DB3__LCD_EN CYREG_PRT6_LCD_EN\r
+#define SCSI_Out_DBx__DB3__MASK 0x10u\r
+#define SCSI_Out_DBx__DB3__PC CYREG_PRT6_PC4\r
+#define SCSI_Out_DBx__DB3__PORT 6u\r
+#define SCSI_Out_DBx__DB3__PRT CYREG_PRT6_PRT\r
+#define SCSI_Out_DBx__DB3__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
+#define SCSI_Out_DBx__DB3__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
+#define SCSI_Out_DBx__DB3__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
+#define SCSI_Out_DBx__DB3__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
+#define SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
+#define SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
+#define SCSI_Out_DBx__DB3__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
+#define SCSI_Out_DBx__DB3__PS CYREG_PRT6_PS\r
+#define SCSI_Out_DBx__DB3__SHIFT 4u\r
+#define SCSI_Out_DBx__DB3__SLW CYREG_PRT6_SLW\r
+#define SCSI_Out_DBx__DB4__AG CYREG_PRT2_AG\r
+#define SCSI_Out_DBx__DB4__AMUX CYREG_PRT2_AMUX\r
+#define SCSI_Out_DBx__DB4__BIE CYREG_PRT2_BIE\r
+#define SCSI_Out_DBx__DB4__BIT_MASK CYREG_PRT2_BIT_MASK\r
+#define SCSI_Out_DBx__DB4__BYP CYREG_PRT2_BYP\r
+#define SCSI_Out_DBx__DB4__CTL CYREG_PRT2_CTL\r
+#define SCSI_Out_DBx__DB4__DM0 CYREG_PRT2_DM0\r
+#define SCSI_Out_DBx__DB4__DM1 CYREG_PRT2_DM1\r
+#define SCSI_Out_DBx__DB4__DM2 CYREG_PRT2_DM2\r
+#define SCSI_Out_DBx__DB4__DR CYREG_PRT2_DR\r
+#define SCSI_Out_DBx__DB4__INP_DIS CYREG_PRT2_INP_DIS\r
+#define SCSI_Out_DBx__DB4__INTTYPE CYREG_PICU2_INTTYPE7\r
+#define SCSI_Out_DBx__DB4__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG\r
+#define SCSI_Out_DBx__DB4__LCD_EN CYREG_PRT2_LCD_EN\r
+#define SCSI_Out_DBx__DB4__MASK 0x80u\r
+#define SCSI_Out_DBx__DB4__PC CYREG_PRT2_PC7\r
+#define SCSI_Out_DBx__DB4__PORT 2u\r
+#define SCSI_Out_DBx__DB4__PRT CYREG_PRT2_PRT\r
+#define SCSI_Out_DBx__DB4__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL\r
+#define SCSI_Out_DBx__DB4__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN\r
+#define SCSI_Out_DBx__DB4__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0\r
+#define SCSI_Out_DBx__DB4__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1\r
+#define SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0\r
+#define SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1\r
+#define SCSI_Out_DBx__DB4__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT\r
+#define SCSI_Out_DBx__DB4__PS CYREG_PRT2_PS\r
+#define SCSI_Out_DBx__DB4__SHIFT 7u\r
+#define SCSI_Out_DBx__DB4__SLW CYREG_PRT2_SLW\r
+#define SCSI_Out_DBx__DB5__AG CYREG_PRT2_AG\r
+#define SCSI_Out_DBx__DB5__AMUX CYREG_PRT2_AMUX\r
+#define SCSI_Out_DBx__DB5__BIE CYREG_PRT2_BIE\r
+#define SCSI_Out_DBx__DB5__BIT_MASK CYREG_PRT2_BIT_MASK\r
+#define SCSI_Out_DBx__DB5__BYP CYREG_PRT2_BYP\r
+#define SCSI_Out_DBx__DB5__CTL CYREG_PRT2_CTL\r
+#define SCSI_Out_DBx__DB5__DM0 CYREG_PRT2_DM0\r
+#define SCSI_Out_DBx__DB5__DM1 CYREG_PRT2_DM1\r
+#define SCSI_Out_DBx__DB5__DM2 CYREG_PRT2_DM2\r
+#define SCSI_Out_DBx__DB5__DR CYREG_PRT2_DR\r
+#define SCSI_Out_DBx__DB5__INP_DIS CYREG_PRT2_INP_DIS\r
+#define SCSI_Out_DBx__DB5__INTTYPE CYREG_PICU2_INTTYPE6\r
+#define SCSI_Out_DBx__DB5__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG\r
+#define SCSI_Out_DBx__DB5__LCD_EN CYREG_PRT2_LCD_EN\r
+#define SCSI_Out_DBx__DB5__MASK 0x40u\r
+#define SCSI_Out_DBx__DB5__PC CYREG_PRT2_PC6\r
+#define SCSI_Out_DBx__DB5__PORT 2u\r
+#define SCSI_Out_DBx__DB5__PRT CYREG_PRT2_PRT\r
+#define SCSI_Out_DBx__DB5__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL\r
+#define SCSI_Out_DBx__DB5__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN\r
+#define SCSI_Out_DBx__DB5__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0\r
+#define SCSI_Out_DBx__DB5__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1\r
+#define SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0\r
+#define SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1\r
+#define SCSI_Out_DBx__DB5__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT\r
+#define SCSI_Out_DBx__DB5__PS CYREG_PRT2_PS\r
+#define SCSI_Out_DBx__DB5__SHIFT 6u\r
+#define SCSI_Out_DBx__DB5__SLW CYREG_PRT2_SLW\r
+#define SCSI_Out_DBx__DB6__AG CYREG_PRT2_AG\r
+#define SCSI_Out_DBx__DB6__AMUX CYREG_PRT2_AMUX\r
+#define SCSI_Out_DBx__DB6__BIE CYREG_PRT2_BIE\r
+#define SCSI_Out_DBx__DB6__BIT_MASK CYREG_PRT2_BIT_MASK\r
+#define SCSI_Out_DBx__DB6__BYP CYREG_PRT2_BYP\r
+#define SCSI_Out_DBx__DB6__CTL CYREG_PRT2_CTL\r
+#define SCSI_Out_DBx__DB6__DM0 CYREG_PRT2_DM0\r
+#define SCSI_Out_DBx__DB6__DM1 CYREG_PRT2_DM1\r
+#define SCSI_Out_DBx__DB6__DM2 CYREG_PRT2_DM2\r
+#define SCSI_Out_DBx__DB6__DR CYREG_PRT2_DR\r
+#define SCSI_Out_DBx__DB6__INP_DIS CYREG_PRT2_INP_DIS\r
+#define SCSI_Out_DBx__DB6__INTTYPE CYREG_PICU2_INTTYPE3\r
+#define SCSI_Out_DBx__DB6__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG\r
+#define SCSI_Out_DBx__DB6__LCD_EN CYREG_PRT2_LCD_EN\r
+#define SCSI_Out_DBx__DB6__MASK 0x08u\r
+#define SCSI_Out_DBx__DB6__PC CYREG_PRT2_PC3\r
+#define SCSI_Out_DBx__DB6__PORT 2u\r
+#define SCSI_Out_DBx__DB6__PRT CYREG_PRT2_PRT\r
+#define SCSI_Out_DBx__DB6__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL\r
+#define SCSI_Out_DBx__DB6__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN\r
+#define SCSI_Out_DBx__DB6__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0\r
+#define SCSI_Out_DBx__DB6__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1\r
+#define SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0\r
+#define SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1\r
+#define SCSI_Out_DBx__DB6__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT\r
+#define SCSI_Out_DBx__DB6__PS CYREG_PRT2_PS\r
+#define SCSI_Out_DBx__DB6__SHIFT 3u\r
+#define SCSI_Out_DBx__DB6__SLW CYREG_PRT2_SLW\r
+#define SCSI_Out_DBx__DB7__AG CYREG_PRT2_AG\r
+#define SCSI_Out_DBx__DB7__AMUX CYREG_PRT2_AMUX\r
+#define SCSI_Out_DBx__DB7__BIE CYREG_PRT2_BIE\r
+#define SCSI_Out_DBx__DB7__BIT_MASK CYREG_PRT2_BIT_MASK\r
+#define SCSI_Out_DBx__DB7__BYP CYREG_PRT2_BYP\r
+#define SCSI_Out_DBx__DB7__CTL CYREG_PRT2_CTL\r
+#define SCSI_Out_DBx__DB7__DM0 CYREG_PRT2_DM0\r
+#define SCSI_Out_DBx__DB7__DM1 CYREG_PRT2_DM1\r
+#define SCSI_Out_DBx__DB7__DM2 CYREG_PRT2_DM2\r
+#define SCSI_Out_DBx__DB7__DR CYREG_PRT2_DR\r
+#define SCSI_Out_DBx__DB7__INP_DIS CYREG_PRT2_INP_DIS\r
+#define SCSI_Out_DBx__DB7__INTTYPE CYREG_PICU2_INTTYPE2\r
+#define SCSI_Out_DBx__DB7__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG\r
+#define SCSI_Out_DBx__DB7__LCD_EN CYREG_PRT2_LCD_EN\r
+#define SCSI_Out_DBx__DB7__MASK 0x04u\r
+#define SCSI_Out_DBx__DB7__PC CYREG_PRT2_PC2\r
+#define SCSI_Out_DBx__DB7__PORT 2u\r
+#define SCSI_Out_DBx__DB7__PRT CYREG_PRT2_PRT\r
+#define SCSI_Out_DBx__DB7__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL\r
+#define SCSI_Out_DBx__DB7__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN\r
+#define SCSI_Out_DBx__DB7__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0\r
+#define SCSI_Out_DBx__DB7__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1\r
+#define SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0\r
+#define SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1\r
+#define SCSI_Out_DBx__DB7__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT\r
+#define SCSI_Out_DBx__DB7__PS CYREG_PRT2_PS\r
+#define SCSI_Out_DBx__DB7__SHIFT 2u\r
+#define SCSI_Out_DBx__DB7__SLW CYREG_PRT2_SLW\r
+\r
+/* SCSI_Parity_Error */\r
+#define SCSI_Parity_Error_sts_sts_reg__0__MASK 0x01u\r
+#define SCSI_Parity_Error_sts_sts_reg__0__POS 0\r
+#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB05_06_ACTL\r
+#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB05_06_ST\r
+#define SCSI_Parity_Error_sts_sts_reg__MASK 0x01u\r
+#define SCSI_Parity_Error_sts_sts_reg__MASK_REG CYREG_B0_UDB05_MSK\r
+#define SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB05_ACTL\r
+#define SCSI_Parity_Error_sts_sts_reg__STATUS_REG CYREG_B0_UDB05_ST\r
+\r
+/* SCSI_RST_ISR */\r
+#define SCSI_RST_ISR__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
+#define SCSI_RST_ISR__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
+#define SCSI_RST_ISR__INTC_MASK 0x02u\r
+#define SCSI_RST_ISR__INTC_NUMBER 1u\r
+#define SCSI_RST_ISR__INTC_PRIOR_NUM 7u\r
+#define SCSI_RST_ISR__INTC_PRIOR_REG CYREG_NVIC_PRI_1\r
+#define SCSI_RST_ISR__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
+#define SCSI_RST_ISR__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
+\r
+/* SCSI_RX_DMA */\r
+#define SCSI_RX_DMA__DRQ_CTL CYREG_IDMUX_DRQ_CTL0\r
+#define SCSI_RX_DMA__DRQ_NUMBER 0u\r
+#define SCSI_RX_DMA__NUMBEROF_TDS 0u\r
+#define SCSI_RX_DMA__PRIORITY 2u\r
+#define SCSI_RX_DMA__TERMIN_EN 0u\r
+#define SCSI_RX_DMA__TERMIN_SEL 0u\r
+#define SCSI_RX_DMA__TERMOUT0_EN 1u\r
+#define SCSI_RX_DMA__TERMOUT0_SEL 0u\r
+#define SCSI_RX_DMA__TERMOUT1_EN 0u\r
+#define SCSI_RX_DMA__TERMOUT1_SEL 0u\r
+#define SCSI_RX_DMA_COMPLETE__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
+#define SCSI_RX_DMA_COMPLETE__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
+#define SCSI_RX_DMA_COMPLETE__INTC_MASK 0x04u\r
+#define SCSI_RX_DMA_COMPLETE__INTC_NUMBER 2u\r
+#define SCSI_RX_DMA_COMPLETE__INTC_PRIOR_NUM 7u\r
+#define SCSI_RX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_2\r
+#define SCSI_RX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
+#define SCSI_RX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
+\r
+/* SCSI_SEL_ISR */\r
+#define SCSI_SEL_ISR__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
+#define SCSI_SEL_ISR__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
+#define SCSI_SEL_ISR__INTC_MASK 0x08u\r
+#define SCSI_SEL_ISR__INTC_NUMBER 3u\r
+#define SCSI_SEL_ISR__INTC_PRIOR_NUM 7u\r
+#define SCSI_SEL_ISR__INTC_PRIOR_REG CYREG_NVIC_PRI_3\r
+#define SCSI_SEL_ISR__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
+#define SCSI_SEL_ISR__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
+\r
+/* SCSI_TX_DMA */\r
+#define SCSI_TX_DMA__DRQ_CTL CYREG_IDMUX_DRQ_CTL0\r
+#define SCSI_TX_DMA__DRQ_NUMBER 1u\r
+#define SCSI_TX_DMA__NUMBEROF_TDS 0u\r
+#define SCSI_TX_DMA__PRIORITY 2u\r
+#define SCSI_TX_DMA__TERMIN_EN 0u\r
+#define SCSI_TX_DMA__TERMIN_SEL 0u\r
+#define SCSI_TX_DMA__TERMOUT0_EN 1u\r
+#define SCSI_TX_DMA__TERMOUT0_SEL 1u\r
+#define SCSI_TX_DMA__TERMOUT1_EN 0u\r
+#define SCSI_TX_DMA__TERMOUT1_SEL 0u\r
+#define SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
+#define SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
+#define SCSI_TX_DMA_COMPLETE__INTC_MASK 0x10u\r
+#define SCSI_TX_DMA_COMPLETE__INTC_NUMBER 4u\r
+#define SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM 7u\r
+#define SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_4\r
+#define SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
+#define SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
+\r
+/* SDCard_BSPIM */\r
+#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB05_06_ACTL\r
+#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB05_06_CTL\r
+#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB05_06_CTL\r
+#define SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB05_06_CTL\r
+#define SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B1_UDB05_06_CTL\r
+#define SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B1_UDB05_06_MSK\r
+#define SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B1_UDB05_06_MSK\r
+#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B1_UDB05_06_MSK\r
+#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB05_06_MSK\r
+#define SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B1_UDB05_ACTL\r
+#define SDCard_BSPIM_BitCounter__CONTROL_REG CYREG_B1_UDB05_CTL\r
+#define SDCard_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B1_UDB05_ST_CTL\r
+#define SDCard_BSPIM_BitCounter__COUNT_REG CYREG_B1_UDB05_CTL\r
+#define SDCard_BSPIM_BitCounter__COUNT_ST_REG CYREG_B1_UDB05_ST_CTL\r
+#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB05_MSK_ACTL\r
+#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B1_UDB05_MSK_ACTL\r
+#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B1_UDB05_MSK\r
+#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB05_06_ACTL\r
+#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B1_UDB05_06_ST\r
+#define SDCard_BSPIM_BitCounter_ST__MASK_REG CYREG_B1_UDB05_MSK\r
+#define SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B1_UDB05_MSK_ACTL\r
+#define SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B1_UDB05_MSK_ACTL\r
+#define SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B1_UDB05_ACTL\r
+#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B1_UDB05_ST_CTL\r
+#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B1_UDB05_ST_CTL\r
+#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B1_UDB05_ST\r
+#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB07_08_ACTL\r
+#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B1_UDB07_08_ST\r
+#define SDCard_BSPIM_RxStsReg__4__MASK 0x10u\r
+#define SDCard_BSPIM_RxStsReg__4__POS 4\r
+#define SDCard_BSPIM_RxStsReg__5__MASK 0x20u\r
+#define SDCard_BSPIM_RxStsReg__5__POS 5\r
+#define SDCard_BSPIM_RxStsReg__6__MASK 0x40u\r
+#define SDCard_BSPIM_RxStsReg__6__POS 6\r
+#define SDCard_BSPIM_RxStsReg__MASK 0x70u\r
+#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B1_UDB07_MSK\r
+#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB07_ACTL\r
+#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B1_UDB07_ST\r
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B1_UDB04_05_A0\r
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B1_UDB04_05_A1\r
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG CYREG_B1_UDB04_05_D0\r
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG CYREG_B1_UDB04_05_D1\r
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG CYREG_B1_UDB04_05_ACTL\r
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG CYREG_B1_UDB04_05_F0\r
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG CYREG_B1_UDB04_05_F1\r
+#define SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG CYREG_B1_UDB04_A0_A1\r
+#define SDCard_BSPIM_sR8_Dp_u0__A0_REG CYREG_B1_UDB04_A0\r
+#define SDCard_BSPIM_sR8_Dp_u0__A1_REG CYREG_B1_UDB04_A1\r
+#define SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG CYREG_B1_UDB04_D0_D1\r
+#define SDCard_BSPIM_sR8_Dp_u0__D0_REG CYREG_B1_UDB04_D0\r
+#define SDCard_BSPIM_sR8_Dp_u0__D1_REG CYREG_B1_UDB04_D1\r
+#define SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG CYREG_B1_UDB04_ACTL\r
+#define SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG CYREG_B1_UDB04_F0_F1\r
+#define SDCard_BSPIM_sR8_Dp_u0__F0_REG CYREG_B1_UDB04_F0\r
+#define SDCard_BSPIM_sR8_Dp_u0__F1_REG CYREG_B1_UDB04_F1\r
+#define SDCard_BSPIM_TxStsReg__0__MASK 0x01u\r
+#define SDCard_BSPIM_TxStsReg__0__POS 0\r
+#define SDCard_BSPIM_TxStsReg__1__MASK 0x02u\r
+#define SDCard_BSPIM_TxStsReg__1__POS 1\r
+#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB06_07_ACTL\r
+#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B1_UDB06_07_ST\r
+#define SDCard_BSPIM_TxStsReg__2__MASK 0x04u\r
+#define SDCard_BSPIM_TxStsReg__2__POS 2\r
+#define SDCard_BSPIM_TxStsReg__3__MASK 0x08u\r
+#define SDCard_BSPIM_TxStsReg__3__POS 3\r
+#define SDCard_BSPIM_TxStsReg__4__MASK 0x10u\r
+#define SDCard_BSPIM_TxStsReg__4__POS 4\r
+#define SDCard_BSPIM_TxStsReg__MASK 0x1Fu\r
+#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B1_UDB06_MSK\r
+#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB06_ACTL\r
+#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B1_UDB06_ST\r
+\r
+/* SD_CD */\r
+#define SD_CD__0__INTTYPE CYREG_PICU3_INTTYPE5\r
+#define SD_CD__0__MASK 0x20u\r
+#define SD_CD__0__PC CYREG_PRT3_PC5\r
+#define SD_CD__0__PORT 3u\r
+#define SD_CD__0__SHIFT 5u\r
+#define SD_CD__AG CYREG_PRT3_AG\r
+#define SD_CD__AMUX CYREG_PRT3_AMUX\r
+#define SD_CD__BIE CYREG_PRT3_BIE\r
+#define SD_CD__BIT_MASK CYREG_PRT3_BIT_MASK\r
+#define SD_CD__BYP CYREG_PRT3_BYP\r
+#define SD_CD__CTL CYREG_PRT3_CTL\r
+#define SD_CD__DM0 CYREG_PRT3_DM0\r
+#define SD_CD__DM1 CYREG_PRT3_DM1\r
+#define SD_CD__DM2 CYREG_PRT3_DM2\r
+#define SD_CD__DR CYREG_PRT3_DR\r
+#define SD_CD__INP_DIS CYREG_PRT3_INP_DIS\r
+#define SD_CD__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU3_BASE\r
+#define SD_CD__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG\r
+#define SD_CD__LCD_EN CYREG_PRT3_LCD_EN\r
+#define SD_CD__MASK 0x20u\r
+#define SD_CD__PORT 3u\r
+#define SD_CD__PRT CYREG_PRT3_PRT\r
+#define SD_CD__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL\r
+#define SD_CD__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN\r
+#define SD_CD__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0\r
+#define SD_CD__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1\r
+#define SD_CD__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0\r
+#define SD_CD__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1\r
+#define SD_CD__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT\r
+#define SD_CD__PS CYREG_PRT3_PS\r
+#define SD_CD__SHIFT 5u\r
+#define SD_CD__SLW CYREG_PRT3_SLW\r
+\r
+/* SD_CS */\r
+#define SD_CS__0__INTTYPE CYREG_PICU3_INTTYPE4\r
+#define SD_CS__0__MASK 0x10u\r
+#define SD_CS__0__PC CYREG_PRT3_PC4\r
+#define SD_CS__0__PORT 3u\r
+#define SD_CS__0__SHIFT 4u\r
+#define SD_CS__AG CYREG_PRT3_AG\r
+#define SD_CS__AMUX CYREG_PRT3_AMUX\r
+#define SD_CS__BIE CYREG_PRT3_BIE\r
+#define SD_CS__BIT_MASK CYREG_PRT3_BIT_MASK\r
+#define SD_CS__BYP CYREG_PRT3_BYP\r
+#define SD_CS__CTL CYREG_PRT3_CTL\r
+#define SD_CS__DM0 CYREG_PRT3_DM0\r
+#define SD_CS__DM1 CYREG_PRT3_DM1\r
+#define SD_CS__DM2 CYREG_PRT3_DM2\r
+#define SD_CS__DR CYREG_PRT3_DR\r
+#define SD_CS__INP_DIS CYREG_PRT3_INP_DIS\r
+#define SD_CS__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU3_BASE\r
+#define SD_CS__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG\r
+#define SD_CS__LCD_EN CYREG_PRT3_LCD_EN\r
+#define SD_CS__MASK 0x10u\r
+#define SD_CS__PORT 3u\r
+#define SD_CS__PRT CYREG_PRT3_PRT\r
+#define SD_CS__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL\r
+#define SD_CS__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN\r
+#define SD_CS__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0\r
+#define SD_CS__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1\r
+#define SD_CS__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0\r
+#define SD_CS__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1\r
+#define SD_CS__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT\r
+#define SD_CS__PS CYREG_PRT3_PS\r
+#define SD_CS__SHIFT 4u\r
+#define SD_CS__SLW CYREG_PRT3_SLW\r
+\r
+/* SD_Data_Clk */\r
+#define SD_Data_Clk__CFG0 CYREG_CLKDIST_DCFG0_CFG0\r
+#define SD_Data_Clk__CFG1 CYREG_CLKDIST_DCFG0_CFG1\r
+#define SD_Data_Clk__CFG2 CYREG_CLKDIST_DCFG0_CFG2\r
+#define SD_Data_Clk__CFG2_SRC_SEL_MASK 0x07u\r
+#define SD_Data_Clk__INDEX 0x00u\r
+#define SD_Data_Clk__PM_ACT_CFG CYREG_PM_ACT_CFG2\r
+#define SD_Data_Clk__PM_ACT_MSK 0x01u\r
+#define SD_Data_Clk__PM_STBY_CFG CYREG_PM_STBY_CFG2\r
+#define SD_Data_Clk__PM_STBY_MSK 0x01u\r
+\r
+/* SD_MISO */\r
+#define SD_MISO__0__INTTYPE CYREG_PICU3_INTTYPE1\r
+#define SD_MISO__0__MASK 0x02u\r
+#define SD_MISO__0__PC CYREG_PRT3_PC1\r
+#define SD_MISO__0__PORT 3u\r
+#define SD_MISO__0__SHIFT 1u\r
+#define SD_MISO__AG CYREG_PRT3_AG\r
+#define SD_MISO__AMUX CYREG_PRT3_AMUX\r
+#define SD_MISO__BIE CYREG_PRT3_BIE\r
+#define SD_MISO__BIT_MASK CYREG_PRT3_BIT_MASK\r
+#define SD_MISO__BYP CYREG_PRT3_BYP\r
+#define SD_MISO__CTL CYREG_PRT3_CTL\r
+#define SD_MISO__DM0 CYREG_PRT3_DM0\r
+#define SD_MISO__DM1 CYREG_PRT3_DM1\r
+#define SD_MISO__DM2 CYREG_PRT3_DM2\r
+#define SD_MISO__DR CYREG_PRT3_DR\r
+#define SD_MISO__INP_DIS CYREG_PRT3_INP_DIS\r
+#define SD_MISO__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU3_BASE\r
+#define SD_MISO__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG\r
+#define SD_MISO__LCD_EN CYREG_PRT3_LCD_EN\r
+#define SD_MISO__MASK 0x02u\r
+#define SD_MISO__PORT 3u\r
+#define SD_MISO__PRT CYREG_PRT3_PRT\r
+#define SD_MISO__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL\r
+#define SD_MISO__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN\r
+#define SD_MISO__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0\r
+#define SD_MISO__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1\r
+#define SD_MISO__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0\r
+#define SD_MISO__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1\r
+#define SD_MISO__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT\r
+#define SD_MISO__PS CYREG_PRT3_PS\r
+#define SD_MISO__SHIFT 1u\r
+#define SD_MISO__SLW CYREG_PRT3_SLW\r
+\r
+/* SD_MOSI */\r
+#define SD_MOSI__0__INTTYPE CYREG_PICU3_INTTYPE3\r
+#define SD_MOSI__0__MASK 0x08u\r
+#define SD_MOSI__0__PC CYREG_PRT3_PC3\r
+#define SD_MOSI__0__PORT 3u\r
+#define SD_MOSI__0__SHIFT 3u\r
+#define SD_MOSI__AG CYREG_PRT3_AG\r
+#define SD_MOSI__AMUX CYREG_PRT3_AMUX\r
+#define SD_MOSI__BIE CYREG_PRT3_BIE\r
+#define SD_MOSI__BIT_MASK CYREG_PRT3_BIT_MASK\r
+#define SD_MOSI__BYP CYREG_PRT3_BYP\r
+#define SD_MOSI__CTL CYREG_PRT3_CTL\r
+#define SD_MOSI__DM0 CYREG_PRT3_DM0\r
+#define SD_MOSI__DM1 CYREG_PRT3_DM1\r
+#define SD_MOSI__DM2 CYREG_PRT3_DM2\r
+#define SD_MOSI__DR CYREG_PRT3_DR\r
+#define SD_MOSI__INP_DIS CYREG_PRT3_INP_DIS\r
+#define SD_MOSI__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU3_BASE\r
+#define SD_MOSI__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG\r
+#define SD_MOSI__LCD_EN CYREG_PRT3_LCD_EN\r
+#define SD_MOSI__MASK 0x08u\r
+#define SD_MOSI__PORT 3u\r
+#define SD_MOSI__PRT CYREG_PRT3_PRT\r
+#define SD_MOSI__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL\r
+#define SD_MOSI__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN\r
+#define SD_MOSI__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0\r
+#define SD_MOSI__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1\r
+#define SD_MOSI__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0\r
+#define SD_MOSI__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1\r
+#define SD_MOSI__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT\r
+#define SD_MOSI__PS CYREG_PRT3_PS\r
+#define SD_MOSI__SHIFT 3u\r
+#define SD_MOSI__SLW CYREG_PRT3_SLW\r
+\r
+/* SD_RX_DMA */\r
+#define SD_RX_DMA__DRQ_CTL CYREG_IDMUX_DRQ_CTL0\r
+#define SD_RX_DMA__DRQ_NUMBER 2u\r
+#define SD_RX_DMA__NUMBEROF_TDS 0u\r
+#define SD_RX_DMA__PRIORITY 0u\r
+#define SD_RX_DMA__TERMIN_EN 0u\r
+#define SD_RX_DMA__TERMIN_SEL 0u\r
+#define SD_RX_DMA__TERMOUT0_EN 1u\r
+#define SD_RX_DMA__TERMOUT0_SEL 2u\r
+#define SD_RX_DMA__TERMOUT1_EN 0u\r
+#define SD_RX_DMA__TERMOUT1_SEL 0u\r
+#define SD_RX_DMA_COMPLETE__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
+#define SD_RX_DMA_COMPLETE__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
+#define SD_RX_DMA_COMPLETE__INTC_MASK 0x20u\r
+#define SD_RX_DMA_COMPLETE__INTC_NUMBER 5u\r
+#define SD_RX_DMA_COMPLETE__INTC_PRIOR_NUM 7u\r
+#define SD_RX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_5\r
+#define SD_RX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
+#define SD_RX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
+\r
+/* SD_SCK */\r
+#define SD_SCK__0__INTTYPE CYREG_PICU3_INTTYPE2\r
+#define SD_SCK__0__MASK 0x04u\r
+#define SD_SCK__0__PC CYREG_PRT3_PC2\r
+#define SD_SCK__0__PORT 3u\r
+#define SD_SCK__0__SHIFT 2u\r
+#define SD_SCK__AG CYREG_PRT3_AG\r
+#define SD_SCK__AMUX CYREG_PRT3_AMUX\r
+#define SD_SCK__BIE CYREG_PRT3_BIE\r
+#define SD_SCK__BIT_MASK CYREG_PRT3_BIT_MASK\r
+#define SD_SCK__BYP CYREG_PRT3_BYP\r
+#define SD_SCK__CTL CYREG_PRT3_CTL\r
+#define SD_SCK__DM0 CYREG_PRT3_DM0\r
+#define SD_SCK__DM1 CYREG_PRT3_DM1\r
+#define SD_SCK__DM2 CYREG_PRT3_DM2\r
+#define SD_SCK__DR CYREG_PRT3_DR\r
+#define SD_SCK__INP_DIS CYREG_PRT3_INP_DIS\r
+#define SD_SCK__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU3_BASE\r
+#define SD_SCK__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG\r
+#define SD_SCK__LCD_EN CYREG_PRT3_LCD_EN\r
+#define SD_SCK__MASK 0x04u\r
+#define SD_SCK__PORT 3u\r
+#define SD_SCK__PRT CYREG_PRT3_PRT\r
+#define SD_SCK__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL\r
+#define SD_SCK__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN\r
+#define SD_SCK__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0\r
+#define SD_SCK__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1\r
+#define SD_SCK__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0\r
+#define SD_SCK__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1\r
+#define SD_SCK__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT\r
+#define SD_SCK__PS CYREG_PRT3_PS\r
+#define SD_SCK__SHIFT 2u\r
+#define SD_SCK__SLW CYREG_PRT3_SLW\r
+\r
+/* SD_TX_DMA */\r
+#define SD_TX_DMA__DRQ_CTL CYREG_IDMUX_DRQ_CTL0\r
+#define SD_TX_DMA__DRQ_NUMBER 3u\r
+#define SD_TX_DMA__NUMBEROF_TDS 0u\r
+#define SD_TX_DMA__PRIORITY 1u\r
+#define SD_TX_DMA__TERMIN_EN 0u\r
+#define SD_TX_DMA__TERMIN_SEL 0u\r
+#define SD_TX_DMA__TERMOUT0_EN 1u\r
+#define SD_TX_DMA__TERMOUT0_SEL 3u\r
+#define SD_TX_DMA__TERMOUT1_EN 0u\r
+#define SD_TX_DMA__TERMOUT1_SEL 0u\r
+#define SD_TX_DMA_COMPLETE__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
+#define SD_TX_DMA_COMPLETE__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
+#define SD_TX_DMA_COMPLETE__INTC_MASK 0x40u\r
+#define SD_TX_DMA_COMPLETE__INTC_NUMBER 6u\r
+#define SD_TX_DMA_COMPLETE__INTC_PRIOR_NUM 7u\r
+#define SD_TX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_6\r
+#define SD_TX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
+#define SD_TX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
+\r
+/* USBFS */\r
+#define USBFS_arb_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
+#define USBFS_arb_int__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
+#define USBFS_arb_int__INTC_MASK 0x400000u\r
+#define USBFS_arb_int__INTC_NUMBER 22u\r
+#define USBFS_arb_int__INTC_PRIOR_NUM 6u\r
+#define USBFS_arb_int__INTC_PRIOR_REG CYREG_NVIC_PRI_22\r
+#define USBFS_arb_int__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
+#define USBFS_arb_int__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
+#define USBFS_bus_reset__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
+#define USBFS_bus_reset__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
+#define USBFS_bus_reset__INTC_MASK 0x800000u\r
+#define USBFS_bus_reset__INTC_NUMBER 23u\r
+#define USBFS_bus_reset__INTC_PRIOR_NUM 7u\r
+#define USBFS_bus_reset__INTC_PRIOR_REG CYREG_NVIC_PRI_23\r
+#define USBFS_bus_reset__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
+#define USBFS_bus_reset__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
+#define USBFS_Dm__0__INTTYPE CYREG_PICU15_INTTYPE7\r
+#define USBFS_Dm__0__MASK 0x80u\r
+#define USBFS_Dm__0__PC CYREG_IO_PC_PRT15_7_6_PC1\r
+#define USBFS_Dm__0__PORT 15u\r
+#define USBFS_Dm__0__SHIFT 7u\r
+#define USBFS_Dm__AG CYREG_PRT15_AG\r
+#define USBFS_Dm__AMUX CYREG_PRT15_AMUX\r
+#define USBFS_Dm__BIE CYREG_PRT15_BIE\r
+#define USBFS_Dm__BIT_MASK CYREG_PRT15_BIT_MASK\r
+#define USBFS_Dm__BYP CYREG_PRT15_BYP\r
+#define USBFS_Dm__CTL CYREG_PRT15_CTL\r
+#define USBFS_Dm__DM0 CYREG_PRT15_DM0\r
+#define USBFS_Dm__DM1 CYREG_PRT15_DM1\r
+#define USBFS_Dm__DM2 CYREG_PRT15_DM2\r
+#define USBFS_Dm__DR CYREG_PRT15_DR\r
+#define USBFS_Dm__INP_DIS CYREG_PRT15_INP_DIS\r
+#define USBFS_Dm__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU15_BASE\r
+#define USBFS_Dm__LCD_COM_SEG CYREG_PRT15_LCD_COM_SEG\r
+#define USBFS_Dm__LCD_EN CYREG_PRT15_LCD_EN\r
+#define USBFS_Dm__MASK 0x80u\r
+#define USBFS_Dm__PORT 15u\r
+#define USBFS_Dm__PRT CYREG_PRT15_PRT\r
+#define USBFS_Dm__PRTDSI__CAPS_SEL CYREG_PRT15_CAPS_SEL\r
+#define USBFS_Dm__PRTDSI__DBL_SYNC_IN CYREG_PRT15_DBL_SYNC_IN\r
+#define USBFS_Dm__PRTDSI__OE_SEL0 CYREG_PRT15_OE_SEL0\r
+#define USBFS_Dm__PRTDSI__OE_SEL1 CYREG_PRT15_OE_SEL1\r
+#define USBFS_Dm__PRTDSI__OUT_SEL0 CYREG_PRT15_OUT_SEL0\r
+#define USBFS_Dm__PRTDSI__OUT_SEL1 CYREG_PRT15_OUT_SEL1\r
+#define USBFS_Dm__PRTDSI__SYNC_OUT CYREG_PRT15_SYNC_OUT\r
+#define USBFS_Dm__PS CYREG_PRT15_PS\r
+#define USBFS_Dm__SHIFT 7u\r
+#define USBFS_Dm__SLW CYREG_PRT15_SLW\r
+#define USBFS_Dp__0__INTTYPE CYREG_PICU15_INTTYPE6\r
+#define USBFS_Dp__0__MASK 0x40u\r
+#define USBFS_Dp__0__PC CYREG_IO_PC_PRT15_7_6_PC0\r
+#define USBFS_Dp__0__PORT 15u\r
+#define USBFS_Dp__0__SHIFT 6u\r
+#define USBFS_Dp__AG CYREG_PRT15_AG\r
+#define USBFS_Dp__AMUX CYREG_PRT15_AMUX\r
+#define USBFS_Dp__BIE CYREG_PRT15_BIE\r
+#define USBFS_Dp__BIT_MASK CYREG_PRT15_BIT_MASK\r
+#define USBFS_Dp__BYP CYREG_PRT15_BYP\r
+#define USBFS_Dp__CTL CYREG_PRT15_CTL\r
+#define USBFS_Dp__DM0 CYREG_PRT15_DM0\r
+#define USBFS_Dp__DM1 CYREG_PRT15_DM1\r
+#define USBFS_Dp__DM2 CYREG_PRT15_DM2\r
+#define USBFS_Dp__DR CYREG_PRT15_DR\r
+#define USBFS_Dp__INP_DIS CYREG_PRT15_INP_DIS\r
+#define USBFS_Dp__INTSTAT CYREG_PICU15_INTSTAT\r
+#define USBFS_Dp__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU15_BASE\r
+#define USBFS_Dp__LCD_COM_SEG CYREG_PRT15_LCD_COM_SEG\r
+#define USBFS_Dp__LCD_EN CYREG_PRT15_LCD_EN\r
+#define USBFS_Dp__MASK 0x40u\r
+#define USBFS_Dp__PORT 15u\r
+#define USBFS_Dp__PRT CYREG_PRT15_PRT\r
+#define USBFS_Dp__PRTDSI__CAPS_SEL CYREG_PRT15_CAPS_SEL\r
+#define USBFS_Dp__PRTDSI__DBL_SYNC_IN CYREG_PRT15_DBL_SYNC_IN\r
+#define USBFS_Dp__PRTDSI__OE_SEL0 CYREG_PRT15_OE_SEL0\r
+#define USBFS_Dp__PRTDSI__OE_SEL1 CYREG_PRT15_OE_SEL1\r
+#define USBFS_Dp__PRTDSI__OUT_SEL0 CYREG_PRT15_OUT_SEL0\r
+#define USBFS_Dp__PRTDSI__OUT_SEL1 CYREG_PRT15_OUT_SEL1\r
+#define USBFS_Dp__PRTDSI__SYNC_OUT CYREG_PRT15_SYNC_OUT\r
+#define USBFS_Dp__PS CYREG_PRT15_PS\r
+#define USBFS_Dp__SHIFT 6u\r
+#define USBFS_Dp__SLW CYREG_PRT15_SLW\r
+#define USBFS_Dp__SNAP CYREG_PICU_15_SNAP_15\r
+#define USBFS_dp_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
+#define USBFS_dp_int__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
+#define USBFS_dp_int__INTC_MASK 0x1000u\r
+#define USBFS_dp_int__INTC_NUMBER 12u\r
+#define USBFS_dp_int__INTC_PRIOR_NUM 7u\r
+#define USBFS_dp_int__INTC_PRIOR_REG CYREG_NVIC_PRI_12\r
+#define USBFS_dp_int__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
+#define USBFS_dp_int__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
+#define USBFS_ep_0__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
+#define USBFS_ep_0__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
+#define USBFS_ep_0__INTC_MASK 0x1000000u\r
+#define USBFS_ep_0__INTC_NUMBER 24u\r
+#define USBFS_ep_0__INTC_PRIOR_NUM 7u\r
+#define USBFS_ep_0__INTC_PRIOR_REG CYREG_NVIC_PRI_24\r
+#define USBFS_ep_0__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
+#define USBFS_ep_0__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
+#define USBFS_ep_1__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
+#define USBFS_ep_1__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
+#define USBFS_ep_1__INTC_MASK 0x80u\r
+#define USBFS_ep_1__INTC_NUMBER 7u\r
+#define USBFS_ep_1__INTC_PRIOR_NUM 7u\r
+#define USBFS_ep_1__INTC_PRIOR_REG CYREG_NVIC_PRI_7\r
+#define USBFS_ep_1__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
+#define USBFS_ep_1__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
+#define USBFS_ep_2__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
+#define USBFS_ep_2__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
+#define USBFS_ep_2__INTC_MASK 0x100u\r
+#define USBFS_ep_2__INTC_NUMBER 8u\r
+#define USBFS_ep_2__INTC_PRIOR_NUM 7u\r
+#define USBFS_ep_2__INTC_PRIOR_REG CYREG_NVIC_PRI_8\r
+#define USBFS_ep_2__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
+#define USBFS_ep_2__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
+#define USBFS_ep_3__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
+#define USBFS_ep_3__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
+#define USBFS_ep_3__INTC_MASK 0x200u\r
+#define USBFS_ep_3__INTC_NUMBER 9u\r
+#define USBFS_ep_3__INTC_PRIOR_NUM 7u\r
+#define USBFS_ep_3__INTC_PRIOR_REG CYREG_NVIC_PRI_9\r
+#define USBFS_ep_3__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
+#define USBFS_ep_3__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
+#define USBFS_ep_4__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
+#define USBFS_ep_4__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
+#define USBFS_ep_4__INTC_MASK 0x400u\r
+#define USBFS_ep_4__INTC_NUMBER 10u\r
+#define USBFS_ep_4__INTC_PRIOR_NUM 7u\r
+#define USBFS_ep_4__INTC_PRIOR_REG CYREG_NVIC_PRI_10\r
+#define USBFS_ep_4__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
+#define USBFS_ep_4__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
+#define USBFS_sof_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
+#define USBFS_sof_int__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
+#define USBFS_sof_int__INTC_MASK 0x200000u\r
+#define USBFS_sof_int__INTC_NUMBER 21u\r
+#define USBFS_sof_int__INTC_PRIOR_NUM 7u\r
+#define USBFS_sof_int__INTC_PRIOR_REG CYREG_NVIC_PRI_21\r
+#define USBFS_sof_int__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
+#define USBFS_sof_int__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
+#define USBFS_USB__ARB_CFG CYREG_USB_ARB_CFG\r
+#define USBFS_USB__ARB_EP1_CFG CYREG_USB_ARB_EP1_CFG\r
+#define USBFS_USB__ARB_EP1_INT_EN CYREG_USB_ARB_EP1_INT_EN\r
+#define USBFS_USB__ARB_EP1_SR CYREG_USB_ARB_EP1_SR\r
+#define USBFS_USB__ARB_EP2_CFG CYREG_USB_ARB_EP2_CFG\r
+#define USBFS_USB__ARB_EP2_INT_EN CYREG_USB_ARB_EP2_INT_EN\r
+#define USBFS_USB__ARB_EP2_SR CYREG_USB_ARB_EP2_SR\r
+#define USBFS_USB__ARB_EP3_CFG CYREG_USB_ARB_EP3_CFG\r
+#define USBFS_USB__ARB_EP3_INT_EN CYREG_USB_ARB_EP3_INT_EN\r
+#define USBFS_USB__ARB_EP3_SR CYREG_USB_ARB_EP3_SR\r
+#define USBFS_USB__ARB_EP4_CFG CYREG_USB_ARB_EP4_CFG\r
+#define USBFS_USB__ARB_EP4_INT_EN CYREG_USB_ARB_EP4_INT_EN\r
+#define USBFS_USB__ARB_EP4_SR CYREG_USB_ARB_EP4_SR\r
+#define USBFS_USB__ARB_EP5_CFG CYREG_USB_ARB_EP5_CFG\r
+#define USBFS_USB__ARB_EP5_INT_EN CYREG_USB_ARB_EP5_INT_EN\r
+#define USBFS_USB__ARB_EP5_SR CYREG_USB_ARB_EP5_SR\r
+#define USBFS_USB__ARB_EP6_CFG CYREG_USB_ARB_EP6_CFG\r
+#define USBFS_USB__ARB_EP6_INT_EN CYREG_USB_ARB_EP6_INT_EN\r
+#define USBFS_USB__ARB_EP6_SR CYREG_USB_ARB_EP6_SR\r
+#define USBFS_USB__ARB_EP7_CFG CYREG_USB_ARB_EP7_CFG\r
+#define USBFS_USB__ARB_EP7_INT_EN CYREG_USB_ARB_EP7_INT_EN\r
+#define USBFS_USB__ARB_EP7_SR CYREG_USB_ARB_EP7_SR\r
+#define USBFS_USB__ARB_EP8_CFG CYREG_USB_ARB_EP8_CFG\r
+#define USBFS_USB__ARB_EP8_INT_EN CYREG_USB_ARB_EP8_INT_EN\r
+#define USBFS_USB__ARB_EP8_SR CYREG_USB_ARB_EP8_SR\r
+#define USBFS_USB__ARB_INT_EN CYREG_USB_ARB_INT_EN\r
+#define USBFS_USB__ARB_INT_SR CYREG_USB_ARB_INT_SR\r
+#define USBFS_USB__ARB_RW1_DR CYREG_USB_ARB_RW1_DR\r
+#define USBFS_USB__ARB_RW1_RA CYREG_USB_ARB_RW1_RA\r
+#define USBFS_USB__ARB_RW1_RA_MSB CYREG_USB_ARB_RW1_RA_MSB\r
+#define USBFS_USB__ARB_RW1_WA CYREG_USB_ARB_RW1_WA\r
+#define USBFS_USB__ARB_RW1_WA_MSB CYREG_USB_ARB_RW1_WA_MSB\r
+#define USBFS_USB__ARB_RW2_DR CYREG_USB_ARB_RW2_DR\r
+#define USBFS_USB__ARB_RW2_RA CYREG_USB_ARB_RW2_RA\r
+#define USBFS_USB__ARB_RW2_RA_MSB CYREG_USB_ARB_RW2_RA_MSB\r
+#define USBFS_USB__ARB_RW2_WA CYREG_USB_ARB_RW2_WA\r
+#define USBFS_USB__ARB_RW2_WA_MSB CYREG_USB_ARB_RW2_WA_MSB\r
+#define USBFS_USB__ARB_RW3_DR CYREG_USB_ARB_RW3_DR\r
+#define USBFS_USB__ARB_RW3_RA CYREG_USB_ARB_RW3_RA\r
+#define USBFS_USB__ARB_RW3_RA_MSB CYREG_USB_ARB_RW3_RA_MSB\r
+#define USBFS_USB__ARB_RW3_WA CYREG_USB_ARB_RW3_WA\r
+#define USBFS_USB__ARB_RW3_WA_MSB CYREG_USB_ARB_RW3_WA_MSB\r
+#define USBFS_USB__ARB_RW4_DR CYREG_USB_ARB_RW4_DR\r
+#define USBFS_USB__ARB_RW4_RA CYREG_USB_ARB_RW4_RA\r
+#define USBFS_USB__ARB_RW4_RA_MSB CYREG_USB_ARB_RW4_RA_MSB\r
+#define USBFS_USB__ARB_RW4_WA CYREG_USB_ARB_RW4_WA\r
+#define USBFS_USB__ARB_RW4_WA_MSB CYREG_USB_ARB_RW4_WA_MSB\r
+#define USBFS_USB__ARB_RW5_DR CYREG_USB_ARB_RW5_DR\r
+#define USBFS_USB__ARB_RW5_RA CYREG_USB_ARB_RW5_RA\r
+#define USBFS_USB__ARB_RW5_RA_MSB CYREG_USB_ARB_RW5_RA_MSB\r
+#define USBFS_USB__ARB_RW5_WA CYREG_USB_ARB_RW5_WA\r
+#define USBFS_USB__ARB_RW5_WA_MSB CYREG_USB_ARB_RW5_WA_MSB\r
+#define USBFS_USB__ARB_RW6_DR CYREG_USB_ARB_RW6_DR\r
+#define USBFS_USB__ARB_RW6_RA CYREG_USB_ARB_RW6_RA\r
+#define USBFS_USB__ARB_RW6_RA_MSB CYREG_USB_ARB_RW6_RA_MSB\r
+#define USBFS_USB__ARB_RW6_WA CYREG_USB_ARB_RW6_WA\r
+#define USBFS_USB__ARB_RW6_WA_MSB CYREG_USB_ARB_RW6_WA_MSB\r
+#define USBFS_USB__ARB_RW7_DR CYREG_USB_ARB_RW7_DR\r
+#define USBFS_USB__ARB_RW7_RA CYREG_USB_ARB_RW7_RA\r
+#define USBFS_USB__ARB_RW7_RA_MSB CYREG_USB_ARB_RW7_RA_MSB\r
+#define USBFS_USB__ARB_RW7_WA CYREG_USB_ARB_RW7_WA\r
+#define USBFS_USB__ARB_RW7_WA_MSB CYREG_USB_ARB_RW7_WA_MSB\r
+#define USBFS_USB__ARB_RW8_DR CYREG_USB_ARB_RW8_DR\r
+#define USBFS_USB__ARB_RW8_RA CYREG_USB_ARB_RW8_RA\r
+#define USBFS_USB__ARB_RW8_RA_MSB CYREG_USB_ARB_RW8_RA_MSB\r
+#define USBFS_USB__ARB_RW8_WA CYREG_USB_ARB_RW8_WA\r
+#define USBFS_USB__ARB_RW8_WA_MSB CYREG_USB_ARB_RW8_WA_MSB\r
+#define USBFS_USB__BUF_SIZE CYREG_USB_BUF_SIZE\r
+#define USBFS_USB__BUS_RST_CNT CYREG_USB_BUS_RST_CNT\r
+#define USBFS_USB__CR0 CYREG_USB_CR0\r
+#define USBFS_USB__CR1 CYREG_USB_CR1\r
+#define USBFS_USB__CWA CYREG_USB_CWA\r
+#define USBFS_USB__CWA_MSB CYREG_USB_CWA_MSB\r
+#define USBFS_USB__DMA_THRES CYREG_USB_DMA_THRES\r
+#define USBFS_USB__DMA_THRES_MSB CYREG_USB_DMA_THRES_MSB\r
+#define USBFS_USB__DYN_RECONFIG CYREG_USB_DYN_RECONFIG\r
+#define USBFS_USB__EP_ACTIVE CYREG_USB_EP_ACTIVE\r
+#define USBFS_USB__EP_TYPE CYREG_USB_EP_TYPE\r
+#define USBFS_USB__EP0_CNT CYREG_USB_EP0_CNT\r
+#define USBFS_USB__EP0_CR CYREG_USB_EP0_CR\r
+#define USBFS_USB__EP0_DR0 CYREG_USB_EP0_DR0\r
+#define USBFS_USB__EP0_DR1 CYREG_USB_EP0_DR1\r
+#define USBFS_USB__EP0_DR2 CYREG_USB_EP0_DR2\r
+#define USBFS_USB__EP0_DR3 CYREG_USB_EP0_DR3\r
+#define USBFS_USB__EP0_DR4 CYREG_USB_EP0_DR4\r
+#define USBFS_USB__EP0_DR5 CYREG_USB_EP0_DR5\r
+#define USBFS_USB__EP0_DR6 CYREG_USB_EP0_DR6\r
+#define USBFS_USB__EP0_DR7 CYREG_USB_EP0_DR7\r
+#define USBFS_USB__MEM_DATA CYREG_USB_MEM_DATA_MBASE\r
+#define USBFS_USB__PM_ACT_CFG CYREG_PM_ACT_CFG5\r
+#define USBFS_USB__PM_ACT_MSK 0x01u\r
+#define USBFS_USB__PM_STBY_CFG CYREG_PM_STBY_CFG5\r
+#define USBFS_USB__PM_STBY_MSK 0x01u\r
+#define USBFS_USB__SIE_EP_INT_EN CYREG_USB_SIE_EP_INT_EN\r
+#define USBFS_USB__SIE_EP_INT_SR CYREG_USB_SIE_EP_INT_SR\r
+#define USBFS_USB__SIE_EP1_CNT0 CYREG_USB_SIE_EP1_CNT0\r
+#define USBFS_USB__SIE_EP1_CNT1 CYREG_USB_SIE_EP1_CNT1\r
+#define USBFS_USB__SIE_EP1_CR0 CYREG_USB_SIE_EP1_CR0\r
+#define USBFS_USB__SIE_EP2_CNT0 CYREG_USB_SIE_EP2_CNT0\r
+#define USBFS_USB__SIE_EP2_CNT1 CYREG_USB_SIE_EP2_CNT1\r
+#define USBFS_USB__SIE_EP2_CR0 CYREG_USB_SIE_EP2_CR0\r
+#define USBFS_USB__SIE_EP3_CNT0 CYREG_USB_SIE_EP3_CNT0\r
+#define USBFS_USB__SIE_EP3_CNT1 CYREG_USB_SIE_EP3_CNT1\r
+#define USBFS_USB__SIE_EP3_CR0 CYREG_USB_SIE_EP3_CR0\r
+#define USBFS_USB__SIE_EP4_CNT0 CYREG_USB_SIE_EP4_CNT0\r
+#define USBFS_USB__SIE_EP4_CNT1 CYREG_USB_SIE_EP4_CNT1\r
+#define USBFS_USB__SIE_EP4_CR0 CYREG_USB_SIE_EP4_CR0\r
+#define USBFS_USB__SIE_EP5_CNT0 CYREG_USB_SIE_EP5_CNT0\r
+#define USBFS_USB__SIE_EP5_CNT1 CYREG_USB_SIE_EP5_CNT1\r
+#define USBFS_USB__SIE_EP5_CR0 CYREG_USB_SIE_EP5_CR0\r
+#define USBFS_USB__SIE_EP6_CNT0 CYREG_USB_SIE_EP6_CNT0\r
+#define USBFS_USB__SIE_EP6_CNT1 CYREG_USB_SIE_EP6_CNT1\r
+#define USBFS_USB__SIE_EP6_CR0 CYREG_USB_SIE_EP6_CR0\r
+#define USBFS_USB__SIE_EP7_CNT0 CYREG_USB_SIE_EP7_CNT0\r
+#define USBFS_USB__SIE_EP7_CNT1 CYREG_USB_SIE_EP7_CNT1\r
+#define USBFS_USB__SIE_EP7_CR0 CYREG_USB_SIE_EP7_CR0\r
+#define USBFS_USB__SIE_EP8_CNT0 CYREG_USB_SIE_EP8_CNT0\r
+#define USBFS_USB__SIE_EP8_CNT1 CYREG_USB_SIE_EP8_CNT1\r
+#define USBFS_USB__SIE_EP8_CR0 CYREG_USB_SIE_EP8_CR0\r
+#define USBFS_USB__SOF0 CYREG_USB_SOF0\r
+#define USBFS_USB__SOF1 CYREG_USB_SOF1\r
+#define USBFS_USB__USB_CLK_EN CYREG_USB_USB_CLK_EN\r
+#define USBFS_USB__USBIO_CR0 CYREG_USB_USBIO_CR0\r
+#define USBFS_USB__USBIO_CR1 CYREG_USB_USBIO_CR1\r
+\r
 /* scsiTarget */\r
 #define scsiTarget_datapath__16BIT_A0_REG CYREG_B0_UDB00_01_A0\r
 #define scsiTarget_datapath__16BIT_A1_REG CYREG_B0_UDB00_01_A1\r
@@ -2798,89 +2955,6 @@
 #define scsiTarget_StatusReg__STATUS_AUX_CTL_REG CYREG_B0_UDB02_ACTL\r
 #define scsiTarget_StatusReg__STATUS_REG CYREG_B0_UDB02_ST\r
 \r
-/* Debug_Timer_Interrupt */\r
-#define Debug_Timer_Interrupt__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
-#define Debug_Timer_Interrupt__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
-#define Debug_Timer_Interrupt__INTC_MASK 0x02u\r
-#define Debug_Timer_Interrupt__INTC_NUMBER 1u\r
-#define Debug_Timer_Interrupt__INTC_PRIOR_NUM 7u\r
-#define Debug_Timer_Interrupt__INTC_PRIOR_REG CYREG_NVIC_PRI_1\r
-#define Debug_Timer_Interrupt__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
-#define Debug_Timer_Interrupt__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
-\r
-/* Debug_Timer_TimerHW */\r
-#define Debug_Timer_TimerHW__CAP0 CYREG_TMR0_CAP0\r
-#define Debug_Timer_TimerHW__CAP1 CYREG_TMR0_CAP1\r
-#define Debug_Timer_TimerHW__CFG0 CYREG_TMR0_CFG0\r
-#define Debug_Timer_TimerHW__CFG1 CYREG_TMR0_CFG1\r
-#define Debug_Timer_TimerHW__CFG2 CYREG_TMR0_CFG2\r
-#define Debug_Timer_TimerHW__CNT_CMP0 CYREG_TMR0_CNT_CMP0\r
-#define Debug_Timer_TimerHW__CNT_CMP1 CYREG_TMR0_CNT_CMP1\r
-#define Debug_Timer_TimerHW__PER0 CYREG_TMR0_PER0\r
-#define Debug_Timer_TimerHW__PER1 CYREG_TMR0_PER1\r
-#define Debug_Timer_TimerHW__PM_ACT_CFG CYREG_PM_ACT_CFG3\r
-#define Debug_Timer_TimerHW__PM_ACT_MSK 0x01u\r
-#define Debug_Timer_TimerHW__PM_STBY_CFG CYREG_PM_STBY_CFG3\r
-#define Debug_Timer_TimerHW__PM_STBY_MSK 0x01u\r
-#define Debug_Timer_TimerHW__RT0 CYREG_TMR0_RT0\r
-#define Debug_Timer_TimerHW__RT1 CYREG_TMR0_RT1\r
-#define Debug_Timer_TimerHW__SR0 CYREG_TMR0_SR0\r
-\r
-/* SCSI_RX_DMA */\r
-#define SCSI_RX_DMA__DRQ_CTL CYREG_IDMUX_DRQ_CTL0\r
-#define SCSI_RX_DMA__DRQ_NUMBER 0u\r
-#define SCSI_RX_DMA__NUMBEROF_TDS 0u\r
-#define SCSI_RX_DMA__PRIORITY 2u\r
-#define SCSI_RX_DMA__TERMIN_EN 0u\r
-#define SCSI_RX_DMA__TERMIN_SEL 0u\r
-#define SCSI_RX_DMA__TERMOUT0_EN 1u\r
-#define SCSI_RX_DMA__TERMOUT0_SEL 0u\r
-#define SCSI_RX_DMA__TERMOUT1_EN 0u\r
-#define SCSI_RX_DMA__TERMOUT1_SEL 0u\r
-\r
-/* SCSI_RX_DMA_COMPLETE */\r
-#define SCSI_RX_DMA_COMPLETE__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
-#define SCSI_RX_DMA_COMPLETE__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
-#define SCSI_RX_DMA_COMPLETE__INTC_MASK 0x01u\r
-#define SCSI_RX_DMA_COMPLETE__INTC_NUMBER 0u\r
-#define SCSI_RX_DMA_COMPLETE__INTC_PRIOR_NUM 7u\r
-#define SCSI_RX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_0\r
-#define SCSI_RX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
-#define SCSI_RX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
-\r
-/* SCSI_TX_DMA */\r
-#define SCSI_TX_DMA__DRQ_CTL CYREG_IDMUX_DRQ_CTL0\r
-#define SCSI_TX_DMA__DRQ_NUMBER 1u\r
-#define SCSI_TX_DMA__NUMBEROF_TDS 0u\r
-#define SCSI_TX_DMA__PRIORITY 2u\r
-#define SCSI_TX_DMA__TERMIN_EN 0u\r
-#define SCSI_TX_DMA__TERMIN_SEL 0u\r
-#define SCSI_TX_DMA__TERMOUT0_EN 1u\r
-#define SCSI_TX_DMA__TERMOUT0_SEL 1u\r
-#define SCSI_TX_DMA__TERMOUT1_EN 0u\r
-#define SCSI_TX_DMA__TERMOUT1_SEL 0u\r
-\r
-/* SCSI_TX_DMA_COMPLETE */\r
-#define SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
-#define SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
-#define SCSI_TX_DMA_COMPLETE__INTC_MASK 0x10u\r
-#define SCSI_TX_DMA_COMPLETE__INTC_NUMBER 4u\r
-#define SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM 7u\r
-#define SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_4\r
-#define SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
-#define SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
-\r
-/* SD_Data_Clk */\r
-#define SD_Data_Clk__CFG0 CYREG_CLKDIST_DCFG0_CFG0\r
-#define SD_Data_Clk__CFG1 CYREG_CLKDIST_DCFG0_CFG1\r
-#define SD_Data_Clk__CFG2 CYREG_CLKDIST_DCFG0_CFG2\r
-#define SD_Data_Clk__CFG2_SRC_SEL_MASK 0x07u\r
-#define SD_Data_Clk__INDEX 0x00u\r
-#define SD_Data_Clk__PM_ACT_CFG CYREG_PM_ACT_CFG2\r
-#define SD_Data_Clk__PM_ACT_MSK 0x01u\r
-#define SD_Data_Clk__PM_STBY_CFG CYREG_PM_STBY_CFG2\r
-#define SD_Data_Clk__PM_STBY_MSK 0x01u\r
-\r
 /* timer_clock */\r
 #define timer_clock__CFG0 CYREG_CLKDIST_DCFG2_CFG0\r
 #define timer_clock__CFG1 CYREG_CLKDIST_DCFG2_CFG1\r
@@ -2892,148 +2966,55 @@
 #define timer_clock__PM_STBY_CFG CYREG_PM_STBY_CFG2\r
 #define timer_clock__PM_STBY_MSK 0x04u\r
 \r
-/* SCSI_RST_ISR */\r
-#define SCSI_RST_ISR__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
-#define SCSI_RST_ISR__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
-#define SCSI_RST_ISR__INTC_MASK 0x04u\r
-#define SCSI_RST_ISR__INTC_NUMBER 2u\r
-#define SCSI_RST_ISR__INTC_PRIOR_NUM 7u\r
-#define SCSI_RST_ISR__INTC_PRIOR_REG CYREG_NVIC_PRI_2\r
-#define SCSI_RST_ISR__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
-#define SCSI_RST_ISR__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
-\r
-/* SCSI_SEL_ISR */\r
-#define SCSI_SEL_ISR__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
-#define SCSI_SEL_ISR__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
-#define SCSI_SEL_ISR__INTC_MASK 0x08u\r
-#define SCSI_SEL_ISR__INTC_NUMBER 3u\r
-#define SCSI_SEL_ISR__INTC_PRIOR_NUM 7u\r
-#define SCSI_SEL_ISR__INTC_PRIOR_REG CYREG_NVIC_PRI_3\r
-#define SCSI_SEL_ISR__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
-#define SCSI_SEL_ISR__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
-\r
-/* SCSI_Filtered */\r
-#define SCSI_Filtered_sts_sts_reg__0__MASK 0x01u\r
-#define SCSI_Filtered_sts_sts_reg__0__POS 0\r
-#define SCSI_Filtered_sts_sts_reg__1__MASK 0x02u\r
-#define SCSI_Filtered_sts_sts_reg__1__POS 1\r
-#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB11_12_ACTL\r
-#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB11_12_ST\r
-#define SCSI_Filtered_sts_sts_reg__2__MASK 0x04u\r
-#define SCSI_Filtered_sts_sts_reg__2__POS 2\r
-#define SCSI_Filtered_sts_sts_reg__3__MASK 0x08u\r
-#define SCSI_Filtered_sts_sts_reg__3__POS 3\r
-#define SCSI_Filtered_sts_sts_reg__4__MASK 0x10u\r
-#define SCSI_Filtered_sts_sts_reg__4__POS 4\r
-#define SCSI_Filtered_sts_sts_reg__MASK 0x1Fu\r
-#define SCSI_Filtered_sts_sts_reg__MASK_REG CYREG_B0_UDB11_MSK\r
-#define SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB11_ACTL\r
-#define SCSI_Filtered_sts_sts_reg__STATUS_REG CYREG_B0_UDB11_ST\r
-\r
-/* SCSI_CTL_PHASE */\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK 0x01u\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS 0\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK 0x02u\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS 1\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB06_07_ACTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB06_07_CTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB06_07_CTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB06_07_CTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB06_07_CTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB06_07_MSK\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB06_07_MSK\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB06_07_MSK\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB06_07_MSK\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK 0x04u\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS 2\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB06_ACTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB06_CTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB06_ST_CTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB06_CTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB06_ST_CTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK 0x07u\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB06_MSK\r
-\r
-/* SCSI_Glitch_Ctl */\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK 0x01u\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS 0\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB04_05_ACTL\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB04_05_CTL\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB04_05_CTL\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB04_05_CTL\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB04_05_CTL\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB04_05_MSK\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB04_05_MSK\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB04_05_MSK\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB04_05_MSK\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB04_ACTL\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB04_CTL\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB04_ST_CTL\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB04_CTL\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB04_ST_CTL\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK 0x01u\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB04_MSK\r
-\r
-/* SCSI_Parity_Error */\r
-#define SCSI_Parity_Error_sts_sts_reg__0__MASK 0x01u\r
-#define SCSI_Parity_Error_sts_sts_reg__0__POS 0\r
-#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB05_06_ACTL\r
-#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB05_06_ST\r
-#define SCSI_Parity_Error_sts_sts_reg__MASK 0x01u\r
-#define SCSI_Parity_Error_sts_sts_reg__MASK_REG CYREG_B0_UDB05_MSK\r
-#define SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB05_ACTL\r
-#define SCSI_Parity_Error_sts_sts_reg__STATUS_REG CYREG_B0_UDB05_ST\r
-\r
 /* Miscellaneous */\r
 #define BCLK__BUS_CLK__HZ 50000000U\r
 #define BCLK__BUS_CLK__KHZ 50000U\r
 #define BCLK__BUS_CLK__MHZ 50U\r
 #define CY_PROJECT_NAME "SCSI2SD"\r
-#define CY_VERSION "PSoC Creator  4.0 Update 1"\r
+#define CY_VERSION "PSoC Creator  4.1"\r
 #define CYDEV_CHIP_DIE_LEOPARD 1u\r
-#define CYDEV_CHIP_DIE_PSOC4A 12u\r
-#define CYDEV_CHIP_DIE_PSOC5LP 19u\r
-#define CYDEV_CHIP_DIE_PSOC5TM 20u\r
-#define CYDEV_CHIP_DIE_TMA4 2u\r
+#define CYDEV_CHIP_DIE_PSOC4A 16u\r
+#define CYDEV_CHIP_DIE_PSOC5LP 2u\r
+#define CYDEV_CHIP_DIE_PSOC5TM 3u\r
+#define CYDEV_CHIP_DIE_TMA4 4u\r
 #define CYDEV_CHIP_DIE_UNKNOWN 0u\r
-#define CYDEV_CHIP_FAMILY_FM0P 4u\r
-#define CYDEV_CHIP_FAMILY_FM3 5u\r
-#define CYDEV_CHIP_FAMILY_FM4 6u\r
+#define CYDEV_CHIP_FAMILY_FM0P 5u\r
+#define CYDEV_CHIP_FAMILY_FM3 6u\r
+#define CYDEV_CHIP_FAMILY_FM4 7u\r
 #define CYDEV_CHIP_FAMILY_PSOC3 1u\r
 #define CYDEV_CHIP_FAMILY_PSOC4 2u\r
 #define CYDEV_CHIP_FAMILY_PSOC5 3u\r
+#define CYDEV_CHIP_FAMILY_PSOC6 4u\r
 #define CYDEV_CHIP_FAMILY_UNKNOWN 0u\r
 #define CYDEV_CHIP_FAMILY_USED CYDEV_CHIP_FAMILY_PSOC5\r
 #define CYDEV_CHIP_JTAG_ID 0x2E133069u\r
 #define CYDEV_CHIP_MEMBER_3A 1u\r
-#define CYDEV_CHIP_MEMBER_4A 12u\r
-#define CYDEV_CHIP_MEMBER_4C 18u\r
-#define CYDEV_CHIP_MEMBER_4D 8u\r
-#define CYDEV_CHIP_MEMBER_4E 4u\r
-#define CYDEV_CHIP_MEMBER_4F 13u\r
-#define CYDEV_CHIP_MEMBER_4G 2u\r
-#define CYDEV_CHIP_MEMBER_4H 11u\r
-#define CYDEV_CHIP_MEMBER_4I 17u\r
-#define CYDEV_CHIP_MEMBER_4J 9u\r
-#define CYDEV_CHIP_MEMBER_4K 10u\r
-#define CYDEV_CHIP_MEMBER_4L 16u\r
-#define CYDEV_CHIP_MEMBER_4M 15u\r
-#define CYDEV_CHIP_MEMBER_4N 6u\r
-#define CYDEV_CHIP_MEMBER_4O 5u\r
-#define CYDEV_CHIP_MEMBER_4P 14u\r
-#define CYDEV_CHIP_MEMBER_4Q 7u\r
-#define CYDEV_CHIP_MEMBER_4U 3u\r
-#define CYDEV_CHIP_MEMBER_5A 20u\r
-#define CYDEV_CHIP_MEMBER_5B 19u\r
-#define CYDEV_CHIP_MEMBER_FM3 24u\r
-#define CYDEV_CHIP_MEMBER_FM4 25u\r
-#define CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE1 21u\r
-#define CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE2 22u\r
-#define CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE3 23u\r
+#define CYDEV_CHIP_MEMBER_4A 16u\r
+#define CYDEV_CHIP_MEMBER_4D 12u\r
+#define CYDEV_CHIP_MEMBER_4E 6u\r
+#define CYDEV_CHIP_MEMBER_4F 17u\r
+#define CYDEV_CHIP_MEMBER_4G 4u\r
+#define CYDEV_CHIP_MEMBER_4H 15u\r
+#define CYDEV_CHIP_MEMBER_4I 21u\r
+#define CYDEV_CHIP_MEMBER_4J 13u\r
+#define CYDEV_CHIP_MEMBER_4K 14u\r
+#define CYDEV_CHIP_MEMBER_4L 20u\r
+#define CYDEV_CHIP_MEMBER_4M 19u\r
+#define CYDEV_CHIP_MEMBER_4N 9u\r
+#define CYDEV_CHIP_MEMBER_4O 7u\r
+#define CYDEV_CHIP_MEMBER_4P 18u\r
+#define CYDEV_CHIP_MEMBER_4Q 11u\r
+#define CYDEV_CHIP_MEMBER_4R 8u\r
+#define CYDEV_CHIP_MEMBER_4S 10u\r
+#define CYDEV_CHIP_MEMBER_4U 5u\r
+#define CYDEV_CHIP_MEMBER_5A 3u\r
+#define CYDEV_CHIP_MEMBER_5B 2u\r
+#define CYDEV_CHIP_MEMBER_6A 22u\r
+#define CYDEV_CHIP_MEMBER_FM3 26u\r
+#define CYDEV_CHIP_MEMBER_FM4 27u\r
+#define CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE1 23u\r
+#define CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE2 24u\r
+#define CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE3 25u\r
 #define CYDEV_CHIP_MEMBER_UNKNOWN 0u\r
 #define CYDEV_CHIP_MEMBER_USED CYDEV_CHIP_MEMBER_5B\r
 #define CYDEV_CHIP_DIE_EXPECT CYDEV_CHIP_MEMBER_USED\r
@@ -3058,7 +3039,6 @@
 #define CYDEV_CHIP_REVISION_3A_PRODUCTION 3u\r
 #define CYDEV_CHIP_REVISION_4A_ES0 17u\r
 #define CYDEV_CHIP_REVISION_4A_PRODUCTION 17u\r
-#define CYDEV_CHIP_REVISION_4C_PRODUCTION 0u\r
 #define CYDEV_CHIP_REVISION_4D_PRODUCTION 0u\r
 #define CYDEV_CHIP_REVISION_4E_PRODUCTION 0u\r
 #define CYDEV_CHIP_REVISION_4F_PRODUCTION 0u\r
@@ -3077,12 +3057,16 @@
 #define CYDEV_CHIP_REVISION_4O_PRODUCTION 0u\r
 #define CYDEV_CHIP_REVISION_4P_PRODUCTION 0u\r
 #define CYDEV_CHIP_REVISION_4Q_PRODUCTION 0u\r
+#define CYDEV_CHIP_REVISION_4R_PRODUCTION 0u\r
+#define CYDEV_CHIP_REVISION_4S_PRODUCTION 0u\r
 #define CYDEV_CHIP_REVISION_4U_PRODUCTION 0u\r
 #define CYDEV_CHIP_REVISION_5A_ES0 0u\r
 #define CYDEV_CHIP_REVISION_5A_ES1 1u\r
 #define CYDEV_CHIP_REVISION_5A_PRODUCTION 1u\r
 #define CYDEV_CHIP_REVISION_5B_ES0 0u\r
 #define CYDEV_CHIP_REVISION_5B_PRODUCTION 0u\r
+#define CYDEV_CHIP_REVISION_6A_NO_UDB 0u\r
+#define CYDEV_CHIP_REVISION_6A_PRODUCTION 0u\r
 #define CYDEV_CHIP_REVISION_FM3_PRODUCTION 0u\r
 #define CYDEV_CHIP_REVISION_FM4_PRODUCTION 0u\r
 #define CYDEV_CHIP_REVISION_PDL_FM0P_TYPE1_PRODUCTION 0u\r
@@ -3114,7 +3098,7 @@
 #define CYDEV_ECC_ENABLE 0\r
 #define CYDEV_HEAP_SIZE 0x0400\r
 #define CYDEV_INSTRUCT_CACHE_ENABLED 1\r
-#define CYDEV_INTR_RISING 0x0000007Eu\r
+#define CYDEV_INTR_RISING 0x0000007Fu\r
 #define CYDEV_IS_EXPORTING_CODE 0\r
 #define CYDEV_IS_IMPORTING_CODE 0\r
 #define CYDEV_PROJ_TYPE 2\r

diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c
index 480eb2918ca1b843bb84126a9f0d3c1a5d964f96..2e1f70d2e23e6a5b65c84309439f9f41f1b8df76 100755 (executable)
--- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c
+++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c
@@ -1,7 +1,8 @@
+\r
 /*******************************************************************************\r
 * File Name: cyfitter_cfg.c\r
 * \r
-* PSoC Creator  4.0 Update 1\r
+* PSoC Creator  4.1\r
 *\r
 * Description:\r
 * This file contains device initialization code.\r
@@ -9,7 +10,7 @@
 * This file is automatically generated by PSoC Creator.\r
 *\r
 ********************************************************************************\r
-* Copyright (c) 2007-2016 Cypress Semiconductor.  All rights reserved.\r
+* Copyright (c) 2007-2017 Cypress Semiconductor.  All rights reserved.\r
 * You may use this file only in accordance with the license, terms, conditions, \r
 * disclaimers, and limitations in the end user license agreement accompanying \r
 * the software package with which this file was provided.\r
@@ -55,6 +56,19 @@
     #error Unsupported toolchain\r
 #endif\r
 \r
+#ifndef CYCODE\r
+    #define CYCODE\r
+#endif\r
+#ifndef CYDATA\r
+    #define CYDATA\r
+#endif\r
+#ifndef CYFAR\r
+    #define CYFAR\r
+#endif\r
+#ifndef CYXDATA\r
+    #define CYXDATA\r
+#endif\r
+\r
 \r
 CY_CFG_UNUSED\r
 static void CYMEMZERO(void *s, size_t n);\r
@@ -86,6 +100,7 @@ static void CYCONFIGCPYCODE(void *dest, const void *src, size_t n)
 #define CYCLOCKSTART_XTAL_ERROR  1u\r
 #define CYCLOCKSTART_32KHZ_ERROR 2u\r
 #define CYCLOCKSTART_PLL_ERROR   3u\r
+#define CYCLOCKSTART_FLL_ERROR   4u\r
 \r
 \r
 #ifdef CY_NEED_CYCLOCKSTARTUPERROR\r
@@ -109,17 +124,21 @@ static void CyClockStartupError(uint8 errorCode);
 CY_CFG_UNUSED\r
 static void CyClockStartupError(uint8 errorCode)\r
 {\r
-    /* To remove the compiler warning if errorCode not used.                */\r
+    /* To remove the compiler warning if errorCode not used. */\r
+#if defined(CY_PSOC3) && (CY_PSOC3)\r
     errorCode = errorCode;\r
+#else\r
+    (void)errorCode;\r
+#endif /* CY_PSOC3 */\r
 \r
     /* If we have a clock startup error (bad MHz crystal, PLL lock, etc.),  */\r
     /* we will end up here to allow the customer to implement something to  */\r
     /* deal with the clock condition.                                       */\r
 \r
 #ifdef CY_CFG_CLOCK_STARTUP_ERROR_CALLBACK\r
-       CY_CFG_Clock_Startup_ErrorCallback();\r
+    CY_CFG_Clock_Startup_ErrorCallback();\r
 #else\r
-       /*  If not using CY_CFG_CLOCK_STARTUP_ERROR_CALLBACK, place your clock startup code here. */\r
+    /*  If not using CY_CFG_CLOCK_STARTUP_ERROR_CALLBACK, place your clock startup code here. */\r
     /* `#START CyClockStartupError` */\r
 \r
     /* If we have a clock startup error (bad MHz crystal, PLL lock, etc.),  */\r
@@ -128,10 +147,8 @@ static void CyClockStartupError(uint8 errorCode)
 \r
     /* `#END` */\r
 \r
-    /* If nothing else, stop here since the clocks have not started         */\r
-    /* correctly.                                                           */\r
     while(1) {}\r
-#endif /* CY_CFG_CLOCK_STARTUP_ERROR_CALLBACK */ \r
+#endif /* CY_CFG_CLOCK_STARTUP_ERROR_CALLBACK */\r
 }\r
 #endif\r
 \r
@@ -170,7 +187,7 @@ static void cfg_write_bytes32(const uint32 addr_table[], const cy_cfg_addrvalue_
                baseAddr &= 0xFFFFFF00u;\r
                while (count != 0u)\r
                {\r
-                       CY_SET_XTND_REG8((void CYFAR *)(baseAddr + data_table[j].offset), data_table[j].value);\r
+                       CY_SET_REG8((void *)(baseAddr + data_table[j].offset), data_table[j].value);\r
                        j++;\r
                        count--;\r
                }\r
@@ -205,8 +222,8 @@ static void ClockSetup(void)
        CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_DCFG0_CFG0 + 0x2u), 0x58u);\r
        CY_SET_XTND_REG16((void CYFAR *)(CYREG_CLKDIST_DCFG1_CFG0), 0x0001u);\r
        CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_DCFG1_CFG0 + 0x2u), 0x18u);\r
-       CY_SET_XTND_REG16((void CYFAR *)(CYREG_CLKDIST_DCFG2_CFG0), 0x0017u);\r
-       CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_DCFG2_CFG0 + 0x2u), 0x19u);\r
+       CY_SET_XTND_REG16((void CYFAR *)(CYREG_CLKDIST_DCFG2_CFG0), 0x0031u);\r
+       CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_DCFG2_CFG0 + 0x2u), 0x18u);\r
 \r
        /* Configure ILO based on settings from Clock DWR */\r
        CY_SET_XTND_REG8((void CYFAR *)(CYREG_SLOWCLK_ILO_CR0), 0x06u);\r
@@ -305,7 +322,7 @@ void SetAnalogRoutingPumps(uint8 enabled)
        CY_SET_XTND_REG8((void CYFAR *)CYREG_PUMP_CR0, regValue);\r
 }\r
 \r
-#define CY_AMUX_UNUSED CYREG_BOOST_SR\r
+\r
 \r
 \r
 /*******************************************************************************\r
@@ -317,7 +334,7 @@ void SetAnalogRoutingPumps(uint8 enabled)
 *  settings.  This includes settings from the Design Wide Resources (DWR) such\r
 *  as Clocks and Pins as well as any component configuration that is necessary.\r
 *\r
-* Parameters:  \r
+* Parameters:\r
 *   void\r
 *\r
 * Return:\r
@@ -398,44 +415,44 @@ void cyfitter_cfg(void)
                static const uint32 CYCODE cy_cfg_addr_table[] = {\r
                        0x40004501u, /* Base address: 0x40004500 Count: 1 */\r
                        0x40004F02u, /* Base address: 0x40004F00 Count: 2 */\r
-                       0x4000520Bu, /* Base address: 0x40005200 Count: 11 */\r
+                       0x4000520Eu, /* Base address: 0x40005200 Count: 14 */\r
                        0x40006401u, /* Base address: 0x40006400 Count: 1 */\r
                        0x40006501u, /* Base address: 0x40006500 Count: 1 */\r
                        0x40010045u, /* Base address: 0x40010000 Count: 69 */\r
                        0x4001013Du, /* Base address: 0x40010100 Count: 61 */\r
                        0x40010247u, /* Base address: 0x40010200 Count: 71 */\r
-                       0x40010355u, /* Base address: 0x40010300 Count: 85 */\r
+                       0x4001035Fu, /* Base address: 0x40010300 Count: 95 */\r
                        0x4001045Fu, /* Base address: 0x40010400 Count: 95 */\r
-                       0x40010563u, /* Base address: 0x40010500 Count: 99 */\r
+                       0x40010560u, /* Base address: 0x40010500 Count: 96 */\r
                        0x40010650u, /* Base address: 0x40010600 Count: 80 */\r
-                       0x4001074Eu, /* Base address: 0x40010700 Count: 78 */\r
-                       0x4001090Du, /* Base address: 0x40010900 Count: 13 */\r
+                       0x40010755u, /* Base address: 0x40010700 Count: 85 */\r
+                       0x40010912u, /* Base address: 0x40010900 Count: 18 */\r
                        0x40010A46u, /* Base address: 0x40010A00 Count: 70 */\r
-                       0x40010B51u, /* Base address: 0x40010B00 Count: 81 */\r
+                       0x40010B50u, /* Base address: 0x40010B00 Count: 80 */\r
                        0x40010C56u, /* Base address: 0x40010C00 Count: 86 */\r
-                       0x40010D52u, /* Base address: 0x40010D00 Count: 82 */\r
+                       0x40010D58u, /* Base address: 0x40010D00 Count: 88 */\r
                        0x40010E4Cu, /* Base address: 0x40010E00 Count: 76 */\r
                        0x40010F3Bu, /* Base address: 0x40010F00 Count: 59 */\r
                        0x4001141Fu, /* Base address: 0x40011400 Count: 31 */\r
-                       0x4001154Fu, /* Base address: 0x40011500 Count: 79 */\r
+                       0x40011554u, /* Base address: 0x40011500 Count: 84 */\r
                        0x40011656u, /* Base address: 0x40011600 Count: 86 */\r
-                       0x40011745u, /* Base address: 0x40011700 Count: 69 */\r
+                       0x40011744u, /* Base address: 0x40011700 Count: 68 */\r
                        0x40011804u, /* Base address: 0x40011800 Count: 4 */\r
-                       0x4001190Au, /* Base address: 0x40011900 Count: 10 */\r
+                       0x40011905u, /* Base address: 0x40011900 Count: 5 */\r
                        0x40011B02u, /* Base address: 0x40011B00 Count: 2 */\r
-                       0x40014016u, /* Base address: 0x40014000 Count: 22 */\r
-                       0x4001411Bu, /* Base address: 0x40014100 Count: 27 */\r
-                       0x4001420Bu, /* Base address: 0x40014200 Count: 11 */\r
-                       0x4001430Cu, /* Base address: 0x40014300 Count: 12 */\r
-                       0x4001440Fu, /* Base address: 0x40014400 Count: 15 */\r
-                       0x4001451Du, /* Base address: 0x40014500 Count: 29 */\r
-                       0x4001460Fu, /* Base address: 0x40014600 Count: 15 */\r
-                       0x4001470Eu, /* Base address: 0x40014700 Count: 14 */\r
+                       0x40014019u, /* Base address: 0x40014000 Count: 25 */\r
+                       0x40014118u, /* Base address: 0x40014100 Count: 24 */\r
+                       0x4001420Du, /* Base address: 0x40014200 Count: 13 */\r
+                       0x4001430Du, /* Base address: 0x40014300 Count: 13 */\r
+                       0x40014411u, /* Base address: 0x40014400 Count: 17 */\r
+                       0x40014518u, /* Base address: 0x40014500 Count: 24 */\r
+                       0x4001460Eu, /* Base address: 0x40014600 Count: 14 */\r
+                       0x4001470Fu, /* Base address: 0x40014700 Count: 15 */\r
                        0x40014809u, /* Base address: 0x40014800 Count: 9 */\r
-                       0x4001490Bu, /* Base address: 0x40014900 Count: 11 */\r
-                       0x40014C07u, /* Base address: 0x40014C00 Count: 7 */\r
+                       0x4001490Du, /* Base address: 0x40014900 Count: 13 */\r
+                       0x40014C08u, /* Base address: 0x40014C00 Count: 8 */\r
                        0x40014D0Bu, /* Base address: 0x40014D00 Count: 11 */\r
-                       0x40015002u, /* Base address: 0x40015000 Count: 2 */\r
+                       0x40015004u, /* Base address: 0x40015000 Count: 4 */\r
                        0x40015104u, /* Base address: 0x40015100 Count: 4 */\r
                };\r
 \r
@@ -451,8 +468,11 @@ void cyfitter_cfg(void)
                        {0x18u, 0x04u},\r
                        {0x1Cu, 0x30u},\r
                        {0x24u, 0x44u},\r
-                       {0x28u, 0x01u},\r
-                       {0x31u, 0x20u},\r
+                       {0x28u, 0x02u},\r
+                       {0x30u, 0x20u},\r
+                       {0x31u, 0x30u},\r
+                       {0x78u, 0x20u},\r
+                       {0x79u, 0x20u},\r
                        {0x7Cu, 0x40u},\r
                        {0x20u, 0x01u},\r
                        {0x85u, 0x0Fu},\r
@@ -460,10 +480,9 @@ void cyfitter_cfg(void)
                        {0x04u, 0x0Fu},\r
                        {0x06u, 0xF0u},\r
                        {0x0Au, 0xFFu},\r
-                       {0x0Bu, 0x01u},\r
-                       {0x0Cu, 0x69u},\r
-                       {0x0Eu, 0x96u},\r
-                       {0x12u, 0xFFu},\r
+                       {0x0Eu, 0xFFu},\r
+                       {0x10u, 0x69u},\r
+                       {0x12u, 0x96u},\r
                        {0x14u, 0xFFu},\r
                        {0x18u, 0x55u},\r
                        {0x19u, 0x04u},\r
@@ -471,20 +490,21 @@ void cyfitter_cfg(void)
                        {0x1Cu, 0xFFu},\r
                        {0x1Du, 0x01u},\r
                        {0x1Fu, 0x02u},\r
+                       {0x23u, 0x01u},\r
                        {0x28u, 0x33u},\r
                        {0x2Au, 0xCCu},\r
                        {0x2Bu, 0x02u},\r
                        {0x31u, 0x04u},\r
                        {0x32u, 0xFFu},\r
-                       {0x37u, 0x03u},\r
+                       {0x35u, 0x03u},\r
                        {0x3Au, 0x08u},\r
-                       {0x3Fu, 0x40u},\r
+                       {0x3Fu, 0x10u},\r
                        {0x40u, 0x53u},\r
                        {0x41u, 0x06u},\r
                        {0x42u, 0x40u},\r
                        {0x45u, 0xEFu},\r
-                       {0x46u, 0xD2u},\r
-                       {0x47u, 0xC0u},\r
+                       {0x46u, 0xDCu},\r
+                       {0x47u, 0x20u},\r
                        {0x48u, 0x2Fu},\r
                        {0x49u, 0xFFu},\r
                        {0x4Au, 0xFFu},\r
@@ -525,69 +545,68 @@ void cyfitter_cfg(void)
                        {0xDCu, 0x10u},\r
                        {0xDDu, 0x90u},\r
                        {0xDFu, 0x01u},\r
-                       {0x01u, 0x28u},\r
-                       {0x02u, 0x01u},\r
+                       {0x01u, 0xA8u},\r
                        {0x03u, 0x40u},\r
                        {0x09u, 0x08u},\r
-                       {0x0Au, 0x01u},\r
+                       {0x0Au, 0x02u},\r
                        {0x0Bu, 0x44u},\r
                        {0x12u, 0x04u},\r
                        {0x19u, 0x08u},\r
                        {0x1Au, 0x10u},\r
-                       {0x21u, 0x82u},\r
+                       {0x21u, 0x02u},\r
+                       {0x22u, 0x10u},\r
                        {0x25u, 0x41u},\r
                        {0x27u, 0x18u},\r
                        {0x2Au, 0x10u},\r
+                       {0x2Bu, 0xC0u},\r
                        {0x32u, 0x80u},\r
                        {0x33u, 0x10u},\r
                        {0x34u, 0x02u},\r
                        {0x37u, 0x18u},\r
-                       {0x3Au, 0x20u},\r
                        {0x3Du, 0x82u},\r
                        {0x41u, 0x09u},\r
                        {0x48u, 0x01u},\r
-                       {0x49u, 0x20u},\r
+                       {0x49u, 0xA0u},\r
                        {0x4Au, 0x50u},\r
-                       {0x4Bu, 0x40u},\r
-                       {0x50u, 0x41u},\r
-                       {0x51u, 0x10u},\r
-                       {0x52u, 0x20u},\r
+                       {0x51u, 0x50u},\r
+                       {0x52u, 0x21u},\r
                        {0x59u, 0x10u},\r
                        {0x5Au, 0x84u},\r
                        {0x5Bu, 0x01u},\r
                        {0x5Cu, 0x40u},\r
+                       {0x60u, 0x80u},\r
                        {0x61u, 0x20u},\r
-                       {0x62u, 0x0Au},\r
+                       {0x62u, 0x08u},\r
                        {0x63u, 0x02u},\r
                        {0x64u, 0x02u},\r
                        {0x68u, 0x04u},\r
                        {0x69u, 0x45u},\r
                        {0x70u, 0x94u},\r
-                       {0x71u, 0x01u},\r
-                       {0x81u, 0x81u},\r
+                       {0x72u, 0x80u},\r
+                       {0x81u, 0x04u},\r
                        {0x82u, 0x80u},\r
                        {0x83u, 0x01u},\r
-                       {0x85u, 0x14u},\r
+                       {0x85u, 0x04u},\r
                        {0x86u, 0x10u},\r
                        {0x88u, 0x04u},\r
+                       {0x8Au, 0x10u},\r
                        {0x8Cu, 0x10u},\r
                        {0x8Du, 0x20u},\r
+                       {0x8Eu, 0x90u},\r
                        {0xC0u, 0x0Fu},\r
                        {0xC2u, 0x0Fu},\r
                        {0xC4u, 0x02u},\r
-                       {0xCAu, 0x04u},\r
+                       {0xCAu, 0x05u},\r
                        {0xCCu, 0xECu},\r
-                       {0xCEu, 0x94u},\r
+                       {0xCEu, 0x90u},\r
                        {0xD0u, 0x03u},\r
                        {0xD2u, 0x0Cu},\r
                        {0xD6u, 0x1Fu},\r
                        {0xD8u, 0x1Fu},\r
-                       {0xE0u, 0x84u},\r
-                       {0xE2u, 0x02u},\r
-                       {0xE4u, 0x03u},\r
-                       {0xE6u, 0x0Cu},\r
-                       {0x00u, 0x06u},\r
-                       {0x04u, 0x01u},\r
+                       {0xE2u, 0x82u},\r
+                       {0xE4u, 0x02u},\r
+                       {0xE6u, 0x05u},\r
+                       {0x02u, 0xFFu},\r
                        {0x08u, 0x0Bu},\r
                        {0x0Au, 0xF4u},\r
                        {0x10u, 0xE0u},\r
@@ -595,12 +614,13 @@ void cyfitter_cfg(void)
                        {0x16u, 0x15u},\r
                        {0x18u, 0x40u},\r
                        {0x1Au, 0x80u},\r
-                       {0x1Cu, 0x40u},\r
-                       {0x1Eu, 0x80u},\r
-                       {0x24u, 0x11u},\r
-                       {0x26u, 0xECu},\r
+                       {0x1Cu, 0x11u},\r
+                       {0x1Eu, 0xECu},\r
+                       {0x20u, 0x40u},\r
+                       {0x22u, 0x80u},\r
+                       {0x24u, 0x01u},\r
                        {0x2Au, 0x10u},\r
-                       {0x2Eu, 0xFFu},\r
+                       {0x2Cu, 0x06u},\r
                        {0x32u, 0x3Fu},\r
                        {0x34u, 0xC0u},\r
                        {0x3Au, 0x20u},\r
@@ -608,48 +628,48 @@ void cyfitter_cfg(void)
                        {0x5Bu, 0x04u},\r
                        {0x5Cu, 0x01u},\r
                        {0x5Fu, 0x01u},\r
-                       {0x80u, 0x05u},\r
-                       {0x81u, 0x01u},\r
-                       {0x82u, 0x0Au},\r
-                       {0x83u, 0x02u},\r
-                       {0x84u, 0x06u},\r
-                       {0x86u, 0x09u},\r
+                       {0x80u, 0x03u},\r
+                       {0x81u, 0x08u},\r
+                       {0x82u, 0x0Cu},\r
+                       {0x83u, 0x10u},\r
+                       {0x86u, 0xFFu},\r
                        {0x87u, 0x80u},\r
-                       {0x88u, 0x60u},\r
-                       {0x8Au, 0x90u},\r
+                       {0x88u, 0x05u},\r
+                       {0x8Au, 0x0Au},\r
                        {0x8Bu, 0x04u},\r
                        {0x8Fu, 0x9Bu},\r
-                       {0x92u, 0xFFu},\r
+                       {0x90u, 0x06u},\r
+                       {0x92u, 0x09u},\r
                        {0x93u, 0x60u},\r
-                       {0x94u, 0x03u},\r
                        {0x95u, 0x01u},\r
-                       {0x96u, 0x0Cu},\r
                        {0x97u, 0x02u},\r
-                       {0x98u, 0x50u},\r
-                       {0x9Au, 0xA0u},\r
-                       {0x9Bu, 0x1Bu},\r
+                       {0x98u, 0x60u},\r
+                       {0x99u, 0x9Bu},\r
+                       {0x9Au, 0x90u},\r
+                       {0x9Bu, 0x40u},\r
                        {0x9Cu, 0x0Fu},\r
                        {0x9Du, 0x08u},\r
                        {0x9Eu, 0xF0u},\r
                        {0x9Fu, 0x10u},\r
                        {0xA1u, 0x1Bu},\r
+                       {0xA2u, 0xFFu},\r
                        {0xA4u, 0x30u},\r
-                       {0xA5u, 0x9Bu},\r
+                       {0xA5u, 0x01u},\r
                        {0xA6u, 0xC0u},\r
-                       {0xA7u, 0x40u},\r
+                       {0xA7u, 0x02u},\r
                        {0xA8u, 0xFFu},\r
                        {0xA9u, 0x80u},\r
                        {0xABu, 0x3Bu},\r
-                       {0xADu, 0x08u},\r
-                       {0xAEu, 0xFFu},\r
-                       {0xAFu, 0x10u},\r
-                       {0xB0u, 0xFFu},\r
+                       {0xACu, 0x50u},\r
+                       {0xAEu, 0xA0u},\r
+                       {0xAFu, 0x1Bu},\r
                        {0xB1u, 0xE0u},\r
                        {0xB3u, 0x03u},\r
+                       {0xB4u, 0xFFu},\r
                        {0xB5u, 0x04u},\r
                        {0xB7u, 0x18u},\r
                        {0xBBu, 0x88u},\r
-                       {0xBEu, 0x01u},\r
+                       {0xBEu, 0x10u},\r
                        {0xD6u, 0x08u},\r
                        {0xD8u, 0x04u},\r
                        {0xD9u, 0x04u},\r
@@ -657,91 +677,101 @@ void cyfitter_cfg(void)
                        {0xDCu, 0x10u},\r
                        {0xDDu, 0x90u},\r
                        {0xDFu, 0x01u},\r
-                       {0x00u, 0x04u},\r
-                       {0x01u, 0x10u},\r
-                       {0x03u, 0x80u},\r
-                       {0x04u, 0x02u},\r
+                       {0x01u, 0x04u},\r
+                       {0x03u, 0x84u},\r
                        {0x05u, 0x20u},\r
-                       {0x06u, 0x20u},\r
-                       {0x09u, 0x14u},\r
-                       {0x0Bu, 0x42u},\r
+                       {0x07u, 0x40u},\r
+                       {0x0Au, 0x48u},\r
+                       {0x0Bu, 0x02u},\r
                        {0x0Du, 0x08u},\r
-                       {0x0Eu, 0x04u},\r
-                       {0x0Fu, 0x81u},\r
-                       {0x10u, 0x02u},\r
+                       {0x0Eu, 0x05u},\r
+                       {0x0Fu, 0x80u},\r
+                       {0x11u, 0x02u},\r
                        {0x12u, 0x10u},\r
-                       {0x13u, 0x20u},\r
-                       {0x14u, 0x20u},\r
-                       {0x15u, 0x20u},\r
-                       {0x17u, 0x40u},\r
-                       {0x1Bu, 0x02u},\r
-                       {0x1Du, 0x0Cu},\r
+                       {0x13u, 0x90u},\r
+                       {0x15u, 0xA4u},\r
+                       {0x16u, 0x40u},\r
+                       {0x1Bu, 0x20u},\r
+                       {0x1Du, 0x08u},\r
                        {0x1Eu, 0x04u},\r
-                       {0x22u, 0x99u},\r
-                       {0x23u, 0x02u},\r
-                       {0x29u, 0xA4u},\r
+                       {0x22u, 0x9Au},\r
+                       {0x28u, 0x22u},\r
+                       {0x29u, 0x20u},\r
                        {0x2Bu, 0x40u},\r
-                       {0x30u, 0x20u},\r
-                       {0x32u, 0x89u},\r
-                       {0x36u, 0x02u},\r
-                       {0x37u, 0x02u},\r
+                       {0x2Cu, 0x20u},\r
+                       {0x2Fu, 0x20u},\r
+                       {0x30u, 0x10u},\r
+                       {0x32u, 0x8Au},\r
+                       {0x34u, 0x80u},\r
+                       {0x36u, 0x80u},\r
                        {0x38u, 0x28u},\r
                        {0x3Au, 0x02u},\r
                        {0x3Bu, 0x80u},\r
-                       {0x58u, 0x99u},\r
-                       {0x5Du, 0x08u},\r
+                       {0x44u, 0x10u},\r
+                       {0x45u, 0x08u},\r
+                       {0x58u, 0x01u},\r
+                       {0x59u, 0x84u},\r
+                       {0x5Bu, 0x20u},\r
+                       {0x5Cu, 0x04u},\r
                        {0x5Eu, 0xA2u},\r
-                       {0x60u, 0x02u},\r
-                       {0x61u, 0x81u},\r
-                       {0x62u, 0x05u},\r
-                       {0x63u, 0x0Cu},\r
+                       {0x60u, 0x08u},\r
+                       {0x62u, 0x04u},\r
+                       {0x63u, 0x45u},\r
                        {0x66u, 0x80u},\r
-                       {0x80u, 0x82u},\r
-                       {0x81u, 0x10u},\r
-                       {0x82u, 0x20u},\r
-                       {0x83u, 0x80u},\r
-                       {0x86u, 0x02u},\r
-                       {0x88u, 0x08u},\r
-                       {0x8Bu, 0x40u},\r
-                       {0x90u, 0x8Au},\r
-                       {0x91u, 0x71u},\r
+                       {0x79u, 0x80u},\r
+                       {0x7Bu, 0x02u},\r
+                       {0x81u, 0x81u},\r
+                       {0x82u, 0x02u},\r
+                       {0x84u, 0x20u},\r
+                       {0x88u, 0x40u},\r
+                       {0x89u, 0x44u},\r
+                       {0x8Bu, 0x10u},\r
+                       {0x8Cu, 0x04u},\r
+                       {0x8Eu, 0x21u},\r
+                       {0x8Fu, 0x02u},\r
+                       {0x90u, 0x08u},\r
+                       {0x91u, 0xE1u},\r
                        {0x92u, 0x10u},\r
                        {0x93u, 0x02u},\r
                        {0x95u, 0x02u},\r
-                       {0x96u, 0x85u},\r
-                       {0x97u, 0x04u},\r
-                       {0x98u, 0x11u},\r
-                       {0x9Au, 0x10u},\r
-                       {0x9Bu, 0x10u},\r
+                       {0x96u, 0x86u},\r
+                       {0x97u, 0x44u},\r
+                       {0x98u, 0x01u},\r
+                       {0x99u, 0x04u},\r
+                       {0x9Au, 0x11u},\r
+                       {0x9Bu, 0x30u},\r
+                       {0x9Cu, 0x80u},\r
                        {0x9Du, 0x30u},\r
-                       {0x9Eu, 0x05u},\r
+                       {0x9Eu, 0x04u},\r
                        {0x9Fu, 0x41u},\r
                        {0xA0u, 0x80u},\r
-                       {0xA1u, 0x04u},\r
                        {0xA2u, 0x70u},\r
+                       {0xA3u, 0x80u},\r
                        {0xA4u, 0x01u},\r
                        {0xA5u, 0x28u},\r
-                       {0xA6u, 0x0Au},\r
+                       {0xA6u, 0x08u},\r
                        {0xA7u, 0x01u},\r
-                       {0xA9u, 0x06u},\r
-                       {0xAAu, 0x20u},\r
-                       {0xAEu, 0x50u},\r
-                       {0xB0u, 0x11u},\r
+                       {0xA9u, 0x02u},\r
+                       {0xABu, 0x40u},\r
+                       {0xACu, 0x01u},\r
+                       {0xAEu, 0x40u},\r
+                       {0xAFu, 0x20u},\r
+                       {0xB0u, 0x01u},\r
                        {0xB4u, 0x40u},\r
                        {0xB5u, 0x08u},\r
-                       {0xC0u, 0x7Eu},\r
-                       {0xC2u, 0xFFu},\r
-                       {0xC4u, 0xE7u},\r
+                       {0xC0u, 0x5Eu},\r
+                       {0xC2u, 0xFBu},\r
+                       {0xC4u, 0xFFu},\r
                        {0xCAu, 0x0Fu},\r
                        {0xCCu, 0x0Fu},\r
                        {0xCEu, 0x0Fu},\r
                        {0xD6u, 0xFFu},\r
                        {0xD8u, 0x1Fu},\r
-                       {0xE0u, 0x04u},\r
-                       {0xE2u, 0x01u},\r
-                       {0xE6u, 0x2Du},\r
+                       {0xE2u, 0x24u},\r
+                       {0xE6u, 0x0Du},\r
                        {0xE8u, 0x40u},\r
-                       {0xEAu, 0x04u},\r
+                       {0xEAu, 0x06u},\r
+                       {0xECu, 0x08u},\r
                        {0x01u, 0x40u},\r
                        {0x02u, 0x24u},\r
                        {0x03u, 0x80u},\r
@@ -752,12 +782,12 @@ void cyfitter_cfg(void)
                        {0x09u, 0x04u},\r
                        {0x0Au, 0x09u},\r
                        {0x0Bu, 0x08u},\r
-                       {0x0Du, 0x80u},\r
+                       {0x0Du, 0x01u},\r
                        {0x0Eu, 0x20u},\r
-                       {0x0Fu, 0x7Fu},\r
-                       {0x11u, 0x01u},\r
+                       {0x0Fu, 0x02u},\r
+                       {0x11u, 0x3Fu},\r
                        {0x12u, 0x18u},\r
-                       {0x13u, 0x02u},\r
+                       {0x13u, 0x40u},\r
                        {0x14u, 0x24u},\r
                        {0x15u, 0x3Fu},\r
                        {0x16u, 0x12u},\r
@@ -765,17 +795,17 @@ void cyfitter_cfg(void)
                        {0x19u, 0x01u},\r
                        {0x1Au, 0x03u},\r
                        {0x1Bu, 0x02u},\r
-                       {0x1Du, 0x10u},\r
                        {0x1Eu, 0x80u},\r
-                       {0x1Fu, 0x20u},\r
-                       {0x21u, 0x3Fu},\r
+                       {0x1Fu, 0x7Fu},\r
+                       {0x21u, 0x10u},\r
                        {0x22u, 0x04u},\r
-                       {0x23u, 0x40u},\r
+                       {0x23u, 0x20u},\r
                        {0x25u, 0x80u},\r
                        {0x27u, 0x7Fu},\r
                        {0x29u, 0x10u},\r
                        {0x2Bu, 0x20u},\r
                        {0x2Cu, 0x40u},\r
+                       {0x2Du, 0x80u},\r
                        {0x2Eu, 0x80u},\r
                        {0x2Fu, 0x7Fu},\r
                        {0x30u, 0x38u},\r
@@ -794,42 +824,42 @@ void cyfitter_cfg(void)
                        {0x5Cu, 0x11u},\r
                        {0x5Du, 0x90u},\r
                        {0x5Fu, 0x01u},\r
-                       {0x80u, 0x64u},\r
-                       {0x84u, 0x78u},\r
+                       {0x82u, 0x7Fu},\r
                        {0x85u, 0x0Fu},\r
-                       {0x86u, 0x03u},\r
                        {0x88u, 0x20u},\r
                        {0x89u, 0x05u},\r
                        {0x8Au, 0x40u},\r
                        {0x8Bu, 0x0Au},\r
                        {0x8Eu, 0x08u},\r
-                       {0x91u, 0xA0u},\r
-                       {0x93u, 0x4Fu},\r
+                       {0x90u, 0x64u},\r
+                       {0x94u, 0x78u},\r
                        {0x95u, 0x06u},\r
+                       {0x96u, 0x03u},\r
                        {0x97u, 0x09u},\r
                        {0x98u, 0x02u},\r
-                       {0x9Bu, 0x80u},\r
+                       {0x99u, 0x90u},\r
+                       {0x9Bu, 0x2Fu},\r
                        {0x9Cu, 0x03u},\r
                        {0x9Eu, 0x74u},\r
                        {0x9Fu, 0x70u},\r
-                       {0xA0u, 0x20u},\r
                        {0xA1u, 0xC0u},\r
-                       {0xA2u, 0x40u},\r
                        {0xA3u, 0x1Fu},\r
                        {0xA5u, 0x03u},\r
                        {0xA6u, 0x01u},\r
                        {0xA7u, 0x0Cu},\r
                        {0xA8u, 0x01u},\r
-                       {0xA9u, 0x90u},\r
+                       {0xA9u, 0xA0u},\r
                        {0xAAu, 0x6Eu},\r
-                       {0xABu, 0x2Fu},\r
-                       {0xAEu, 0x7Fu},\r
+                       {0xABu, 0x4Fu},\r
+                       {0xACu, 0x20u},\r
+                       {0xAEu, 0x40u},\r
+                       {0xAFu, 0x80u},\r
                        {0xB1u, 0x7Fu},\r
                        {0xB4u, 0x60u},\r
+                       {0xB5u, 0x80u},\r
                        {0xB6u, 0x1Fu},\r
-                       {0xB7u, 0x80u},\r
                        {0xBAu, 0x20u},\r
-                       {0xBFu, 0x40u},\r
+                       {0xBFu, 0x10u},\r
                        {0xD4u, 0x01u},\r
                        {0xD8u, 0x04u},\r
                        {0xD9u, 0x04u},\r
@@ -840,117 +870,114 @@ void cyfitter_cfg(void)
                        {0x00u, 0x02u},\r
                        {0x01u, 0x60u},\r
                        {0x03u, 0x20u},\r
-                       {0x04u, 0x81u},\r
-                       {0x05u, 0x14u},\r
-                       {0x09u, 0x88u},\r
+                       {0x04u, 0x80u},\r
+                       {0x05u, 0x10u},\r
+                       {0x06u, 0x01u},\r
+                       {0x07u, 0x40u},\r
+                       {0x09u, 0x08u},\r
                        {0x0Au, 0x48u},\r
-                       {0x0Du, 0x10u},\r
-                       {0x0Eu, 0x02u},\r
+                       {0x0Bu, 0x01u},\r
+                       {0x0Du, 0x18u},\r
+                       {0x0Eu, 0x01u},\r
+                       {0x0Fu, 0x80u},\r
                        {0x10u, 0x82u},\r
-                       {0x14u, 0x01u},\r
-                       {0x16u, 0x68u},\r
-                       {0x17u, 0x40u},\r
-                       {0x18u, 0x01u},\r
-                       {0x1Au, 0x49u},\r
-                       {0x1Bu, 0x50u},\r
+                       {0x14u, 0x02u},\r
+                       {0x15u, 0x04u},\r
+                       {0x16u, 0x08u},\r
+                       {0x18u, 0x09u},\r
+                       {0x1Au, 0x4Au},\r
+                       {0x1Bu, 0x40u},\r
                        {0x1Cu, 0x02u},\r
-                       {0x1Du, 0x10u},\r
-                       {0x1Eu, 0x02u},\r
+                       {0x1Du, 0x50u},\r
+                       {0x1Eu, 0x01u},\r
                        {0x1Fu, 0x40u},\r
                        {0x21u, 0x21u},\r
                        {0x22u, 0x40u},\r
                        {0x23u, 0x30u},\r
-                       {0x25u, 0x40u},\r
+                       {0x25u, 0x10u},\r
                        {0x27u, 0x80u},\r
-                       {0x28u, 0x01u},\r
+                       {0x28u, 0x80u},\r
+                       {0x29u, 0x40u},\r
                        {0x2Au, 0x18u},\r
-                       {0x2Bu, 0x40u},\r
-                       {0x2Du, 0x20u},\r
                        {0x2Eu, 0x04u},\r
-                       {0x2Fu, 0x40u},\r
-                       {0x31u, 0x25u},\r
-                       {0x32u, 0x40u},\r
-                       {0x34u, 0x20u},\r
-                       {0x36u, 0x02u},\r
+                       {0x2Fu, 0x4Au},\r
+                       {0x31u, 0x28u},\r
+                       {0x32u, 0x01u},\r
+                       {0x33u, 0x48u},\r
+                       {0x35u, 0x20u},\r
                        {0x37u, 0x88u},\r
                        {0x39u, 0x02u},\r
                        {0x3Au, 0x04u},\r
-                       {0x3Bu, 0x90u},\r
-                       {0x3Du, 0x88u},\r
-                       {0x3Eu, 0x90u},\r
-                       {0x59u, 0x80u},\r
+                       {0x3Bu, 0x50u},\r
+                       {0x3Du, 0x04u},\r
+                       {0x3Eu, 0x10u},\r
+                       {0x58u, 0x40u},\r
                        {0x5Fu, 0x80u},\r
-                       {0x63u, 0x01u},\r
+                       {0x62u, 0x40u},\r
                        {0x68u, 0x02u},\r
-                       {0x78u, 0x10u},\r
-                       {0x7Bu, 0x04u},\r
-                       {0x80u, 0x20u},\r
-                       {0x83u, 0x50u},\r
-                       {0x85u, 0x08u},\r
-                       {0x86u, 0x02u},\r
-                       {0x87u, 0x60u},\r
-                       {0x89u, 0xA0u},\r
+                       {0x83u, 0x14u},\r
+                       {0x87u, 0x20u},\r
+                       {0x88u, 0x01u},\r
+                       {0x89u, 0x20u},\r
                        {0x8Au, 0x08u},\r
-                       {0x90u, 0x82u},\r
+                       {0x8Cu, 0x24u},\r
                        {0x91u, 0x61u},\r
                        {0x92u, 0x30u},\r
+                       {0x93u, 0x41u},\r
                        {0x94u, 0x20u},\r
-                       {0x95u, 0x02u},\r
-                       {0x96u, 0xC1u},\r
-                       {0x97u, 0x81u},\r
-                       {0x98u, 0x02u},\r
-                       {0x99u, 0x05u},\r
-                       {0x9Au, 0x04u},\r
-                       {0x9Bu, 0x10u},\r
+                       {0x95u, 0x06u},\r
+                       {0x96u, 0xC3u},\r
+                       {0x97u, 0x80u},\r
+                       {0x98u, 0x48u},\r
+                       {0x9Au, 0x05u},\r
+                       {0x9Bu, 0x50u},\r
                        {0x9Du, 0x30u},\r
-                       {0x9Eu, 0xA0u},\r
-                       {0x9Fu, 0x41u},\r
-                       {0xA0u, 0x80u},\r
-                       {0xA1u, 0x88u},\r
+                       {0x9Eu, 0x40u},\r
+                       {0x9Fu, 0x05u},\r
+                       {0xA0u, 0xA0u},\r
+                       {0xA1u, 0x48u},\r
                        {0xA2u, 0x20u},\r
-                       {0xA3u, 0x06u},\r
+                       {0xA3u, 0x02u},\r
                        {0xA4u, 0x01u},\r
-                       {0xA5u, 0x20u},\r
-                       {0xA7u, 0x51u},\r
-                       {0xA8u, 0x04u},\r
-                       {0xAAu, 0x61u},\r
-                       {0xACu, 0x20u},\r
-                       {0xAEu, 0x01u},\r
-                       {0xB0u, 0x21u},\r
-                       {0xB1u, 0x80u},\r
-                       {0xB4u, 0x01u},\r
-                       {0xB5u, 0x08u},\r
-                       {0xB7u, 0x30u},\r
-                       {0xC0u, 0xFFu},\r
-                       {0xC2u, 0xCFu},\r
-                       {0xC4u, 0xF9u},\r
-                       {0xCAu, 0xEFu},\r
-                       {0xCCu, 0xFFu},\r
+                       {0xA5u, 0x30u},\r
+                       {0xA7u, 0x41u},\r
+                       {0xA8u, 0x02u},\r
+                       {0xAAu, 0x42u},\r
+                       {0xABu, 0x40u},\r
+                       {0xAEu, 0x04u},\r
+                       {0xAFu, 0x80u},\r
+                       {0xB5u, 0x10u},\r
+                       {0xB6u, 0x80u},\r
+                       {0xC0u, 0xDFu},\r
+                       {0xC2u, 0xFFu},\r
+                       {0xC4u, 0xE9u},\r
+                       {0xCAu, 0xFFu},\r
+                       {0xCCu, 0x7Fu},\r
                        {0xCEu, 0x6Fu},\r
                        {0xD6u, 0x18u},\r
                        {0xD8u, 0x08u},\r
-                       {0xE0u, 0x06u},\r
+                       {0xE0u, 0x04u},\r
                        {0xE2u, 0x01u},\r
                        {0xE4u, 0x08u},\r
-                       {0xE6u, 0x43u},\r
-                       {0xE8u, 0x04u},\r
-                       {0xEAu, 0x02u},\r
-                       {0xECu, 0x02u},\r
+                       {0xE8u, 0x05u},\r
+                       {0xEAu, 0x12u},\r
+                       {0xECu, 0x80u},\r
+                       {0xEEu, 0x09u},\r
                        {0x00u, 0x55u},\r
                        {0x02u, 0xAAu},\r
-                       {0x04u, 0xFFu},\r
                        {0x0Au, 0xFFu},\r
                        {0x0Eu, 0xFFu},\r
                        {0x0Fu, 0x12u},\r
                        {0x10u, 0xFFu},\r
                        {0x13u, 0x01u},\r
+                       {0x14u, 0xFFu},\r
                        {0x17u, 0x0Cu},\r
                        {0x18u, 0x0Fu},\r
                        {0x19u, 0x24u},\r
                        {0x1Au, 0xF0u},\r
                        {0x1Bu, 0x03u},\r
-                       {0x1Cu, 0x69u},\r
-                       {0x1Eu, 0x96u},\r
+                       {0x20u, 0x69u},\r
+                       {0x22u, 0x96u},\r
                        {0x24u, 0x33u},\r
                        {0x25u, 0x28u},\r
                        {0x26u, 0xCCu},\r
@@ -959,11 +986,11 @@ void cyfitter_cfg(void)
                        {0x2Bu, 0x02u},\r
                        {0x2Eu, 0xFFu},\r
                        {0x31u, 0x10u},\r
+                       {0x33u, 0x20u},\r
                        {0x34u, 0xFFu},\r
                        {0x35u, 0x0Fu},\r
-                       {0x37u, 0x20u},\r
                        {0x3Au, 0x20u},\r
-                       {0x3Fu, 0x40u},\r
+                       {0x3Fu, 0x04u},\r
                        {0x58u, 0x04u},\r
                        {0x59u, 0x04u},\r
                        {0x5Bu, 0x04u},\r
@@ -974,22 +1001,22 @@ void cyfitter_cfg(void)
                        {0x83u, 0x40u},\r
                        {0x84u, 0x01u},\r
                        {0x86u, 0x02u},\r
-                       {0x87u, 0x30u},\r
-                       {0x88u, 0x02u},\r
-                       {0x8Au, 0x01u},\r
                        {0x8Bu, 0x80u},\r
-                       {0x8Cu, 0x10u},\r
+                       {0x8Cu, 0x02u},\r
+                       {0x8Eu, 0x01u},\r
                        {0x8Fu, 0x01u},\r
-                       {0x90u, 0x02u},\r
                        {0x91u, 0x03u},\r
-                       {0x92u, 0x05u},\r
                        {0x93u, 0x0Cu},\r
                        {0x94u, 0x02u},\r
                        {0x96u, 0x01u},\r
+                       {0x97u, 0x30u},\r
                        {0x98u, 0x10u},\r
                        {0x99u, 0x02u},\r
+                       {0x9Cu, 0x10u},\r
                        {0x9Fu, 0x07u},\r
+                       {0xA0u, 0x02u},\r
                        {0xA1u, 0x04u},\r
+                       {0xA2u, 0x05u},\r
                        {0xA4u, 0x10u},\r
                        {0xA5u, 0x4Du},\r
                        {0xA7u, 0x22u},\r
@@ -1016,116 +1043,128 @@ void cyfitter_cfg(void)
                        {0xDCu, 0x11u},\r
                        {0xDDu, 0x90u},\r
                        {0xDFu, 0x01u},\r
-                       {0x01u, 0x02u},\r
-                       {0x03u, 0x2Au},\r
-                       {0x05u, 0xA4u},\r
-                       {0x06u, 0x42u},\r
-                       {0x08u, 0x22u},\r
+                       {0x01u, 0x82u},\r
+                       {0x03u, 0x20u},\r
+                       {0x04u, 0x01u},\r
+                       {0x05u, 0x60u},\r
+                       {0x08u, 0x20u},\r
+                       {0x09u, 0x40u},\r
                        {0x0Au, 0x20u},\r
+                       {0x0Cu, 0x04u},\r
+                       {0x0Du, 0x08u},\r
                        {0x0Eu, 0x04u},\r
-                       {0x0Fu, 0x81u},\r
+                       {0x0Fu, 0xA0u},\r
                        {0x10u, 0x20u},\r
-                       {0x13u, 0x40u},\r
-                       {0x14u, 0x01u},\r
-                       {0x16u, 0x90u},\r
-                       {0x17u, 0x42u},\r
+                       {0x11u, 0x40u},\r
+                       {0x13u, 0x01u},\r
+                       {0x16u, 0x50u},\r
+                       {0x17u, 0x40u},\r
                        {0x18u, 0x20u},\r
-                       {0x19u, 0x42u},\r
-                       {0x1Bu, 0x28u},\r
+                       {0x19u, 0x02u},\r
+                       {0x1Au, 0x01u},\r
+                       {0x1Bu, 0x20u},\r
                        {0x1Eu, 0x04u},\r
                        {0x20u, 0x08u},\r
-                       {0x21u, 0x06u},\r
+                       {0x21u, 0x02u},\r
+                       {0x22u, 0x04u},\r
                        {0x26u, 0x02u},\r
-                       {0x27u, 0x0Au},\r
-                       {0x29u, 0xA4u},\r
-                       {0x2Au, 0x04u},\r
-                       {0x2Bu, 0x40u},\r
-                       {0x2Fu, 0x14u},\r
+                       {0x27u, 0x28u},\r
+                       {0x29u, 0x60u},\r
+                       {0x2Bu, 0x50u},\r
+                       {0x2Fu, 0x18u},\r
                        {0x31u, 0x02u},\r
-                       {0x32u, 0x20u},\r
+                       {0x32u, 0x24u},\r
                        {0x33u, 0x40u},\r
                        {0x35u, 0x08u},\r
                        {0x36u, 0x02u},\r
                        {0x37u, 0x18u},\r
                        {0x38u, 0x80u},\r
-                       {0x39u, 0x19u},\r
-                       {0x3Cu, 0x82u},\r
-                       {0x3Du, 0x02u},\r
-                       {0x3Eu, 0x02u},\r
-                       {0x45u, 0x04u},\r
-                       {0x46u, 0x20u},\r
+                       {0x39u, 0x11u},\r
+                       {0x3Cu, 0x80u},\r
+                       {0x49u, 0x40u},\r
+                       {0x4Bu, 0x80u},\r
                        {0x58u, 0x40u},\r
-                       {0x5Bu, 0x20u},\r
-                       {0x62u, 0x50u},\r
-                       {0x6Du, 0x08u},\r
+                       {0x59u, 0x10u},\r
+                       {0x60u, 0x03u},\r
+                       {0x62u, 0x10u},\r
+                       {0x6Du, 0x04u},\r
                        {0x6Eu, 0x60u},\r
-                       {0x80u, 0x20u},\r
-                       {0x81u, 0x02u},\r
-                       {0x82u, 0x01u},\r
-                       {0x86u, 0x10u},\r
-                       {0x90u, 0x81u},\r
+                       {0x80u, 0x10u},\r
+                       {0x81u, 0xC2u},\r
+                       {0x86u, 0x11u},\r
+                       {0x8Au, 0x04u},\r
+                       {0x8Du, 0x10u},\r
+                       {0x90u, 0x80u},\r
                        {0x91u, 0x11u},\r
-                       {0x92u, 0x20u},\r
-                       {0x93u, 0x41u},\r
+                       {0x92u, 0x22u},\r
+                       {0x93u, 0x81u},\r
                        {0x94u, 0x20u},\r
+                       {0x95u, 0x04u},\r
                        {0x96u, 0x04u},\r
-                       {0x98u, 0x12u},\r
-                       {0x99u, 0x04u},\r
+                       {0x98u, 0x28u},\r
+                       {0x9Au, 0x40u},\r
                        {0x9Bu, 0x40u},\r
+                       {0x9Cu, 0x02u},\r
                        {0x9Du, 0x20u},\r
-                       {0x9Eu, 0x70u},\r
-                       {0xA0u, 0x21u},\r
+                       {0x9Eu, 0x10u},\r
+                       {0xA0u, 0x20u},\r
+                       {0xA1u, 0x48u},\r
                        {0xA2u, 0x20u},\r
-                       {0xA3u, 0x42u},\r
-                       {0xA5u, 0x04u},\r
+                       {0xA3u, 0x40u},\r
                        {0xA7u, 0x21u},\r
-                       {0xA8u, 0x21u},\r
+                       {0xA8u, 0x80u},\r
+                       {0xAAu, 0x40u},\r
                        {0xAFu, 0x29u},\r
-                       {0xB1u, 0x10u},\r
+                       {0xB1u, 0x18u},\r
                        {0xB4u, 0x01u},\r
-                       {0xC0u, 0xFFu},\r
-                       {0xC2u, 0xDEu},\r
-                       {0xC4u, 0xA5u},\r
+                       {0xC0u, 0xDDu},\r
+                       {0xC2u, 0x77u},\r
+                       {0xC4u, 0xBDu},\r
                        {0xCAu, 0x6Fu},\r
-                       {0xCCu, 0xEDu},\r
-                       {0xCEu, 0x1Fu},\r
+                       {0xCCu, 0xEFu},\r
+                       {0xCEu, 0x1Du},\r
                        {0xD6u, 0x0Cu},\r
                        {0xD8u, 0x0Cu},\r
-                       {0xE6u, 0x04u},\r
+                       {0xE0u, 0x08u},\r
+                       {0xE6u, 0x05u},\r
                        {0xEAu, 0x09u},\r
-                       {0xEEu, 0x20u},\r
-                       {0x83u, 0x01u},\r
-                       {0x90u, 0x80u},\r
-                       {0x93u, 0x02u},\r
-                       {0xA6u, 0x08u},\r
+                       {0x82u, 0x80u},\r
+                       {0x89u, 0x08u},\r
+                       {0x9Du, 0x08u},\r
+                       {0xA2u, 0x80u},\r
                        {0xA7u, 0x08u},\r
                        {0xADu, 0x08u},\r
+                       {0xAEu, 0x04u},\r
                        {0xAFu, 0x92u},\r
-                       {0xB2u, 0x10u},\r
+                       {0xB1u, 0x20u},\r
+                       {0xB2u, 0x14u},\r
+                       {0xB3u, 0x02u},\r
                        {0xB4u, 0x80u},\r
-                       {0xB6u, 0x80u},\r
+                       {0xB7u, 0x20u},\r
+                       {0xE0u, 0x88u},\r
+                       {0xE2u, 0x40u},\r
+                       {0xE6u, 0x01u},\r
                        {0xEAu, 0x81u},\r
-                       {0xECu, 0x10u},\r
-                       {0xEEu, 0x20u},\r
-                       {0x02u, 0x20u},\r
+                       {0xECu, 0x38u},\r
+                       {0x02u, 0x04u},\r
                        {0x05u, 0x08u},\r
+                       {0x06u, 0x08u},\r
                        {0x07u, 0x05u},\r
-                       {0x0Au, 0x40u},\r
                        {0x0Cu, 0x2Au},\r
                        {0x0Du, 0x08u},\r
                        {0x0Eu, 0x54u},\r
                        {0x0Fu, 0x04u},\r
                        {0x12u, 0x01u},\r
                        {0x15u, 0x04u},\r
-                       {0x16u, 0x04u},\r
+                       {0x16u, 0x02u},\r
                        {0x17u, 0x08u},\r
                        {0x19u, 0x08u},\r
+                       {0x1Au, 0x40u},\r
                        {0x1Bu, 0x06u},\r
                        {0x1Du, 0x08u},\r
+                       {0x1Eu, 0x20u},\r
                        {0x1Fu, 0x14u},\r
                        {0x22u, 0x10u},\r
-                       {0x26u, 0x02u},\r
-                       {0x2Au, 0x08u},\r
                        {0x30u, 0x06u},\r
                        {0x31u, 0x02u},\r
                        {0x32u, 0x01u},\r
@@ -1143,7 +1182,7 @@ void cyfitter_cfg(void)
                        {0x5Cu, 0x11u},\r
                        {0x5Du, 0x90u},\r
                        {0x5Fu, 0x01u},\r
-                       {0x80u, 0xFFu},\r
+                       {0x84u, 0xFFu},\r
                        {0x89u, 0x04u},\r
                        {0x8Au, 0xFFu},\r
                        {0x8Bu, 0x03u},\r
@@ -1177,132 +1216,132 @@ void cyfitter_cfg(void)
                        {0xDBu, 0x04u},\r
                        {0xDCu, 0x11u},\r
                        {0xDFu, 0x01u},\r
-                       {0x01u, 0x42u},\r
-                       {0x03u, 0x04u},\r
+                       {0x00u, 0x02u},\r
+                       {0x01u, 0x48u},\r
                        {0x05u, 0x20u},\r
-                       {0x06u, 0x80u},\r
-                       {0x08u, 0x04u},\r
+                       {0x07u, 0x20u},\r
+                       {0x09u, 0x04u},\r
                        {0x0Au, 0x80u},\r
+                       {0x0Bu, 0x05u},\r
                        {0x0Eu, 0x04u},\r
                        {0x0Fu, 0x12u},\r
                        {0x10u, 0x80u},\r
-                       {0x11u, 0x08u},\r
-                       {0x12u, 0x08u},\r
-                       {0x14u, 0x0Au},\r
-                       {0x15u, 0x04u},\r
+                       {0x14u, 0x02u},\r
+                       {0x15u, 0x14u},\r
                        {0x16u, 0x40u},\r
-                       {0x18u, 0x89u},\r
-                       {0x1Au, 0x20u},\r
+                       {0x19u, 0x01u},\r
+                       {0x1Au, 0x28u},\r
+                       {0x1Bu, 0x80u},\r
                        {0x1Fu, 0x02u},\r
                        {0x20u, 0x40u},\r
                        {0x21u, 0x88u},\r
                        {0x22u, 0x20u},\r
                        {0x24u, 0x10u},\r
-                       {0x26u, 0x14u},\r
+                       {0x26u, 0x18u},\r
                        {0x27u, 0x01u},\r
                        {0x2Fu, 0x08u},\r
                        {0x31u, 0x88u},\r
                        {0x32u, 0x20u},\r
-                       {0x36u, 0x14u},\r
+                       {0x36u, 0x18u},\r
                        {0x37u, 0x01u},\r
                        {0x38u, 0x44u},\r
                        {0x3Fu, 0x20u},\r
-                       {0x58u, 0x90u},\r
-                       {0x59u, 0x04u},\r
+                       {0x58u, 0x94u},\r
                        {0x5Cu, 0x10u},\r
                        {0x5Fu, 0x8Au},\r
                        {0x60u, 0x04u},\r
                        {0x62u, 0x40u},\r
                        {0x63u, 0x20u},\r
                        {0x65u, 0x40u},\r
-                       {0x81u, 0x30u},\r
-                       {0x83u, 0x0Au},\r
-                       {0x84u, 0x04u},\r
+                       {0x80u, 0x40u},\r
+                       {0x83u, 0x89u},\r
                        {0x85u, 0x40u},\r
-                       {0x86u, 0x04u},\r
-                       {0x89u, 0x04u},\r
-                       {0x8Cu, 0x01u},\r
+                       {0x88u, 0x04u},\r
+                       {0x89u, 0x14u},\r
+                       {0x8Du, 0x15u},\r
+                       {0x90u, 0x80u},\r
                        {0x91u, 0x40u},\r
                        {0x92u, 0x80u},\r
-                       {0x93u, 0x02u},\r
-                       {0x94u, 0x08u},\r
+                       {0x93u, 0x04u},\r
                        {0x96u, 0x20u},\r
-                       {0x98u, 0x1Eu},\r
-                       {0x99u, 0x26u},\r
-                       {0x9Bu, 0x04u},\r
-                       {0xA0u, 0x84u},\r
-                       {0xA1u, 0x14u},\r
+                       {0x98u, 0x12u},\r
+                       {0x99u, 0x30u},\r
+                       {0x9Du, 0x0Cu},\r
+                       {0xA0u, 0x81u},\r
+                       {0xA1u, 0x04u},\r
+                       {0xA2u, 0x80u},\r
                        {0xA3u, 0x01u},\r
-                       {0xA6u, 0x08u},\r
-                       {0xA9u, 0x04u},\r
-                       {0xABu, 0xC0u},\r
-                       {0xACu, 0x80u},\r
-                       {0xAEu, 0x04u},\r
-                       {0xAFu, 0x10u},\r
-                       {0xB0u, 0x18u},\r
-                       {0xB2u, 0x40u},\r
-                       {0xB3u, 0x24u},\r
+                       {0xA8u, 0x01u},\r
+                       {0xA9u, 0x24u},\r
+                       {0xAAu, 0x04u},\r
+                       {0xABu, 0x41u},\r
+                       {0xACu, 0x01u},\r
+                       {0xADu, 0x10u},\r
+                       {0xAFu, 0x80u},\r
+                       {0xB0u, 0x10u},\r
+                       {0xB2u, 0x02u},\r
+                       {0xB3u, 0x10u},\r
                        {0xB4u, 0x40u},\r
-                       {0xB5u, 0x08u},\r
                        {0xB6u, 0x20u},\r
-                       {0xC0u, 0x5Bu},\r
-                       {0xC2u, 0xECu},\r
-                       {0xC4u, 0xFEu},\r
+                       {0xC0u, 0x6Du},\r
+                       {0xC2u, 0xEFu},\r
+                       {0xC4u, 0xF8u},\r
                        {0xCAu, 0x20u},\r
                        {0xCCu, 0xEEu},\r
                        {0xCEu, 0x2Au},\r
                        {0xD6u, 0xFEu},\r
                        {0xD8u, 0x1Eu},\r
-                       {0xE0u, 0x20u},\r
-                       {0xE6u, 0xC0u},\r
-                       {0xE8u, 0x90u},\r
-                       {0xECu, 0x04u},\r
-                       {0xEEu, 0x90u},\r
-                       {0x00u, 0x05u},\r
-                       {0x02u, 0x0Au},\r
+                       {0xE0u, 0xB0u},\r
+                       {0xE2u, 0x40u},\r
+                       {0xE4u, 0x04u},\r
+                       {0xEAu, 0x10u},\r
+                       {0xECu, 0x84u},\r
+                       {0x01u, 0xFFu},\r
                        {0x04u, 0x03u},\r
-                       {0x05u, 0x30u},\r
+                       {0x05u, 0x03u},\r
                        {0x06u, 0x0Cu},\r
-                       {0x07u, 0xC0u},\r
+                       {0x07u, 0x0Cu},\r
+                       {0x09u, 0x30u},\r
                        {0x0Au, 0xFFu},\r
-                       {0x0Bu, 0xFFu},\r
-                       {0x0Cu, 0x0Fu},\r
+                       {0x0Bu, 0xC0u},\r
+                       {0x0Cu, 0x05u},\r
                        {0x0Du, 0x06u},\r
-                       {0x0Eu, 0xF0u},\r
+                       {0x0Eu, 0x0Au},\r
                        {0x0Fu, 0x09u},\r
                        {0x10u, 0x09u},\r
-                       {0x11u, 0x05u},\r
                        {0x12u, 0x06u},\r
-                       {0x13u, 0x0Au},\r
                        {0x14u, 0x90u},\r
-                       {0x15u, 0x50u},\r
                        {0x16u, 0x60u},\r
-                       {0x17u, 0xA0u},\r
-                       {0x19u, 0x60u},\r
-                       {0x1Au, 0xFFu},\r
-                       {0x1Bu, 0x90u},\r
-                       {0x21u, 0xFFu},\r
-                       {0x22u, 0xFFu},\r
-                       {0x24u, 0x50u},\r
-                       {0x26u, 0xA0u},\r
-                       {0x27u, 0xFFu},\r
+                       {0x17u, 0xFFu},\r
+                       {0x18u, 0x50u},\r
+                       {0x1Au, 0xA0u},\r
+                       {0x1Bu, 0xFFu},\r
+                       {0x1Du, 0x0Fu},\r
+                       {0x1Eu, 0xFFu},\r
+                       {0x1Fu, 0xF0u},\r
+                       {0x20u, 0x0Fu},\r
+                       {0x21u, 0x60u},\r
+                       {0x22u, 0xF0u},\r
+                       {0x23u, 0x90u},\r
+                       {0x25u, 0x50u},\r
+                       {0x26u, 0xFFu},\r
+                       {0x27u, 0xA0u},\r
                        {0x28u, 0x30u},\r
-                       {0x29u, 0x03u},\r
                        {0x2Au, 0xC0u},\r
-                       {0x2Bu, 0x0Cu},\r
-                       {0x2Du, 0x0Fu},\r
-                       {0x2Fu, 0xF0u},\r
-                       {0x34u, 0xFFu},\r
-                       {0x35u, 0xFFu},\r
-                       {0x3Eu, 0x10u},\r
-                       {0x3Fu, 0x10u},\r
+                       {0x2Du, 0x05u},\r
+                       {0x2Fu, 0x0Au},\r
+                       {0x30u, 0xFFu},\r
+                       {0x37u, 0xFFu},\r
+                       {0x3Eu, 0x01u},\r
+                       {0x3Fu, 0x40u},\r
                        {0x56u, 0x08u},\r
                        {0x58u, 0x04u},\r
                        {0x59u, 0x04u},\r
                        {0x5Bu, 0x04u},\r
                        {0x5Du, 0x90u},\r
                        {0x5Fu, 0x01u},\r
-                       {0x86u, 0x02u},\r
+                       {0x81u, 0x08u},\r
+                       {0x83u, 0x50u},\r
                        {0x88u, 0x20u},\r
                        {0x8Au, 0x10u},\r
                        {0x8Cu, 0x01u},\r
@@ -1312,31 +1351,30 @@ void cyfitter_cfg(void)
                        {0x92u, 0x10u},\r
                        {0x93u, 0x58u},\r
                        {0x94u, 0x20u},\r
-                       {0x95u, 0x04u},\r
+                       {0x95u, 0x02u},\r
                        {0x96u, 0x18u},\r
-                       {0x97u, 0x02u},\r
+                       {0x97u, 0x24u},\r
                        {0x98u, 0x10u},\r
-                       {0x99u, 0x02u},\r
                        {0x9Au, 0x20u},\r
-                       {0x9Bu, 0x24u},\r
                        {0x9Du, 0x10u},\r
                        {0x9Eu, 0x01u},\r
                        {0x9Fu, 0x08u},\r
-                       {0xA1u, 0x08u},\r
-                       {0xA3u, 0x50u},\r
                        {0xA4u, 0x20u},\r
+                       {0xA5u, 0x04u},\r
                        {0xA6u, 0x14u},\r
+                       {0xA7u, 0x02u},\r
                        {0xA9u, 0x01u},\r
+                       {0xAAu, 0x02u},\r
                        {0xB0u, 0x04u},\r
-                       {0xB1u, 0x01u},\r
+                       {0xB1u, 0x60u},\r
                        {0xB2u, 0x08u},\r
                        {0xB3u, 0x1Eu},\r
                        {0xB4u, 0x30u},\r
-                       {0xB5u, 0x60u},\r
+                       {0xB5u, 0x01u},\r
                        {0xB6u, 0x03u},\r
                        {0xBAu, 0x20u},\r
                        {0xBEu, 0x40u},\r
-                       {0xBFu, 0x14u},\r
+                       {0xBFu, 0x05u},\r
                        {0xD6u, 0x08u},\r
                        {0xD8u, 0x04u},\r
                        {0xD9u, 0x04u},\r
@@ -1344,99 +1382,105 @@ void cyfitter_cfg(void)
                        {0xDCu, 0x91u},\r
                        {0xDDu, 0x90u},\r
                        {0xDFu, 0x01u},\r
-                       {0x01u, 0x04u},\r
                        {0x03u, 0x09u},\r
-                       {0x04u, 0x10u},\r
-                       {0x05u, 0x02u},\r
-                       {0x06u, 0x20u},\r
-                       {0x07u, 0x11u},\r
-                       {0x08u, 0x80u},\r
-                       {0x0Au, 0xA4u},\r
-                       {0x0Cu, 0x24u},\r
-                       {0x0Du, 0x20u},\r
-                       {0x0Eu, 0x20u},\r
-                       {0x0Fu, 0x80u},\r
+                       {0x04u, 0x84u},\r
+                       {0x05u, 0x80u},\r
+                       {0x06u, 0x08u},\r
+                       {0x07u, 0x14u},\r
+                       {0x0Au, 0xA8u},\r
+                       {0x0Bu, 0x01u},\r
+                       {0x0Cu, 0x20u},\r
+                       {0x0Du, 0x90u},\r
+                       {0x0Eu, 0x21u},\r
+                       {0x0Fu, 0x84u},\r
+                       {0x10u, 0x08u},\r
                        {0x12u, 0x10u},\r
-                       {0x15u, 0x03u},\r
-                       {0x16u, 0x08u},\r
-                       {0x17u, 0x24u},\r
+                       {0x14u, 0x20u},\r
+                       {0x15u, 0x18u},\r
+                       {0x17u, 0x21u},\r
+                       {0x18u, 0x02u},\r
                        {0x19u, 0x20u},\r
-                       {0x1Au, 0x84u},\r
-                       {0x1Bu, 0x88u},\r
-                       {0x1Cu, 0x08u},\r
-                       {0x20u, 0x90u},\r
-                       {0x21u, 0x08u},\r
-                       {0x23u, 0x04u},\r
-                       {0x25u, 0x10u},\r
-                       {0x29u, 0x20u},\r
-                       {0x2Au, 0x02u},\r
+                       {0x1Au, 0x88u},\r
+                       {0x1Bu, 0x08u},\r
+                       {0x1Cu, 0x80u},\r
+                       {0x21u, 0x04u},\r
+                       {0x22u, 0x22u},\r
+                       {0x26u, 0x80u},\r
+                       {0x29u, 0x28u},\r
                        {0x2Cu, 0x20u},\r
-                       {0x2Du, 0x41u},\r
-                       {0x2Eu, 0x20u},\r
+                       {0x2Du, 0x80u},\r
+                       {0x2Fu, 0x80u},\r
                        {0x30u, 0x80u},\r
-                       {0x32u, 0x28u},\r
-                       {0x33u, 0x41u},\r
-                       {0x35u, 0x02u},\r
-                       {0x36u, 0x10u},\r
+                       {0x31u, 0x04u},\r
+                       {0x33u, 0x01u},\r
+                       {0x34u, 0x20u},\r
+                       {0x36u, 0x40u},\r
                        {0x37u, 0x04u},\r
-                       {0x3Cu, 0x10u},\r
-                       {0x3Eu, 0x08u},\r
+                       {0x3Au, 0x02u},\r
+                       {0x3Cu, 0x04u},\r
+                       {0x3Du, 0x10u},\r
+                       {0x3Eu, 0x01u},\r
                        {0x3Fu, 0x80u},\r
-                       {0x59u, 0x80u},\r
+                       {0x5Bu, 0x80u},\r
                        {0x5Cu, 0x40u},\r
-                       {0x5Du, 0x10u},\r
+                       {0x5Fu, 0x10u},\r
                        {0x63u, 0x02u},\r
                        {0x64u, 0x02u},\r
-                       {0x66u, 0x50u},\r
+                       {0x66u, 0x10u},\r
+                       {0x67u, 0x02u},\r
                        {0x6Du, 0x40u},\r
+                       {0x6Eu, 0x80u},\r
                        {0x6Fu, 0x01u},\r
-                       {0x81u, 0x22u},\r
-                       {0x83u, 0x04u},\r
+                       {0x81u, 0x80u},\r
+                       {0x83u, 0x81u},\r
                        {0x87u, 0x01u},\r
                        {0x88u, 0x40u},\r
-                       {0x89u, 0x01u},\r
-                       {0x8Cu, 0x04u},\r
-                       {0x8Du, 0x80u},\r
-                       {0x91u, 0x16u},\r
-                       {0x93u, 0x02u},\r
-                       {0x95u, 0x40u},\r
-                       {0x97u, 0x20u},\r
-                       {0x99u, 0x06u},\r
+                       {0x89u, 0x04u},\r
+                       {0x8Au, 0x08u},\r
+                       {0x8Eu, 0x08u},\r
+                       {0x8Fu, 0x10u},\r
+                       {0x90u, 0x80u},\r
+                       {0x91u, 0x20u},\r
+                       {0x95u, 0x48u},\r
+                       {0x99u, 0x10u},\r
                        {0x9Au, 0x02u},\r
-                       {0x9Bu, 0x74u},\r
-                       {0x9Cu, 0x08u},\r
+                       {0x9Bu, 0x30u},\r
+                       {0x9Eu, 0x04u},\r
+                       {0xA0u, 0x89u},\r
+                       {0xA1u, 0x80u},\r
                        {0xA2u, 0x10u},\r
-                       {0xA5u, 0x28u},\r
-                       {0xA7u, 0x60u},\r
-                       {0xA9u, 0x04u},\r
-                       {0xAAu, 0x10u},\r
+                       {0xA7u, 0x50u},\r
+                       {0xA8u, 0x01u},\r
                        {0xABu, 0x10u},\r
+                       {0xACu, 0x08u},\r
+                       {0xAFu, 0x20u},\r
                        {0xB7u, 0x01u},\r
-                       {0xC0u, 0xF7u},\r
-                       {0xC2u, 0x7Fu},\r
-                       {0xC4u, 0x74u},\r
-                       {0xCAu, 0xF5u},\r
-                       {0xCCu, 0xEFu},\r
-                       {0xCEu, 0x70u},\r
+                       {0xC0u, 0xE3u},\r
+                       {0xC2u, 0xFFu},\r
+                       {0xC4u, 0x76u},\r
+                       {0xCAu, 0xD6u},\r
+                       {0xCCu, 0x7Bu},\r
+                       {0xCEu, 0xF1u},\r
                        {0xD6u, 0x38u},\r
                        {0xD8u, 0x38u},\r
-                       {0xE2u, 0xA0u},\r
-                       {0xE6u, 0x21u},\r
+                       {0xE0u, 0x20u},\r
+                       {0xE2u, 0x85u},\r
+                       {0xE6u, 0xA0u},\r
                        {0xE8u, 0x01u},\r
-                       {0xEAu, 0x20u},\r
+                       {0xEAu, 0x02u},\r
                        {0xECu, 0x10u},\r
-                       {0xEEu, 0x21u},\r
-                       {0x02u, 0x03u},\r
+                       {0xEEu, 0x20u},\r
+                       {0x00u, 0x24u},\r
+                       {0x02u, 0x09u},\r
                        {0x05u, 0x50u},\r
                        {0x06u, 0x58u},\r
                        {0x07u, 0xA0u},\r
-                       {0x09u, 0x05u},\r
-                       {0x0Bu, 0x0Au},\r
+                       {0x09u, 0x60u},\r
+                       {0x0Bu, 0x90u},\r
                        {0x0Du, 0x0Fu},\r
                        {0x0Fu, 0xF0u},\r
-                       {0x10u, 0x24u},\r
                        {0x11u, 0x30u},\r
-                       {0x12u, 0x09u},\r
+                       {0x12u, 0x03u},\r
                        {0x13u, 0xC0u},\r
                        {0x15u, 0x06u},\r
                        {0x16u, 0x24u},\r
@@ -1446,26 +1490,24 @@ void cyfitter_cfg(void)
                        {0x1Eu, 0x04u},\r
                        {0x20u, 0x24u},\r
                        {0x22u, 0x12u},\r
+                       {0x25u, 0x05u},\r
                        {0x26u, 0x80u},\r
-                       {0x29u, 0x60u},\r
+                       {0x27u, 0x0Au},\r
                        {0x2Au, 0x20u},\r
-                       {0x2Bu, 0x90u},\r
                        {0x2Cu, 0x40u},\r
                        {0x2Eu, 0x80u},\r
                        {0x30u, 0x07u},\r
-                       {0x31u, 0xFFu},\r
-                       {0x32u, 0xC0u},\r
                        {0x34u, 0x38u},\r
-                       {0x3Eu, 0x04u},\r
-                       {0x3Fu, 0x01u},\r
+                       {0x36u, 0xC0u},\r
+                       {0x37u, 0xFFu},\r
+                       {0x3Eu, 0x40u},\r
+                       {0x3Fu, 0x40u},\r
                        {0x58u, 0x04u},\r
                        {0x59u, 0x04u},\r
                        {0x5Bu, 0x04u},\r
                        {0x5Cu, 0x01u},\r
                        {0x5Fu, 0x01u},\r
-                       {0x80u, 0x05u},\r
                        {0x81u, 0x90u},\r
-                       {0x82u, 0x0Au},\r
                        {0x83u, 0x48u},\r
                        {0x84u, 0x03u},\r
                        {0x86u, 0x0Cu},\r
@@ -1480,11 +1522,13 @@ void cyfitter_cfg(void)
                        {0x91u, 0x90u},\r
                        {0x92u, 0x06u},\r
                        {0x93u, 0x24u},\r
-                       {0x94u, 0xFFu},\r
+                       {0x96u, 0xFFu},\r
                        {0x97u, 0x10u},\r
-                       {0x9Au, 0xFFu},\r
                        {0x9Bu, 0x60u},\r
+                       {0x9Cu, 0x05u},\r
+                       {0x9Eu, 0x0Au},\r
                        {0xA0u, 0xFFu},\r
+                       {0xA4u, 0xFFu},\r
                        {0xA7u, 0x90u},\r
                        {0xA8u, 0x30u},\r
                        {0xAAu, 0xC0u},\r
@@ -1492,75 +1536,75 @@ void cyfitter_cfg(void)
                        {0xADu, 0x01u},\r
                        {0xAEu, 0xF0u},\r
                        {0xAFu, 0x02u},\r
-                       {0xB0u, 0xFFu},\r
                        {0xB3u, 0xE0u},\r
+                       {0xB4u, 0xFFu},\r
                        {0xB5u, 0x1Cu},\r
                        {0xB7u, 0x03u},\r
-                       {0xBEu, 0x01u},\r
+                       {0xBEu, 0x10u},\r
                        {0xBFu, 0x40u},\r
                        {0xD8u, 0x04u},\r
                        {0xD9u, 0x04u},\r
                        {0xDCu, 0x10u},\r
                        {0xDFu, 0x01u},\r
                        {0x00u, 0x04u},\r
-                       {0x01u, 0x02u},\r
-                       {0x05u, 0x42u},\r
-                       {0x07u, 0x14u},\r
-                       {0x08u, 0x0Au},\r
-                       {0x0Au, 0x02u},\r
-                       {0x0Du, 0x28u},\r
-                       {0x0Fu, 0x80u},\r
+                       {0x03u, 0x40u},\r
+                       {0x05u, 0x40u},\r
+                       {0x07u, 0x18u},\r
+                       {0x08u, 0x08u},\r
+                       {0x0Au, 0x42u},\r
+                       {0x0Fu, 0xA2u},\r
                        {0x10u, 0x20u},\r
                        {0x11u, 0x40u},\r
                        {0x12u, 0x08u},\r
                        {0x13u, 0x01u},\r
-                       {0x15u, 0x42u},\r
-                       {0x17u, 0x20u},\r
-                       {0x18u, 0x04u},\r
-                       {0x19u, 0x02u},\r
-                       {0x1Au, 0x18u},\r
-                       {0x1Fu, 0x01u},\r
-                       {0x21u, 0x01u},\r
+                       {0x15u, 0x48u},\r
+                       {0x17u, 0x22u},\r
+                       {0x18u, 0x85u},\r
+                       {0x1Au, 0x48u},\r
+                       {0x1Bu, 0x01u},\r
+                       {0x1Du, 0x10u},\r
+                       {0x21u, 0x80u},\r
+                       {0x23u, 0x02u},\r
                        {0x25u, 0x50u},\r
                        {0x26u, 0x20u},\r
                        {0x27u, 0x10u},\r
-                       {0x29u, 0x10u},\r
+                       {0x2Au, 0x04u},\r
                        {0x2Du, 0x40u},\r
                        {0x2Fu, 0x20u},\r
                        {0x31u, 0x02u},\r
                        {0x32u, 0x24u},\r
-                       {0x34u, 0x02u},\r
-                       {0x37u, 0x18u},\r
-                       {0x38u, 0x08u},\r
-                       {0x39u, 0x44u},\r
-                       {0x3Bu, 0x20u},\r
+                       {0x36u, 0x01u},\r
+                       {0x37u, 0x14u},\r
+                       {0x38u, 0x28u},\r
+                       {0x39u, 0x40u},\r
                        {0x3Du, 0x20u},\r
                        {0x3Eu, 0x08u},\r
                        {0x3Fu, 0x41u},\r
-                       {0x68u, 0x01u},\r
-                       {0x6Bu, 0x64u},\r
-                       {0x70u, 0x24u},\r
-                       {0x71u, 0x12u},\r
+                       {0x68u, 0x81u},\r
+                       {0x69u, 0x20u},\r
+                       {0x6Bu, 0x28u},\r
+                       {0x70u, 0x3Cu},\r
+                       {0x71u, 0x02u},\r
                        {0x72u, 0x02u},\r
                        {0x73u, 0x40u},\r
                        {0x81u, 0x40u},\r
-                       {0x83u, 0x08u},\r
                        {0x84u, 0x01u},\r
                        {0x85u, 0x40u},\r
                        {0x86u, 0x18u},\r
                        {0x87u, 0x20u},\r
-                       {0x89u, 0x50u},\r
+                       {0x89u, 0x40u},\r
                        {0x8Au, 0x01u},\r
-                       {0x8Cu, 0x02u},\r
-                       {0x8Eu, 0x08u},\r
-                       {0xC0u, 0xFCu},\r
-                       {0xC2u, 0x7Du},\r
-                       {0xC4u, 0xDFu},\r
-                       {0xCAu, 0x54u},\r
+                       {0x8Eu, 0x09u},\r
+                       {0x8Fu, 0x44u},\r
+                       {0xC0u, 0xECu},\r
+                       {0xC2u, 0xBDu},\r
+                       {0xC4u, 0xFFu},\r
+                       {0xCAu, 0x52u},\r
                        {0xCCu, 0xE7u},\r
                        {0xCEu, 0xFEu},\r
-                       {0xE0u, 0xB0u},\r
-                       {0xE4u, 0x41u},\r
+                       {0xE0u, 0x70u},\r
+                       {0xE4u, 0x50u},\r
+                       {0xE6u, 0x01u},\r
                        {0x84u, 0x08u},\r
                        {0x85u, 0x25u},\r
                        {0x86u, 0x13u},\r
@@ -1592,17 +1636,19 @@ void cyfitter_cfg(void)
                        {0xD9u, 0x04u},\r
                        {0xDBu, 0x04u},\r
                        {0xDFu, 0x01u},\r
-                       {0x01u, 0xA2u},\r
-                       {0x03u, 0x10u},\r
+                       {0x01u, 0x82u},\r
+                       {0x03u, 0x18u},\r
                        {0x05u, 0x04u},\r
                        {0x09u, 0x01u},\r
-                       {0x0Bu, 0x2Au},\r
+                       {0x0Au, 0x08u},\r
+                       {0x0Bu, 0x22u},\r
                        {0x0Eu, 0x25u},\r
                        {0x10u, 0x20u},\r
                        {0x11u, 0x40u},\r
                        {0x12u, 0x88u},\r
                        {0x17u, 0x10u},\r
-                       {0x19u, 0x23u},\r
+                       {0x19u, 0x03u},\r
+                       {0x1Au, 0x08u},\r
                        {0x1Cu, 0x20u},\r
                        {0x1Eu, 0x21u},\r
                        {0x22u, 0x08u},\r
@@ -1641,7 +1687,7 @@ void cyfitter_cfg(void)
                        {0x8Cu, 0x02u},\r
                        {0x90u, 0x04u},\r
                        {0x92u, 0x04u},\r
-                       {0x93u, 0x2Au},\r
+                       {0x93u, 0x22u},\r
                        {0x94u, 0x28u},\r
                        {0x95u, 0x41u},\r
                        {0x97u, 0x04u},\r
@@ -1655,6 +1701,9 @@ void cyfitter_cfg(void)
                        {0xA4u, 0xC8u},\r
                        {0xA6u, 0x20u},\r
                        {0xA7u, 0x20u},\r
+                       {0xA9u, 0x02u},\r
+                       {0xAEu, 0x80u},\r
+                       {0xAFu, 0x20u},\r
                        {0xB0u, 0x80u},\r
                        {0xB1u, 0x10u},\r
                        {0xB2u, 0x80u},\r
@@ -1722,9 +1771,10 @@ void cyfitter_cfg(void)
                        {0x59u, 0x04u},\r
                        {0x5Bu, 0x04u},\r
                        {0x5Fu, 0x01u},\r
-                       {0x80u, 0x30u},\r
+                       {0x80u, 0x02u},\r
                        {0x81u, 0x03u},\r
-                       {0x82u, 0x08u},\r
+                       {0x82u, 0x30u},\r
+                       {0x86u, 0x01u},\r
                        {0x87u, 0x01u},\r
                        {0x88u, 0x05u},\r
                        {0x89u, 0x03u},\r
@@ -1734,15 +1784,14 @@ void cyfitter_cfg(void)
                        {0x8Fu, 0x03u},\r
                        {0x90u, 0x01u},\r
                        {0x92u, 0x38u},\r
+                       {0x94u, 0x10u},\r
                        {0x95u, 0x03u},\r
-                       {0x98u, 0x10u},\r
-                       {0x9Au, 0x20u},\r
-                       {0xA6u, 0x01u},\r
+                       {0x96u, 0x20u},\r
+                       {0x9Cu, 0x30u},\r
+                       {0x9Eu, 0x08u},\r
                        {0xA8u, 0x34u},\r
                        {0xAAu, 0x08u},\r
-                       {0xACu, 0x02u},\r
                        {0xADu, 0x03u},\r
-                       {0xAEu, 0x30u},\r
                        {0xB0u, 0x30u},\r
                        {0xB3u, 0x01u},\r
                        {0xB4u, 0x0Fu},\r
@@ -1757,18 +1806,16 @@ void cyfitter_cfg(void)
                        {0xDBu, 0x04u},\r
                        {0xDCu, 0x01u},\r
                        {0xDFu, 0x01u},\r
-                       {0x00u, 0x01u},\r
-                       {0x01u, 0x20u},\r
-                       {0x03u, 0x02u},\r
+                       {0x01u, 0x24u},\r
+                       {0x03u, 0x42u},\r
                        {0x04u, 0x20u},\r
                        {0x05u, 0x45u},\r
-                       {0x08u, 0x10u},\r
-                       {0x09u, 0x01u},\r
+                       {0x08u, 0x08u},\r
+                       {0x0Au, 0x02u},\r
+                       {0x0Bu, 0x80u},\r
                        {0x0Cu, 0x88u},\r
                        {0x0Eu, 0x04u},\r
-                       {0x10u, 0x01u},\r
-                       {0x11u, 0x08u},\r
-                       {0x12u, 0x04u},\r
+                       {0x10u, 0x04u},\r
                        {0x15u, 0x41u},\r
                        {0x17u, 0x10u},\r
                        {0x19u, 0x20u},\r
@@ -1776,7 +1823,7 @@ void cyfitter_cfg(void)
                        {0x1Cu, 0x04u},\r
                        {0x1Du, 0x05u},\r
                        {0x1Eu, 0x04u},\r
-                       {0x1Fu, 0x1Du},\r
+                       {0x1Fu, 0x19u},\r
                        {0x20u, 0x02u},\r
                        {0x22u, 0x08u},\r
                        {0x23u, 0x01u},\r
@@ -1798,236 +1845,237 @@ void cyfitter_cfg(void)
                        {0x4Du, 0x10u},\r
                        {0x5Eu, 0x80u},\r
                        {0x5Fu, 0x15u},\r
-                       {0x62u, 0xAAu},\r
-                       {0x66u, 0x81u},\r
-                       {0x86u, 0x02u},\r
-                       {0x8Bu, 0x20u},\r
-                       {0x90u, 0x01u},\r
-                       {0x97u, 0x28u},\r
-                       {0x98u, 0x11u},\r
+                       {0x61u, 0x02u},\r
+                       {0x62u, 0xA8u},\r
+                       {0x64u, 0x80u},\r
+                       {0x66u, 0x80u},\r
+                       {0x91u, 0x04u},\r
+                       {0x92u, 0x02u},\r
+                       {0x93u, 0x80u},\r
+                       {0x97u, 0x20u},\r
+                       {0x98u, 0x0Cu},\r
                        {0x99u, 0x08u},\r
-                       {0x9Au, 0x84u},\r
-                       {0x9Cu, 0x40u},\r
+                       {0x9Bu, 0x60u},\r
+                       {0x9Cu, 0xC0u},\r
                        {0x9Du, 0x20u},\r
-                       {0x9Eu, 0x01u},\r
-                       {0x9Fu, 0x30u},\r
-                       {0xA1u, 0x05u},\r
+                       {0x9Fu, 0x10u},\r
                        {0xA4u, 0x40u},\r
-                       {0xA7u, 0x01u},\r
+                       {0xA7u, 0x09u},\r
                        {0xAAu, 0x40u},\r
                        {0xB0u, 0x04u},\r
-                       {0xB1u, 0x44u},\r
-                       {0xC0u, 0xFBu},\r
-                       {0xC2u, 0xEAu},\r
-                       {0xC4u, 0xD7u},\r
+                       {0xB4u, 0x80u},\r
+                       {0xC0u, 0xFFu},\r
+                       {0xC2u, 0xEDu},\r
+                       {0xC4u, 0xD2u},\r
                        {0xCAu, 0xF8u},\r
                        {0xCCu, 0xF2u},\r
                        {0xCEu, 0xEFu},\r
                        {0xD6u, 0xF0u},\r
                        {0xD8u, 0x9Fu},\r
-                       {0xEEu, 0x01u},\r
+                       {0xEAu, 0x12u},\r
+                       {0xEEu, 0x08u},\r
                        {0xB8u, 0x08u},\r
                        {0xBEu, 0x04u},\r
                        {0xD8u, 0x04u},\r
                        {0xDFu, 0x01u},\r
                        {0x1Bu, 0x08u},\r
-                       {0x80u, 0x40u},\r
-                       {0x90u, 0x80u},\r
-                       {0xB2u, 0x08u},\r
                        {0xB3u, 0x08u},\r
-                       {0xE0u, 0x01u},\r
-                       {0xE6u, 0x20u},\r
-                       {0xE8u, 0xA0u},\r
-                       {0xECu, 0x80u},\r
-                       {0xEEu, 0x01u},\r
+                       {0xE8u, 0x20u},\r
+                       {0xEAu, 0x02u},\r
+                       {0xEEu, 0x08u},\r
                        {0xAFu, 0x08u},\r
                        {0xE2u, 0x80u},\r
                        {0x06u, 0x02u},\r
-                       {0x0Fu, 0x02u},\r
+                       {0x0Du, 0x20u},\r
                        {0x12u, 0x08u},\r
+                       {0x13u, 0x02u},\r
                        {0x16u, 0x80u},\r
                        {0x17u, 0x80u},\r
-                       {0x30u, 0x08u},\r
-                       {0x36u, 0x80u},\r
+                       {0x30u, 0x10u},\r
+                       {0x33u, 0x01u},\r
+                       {0x36u, 0x20u},\r
                        {0x37u, 0x04u},\r
                        {0x39u, 0x04u},\r
                        {0x3Au, 0x80u},\r
+                       {0x3Cu, 0x01u},\r
                        {0x3Du, 0x10u},\r
-                       {0x3Eu, 0x04u},\r
-                       {0x41u, 0x20u},\r
+                       {0x40u, 0x02u},\r
                        {0x5Bu, 0x08u},\r
-                       {0x8Bu, 0x01u},\r
+                       {0x6Bu, 0x03u},\r
+                       {0x89u, 0x10u},\r
                        {0xC0u, 0x80u},\r
                        {0xC2u, 0x80u},\r
-                       {0xC4u, 0xE0u},\r
-                       {0xCCu, 0xE0u},\r
+                       {0xC4u, 0xF0u},\r
+                       {0xCCu, 0xF0u},\r
                        {0xCEu, 0xF0u},\r
                        {0xD0u, 0x10u},\r
                        {0xD6u, 0x40u},\r
-                       {0x31u, 0x02u},\r
-                       {0x33u, 0x10u},\r
-                       {0x36u, 0x08u},\r
+                       {0x33u, 0x11u},\r
+                       {0x36u, 0x01u},\r
                        {0x37u, 0x80u},\r
                        {0x39u, 0x80u},\r
                        {0x5Au, 0x10u},\r
-                       {0x5Eu, 0x40u},\r
+                       {0x5Eu, 0x80u},\r
                        {0x63u, 0x02u},\r
-                       {0x82u, 0x40u},\r
-                       {0x88u, 0x08u},\r
-                       {0x96u, 0x04u},\r
+                       {0x8Au, 0x40u},\r
+                       {0x94u, 0x01u},\r
                        {0x9Bu, 0x90u},\r
+                       {0x9Cu, 0x12u},\r
                        {0x9Fu, 0x08u},\r
-                       {0xA4u, 0x08u},\r
-                       {0xA5u, 0x20u},\r
-                       {0xA6u, 0x80u},\r
+                       {0xA1u, 0x20u},\r
+                       {0xA6u, 0x20u},\r
                        {0xAAu, 0x08u},\r
                        {0xABu, 0x14u},\r
-                       {0xADu, 0x14u},\r
+                       {0xADu, 0x04u},\r
                        {0xB6u, 0x02u},\r
                        {0xCCu, 0xF0u},\r
                        {0xCEu, 0x10u},\r
                        {0xD4u, 0x80u},\r
                        {0xD6u, 0x60u},\r
-                       {0xE2u, 0x20u},\r
                        {0xEAu, 0x80u},\r
-                       {0xEEu, 0x50u},\r
-                       {0x12u, 0x80u},\r
-                       {0x32u, 0x40u},\r
-                       {0x8Eu, 0x08u},\r
+                       {0xEEu, 0x40u},\r
+                       {0x10u, 0x10u},\r
+                       {0x31u, 0x40u},\r
+                       {0x94u, 0x01u},\r
                        {0x95u, 0x80u},\r
-                       {0x96u, 0x14u},\r
-                       {0x9Fu, 0x08u},\r
-                       {0xA5u, 0x22u},\r
-                       {0xA6u, 0x88u},\r
+                       {0x96u, 0x10u},\r
+                       {0x9Cu, 0x12u},\r
+                       {0x9Fu, 0x09u},\r
+                       {0xA6u, 0x01u},\r
                        {0xA7u, 0x01u},\r
+                       {0xB1u, 0x20u},\r
+                       {0xB6u, 0x20u},\r
                        {0xC4u, 0x10u},\r
                        {0xCCu, 0x10u},\r
-                       {0x81u, 0x20u},\r
-                       {0x82u, 0x10u},\r
+                       {0x82u, 0x11u},\r
                        {0x87u, 0x01u},\r
-                       {0x96u, 0x94u},\r
-                       {0x9Fu, 0x08u},\r
-                       {0xA5u, 0x20u},\r
+                       {0x94u, 0x01u},\r
+                       {0x96u, 0x10u},\r
+                       {0x9Cu, 0x02u},\r
+                       {0x9Du, 0x40u},\r
+                       {0x9Fu, 0x09u},\r
+                       {0xA6u, 0x01u},\r
                        {0xA7u, 0x01u},\r
                        {0xA9u, 0x40u},\r
-                       {0xB1u, 0x02u},\r
-                       {0xE2u, 0xA0u},\r
-                       {0xE6u, 0x10u},\r
+                       {0xE2u, 0x80u},\r
+                       {0xE6u, 0x90u},\r
                        {0xEAu, 0x80u},\r
-                       {0x01u, 0x20u},\r
-                       {0x07u, 0x02u},\r
-                       {0x0Au, 0x08u},\r
-                       {0x0Eu, 0x01u},\r
+                       {0x02u, 0x01u},\r
+                       {0x07u, 0x08u},\r
+                       {0x09u, 0x80u},\r
+                       {0x0Cu, 0x40u},\r
                        {0x10u, 0x20u},\r
-                       {0x14u, 0x10u},\r
-                       {0x61u, 0x84u},\r
-                       {0x81u, 0x04u},\r
+                       {0x16u, 0x80u},\r
+                       {0x60u, 0x20u},\r
+                       {0x66u, 0x02u},\r
+                       {0x81u, 0x80u},\r
                        {0x8Bu, 0x20u},\r
+                       {0x8Eu, 0x02u},\r
                        {0xC0u, 0x03u},\r
                        {0xC2u, 0x03u},\r
                        {0xC4u, 0x0Cu},\r
-                       {0xD6u, 0x02u},\r
-                       {0xD8u, 0x02u},\r
+                       {0xD8u, 0x03u},\r
+                       {0xE0u, 0x02u},\r
                        {0xE4u, 0x04u},\r
                        {0x00u, 0x08u},\r
-                       {0x07u, 0x40u},\r
+                       {0x05u, 0x04u},\r
                        {0x0Au, 0x20u},\r
-                       {0x0Eu, 0x40u},\r
+                       {0x0Cu, 0x08u},\r
                        {0x52u, 0x80u},\r
                        {0x5Fu, 0x20u},\r
                        {0x66u, 0x84u},\r
-                       {0x81u, 0x20u},\r
-                       {0x8Au, 0x04u},\r
-                       {0x8Du, 0x80u},\r
-                       {0x8Eu, 0x40u},\r
-                       {0x92u, 0x09u},\r
-                       {0x99u, 0x20u},\r
-                       {0x9Au, 0x04u},\r
-                       {0x9Bu, 0x20u},\r
-                       {0xA5u, 0x80u},\r
+                       {0x80u, 0x08u},\r
+                       {0x82u, 0x01u},\r
+                       {0x88u, 0x40u},\r
+                       {0x98u, 0x40u},\r
+                       {0x9Au, 0x05u},\r
+                       {0x9Bu, 0x28u},\r
+                       {0x9Cu, 0x20u},\r
                        {0xAAu, 0x04u},\r
-                       {0xABu, 0x02u},\r
-                       {0xB0u, 0x30u},\r
+                       {0xAEu, 0x80u},\r
+                       {0xB0u, 0x20u},\r
                        {0xC0u, 0x0Cu},\r
                        {0xC2u, 0x0Cu},\r
                        {0xD4u, 0x04u},\r
                        {0xD6u, 0x05u},\r
                        {0xD8u, 0x01u},\r
-                       {0xE0u, 0x08u},\r
                        {0xE2u, 0x01u},\r
-                       {0xE6u, 0x02u},\r
-                       {0xEAu, 0x04u},\r
                        {0xEEu, 0x04u},\r
-                       {0x53u, 0x04u},\r
-                       {0x8Au, 0x01u},\r
-                       {0x8Cu, 0x02u},\r
-                       {0x8Eu, 0x80u},\r
-                       {0x92u, 0x01u},\r
-                       {0x9Bu, 0x40u},\r
+                       {0x83u, 0x20u},\r
+                       {0x8Bu, 0x08u},\r
+                       {0x8Du, 0x04u},\r
+                       {0x99u, 0x04u},\r
+                       {0x9Bu, 0x08u},\r
+                       {0x9Cu, 0x20u},\r
                        {0xAAu, 0x80u},\r
                        {0xB0u, 0x04u},\r
                        {0xB2u, 0x80u},\r
                        {0xB6u, 0x10u},\r
-                       {0xD4u, 0x04u},\r
-                       {0xE4u, 0x08u},\r
-                       {0xE6u, 0x03u},\r
+                       {0xE4u, 0x02u},\r
+                       {0xE6u, 0x01u},\r
                        {0xEAu, 0x06u},\r
                        {0xECu, 0x04u},\r
                        {0x09u, 0x08u},\r
                        {0x0Bu, 0x01u},\r
-                       {0x0Cu, 0x02u},\r
-                       {0x0Eu, 0x02u},\r
-                       {0x97u, 0x09u},\r
-                       {0x9Au, 0x80u},\r
-                       {0xA4u, 0x02u},\r
-                       {0xA5u, 0x08u},\r
+                       {0x0Fu, 0x22u},\r
+                       {0x83u, 0x10u},\r
+                       {0x86u, 0x20u},\r
+                       {0x8Du, 0x10u},\r
+                       {0x97u, 0x01u},\r
+                       {0xA1u, 0x04u},\r
+                       {0xA3u, 0x20u},\r
                        {0xABu, 0x01u},\r
-                       {0xB1u, 0x08u},\r
-                       {0xB7u, 0x40u},\r
+                       {0xACu, 0x20u},\r
+                       {0xB5u, 0x04u},\r
                        {0xC2u, 0x0Fu},\r
+                       {0xE2u, 0x02u},\r
                        {0xEAu, 0x08u},\r
-                       {0xEEu, 0x04u},\r
                        {0x67u, 0x40u},\r
-                       {0x86u, 0x04u},\r
-                       {0x96u, 0x04u},\r
-                       {0xAAu, 0x40u},\r
+                       {0x94u, 0x01u},\r
                        {0xABu, 0x08u},\r
+                       {0xADu, 0x40u},\r
+                       {0xAFu, 0x01u},\r
+                       {0xB4u, 0x02u},\r
                        {0xD8u, 0x80u},\r
-                       {0xE2u, 0x40u},\r
-                       {0xEAu, 0x20u},\r
-                       {0xEEu, 0x80u},\r
+                       {0xEAu, 0x60u},\r
+                       {0xEEu, 0x10u},\r
                        {0x04u, 0x08u},\r
                        {0x51u, 0x10u},\r
                        {0x56u, 0x40u},\r
                        {0x86u, 0x40u},\r
                        {0x89u, 0x10u},\r
                        {0x8Cu, 0x04u},\r
+                       {0xA8u, 0x01u},\r
                        {0xAFu, 0x40u},\r
                        {0xC0u, 0x20u},\r
                        {0xD4u, 0x60u},\r
                        {0xE2u, 0x10u},\r
+                       {0xEAu, 0x80u},\r
                        {0xEEu, 0x40u},\r
-                       {0x81u, 0x08u},\r
-                       {0x8Bu, 0x01u},\r
-                       {0x9Au, 0x80u},\r
-                       {0xAAu, 0x01u},\r
-                       {0xB3u, 0x04u},\r
-                       {0xE6u, 0x04u},\r
-                       {0xE8u, 0x01u},\r
+                       {0x76u, 0x20u},\r
+                       {0x9Au, 0x20u},\r
+                       {0x9Du, 0x10u},\r
+                       {0xA1u, 0x04u},\r
+                       {0xA3u, 0x20u},\r
+                       {0xADu, 0x08u},\r
+                       {0xAFu, 0x01u},\r
+                       {0xDEu, 0x04u},\r
                        {0x01u, 0x10u},\r
-                       {0x07u, 0x01u},\r
-                       {0x51u, 0x08u},\r
-                       {0x56u, 0x80u},\r
+                       {0x05u, 0x10u},\r
+                       {0x53u, 0x20u},\r
+                       {0x55u, 0x04u},\r
                        {0x89u, 0x10u},\r
-                       {0x9Au, 0x80u},\r
-                       {0x9Fu, 0x01u},\r
-                       {0xA1u, 0x08u},\r
+                       {0x9Du, 0x10u},\r
+                       {0xA1u, 0x04u},\r
+                       {0xA3u, 0x20u},\r
                        {0xC0u, 0x03u},\r
                        {0xD4u, 0x06u},\r
                        {0xE2u, 0x01u},\r
                        {0x10u, 0x03u},\r
+                       {0x11u, 0x01u},\r
                        {0x1Au, 0x03u},\r
-                       {0x00u, 0xFDu},\r
+                       {0x1Bu, 0x01u},\r
+                       {0x00u, 0xFFu},\r
                        {0x01u, 0xBFu},\r
                        {0x02u, 0x2Au},\r
                        {0x10u, 0x95u},\r
@@ -2047,7 +2095,7 @@ void cyfitter_cfg(void)
                        uint16 size;\r
                } CYPACKED_ATTR cfg_memcpy_t;\r
 \r
-               static const cfg_memset_t CYCODE cfg_memset_list [] = {\r
+               static const cfg_memset_t CYCODE cfg_memset_list[] = {\r
                        /* address, size */\r
                        {(void CYFAR *)(CYREG_TMR0_CFG0), 12u},\r
                        {(void CYFAR *)(CYDEV_UCFG_B0_P0_U0_BASE), 4096u},\r
@@ -2059,8 +2107,8 @@ void cyfitter_cfg(void)
 \r
                /* UDB_1_0_0_CONFIG Address: CYDEV_UCFG_B1_P2_U0_BASE Size (bytes): 128 */\r
                static const uint8 CYCODE BS_UDB_1_0_0_CONFIG_VAL[] = {\r
-                       0x04u, 0x80u, 0x00u, 0x00u, 0x08u, 0x00u, 0x21u, 0x00u, 0x40u, 0x7Fu, 0x00u, 0x80u, 0x01u, 0xC0u, 0x00u, 0x02u, \r
-                       0x01u, 0x90u, 0x00u, 0x40u, 0x22u, 0xC0u, 0x08u, 0x08u, 0x07u, 0x00u, 0x18u, 0xFFu, 0x01u, 0x00u, 0x00u, 0x9Fu, \r
+                       0x04u, 0x80u, 0x00u, 0x00u, 0x08u, 0x00u, 0x21u, 0x00u, 0x07u, 0x7Fu, 0x18u, 0x80u, 0x01u, 0xC0u, 0x00u, 0x02u, \r
+                       0x01u, 0x90u, 0x00u, 0x40u, 0x22u, 0xC0u, 0x08u, 0x08u, 0x40u, 0x00u, 0x00u, 0xFFu, 0x01u, 0x00u, 0x00u, 0x9Fu, \r
                        0x10u, 0x00u, 0x00u, 0x60u, 0x01u, 0xC0u, 0x00u, 0x04u, 0x40u, 0x1Fu, 0x00u, 0x20u, 0x01u, 0xC0u, 0x00u, 0x01u, \r
                        0x40u, 0x00u, 0x00u, 0xFFu, 0x3Fu, 0x00u, 0x00u, 0x00u, 0x22u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x10u, 0x04u, \r
                        0x62u, 0x03u, 0x50u, 0x00u, 0x01u, 0xBEu, 0xFCu, 0x0Du, 0x1Fu, 0xFFu, 0xFFu, 0xFFu, 0x22u, 0x00u, 0xF0u, 0x08u, \r

diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.h b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.h
index 72521357129e3a5425f7dde53296ab03568cd940..3a40dcb89c8df23cf00f847f24ef27580ddd5c32 100755 (executable)
--- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.h
+++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.h
@@ -1,14 +1,14 @@
 /*******************************************************************************\r
 * File Name: cyfitter_cfg.h\r
 * \r
-* PSoC Creator  4.0 Update 1\r
+* PSoC Creator  4.1\r
 *\r
 * Description:\r
-* This file provides basic startup and mux configration settings\r
+* This file provides basic startup and mux configuration settings\r
 * This file is automatically generated by PSoC Creator.\r
 *\r
 ********************************************************************************\r
-* Copyright (c) 2007-2016 Cypress Semiconductor.  All rights reserved.\r
+* Copyright (c) 2007-2017 Cypress Semiconductor.  All rights reserved.\r
 * You may use this file only in accordance with the license, terms, conditions, \r
 * disclaimers, and limitations in the end user license agreement accompanying \r
 * the software package with which this file was provided.\r

diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfittergnu.inc b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfittergnu.inc
index 07d8d564bba45f6f79dcf9f2b222bfc416f2d418..9a3d42a26b9a57f19091a5100b9f7f5af32415db 100755 (executable)
--- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfittergnu.inc
+++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfittergnu.inc
@@ -1,8 +1,86 @@
+/*******************************************************************************\r
+* File Name: cyfittergnu.inc\r
+* \r
+* PSoC Creator  4.1\r
+*\r
+* Description:\r
+* \r
+* This file is automatically generated by PSoC Creator.\r
+*\r
+********************************************************************************\r
+* Copyright (c) 2007-2017 Cypress Semiconductor.  All rights reserved.\r
+* You may use this file only in accordance with the license, terms, conditions, \r
+* disclaimers, and limitations in the end user license agreement accompanying \r
+* the software package with which this file was provided.\r
+********************************************************************************/\r
+\r
 .ifndef INCLUDED_CYFITTERGNU_INC\r
 .set INCLUDED_CYFITTERGNU_INC, 1\r
 .include "cydevicegnu.inc"\r
 .include "cydevicegnu_trm.inc"\r
 \r
+/* Debug_Timer_Interrupt */\r
+.set Debug_Timer_Interrupt__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
+.set Debug_Timer_Interrupt__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
+.set Debug_Timer_Interrupt__INTC_MASK, 0x01\r
+.set Debug_Timer_Interrupt__INTC_NUMBER, 0\r
+.set Debug_Timer_Interrupt__INTC_PRIOR_NUM, 7\r
+.set Debug_Timer_Interrupt__INTC_PRIOR_REG, CYREG_NVIC_PRI_0\r
+.set Debug_Timer_Interrupt__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
+.set Debug_Timer_Interrupt__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
+\r
+/* Debug_Timer_TimerHW */\r
+.set Debug_Timer_TimerHW__CAP0, CYREG_TMR0_CAP0\r
+.set Debug_Timer_TimerHW__CAP1, CYREG_TMR0_CAP1\r
+.set Debug_Timer_TimerHW__CFG0, CYREG_TMR0_CFG0\r
+.set Debug_Timer_TimerHW__CFG1, CYREG_TMR0_CFG1\r
+.set Debug_Timer_TimerHW__CFG2, CYREG_TMR0_CFG2\r
+.set Debug_Timer_TimerHW__CNT_CMP0, CYREG_TMR0_CNT_CMP0\r
+.set Debug_Timer_TimerHW__CNT_CMP1, CYREG_TMR0_CNT_CMP1\r
+.set Debug_Timer_TimerHW__PER0, CYREG_TMR0_PER0\r
+.set Debug_Timer_TimerHW__PER1, CYREG_TMR0_PER1\r
+.set Debug_Timer_TimerHW__PM_ACT_CFG, CYREG_PM_ACT_CFG3\r
+.set Debug_Timer_TimerHW__PM_ACT_MSK, 0x01\r
+.set Debug_Timer_TimerHW__PM_STBY_CFG, CYREG_PM_STBY_CFG3\r
+.set Debug_Timer_TimerHW__PM_STBY_MSK, 0x01\r
+.set Debug_Timer_TimerHW__RT0, CYREG_TMR0_RT0\r
+.set Debug_Timer_TimerHW__RT1, CYREG_TMR0_RT1\r
+.set Debug_Timer_TimerHW__SR0, CYREG_TMR0_SR0\r
+\r
+/* EXTLED */\r
+.set EXTLED__0__INTTYPE, CYREG_PICU0_INTTYPE0\r
+.set EXTLED__0__MASK, 0x01\r
+.set EXTLED__0__PC, CYREG_PRT0_PC0\r
+.set EXTLED__0__PORT, 0\r
+.set EXTLED__0__SHIFT, 0\r
+.set EXTLED__AG, CYREG_PRT0_AG\r
+.set EXTLED__AMUX, CYREG_PRT0_AMUX\r
+.set EXTLED__BIE, CYREG_PRT0_BIE\r
+.set EXTLED__BIT_MASK, CYREG_PRT0_BIT_MASK\r
+.set EXTLED__BYP, CYREG_PRT0_BYP\r
+.set EXTLED__CTL, CYREG_PRT0_CTL\r
+.set EXTLED__DM0, CYREG_PRT0_DM0\r
+.set EXTLED__DM1, CYREG_PRT0_DM1\r
+.set EXTLED__DM2, CYREG_PRT0_DM2\r
+.set EXTLED__DR, CYREG_PRT0_DR\r
+.set EXTLED__INP_DIS, CYREG_PRT0_INP_DIS\r
+.set EXTLED__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU0_BASE\r
+.set EXTLED__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG\r
+.set EXTLED__LCD_EN, CYREG_PRT0_LCD_EN\r
+.set EXTLED__MASK, 0x01\r
+.set EXTLED__PORT, 0\r
+.set EXTLED__PRT, CYREG_PRT0_PRT\r
+.set EXTLED__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL\r
+.set EXTLED__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN\r
+.set EXTLED__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0\r
+.set EXTLED__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1\r
+.set EXTLED__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0\r
+.set EXTLED__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1\r
+.set EXTLED__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT\r
+.set EXTLED__PS, CYREG_PRT0_PS\r
+.set EXTLED__SHIFT, 0\r
+.set EXTLED__SLW, CYREG_PRT0_SLW\r
+\r
 /* LED1 */\r
 .set LED1__0__INTTYPE, CYREG_PICU0_INTTYPE1\r
 .set LED1__0__MASK, 0x02\r
@@ -37,2421 +115,808 @@
 .set LED1__SHIFT, 1\r
 .set LED1__SLW, CYREG_PRT0_SLW\r
 \r
-/* SD_CD */\r
-.set SD_CD__0__INTTYPE, CYREG_PICU3_INTTYPE5\r
-.set SD_CD__0__MASK, 0x20\r
-.set SD_CD__0__PC, CYREG_PRT3_PC5\r
-.set SD_CD__0__PORT, 3\r
-.set SD_CD__0__SHIFT, 5\r
-.set SD_CD__AG, CYREG_PRT3_AG\r
-.set SD_CD__AMUX, CYREG_PRT3_AMUX\r
-.set SD_CD__BIE, CYREG_PRT3_BIE\r
-.set SD_CD__BIT_MASK, CYREG_PRT3_BIT_MASK\r
-.set SD_CD__BYP, CYREG_PRT3_BYP\r
-.set SD_CD__CTL, CYREG_PRT3_CTL\r
-.set SD_CD__DM0, CYREG_PRT3_DM0\r
-.set SD_CD__DM1, CYREG_PRT3_DM1\r
-.set SD_CD__DM2, CYREG_PRT3_DM2\r
-.set SD_CD__DR, CYREG_PRT3_DR\r
-.set SD_CD__INP_DIS, CYREG_PRT3_INP_DIS\r
-.set SD_CD__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU3_BASE\r
-.set SD_CD__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG\r
-.set SD_CD__LCD_EN, CYREG_PRT3_LCD_EN\r
-.set SD_CD__MASK, 0x20\r
-.set SD_CD__PORT, 3\r
-.set SD_CD__PRT, CYREG_PRT3_PRT\r
-.set SD_CD__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL\r
-.set SD_CD__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN\r
-.set SD_CD__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0\r
-.set SD_CD__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1\r
-.set SD_CD__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0\r
-.set SD_CD__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1\r
-.set SD_CD__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT\r
-.set SD_CD__PS, CYREG_PRT3_PS\r
-.set SD_CD__SHIFT, 5\r
-.set SD_CD__SLW, CYREG_PRT3_SLW\r
-\r
-/* SD_CS */\r
-.set SD_CS__0__INTTYPE, CYREG_PICU3_INTTYPE4\r
-.set SD_CS__0__MASK, 0x10\r
-.set SD_CS__0__PC, CYREG_PRT3_PC4\r
-.set SD_CS__0__PORT, 3\r
-.set SD_CS__0__SHIFT, 4\r
-.set SD_CS__AG, CYREG_PRT3_AG\r
-.set SD_CS__AMUX, CYREG_PRT3_AMUX\r
-.set SD_CS__BIE, CYREG_PRT3_BIE\r
-.set SD_CS__BIT_MASK, CYREG_PRT3_BIT_MASK\r
-.set SD_CS__BYP, CYREG_PRT3_BYP\r
-.set SD_CS__CTL, CYREG_PRT3_CTL\r
-.set SD_CS__DM0, CYREG_PRT3_DM0\r
-.set SD_CS__DM1, CYREG_PRT3_DM1\r
-.set SD_CS__DM2, CYREG_PRT3_DM2\r
-.set SD_CS__DR, CYREG_PRT3_DR\r
-.set SD_CS__INP_DIS, CYREG_PRT3_INP_DIS\r
-.set SD_CS__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU3_BASE\r
-.set SD_CS__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG\r
-.set SD_CS__LCD_EN, CYREG_PRT3_LCD_EN\r
-.set SD_CS__MASK, 0x10\r
-.set SD_CS__PORT, 3\r
-.set SD_CS__PRT, CYREG_PRT3_PRT\r
-.set SD_CS__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL\r
-.set SD_CS__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN\r
-.set SD_CS__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0\r
-.set SD_CS__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1\r
-.set SD_CS__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0\r
-.set SD_CS__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1\r
-.set SD_CS__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT\r
-.set SD_CS__PS, CYREG_PRT3_PS\r
-.set SD_CS__SHIFT, 4\r
-.set SD_CS__SLW, CYREG_PRT3_SLW\r
+/* SCSI_CLK */\r
+.set SCSI_CLK__CFG0, CYREG_CLKDIST_DCFG1_CFG0\r
+.set SCSI_CLK__CFG1, CYREG_CLKDIST_DCFG1_CFG1\r
+.set SCSI_CLK__CFG2, CYREG_CLKDIST_DCFG1_CFG2\r
+.set SCSI_CLK__CFG2_SRC_SEL_MASK, 0x07\r
+.set SCSI_CLK__INDEX, 0x01\r
+.set SCSI_CLK__PM_ACT_CFG, CYREG_PM_ACT_CFG2\r
+.set SCSI_CLK__PM_ACT_MSK, 0x02\r
+.set SCSI_CLK__PM_STBY_CFG, CYREG_PM_STBY_CFG2\r
+.set SCSI_CLK__PM_STBY_MSK, 0x02\r
 \r
-/* USBFS_arb_int */\r
-.set USBFS_arb_int__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
-.set USBFS_arb_int__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
-.set USBFS_arb_int__INTC_MASK, 0x400000\r
-.set USBFS_arb_int__INTC_NUMBER, 22\r
-.set USBFS_arb_int__INTC_PRIOR_NUM, 6\r
-.set USBFS_arb_int__INTC_PRIOR_REG, CYREG_NVIC_PRI_22\r
-.set USBFS_arb_int__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
-.set USBFS_arb_int__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
+/* SCSI_CTL_PHASE */\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK, 0x01\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS, 0\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK, 0x02\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS, 1\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB06_07_ACTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB06_07_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB06_07_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB06_07_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB06_07_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB06_07_MSK\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB06_07_MSK\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB06_07_MSK\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB06_07_MSK\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK, 0x04\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS, 2\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB06_ACTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB06_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB06_ST_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB06_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB06_ST_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK, 0x07\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB06_MSK_ACTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB06_MSK_ACTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB06_MSK\r
 \r
-/* USBFS_bus_reset */\r
-.set USBFS_bus_reset__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
-.set USBFS_bus_reset__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
-.set USBFS_bus_reset__INTC_MASK, 0x800000\r
-.set USBFS_bus_reset__INTC_NUMBER, 23\r
-.set USBFS_bus_reset__INTC_PRIOR_NUM, 7\r
-.set USBFS_bus_reset__INTC_PRIOR_REG, CYREG_NVIC_PRI_23\r
-.set USBFS_bus_reset__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
-.set USBFS_bus_reset__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
+/* SCSI_Filtered */\r
+.set SCSI_Filtered_sts_sts_reg__0__MASK, 0x01\r
+.set SCSI_Filtered_sts_sts_reg__0__POS, 0\r
+.set SCSI_Filtered_sts_sts_reg__1__MASK, 0x02\r
+.set SCSI_Filtered_sts_sts_reg__1__POS, 1\r
+.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB11_12_ACTL\r
+.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB11_12_ST\r
+.set SCSI_Filtered_sts_sts_reg__2__MASK, 0x04\r
+.set SCSI_Filtered_sts_sts_reg__2__POS, 2\r
+.set SCSI_Filtered_sts_sts_reg__3__MASK, 0x08\r
+.set SCSI_Filtered_sts_sts_reg__3__POS, 3\r
+.set SCSI_Filtered_sts_sts_reg__4__MASK, 0x10\r
+.set SCSI_Filtered_sts_sts_reg__4__POS, 4\r
+.set SCSI_Filtered_sts_sts_reg__MASK, 0x1F\r
+.set SCSI_Filtered_sts_sts_reg__MASK_REG, CYREG_B0_UDB11_MSK\r
+.set SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB11_ACTL\r
+.set SCSI_Filtered_sts_sts_reg__STATUS_REG, CYREG_B0_UDB11_ST\r
 \r
-/* USBFS_Dm */\r
-.set USBFS_Dm__0__INTTYPE, CYREG_PICU15_INTTYPE7\r
-.set USBFS_Dm__0__MASK, 0x80\r
-.set USBFS_Dm__0__PC, CYREG_IO_PC_PRT15_7_6_PC1\r
-.set USBFS_Dm__0__PORT, 15\r
-.set USBFS_Dm__0__SHIFT, 7\r
-.set USBFS_Dm__AG, CYREG_PRT15_AG\r
-.set USBFS_Dm__AMUX, CYREG_PRT15_AMUX\r
-.set USBFS_Dm__BIE, CYREG_PRT15_BIE\r
-.set USBFS_Dm__BIT_MASK, CYREG_PRT15_BIT_MASK\r
-.set USBFS_Dm__BYP, CYREG_PRT15_BYP\r
-.set USBFS_Dm__CTL, CYREG_PRT15_CTL\r
-.set USBFS_Dm__DM0, CYREG_PRT15_DM0\r
-.set USBFS_Dm__DM1, CYREG_PRT15_DM1\r
-.set USBFS_Dm__DM2, CYREG_PRT15_DM2\r
-.set USBFS_Dm__DR, CYREG_PRT15_DR\r
-.set USBFS_Dm__INP_DIS, CYREG_PRT15_INP_DIS\r
-.set USBFS_Dm__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU15_BASE\r
-.set USBFS_Dm__LCD_COM_SEG, CYREG_PRT15_LCD_COM_SEG\r
-.set USBFS_Dm__LCD_EN, CYREG_PRT15_LCD_EN\r
-.set USBFS_Dm__MASK, 0x80\r
-.set USBFS_Dm__PORT, 15\r
-.set USBFS_Dm__PRT, CYREG_PRT15_PRT\r
-.set USBFS_Dm__PRTDSI__CAPS_SEL, CYREG_PRT15_CAPS_SEL\r
-.set USBFS_Dm__PRTDSI__DBL_SYNC_IN, CYREG_PRT15_DBL_SYNC_IN\r
-.set USBFS_Dm__PRTDSI__OE_SEL0, CYREG_PRT15_OE_SEL0\r
-.set USBFS_Dm__PRTDSI__OE_SEL1, CYREG_PRT15_OE_SEL1\r
-.set USBFS_Dm__PRTDSI__OUT_SEL0, CYREG_PRT15_OUT_SEL0\r
-.set USBFS_Dm__PRTDSI__OUT_SEL1, CYREG_PRT15_OUT_SEL1\r
-.set USBFS_Dm__PRTDSI__SYNC_OUT, CYREG_PRT15_SYNC_OUT\r
-.set USBFS_Dm__PS, CYREG_PRT15_PS\r
-.set USBFS_Dm__SHIFT, 7\r
-.set USBFS_Dm__SLW, CYREG_PRT15_SLW\r
+/* SCSI_Glitch_Ctl */\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK, 0x01\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS, 0\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB04_05_ACTL\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB04_05_CTL\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB04_05_CTL\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB04_05_CTL\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB04_05_CTL\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB04_05_MSK\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB04_05_MSK\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB04_05_MSK\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB04_05_MSK\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB04_ACTL\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB04_CTL\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB04_ST_CTL\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB04_CTL\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB04_ST_CTL\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK, 0x01\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB04_MSK\r
 \r
-/* USBFS_Dp */\r
-.set USBFS_Dp__0__INTTYPE, CYREG_PICU15_INTTYPE6\r
-.set USBFS_Dp__0__MASK, 0x40\r
-.set USBFS_Dp__0__PC, CYREG_IO_PC_PRT15_7_6_PC0\r
-.set USBFS_Dp__0__PORT, 15\r
-.set USBFS_Dp__0__SHIFT, 6\r
-.set USBFS_Dp__AG, CYREG_PRT15_AG\r
-.set USBFS_Dp__AMUX, CYREG_PRT15_AMUX\r
-.set USBFS_Dp__BIE, CYREG_PRT15_BIE\r
-.set USBFS_Dp__BIT_MASK, CYREG_PRT15_BIT_MASK\r
-.set USBFS_Dp__BYP, CYREG_PRT15_BYP\r
-.set USBFS_Dp__CTL, CYREG_PRT15_CTL\r
-.set USBFS_Dp__DM0, CYREG_PRT15_DM0\r
-.set USBFS_Dp__DM1, CYREG_PRT15_DM1\r
-.set USBFS_Dp__DM2, CYREG_PRT15_DM2\r
-.set USBFS_Dp__DR, CYREG_PRT15_DR\r
-.set USBFS_Dp__INP_DIS, CYREG_PRT15_INP_DIS\r
-.set USBFS_Dp__INTSTAT, CYREG_PICU15_INTSTAT\r
-.set USBFS_Dp__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU15_BASE\r
-.set USBFS_Dp__LCD_COM_SEG, CYREG_PRT15_LCD_COM_SEG\r
-.set USBFS_Dp__LCD_EN, CYREG_PRT15_LCD_EN\r
-.set USBFS_Dp__MASK, 0x40\r
-.set USBFS_Dp__PORT, 15\r
-.set USBFS_Dp__PRT, CYREG_PRT15_PRT\r
-.set USBFS_Dp__PRTDSI__CAPS_SEL, CYREG_PRT15_CAPS_SEL\r
-.set USBFS_Dp__PRTDSI__DBL_SYNC_IN, CYREG_PRT15_DBL_SYNC_IN\r
-.set USBFS_Dp__PRTDSI__OE_SEL0, CYREG_PRT15_OE_SEL0\r
-.set USBFS_Dp__PRTDSI__OE_SEL1, CYREG_PRT15_OE_SEL1\r
-.set USBFS_Dp__PRTDSI__OUT_SEL0, CYREG_PRT15_OUT_SEL0\r
-.set USBFS_Dp__PRTDSI__OUT_SEL1, CYREG_PRT15_OUT_SEL1\r
-.set USBFS_Dp__PRTDSI__SYNC_OUT, CYREG_PRT15_SYNC_OUT\r
-.set USBFS_Dp__PS, CYREG_PRT15_PS\r
-.set USBFS_Dp__SHIFT, 6\r
-.set USBFS_Dp__SLW, CYREG_PRT15_SLW\r
-.set USBFS_Dp__SNAP, CYREG_PICU_15_SNAP_15\r
-\r
-/* USBFS_dp_int */\r
-.set USBFS_dp_int__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
-.set USBFS_dp_int__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
-.set USBFS_dp_int__INTC_MASK, 0x1000\r
-.set USBFS_dp_int__INTC_NUMBER, 12\r
-.set USBFS_dp_int__INTC_PRIOR_NUM, 7\r
-.set USBFS_dp_int__INTC_PRIOR_REG, CYREG_NVIC_PRI_12\r
-.set USBFS_dp_int__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
-.set USBFS_dp_int__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
-\r
-/* USBFS_ep_0 */\r
-.set USBFS_ep_0__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
-.set USBFS_ep_0__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
-.set USBFS_ep_0__INTC_MASK, 0x1000000\r
-.set USBFS_ep_0__INTC_NUMBER, 24\r
-.set USBFS_ep_0__INTC_PRIOR_NUM, 7\r
-.set USBFS_ep_0__INTC_PRIOR_REG, CYREG_NVIC_PRI_24\r
-.set USBFS_ep_0__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
-.set USBFS_ep_0__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
-\r
-/* USBFS_ep_1 */\r
-.set USBFS_ep_1__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
-.set USBFS_ep_1__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
-.set USBFS_ep_1__INTC_MASK, 0x80\r
-.set USBFS_ep_1__INTC_NUMBER, 7\r
-.set USBFS_ep_1__INTC_PRIOR_NUM, 7\r
-.set USBFS_ep_1__INTC_PRIOR_REG, CYREG_NVIC_PRI_7\r
-.set USBFS_ep_1__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
-.set USBFS_ep_1__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
-\r
-/* USBFS_ep_2 */\r
-.set USBFS_ep_2__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
-.set USBFS_ep_2__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
-.set USBFS_ep_2__INTC_MASK, 0x100\r
-.set USBFS_ep_2__INTC_NUMBER, 8\r
-.set USBFS_ep_2__INTC_PRIOR_NUM, 7\r
-.set USBFS_ep_2__INTC_PRIOR_REG, CYREG_NVIC_PRI_8\r
-.set USBFS_ep_2__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
-.set USBFS_ep_2__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
-\r
-/* USBFS_ep_3 */\r
-.set USBFS_ep_3__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
-.set USBFS_ep_3__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
-.set USBFS_ep_3__INTC_MASK, 0x200\r
-.set USBFS_ep_3__INTC_NUMBER, 9\r
-.set USBFS_ep_3__INTC_PRIOR_NUM, 7\r
-.set USBFS_ep_3__INTC_PRIOR_REG, CYREG_NVIC_PRI_9\r
-.set USBFS_ep_3__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
-.set USBFS_ep_3__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
-\r
-/* USBFS_ep_4 */\r
-.set USBFS_ep_4__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
-.set USBFS_ep_4__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
-.set USBFS_ep_4__INTC_MASK, 0x400\r
-.set USBFS_ep_4__INTC_NUMBER, 10\r
-.set USBFS_ep_4__INTC_PRIOR_NUM, 7\r
-.set USBFS_ep_4__INTC_PRIOR_REG, CYREG_NVIC_PRI_10\r
-.set USBFS_ep_4__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
-.set USBFS_ep_4__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
-\r
-/* USBFS_sof_int */\r
-.set USBFS_sof_int__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
-.set USBFS_sof_int__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
-.set USBFS_sof_int__INTC_MASK, 0x200000\r
-.set USBFS_sof_int__INTC_NUMBER, 21\r
-.set USBFS_sof_int__INTC_PRIOR_NUM, 7\r
-.set USBFS_sof_int__INTC_PRIOR_REG, CYREG_NVIC_PRI_21\r
-.set USBFS_sof_int__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
-.set USBFS_sof_int__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
-\r
-/* USBFS_USB */\r
-.set USBFS_USB__ARB_CFG, CYREG_USB_ARB_CFG\r
-.set USBFS_USB__ARB_EP1_CFG, CYREG_USB_ARB_EP1_CFG\r
-.set USBFS_USB__ARB_EP1_INT_EN, CYREG_USB_ARB_EP1_INT_EN\r
-.set USBFS_USB__ARB_EP1_SR, CYREG_USB_ARB_EP1_SR\r
-.set USBFS_USB__ARB_EP2_CFG, CYREG_USB_ARB_EP2_CFG\r
-.set USBFS_USB__ARB_EP2_INT_EN, CYREG_USB_ARB_EP2_INT_EN\r
-.set USBFS_USB__ARB_EP2_SR, CYREG_USB_ARB_EP2_SR\r
-.set USBFS_USB__ARB_EP3_CFG, CYREG_USB_ARB_EP3_CFG\r
-.set USBFS_USB__ARB_EP3_INT_EN, CYREG_USB_ARB_EP3_INT_EN\r
-.set USBFS_USB__ARB_EP3_SR, CYREG_USB_ARB_EP3_SR\r
-.set USBFS_USB__ARB_EP4_CFG, CYREG_USB_ARB_EP4_CFG\r
-.set USBFS_USB__ARB_EP4_INT_EN, CYREG_USB_ARB_EP4_INT_EN\r
-.set USBFS_USB__ARB_EP4_SR, CYREG_USB_ARB_EP4_SR\r
-.set USBFS_USB__ARB_EP5_CFG, CYREG_USB_ARB_EP5_CFG\r
-.set USBFS_USB__ARB_EP5_INT_EN, CYREG_USB_ARB_EP5_INT_EN\r
-.set USBFS_USB__ARB_EP5_SR, CYREG_USB_ARB_EP5_SR\r
-.set USBFS_USB__ARB_EP6_CFG, CYREG_USB_ARB_EP6_CFG\r
-.set USBFS_USB__ARB_EP6_INT_EN, CYREG_USB_ARB_EP6_INT_EN\r
-.set USBFS_USB__ARB_EP6_SR, CYREG_USB_ARB_EP6_SR\r
-.set USBFS_USB__ARB_EP7_CFG, CYREG_USB_ARB_EP7_CFG\r
-.set USBFS_USB__ARB_EP7_INT_EN, CYREG_USB_ARB_EP7_INT_EN\r
-.set USBFS_USB__ARB_EP7_SR, CYREG_USB_ARB_EP7_SR\r
-.set USBFS_USB__ARB_EP8_CFG, CYREG_USB_ARB_EP8_CFG\r
-.set USBFS_USB__ARB_EP8_INT_EN, CYREG_USB_ARB_EP8_INT_EN\r
-.set USBFS_USB__ARB_EP8_SR, CYREG_USB_ARB_EP8_SR\r
-.set USBFS_USB__ARB_INT_EN, CYREG_USB_ARB_INT_EN\r
-.set USBFS_USB__ARB_INT_SR, CYREG_USB_ARB_INT_SR\r
-.set USBFS_USB__ARB_RW1_DR, CYREG_USB_ARB_RW1_DR\r
-.set USBFS_USB__ARB_RW1_RA, CYREG_USB_ARB_RW1_RA\r
-.set USBFS_USB__ARB_RW1_RA_MSB, CYREG_USB_ARB_RW1_RA_MSB\r
-.set USBFS_USB__ARB_RW1_WA, CYREG_USB_ARB_RW1_WA\r
-.set USBFS_USB__ARB_RW1_WA_MSB, CYREG_USB_ARB_RW1_WA_MSB\r
-.set USBFS_USB__ARB_RW2_DR, CYREG_USB_ARB_RW2_DR\r
-.set USBFS_USB__ARB_RW2_RA, CYREG_USB_ARB_RW2_RA\r
-.set USBFS_USB__ARB_RW2_RA_MSB, CYREG_USB_ARB_RW2_RA_MSB\r
-.set USBFS_USB__ARB_RW2_WA, CYREG_USB_ARB_RW2_WA\r
-.set USBFS_USB__ARB_RW2_WA_MSB, CYREG_USB_ARB_RW2_WA_MSB\r
-.set USBFS_USB__ARB_RW3_DR, CYREG_USB_ARB_RW3_DR\r
-.set USBFS_USB__ARB_RW3_RA, CYREG_USB_ARB_RW3_RA\r
-.set USBFS_USB__ARB_RW3_RA_MSB, CYREG_USB_ARB_RW3_RA_MSB\r
-.set USBFS_USB__ARB_RW3_WA, CYREG_USB_ARB_RW3_WA\r
-.set USBFS_USB__ARB_RW3_WA_MSB, CYREG_USB_ARB_RW3_WA_MSB\r
-.set USBFS_USB__ARB_RW4_DR, CYREG_USB_ARB_RW4_DR\r
-.set USBFS_USB__ARB_RW4_RA, CYREG_USB_ARB_RW4_RA\r
-.set USBFS_USB__ARB_RW4_RA_MSB, CYREG_USB_ARB_RW4_RA_MSB\r
-.set USBFS_USB__ARB_RW4_WA, CYREG_USB_ARB_RW4_WA\r
-.set USBFS_USB__ARB_RW4_WA_MSB, CYREG_USB_ARB_RW4_WA_MSB\r
-.set USBFS_USB__ARB_RW5_DR, CYREG_USB_ARB_RW5_DR\r
-.set USBFS_USB__ARB_RW5_RA, CYREG_USB_ARB_RW5_RA\r
-.set USBFS_USB__ARB_RW5_RA_MSB, CYREG_USB_ARB_RW5_RA_MSB\r
-.set USBFS_USB__ARB_RW5_WA, CYREG_USB_ARB_RW5_WA\r
-.set USBFS_USB__ARB_RW5_WA_MSB, CYREG_USB_ARB_RW5_WA_MSB\r
-.set USBFS_USB__ARB_RW6_DR, CYREG_USB_ARB_RW6_DR\r
-.set USBFS_USB__ARB_RW6_RA, CYREG_USB_ARB_RW6_RA\r
-.set USBFS_USB__ARB_RW6_RA_MSB, CYREG_USB_ARB_RW6_RA_MSB\r
-.set USBFS_USB__ARB_RW6_WA, CYREG_USB_ARB_RW6_WA\r
-.set USBFS_USB__ARB_RW6_WA_MSB, CYREG_USB_ARB_RW6_WA_MSB\r
-.set USBFS_USB__ARB_RW7_DR, CYREG_USB_ARB_RW7_DR\r
-.set USBFS_USB__ARB_RW7_RA, CYREG_USB_ARB_RW7_RA\r
-.set USBFS_USB__ARB_RW7_RA_MSB, CYREG_USB_ARB_RW7_RA_MSB\r
-.set USBFS_USB__ARB_RW7_WA, CYREG_USB_ARB_RW7_WA\r
-.set USBFS_USB__ARB_RW7_WA_MSB, CYREG_USB_ARB_RW7_WA_MSB\r
-.set USBFS_USB__ARB_RW8_DR, CYREG_USB_ARB_RW8_DR\r
-.set USBFS_USB__ARB_RW8_RA, CYREG_USB_ARB_RW8_RA\r
-.set USBFS_USB__ARB_RW8_RA_MSB, CYREG_USB_ARB_RW8_RA_MSB\r
-.set USBFS_USB__ARB_RW8_WA, CYREG_USB_ARB_RW8_WA\r
-.set USBFS_USB__ARB_RW8_WA_MSB, CYREG_USB_ARB_RW8_WA_MSB\r
-.set USBFS_USB__BUF_SIZE, CYREG_USB_BUF_SIZE\r
-.set USBFS_USB__BUS_RST_CNT, CYREG_USB_BUS_RST_CNT\r
-.set USBFS_USB__CR0, CYREG_USB_CR0\r
-.set USBFS_USB__CR1, CYREG_USB_CR1\r
-.set USBFS_USB__CWA, CYREG_USB_CWA\r
-.set USBFS_USB__CWA_MSB, CYREG_USB_CWA_MSB\r
-.set USBFS_USB__DMA_THRES, CYREG_USB_DMA_THRES\r
-.set USBFS_USB__DMA_THRES_MSB, CYREG_USB_DMA_THRES_MSB\r
-.set USBFS_USB__DYN_RECONFIG, CYREG_USB_DYN_RECONFIG\r
-.set USBFS_USB__EP_ACTIVE, CYREG_USB_EP_ACTIVE\r
-.set USBFS_USB__EP_TYPE, CYREG_USB_EP_TYPE\r
-.set USBFS_USB__EP0_CNT, CYREG_USB_EP0_CNT\r
-.set USBFS_USB__EP0_CR, CYREG_USB_EP0_CR\r
-.set USBFS_USB__EP0_DR0, CYREG_USB_EP0_DR0\r
-.set USBFS_USB__EP0_DR1, CYREG_USB_EP0_DR1\r
-.set USBFS_USB__EP0_DR2, CYREG_USB_EP0_DR2\r
-.set USBFS_USB__EP0_DR3, CYREG_USB_EP0_DR3\r
-.set USBFS_USB__EP0_DR4, CYREG_USB_EP0_DR4\r
-.set USBFS_USB__EP0_DR5, CYREG_USB_EP0_DR5\r
-.set USBFS_USB__EP0_DR6, CYREG_USB_EP0_DR6\r
-.set USBFS_USB__EP0_DR7, CYREG_USB_EP0_DR7\r
-.set USBFS_USB__MEM_DATA, CYREG_USB_MEM_DATA_MBASE\r
-.set USBFS_USB__PM_ACT_CFG, CYREG_PM_ACT_CFG5\r
-.set USBFS_USB__PM_ACT_MSK, 0x01\r
-.set USBFS_USB__PM_STBY_CFG, CYREG_PM_STBY_CFG5\r
-.set USBFS_USB__PM_STBY_MSK, 0x01\r
-.set USBFS_USB__SIE_EP_INT_EN, CYREG_USB_SIE_EP_INT_EN\r
-.set USBFS_USB__SIE_EP_INT_SR, CYREG_USB_SIE_EP_INT_SR\r
-.set USBFS_USB__SIE_EP1_CNT0, CYREG_USB_SIE_EP1_CNT0\r
-.set USBFS_USB__SIE_EP1_CNT1, CYREG_USB_SIE_EP1_CNT1\r
-.set USBFS_USB__SIE_EP1_CR0, CYREG_USB_SIE_EP1_CR0\r
-.set USBFS_USB__SIE_EP2_CNT0, CYREG_USB_SIE_EP2_CNT0\r
-.set USBFS_USB__SIE_EP2_CNT1, CYREG_USB_SIE_EP2_CNT1\r
-.set USBFS_USB__SIE_EP2_CR0, CYREG_USB_SIE_EP2_CR0\r
-.set USBFS_USB__SIE_EP3_CNT0, CYREG_USB_SIE_EP3_CNT0\r
-.set USBFS_USB__SIE_EP3_CNT1, CYREG_USB_SIE_EP3_CNT1\r
-.set USBFS_USB__SIE_EP3_CR0, CYREG_USB_SIE_EP3_CR0\r
-.set USBFS_USB__SIE_EP4_CNT0, CYREG_USB_SIE_EP4_CNT0\r
-.set USBFS_USB__SIE_EP4_CNT1, CYREG_USB_SIE_EP4_CNT1\r
-.set USBFS_USB__SIE_EP4_CR0, CYREG_USB_SIE_EP4_CR0\r
-.set USBFS_USB__SIE_EP5_CNT0, CYREG_USB_SIE_EP5_CNT0\r
-.set USBFS_USB__SIE_EP5_CNT1, CYREG_USB_SIE_EP5_CNT1\r
-.set USBFS_USB__SIE_EP5_CR0, CYREG_USB_SIE_EP5_CR0\r
-.set USBFS_USB__SIE_EP6_CNT0, CYREG_USB_SIE_EP6_CNT0\r
-.set USBFS_USB__SIE_EP6_CNT1, CYREG_USB_SIE_EP6_CNT1\r
-.set USBFS_USB__SIE_EP6_CR0, CYREG_USB_SIE_EP6_CR0\r
-.set USBFS_USB__SIE_EP7_CNT0, CYREG_USB_SIE_EP7_CNT0\r
-.set USBFS_USB__SIE_EP7_CNT1, CYREG_USB_SIE_EP7_CNT1\r
-.set USBFS_USB__SIE_EP7_CR0, CYREG_USB_SIE_EP7_CR0\r
-.set USBFS_USB__SIE_EP8_CNT0, CYREG_USB_SIE_EP8_CNT0\r
-.set USBFS_USB__SIE_EP8_CNT1, CYREG_USB_SIE_EP8_CNT1\r
-.set USBFS_USB__SIE_EP8_CR0, CYREG_USB_SIE_EP8_CR0\r
-.set USBFS_USB__SOF0, CYREG_USB_SOF0\r
-.set USBFS_USB__SOF1, CYREG_USB_SOF1\r
-.set USBFS_USB__USB_CLK_EN, CYREG_USB_USB_CLK_EN\r
-.set USBFS_USB__USBIO_CR0, CYREG_USB_USBIO_CR0\r
-.set USBFS_USB__USBIO_CR1, CYREG_USB_USBIO_CR1\r
-\r
-/* EXTLED */\r
-.set EXTLED__0__INTTYPE, CYREG_PICU0_INTTYPE0\r
-.set EXTLED__0__MASK, 0x01\r
-.set EXTLED__0__PC, CYREG_PRT0_PC0\r
-.set EXTLED__0__PORT, 0\r
-.set EXTLED__0__SHIFT, 0\r
-.set EXTLED__AG, CYREG_PRT0_AG\r
-.set EXTLED__AMUX, CYREG_PRT0_AMUX\r
-.set EXTLED__BIE, CYREG_PRT0_BIE\r
-.set EXTLED__BIT_MASK, CYREG_PRT0_BIT_MASK\r
-.set EXTLED__BYP, CYREG_PRT0_BYP\r
-.set EXTLED__CTL, CYREG_PRT0_CTL\r
-.set EXTLED__DM0, CYREG_PRT0_DM0\r
-.set EXTLED__DM1, CYREG_PRT0_DM1\r
-.set EXTLED__DM2, CYREG_PRT0_DM2\r
-.set EXTLED__DR, CYREG_PRT0_DR\r
-.set EXTLED__INP_DIS, CYREG_PRT0_INP_DIS\r
-.set EXTLED__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU0_BASE\r
-.set EXTLED__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG\r
-.set EXTLED__LCD_EN, CYREG_PRT0_LCD_EN\r
-.set EXTLED__MASK, 0x01\r
-.set EXTLED__PORT, 0\r
-.set EXTLED__PRT, CYREG_PRT0_PRT\r
-.set EXTLED__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL\r
-.set EXTLED__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN\r
-.set EXTLED__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0\r
-.set EXTLED__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1\r
-.set EXTLED__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0\r
-.set EXTLED__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1\r
-.set EXTLED__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT\r
-.set EXTLED__PS, CYREG_PRT0_PS\r
-.set EXTLED__SHIFT, 0\r
-.set EXTLED__SLW, CYREG_PRT0_SLW\r
-\r
-/* SDCard_BSPIM */\r
-.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB05_06_ACTL\r
-.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB05_06_CTL\r
-.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB05_06_CTL\r
-.set SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB05_06_CTL\r
-.set SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB05_06_CTL\r
-.set SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B1_UDB05_06_MSK\r
-.set SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB05_06_MSK\r
-.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB05_06_MSK\r
-.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB05_06_MSK\r
-.set SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B1_UDB05_ACTL\r
-.set SDCard_BSPIM_BitCounter__CONTROL_REG, CYREG_B1_UDB05_CTL\r
-.set SDCard_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B1_UDB05_ST_CTL\r
-.set SDCard_BSPIM_BitCounter__COUNT_REG, CYREG_B1_UDB05_CTL\r
-.set SDCard_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B1_UDB05_ST_CTL\r
-.set SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB05_MSK_ACTL\r
-.set SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB05_MSK_ACTL\r
-.set SDCard_BSPIM_BitCounter__PERIOD_REG, CYREG_B1_UDB05_MSK\r
-.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB05_06_ACTL\r
-.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B1_UDB05_06_ST\r
-.set SDCard_BSPIM_BitCounter_ST__MASK_REG, CYREG_B1_UDB05_MSK\r
-.set SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B1_UDB05_MSK_ACTL\r
-.set SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B1_UDB05_MSK_ACTL\r
-.set SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B1_UDB05_ACTL\r
-.set SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B1_UDB05_ST_CTL\r
-.set SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B1_UDB05_ST_CTL\r
-.set SDCard_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B1_UDB05_ST\r
-.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB07_08_ACTL\r
-.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB07_08_ST\r
-.set SDCard_BSPIM_RxStsReg__4__MASK, 0x10\r
-.set SDCard_BSPIM_RxStsReg__4__POS, 4\r
-.set SDCard_BSPIM_RxStsReg__5__MASK, 0x20\r
-.set SDCard_BSPIM_RxStsReg__5__POS, 5\r
-.set SDCard_BSPIM_RxStsReg__6__MASK, 0x40\r
-.set SDCard_BSPIM_RxStsReg__6__POS, 6\r
-.set SDCard_BSPIM_RxStsReg__MASK, 0x70\r
-.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B1_UDB07_MSK\r
-.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB07_ACTL\r
-.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B1_UDB07_ST\r
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG, CYREG_B1_UDB04_05_A0\r
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG, CYREG_B1_UDB04_05_A1\r
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG, CYREG_B1_UDB04_05_D0\r
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG, CYREG_B1_UDB04_05_D1\r
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG, CYREG_B1_UDB04_05_ACTL\r
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG, CYREG_B1_UDB04_05_F0\r
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG, CYREG_B1_UDB04_05_F1\r
-.set SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG, CYREG_B1_UDB04_A0_A1\r
-.set SDCard_BSPIM_sR8_Dp_u0__A0_REG, CYREG_B1_UDB04_A0\r
-.set SDCard_BSPIM_sR8_Dp_u0__A1_REG, CYREG_B1_UDB04_A1\r
-.set SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG, CYREG_B1_UDB04_D0_D1\r
-.set SDCard_BSPIM_sR8_Dp_u0__D0_REG, CYREG_B1_UDB04_D0\r
-.set SDCard_BSPIM_sR8_Dp_u0__D1_REG, CYREG_B1_UDB04_D1\r
-.set SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG, CYREG_B1_UDB04_ACTL\r
-.set SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG, CYREG_B1_UDB04_F0_F1\r
-.set SDCard_BSPIM_sR8_Dp_u0__F0_REG, CYREG_B1_UDB04_F0\r
-.set SDCard_BSPIM_sR8_Dp_u0__F1_REG, CYREG_B1_UDB04_F1\r
-.set SDCard_BSPIM_TxStsReg__0__MASK, 0x01\r
-.set SDCard_BSPIM_TxStsReg__0__POS, 0\r
-.set SDCard_BSPIM_TxStsReg__1__MASK, 0x02\r
-.set SDCard_BSPIM_TxStsReg__1__POS, 1\r
-.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB06_07_ACTL\r
-.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB06_07_ST\r
-.set SDCard_BSPIM_TxStsReg__2__MASK, 0x04\r
-.set SDCard_BSPIM_TxStsReg__2__POS, 2\r
-.set SDCard_BSPIM_TxStsReg__3__MASK, 0x08\r
-.set SDCard_BSPIM_TxStsReg__3__POS, 3\r
-.set SDCard_BSPIM_TxStsReg__4__MASK, 0x10\r
-.set SDCard_BSPIM_TxStsReg__4__POS, 4\r
-.set SDCard_BSPIM_TxStsReg__MASK, 0x1F\r
-.set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B1_UDB06_MSK\r
-.set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB06_ACTL\r
-.set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B1_UDB06_ST\r
-\r
-/* SD_SCK */\r
-.set SD_SCK__0__INTTYPE, CYREG_PICU3_INTTYPE2\r
-.set SD_SCK__0__MASK, 0x04\r
-.set SD_SCK__0__PC, CYREG_PRT3_PC2\r
-.set SD_SCK__0__PORT, 3\r
-.set SD_SCK__0__SHIFT, 2\r
-.set SD_SCK__AG, CYREG_PRT3_AG\r
-.set SD_SCK__AMUX, CYREG_PRT3_AMUX\r
-.set SD_SCK__BIE, CYREG_PRT3_BIE\r
-.set SD_SCK__BIT_MASK, CYREG_PRT3_BIT_MASK\r
-.set SD_SCK__BYP, CYREG_PRT3_BYP\r
-.set SD_SCK__CTL, CYREG_PRT3_CTL\r
-.set SD_SCK__DM0, CYREG_PRT3_DM0\r
-.set SD_SCK__DM1, CYREG_PRT3_DM1\r
-.set SD_SCK__DM2, CYREG_PRT3_DM2\r
-.set SD_SCK__DR, CYREG_PRT3_DR\r
-.set SD_SCK__INP_DIS, CYREG_PRT3_INP_DIS\r
-.set SD_SCK__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU3_BASE\r
-.set SD_SCK__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG\r
-.set SD_SCK__LCD_EN, CYREG_PRT3_LCD_EN\r
-.set SD_SCK__MASK, 0x04\r
-.set SD_SCK__PORT, 3\r
-.set SD_SCK__PRT, CYREG_PRT3_PRT\r
-.set SD_SCK__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL\r
-.set SD_SCK__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN\r
-.set SD_SCK__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0\r
-.set SD_SCK__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1\r
-.set SD_SCK__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0\r
-.set SD_SCK__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1\r
-.set SD_SCK__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT\r
-.set SD_SCK__PS, CYREG_PRT3_PS\r
-.set SD_SCK__SHIFT, 2\r
-.set SD_SCK__SLW, CYREG_PRT3_SLW\r
-\r
-/* SCSI_In */\r
-.set SCSI_In__0__AG, CYREG_PRT2_AG\r
-.set SCSI_In__0__AMUX, CYREG_PRT2_AMUX\r
-.set SCSI_In__0__BIE, CYREG_PRT2_BIE\r
-.set SCSI_In__0__BIT_MASK, CYREG_PRT2_BIT_MASK\r
-.set SCSI_In__0__BYP, CYREG_PRT2_BYP\r
-.set SCSI_In__0__CTL, CYREG_PRT2_CTL\r
-.set SCSI_In__0__DM0, CYREG_PRT2_DM0\r
-.set SCSI_In__0__DM1, CYREG_PRT2_DM1\r
-.set SCSI_In__0__DM2, CYREG_PRT2_DM2\r
-.set SCSI_In__0__DR, CYREG_PRT2_DR\r
-.set SCSI_In__0__INP_DIS, CYREG_PRT2_INP_DIS\r
-.set SCSI_In__0__INTTYPE, CYREG_PICU2_INTTYPE1\r
-.set SCSI_In__0__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG\r
-.set SCSI_In__0__LCD_EN, CYREG_PRT2_LCD_EN\r
-.set SCSI_In__0__MASK, 0x02\r
-.set SCSI_In__0__PC, CYREG_PRT2_PC1\r
-.set SCSI_In__0__PORT, 2\r
-.set SCSI_In__0__PRT, CYREG_PRT2_PRT\r
-.set SCSI_In__0__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL\r
-.set SCSI_In__0__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN\r
-.set SCSI_In__0__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0\r
-.set SCSI_In__0__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1\r
-.set SCSI_In__0__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0\r
-.set SCSI_In__0__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1\r
-.set SCSI_In__0__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT\r
-.set SCSI_In__0__PS, CYREG_PRT2_PS\r
-.set SCSI_In__0__SHIFT, 1\r
-.set SCSI_In__0__SLW, CYREG_PRT2_SLW\r
-.set SCSI_In__1__AG, CYREG_PRT4_AG\r
-.set SCSI_In__1__AMUX, CYREG_PRT4_AMUX\r
-.set SCSI_In__1__BIE, CYREG_PRT4_BIE\r
-.set SCSI_In__1__BIT_MASK, CYREG_PRT4_BIT_MASK\r
-.set SCSI_In__1__BYP, CYREG_PRT4_BYP\r
-.set SCSI_In__1__CTL, CYREG_PRT4_CTL\r
-.set SCSI_In__1__DM0, CYREG_PRT4_DM0\r
-.set SCSI_In__1__DM1, CYREG_PRT4_DM1\r
-.set SCSI_In__1__DM2, CYREG_PRT4_DM2\r
-.set SCSI_In__1__DR, CYREG_PRT4_DR\r
-.set SCSI_In__1__INP_DIS, CYREG_PRT4_INP_DIS\r
-.set SCSI_In__1__INTTYPE, CYREG_PICU4_INTTYPE6\r
-.set SCSI_In__1__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG\r
-.set SCSI_In__1__LCD_EN, CYREG_PRT4_LCD_EN\r
-.set SCSI_In__1__MASK, 0x40\r
-.set SCSI_In__1__PC, CYREG_PRT4_PC6\r
-.set SCSI_In__1__PORT, 4\r
-.set SCSI_In__1__PRT, CYREG_PRT4_PRT\r
-.set SCSI_In__1__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL\r
-.set SCSI_In__1__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN\r
-.set SCSI_In__1__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0\r
-.set SCSI_In__1__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1\r
-.set SCSI_In__1__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0\r
-.set SCSI_In__1__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1\r
-.set SCSI_In__1__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT\r
-.set SCSI_In__1__PS, CYREG_PRT4_PS\r
-.set SCSI_In__1__SHIFT, 6\r
-.set SCSI_In__1__SLW, CYREG_PRT4_SLW\r
-.set SCSI_In__2__AG, CYREG_PRT4_AG\r
-.set SCSI_In__2__AMUX, CYREG_PRT4_AMUX\r
-.set SCSI_In__2__BIE, CYREG_PRT4_BIE\r
-.set SCSI_In__2__BIT_MASK, CYREG_PRT4_BIT_MASK\r
-.set SCSI_In__2__BYP, CYREG_PRT4_BYP\r
-.set SCSI_In__2__CTL, CYREG_PRT4_CTL\r
-.set SCSI_In__2__DM0, CYREG_PRT4_DM0\r
-.set SCSI_In__2__DM1, CYREG_PRT4_DM1\r
-.set SCSI_In__2__DM2, CYREG_PRT4_DM2\r
-.set SCSI_In__2__DR, CYREG_PRT4_DR\r
-.set SCSI_In__2__INP_DIS, CYREG_PRT4_INP_DIS\r
-.set SCSI_In__2__INTTYPE, CYREG_PICU4_INTTYPE2\r
-.set SCSI_In__2__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG\r
-.set SCSI_In__2__LCD_EN, CYREG_PRT4_LCD_EN\r
-.set SCSI_In__2__MASK, 0x04\r
-.set SCSI_In__2__PC, CYREG_PRT4_PC2\r
-.set SCSI_In__2__PORT, 4\r
-.set SCSI_In__2__PRT, CYREG_PRT4_PRT\r
-.set SCSI_In__2__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL\r
-.set SCSI_In__2__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN\r
-.set SCSI_In__2__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0\r
-.set SCSI_In__2__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1\r
-.set SCSI_In__2__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0\r
-.set SCSI_In__2__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1\r
-.set SCSI_In__2__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT\r
-.set SCSI_In__2__PS, CYREG_PRT4_PS\r
-.set SCSI_In__2__SHIFT, 2\r
-.set SCSI_In__2__SLW, CYREG_PRT4_SLW\r
-.set SCSI_In__3__AG, CYREG_PRT0_AG\r
-.set SCSI_In__3__AMUX, CYREG_PRT0_AMUX\r
-.set SCSI_In__3__BIE, CYREG_PRT0_BIE\r
-.set SCSI_In__3__BIT_MASK, CYREG_PRT0_BIT_MASK\r
-.set SCSI_In__3__BYP, CYREG_PRT0_BYP\r
-.set SCSI_In__3__CTL, CYREG_PRT0_CTL\r
-.set SCSI_In__3__DM0, CYREG_PRT0_DM0\r
-.set SCSI_In__3__DM1, CYREG_PRT0_DM1\r
-.set SCSI_In__3__DM2, CYREG_PRT0_DM2\r
-.set SCSI_In__3__DR, CYREG_PRT0_DR\r
-.set SCSI_In__3__INP_DIS, CYREG_PRT0_INP_DIS\r
-.set SCSI_In__3__INTTYPE, CYREG_PICU0_INTTYPE5\r
-.set SCSI_In__3__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG\r
-.set SCSI_In__3__LCD_EN, CYREG_PRT0_LCD_EN\r
-.set SCSI_In__3__MASK, 0x20\r
-.set SCSI_In__3__PC, CYREG_PRT0_PC5\r
-.set SCSI_In__3__PORT, 0\r
-.set SCSI_In__3__PRT, CYREG_PRT0_PRT\r
-.set SCSI_In__3__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL\r
-.set SCSI_In__3__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN\r
-.set SCSI_In__3__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0\r
-.set SCSI_In__3__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1\r
-.set SCSI_In__3__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0\r
-.set SCSI_In__3__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1\r
-.set SCSI_In__3__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT\r
-.set SCSI_In__3__PS, CYREG_PRT0_PS\r
-.set SCSI_In__3__SHIFT, 5\r
-.set SCSI_In__3__SLW, CYREG_PRT0_SLW\r
-.set SCSI_In__4__AG, CYREG_PRT0_AG\r
-.set SCSI_In__4__AMUX, CYREG_PRT0_AMUX\r
-.set SCSI_In__4__BIE, CYREG_PRT0_BIE\r
-.set SCSI_In__4__BIT_MASK, CYREG_PRT0_BIT_MASK\r
-.set SCSI_In__4__BYP, CYREG_PRT0_BYP\r
-.set SCSI_In__4__CTL, CYREG_PRT0_CTL\r
-.set SCSI_In__4__DM0, CYREG_PRT0_DM0\r
-.set SCSI_In__4__DM1, CYREG_PRT0_DM1\r
-.set SCSI_In__4__DM2, CYREG_PRT0_DM2\r
-.set SCSI_In__4__DR, CYREG_PRT0_DR\r
-.set SCSI_In__4__INP_DIS, CYREG_PRT0_INP_DIS\r
-.set SCSI_In__4__INTTYPE, CYREG_PICU0_INTTYPE4\r
-.set SCSI_In__4__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG\r
-.set SCSI_In__4__LCD_EN, CYREG_PRT0_LCD_EN\r
-.set SCSI_In__4__MASK, 0x10\r
-.set SCSI_In__4__PC, CYREG_PRT0_PC4\r
-.set SCSI_In__4__PORT, 0\r
-.set SCSI_In__4__PRT, CYREG_PRT0_PRT\r
-.set SCSI_In__4__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL\r
-.set SCSI_In__4__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN\r
-.set SCSI_In__4__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0\r
-.set SCSI_In__4__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1\r
-.set SCSI_In__4__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0\r
-.set SCSI_In__4__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1\r
-.set SCSI_In__4__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT\r
-.set SCSI_In__4__PS, CYREG_PRT0_PS\r
-.set SCSI_In__4__SHIFT, 4\r
-.set SCSI_In__4__SLW, CYREG_PRT0_SLW\r
-.set SCSI_In__CD__AG, CYREG_PRT4_AG\r
-.set SCSI_In__CD__AMUX, CYREG_PRT4_AMUX\r
-.set SCSI_In__CD__BIE, CYREG_PRT4_BIE\r
-.set SCSI_In__CD__BIT_MASK, CYREG_PRT4_BIT_MASK\r
-.set SCSI_In__CD__BYP, CYREG_PRT4_BYP\r
-.set SCSI_In__CD__CTL, CYREG_PRT4_CTL\r
-.set SCSI_In__CD__DM0, CYREG_PRT4_DM0\r
-.set SCSI_In__CD__DM1, CYREG_PRT4_DM1\r
-.set SCSI_In__CD__DM2, CYREG_PRT4_DM2\r
-.set SCSI_In__CD__DR, CYREG_PRT4_DR\r
-.set SCSI_In__CD__INP_DIS, CYREG_PRT4_INP_DIS\r
-.set SCSI_In__CD__INTTYPE, CYREG_PICU4_INTTYPE2\r
-.set SCSI_In__CD__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG\r
-.set SCSI_In__CD__LCD_EN, CYREG_PRT4_LCD_EN\r
-.set SCSI_In__CD__MASK, 0x04\r
-.set SCSI_In__CD__PC, CYREG_PRT4_PC2\r
-.set SCSI_In__CD__PORT, 4\r
-.set SCSI_In__CD__PRT, CYREG_PRT4_PRT\r
-.set SCSI_In__CD__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL\r
-.set SCSI_In__CD__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN\r
-.set SCSI_In__CD__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0\r
-.set SCSI_In__CD__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1\r
-.set SCSI_In__CD__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0\r
-.set SCSI_In__CD__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1\r
-.set SCSI_In__CD__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT\r
-.set SCSI_In__CD__PS, CYREG_PRT4_PS\r
-.set SCSI_In__CD__SHIFT, 2\r
-.set SCSI_In__CD__SLW, CYREG_PRT4_SLW\r
-.set SCSI_In__DBP__AG, CYREG_PRT2_AG\r
-.set SCSI_In__DBP__AMUX, CYREG_PRT2_AMUX\r
-.set SCSI_In__DBP__BIE, CYREG_PRT2_BIE\r
-.set SCSI_In__DBP__BIT_MASK, CYREG_PRT2_BIT_MASK\r
-.set SCSI_In__DBP__BYP, CYREG_PRT2_BYP\r
-.set SCSI_In__DBP__CTL, CYREG_PRT2_CTL\r
-.set SCSI_In__DBP__DM0, CYREG_PRT2_DM0\r
-.set SCSI_In__DBP__DM1, CYREG_PRT2_DM1\r
-.set SCSI_In__DBP__DM2, CYREG_PRT2_DM2\r
-.set SCSI_In__DBP__DR, CYREG_PRT2_DR\r
-.set SCSI_In__DBP__INP_DIS, CYREG_PRT2_INP_DIS\r
-.set SCSI_In__DBP__INTTYPE, CYREG_PICU2_INTTYPE1\r
-.set SCSI_In__DBP__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG\r
-.set SCSI_In__DBP__LCD_EN, CYREG_PRT2_LCD_EN\r
-.set SCSI_In__DBP__MASK, 0x02\r
-.set SCSI_In__DBP__PC, CYREG_PRT2_PC1\r
-.set SCSI_In__DBP__PORT, 2\r
-.set SCSI_In__DBP__PRT, CYREG_PRT2_PRT\r
-.set SCSI_In__DBP__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL\r
-.set SCSI_In__DBP__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN\r
-.set SCSI_In__DBP__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0\r
-.set SCSI_In__DBP__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1\r
-.set SCSI_In__DBP__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0\r
-.set SCSI_In__DBP__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1\r
-.set SCSI_In__DBP__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT\r
-.set SCSI_In__DBP__PS, CYREG_PRT2_PS\r
-.set SCSI_In__DBP__SHIFT, 1\r
-.set SCSI_In__DBP__SLW, CYREG_PRT2_SLW\r
-.set SCSI_In__IO__AG, CYREG_PRT0_AG\r
-.set SCSI_In__IO__AMUX, CYREG_PRT0_AMUX\r
-.set SCSI_In__IO__BIE, CYREG_PRT0_BIE\r
-.set SCSI_In__IO__BIT_MASK, CYREG_PRT0_BIT_MASK\r
-.set SCSI_In__IO__BYP, CYREG_PRT0_BYP\r
-.set SCSI_In__IO__CTL, CYREG_PRT0_CTL\r
-.set SCSI_In__IO__DM0, CYREG_PRT0_DM0\r
-.set SCSI_In__IO__DM1, CYREG_PRT0_DM1\r
-.set SCSI_In__IO__DM2, CYREG_PRT0_DM2\r
-.set SCSI_In__IO__DR, CYREG_PRT0_DR\r
-.set SCSI_In__IO__INP_DIS, CYREG_PRT0_INP_DIS\r
-.set SCSI_In__IO__INTTYPE, CYREG_PICU0_INTTYPE4\r
-.set SCSI_In__IO__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG\r
-.set SCSI_In__IO__LCD_EN, CYREG_PRT0_LCD_EN\r
-.set SCSI_In__IO__MASK, 0x10\r
-.set SCSI_In__IO__PC, CYREG_PRT0_PC4\r
-.set SCSI_In__IO__PORT, 0\r
-.set SCSI_In__IO__PRT, CYREG_PRT0_PRT\r
-.set SCSI_In__IO__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL\r
-.set SCSI_In__IO__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN\r
-.set SCSI_In__IO__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0\r
-.set SCSI_In__IO__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1\r
-.set SCSI_In__IO__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0\r
-.set SCSI_In__IO__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1\r
-.set SCSI_In__IO__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT\r
-.set SCSI_In__IO__PS, CYREG_PRT0_PS\r
-.set SCSI_In__IO__SHIFT, 4\r
-.set SCSI_In__IO__SLW, CYREG_PRT0_SLW\r
-.set SCSI_In__MSG__AG, CYREG_PRT4_AG\r
-.set SCSI_In__MSG__AMUX, CYREG_PRT4_AMUX\r
-.set SCSI_In__MSG__BIE, CYREG_PRT4_BIE\r
-.set SCSI_In__MSG__BIT_MASK, CYREG_PRT4_BIT_MASK\r
-.set SCSI_In__MSG__BYP, CYREG_PRT4_BYP\r
-.set SCSI_In__MSG__CTL, CYREG_PRT4_CTL\r
-.set SCSI_In__MSG__DM0, CYREG_PRT4_DM0\r
-.set SCSI_In__MSG__DM1, CYREG_PRT4_DM1\r
-.set SCSI_In__MSG__DM2, CYREG_PRT4_DM2\r
-.set SCSI_In__MSG__DR, CYREG_PRT4_DR\r
-.set SCSI_In__MSG__INP_DIS, CYREG_PRT4_INP_DIS\r
-.set SCSI_In__MSG__INTTYPE, CYREG_PICU4_INTTYPE6\r
-.set SCSI_In__MSG__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG\r
-.set SCSI_In__MSG__LCD_EN, CYREG_PRT4_LCD_EN\r
-.set SCSI_In__MSG__MASK, 0x40\r
-.set SCSI_In__MSG__PC, CYREG_PRT4_PC6\r
-.set SCSI_In__MSG__PORT, 4\r
-.set SCSI_In__MSG__PRT, CYREG_PRT4_PRT\r
-.set SCSI_In__MSG__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL\r
-.set SCSI_In__MSG__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN\r
-.set SCSI_In__MSG__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0\r
-.set SCSI_In__MSG__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1\r
-.set SCSI_In__MSG__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0\r
-.set SCSI_In__MSG__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1\r
-.set SCSI_In__MSG__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT\r
-.set SCSI_In__MSG__PS, CYREG_PRT4_PS\r
-.set SCSI_In__MSG__SHIFT, 6\r
-.set SCSI_In__MSG__SLW, CYREG_PRT4_SLW\r
-.set SCSI_In__REQ__AG, CYREG_PRT0_AG\r
-.set SCSI_In__REQ__AMUX, CYREG_PRT0_AMUX\r
-.set SCSI_In__REQ__BIE, CYREG_PRT0_BIE\r
-.set SCSI_In__REQ__BIT_MASK, CYREG_PRT0_BIT_MASK\r
-.set SCSI_In__REQ__BYP, CYREG_PRT0_BYP\r
-.set SCSI_In__REQ__CTL, CYREG_PRT0_CTL\r
-.set SCSI_In__REQ__DM0, CYREG_PRT0_DM0\r
-.set SCSI_In__REQ__DM1, CYREG_PRT0_DM1\r
-.set SCSI_In__REQ__DM2, CYREG_PRT0_DM2\r
-.set SCSI_In__REQ__DR, CYREG_PRT0_DR\r
-.set SCSI_In__REQ__INP_DIS, CYREG_PRT0_INP_DIS\r
-.set SCSI_In__REQ__INTTYPE, CYREG_PICU0_INTTYPE5\r
-.set SCSI_In__REQ__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG\r
-.set SCSI_In__REQ__LCD_EN, CYREG_PRT0_LCD_EN\r
-.set SCSI_In__REQ__MASK, 0x20\r
-.set SCSI_In__REQ__PC, CYREG_PRT0_PC5\r
-.set SCSI_In__REQ__PORT, 0\r
-.set SCSI_In__REQ__PRT, CYREG_PRT0_PRT\r
-.set SCSI_In__REQ__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL\r
-.set SCSI_In__REQ__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN\r
-.set SCSI_In__REQ__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0\r
-.set SCSI_In__REQ__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1\r
-.set SCSI_In__REQ__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0\r
-.set SCSI_In__REQ__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1\r
-.set SCSI_In__REQ__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT\r
-.set SCSI_In__REQ__PS, CYREG_PRT0_PS\r
-.set SCSI_In__REQ__SHIFT, 5\r
-.set SCSI_In__REQ__SLW, CYREG_PRT0_SLW\r
-\r
-/* SCSI_In_DBx */\r
-.set SCSI_In_DBx__0__AG, CYREG_PRT5_AG\r
-.set SCSI_In_DBx__0__AMUX, CYREG_PRT5_AMUX\r
-.set SCSI_In_DBx__0__BIE, CYREG_PRT5_BIE\r
-.set SCSI_In_DBx__0__BIT_MASK, CYREG_PRT5_BIT_MASK\r
-.set SCSI_In_DBx__0__BYP, CYREG_PRT5_BYP\r
-.set SCSI_In_DBx__0__CTL, CYREG_PRT5_CTL\r
-.set SCSI_In_DBx__0__DM0, CYREG_PRT5_DM0\r
-.set SCSI_In_DBx__0__DM1, CYREG_PRT5_DM1\r
-.set SCSI_In_DBx__0__DM2, CYREG_PRT5_DM2\r
-.set SCSI_In_DBx__0__DR, CYREG_PRT5_DR\r
-.set SCSI_In_DBx__0__INP_DIS, CYREG_PRT5_INP_DIS\r
-.set SCSI_In_DBx__0__INTTYPE, CYREG_PICU5_INTTYPE3\r
-.set SCSI_In_DBx__0__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG\r
-.set SCSI_In_DBx__0__LCD_EN, CYREG_PRT5_LCD_EN\r
-.set SCSI_In_DBx__0__MASK, 0x08\r
-.set SCSI_In_DBx__0__PC, CYREG_PRT5_PC3\r
-.set SCSI_In_DBx__0__PORT, 5\r
-.set SCSI_In_DBx__0__PRT, CYREG_PRT5_PRT\r
-.set SCSI_In_DBx__0__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL\r
-.set SCSI_In_DBx__0__PRTDSI__DBL_SYNC_IN, CYREG_PRT5_DBL_SYNC_IN\r
-.set SCSI_In_DBx__0__PRTDSI__OE_SEL0, CYREG_PRT5_OE_SEL0\r
-.set SCSI_In_DBx__0__PRTDSI__OE_SEL1, CYREG_PRT5_OE_SEL1\r
-.set SCSI_In_DBx__0__PRTDSI__OUT_SEL0, CYREG_PRT5_OUT_SEL0\r
-.set SCSI_In_DBx__0__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1\r
-.set SCSI_In_DBx__0__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT\r
-.set SCSI_In_DBx__0__PS, CYREG_PRT5_PS\r
-.set SCSI_In_DBx__0__SHIFT, 3\r
-.set SCSI_In_DBx__0__SLW, CYREG_PRT5_SLW\r
-.set SCSI_In_DBx__1__AG, CYREG_PRT5_AG\r
-.set SCSI_In_DBx__1__AMUX, CYREG_PRT5_AMUX\r
-.set SCSI_In_DBx__1__BIE, CYREG_PRT5_BIE\r
-.set SCSI_In_DBx__1__BIT_MASK, CYREG_PRT5_BIT_MASK\r
-.set SCSI_In_DBx__1__BYP, CYREG_PRT5_BYP\r
-.set SCSI_In_DBx__1__CTL, CYREG_PRT5_CTL\r
-.set SCSI_In_DBx__1__DM0, CYREG_PRT5_DM0\r
-.set SCSI_In_DBx__1__DM1, CYREG_PRT5_DM1\r
-.set SCSI_In_DBx__1__DM2, CYREG_PRT5_DM2\r
-.set SCSI_In_DBx__1__DR, CYREG_PRT5_DR\r
-.set SCSI_In_DBx__1__INP_DIS, CYREG_PRT5_INP_DIS\r
-.set SCSI_In_DBx__1__INTTYPE, CYREG_PICU5_INTTYPE2\r
-.set SCSI_In_DBx__1__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG\r
-.set SCSI_In_DBx__1__LCD_EN, CYREG_PRT5_LCD_EN\r
-.set SCSI_In_DBx__1__MASK, 0x04\r
-.set SCSI_In_DBx__1__PC, CYREG_PRT5_PC2\r
-.set SCSI_In_DBx__1__PORT, 5\r
-.set SCSI_In_DBx__1__PRT, CYREG_PRT5_PRT\r
-.set SCSI_In_DBx__1__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL\r
-.set SCSI_In_DBx__1__PRTDSI__DBL_SYNC_IN, CYREG_PRT5_DBL_SYNC_IN\r
-.set SCSI_In_DBx__1__PRTDSI__OE_SEL0, CYREG_PRT5_OE_SEL0\r
-.set SCSI_In_DBx__1__PRTDSI__OE_SEL1, CYREG_PRT5_OE_SEL1\r
-.set SCSI_In_DBx__1__PRTDSI__OUT_SEL0, CYREG_PRT5_OUT_SEL0\r
-.set SCSI_In_DBx__1__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1\r
-.set SCSI_In_DBx__1__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT\r
-.set SCSI_In_DBx__1__PS, CYREG_PRT5_PS\r
-.set SCSI_In_DBx__1__SHIFT, 2\r
-.set SCSI_In_DBx__1__SLW, CYREG_PRT5_SLW\r
-.set SCSI_In_DBx__2__AG, CYREG_PRT6_AG\r
-.set SCSI_In_DBx__2__AMUX, CYREG_PRT6_AMUX\r
-.set SCSI_In_DBx__2__BIE, CYREG_PRT6_BIE\r
-.set SCSI_In_DBx__2__BIT_MASK, CYREG_PRT6_BIT_MASK\r
-.set SCSI_In_DBx__2__BYP, CYREG_PRT6_BYP\r
-.set SCSI_In_DBx__2__CTL, CYREG_PRT6_CTL\r
-.set SCSI_In_DBx__2__DM0, CYREG_PRT6_DM0\r
-.set SCSI_In_DBx__2__DM1, CYREG_PRT6_DM1\r
-.set SCSI_In_DBx__2__DM2, CYREG_PRT6_DM2\r
-.set SCSI_In_DBx__2__DR, CYREG_PRT6_DR\r
-.set SCSI_In_DBx__2__INP_DIS, CYREG_PRT6_INP_DIS\r
-.set SCSI_In_DBx__2__INTTYPE, CYREG_PICU6_INTTYPE7\r
-.set SCSI_In_DBx__2__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG\r
-.set SCSI_In_DBx__2__LCD_EN, CYREG_PRT6_LCD_EN\r
-.set SCSI_In_DBx__2__MASK, 0x80\r
-.set SCSI_In_DBx__2__PC, CYREG_PRT6_PC7\r
-.set SCSI_In_DBx__2__PORT, 6\r
-.set SCSI_In_DBx__2__PRT, CYREG_PRT6_PRT\r
-.set SCSI_In_DBx__2__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL\r
-.set SCSI_In_DBx__2__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN\r
-.set SCSI_In_DBx__2__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0\r
-.set SCSI_In_DBx__2__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1\r
-.set SCSI_In_DBx__2__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0\r
-.set SCSI_In_DBx__2__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1\r
-.set SCSI_In_DBx__2__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT\r
-.set SCSI_In_DBx__2__PS, CYREG_PRT6_PS\r
-.set SCSI_In_DBx__2__SHIFT, 7\r
-.set SCSI_In_DBx__2__SLW, CYREG_PRT6_SLW\r
-.set SCSI_In_DBx__3__AG, CYREG_PRT6_AG\r
-.set SCSI_In_DBx__3__AMUX, CYREG_PRT6_AMUX\r
-.set SCSI_In_DBx__3__BIE, CYREG_PRT6_BIE\r
-.set SCSI_In_DBx__3__BIT_MASK, CYREG_PRT6_BIT_MASK\r
-.set SCSI_In_DBx__3__BYP, CYREG_PRT6_BYP\r
-.set SCSI_In_DBx__3__CTL, CYREG_PRT6_CTL\r
-.set SCSI_In_DBx__3__DM0, CYREG_PRT6_DM0\r
-.set SCSI_In_DBx__3__DM1, CYREG_PRT6_DM1\r
-.set SCSI_In_DBx__3__DM2, CYREG_PRT6_DM2\r
-.set SCSI_In_DBx__3__DR, CYREG_PRT6_DR\r
-.set SCSI_In_DBx__3__INP_DIS, CYREG_PRT6_INP_DIS\r
-.set SCSI_In_DBx__3__INTTYPE, CYREG_PICU6_INTTYPE6\r
-.set SCSI_In_DBx__3__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG\r
-.set SCSI_In_DBx__3__LCD_EN, CYREG_PRT6_LCD_EN\r
-.set SCSI_In_DBx__3__MASK, 0x40\r
-.set SCSI_In_DBx__3__PC, CYREG_PRT6_PC6\r
-.set SCSI_In_DBx__3__PORT, 6\r
-.set SCSI_In_DBx__3__PRT, CYREG_PRT6_PRT\r
-.set SCSI_In_DBx__3__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL\r
-.set SCSI_In_DBx__3__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN\r
-.set SCSI_In_DBx__3__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0\r
-.set SCSI_In_DBx__3__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1\r
-.set SCSI_In_DBx__3__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0\r
-.set SCSI_In_DBx__3__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1\r
-.set SCSI_In_DBx__3__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT\r
-.set SCSI_In_DBx__3__PS, CYREG_PRT6_PS\r
-.set SCSI_In_DBx__3__SHIFT, 6\r
-.set SCSI_In_DBx__3__SLW, CYREG_PRT6_SLW\r
-.set SCSI_In_DBx__4__AG, CYREG_PRT12_AG\r
-.set SCSI_In_DBx__4__BIE, CYREG_PRT12_BIE\r
-.set SCSI_In_DBx__4__BIT_MASK, CYREG_PRT12_BIT_MASK\r
-.set SCSI_In_DBx__4__BYP, CYREG_PRT12_BYP\r
-.set SCSI_In_DBx__4__DM0, CYREG_PRT12_DM0\r
-.set SCSI_In_DBx__4__DM1, CYREG_PRT12_DM1\r
-.set SCSI_In_DBx__4__DM2, CYREG_PRT12_DM2\r
-.set SCSI_In_DBx__4__DR, CYREG_PRT12_DR\r
-.set SCSI_In_DBx__4__INP_DIS, CYREG_PRT12_INP_DIS\r
-.set SCSI_In_DBx__4__INTTYPE, CYREG_PICU12_INTTYPE5\r
-.set SCSI_In_DBx__4__MASK, 0x20\r
-.set SCSI_In_DBx__4__PC, CYREG_PRT12_PC5\r
-.set SCSI_In_DBx__4__PORT, 12\r
-.set SCSI_In_DBx__4__PRT, CYREG_PRT12_PRT\r
-.set SCSI_In_DBx__4__PRTDSI__DBL_SYNC_IN, CYREG_PRT12_DBL_SYNC_IN\r
-.set SCSI_In_DBx__4__PRTDSI__OE_SEL0, CYREG_PRT12_OE_SEL0\r
-.set SCSI_In_DBx__4__PRTDSI__OE_SEL1, CYREG_PRT12_OE_SEL1\r
-.set SCSI_In_DBx__4__PRTDSI__OUT_SEL0, CYREG_PRT12_OUT_SEL0\r
-.set SCSI_In_DBx__4__PRTDSI__OUT_SEL1, CYREG_PRT12_OUT_SEL1\r
-.set SCSI_In_DBx__4__PRTDSI__SYNC_OUT, CYREG_PRT12_SYNC_OUT\r
-.set SCSI_In_DBx__4__PS, CYREG_PRT12_PS\r
-.set SCSI_In_DBx__4__SHIFT, 5\r
-.set SCSI_In_DBx__4__SIO_CFG, CYREG_PRT12_SIO_CFG\r
-.set SCSI_In_DBx__4__SIO_DIFF, CYREG_PRT12_SIO_DIFF\r
-.set SCSI_In_DBx__4__SIO_HYST_EN, CYREG_PRT12_SIO_HYST_EN\r
-.set SCSI_In_DBx__4__SIO_REG_HIFREQ, CYREG_PRT12_SIO_REG_HIFREQ\r
-.set SCSI_In_DBx__4__SLW, CYREG_PRT12_SLW\r
-.set SCSI_In_DBx__5__AG, CYREG_PRT12_AG\r
-.set SCSI_In_DBx__5__BIE, CYREG_PRT12_BIE\r
-.set SCSI_In_DBx__5__BIT_MASK, CYREG_PRT12_BIT_MASK\r
-.set SCSI_In_DBx__5__BYP, CYREG_PRT12_BYP\r
-.set SCSI_In_DBx__5__DM0, CYREG_PRT12_DM0\r
-.set SCSI_In_DBx__5__DM1, CYREG_PRT12_DM1\r
-.set SCSI_In_DBx__5__DM2, CYREG_PRT12_DM2\r
-.set SCSI_In_DBx__5__DR, CYREG_PRT12_DR\r
-.set SCSI_In_DBx__5__INP_DIS, CYREG_PRT12_INP_DIS\r
-.set SCSI_In_DBx__5__INTTYPE, CYREG_PICU12_INTTYPE4\r
-.set SCSI_In_DBx__5__MASK, 0x10\r
-.set SCSI_In_DBx__5__PC, CYREG_PRT12_PC4\r
-.set SCSI_In_DBx__5__PORT, 12\r
-.set SCSI_In_DBx__5__PRT, CYREG_PRT12_PRT\r
-.set SCSI_In_DBx__5__PRTDSI__DBL_SYNC_IN, CYREG_PRT12_DBL_SYNC_IN\r
-.set SCSI_In_DBx__5__PRTDSI__OE_SEL0, CYREG_PRT12_OE_SEL0\r
-.set SCSI_In_DBx__5__PRTDSI__OE_SEL1, CYREG_PRT12_OE_SEL1\r
-.set SCSI_In_DBx__5__PRTDSI__OUT_SEL0, CYREG_PRT12_OUT_SEL0\r
-.set SCSI_In_DBx__5__PRTDSI__OUT_SEL1, CYREG_PRT12_OUT_SEL1\r
-.set SCSI_In_DBx__5__PRTDSI__SYNC_OUT, CYREG_PRT12_SYNC_OUT\r
-.set SCSI_In_DBx__5__PS, CYREG_PRT12_PS\r
-.set SCSI_In_DBx__5__SHIFT, 4\r
-.set SCSI_In_DBx__5__SIO_CFG, CYREG_PRT12_SIO_CFG\r
-.set SCSI_In_DBx__5__SIO_DIFF, CYREG_PRT12_SIO_DIFF\r
-.set SCSI_In_DBx__5__SIO_HYST_EN, CYREG_PRT12_SIO_HYST_EN\r
-.set SCSI_In_DBx__5__SIO_REG_HIFREQ, CYREG_PRT12_SIO_REG_HIFREQ\r
-.set SCSI_In_DBx__5__SLW, CYREG_PRT12_SLW\r
-.set SCSI_In_DBx__6__AG, CYREG_PRT2_AG\r
-.set SCSI_In_DBx__6__AMUX, CYREG_PRT2_AMUX\r
-.set SCSI_In_DBx__6__BIE, CYREG_PRT2_BIE\r
-.set SCSI_In_DBx__6__BIT_MASK, CYREG_PRT2_BIT_MASK\r
-.set SCSI_In_DBx__6__BYP, CYREG_PRT2_BYP\r
-.set SCSI_In_DBx__6__CTL, CYREG_PRT2_CTL\r
-.set SCSI_In_DBx__6__DM0, CYREG_PRT2_DM0\r
-.set SCSI_In_DBx__6__DM1, CYREG_PRT2_DM1\r
-.set SCSI_In_DBx__6__DM2, CYREG_PRT2_DM2\r
-.set SCSI_In_DBx__6__DR, CYREG_PRT2_DR\r
-.set SCSI_In_DBx__6__INP_DIS, CYREG_PRT2_INP_DIS\r
-.set SCSI_In_DBx__6__INTTYPE, CYREG_PICU2_INTTYPE5\r
-.set SCSI_In_DBx__6__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG\r
-.set SCSI_In_DBx__6__LCD_EN, CYREG_PRT2_LCD_EN\r
-.set SCSI_In_DBx__6__MASK, 0x20\r
-.set SCSI_In_DBx__6__PC, CYREG_PRT2_PC5\r
-.set SCSI_In_DBx__6__PORT, 2\r
-.set SCSI_In_DBx__6__PRT, CYREG_PRT2_PRT\r
-.set SCSI_In_DBx__6__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL\r
-.set SCSI_In_DBx__6__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN\r
-.set SCSI_In_DBx__6__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0\r
-.set SCSI_In_DBx__6__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1\r
-.set SCSI_In_DBx__6__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0\r
-.set SCSI_In_DBx__6__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1\r
-.set SCSI_In_DBx__6__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT\r
-.set SCSI_In_DBx__6__PS, CYREG_PRT2_PS\r
-.set SCSI_In_DBx__6__SHIFT, 5\r
-.set SCSI_In_DBx__6__SLW, CYREG_PRT2_SLW\r
-.set SCSI_In_DBx__7__AG, CYREG_PRT2_AG\r
-.set SCSI_In_DBx__7__AMUX, CYREG_PRT2_AMUX\r
-.set SCSI_In_DBx__7__BIE, CYREG_PRT2_BIE\r
-.set SCSI_In_DBx__7__BIT_MASK, CYREG_PRT2_BIT_MASK\r
-.set SCSI_In_DBx__7__BYP, CYREG_PRT2_BYP\r
-.set SCSI_In_DBx__7__CTL, CYREG_PRT2_CTL\r
-.set SCSI_In_DBx__7__DM0, CYREG_PRT2_DM0\r
-.set SCSI_In_DBx__7__DM1, CYREG_PRT2_DM1\r
-.set SCSI_In_DBx__7__DM2, CYREG_PRT2_DM2\r
-.set SCSI_In_DBx__7__DR, CYREG_PRT2_DR\r
-.set SCSI_In_DBx__7__INP_DIS, CYREG_PRT2_INP_DIS\r
-.set SCSI_In_DBx__7__INTTYPE, CYREG_PICU2_INTTYPE4\r
-.set SCSI_In_DBx__7__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG\r
-.set SCSI_In_DBx__7__LCD_EN, CYREG_PRT2_LCD_EN\r
-.set SCSI_In_DBx__7__MASK, 0x10\r
-.set SCSI_In_DBx__7__PC, CYREG_PRT2_PC4\r
-.set SCSI_In_DBx__7__PORT, 2\r
-.set SCSI_In_DBx__7__PRT, CYREG_PRT2_PRT\r
-.set SCSI_In_DBx__7__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL\r
-.set SCSI_In_DBx__7__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN\r
-.set SCSI_In_DBx__7__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0\r
-.set SCSI_In_DBx__7__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1\r
-.set SCSI_In_DBx__7__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0\r
-.set SCSI_In_DBx__7__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1\r
-.set SCSI_In_DBx__7__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT\r
-.set SCSI_In_DBx__7__PS, CYREG_PRT2_PS\r
-.set SCSI_In_DBx__7__SHIFT, 4\r
-.set SCSI_In_DBx__7__SLW, CYREG_PRT2_SLW\r
-.set SCSI_In_DBx__DB0__AG, CYREG_PRT5_AG\r
-.set SCSI_In_DBx__DB0__AMUX, CYREG_PRT5_AMUX\r
-.set SCSI_In_DBx__DB0__BIE, CYREG_PRT5_BIE\r
-.set SCSI_In_DBx__DB0__BIT_MASK, CYREG_PRT5_BIT_MASK\r
-.set SCSI_In_DBx__DB0__BYP, CYREG_PRT5_BYP\r
-.set SCSI_In_DBx__DB0__CTL, CYREG_PRT5_CTL\r
-.set SCSI_In_DBx__DB0__DM0, CYREG_PRT5_DM0\r
-.set SCSI_In_DBx__DB0__DM1, CYREG_PRT5_DM1\r
-.set SCSI_In_DBx__DB0__DM2, CYREG_PRT5_DM2\r
-.set SCSI_In_DBx__DB0__DR, CYREG_PRT5_DR\r
-.set SCSI_In_DBx__DB0__INP_DIS, CYREG_PRT5_INP_DIS\r
-.set SCSI_In_DBx__DB0__INTTYPE, CYREG_PICU5_INTTYPE3\r
-.set SCSI_In_DBx__DB0__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG\r
-.set SCSI_In_DBx__DB0__LCD_EN, CYREG_PRT5_LCD_EN\r
-.set SCSI_In_DBx__DB0__MASK, 0x08\r
-.set SCSI_In_DBx__DB0__PC, CYREG_PRT5_PC3\r
-.set SCSI_In_DBx__DB0__PORT, 5\r
-.set SCSI_In_DBx__DB0__PRT, CYREG_PRT5_PRT\r
-.set SCSI_In_DBx__DB0__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL\r
-.set SCSI_In_DBx__DB0__PRTDSI__DBL_SYNC_IN, CYREG_PRT5_DBL_SYNC_IN\r
-.set SCSI_In_DBx__DB0__PRTDSI__OE_SEL0, CYREG_PRT5_OE_SEL0\r
-.set SCSI_In_DBx__DB0__PRTDSI__OE_SEL1, CYREG_PRT5_OE_SEL1\r
-.set SCSI_In_DBx__DB0__PRTDSI__OUT_SEL0, CYREG_PRT5_OUT_SEL0\r
-.set SCSI_In_DBx__DB0__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1\r
-.set SCSI_In_DBx__DB0__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT\r
-.set SCSI_In_DBx__DB0__PS, CYREG_PRT5_PS\r
-.set SCSI_In_DBx__DB0__SHIFT, 3\r
-.set SCSI_In_DBx__DB0__SLW, CYREG_PRT5_SLW\r
-.set SCSI_In_DBx__DB1__AG, CYREG_PRT5_AG\r
-.set SCSI_In_DBx__DB1__AMUX, CYREG_PRT5_AMUX\r
-.set SCSI_In_DBx__DB1__BIE, CYREG_PRT5_BIE\r
-.set SCSI_In_DBx__DB1__BIT_MASK, CYREG_PRT5_BIT_MASK\r
-.set SCSI_In_DBx__DB1__BYP, CYREG_PRT5_BYP\r
-.set SCSI_In_DBx__DB1__CTL, CYREG_PRT5_CTL\r
-.set SCSI_In_DBx__DB1__DM0, CYREG_PRT5_DM0\r
-.set SCSI_In_DBx__DB1__DM1, CYREG_PRT5_DM1\r
-.set SCSI_In_DBx__DB1__DM2, CYREG_PRT5_DM2\r
-.set SCSI_In_DBx__DB1__DR, CYREG_PRT5_DR\r
-.set SCSI_In_DBx__DB1__INP_DIS, CYREG_PRT5_INP_DIS\r
-.set SCSI_In_DBx__DB1__INTTYPE, CYREG_PICU5_INTTYPE2\r
-.set SCSI_In_DBx__DB1__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG\r
-.set SCSI_In_DBx__DB1__LCD_EN, CYREG_PRT5_LCD_EN\r
-.set SCSI_In_DBx__DB1__MASK, 0x04\r
-.set SCSI_In_DBx__DB1__PC, CYREG_PRT5_PC2\r
-.set SCSI_In_DBx__DB1__PORT, 5\r
-.set SCSI_In_DBx__DB1__PRT, CYREG_PRT5_PRT\r
-.set SCSI_In_DBx__DB1__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL\r
-.set SCSI_In_DBx__DB1__PRTDSI__DBL_SYNC_IN, CYREG_PRT5_DBL_SYNC_IN\r
-.set SCSI_In_DBx__DB1__PRTDSI__OE_SEL0, CYREG_PRT5_OE_SEL0\r
-.set SCSI_In_DBx__DB1__PRTDSI__OE_SEL1, CYREG_PRT5_OE_SEL1\r
-.set SCSI_In_DBx__DB1__PRTDSI__OUT_SEL0, CYREG_PRT5_OUT_SEL0\r
-.set SCSI_In_DBx__DB1__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1\r
-.set SCSI_In_DBx__DB1__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT\r
-.set SCSI_In_DBx__DB1__PS, CYREG_PRT5_PS\r
-.set SCSI_In_DBx__DB1__SHIFT, 2\r
-.set SCSI_In_DBx__DB1__SLW, CYREG_PRT5_SLW\r
-.set SCSI_In_DBx__DB2__AG, CYREG_PRT6_AG\r
-.set SCSI_In_DBx__DB2__AMUX, CYREG_PRT6_AMUX\r
-.set SCSI_In_DBx__DB2__BIE, CYREG_PRT6_BIE\r
-.set SCSI_In_DBx__DB2__BIT_MASK, CYREG_PRT6_BIT_MASK\r
-.set SCSI_In_DBx__DB2__BYP, CYREG_PRT6_BYP\r
-.set SCSI_In_DBx__DB2__CTL, CYREG_PRT6_CTL\r
-.set SCSI_In_DBx__DB2__DM0, CYREG_PRT6_DM0\r
-.set SCSI_In_DBx__DB2__DM1, CYREG_PRT6_DM1\r
-.set SCSI_In_DBx__DB2__DM2, CYREG_PRT6_DM2\r
-.set SCSI_In_DBx__DB2__DR, CYREG_PRT6_DR\r
-.set SCSI_In_DBx__DB2__INP_DIS, CYREG_PRT6_INP_DIS\r
-.set SCSI_In_DBx__DB2__INTTYPE, CYREG_PICU6_INTTYPE7\r
-.set SCSI_In_DBx__DB2__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG\r
-.set SCSI_In_DBx__DB2__LCD_EN, CYREG_PRT6_LCD_EN\r
-.set SCSI_In_DBx__DB2__MASK, 0x80\r
-.set SCSI_In_DBx__DB2__PC, CYREG_PRT6_PC7\r
-.set SCSI_In_DBx__DB2__PORT, 6\r
-.set SCSI_In_DBx__DB2__PRT, CYREG_PRT6_PRT\r
-.set SCSI_In_DBx__DB2__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL\r
-.set SCSI_In_DBx__DB2__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN\r
-.set SCSI_In_DBx__DB2__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0\r
-.set SCSI_In_DBx__DB2__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1\r
-.set SCSI_In_DBx__DB2__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0\r
-.set SCSI_In_DBx__DB2__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1\r
-.set SCSI_In_DBx__DB2__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT\r
-.set SCSI_In_DBx__DB2__PS, CYREG_PRT6_PS\r
-.set SCSI_In_DBx__DB2__SHIFT, 7\r
-.set SCSI_In_DBx__DB2__SLW, CYREG_PRT6_SLW\r
-.set SCSI_In_DBx__DB3__AG, CYREG_PRT6_AG\r
-.set SCSI_In_DBx__DB3__AMUX, CYREG_PRT6_AMUX\r
-.set SCSI_In_DBx__DB3__BIE, CYREG_PRT6_BIE\r
-.set SCSI_In_DBx__DB3__BIT_MASK, CYREG_PRT6_BIT_MASK\r
-.set SCSI_In_DBx__DB3__BYP, CYREG_PRT6_BYP\r
-.set SCSI_In_DBx__DB3__CTL, CYREG_PRT6_CTL\r
-.set SCSI_In_DBx__DB3__DM0, CYREG_PRT6_DM0\r
-.set SCSI_In_DBx__DB3__DM1, CYREG_PRT6_DM1\r
-.set SCSI_In_DBx__DB3__DM2, CYREG_PRT6_DM2\r
-.set SCSI_In_DBx__DB3__DR, CYREG_PRT6_DR\r
-.set SCSI_In_DBx__DB3__INP_DIS, CYREG_PRT6_INP_DIS\r
-.set SCSI_In_DBx__DB3__INTTYPE, CYREG_PICU6_INTTYPE6\r
-.set SCSI_In_DBx__DB3__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG\r
-.set SCSI_In_DBx__DB3__LCD_EN, CYREG_PRT6_LCD_EN\r
-.set SCSI_In_DBx__DB3__MASK, 0x40\r
-.set SCSI_In_DBx__DB3__PC, CYREG_PRT6_PC6\r
-.set SCSI_In_DBx__DB3__PORT, 6\r
-.set SCSI_In_DBx__DB3__PRT, CYREG_PRT6_PRT\r
-.set SCSI_In_DBx__DB3__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL\r
-.set SCSI_In_DBx__DB3__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN\r
-.set SCSI_In_DBx__DB3__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0\r
-.set SCSI_In_DBx__DB3__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1\r
-.set SCSI_In_DBx__DB3__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0\r
-.set SCSI_In_DBx__DB3__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1\r
-.set SCSI_In_DBx__DB3__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT\r
-.set SCSI_In_DBx__DB3__PS, CYREG_PRT6_PS\r
-.set SCSI_In_DBx__DB3__SHIFT, 6\r
-.set SCSI_In_DBx__DB3__SLW, CYREG_PRT6_SLW\r
-.set SCSI_In_DBx__DB4__AG, CYREG_PRT12_AG\r
-.set SCSI_In_DBx__DB4__BIE, CYREG_PRT12_BIE\r
-.set SCSI_In_DBx__DB4__BIT_MASK, CYREG_PRT12_BIT_MASK\r
-.set SCSI_In_DBx__DB4__BYP, CYREG_PRT12_BYP\r
-.set SCSI_In_DBx__DB4__DM0, CYREG_PRT12_DM0\r
-.set SCSI_In_DBx__DB4__DM1, CYREG_PRT12_DM1\r
-.set SCSI_In_DBx__DB4__DM2, CYREG_PRT12_DM2\r
-.set SCSI_In_DBx__DB4__DR, CYREG_PRT12_DR\r
-.set SCSI_In_DBx__DB4__INP_DIS, CYREG_PRT12_INP_DIS\r
-.set SCSI_In_DBx__DB4__INTTYPE, CYREG_PICU12_INTTYPE5\r
-.set SCSI_In_DBx__DB4__MASK, 0x20\r
-.set SCSI_In_DBx__DB4__PC, CYREG_PRT12_PC5\r
-.set SCSI_In_DBx__DB4__PORT, 12\r
-.set SCSI_In_DBx__DB4__PRT, CYREG_PRT12_PRT\r
-.set SCSI_In_DBx__DB4__PRTDSI__DBL_SYNC_IN, CYREG_PRT12_DBL_SYNC_IN\r
-.set SCSI_In_DBx__DB4__PRTDSI__OE_SEL0, CYREG_PRT12_OE_SEL0\r
-.set SCSI_In_DBx__DB4__PRTDSI__OE_SEL1, CYREG_PRT12_OE_SEL1\r
-.set SCSI_In_DBx__DB4__PRTDSI__OUT_SEL0, CYREG_PRT12_OUT_SEL0\r
-.set SCSI_In_DBx__DB4__PRTDSI__OUT_SEL1, CYREG_PRT12_OUT_SEL1\r
-.set SCSI_In_DBx__DB4__PRTDSI__SYNC_OUT, CYREG_PRT12_SYNC_OUT\r
-.set SCSI_In_DBx__DB4__PS, CYREG_PRT12_PS\r
-.set SCSI_In_DBx__DB4__SHIFT, 5\r
-.set SCSI_In_DBx__DB4__SIO_CFG, CYREG_PRT12_SIO_CFG\r
-.set SCSI_In_DBx__DB4__SIO_DIFF, CYREG_PRT12_SIO_DIFF\r
-.set SCSI_In_DBx__DB4__SIO_HYST_EN, CYREG_PRT12_SIO_HYST_EN\r
-.set SCSI_In_DBx__DB4__SIO_REG_HIFREQ, CYREG_PRT12_SIO_REG_HIFREQ\r
-.set SCSI_In_DBx__DB4__SLW, CYREG_PRT12_SLW\r
-.set SCSI_In_DBx__DB5__AG, CYREG_PRT12_AG\r
-.set SCSI_In_DBx__DB5__BIE, CYREG_PRT12_BIE\r
-.set SCSI_In_DBx__DB5__BIT_MASK, CYREG_PRT12_BIT_MASK\r
-.set SCSI_In_DBx__DB5__BYP, CYREG_PRT12_BYP\r
-.set SCSI_In_DBx__DB5__DM0, CYREG_PRT12_DM0\r
-.set SCSI_In_DBx__DB5__DM1, CYREG_PRT12_DM1\r
-.set SCSI_In_DBx__DB5__DM2, CYREG_PRT12_DM2\r
-.set SCSI_In_DBx__DB5__DR, CYREG_PRT12_DR\r
-.set SCSI_In_DBx__DB5__INP_DIS, CYREG_PRT12_INP_DIS\r
-.set SCSI_In_DBx__DB5__INTTYPE, CYREG_PICU12_INTTYPE4\r
-.set SCSI_In_DBx__DB5__MASK, 0x10\r
-.set SCSI_In_DBx__DB5__PC, CYREG_PRT12_PC4\r
-.set SCSI_In_DBx__DB5__PORT, 12\r
-.set SCSI_In_DBx__DB5__PRT, CYREG_PRT12_PRT\r
-.set SCSI_In_DBx__DB5__PRTDSI__DBL_SYNC_IN, CYREG_PRT12_DBL_SYNC_IN\r
-.set SCSI_In_DBx__DB5__PRTDSI__OE_SEL0, CYREG_PRT12_OE_SEL0\r
-.set SCSI_In_DBx__DB5__PRTDSI__OE_SEL1, CYREG_PRT12_OE_SEL1\r
-.set SCSI_In_DBx__DB5__PRTDSI__OUT_SEL0, CYREG_PRT12_OUT_SEL0\r
-.set SCSI_In_DBx__DB5__PRTDSI__OUT_SEL1, CYREG_PRT12_OUT_SEL1\r
-.set SCSI_In_DBx__DB5__PRTDSI__SYNC_OUT, CYREG_PRT12_SYNC_OUT\r
-.set SCSI_In_DBx__DB5__PS, CYREG_PRT12_PS\r
-.set SCSI_In_DBx__DB5__SHIFT, 4\r
-.set SCSI_In_DBx__DB5__SIO_CFG, CYREG_PRT12_SIO_CFG\r
-.set SCSI_In_DBx__DB5__SIO_DIFF, CYREG_PRT12_SIO_DIFF\r
-.set SCSI_In_DBx__DB5__SIO_HYST_EN, CYREG_PRT12_SIO_HYST_EN\r
-.set SCSI_In_DBx__DB5__SIO_REG_HIFREQ, CYREG_PRT12_SIO_REG_HIFREQ\r
-.set SCSI_In_DBx__DB5__SLW, CYREG_PRT12_SLW\r
-.set SCSI_In_DBx__DB6__AG, CYREG_PRT2_AG\r
-.set SCSI_In_DBx__DB6__AMUX, CYREG_PRT2_AMUX\r
-.set SCSI_In_DBx__DB6__BIE, CYREG_PRT2_BIE\r
-.set SCSI_In_DBx__DB6__BIT_MASK, CYREG_PRT2_BIT_MASK\r
-.set SCSI_In_DBx__DB6__BYP, CYREG_PRT2_BYP\r
-.set SCSI_In_DBx__DB6__CTL, CYREG_PRT2_CTL\r
-.set SCSI_In_DBx__DB6__DM0, CYREG_PRT2_DM0\r
-.set SCSI_In_DBx__DB6__DM1, CYREG_PRT2_DM1\r
-.set SCSI_In_DBx__DB6__DM2, CYREG_PRT2_DM2\r
-.set SCSI_In_DBx__DB6__DR, CYREG_PRT2_DR\r
-.set SCSI_In_DBx__DB6__INP_DIS, CYREG_PRT2_INP_DIS\r
-.set SCSI_In_DBx__DB6__INTTYPE, CYREG_PICU2_INTTYPE5\r
-.set SCSI_In_DBx__DB6__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG\r
-.set SCSI_In_DBx__DB6__LCD_EN, CYREG_PRT2_LCD_EN\r
-.set SCSI_In_DBx__DB6__MASK, 0x20\r
-.set SCSI_In_DBx__DB6__PC, CYREG_PRT2_PC5\r
-.set SCSI_In_DBx__DB6__PORT, 2\r
-.set SCSI_In_DBx__DB6__PRT, CYREG_PRT2_PRT\r
-.set SCSI_In_DBx__DB6__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL\r
-.set SCSI_In_DBx__DB6__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN\r
-.set SCSI_In_DBx__DB6__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0\r
-.set SCSI_In_DBx__DB6__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1\r
-.set SCSI_In_DBx__DB6__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0\r
-.set SCSI_In_DBx__DB6__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1\r
-.set SCSI_In_DBx__DB6__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT\r
-.set SCSI_In_DBx__DB6__PS, CYREG_PRT2_PS\r
-.set SCSI_In_DBx__DB6__SHIFT, 5\r
-.set SCSI_In_DBx__DB6__SLW, CYREG_PRT2_SLW\r
-.set SCSI_In_DBx__DB7__AG, CYREG_PRT2_AG\r
-.set SCSI_In_DBx__DB7__AMUX, CYREG_PRT2_AMUX\r
-.set SCSI_In_DBx__DB7__BIE, CYREG_PRT2_BIE\r
-.set SCSI_In_DBx__DB7__BIT_MASK, CYREG_PRT2_BIT_MASK\r
-.set SCSI_In_DBx__DB7__BYP, CYREG_PRT2_BYP\r
-.set SCSI_In_DBx__DB7__CTL, CYREG_PRT2_CTL\r
-.set SCSI_In_DBx__DB7__DM0, CYREG_PRT2_DM0\r
-.set SCSI_In_DBx__DB7__DM1, CYREG_PRT2_DM1\r
-.set SCSI_In_DBx__DB7__DM2, CYREG_PRT2_DM2\r
-.set SCSI_In_DBx__DB7__DR, CYREG_PRT2_DR\r
-.set SCSI_In_DBx__DB7__INP_DIS, CYREG_PRT2_INP_DIS\r
-.set SCSI_In_DBx__DB7__INTTYPE, CYREG_PICU2_INTTYPE4\r
-.set SCSI_In_DBx__DB7__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG\r
-.set SCSI_In_DBx__DB7__LCD_EN, CYREG_PRT2_LCD_EN\r
-.set SCSI_In_DBx__DB7__MASK, 0x10\r
-.set SCSI_In_DBx__DB7__PC, CYREG_PRT2_PC4\r
-.set SCSI_In_DBx__DB7__PORT, 2\r
-.set SCSI_In_DBx__DB7__PRT, CYREG_PRT2_PRT\r
-.set SCSI_In_DBx__DB7__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL\r
-.set SCSI_In_DBx__DB7__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN\r
-.set SCSI_In_DBx__DB7__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0\r
-.set SCSI_In_DBx__DB7__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1\r
-.set SCSI_In_DBx__DB7__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0\r
-.set SCSI_In_DBx__DB7__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1\r
-.set SCSI_In_DBx__DB7__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT\r
-.set SCSI_In_DBx__DB7__PS, CYREG_PRT2_PS\r
-.set SCSI_In_DBx__DB7__SHIFT, 4\r
-.set SCSI_In_DBx__DB7__SLW, CYREG_PRT2_SLW\r
-\r
-/* SD_MISO */\r
-.set SD_MISO__0__INTTYPE, CYREG_PICU3_INTTYPE1\r
-.set SD_MISO__0__MASK, 0x02\r
-.set SD_MISO__0__PC, CYREG_PRT3_PC1\r
-.set SD_MISO__0__PORT, 3\r
-.set SD_MISO__0__SHIFT, 1\r
-.set SD_MISO__AG, CYREG_PRT3_AG\r
-.set SD_MISO__AMUX, CYREG_PRT3_AMUX\r
-.set SD_MISO__BIE, CYREG_PRT3_BIE\r
-.set SD_MISO__BIT_MASK, CYREG_PRT3_BIT_MASK\r
-.set SD_MISO__BYP, CYREG_PRT3_BYP\r
-.set SD_MISO__CTL, CYREG_PRT3_CTL\r
-.set SD_MISO__DM0, CYREG_PRT3_DM0\r
-.set SD_MISO__DM1, CYREG_PRT3_DM1\r
-.set SD_MISO__DM2, CYREG_PRT3_DM2\r
-.set SD_MISO__DR, CYREG_PRT3_DR\r
-.set SD_MISO__INP_DIS, CYREG_PRT3_INP_DIS\r
-.set SD_MISO__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU3_BASE\r
-.set SD_MISO__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG\r
-.set SD_MISO__LCD_EN, CYREG_PRT3_LCD_EN\r
-.set SD_MISO__MASK, 0x02\r
-.set SD_MISO__PORT, 3\r
-.set SD_MISO__PRT, CYREG_PRT3_PRT\r
-.set SD_MISO__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL\r
-.set SD_MISO__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN\r
-.set SD_MISO__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0\r
-.set SD_MISO__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1\r
-.set SD_MISO__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0\r
-.set SD_MISO__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1\r
-.set SD_MISO__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT\r
-.set SD_MISO__PS, CYREG_PRT3_PS\r
-.set SD_MISO__SHIFT, 1\r
-.set SD_MISO__SLW, CYREG_PRT3_SLW\r
-\r
-/* SD_MOSI */\r
-.set SD_MOSI__0__INTTYPE, CYREG_PICU3_INTTYPE3\r
-.set SD_MOSI__0__MASK, 0x08\r
-.set SD_MOSI__0__PC, CYREG_PRT3_PC3\r
-.set SD_MOSI__0__PORT, 3\r
-.set SD_MOSI__0__SHIFT, 3\r
-.set SD_MOSI__AG, CYREG_PRT3_AG\r
-.set SD_MOSI__AMUX, CYREG_PRT3_AMUX\r
-.set SD_MOSI__BIE, CYREG_PRT3_BIE\r
-.set SD_MOSI__BIT_MASK, CYREG_PRT3_BIT_MASK\r
-.set SD_MOSI__BYP, CYREG_PRT3_BYP\r
-.set SD_MOSI__CTL, CYREG_PRT3_CTL\r
-.set SD_MOSI__DM0, CYREG_PRT3_DM0\r
-.set SD_MOSI__DM1, CYREG_PRT3_DM1\r
-.set SD_MOSI__DM2, CYREG_PRT3_DM2\r
-.set SD_MOSI__DR, CYREG_PRT3_DR\r
-.set SD_MOSI__INP_DIS, CYREG_PRT3_INP_DIS\r
-.set SD_MOSI__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU3_BASE\r
-.set SD_MOSI__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG\r
-.set SD_MOSI__LCD_EN, CYREG_PRT3_LCD_EN\r
-.set SD_MOSI__MASK, 0x08\r
-.set SD_MOSI__PORT, 3\r
-.set SD_MOSI__PRT, CYREG_PRT3_PRT\r
-.set SD_MOSI__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL\r
-.set SD_MOSI__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN\r
-.set SD_MOSI__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0\r
-.set SD_MOSI__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1\r
-.set SD_MOSI__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0\r
-.set SD_MOSI__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1\r
-.set SD_MOSI__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT\r
-.set SD_MOSI__PS, CYREG_PRT3_PS\r
-.set SD_MOSI__SHIFT, 3\r
-.set SD_MOSI__SLW, CYREG_PRT3_SLW\r
-\r
-/* SCSI_CLK */\r
-.set SCSI_CLK__CFG0, CYREG_CLKDIST_DCFG1_CFG0\r
-.set SCSI_CLK__CFG1, CYREG_CLKDIST_DCFG1_CFG1\r
-.set SCSI_CLK__CFG2, CYREG_CLKDIST_DCFG1_CFG2\r
-.set SCSI_CLK__CFG2_SRC_SEL_MASK, 0x07\r
-.set SCSI_CLK__INDEX, 0x01\r
-.set SCSI_CLK__PM_ACT_CFG, CYREG_PM_ACT_CFG2\r
-.set SCSI_CLK__PM_ACT_MSK, 0x02\r
-.set SCSI_CLK__PM_STBY_CFG, CYREG_PM_STBY_CFG2\r
-.set SCSI_CLK__PM_STBY_MSK, 0x02\r
-\r
-/* SCSI_Out */\r
-.set SCSI_Out__0__AG, CYREG_PRT15_AG\r
-.set SCSI_Out__0__AMUX, CYREG_PRT15_AMUX\r
-.set SCSI_Out__0__BIE, CYREG_PRT15_BIE\r
-.set SCSI_Out__0__BIT_MASK, CYREG_PRT15_BIT_MASK\r
-.set SCSI_Out__0__BYP, CYREG_PRT15_BYP\r
-.set SCSI_Out__0__CTL, CYREG_PRT15_CTL\r
-.set SCSI_Out__0__DM0, CYREG_PRT15_DM0\r
-.set SCSI_Out__0__DM1, CYREG_PRT15_DM1\r
-.set SCSI_Out__0__DM2, CYREG_PRT15_DM2\r
-.set SCSI_Out__0__DR, CYREG_PRT15_DR\r
-.set SCSI_Out__0__INP_DIS, CYREG_PRT15_INP_DIS\r
-.set SCSI_Out__0__INTTYPE, CYREG_PICU15_INTTYPE5\r
-.set SCSI_Out__0__LCD_COM_SEG, CYREG_PRT15_LCD_COM_SEG\r
-.set SCSI_Out__0__LCD_EN, CYREG_PRT15_LCD_EN\r
-.set SCSI_Out__0__MASK, 0x20\r
-.set SCSI_Out__0__PC, CYREG_IO_PC_PRT15_PC5\r
-.set SCSI_Out__0__PORT, 15\r
-.set SCSI_Out__0__PRT, CYREG_PRT15_PRT\r
-.set SCSI_Out__0__PRTDSI__CAPS_SEL, CYREG_PRT15_CAPS_SEL\r
-.set SCSI_Out__0__PRTDSI__DBL_SYNC_IN, CYREG_PRT15_DBL_SYNC_IN\r
-.set SCSI_Out__0__PRTDSI__OE_SEL0, CYREG_PRT15_OE_SEL0\r
-.set SCSI_Out__0__PRTDSI__OE_SEL1, CYREG_PRT15_OE_SEL1\r
-.set SCSI_Out__0__PRTDSI__OUT_SEL0, CYREG_PRT15_OUT_SEL0\r
-.set SCSI_Out__0__PRTDSI__OUT_SEL1, CYREG_PRT15_OUT_SEL1\r
-.set SCSI_Out__0__PRTDSI__SYNC_OUT, CYREG_PRT15_SYNC_OUT\r
-.set SCSI_Out__0__PS, CYREG_PRT15_PS\r
-.set SCSI_Out__0__SHIFT, 5\r
-.set SCSI_Out__0__SLW, CYREG_PRT15_SLW\r
-.set SCSI_Out__1__AG, CYREG_PRT15_AG\r
-.set SCSI_Out__1__AMUX, CYREG_PRT15_AMUX\r
-.set SCSI_Out__1__BIE, CYREG_PRT15_BIE\r
-.set SCSI_Out__1__BIT_MASK, CYREG_PRT15_BIT_MASK\r
-.set SCSI_Out__1__BYP, CYREG_PRT15_BYP\r
-.set SCSI_Out__1__CTL, CYREG_PRT15_CTL\r
-.set SCSI_Out__1__DM0, CYREG_PRT15_DM0\r
-.set SCSI_Out__1__DM1, CYREG_PRT15_DM1\r
-.set SCSI_Out__1__DM2, CYREG_PRT15_DM2\r
-.set SCSI_Out__1__DR, CYREG_PRT15_DR\r
-.set SCSI_Out__1__INP_DIS, CYREG_PRT15_INP_DIS\r
-.set SCSI_Out__1__INTTYPE, CYREG_PICU15_INTTYPE4\r
-.set SCSI_Out__1__LCD_COM_SEG, CYREG_PRT15_LCD_COM_SEG\r
-.set SCSI_Out__1__LCD_EN, CYREG_PRT15_LCD_EN\r
-.set SCSI_Out__1__MASK, 0x10\r
-.set SCSI_Out__1__PC, CYREG_IO_PC_PRT15_PC4\r
-.set SCSI_Out__1__PORT, 15\r
-.set SCSI_Out__1__PRT, CYREG_PRT15_PRT\r
-.set SCSI_Out__1__PRTDSI__CAPS_SEL, CYREG_PRT15_CAPS_SEL\r
-.set SCSI_Out__1__PRTDSI__DBL_SYNC_IN, CYREG_PRT15_DBL_SYNC_IN\r
-.set SCSI_Out__1__PRTDSI__OE_SEL0, CYREG_PRT15_OE_SEL0\r
-.set SCSI_Out__1__PRTDSI__OE_SEL1, CYREG_PRT15_OE_SEL1\r
-.set SCSI_Out__1__PRTDSI__OUT_SEL0, CYREG_PRT15_OUT_SEL0\r
-.set SCSI_Out__1__PRTDSI__OUT_SEL1, CYREG_PRT15_OUT_SEL1\r
-.set SCSI_Out__1__PRTDSI__SYNC_OUT, CYREG_PRT15_SYNC_OUT\r
-.set SCSI_Out__1__PS, CYREG_PRT15_PS\r
-.set SCSI_Out__1__SHIFT, 4\r
-.set SCSI_Out__1__SLW, CYREG_PRT15_SLW\r
-.set SCSI_Out__2__AG, CYREG_PRT6_AG\r
-.set SCSI_Out__2__AMUX, CYREG_PRT6_AMUX\r
-.set SCSI_Out__2__BIE, CYREG_PRT6_BIE\r
-.set SCSI_Out__2__BIT_MASK, CYREG_PRT6_BIT_MASK\r
-.set SCSI_Out__2__BYP, CYREG_PRT6_BYP\r
-.set SCSI_Out__2__CTL, CYREG_PRT6_CTL\r
-.set SCSI_Out__2__DM0, CYREG_PRT6_DM0\r
-.set SCSI_Out__2__DM1, CYREG_PRT6_DM1\r
-.set SCSI_Out__2__DM2, CYREG_PRT6_DM2\r
-.set SCSI_Out__2__DR, CYREG_PRT6_DR\r
-.set SCSI_Out__2__INP_DIS, CYREG_PRT6_INP_DIS\r
-.set SCSI_Out__2__INTTYPE, CYREG_PICU6_INTTYPE1\r
-.set SCSI_Out__2__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG\r
-.set SCSI_Out__2__LCD_EN, CYREG_PRT6_LCD_EN\r
-.set SCSI_Out__2__MASK, 0x02\r
-.set SCSI_Out__2__PC, CYREG_PRT6_PC1\r
-.set SCSI_Out__2__PORT, 6\r
-.set SCSI_Out__2__PRT, CYREG_PRT6_PRT\r
-.set SCSI_Out__2__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL\r
-.set SCSI_Out__2__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN\r
-.set SCSI_Out__2__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0\r
-.set SCSI_Out__2__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1\r
-.set SCSI_Out__2__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0\r
-.set SCSI_Out__2__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1\r
-.set SCSI_Out__2__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT\r
-.set SCSI_Out__2__PS, CYREG_PRT6_PS\r
-.set SCSI_Out__2__SHIFT, 1\r
-.set SCSI_Out__2__SLW, CYREG_PRT6_SLW\r
-.set SCSI_Out__3__AG, CYREG_PRT6_AG\r
-.set SCSI_Out__3__AMUX, CYREG_PRT6_AMUX\r
-.set SCSI_Out__3__BIE, CYREG_PRT6_BIE\r
-.set SCSI_Out__3__BIT_MASK, CYREG_PRT6_BIT_MASK\r
-.set SCSI_Out__3__BYP, CYREG_PRT6_BYP\r
-.set SCSI_Out__3__CTL, CYREG_PRT6_CTL\r
-.set SCSI_Out__3__DM0, CYREG_PRT6_DM0\r
-.set SCSI_Out__3__DM1, CYREG_PRT6_DM1\r
-.set SCSI_Out__3__DM2, CYREG_PRT6_DM2\r
-.set SCSI_Out__3__DR, CYREG_PRT6_DR\r
-.set SCSI_Out__3__INP_DIS, CYREG_PRT6_INP_DIS\r
-.set SCSI_Out__3__INTTYPE, CYREG_PICU6_INTTYPE0\r
-.set SCSI_Out__3__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG\r
-.set SCSI_Out__3__LCD_EN, CYREG_PRT6_LCD_EN\r
-.set SCSI_Out__3__MASK, 0x01\r
-.set SCSI_Out__3__PC, CYREG_PRT6_PC0\r
-.set SCSI_Out__3__PORT, 6\r
-.set SCSI_Out__3__PRT, CYREG_PRT6_PRT\r
-.set SCSI_Out__3__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL\r
-.set SCSI_Out__3__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN\r
-.set SCSI_Out__3__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0\r
-.set SCSI_Out__3__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1\r
-.set SCSI_Out__3__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0\r
-.set SCSI_Out__3__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1\r
-.set SCSI_Out__3__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT\r
-.set SCSI_Out__3__PS, CYREG_PRT6_PS\r
-.set SCSI_Out__3__SHIFT, 0\r
-.set SCSI_Out__3__SLW, CYREG_PRT6_SLW\r
-.set SCSI_Out__4__AG, CYREG_PRT4_AG\r
-.set SCSI_Out__4__AMUX, CYREG_PRT4_AMUX\r
-.set SCSI_Out__4__BIE, CYREG_PRT4_BIE\r
-.set SCSI_Out__4__BIT_MASK, CYREG_PRT4_BIT_MASK\r
-.set SCSI_Out__4__BYP, CYREG_PRT4_BYP\r
-.set SCSI_Out__4__CTL, CYREG_PRT4_CTL\r
-.set SCSI_Out__4__DM0, CYREG_PRT4_DM0\r
-.set SCSI_Out__4__DM1, CYREG_PRT4_DM1\r
-.set SCSI_Out__4__DM2, CYREG_PRT4_DM2\r
-.set SCSI_Out__4__DR, CYREG_PRT4_DR\r
-.set SCSI_Out__4__INP_DIS, CYREG_PRT4_INP_DIS\r
-.set SCSI_Out__4__INTTYPE, CYREG_PICU4_INTTYPE5\r
-.set SCSI_Out__4__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG\r
-.set SCSI_Out__4__LCD_EN, CYREG_PRT4_LCD_EN\r
-.set SCSI_Out__4__MASK, 0x20\r
-.set SCSI_Out__4__PC, CYREG_PRT4_PC5\r
-.set SCSI_Out__4__PORT, 4\r
-.set SCSI_Out__4__PRT, CYREG_PRT4_PRT\r
-.set SCSI_Out__4__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL\r
-.set SCSI_Out__4__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN\r
-.set SCSI_Out__4__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0\r
-.set SCSI_Out__4__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1\r
-.set SCSI_Out__4__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0\r
-.set SCSI_Out__4__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1\r
-.set SCSI_Out__4__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT\r
-.set SCSI_Out__4__PS, CYREG_PRT4_PS\r
-.set SCSI_Out__4__SHIFT, 5\r
-.set SCSI_Out__4__SLW, CYREG_PRT4_SLW\r
-.set SCSI_Out__5__AG, CYREG_PRT4_AG\r
-.set SCSI_Out__5__AMUX, CYREG_PRT4_AMUX\r
-.set SCSI_Out__5__BIE, CYREG_PRT4_BIE\r
-.set SCSI_Out__5__BIT_MASK, CYREG_PRT4_BIT_MASK\r
-.set SCSI_Out__5__BYP, CYREG_PRT4_BYP\r
-.set SCSI_Out__5__CTL, CYREG_PRT4_CTL\r
-.set SCSI_Out__5__DM0, CYREG_PRT4_DM0\r
-.set SCSI_Out__5__DM1, CYREG_PRT4_DM1\r
-.set SCSI_Out__5__DM2, CYREG_PRT4_DM2\r
-.set SCSI_Out__5__DR, CYREG_PRT4_DR\r
-.set SCSI_Out__5__INP_DIS, CYREG_PRT4_INP_DIS\r
-.set SCSI_Out__5__INTTYPE, CYREG_PICU4_INTTYPE4\r
-.set SCSI_Out__5__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG\r
-.set SCSI_Out__5__LCD_EN, CYREG_PRT4_LCD_EN\r
-.set SCSI_Out__5__MASK, 0x10\r
-.set SCSI_Out__5__PC, CYREG_PRT4_PC4\r
-.set SCSI_Out__5__PORT, 4\r
-.set SCSI_Out__5__PRT, CYREG_PRT4_PRT\r
-.set SCSI_Out__5__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL\r
-.set SCSI_Out__5__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN\r
-.set SCSI_Out__5__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0\r
-.set SCSI_Out__5__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1\r
-.set SCSI_Out__5__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0\r
-.set SCSI_Out__5__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1\r
-.set SCSI_Out__5__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT\r
-.set SCSI_Out__5__PS, CYREG_PRT4_PS\r
-.set SCSI_Out__5__SHIFT, 4\r
-.set SCSI_Out__5__SLW, CYREG_PRT4_SLW\r
-.set SCSI_Out__6__AG, CYREG_PRT0_AG\r
-.set SCSI_Out__6__AMUX, CYREG_PRT0_AMUX\r
-.set SCSI_Out__6__BIE, CYREG_PRT0_BIE\r
-.set SCSI_Out__6__BIT_MASK, CYREG_PRT0_BIT_MASK\r
-.set SCSI_Out__6__BYP, CYREG_PRT0_BYP\r
-.set SCSI_Out__6__CTL, CYREG_PRT0_CTL\r
-.set SCSI_Out__6__DM0, CYREG_PRT0_DM0\r
-.set SCSI_Out__6__DM1, CYREG_PRT0_DM1\r
-.set SCSI_Out__6__DM2, CYREG_PRT0_DM2\r
-.set SCSI_Out__6__DR, CYREG_PRT0_DR\r
-.set SCSI_Out__6__INP_DIS, CYREG_PRT0_INP_DIS\r
-.set SCSI_Out__6__INTTYPE, CYREG_PICU0_INTTYPE7\r
-.set SCSI_Out__6__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG\r
-.set SCSI_Out__6__LCD_EN, CYREG_PRT0_LCD_EN\r
-.set SCSI_Out__6__MASK, 0x80\r
-.set SCSI_Out__6__PC, CYREG_PRT0_PC7\r
-.set SCSI_Out__6__PORT, 0\r
-.set SCSI_Out__6__PRT, CYREG_PRT0_PRT\r
-.set SCSI_Out__6__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL\r
-.set SCSI_Out__6__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN\r
-.set SCSI_Out__6__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0\r
-.set SCSI_Out__6__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1\r
-.set SCSI_Out__6__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0\r
-.set SCSI_Out__6__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1\r
-.set SCSI_Out__6__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT\r
-.set SCSI_Out__6__PS, CYREG_PRT0_PS\r
-.set SCSI_Out__6__SHIFT, 7\r
-.set SCSI_Out__6__SLW, CYREG_PRT0_SLW\r
-.set SCSI_Out__7__AG, CYREG_PRT0_AG\r
-.set SCSI_Out__7__AMUX, CYREG_PRT0_AMUX\r
-.set SCSI_Out__7__BIE, CYREG_PRT0_BIE\r
-.set SCSI_Out__7__BIT_MASK, CYREG_PRT0_BIT_MASK\r
-.set SCSI_Out__7__BYP, CYREG_PRT0_BYP\r
-.set SCSI_Out__7__CTL, CYREG_PRT0_CTL\r
-.set SCSI_Out__7__DM0, CYREG_PRT0_DM0\r
-.set SCSI_Out__7__DM1, CYREG_PRT0_DM1\r
-.set SCSI_Out__7__DM2, CYREG_PRT0_DM2\r
-.set SCSI_Out__7__DR, CYREG_PRT0_DR\r
-.set SCSI_Out__7__INP_DIS, CYREG_PRT0_INP_DIS\r
-.set SCSI_Out__7__INTTYPE, CYREG_PICU0_INTTYPE6\r
-.set SCSI_Out__7__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG\r
-.set SCSI_Out__7__LCD_EN, CYREG_PRT0_LCD_EN\r
-.set SCSI_Out__7__MASK, 0x40\r
-.set SCSI_Out__7__PC, CYREG_PRT0_PC6\r
-.set SCSI_Out__7__PORT, 0\r
-.set SCSI_Out__7__PRT, CYREG_PRT0_PRT\r
-.set SCSI_Out__7__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL\r
-.set SCSI_Out__7__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN\r
-.set SCSI_Out__7__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0\r
-.set SCSI_Out__7__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1\r
-.set SCSI_Out__7__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0\r
-.set SCSI_Out__7__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1\r
-.set SCSI_Out__7__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT\r
-.set SCSI_Out__7__PS, CYREG_PRT0_PS\r
-.set SCSI_Out__7__SHIFT, 6\r
-.set SCSI_Out__7__SLW, CYREG_PRT0_SLW\r
-.set SCSI_Out__8__AG, CYREG_PRT0_AG\r
-.set SCSI_Out__8__AMUX, CYREG_PRT0_AMUX\r
-.set SCSI_Out__8__BIE, CYREG_PRT0_BIE\r
-.set SCSI_Out__8__BIT_MASK, CYREG_PRT0_BIT_MASK\r
-.set SCSI_Out__8__BYP, CYREG_PRT0_BYP\r
-.set SCSI_Out__8__CTL, CYREG_PRT0_CTL\r
-.set SCSI_Out__8__DM0, CYREG_PRT0_DM0\r
-.set SCSI_Out__8__DM1, CYREG_PRT0_DM1\r
-.set SCSI_Out__8__DM2, CYREG_PRT0_DM2\r
-.set SCSI_Out__8__DR, CYREG_PRT0_DR\r
-.set SCSI_Out__8__INP_DIS, CYREG_PRT0_INP_DIS\r
-.set SCSI_Out__8__INTTYPE, CYREG_PICU0_INTTYPE3\r
-.set SCSI_Out__8__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG\r
-.set SCSI_Out__8__LCD_EN, CYREG_PRT0_LCD_EN\r
-.set SCSI_Out__8__MASK, 0x08\r
-.set SCSI_Out__8__PC, CYREG_PRT0_PC3\r
-.set SCSI_Out__8__PORT, 0\r
-.set SCSI_Out__8__PRT, CYREG_PRT0_PRT\r
-.set SCSI_Out__8__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL\r
-.set SCSI_Out__8__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN\r
-.set SCSI_Out__8__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0\r
-.set SCSI_Out__8__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1\r
-.set SCSI_Out__8__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0\r
-.set SCSI_Out__8__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1\r
-.set SCSI_Out__8__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT\r
-.set SCSI_Out__8__PS, CYREG_PRT0_PS\r
-.set SCSI_Out__8__SHIFT, 3\r
-.set SCSI_Out__8__SLW, CYREG_PRT0_SLW\r
-.set SCSI_Out__9__AG, CYREG_PRT0_AG\r
-.set SCSI_Out__9__AMUX, CYREG_PRT0_AMUX\r
-.set SCSI_Out__9__BIE, CYREG_PRT0_BIE\r
-.set SCSI_Out__9__BIT_MASK, CYREG_PRT0_BIT_MASK\r
-.set SCSI_Out__9__BYP, CYREG_PRT0_BYP\r
-.set SCSI_Out__9__CTL, CYREG_PRT0_CTL\r
-.set SCSI_Out__9__DM0, CYREG_PRT0_DM0\r
-.set SCSI_Out__9__DM1, CYREG_PRT0_DM1\r
-.set SCSI_Out__9__DM2, CYREG_PRT0_DM2\r
-.set SCSI_Out__9__DR, CYREG_PRT0_DR\r
-.set SCSI_Out__9__INP_DIS, CYREG_PRT0_INP_DIS\r
-.set SCSI_Out__9__INTTYPE, CYREG_PICU0_INTTYPE2\r
-.set SCSI_Out__9__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG\r
-.set SCSI_Out__9__LCD_EN, CYREG_PRT0_LCD_EN\r
-.set SCSI_Out__9__MASK, 0x04\r
-.set SCSI_Out__9__PC, CYREG_PRT0_PC2\r
-.set SCSI_Out__9__PORT, 0\r
-.set SCSI_Out__9__PRT, CYREG_PRT0_PRT\r
-.set SCSI_Out__9__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL\r
-.set SCSI_Out__9__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN\r
-.set SCSI_Out__9__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0\r
-.set SCSI_Out__9__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1\r
-.set SCSI_Out__9__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0\r
-.set SCSI_Out__9__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1\r
-.set SCSI_Out__9__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT\r
-.set SCSI_Out__9__PS, CYREG_PRT0_PS\r
-.set SCSI_Out__9__SHIFT, 2\r
-.set SCSI_Out__9__SLW, CYREG_PRT0_SLW\r
-.set SCSI_Out__ACK__AG, CYREG_PRT6_AG\r
-.set SCSI_Out__ACK__AMUX, CYREG_PRT6_AMUX\r
-.set SCSI_Out__ACK__BIE, CYREG_PRT6_BIE\r
-.set SCSI_Out__ACK__BIT_MASK, CYREG_PRT6_BIT_MASK\r
-.set SCSI_Out__ACK__BYP, CYREG_PRT6_BYP\r
-.set SCSI_Out__ACK__CTL, CYREG_PRT6_CTL\r
-.set SCSI_Out__ACK__DM0, CYREG_PRT6_DM0\r
-.set SCSI_Out__ACK__DM1, CYREG_PRT6_DM1\r
-.set SCSI_Out__ACK__DM2, CYREG_PRT6_DM2\r
-.set SCSI_Out__ACK__DR, CYREG_PRT6_DR\r
-.set SCSI_Out__ACK__INP_DIS, CYREG_PRT6_INP_DIS\r
-.set SCSI_Out__ACK__INTTYPE, CYREG_PICU6_INTTYPE0\r
-.set SCSI_Out__ACK__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG\r
-.set SCSI_Out__ACK__LCD_EN, CYREG_PRT6_LCD_EN\r
-.set SCSI_Out__ACK__MASK, 0x01\r
-.set SCSI_Out__ACK__PC, CYREG_PRT6_PC0\r
-.set SCSI_Out__ACK__PORT, 6\r
-.set SCSI_Out__ACK__PRT, CYREG_PRT6_PRT\r
-.set SCSI_Out__ACK__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL\r
-.set SCSI_Out__ACK__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN\r
-.set SCSI_Out__ACK__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0\r
-.set SCSI_Out__ACK__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1\r
-.set SCSI_Out__ACK__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0\r
-.set SCSI_Out__ACK__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1\r
-.set SCSI_Out__ACK__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT\r
-.set SCSI_Out__ACK__PS, CYREG_PRT6_PS\r
-.set SCSI_Out__ACK__SHIFT, 0\r
-.set SCSI_Out__ACK__SLW, CYREG_PRT6_SLW\r
-.set SCSI_Out__ATN__AG, CYREG_PRT15_AG\r
-.set SCSI_Out__ATN__AMUX, CYREG_PRT15_AMUX\r
-.set SCSI_Out__ATN__BIE, CYREG_PRT15_BIE\r
-.set SCSI_Out__ATN__BIT_MASK, CYREG_PRT15_BIT_MASK\r
-.set SCSI_Out__ATN__BYP, CYREG_PRT15_BYP\r
-.set SCSI_Out__ATN__CTL, CYREG_PRT15_CTL\r
-.set SCSI_Out__ATN__DM0, CYREG_PRT15_DM0\r
-.set SCSI_Out__ATN__DM1, CYREG_PRT15_DM1\r
-.set SCSI_Out__ATN__DM2, CYREG_PRT15_DM2\r
-.set SCSI_Out__ATN__DR, CYREG_PRT15_DR\r
-.set SCSI_Out__ATN__INP_DIS, CYREG_PRT15_INP_DIS\r
-.set SCSI_Out__ATN__INTTYPE, CYREG_PICU15_INTTYPE4\r
-.set SCSI_Out__ATN__LCD_COM_SEG, CYREG_PRT15_LCD_COM_SEG\r
-.set SCSI_Out__ATN__LCD_EN, CYREG_PRT15_LCD_EN\r
-.set SCSI_Out__ATN__MASK, 0x10\r
-.set SCSI_Out__ATN__PC, CYREG_IO_PC_PRT15_PC4\r
-.set SCSI_Out__ATN__PORT, 15\r
-.set SCSI_Out__ATN__PRT, CYREG_PRT15_PRT\r
-.set SCSI_Out__ATN__PRTDSI__CAPS_SEL, CYREG_PRT15_CAPS_SEL\r
-.set SCSI_Out__ATN__PRTDSI__DBL_SYNC_IN, CYREG_PRT15_DBL_SYNC_IN\r
-.set SCSI_Out__ATN__PRTDSI__OE_SEL0, CYREG_PRT15_OE_SEL0\r
-.set SCSI_Out__ATN__PRTDSI__OE_SEL1, CYREG_PRT15_OE_SEL1\r
-.set SCSI_Out__ATN__PRTDSI__OUT_SEL0, CYREG_PRT15_OUT_SEL0\r
-.set SCSI_Out__ATN__PRTDSI__OUT_SEL1, CYREG_PRT15_OUT_SEL1\r
-.set SCSI_Out__ATN__PRTDSI__SYNC_OUT, CYREG_PRT15_SYNC_OUT\r
-.set SCSI_Out__ATN__PS, CYREG_PRT15_PS\r
-.set SCSI_Out__ATN__SHIFT, 4\r
-.set SCSI_Out__ATN__SLW, CYREG_PRT15_SLW\r
-.set SCSI_Out__BSY__AG, CYREG_PRT6_AG\r
-.set SCSI_Out__BSY__AMUX, CYREG_PRT6_AMUX\r
-.set SCSI_Out__BSY__BIE, CYREG_PRT6_BIE\r
-.set SCSI_Out__BSY__BIT_MASK, CYREG_PRT6_BIT_MASK\r
-.set SCSI_Out__BSY__BYP, CYREG_PRT6_BYP\r
-.set SCSI_Out__BSY__CTL, CYREG_PRT6_CTL\r
-.set SCSI_Out__BSY__DM0, CYREG_PRT6_DM0\r
-.set SCSI_Out__BSY__DM1, CYREG_PRT6_DM1\r
-.set SCSI_Out__BSY__DM2, CYREG_PRT6_DM2\r
-.set SCSI_Out__BSY__DR, CYREG_PRT6_DR\r
-.set SCSI_Out__BSY__INP_DIS, CYREG_PRT6_INP_DIS\r
-.set SCSI_Out__BSY__INTTYPE, CYREG_PICU6_INTTYPE1\r
-.set SCSI_Out__BSY__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG\r
-.set SCSI_Out__BSY__LCD_EN, CYREG_PRT6_LCD_EN\r
-.set SCSI_Out__BSY__MASK, 0x02\r
-.set SCSI_Out__BSY__PC, CYREG_PRT6_PC1\r
-.set SCSI_Out__BSY__PORT, 6\r
-.set SCSI_Out__BSY__PRT, CYREG_PRT6_PRT\r
-.set SCSI_Out__BSY__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL\r
-.set SCSI_Out__BSY__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN\r
-.set SCSI_Out__BSY__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0\r
-.set SCSI_Out__BSY__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1\r
-.set SCSI_Out__BSY__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0\r
-.set SCSI_Out__BSY__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1\r
-.set SCSI_Out__BSY__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT\r
-.set SCSI_Out__BSY__PS, CYREG_PRT6_PS\r
-.set SCSI_Out__BSY__SHIFT, 1\r
-.set SCSI_Out__BSY__SLW, CYREG_PRT6_SLW\r
-.set SCSI_Out__CD_raw__AG, CYREG_PRT0_AG\r
-.set SCSI_Out__CD_raw__AMUX, CYREG_PRT0_AMUX\r
-.set SCSI_Out__CD_raw__BIE, CYREG_PRT0_BIE\r
-.set SCSI_Out__CD_raw__BIT_MASK, CYREG_PRT0_BIT_MASK\r
-.set SCSI_Out__CD_raw__BYP, CYREG_PRT0_BYP\r
-.set SCSI_Out__CD_raw__CTL, CYREG_PRT0_CTL\r
-.set SCSI_Out__CD_raw__DM0, CYREG_PRT0_DM0\r
-.set SCSI_Out__CD_raw__DM1, CYREG_PRT0_DM1\r
-.set SCSI_Out__CD_raw__DM2, CYREG_PRT0_DM2\r
-.set SCSI_Out__CD_raw__DR, CYREG_PRT0_DR\r
-.set SCSI_Out__CD_raw__INP_DIS, CYREG_PRT0_INP_DIS\r
-.set SCSI_Out__CD_raw__INTTYPE, CYREG_PICU0_INTTYPE6\r
-.set SCSI_Out__CD_raw__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG\r
-.set SCSI_Out__CD_raw__LCD_EN, CYREG_PRT0_LCD_EN\r
-.set SCSI_Out__CD_raw__MASK, 0x40\r
-.set SCSI_Out__CD_raw__PC, CYREG_PRT0_PC6\r
-.set SCSI_Out__CD_raw__PORT, 0\r
-.set SCSI_Out__CD_raw__PRT, CYREG_PRT0_PRT\r
-.set SCSI_Out__CD_raw__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL\r
-.set SCSI_Out__CD_raw__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN\r
-.set SCSI_Out__CD_raw__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0\r
-.set SCSI_Out__CD_raw__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1\r
-.set SCSI_Out__CD_raw__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0\r
-.set SCSI_Out__CD_raw__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1\r
-.set SCSI_Out__CD_raw__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT\r
-.set SCSI_Out__CD_raw__PS, CYREG_PRT0_PS\r
-.set SCSI_Out__CD_raw__SHIFT, 6\r
-.set SCSI_Out__CD_raw__SLW, CYREG_PRT0_SLW\r
-.set SCSI_Out__DBP_raw__AG, CYREG_PRT15_AG\r
-.set SCSI_Out__DBP_raw__AMUX, CYREG_PRT15_AMUX\r
-.set SCSI_Out__DBP_raw__BIE, CYREG_PRT15_BIE\r
-.set SCSI_Out__DBP_raw__BIT_MASK, CYREG_PRT15_BIT_MASK\r
-.set SCSI_Out__DBP_raw__BYP, CYREG_PRT15_BYP\r
-.set SCSI_Out__DBP_raw__CTL, CYREG_PRT15_CTL\r
-.set SCSI_Out__DBP_raw__DM0, CYREG_PRT15_DM0\r
-.set SCSI_Out__DBP_raw__DM1, CYREG_PRT15_DM1\r
-.set SCSI_Out__DBP_raw__DM2, CYREG_PRT15_DM2\r
-.set SCSI_Out__DBP_raw__DR, CYREG_PRT15_DR\r
-.set SCSI_Out__DBP_raw__INP_DIS, CYREG_PRT15_INP_DIS\r
-.set SCSI_Out__DBP_raw__INTTYPE, CYREG_PICU15_INTTYPE5\r
-.set SCSI_Out__DBP_raw__LCD_COM_SEG, CYREG_PRT15_LCD_COM_SEG\r
-.set SCSI_Out__DBP_raw__LCD_EN, CYREG_PRT15_LCD_EN\r
-.set SCSI_Out__DBP_raw__MASK, 0x20\r
-.set SCSI_Out__DBP_raw__PC, CYREG_IO_PC_PRT15_PC5\r
-.set SCSI_Out__DBP_raw__PORT, 15\r
-.set SCSI_Out__DBP_raw__PRT, CYREG_PRT15_PRT\r
-.set SCSI_Out__DBP_raw__PRTDSI__CAPS_SEL, CYREG_PRT15_CAPS_SEL\r
-.set SCSI_Out__DBP_raw__PRTDSI__DBL_SYNC_IN, CYREG_PRT15_DBL_SYNC_IN\r
-.set SCSI_Out__DBP_raw__PRTDSI__OE_SEL0, CYREG_PRT15_OE_SEL0\r
-.set SCSI_Out__DBP_raw__PRTDSI__OE_SEL1, CYREG_PRT15_OE_SEL1\r
-.set SCSI_Out__DBP_raw__PRTDSI__OUT_SEL0, CYREG_PRT15_OUT_SEL0\r
-.set SCSI_Out__DBP_raw__PRTDSI__OUT_SEL1, CYREG_PRT15_OUT_SEL1\r
-.set SCSI_Out__DBP_raw__PRTDSI__SYNC_OUT, CYREG_PRT15_SYNC_OUT\r
-.set SCSI_Out__DBP_raw__PS, CYREG_PRT15_PS\r
-.set SCSI_Out__DBP_raw__SHIFT, 5\r
-.set SCSI_Out__DBP_raw__SLW, CYREG_PRT15_SLW\r
-.set SCSI_Out__IO_raw__AG, CYREG_PRT0_AG\r
-.set SCSI_Out__IO_raw__AMUX, CYREG_PRT0_AMUX\r
-.set SCSI_Out__IO_raw__BIE, CYREG_PRT0_BIE\r
-.set SCSI_Out__IO_raw__BIT_MASK, CYREG_PRT0_BIT_MASK\r
-.set SCSI_Out__IO_raw__BYP, CYREG_PRT0_BYP\r
-.set SCSI_Out__IO_raw__CTL, CYREG_PRT0_CTL\r
-.set SCSI_Out__IO_raw__DM0, CYREG_PRT0_DM0\r
-.set SCSI_Out__IO_raw__DM1, CYREG_PRT0_DM1\r
-.set SCSI_Out__IO_raw__DM2, CYREG_PRT0_DM2\r
-.set SCSI_Out__IO_raw__DR, CYREG_PRT0_DR\r
-.set SCSI_Out__IO_raw__INP_DIS, CYREG_PRT0_INP_DIS\r
-.set SCSI_Out__IO_raw__INTTYPE, CYREG_PICU0_INTTYPE2\r
-.set SCSI_Out__IO_raw__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG\r
-.set SCSI_Out__IO_raw__LCD_EN, CYREG_PRT0_LCD_EN\r
-.set SCSI_Out__IO_raw__MASK, 0x04\r
-.set SCSI_Out__IO_raw__PC, CYREG_PRT0_PC2\r
-.set SCSI_Out__IO_raw__PORT, 0\r
-.set SCSI_Out__IO_raw__PRT, CYREG_PRT0_PRT\r
-.set SCSI_Out__IO_raw__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL\r
-.set SCSI_Out__IO_raw__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN\r
-.set SCSI_Out__IO_raw__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0\r
-.set SCSI_Out__IO_raw__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1\r
-.set SCSI_Out__IO_raw__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0\r
-.set SCSI_Out__IO_raw__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1\r
-.set SCSI_Out__IO_raw__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT\r
-.set SCSI_Out__IO_raw__PS, CYREG_PRT0_PS\r
-.set SCSI_Out__IO_raw__SHIFT, 2\r
-.set SCSI_Out__IO_raw__SLW, CYREG_PRT0_SLW\r
-.set SCSI_Out__MSG_raw__AG, CYREG_PRT4_AG\r
-.set SCSI_Out__MSG_raw__AMUX, CYREG_PRT4_AMUX\r
-.set SCSI_Out__MSG_raw__BIE, CYREG_PRT4_BIE\r
-.set SCSI_Out__MSG_raw__BIT_MASK, CYREG_PRT4_BIT_MASK\r
-.set SCSI_Out__MSG_raw__BYP, CYREG_PRT4_BYP\r
-.set SCSI_Out__MSG_raw__CTL, CYREG_PRT4_CTL\r
-.set SCSI_Out__MSG_raw__DM0, CYREG_PRT4_DM0\r
-.set SCSI_Out__MSG_raw__DM1, CYREG_PRT4_DM1\r
-.set SCSI_Out__MSG_raw__DM2, CYREG_PRT4_DM2\r
-.set SCSI_Out__MSG_raw__DR, CYREG_PRT4_DR\r
-.set SCSI_Out__MSG_raw__INP_DIS, CYREG_PRT4_INP_DIS\r
-.set SCSI_Out__MSG_raw__INTTYPE, CYREG_PICU4_INTTYPE4\r
-.set SCSI_Out__MSG_raw__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG\r
-.set SCSI_Out__MSG_raw__LCD_EN, CYREG_PRT4_LCD_EN\r
-.set SCSI_Out__MSG_raw__MASK, 0x10\r
-.set SCSI_Out__MSG_raw__PC, CYREG_PRT4_PC4\r
-.set SCSI_Out__MSG_raw__PORT, 4\r
-.set SCSI_Out__MSG_raw__PRT, CYREG_PRT4_PRT\r
-.set SCSI_Out__MSG_raw__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL\r
-.set SCSI_Out__MSG_raw__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN\r
-.set SCSI_Out__MSG_raw__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0\r
-.set SCSI_Out__MSG_raw__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1\r
-.set SCSI_Out__MSG_raw__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0\r
-.set SCSI_Out__MSG_raw__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1\r
-.set SCSI_Out__MSG_raw__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT\r
-.set SCSI_Out__MSG_raw__PS, CYREG_PRT4_PS\r
-.set SCSI_Out__MSG_raw__SHIFT, 4\r
-.set SCSI_Out__MSG_raw__SLW, CYREG_PRT4_SLW\r
-.set SCSI_Out__REQ__AG, CYREG_PRT0_AG\r
-.set SCSI_Out__REQ__AMUX, CYREG_PRT0_AMUX\r
-.set SCSI_Out__REQ__BIE, CYREG_PRT0_BIE\r
-.set SCSI_Out__REQ__BIT_MASK, CYREG_PRT0_BIT_MASK\r
-.set SCSI_Out__REQ__BYP, CYREG_PRT0_BYP\r
-.set SCSI_Out__REQ__CTL, CYREG_PRT0_CTL\r
-.set SCSI_Out__REQ__DM0, CYREG_PRT0_DM0\r
-.set SCSI_Out__REQ__DM1, CYREG_PRT0_DM1\r
-.set SCSI_Out__REQ__DM2, CYREG_PRT0_DM2\r
-.set SCSI_Out__REQ__DR, CYREG_PRT0_DR\r
-.set SCSI_Out__REQ__INP_DIS, CYREG_PRT0_INP_DIS\r
-.set SCSI_Out__REQ__INTTYPE, CYREG_PICU0_INTTYPE3\r
-.set SCSI_Out__REQ__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG\r
-.set SCSI_Out__REQ__LCD_EN, CYREG_PRT0_LCD_EN\r
-.set SCSI_Out__REQ__MASK, 0x08\r
-.set SCSI_Out__REQ__PC, CYREG_PRT0_PC3\r
-.set SCSI_Out__REQ__PORT, 0\r
-.set SCSI_Out__REQ__PRT, CYREG_PRT0_PRT\r
-.set SCSI_Out__REQ__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL\r
-.set SCSI_Out__REQ__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN\r
-.set SCSI_Out__REQ__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0\r
-.set SCSI_Out__REQ__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1\r
-.set SCSI_Out__REQ__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0\r
-.set SCSI_Out__REQ__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1\r
-.set SCSI_Out__REQ__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT\r
-.set SCSI_Out__REQ__PS, CYREG_PRT0_PS\r
-.set SCSI_Out__REQ__SHIFT, 3\r
-.set SCSI_Out__REQ__SLW, CYREG_PRT0_SLW\r
-.set SCSI_Out__RST__AG, CYREG_PRT4_AG\r
-.set SCSI_Out__RST__AMUX, CYREG_PRT4_AMUX\r
-.set SCSI_Out__RST__BIE, CYREG_PRT4_BIE\r
-.set SCSI_Out__RST__BIT_MASK, CYREG_PRT4_BIT_MASK\r
-.set SCSI_Out__RST__BYP, CYREG_PRT4_BYP\r
-.set SCSI_Out__RST__CTL, CYREG_PRT4_CTL\r
-.set SCSI_Out__RST__DM0, CYREG_PRT4_DM0\r
-.set SCSI_Out__RST__DM1, CYREG_PRT4_DM1\r
-.set SCSI_Out__RST__DM2, CYREG_PRT4_DM2\r
-.set SCSI_Out__RST__DR, CYREG_PRT4_DR\r
-.set SCSI_Out__RST__INP_DIS, CYREG_PRT4_INP_DIS\r
-.set SCSI_Out__RST__INTTYPE, CYREG_PICU4_INTTYPE5\r
-.set SCSI_Out__RST__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG\r
-.set SCSI_Out__RST__LCD_EN, CYREG_PRT4_LCD_EN\r
-.set SCSI_Out__RST__MASK, 0x20\r
-.set SCSI_Out__RST__PC, CYREG_PRT4_PC5\r
-.set SCSI_Out__RST__PORT, 4\r
-.set SCSI_Out__RST__PRT, CYREG_PRT4_PRT\r
-.set SCSI_Out__RST__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL\r
-.set SCSI_Out__RST__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN\r
-.set SCSI_Out__RST__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0\r
-.set SCSI_Out__RST__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1\r
-.set SCSI_Out__RST__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0\r
-.set SCSI_Out__RST__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1\r
-.set SCSI_Out__RST__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT\r
-.set SCSI_Out__RST__PS, CYREG_PRT4_PS\r
-.set SCSI_Out__RST__SHIFT, 5\r
-.set SCSI_Out__RST__SLW, CYREG_PRT4_SLW\r
-.set SCSI_Out__SEL__AG, CYREG_PRT0_AG\r
-.set SCSI_Out__SEL__AMUX, CYREG_PRT0_AMUX\r
-.set SCSI_Out__SEL__BIE, CYREG_PRT0_BIE\r
-.set SCSI_Out__SEL__BIT_MASK, CYREG_PRT0_BIT_MASK\r
-.set SCSI_Out__SEL__BYP, CYREG_PRT0_BYP\r
-.set SCSI_Out__SEL__CTL, CYREG_PRT0_CTL\r
-.set SCSI_Out__SEL__DM0, CYREG_PRT0_DM0\r
-.set SCSI_Out__SEL__DM1, CYREG_PRT0_DM1\r
-.set SCSI_Out__SEL__DM2, CYREG_PRT0_DM2\r
-.set SCSI_Out__SEL__DR, CYREG_PRT0_DR\r
-.set SCSI_Out__SEL__INP_DIS, CYREG_PRT0_INP_DIS\r
-.set SCSI_Out__SEL__INTTYPE, CYREG_PICU0_INTTYPE7\r
-.set SCSI_Out__SEL__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG\r
-.set SCSI_Out__SEL__LCD_EN, CYREG_PRT0_LCD_EN\r
-.set SCSI_Out__SEL__MASK, 0x80\r
-.set SCSI_Out__SEL__PC, CYREG_PRT0_PC7\r
-.set SCSI_Out__SEL__PORT, 0\r
-.set SCSI_Out__SEL__PRT, CYREG_PRT0_PRT\r
-.set SCSI_Out__SEL__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL\r
-.set SCSI_Out__SEL__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN\r
-.set SCSI_Out__SEL__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0\r
-.set SCSI_Out__SEL__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1\r
-.set SCSI_Out__SEL__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0\r
-.set SCSI_Out__SEL__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1\r
-.set SCSI_Out__SEL__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT\r
-.set SCSI_Out__SEL__PS, CYREG_PRT0_PS\r
-.set SCSI_Out__SEL__SHIFT, 7\r
-.set SCSI_Out__SEL__SLW, CYREG_PRT0_SLW\r
-\r
-/* SCSI_Out_Bits */\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__0__MASK, 0x01\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__0__POS, 0\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__1__MASK, 0x02\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__1__POS, 1\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB14_15_ACTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB14_15_CTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB14_15_CTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB14_15_CTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB14_15_CTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB14_15_MSK\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB14_15_MSK\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB14_15_MSK\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB14_15_MSK\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__2__MASK, 0x04\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__2__POS, 2\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__3__MASK, 0x08\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__3__POS, 3\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__4__MASK, 0x10\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__4__POS, 4\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__5__MASK, 0x20\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__5__POS, 5\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__6__MASK, 0x40\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__6__POS, 6\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__7__MASK, 0x80\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__7__POS, 7\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB14_ACTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB14_CTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB14_ST_CTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB14_CTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB14_ST_CTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__MASK, 0xFF\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB14_MSK_ACTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB14_MSK_ACTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB14_MSK\r
-\r
-/* SCSI_Out_Ctl */\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK, 0x01\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__0__POS, 0\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB12_13_ACTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB12_13_CTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB12_13_CTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB12_13_CTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB12_13_CTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB12_13_MSK\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB12_13_MSK\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB12_13_MSK\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB12_13_MSK\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB12_ACTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB12_CTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB12_ST_CTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB12_CTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB12_ST_CTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK, 0x01\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB12_MSK\r
-\r
-/* SCSI_Out_DBx */\r
-.set SCSI_Out_DBx__0__AG, CYREG_PRT5_AG\r
-.set SCSI_Out_DBx__0__AMUX, CYREG_PRT5_AMUX\r
-.set SCSI_Out_DBx__0__BIE, CYREG_PRT5_BIE\r
-.set SCSI_Out_DBx__0__BIT_MASK, CYREG_PRT5_BIT_MASK\r
-.set SCSI_Out_DBx__0__BYP, CYREG_PRT5_BYP\r
-.set SCSI_Out_DBx__0__CTL, CYREG_PRT5_CTL\r
-.set SCSI_Out_DBx__0__DM0, CYREG_PRT5_DM0\r
-.set SCSI_Out_DBx__0__DM1, CYREG_PRT5_DM1\r
-.set SCSI_Out_DBx__0__DM2, CYREG_PRT5_DM2\r
-.set SCSI_Out_DBx__0__DR, CYREG_PRT5_DR\r
-.set SCSI_Out_DBx__0__INP_DIS, CYREG_PRT5_INP_DIS\r
-.set SCSI_Out_DBx__0__INTTYPE, CYREG_PICU5_INTTYPE1\r
-.set SCSI_Out_DBx__0__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG\r
-.set SCSI_Out_DBx__0__LCD_EN, CYREG_PRT5_LCD_EN\r
-.set SCSI_Out_DBx__0__MASK, 0x02\r
-.set SCSI_Out_DBx__0__PC, CYREG_PRT5_PC1\r
-.set SCSI_Out_DBx__0__PORT, 5\r
-.set SCSI_Out_DBx__0__PRT, CYREG_PRT5_PRT\r
-.set SCSI_Out_DBx__0__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL\r
-.set SCSI_Out_DBx__0__PRTDSI__DBL_SYNC_IN, CYREG_PRT5_DBL_SYNC_IN\r
-.set SCSI_Out_DBx__0__PRTDSI__OE_SEL0, CYREG_PRT5_OE_SEL0\r
-.set SCSI_Out_DBx__0__PRTDSI__OE_SEL1, CYREG_PRT5_OE_SEL1\r
-.set SCSI_Out_DBx__0__PRTDSI__OUT_SEL0, CYREG_PRT5_OUT_SEL0\r
-.set SCSI_Out_DBx__0__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1\r
-.set SCSI_Out_DBx__0__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT\r
-.set SCSI_Out_DBx__0__PS, CYREG_PRT5_PS\r
-.set SCSI_Out_DBx__0__SHIFT, 1\r
-.set SCSI_Out_DBx__0__SLW, CYREG_PRT5_SLW\r
-.set SCSI_Out_DBx__1__AG, CYREG_PRT5_AG\r
-.set SCSI_Out_DBx__1__AMUX, CYREG_PRT5_AMUX\r
-.set SCSI_Out_DBx__1__BIE, CYREG_PRT5_BIE\r
-.set SCSI_Out_DBx__1__BIT_MASK, CYREG_PRT5_BIT_MASK\r
-.set SCSI_Out_DBx__1__BYP, CYREG_PRT5_BYP\r
-.set SCSI_Out_DBx__1__CTL, CYREG_PRT5_CTL\r
-.set SCSI_Out_DBx__1__DM0, CYREG_PRT5_DM0\r
-.set SCSI_Out_DBx__1__DM1, CYREG_PRT5_DM1\r
-.set SCSI_Out_DBx__1__DM2, CYREG_PRT5_DM2\r
-.set SCSI_Out_DBx__1__DR, CYREG_PRT5_DR\r
-.set SCSI_Out_DBx__1__INP_DIS, CYREG_PRT5_INP_DIS\r
-.set SCSI_Out_DBx__1__INTTYPE, CYREG_PICU5_INTTYPE0\r
-.set SCSI_Out_DBx__1__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG\r
-.set SCSI_Out_DBx__1__LCD_EN, CYREG_PRT5_LCD_EN\r
-.set SCSI_Out_DBx__1__MASK, 0x01\r
-.set SCSI_Out_DBx__1__PC, CYREG_PRT5_PC0\r
-.set SCSI_Out_DBx__1__PORT, 5\r
-.set SCSI_Out_DBx__1__PRT, CYREG_PRT5_PRT\r
-.set SCSI_Out_DBx__1__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL\r
-.set SCSI_Out_DBx__1__PRTDSI__DBL_SYNC_IN, CYREG_PRT5_DBL_SYNC_IN\r
-.set SCSI_Out_DBx__1__PRTDSI__OE_SEL0, CYREG_PRT5_OE_SEL0\r
-.set SCSI_Out_DBx__1__PRTDSI__OE_SEL1, CYREG_PRT5_OE_SEL1\r
-.set SCSI_Out_DBx__1__PRTDSI__OUT_SEL0, CYREG_PRT5_OUT_SEL0\r
-.set SCSI_Out_DBx__1__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1\r
-.set SCSI_Out_DBx__1__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT\r
-.set SCSI_Out_DBx__1__PS, CYREG_PRT5_PS\r
-.set SCSI_Out_DBx__1__SHIFT, 0\r
-.set SCSI_Out_DBx__1__SLW, CYREG_PRT5_SLW\r
-.set SCSI_Out_DBx__2__AG, CYREG_PRT6_AG\r
-.set SCSI_Out_DBx__2__AMUX, CYREG_PRT6_AMUX\r
-.set SCSI_Out_DBx__2__BIE, CYREG_PRT6_BIE\r
-.set SCSI_Out_DBx__2__BIT_MASK, CYREG_PRT6_BIT_MASK\r
-.set SCSI_Out_DBx__2__BYP, CYREG_PRT6_BYP\r
-.set SCSI_Out_DBx__2__CTL, CYREG_PRT6_CTL\r
-.set SCSI_Out_DBx__2__DM0, CYREG_PRT6_DM0\r
-.set SCSI_Out_DBx__2__DM1, CYREG_PRT6_DM1\r
-.set SCSI_Out_DBx__2__DM2, CYREG_PRT6_DM2\r
-.set SCSI_Out_DBx__2__DR, CYREG_PRT6_DR\r
-.set SCSI_Out_DBx__2__INP_DIS, CYREG_PRT6_INP_DIS\r
-.set SCSI_Out_DBx__2__INTTYPE, CYREG_PICU6_INTTYPE5\r
-.set SCSI_Out_DBx__2__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG\r
-.set SCSI_Out_DBx__2__LCD_EN, CYREG_PRT6_LCD_EN\r
-.set SCSI_Out_DBx__2__MASK, 0x20\r
-.set SCSI_Out_DBx__2__PC, CYREG_PRT6_PC5\r
-.set SCSI_Out_DBx__2__PORT, 6\r
-.set SCSI_Out_DBx__2__PRT, CYREG_PRT6_PRT\r
-.set SCSI_Out_DBx__2__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL\r
-.set SCSI_Out_DBx__2__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN\r
-.set SCSI_Out_DBx__2__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0\r
-.set SCSI_Out_DBx__2__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1\r
-.set SCSI_Out_DBx__2__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0\r
-.set SCSI_Out_DBx__2__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1\r
-.set SCSI_Out_DBx__2__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT\r
-.set SCSI_Out_DBx__2__PS, CYREG_PRT6_PS\r
-.set SCSI_Out_DBx__2__SHIFT, 5\r
-.set SCSI_Out_DBx__2__SLW, CYREG_PRT6_SLW\r
-.set SCSI_Out_DBx__3__AG, CYREG_PRT6_AG\r
-.set SCSI_Out_DBx__3__AMUX, CYREG_PRT6_AMUX\r
-.set SCSI_Out_DBx__3__BIE, CYREG_PRT6_BIE\r
-.set SCSI_Out_DBx__3__BIT_MASK, CYREG_PRT6_BIT_MASK\r
-.set SCSI_Out_DBx__3__BYP, CYREG_PRT6_BYP\r
-.set SCSI_Out_DBx__3__CTL, CYREG_PRT6_CTL\r
-.set SCSI_Out_DBx__3__DM0, CYREG_PRT6_DM0\r
-.set SCSI_Out_DBx__3__DM1, CYREG_PRT6_DM1\r
-.set SCSI_Out_DBx__3__DM2, CYREG_PRT6_DM2\r
-.set SCSI_Out_DBx__3__DR, CYREG_PRT6_DR\r
-.set SCSI_Out_DBx__3__INP_DIS, CYREG_PRT6_INP_DIS\r
-.set SCSI_Out_DBx__3__INTTYPE, CYREG_PICU6_INTTYPE4\r
-.set SCSI_Out_DBx__3__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG\r
-.set SCSI_Out_DBx__3__LCD_EN, CYREG_PRT6_LCD_EN\r
-.set SCSI_Out_DBx__3__MASK, 0x10\r
-.set SCSI_Out_DBx__3__PC, CYREG_PRT6_PC4\r
-.set SCSI_Out_DBx__3__PORT, 6\r
-.set SCSI_Out_DBx__3__PRT, CYREG_PRT6_PRT\r
-.set SCSI_Out_DBx__3__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL\r
-.set SCSI_Out_DBx__3__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN\r
-.set SCSI_Out_DBx__3__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0\r
-.set SCSI_Out_DBx__3__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1\r
-.set SCSI_Out_DBx__3__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0\r
-.set SCSI_Out_DBx__3__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1\r
-.set SCSI_Out_DBx__3__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT\r
-.set SCSI_Out_DBx__3__PS, CYREG_PRT6_PS\r
-.set SCSI_Out_DBx__3__SHIFT, 4\r
-.set SCSI_Out_DBx__3__SLW, CYREG_PRT6_SLW\r
-.set SCSI_Out_DBx__4__AG, CYREG_PRT2_AG\r
-.set SCSI_Out_DBx__4__AMUX, CYREG_PRT2_AMUX\r
-.set SCSI_Out_DBx__4__BIE, CYREG_PRT2_BIE\r
-.set SCSI_Out_DBx__4__BIT_MASK, CYREG_PRT2_BIT_MASK\r
-.set SCSI_Out_DBx__4__BYP, CYREG_PRT2_BYP\r
-.set SCSI_Out_DBx__4__CTL, CYREG_PRT2_CTL\r
-.set SCSI_Out_DBx__4__DM0, CYREG_PRT2_DM0\r
-.set SCSI_Out_DBx__4__DM1, CYREG_PRT2_DM1\r
-.set SCSI_Out_DBx__4__DM2, CYREG_PRT2_DM2\r
-.set SCSI_Out_DBx__4__DR, CYREG_PRT2_DR\r
-.set SCSI_Out_DBx__4__INP_DIS, CYREG_PRT2_INP_DIS\r
-.set SCSI_Out_DBx__4__INTTYPE, CYREG_PICU2_INTTYPE7\r
-.set SCSI_Out_DBx__4__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG\r
-.set SCSI_Out_DBx__4__LCD_EN, CYREG_PRT2_LCD_EN\r
-.set SCSI_Out_DBx__4__MASK, 0x80\r
-.set SCSI_Out_DBx__4__PC, CYREG_PRT2_PC7\r
-.set SCSI_Out_DBx__4__PORT, 2\r
-.set SCSI_Out_DBx__4__PRT, CYREG_PRT2_PRT\r
-.set SCSI_Out_DBx__4__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL\r
-.set SCSI_Out_DBx__4__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN\r
-.set SCSI_Out_DBx__4__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0\r
-.set SCSI_Out_DBx__4__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1\r
-.set SCSI_Out_DBx__4__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0\r
-.set SCSI_Out_DBx__4__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1\r
-.set SCSI_Out_DBx__4__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT\r
-.set SCSI_Out_DBx__4__PS, CYREG_PRT2_PS\r
-.set SCSI_Out_DBx__4__SHIFT, 7\r
-.set SCSI_Out_DBx__4__SLW, CYREG_PRT2_SLW\r
-.set SCSI_Out_DBx__5__AG, CYREG_PRT2_AG\r
-.set SCSI_Out_DBx__5__AMUX, CYREG_PRT2_AMUX\r
-.set SCSI_Out_DBx__5__BIE, CYREG_PRT2_BIE\r
-.set SCSI_Out_DBx__5__BIT_MASK, CYREG_PRT2_BIT_MASK\r
-.set SCSI_Out_DBx__5__BYP, CYREG_PRT2_BYP\r
-.set SCSI_Out_DBx__5__CTL, CYREG_PRT2_CTL\r
-.set SCSI_Out_DBx__5__DM0, CYREG_PRT2_DM0\r
-.set SCSI_Out_DBx__5__DM1, CYREG_PRT2_DM1\r
-.set SCSI_Out_DBx__5__DM2, CYREG_PRT2_DM2\r
-.set SCSI_Out_DBx__5__DR, CYREG_PRT2_DR\r
-.set SCSI_Out_DBx__5__INP_DIS, CYREG_PRT2_INP_DIS\r
-.set SCSI_Out_DBx__5__INTTYPE, CYREG_PICU2_INTTYPE6\r
-.set SCSI_Out_DBx__5__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG\r
-.set SCSI_Out_DBx__5__LCD_EN, CYREG_PRT2_LCD_EN\r
-.set SCSI_Out_DBx__5__MASK, 0x40\r
-.set SCSI_Out_DBx__5__PC, CYREG_PRT2_PC6\r
-.set SCSI_Out_DBx__5__PORT, 2\r
-.set SCSI_Out_DBx__5__PRT, CYREG_PRT2_PRT\r
-.set SCSI_Out_DBx__5__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL\r
-.set SCSI_Out_DBx__5__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN\r
-.set SCSI_Out_DBx__5__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0\r
-.set SCSI_Out_DBx__5__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1\r
-.set SCSI_Out_DBx__5__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0\r
-.set SCSI_Out_DBx__5__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1\r
-.set SCSI_Out_DBx__5__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT\r
-.set SCSI_Out_DBx__5__PS, CYREG_PRT2_PS\r
-.set SCSI_Out_DBx__5__SHIFT, 6\r
-.set SCSI_Out_DBx__5__SLW, CYREG_PRT2_SLW\r
-.set SCSI_Out_DBx__6__AG, CYREG_PRT2_AG\r
-.set SCSI_Out_DBx__6__AMUX, CYREG_PRT2_AMUX\r
-.set SCSI_Out_DBx__6__BIE, CYREG_PRT2_BIE\r
-.set SCSI_Out_DBx__6__BIT_MASK, CYREG_PRT2_BIT_MASK\r
-.set SCSI_Out_DBx__6__BYP, CYREG_PRT2_BYP\r
-.set SCSI_Out_DBx__6__CTL, CYREG_PRT2_CTL\r
-.set SCSI_Out_DBx__6__DM0, CYREG_PRT2_DM0\r
-.set SCSI_Out_DBx__6__DM1, CYREG_PRT2_DM1\r
-.set SCSI_Out_DBx__6__DM2, CYREG_PRT2_DM2\r
-.set SCSI_Out_DBx__6__DR, CYREG_PRT2_DR\r
-.set SCSI_Out_DBx__6__INP_DIS, CYREG_PRT2_INP_DIS\r
-.set SCSI_Out_DBx__6__INTTYPE, CYREG_PICU2_INTTYPE3\r
-.set SCSI_Out_DBx__6__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG\r
-.set SCSI_Out_DBx__6__LCD_EN, CYREG_PRT2_LCD_EN\r
-.set SCSI_Out_DBx__6__MASK, 0x08\r
-.set SCSI_Out_DBx__6__PC, CYREG_PRT2_PC3\r
-.set SCSI_Out_DBx__6__PORT, 2\r
-.set SCSI_Out_DBx__6__PRT, CYREG_PRT2_PRT\r
-.set SCSI_Out_DBx__6__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL\r
-.set SCSI_Out_DBx__6__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN\r
-.set SCSI_Out_DBx__6__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0\r
-.set SCSI_Out_DBx__6__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1\r
-.set SCSI_Out_DBx__6__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0\r
-.set SCSI_Out_DBx__6__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1\r
-.set SCSI_Out_DBx__6__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT\r
-.set SCSI_Out_DBx__6__PS, CYREG_PRT2_PS\r
-.set SCSI_Out_DBx__6__SHIFT, 3\r
-.set SCSI_Out_DBx__6__SLW, CYREG_PRT2_SLW\r
-.set SCSI_Out_DBx__7__AG, CYREG_PRT2_AG\r
-.set SCSI_Out_DBx__7__AMUX, CYREG_PRT2_AMUX\r
-.set SCSI_Out_DBx__7__BIE, CYREG_PRT2_BIE\r
-.set SCSI_Out_DBx__7__BIT_MASK, CYREG_PRT2_BIT_MASK\r
-.set SCSI_Out_DBx__7__BYP, CYREG_PRT2_BYP\r
-.set SCSI_Out_DBx__7__CTL, CYREG_PRT2_CTL\r
-.set SCSI_Out_DBx__7__DM0, CYREG_PRT2_DM0\r
-.set SCSI_Out_DBx__7__DM1, CYREG_PRT2_DM1\r
-.set SCSI_Out_DBx__7__DM2, CYREG_PRT2_DM2\r
-.set SCSI_Out_DBx__7__DR, CYREG_PRT2_DR\r
-.set SCSI_Out_DBx__7__INP_DIS, CYREG_PRT2_INP_DIS\r
-.set SCSI_Out_DBx__7__INTTYPE, CYREG_PICU2_INTTYPE2\r
-.set SCSI_Out_DBx__7__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG\r
-.set SCSI_Out_DBx__7__LCD_EN, CYREG_PRT2_LCD_EN\r
-.set SCSI_Out_DBx__7__MASK, 0x04\r
-.set SCSI_Out_DBx__7__PC, CYREG_PRT2_PC2\r
-.set SCSI_Out_DBx__7__PORT, 2\r
-.set SCSI_Out_DBx__7__PRT, CYREG_PRT2_PRT\r
-.set SCSI_Out_DBx__7__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL\r
-.set SCSI_Out_DBx__7__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN\r
-.set SCSI_Out_DBx__7__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0\r
-.set SCSI_Out_DBx__7__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1\r
-.set SCSI_Out_DBx__7__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0\r
-.set SCSI_Out_DBx__7__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1\r
-.set SCSI_Out_DBx__7__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT\r
-.set SCSI_Out_DBx__7__PS, CYREG_PRT2_PS\r
-.set SCSI_Out_DBx__7__SHIFT, 2\r
-.set SCSI_Out_DBx__7__SLW, CYREG_PRT2_SLW\r
-.set SCSI_Out_DBx__DB0__AG, CYREG_PRT5_AG\r
-.set SCSI_Out_DBx__DB0__AMUX, CYREG_PRT5_AMUX\r
-.set SCSI_Out_DBx__DB0__BIE, CYREG_PRT5_BIE\r
-.set SCSI_Out_DBx__DB0__BIT_MASK, CYREG_PRT5_BIT_MASK\r
-.set SCSI_Out_DBx__DB0__BYP, CYREG_PRT5_BYP\r
-.set SCSI_Out_DBx__DB0__CTL, CYREG_PRT5_CTL\r
-.set SCSI_Out_DBx__DB0__DM0, CYREG_PRT5_DM0\r
-.set SCSI_Out_DBx__DB0__DM1, CYREG_PRT5_DM1\r
-.set SCSI_Out_DBx__DB0__DM2, CYREG_PRT5_DM2\r
-.set SCSI_Out_DBx__DB0__DR, CYREG_PRT5_DR\r
-.set SCSI_Out_DBx__DB0__INP_DIS, CYREG_PRT5_INP_DIS\r
-.set SCSI_Out_DBx__DB0__INTTYPE, CYREG_PICU5_INTTYPE1\r
-.set SCSI_Out_DBx__DB0__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG\r
-.set SCSI_Out_DBx__DB0__LCD_EN, CYREG_PRT5_LCD_EN\r
-.set SCSI_Out_DBx__DB0__MASK, 0x02\r
-.set SCSI_Out_DBx__DB0__PC, CYREG_PRT5_PC1\r
-.set SCSI_Out_DBx__DB0__PORT, 5\r
-.set SCSI_Out_DBx__DB0__PRT, CYREG_PRT5_PRT\r
-.set SCSI_Out_DBx__DB0__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL\r
-.set SCSI_Out_DBx__DB0__PRTDSI__DBL_SYNC_IN, CYREG_PRT5_DBL_SYNC_IN\r
-.set SCSI_Out_DBx__DB0__PRTDSI__OE_SEL0, CYREG_PRT5_OE_SEL0\r
-.set SCSI_Out_DBx__DB0__PRTDSI__OE_SEL1, CYREG_PRT5_OE_SEL1\r
-.set SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL0, CYREG_PRT5_OUT_SEL0\r
-.set SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1\r
-.set SCSI_Out_DBx__DB0__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT\r
-.set SCSI_Out_DBx__DB0__PS, CYREG_PRT5_PS\r
-.set SCSI_Out_DBx__DB0__SHIFT, 1\r
-.set SCSI_Out_DBx__DB0__SLW, CYREG_PRT5_SLW\r
-.set SCSI_Out_DBx__DB1__AG, CYREG_PRT5_AG\r
-.set SCSI_Out_DBx__DB1__AMUX, CYREG_PRT5_AMUX\r
-.set SCSI_Out_DBx__DB1__BIE, CYREG_PRT5_BIE\r
-.set SCSI_Out_DBx__DB1__BIT_MASK, CYREG_PRT5_BIT_MASK\r
-.set SCSI_Out_DBx__DB1__BYP, CYREG_PRT5_BYP\r
-.set SCSI_Out_DBx__DB1__CTL, CYREG_PRT5_CTL\r
-.set SCSI_Out_DBx__DB1__DM0, CYREG_PRT5_DM0\r
-.set SCSI_Out_DBx__DB1__DM1, CYREG_PRT5_DM1\r
-.set SCSI_Out_DBx__DB1__DM2, CYREG_PRT5_DM2\r
-.set SCSI_Out_DBx__DB1__DR, CYREG_PRT5_DR\r
-.set SCSI_Out_DBx__DB1__INP_DIS, CYREG_PRT5_INP_DIS\r
-.set SCSI_Out_DBx__DB1__INTTYPE, CYREG_PICU5_INTTYPE0\r
-.set SCSI_Out_DBx__DB1__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG\r
-.set SCSI_Out_DBx__DB1__LCD_EN, CYREG_PRT5_LCD_EN\r
-.set SCSI_Out_DBx__DB1__MASK, 0x01\r
-.set SCSI_Out_DBx__DB1__PC, CYREG_PRT5_PC0\r
-.set SCSI_Out_DBx__DB1__PORT, 5\r
-.set SCSI_Out_DBx__DB1__PRT, CYREG_PRT5_PRT\r
-.set SCSI_Out_DBx__DB1__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL\r
-.set SCSI_Out_DBx__DB1__PRTDSI__DBL_SYNC_IN, CYREG_PRT5_DBL_SYNC_IN\r
-.set SCSI_Out_DBx__DB1__PRTDSI__OE_SEL0, CYREG_PRT5_OE_SEL0\r
-.set SCSI_Out_DBx__DB1__PRTDSI__OE_SEL1, CYREG_PRT5_OE_SEL1\r
-.set SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL0, CYREG_PRT5_OUT_SEL0\r
-.set SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1\r
-.set SCSI_Out_DBx__DB1__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT\r
-.set SCSI_Out_DBx__DB1__PS, CYREG_PRT5_PS\r
-.set SCSI_Out_DBx__DB1__SHIFT, 0\r
-.set SCSI_Out_DBx__DB1__SLW, CYREG_PRT5_SLW\r
-.set SCSI_Out_DBx__DB2__AG, CYREG_PRT6_AG\r
-.set SCSI_Out_DBx__DB2__AMUX, CYREG_PRT6_AMUX\r
-.set SCSI_Out_DBx__DB2__BIE, CYREG_PRT6_BIE\r
-.set SCSI_Out_DBx__DB2__BIT_MASK, CYREG_PRT6_BIT_MASK\r
-.set SCSI_Out_DBx__DB2__BYP, CYREG_PRT6_BYP\r
-.set SCSI_Out_DBx__DB2__CTL, CYREG_PRT6_CTL\r
-.set SCSI_Out_DBx__DB2__DM0, CYREG_PRT6_DM0\r
-.set SCSI_Out_DBx__DB2__DM1, CYREG_PRT6_DM1\r
-.set SCSI_Out_DBx__DB2__DM2, CYREG_PRT6_DM2\r
-.set SCSI_Out_DBx__DB2__DR, CYREG_PRT6_DR\r
-.set SCSI_Out_DBx__DB2__INP_DIS, CYREG_PRT6_INP_DIS\r
-.set SCSI_Out_DBx__DB2__INTTYPE, CYREG_PICU6_INTTYPE5\r
-.set SCSI_Out_DBx__DB2__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG\r
-.set SCSI_Out_DBx__DB2__LCD_EN, CYREG_PRT6_LCD_EN\r
-.set SCSI_Out_DBx__DB2__MASK, 0x20\r
-.set SCSI_Out_DBx__DB2__PC, CYREG_PRT6_PC5\r
-.set SCSI_Out_DBx__DB2__PORT, 6\r
-.set SCSI_Out_DBx__DB2__PRT, CYREG_PRT6_PRT\r
-.set SCSI_Out_DBx__DB2__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL\r
-.set SCSI_Out_DBx__DB2__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN\r
-.set SCSI_Out_DBx__DB2__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0\r
-.set SCSI_Out_DBx__DB2__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1\r
-.set SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0\r
-.set SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1\r
-.set SCSI_Out_DBx__DB2__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT\r
-.set SCSI_Out_DBx__DB2__PS, CYREG_PRT6_PS\r
-.set SCSI_Out_DBx__DB2__SHIFT, 5\r
-.set SCSI_Out_DBx__DB2__SLW, CYREG_PRT6_SLW\r
-.set SCSI_Out_DBx__DB3__AG, CYREG_PRT6_AG\r
-.set SCSI_Out_DBx__DB3__AMUX, CYREG_PRT6_AMUX\r
-.set SCSI_Out_DBx__DB3__BIE, CYREG_PRT6_BIE\r
-.set SCSI_Out_DBx__DB3__BIT_MASK, CYREG_PRT6_BIT_MASK\r
-.set SCSI_Out_DBx__DB3__BYP, CYREG_PRT6_BYP\r
-.set SCSI_Out_DBx__DB3__CTL, CYREG_PRT6_CTL\r
-.set SCSI_Out_DBx__DB3__DM0, CYREG_PRT6_DM0\r
-.set SCSI_Out_DBx__DB3__DM1, CYREG_PRT6_DM1\r
-.set SCSI_Out_DBx__DB3__DM2, CYREG_PRT6_DM2\r
-.set SCSI_Out_DBx__DB3__DR, CYREG_PRT6_DR\r
-.set SCSI_Out_DBx__DB3__INP_DIS, CYREG_PRT6_INP_DIS\r
-.set SCSI_Out_DBx__DB3__INTTYPE, CYREG_PICU6_INTTYPE4\r
-.set SCSI_Out_DBx__DB3__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG\r
-.set SCSI_Out_DBx__DB3__LCD_EN, CYREG_PRT6_LCD_EN\r
-.set SCSI_Out_DBx__DB3__MASK, 0x10\r
-.set SCSI_Out_DBx__DB3__PC, CYREG_PRT6_PC4\r
-.set SCSI_Out_DBx__DB3__PORT, 6\r
-.set SCSI_Out_DBx__DB3__PRT, CYREG_PRT6_PRT\r
-.set SCSI_Out_DBx__DB3__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL\r
-.set SCSI_Out_DBx__DB3__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN\r
-.set SCSI_Out_DBx__DB3__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0\r
-.set SCSI_Out_DBx__DB3__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1\r
-.set SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0\r
-.set SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1\r
-.set SCSI_Out_DBx__DB3__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT\r
-.set SCSI_Out_DBx__DB3__PS, CYREG_PRT6_PS\r
-.set SCSI_Out_DBx__DB3__SHIFT, 4\r
-.set SCSI_Out_DBx__DB3__SLW, CYREG_PRT6_SLW\r
-.set SCSI_Out_DBx__DB4__AG, CYREG_PRT2_AG\r
-.set SCSI_Out_DBx__DB4__AMUX, CYREG_PRT2_AMUX\r
-.set SCSI_Out_DBx__DB4__BIE, CYREG_PRT2_BIE\r
-.set SCSI_Out_DBx__DB4__BIT_MASK, CYREG_PRT2_BIT_MASK\r
-.set SCSI_Out_DBx__DB4__BYP, CYREG_PRT2_BYP\r
-.set SCSI_Out_DBx__DB4__CTL, CYREG_PRT2_CTL\r
-.set SCSI_Out_DBx__DB4__DM0, CYREG_PRT2_DM0\r
-.set SCSI_Out_DBx__DB4__DM1, CYREG_PRT2_DM1\r
-.set SCSI_Out_DBx__DB4__DM2, CYREG_PRT2_DM2\r
-.set SCSI_Out_DBx__DB4__DR, CYREG_PRT2_DR\r
-.set SCSI_Out_DBx__DB4__INP_DIS, CYREG_PRT2_INP_DIS\r
-.set SCSI_Out_DBx__DB4__INTTYPE, CYREG_PICU2_INTTYPE7\r
-.set SCSI_Out_DBx__DB4__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG\r
-.set SCSI_Out_DBx__DB4__LCD_EN, CYREG_PRT2_LCD_EN\r
-.set SCSI_Out_DBx__DB4__MASK, 0x80\r
-.set SCSI_Out_DBx__DB4__PC, CYREG_PRT2_PC7\r
-.set SCSI_Out_DBx__DB4__PORT, 2\r
-.set SCSI_Out_DBx__DB4__PRT, CYREG_PRT2_PRT\r
-.set SCSI_Out_DBx__DB4__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL\r
-.set SCSI_Out_DBx__DB4__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN\r
-.set SCSI_Out_DBx__DB4__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0\r
-.set SCSI_Out_DBx__DB4__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1\r
-.set SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0\r
-.set SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1\r
-.set SCSI_Out_DBx__DB4__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT\r
-.set SCSI_Out_DBx__DB4__PS, CYREG_PRT2_PS\r
-.set SCSI_Out_DBx__DB4__SHIFT, 7\r
-.set SCSI_Out_DBx__DB4__SLW, CYREG_PRT2_SLW\r
-.set SCSI_Out_DBx__DB5__AG, CYREG_PRT2_AG\r
-.set SCSI_Out_DBx__DB5__AMUX, CYREG_PRT2_AMUX\r
-.set SCSI_Out_DBx__DB5__BIE, CYREG_PRT2_BIE\r
-.set SCSI_Out_DBx__DB5__BIT_MASK, CYREG_PRT2_BIT_MASK\r
-.set SCSI_Out_DBx__DB5__BYP, CYREG_PRT2_BYP\r
-.set SCSI_Out_DBx__DB5__CTL, CYREG_PRT2_CTL\r
-.set SCSI_Out_DBx__DB5__DM0, CYREG_PRT2_DM0\r
-.set SCSI_Out_DBx__DB5__DM1, CYREG_PRT2_DM1\r
-.set SCSI_Out_DBx__DB5__DM2, CYREG_PRT2_DM2\r
-.set SCSI_Out_DBx__DB5__DR, CYREG_PRT2_DR\r
-.set SCSI_Out_DBx__DB5__INP_DIS, CYREG_PRT2_INP_DIS\r
-.set SCSI_Out_DBx__DB5__INTTYPE, CYREG_PICU2_INTTYPE6\r
-.set SCSI_Out_DBx__DB5__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG\r
-.set SCSI_Out_DBx__DB5__LCD_EN, CYREG_PRT2_LCD_EN\r
-.set SCSI_Out_DBx__DB5__MASK, 0x40\r
-.set SCSI_Out_DBx__DB5__PC, CYREG_PRT2_PC6\r
-.set SCSI_Out_DBx__DB5__PORT, 2\r
-.set SCSI_Out_DBx__DB5__PRT, CYREG_PRT2_PRT\r
-.set SCSI_Out_DBx__DB5__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL\r
-.set SCSI_Out_DBx__DB5__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN\r
-.set SCSI_Out_DBx__DB5__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0\r
-.set SCSI_Out_DBx__DB5__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1\r
-.set SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0\r
-.set SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1\r
-.set SCSI_Out_DBx__DB5__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT\r
-.set SCSI_Out_DBx__DB5__PS, CYREG_PRT2_PS\r
-.set SCSI_Out_DBx__DB5__SHIFT, 6\r
-.set SCSI_Out_DBx__DB5__SLW, CYREG_PRT2_SLW\r
-.set SCSI_Out_DBx__DB6__AG, CYREG_PRT2_AG\r
-.set SCSI_Out_DBx__DB6__AMUX, CYREG_PRT2_AMUX\r
-.set SCSI_Out_DBx__DB6__BIE, CYREG_PRT2_BIE\r
-.set SCSI_Out_DBx__DB6__BIT_MASK, CYREG_PRT2_BIT_MASK\r
-.set SCSI_Out_DBx__DB6__BYP, CYREG_PRT2_BYP\r
-.set SCSI_Out_DBx__DB6__CTL, CYREG_PRT2_CTL\r
-.set SCSI_Out_DBx__DB6__DM0, CYREG_PRT2_DM0\r
-.set SCSI_Out_DBx__DB6__DM1, CYREG_PRT2_DM1\r
-.set SCSI_Out_DBx__DB6__DM2, CYREG_PRT2_DM2\r
-.set SCSI_Out_DBx__DB6__DR, CYREG_PRT2_DR\r
-.set SCSI_Out_DBx__DB6__INP_DIS, CYREG_PRT2_INP_DIS\r
-.set SCSI_Out_DBx__DB6__INTTYPE, CYREG_PICU2_INTTYPE3\r
-.set SCSI_Out_DBx__DB6__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG\r
-.set SCSI_Out_DBx__DB6__LCD_EN, CYREG_PRT2_LCD_EN\r
-.set SCSI_Out_DBx__DB6__MASK, 0x08\r
-.set SCSI_Out_DBx__DB6__PC, CYREG_PRT2_PC3\r
-.set SCSI_Out_DBx__DB6__PORT, 2\r
-.set SCSI_Out_DBx__DB6__PRT, CYREG_PRT2_PRT\r
-.set SCSI_Out_DBx__DB6__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL\r
-.set SCSI_Out_DBx__DB6__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN\r
-.set SCSI_Out_DBx__DB6__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0\r
-.set SCSI_Out_DBx__DB6__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1\r
-.set SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0\r
-.set SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1\r
-.set SCSI_Out_DBx__DB6__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT\r
-.set SCSI_Out_DBx__DB6__PS, CYREG_PRT2_PS\r
-.set SCSI_Out_DBx__DB6__SHIFT, 3\r
-.set SCSI_Out_DBx__DB6__SLW, CYREG_PRT2_SLW\r
-.set SCSI_Out_DBx__DB7__AG, CYREG_PRT2_AG\r
-.set SCSI_Out_DBx__DB7__AMUX, CYREG_PRT2_AMUX\r
-.set SCSI_Out_DBx__DB7__BIE, CYREG_PRT2_BIE\r
-.set SCSI_Out_DBx__DB7__BIT_MASK, CYREG_PRT2_BIT_MASK\r
-.set SCSI_Out_DBx__DB7__BYP, CYREG_PRT2_BYP\r
-.set SCSI_Out_DBx__DB7__CTL, CYREG_PRT2_CTL\r
-.set SCSI_Out_DBx__DB7__DM0, CYREG_PRT2_DM0\r
-.set SCSI_Out_DBx__DB7__DM1, CYREG_PRT2_DM1\r
-.set SCSI_Out_DBx__DB7__DM2, CYREG_PRT2_DM2\r
-.set SCSI_Out_DBx__DB7__DR, CYREG_PRT2_DR\r
-.set SCSI_Out_DBx__DB7__INP_DIS, CYREG_PRT2_INP_DIS\r
-.set SCSI_Out_DBx__DB7__INTTYPE, CYREG_PICU2_INTTYPE2\r
-.set SCSI_Out_DBx__DB7__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG\r
-.set SCSI_Out_DBx__DB7__LCD_EN, CYREG_PRT2_LCD_EN\r
-.set SCSI_Out_DBx__DB7__MASK, 0x04\r
-.set SCSI_Out_DBx__DB7__PC, CYREG_PRT2_PC2\r
-.set SCSI_Out_DBx__DB7__PORT, 2\r
-.set SCSI_Out_DBx__DB7__PRT, CYREG_PRT2_PRT\r
-.set SCSI_Out_DBx__DB7__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL\r
-.set SCSI_Out_DBx__DB7__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN\r
-.set SCSI_Out_DBx__DB7__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0\r
-.set SCSI_Out_DBx__DB7__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1\r
-.set SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0\r
-.set SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1\r
-.set SCSI_Out_DBx__DB7__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT\r
-.set SCSI_Out_DBx__DB7__PS, CYREG_PRT2_PS\r
-.set SCSI_Out_DBx__DB7__SHIFT, 2\r
-.set SCSI_Out_DBx__DB7__SLW, CYREG_PRT2_SLW\r
-\r
-/* SD_RX_DMA */\r
-.set SD_RX_DMA__DRQ_CTL, CYREG_IDMUX_DRQ_CTL0\r
-.set SD_RX_DMA__DRQ_NUMBER, 2\r
-.set SD_RX_DMA__NUMBEROF_TDS, 0\r
-.set SD_RX_DMA__PRIORITY, 0\r
-.set SD_RX_DMA__TERMIN_EN, 0\r
-.set SD_RX_DMA__TERMIN_SEL, 0\r
-.set SD_RX_DMA__TERMOUT0_EN, 1\r
-.set SD_RX_DMA__TERMOUT0_SEL, 2\r
-.set SD_RX_DMA__TERMOUT1_EN, 0\r
-.set SD_RX_DMA__TERMOUT1_SEL, 0\r
-\r
-/* SD_RX_DMA_COMPLETE */\r
-.set SD_RX_DMA_COMPLETE__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
-.set SD_RX_DMA_COMPLETE__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
-.set SD_RX_DMA_COMPLETE__INTC_MASK, 0x20\r
-.set SD_RX_DMA_COMPLETE__INTC_NUMBER, 5\r
-.set SD_RX_DMA_COMPLETE__INTC_PRIOR_NUM, 7\r
-.set SD_RX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_5\r
-.set SD_RX_DMA_COMPLETE__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
-.set SD_RX_DMA_COMPLETE__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
-\r
-/* SD_TX_DMA */\r
-.set SD_TX_DMA__DRQ_CTL, CYREG_IDMUX_DRQ_CTL0\r
-.set SD_TX_DMA__DRQ_NUMBER, 3\r
-.set SD_TX_DMA__NUMBEROF_TDS, 0\r
-.set SD_TX_DMA__PRIORITY, 1\r
-.set SD_TX_DMA__TERMIN_EN, 0\r
-.set SD_TX_DMA__TERMIN_SEL, 0\r
-.set SD_TX_DMA__TERMOUT0_EN, 1\r
-.set SD_TX_DMA__TERMOUT0_SEL, 3\r
-.set SD_TX_DMA__TERMOUT1_EN, 0\r
-.set SD_TX_DMA__TERMOUT1_SEL, 0\r
-\r
-/* SD_TX_DMA_COMPLETE */\r
-.set SD_TX_DMA_COMPLETE__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
-.set SD_TX_DMA_COMPLETE__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
-.set SD_TX_DMA_COMPLETE__INTC_MASK, 0x40\r
-.set SD_TX_DMA_COMPLETE__INTC_NUMBER, 6\r
-.set SD_TX_DMA_COMPLETE__INTC_PRIOR_NUM, 7\r
-.set SD_TX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_6\r
-.set SD_TX_DMA_COMPLETE__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
-.set SD_TX_DMA_COMPLETE__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
+/* SCSI_In */\r
+.set SCSI_In__0__AG, CYREG_PRT2_AG\r
+.set SCSI_In__0__AMUX, CYREG_PRT2_AMUX\r
+.set SCSI_In__0__BIE, CYREG_PRT2_BIE\r
+.set SCSI_In__0__BIT_MASK, CYREG_PRT2_BIT_MASK\r
+.set SCSI_In__0__BYP, CYREG_PRT2_BYP\r
+.set SCSI_In__0__CTL, CYREG_PRT2_CTL\r
+.set SCSI_In__0__DM0, CYREG_PRT2_DM0\r
+.set SCSI_In__0__DM1, CYREG_PRT2_DM1\r
+.set SCSI_In__0__DM2, CYREG_PRT2_DM2\r
+.set SCSI_In__0__DR, CYREG_PRT2_DR\r
+.set SCSI_In__0__INP_DIS, CYREG_PRT2_INP_DIS\r
+.set SCSI_In__0__INTTYPE, CYREG_PICU2_INTTYPE1\r
+.set SCSI_In__0__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG\r
+.set SCSI_In__0__LCD_EN, CYREG_PRT2_LCD_EN\r
+.set SCSI_In__0__MASK, 0x02\r
+.set SCSI_In__0__PC, CYREG_PRT2_PC1\r
+.set SCSI_In__0__PORT, 2\r
+.set SCSI_In__0__PRT, CYREG_PRT2_PRT\r
+.set SCSI_In__0__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL\r
+.set SCSI_In__0__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN\r
+.set SCSI_In__0__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0\r
+.set SCSI_In__0__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1\r
+.set SCSI_In__0__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0\r
+.set SCSI_In__0__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1\r
+.set SCSI_In__0__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT\r
+.set SCSI_In__0__PS, CYREG_PRT2_PS\r
+.set SCSI_In__0__SHIFT, 1\r
+.set SCSI_In__0__SLW, CYREG_PRT2_SLW\r
+.set SCSI_In__1__AG, CYREG_PRT4_AG\r
+.set SCSI_In__1__AMUX, CYREG_PRT4_AMUX\r
+.set SCSI_In__1__BIE, CYREG_PRT4_BIE\r
+.set SCSI_In__1__BIT_MASK, CYREG_PRT4_BIT_MASK\r
+.set SCSI_In__1__BYP, CYREG_PRT4_BYP\r
+.set SCSI_In__1__CTL, CYREG_PRT4_CTL\r
+.set SCSI_In__1__DM0, CYREG_PRT4_DM0\r
+.set SCSI_In__1__DM1, CYREG_PRT4_DM1\r
+.set SCSI_In__1__DM2, CYREG_PRT4_DM2\r
+.set SCSI_In__1__DR, CYREG_PRT4_DR\r
+.set SCSI_In__1__INP_DIS, CYREG_PRT4_INP_DIS\r
+.set SCSI_In__1__INTTYPE, CYREG_PICU4_INTTYPE6\r
+.set SCSI_In__1__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG\r
+.set SCSI_In__1__LCD_EN, CYREG_PRT4_LCD_EN\r
+.set SCSI_In__1__MASK, 0x40\r
+.set SCSI_In__1__PC, CYREG_PRT4_PC6\r
+.set SCSI_In__1__PORT, 4\r
+.set SCSI_In__1__PRT, CYREG_PRT4_PRT\r
+.set SCSI_In__1__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL\r
+.set SCSI_In__1__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN\r
+.set SCSI_In__1__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0\r
+.set SCSI_In__1__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1\r
+.set SCSI_In__1__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0\r
+.set SCSI_In__1__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1\r
+.set SCSI_In__1__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT\r
+.set SCSI_In__1__PS, CYREG_PRT4_PS\r
+.set SCSI_In__1__SHIFT, 6\r
+.set SCSI_In__1__SLW, CYREG_PRT4_SLW\r
+.set SCSI_In__2__AG, CYREG_PRT4_AG\r
+.set SCSI_In__2__AMUX, CYREG_PRT4_AMUX\r
+.set SCSI_In__2__BIE, CYREG_PRT4_BIE\r
+.set SCSI_In__2__BIT_MASK, CYREG_PRT4_BIT_MASK\r
+.set SCSI_In__2__BYP, CYREG_PRT4_BYP\r
+.set SCSI_In__2__CTL, CYREG_PRT4_CTL\r
+.set SCSI_In__2__DM0, CYREG_PRT4_DM0\r
+.set SCSI_In__2__DM1, CYREG_PRT4_DM1\r
+.set SCSI_In__2__DM2, CYREG_PRT4_DM2\r
+.set SCSI_In__2__DR, CYREG_PRT4_DR\r
+.set SCSI_In__2__INP_DIS, CYREG_PRT4_INP_DIS\r
+.set SCSI_In__2__INTTYPE, CYREG_PICU4_INTTYPE2\r
+.set SCSI_In__2__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG\r
+.set SCSI_In__2__LCD_EN, CYREG_PRT4_LCD_EN\r
+.set SCSI_In__2__MASK, 0x04\r
+.set SCSI_In__2__PC, CYREG_PRT4_PC2\r
+.set SCSI_In__2__PORT, 4\r
+.set SCSI_In__2__PRT, CYREG_PRT4_PRT\r
+.set SCSI_In__2__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL\r
+.set SCSI_In__2__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN\r
+.set SCSI_In__2__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0\r
+.set SCSI_In__2__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1\r
+.set SCSI_In__2__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0\r
+.set SCSI_In__2__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1\r
+.set SCSI_In__2__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT\r
+.set SCSI_In__2__PS, CYREG_PRT4_PS\r
+.set SCSI_In__2__SHIFT, 2\r
+.set SCSI_In__2__SLW, CYREG_PRT4_SLW\r
+.set SCSI_In__3__AG, CYREG_PRT0_AG\r
+.set SCSI_In__3__AMUX, CYREG_PRT0_AMUX\r
+.set SCSI_In__3__BIE, CYREG_PRT0_BIE\r
+.set SCSI_In__3__BIT_MASK, CYREG_PRT0_BIT_MASK\r
+.set SCSI_In__3__BYP, CYREG_PRT0_BYP\r
+.set SCSI_In__3__CTL, CYREG_PRT0_CTL\r
+.set SCSI_In__3__DM0, CYREG_PRT0_DM0\r
+.set SCSI_In__3__DM1, CYREG_PRT0_DM1\r
+.set SCSI_In__3__DM2, CYREG_PRT0_DM2\r
+.set SCSI_In__3__DR, CYREG_PRT0_DR\r
+.set SCSI_In__3__INP_DIS, CYREG_PRT0_INP_DIS\r
+.set SCSI_In__3__INTTYPE, CYREG_PICU0_INTTYPE5\r
+.set SCSI_In__3__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG\r
+.set SCSI_In__3__LCD_EN, CYREG_PRT0_LCD_EN\r
+.set SCSI_In__3__MASK, 0x20\r
+.set SCSI_In__3__PC, CYREG_PRT0_PC5\r
+.set SCSI_In__3__PORT, 0\r
+.set SCSI_In__3__PRT, CYREG_PRT0_PRT\r
+.set SCSI_In__3__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL\r
+.set SCSI_In__3__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN\r
+.set SCSI_In__3__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0\r
+.set SCSI_In__3__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1\r
+.set SCSI_In__3__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0\r
+.set SCSI_In__3__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1\r
+.set SCSI_In__3__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT\r
+.set SCSI_In__3__PS, CYREG_PRT0_PS\r
+.set SCSI_In__3__SHIFT, 5\r
+.set SCSI_In__3__SLW, CYREG_PRT0_SLW\r
+.set SCSI_In__4__AG, CYREG_PRT0_AG\r
+.set SCSI_In__4__AMUX, CYREG_PRT0_AMUX\r
+.set SCSI_In__4__BIE, CYREG_PRT0_BIE\r
+.set SCSI_In__4__BIT_MASK, CYREG_PRT0_BIT_MASK\r
+.set SCSI_In__4__BYP, CYREG_PRT0_BYP\r
+.set SCSI_In__4__CTL, CYREG_PRT0_CTL\r
+.set SCSI_In__4__DM0, CYREG_PRT0_DM0\r
+.set SCSI_In__4__DM1, CYREG_PRT0_DM1\r
+.set SCSI_In__4__DM2, CYREG_PRT0_DM2\r
+.set SCSI_In__4__DR, CYREG_PRT0_DR\r
+.set SCSI_In__4__INP_DIS, CYREG_PRT0_INP_DIS\r
+.set SCSI_In__4__INTTYPE, CYREG_PICU0_INTTYPE4\r
+.set SCSI_In__4__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG\r
+.set SCSI_In__4__LCD_EN, CYREG_PRT0_LCD_EN\r
+.set SCSI_In__4__MASK, 0x10\r
+.set SCSI_In__4__PC, CYREG_PRT0_PC4\r
+.set SCSI_In__4__PORT, 0\r
+.set SCSI_In__4__PRT, CYREG_PRT0_PRT\r
+.set SCSI_In__4__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL\r
+.set SCSI_In__4__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN\r
+.set SCSI_In__4__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0\r
+.set SCSI_In__4__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1\r
+.set SCSI_In__4__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0\r
+.set SCSI_In__4__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1\r
+.set SCSI_In__4__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT\r
+.set SCSI_In__4__PS, CYREG_PRT0_PS\r
+.set SCSI_In__4__SHIFT, 4\r
+.set SCSI_In__4__SLW, CYREG_PRT0_SLW\r
+.set SCSI_In__CD__AG, CYREG_PRT4_AG\r
+.set SCSI_In__CD__AMUX, CYREG_PRT4_AMUX\r
+.set SCSI_In__CD__BIE, CYREG_PRT4_BIE\r
+.set SCSI_In__CD__BIT_MASK, CYREG_PRT4_BIT_MASK\r
+.set SCSI_In__CD__BYP, CYREG_PRT4_BYP\r
+.set SCSI_In__CD__CTL, CYREG_PRT4_CTL\r
+.set SCSI_In__CD__DM0, CYREG_PRT4_DM0\r
+.set SCSI_In__CD__DM1, CYREG_PRT4_DM1\r
+.set SCSI_In__CD__DM2, CYREG_PRT4_DM2\r
+.set SCSI_In__CD__DR, CYREG_PRT4_DR\r
+.set SCSI_In__CD__INP_DIS, CYREG_PRT4_INP_DIS\r
+.set SCSI_In__CD__INTTYPE, CYREG_PICU4_INTTYPE2\r
+.set SCSI_In__CD__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG\r
+.set SCSI_In__CD__LCD_EN, CYREG_PRT4_LCD_EN\r
+.set SCSI_In__CD__MASK, 0x04\r
+.set SCSI_In__CD__PC, CYREG_PRT4_PC2\r
+.set SCSI_In__CD__PORT, 4\r
+.set SCSI_In__CD__PRT, CYREG_PRT4_PRT\r
+.set SCSI_In__CD__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL\r
+.set SCSI_In__CD__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN\r
+.set SCSI_In__CD__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0\r
+.set SCSI_In__CD__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1\r
+.set SCSI_In__CD__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0\r
+.set SCSI_In__CD__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1\r
+.set SCSI_In__CD__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT\r
+.set SCSI_In__CD__PS, CYREG_PRT4_PS\r
+.set SCSI_In__CD__SHIFT, 2\r
+.set SCSI_In__CD__SLW, CYREG_PRT4_SLW\r
+.set SCSI_In__DBP__AG, CYREG_PRT2_AG\r
+.set SCSI_In__DBP__AMUX, CYREG_PRT2_AMUX\r
+.set SCSI_In__DBP__BIE, CYREG_PRT2_BIE\r
+.set SCSI_In__DBP__BIT_MASK, CYREG_PRT2_BIT_MASK\r
+.set SCSI_In__DBP__BYP, CYREG_PRT2_BYP\r
+.set SCSI_In__DBP__CTL, CYREG_PRT2_CTL\r
+.set SCSI_In__DBP__DM0, CYREG_PRT2_DM0\r
+.set SCSI_In__DBP__DM1, CYREG_PRT2_DM1\r
+.set SCSI_In__DBP__DM2, CYREG_PRT2_DM2\r
+.set SCSI_In__DBP__DR, CYREG_PRT2_DR\r
+.set SCSI_In__DBP__INP_DIS, CYREG_PRT2_INP_DIS\r
+.set SCSI_In__DBP__INTTYPE, CYREG_PICU2_INTTYPE1\r
+.set SCSI_In__DBP__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG\r
+.set SCSI_In__DBP__LCD_EN, CYREG_PRT2_LCD_EN\r
+.set SCSI_In__DBP__MASK, 0x02\r
+.set SCSI_In__DBP__PC, CYREG_PRT2_PC1\r
+.set SCSI_In__DBP__PORT, 2\r
+.set SCSI_In__DBP__PRT, CYREG_PRT2_PRT\r
+.set SCSI_In__DBP__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL\r
+.set SCSI_In__DBP__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN\r
+.set SCSI_In__DBP__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0\r
+.set SCSI_In__DBP__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1\r
+.set SCSI_In__DBP__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0\r
+.set SCSI_In__DBP__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1\r
+.set SCSI_In__DBP__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT\r
+.set SCSI_In__DBP__PS, CYREG_PRT2_PS\r
+.set SCSI_In__DBP__SHIFT, 1\r
+.set SCSI_In__DBP__SLW, CYREG_PRT2_SLW\r
+.set SCSI_In__IO__AG, CYREG_PRT0_AG\r
+.set SCSI_In__IO__AMUX, CYREG_PRT0_AMUX\r
+.set SCSI_In__IO__BIE, CYREG_PRT0_BIE\r
+.set SCSI_In__IO__BIT_MASK, CYREG_PRT0_BIT_MASK\r
+.set SCSI_In__IO__BYP, CYREG_PRT0_BYP\r
+.set SCSI_In__IO__CTL, CYREG_PRT0_CTL\r
+.set SCSI_In__IO__DM0, CYREG_PRT0_DM0\r
+.set SCSI_In__IO__DM1, CYREG_PRT0_DM1\r
+.set SCSI_In__IO__DM2, CYREG_PRT0_DM2\r
+.set SCSI_In__IO__DR, CYREG_PRT0_DR\r
+.set SCSI_In__IO__INP_DIS, CYREG_PRT0_INP_DIS\r
+.set SCSI_In__IO__INTTYPE, CYREG_PICU0_INTTYPE4\r
+.set SCSI_In__IO__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG\r
+.set SCSI_In__IO__LCD_EN, CYREG_PRT0_LCD_EN\r
+.set SCSI_In__IO__MASK, 0x10\r
+.set SCSI_In__IO__PC, CYREG_PRT0_PC4\r
+.set SCSI_In__IO__PORT, 0\r
+.set SCSI_In__IO__PRT, CYREG_PRT0_PRT\r
+.set SCSI_In__IO__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL\r
+.set SCSI_In__IO__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN\r
+.set SCSI_In__IO__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0\r
+.set SCSI_In__IO__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1\r
+.set SCSI_In__IO__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0\r
+.set SCSI_In__IO__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1\r
+.set SCSI_In__IO__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT\r
+.set SCSI_In__IO__PS, CYREG_PRT0_PS\r
+.set SCSI_In__IO__SHIFT, 4\r
+.set SCSI_In__IO__SLW, CYREG_PRT0_SLW\r
+.set SCSI_In__MSG__AG, CYREG_PRT4_AG\r
+.set SCSI_In__MSG__AMUX, CYREG_PRT4_AMUX\r
+.set SCSI_In__MSG__BIE, CYREG_PRT4_BIE\r
+.set SCSI_In__MSG__BIT_MASK, CYREG_PRT4_BIT_MASK\r
+.set SCSI_In__MSG__BYP, CYREG_PRT4_BYP\r
+.set SCSI_In__MSG__CTL, CYREG_PRT4_CTL\r
+.set SCSI_In__MSG__DM0, CYREG_PRT4_DM0\r
+.set SCSI_In__MSG__DM1, CYREG_PRT4_DM1\r
+.set SCSI_In__MSG__DM2, CYREG_PRT4_DM2\r
+.set SCSI_In__MSG__DR, CYREG_PRT4_DR\r
+.set SCSI_In__MSG__INP_DIS, CYREG_PRT4_INP_DIS\r
+.set SCSI_In__MSG__INTTYPE, CYREG_PICU4_INTTYPE6\r
+.set SCSI_In__MSG__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG\r
+.set SCSI_In__MSG__LCD_EN, CYREG_PRT4_LCD_EN\r
+.set SCSI_In__MSG__MASK, 0x40\r
+.set SCSI_In__MSG__PC, CYREG_PRT4_PC6\r
+.set SCSI_In__MSG__PORT, 4\r
+.set SCSI_In__MSG__PRT, CYREG_PRT4_PRT\r
+.set SCSI_In__MSG__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL\r
+.set SCSI_In__MSG__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN\r
+.set SCSI_In__MSG__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0\r
+.set SCSI_In__MSG__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1\r
+.set SCSI_In__MSG__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0\r
+.set SCSI_In__MSG__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1\r
+.set SCSI_In__MSG__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT\r
+.set SCSI_In__MSG__PS, CYREG_PRT4_PS\r
+.set SCSI_In__MSG__SHIFT, 6\r
+.set SCSI_In__MSG__SLW, CYREG_PRT4_SLW\r
+.set SCSI_In__REQ__AG, CYREG_PRT0_AG\r
+.set SCSI_In__REQ__AMUX, CYREG_PRT0_AMUX\r
+.set SCSI_In__REQ__BIE, CYREG_PRT0_BIE\r
+.set SCSI_In__REQ__BIT_MASK, CYREG_PRT0_BIT_MASK\r
+.set SCSI_In__REQ__BYP, CYREG_PRT0_BYP\r
+.set SCSI_In__REQ__CTL, CYREG_PRT0_CTL\r
+.set SCSI_In__REQ__DM0, CYREG_PRT0_DM0\r
+.set SCSI_In__REQ__DM1, CYREG_PRT0_DM1\r
+.set SCSI_In__REQ__DM2, CYREG_PRT0_DM2\r
+.set SCSI_In__REQ__DR, CYREG_PRT0_DR\r
+.set SCSI_In__REQ__INP_DIS, CYREG_PRT0_INP_DIS\r
+.set SCSI_In__REQ__INTTYPE, CYREG_PICU0_INTTYPE5\r
+.set SCSI_In__REQ__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG\r
+.set SCSI_In__REQ__LCD_EN, CYREG_PRT0_LCD_EN\r
+.set SCSI_In__REQ__MASK, 0x20\r
+.set SCSI_In__REQ__PC, CYREG_PRT0_PC5\r
+.set SCSI_In__REQ__PORT, 0\r
+.set SCSI_In__REQ__PRT, CYREG_PRT0_PRT\r
+.set SCSI_In__REQ__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL\r
+.set SCSI_In__REQ__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN\r
+.set SCSI_In__REQ__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0\r
+.set SCSI_In__REQ__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1\r
+.set SCSI_In__REQ__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0\r
+.set SCSI_In__REQ__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1\r
+.set SCSI_In__REQ__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT\r
+.set SCSI_In__REQ__PS, CYREG_PRT0_PS\r
+.set SCSI_In__REQ__SHIFT, 5\r
+.set SCSI_In__REQ__SLW, CYREG_PRT0_SLW\r
+.set SCSI_In_DBx__0__AG, CYREG_PRT5_AG\r
+.set SCSI_In_DBx__0__AMUX, CYREG_PRT5_AMUX\r
+.set SCSI_In_DBx__0__BIE, CYREG_PRT5_BIE\r
+.set SCSI_In_DBx__0__BIT_MASK, CYREG_PRT5_BIT_MASK\r
+.set SCSI_In_DBx__0__BYP, CYREG_PRT5_BYP\r
+.set SCSI_In_DBx__0__CTL, CYREG_PRT5_CTL\r
+.set SCSI_In_DBx__0__DM0, CYREG_PRT5_DM0\r
+.set SCSI_In_DBx__0__DM1, CYREG_PRT5_DM1\r
+.set SCSI_In_DBx__0__DM2, CYREG_PRT5_DM2\r
+.set SCSI_In_DBx__0__DR, CYREG_PRT5_DR\r
+.set SCSI_In_DBx__0__INP_DIS, CYREG_PRT5_INP_DIS\r
+.set SCSI_In_DBx__0__INTTYPE, CYREG_PICU5_INTTYPE3\r
+.set SCSI_In_DBx__0__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG\r
+.set SCSI_In_DBx__0__LCD_EN, CYREG_PRT5_LCD_EN\r
+.set SCSI_In_DBx__0__MASK, 0x08\r
+.set SCSI_In_DBx__0__PC, CYREG_PRT5_PC3\r
+.set SCSI_In_DBx__0__PORT, 5\r
+.set SCSI_In_DBx__0__PRT, CYREG_PRT5_PRT\r
+.set SCSI_In_DBx__0__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL\r
+.set SCSI_In_DBx__0__PRTDSI__DBL_SYNC_IN, CYREG_PRT5_DBL_SYNC_IN\r
+.set SCSI_In_DBx__0__PRTDSI__OE_SEL0, CYREG_PRT5_OE_SEL0\r
+.set SCSI_In_DBx__0__PRTDSI__OE_SEL1, CYREG_PRT5_OE_SEL1\r
+.set SCSI_In_DBx__0__PRTDSI__OUT_SEL0, CYREG_PRT5_OUT_SEL0\r
+.set SCSI_In_DBx__0__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1\r
+.set SCSI_In_DBx__0__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT\r
+.set SCSI_In_DBx__0__PS, CYREG_PRT5_PS\r
+.set SCSI_In_DBx__0__SHIFT, 3\r
+.set SCSI_In_DBx__0__SLW, CYREG_PRT5_SLW\r
+.set SCSI_In_DBx__1__AG, CYREG_PRT5_AG\r
+.set SCSI_In_DBx__1__AMUX, CYREG_PRT5_AMUX\r
+.set SCSI_In_DBx__1__BIE, CYREG_PRT5_BIE\r
+.set SCSI_In_DBx__1__BIT_MASK, CYREG_PRT5_BIT_MASK\r
+.set SCSI_In_DBx__1__BYP, CYREG_PRT5_BYP\r
+.set SCSI_In_DBx__1__CTL, CYREG_PRT5_CTL\r
+.set SCSI_In_DBx__1__DM0, CYREG_PRT5_DM0\r
+.set SCSI_In_DBx__1__DM1, CYREG_PRT5_DM1\r
+.set SCSI_In_DBx__1__DM2, CYREG_PRT5_DM2\r
+.set SCSI_In_DBx__1__DR, CYREG_PRT5_DR\r
+.set SCSI_In_DBx__1__INP_DIS, CYREG_PRT5_INP_DIS\r
+.set SCSI_In_DBx__1__INTTYPE, CYREG_PICU5_INTTYPE2\r
+.set SCSI_In_DBx__1__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG\r
+.set SCSI_In_DBx__1__LCD_EN, CYREG_PRT5_LCD_EN\r
+.set SCSI_In_DBx__1__MASK, 0x04\r
+.set SCSI_In_DBx__1__PC, CYREG_PRT5_PC2\r
+.set SCSI_In_DBx__1__PORT, 5\r
+.set SCSI_In_DBx__1__PRT, CYREG_PRT5_PRT\r
+.set SCSI_In_DBx__1__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL\r
+.set SCSI_In_DBx__1__PRTDSI__DBL_SYNC_IN, CYREG_PRT5_DBL_SYNC_IN\r
+.set SCSI_In_DBx__1__PRTDSI__OE_SEL0, CYREG_PRT5_OE_SEL0\r
+.set SCSI_In_DBx__1__PRTDSI__OE_SEL1, CYREG_PRT5_OE_SEL1\r
+.set SCSI_In_DBx__1__PRTDSI__OUT_SEL0, CYREG_PRT5_OUT_SEL0\r
+.set SCSI_In_DBx__1__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1\r
+.set SCSI_In_DBx__1__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT\r
+.set SCSI_In_DBx__1__PS, CYREG_PRT5_PS\r
+.set SCSI_In_DBx__1__SHIFT, 2\r
+.set SCSI_In_DBx__1__SLW, CYREG_PRT5_SLW\r
+.set SCSI_In_DBx__2__AG, CYREG_PRT6_AG\r
+.set SCSI_In_DBx__2__AMUX, CYREG_PRT6_AMUX\r
+.set SCSI_In_DBx__2__BIE, CYREG_PRT6_BIE\r
+.set SCSI_In_DBx__2__BIT_MASK, CYREG_PRT6_BIT_MASK\r
+.set SCSI_In_DBx__2__BYP, CYREG_PRT6_BYP\r
+.set SCSI_In_DBx__2__CTL, CYREG_PRT6_CTL\r
+.set SCSI_In_DBx__2__DM0, CYREG_PRT6_DM0\r
+.set SCSI_In_DBx__2__DM1, CYREG_PRT6_DM1\r
+.set SCSI_In_DBx__2__DM2, CYREG_PRT6_DM2\r
+.set SCSI_In_DBx__2__DR, CYREG_PRT6_DR\r
+.set SCSI_In_DBx__2__INP_DIS, CYREG_PRT6_INP_DIS\r
+.set SCSI_In_DBx__2__INTTYPE, CYREG_PICU6_INTTYPE7\r
+.set SCSI_In_DBx__2__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG\r
+.set SCSI_In_DBx__2__LCD_EN, CYREG_PRT6_LCD_EN\r
+.set SCSI_In_DBx__2__MASK, 0x80\r
+.set SCSI_In_DBx__2__PC, CYREG_PRT6_PC7\r
+.set SCSI_In_DBx__2__PORT, 6\r
+.set SCSI_In_DBx__2__PRT, CYREG_PRT6_PRT\r
+.set SCSI_In_DBx__2__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL\r
+.set SCSI_In_DBx__2__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN\r
+.set SCSI_In_DBx__2__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0\r
+.set SCSI_In_DBx__2__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1\r
+.set SCSI_In_DBx__2__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0\r
+.set SCSI_In_DBx__2__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1\r
+.set SCSI_In_DBx__2__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT\r
+.set SCSI_In_DBx__2__PS, CYREG_PRT6_PS\r
+.set SCSI_In_DBx__2__SHIFT, 7\r
+.set SCSI_In_DBx__2__SLW, CYREG_PRT6_SLW\r
+.set SCSI_In_DBx__3__AG, CYREG_PRT6_AG\r
+.set SCSI_In_DBx__3__AMUX, CYREG_PRT6_AMUX\r
+.set SCSI_In_DBx__3__BIE, CYREG_PRT6_BIE\r
+.set SCSI_In_DBx__3__BIT_MASK, CYREG_PRT6_BIT_MASK\r
+.set SCSI_In_DBx__3__BYP, CYREG_PRT6_BYP\r
+.set SCSI_In_DBx__3__CTL, CYREG_PRT6_CTL\r
+.set SCSI_In_DBx__3__DM0, CYREG_PRT6_DM0\r
+.set SCSI_In_DBx__3__DM1, CYREG_PRT6_DM1\r
+.set SCSI_In_DBx__3__DM2, CYREG_PRT6_DM2\r
+.set SCSI_In_DBx__3__DR, CYREG_PRT6_DR\r
+.set SCSI_In_DBx__3__INP_DIS, CYREG_PRT6_INP_DIS\r
+.set SCSI_In_DBx__3__INTTYPE, CYREG_PICU6_INTTYPE6\r
+.set SCSI_In_DBx__3__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG\r
+.set SCSI_In_DBx__3__LCD_EN, CYREG_PRT6_LCD_EN\r
+.set SCSI_In_DBx__3__MASK, 0x40\r
+.set SCSI_In_DBx__3__PC, CYREG_PRT6_PC6\r
+.set SCSI_In_DBx__3__PORT, 6\r
+.set SCSI_In_DBx__3__PRT, CYREG_PRT6_PRT\r
+.set SCSI_In_DBx__3__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL\r
+.set SCSI_In_DBx__3__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN\r
+.set SCSI_In_DBx__3__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0\r
+.set SCSI_In_DBx__3__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1\r
+.set SCSI_In_DBx__3__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0\r
+.set SCSI_In_DBx__3__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1\r
+.set SCSI_In_DBx__3__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT\r
+.set SCSI_In_DBx__3__PS, CYREG_PRT6_PS\r
+.set SCSI_In_DBx__3__SHIFT, 6\r
+.set SCSI_In_DBx__3__SLW, CYREG_PRT6_SLW\r
+.set SCSI_In_DBx__4__AG, CYREG_PRT12_AG\r
+.set SCSI_In_DBx__4__BIE, CYREG_PRT12_BIE\r
+.set SCSI_In_DBx__4__BIT_MASK, CYREG_PRT12_BIT_MASK\r
+.set SCSI_In_DBx__4__BYP, CYREG_PRT12_BYP\r
+.set SCSI_In_DBx__4__DM0, CYREG_PRT12_DM0\r
+.set SCSI_In_DBx__4__DM1, CYREG_PRT12_DM1\r
+.set SCSI_In_DBx__4__DM2, CYREG_PRT12_DM2\r
+.set SCSI_In_DBx__4__DR, CYREG_PRT12_DR\r
+.set SCSI_In_DBx__4__INP_DIS, CYREG_PRT12_INP_DIS\r
+.set SCSI_In_DBx__4__INTTYPE, CYREG_PICU12_INTTYPE5\r
+.set SCSI_In_DBx__4__MASK, 0x20\r
+.set SCSI_In_DBx__4__PC, CYREG_PRT12_PC5\r
+.set SCSI_In_DBx__4__PORT, 12\r
+.set SCSI_In_DBx__4__PRT, CYREG_PRT12_PRT\r
+.set SCSI_In_DBx__4__PRTDSI__DBL_SYNC_IN, CYREG_PRT12_DBL_SYNC_IN\r
+.set SCSI_In_DBx__4__PRTDSI__OE_SEL0, CYREG_PRT12_OE_SEL0\r
+.set SCSI_In_DBx__4__PRTDSI__OE_SEL1, CYREG_PRT12_OE_SEL1\r
+.set SCSI_In_DBx__4__PRTDSI__OUT_SEL0, CYREG_PRT12_OUT_SEL0\r
+.set SCSI_In_DBx__4__PRTDSI__OUT_SEL1, CYREG_PRT12_OUT_SEL1\r
+.set SCSI_In_DBx__4__PRTDSI__SYNC_OUT, CYREG_PRT12_SYNC_OUT\r
+.set SCSI_In_DBx__4__PS, CYREG_PRT12_PS\r
+.set SCSI_In_DBx__4__SHIFT, 5\r
+.set SCSI_In_DBx__4__SIO_CFG, CYREG_PRT12_SIO_CFG\r
+.set SCSI_In_DBx__4__SIO_DIFF, CYREG_PRT12_SIO_DIFF\r
+.set SCSI_In_DBx__4__SIO_HYST_EN, CYREG_PRT12_SIO_HYST_EN\r
+.set SCSI_In_DBx__4__SIO_REG_HIFREQ, CYREG_PRT12_SIO_REG_HIFREQ\r
+.set SCSI_In_DBx__4__SLW, CYREG_PRT12_SLW\r
+.set SCSI_In_DBx__5__AG, CYREG_PRT12_AG\r
+.set SCSI_In_DBx__5__BIE, CYREG_PRT12_BIE\r
+.set SCSI_In_DBx__5__BIT_MASK, CYREG_PRT12_BIT_MASK\r
+.set SCSI_In_DBx__5__BYP, CYREG_PRT12_BYP\r
+.set SCSI_In_DBx__5__DM0, CYREG_PRT12_DM0\r
+.set SCSI_In_DBx__5__DM1, CYREG_PRT12_DM1\r
+.set SCSI_In_DBx__5__DM2, CYREG_PRT12_DM2\r
+.set SCSI_In_DBx__5__DR, CYREG_PRT12_DR\r
+.set SCSI_In_DBx__5__INP_DIS, CYREG_PRT12_INP_DIS\r
+.set SCSI_In_DBx__5__INTTYPE, CYREG_PICU12_INTTYPE4\r
+.set SCSI_In_DBx__5__MASK, 0x10\r
+.set SCSI_In_DBx__5__PC, CYREG_PRT12_PC4\r
+.set SCSI_In_DBx__5__PORT, 12\r
+.set SCSI_In_DBx__5__PRT, CYREG_PRT12_PRT\r
+.set SCSI_In_DBx__5__PRTDSI__DBL_SYNC_IN, CYREG_PRT12_DBL_SYNC_IN\r
+.set SCSI_In_DBx__5__PRTDSI__OE_SEL0, CYREG_PRT12_OE_SEL0\r
+.set SCSI_In_DBx__5__PRTDSI__OE_SEL1, CYREG_PRT12_OE_SEL1\r
+.set SCSI_In_DBx__5__PRTDSI__OUT_SEL0, CYREG_PRT12_OUT_SEL0\r
+.set SCSI_In_DBx__5__PRTDSI__OUT_SEL1, CYREG_PRT12_OUT_SEL1\r
+.set SCSI_In_DBx__5__PRTDSI__SYNC_OUT, CYREG_PRT12_SYNC_OUT\r
+.set SCSI_In_DBx__5__PS, CYREG_PRT12_PS\r
+.set SCSI_In_DBx__5__SHIFT, 4\r
+.set SCSI_In_DBx__5__SIO_CFG, CYREG_PRT12_SIO_CFG\r
+.set SCSI_In_DBx__5__SIO_DIFF, CYREG_PRT12_SIO_DIFF\r
+.set SCSI_In_DBx__5__SIO_HYST_EN, CYREG_PRT12_SIO_HYST_EN\r
+.set SCSI_In_DBx__5__SIO_REG_HIFREQ, CYREG_PRT12_SIO_REG_HIFREQ\r
+.set SCSI_In_DBx__5__SLW, CYREG_PRT12_SLW\r
+.set SCSI_In_DBx__6__AG, CYREG_PRT2_AG\r
+.set SCSI_In_DBx__6__AMUX, CYREG_PRT2_AMUX\r
+.set SCSI_In_DBx__6__BIE, CYREG_PRT2_BIE\r
+.set SCSI_In_DBx__6__BIT_MASK, CYREG_PRT2_BIT_MASK\r
+.set SCSI_In_DBx__6__BYP, CYREG_PRT2_BYP\r
+.set SCSI_In_DBx__6__CTL, CYREG_PRT2_CTL\r
+.set SCSI_In_DBx__6__DM0, CYREG_PRT2_DM0\r
+.set SCSI_In_DBx__6__DM1, CYREG_PRT2_DM1\r
+.set SCSI_In_DBx__6__DM2, CYREG_PRT2_DM2\r
+.set SCSI_In_DBx__6__DR, CYREG_PRT2_DR\r
+.set SCSI_In_DBx__6__INP_DIS, CYREG_PRT2_INP_DIS\r
+.set SCSI_In_DBx__6__INTTYPE, CYREG_PICU2_INTTYPE5\r
+.set SCSI_In_DBx__6__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG\r
+.set SCSI_In_DBx__6__LCD_EN, CYREG_PRT2_LCD_EN\r
+.set SCSI_In_DBx__6__MASK, 0x20\r
+.set SCSI_In_DBx__6__PC, CYREG_PRT2_PC5\r
+.set SCSI_In_DBx__6__PORT, 2\r
+.set SCSI_In_DBx__6__PRT, CYREG_PRT2_PRT\r
+.set SCSI_In_DBx__6__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL\r
+.set SCSI_In_DBx__6__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN\r
+.set SCSI_In_DBx__6__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0\r
+.set SCSI_In_DBx__6__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1\r
+.set SCSI_In_DBx__6__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0\r
+.set SCSI_In_DBx__6__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1\r
+.set SCSI_In_DBx__6__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT\r
+.set SCSI_In_DBx__6__PS, CYREG_PRT2_PS\r
+.set SCSI_In_DBx__6__SHIFT, 5\r
+.set SCSI_In_DBx__6__SLW, CYREG_PRT2_SLW\r
+.set SCSI_In_DBx__7__AG, CYREG_PRT2_AG\r
+.set SCSI_In_DBx__7__AMUX, CYREG_PRT2_AMUX\r
+.set SCSI_In_DBx__7__BIE, CYREG_PRT2_BIE\r
+.set SCSI_In_DBx__7__BIT_MASK, CYREG_PRT2_BIT_MASK\r
+.set SCSI_In_DBx__7__BYP, CYREG_PRT2_BYP\r
+.set SCSI_In_DBx__7__CTL, CYREG_PRT2_CTL\r
+.set SCSI_In_DBx__7__DM0, CYREG_PRT2_DM0\r
+.set SCSI_In_DBx__7__DM1, CYREG_PRT2_DM1\r
+.set SCSI_In_DBx__7__DM2, CYREG_PRT2_DM2\r
+.set SCSI_In_DBx__7__DR, CYREG_PRT2_DR\r
+.set SCSI_In_DBx__7__INP_DIS, CYREG_PRT2_INP_DIS\r
+.set SCSI_In_DBx__7__INTTYPE, CYREG_PICU2_INTTYPE4\r
+.set SCSI_In_DBx__7__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG\r
+.set SCSI_In_DBx__7__LCD_EN, CYREG_PRT2_LCD_EN\r
+.set SCSI_In_DBx__7__MASK, 0x10\r
+.set SCSI_In_DBx__7__PC, CYREG_PRT2_PC4\r
+.set SCSI_In_DBx__7__PORT, 2\r
+.set SCSI_In_DBx__7__PRT, CYREG_PRT2_PRT\r
+.set SCSI_In_DBx__7__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL\r
+.set SCSI_In_DBx__7__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN\r
+.set SCSI_In_DBx__7__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0\r
+.set SCSI_In_DBx__7__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1\r
+.set SCSI_In_DBx__7__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0\r
+.set SCSI_In_DBx__7__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1\r
+.set SCSI_In_DBx__7__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT\r
+.set SCSI_In_DBx__7__PS, CYREG_PRT2_PS\r
+.set SCSI_In_DBx__7__SHIFT, 4\r
+.set SCSI_In_DBx__7__SLW, CYREG_PRT2_SLW\r
+.set SCSI_In_DBx__DB0__AG, CYREG_PRT5_AG\r
+.set SCSI_In_DBx__DB0__AMUX, CYREG_PRT5_AMUX\r
+.set SCSI_In_DBx__DB0__BIE, CYREG_PRT5_BIE\r
+.set SCSI_In_DBx__DB0__BIT_MASK, CYREG_PRT5_BIT_MASK\r
+.set SCSI_In_DBx__DB0__BYP, CYREG_PRT5_BYP\r
+.set SCSI_In_DBx__DB0__CTL, CYREG_PRT5_CTL\r
+.set SCSI_In_DBx__DB0__DM0, CYREG_PRT5_DM0\r
+.set SCSI_In_DBx__DB0__DM1, CYREG_PRT5_DM1\r
+.set SCSI_In_DBx__DB0__DM2, CYREG_PRT5_DM2\r
+.set SCSI_In_DBx__DB0__DR, CYREG_PRT5_DR\r
+.set SCSI_In_DBx__DB0__INP_DIS, CYREG_PRT5_INP_DIS\r
+.set SCSI_In_DBx__DB0__INTTYPE, CYREG_PICU5_INTTYPE3\r
+.set SCSI_In_DBx__DB0__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG\r
+.set SCSI_In_DBx__DB0__LCD_EN, CYREG_PRT5_LCD_EN\r
+.set SCSI_In_DBx__DB0__MASK, 0x08\r
+.set SCSI_In_DBx__DB0__PC, CYREG_PRT5_PC3\r
+.set SCSI_In_DBx__DB0__PORT, 5\r
+.set SCSI_In_DBx__DB0__PRT, CYREG_PRT5_PRT\r
+.set SCSI_In_DBx__DB0__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL\r
+.set SCSI_In_DBx__DB0__PRTDSI__DBL_SYNC_IN, CYREG_PRT5_DBL_SYNC_IN\r
+.set SCSI_In_DBx__DB0__PRTDSI__OE_SEL0, CYREG_PRT5_OE_SEL0\r
+.set SCSI_In_DBx__DB0__PRTDSI__OE_SEL1, CYREG_PRT5_OE_SEL1\r
+.set SCSI_In_DBx__DB0__PRTDSI__OUT_SEL0, CYREG_PRT5_OUT_SEL0\r
+.set SCSI_In_DBx__DB0__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1\r
+.set SCSI_In_DBx__DB0__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT\r
+.set SCSI_In_DBx__DB0__PS, CYREG_PRT5_PS\r
+.set SCSI_In_DBx__DB0__SHIFT, 3\r
+.set SCSI_In_DBx__DB0__SLW, CYREG_PRT5_SLW\r
+.set SCSI_In_DBx__DB1__AG, CYREG_PRT5_AG\r
+.set SCSI_In_DBx__DB1__AMUX, CYREG_PRT5_AMUX\r
+.set SCSI_In_DBx__DB1__BIE, CYREG_PRT5_BIE\r
+.set SCSI_In_DBx__DB1__BIT_MASK, CYREG_PRT5_BIT_MASK\r
+.set SCSI_In_DBx__DB1__BYP, CYREG_PRT5_BYP\r
+.set SCSI_In_DBx__DB1__CTL, CYREG_PRT5_CTL\r
+.set SCSI_In_DBx__DB1__DM0, CYREG_PRT5_DM0\r
+.set SCSI_In_DBx__DB1__DM1, CYREG_PRT5_DM1\r
+.set SCSI_In_DBx__DB1__DM2, CYREG_PRT5_DM2\r
+.set SCSI_In_DBx__DB1__DR, CYREG_PRT5_DR\r
+.set SCSI_In_DBx__DB1__INP_DIS, CYREG_PRT5_INP_DIS\r
+.set SCSI_In_DBx__DB1__INTTYPE, CYREG_PICU5_INTTYPE2\r
+.set SCSI_In_DBx__DB1__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG\r
+.set SCSI_In_DBx__DB1__LCD_EN, CYREG_PRT5_LCD_EN\r
+.set SCSI_In_DBx__DB1__MASK, 0x04\r
+.set SCSI_In_DBx__DB1__PC, CYREG_PRT5_PC2\r
+.set SCSI_In_DBx__DB1__PORT, 5\r
+.set SCSI_In_DBx__DB1__PRT, CYREG_PRT5_PRT\r
+.set SCSI_In_DBx__DB1__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL\r
+.set SCSI_In_DBx__DB1__PRTDSI__DBL_SYNC_IN, CYREG_PRT5_DBL_SYNC_IN\r
+.set SCSI_In_DBx__DB1__PRTDSI__OE_SEL0, CYREG_PRT5_OE_SEL0\r
+.set SCSI_In_DBx__DB1__PRTDSI__OE_SEL1, CYREG_PRT5_OE_SEL1\r
+.set SCSI_In_DBx__DB1__PRTDSI__OUT_SEL0, CYREG_PRT5_OUT_SEL0\r
+.set SCSI_In_DBx__DB1__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1\r
+.set SCSI_In_DBx__DB1__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT\r
+.set SCSI_In_DBx__DB1__PS, CYREG_PRT5_PS\r
+.set SCSI_In_DBx__DB1__SHIFT, 2\r
+.set SCSI_In_DBx__DB1__SLW, CYREG_PRT5_SLW\r
+.set SCSI_In_DBx__DB2__AG, CYREG_PRT6_AG\r
+.set SCSI_In_DBx__DB2__AMUX, CYREG_PRT6_AMUX\r
+.set SCSI_In_DBx__DB2__BIE, CYREG_PRT6_BIE\r
+.set SCSI_In_DBx__DB2__BIT_MASK, CYREG_PRT6_BIT_MASK\r
+.set SCSI_In_DBx__DB2__BYP, CYREG_PRT6_BYP\r
+.set SCSI_In_DBx__DB2__CTL, CYREG_PRT6_CTL\r
+.set SCSI_In_DBx__DB2__DM0, CYREG_PRT6_DM0\r
+.set SCSI_In_DBx__DB2__DM1, CYREG_PRT6_DM1\r
+.set SCSI_In_DBx__DB2__DM2, CYREG_PRT6_DM2\r
+.set SCSI_In_DBx__DB2__DR, CYREG_PRT6_DR\r
+.set SCSI_In_DBx__DB2__INP_DIS, CYREG_PRT6_INP_DIS\r
+.set SCSI_In_DBx__DB2__INTTYPE, CYREG_PICU6_INTTYPE7\r
+.set SCSI_In_DBx__DB2__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG\r
+.set SCSI_In_DBx__DB2__LCD_EN, CYREG_PRT6_LCD_EN\r
+.set SCSI_In_DBx__DB2__MASK, 0x80\r
+.set SCSI_In_DBx__DB2__PC, CYREG_PRT6_PC7\r
+.set SCSI_In_DBx__DB2__PORT, 6\r
+.set SCSI_In_DBx__DB2__PRT, CYREG_PRT6_PRT\r
+.set SCSI_In_DBx__DB2__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL\r
+.set SCSI_In_DBx__DB2__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN\r
+.set SCSI_In_DBx__DB2__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0\r
+.set SCSI_In_DBx__DB2__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1\r
+.set SCSI_In_DBx__DB2__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0\r
+.set SCSI_In_DBx__DB2__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1\r
+.set SCSI_In_DBx__DB2__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT\r
+.set SCSI_In_DBx__DB2__PS, CYREG_PRT6_PS\r
+.set SCSI_In_DBx__DB2__SHIFT, 7\r
+.set SCSI_In_DBx__DB2__SLW, CYREG_PRT6_SLW\r
+.set SCSI_In_DBx__DB3__AG, CYREG_PRT6_AG\r
+.set SCSI_In_DBx__DB3__AMUX, CYREG_PRT6_AMUX\r
+.set SCSI_In_DBx__DB3__BIE, CYREG_PRT6_BIE\r
+.set SCSI_In_DBx__DB3__BIT_MASK, CYREG_PRT6_BIT_MASK\r
+.set SCSI_In_DBx__DB3__BYP, CYREG_PRT6_BYP\r
+.set SCSI_In_DBx__DB3__CTL, CYREG_PRT6_CTL\r
+.set SCSI_In_DBx__DB3__DM0, CYREG_PRT6_DM0\r
+.set SCSI_In_DBx__DB3__DM1, CYREG_PRT6_DM1\r
+.set SCSI_In_DBx__DB3__DM2, CYREG_PRT6_DM2\r
+.set SCSI_In_DBx__DB3__DR, CYREG_PRT6_DR\r
+.set SCSI_In_DBx__DB3__INP_DIS, CYREG_PRT6_INP_DIS\r
+.set SCSI_In_DBx__DB3__INTTYPE, CYREG_PICU6_INTTYPE6\r
+.set SCSI_In_DBx__DB3__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG\r
+.set SCSI_In_DBx__DB3__LCD_EN, CYREG_PRT6_LCD_EN\r
+.set SCSI_In_DBx__DB3__MASK, 0x40\r
+.set SCSI_In_DBx__DB3__PC, CYREG_PRT6_PC6\r
+.set SCSI_In_DBx__DB3__PORT, 6\r
+.set SCSI_In_DBx__DB3__PRT, CYREG_PRT6_PRT\r
+.set SCSI_In_DBx__DB3__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL\r
+.set SCSI_In_DBx__DB3__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN\r
+.set SCSI_In_DBx__DB3__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0\r
+.set SCSI_In_DBx__DB3__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1\r
+.set SCSI_In_DBx__DB3__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0\r
+.set SCSI_In_DBx__DB3__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1\r
+.set SCSI_In_DBx__DB3__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT\r
+.set SCSI_In_DBx__DB3__PS, CYREG_PRT6_PS\r
+.set SCSI_In_DBx__DB3__SHIFT, 6\r
+.set SCSI_In_DBx__DB3__SLW, CYREG_PRT6_SLW\r
+.set SCSI_In_DBx__DB4__AG, CYREG_PRT12_AG\r
+.set SCSI_In_DBx__DB4__BIE, CYREG_PRT12_BIE\r
+.set SCSI_In_DBx__DB4__BIT_MASK, CYREG_PRT12_BIT_MASK\r
+.set SCSI_In_DBx__DB4__BYP, CYREG_PRT12_BYP\r
+.set SCSI_In_DBx__DB4__DM0, CYREG_PRT12_DM0\r
+.set SCSI_In_DBx__DB4__DM1, CYREG_PRT12_DM1\r
+.set SCSI_In_DBx__DB4__DM2, CYREG_PRT12_DM2\r
+.set SCSI_In_DBx__DB4__DR, CYREG_PRT12_DR\r
+.set SCSI_In_DBx__DB4__INP_DIS, CYREG_PRT12_INP_DIS\r
+.set SCSI_In_DBx__DB4__INTTYPE, CYREG_PICU12_INTTYPE5\r
+.set SCSI_In_DBx__DB4__MASK, 0x20\r
+.set SCSI_In_DBx__DB4__PC, CYREG_PRT12_PC5\r
+.set SCSI_In_DBx__DB4__PORT, 12\r
+.set SCSI_In_DBx__DB4__PRT, CYREG_PRT12_PRT\r
+.set SCSI_In_DBx__DB4__PRTDSI__DBL_SYNC_IN, CYREG_PRT12_DBL_SYNC_IN\r
+.set SCSI_In_DBx__DB4__PRTDSI__OE_SEL0, CYREG_PRT12_OE_SEL0\r
+.set SCSI_In_DBx__DB4__PRTDSI__OE_SEL1, CYREG_PRT12_OE_SEL1\r
+.set SCSI_In_DBx__DB4__PRTDSI__OUT_SEL0, CYREG_PRT12_OUT_SEL0\r
+.set SCSI_In_DBx__DB4__PRTDSI__OUT_SEL1, CYREG_PRT12_OUT_SEL1\r
+.set SCSI_In_DBx__DB4__PRTDSI__SYNC_OUT, CYREG_PRT12_SYNC_OUT\r
+.set SCSI_In_DBx__DB4__PS, CYREG_PRT12_PS\r
+.set SCSI_In_DBx__DB4__SHIFT, 5\r
+.set SCSI_In_DBx__DB4__SIO_CFG, CYREG_PRT12_SIO_CFG\r
+.set SCSI_In_DBx__DB4__SIO_DIFF, CYREG_PRT12_SIO_DIFF\r
+.set SCSI_In_DBx__DB4__SIO_HYST_EN, CYREG_PRT12_SIO_HYST_EN\r
+.set SCSI_In_DBx__DB4__SIO_REG_HIFREQ, CYREG_PRT12_SIO_REG_HIFREQ\r
+.set SCSI_In_DBx__DB4__SLW, CYREG_PRT12_SLW\r
+.set SCSI_In_DBx__DB5__AG, CYREG_PRT12_AG\r
+.set SCSI_In_DBx__DB5__BIE, CYREG_PRT12_BIE\r
+.set SCSI_In_DBx__DB5__BIT_MASK, CYREG_PRT12_BIT_MASK\r
+.set SCSI_In_DBx__DB5__BYP, CYREG_PRT12_BYP\r
+.set SCSI_In_DBx__DB5__DM0, CYREG_PRT12_DM0\r
+.set SCSI_In_DBx__DB5__DM1, CYREG_PRT12_DM1\r
+.set SCSI_In_DBx__DB5__DM2, CYREG_PRT12_DM2\r
+.set SCSI_In_DBx__DB5__DR, CYREG_PRT12_DR\r
+.set SCSI_In_DBx__DB5__INP_DIS, CYREG_PRT12_INP_DIS\r
+.set SCSI_In_DBx__DB5__INTTYPE, CYREG_PICU12_INTTYPE4\r
+.set SCSI_In_DBx__DB5__MASK, 0x10\r
+.set SCSI_In_DBx__DB5__PC, CYREG_PRT12_PC4\r
+.set SCSI_In_DBx__DB5__PORT, 12\r
+.set SCSI_In_DBx__DB5__PRT, CYREG_PRT12_PRT\r
+.set SCSI_In_DBx__DB5__PRTDSI__DBL_SYNC_IN, CYREG_PRT12_DBL_SYNC_IN\r
+.set SCSI_In_DBx__DB5__PRTDSI__OE_SEL0, CYREG_PRT12_OE_SEL0\r
+.set SCSI_In_DBx__DB5__PRTDSI__OE_SEL1, CYREG_PRT12_OE_SEL1\r
+.set SCSI_In_DBx__DB5__PRTDSI__OUT_SEL0, CYREG_PRT12_OUT_SEL0\r
+.set SCSI_In_DBx__DB5__PRTDSI__OUT_SEL1, CYREG_PRT12_OUT_SEL1\r
+.set SCSI_In_DBx__DB5__PRTDSI__SYNC_OUT, CYREG_PRT12_SYNC_OUT\r
+.set SCSI_In_DBx__DB5__PS, CYREG_PRT12_PS\r
+.set SCSI_In_DBx__DB5__SHIFT, 4\r
+.set SCSI_In_DBx__DB5__SIO_CFG, CYREG_PRT12_SIO_CFG\r
+.set SCSI_In_DBx__DB5__SIO_DIFF, CYREG_PRT12_SIO_DIFF\r
+.set SCSI_In_DBx__DB5__SIO_HYST_EN, CYREG_PRT12_SIO_HYST_EN\r
+.set SCSI_In_DBx__DB5__SIO_REG_HIFREQ, CYREG_PRT12_SIO_REG_HIFREQ\r
+.set SCSI_In_DBx__DB5__SLW, CYREG_PRT12_SLW\r
+.set SCSI_In_DBx__DB6__AG, CYREG_PRT2_AG\r
+.set SCSI_In_DBx__DB6__AMUX, CYREG_PRT2_AMUX\r
+.set SCSI_In_DBx__DB6__BIE, CYREG_PRT2_BIE\r
+.set SCSI_In_DBx__DB6__BIT_MASK, CYREG_PRT2_BIT_MASK\r
+.set SCSI_In_DBx__DB6__BYP, CYREG_PRT2_BYP\r
+.set SCSI_In_DBx__DB6__CTL, CYREG_PRT2_CTL\r
+.set SCSI_In_DBx__DB6__DM0, CYREG_PRT2_DM0\r
+.set SCSI_In_DBx__DB6__DM1, CYREG_PRT2_DM1\r
+.set SCSI_In_DBx__DB6__DM2, CYREG_PRT2_DM2\r
+.set SCSI_In_DBx__DB6__DR, CYREG_PRT2_DR\r
+.set SCSI_In_DBx__DB6__INP_DIS, CYREG_PRT2_INP_DIS\r
+.set SCSI_In_DBx__DB6__INTTYPE, CYREG_PICU2_INTTYPE5\r
+.set SCSI_In_DBx__DB6__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG\r
+.set SCSI_In_DBx__DB6__LCD_EN, CYREG_PRT2_LCD_EN\r
+.set SCSI_In_DBx__DB6__MASK, 0x20\r
+.set SCSI_In_DBx__DB6__PC, CYREG_PRT2_PC5\r
+.set SCSI_In_DBx__DB6__PORT, 2\r
+.set SCSI_In_DBx__DB6__PRT, CYREG_PRT2_PRT\r
+.set SCSI_In_DBx__DB6__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL\r
+.set SCSI_In_DBx__DB6__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN\r
+.set SCSI_In_DBx__DB6__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0\r
+.set SCSI_In_DBx__DB6__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1\r
+.set SCSI_In_DBx__DB6__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0\r
+.set SCSI_In_DBx__DB6__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1\r
+.set SCSI_In_DBx__DB6__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT\r
+.set SCSI_In_DBx__DB6__PS, CYREG_PRT2_PS\r
+.set SCSI_In_DBx__DB6__SHIFT, 5\r
+.set SCSI_In_DBx__DB6__SLW, CYREG_PRT2_SLW\r
+.set SCSI_In_DBx__DB7__AG, CYREG_PRT2_AG\r
+.set SCSI_In_DBx__DB7__AMUX, CYREG_PRT2_AMUX\r
+.set SCSI_In_DBx__DB7__BIE, CYREG_PRT2_BIE\r
+.set SCSI_In_DBx__DB7__BIT_MASK, CYREG_PRT2_BIT_MASK\r
+.set SCSI_In_DBx__DB7__BYP, CYREG_PRT2_BYP\r
+.set SCSI_In_DBx__DB7__CTL, CYREG_PRT2_CTL\r
+.set SCSI_In_DBx__DB7__DM0, CYREG_PRT2_DM0\r
+.set SCSI_In_DBx__DB7__DM1, CYREG_PRT2_DM1\r
+.set SCSI_In_DBx__DB7__DM2, CYREG_PRT2_DM2\r
+.set SCSI_In_DBx__DB7__DR, CYREG_PRT2_DR\r
+.set SCSI_In_DBx__DB7__INP_DIS, CYREG_PRT2_INP_DIS\r
+.set SCSI_In_DBx__DB7__INTTYPE, CYREG_PICU2_INTTYPE4\r
+.set SCSI_In_DBx__DB7__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG\r
+.set SCSI_In_DBx__DB7__LCD_EN, CYREG_PRT2_LCD_EN\r
+.set SCSI_In_DBx__DB7__MASK, 0x10\r
+.set SCSI_In_DBx__DB7__PC, CYREG_PRT2_PC4\r
+.set SCSI_In_DBx__DB7__PORT, 2\r
+.set SCSI_In_DBx__DB7__PRT, CYREG_PRT2_PRT\r
+.set SCSI_In_DBx__DB7__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL\r
+.set SCSI_In_DBx__DB7__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN\r
+.set SCSI_In_DBx__DB7__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0\r
+.set SCSI_In_DBx__DB7__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1\r
+.set SCSI_In_DBx__DB7__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0\r
+.set SCSI_In_DBx__DB7__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1\r
+.set SCSI_In_DBx__DB7__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT\r
+.set SCSI_In_DBx__DB7__PS, CYREG_PRT2_PS\r
+.set SCSI_In_DBx__DB7__SHIFT, 4\r
+.set SCSI_In_DBx__DB7__SLW, CYREG_PRT2_SLW\r
 \r
 /* SCSI_Noise */\r
 .set SCSI_Noise__0__AG, CYREG_PRT2_AG\r
@@ -2735,6 +1200,1698 @@
 .set SCSI_Noise__SEL__SHIFT, 3\r
 .set SCSI_Noise__SEL__SLW, CYREG_PRT4_SLW\r
 \r
+/* SCSI_Out */\r
+.set SCSI_Out__0__AG, CYREG_PRT15_AG\r
+.set SCSI_Out__0__AMUX, CYREG_PRT15_AMUX\r
+.set SCSI_Out__0__BIE, CYREG_PRT15_BIE\r
+.set SCSI_Out__0__BIT_MASK, CYREG_PRT15_BIT_MASK\r
+.set SCSI_Out__0__BYP, CYREG_PRT15_BYP\r
+.set SCSI_Out__0__CTL, CYREG_PRT15_CTL\r
+.set SCSI_Out__0__DM0, CYREG_PRT15_DM0\r
+.set SCSI_Out__0__DM1, CYREG_PRT15_DM1\r
+.set SCSI_Out__0__DM2, CYREG_PRT15_DM2\r
+.set SCSI_Out__0__DR, CYREG_PRT15_DR\r
+.set SCSI_Out__0__INP_DIS, CYREG_PRT15_INP_DIS\r
+.set SCSI_Out__0__INTTYPE, CYREG_PICU15_INTTYPE5\r
+.set SCSI_Out__0__LCD_COM_SEG, CYREG_PRT15_LCD_COM_SEG\r
+.set SCSI_Out__0__LCD_EN, CYREG_PRT15_LCD_EN\r
+.set SCSI_Out__0__MASK, 0x20\r
+.set SCSI_Out__0__PC, CYREG_IO_PC_PRT15_PC5\r
+.set SCSI_Out__0__PORT, 15\r
+.set SCSI_Out__0__PRT, CYREG_PRT15_PRT\r
+.set SCSI_Out__0__PRTDSI__CAPS_SEL, CYREG_PRT15_CAPS_SEL\r
+.set SCSI_Out__0__PRTDSI__DBL_SYNC_IN, CYREG_PRT15_DBL_SYNC_IN\r
+.set SCSI_Out__0__PRTDSI__OE_SEL0, CYREG_PRT15_OE_SEL0\r
+.set SCSI_Out__0__PRTDSI__OE_SEL1, CYREG_PRT15_OE_SEL1\r
+.set SCSI_Out__0__PRTDSI__OUT_SEL0, CYREG_PRT15_OUT_SEL0\r
+.set SCSI_Out__0__PRTDSI__OUT_SEL1, CYREG_PRT15_OUT_SEL1\r
+.set SCSI_Out__0__PRTDSI__SYNC_OUT, CYREG_PRT15_SYNC_OUT\r
+.set SCSI_Out__0__PS, CYREG_PRT15_PS\r
+.set SCSI_Out__0__SHIFT, 5\r
+.set SCSI_Out__0__SLW, CYREG_PRT15_SLW\r
+.set SCSI_Out__1__AG, CYREG_PRT15_AG\r
+.set SCSI_Out__1__AMUX, CYREG_PRT15_AMUX\r
+.set SCSI_Out__1__BIE, CYREG_PRT15_BIE\r
+.set SCSI_Out__1__BIT_MASK, CYREG_PRT15_BIT_MASK\r
+.set SCSI_Out__1__BYP, CYREG_PRT15_BYP\r
+.set SCSI_Out__1__CTL, CYREG_PRT15_CTL\r
+.set SCSI_Out__1__DM0, CYREG_PRT15_DM0\r
+.set SCSI_Out__1__DM1, CYREG_PRT15_DM1\r
+.set SCSI_Out__1__DM2, CYREG_PRT15_DM2\r
+.set SCSI_Out__1__DR, CYREG_PRT15_DR\r
+.set SCSI_Out__1__INP_DIS, CYREG_PRT15_INP_DIS\r
+.set SCSI_Out__1__INTTYPE, CYREG_PICU15_INTTYPE4\r
+.set SCSI_Out__1__LCD_COM_SEG, CYREG_PRT15_LCD_COM_SEG\r
+.set SCSI_Out__1__LCD_EN, CYREG_PRT15_LCD_EN\r
+.set SCSI_Out__1__MASK, 0x10\r
+.set SCSI_Out__1__PC, CYREG_IO_PC_PRT15_PC4\r
+.set SCSI_Out__1__PORT, 15\r
+.set SCSI_Out__1__PRT, CYREG_PRT15_PRT\r
+.set SCSI_Out__1__PRTDSI__CAPS_SEL, CYREG_PRT15_CAPS_SEL\r
+.set SCSI_Out__1__PRTDSI__DBL_SYNC_IN, CYREG_PRT15_DBL_SYNC_IN\r
+.set SCSI_Out__1__PRTDSI__OE_SEL0, CYREG_PRT15_OE_SEL0\r
+.set SCSI_Out__1__PRTDSI__OE_SEL1, CYREG_PRT15_OE_SEL1\r
+.set SCSI_Out__1__PRTDSI__OUT_SEL0, CYREG_PRT15_OUT_SEL0\r
+.set SCSI_Out__1__PRTDSI__OUT_SEL1, CYREG_PRT15_OUT_SEL1\r
+.set SCSI_Out__1__PRTDSI__SYNC_OUT, CYREG_PRT15_SYNC_OUT\r
+.set SCSI_Out__1__PS, CYREG_PRT15_PS\r
+.set SCSI_Out__1__SHIFT, 4\r
+.set SCSI_Out__1__SLW, CYREG_PRT15_SLW\r
+.set SCSI_Out__2__AG, CYREG_PRT6_AG\r
+.set SCSI_Out__2__AMUX, CYREG_PRT6_AMUX\r
+.set SCSI_Out__2__BIE, CYREG_PRT6_BIE\r
+.set SCSI_Out__2__BIT_MASK, CYREG_PRT6_BIT_MASK\r
+.set SCSI_Out__2__BYP, CYREG_PRT6_BYP\r
+.set SCSI_Out__2__CTL, CYREG_PRT6_CTL\r
+.set SCSI_Out__2__DM0, CYREG_PRT6_DM0\r
+.set SCSI_Out__2__DM1, CYREG_PRT6_DM1\r
+.set SCSI_Out__2__DM2, CYREG_PRT6_DM2\r
+.set SCSI_Out__2__DR, CYREG_PRT6_DR\r
+.set SCSI_Out__2__INP_DIS, CYREG_PRT6_INP_DIS\r
+.set SCSI_Out__2__INTTYPE, CYREG_PICU6_INTTYPE1\r
+.set SCSI_Out__2__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG\r
+.set SCSI_Out__2__LCD_EN, CYREG_PRT6_LCD_EN\r
+.set SCSI_Out__2__MASK, 0x02\r
+.set SCSI_Out__2__PC, CYREG_PRT6_PC1\r
+.set SCSI_Out__2__PORT, 6\r
+.set SCSI_Out__2__PRT, CYREG_PRT6_PRT\r
+.set SCSI_Out__2__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL\r
+.set SCSI_Out__2__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN\r
+.set SCSI_Out__2__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0\r
+.set SCSI_Out__2__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1\r
+.set SCSI_Out__2__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0\r
+.set SCSI_Out__2__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1\r
+.set SCSI_Out__2__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT\r
+.set SCSI_Out__2__PS, CYREG_PRT6_PS\r
+.set SCSI_Out__2__SHIFT, 1\r
+.set SCSI_Out__2__SLW, CYREG_PRT6_SLW\r
+.set SCSI_Out__3__AG, CYREG_PRT6_AG\r
+.set SCSI_Out__3__AMUX, CYREG_PRT6_AMUX\r
+.set SCSI_Out__3__BIE, CYREG_PRT6_BIE\r
+.set SCSI_Out__3__BIT_MASK, CYREG_PRT6_BIT_MASK\r
+.set SCSI_Out__3__BYP, CYREG_PRT6_BYP\r
+.set SCSI_Out__3__CTL, CYREG_PRT6_CTL\r
+.set SCSI_Out__3__DM0, CYREG_PRT6_DM0\r
+.set SCSI_Out__3__DM1, CYREG_PRT6_DM1\r
+.set SCSI_Out__3__DM2, CYREG_PRT6_DM2\r
+.set SCSI_Out__3__DR, CYREG_PRT6_DR\r
+.set SCSI_Out__3__INP_DIS, CYREG_PRT6_INP_DIS\r
+.set SCSI_Out__3__INTTYPE, CYREG_PICU6_INTTYPE0\r
+.set SCSI_Out__3__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG\r
+.set SCSI_Out__3__LCD_EN, CYREG_PRT6_LCD_EN\r
+.set SCSI_Out__3__MASK, 0x01\r
+.set SCSI_Out__3__PC, CYREG_PRT6_PC0\r
+.set SCSI_Out__3__PORT, 6\r
+.set SCSI_Out__3__PRT, CYREG_PRT6_PRT\r
+.set SCSI_Out__3__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL\r
+.set SCSI_Out__3__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN\r
+.set SCSI_Out__3__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0\r
+.set SCSI_Out__3__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1\r
+.set SCSI_Out__3__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0\r
+.set SCSI_Out__3__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1\r
+.set SCSI_Out__3__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT\r
+.set SCSI_Out__3__PS, CYREG_PRT6_PS\r
+.set SCSI_Out__3__SHIFT, 0\r
+.set SCSI_Out__3__SLW, CYREG_PRT6_SLW\r
+.set SCSI_Out__4__AG, CYREG_PRT4_AG\r
+.set SCSI_Out__4__AMUX, CYREG_PRT4_AMUX\r
+.set SCSI_Out__4__BIE, CYREG_PRT4_BIE\r
+.set SCSI_Out__4__BIT_MASK, CYREG_PRT4_BIT_MASK\r
+.set SCSI_Out__4__BYP, CYREG_PRT4_BYP\r
+.set SCSI_Out__4__CTL, CYREG_PRT4_CTL\r
+.set SCSI_Out__4__DM0, CYREG_PRT4_DM0\r
+.set SCSI_Out__4__DM1, CYREG_PRT4_DM1\r
+.set SCSI_Out__4__DM2, CYREG_PRT4_DM2\r
+.set SCSI_Out__4__DR, CYREG_PRT4_DR\r
+.set SCSI_Out__4__INP_DIS, CYREG_PRT4_INP_DIS\r
+.set SCSI_Out__4__INTTYPE, CYREG_PICU4_INTTYPE5\r
+.set SCSI_Out__4__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG\r
+.set SCSI_Out__4__LCD_EN, CYREG_PRT4_LCD_EN\r
+.set SCSI_Out__4__MASK, 0x20\r
+.set SCSI_Out__4__PC, CYREG_PRT4_PC5\r
+.set SCSI_Out__4__PORT, 4\r
+.set SCSI_Out__4__PRT, CYREG_PRT4_PRT\r
+.set SCSI_Out__4__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL\r
+.set SCSI_Out__4__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN\r
+.set SCSI_Out__4__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0\r
+.set SCSI_Out__4__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1\r
+.set SCSI_Out__4__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0\r
+.set SCSI_Out__4__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1\r
+.set SCSI_Out__4__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT\r
+.set SCSI_Out__4__PS, CYREG_PRT4_PS\r
+.set SCSI_Out__4__SHIFT, 5\r
+.set SCSI_Out__4__SLW, CYREG_PRT4_SLW\r
+.set SCSI_Out__5__AG, CYREG_PRT4_AG\r
+.set SCSI_Out__5__AMUX, CYREG_PRT4_AMUX\r
+.set SCSI_Out__5__BIE, CYREG_PRT4_BIE\r
+.set SCSI_Out__5__BIT_MASK, CYREG_PRT4_BIT_MASK\r
+.set SCSI_Out__5__BYP, CYREG_PRT4_BYP\r
+.set SCSI_Out__5__CTL, CYREG_PRT4_CTL\r
+.set SCSI_Out__5__DM0, CYREG_PRT4_DM0\r
+.set SCSI_Out__5__DM1, CYREG_PRT4_DM1\r
+.set SCSI_Out__5__DM2, CYREG_PRT4_DM2\r
+.set SCSI_Out__5__DR, CYREG_PRT4_DR\r
+.set SCSI_Out__5__INP_DIS, CYREG_PRT4_INP_DIS\r
+.set SCSI_Out__5__INTTYPE, CYREG_PICU4_INTTYPE4\r
+.set SCSI_Out__5__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG\r
+.set SCSI_Out__5__LCD_EN, CYREG_PRT4_LCD_EN\r
+.set SCSI_Out__5__MASK, 0x10\r
+.set SCSI_Out__5__PC, CYREG_PRT4_PC4\r
+.set SCSI_Out__5__PORT, 4\r
+.set SCSI_Out__5__PRT, CYREG_PRT4_PRT\r
+.set SCSI_Out__5__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL\r
+.set SCSI_Out__5__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN\r
+.set SCSI_Out__5__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0\r
+.set SCSI_Out__5__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1\r
+.set SCSI_Out__5__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0\r
+.set SCSI_Out__5__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1\r
+.set SCSI_Out__5__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT\r
+.set SCSI_Out__5__PS, CYREG_PRT4_PS\r
+.set SCSI_Out__5__SHIFT, 4\r
+.set SCSI_Out__5__SLW, CYREG_PRT4_SLW\r
+.set SCSI_Out__6__AG, CYREG_PRT0_AG\r
+.set SCSI_Out__6__AMUX, CYREG_PRT0_AMUX\r
+.set SCSI_Out__6__BIE, CYREG_PRT0_BIE\r
+.set SCSI_Out__6__BIT_MASK, CYREG_PRT0_BIT_MASK\r
+.set SCSI_Out__6__BYP, CYREG_PRT0_BYP\r
+.set SCSI_Out__6__CTL, CYREG_PRT0_CTL\r
+.set SCSI_Out__6__DM0, CYREG_PRT0_DM0\r
+.set SCSI_Out__6__DM1, CYREG_PRT0_DM1\r
+.set SCSI_Out__6__DM2, CYREG_PRT0_DM2\r
+.set SCSI_Out__6__DR, CYREG_PRT0_DR\r
+.set SCSI_Out__6__INP_DIS, CYREG_PRT0_INP_DIS\r
+.set SCSI_Out__6__INTTYPE, CYREG_PICU0_INTTYPE7\r
+.set SCSI_Out__6__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG\r
+.set SCSI_Out__6__LCD_EN, CYREG_PRT0_LCD_EN\r
+.set SCSI_Out__6__MASK, 0x80\r
+.set SCSI_Out__6__PC, CYREG_PRT0_PC7\r
+.set SCSI_Out__6__PORT, 0\r
+.set SCSI_Out__6__PRT, CYREG_PRT0_PRT\r
+.set SCSI_Out__6__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL\r
+.set SCSI_Out__6__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN\r
+.set SCSI_Out__6__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0\r
+.set SCSI_Out__6__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1\r
+.set SCSI_Out__6__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0\r
+.set SCSI_Out__6__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1\r
+.set SCSI_Out__6__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT\r
+.set SCSI_Out__6__PS, CYREG_PRT0_PS\r
+.set SCSI_Out__6__SHIFT, 7\r
+.set SCSI_Out__6__SLW, CYREG_PRT0_SLW\r
+.set SCSI_Out__7__AG, CYREG_PRT0_AG\r
+.set SCSI_Out__7__AMUX, CYREG_PRT0_AMUX\r
+.set SCSI_Out__7__BIE, CYREG_PRT0_BIE\r
+.set SCSI_Out__7__BIT_MASK, CYREG_PRT0_BIT_MASK\r
+.set SCSI_Out__7__BYP, CYREG_PRT0_BYP\r
+.set SCSI_Out__7__CTL, CYREG_PRT0_CTL\r
+.set SCSI_Out__7__DM0, CYREG_PRT0_DM0\r
+.set SCSI_Out__7__DM1, CYREG_PRT0_DM1\r
+.set SCSI_Out__7__DM2, CYREG_PRT0_DM2\r
+.set SCSI_Out__7__DR, CYREG_PRT0_DR\r
+.set SCSI_Out__7__INP_DIS, CYREG_PRT0_INP_DIS\r
+.set SCSI_Out__7__INTTYPE, CYREG_PICU0_INTTYPE6\r
+.set SCSI_Out__7__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG\r
+.set SCSI_Out__7__LCD_EN, CYREG_PRT0_LCD_EN\r
+.set SCSI_Out__7__MASK, 0x40\r
+.set SCSI_Out__7__PC, CYREG_PRT0_PC6\r
+.set SCSI_Out__7__PORT, 0\r
+.set SCSI_Out__7__PRT, CYREG_PRT0_PRT\r
+.set SCSI_Out__7__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL\r
+.set SCSI_Out__7__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN\r
+.set SCSI_Out__7__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0\r
+.set SCSI_Out__7__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1\r
+.set SCSI_Out__7__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0\r
+.set SCSI_Out__7__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1\r
+.set SCSI_Out__7__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT\r
+.set SCSI_Out__7__PS, CYREG_PRT0_PS\r
+.set SCSI_Out__7__SHIFT, 6\r
+.set SCSI_Out__7__SLW, CYREG_PRT0_SLW\r
+.set SCSI_Out__8__AG, CYREG_PRT0_AG\r
+.set SCSI_Out__8__AMUX, CYREG_PRT0_AMUX\r
+.set SCSI_Out__8__BIE, CYREG_PRT0_BIE\r
+.set SCSI_Out__8__BIT_MASK, CYREG_PRT0_BIT_MASK\r
+.set SCSI_Out__8__BYP, CYREG_PRT0_BYP\r
+.set SCSI_Out__8__CTL, CYREG_PRT0_CTL\r
+.set SCSI_Out__8__DM0, CYREG_PRT0_DM0\r
+.set SCSI_Out__8__DM1, CYREG_PRT0_DM1\r
+.set SCSI_Out__8__DM2, CYREG_PRT0_DM2\r
+.set SCSI_Out__8__DR, CYREG_PRT0_DR\r
+.set SCSI_Out__8__INP_DIS, CYREG_PRT0_INP_DIS\r
+.set SCSI_Out__8__INTTYPE, CYREG_PICU0_INTTYPE3\r
+.set SCSI_Out__8__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG\r
+.set SCSI_Out__8__LCD_EN, CYREG_PRT0_LCD_EN\r
+.set SCSI_Out__8__MASK, 0x08\r
+.set SCSI_Out__8__PC, CYREG_PRT0_PC3\r
+.set SCSI_Out__8__PORT, 0\r
+.set SCSI_Out__8__PRT, CYREG_PRT0_PRT\r
+.set SCSI_Out__8__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL\r
+.set SCSI_Out__8__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN\r
+.set SCSI_Out__8__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0\r
+.set SCSI_Out__8__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1\r
+.set SCSI_Out__8__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0\r
+.set SCSI_Out__8__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1\r
+.set SCSI_Out__8__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT\r
+.set SCSI_Out__8__PS, CYREG_PRT0_PS\r
+.set SCSI_Out__8__SHIFT, 3\r
+.set SCSI_Out__8__SLW, CYREG_PRT0_SLW\r
+.set SCSI_Out__9__AG, CYREG_PRT0_AG\r
+.set SCSI_Out__9__AMUX, CYREG_PRT0_AMUX\r
+.set SCSI_Out__9__BIE, CYREG_PRT0_BIE\r
+.set SCSI_Out__9__BIT_MASK, CYREG_PRT0_BIT_MASK\r
+.set SCSI_Out__9__BYP, CYREG_PRT0_BYP\r
+.set SCSI_Out__9__CTL, CYREG_PRT0_CTL\r
+.set SCSI_Out__9__DM0, CYREG_PRT0_DM0\r
+.set SCSI_Out__9__DM1, CYREG_PRT0_DM1\r
+.set SCSI_Out__9__DM2, CYREG_PRT0_DM2\r
+.set SCSI_Out__9__DR, CYREG_PRT0_DR\r
+.set SCSI_Out__9__INP_DIS, CYREG_PRT0_INP_DIS\r
+.set SCSI_Out__9__INTTYPE, CYREG_PICU0_INTTYPE2\r
+.set SCSI_Out__9__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG\r
+.set SCSI_Out__9__LCD_EN, CYREG_PRT0_LCD_EN\r
+.set SCSI_Out__9__MASK, 0x04\r
+.set SCSI_Out__9__PC, CYREG_PRT0_PC2\r
+.set SCSI_Out__9__PORT, 0\r
+.set SCSI_Out__9__PRT, CYREG_PRT0_PRT\r
+.set SCSI_Out__9__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL\r
+.set SCSI_Out__9__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN\r
+.set SCSI_Out__9__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0\r
+.set SCSI_Out__9__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1\r
+.set SCSI_Out__9__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0\r
+.set SCSI_Out__9__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1\r
+.set SCSI_Out__9__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT\r
+.set SCSI_Out__9__PS, CYREG_PRT0_PS\r
+.set SCSI_Out__9__SHIFT, 2\r
+.set SCSI_Out__9__SLW, CYREG_PRT0_SLW\r
+.set SCSI_Out__ACK__AG, CYREG_PRT6_AG\r
+.set SCSI_Out__ACK__AMUX, CYREG_PRT6_AMUX\r
+.set SCSI_Out__ACK__BIE, CYREG_PRT6_BIE\r
+.set SCSI_Out__ACK__BIT_MASK, CYREG_PRT6_BIT_MASK\r
+.set SCSI_Out__ACK__BYP, CYREG_PRT6_BYP\r
+.set SCSI_Out__ACK__CTL, CYREG_PRT6_CTL\r
+.set SCSI_Out__ACK__DM0, CYREG_PRT6_DM0\r
+.set SCSI_Out__ACK__DM1, CYREG_PRT6_DM1\r
+.set SCSI_Out__ACK__DM2, CYREG_PRT6_DM2\r
+.set SCSI_Out__ACK__DR, CYREG_PRT6_DR\r
+.set SCSI_Out__ACK__INP_DIS, CYREG_PRT6_INP_DIS\r
+.set SCSI_Out__ACK__INTTYPE, CYREG_PICU6_INTTYPE0\r
+.set SCSI_Out__ACK__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG\r
+.set SCSI_Out__ACK__LCD_EN, CYREG_PRT6_LCD_EN\r
+.set SCSI_Out__ACK__MASK, 0x01\r
+.set SCSI_Out__ACK__PC, CYREG_PRT6_PC0\r
+.set SCSI_Out__ACK__PORT, 6\r
+.set SCSI_Out__ACK__PRT, CYREG_PRT6_PRT\r
+.set SCSI_Out__ACK__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL\r
+.set SCSI_Out__ACK__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN\r
+.set SCSI_Out__ACK__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0\r
+.set SCSI_Out__ACK__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1\r
+.set SCSI_Out__ACK__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0\r
+.set SCSI_Out__ACK__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1\r
+.set SCSI_Out__ACK__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT\r
+.set SCSI_Out__ACK__PS, CYREG_PRT6_PS\r
+.set SCSI_Out__ACK__SHIFT, 0\r
+.set SCSI_Out__ACK__SLW, CYREG_PRT6_SLW\r
+.set SCSI_Out__ATN__AG, CYREG_PRT15_AG\r
+.set SCSI_Out__ATN__AMUX, CYREG_PRT15_AMUX\r
+.set SCSI_Out__ATN__BIE, CYREG_PRT15_BIE\r
+.set SCSI_Out__ATN__BIT_MASK, CYREG_PRT15_BIT_MASK\r
+.set SCSI_Out__ATN__BYP, CYREG_PRT15_BYP\r
+.set SCSI_Out__ATN__CTL, CYREG_PRT15_CTL\r
+.set SCSI_Out__ATN__DM0, CYREG_PRT15_DM0\r
+.set SCSI_Out__ATN__DM1, CYREG_PRT15_DM1\r
+.set SCSI_Out__ATN__DM2, CYREG_PRT15_DM2\r
+.set SCSI_Out__ATN__DR, CYREG_PRT15_DR\r
+.set SCSI_Out__ATN__INP_DIS, CYREG_PRT15_INP_DIS\r
+.set SCSI_Out__ATN__INTTYPE, CYREG_PICU15_INTTYPE4\r
+.set SCSI_Out__ATN__LCD_COM_SEG, CYREG_PRT15_LCD_COM_SEG\r
+.set SCSI_Out__ATN__LCD_EN, CYREG_PRT15_LCD_EN\r
+.set SCSI_Out__ATN__MASK, 0x10\r
+.set SCSI_Out__ATN__PC, CYREG_IO_PC_PRT15_PC4\r
+.set SCSI_Out__ATN__PORT, 15\r
+.set SCSI_Out__ATN__PRT, CYREG_PRT15_PRT\r
+.set SCSI_Out__ATN__PRTDSI__CAPS_SEL, CYREG_PRT15_CAPS_SEL\r
+.set SCSI_Out__ATN__PRTDSI__DBL_SYNC_IN, CYREG_PRT15_DBL_SYNC_IN\r
+.set SCSI_Out__ATN__PRTDSI__OE_SEL0, CYREG_PRT15_OE_SEL0\r
+.set SCSI_Out__ATN__PRTDSI__OE_SEL1, CYREG_PRT15_OE_SEL1\r
+.set SCSI_Out__ATN__PRTDSI__OUT_SEL0, CYREG_PRT15_OUT_SEL0\r
+.set SCSI_Out__ATN__PRTDSI__OUT_SEL1, CYREG_PRT15_OUT_SEL1\r
+.set SCSI_Out__ATN__PRTDSI__SYNC_OUT, CYREG_PRT15_SYNC_OUT\r
+.set SCSI_Out__ATN__PS, CYREG_PRT15_PS\r
+.set SCSI_Out__ATN__SHIFT, 4\r
+.set SCSI_Out__ATN__SLW, CYREG_PRT15_SLW\r
+.set SCSI_Out__BSY__AG, CYREG_PRT6_AG\r
+.set SCSI_Out__BSY__AMUX, CYREG_PRT6_AMUX\r
+.set SCSI_Out__BSY__BIE, CYREG_PRT6_BIE\r
+.set SCSI_Out__BSY__BIT_MASK, CYREG_PRT6_BIT_MASK\r
+.set SCSI_Out__BSY__BYP, CYREG_PRT6_BYP\r
+.set SCSI_Out__BSY__CTL, CYREG_PRT6_CTL\r
+.set SCSI_Out__BSY__DM0, CYREG_PRT6_DM0\r
+.set SCSI_Out__BSY__DM1, CYREG_PRT6_DM1\r
+.set SCSI_Out__BSY__DM2, CYREG_PRT6_DM2\r
+.set SCSI_Out__BSY__DR, CYREG_PRT6_DR\r
+.set SCSI_Out__BSY__INP_DIS, CYREG_PRT6_INP_DIS\r
+.set SCSI_Out__BSY__INTTYPE, CYREG_PICU6_INTTYPE1\r
+.set SCSI_Out__BSY__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG\r
+.set SCSI_Out__BSY__LCD_EN, CYREG_PRT6_LCD_EN\r
+.set SCSI_Out__BSY__MASK, 0x02\r
+.set SCSI_Out__BSY__PC, CYREG_PRT6_PC1\r
+.set SCSI_Out__BSY__PORT, 6\r
+.set SCSI_Out__BSY__PRT, CYREG_PRT6_PRT\r
+.set SCSI_Out__BSY__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL\r
+.set SCSI_Out__BSY__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN\r
+.set SCSI_Out__BSY__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0\r
+.set SCSI_Out__BSY__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1\r
+.set SCSI_Out__BSY__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0\r
+.set SCSI_Out__BSY__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1\r
+.set SCSI_Out__BSY__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT\r
+.set SCSI_Out__BSY__PS, CYREG_PRT6_PS\r
+.set SCSI_Out__BSY__SHIFT, 1\r
+.set SCSI_Out__BSY__SLW, CYREG_PRT6_SLW\r
+.set SCSI_Out__CD_raw__AG, CYREG_PRT0_AG\r
+.set SCSI_Out__CD_raw__AMUX, CYREG_PRT0_AMUX\r
+.set SCSI_Out__CD_raw__BIE, CYREG_PRT0_BIE\r
+.set SCSI_Out__CD_raw__BIT_MASK, CYREG_PRT0_BIT_MASK\r
+.set SCSI_Out__CD_raw__BYP, CYREG_PRT0_BYP\r
+.set SCSI_Out__CD_raw__CTL, CYREG_PRT0_CTL\r
+.set SCSI_Out__CD_raw__DM0, CYREG_PRT0_DM0\r
+.set SCSI_Out__CD_raw__DM1, CYREG_PRT0_DM1\r
+.set SCSI_Out__CD_raw__DM2, CYREG_PRT0_DM2\r
+.set SCSI_Out__CD_raw__DR, CYREG_PRT0_DR\r
+.set SCSI_Out__CD_raw__INP_DIS, CYREG_PRT0_INP_DIS\r
+.set SCSI_Out__CD_raw__INTTYPE, CYREG_PICU0_INTTYPE6\r
+.set SCSI_Out__CD_raw__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG\r
+.set SCSI_Out__CD_raw__LCD_EN, CYREG_PRT0_LCD_EN\r
+.set SCSI_Out__CD_raw__MASK, 0x40\r
+.set SCSI_Out__CD_raw__PC, CYREG_PRT0_PC6\r
+.set SCSI_Out__CD_raw__PORT, 0\r
+.set SCSI_Out__CD_raw__PRT, CYREG_PRT0_PRT\r
+.set SCSI_Out__CD_raw__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL\r
+.set SCSI_Out__CD_raw__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN\r
+.set SCSI_Out__CD_raw__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0\r
+.set SCSI_Out__CD_raw__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1\r
+.set SCSI_Out__CD_raw__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0\r
+.set SCSI_Out__CD_raw__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1\r
+.set SCSI_Out__CD_raw__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT\r
+.set SCSI_Out__CD_raw__PS, CYREG_PRT0_PS\r
+.set SCSI_Out__CD_raw__SHIFT, 6\r
+.set SCSI_Out__CD_raw__SLW, CYREG_PRT0_SLW\r
+.set SCSI_Out__DBP_raw__AG, CYREG_PRT15_AG\r
+.set SCSI_Out__DBP_raw__AMUX, CYREG_PRT15_AMUX\r
+.set SCSI_Out__DBP_raw__BIE, CYREG_PRT15_BIE\r
+.set SCSI_Out__DBP_raw__BIT_MASK, CYREG_PRT15_BIT_MASK\r
+.set SCSI_Out__DBP_raw__BYP, CYREG_PRT15_BYP\r
+.set SCSI_Out__DBP_raw__CTL, CYREG_PRT15_CTL\r
+.set SCSI_Out__DBP_raw__DM0, CYREG_PRT15_DM0\r
+.set SCSI_Out__DBP_raw__DM1, CYREG_PRT15_DM1\r
+.set SCSI_Out__DBP_raw__DM2, CYREG_PRT15_DM2\r
+.set SCSI_Out__DBP_raw__DR, CYREG_PRT15_DR\r
+.set SCSI_Out__DBP_raw__INP_DIS, CYREG_PRT15_INP_DIS\r
+.set SCSI_Out__DBP_raw__INTTYPE, CYREG_PICU15_INTTYPE5\r
+.set SCSI_Out__DBP_raw__LCD_COM_SEG, CYREG_PRT15_LCD_COM_SEG\r
+.set SCSI_Out__DBP_raw__LCD_EN, CYREG_PRT15_LCD_EN\r
+.set SCSI_Out__DBP_raw__MASK, 0x20\r
+.set SCSI_Out__DBP_raw__PC, CYREG_IO_PC_PRT15_PC5\r
+.set SCSI_Out__DBP_raw__PORT, 15\r
+.set SCSI_Out__DBP_raw__PRT, CYREG_PRT15_PRT\r
+.set SCSI_Out__DBP_raw__PRTDSI__CAPS_SEL, CYREG_PRT15_CAPS_SEL\r
+.set SCSI_Out__DBP_raw__PRTDSI__DBL_SYNC_IN, CYREG_PRT15_DBL_SYNC_IN\r
+.set SCSI_Out__DBP_raw__PRTDSI__OE_SEL0, CYREG_PRT15_OE_SEL0\r
+.set SCSI_Out__DBP_raw__PRTDSI__OE_SEL1, CYREG_PRT15_OE_SEL1\r
+.set SCSI_Out__DBP_raw__PRTDSI__OUT_SEL0, CYREG_PRT15_OUT_SEL0\r
+.set SCSI_Out__DBP_raw__PRTDSI__OUT_SEL1, CYREG_PRT15_OUT_SEL1\r
+.set SCSI_Out__DBP_raw__PRTDSI__SYNC_OUT, CYREG_PRT15_SYNC_OUT\r
+.set SCSI_Out__DBP_raw__PS, CYREG_PRT15_PS\r
+.set SCSI_Out__DBP_raw__SHIFT, 5\r
+.set SCSI_Out__DBP_raw__SLW, CYREG_PRT15_SLW\r
+.set SCSI_Out__IO_raw__AG, CYREG_PRT0_AG\r
+.set SCSI_Out__IO_raw__AMUX, CYREG_PRT0_AMUX\r
+.set SCSI_Out__IO_raw__BIE, CYREG_PRT0_BIE\r
+.set SCSI_Out__IO_raw__BIT_MASK, CYREG_PRT0_BIT_MASK\r
+.set SCSI_Out__IO_raw__BYP, CYREG_PRT0_BYP\r
+.set SCSI_Out__IO_raw__CTL, CYREG_PRT0_CTL\r
+.set SCSI_Out__IO_raw__DM0, CYREG_PRT0_DM0\r
+.set SCSI_Out__IO_raw__DM1, CYREG_PRT0_DM1\r
+.set SCSI_Out__IO_raw__DM2, CYREG_PRT0_DM2\r
+.set SCSI_Out__IO_raw__DR, CYREG_PRT0_DR\r
+.set SCSI_Out__IO_raw__INP_DIS, CYREG_PRT0_INP_DIS\r
+.set SCSI_Out__IO_raw__INTTYPE, CYREG_PICU0_INTTYPE2\r
+.set SCSI_Out__IO_raw__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG\r
+.set SCSI_Out__IO_raw__LCD_EN, CYREG_PRT0_LCD_EN\r
+.set SCSI_Out__IO_raw__MASK, 0x04\r
+.set SCSI_Out__IO_raw__PC, CYREG_PRT0_PC2\r
+.set SCSI_Out__IO_raw__PORT, 0\r
+.set SCSI_Out__IO_raw__PRT, CYREG_PRT0_PRT\r
+.set SCSI_Out__IO_raw__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL\r
+.set SCSI_Out__IO_raw__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN\r
+.set SCSI_Out__IO_raw__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0\r
+.set SCSI_Out__IO_raw__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1\r
+.set SCSI_Out__IO_raw__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0\r
+.set SCSI_Out__IO_raw__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1\r
+.set SCSI_Out__IO_raw__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT\r
+.set SCSI_Out__IO_raw__PS, CYREG_PRT0_PS\r
+.set SCSI_Out__IO_raw__SHIFT, 2\r
+.set SCSI_Out__IO_raw__SLW, CYREG_PRT0_SLW\r
+.set SCSI_Out__MSG_raw__AG, CYREG_PRT4_AG\r
+.set SCSI_Out__MSG_raw__AMUX, CYREG_PRT4_AMUX\r
+.set SCSI_Out__MSG_raw__BIE, CYREG_PRT4_BIE\r
+.set SCSI_Out__MSG_raw__BIT_MASK, CYREG_PRT4_BIT_MASK\r
+.set SCSI_Out__MSG_raw__BYP, CYREG_PRT4_BYP\r
+.set SCSI_Out__MSG_raw__CTL, CYREG_PRT4_CTL\r
+.set SCSI_Out__MSG_raw__DM0, CYREG_PRT4_DM0\r
+.set SCSI_Out__MSG_raw__DM1, CYREG_PRT4_DM1\r
+.set SCSI_Out__MSG_raw__DM2, CYREG_PRT4_DM2\r
+.set SCSI_Out__MSG_raw__DR, CYREG_PRT4_DR\r
+.set SCSI_Out__MSG_raw__INP_DIS, CYREG_PRT4_INP_DIS\r
+.set SCSI_Out__MSG_raw__INTTYPE, CYREG_PICU4_INTTYPE4\r
+.set SCSI_Out__MSG_raw__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG\r
+.set SCSI_Out__MSG_raw__LCD_EN, CYREG_PRT4_LCD_EN\r
+.set SCSI_Out__MSG_raw__MASK, 0x10\r
+.set SCSI_Out__MSG_raw__PC, CYREG_PRT4_PC4\r
+.set SCSI_Out__MSG_raw__PORT, 4\r
+.set SCSI_Out__MSG_raw__PRT, CYREG_PRT4_PRT\r
+.set SCSI_Out__MSG_raw__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL\r
+.set SCSI_Out__MSG_raw__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN\r
+.set SCSI_Out__MSG_raw__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0\r
+.set SCSI_Out__MSG_raw__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1\r
+.set SCSI_Out__MSG_raw__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0\r
+.set SCSI_Out__MSG_raw__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1\r
+.set SCSI_Out__MSG_raw__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT\r
+.set SCSI_Out__MSG_raw__PS, CYREG_PRT4_PS\r
+.set SCSI_Out__MSG_raw__SHIFT, 4\r
+.set SCSI_Out__MSG_raw__SLW, CYREG_PRT4_SLW\r
+.set SCSI_Out__REQ__AG, CYREG_PRT0_AG\r
+.set SCSI_Out__REQ__AMUX, CYREG_PRT0_AMUX\r
+.set SCSI_Out__REQ__BIE, CYREG_PRT0_BIE\r
+.set SCSI_Out__REQ__BIT_MASK, CYREG_PRT0_BIT_MASK\r
+.set SCSI_Out__REQ__BYP, CYREG_PRT0_BYP\r
+.set SCSI_Out__REQ__CTL, CYREG_PRT0_CTL\r
+.set SCSI_Out__REQ__DM0, CYREG_PRT0_DM0\r
+.set SCSI_Out__REQ__DM1, CYREG_PRT0_DM1\r
+.set SCSI_Out__REQ__DM2, CYREG_PRT0_DM2\r
+.set SCSI_Out__REQ__DR, CYREG_PRT0_DR\r
+.set SCSI_Out__REQ__INP_DIS, CYREG_PRT0_INP_DIS\r
+.set SCSI_Out__REQ__INTTYPE, CYREG_PICU0_INTTYPE3\r
+.set SCSI_Out__REQ__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG\r
+.set SCSI_Out__REQ__LCD_EN, CYREG_PRT0_LCD_EN\r
+.set SCSI_Out__REQ__MASK, 0x08\r
+.set SCSI_Out__REQ__PC, CYREG_PRT0_PC3\r
+.set SCSI_Out__REQ__PORT, 0\r
+.set SCSI_Out__REQ__PRT, CYREG_PRT0_PRT\r
+.set SCSI_Out__REQ__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL\r
+.set SCSI_Out__REQ__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN\r
+.set SCSI_Out__REQ__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0\r
+.set SCSI_Out__REQ__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1\r
+.set SCSI_Out__REQ__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0\r
+.set SCSI_Out__REQ__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1\r
+.set SCSI_Out__REQ__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT\r
+.set SCSI_Out__REQ__PS, CYREG_PRT0_PS\r
+.set SCSI_Out__REQ__SHIFT, 3\r
+.set SCSI_Out__REQ__SLW, CYREG_PRT0_SLW\r
+.set SCSI_Out__RST__AG, CYREG_PRT4_AG\r
+.set SCSI_Out__RST__AMUX, CYREG_PRT4_AMUX\r
+.set SCSI_Out__RST__BIE, CYREG_PRT4_BIE\r
+.set SCSI_Out__RST__BIT_MASK, CYREG_PRT4_BIT_MASK\r
+.set SCSI_Out__RST__BYP, CYREG_PRT4_BYP\r
+.set SCSI_Out__RST__CTL, CYREG_PRT4_CTL\r
+.set SCSI_Out__RST__DM0, CYREG_PRT4_DM0\r
+.set SCSI_Out__RST__DM1, CYREG_PRT4_DM1\r
+.set SCSI_Out__RST__DM2, CYREG_PRT4_DM2\r
+.set SCSI_Out__RST__DR, CYREG_PRT4_DR\r
+.set SCSI_Out__RST__INP_DIS, CYREG_PRT4_INP_DIS\r
+.set SCSI_Out__RST__INTTYPE, CYREG_PICU4_INTTYPE5\r
+.set SCSI_Out__RST__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG\r
+.set SCSI_Out__RST__LCD_EN, CYREG_PRT4_LCD_EN\r
+.set SCSI_Out__RST__MASK, 0x20\r
+.set SCSI_Out__RST__PC, CYREG_PRT4_PC5\r
+.set SCSI_Out__RST__PORT, 4\r
+.set SCSI_Out__RST__PRT, CYREG_PRT4_PRT\r
+.set SCSI_Out__RST__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL\r
+.set SCSI_Out__RST__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN\r
+.set SCSI_Out__RST__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0\r
+.set SCSI_Out__RST__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1\r
+.set SCSI_Out__RST__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0\r
+.set SCSI_Out__RST__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1\r
+.set SCSI_Out__RST__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT\r
+.set SCSI_Out__RST__PS, CYREG_PRT4_PS\r
+.set SCSI_Out__RST__SHIFT, 5\r
+.set SCSI_Out__RST__SLW, CYREG_PRT4_SLW\r
+.set SCSI_Out__SEL__AG, CYREG_PRT0_AG\r
+.set SCSI_Out__SEL__AMUX, CYREG_PRT0_AMUX\r
+.set SCSI_Out__SEL__BIE, CYREG_PRT0_BIE\r
+.set SCSI_Out__SEL__BIT_MASK, CYREG_PRT0_BIT_MASK\r
+.set SCSI_Out__SEL__BYP, CYREG_PRT0_BYP\r
+.set SCSI_Out__SEL__CTL, CYREG_PRT0_CTL\r
+.set SCSI_Out__SEL__DM0, CYREG_PRT0_DM0\r
+.set SCSI_Out__SEL__DM1, CYREG_PRT0_DM1\r
+.set SCSI_Out__SEL__DM2, CYREG_PRT0_DM2\r
+.set SCSI_Out__SEL__DR, CYREG_PRT0_DR\r
+.set SCSI_Out__SEL__INP_DIS, CYREG_PRT0_INP_DIS\r
+.set SCSI_Out__SEL__INTTYPE, CYREG_PICU0_INTTYPE7\r
+.set SCSI_Out__SEL__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG\r
+.set SCSI_Out__SEL__LCD_EN, CYREG_PRT0_LCD_EN\r
+.set SCSI_Out__SEL__MASK, 0x80\r
+.set SCSI_Out__SEL__PC, CYREG_PRT0_PC7\r
+.set SCSI_Out__SEL__PORT, 0\r
+.set SCSI_Out__SEL__PRT, CYREG_PRT0_PRT\r
+.set SCSI_Out__SEL__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL\r
+.set SCSI_Out__SEL__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN\r
+.set SCSI_Out__SEL__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0\r
+.set SCSI_Out__SEL__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1\r
+.set SCSI_Out__SEL__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0\r
+.set SCSI_Out__SEL__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1\r
+.set SCSI_Out__SEL__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT\r
+.set SCSI_Out__SEL__PS, CYREG_PRT0_PS\r
+.set SCSI_Out__SEL__SHIFT, 7\r
+.set SCSI_Out__SEL__SLW, CYREG_PRT0_SLW\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__0__MASK, 0x01\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__0__POS, 0\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__1__MASK, 0x02\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__1__POS, 1\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB14_15_ACTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB14_15_CTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB14_15_CTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB14_15_CTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB14_15_CTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB14_15_MSK\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB14_15_MSK\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB14_15_MSK\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB14_15_MSK\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__2__MASK, 0x04\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__2__POS, 2\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__3__MASK, 0x08\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__3__POS, 3\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__4__MASK, 0x10\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__4__POS, 4\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__5__MASK, 0x20\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__5__POS, 5\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__6__MASK, 0x40\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__6__POS, 6\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__7__MASK, 0x80\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__7__POS, 7\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB14_ACTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB14_CTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB14_ST_CTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB14_CTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB14_ST_CTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__MASK, 0xFF\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB14_MSK_ACTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB14_MSK_ACTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB14_MSK\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK, 0x01\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__0__POS, 0\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB12_13_ACTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB12_13_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB12_13_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB12_13_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB12_13_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB12_13_MSK\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB12_13_MSK\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB12_13_MSK\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB12_13_MSK\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB12_ACTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB12_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB12_ST_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB12_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB12_ST_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK, 0x01\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB12_MSK\r
+.set SCSI_Out_DBx__0__AG, CYREG_PRT5_AG\r
+.set SCSI_Out_DBx__0__AMUX, CYREG_PRT5_AMUX\r
+.set SCSI_Out_DBx__0__BIE, CYREG_PRT5_BIE\r
+.set SCSI_Out_DBx__0__BIT_MASK, CYREG_PRT5_BIT_MASK\r
+.set SCSI_Out_DBx__0__BYP, CYREG_PRT5_BYP\r
+.set SCSI_Out_DBx__0__CTL, CYREG_PRT5_CTL\r
+.set SCSI_Out_DBx__0__DM0, CYREG_PRT5_DM0\r
+.set SCSI_Out_DBx__0__DM1, CYREG_PRT5_DM1\r
+.set SCSI_Out_DBx__0__DM2, CYREG_PRT5_DM2\r
+.set SCSI_Out_DBx__0__DR, CYREG_PRT5_DR\r
+.set SCSI_Out_DBx__0__INP_DIS, CYREG_PRT5_INP_DIS\r
+.set SCSI_Out_DBx__0__INTTYPE, CYREG_PICU5_INTTYPE1\r
+.set SCSI_Out_DBx__0__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG\r
+.set SCSI_Out_DBx__0__LCD_EN, CYREG_PRT5_LCD_EN\r
+.set SCSI_Out_DBx__0__MASK, 0x02\r
+.set SCSI_Out_DBx__0__PC, CYREG_PRT5_PC1\r
+.set SCSI_Out_DBx__0__PORT, 5\r
+.set SCSI_Out_DBx__0__PRT, CYREG_PRT5_PRT\r
+.set SCSI_Out_DBx__0__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL\r
+.set SCSI_Out_DBx__0__PRTDSI__DBL_SYNC_IN, CYREG_PRT5_DBL_SYNC_IN\r
+.set SCSI_Out_DBx__0__PRTDSI__OE_SEL0, CYREG_PRT5_OE_SEL0\r
+.set SCSI_Out_DBx__0__PRTDSI__OE_SEL1, CYREG_PRT5_OE_SEL1\r
+.set SCSI_Out_DBx__0__PRTDSI__OUT_SEL0, CYREG_PRT5_OUT_SEL0\r
+.set SCSI_Out_DBx__0__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1\r
+.set SCSI_Out_DBx__0__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT\r
+.set SCSI_Out_DBx__0__PS, CYREG_PRT5_PS\r
+.set SCSI_Out_DBx__0__SHIFT, 1\r
+.set SCSI_Out_DBx__0__SLW, CYREG_PRT5_SLW\r
+.set SCSI_Out_DBx__1__AG, CYREG_PRT5_AG\r
+.set SCSI_Out_DBx__1__AMUX, CYREG_PRT5_AMUX\r
+.set SCSI_Out_DBx__1__BIE, CYREG_PRT5_BIE\r
+.set SCSI_Out_DBx__1__BIT_MASK, CYREG_PRT5_BIT_MASK\r
+.set SCSI_Out_DBx__1__BYP, CYREG_PRT5_BYP\r
+.set SCSI_Out_DBx__1__CTL, CYREG_PRT5_CTL\r
+.set SCSI_Out_DBx__1__DM0, CYREG_PRT5_DM0\r
+.set SCSI_Out_DBx__1__DM1, CYREG_PRT5_DM1\r
+.set SCSI_Out_DBx__1__DM2, CYREG_PRT5_DM2\r
+.set SCSI_Out_DBx__1__DR, CYREG_PRT5_DR\r
+.set SCSI_Out_DBx__1__INP_DIS, CYREG_PRT5_INP_DIS\r
+.set SCSI_Out_DBx__1__INTTYPE, CYREG_PICU5_INTTYPE0\r
+.set SCSI_Out_DBx__1__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG\r
+.set SCSI_Out_DBx__1__LCD_EN, CYREG_PRT5_LCD_EN\r
+.set SCSI_Out_DBx__1__MASK, 0x01\r
+.set SCSI_Out_DBx__1__PC, CYREG_PRT5_PC0\r
+.set SCSI_Out_DBx__1__PORT, 5\r
+.set SCSI_Out_DBx__1__PRT, CYREG_PRT5_PRT\r
+.set SCSI_Out_DBx__1__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL\r
+.set SCSI_Out_DBx__1__PRTDSI__DBL_SYNC_IN, CYREG_PRT5_DBL_SYNC_IN\r
+.set SCSI_Out_DBx__1__PRTDSI__OE_SEL0, CYREG_PRT5_OE_SEL0\r
+.set SCSI_Out_DBx__1__PRTDSI__OE_SEL1, CYREG_PRT5_OE_SEL1\r
+.set SCSI_Out_DBx__1__PRTDSI__OUT_SEL0, CYREG_PRT5_OUT_SEL0\r
+.set SCSI_Out_DBx__1__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1\r
+.set SCSI_Out_DBx__1__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT\r
+.set SCSI_Out_DBx__1__PS, CYREG_PRT5_PS\r
+.set SCSI_Out_DBx__1__SHIFT, 0\r
+.set SCSI_Out_DBx__1__SLW, CYREG_PRT5_SLW\r
+.set SCSI_Out_DBx__2__AG, CYREG_PRT6_AG\r
+.set SCSI_Out_DBx__2__AMUX, CYREG_PRT6_AMUX\r
+.set SCSI_Out_DBx__2__BIE, CYREG_PRT6_BIE\r
+.set SCSI_Out_DBx__2__BIT_MASK, CYREG_PRT6_BIT_MASK\r
+.set SCSI_Out_DBx__2__BYP, CYREG_PRT6_BYP\r
+.set SCSI_Out_DBx__2__CTL, CYREG_PRT6_CTL\r
+.set SCSI_Out_DBx__2__DM0, CYREG_PRT6_DM0\r
+.set SCSI_Out_DBx__2__DM1, CYREG_PRT6_DM1\r
+.set SCSI_Out_DBx__2__DM2, CYREG_PRT6_DM2\r
+.set SCSI_Out_DBx__2__DR, CYREG_PRT6_DR\r
+.set SCSI_Out_DBx__2__INP_DIS, CYREG_PRT6_INP_DIS\r
+.set SCSI_Out_DBx__2__INTTYPE, CYREG_PICU6_INTTYPE5\r
+.set SCSI_Out_DBx__2__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG\r
+.set SCSI_Out_DBx__2__LCD_EN, CYREG_PRT6_LCD_EN\r
+.set SCSI_Out_DBx__2__MASK, 0x20\r
+.set SCSI_Out_DBx__2__PC, CYREG_PRT6_PC5\r
+.set SCSI_Out_DBx__2__PORT, 6\r
+.set SCSI_Out_DBx__2__PRT, CYREG_PRT6_PRT\r
+.set SCSI_Out_DBx__2__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL\r
+.set SCSI_Out_DBx__2__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN\r
+.set SCSI_Out_DBx__2__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0\r
+.set SCSI_Out_DBx__2__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1\r
+.set SCSI_Out_DBx__2__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0\r
+.set SCSI_Out_DBx__2__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1\r
+.set SCSI_Out_DBx__2__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT\r
+.set SCSI_Out_DBx__2__PS, CYREG_PRT6_PS\r
+.set SCSI_Out_DBx__2__SHIFT, 5\r
+.set SCSI_Out_DBx__2__SLW, CYREG_PRT6_SLW\r
+.set SCSI_Out_DBx__3__AG, CYREG_PRT6_AG\r
+.set SCSI_Out_DBx__3__AMUX, CYREG_PRT6_AMUX\r
+.set SCSI_Out_DBx__3__BIE, CYREG_PRT6_BIE\r
+.set SCSI_Out_DBx__3__BIT_MASK, CYREG_PRT6_BIT_MASK\r
+.set SCSI_Out_DBx__3__BYP, CYREG_PRT6_BYP\r
+.set SCSI_Out_DBx__3__CTL, CYREG_PRT6_CTL\r
+.set SCSI_Out_DBx__3__DM0, CYREG_PRT6_DM0\r
+.set SCSI_Out_DBx__3__DM1, CYREG_PRT6_DM1\r
+.set SCSI_Out_DBx__3__DM2, CYREG_PRT6_DM2\r
+.set SCSI_Out_DBx__3__DR, CYREG_PRT6_DR\r
+.set SCSI_Out_DBx__3__INP_DIS, CYREG_PRT6_INP_DIS\r
+.set SCSI_Out_DBx__3__INTTYPE, CYREG_PICU6_INTTYPE4\r
+.set SCSI_Out_DBx__3__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG\r
+.set SCSI_Out_DBx__3__LCD_EN, CYREG_PRT6_LCD_EN\r
+.set SCSI_Out_DBx__3__MASK, 0x10\r
+.set SCSI_Out_DBx__3__PC, CYREG_PRT6_PC4\r
+.set SCSI_Out_DBx__3__PORT, 6\r
+.set SCSI_Out_DBx__3__PRT, CYREG_PRT6_PRT\r
+.set SCSI_Out_DBx__3__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL\r
+.set SCSI_Out_DBx__3__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN\r
+.set SCSI_Out_DBx__3__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0\r
+.set SCSI_Out_DBx__3__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1\r
+.set SCSI_Out_DBx__3__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0\r
+.set SCSI_Out_DBx__3__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1\r
+.set SCSI_Out_DBx__3__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT\r
+.set SCSI_Out_DBx__3__PS, CYREG_PRT6_PS\r
+.set SCSI_Out_DBx__3__SHIFT, 4\r
+.set SCSI_Out_DBx__3__SLW, CYREG_PRT6_SLW\r
+.set SCSI_Out_DBx__4__AG, CYREG_PRT2_AG\r
+.set SCSI_Out_DBx__4__AMUX, CYREG_PRT2_AMUX\r
+.set SCSI_Out_DBx__4__BIE, CYREG_PRT2_BIE\r
+.set SCSI_Out_DBx__4__BIT_MASK, CYREG_PRT2_BIT_MASK\r
+.set SCSI_Out_DBx__4__BYP, CYREG_PRT2_BYP\r
+.set SCSI_Out_DBx__4__CTL, CYREG_PRT2_CTL\r
+.set SCSI_Out_DBx__4__DM0, CYREG_PRT2_DM0\r
+.set SCSI_Out_DBx__4__DM1, CYREG_PRT2_DM1\r
+.set SCSI_Out_DBx__4__DM2, CYREG_PRT2_DM2\r
+.set SCSI_Out_DBx__4__DR, CYREG_PRT2_DR\r
+.set SCSI_Out_DBx__4__INP_DIS, CYREG_PRT2_INP_DIS\r
+.set SCSI_Out_DBx__4__INTTYPE, CYREG_PICU2_INTTYPE7\r
+.set SCSI_Out_DBx__4__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG\r
+.set SCSI_Out_DBx__4__LCD_EN, CYREG_PRT2_LCD_EN\r
+.set SCSI_Out_DBx__4__MASK, 0x80\r
+.set SCSI_Out_DBx__4__PC, CYREG_PRT2_PC7\r
+.set SCSI_Out_DBx__4__PORT, 2\r
+.set SCSI_Out_DBx__4__PRT, CYREG_PRT2_PRT\r
+.set SCSI_Out_DBx__4__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL\r
+.set SCSI_Out_DBx__4__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN\r
+.set SCSI_Out_DBx__4__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0\r
+.set SCSI_Out_DBx__4__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1\r
+.set SCSI_Out_DBx__4__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0\r
+.set SCSI_Out_DBx__4__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1\r
+.set SCSI_Out_DBx__4__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT\r
+.set SCSI_Out_DBx__4__PS, CYREG_PRT2_PS\r
+.set SCSI_Out_DBx__4__SHIFT, 7\r
+.set SCSI_Out_DBx__4__SLW, CYREG_PRT2_SLW\r
+.set SCSI_Out_DBx__5__AG, CYREG_PRT2_AG\r
+.set SCSI_Out_DBx__5__AMUX, CYREG_PRT2_AMUX\r
+.set SCSI_Out_DBx__5__BIE, CYREG_PRT2_BIE\r
+.set SCSI_Out_DBx__5__BIT_MASK, CYREG_PRT2_BIT_MASK\r
+.set SCSI_Out_DBx__5__BYP, CYREG_PRT2_BYP\r
+.set SCSI_Out_DBx__5__CTL, CYREG_PRT2_CTL\r
+.set SCSI_Out_DBx__5__DM0, CYREG_PRT2_DM0\r
+.set SCSI_Out_DBx__5__DM1, CYREG_PRT2_DM1\r
+.set SCSI_Out_DBx__5__DM2, CYREG_PRT2_DM2\r
+.set SCSI_Out_DBx__5__DR, CYREG_PRT2_DR\r
+.set SCSI_Out_DBx__5__INP_DIS, CYREG_PRT2_INP_DIS\r
+.set SCSI_Out_DBx__5__INTTYPE, CYREG_PICU2_INTTYPE6\r
+.set SCSI_Out_DBx__5__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG\r
+.set SCSI_Out_DBx__5__LCD_EN, CYREG_PRT2_LCD_EN\r
+.set SCSI_Out_DBx__5__MASK, 0x40\r
+.set SCSI_Out_DBx__5__PC, CYREG_PRT2_PC6\r
+.set SCSI_Out_DBx__5__PORT, 2\r
+.set SCSI_Out_DBx__5__PRT, CYREG_PRT2_PRT\r
+.set SCSI_Out_DBx__5__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL\r
+.set SCSI_Out_DBx__5__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN\r
+.set SCSI_Out_DBx__5__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0\r
+.set SCSI_Out_DBx__5__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1\r
+.set SCSI_Out_DBx__5__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0\r
+.set SCSI_Out_DBx__5__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1\r
+.set SCSI_Out_DBx__5__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT\r
+.set SCSI_Out_DBx__5__PS, CYREG_PRT2_PS\r
+.set SCSI_Out_DBx__5__SHIFT, 6\r
+.set SCSI_Out_DBx__5__SLW, CYREG_PRT2_SLW\r
+.set SCSI_Out_DBx__6__AG, CYREG_PRT2_AG\r
+.set SCSI_Out_DBx__6__AMUX, CYREG_PRT2_AMUX\r
+.set SCSI_Out_DBx__6__BIE, CYREG_PRT2_BIE\r
+.set SCSI_Out_DBx__6__BIT_MASK, CYREG_PRT2_BIT_MASK\r
+.set SCSI_Out_DBx__6__BYP, CYREG_PRT2_BYP\r
+.set SCSI_Out_DBx__6__CTL, CYREG_PRT2_CTL\r
+.set SCSI_Out_DBx__6__DM0, CYREG_PRT2_DM0\r
+.set SCSI_Out_DBx__6__DM1, CYREG_PRT2_DM1\r
+.set SCSI_Out_DBx__6__DM2, CYREG_PRT2_DM2\r
+.set SCSI_Out_DBx__6__DR, CYREG_PRT2_DR\r
+.set SCSI_Out_DBx__6__INP_DIS, CYREG_PRT2_INP_DIS\r
+.set SCSI_Out_DBx__6__INTTYPE, CYREG_PICU2_INTTYPE3\r
+.set SCSI_Out_DBx__6__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG\r
+.set SCSI_Out_DBx__6__LCD_EN, CYREG_PRT2_LCD_EN\r
+.set SCSI_Out_DBx__6__MASK, 0x08\r
+.set SCSI_Out_DBx__6__PC, CYREG_PRT2_PC3\r
+.set SCSI_Out_DBx__6__PORT, 2\r
+.set SCSI_Out_DBx__6__PRT, CYREG_PRT2_PRT\r
+.set SCSI_Out_DBx__6__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL\r
+.set SCSI_Out_DBx__6__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN\r
+.set SCSI_Out_DBx__6__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0\r
+.set SCSI_Out_DBx__6__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1\r
+.set SCSI_Out_DBx__6__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0\r
+.set SCSI_Out_DBx__6__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1\r
+.set SCSI_Out_DBx__6__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT\r
+.set SCSI_Out_DBx__6__PS, CYREG_PRT2_PS\r
+.set SCSI_Out_DBx__6__SHIFT, 3\r
+.set SCSI_Out_DBx__6__SLW, CYREG_PRT2_SLW\r
+.set SCSI_Out_DBx__7__AG, CYREG_PRT2_AG\r
+.set SCSI_Out_DBx__7__AMUX, CYREG_PRT2_AMUX\r
+.set SCSI_Out_DBx__7__BIE, CYREG_PRT2_BIE\r
+.set SCSI_Out_DBx__7__BIT_MASK, CYREG_PRT2_BIT_MASK\r
+.set SCSI_Out_DBx__7__BYP, CYREG_PRT2_BYP\r
+.set SCSI_Out_DBx__7__CTL, CYREG_PRT2_CTL\r
+.set SCSI_Out_DBx__7__DM0, CYREG_PRT2_DM0\r
+.set SCSI_Out_DBx__7__DM1, CYREG_PRT2_DM1\r
+.set SCSI_Out_DBx__7__DM2, CYREG_PRT2_DM2\r
+.set SCSI_Out_DBx__7__DR, CYREG_PRT2_DR\r
+.set SCSI_Out_DBx__7__INP_DIS, CYREG_PRT2_INP_DIS\r
+.set SCSI_Out_DBx__7__INTTYPE, CYREG_PICU2_INTTYPE2\r
+.set SCSI_Out_DBx__7__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG\r
+.set SCSI_Out_DBx__7__LCD_EN, CYREG_PRT2_LCD_EN\r
+.set SCSI_Out_DBx__7__MASK, 0x04\r
+.set SCSI_Out_DBx__7__PC, CYREG_PRT2_PC2\r
+.set SCSI_Out_DBx__7__PORT, 2\r
+.set SCSI_Out_DBx__7__PRT, CYREG_PRT2_PRT\r
+.set SCSI_Out_DBx__7__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL\r
+.set SCSI_Out_DBx__7__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN\r
+.set SCSI_Out_DBx__7__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0\r
+.set SCSI_Out_DBx__7__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1\r
+.set SCSI_Out_DBx__7__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0\r
+.set SCSI_Out_DBx__7__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1\r
+.set SCSI_Out_DBx__7__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT\r
+.set SCSI_Out_DBx__7__PS, CYREG_PRT2_PS\r
+.set SCSI_Out_DBx__7__SHIFT, 2\r
+.set SCSI_Out_DBx__7__SLW, CYREG_PRT2_SLW\r
+.set SCSI_Out_DBx__DB0__AG, CYREG_PRT5_AG\r
+.set SCSI_Out_DBx__DB0__AMUX, CYREG_PRT5_AMUX\r
+.set SCSI_Out_DBx__DB0__BIE, CYREG_PRT5_BIE\r
+.set SCSI_Out_DBx__DB0__BIT_MASK, CYREG_PRT5_BIT_MASK\r
+.set SCSI_Out_DBx__DB0__BYP, CYREG_PRT5_BYP\r
+.set SCSI_Out_DBx__DB0__CTL, CYREG_PRT5_CTL\r
+.set SCSI_Out_DBx__DB0__DM0, CYREG_PRT5_DM0\r
+.set SCSI_Out_DBx__DB0__DM1, CYREG_PRT5_DM1\r
+.set SCSI_Out_DBx__DB0__DM2, CYREG_PRT5_DM2\r
+.set SCSI_Out_DBx__DB0__DR, CYREG_PRT5_DR\r
+.set SCSI_Out_DBx__DB0__INP_DIS, CYREG_PRT5_INP_DIS\r
+.set SCSI_Out_DBx__DB0__INTTYPE, CYREG_PICU5_INTTYPE1\r
+.set SCSI_Out_DBx__DB0__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG\r
+.set SCSI_Out_DBx__DB0__LCD_EN, CYREG_PRT5_LCD_EN\r
+.set SCSI_Out_DBx__DB0__MASK, 0x02\r
+.set SCSI_Out_DBx__DB0__PC, CYREG_PRT5_PC1\r
+.set SCSI_Out_DBx__DB0__PORT, 5\r
+.set SCSI_Out_DBx__DB0__PRT, CYREG_PRT5_PRT\r
+.set SCSI_Out_DBx__DB0__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL\r
+.set SCSI_Out_DBx__DB0__PRTDSI__DBL_SYNC_IN, CYREG_PRT5_DBL_SYNC_IN\r
+.set SCSI_Out_DBx__DB0__PRTDSI__OE_SEL0, CYREG_PRT5_OE_SEL0\r
+.set SCSI_Out_DBx__DB0__PRTDSI__OE_SEL1, CYREG_PRT5_OE_SEL1\r
+.set SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL0, CYREG_PRT5_OUT_SEL0\r
+.set SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1\r
+.set SCSI_Out_DBx__DB0__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT\r
+.set SCSI_Out_DBx__DB0__PS, CYREG_PRT5_PS\r
+.set SCSI_Out_DBx__DB0__SHIFT, 1\r
+.set SCSI_Out_DBx__DB0__SLW, CYREG_PRT5_SLW\r
+.set SCSI_Out_DBx__DB1__AG, CYREG_PRT5_AG\r
+.set SCSI_Out_DBx__DB1__AMUX, CYREG_PRT5_AMUX\r
+.set SCSI_Out_DBx__DB1__BIE, CYREG_PRT5_BIE\r
+.set SCSI_Out_DBx__DB1__BIT_MASK, CYREG_PRT5_BIT_MASK\r
+.set SCSI_Out_DBx__DB1__BYP, CYREG_PRT5_BYP\r
+.set SCSI_Out_DBx__DB1__CTL, CYREG_PRT5_CTL\r
+.set SCSI_Out_DBx__DB1__DM0, CYREG_PRT5_DM0\r
+.set SCSI_Out_DBx__DB1__DM1, CYREG_PRT5_DM1\r
+.set SCSI_Out_DBx__DB1__DM2, CYREG_PRT5_DM2\r
+.set SCSI_Out_DBx__DB1__DR, CYREG_PRT5_DR\r
+.set SCSI_Out_DBx__DB1__INP_DIS, CYREG_PRT5_INP_DIS\r
+.set SCSI_Out_DBx__DB1__INTTYPE, CYREG_PICU5_INTTYPE0\r
+.set SCSI_Out_DBx__DB1__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG\r
+.set SCSI_Out_DBx__DB1__LCD_EN, CYREG_PRT5_LCD_EN\r
+.set SCSI_Out_DBx__DB1__MASK, 0x01\r
+.set SCSI_Out_DBx__DB1__PC, CYREG_PRT5_PC0\r
+.set SCSI_Out_DBx__DB1__PORT, 5\r
+.set SCSI_Out_DBx__DB1__PRT, CYREG_PRT5_PRT\r
+.set SCSI_Out_DBx__DB1__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL\r
+.set SCSI_Out_DBx__DB1__PRTDSI__DBL_SYNC_IN, CYREG_PRT5_DBL_SYNC_IN\r
+.set SCSI_Out_DBx__DB1__PRTDSI__OE_SEL0, CYREG_PRT5_OE_SEL0\r
+.set SCSI_Out_DBx__DB1__PRTDSI__OE_SEL1, CYREG_PRT5_OE_SEL1\r
+.set SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL0, CYREG_PRT5_OUT_SEL0\r
+.set SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1\r
+.set SCSI_Out_DBx__DB1__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT\r
+.set SCSI_Out_DBx__DB1__PS, CYREG_PRT5_PS\r
+.set SCSI_Out_DBx__DB1__SHIFT, 0\r
+.set SCSI_Out_DBx__DB1__SLW, CYREG_PRT5_SLW\r
+.set SCSI_Out_DBx__DB2__AG, CYREG_PRT6_AG\r
+.set SCSI_Out_DBx__DB2__AMUX, CYREG_PRT6_AMUX\r
+.set SCSI_Out_DBx__DB2__BIE, CYREG_PRT6_BIE\r
+.set SCSI_Out_DBx__DB2__BIT_MASK, CYREG_PRT6_BIT_MASK\r
+.set SCSI_Out_DBx__DB2__BYP, CYREG_PRT6_BYP\r
+.set SCSI_Out_DBx__DB2__CTL, CYREG_PRT6_CTL\r
+.set SCSI_Out_DBx__DB2__DM0, CYREG_PRT6_DM0\r
+.set SCSI_Out_DBx__DB2__DM1, CYREG_PRT6_DM1\r
+.set SCSI_Out_DBx__DB2__DM2, CYREG_PRT6_DM2\r
+.set SCSI_Out_DBx__DB2__DR, CYREG_PRT6_DR\r
+.set SCSI_Out_DBx__DB2__INP_DIS, CYREG_PRT6_INP_DIS\r
+.set SCSI_Out_DBx__DB2__INTTYPE, CYREG_PICU6_INTTYPE5\r
+.set SCSI_Out_DBx__DB2__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG\r
+.set SCSI_Out_DBx__DB2__LCD_EN, CYREG_PRT6_LCD_EN\r
+.set SCSI_Out_DBx__DB2__MASK, 0x20\r
+.set SCSI_Out_DBx__DB2__PC, CYREG_PRT6_PC5\r
+.set SCSI_Out_DBx__DB2__PORT, 6\r
+.set SCSI_Out_DBx__DB2__PRT, CYREG_PRT6_PRT\r
+.set SCSI_Out_DBx__DB2__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL\r
+.set SCSI_Out_DBx__DB2__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN\r
+.set SCSI_Out_DBx__DB2__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0\r
+.set SCSI_Out_DBx__DB2__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1\r
+.set SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0\r
+.set SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1\r
+.set SCSI_Out_DBx__DB2__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT\r
+.set SCSI_Out_DBx__DB2__PS, CYREG_PRT6_PS\r
+.set SCSI_Out_DBx__DB2__SHIFT, 5\r
+.set SCSI_Out_DBx__DB2__SLW, CYREG_PRT6_SLW\r
+.set SCSI_Out_DBx__DB3__AG, CYREG_PRT6_AG\r
+.set SCSI_Out_DBx__DB3__AMUX, CYREG_PRT6_AMUX\r
+.set SCSI_Out_DBx__DB3__BIE, CYREG_PRT6_BIE\r
+.set SCSI_Out_DBx__DB3__BIT_MASK, CYREG_PRT6_BIT_MASK\r
+.set SCSI_Out_DBx__DB3__BYP, CYREG_PRT6_BYP\r
+.set SCSI_Out_DBx__DB3__CTL, CYREG_PRT6_CTL\r
+.set SCSI_Out_DBx__DB3__DM0, CYREG_PRT6_DM0\r
+.set SCSI_Out_DBx__DB3__DM1, CYREG_PRT6_DM1\r
+.set SCSI_Out_DBx__DB3__DM2, CYREG_PRT6_DM2\r
+.set SCSI_Out_DBx__DB3__DR, CYREG_PRT6_DR\r
+.set SCSI_Out_DBx__DB3__INP_DIS, CYREG_PRT6_INP_DIS\r
+.set SCSI_Out_DBx__DB3__INTTYPE, CYREG_PICU6_INTTYPE4\r
+.set SCSI_Out_DBx__DB3__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG\r
+.set SCSI_Out_DBx__DB3__LCD_EN, CYREG_PRT6_LCD_EN\r
+.set SCSI_Out_DBx__DB3__MASK, 0x10\r
+.set SCSI_Out_DBx__DB3__PC, CYREG_PRT6_PC4\r
+.set SCSI_Out_DBx__DB3__PORT, 6\r
+.set SCSI_Out_DBx__DB3__PRT, CYREG_PRT6_PRT\r
+.set SCSI_Out_DBx__DB3__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL\r
+.set SCSI_Out_DBx__DB3__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN\r
+.set SCSI_Out_DBx__DB3__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0\r
+.set SCSI_Out_DBx__DB3__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1\r
+.set SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0\r
+.set SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1\r
+.set SCSI_Out_DBx__DB3__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT\r
+.set SCSI_Out_DBx__DB3__PS, CYREG_PRT6_PS\r
+.set SCSI_Out_DBx__DB3__SHIFT, 4\r
+.set SCSI_Out_DBx__DB3__SLW, CYREG_PRT6_SLW\r
+.set SCSI_Out_DBx__DB4__AG, CYREG_PRT2_AG\r
+.set SCSI_Out_DBx__DB4__AMUX, CYREG_PRT2_AMUX\r
+.set SCSI_Out_DBx__DB4__BIE, CYREG_PRT2_BIE\r
+.set SCSI_Out_DBx__DB4__BIT_MASK, CYREG_PRT2_BIT_MASK\r
+.set SCSI_Out_DBx__DB4__BYP, CYREG_PRT2_BYP\r
+.set SCSI_Out_DBx__DB4__CTL, CYREG_PRT2_CTL\r
+.set SCSI_Out_DBx__DB4__DM0, CYREG_PRT2_DM0\r
+.set SCSI_Out_DBx__DB4__DM1, CYREG_PRT2_DM1\r
+.set SCSI_Out_DBx__DB4__DM2, CYREG_PRT2_DM2\r
+.set SCSI_Out_DBx__DB4__DR, CYREG_PRT2_DR\r
+.set SCSI_Out_DBx__DB4__INP_DIS, CYREG_PRT2_INP_DIS\r
+.set SCSI_Out_DBx__DB4__INTTYPE, CYREG_PICU2_INTTYPE7\r
+.set SCSI_Out_DBx__DB4__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG\r
+.set SCSI_Out_DBx__DB4__LCD_EN, CYREG_PRT2_LCD_EN\r
+.set SCSI_Out_DBx__DB4__MASK, 0x80\r
+.set SCSI_Out_DBx__DB4__PC, CYREG_PRT2_PC7\r
+.set SCSI_Out_DBx__DB4__PORT, 2\r
+.set SCSI_Out_DBx__DB4__PRT, CYREG_PRT2_PRT\r
+.set SCSI_Out_DBx__DB4__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL\r
+.set SCSI_Out_DBx__DB4__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN\r
+.set SCSI_Out_DBx__DB4__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0\r
+.set SCSI_Out_DBx__DB4__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1\r
+.set SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0\r
+.set SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1\r
+.set SCSI_Out_DBx__DB4__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT\r
+.set SCSI_Out_DBx__DB4__PS, CYREG_PRT2_PS\r
+.set SCSI_Out_DBx__DB4__SHIFT, 7\r
+.set SCSI_Out_DBx__DB4__SLW, CYREG_PRT2_SLW\r
+.set SCSI_Out_DBx__DB5__AG, CYREG_PRT2_AG\r
+.set SCSI_Out_DBx__DB5__AMUX, CYREG_PRT2_AMUX\r
+.set SCSI_Out_DBx__DB5__BIE, CYREG_PRT2_BIE\r
+.set SCSI_Out_DBx__DB5__BIT_MASK, CYREG_PRT2_BIT_MASK\r
+.set SCSI_Out_DBx__DB5__BYP, CYREG_PRT2_BYP\r
+.set SCSI_Out_DBx__DB5__CTL, CYREG_PRT2_CTL\r
+.set SCSI_Out_DBx__DB5__DM0, CYREG_PRT2_DM0\r
+.set SCSI_Out_DBx__DB5__DM1, CYREG_PRT2_DM1\r
+.set SCSI_Out_DBx__DB5__DM2, CYREG_PRT2_DM2\r
+.set SCSI_Out_DBx__DB5__DR, CYREG_PRT2_DR\r
+.set SCSI_Out_DBx__DB5__INP_DIS, CYREG_PRT2_INP_DIS\r
+.set SCSI_Out_DBx__DB5__INTTYPE, CYREG_PICU2_INTTYPE6\r
+.set SCSI_Out_DBx__DB5__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG\r
+.set SCSI_Out_DBx__DB5__LCD_EN, CYREG_PRT2_LCD_EN\r
+.set SCSI_Out_DBx__DB5__MASK, 0x40\r
+.set SCSI_Out_DBx__DB5__PC, CYREG_PRT2_PC6\r
+.set SCSI_Out_DBx__DB5__PORT, 2\r
+.set SCSI_Out_DBx__DB5__PRT, CYREG_PRT2_PRT\r
+.set SCSI_Out_DBx__DB5__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL\r
+.set SCSI_Out_DBx__DB5__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN\r
+.set SCSI_Out_DBx__DB5__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0\r
+.set SCSI_Out_DBx__DB5__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1\r
+.set SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0\r
+.set SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1\r
+.set SCSI_Out_DBx__DB5__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT\r
+.set SCSI_Out_DBx__DB5__PS, CYREG_PRT2_PS\r
+.set SCSI_Out_DBx__DB5__SHIFT, 6\r
+.set SCSI_Out_DBx__DB5__SLW, CYREG_PRT2_SLW\r
+.set SCSI_Out_DBx__DB6__AG, CYREG_PRT2_AG\r
+.set SCSI_Out_DBx__DB6__AMUX, CYREG_PRT2_AMUX\r
+.set SCSI_Out_DBx__DB6__BIE, CYREG_PRT2_BIE\r
+.set SCSI_Out_DBx__DB6__BIT_MASK, CYREG_PRT2_BIT_MASK\r
+.set SCSI_Out_DBx__DB6__BYP, CYREG_PRT2_BYP\r
+.set SCSI_Out_DBx__DB6__CTL, CYREG_PRT2_CTL\r
+.set SCSI_Out_DBx__DB6__DM0, CYREG_PRT2_DM0\r
+.set SCSI_Out_DBx__DB6__DM1, CYREG_PRT2_DM1\r
+.set SCSI_Out_DBx__DB6__DM2, CYREG_PRT2_DM2\r
+.set SCSI_Out_DBx__DB6__DR, CYREG_PRT2_DR\r
+.set SCSI_Out_DBx__DB6__INP_DIS, CYREG_PRT2_INP_DIS\r
+.set SCSI_Out_DBx__DB6__INTTYPE, CYREG_PICU2_INTTYPE3\r
+.set SCSI_Out_DBx__DB6__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG\r
+.set SCSI_Out_DBx__DB6__LCD_EN, CYREG_PRT2_LCD_EN\r
+.set SCSI_Out_DBx__DB6__MASK, 0x08\r
+.set SCSI_Out_DBx__DB6__PC, CYREG_PRT2_PC3\r
+.set SCSI_Out_DBx__DB6__PORT, 2\r
+.set SCSI_Out_DBx__DB6__PRT, CYREG_PRT2_PRT\r
+.set SCSI_Out_DBx__DB6__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL\r
+.set SCSI_Out_DBx__DB6__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN\r
+.set SCSI_Out_DBx__DB6__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0\r
+.set SCSI_Out_DBx__DB6__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1\r
+.set SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0\r
+.set SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1\r
+.set SCSI_Out_DBx__DB6__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT\r
+.set SCSI_Out_DBx__DB6__PS, CYREG_PRT2_PS\r
+.set SCSI_Out_DBx__DB6__SHIFT, 3\r
+.set SCSI_Out_DBx__DB6__SLW, CYREG_PRT2_SLW\r
+.set SCSI_Out_DBx__DB7__AG, CYREG_PRT2_AG\r
+.set SCSI_Out_DBx__DB7__AMUX, CYREG_PRT2_AMUX\r
+.set SCSI_Out_DBx__DB7__BIE, CYREG_PRT2_BIE\r
+.set SCSI_Out_DBx__DB7__BIT_MASK, CYREG_PRT2_BIT_MASK\r
+.set SCSI_Out_DBx__DB7__BYP, CYREG_PRT2_BYP\r
+.set SCSI_Out_DBx__DB7__CTL, CYREG_PRT2_CTL\r
+.set SCSI_Out_DBx__DB7__DM0, CYREG_PRT2_DM0\r
+.set SCSI_Out_DBx__DB7__DM1, CYREG_PRT2_DM1\r
+.set SCSI_Out_DBx__DB7__DM2, CYREG_PRT2_DM2\r
+.set SCSI_Out_DBx__DB7__DR, CYREG_PRT2_DR\r
+.set SCSI_Out_DBx__DB7__INP_DIS, CYREG_PRT2_INP_DIS\r
+.set SCSI_Out_DBx__DB7__INTTYPE, CYREG_PICU2_INTTYPE2\r
+.set SCSI_Out_DBx__DB7__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG\r
+.set SCSI_Out_DBx__DB7__LCD_EN, CYREG_PRT2_LCD_EN\r
+.set SCSI_Out_DBx__DB7__MASK, 0x04\r
+.set SCSI_Out_DBx__DB7__PC, CYREG_PRT2_PC2\r
+.set SCSI_Out_DBx__DB7__PORT, 2\r
+.set SCSI_Out_DBx__DB7__PRT, CYREG_PRT2_PRT\r
+.set SCSI_Out_DBx__DB7__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL\r
+.set SCSI_Out_DBx__DB7__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN\r
+.set SCSI_Out_DBx__DB7__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0\r
+.set SCSI_Out_DBx__DB7__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1\r
+.set SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0\r
+.set SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1\r
+.set SCSI_Out_DBx__DB7__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT\r
+.set SCSI_Out_DBx__DB7__PS, CYREG_PRT2_PS\r
+.set SCSI_Out_DBx__DB7__SHIFT, 2\r
+.set SCSI_Out_DBx__DB7__SLW, CYREG_PRT2_SLW\r
+\r
+/* SCSI_Parity_Error */\r
+.set SCSI_Parity_Error_sts_sts_reg__0__MASK, 0x01\r
+.set SCSI_Parity_Error_sts_sts_reg__0__POS, 0\r
+.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB05_06_ACTL\r
+.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB05_06_ST\r
+.set SCSI_Parity_Error_sts_sts_reg__MASK, 0x01\r
+.set SCSI_Parity_Error_sts_sts_reg__MASK_REG, CYREG_B0_UDB05_MSK\r
+.set SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB05_ACTL\r
+.set SCSI_Parity_Error_sts_sts_reg__STATUS_REG, CYREG_B0_UDB05_ST\r
+\r
+/* SCSI_RST_ISR */\r
+.set SCSI_RST_ISR__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
+.set SCSI_RST_ISR__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
+.set SCSI_RST_ISR__INTC_MASK, 0x02\r
+.set SCSI_RST_ISR__INTC_NUMBER, 1\r
+.set SCSI_RST_ISR__INTC_PRIOR_NUM, 7\r
+.set SCSI_RST_ISR__INTC_PRIOR_REG, CYREG_NVIC_PRI_1\r
+.set SCSI_RST_ISR__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
+.set SCSI_RST_ISR__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
+\r
+/* SCSI_RX_DMA */\r
+.set SCSI_RX_DMA__DRQ_CTL, CYREG_IDMUX_DRQ_CTL0\r
+.set SCSI_RX_DMA__DRQ_NUMBER, 0\r
+.set SCSI_RX_DMA__NUMBEROF_TDS, 0\r
+.set SCSI_RX_DMA__PRIORITY, 2\r
+.set SCSI_RX_DMA__TERMIN_EN, 0\r
+.set SCSI_RX_DMA__TERMIN_SEL, 0\r
+.set SCSI_RX_DMA__TERMOUT0_EN, 1\r
+.set SCSI_RX_DMA__TERMOUT0_SEL, 0\r
+.set SCSI_RX_DMA__TERMOUT1_EN, 0\r
+.set SCSI_RX_DMA__TERMOUT1_SEL, 0\r
+.set SCSI_RX_DMA_COMPLETE__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
+.set SCSI_RX_DMA_COMPLETE__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
+.set SCSI_RX_DMA_COMPLETE__INTC_MASK, 0x04\r
+.set SCSI_RX_DMA_COMPLETE__INTC_NUMBER, 2\r
+.set SCSI_RX_DMA_COMPLETE__INTC_PRIOR_NUM, 7\r
+.set SCSI_RX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_2\r
+.set SCSI_RX_DMA_COMPLETE__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
+.set SCSI_RX_DMA_COMPLETE__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
+\r
+/* SCSI_SEL_ISR */\r
+.set SCSI_SEL_ISR__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
+.set SCSI_SEL_ISR__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
+.set SCSI_SEL_ISR__INTC_MASK, 0x08\r
+.set SCSI_SEL_ISR__INTC_NUMBER, 3\r
+.set SCSI_SEL_ISR__INTC_PRIOR_NUM, 7\r
+.set SCSI_SEL_ISR__INTC_PRIOR_REG, CYREG_NVIC_PRI_3\r
+.set SCSI_SEL_ISR__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
+.set SCSI_SEL_ISR__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
+\r
+/* SCSI_TX_DMA */\r
+.set SCSI_TX_DMA__DRQ_CTL, CYREG_IDMUX_DRQ_CTL0\r
+.set SCSI_TX_DMA__DRQ_NUMBER, 1\r
+.set SCSI_TX_DMA__NUMBEROF_TDS, 0\r
+.set SCSI_TX_DMA__PRIORITY, 2\r
+.set SCSI_TX_DMA__TERMIN_EN, 0\r
+.set SCSI_TX_DMA__TERMIN_SEL, 0\r
+.set SCSI_TX_DMA__TERMOUT0_EN, 1\r
+.set SCSI_TX_DMA__TERMOUT0_SEL, 1\r
+.set SCSI_TX_DMA__TERMOUT1_EN, 0\r
+.set SCSI_TX_DMA__TERMOUT1_SEL, 0\r
+.set SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
+.set SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
+.set SCSI_TX_DMA_COMPLETE__INTC_MASK, 0x10\r
+.set SCSI_TX_DMA_COMPLETE__INTC_NUMBER, 4\r
+.set SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM, 7\r
+.set SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_4\r
+.set SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
+.set SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
+\r
+/* SDCard_BSPIM */\r
+.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB05_06_ACTL\r
+.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB05_06_CTL\r
+.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB05_06_CTL\r
+.set SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB05_06_CTL\r
+.set SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB05_06_CTL\r
+.set SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B1_UDB05_06_MSK\r
+.set SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB05_06_MSK\r
+.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB05_06_MSK\r
+.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB05_06_MSK\r
+.set SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B1_UDB05_ACTL\r
+.set SDCard_BSPIM_BitCounter__CONTROL_REG, CYREG_B1_UDB05_CTL\r
+.set SDCard_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B1_UDB05_ST_CTL\r
+.set SDCard_BSPIM_BitCounter__COUNT_REG, CYREG_B1_UDB05_CTL\r
+.set SDCard_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B1_UDB05_ST_CTL\r
+.set SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB05_MSK_ACTL\r
+.set SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB05_MSK_ACTL\r
+.set SDCard_BSPIM_BitCounter__PERIOD_REG, CYREG_B1_UDB05_MSK\r
+.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB05_06_ACTL\r
+.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B1_UDB05_06_ST\r
+.set SDCard_BSPIM_BitCounter_ST__MASK_REG, CYREG_B1_UDB05_MSK\r
+.set SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B1_UDB05_MSK_ACTL\r
+.set SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B1_UDB05_MSK_ACTL\r
+.set SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B1_UDB05_ACTL\r
+.set SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B1_UDB05_ST_CTL\r
+.set SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B1_UDB05_ST_CTL\r
+.set SDCard_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B1_UDB05_ST\r
+.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB07_08_ACTL\r
+.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB07_08_ST\r
+.set SDCard_BSPIM_RxStsReg__4__MASK, 0x10\r
+.set SDCard_BSPIM_RxStsReg__4__POS, 4\r
+.set SDCard_BSPIM_RxStsReg__5__MASK, 0x20\r
+.set SDCard_BSPIM_RxStsReg__5__POS, 5\r
+.set SDCard_BSPIM_RxStsReg__6__MASK, 0x40\r
+.set SDCard_BSPIM_RxStsReg__6__POS, 6\r
+.set SDCard_BSPIM_RxStsReg__MASK, 0x70\r
+.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B1_UDB07_MSK\r
+.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB07_ACTL\r
+.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B1_UDB07_ST\r
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG, CYREG_B1_UDB04_05_A0\r
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG, CYREG_B1_UDB04_05_A1\r
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG, CYREG_B1_UDB04_05_D0\r
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG, CYREG_B1_UDB04_05_D1\r
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG, CYREG_B1_UDB04_05_ACTL\r
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG, CYREG_B1_UDB04_05_F0\r
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG, CYREG_B1_UDB04_05_F1\r
+.set SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG, CYREG_B1_UDB04_A0_A1\r
+.set SDCard_BSPIM_sR8_Dp_u0__A0_REG, CYREG_B1_UDB04_A0\r
+.set SDCard_BSPIM_sR8_Dp_u0__A1_REG, CYREG_B1_UDB04_A1\r
+.set SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG, CYREG_B1_UDB04_D0_D1\r
+.set SDCard_BSPIM_sR8_Dp_u0__D0_REG, CYREG_B1_UDB04_D0\r
+.set SDCard_BSPIM_sR8_Dp_u0__D1_REG, CYREG_B1_UDB04_D1\r
+.set SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG, CYREG_B1_UDB04_ACTL\r
+.set SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG, CYREG_B1_UDB04_F0_F1\r
+.set SDCard_BSPIM_sR8_Dp_u0__F0_REG, CYREG_B1_UDB04_F0\r
+.set SDCard_BSPIM_sR8_Dp_u0__F1_REG, CYREG_B1_UDB04_F1\r
+.set SDCard_BSPIM_TxStsReg__0__MASK, 0x01\r
+.set SDCard_BSPIM_TxStsReg__0__POS, 0\r
+.set SDCard_BSPIM_TxStsReg__1__MASK, 0x02\r
+.set SDCard_BSPIM_TxStsReg__1__POS, 1\r
+.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB06_07_ACTL\r
+.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB06_07_ST\r
+.set SDCard_BSPIM_TxStsReg__2__MASK, 0x04\r
+.set SDCard_BSPIM_TxStsReg__2__POS, 2\r
+.set SDCard_BSPIM_TxStsReg__3__MASK, 0x08\r
+.set SDCard_BSPIM_TxStsReg__3__POS, 3\r
+.set SDCard_BSPIM_TxStsReg__4__MASK, 0x10\r
+.set SDCard_BSPIM_TxStsReg__4__POS, 4\r
+.set SDCard_BSPIM_TxStsReg__MASK, 0x1F\r
+.set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B1_UDB06_MSK\r
+.set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB06_ACTL\r
+.set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B1_UDB06_ST\r
+\r
+/* SD_CD */\r
+.set SD_CD__0__INTTYPE, CYREG_PICU3_INTTYPE5\r
+.set SD_CD__0__MASK, 0x20\r
+.set SD_CD__0__PC, CYREG_PRT3_PC5\r
+.set SD_CD__0__PORT, 3\r
+.set SD_CD__0__SHIFT, 5\r
+.set SD_CD__AG, CYREG_PRT3_AG\r
+.set SD_CD__AMUX, CYREG_PRT3_AMUX\r
+.set SD_CD__BIE, CYREG_PRT3_BIE\r
+.set SD_CD__BIT_MASK, CYREG_PRT3_BIT_MASK\r
+.set SD_CD__BYP, CYREG_PRT3_BYP\r
+.set SD_CD__CTL, CYREG_PRT3_CTL\r
+.set SD_CD__DM0, CYREG_PRT3_DM0\r
+.set SD_CD__DM1, CYREG_PRT3_DM1\r
+.set SD_CD__DM2, CYREG_PRT3_DM2\r
+.set SD_CD__DR, CYREG_PRT3_DR\r
+.set SD_CD__INP_DIS, CYREG_PRT3_INP_DIS\r
+.set SD_CD__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU3_BASE\r
+.set SD_CD__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG\r
+.set SD_CD__LCD_EN, CYREG_PRT3_LCD_EN\r
+.set SD_CD__MASK, 0x20\r
+.set SD_CD__PORT, 3\r
+.set SD_CD__PRT, CYREG_PRT3_PRT\r
+.set SD_CD__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL\r
+.set SD_CD__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN\r
+.set SD_CD__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0\r
+.set SD_CD__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1\r
+.set SD_CD__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0\r
+.set SD_CD__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1\r
+.set SD_CD__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT\r
+.set SD_CD__PS, CYREG_PRT3_PS\r
+.set SD_CD__SHIFT, 5\r
+.set SD_CD__SLW, CYREG_PRT3_SLW\r
+\r
+/* SD_CS */\r
+.set SD_CS__0__INTTYPE, CYREG_PICU3_INTTYPE4\r
+.set SD_CS__0__MASK, 0x10\r
+.set SD_CS__0__PC, CYREG_PRT3_PC4\r
+.set SD_CS__0__PORT, 3\r
+.set SD_CS__0__SHIFT, 4\r
+.set SD_CS__AG, CYREG_PRT3_AG\r
+.set SD_CS__AMUX, CYREG_PRT3_AMUX\r
+.set SD_CS__BIE, CYREG_PRT3_BIE\r
+.set SD_CS__BIT_MASK, CYREG_PRT3_BIT_MASK\r
+.set SD_CS__BYP, CYREG_PRT3_BYP\r
+.set SD_CS__CTL, CYREG_PRT3_CTL\r
+.set SD_CS__DM0, CYREG_PRT3_DM0\r
+.set SD_CS__DM1, CYREG_PRT3_DM1\r
+.set SD_CS__DM2, CYREG_PRT3_DM2\r
+.set SD_CS__DR, CYREG_PRT3_DR\r
+.set SD_CS__INP_DIS, CYREG_PRT3_INP_DIS\r
+.set SD_CS__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU3_BASE\r
+.set SD_CS__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG\r
+.set SD_CS__LCD_EN, CYREG_PRT3_LCD_EN\r
+.set SD_CS__MASK, 0x10\r
+.set SD_CS__PORT, 3\r
+.set SD_CS__PRT, CYREG_PRT3_PRT\r
+.set SD_CS__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL\r
+.set SD_CS__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN\r
+.set SD_CS__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0\r
+.set SD_CS__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1\r
+.set SD_CS__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0\r
+.set SD_CS__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1\r
+.set SD_CS__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT\r
+.set SD_CS__PS, CYREG_PRT3_PS\r
+.set SD_CS__SHIFT, 4\r
+.set SD_CS__SLW, CYREG_PRT3_SLW\r
+\r
+/* SD_Data_Clk */\r
+.set SD_Data_Clk__CFG0, CYREG_CLKDIST_DCFG0_CFG0\r
+.set SD_Data_Clk__CFG1, CYREG_CLKDIST_DCFG0_CFG1\r
+.set SD_Data_Clk__CFG2, CYREG_CLKDIST_DCFG0_CFG2\r
+.set SD_Data_Clk__CFG2_SRC_SEL_MASK, 0x07\r
+.set SD_Data_Clk__INDEX, 0x00\r
+.set SD_Data_Clk__PM_ACT_CFG, CYREG_PM_ACT_CFG2\r
+.set SD_Data_Clk__PM_ACT_MSK, 0x01\r
+.set SD_Data_Clk__PM_STBY_CFG, CYREG_PM_STBY_CFG2\r
+.set SD_Data_Clk__PM_STBY_MSK, 0x01\r
+\r
+/* SD_MISO */\r
+.set SD_MISO__0__INTTYPE, CYREG_PICU3_INTTYPE1\r
+.set SD_MISO__0__MASK, 0x02\r
+.set SD_MISO__0__PC, CYREG_PRT3_PC1\r
+.set SD_MISO__0__PORT, 3\r
+.set SD_MISO__0__SHIFT, 1\r
+.set SD_MISO__AG, CYREG_PRT3_AG\r
+.set SD_MISO__AMUX, CYREG_PRT3_AMUX\r
+.set SD_MISO__BIE, CYREG_PRT3_BIE\r
+.set SD_MISO__BIT_MASK, CYREG_PRT3_BIT_MASK\r
+.set SD_MISO__BYP, CYREG_PRT3_BYP\r
+.set SD_MISO__CTL, CYREG_PRT3_CTL\r
+.set SD_MISO__DM0, CYREG_PRT3_DM0\r
+.set SD_MISO__DM1, CYREG_PRT3_DM1\r
+.set SD_MISO__DM2, CYREG_PRT3_DM2\r
+.set SD_MISO__DR, CYREG_PRT3_DR\r
+.set SD_MISO__INP_DIS, CYREG_PRT3_INP_DIS\r
+.set SD_MISO__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU3_BASE\r
+.set SD_MISO__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG\r
+.set SD_MISO__LCD_EN, CYREG_PRT3_LCD_EN\r
+.set SD_MISO__MASK, 0x02\r
+.set SD_MISO__PORT, 3\r
+.set SD_MISO__PRT, CYREG_PRT3_PRT\r
+.set SD_MISO__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL\r
+.set SD_MISO__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN\r
+.set SD_MISO__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0\r
+.set SD_MISO__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1\r
+.set SD_MISO__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0\r
+.set SD_MISO__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1\r
+.set SD_MISO__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT\r
+.set SD_MISO__PS, CYREG_PRT3_PS\r
+.set SD_MISO__SHIFT, 1\r
+.set SD_MISO__SLW, CYREG_PRT3_SLW\r
+\r
+/* SD_MOSI */\r
+.set SD_MOSI__0__INTTYPE, CYREG_PICU3_INTTYPE3\r
+.set SD_MOSI__0__MASK, 0x08\r
+.set SD_MOSI__0__PC, CYREG_PRT3_PC3\r
+.set SD_MOSI__0__PORT, 3\r
+.set SD_MOSI__0__SHIFT, 3\r
+.set SD_MOSI__AG, CYREG_PRT3_AG\r
+.set SD_MOSI__AMUX, CYREG_PRT3_AMUX\r
+.set SD_MOSI__BIE, CYREG_PRT3_BIE\r
+.set SD_MOSI__BIT_MASK, CYREG_PRT3_BIT_MASK\r
+.set SD_MOSI__BYP, CYREG_PRT3_BYP\r
+.set SD_MOSI__CTL, CYREG_PRT3_CTL\r
+.set SD_MOSI__DM0, CYREG_PRT3_DM0\r
+.set SD_MOSI__DM1, CYREG_PRT3_DM1\r
+.set SD_MOSI__DM2, CYREG_PRT3_DM2\r
+.set SD_MOSI__DR, CYREG_PRT3_DR\r
+.set SD_MOSI__INP_DIS, CYREG_PRT3_INP_DIS\r
+.set SD_MOSI__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU3_BASE\r
+.set SD_MOSI__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG\r
+.set SD_MOSI__LCD_EN, CYREG_PRT3_LCD_EN\r
+.set SD_MOSI__MASK, 0x08\r
+.set SD_MOSI__PORT, 3\r
+.set SD_MOSI__PRT, CYREG_PRT3_PRT\r
+.set SD_MOSI__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL\r
+.set SD_MOSI__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN\r
+.set SD_MOSI__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0\r
+.set SD_MOSI__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1\r
+.set SD_MOSI__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0\r
+.set SD_MOSI__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1\r
+.set SD_MOSI__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT\r
+.set SD_MOSI__PS, CYREG_PRT3_PS\r
+.set SD_MOSI__SHIFT, 3\r
+.set SD_MOSI__SLW, CYREG_PRT3_SLW\r
+\r
+/* SD_RX_DMA */\r
+.set SD_RX_DMA__DRQ_CTL, CYREG_IDMUX_DRQ_CTL0\r
+.set SD_RX_DMA__DRQ_NUMBER, 2\r
+.set SD_RX_DMA__NUMBEROF_TDS, 0\r
+.set SD_RX_DMA__PRIORITY, 0\r
+.set SD_RX_DMA__TERMIN_EN, 0\r
+.set SD_RX_DMA__TERMIN_SEL, 0\r
+.set SD_RX_DMA__TERMOUT0_EN, 1\r
+.set SD_RX_DMA__TERMOUT0_SEL, 2\r
+.set SD_RX_DMA__TERMOUT1_EN, 0\r
+.set SD_RX_DMA__TERMOUT1_SEL, 0\r
+.set SD_RX_DMA_COMPLETE__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
+.set SD_RX_DMA_COMPLETE__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
+.set SD_RX_DMA_COMPLETE__INTC_MASK, 0x20\r
+.set SD_RX_DMA_COMPLETE__INTC_NUMBER, 5\r
+.set SD_RX_DMA_COMPLETE__INTC_PRIOR_NUM, 7\r
+.set SD_RX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_5\r
+.set SD_RX_DMA_COMPLETE__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
+.set SD_RX_DMA_COMPLETE__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
+\r
+/* SD_SCK */\r
+.set SD_SCK__0__INTTYPE, CYREG_PICU3_INTTYPE2\r
+.set SD_SCK__0__MASK, 0x04\r
+.set SD_SCK__0__PC, CYREG_PRT3_PC2\r
+.set SD_SCK__0__PORT, 3\r
+.set SD_SCK__0__SHIFT, 2\r
+.set SD_SCK__AG, CYREG_PRT3_AG\r
+.set SD_SCK__AMUX, CYREG_PRT3_AMUX\r
+.set SD_SCK__BIE, CYREG_PRT3_BIE\r
+.set SD_SCK__BIT_MASK, CYREG_PRT3_BIT_MASK\r
+.set SD_SCK__BYP, CYREG_PRT3_BYP\r
+.set SD_SCK__CTL, CYREG_PRT3_CTL\r
+.set SD_SCK__DM0, CYREG_PRT3_DM0\r
+.set SD_SCK__DM1, CYREG_PRT3_DM1\r
+.set SD_SCK__DM2, CYREG_PRT3_DM2\r
+.set SD_SCK__DR, CYREG_PRT3_DR\r
+.set SD_SCK__INP_DIS, CYREG_PRT3_INP_DIS\r
+.set SD_SCK__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU3_BASE\r
+.set SD_SCK__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG\r
+.set SD_SCK__LCD_EN, CYREG_PRT3_LCD_EN\r
+.set SD_SCK__MASK, 0x04\r
+.set SD_SCK__PORT, 3\r
+.set SD_SCK__PRT, CYREG_PRT3_PRT\r
+.set SD_SCK__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL\r
+.set SD_SCK__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN\r
+.set SD_SCK__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0\r
+.set SD_SCK__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1\r
+.set SD_SCK__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0\r
+.set SD_SCK__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1\r
+.set SD_SCK__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT\r
+.set SD_SCK__PS, CYREG_PRT3_PS\r
+.set SD_SCK__SHIFT, 2\r
+.set SD_SCK__SLW, CYREG_PRT3_SLW\r
+\r
+/* SD_TX_DMA */\r
+.set SD_TX_DMA__DRQ_CTL, CYREG_IDMUX_DRQ_CTL0\r
+.set SD_TX_DMA__DRQ_NUMBER, 3\r
+.set SD_TX_DMA__NUMBEROF_TDS, 0\r
+.set SD_TX_DMA__PRIORITY, 1\r
+.set SD_TX_DMA__TERMIN_EN, 0\r
+.set SD_TX_DMA__TERMIN_SEL, 0\r
+.set SD_TX_DMA__TERMOUT0_EN, 1\r
+.set SD_TX_DMA__TERMOUT0_SEL, 3\r
+.set SD_TX_DMA__TERMOUT1_EN, 0\r
+.set SD_TX_DMA__TERMOUT1_SEL, 0\r
+.set SD_TX_DMA_COMPLETE__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
+.set SD_TX_DMA_COMPLETE__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
+.set SD_TX_DMA_COMPLETE__INTC_MASK, 0x40\r
+.set SD_TX_DMA_COMPLETE__INTC_NUMBER, 6\r
+.set SD_TX_DMA_COMPLETE__INTC_PRIOR_NUM, 7\r
+.set SD_TX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_6\r
+.set SD_TX_DMA_COMPLETE__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
+.set SD_TX_DMA_COMPLETE__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
+\r
+/* USBFS */\r
+.set USBFS_arb_int__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
+.set USBFS_arb_int__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
+.set USBFS_arb_int__INTC_MASK, 0x400000\r
+.set USBFS_arb_int__INTC_NUMBER, 22\r
+.set USBFS_arb_int__INTC_PRIOR_NUM, 6\r
+.set USBFS_arb_int__INTC_PRIOR_REG, CYREG_NVIC_PRI_22\r
+.set USBFS_arb_int__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
+.set USBFS_arb_int__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
+.set USBFS_bus_reset__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
+.set USBFS_bus_reset__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
+.set USBFS_bus_reset__INTC_MASK, 0x800000\r
+.set USBFS_bus_reset__INTC_NUMBER, 23\r
+.set USBFS_bus_reset__INTC_PRIOR_NUM, 7\r
+.set USBFS_bus_reset__INTC_PRIOR_REG, CYREG_NVIC_PRI_23\r
+.set USBFS_bus_reset__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
+.set USBFS_bus_reset__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
+.set USBFS_Dm__0__INTTYPE, CYREG_PICU15_INTTYPE7\r
+.set USBFS_Dm__0__MASK, 0x80\r
+.set USBFS_Dm__0__PC, CYREG_IO_PC_PRT15_7_6_PC1\r
+.set USBFS_Dm__0__PORT, 15\r
+.set USBFS_Dm__0__SHIFT, 7\r
+.set USBFS_Dm__AG, CYREG_PRT15_AG\r
+.set USBFS_Dm__AMUX, CYREG_PRT15_AMUX\r
+.set USBFS_Dm__BIE, CYREG_PRT15_BIE\r
+.set USBFS_Dm__BIT_MASK, CYREG_PRT15_BIT_MASK\r
+.set USBFS_Dm__BYP, CYREG_PRT15_BYP\r
+.set USBFS_Dm__CTL, CYREG_PRT15_CTL\r
+.set USBFS_Dm__DM0, CYREG_PRT15_DM0\r
+.set USBFS_Dm__DM1, CYREG_PRT15_DM1\r
+.set USBFS_Dm__DM2, CYREG_PRT15_DM2\r
+.set USBFS_Dm__DR, CYREG_PRT15_DR\r
+.set USBFS_Dm__INP_DIS, CYREG_PRT15_INP_DIS\r
+.set USBFS_Dm__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU15_BASE\r
+.set USBFS_Dm__LCD_COM_SEG, CYREG_PRT15_LCD_COM_SEG\r
+.set USBFS_Dm__LCD_EN, CYREG_PRT15_LCD_EN\r
+.set USBFS_Dm__MASK, 0x80\r
+.set USBFS_Dm__PORT, 15\r
+.set USBFS_Dm__PRT, CYREG_PRT15_PRT\r
+.set USBFS_Dm__PRTDSI__CAPS_SEL, CYREG_PRT15_CAPS_SEL\r
+.set USBFS_Dm__PRTDSI__DBL_SYNC_IN, CYREG_PRT15_DBL_SYNC_IN\r
+.set USBFS_Dm__PRTDSI__OE_SEL0, CYREG_PRT15_OE_SEL0\r
+.set USBFS_Dm__PRTDSI__OE_SEL1, CYREG_PRT15_OE_SEL1\r
+.set USBFS_Dm__PRTDSI__OUT_SEL0, CYREG_PRT15_OUT_SEL0\r
+.set USBFS_Dm__PRTDSI__OUT_SEL1, CYREG_PRT15_OUT_SEL1\r
+.set USBFS_Dm__PRTDSI__SYNC_OUT, CYREG_PRT15_SYNC_OUT\r
+.set USBFS_Dm__PS, CYREG_PRT15_PS\r
+.set USBFS_Dm__SHIFT, 7\r
+.set USBFS_Dm__SLW, CYREG_PRT15_SLW\r
+.set USBFS_Dp__0__INTTYPE, CYREG_PICU15_INTTYPE6\r
+.set USBFS_Dp__0__MASK, 0x40\r
+.set USBFS_Dp__0__PC, CYREG_IO_PC_PRT15_7_6_PC0\r
+.set USBFS_Dp__0__PORT, 15\r
+.set USBFS_Dp__0__SHIFT, 6\r
+.set USBFS_Dp__AG, CYREG_PRT15_AG\r
+.set USBFS_Dp__AMUX, CYREG_PRT15_AMUX\r
+.set USBFS_Dp__BIE, CYREG_PRT15_BIE\r
+.set USBFS_Dp__BIT_MASK, CYREG_PRT15_BIT_MASK\r
+.set USBFS_Dp__BYP, CYREG_PRT15_BYP\r
+.set USBFS_Dp__CTL, CYREG_PRT15_CTL\r
+.set USBFS_Dp__DM0, CYREG_PRT15_DM0\r
+.set USBFS_Dp__DM1, CYREG_PRT15_DM1\r
+.set USBFS_Dp__DM2, CYREG_PRT15_DM2\r
+.set USBFS_Dp__DR, CYREG_PRT15_DR\r
+.set USBFS_Dp__INP_DIS, CYREG_PRT15_INP_DIS\r
+.set USBFS_Dp__INTSTAT, CYREG_PICU15_INTSTAT\r
+.set USBFS_Dp__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU15_BASE\r
+.set USBFS_Dp__LCD_COM_SEG, CYREG_PRT15_LCD_COM_SEG\r
+.set USBFS_Dp__LCD_EN, CYREG_PRT15_LCD_EN\r
+.set USBFS_Dp__MASK, 0x40\r
+.set USBFS_Dp__PORT, 15\r
+.set USBFS_Dp__PRT, CYREG_PRT15_PRT\r
+.set USBFS_Dp__PRTDSI__CAPS_SEL, CYREG_PRT15_CAPS_SEL\r
+.set USBFS_Dp__PRTDSI__DBL_SYNC_IN, CYREG_PRT15_DBL_SYNC_IN\r
+.set USBFS_Dp__PRTDSI__OE_SEL0, CYREG_PRT15_OE_SEL0\r
+.set USBFS_Dp__PRTDSI__OE_SEL1, CYREG_PRT15_OE_SEL1\r
+.set USBFS_Dp__PRTDSI__OUT_SEL0, CYREG_PRT15_OUT_SEL0\r
+.set USBFS_Dp__PRTDSI__OUT_SEL1, CYREG_PRT15_OUT_SEL1\r
+.set USBFS_Dp__PRTDSI__SYNC_OUT, CYREG_PRT15_SYNC_OUT\r
+.set USBFS_Dp__PS, CYREG_PRT15_PS\r
+.set USBFS_Dp__SHIFT, 6\r
+.set USBFS_Dp__SLW, CYREG_PRT15_SLW\r
+.set USBFS_Dp__SNAP, CYREG_PICU_15_SNAP_15\r
+.set USBFS_dp_int__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
+.set USBFS_dp_int__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
+.set USBFS_dp_int__INTC_MASK, 0x1000\r
+.set USBFS_dp_int__INTC_NUMBER, 12\r
+.set USBFS_dp_int__INTC_PRIOR_NUM, 7\r
+.set USBFS_dp_int__INTC_PRIOR_REG, CYREG_NVIC_PRI_12\r
+.set USBFS_dp_int__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
+.set USBFS_dp_int__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
+.set USBFS_ep_0__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
+.set USBFS_ep_0__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
+.set USBFS_ep_0__INTC_MASK, 0x1000000\r
+.set USBFS_ep_0__INTC_NUMBER, 24\r
+.set USBFS_ep_0__INTC_PRIOR_NUM, 7\r
+.set USBFS_ep_0__INTC_PRIOR_REG, CYREG_NVIC_PRI_24\r
+.set USBFS_ep_0__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
+.set USBFS_ep_0__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
+.set USBFS_ep_1__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
+.set USBFS_ep_1__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
+.set USBFS_ep_1__INTC_MASK, 0x80\r
+.set USBFS_ep_1__INTC_NUMBER, 7\r
+.set USBFS_ep_1__INTC_PRIOR_NUM, 7\r
+.set USBFS_ep_1__INTC_PRIOR_REG, CYREG_NVIC_PRI_7\r
+.set USBFS_ep_1__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
+.set USBFS_ep_1__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
+.set USBFS_ep_2__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
+.set USBFS_ep_2__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
+.set USBFS_ep_2__INTC_MASK, 0x100\r
+.set USBFS_ep_2__INTC_NUMBER, 8\r
+.set USBFS_ep_2__INTC_PRIOR_NUM, 7\r
+.set USBFS_ep_2__INTC_PRIOR_REG, CYREG_NVIC_PRI_8\r
+.set USBFS_ep_2__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
+.set USBFS_ep_2__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
+.set USBFS_ep_3__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
+.set USBFS_ep_3__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
+.set USBFS_ep_3__INTC_MASK, 0x200\r
+.set USBFS_ep_3__INTC_NUMBER, 9\r
+.set USBFS_ep_3__INTC_PRIOR_NUM, 7\r
+.set USBFS_ep_3__INTC_PRIOR_REG, CYREG_NVIC_PRI_9\r
+.set USBFS_ep_3__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
+.set USBFS_ep_3__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
+.set USBFS_ep_4__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
+.set USBFS_ep_4__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
+.set USBFS_ep_4__INTC_MASK, 0x400\r
+.set USBFS_ep_4__INTC_NUMBER, 10\r
+.set USBFS_ep_4__INTC_PRIOR_NUM, 7\r
+.set USBFS_ep_4__INTC_PRIOR_REG, CYREG_NVIC_PRI_10\r
+.set USBFS_ep_4__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
+.set USBFS_ep_4__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
+.set USBFS_sof_int__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
+.set USBFS_sof_int__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
+.set USBFS_sof_int__INTC_MASK, 0x200000\r
+.set USBFS_sof_int__INTC_NUMBER, 21\r
+.set USBFS_sof_int__INTC_PRIOR_NUM, 7\r
+.set USBFS_sof_int__INTC_PRIOR_REG, CYREG_NVIC_PRI_21\r
+.set USBFS_sof_int__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
+.set USBFS_sof_int__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
+.set USBFS_USB__ARB_CFG, CYREG_USB_ARB_CFG\r
+.set USBFS_USB__ARB_EP1_CFG, CYREG_USB_ARB_EP1_CFG\r
+.set USBFS_USB__ARB_EP1_INT_EN, CYREG_USB_ARB_EP1_INT_EN\r
+.set USBFS_USB__ARB_EP1_SR, CYREG_USB_ARB_EP1_SR\r
+.set USBFS_USB__ARB_EP2_CFG, CYREG_USB_ARB_EP2_CFG\r
+.set USBFS_USB__ARB_EP2_INT_EN, CYREG_USB_ARB_EP2_INT_EN\r
+.set USBFS_USB__ARB_EP2_SR, CYREG_USB_ARB_EP2_SR\r
+.set USBFS_USB__ARB_EP3_CFG, CYREG_USB_ARB_EP3_CFG\r
+.set USBFS_USB__ARB_EP3_INT_EN, CYREG_USB_ARB_EP3_INT_EN\r
+.set USBFS_USB__ARB_EP3_SR, CYREG_USB_ARB_EP3_SR\r
+.set USBFS_USB__ARB_EP4_CFG, CYREG_USB_ARB_EP4_CFG\r
+.set USBFS_USB__ARB_EP4_INT_EN, CYREG_USB_ARB_EP4_INT_EN\r
+.set USBFS_USB__ARB_EP4_SR, CYREG_USB_ARB_EP4_SR\r
+.set USBFS_USB__ARB_EP5_CFG, CYREG_USB_ARB_EP5_CFG\r
+.set USBFS_USB__ARB_EP5_INT_EN, CYREG_USB_ARB_EP5_INT_EN\r
+.set USBFS_USB__ARB_EP5_SR, CYREG_USB_ARB_EP5_SR\r
+.set USBFS_USB__ARB_EP6_CFG, CYREG_USB_ARB_EP6_CFG\r
+.set USBFS_USB__ARB_EP6_INT_EN, CYREG_USB_ARB_EP6_INT_EN\r
+.set USBFS_USB__ARB_EP6_SR, CYREG_USB_ARB_EP6_SR\r
+.set USBFS_USB__ARB_EP7_CFG, CYREG_USB_ARB_EP7_CFG\r
+.set USBFS_USB__ARB_EP7_INT_EN, CYREG_USB_ARB_EP7_INT_EN\r
+.set USBFS_USB__ARB_EP7_SR, CYREG_USB_ARB_EP7_SR\r
+.set USBFS_USB__ARB_EP8_CFG, CYREG_USB_ARB_EP8_CFG\r
+.set USBFS_USB__ARB_EP8_INT_EN, CYREG_USB_ARB_EP8_INT_EN\r
+.set USBFS_USB__ARB_EP8_SR, CYREG_USB_ARB_EP8_SR\r
+.set USBFS_USB__ARB_INT_EN, CYREG_USB_ARB_INT_EN\r
+.set USBFS_USB__ARB_INT_SR, CYREG_USB_ARB_INT_SR\r
+.set USBFS_USB__ARB_RW1_DR, CYREG_USB_ARB_RW1_DR\r
+.set USBFS_USB__ARB_RW1_RA, CYREG_USB_ARB_RW1_RA\r
+.set USBFS_USB__ARB_RW1_RA_MSB, CYREG_USB_ARB_RW1_RA_MSB\r
+.set USBFS_USB__ARB_RW1_WA, CYREG_USB_ARB_RW1_WA\r
+.set USBFS_USB__ARB_RW1_WA_MSB, CYREG_USB_ARB_RW1_WA_MSB\r
+.set USBFS_USB__ARB_RW2_DR, CYREG_USB_ARB_RW2_DR\r
+.set USBFS_USB__ARB_RW2_RA, CYREG_USB_ARB_RW2_RA\r
+.set USBFS_USB__ARB_RW2_RA_MSB, CYREG_USB_ARB_RW2_RA_MSB\r
+.set USBFS_USB__ARB_RW2_WA, CYREG_USB_ARB_RW2_WA\r
+.set USBFS_USB__ARB_RW2_WA_MSB, CYREG_USB_ARB_RW2_WA_MSB\r
+.set USBFS_USB__ARB_RW3_DR, CYREG_USB_ARB_RW3_DR\r
+.set USBFS_USB__ARB_RW3_RA, CYREG_USB_ARB_RW3_RA\r
+.set USBFS_USB__ARB_RW3_RA_MSB, CYREG_USB_ARB_RW3_RA_MSB\r
+.set USBFS_USB__ARB_RW3_WA, CYREG_USB_ARB_RW3_WA\r
+.set USBFS_USB__ARB_RW3_WA_MSB, CYREG_USB_ARB_RW3_WA_MSB\r
+.set USBFS_USB__ARB_RW4_DR, CYREG_USB_ARB_RW4_DR\r
+.set USBFS_USB__ARB_RW4_RA, CYREG_USB_ARB_RW4_RA\r
+.set USBFS_USB__ARB_RW4_RA_MSB, CYREG_USB_ARB_RW4_RA_MSB\r
+.set USBFS_USB__ARB_RW4_WA, CYREG_USB_ARB_RW4_WA\r
+.set USBFS_USB__ARB_RW4_WA_MSB, CYREG_USB_ARB_RW4_WA_MSB\r
+.set USBFS_USB__ARB_RW5_DR, CYREG_USB_ARB_RW5_DR\r
+.set USBFS_USB__ARB_RW5_RA, CYREG_USB_ARB_RW5_RA\r
+.set USBFS_USB__ARB_RW5_RA_MSB, CYREG_USB_ARB_RW5_RA_MSB\r
+.set USBFS_USB__ARB_RW5_WA, CYREG_USB_ARB_RW5_WA\r
+.set USBFS_USB__ARB_RW5_WA_MSB, CYREG_USB_ARB_RW5_WA_MSB\r
+.set USBFS_USB__ARB_RW6_DR, CYREG_USB_ARB_RW6_DR\r
+.set USBFS_USB__ARB_RW6_RA, CYREG_USB_ARB_RW6_RA\r
+.set USBFS_USB__ARB_RW6_RA_MSB, CYREG_USB_ARB_RW6_RA_MSB\r
+.set USBFS_USB__ARB_RW6_WA, CYREG_USB_ARB_RW6_WA\r
+.set USBFS_USB__ARB_RW6_WA_MSB, CYREG_USB_ARB_RW6_WA_MSB\r
+.set USBFS_USB__ARB_RW7_DR, CYREG_USB_ARB_RW7_DR\r
+.set USBFS_USB__ARB_RW7_RA, CYREG_USB_ARB_RW7_RA\r
+.set USBFS_USB__ARB_RW7_RA_MSB, CYREG_USB_ARB_RW7_RA_MSB\r
+.set USBFS_USB__ARB_RW7_WA, CYREG_USB_ARB_RW7_WA\r
+.set USBFS_USB__ARB_RW7_WA_MSB, CYREG_USB_ARB_RW7_WA_MSB\r
+.set USBFS_USB__ARB_RW8_DR, CYREG_USB_ARB_RW8_DR\r
+.set USBFS_USB__ARB_RW8_RA, CYREG_USB_ARB_RW8_RA\r
+.set USBFS_USB__ARB_RW8_RA_MSB, CYREG_USB_ARB_RW8_RA_MSB\r
+.set USBFS_USB__ARB_RW8_WA, CYREG_USB_ARB_RW8_WA\r
+.set USBFS_USB__ARB_RW8_WA_MSB, CYREG_USB_ARB_RW8_WA_MSB\r
+.set USBFS_USB__BUF_SIZE, CYREG_USB_BUF_SIZE\r
+.set USBFS_USB__BUS_RST_CNT, CYREG_USB_BUS_RST_CNT\r
+.set USBFS_USB__CR0, CYREG_USB_CR0\r
+.set USBFS_USB__CR1, CYREG_USB_CR1\r
+.set USBFS_USB__CWA, CYREG_USB_CWA\r
+.set USBFS_USB__CWA_MSB, CYREG_USB_CWA_MSB\r
+.set USBFS_USB__DMA_THRES, CYREG_USB_DMA_THRES\r
+.set USBFS_USB__DMA_THRES_MSB, CYREG_USB_DMA_THRES_MSB\r
+.set USBFS_USB__DYN_RECONFIG, CYREG_USB_DYN_RECONFIG\r
+.set USBFS_USB__EP_ACTIVE, CYREG_USB_EP_ACTIVE\r
+.set USBFS_USB__EP_TYPE, CYREG_USB_EP_TYPE\r
+.set USBFS_USB__EP0_CNT, CYREG_USB_EP0_CNT\r
+.set USBFS_USB__EP0_CR, CYREG_USB_EP0_CR\r
+.set USBFS_USB__EP0_DR0, CYREG_USB_EP0_DR0\r
+.set USBFS_USB__EP0_DR1, CYREG_USB_EP0_DR1\r
+.set USBFS_USB__EP0_DR2, CYREG_USB_EP0_DR2\r
+.set USBFS_USB__EP0_DR3, CYREG_USB_EP0_DR3\r
+.set USBFS_USB__EP0_DR4, CYREG_USB_EP0_DR4\r
+.set USBFS_USB__EP0_DR5, CYREG_USB_EP0_DR5\r
+.set USBFS_USB__EP0_DR6, CYREG_USB_EP0_DR6\r
+.set USBFS_USB__EP0_DR7, CYREG_USB_EP0_DR7\r
+.set USBFS_USB__MEM_DATA, CYREG_USB_MEM_DATA_MBASE\r
+.set USBFS_USB__PM_ACT_CFG, CYREG_PM_ACT_CFG5\r
+.set USBFS_USB__PM_ACT_MSK, 0x01\r
+.set USBFS_USB__PM_STBY_CFG, CYREG_PM_STBY_CFG5\r
+.set USBFS_USB__PM_STBY_MSK, 0x01\r
+.set USBFS_USB__SIE_EP_INT_EN, CYREG_USB_SIE_EP_INT_EN\r
+.set USBFS_USB__SIE_EP_INT_SR, CYREG_USB_SIE_EP_INT_SR\r
+.set USBFS_USB__SIE_EP1_CNT0, CYREG_USB_SIE_EP1_CNT0\r
+.set USBFS_USB__SIE_EP1_CNT1, CYREG_USB_SIE_EP1_CNT1\r
+.set USBFS_USB__SIE_EP1_CR0, CYREG_USB_SIE_EP1_CR0\r
+.set USBFS_USB__SIE_EP2_CNT0, CYREG_USB_SIE_EP2_CNT0\r
+.set USBFS_USB__SIE_EP2_CNT1, CYREG_USB_SIE_EP2_CNT1\r
+.set USBFS_USB__SIE_EP2_CR0, CYREG_USB_SIE_EP2_CR0\r
+.set USBFS_USB__SIE_EP3_CNT0, CYREG_USB_SIE_EP3_CNT0\r
+.set USBFS_USB__SIE_EP3_CNT1, CYREG_USB_SIE_EP3_CNT1\r
+.set USBFS_USB__SIE_EP3_CR0, CYREG_USB_SIE_EP3_CR0\r
+.set USBFS_USB__SIE_EP4_CNT0, CYREG_USB_SIE_EP4_CNT0\r
+.set USBFS_USB__SIE_EP4_CNT1, CYREG_USB_SIE_EP4_CNT1\r
+.set USBFS_USB__SIE_EP4_CR0, CYREG_USB_SIE_EP4_CR0\r
+.set USBFS_USB__SIE_EP5_CNT0, CYREG_USB_SIE_EP5_CNT0\r
+.set USBFS_USB__SIE_EP5_CNT1, CYREG_USB_SIE_EP5_CNT1\r
+.set USBFS_USB__SIE_EP5_CR0, CYREG_USB_SIE_EP5_CR0\r
+.set USBFS_USB__SIE_EP6_CNT0, CYREG_USB_SIE_EP6_CNT0\r
+.set USBFS_USB__SIE_EP6_CNT1, CYREG_USB_SIE_EP6_CNT1\r
+.set USBFS_USB__SIE_EP6_CR0, CYREG_USB_SIE_EP6_CR0\r
+.set USBFS_USB__SIE_EP7_CNT0, CYREG_USB_SIE_EP7_CNT0\r
+.set USBFS_USB__SIE_EP7_CNT1, CYREG_USB_SIE_EP7_CNT1\r
+.set USBFS_USB__SIE_EP7_CR0, CYREG_USB_SIE_EP7_CR0\r
+.set USBFS_USB__SIE_EP8_CNT0, CYREG_USB_SIE_EP8_CNT0\r
+.set USBFS_USB__SIE_EP8_CNT1, CYREG_USB_SIE_EP8_CNT1\r
+.set USBFS_USB__SIE_EP8_CR0, CYREG_USB_SIE_EP8_CR0\r
+.set USBFS_USB__SOF0, CYREG_USB_SOF0\r
+.set USBFS_USB__SOF1, CYREG_USB_SOF1\r
+.set USBFS_USB__USB_CLK_EN, CYREG_USB_USB_CLK_EN\r
+.set USBFS_USB__USBIO_CR0, CYREG_USB_USBIO_CR0\r
+.set USBFS_USB__USBIO_CR1, CYREG_USB_USBIO_CR1\r
+\r
 /* scsiTarget */\r
 .set scsiTarget_datapath__16BIT_A0_REG, CYREG_B0_UDB00_01_A0\r
 .set scsiTarget_datapath__16BIT_A1_REG, CYREG_B0_UDB00_01_A1\r
@@ -2798,89 +2955,6 @@
 .set scsiTarget_StatusReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB02_ACTL\r
 .set scsiTarget_StatusReg__STATUS_REG, CYREG_B0_UDB02_ST\r
 \r
-/* Debug_Timer_Interrupt */\r
-.set Debug_Timer_Interrupt__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
-.set Debug_Timer_Interrupt__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
-.set Debug_Timer_Interrupt__INTC_MASK, 0x02\r
-.set Debug_Timer_Interrupt__INTC_NUMBER, 1\r
-.set Debug_Timer_Interrupt__INTC_PRIOR_NUM, 7\r
-.set Debug_Timer_Interrupt__INTC_PRIOR_REG, CYREG_NVIC_PRI_1\r
-.set Debug_Timer_Interrupt__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
-.set Debug_Timer_Interrupt__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
-\r
-/* Debug_Timer_TimerHW */\r
-.set Debug_Timer_TimerHW__CAP0, CYREG_TMR0_CAP0\r
-.set Debug_Timer_TimerHW__CAP1, CYREG_TMR0_CAP1\r
-.set Debug_Timer_TimerHW__CFG0, CYREG_TMR0_CFG0\r
-.set Debug_Timer_TimerHW__CFG1, CYREG_TMR0_CFG1\r
-.set Debug_Timer_TimerHW__CFG2, CYREG_TMR0_CFG2\r
-.set Debug_Timer_TimerHW__CNT_CMP0, CYREG_TMR0_CNT_CMP0\r
-.set Debug_Timer_TimerHW__CNT_CMP1, CYREG_TMR0_CNT_CMP1\r
-.set Debug_Timer_TimerHW__PER0, CYREG_TMR0_PER0\r
-.set Debug_Timer_TimerHW__PER1, CYREG_TMR0_PER1\r
-.set Debug_Timer_TimerHW__PM_ACT_CFG, CYREG_PM_ACT_CFG3\r
-.set Debug_Timer_TimerHW__PM_ACT_MSK, 0x01\r
-.set Debug_Timer_TimerHW__PM_STBY_CFG, CYREG_PM_STBY_CFG3\r
-.set Debug_Timer_TimerHW__PM_STBY_MSK, 0x01\r
-.set Debug_Timer_TimerHW__RT0, CYREG_TMR0_RT0\r
-.set Debug_Timer_TimerHW__RT1, CYREG_TMR0_RT1\r
-.set Debug_Timer_TimerHW__SR0, CYREG_TMR0_SR0\r
-\r
-/* SCSI_RX_DMA */\r
-.set SCSI_RX_DMA__DRQ_CTL, CYREG_IDMUX_DRQ_CTL0\r
-.set SCSI_RX_DMA__DRQ_NUMBER, 0\r
-.set SCSI_RX_DMA__NUMBEROF_TDS, 0\r
-.set SCSI_RX_DMA__PRIORITY, 2\r
-.set SCSI_RX_DMA__TERMIN_EN, 0\r
-.set SCSI_RX_DMA__TERMIN_SEL, 0\r
-.set SCSI_RX_DMA__TERMOUT0_EN, 1\r
-.set SCSI_RX_DMA__TERMOUT0_SEL, 0\r
-.set SCSI_RX_DMA__TERMOUT1_EN, 0\r
-.set SCSI_RX_DMA__TERMOUT1_SEL, 0\r
-\r
-/* SCSI_RX_DMA_COMPLETE */\r
-.set SCSI_RX_DMA_COMPLETE__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
-.set SCSI_RX_DMA_COMPLETE__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
-.set SCSI_RX_DMA_COMPLETE__INTC_MASK, 0x01\r
-.set SCSI_RX_DMA_COMPLETE__INTC_NUMBER, 0\r
-.set SCSI_RX_DMA_COMPLETE__INTC_PRIOR_NUM, 7\r
-.set SCSI_RX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_0\r
-.set SCSI_RX_DMA_COMPLETE__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
-.set SCSI_RX_DMA_COMPLETE__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
-\r
-/* SCSI_TX_DMA */\r
-.set SCSI_TX_DMA__DRQ_CTL, CYREG_IDMUX_DRQ_CTL0\r
-.set SCSI_TX_DMA__DRQ_NUMBER, 1\r
-.set SCSI_TX_DMA__NUMBEROF_TDS, 0\r
-.set SCSI_TX_DMA__PRIORITY, 2\r
-.set SCSI_TX_DMA__TERMIN_EN, 0\r
-.set SCSI_TX_DMA__TERMIN_SEL, 0\r
-.set SCSI_TX_DMA__TERMOUT0_EN, 1\r
-.set SCSI_TX_DMA__TERMOUT0_SEL, 1\r
-.set SCSI_TX_DMA__TERMOUT1_EN, 0\r
-.set SCSI_TX_DMA__TERMOUT1_SEL, 0\r
-\r
-/* SCSI_TX_DMA_COMPLETE */\r
-.set SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
-.set SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
-.set SCSI_TX_DMA_COMPLETE__INTC_MASK, 0x10\r
-.set SCSI_TX_DMA_COMPLETE__INTC_NUMBER, 4\r
-.set SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM, 7\r
-.set SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_4\r
-.set SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
-.set SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
-\r
-/* SD_Data_Clk */\r
-.set SD_Data_Clk__CFG0, CYREG_CLKDIST_DCFG0_CFG0\r
-.set SD_Data_Clk__CFG1, CYREG_CLKDIST_DCFG0_CFG1\r
-.set SD_Data_Clk__CFG2, CYREG_CLKDIST_DCFG0_CFG2\r
-.set SD_Data_Clk__CFG2_SRC_SEL_MASK, 0x07\r
-.set SD_Data_Clk__INDEX, 0x00\r
-.set SD_Data_Clk__PM_ACT_CFG, CYREG_PM_ACT_CFG2\r
-.set SD_Data_Clk__PM_ACT_MSK, 0x01\r
-.set SD_Data_Clk__PM_STBY_CFG, CYREG_PM_STBY_CFG2\r
-.set SD_Data_Clk__PM_STBY_MSK, 0x01\r
-\r
 /* timer_clock */\r
 .set timer_clock__CFG0, CYREG_CLKDIST_DCFG2_CFG0\r
 .set timer_clock__CFG1, CYREG_CLKDIST_DCFG2_CFG1\r
@@ -2892,146 +2966,53 @@
 .set timer_clock__PM_STBY_CFG, CYREG_PM_STBY_CFG2\r
 .set timer_clock__PM_STBY_MSK, 0x04\r
 \r
-/* SCSI_RST_ISR */\r
-.set SCSI_RST_ISR__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
-.set SCSI_RST_ISR__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
-.set SCSI_RST_ISR__INTC_MASK, 0x04\r
-.set SCSI_RST_ISR__INTC_NUMBER, 2\r
-.set SCSI_RST_ISR__INTC_PRIOR_NUM, 7\r
-.set SCSI_RST_ISR__INTC_PRIOR_REG, CYREG_NVIC_PRI_2\r
-.set SCSI_RST_ISR__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
-.set SCSI_RST_ISR__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
-\r
-/* SCSI_SEL_ISR */\r
-.set SCSI_SEL_ISR__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
-.set SCSI_SEL_ISR__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
-.set SCSI_SEL_ISR__INTC_MASK, 0x08\r
-.set SCSI_SEL_ISR__INTC_NUMBER, 3\r
-.set SCSI_SEL_ISR__INTC_PRIOR_NUM, 7\r
-.set SCSI_SEL_ISR__INTC_PRIOR_REG, CYREG_NVIC_PRI_3\r
-.set SCSI_SEL_ISR__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
-.set SCSI_SEL_ISR__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
-\r
-/* SCSI_Filtered */\r
-.set SCSI_Filtered_sts_sts_reg__0__MASK, 0x01\r
-.set SCSI_Filtered_sts_sts_reg__0__POS, 0\r
-.set SCSI_Filtered_sts_sts_reg__1__MASK, 0x02\r
-.set SCSI_Filtered_sts_sts_reg__1__POS, 1\r
-.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB11_12_ACTL\r
-.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB11_12_ST\r
-.set SCSI_Filtered_sts_sts_reg__2__MASK, 0x04\r
-.set SCSI_Filtered_sts_sts_reg__2__POS, 2\r
-.set SCSI_Filtered_sts_sts_reg__3__MASK, 0x08\r
-.set SCSI_Filtered_sts_sts_reg__3__POS, 3\r
-.set SCSI_Filtered_sts_sts_reg__4__MASK, 0x10\r
-.set SCSI_Filtered_sts_sts_reg__4__POS, 4\r
-.set SCSI_Filtered_sts_sts_reg__MASK, 0x1F\r
-.set SCSI_Filtered_sts_sts_reg__MASK_REG, CYREG_B0_UDB11_MSK\r
-.set SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB11_ACTL\r
-.set SCSI_Filtered_sts_sts_reg__STATUS_REG, CYREG_B0_UDB11_ST\r
-\r
-/* SCSI_CTL_PHASE */\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK, 0x01\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS, 0\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK, 0x02\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS, 1\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB06_07_ACTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB06_07_CTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB06_07_CTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB06_07_CTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB06_07_CTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB06_07_MSK\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB06_07_MSK\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB06_07_MSK\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB06_07_MSK\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK, 0x04\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS, 2\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB06_ACTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB06_CTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB06_ST_CTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB06_CTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB06_ST_CTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK, 0x07\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB06_MSK_ACTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB06_MSK_ACTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB06_MSK\r
-\r
-/* SCSI_Glitch_Ctl */\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK, 0x01\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS, 0\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB04_05_ACTL\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB04_05_CTL\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB04_05_CTL\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB04_05_CTL\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB04_05_CTL\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB04_05_MSK\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB04_05_MSK\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB04_05_MSK\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB04_05_MSK\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB04_ACTL\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB04_CTL\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB04_ST_CTL\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB04_CTL\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB04_ST_CTL\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK, 0x01\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB04_MSK\r
-\r
-/* SCSI_Parity_Error */\r
-.set SCSI_Parity_Error_sts_sts_reg__0__MASK, 0x01\r
-.set SCSI_Parity_Error_sts_sts_reg__0__POS, 0\r
-.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB05_06_ACTL\r
-.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB05_06_ST\r
-.set SCSI_Parity_Error_sts_sts_reg__MASK, 0x01\r
-.set SCSI_Parity_Error_sts_sts_reg__MASK_REG, CYREG_B0_UDB05_MSK\r
-.set SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB05_ACTL\r
-.set SCSI_Parity_Error_sts_sts_reg__STATUS_REG, CYREG_B0_UDB05_ST\r
-\r
 /* Miscellaneous */\r
 .set BCLK__BUS_CLK__HZ, 50000000\r
 .set BCLK__BUS_CLK__KHZ, 50000\r
 .set BCLK__BUS_CLK__MHZ, 50\r
 .set CYDEV_CHIP_DIE_LEOPARD, 1\r
-.set CYDEV_CHIP_DIE_PSOC4A, 12\r
-.set CYDEV_CHIP_DIE_PSOC5LP, 19\r
-.set CYDEV_CHIP_DIE_PSOC5TM, 20\r
-.set CYDEV_CHIP_DIE_TMA4, 2\r
+.set CYDEV_CHIP_DIE_PSOC4A, 16\r
+.set CYDEV_CHIP_DIE_PSOC5LP, 2\r
+.set CYDEV_CHIP_DIE_PSOC5TM, 3\r
+.set CYDEV_CHIP_DIE_TMA4, 4\r
 .set CYDEV_CHIP_DIE_UNKNOWN, 0\r
-.set CYDEV_CHIP_FAMILY_FM0P, 4\r
-.set CYDEV_CHIP_FAMILY_FM3, 5\r
-.set CYDEV_CHIP_FAMILY_FM4, 6\r
+.set CYDEV_CHIP_FAMILY_FM0P, 5\r
+.set CYDEV_CHIP_FAMILY_FM3, 6\r
+.set CYDEV_CHIP_FAMILY_FM4, 7\r
 .set CYDEV_CHIP_FAMILY_PSOC3, 1\r
 .set CYDEV_CHIP_FAMILY_PSOC4, 2\r
 .set CYDEV_CHIP_FAMILY_PSOC5, 3\r
+.set CYDEV_CHIP_FAMILY_PSOC6, 4\r
 .set CYDEV_CHIP_FAMILY_UNKNOWN, 0\r
 .set CYDEV_CHIP_FAMILY_USED, CYDEV_CHIP_FAMILY_PSOC5\r
 .set CYDEV_CHIP_JTAG_ID, 0x2E133069\r
 .set CYDEV_CHIP_MEMBER_3A, 1\r
-.set CYDEV_CHIP_MEMBER_4A, 12\r
-.set CYDEV_CHIP_MEMBER_4C, 18\r
-.set CYDEV_CHIP_MEMBER_4D, 8\r
-.set CYDEV_CHIP_MEMBER_4E, 4\r
-.set CYDEV_CHIP_MEMBER_4F, 13\r
-.set CYDEV_CHIP_MEMBER_4G, 2\r
-.set CYDEV_CHIP_MEMBER_4H, 11\r
-.set CYDEV_CHIP_MEMBER_4I, 17\r
-.set CYDEV_CHIP_MEMBER_4J, 9\r
-.set CYDEV_CHIP_MEMBER_4K, 10\r
-.set CYDEV_CHIP_MEMBER_4L, 16\r
-.set CYDEV_CHIP_MEMBER_4M, 15\r
-.set CYDEV_CHIP_MEMBER_4N, 6\r
-.set CYDEV_CHIP_MEMBER_4O, 5\r
-.set CYDEV_CHIP_MEMBER_4P, 14\r
-.set CYDEV_CHIP_MEMBER_4Q, 7\r
-.set CYDEV_CHIP_MEMBER_4U, 3\r
-.set CYDEV_CHIP_MEMBER_5A, 20\r
-.set CYDEV_CHIP_MEMBER_5B, 19\r
-.set CYDEV_CHIP_MEMBER_FM3, 24\r
-.set CYDEV_CHIP_MEMBER_FM4, 25\r
-.set CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE1, 21\r
-.set CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE2, 22\r
-.set CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE3, 23\r
+.set CYDEV_CHIP_MEMBER_4A, 16\r
+.set CYDEV_CHIP_MEMBER_4D, 12\r
+.set CYDEV_CHIP_MEMBER_4E, 6\r
+.set CYDEV_CHIP_MEMBER_4F, 17\r
+.set CYDEV_CHIP_MEMBER_4G, 4\r
+.set CYDEV_CHIP_MEMBER_4H, 15\r
+.set CYDEV_CHIP_MEMBER_4I, 21\r
+.set CYDEV_CHIP_MEMBER_4J, 13\r
+.set CYDEV_CHIP_MEMBER_4K, 14\r
+.set CYDEV_CHIP_MEMBER_4L, 20\r
+.set CYDEV_CHIP_MEMBER_4M, 19\r
+.set CYDEV_CHIP_MEMBER_4N, 9\r
+.set CYDEV_CHIP_MEMBER_4O, 7\r
+.set CYDEV_CHIP_MEMBER_4P, 18\r
+.set CYDEV_CHIP_MEMBER_4Q, 11\r
+.set CYDEV_CHIP_MEMBER_4R, 8\r
+.set CYDEV_CHIP_MEMBER_4S, 10\r
+.set CYDEV_CHIP_MEMBER_4U, 5\r
+.set CYDEV_CHIP_MEMBER_5A, 3\r
+.set CYDEV_CHIP_MEMBER_5B, 2\r
+.set CYDEV_CHIP_MEMBER_6A, 22\r
+.set CYDEV_CHIP_MEMBER_FM3, 26\r
+.set CYDEV_CHIP_MEMBER_FM4, 27\r
+.set CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE1, 23\r
+.set CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE2, 24\r
+.set CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE3, 25\r
 .set CYDEV_CHIP_MEMBER_UNKNOWN, 0\r
 .set CYDEV_CHIP_MEMBER_USED, CYDEV_CHIP_MEMBER_5B\r
 .set CYDEV_CHIP_DIE_EXPECT, CYDEV_CHIP_MEMBER_USED\r
@@ -3056,7 +3037,6 @@
 .set CYDEV_CHIP_REVISION_3A_PRODUCTION, 3\r
 .set CYDEV_CHIP_REVISION_4A_ES0, 17\r
 .set CYDEV_CHIP_REVISION_4A_PRODUCTION, 17\r
-.set CYDEV_CHIP_REVISION_4C_PRODUCTION, 0\r
 .set CYDEV_CHIP_REVISION_4D_PRODUCTION, 0\r
 .set CYDEV_CHIP_REVISION_4E_PRODUCTION, 0\r
 .set CYDEV_CHIP_REVISION_4F_PRODUCTION, 0\r
@@ -3075,12 +3055,16 @@
 .set CYDEV_CHIP_REVISION_4O_PRODUCTION, 0\r
 .set CYDEV_CHIP_REVISION_4P_PRODUCTION, 0\r
 .set CYDEV_CHIP_REVISION_4Q_PRODUCTION, 0\r
+.set CYDEV_CHIP_REVISION_4R_PRODUCTION, 0\r
+.set CYDEV_CHIP_REVISION_4S_PRODUCTION, 0\r
 .set CYDEV_CHIP_REVISION_4U_PRODUCTION, 0\r
 .set CYDEV_CHIP_REVISION_5A_ES0, 0\r
 .set CYDEV_CHIP_REVISION_5A_ES1, 1\r
 .set CYDEV_CHIP_REVISION_5A_PRODUCTION, 1\r
 .set CYDEV_CHIP_REVISION_5B_ES0, 0\r
 .set CYDEV_CHIP_REVISION_5B_PRODUCTION, 0\r
+.set CYDEV_CHIP_REVISION_6A_NO_UDB, 0\r
+.set CYDEV_CHIP_REVISION_6A_PRODUCTION, 0\r
 .set CYDEV_CHIP_REVISION_FM3_PRODUCTION, 0\r
 .set CYDEV_CHIP_REVISION_FM4_PRODUCTION, 0\r
 .set CYDEV_CHIP_REVISION_PDL_FM0P_TYPE1_PRODUCTION, 0\r
@@ -3112,7 +3096,7 @@
 .set CYDEV_ECC_ENABLE, 0\r
 .set CYDEV_HEAP_SIZE, 0x0400\r
 .set CYDEV_INSTRUCT_CACHE_ENABLED, 1\r
-.set CYDEV_INTR_RISING, 0x0000007E\r
+.set CYDEV_INTR_RISING, 0x0000007F\r
 .set CYDEV_IS_EXPORTING_CODE, 0\r
 .set CYDEV_IS_IMPORTING_CODE, 0\r
 .set CYDEV_PROJ_TYPE, 2\r

diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitteriar.inc b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitteriar.inc
index fcd0bffaebc50dbb2609141f8e4d97ec9f05eaa3..0ecaa2690cb3a374e6bee2a88f472a56f82deb6e 100755 (executable)
--- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitteriar.inc
+++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitteriar.inc
@@ -1,8 +1,85 @@
+;\r
+; File Name: cyfitteriar.inc\r
+; \r
+; PSoC Creator  4.1\r
+;\r
+; Description:\r
+; \r
+;\r
+;-------------------------------------------------------------------------------\r
+; Copyright (c) 2007-2017 Cypress Semiconductor.  All rights reserved.\r
+; You may use this file only in accordance with the license, terms, conditions, \r
+; disclaimers, and limitations in the end user license agreement accompanying \r
+; the software package with which this file was provided.\r
+;-------------------------------------------------------------------------------\r
+\r
 #ifndef INCLUDED_CYFITTERIAR_INC\r
 #define INCLUDED_CYFITTERIAR_INC\r
     INCLUDE cydeviceiar.inc\r
     INCLUDE cydeviceiar_trm.inc\r
 \r
+/* Debug_Timer_Interrupt */\r
+Debug_Timer_Interrupt__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
+Debug_Timer_Interrupt__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
+Debug_Timer_Interrupt__INTC_MASK EQU 0x01\r
+Debug_Timer_Interrupt__INTC_NUMBER EQU 0\r
+Debug_Timer_Interrupt__INTC_PRIOR_NUM EQU 7\r
+Debug_Timer_Interrupt__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_0\r
+Debug_Timer_Interrupt__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
+Debug_Timer_Interrupt__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
+\r
+/* Debug_Timer_TimerHW */\r
+Debug_Timer_TimerHW__CAP0 EQU CYREG_TMR0_CAP0\r
+Debug_Timer_TimerHW__CAP1 EQU CYREG_TMR0_CAP1\r
+Debug_Timer_TimerHW__CFG0 EQU CYREG_TMR0_CFG0\r
+Debug_Timer_TimerHW__CFG1 EQU CYREG_TMR0_CFG1\r
+Debug_Timer_TimerHW__CFG2 EQU CYREG_TMR0_CFG2\r
+Debug_Timer_TimerHW__CNT_CMP0 EQU CYREG_TMR0_CNT_CMP0\r
+Debug_Timer_TimerHW__CNT_CMP1 EQU CYREG_TMR0_CNT_CMP1\r
+Debug_Timer_TimerHW__PER0 EQU CYREG_TMR0_PER0\r
+Debug_Timer_TimerHW__PER1 EQU CYREG_TMR0_PER1\r
+Debug_Timer_TimerHW__PM_ACT_CFG EQU CYREG_PM_ACT_CFG3\r
+Debug_Timer_TimerHW__PM_ACT_MSK EQU 0x01\r
+Debug_Timer_TimerHW__PM_STBY_CFG EQU CYREG_PM_STBY_CFG3\r
+Debug_Timer_TimerHW__PM_STBY_MSK EQU 0x01\r
+Debug_Timer_TimerHW__RT0 EQU CYREG_TMR0_RT0\r
+Debug_Timer_TimerHW__RT1 EQU CYREG_TMR0_RT1\r
+Debug_Timer_TimerHW__SR0 EQU CYREG_TMR0_SR0\r
+\r
+/* EXTLED */\r
+EXTLED__0__INTTYPE EQU CYREG_PICU0_INTTYPE0\r
+EXTLED__0__MASK EQU 0x01\r
+EXTLED__0__PC EQU CYREG_PRT0_PC0\r
+EXTLED__0__PORT EQU 0\r
+EXTLED__0__SHIFT EQU 0\r
+EXTLED__AG EQU CYREG_PRT0_AG\r
+EXTLED__AMUX EQU CYREG_PRT0_AMUX\r
+EXTLED__BIE EQU CYREG_PRT0_BIE\r
+EXTLED__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
+EXTLED__BYP EQU CYREG_PRT0_BYP\r
+EXTLED__CTL EQU CYREG_PRT0_CTL\r
+EXTLED__DM0 EQU CYREG_PRT0_DM0\r
+EXTLED__DM1 EQU CYREG_PRT0_DM1\r
+EXTLED__DM2 EQU CYREG_PRT0_DM2\r
+EXTLED__DR EQU CYREG_PRT0_DR\r
+EXTLED__INP_DIS EQU CYREG_PRT0_INP_DIS\r
+EXTLED__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU0_BASE\r
+EXTLED__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
+EXTLED__LCD_EN EQU CYREG_PRT0_LCD_EN\r
+EXTLED__MASK EQU 0x01\r
+EXTLED__PORT EQU 0\r
+EXTLED__PRT EQU CYREG_PRT0_PRT\r
+EXTLED__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
+EXTLED__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
+EXTLED__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
+EXTLED__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
+EXTLED__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
+EXTLED__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
+EXTLED__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
+EXTLED__PS EQU CYREG_PRT0_PS\r
+EXTLED__SHIFT EQU 0\r
+EXTLED__SLW EQU CYREG_PRT0_SLW\r
+\r
 /* LED1 */\r
 LED1__0__INTTYPE EQU CYREG_PICU0_INTTYPE1\r
 LED1__0__MASK EQU 0x02\r
@@ -37,2421 +114,808 @@ LED1__PS EQU CYREG_PRT0_PS
 LED1__SHIFT EQU 1\r
 LED1__SLW EQU CYREG_PRT0_SLW\r
 \r
-/* SD_CD */\r
-SD_CD__0__INTTYPE EQU CYREG_PICU3_INTTYPE5\r
-SD_CD__0__MASK EQU 0x20\r
-SD_CD__0__PC EQU CYREG_PRT3_PC5\r
-SD_CD__0__PORT EQU 3\r
-SD_CD__0__SHIFT EQU 5\r
-SD_CD__AG EQU CYREG_PRT3_AG\r
-SD_CD__AMUX EQU CYREG_PRT3_AMUX\r
-SD_CD__BIE EQU CYREG_PRT3_BIE\r
-SD_CD__BIT_MASK EQU CYREG_PRT3_BIT_MASK\r
-SD_CD__BYP EQU CYREG_PRT3_BYP\r
-SD_CD__CTL EQU CYREG_PRT3_CTL\r
-SD_CD__DM0 EQU CYREG_PRT3_DM0\r
-SD_CD__DM1 EQU CYREG_PRT3_DM1\r
-SD_CD__DM2 EQU CYREG_PRT3_DM2\r
-SD_CD__DR EQU CYREG_PRT3_DR\r
-SD_CD__INP_DIS EQU CYREG_PRT3_INP_DIS\r
-SD_CD__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE\r
-SD_CD__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG\r
-SD_CD__LCD_EN EQU CYREG_PRT3_LCD_EN\r
-SD_CD__MASK EQU 0x20\r
-SD_CD__PORT EQU 3\r
-SD_CD__PRT EQU CYREG_PRT3_PRT\r
-SD_CD__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL\r
-SD_CD__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN\r
-SD_CD__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0\r
-SD_CD__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1\r
-SD_CD__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0\r
-SD_CD__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1\r
-SD_CD__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT\r
-SD_CD__PS EQU CYREG_PRT3_PS\r
-SD_CD__SHIFT EQU 5\r
-SD_CD__SLW EQU CYREG_PRT3_SLW\r
-\r
-/* SD_CS */\r
-SD_CS__0__INTTYPE EQU CYREG_PICU3_INTTYPE4\r
-SD_CS__0__MASK EQU 0x10\r
-SD_CS__0__PC EQU CYREG_PRT3_PC4\r
-SD_CS__0__PORT EQU 3\r
-SD_CS__0__SHIFT EQU 4\r
-SD_CS__AG EQU CYREG_PRT3_AG\r
-SD_CS__AMUX EQU CYREG_PRT3_AMUX\r
-SD_CS__BIE EQU CYREG_PRT3_BIE\r
-SD_CS__BIT_MASK EQU CYREG_PRT3_BIT_MASK\r
-SD_CS__BYP EQU CYREG_PRT3_BYP\r
-SD_CS__CTL EQU CYREG_PRT3_CTL\r
-SD_CS__DM0 EQU CYREG_PRT3_DM0\r
-SD_CS__DM1 EQU CYREG_PRT3_DM1\r
-SD_CS__DM2 EQU CYREG_PRT3_DM2\r
-SD_CS__DR EQU CYREG_PRT3_DR\r
-SD_CS__INP_DIS EQU CYREG_PRT3_INP_DIS\r
-SD_CS__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE\r
-SD_CS__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG\r
-SD_CS__LCD_EN EQU CYREG_PRT3_LCD_EN\r
-SD_CS__MASK EQU 0x10\r
-SD_CS__PORT EQU 3\r
-SD_CS__PRT EQU CYREG_PRT3_PRT\r
-SD_CS__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL\r
-SD_CS__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN\r
-SD_CS__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0\r
-SD_CS__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1\r
-SD_CS__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0\r
-SD_CS__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1\r
-SD_CS__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT\r
-SD_CS__PS EQU CYREG_PRT3_PS\r
-SD_CS__SHIFT EQU 4\r
-SD_CS__SLW EQU CYREG_PRT3_SLW\r
+/* SCSI_CLK */\r
+SCSI_CLK__CFG0 EQU CYREG_CLKDIST_DCFG1_CFG0\r
+SCSI_CLK__CFG1 EQU CYREG_CLKDIST_DCFG1_CFG1\r
+SCSI_CLK__CFG2 EQU CYREG_CLKDIST_DCFG1_CFG2\r
+SCSI_CLK__CFG2_SRC_SEL_MASK EQU 0x07\r
+SCSI_CLK__INDEX EQU 0x01\r
+SCSI_CLK__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2\r
+SCSI_CLK__PM_ACT_MSK EQU 0x02\r
+SCSI_CLK__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2\r
+SCSI_CLK__PM_STBY_MSK EQU 0x02\r
 \r
-/* USBFS_arb_int */\r
-USBFS_arb_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
-USBFS_arb_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
-USBFS_arb_int__INTC_MASK EQU 0x400000\r
-USBFS_arb_int__INTC_NUMBER EQU 22\r
-USBFS_arb_int__INTC_PRIOR_NUM EQU 6\r
-USBFS_arb_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_22\r
-USBFS_arb_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
-USBFS_arb_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
+/* SCSI_CTL_PHASE */\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS EQU 0\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK EQU 0x02\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS EQU 1\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB06_07_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB06_07_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB06_07_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB06_07_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB06_07_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB06_07_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB06_07_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB06_07_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK EQU 0x04\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS EQU 2\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB06_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB06_ST_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB06_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB06_ST_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__MASK EQU 0x07\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB06_MSK\r
 \r
-/* USBFS_bus_reset */\r
-USBFS_bus_reset__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
-USBFS_bus_reset__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
-USBFS_bus_reset__INTC_MASK EQU 0x800000\r
-USBFS_bus_reset__INTC_NUMBER EQU 23\r
-USBFS_bus_reset__INTC_PRIOR_NUM EQU 7\r
-USBFS_bus_reset__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_23\r
-USBFS_bus_reset__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
-USBFS_bus_reset__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
+/* SCSI_Filtered */\r
+SCSI_Filtered_sts_sts_reg__0__MASK EQU 0x01\r
+SCSI_Filtered_sts_sts_reg__0__POS EQU 0\r
+SCSI_Filtered_sts_sts_reg__1__MASK EQU 0x02\r
+SCSI_Filtered_sts_sts_reg__1__POS EQU 1\r
+SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL\r
+SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB11_12_ST\r
+SCSI_Filtered_sts_sts_reg__2__MASK EQU 0x04\r
+SCSI_Filtered_sts_sts_reg__2__POS EQU 2\r
+SCSI_Filtered_sts_sts_reg__3__MASK EQU 0x08\r
+SCSI_Filtered_sts_sts_reg__3__POS EQU 3\r
+SCSI_Filtered_sts_sts_reg__4__MASK EQU 0x10\r
+SCSI_Filtered_sts_sts_reg__4__POS EQU 4\r
+SCSI_Filtered_sts_sts_reg__MASK EQU 0x1F\r
+SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB11_MSK\r
+SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL\r
+SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB11_ST\r
 \r
-/* USBFS_Dm */\r
-USBFS_Dm__0__INTTYPE EQU CYREG_PICU15_INTTYPE7\r
-USBFS_Dm__0__MASK EQU 0x80\r
-USBFS_Dm__0__PC EQU CYREG_IO_PC_PRT15_7_6_PC1\r
-USBFS_Dm__0__PORT EQU 15\r
-USBFS_Dm__0__SHIFT EQU 7\r
-USBFS_Dm__AG EQU CYREG_PRT15_AG\r
-USBFS_Dm__AMUX EQU CYREG_PRT15_AMUX\r
-USBFS_Dm__BIE EQU CYREG_PRT15_BIE\r
-USBFS_Dm__BIT_MASK EQU CYREG_PRT15_BIT_MASK\r
-USBFS_Dm__BYP EQU CYREG_PRT15_BYP\r
-USBFS_Dm__CTL EQU CYREG_PRT15_CTL\r
-USBFS_Dm__DM0 EQU CYREG_PRT15_DM0\r
-USBFS_Dm__DM1 EQU CYREG_PRT15_DM1\r
-USBFS_Dm__DM2 EQU CYREG_PRT15_DM2\r
-USBFS_Dm__DR EQU CYREG_PRT15_DR\r
-USBFS_Dm__INP_DIS EQU CYREG_PRT15_INP_DIS\r
-USBFS_Dm__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU15_BASE\r
-USBFS_Dm__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG\r
-USBFS_Dm__LCD_EN EQU CYREG_PRT15_LCD_EN\r
-USBFS_Dm__MASK EQU 0x80\r
-USBFS_Dm__PORT EQU 15\r
-USBFS_Dm__PRT EQU CYREG_PRT15_PRT\r
-USBFS_Dm__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL\r
-USBFS_Dm__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN\r
-USBFS_Dm__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0\r
-USBFS_Dm__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1\r
-USBFS_Dm__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0\r
-USBFS_Dm__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1\r
-USBFS_Dm__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT\r
-USBFS_Dm__PS EQU CYREG_PRT15_PS\r
-USBFS_Dm__SHIFT EQU 7\r
-USBFS_Dm__SLW EQU CYREG_PRT15_SLW\r
+/* SCSI_Glitch_Ctl */\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS EQU 0\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB04_05_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB04_05_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB04_05_MSK\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB04_05_MSK\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB04_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB04_ST_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB04_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB04_ST_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK EQU 0x01\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB04_MSK\r
 \r
-/* USBFS_Dp */\r
-USBFS_Dp__0__INTTYPE EQU CYREG_PICU15_INTTYPE6\r
-USBFS_Dp__0__MASK EQU 0x40\r
-USBFS_Dp__0__PC EQU CYREG_IO_PC_PRT15_7_6_PC0\r
-USBFS_Dp__0__PORT EQU 15\r
-USBFS_Dp__0__SHIFT EQU 6\r
-USBFS_Dp__AG EQU CYREG_PRT15_AG\r
-USBFS_Dp__AMUX EQU CYREG_PRT15_AMUX\r
-USBFS_Dp__BIE EQU CYREG_PRT15_BIE\r
-USBFS_Dp__BIT_MASK EQU CYREG_PRT15_BIT_MASK\r
-USBFS_Dp__BYP EQU CYREG_PRT15_BYP\r
-USBFS_Dp__CTL EQU CYREG_PRT15_CTL\r
-USBFS_Dp__DM0 EQU CYREG_PRT15_DM0\r
-USBFS_Dp__DM1 EQU CYREG_PRT15_DM1\r
-USBFS_Dp__DM2 EQU CYREG_PRT15_DM2\r
-USBFS_Dp__DR EQU CYREG_PRT15_DR\r
-USBFS_Dp__INP_DIS EQU CYREG_PRT15_INP_DIS\r
-USBFS_Dp__INTSTAT EQU CYREG_PICU15_INTSTAT\r
-USBFS_Dp__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU15_BASE\r
-USBFS_Dp__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG\r
-USBFS_Dp__LCD_EN EQU CYREG_PRT15_LCD_EN\r
-USBFS_Dp__MASK EQU 0x40\r
-USBFS_Dp__PORT EQU 15\r
-USBFS_Dp__PRT EQU CYREG_PRT15_PRT\r
-USBFS_Dp__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL\r
-USBFS_Dp__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN\r
-USBFS_Dp__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0\r
-USBFS_Dp__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1\r
-USBFS_Dp__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0\r
-USBFS_Dp__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1\r
-USBFS_Dp__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT\r
-USBFS_Dp__PS EQU CYREG_PRT15_PS\r
-USBFS_Dp__SHIFT EQU 6\r
-USBFS_Dp__SLW EQU CYREG_PRT15_SLW\r
-USBFS_Dp__SNAP EQU CYREG_PICU_15_SNAP_15\r
-\r
-/* USBFS_dp_int */\r
-USBFS_dp_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
-USBFS_dp_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
-USBFS_dp_int__INTC_MASK EQU 0x1000\r
-USBFS_dp_int__INTC_NUMBER EQU 12\r
-USBFS_dp_int__INTC_PRIOR_NUM EQU 7\r
-USBFS_dp_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_12\r
-USBFS_dp_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
-USBFS_dp_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
-\r
-/* USBFS_ep_0 */\r
-USBFS_ep_0__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
-USBFS_ep_0__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
-USBFS_ep_0__INTC_MASK EQU 0x1000000\r
-USBFS_ep_0__INTC_NUMBER EQU 24\r
-USBFS_ep_0__INTC_PRIOR_NUM EQU 7\r
-USBFS_ep_0__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_24\r
-USBFS_ep_0__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
-USBFS_ep_0__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
-\r
-/* USBFS_ep_1 */\r
-USBFS_ep_1__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
-USBFS_ep_1__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
-USBFS_ep_1__INTC_MASK EQU 0x80\r
-USBFS_ep_1__INTC_NUMBER EQU 7\r
-USBFS_ep_1__INTC_PRIOR_NUM EQU 7\r
-USBFS_ep_1__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_7\r
-USBFS_ep_1__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
-USBFS_ep_1__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
-\r
-/* USBFS_ep_2 */\r
-USBFS_ep_2__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
-USBFS_ep_2__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
-USBFS_ep_2__INTC_MASK EQU 0x100\r
-USBFS_ep_2__INTC_NUMBER EQU 8\r
-USBFS_ep_2__INTC_PRIOR_NUM EQU 7\r
-USBFS_ep_2__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_8\r
-USBFS_ep_2__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
-USBFS_ep_2__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
-\r
-/* USBFS_ep_3 */\r
-USBFS_ep_3__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
-USBFS_ep_3__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
-USBFS_ep_3__INTC_MASK EQU 0x200\r
-USBFS_ep_3__INTC_NUMBER EQU 9\r
-USBFS_ep_3__INTC_PRIOR_NUM EQU 7\r
-USBFS_ep_3__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_9\r
-USBFS_ep_3__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
-USBFS_ep_3__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
-\r
-/* USBFS_ep_4 */\r
-USBFS_ep_4__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
-USBFS_ep_4__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
-USBFS_ep_4__INTC_MASK EQU 0x400\r
-USBFS_ep_4__INTC_NUMBER EQU 10\r
-USBFS_ep_4__INTC_PRIOR_NUM EQU 7\r
-USBFS_ep_4__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_10\r
-USBFS_ep_4__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
-USBFS_ep_4__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
-\r
-/* USBFS_sof_int */\r
-USBFS_sof_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
-USBFS_sof_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
-USBFS_sof_int__INTC_MASK EQU 0x200000\r
-USBFS_sof_int__INTC_NUMBER EQU 21\r
-USBFS_sof_int__INTC_PRIOR_NUM EQU 7\r
-USBFS_sof_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_21\r
-USBFS_sof_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
-USBFS_sof_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
-\r
-/* USBFS_USB */\r
-USBFS_USB__ARB_CFG EQU CYREG_USB_ARB_CFG\r
-USBFS_USB__ARB_EP1_CFG EQU CYREG_USB_ARB_EP1_CFG\r
-USBFS_USB__ARB_EP1_INT_EN EQU CYREG_USB_ARB_EP1_INT_EN\r
-USBFS_USB__ARB_EP1_SR EQU CYREG_USB_ARB_EP1_SR\r
-USBFS_USB__ARB_EP2_CFG EQU CYREG_USB_ARB_EP2_CFG\r
-USBFS_USB__ARB_EP2_INT_EN EQU CYREG_USB_ARB_EP2_INT_EN\r
-USBFS_USB__ARB_EP2_SR EQU CYREG_USB_ARB_EP2_SR\r
-USBFS_USB__ARB_EP3_CFG EQU CYREG_USB_ARB_EP3_CFG\r
-USBFS_USB__ARB_EP3_INT_EN EQU CYREG_USB_ARB_EP3_INT_EN\r
-USBFS_USB__ARB_EP3_SR EQU CYREG_USB_ARB_EP3_SR\r
-USBFS_USB__ARB_EP4_CFG EQU CYREG_USB_ARB_EP4_CFG\r
-USBFS_USB__ARB_EP4_INT_EN EQU CYREG_USB_ARB_EP4_INT_EN\r
-USBFS_USB__ARB_EP4_SR EQU CYREG_USB_ARB_EP4_SR\r
-USBFS_USB__ARB_EP5_CFG EQU CYREG_USB_ARB_EP5_CFG\r
-USBFS_USB__ARB_EP5_INT_EN EQU CYREG_USB_ARB_EP5_INT_EN\r
-USBFS_USB__ARB_EP5_SR EQU CYREG_USB_ARB_EP5_SR\r
-USBFS_USB__ARB_EP6_CFG EQU CYREG_USB_ARB_EP6_CFG\r
-USBFS_USB__ARB_EP6_INT_EN EQU CYREG_USB_ARB_EP6_INT_EN\r
-USBFS_USB__ARB_EP6_SR EQU CYREG_USB_ARB_EP6_SR\r
-USBFS_USB__ARB_EP7_CFG EQU CYREG_USB_ARB_EP7_CFG\r
-USBFS_USB__ARB_EP7_INT_EN EQU CYREG_USB_ARB_EP7_INT_EN\r
-USBFS_USB__ARB_EP7_SR EQU CYREG_USB_ARB_EP7_SR\r
-USBFS_USB__ARB_EP8_CFG EQU CYREG_USB_ARB_EP8_CFG\r
-USBFS_USB__ARB_EP8_INT_EN EQU CYREG_USB_ARB_EP8_INT_EN\r
-USBFS_USB__ARB_EP8_SR EQU CYREG_USB_ARB_EP8_SR\r
-USBFS_USB__ARB_INT_EN EQU CYREG_USB_ARB_INT_EN\r
-USBFS_USB__ARB_INT_SR EQU CYREG_USB_ARB_INT_SR\r
-USBFS_USB__ARB_RW1_DR EQU CYREG_USB_ARB_RW1_DR\r
-USBFS_USB__ARB_RW1_RA EQU CYREG_USB_ARB_RW1_RA\r
-USBFS_USB__ARB_RW1_RA_MSB EQU CYREG_USB_ARB_RW1_RA_MSB\r
-USBFS_USB__ARB_RW1_WA EQU CYREG_USB_ARB_RW1_WA\r
-USBFS_USB__ARB_RW1_WA_MSB EQU CYREG_USB_ARB_RW1_WA_MSB\r
-USBFS_USB__ARB_RW2_DR EQU CYREG_USB_ARB_RW2_DR\r
-USBFS_USB__ARB_RW2_RA EQU CYREG_USB_ARB_RW2_RA\r
-USBFS_USB__ARB_RW2_RA_MSB EQU CYREG_USB_ARB_RW2_RA_MSB\r
-USBFS_USB__ARB_RW2_WA EQU CYREG_USB_ARB_RW2_WA\r
-USBFS_USB__ARB_RW2_WA_MSB EQU CYREG_USB_ARB_RW2_WA_MSB\r
-USBFS_USB__ARB_RW3_DR EQU CYREG_USB_ARB_RW3_DR\r
-USBFS_USB__ARB_RW3_RA EQU CYREG_USB_ARB_RW3_RA\r
-USBFS_USB__ARB_RW3_RA_MSB EQU CYREG_USB_ARB_RW3_RA_MSB\r
-USBFS_USB__ARB_RW3_WA EQU CYREG_USB_ARB_RW3_WA\r
-USBFS_USB__ARB_RW3_WA_MSB EQU CYREG_USB_ARB_RW3_WA_MSB\r
-USBFS_USB__ARB_RW4_DR EQU CYREG_USB_ARB_RW4_DR\r
-USBFS_USB__ARB_RW4_RA EQU CYREG_USB_ARB_RW4_RA\r
-USBFS_USB__ARB_RW4_RA_MSB EQU CYREG_USB_ARB_RW4_RA_MSB\r
-USBFS_USB__ARB_RW4_WA EQU CYREG_USB_ARB_RW4_WA\r
-USBFS_USB__ARB_RW4_WA_MSB EQU CYREG_USB_ARB_RW4_WA_MSB\r
-USBFS_USB__ARB_RW5_DR EQU CYREG_USB_ARB_RW5_DR\r
-USBFS_USB__ARB_RW5_RA EQU CYREG_USB_ARB_RW5_RA\r
-USBFS_USB__ARB_RW5_RA_MSB EQU CYREG_USB_ARB_RW5_RA_MSB\r
-USBFS_USB__ARB_RW5_WA EQU CYREG_USB_ARB_RW5_WA\r
-USBFS_USB__ARB_RW5_WA_MSB EQU CYREG_USB_ARB_RW5_WA_MSB\r
-USBFS_USB__ARB_RW6_DR EQU CYREG_USB_ARB_RW6_DR\r
-USBFS_USB__ARB_RW6_RA EQU CYREG_USB_ARB_RW6_RA\r
-USBFS_USB__ARB_RW6_RA_MSB EQU CYREG_USB_ARB_RW6_RA_MSB\r
-USBFS_USB__ARB_RW6_WA EQU CYREG_USB_ARB_RW6_WA\r
-USBFS_USB__ARB_RW6_WA_MSB EQU CYREG_USB_ARB_RW6_WA_MSB\r
-USBFS_USB__ARB_RW7_DR EQU CYREG_USB_ARB_RW7_DR\r
-USBFS_USB__ARB_RW7_RA EQU CYREG_USB_ARB_RW7_RA\r
-USBFS_USB__ARB_RW7_RA_MSB EQU CYREG_USB_ARB_RW7_RA_MSB\r
-USBFS_USB__ARB_RW7_WA EQU CYREG_USB_ARB_RW7_WA\r
-USBFS_USB__ARB_RW7_WA_MSB EQU CYREG_USB_ARB_RW7_WA_MSB\r
-USBFS_USB__ARB_RW8_DR EQU CYREG_USB_ARB_RW8_DR\r
-USBFS_USB__ARB_RW8_RA EQU CYREG_USB_ARB_RW8_RA\r
-USBFS_USB__ARB_RW8_RA_MSB EQU CYREG_USB_ARB_RW8_RA_MSB\r
-USBFS_USB__ARB_RW8_WA EQU CYREG_USB_ARB_RW8_WA\r
-USBFS_USB__ARB_RW8_WA_MSB EQU CYREG_USB_ARB_RW8_WA_MSB\r
-USBFS_USB__BUF_SIZE EQU CYREG_USB_BUF_SIZE\r
-USBFS_USB__BUS_RST_CNT EQU CYREG_USB_BUS_RST_CNT\r
-USBFS_USB__CR0 EQU CYREG_USB_CR0\r
-USBFS_USB__CR1 EQU CYREG_USB_CR1\r
-USBFS_USB__CWA EQU CYREG_USB_CWA\r
-USBFS_USB__CWA_MSB EQU CYREG_USB_CWA_MSB\r
-USBFS_USB__DMA_THRES EQU CYREG_USB_DMA_THRES\r
-USBFS_USB__DMA_THRES_MSB EQU CYREG_USB_DMA_THRES_MSB\r
-USBFS_USB__DYN_RECONFIG EQU CYREG_USB_DYN_RECONFIG\r
-USBFS_USB__EP_ACTIVE EQU CYREG_USB_EP_ACTIVE\r
-USBFS_USB__EP_TYPE EQU CYREG_USB_EP_TYPE\r
-USBFS_USB__EP0_CNT EQU CYREG_USB_EP0_CNT\r
-USBFS_USB__EP0_CR EQU CYREG_USB_EP0_CR\r
-USBFS_USB__EP0_DR0 EQU CYREG_USB_EP0_DR0\r
-USBFS_USB__EP0_DR1 EQU CYREG_USB_EP0_DR1\r
-USBFS_USB__EP0_DR2 EQU CYREG_USB_EP0_DR2\r
-USBFS_USB__EP0_DR3 EQU CYREG_USB_EP0_DR3\r
-USBFS_USB__EP0_DR4 EQU CYREG_USB_EP0_DR4\r
-USBFS_USB__EP0_DR5 EQU CYREG_USB_EP0_DR5\r
-USBFS_USB__EP0_DR6 EQU CYREG_USB_EP0_DR6\r
-USBFS_USB__EP0_DR7 EQU CYREG_USB_EP0_DR7\r
-USBFS_USB__MEM_DATA EQU CYREG_USB_MEM_DATA_MBASE\r
-USBFS_USB__PM_ACT_CFG EQU CYREG_PM_ACT_CFG5\r
-USBFS_USB__PM_ACT_MSK EQU 0x01\r
-USBFS_USB__PM_STBY_CFG EQU CYREG_PM_STBY_CFG5\r
-USBFS_USB__PM_STBY_MSK EQU 0x01\r
-USBFS_USB__SIE_EP_INT_EN EQU CYREG_USB_SIE_EP_INT_EN\r
-USBFS_USB__SIE_EP_INT_SR EQU CYREG_USB_SIE_EP_INT_SR\r
-USBFS_USB__SIE_EP1_CNT0 EQU CYREG_USB_SIE_EP1_CNT0\r
-USBFS_USB__SIE_EP1_CNT1 EQU CYREG_USB_SIE_EP1_CNT1\r
-USBFS_USB__SIE_EP1_CR0 EQU CYREG_USB_SIE_EP1_CR0\r
-USBFS_USB__SIE_EP2_CNT0 EQU CYREG_USB_SIE_EP2_CNT0\r
-USBFS_USB__SIE_EP2_CNT1 EQU CYREG_USB_SIE_EP2_CNT1\r
-USBFS_USB__SIE_EP2_CR0 EQU CYREG_USB_SIE_EP2_CR0\r
-USBFS_USB__SIE_EP3_CNT0 EQU CYREG_USB_SIE_EP3_CNT0\r
-USBFS_USB__SIE_EP3_CNT1 EQU CYREG_USB_SIE_EP3_CNT1\r
-USBFS_USB__SIE_EP3_CR0 EQU CYREG_USB_SIE_EP3_CR0\r
-USBFS_USB__SIE_EP4_CNT0 EQU CYREG_USB_SIE_EP4_CNT0\r
-USBFS_USB__SIE_EP4_CNT1 EQU CYREG_USB_SIE_EP4_CNT1\r
-USBFS_USB__SIE_EP4_CR0 EQU CYREG_USB_SIE_EP4_CR0\r
-USBFS_USB__SIE_EP5_CNT0 EQU CYREG_USB_SIE_EP5_CNT0\r
-USBFS_USB__SIE_EP5_CNT1 EQU CYREG_USB_SIE_EP5_CNT1\r
-USBFS_USB__SIE_EP5_CR0 EQU CYREG_USB_SIE_EP5_CR0\r
-USBFS_USB__SIE_EP6_CNT0 EQU CYREG_USB_SIE_EP6_CNT0\r
-USBFS_USB__SIE_EP6_CNT1 EQU CYREG_USB_SIE_EP6_CNT1\r
-USBFS_USB__SIE_EP6_CR0 EQU CYREG_USB_SIE_EP6_CR0\r
-USBFS_USB__SIE_EP7_CNT0 EQU CYREG_USB_SIE_EP7_CNT0\r
-USBFS_USB__SIE_EP7_CNT1 EQU CYREG_USB_SIE_EP7_CNT1\r
-USBFS_USB__SIE_EP7_CR0 EQU CYREG_USB_SIE_EP7_CR0\r
-USBFS_USB__SIE_EP8_CNT0 EQU CYREG_USB_SIE_EP8_CNT0\r
-USBFS_USB__SIE_EP8_CNT1 EQU CYREG_USB_SIE_EP8_CNT1\r
-USBFS_USB__SIE_EP8_CR0 EQU CYREG_USB_SIE_EP8_CR0\r
-USBFS_USB__SOF0 EQU CYREG_USB_SOF0\r
-USBFS_USB__SOF1 EQU CYREG_USB_SOF1\r
-USBFS_USB__USB_CLK_EN EQU CYREG_USB_USB_CLK_EN\r
-USBFS_USB__USBIO_CR0 EQU CYREG_USB_USBIO_CR0\r
-USBFS_USB__USBIO_CR1 EQU CYREG_USB_USBIO_CR1\r
-\r
-/* EXTLED */\r
-EXTLED__0__INTTYPE EQU CYREG_PICU0_INTTYPE0\r
-EXTLED__0__MASK EQU 0x01\r
-EXTLED__0__PC EQU CYREG_PRT0_PC0\r
-EXTLED__0__PORT EQU 0\r
-EXTLED__0__SHIFT EQU 0\r
-EXTLED__AG EQU CYREG_PRT0_AG\r
-EXTLED__AMUX EQU CYREG_PRT0_AMUX\r
-EXTLED__BIE EQU CYREG_PRT0_BIE\r
-EXTLED__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
-EXTLED__BYP EQU CYREG_PRT0_BYP\r
-EXTLED__CTL EQU CYREG_PRT0_CTL\r
-EXTLED__DM0 EQU CYREG_PRT0_DM0\r
-EXTLED__DM1 EQU CYREG_PRT0_DM1\r
-EXTLED__DM2 EQU CYREG_PRT0_DM2\r
-EXTLED__DR EQU CYREG_PRT0_DR\r
-EXTLED__INP_DIS EQU CYREG_PRT0_INP_DIS\r
-EXTLED__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU0_BASE\r
-EXTLED__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
-EXTLED__LCD_EN EQU CYREG_PRT0_LCD_EN\r
-EXTLED__MASK EQU 0x01\r
-EXTLED__PORT EQU 0\r
-EXTLED__PRT EQU CYREG_PRT0_PRT\r
-EXTLED__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
-EXTLED__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
-EXTLED__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
-EXTLED__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
-EXTLED__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
-EXTLED__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
-EXTLED__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
-EXTLED__PS EQU CYREG_PRT0_PS\r
-EXTLED__SHIFT EQU 0\r
-EXTLED__SLW EQU CYREG_PRT0_SLW\r
-\r
-/* SDCard_BSPIM */\r
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB05_06_ACTL\r
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB05_06_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB05_06_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB05_06_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB05_06_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB05_06_MSK\r
-SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB05_06_MSK\r
-SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB05_06_MSK\r
-SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB05_06_MSK\r
-SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB05_ACTL\r
-SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB05_CTL\r
-SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB05_ST_CTL\r
-SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB05_CTL\r
-SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB05_ST_CTL\r
-SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL\r
-SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL\r
-SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB05_MSK\r
-SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB05_06_ACTL\r
-SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB05_06_ST\r
-SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB05_MSK\r
-SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL\r
-SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB05_ACTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB05_ST_CTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB05_ST_CTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB05_ST\r
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL\r
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST\r
-SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10\r
-SDCard_BSPIM_RxStsReg__4__POS EQU 4\r
-SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20\r
-SDCard_BSPIM_RxStsReg__5__POS EQU 5\r
-SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40\r
-SDCard_BSPIM_RxStsReg__6__POS EQU 6\r
-SDCard_BSPIM_RxStsReg__MASK EQU 0x70\r
-SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB07_MSK\r
-SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL\r
-SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB07_ST\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB04_05_A0\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB04_05_A1\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B1_UDB04_05_D0\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B1_UDB04_05_D1\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B1_UDB04_05_F0\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B1_UDB04_05_F1\r
-SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B1_UDB04_A0_A1\r
-SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B1_UDB04_A0\r
-SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B1_UDB04_A1\r
-SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B1_UDB04_D0_D1\r
-SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B1_UDB04_D0\r
-SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B1_UDB04_D1\r
-SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL\r
-SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B1_UDB04_F0_F1\r
-SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B1_UDB04_F0\r
-SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B1_UDB04_F1\r
-SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01\r
-SDCard_BSPIM_TxStsReg__0__POS EQU 0\r
-SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02\r
-SDCard_BSPIM_TxStsReg__1__POS EQU 1\r
-SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL\r
-SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB06_07_ST\r
-SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04\r
-SDCard_BSPIM_TxStsReg__2__POS EQU 2\r
-SDCard_BSPIM_TxStsReg__3__MASK EQU 0x08\r
-SDCard_BSPIM_TxStsReg__3__POS EQU 3\r
-SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10\r
-SDCard_BSPIM_TxStsReg__4__POS EQU 4\r
-SDCard_BSPIM_TxStsReg__MASK EQU 0x1F\r
-SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB06_MSK\r
-SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL\r
-SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB06_ST\r
-\r
-/* SD_SCK */\r
-SD_SCK__0__INTTYPE EQU CYREG_PICU3_INTTYPE2\r
-SD_SCK__0__MASK EQU 0x04\r
-SD_SCK__0__PC EQU CYREG_PRT3_PC2\r
-SD_SCK__0__PORT EQU 3\r
-SD_SCK__0__SHIFT EQU 2\r
-SD_SCK__AG EQU CYREG_PRT3_AG\r
-SD_SCK__AMUX EQU CYREG_PRT3_AMUX\r
-SD_SCK__BIE EQU CYREG_PRT3_BIE\r
-SD_SCK__BIT_MASK EQU CYREG_PRT3_BIT_MASK\r
-SD_SCK__BYP EQU CYREG_PRT3_BYP\r
-SD_SCK__CTL EQU CYREG_PRT3_CTL\r
-SD_SCK__DM0 EQU CYREG_PRT3_DM0\r
-SD_SCK__DM1 EQU CYREG_PRT3_DM1\r
-SD_SCK__DM2 EQU CYREG_PRT3_DM2\r
-SD_SCK__DR EQU CYREG_PRT3_DR\r
-SD_SCK__INP_DIS EQU CYREG_PRT3_INP_DIS\r
-SD_SCK__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE\r
-SD_SCK__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG\r
-SD_SCK__LCD_EN EQU CYREG_PRT3_LCD_EN\r
-SD_SCK__MASK EQU 0x04\r
-SD_SCK__PORT EQU 3\r
-SD_SCK__PRT EQU CYREG_PRT3_PRT\r
-SD_SCK__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL\r
-SD_SCK__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN\r
-SD_SCK__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0\r
-SD_SCK__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1\r
-SD_SCK__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0\r
-SD_SCK__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1\r
-SD_SCK__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT\r
-SD_SCK__PS EQU CYREG_PRT3_PS\r
-SD_SCK__SHIFT EQU 2\r
-SD_SCK__SLW EQU CYREG_PRT3_SLW\r
-\r
-/* SCSI_In */\r
-SCSI_In__0__AG EQU CYREG_PRT2_AG\r
-SCSI_In__0__AMUX EQU CYREG_PRT2_AMUX\r
-SCSI_In__0__BIE EQU CYREG_PRT2_BIE\r
-SCSI_In__0__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
-SCSI_In__0__BYP EQU CYREG_PRT2_BYP\r
-SCSI_In__0__CTL EQU CYREG_PRT2_CTL\r
-SCSI_In__0__DM0 EQU CYREG_PRT2_DM0\r
-SCSI_In__0__DM1 EQU CYREG_PRT2_DM1\r
-SCSI_In__0__DM2 EQU CYREG_PRT2_DM2\r
-SCSI_In__0__DR EQU CYREG_PRT2_DR\r
-SCSI_In__0__INP_DIS EQU CYREG_PRT2_INP_DIS\r
-SCSI_In__0__INTTYPE EQU CYREG_PICU2_INTTYPE1\r
-SCSI_In__0__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
-SCSI_In__0__LCD_EN EQU CYREG_PRT2_LCD_EN\r
-SCSI_In__0__MASK EQU 0x02\r
-SCSI_In__0__PC EQU CYREG_PRT2_PC1\r
-SCSI_In__0__PORT EQU 2\r
-SCSI_In__0__PRT EQU CYREG_PRT2_PRT\r
-SCSI_In__0__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
-SCSI_In__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
-SCSI_In__0__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
-SCSI_In__0__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
-SCSI_In__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
-SCSI_In__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
-SCSI_In__0__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
-SCSI_In__0__PS EQU CYREG_PRT2_PS\r
-SCSI_In__0__SHIFT EQU 1\r
-SCSI_In__0__SLW EQU CYREG_PRT2_SLW\r
-SCSI_In__1__AG EQU CYREG_PRT4_AG\r
-SCSI_In__1__AMUX EQU CYREG_PRT4_AMUX\r
-SCSI_In__1__BIE EQU CYREG_PRT4_BIE\r
-SCSI_In__1__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
-SCSI_In__1__BYP EQU CYREG_PRT4_BYP\r
-SCSI_In__1__CTL EQU CYREG_PRT4_CTL\r
-SCSI_In__1__DM0 EQU CYREG_PRT4_DM0\r
-SCSI_In__1__DM1 EQU CYREG_PRT4_DM1\r
-SCSI_In__1__DM2 EQU CYREG_PRT4_DM2\r
-SCSI_In__1__DR EQU CYREG_PRT4_DR\r
-SCSI_In__1__INP_DIS EQU CYREG_PRT4_INP_DIS\r
-SCSI_In__1__INTTYPE EQU CYREG_PICU4_INTTYPE6\r
-SCSI_In__1__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
-SCSI_In__1__LCD_EN EQU CYREG_PRT4_LCD_EN\r
-SCSI_In__1__MASK EQU 0x40\r
-SCSI_In__1__PC EQU CYREG_PRT4_PC6\r
-SCSI_In__1__PORT EQU 4\r
-SCSI_In__1__PRT EQU CYREG_PRT4_PRT\r
-SCSI_In__1__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
-SCSI_In__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
-SCSI_In__1__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
-SCSI_In__1__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
-SCSI_In__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
-SCSI_In__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
-SCSI_In__1__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
-SCSI_In__1__PS EQU CYREG_PRT4_PS\r
-SCSI_In__1__SHIFT EQU 6\r
-SCSI_In__1__SLW EQU CYREG_PRT4_SLW\r
-SCSI_In__2__AG EQU CYREG_PRT4_AG\r
-SCSI_In__2__AMUX EQU CYREG_PRT4_AMUX\r
-SCSI_In__2__BIE EQU CYREG_PRT4_BIE\r
-SCSI_In__2__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
-SCSI_In__2__BYP EQU CYREG_PRT4_BYP\r
-SCSI_In__2__CTL EQU CYREG_PRT4_CTL\r
-SCSI_In__2__DM0 EQU CYREG_PRT4_DM0\r
-SCSI_In__2__DM1 EQU CYREG_PRT4_DM1\r
-SCSI_In__2__DM2 EQU CYREG_PRT4_DM2\r
-SCSI_In__2__DR EQU CYREG_PRT4_DR\r
-SCSI_In__2__INP_DIS EQU CYREG_PRT4_INP_DIS\r
-SCSI_In__2__INTTYPE EQU CYREG_PICU4_INTTYPE2\r
-SCSI_In__2__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
-SCSI_In__2__LCD_EN EQU CYREG_PRT4_LCD_EN\r
-SCSI_In__2__MASK EQU 0x04\r
-SCSI_In__2__PC EQU CYREG_PRT4_PC2\r
-SCSI_In__2__PORT EQU 4\r
-SCSI_In__2__PRT EQU CYREG_PRT4_PRT\r
-SCSI_In__2__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
-SCSI_In__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
-SCSI_In__2__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
-SCSI_In__2__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
-SCSI_In__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
-SCSI_In__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
-SCSI_In__2__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
-SCSI_In__2__PS EQU CYREG_PRT4_PS\r
-SCSI_In__2__SHIFT EQU 2\r
-SCSI_In__2__SLW EQU CYREG_PRT4_SLW\r
-SCSI_In__3__AG EQU CYREG_PRT0_AG\r
-SCSI_In__3__AMUX EQU CYREG_PRT0_AMUX\r
-SCSI_In__3__BIE EQU CYREG_PRT0_BIE\r
-SCSI_In__3__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
-SCSI_In__3__BYP EQU CYREG_PRT0_BYP\r
-SCSI_In__3__CTL EQU CYREG_PRT0_CTL\r
-SCSI_In__3__DM0 EQU CYREG_PRT0_DM0\r
-SCSI_In__3__DM1 EQU CYREG_PRT0_DM1\r
-SCSI_In__3__DM2 EQU CYREG_PRT0_DM2\r
-SCSI_In__3__DR EQU CYREG_PRT0_DR\r
-SCSI_In__3__INP_DIS EQU CYREG_PRT0_INP_DIS\r
-SCSI_In__3__INTTYPE EQU CYREG_PICU0_INTTYPE5\r
-SCSI_In__3__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
-SCSI_In__3__LCD_EN EQU CYREG_PRT0_LCD_EN\r
-SCSI_In__3__MASK EQU 0x20\r
-SCSI_In__3__PC EQU CYREG_PRT0_PC5\r
-SCSI_In__3__PORT EQU 0\r
-SCSI_In__3__PRT EQU CYREG_PRT0_PRT\r
-SCSI_In__3__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
-SCSI_In__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
-SCSI_In__3__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
-SCSI_In__3__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
-SCSI_In__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
-SCSI_In__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
-SCSI_In__3__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
-SCSI_In__3__PS EQU CYREG_PRT0_PS\r
-SCSI_In__3__SHIFT EQU 5\r
-SCSI_In__3__SLW EQU CYREG_PRT0_SLW\r
-SCSI_In__4__AG EQU CYREG_PRT0_AG\r
-SCSI_In__4__AMUX EQU CYREG_PRT0_AMUX\r
-SCSI_In__4__BIE EQU CYREG_PRT0_BIE\r
-SCSI_In__4__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
-SCSI_In__4__BYP EQU CYREG_PRT0_BYP\r
-SCSI_In__4__CTL EQU CYREG_PRT0_CTL\r
-SCSI_In__4__DM0 EQU CYREG_PRT0_DM0\r
-SCSI_In__4__DM1 EQU CYREG_PRT0_DM1\r
-SCSI_In__4__DM2 EQU CYREG_PRT0_DM2\r
-SCSI_In__4__DR EQU CYREG_PRT0_DR\r
-SCSI_In__4__INP_DIS EQU CYREG_PRT0_INP_DIS\r
-SCSI_In__4__INTTYPE EQU CYREG_PICU0_INTTYPE4\r
-SCSI_In__4__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
-SCSI_In__4__LCD_EN EQU CYREG_PRT0_LCD_EN\r
-SCSI_In__4__MASK EQU 0x10\r
-SCSI_In__4__PC EQU CYREG_PRT0_PC4\r
-SCSI_In__4__PORT EQU 0\r
-SCSI_In__4__PRT EQU CYREG_PRT0_PRT\r
-SCSI_In__4__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
-SCSI_In__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
-SCSI_In__4__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
-SCSI_In__4__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
-SCSI_In__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
-SCSI_In__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
-SCSI_In__4__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
-SCSI_In__4__PS EQU CYREG_PRT0_PS\r
-SCSI_In__4__SHIFT EQU 4\r
-SCSI_In__4__SLW EQU CYREG_PRT0_SLW\r
-SCSI_In__CD__AG EQU CYREG_PRT4_AG\r
-SCSI_In__CD__AMUX EQU CYREG_PRT4_AMUX\r
-SCSI_In__CD__BIE EQU CYREG_PRT4_BIE\r
-SCSI_In__CD__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
-SCSI_In__CD__BYP EQU CYREG_PRT4_BYP\r
-SCSI_In__CD__CTL EQU CYREG_PRT4_CTL\r
-SCSI_In__CD__DM0 EQU CYREG_PRT4_DM0\r
-SCSI_In__CD__DM1 EQU CYREG_PRT4_DM1\r
-SCSI_In__CD__DM2 EQU CYREG_PRT4_DM2\r
-SCSI_In__CD__DR EQU CYREG_PRT4_DR\r
-SCSI_In__CD__INP_DIS EQU CYREG_PRT4_INP_DIS\r
-SCSI_In__CD__INTTYPE EQU CYREG_PICU4_INTTYPE2\r
-SCSI_In__CD__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
-SCSI_In__CD__LCD_EN EQU CYREG_PRT4_LCD_EN\r
-SCSI_In__CD__MASK EQU 0x04\r
-SCSI_In__CD__PC EQU CYREG_PRT4_PC2\r
-SCSI_In__CD__PORT EQU 4\r
-SCSI_In__CD__PRT EQU CYREG_PRT4_PRT\r
-SCSI_In__CD__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
-SCSI_In__CD__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
-SCSI_In__CD__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
-SCSI_In__CD__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
-SCSI_In__CD__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
-SCSI_In__CD__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
-SCSI_In__CD__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
-SCSI_In__CD__PS EQU CYREG_PRT4_PS\r
-SCSI_In__CD__SHIFT EQU 2\r
-SCSI_In__CD__SLW EQU CYREG_PRT4_SLW\r
-SCSI_In__DBP__AG EQU CYREG_PRT2_AG\r
-SCSI_In__DBP__AMUX EQU CYREG_PRT2_AMUX\r
-SCSI_In__DBP__BIE EQU CYREG_PRT2_BIE\r
-SCSI_In__DBP__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
-SCSI_In__DBP__BYP EQU CYREG_PRT2_BYP\r
-SCSI_In__DBP__CTL EQU CYREG_PRT2_CTL\r
-SCSI_In__DBP__DM0 EQU CYREG_PRT2_DM0\r
-SCSI_In__DBP__DM1 EQU CYREG_PRT2_DM1\r
-SCSI_In__DBP__DM2 EQU CYREG_PRT2_DM2\r
-SCSI_In__DBP__DR EQU CYREG_PRT2_DR\r
-SCSI_In__DBP__INP_DIS EQU CYREG_PRT2_INP_DIS\r
-SCSI_In__DBP__INTTYPE EQU CYREG_PICU2_INTTYPE1\r
-SCSI_In__DBP__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
-SCSI_In__DBP__LCD_EN EQU CYREG_PRT2_LCD_EN\r
-SCSI_In__DBP__MASK EQU 0x02\r
-SCSI_In__DBP__PC EQU CYREG_PRT2_PC1\r
-SCSI_In__DBP__PORT EQU 2\r
-SCSI_In__DBP__PRT EQU CYREG_PRT2_PRT\r
-SCSI_In__DBP__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
-SCSI_In__DBP__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
-SCSI_In__DBP__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
-SCSI_In__DBP__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
-SCSI_In__DBP__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
-SCSI_In__DBP__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
-SCSI_In__DBP__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
-SCSI_In__DBP__PS EQU CYREG_PRT2_PS\r
-SCSI_In__DBP__SHIFT EQU 1\r
-SCSI_In__DBP__SLW EQU CYREG_PRT2_SLW\r
-SCSI_In__IO__AG EQU CYREG_PRT0_AG\r
-SCSI_In__IO__AMUX EQU CYREG_PRT0_AMUX\r
-SCSI_In__IO__BIE EQU CYREG_PRT0_BIE\r
-SCSI_In__IO__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
-SCSI_In__IO__BYP EQU CYREG_PRT0_BYP\r
-SCSI_In__IO__CTL EQU CYREG_PRT0_CTL\r
-SCSI_In__IO__DM0 EQU CYREG_PRT0_DM0\r
-SCSI_In__IO__DM1 EQU CYREG_PRT0_DM1\r
-SCSI_In__IO__DM2 EQU CYREG_PRT0_DM2\r
-SCSI_In__IO__DR EQU CYREG_PRT0_DR\r
-SCSI_In__IO__INP_DIS EQU CYREG_PRT0_INP_DIS\r
-SCSI_In__IO__INTTYPE EQU CYREG_PICU0_INTTYPE4\r
-SCSI_In__IO__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
-SCSI_In__IO__LCD_EN EQU CYREG_PRT0_LCD_EN\r
-SCSI_In__IO__MASK EQU 0x10\r
-SCSI_In__IO__PC EQU CYREG_PRT0_PC4\r
-SCSI_In__IO__PORT EQU 0\r
-SCSI_In__IO__PRT EQU CYREG_PRT0_PRT\r
-SCSI_In__IO__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
-SCSI_In__IO__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
-SCSI_In__IO__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
-SCSI_In__IO__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
-SCSI_In__IO__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
-SCSI_In__IO__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
-SCSI_In__IO__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
-SCSI_In__IO__PS EQU CYREG_PRT0_PS\r
-SCSI_In__IO__SHIFT EQU 4\r
-SCSI_In__IO__SLW EQU CYREG_PRT0_SLW\r
-SCSI_In__MSG__AG EQU CYREG_PRT4_AG\r
-SCSI_In__MSG__AMUX EQU CYREG_PRT4_AMUX\r
-SCSI_In__MSG__BIE EQU CYREG_PRT4_BIE\r
-SCSI_In__MSG__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
-SCSI_In__MSG__BYP EQU CYREG_PRT4_BYP\r
-SCSI_In__MSG__CTL EQU CYREG_PRT4_CTL\r
-SCSI_In__MSG__DM0 EQU CYREG_PRT4_DM0\r
-SCSI_In__MSG__DM1 EQU CYREG_PRT4_DM1\r
-SCSI_In__MSG__DM2 EQU CYREG_PRT4_DM2\r
-SCSI_In__MSG__DR EQU CYREG_PRT4_DR\r
-SCSI_In__MSG__INP_DIS EQU CYREG_PRT4_INP_DIS\r
-SCSI_In__MSG__INTTYPE EQU CYREG_PICU4_INTTYPE6\r
-SCSI_In__MSG__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
-SCSI_In__MSG__LCD_EN EQU CYREG_PRT4_LCD_EN\r
-SCSI_In__MSG__MASK EQU 0x40\r
-SCSI_In__MSG__PC EQU CYREG_PRT4_PC6\r
-SCSI_In__MSG__PORT EQU 4\r
-SCSI_In__MSG__PRT EQU CYREG_PRT4_PRT\r
-SCSI_In__MSG__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
-SCSI_In__MSG__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
-SCSI_In__MSG__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
-SCSI_In__MSG__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
-SCSI_In__MSG__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
-SCSI_In__MSG__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
-SCSI_In__MSG__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
-SCSI_In__MSG__PS EQU CYREG_PRT4_PS\r
-SCSI_In__MSG__SHIFT EQU 6\r
-SCSI_In__MSG__SLW EQU CYREG_PRT4_SLW\r
-SCSI_In__REQ__AG EQU CYREG_PRT0_AG\r
-SCSI_In__REQ__AMUX EQU CYREG_PRT0_AMUX\r
-SCSI_In__REQ__BIE EQU CYREG_PRT0_BIE\r
-SCSI_In__REQ__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
-SCSI_In__REQ__BYP EQU CYREG_PRT0_BYP\r
-SCSI_In__REQ__CTL EQU CYREG_PRT0_CTL\r
-SCSI_In__REQ__DM0 EQU CYREG_PRT0_DM0\r
-SCSI_In__REQ__DM1 EQU CYREG_PRT0_DM1\r
-SCSI_In__REQ__DM2 EQU CYREG_PRT0_DM2\r
-SCSI_In__REQ__DR EQU CYREG_PRT0_DR\r
-SCSI_In__REQ__INP_DIS EQU CYREG_PRT0_INP_DIS\r
-SCSI_In__REQ__INTTYPE EQU CYREG_PICU0_INTTYPE5\r
-SCSI_In__REQ__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
-SCSI_In__REQ__LCD_EN EQU CYREG_PRT0_LCD_EN\r
-SCSI_In__REQ__MASK EQU 0x20\r
-SCSI_In__REQ__PC EQU CYREG_PRT0_PC5\r
-SCSI_In__REQ__PORT EQU 0\r
-SCSI_In__REQ__PRT EQU CYREG_PRT0_PRT\r
-SCSI_In__REQ__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
-SCSI_In__REQ__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
-SCSI_In__REQ__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
-SCSI_In__REQ__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
-SCSI_In__REQ__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
-SCSI_In__REQ__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
-SCSI_In__REQ__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
-SCSI_In__REQ__PS EQU CYREG_PRT0_PS\r
-SCSI_In__REQ__SHIFT EQU 5\r
-SCSI_In__REQ__SLW EQU CYREG_PRT0_SLW\r
-\r
-/* SCSI_In_DBx */\r
-SCSI_In_DBx__0__AG EQU CYREG_PRT5_AG\r
-SCSI_In_DBx__0__AMUX EQU CYREG_PRT5_AMUX\r
-SCSI_In_DBx__0__BIE EQU CYREG_PRT5_BIE\r
-SCSI_In_DBx__0__BIT_MASK EQU CYREG_PRT5_BIT_MASK\r
-SCSI_In_DBx__0__BYP EQU CYREG_PRT5_BYP\r
-SCSI_In_DBx__0__CTL EQU CYREG_PRT5_CTL\r
-SCSI_In_DBx__0__DM0 EQU CYREG_PRT5_DM0\r
-SCSI_In_DBx__0__DM1 EQU CYREG_PRT5_DM1\r
-SCSI_In_DBx__0__DM2 EQU CYREG_PRT5_DM2\r
-SCSI_In_DBx__0__DR EQU CYREG_PRT5_DR\r
-SCSI_In_DBx__0__INP_DIS EQU CYREG_PRT5_INP_DIS\r
-SCSI_In_DBx__0__INTTYPE EQU CYREG_PICU5_INTTYPE3\r
-SCSI_In_DBx__0__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG\r
-SCSI_In_DBx__0__LCD_EN EQU CYREG_PRT5_LCD_EN\r
-SCSI_In_DBx__0__MASK EQU 0x08\r
-SCSI_In_DBx__0__PC EQU CYREG_PRT5_PC3\r
-SCSI_In_DBx__0__PORT EQU 5\r
-SCSI_In_DBx__0__PRT EQU CYREG_PRT5_PRT\r
-SCSI_In_DBx__0__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL\r
-SCSI_In_DBx__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN\r
-SCSI_In_DBx__0__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0\r
-SCSI_In_DBx__0__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1\r
-SCSI_In_DBx__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0\r
-SCSI_In_DBx__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1\r
-SCSI_In_DBx__0__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT\r
-SCSI_In_DBx__0__PS EQU CYREG_PRT5_PS\r
-SCSI_In_DBx__0__SHIFT EQU 3\r
-SCSI_In_DBx__0__SLW EQU CYREG_PRT5_SLW\r
-SCSI_In_DBx__1__AG EQU CYREG_PRT5_AG\r
-SCSI_In_DBx__1__AMUX EQU CYREG_PRT5_AMUX\r
-SCSI_In_DBx__1__BIE EQU CYREG_PRT5_BIE\r
-SCSI_In_DBx__1__BIT_MASK EQU CYREG_PRT5_BIT_MASK\r
-SCSI_In_DBx__1__BYP EQU CYREG_PRT5_BYP\r
-SCSI_In_DBx__1__CTL EQU CYREG_PRT5_CTL\r
-SCSI_In_DBx__1__DM0 EQU CYREG_PRT5_DM0\r
-SCSI_In_DBx__1__DM1 EQU CYREG_PRT5_DM1\r
-SCSI_In_DBx__1__DM2 EQU CYREG_PRT5_DM2\r
-SCSI_In_DBx__1__DR EQU CYREG_PRT5_DR\r
-SCSI_In_DBx__1__INP_DIS EQU CYREG_PRT5_INP_DIS\r
-SCSI_In_DBx__1__INTTYPE EQU CYREG_PICU5_INTTYPE2\r
-SCSI_In_DBx__1__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG\r
-SCSI_In_DBx__1__LCD_EN EQU CYREG_PRT5_LCD_EN\r
-SCSI_In_DBx__1__MASK EQU 0x04\r
-SCSI_In_DBx__1__PC EQU CYREG_PRT5_PC2\r
-SCSI_In_DBx__1__PORT EQU 5\r
-SCSI_In_DBx__1__PRT EQU CYREG_PRT5_PRT\r
-SCSI_In_DBx__1__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL\r
-SCSI_In_DBx__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN\r
-SCSI_In_DBx__1__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0\r
-SCSI_In_DBx__1__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1\r
-SCSI_In_DBx__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0\r
-SCSI_In_DBx__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1\r
-SCSI_In_DBx__1__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT\r
-SCSI_In_DBx__1__PS EQU CYREG_PRT5_PS\r
-SCSI_In_DBx__1__SHIFT EQU 2\r
-SCSI_In_DBx__1__SLW EQU CYREG_PRT5_SLW\r
-SCSI_In_DBx__2__AG EQU CYREG_PRT6_AG\r
-SCSI_In_DBx__2__AMUX EQU CYREG_PRT6_AMUX\r
-SCSI_In_DBx__2__BIE EQU CYREG_PRT6_BIE\r
-SCSI_In_DBx__2__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
-SCSI_In_DBx__2__BYP EQU CYREG_PRT6_BYP\r
-SCSI_In_DBx__2__CTL EQU CYREG_PRT6_CTL\r
-SCSI_In_DBx__2__DM0 EQU CYREG_PRT6_DM0\r
-SCSI_In_DBx__2__DM1 EQU CYREG_PRT6_DM1\r
-SCSI_In_DBx__2__DM2 EQU CYREG_PRT6_DM2\r
-SCSI_In_DBx__2__DR EQU CYREG_PRT6_DR\r
-SCSI_In_DBx__2__INP_DIS EQU CYREG_PRT6_INP_DIS\r
-SCSI_In_DBx__2__INTTYPE EQU CYREG_PICU6_INTTYPE7\r
-SCSI_In_DBx__2__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
-SCSI_In_DBx__2__LCD_EN EQU CYREG_PRT6_LCD_EN\r
-SCSI_In_DBx__2__MASK EQU 0x80\r
-SCSI_In_DBx__2__PC EQU CYREG_PRT6_PC7\r
-SCSI_In_DBx__2__PORT EQU 6\r
-SCSI_In_DBx__2__PRT EQU CYREG_PRT6_PRT\r
-SCSI_In_DBx__2__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
-SCSI_In_DBx__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
-SCSI_In_DBx__2__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
-SCSI_In_DBx__2__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
-SCSI_In_DBx__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
-SCSI_In_DBx__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
-SCSI_In_DBx__2__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
-SCSI_In_DBx__2__PS EQU CYREG_PRT6_PS\r
-SCSI_In_DBx__2__SHIFT EQU 7\r
-SCSI_In_DBx__2__SLW EQU CYREG_PRT6_SLW\r
-SCSI_In_DBx__3__AG EQU CYREG_PRT6_AG\r
-SCSI_In_DBx__3__AMUX EQU CYREG_PRT6_AMUX\r
-SCSI_In_DBx__3__BIE EQU CYREG_PRT6_BIE\r
-SCSI_In_DBx__3__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
-SCSI_In_DBx__3__BYP EQU CYREG_PRT6_BYP\r
-SCSI_In_DBx__3__CTL EQU CYREG_PRT6_CTL\r
-SCSI_In_DBx__3__DM0 EQU CYREG_PRT6_DM0\r
-SCSI_In_DBx__3__DM1 EQU CYREG_PRT6_DM1\r
-SCSI_In_DBx__3__DM2 EQU CYREG_PRT6_DM2\r
-SCSI_In_DBx__3__DR EQU CYREG_PRT6_DR\r
-SCSI_In_DBx__3__INP_DIS EQU CYREG_PRT6_INP_DIS\r
-SCSI_In_DBx__3__INTTYPE EQU CYREG_PICU6_INTTYPE6\r
-SCSI_In_DBx__3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
-SCSI_In_DBx__3__LCD_EN EQU CYREG_PRT6_LCD_EN\r
-SCSI_In_DBx__3__MASK EQU 0x40\r
-SCSI_In_DBx__3__PC EQU CYREG_PRT6_PC6\r
-SCSI_In_DBx__3__PORT EQU 6\r
-SCSI_In_DBx__3__PRT EQU CYREG_PRT6_PRT\r
-SCSI_In_DBx__3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
-SCSI_In_DBx__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
-SCSI_In_DBx__3__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
-SCSI_In_DBx__3__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
-SCSI_In_DBx__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
-SCSI_In_DBx__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
-SCSI_In_DBx__3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
-SCSI_In_DBx__3__PS EQU CYREG_PRT6_PS\r
-SCSI_In_DBx__3__SHIFT EQU 6\r
-SCSI_In_DBx__3__SLW EQU CYREG_PRT6_SLW\r
-SCSI_In_DBx__4__AG EQU CYREG_PRT12_AG\r
-SCSI_In_DBx__4__BIE EQU CYREG_PRT12_BIE\r
-SCSI_In_DBx__4__BIT_MASK EQU CYREG_PRT12_BIT_MASK\r
-SCSI_In_DBx__4__BYP EQU CYREG_PRT12_BYP\r
-SCSI_In_DBx__4__DM0 EQU CYREG_PRT12_DM0\r
-SCSI_In_DBx__4__DM1 EQU CYREG_PRT12_DM1\r
-SCSI_In_DBx__4__DM2 EQU CYREG_PRT12_DM2\r
-SCSI_In_DBx__4__DR EQU CYREG_PRT12_DR\r
-SCSI_In_DBx__4__INP_DIS EQU CYREG_PRT12_INP_DIS\r
-SCSI_In_DBx__4__INTTYPE EQU CYREG_PICU12_INTTYPE5\r
-SCSI_In_DBx__4__MASK EQU 0x20\r
-SCSI_In_DBx__4__PC EQU CYREG_PRT12_PC5\r
-SCSI_In_DBx__4__PORT EQU 12\r
-SCSI_In_DBx__4__PRT EQU CYREG_PRT12_PRT\r
-SCSI_In_DBx__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN\r
-SCSI_In_DBx__4__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0\r
-SCSI_In_DBx__4__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1\r
-SCSI_In_DBx__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0\r
-SCSI_In_DBx__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1\r
-SCSI_In_DBx__4__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT\r
-SCSI_In_DBx__4__PS EQU CYREG_PRT12_PS\r
-SCSI_In_DBx__4__SHIFT EQU 5\r
-SCSI_In_DBx__4__SIO_CFG EQU CYREG_PRT12_SIO_CFG\r
-SCSI_In_DBx__4__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF\r
-SCSI_In_DBx__4__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN\r
-SCSI_In_DBx__4__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ\r
-SCSI_In_DBx__4__SLW EQU CYREG_PRT12_SLW\r
-SCSI_In_DBx__5__AG EQU CYREG_PRT12_AG\r
-SCSI_In_DBx__5__BIE EQU CYREG_PRT12_BIE\r
-SCSI_In_DBx__5__BIT_MASK EQU CYREG_PRT12_BIT_MASK\r
-SCSI_In_DBx__5__BYP EQU CYREG_PRT12_BYP\r
-SCSI_In_DBx__5__DM0 EQU CYREG_PRT12_DM0\r
-SCSI_In_DBx__5__DM1 EQU CYREG_PRT12_DM1\r
-SCSI_In_DBx__5__DM2 EQU CYREG_PRT12_DM2\r
-SCSI_In_DBx__5__DR EQU CYREG_PRT12_DR\r
-SCSI_In_DBx__5__INP_DIS EQU CYREG_PRT12_INP_DIS\r
-SCSI_In_DBx__5__INTTYPE EQU CYREG_PICU12_INTTYPE4\r
-SCSI_In_DBx__5__MASK EQU 0x10\r
-SCSI_In_DBx__5__PC EQU CYREG_PRT12_PC4\r
-SCSI_In_DBx__5__PORT EQU 12\r
-SCSI_In_DBx__5__PRT EQU CYREG_PRT12_PRT\r
-SCSI_In_DBx__5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN\r
-SCSI_In_DBx__5__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0\r
-SCSI_In_DBx__5__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1\r
-SCSI_In_DBx__5__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0\r
-SCSI_In_DBx__5__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1\r
-SCSI_In_DBx__5__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT\r
-SCSI_In_DBx__5__PS EQU CYREG_PRT12_PS\r
-SCSI_In_DBx__5__SHIFT EQU 4\r
-SCSI_In_DBx__5__SIO_CFG EQU CYREG_PRT12_SIO_CFG\r
-SCSI_In_DBx__5__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF\r
-SCSI_In_DBx__5__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN\r
-SCSI_In_DBx__5__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ\r
-SCSI_In_DBx__5__SLW EQU CYREG_PRT12_SLW\r
-SCSI_In_DBx__6__AG EQU CYREG_PRT2_AG\r
-SCSI_In_DBx__6__AMUX EQU CYREG_PRT2_AMUX\r
-SCSI_In_DBx__6__BIE EQU CYREG_PRT2_BIE\r
-SCSI_In_DBx__6__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
-SCSI_In_DBx__6__BYP EQU CYREG_PRT2_BYP\r
-SCSI_In_DBx__6__CTL EQU CYREG_PRT2_CTL\r
-SCSI_In_DBx__6__DM0 EQU CYREG_PRT2_DM0\r
-SCSI_In_DBx__6__DM1 EQU CYREG_PRT2_DM1\r
-SCSI_In_DBx__6__DM2 EQU CYREG_PRT2_DM2\r
-SCSI_In_DBx__6__DR EQU CYREG_PRT2_DR\r
-SCSI_In_DBx__6__INP_DIS EQU CYREG_PRT2_INP_DIS\r
-SCSI_In_DBx__6__INTTYPE EQU CYREG_PICU2_INTTYPE5\r
-SCSI_In_DBx__6__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
-SCSI_In_DBx__6__LCD_EN EQU CYREG_PRT2_LCD_EN\r
-SCSI_In_DBx__6__MASK EQU 0x20\r
-SCSI_In_DBx__6__PC EQU CYREG_PRT2_PC5\r
-SCSI_In_DBx__6__PORT EQU 2\r
-SCSI_In_DBx__6__PRT EQU CYREG_PRT2_PRT\r
-SCSI_In_DBx__6__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
-SCSI_In_DBx__6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
-SCSI_In_DBx__6__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
-SCSI_In_DBx__6__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
-SCSI_In_DBx__6__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
-SCSI_In_DBx__6__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
-SCSI_In_DBx__6__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
-SCSI_In_DBx__6__PS EQU CYREG_PRT2_PS\r
-SCSI_In_DBx__6__SHIFT EQU 5\r
-SCSI_In_DBx__6__SLW EQU CYREG_PRT2_SLW\r
-SCSI_In_DBx__7__AG EQU CYREG_PRT2_AG\r
-SCSI_In_DBx__7__AMUX EQU CYREG_PRT2_AMUX\r
-SCSI_In_DBx__7__BIE EQU CYREG_PRT2_BIE\r
-SCSI_In_DBx__7__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
-SCSI_In_DBx__7__BYP EQU CYREG_PRT2_BYP\r
-SCSI_In_DBx__7__CTL EQU CYREG_PRT2_CTL\r
-SCSI_In_DBx__7__DM0 EQU CYREG_PRT2_DM0\r
-SCSI_In_DBx__7__DM1 EQU CYREG_PRT2_DM1\r
-SCSI_In_DBx__7__DM2 EQU CYREG_PRT2_DM2\r
-SCSI_In_DBx__7__DR EQU CYREG_PRT2_DR\r
-SCSI_In_DBx__7__INP_DIS EQU CYREG_PRT2_INP_DIS\r
-SCSI_In_DBx__7__INTTYPE EQU CYREG_PICU2_INTTYPE4\r
-SCSI_In_DBx__7__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
-SCSI_In_DBx__7__LCD_EN EQU CYREG_PRT2_LCD_EN\r
-SCSI_In_DBx__7__MASK EQU 0x10\r
-SCSI_In_DBx__7__PC EQU CYREG_PRT2_PC4\r
-SCSI_In_DBx__7__PORT EQU 2\r
-SCSI_In_DBx__7__PRT EQU CYREG_PRT2_PRT\r
-SCSI_In_DBx__7__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
-SCSI_In_DBx__7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
-SCSI_In_DBx__7__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
-SCSI_In_DBx__7__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
-SCSI_In_DBx__7__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
-SCSI_In_DBx__7__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
-SCSI_In_DBx__7__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
-SCSI_In_DBx__7__PS EQU CYREG_PRT2_PS\r
-SCSI_In_DBx__7__SHIFT EQU 4\r
-SCSI_In_DBx__7__SLW EQU CYREG_PRT2_SLW\r
-SCSI_In_DBx__DB0__AG EQU CYREG_PRT5_AG\r
-SCSI_In_DBx__DB0__AMUX EQU CYREG_PRT5_AMUX\r
-SCSI_In_DBx__DB0__BIE EQU CYREG_PRT5_BIE\r
-SCSI_In_DBx__DB0__BIT_MASK EQU CYREG_PRT5_BIT_MASK\r
-SCSI_In_DBx__DB0__BYP EQU CYREG_PRT5_BYP\r
-SCSI_In_DBx__DB0__CTL EQU CYREG_PRT5_CTL\r
-SCSI_In_DBx__DB0__DM0 EQU CYREG_PRT5_DM0\r
-SCSI_In_DBx__DB0__DM1 EQU CYREG_PRT5_DM1\r
-SCSI_In_DBx__DB0__DM2 EQU CYREG_PRT5_DM2\r
-SCSI_In_DBx__DB0__DR EQU CYREG_PRT5_DR\r
-SCSI_In_DBx__DB0__INP_DIS EQU CYREG_PRT5_INP_DIS\r
-SCSI_In_DBx__DB0__INTTYPE EQU CYREG_PICU5_INTTYPE3\r
-SCSI_In_DBx__DB0__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG\r
-SCSI_In_DBx__DB0__LCD_EN EQU CYREG_PRT5_LCD_EN\r
-SCSI_In_DBx__DB0__MASK EQU 0x08\r
-SCSI_In_DBx__DB0__PC EQU CYREG_PRT5_PC3\r
-SCSI_In_DBx__DB0__PORT EQU 5\r
-SCSI_In_DBx__DB0__PRT EQU CYREG_PRT5_PRT\r
-SCSI_In_DBx__DB0__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL\r
-SCSI_In_DBx__DB0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN\r
-SCSI_In_DBx__DB0__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0\r
-SCSI_In_DBx__DB0__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1\r
-SCSI_In_DBx__DB0__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0\r
-SCSI_In_DBx__DB0__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1\r
-SCSI_In_DBx__DB0__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT\r
-SCSI_In_DBx__DB0__PS EQU CYREG_PRT5_PS\r
-SCSI_In_DBx__DB0__SHIFT EQU 3\r
-SCSI_In_DBx__DB0__SLW EQU CYREG_PRT5_SLW\r
-SCSI_In_DBx__DB1__AG EQU CYREG_PRT5_AG\r
-SCSI_In_DBx__DB1__AMUX EQU CYREG_PRT5_AMUX\r
-SCSI_In_DBx__DB1__BIE EQU CYREG_PRT5_BIE\r
-SCSI_In_DBx__DB1__BIT_MASK EQU CYREG_PRT5_BIT_MASK\r
-SCSI_In_DBx__DB1__BYP EQU CYREG_PRT5_BYP\r
-SCSI_In_DBx__DB1__CTL EQU CYREG_PRT5_CTL\r
-SCSI_In_DBx__DB1__DM0 EQU CYREG_PRT5_DM0\r
-SCSI_In_DBx__DB1__DM1 EQU CYREG_PRT5_DM1\r
-SCSI_In_DBx__DB1__DM2 EQU CYREG_PRT5_DM2\r
-SCSI_In_DBx__DB1__DR EQU CYREG_PRT5_DR\r
-SCSI_In_DBx__DB1__INP_DIS EQU CYREG_PRT5_INP_DIS\r
-SCSI_In_DBx__DB1__INTTYPE EQU CYREG_PICU5_INTTYPE2\r
-SCSI_In_DBx__DB1__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG\r
-SCSI_In_DBx__DB1__LCD_EN EQU CYREG_PRT5_LCD_EN\r
-SCSI_In_DBx__DB1__MASK EQU 0x04\r
-SCSI_In_DBx__DB1__PC EQU CYREG_PRT5_PC2\r
-SCSI_In_DBx__DB1__PORT EQU 5\r
-SCSI_In_DBx__DB1__PRT EQU CYREG_PRT5_PRT\r
-SCSI_In_DBx__DB1__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL\r
-SCSI_In_DBx__DB1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN\r
-SCSI_In_DBx__DB1__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0\r
-SCSI_In_DBx__DB1__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1\r
-SCSI_In_DBx__DB1__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0\r
-SCSI_In_DBx__DB1__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1\r
-SCSI_In_DBx__DB1__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT\r
-SCSI_In_DBx__DB1__PS EQU CYREG_PRT5_PS\r
-SCSI_In_DBx__DB1__SHIFT EQU 2\r
-SCSI_In_DBx__DB1__SLW EQU CYREG_PRT5_SLW\r
-SCSI_In_DBx__DB2__AG EQU CYREG_PRT6_AG\r
-SCSI_In_DBx__DB2__AMUX EQU CYREG_PRT6_AMUX\r
-SCSI_In_DBx__DB2__BIE EQU CYREG_PRT6_BIE\r
-SCSI_In_DBx__DB2__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
-SCSI_In_DBx__DB2__BYP EQU CYREG_PRT6_BYP\r
-SCSI_In_DBx__DB2__CTL EQU CYREG_PRT6_CTL\r
-SCSI_In_DBx__DB2__DM0 EQU CYREG_PRT6_DM0\r
-SCSI_In_DBx__DB2__DM1 EQU CYREG_PRT6_DM1\r
-SCSI_In_DBx__DB2__DM2 EQU CYREG_PRT6_DM2\r
-SCSI_In_DBx__DB2__DR EQU CYREG_PRT6_DR\r
-SCSI_In_DBx__DB2__INP_DIS EQU CYREG_PRT6_INP_DIS\r
-SCSI_In_DBx__DB2__INTTYPE EQU CYREG_PICU6_INTTYPE7\r
-SCSI_In_DBx__DB2__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
-SCSI_In_DBx__DB2__LCD_EN EQU CYREG_PRT6_LCD_EN\r
-SCSI_In_DBx__DB2__MASK EQU 0x80\r
-SCSI_In_DBx__DB2__PC EQU CYREG_PRT6_PC7\r
-SCSI_In_DBx__DB2__PORT EQU 6\r
-SCSI_In_DBx__DB2__PRT EQU CYREG_PRT6_PRT\r
-SCSI_In_DBx__DB2__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
-SCSI_In_DBx__DB2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
-SCSI_In_DBx__DB2__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
-SCSI_In_DBx__DB2__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
-SCSI_In_DBx__DB2__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
-SCSI_In_DBx__DB2__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
-SCSI_In_DBx__DB2__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
-SCSI_In_DBx__DB2__PS EQU CYREG_PRT6_PS\r
-SCSI_In_DBx__DB2__SHIFT EQU 7\r
-SCSI_In_DBx__DB2__SLW EQU CYREG_PRT6_SLW\r
-SCSI_In_DBx__DB3__AG EQU CYREG_PRT6_AG\r
-SCSI_In_DBx__DB3__AMUX EQU CYREG_PRT6_AMUX\r
-SCSI_In_DBx__DB3__BIE EQU CYREG_PRT6_BIE\r
-SCSI_In_DBx__DB3__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
-SCSI_In_DBx__DB3__BYP EQU CYREG_PRT6_BYP\r
-SCSI_In_DBx__DB3__CTL EQU CYREG_PRT6_CTL\r
-SCSI_In_DBx__DB3__DM0 EQU CYREG_PRT6_DM0\r
-SCSI_In_DBx__DB3__DM1 EQU CYREG_PRT6_DM1\r
-SCSI_In_DBx__DB3__DM2 EQU CYREG_PRT6_DM2\r
-SCSI_In_DBx__DB3__DR EQU CYREG_PRT6_DR\r
-SCSI_In_DBx__DB3__INP_DIS EQU CYREG_PRT6_INP_DIS\r
-SCSI_In_DBx__DB3__INTTYPE EQU CYREG_PICU6_INTTYPE6\r
-SCSI_In_DBx__DB3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
-SCSI_In_DBx__DB3__LCD_EN EQU CYREG_PRT6_LCD_EN\r
-SCSI_In_DBx__DB3__MASK EQU 0x40\r
-SCSI_In_DBx__DB3__PC EQU CYREG_PRT6_PC6\r
-SCSI_In_DBx__DB3__PORT EQU 6\r
-SCSI_In_DBx__DB3__PRT EQU CYREG_PRT6_PRT\r
-SCSI_In_DBx__DB3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
-SCSI_In_DBx__DB3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
-SCSI_In_DBx__DB3__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
-SCSI_In_DBx__DB3__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
-SCSI_In_DBx__DB3__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
-SCSI_In_DBx__DB3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
-SCSI_In_DBx__DB3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
-SCSI_In_DBx__DB3__PS EQU CYREG_PRT6_PS\r
-SCSI_In_DBx__DB3__SHIFT EQU 6\r
-SCSI_In_DBx__DB3__SLW EQU CYREG_PRT6_SLW\r
-SCSI_In_DBx__DB4__AG EQU CYREG_PRT12_AG\r
-SCSI_In_DBx__DB4__BIE EQU CYREG_PRT12_BIE\r
-SCSI_In_DBx__DB4__BIT_MASK EQU CYREG_PRT12_BIT_MASK\r
-SCSI_In_DBx__DB4__BYP EQU CYREG_PRT12_BYP\r
-SCSI_In_DBx__DB4__DM0 EQU CYREG_PRT12_DM0\r
-SCSI_In_DBx__DB4__DM1 EQU CYREG_PRT12_DM1\r
-SCSI_In_DBx__DB4__DM2 EQU CYREG_PRT12_DM2\r
-SCSI_In_DBx__DB4__DR EQU CYREG_PRT12_DR\r
-SCSI_In_DBx__DB4__INP_DIS EQU CYREG_PRT12_INP_DIS\r
-SCSI_In_DBx__DB4__INTTYPE EQU CYREG_PICU12_INTTYPE5\r
-SCSI_In_DBx__DB4__MASK EQU 0x20\r
-SCSI_In_DBx__DB4__PC EQU CYREG_PRT12_PC5\r
-SCSI_In_DBx__DB4__PORT EQU 12\r
-SCSI_In_DBx__DB4__PRT EQU CYREG_PRT12_PRT\r
-SCSI_In_DBx__DB4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN\r
-SCSI_In_DBx__DB4__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0\r
-SCSI_In_DBx__DB4__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1\r
-SCSI_In_DBx__DB4__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0\r
-SCSI_In_DBx__DB4__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1\r
-SCSI_In_DBx__DB4__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT\r
-SCSI_In_DBx__DB4__PS EQU CYREG_PRT12_PS\r
-SCSI_In_DBx__DB4__SHIFT EQU 5\r
-SCSI_In_DBx__DB4__SIO_CFG EQU CYREG_PRT12_SIO_CFG\r
-SCSI_In_DBx__DB4__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF\r
-SCSI_In_DBx__DB4__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN\r
-SCSI_In_DBx__DB4__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ\r
-SCSI_In_DBx__DB4__SLW EQU CYREG_PRT12_SLW\r
-SCSI_In_DBx__DB5__AG EQU CYREG_PRT12_AG\r
-SCSI_In_DBx__DB5__BIE EQU CYREG_PRT12_BIE\r
-SCSI_In_DBx__DB5__BIT_MASK EQU CYREG_PRT12_BIT_MASK\r
-SCSI_In_DBx__DB5__BYP EQU CYREG_PRT12_BYP\r
-SCSI_In_DBx__DB5__DM0 EQU CYREG_PRT12_DM0\r
-SCSI_In_DBx__DB5__DM1 EQU CYREG_PRT12_DM1\r
-SCSI_In_DBx__DB5__DM2 EQU CYREG_PRT12_DM2\r
-SCSI_In_DBx__DB5__DR EQU CYREG_PRT12_DR\r
-SCSI_In_DBx__DB5__INP_DIS EQU CYREG_PRT12_INP_DIS\r
-SCSI_In_DBx__DB5__INTTYPE EQU CYREG_PICU12_INTTYPE4\r
-SCSI_In_DBx__DB5__MASK EQU 0x10\r
-SCSI_In_DBx__DB5__PC EQU CYREG_PRT12_PC4\r
-SCSI_In_DBx__DB5__PORT EQU 12\r
-SCSI_In_DBx__DB5__PRT EQU CYREG_PRT12_PRT\r
-SCSI_In_DBx__DB5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN\r
-SCSI_In_DBx__DB5__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0\r
-SCSI_In_DBx__DB5__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1\r
-SCSI_In_DBx__DB5__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0\r
-SCSI_In_DBx__DB5__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1\r
-SCSI_In_DBx__DB5__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT\r
-SCSI_In_DBx__DB5__PS EQU CYREG_PRT12_PS\r
-SCSI_In_DBx__DB5__SHIFT EQU 4\r
-SCSI_In_DBx__DB5__SIO_CFG EQU CYREG_PRT12_SIO_CFG\r
-SCSI_In_DBx__DB5__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF\r
-SCSI_In_DBx__DB5__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN\r
-SCSI_In_DBx__DB5__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ\r
-SCSI_In_DBx__DB5__SLW EQU CYREG_PRT12_SLW\r
-SCSI_In_DBx__DB6__AG EQU CYREG_PRT2_AG\r
-SCSI_In_DBx__DB6__AMUX EQU CYREG_PRT2_AMUX\r
-SCSI_In_DBx__DB6__BIE EQU CYREG_PRT2_BIE\r
-SCSI_In_DBx__DB6__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
-SCSI_In_DBx__DB6__BYP EQU CYREG_PRT2_BYP\r
-SCSI_In_DBx__DB6__CTL EQU CYREG_PRT2_CTL\r
-SCSI_In_DBx__DB6__DM0 EQU CYREG_PRT2_DM0\r
-SCSI_In_DBx__DB6__DM1 EQU CYREG_PRT2_DM1\r
-SCSI_In_DBx__DB6__DM2 EQU CYREG_PRT2_DM2\r
-SCSI_In_DBx__DB6__DR EQU CYREG_PRT2_DR\r
-SCSI_In_DBx__DB6__INP_DIS EQU CYREG_PRT2_INP_DIS\r
-SCSI_In_DBx__DB6__INTTYPE EQU CYREG_PICU2_INTTYPE5\r
-SCSI_In_DBx__DB6__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
-SCSI_In_DBx__DB6__LCD_EN EQU CYREG_PRT2_LCD_EN\r
-SCSI_In_DBx__DB6__MASK EQU 0x20\r
-SCSI_In_DBx__DB6__PC EQU CYREG_PRT2_PC5\r
-SCSI_In_DBx__DB6__PORT EQU 2\r
-SCSI_In_DBx__DB6__PRT EQU CYREG_PRT2_PRT\r
-SCSI_In_DBx__DB6__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
-SCSI_In_DBx__DB6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
-SCSI_In_DBx__DB6__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
-SCSI_In_DBx__DB6__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
-SCSI_In_DBx__DB6__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
-SCSI_In_DBx__DB6__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
-SCSI_In_DBx__DB6__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
-SCSI_In_DBx__DB6__PS EQU CYREG_PRT2_PS\r
-SCSI_In_DBx__DB6__SHIFT EQU 5\r
-SCSI_In_DBx__DB6__SLW EQU CYREG_PRT2_SLW\r
-SCSI_In_DBx__DB7__AG EQU CYREG_PRT2_AG\r
-SCSI_In_DBx__DB7__AMUX EQU CYREG_PRT2_AMUX\r
-SCSI_In_DBx__DB7__BIE EQU CYREG_PRT2_BIE\r
-SCSI_In_DBx__DB7__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
-SCSI_In_DBx__DB7__BYP EQU CYREG_PRT2_BYP\r
-SCSI_In_DBx__DB7__CTL EQU CYREG_PRT2_CTL\r
-SCSI_In_DBx__DB7__DM0 EQU CYREG_PRT2_DM0\r
-SCSI_In_DBx__DB7__DM1 EQU CYREG_PRT2_DM1\r
-SCSI_In_DBx__DB7__DM2 EQU CYREG_PRT2_DM2\r
-SCSI_In_DBx__DB7__DR EQU CYREG_PRT2_DR\r
-SCSI_In_DBx__DB7__INP_DIS EQU CYREG_PRT2_INP_DIS\r
-SCSI_In_DBx__DB7__INTTYPE EQU CYREG_PICU2_INTTYPE4\r
-SCSI_In_DBx__DB7__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
-SCSI_In_DBx__DB7__LCD_EN EQU CYREG_PRT2_LCD_EN\r
-SCSI_In_DBx__DB7__MASK EQU 0x10\r
-SCSI_In_DBx__DB7__PC EQU CYREG_PRT2_PC4\r
-SCSI_In_DBx__DB7__PORT EQU 2\r
-SCSI_In_DBx__DB7__PRT EQU CYREG_PRT2_PRT\r
-SCSI_In_DBx__DB7__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
-SCSI_In_DBx__DB7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
-SCSI_In_DBx__DB7__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
-SCSI_In_DBx__DB7__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
-SCSI_In_DBx__DB7__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
-SCSI_In_DBx__DB7__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
-SCSI_In_DBx__DB7__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
-SCSI_In_DBx__DB7__PS EQU CYREG_PRT2_PS\r
-SCSI_In_DBx__DB7__SHIFT EQU 4\r
-SCSI_In_DBx__DB7__SLW EQU CYREG_PRT2_SLW\r
-\r
-/* SD_MISO */\r
-SD_MISO__0__INTTYPE EQU CYREG_PICU3_INTTYPE1\r
-SD_MISO__0__MASK EQU 0x02\r
-SD_MISO__0__PC EQU CYREG_PRT3_PC1\r
-SD_MISO__0__PORT EQU 3\r
-SD_MISO__0__SHIFT EQU 1\r
-SD_MISO__AG EQU CYREG_PRT3_AG\r
-SD_MISO__AMUX EQU CYREG_PRT3_AMUX\r
-SD_MISO__BIE EQU CYREG_PRT3_BIE\r
-SD_MISO__BIT_MASK EQU CYREG_PRT3_BIT_MASK\r
-SD_MISO__BYP EQU CYREG_PRT3_BYP\r
-SD_MISO__CTL EQU CYREG_PRT3_CTL\r
-SD_MISO__DM0 EQU CYREG_PRT3_DM0\r
-SD_MISO__DM1 EQU CYREG_PRT3_DM1\r
-SD_MISO__DM2 EQU CYREG_PRT3_DM2\r
-SD_MISO__DR EQU CYREG_PRT3_DR\r
-SD_MISO__INP_DIS EQU CYREG_PRT3_INP_DIS\r
-SD_MISO__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE\r
-SD_MISO__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG\r
-SD_MISO__LCD_EN EQU CYREG_PRT3_LCD_EN\r
-SD_MISO__MASK EQU 0x02\r
-SD_MISO__PORT EQU 3\r
-SD_MISO__PRT EQU CYREG_PRT3_PRT\r
-SD_MISO__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL\r
-SD_MISO__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN\r
-SD_MISO__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0\r
-SD_MISO__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1\r
-SD_MISO__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0\r
-SD_MISO__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1\r
-SD_MISO__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT\r
-SD_MISO__PS EQU CYREG_PRT3_PS\r
-SD_MISO__SHIFT EQU 1\r
-SD_MISO__SLW EQU CYREG_PRT3_SLW\r
-\r
-/* SD_MOSI */\r
-SD_MOSI__0__INTTYPE EQU CYREG_PICU3_INTTYPE3\r
-SD_MOSI__0__MASK EQU 0x08\r
-SD_MOSI__0__PC EQU CYREG_PRT3_PC3\r
-SD_MOSI__0__PORT EQU 3\r
-SD_MOSI__0__SHIFT EQU 3\r
-SD_MOSI__AG EQU CYREG_PRT3_AG\r
-SD_MOSI__AMUX EQU CYREG_PRT3_AMUX\r
-SD_MOSI__BIE EQU CYREG_PRT3_BIE\r
-SD_MOSI__BIT_MASK EQU CYREG_PRT3_BIT_MASK\r
-SD_MOSI__BYP EQU CYREG_PRT3_BYP\r
-SD_MOSI__CTL EQU CYREG_PRT3_CTL\r
-SD_MOSI__DM0 EQU CYREG_PRT3_DM0\r
-SD_MOSI__DM1 EQU CYREG_PRT3_DM1\r
-SD_MOSI__DM2 EQU CYREG_PRT3_DM2\r
-SD_MOSI__DR EQU CYREG_PRT3_DR\r
-SD_MOSI__INP_DIS EQU CYREG_PRT3_INP_DIS\r
-SD_MOSI__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE\r
-SD_MOSI__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG\r
-SD_MOSI__LCD_EN EQU CYREG_PRT3_LCD_EN\r
-SD_MOSI__MASK EQU 0x08\r
-SD_MOSI__PORT EQU 3\r
-SD_MOSI__PRT EQU CYREG_PRT3_PRT\r
-SD_MOSI__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL\r
-SD_MOSI__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN\r
-SD_MOSI__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0\r
-SD_MOSI__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1\r
-SD_MOSI__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0\r
-SD_MOSI__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1\r
-SD_MOSI__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT\r
-SD_MOSI__PS EQU CYREG_PRT3_PS\r
-SD_MOSI__SHIFT EQU 3\r
-SD_MOSI__SLW EQU CYREG_PRT3_SLW\r
-\r
-/* SCSI_CLK */\r
-SCSI_CLK__CFG0 EQU CYREG_CLKDIST_DCFG1_CFG0\r
-SCSI_CLK__CFG1 EQU CYREG_CLKDIST_DCFG1_CFG1\r
-SCSI_CLK__CFG2 EQU CYREG_CLKDIST_DCFG1_CFG2\r
-SCSI_CLK__CFG2_SRC_SEL_MASK EQU 0x07\r
-SCSI_CLK__INDEX EQU 0x01\r
-SCSI_CLK__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2\r
-SCSI_CLK__PM_ACT_MSK EQU 0x02\r
-SCSI_CLK__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2\r
-SCSI_CLK__PM_STBY_MSK EQU 0x02\r
-\r
-/* SCSI_Out */\r
-SCSI_Out__0__AG EQU CYREG_PRT15_AG\r
-SCSI_Out__0__AMUX EQU CYREG_PRT15_AMUX\r
-SCSI_Out__0__BIE EQU CYREG_PRT15_BIE\r
-SCSI_Out__0__BIT_MASK EQU CYREG_PRT15_BIT_MASK\r
-SCSI_Out__0__BYP EQU CYREG_PRT15_BYP\r
-SCSI_Out__0__CTL EQU CYREG_PRT15_CTL\r
-SCSI_Out__0__DM0 EQU CYREG_PRT15_DM0\r
-SCSI_Out__0__DM1 EQU CYREG_PRT15_DM1\r
-SCSI_Out__0__DM2 EQU CYREG_PRT15_DM2\r
-SCSI_Out__0__DR EQU CYREG_PRT15_DR\r
-SCSI_Out__0__INP_DIS EQU CYREG_PRT15_INP_DIS\r
-SCSI_Out__0__INTTYPE EQU CYREG_PICU15_INTTYPE5\r
-SCSI_Out__0__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG\r
-SCSI_Out__0__LCD_EN EQU CYREG_PRT15_LCD_EN\r
-SCSI_Out__0__MASK EQU 0x20\r
-SCSI_Out__0__PC EQU CYREG_IO_PC_PRT15_PC5\r
-SCSI_Out__0__PORT EQU 15\r
-SCSI_Out__0__PRT EQU CYREG_PRT15_PRT\r
-SCSI_Out__0__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL\r
-SCSI_Out__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN\r
-SCSI_Out__0__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0\r
-SCSI_Out__0__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1\r
-SCSI_Out__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0\r
-SCSI_Out__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1\r
-SCSI_Out__0__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT\r
-SCSI_Out__0__PS EQU CYREG_PRT15_PS\r
-SCSI_Out__0__SHIFT EQU 5\r
-SCSI_Out__0__SLW EQU CYREG_PRT15_SLW\r
-SCSI_Out__1__AG EQU CYREG_PRT15_AG\r
-SCSI_Out__1__AMUX EQU CYREG_PRT15_AMUX\r
-SCSI_Out__1__BIE EQU CYREG_PRT15_BIE\r
-SCSI_Out__1__BIT_MASK EQU CYREG_PRT15_BIT_MASK\r
-SCSI_Out__1__BYP EQU CYREG_PRT15_BYP\r
-SCSI_Out__1__CTL EQU CYREG_PRT15_CTL\r
-SCSI_Out__1__DM0 EQU CYREG_PRT15_DM0\r
-SCSI_Out__1__DM1 EQU CYREG_PRT15_DM1\r
-SCSI_Out__1__DM2 EQU CYREG_PRT15_DM2\r
-SCSI_Out__1__DR EQU CYREG_PRT15_DR\r
-SCSI_Out__1__INP_DIS EQU CYREG_PRT15_INP_DIS\r
-SCSI_Out__1__INTTYPE EQU CYREG_PICU15_INTTYPE4\r
-SCSI_Out__1__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG\r
-SCSI_Out__1__LCD_EN EQU CYREG_PRT15_LCD_EN\r
-SCSI_Out__1__MASK EQU 0x10\r
-SCSI_Out__1__PC EQU CYREG_IO_PC_PRT15_PC4\r
-SCSI_Out__1__PORT EQU 15\r
-SCSI_Out__1__PRT EQU CYREG_PRT15_PRT\r
-SCSI_Out__1__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL\r
-SCSI_Out__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN\r
-SCSI_Out__1__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0\r
-SCSI_Out__1__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1\r
-SCSI_Out__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0\r
-SCSI_Out__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1\r
-SCSI_Out__1__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT\r
-SCSI_Out__1__PS EQU CYREG_PRT15_PS\r
-SCSI_Out__1__SHIFT EQU 4\r
-SCSI_Out__1__SLW EQU CYREG_PRT15_SLW\r
-SCSI_Out__2__AG EQU CYREG_PRT6_AG\r
-SCSI_Out__2__AMUX EQU CYREG_PRT6_AMUX\r
-SCSI_Out__2__BIE EQU CYREG_PRT6_BIE\r
-SCSI_Out__2__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
-SCSI_Out__2__BYP EQU CYREG_PRT6_BYP\r
-SCSI_Out__2__CTL EQU CYREG_PRT6_CTL\r
-SCSI_Out__2__DM0 EQU CYREG_PRT6_DM0\r
-SCSI_Out__2__DM1 EQU CYREG_PRT6_DM1\r
-SCSI_Out__2__DM2 EQU CYREG_PRT6_DM2\r
-SCSI_Out__2__DR EQU CYREG_PRT6_DR\r
-SCSI_Out__2__INP_DIS EQU CYREG_PRT6_INP_DIS\r
-SCSI_Out__2__INTTYPE EQU CYREG_PICU6_INTTYPE1\r
-SCSI_Out__2__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
-SCSI_Out__2__LCD_EN EQU CYREG_PRT6_LCD_EN\r
-SCSI_Out__2__MASK EQU 0x02\r
-SCSI_Out__2__PC EQU CYREG_PRT6_PC1\r
-SCSI_Out__2__PORT EQU 6\r
-SCSI_Out__2__PRT EQU CYREG_PRT6_PRT\r
-SCSI_Out__2__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
-SCSI_Out__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
-SCSI_Out__2__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
-SCSI_Out__2__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
-SCSI_Out__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
-SCSI_Out__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
-SCSI_Out__2__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
-SCSI_Out__2__PS EQU CYREG_PRT6_PS\r
-SCSI_Out__2__SHIFT EQU 1\r
-SCSI_Out__2__SLW EQU CYREG_PRT6_SLW\r
-SCSI_Out__3__AG EQU CYREG_PRT6_AG\r
-SCSI_Out__3__AMUX EQU CYREG_PRT6_AMUX\r
-SCSI_Out__3__BIE EQU CYREG_PRT6_BIE\r
-SCSI_Out__3__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
-SCSI_Out__3__BYP EQU CYREG_PRT6_BYP\r
-SCSI_Out__3__CTL EQU CYREG_PRT6_CTL\r
-SCSI_Out__3__DM0 EQU CYREG_PRT6_DM0\r
-SCSI_Out__3__DM1 EQU CYREG_PRT6_DM1\r
-SCSI_Out__3__DM2 EQU CYREG_PRT6_DM2\r
-SCSI_Out__3__DR EQU CYREG_PRT6_DR\r
-SCSI_Out__3__INP_DIS EQU CYREG_PRT6_INP_DIS\r
-SCSI_Out__3__INTTYPE EQU CYREG_PICU6_INTTYPE0\r
-SCSI_Out__3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
-SCSI_Out__3__LCD_EN EQU CYREG_PRT6_LCD_EN\r
-SCSI_Out__3__MASK EQU 0x01\r
-SCSI_Out__3__PC EQU CYREG_PRT6_PC0\r
-SCSI_Out__3__PORT EQU 6\r
-SCSI_Out__3__PRT EQU CYREG_PRT6_PRT\r
-SCSI_Out__3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
-SCSI_Out__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
-SCSI_Out__3__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
-SCSI_Out__3__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
-SCSI_Out__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
-SCSI_Out__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
-SCSI_Out__3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
-SCSI_Out__3__PS EQU CYREG_PRT6_PS\r
-SCSI_Out__3__SHIFT EQU 0\r
-SCSI_Out__3__SLW EQU CYREG_PRT6_SLW\r
-SCSI_Out__4__AG EQU CYREG_PRT4_AG\r
-SCSI_Out__4__AMUX EQU CYREG_PRT4_AMUX\r
-SCSI_Out__4__BIE EQU CYREG_PRT4_BIE\r
-SCSI_Out__4__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
-SCSI_Out__4__BYP EQU CYREG_PRT4_BYP\r
-SCSI_Out__4__CTL EQU CYREG_PRT4_CTL\r
-SCSI_Out__4__DM0 EQU CYREG_PRT4_DM0\r
-SCSI_Out__4__DM1 EQU CYREG_PRT4_DM1\r
-SCSI_Out__4__DM2 EQU CYREG_PRT4_DM2\r
-SCSI_Out__4__DR EQU CYREG_PRT4_DR\r
-SCSI_Out__4__INP_DIS EQU CYREG_PRT4_INP_DIS\r
-SCSI_Out__4__INTTYPE EQU CYREG_PICU4_INTTYPE5\r
-SCSI_Out__4__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
-SCSI_Out__4__LCD_EN EQU CYREG_PRT4_LCD_EN\r
-SCSI_Out__4__MASK EQU 0x20\r
-SCSI_Out__4__PC EQU CYREG_PRT4_PC5\r
-SCSI_Out__4__PORT EQU 4\r
-SCSI_Out__4__PRT EQU CYREG_PRT4_PRT\r
-SCSI_Out__4__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
-SCSI_Out__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
-SCSI_Out__4__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
-SCSI_Out__4__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
-SCSI_Out__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
-SCSI_Out__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
-SCSI_Out__4__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
-SCSI_Out__4__PS EQU CYREG_PRT4_PS\r
-SCSI_Out__4__SHIFT EQU 5\r
-SCSI_Out__4__SLW EQU CYREG_PRT4_SLW\r
-SCSI_Out__5__AG EQU CYREG_PRT4_AG\r
-SCSI_Out__5__AMUX EQU CYREG_PRT4_AMUX\r
-SCSI_Out__5__BIE EQU CYREG_PRT4_BIE\r
-SCSI_Out__5__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
-SCSI_Out__5__BYP EQU CYREG_PRT4_BYP\r
-SCSI_Out__5__CTL EQU CYREG_PRT4_CTL\r
-SCSI_Out__5__DM0 EQU CYREG_PRT4_DM0\r
-SCSI_Out__5__DM1 EQU CYREG_PRT4_DM1\r
-SCSI_Out__5__DM2 EQU CYREG_PRT4_DM2\r
-SCSI_Out__5__DR EQU CYREG_PRT4_DR\r
-SCSI_Out__5__INP_DIS EQU CYREG_PRT4_INP_DIS\r
-SCSI_Out__5__INTTYPE EQU CYREG_PICU4_INTTYPE4\r
-SCSI_Out__5__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
-SCSI_Out__5__LCD_EN EQU CYREG_PRT4_LCD_EN\r
-SCSI_Out__5__MASK EQU 0x10\r
-SCSI_Out__5__PC EQU CYREG_PRT4_PC4\r
-SCSI_Out__5__PORT EQU 4\r
-SCSI_Out__5__PRT EQU CYREG_PRT4_PRT\r
-SCSI_Out__5__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
-SCSI_Out__5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
-SCSI_Out__5__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
-SCSI_Out__5__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
-SCSI_Out__5__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
-SCSI_Out__5__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
-SCSI_Out__5__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
-SCSI_Out__5__PS EQU CYREG_PRT4_PS\r
-SCSI_Out__5__SHIFT EQU 4\r
-SCSI_Out__5__SLW EQU CYREG_PRT4_SLW\r
-SCSI_Out__6__AG EQU CYREG_PRT0_AG\r
-SCSI_Out__6__AMUX EQU CYREG_PRT0_AMUX\r
-SCSI_Out__6__BIE EQU CYREG_PRT0_BIE\r
-SCSI_Out__6__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
-SCSI_Out__6__BYP EQU CYREG_PRT0_BYP\r
-SCSI_Out__6__CTL EQU CYREG_PRT0_CTL\r
-SCSI_Out__6__DM0 EQU CYREG_PRT0_DM0\r
-SCSI_Out__6__DM1 EQU CYREG_PRT0_DM1\r
-SCSI_Out__6__DM2 EQU CYREG_PRT0_DM2\r
-SCSI_Out__6__DR EQU CYREG_PRT0_DR\r
-SCSI_Out__6__INP_DIS EQU CYREG_PRT0_INP_DIS\r
-SCSI_Out__6__INTTYPE EQU CYREG_PICU0_INTTYPE7\r
-SCSI_Out__6__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
-SCSI_Out__6__LCD_EN EQU CYREG_PRT0_LCD_EN\r
-SCSI_Out__6__MASK EQU 0x80\r
-SCSI_Out__6__PC EQU CYREG_PRT0_PC7\r
-SCSI_Out__6__PORT EQU 0\r
-SCSI_Out__6__PRT EQU CYREG_PRT0_PRT\r
-SCSI_Out__6__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
-SCSI_Out__6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
-SCSI_Out__6__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
-SCSI_Out__6__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
-SCSI_Out__6__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
-SCSI_Out__6__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
-SCSI_Out__6__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
-SCSI_Out__6__PS EQU CYREG_PRT0_PS\r
-SCSI_Out__6__SHIFT EQU 7\r
-SCSI_Out__6__SLW EQU CYREG_PRT0_SLW\r
-SCSI_Out__7__AG EQU CYREG_PRT0_AG\r
-SCSI_Out__7__AMUX EQU CYREG_PRT0_AMUX\r
-SCSI_Out__7__BIE EQU CYREG_PRT0_BIE\r
-SCSI_Out__7__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
-SCSI_Out__7__BYP EQU CYREG_PRT0_BYP\r
-SCSI_Out__7__CTL EQU CYREG_PRT0_CTL\r
-SCSI_Out__7__DM0 EQU CYREG_PRT0_DM0\r
-SCSI_Out__7__DM1 EQU CYREG_PRT0_DM1\r
-SCSI_Out__7__DM2 EQU CYREG_PRT0_DM2\r
-SCSI_Out__7__DR EQU CYREG_PRT0_DR\r
-SCSI_Out__7__INP_DIS EQU CYREG_PRT0_INP_DIS\r
-SCSI_Out__7__INTTYPE EQU CYREG_PICU0_INTTYPE6\r
-SCSI_Out__7__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
-SCSI_Out__7__LCD_EN EQU CYREG_PRT0_LCD_EN\r
-SCSI_Out__7__MASK EQU 0x40\r
-SCSI_Out__7__PC EQU CYREG_PRT0_PC6\r
-SCSI_Out__7__PORT EQU 0\r
-SCSI_Out__7__PRT EQU CYREG_PRT0_PRT\r
-SCSI_Out__7__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
-SCSI_Out__7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
-SCSI_Out__7__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
-SCSI_Out__7__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
-SCSI_Out__7__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
-SCSI_Out__7__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
-SCSI_Out__7__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
-SCSI_Out__7__PS EQU CYREG_PRT0_PS\r
-SCSI_Out__7__SHIFT EQU 6\r
-SCSI_Out__7__SLW EQU CYREG_PRT0_SLW\r
-SCSI_Out__8__AG EQU CYREG_PRT0_AG\r
-SCSI_Out__8__AMUX EQU CYREG_PRT0_AMUX\r
-SCSI_Out__8__BIE EQU CYREG_PRT0_BIE\r
-SCSI_Out__8__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
-SCSI_Out__8__BYP EQU CYREG_PRT0_BYP\r
-SCSI_Out__8__CTL EQU CYREG_PRT0_CTL\r
-SCSI_Out__8__DM0 EQU CYREG_PRT0_DM0\r
-SCSI_Out__8__DM1 EQU CYREG_PRT0_DM1\r
-SCSI_Out__8__DM2 EQU CYREG_PRT0_DM2\r
-SCSI_Out__8__DR EQU CYREG_PRT0_DR\r
-SCSI_Out__8__INP_DIS EQU CYREG_PRT0_INP_DIS\r
-SCSI_Out__8__INTTYPE EQU CYREG_PICU0_INTTYPE3\r
-SCSI_Out__8__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
-SCSI_Out__8__LCD_EN EQU CYREG_PRT0_LCD_EN\r
-SCSI_Out__8__MASK EQU 0x08\r
-SCSI_Out__8__PC EQU CYREG_PRT0_PC3\r
-SCSI_Out__8__PORT EQU 0\r
-SCSI_Out__8__PRT EQU CYREG_PRT0_PRT\r
-SCSI_Out__8__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
-SCSI_Out__8__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
-SCSI_Out__8__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
-SCSI_Out__8__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
-SCSI_Out__8__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
-SCSI_Out__8__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
-SCSI_Out__8__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
-SCSI_Out__8__PS EQU CYREG_PRT0_PS\r
-SCSI_Out__8__SHIFT EQU 3\r
-SCSI_Out__8__SLW EQU CYREG_PRT0_SLW\r
-SCSI_Out__9__AG EQU CYREG_PRT0_AG\r
-SCSI_Out__9__AMUX EQU CYREG_PRT0_AMUX\r
-SCSI_Out__9__BIE EQU CYREG_PRT0_BIE\r
-SCSI_Out__9__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
-SCSI_Out__9__BYP EQU CYREG_PRT0_BYP\r
-SCSI_Out__9__CTL EQU CYREG_PRT0_CTL\r
-SCSI_Out__9__DM0 EQU CYREG_PRT0_DM0\r
-SCSI_Out__9__DM1 EQU CYREG_PRT0_DM1\r
-SCSI_Out__9__DM2 EQU CYREG_PRT0_DM2\r
-SCSI_Out__9__DR EQU CYREG_PRT0_DR\r
-SCSI_Out__9__INP_DIS EQU CYREG_PRT0_INP_DIS\r
-SCSI_Out__9__INTTYPE EQU CYREG_PICU0_INTTYPE2\r
-SCSI_Out__9__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
-SCSI_Out__9__LCD_EN EQU CYREG_PRT0_LCD_EN\r
-SCSI_Out__9__MASK EQU 0x04\r
-SCSI_Out__9__PC EQU CYREG_PRT0_PC2\r
-SCSI_Out__9__PORT EQU 0\r
-SCSI_Out__9__PRT EQU CYREG_PRT0_PRT\r
-SCSI_Out__9__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
-SCSI_Out__9__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
-SCSI_Out__9__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
-SCSI_Out__9__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
-SCSI_Out__9__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
-SCSI_Out__9__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
-SCSI_Out__9__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
-SCSI_Out__9__PS EQU CYREG_PRT0_PS\r
-SCSI_Out__9__SHIFT EQU 2\r
-SCSI_Out__9__SLW EQU CYREG_PRT0_SLW\r
-SCSI_Out__ACK__AG EQU CYREG_PRT6_AG\r
-SCSI_Out__ACK__AMUX EQU CYREG_PRT6_AMUX\r
-SCSI_Out__ACK__BIE EQU CYREG_PRT6_BIE\r
-SCSI_Out__ACK__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
-SCSI_Out__ACK__BYP EQU CYREG_PRT6_BYP\r
-SCSI_Out__ACK__CTL EQU CYREG_PRT6_CTL\r
-SCSI_Out__ACK__DM0 EQU CYREG_PRT6_DM0\r
-SCSI_Out__ACK__DM1 EQU CYREG_PRT6_DM1\r
-SCSI_Out__ACK__DM2 EQU CYREG_PRT6_DM2\r
-SCSI_Out__ACK__DR EQU CYREG_PRT6_DR\r
-SCSI_Out__ACK__INP_DIS EQU CYREG_PRT6_INP_DIS\r
-SCSI_Out__ACK__INTTYPE EQU CYREG_PICU6_INTTYPE0\r
-SCSI_Out__ACK__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
-SCSI_Out__ACK__LCD_EN EQU CYREG_PRT6_LCD_EN\r
-SCSI_Out__ACK__MASK EQU 0x01\r
-SCSI_Out__ACK__PC EQU CYREG_PRT6_PC0\r
-SCSI_Out__ACK__PORT EQU 6\r
-SCSI_Out__ACK__PRT EQU CYREG_PRT6_PRT\r
-SCSI_Out__ACK__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
-SCSI_Out__ACK__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
-SCSI_Out__ACK__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
-SCSI_Out__ACK__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
-SCSI_Out__ACK__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
-SCSI_Out__ACK__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
-SCSI_Out__ACK__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
-SCSI_Out__ACK__PS EQU CYREG_PRT6_PS\r
-SCSI_Out__ACK__SHIFT EQU 0\r
-SCSI_Out__ACK__SLW EQU CYREG_PRT6_SLW\r
-SCSI_Out__ATN__AG EQU CYREG_PRT15_AG\r
-SCSI_Out__ATN__AMUX EQU CYREG_PRT15_AMUX\r
-SCSI_Out__ATN__BIE EQU CYREG_PRT15_BIE\r
-SCSI_Out__ATN__BIT_MASK EQU CYREG_PRT15_BIT_MASK\r
-SCSI_Out__ATN__BYP EQU CYREG_PRT15_BYP\r
-SCSI_Out__ATN__CTL EQU CYREG_PRT15_CTL\r
-SCSI_Out__ATN__DM0 EQU CYREG_PRT15_DM0\r
-SCSI_Out__ATN__DM1 EQU CYREG_PRT15_DM1\r
-SCSI_Out__ATN__DM2 EQU CYREG_PRT15_DM2\r
-SCSI_Out__ATN__DR EQU CYREG_PRT15_DR\r
-SCSI_Out__ATN__INP_DIS EQU CYREG_PRT15_INP_DIS\r
-SCSI_Out__ATN__INTTYPE EQU CYREG_PICU15_INTTYPE4\r
-SCSI_Out__ATN__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG\r
-SCSI_Out__ATN__LCD_EN EQU CYREG_PRT15_LCD_EN\r
-SCSI_Out__ATN__MASK EQU 0x10\r
-SCSI_Out__ATN__PC EQU CYREG_IO_PC_PRT15_PC4\r
-SCSI_Out__ATN__PORT EQU 15\r
-SCSI_Out__ATN__PRT EQU CYREG_PRT15_PRT\r
-SCSI_Out__ATN__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL\r
-SCSI_Out__ATN__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN\r
-SCSI_Out__ATN__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0\r
-SCSI_Out__ATN__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1\r
-SCSI_Out__ATN__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0\r
-SCSI_Out__ATN__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1\r
-SCSI_Out__ATN__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT\r
-SCSI_Out__ATN__PS EQU CYREG_PRT15_PS\r
-SCSI_Out__ATN__SHIFT EQU 4\r
-SCSI_Out__ATN__SLW EQU CYREG_PRT15_SLW\r
-SCSI_Out__BSY__AG EQU CYREG_PRT6_AG\r
-SCSI_Out__BSY__AMUX EQU CYREG_PRT6_AMUX\r
-SCSI_Out__BSY__BIE EQU CYREG_PRT6_BIE\r
-SCSI_Out__BSY__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
-SCSI_Out__BSY__BYP EQU CYREG_PRT6_BYP\r
-SCSI_Out__BSY__CTL EQU CYREG_PRT6_CTL\r
-SCSI_Out__BSY__DM0 EQU CYREG_PRT6_DM0\r
-SCSI_Out__BSY__DM1 EQU CYREG_PRT6_DM1\r
-SCSI_Out__BSY__DM2 EQU CYREG_PRT6_DM2\r
-SCSI_Out__BSY__DR EQU CYREG_PRT6_DR\r
-SCSI_Out__BSY__INP_DIS EQU CYREG_PRT6_INP_DIS\r
-SCSI_Out__BSY__INTTYPE EQU CYREG_PICU6_INTTYPE1\r
-SCSI_Out__BSY__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
-SCSI_Out__BSY__LCD_EN EQU CYREG_PRT6_LCD_EN\r
-SCSI_Out__BSY__MASK EQU 0x02\r
-SCSI_Out__BSY__PC EQU CYREG_PRT6_PC1\r
-SCSI_Out__BSY__PORT EQU 6\r
-SCSI_Out__BSY__PRT EQU CYREG_PRT6_PRT\r
-SCSI_Out__BSY__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
-SCSI_Out__BSY__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
-SCSI_Out__BSY__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
-SCSI_Out__BSY__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
-SCSI_Out__BSY__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
-SCSI_Out__BSY__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
-SCSI_Out__BSY__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
-SCSI_Out__BSY__PS EQU CYREG_PRT6_PS\r
-SCSI_Out__BSY__SHIFT EQU 1\r
-SCSI_Out__BSY__SLW EQU CYREG_PRT6_SLW\r
-SCSI_Out__CD_raw__AG EQU CYREG_PRT0_AG\r
-SCSI_Out__CD_raw__AMUX EQU CYREG_PRT0_AMUX\r
-SCSI_Out__CD_raw__BIE EQU CYREG_PRT0_BIE\r
-SCSI_Out__CD_raw__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
-SCSI_Out__CD_raw__BYP EQU CYREG_PRT0_BYP\r
-SCSI_Out__CD_raw__CTL EQU CYREG_PRT0_CTL\r
-SCSI_Out__CD_raw__DM0 EQU CYREG_PRT0_DM0\r
-SCSI_Out__CD_raw__DM1 EQU CYREG_PRT0_DM1\r
-SCSI_Out__CD_raw__DM2 EQU CYREG_PRT0_DM2\r
-SCSI_Out__CD_raw__DR EQU CYREG_PRT0_DR\r
-SCSI_Out__CD_raw__INP_DIS EQU CYREG_PRT0_INP_DIS\r
-SCSI_Out__CD_raw__INTTYPE EQU CYREG_PICU0_INTTYPE6\r
-SCSI_Out__CD_raw__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
-SCSI_Out__CD_raw__LCD_EN EQU CYREG_PRT0_LCD_EN\r
-SCSI_Out__CD_raw__MASK EQU 0x40\r
-SCSI_Out__CD_raw__PC EQU CYREG_PRT0_PC6\r
-SCSI_Out__CD_raw__PORT EQU 0\r
-SCSI_Out__CD_raw__PRT EQU CYREG_PRT0_PRT\r
-SCSI_Out__CD_raw__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
-SCSI_Out__CD_raw__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
-SCSI_Out__CD_raw__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
-SCSI_Out__CD_raw__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
-SCSI_Out__CD_raw__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
-SCSI_Out__CD_raw__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
-SCSI_Out__CD_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
-SCSI_Out__CD_raw__PS EQU CYREG_PRT0_PS\r
-SCSI_Out__CD_raw__SHIFT EQU 6\r
-SCSI_Out__CD_raw__SLW EQU CYREG_PRT0_SLW\r
-SCSI_Out__DBP_raw__AG EQU CYREG_PRT15_AG\r
-SCSI_Out__DBP_raw__AMUX EQU CYREG_PRT15_AMUX\r
-SCSI_Out__DBP_raw__BIE EQU CYREG_PRT15_BIE\r
-SCSI_Out__DBP_raw__BIT_MASK EQU CYREG_PRT15_BIT_MASK\r
-SCSI_Out__DBP_raw__BYP EQU CYREG_PRT15_BYP\r
-SCSI_Out__DBP_raw__CTL EQU CYREG_PRT15_CTL\r
-SCSI_Out__DBP_raw__DM0 EQU CYREG_PRT15_DM0\r
-SCSI_Out__DBP_raw__DM1 EQU CYREG_PRT15_DM1\r
-SCSI_Out__DBP_raw__DM2 EQU CYREG_PRT15_DM2\r
-SCSI_Out__DBP_raw__DR EQU CYREG_PRT15_DR\r
-SCSI_Out__DBP_raw__INP_DIS EQU CYREG_PRT15_INP_DIS\r
-SCSI_Out__DBP_raw__INTTYPE EQU CYREG_PICU15_INTTYPE5\r
-SCSI_Out__DBP_raw__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG\r
-SCSI_Out__DBP_raw__LCD_EN EQU CYREG_PRT15_LCD_EN\r
-SCSI_Out__DBP_raw__MASK EQU 0x20\r
-SCSI_Out__DBP_raw__PC EQU CYREG_IO_PC_PRT15_PC5\r
-SCSI_Out__DBP_raw__PORT EQU 15\r
-SCSI_Out__DBP_raw__PRT EQU CYREG_PRT15_PRT\r
-SCSI_Out__DBP_raw__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL\r
-SCSI_Out__DBP_raw__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN\r
-SCSI_Out__DBP_raw__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0\r
-SCSI_Out__DBP_raw__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1\r
-SCSI_Out__DBP_raw__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0\r
-SCSI_Out__DBP_raw__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1\r
-SCSI_Out__DBP_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT\r
-SCSI_Out__DBP_raw__PS EQU CYREG_PRT15_PS\r
-SCSI_Out__DBP_raw__SHIFT EQU 5\r
-SCSI_Out__DBP_raw__SLW EQU CYREG_PRT15_SLW\r
-SCSI_Out__IO_raw__AG EQU CYREG_PRT0_AG\r
-SCSI_Out__IO_raw__AMUX EQU CYREG_PRT0_AMUX\r
-SCSI_Out__IO_raw__BIE EQU CYREG_PRT0_BIE\r
-SCSI_Out__IO_raw__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
-SCSI_Out__IO_raw__BYP EQU CYREG_PRT0_BYP\r
-SCSI_Out__IO_raw__CTL EQU CYREG_PRT0_CTL\r
-SCSI_Out__IO_raw__DM0 EQU CYREG_PRT0_DM0\r
-SCSI_Out__IO_raw__DM1 EQU CYREG_PRT0_DM1\r
-SCSI_Out__IO_raw__DM2 EQU CYREG_PRT0_DM2\r
-SCSI_Out__IO_raw__DR EQU CYREG_PRT0_DR\r
-SCSI_Out__IO_raw__INP_DIS EQU CYREG_PRT0_INP_DIS\r
-SCSI_Out__IO_raw__INTTYPE EQU CYREG_PICU0_INTTYPE2\r
-SCSI_Out__IO_raw__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
-SCSI_Out__IO_raw__LCD_EN EQU CYREG_PRT0_LCD_EN\r
-SCSI_Out__IO_raw__MASK EQU 0x04\r
-SCSI_Out__IO_raw__PC EQU CYREG_PRT0_PC2\r
-SCSI_Out__IO_raw__PORT EQU 0\r
-SCSI_Out__IO_raw__PRT EQU CYREG_PRT0_PRT\r
-SCSI_Out__IO_raw__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
-SCSI_Out__IO_raw__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
-SCSI_Out__IO_raw__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
-SCSI_Out__IO_raw__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
-SCSI_Out__IO_raw__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
-SCSI_Out__IO_raw__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
-SCSI_Out__IO_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
-SCSI_Out__IO_raw__PS EQU CYREG_PRT0_PS\r
-SCSI_Out__IO_raw__SHIFT EQU 2\r
-SCSI_Out__IO_raw__SLW EQU CYREG_PRT0_SLW\r
-SCSI_Out__MSG_raw__AG EQU CYREG_PRT4_AG\r
-SCSI_Out__MSG_raw__AMUX EQU CYREG_PRT4_AMUX\r
-SCSI_Out__MSG_raw__BIE EQU CYREG_PRT4_BIE\r
-SCSI_Out__MSG_raw__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
-SCSI_Out__MSG_raw__BYP EQU CYREG_PRT4_BYP\r
-SCSI_Out__MSG_raw__CTL EQU CYREG_PRT4_CTL\r
-SCSI_Out__MSG_raw__DM0 EQU CYREG_PRT4_DM0\r
-SCSI_Out__MSG_raw__DM1 EQU CYREG_PRT4_DM1\r
-SCSI_Out__MSG_raw__DM2 EQU CYREG_PRT4_DM2\r
-SCSI_Out__MSG_raw__DR EQU CYREG_PRT4_DR\r
-SCSI_Out__MSG_raw__INP_DIS EQU CYREG_PRT4_INP_DIS\r
-SCSI_Out__MSG_raw__INTTYPE EQU CYREG_PICU4_INTTYPE4\r
-SCSI_Out__MSG_raw__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
-SCSI_Out__MSG_raw__LCD_EN EQU CYREG_PRT4_LCD_EN\r
-SCSI_Out__MSG_raw__MASK EQU 0x10\r
-SCSI_Out__MSG_raw__PC EQU CYREG_PRT4_PC4\r
-SCSI_Out__MSG_raw__PORT EQU 4\r
-SCSI_Out__MSG_raw__PRT EQU CYREG_PRT4_PRT\r
-SCSI_Out__MSG_raw__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
-SCSI_Out__MSG_raw__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
-SCSI_Out__MSG_raw__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
-SCSI_Out__MSG_raw__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
-SCSI_Out__MSG_raw__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
-SCSI_Out__MSG_raw__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
-SCSI_Out__MSG_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
-SCSI_Out__MSG_raw__PS EQU CYREG_PRT4_PS\r
-SCSI_Out__MSG_raw__SHIFT EQU 4\r
-SCSI_Out__MSG_raw__SLW EQU CYREG_PRT4_SLW\r
-SCSI_Out__REQ__AG EQU CYREG_PRT0_AG\r
-SCSI_Out__REQ__AMUX EQU CYREG_PRT0_AMUX\r
-SCSI_Out__REQ__BIE EQU CYREG_PRT0_BIE\r
-SCSI_Out__REQ__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
-SCSI_Out__REQ__BYP EQU CYREG_PRT0_BYP\r
-SCSI_Out__REQ__CTL EQU CYREG_PRT0_CTL\r
-SCSI_Out__REQ__DM0 EQU CYREG_PRT0_DM0\r
-SCSI_Out__REQ__DM1 EQU CYREG_PRT0_DM1\r
-SCSI_Out__REQ__DM2 EQU CYREG_PRT0_DM2\r
-SCSI_Out__REQ__DR EQU CYREG_PRT0_DR\r
-SCSI_Out__REQ__INP_DIS EQU CYREG_PRT0_INP_DIS\r
-SCSI_Out__REQ__INTTYPE EQU CYREG_PICU0_INTTYPE3\r
-SCSI_Out__REQ__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
-SCSI_Out__REQ__LCD_EN EQU CYREG_PRT0_LCD_EN\r
-SCSI_Out__REQ__MASK EQU 0x08\r
-SCSI_Out__REQ__PC EQU CYREG_PRT0_PC3\r
-SCSI_Out__REQ__PORT EQU 0\r
-SCSI_Out__REQ__PRT EQU CYREG_PRT0_PRT\r
-SCSI_Out__REQ__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
-SCSI_Out__REQ__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
-SCSI_Out__REQ__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
-SCSI_Out__REQ__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
-SCSI_Out__REQ__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
-SCSI_Out__REQ__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
-SCSI_Out__REQ__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
-SCSI_Out__REQ__PS EQU CYREG_PRT0_PS\r
-SCSI_Out__REQ__SHIFT EQU 3\r
-SCSI_Out__REQ__SLW EQU CYREG_PRT0_SLW\r
-SCSI_Out__RST__AG EQU CYREG_PRT4_AG\r
-SCSI_Out__RST__AMUX EQU CYREG_PRT4_AMUX\r
-SCSI_Out__RST__BIE EQU CYREG_PRT4_BIE\r
-SCSI_Out__RST__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
-SCSI_Out__RST__BYP EQU CYREG_PRT4_BYP\r
-SCSI_Out__RST__CTL EQU CYREG_PRT4_CTL\r
-SCSI_Out__RST__DM0 EQU CYREG_PRT4_DM0\r
-SCSI_Out__RST__DM1 EQU CYREG_PRT4_DM1\r
-SCSI_Out__RST__DM2 EQU CYREG_PRT4_DM2\r
-SCSI_Out__RST__DR EQU CYREG_PRT4_DR\r
-SCSI_Out__RST__INP_DIS EQU CYREG_PRT4_INP_DIS\r
-SCSI_Out__RST__INTTYPE EQU CYREG_PICU4_INTTYPE5\r
-SCSI_Out__RST__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
-SCSI_Out__RST__LCD_EN EQU CYREG_PRT4_LCD_EN\r
-SCSI_Out__RST__MASK EQU 0x20\r
-SCSI_Out__RST__PC EQU CYREG_PRT4_PC5\r
-SCSI_Out__RST__PORT EQU 4\r
-SCSI_Out__RST__PRT EQU CYREG_PRT4_PRT\r
-SCSI_Out__RST__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
-SCSI_Out__RST__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
-SCSI_Out__RST__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
-SCSI_Out__RST__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
-SCSI_Out__RST__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
-SCSI_Out__RST__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
-SCSI_Out__RST__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
-SCSI_Out__RST__PS EQU CYREG_PRT4_PS\r
-SCSI_Out__RST__SHIFT EQU 5\r
-SCSI_Out__RST__SLW EQU CYREG_PRT4_SLW\r
-SCSI_Out__SEL__AG EQU CYREG_PRT0_AG\r
-SCSI_Out__SEL__AMUX EQU CYREG_PRT0_AMUX\r
-SCSI_Out__SEL__BIE EQU CYREG_PRT0_BIE\r
-SCSI_Out__SEL__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
-SCSI_Out__SEL__BYP EQU CYREG_PRT0_BYP\r
-SCSI_Out__SEL__CTL EQU CYREG_PRT0_CTL\r
-SCSI_Out__SEL__DM0 EQU CYREG_PRT0_DM0\r
-SCSI_Out__SEL__DM1 EQU CYREG_PRT0_DM1\r
-SCSI_Out__SEL__DM2 EQU CYREG_PRT0_DM2\r
-SCSI_Out__SEL__DR EQU CYREG_PRT0_DR\r
-SCSI_Out__SEL__INP_DIS EQU CYREG_PRT0_INP_DIS\r
-SCSI_Out__SEL__INTTYPE EQU CYREG_PICU0_INTTYPE7\r
-SCSI_Out__SEL__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
-SCSI_Out__SEL__LCD_EN EQU CYREG_PRT0_LCD_EN\r
-SCSI_Out__SEL__MASK EQU 0x80\r
-SCSI_Out__SEL__PC EQU CYREG_PRT0_PC7\r
-SCSI_Out__SEL__PORT EQU 0\r
-SCSI_Out__SEL__PRT EQU CYREG_PRT0_PRT\r
-SCSI_Out__SEL__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
-SCSI_Out__SEL__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
-SCSI_Out__SEL__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
-SCSI_Out__SEL__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
-SCSI_Out__SEL__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
-SCSI_Out__SEL__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
-SCSI_Out__SEL__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
-SCSI_Out__SEL__PS EQU CYREG_PRT0_PS\r
-SCSI_Out__SEL__SHIFT EQU 7\r
-SCSI_Out__SEL__SLW EQU CYREG_PRT0_SLW\r
-\r
-/* SCSI_Out_Bits */\r
-SCSI_Out_Bits_Sync_ctrl_reg__0__MASK EQU 0x01\r
-SCSI_Out_Bits_Sync_ctrl_reg__0__POS EQU 0\r
-SCSI_Out_Bits_Sync_ctrl_reg__1__MASK EQU 0x02\r
-SCSI_Out_Bits_Sync_ctrl_reg__1__POS EQU 1\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB14_15_ACTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB14_15_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB14_15_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB14_15_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB14_15_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB14_15_MSK\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB14_15_MSK\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB14_15_MSK\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB14_15_MSK\r
-SCSI_Out_Bits_Sync_ctrl_reg__2__MASK EQU 0x04\r
-SCSI_Out_Bits_Sync_ctrl_reg__2__POS EQU 2\r
-SCSI_Out_Bits_Sync_ctrl_reg__3__MASK EQU 0x08\r
-SCSI_Out_Bits_Sync_ctrl_reg__3__POS EQU 3\r
-SCSI_Out_Bits_Sync_ctrl_reg__4__MASK EQU 0x10\r
-SCSI_Out_Bits_Sync_ctrl_reg__4__POS EQU 4\r
-SCSI_Out_Bits_Sync_ctrl_reg__5__MASK EQU 0x20\r
-SCSI_Out_Bits_Sync_ctrl_reg__5__POS EQU 5\r
-SCSI_Out_Bits_Sync_ctrl_reg__6__MASK EQU 0x40\r
-SCSI_Out_Bits_Sync_ctrl_reg__6__POS EQU 6\r
-SCSI_Out_Bits_Sync_ctrl_reg__7__MASK EQU 0x80\r
-SCSI_Out_Bits_Sync_ctrl_reg__7__POS EQU 7\r
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB14_ACTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB14_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB14_ST_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB14_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB14_ST_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__MASK EQU 0xFF\r
-SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB14_MSK_ACTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB14_MSK_ACTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB14_MSK\r
-\r
-/* SCSI_Out_Ctl */\r
-SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01\r
-SCSI_Out_Ctl_Sync_ctrl_reg__0__POS EQU 0\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB12_13_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB12_13_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB12_13_MSK\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB12_13_MSK\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK\r
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB12_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB12_ST_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB12_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB12_ST_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__MASK EQU 0x01\r
-SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB12_MSK\r
-\r
-/* SCSI_Out_DBx */\r
-SCSI_Out_DBx__0__AG EQU CYREG_PRT5_AG\r
-SCSI_Out_DBx__0__AMUX EQU CYREG_PRT5_AMUX\r
-SCSI_Out_DBx__0__BIE EQU CYREG_PRT5_BIE\r
-SCSI_Out_DBx__0__BIT_MASK EQU CYREG_PRT5_BIT_MASK\r
-SCSI_Out_DBx__0__BYP EQU CYREG_PRT5_BYP\r
-SCSI_Out_DBx__0__CTL EQU CYREG_PRT5_CTL\r
-SCSI_Out_DBx__0__DM0 EQU CYREG_PRT5_DM0\r
-SCSI_Out_DBx__0__DM1 EQU CYREG_PRT5_DM1\r
-SCSI_Out_DBx__0__DM2 EQU CYREG_PRT5_DM2\r
-SCSI_Out_DBx__0__DR EQU CYREG_PRT5_DR\r
-SCSI_Out_DBx__0__INP_DIS EQU CYREG_PRT5_INP_DIS\r
-SCSI_Out_DBx__0__INTTYPE EQU CYREG_PICU5_INTTYPE1\r
-SCSI_Out_DBx__0__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG\r
-SCSI_Out_DBx__0__LCD_EN EQU CYREG_PRT5_LCD_EN\r
-SCSI_Out_DBx__0__MASK EQU 0x02\r
-SCSI_Out_DBx__0__PC EQU CYREG_PRT5_PC1\r
-SCSI_Out_DBx__0__PORT EQU 5\r
-SCSI_Out_DBx__0__PRT EQU CYREG_PRT5_PRT\r
-SCSI_Out_DBx__0__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL\r
-SCSI_Out_DBx__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN\r
-SCSI_Out_DBx__0__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0\r
-SCSI_Out_DBx__0__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1\r
-SCSI_Out_DBx__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0\r
-SCSI_Out_DBx__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1\r
-SCSI_Out_DBx__0__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT\r
-SCSI_Out_DBx__0__PS EQU CYREG_PRT5_PS\r
-SCSI_Out_DBx__0__SHIFT EQU 1\r
-SCSI_Out_DBx__0__SLW EQU CYREG_PRT5_SLW\r
-SCSI_Out_DBx__1__AG EQU CYREG_PRT5_AG\r
-SCSI_Out_DBx__1__AMUX EQU CYREG_PRT5_AMUX\r
-SCSI_Out_DBx__1__BIE EQU CYREG_PRT5_BIE\r
-SCSI_Out_DBx__1__BIT_MASK EQU CYREG_PRT5_BIT_MASK\r
-SCSI_Out_DBx__1__BYP EQU CYREG_PRT5_BYP\r
-SCSI_Out_DBx__1__CTL EQU CYREG_PRT5_CTL\r
-SCSI_Out_DBx__1__DM0 EQU CYREG_PRT5_DM0\r
-SCSI_Out_DBx__1__DM1 EQU CYREG_PRT5_DM1\r
-SCSI_Out_DBx__1__DM2 EQU CYREG_PRT5_DM2\r
-SCSI_Out_DBx__1__DR EQU CYREG_PRT5_DR\r
-SCSI_Out_DBx__1__INP_DIS EQU CYREG_PRT5_INP_DIS\r
-SCSI_Out_DBx__1__INTTYPE EQU CYREG_PICU5_INTTYPE0\r
-SCSI_Out_DBx__1__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG\r
-SCSI_Out_DBx__1__LCD_EN EQU CYREG_PRT5_LCD_EN\r
-SCSI_Out_DBx__1__MASK EQU 0x01\r
-SCSI_Out_DBx__1__PC EQU CYREG_PRT5_PC0\r
-SCSI_Out_DBx__1__PORT EQU 5\r
-SCSI_Out_DBx__1__PRT EQU CYREG_PRT5_PRT\r
-SCSI_Out_DBx__1__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL\r
-SCSI_Out_DBx__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN\r
-SCSI_Out_DBx__1__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0\r
-SCSI_Out_DBx__1__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1\r
-SCSI_Out_DBx__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0\r
-SCSI_Out_DBx__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1\r
-SCSI_Out_DBx__1__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT\r
-SCSI_Out_DBx__1__PS EQU CYREG_PRT5_PS\r
-SCSI_Out_DBx__1__SHIFT EQU 0\r
-SCSI_Out_DBx__1__SLW EQU CYREG_PRT5_SLW\r
-SCSI_Out_DBx__2__AG EQU CYREG_PRT6_AG\r
-SCSI_Out_DBx__2__AMUX EQU CYREG_PRT6_AMUX\r
-SCSI_Out_DBx__2__BIE EQU CYREG_PRT6_BIE\r
-SCSI_Out_DBx__2__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
-SCSI_Out_DBx__2__BYP EQU CYREG_PRT6_BYP\r
-SCSI_Out_DBx__2__CTL EQU CYREG_PRT6_CTL\r
-SCSI_Out_DBx__2__DM0 EQU CYREG_PRT6_DM0\r
-SCSI_Out_DBx__2__DM1 EQU CYREG_PRT6_DM1\r
-SCSI_Out_DBx__2__DM2 EQU CYREG_PRT6_DM2\r
-SCSI_Out_DBx__2__DR EQU CYREG_PRT6_DR\r
-SCSI_Out_DBx__2__INP_DIS EQU CYREG_PRT6_INP_DIS\r
-SCSI_Out_DBx__2__INTTYPE EQU CYREG_PICU6_INTTYPE5\r
-SCSI_Out_DBx__2__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
-SCSI_Out_DBx__2__LCD_EN EQU CYREG_PRT6_LCD_EN\r
-SCSI_Out_DBx__2__MASK EQU 0x20\r
-SCSI_Out_DBx__2__PC EQU CYREG_PRT6_PC5\r
-SCSI_Out_DBx__2__PORT EQU 6\r
-SCSI_Out_DBx__2__PRT EQU CYREG_PRT6_PRT\r
-SCSI_Out_DBx__2__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
-SCSI_Out_DBx__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
-SCSI_Out_DBx__2__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
-SCSI_Out_DBx__2__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
-SCSI_Out_DBx__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
-SCSI_Out_DBx__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
-SCSI_Out_DBx__2__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
-SCSI_Out_DBx__2__PS EQU CYREG_PRT6_PS\r
-SCSI_Out_DBx__2__SHIFT EQU 5\r
-SCSI_Out_DBx__2__SLW EQU CYREG_PRT6_SLW\r
-SCSI_Out_DBx__3__AG EQU CYREG_PRT6_AG\r
-SCSI_Out_DBx__3__AMUX EQU CYREG_PRT6_AMUX\r
-SCSI_Out_DBx__3__BIE EQU CYREG_PRT6_BIE\r
-SCSI_Out_DBx__3__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
-SCSI_Out_DBx__3__BYP EQU CYREG_PRT6_BYP\r
-SCSI_Out_DBx__3__CTL EQU CYREG_PRT6_CTL\r
-SCSI_Out_DBx__3__DM0 EQU CYREG_PRT6_DM0\r
-SCSI_Out_DBx__3__DM1 EQU CYREG_PRT6_DM1\r
-SCSI_Out_DBx__3__DM2 EQU CYREG_PRT6_DM2\r
-SCSI_Out_DBx__3__DR EQU CYREG_PRT6_DR\r
-SCSI_Out_DBx__3__INP_DIS EQU CYREG_PRT6_INP_DIS\r
-SCSI_Out_DBx__3__INTTYPE EQU CYREG_PICU6_INTTYPE4\r
-SCSI_Out_DBx__3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
-SCSI_Out_DBx__3__LCD_EN EQU CYREG_PRT6_LCD_EN\r
-SCSI_Out_DBx__3__MASK EQU 0x10\r
-SCSI_Out_DBx__3__PC EQU CYREG_PRT6_PC4\r
-SCSI_Out_DBx__3__PORT EQU 6\r
-SCSI_Out_DBx__3__PRT EQU CYREG_PRT6_PRT\r
-SCSI_Out_DBx__3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
-SCSI_Out_DBx__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
-SCSI_Out_DBx__3__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
-SCSI_Out_DBx__3__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
-SCSI_Out_DBx__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
-SCSI_Out_DBx__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
-SCSI_Out_DBx__3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
-SCSI_Out_DBx__3__PS EQU CYREG_PRT6_PS\r
-SCSI_Out_DBx__3__SHIFT EQU 4\r
-SCSI_Out_DBx__3__SLW EQU CYREG_PRT6_SLW\r
-SCSI_Out_DBx__4__AG EQU CYREG_PRT2_AG\r
-SCSI_Out_DBx__4__AMUX EQU CYREG_PRT2_AMUX\r
-SCSI_Out_DBx__4__BIE EQU CYREG_PRT2_BIE\r
-SCSI_Out_DBx__4__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
-SCSI_Out_DBx__4__BYP EQU CYREG_PRT2_BYP\r
-SCSI_Out_DBx__4__CTL EQU CYREG_PRT2_CTL\r
-SCSI_Out_DBx__4__DM0 EQU CYREG_PRT2_DM0\r
-SCSI_Out_DBx__4__DM1 EQU CYREG_PRT2_DM1\r
-SCSI_Out_DBx__4__DM2 EQU CYREG_PRT2_DM2\r
-SCSI_Out_DBx__4__DR EQU CYREG_PRT2_DR\r
-SCSI_Out_DBx__4__INP_DIS EQU CYREG_PRT2_INP_DIS\r
-SCSI_Out_DBx__4__INTTYPE EQU CYREG_PICU2_INTTYPE7\r
-SCSI_Out_DBx__4__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
-SCSI_Out_DBx__4__LCD_EN EQU CYREG_PRT2_LCD_EN\r
-SCSI_Out_DBx__4__MASK EQU 0x80\r
-SCSI_Out_DBx__4__PC EQU CYREG_PRT2_PC7\r
-SCSI_Out_DBx__4__PORT EQU 2\r
-SCSI_Out_DBx__4__PRT EQU CYREG_PRT2_PRT\r
-SCSI_Out_DBx__4__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
-SCSI_Out_DBx__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
-SCSI_Out_DBx__4__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
-SCSI_Out_DBx__4__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
-SCSI_Out_DBx__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
-SCSI_Out_DBx__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
-SCSI_Out_DBx__4__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
-SCSI_Out_DBx__4__PS EQU CYREG_PRT2_PS\r
-SCSI_Out_DBx__4__SHIFT EQU 7\r
-SCSI_Out_DBx__4__SLW EQU CYREG_PRT2_SLW\r
-SCSI_Out_DBx__5__AG EQU CYREG_PRT2_AG\r
-SCSI_Out_DBx__5__AMUX EQU CYREG_PRT2_AMUX\r
-SCSI_Out_DBx__5__BIE EQU CYREG_PRT2_BIE\r
-SCSI_Out_DBx__5__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
-SCSI_Out_DBx__5__BYP EQU CYREG_PRT2_BYP\r
-SCSI_Out_DBx__5__CTL EQU CYREG_PRT2_CTL\r
-SCSI_Out_DBx__5__DM0 EQU CYREG_PRT2_DM0\r
-SCSI_Out_DBx__5__DM1 EQU CYREG_PRT2_DM1\r
-SCSI_Out_DBx__5__DM2 EQU CYREG_PRT2_DM2\r
-SCSI_Out_DBx__5__DR EQU CYREG_PRT2_DR\r
-SCSI_Out_DBx__5__INP_DIS EQU CYREG_PRT2_INP_DIS\r
-SCSI_Out_DBx__5__INTTYPE EQU CYREG_PICU2_INTTYPE6\r
-SCSI_Out_DBx__5__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
-SCSI_Out_DBx__5__LCD_EN EQU CYREG_PRT2_LCD_EN\r
-SCSI_Out_DBx__5__MASK EQU 0x40\r
-SCSI_Out_DBx__5__PC EQU CYREG_PRT2_PC6\r
-SCSI_Out_DBx__5__PORT EQU 2\r
-SCSI_Out_DBx__5__PRT EQU CYREG_PRT2_PRT\r
-SCSI_Out_DBx__5__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
-SCSI_Out_DBx__5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
-SCSI_Out_DBx__5__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
-SCSI_Out_DBx__5__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
-SCSI_Out_DBx__5__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
-SCSI_Out_DBx__5__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
-SCSI_Out_DBx__5__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
-SCSI_Out_DBx__5__PS EQU CYREG_PRT2_PS\r
-SCSI_Out_DBx__5__SHIFT EQU 6\r
-SCSI_Out_DBx__5__SLW EQU CYREG_PRT2_SLW\r
-SCSI_Out_DBx__6__AG EQU CYREG_PRT2_AG\r
-SCSI_Out_DBx__6__AMUX EQU CYREG_PRT2_AMUX\r
-SCSI_Out_DBx__6__BIE EQU CYREG_PRT2_BIE\r
-SCSI_Out_DBx__6__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
-SCSI_Out_DBx__6__BYP EQU CYREG_PRT2_BYP\r
-SCSI_Out_DBx__6__CTL EQU CYREG_PRT2_CTL\r
-SCSI_Out_DBx__6__DM0 EQU CYREG_PRT2_DM0\r
-SCSI_Out_DBx__6__DM1 EQU CYREG_PRT2_DM1\r
-SCSI_Out_DBx__6__DM2 EQU CYREG_PRT2_DM2\r
-SCSI_Out_DBx__6__DR EQU CYREG_PRT2_DR\r
-SCSI_Out_DBx__6__INP_DIS EQU CYREG_PRT2_INP_DIS\r
-SCSI_Out_DBx__6__INTTYPE EQU CYREG_PICU2_INTTYPE3\r
-SCSI_Out_DBx__6__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
-SCSI_Out_DBx__6__LCD_EN EQU CYREG_PRT2_LCD_EN\r
-SCSI_Out_DBx__6__MASK EQU 0x08\r
-SCSI_Out_DBx__6__PC EQU CYREG_PRT2_PC3\r
-SCSI_Out_DBx__6__PORT EQU 2\r
-SCSI_Out_DBx__6__PRT EQU CYREG_PRT2_PRT\r
-SCSI_Out_DBx__6__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
-SCSI_Out_DBx__6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
-SCSI_Out_DBx__6__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
-SCSI_Out_DBx__6__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
-SCSI_Out_DBx__6__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
-SCSI_Out_DBx__6__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
-SCSI_Out_DBx__6__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
-SCSI_Out_DBx__6__PS EQU CYREG_PRT2_PS\r
-SCSI_Out_DBx__6__SHIFT EQU 3\r
-SCSI_Out_DBx__6__SLW EQU CYREG_PRT2_SLW\r
-SCSI_Out_DBx__7__AG EQU CYREG_PRT2_AG\r
-SCSI_Out_DBx__7__AMUX EQU CYREG_PRT2_AMUX\r
-SCSI_Out_DBx__7__BIE EQU CYREG_PRT2_BIE\r
-SCSI_Out_DBx__7__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
-SCSI_Out_DBx__7__BYP EQU CYREG_PRT2_BYP\r
-SCSI_Out_DBx__7__CTL EQU CYREG_PRT2_CTL\r
-SCSI_Out_DBx__7__DM0 EQU CYREG_PRT2_DM0\r
-SCSI_Out_DBx__7__DM1 EQU CYREG_PRT2_DM1\r
-SCSI_Out_DBx__7__DM2 EQU CYREG_PRT2_DM2\r
-SCSI_Out_DBx__7__DR EQU CYREG_PRT2_DR\r
-SCSI_Out_DBx__7__INP_DIS EQU CYREG_PRT2_INP_DIS\r
-SCSI_Out_DBx__7__INTTYPE EQU CYREG_PICU2_INTTYPE2\r
-SCSI_Out_DBx__7__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
-SCSI_Out_DBx__7__LCD_EN EQU CYREG_PRT2_LCD_EN\r
-SCSI_Out_DBx__7__MASK EQU 0x04\r
-SCSI_Out_DBx__7__PC EQU CYREG_PRT2_PC2\r
-SCSI_Out_DBx__7__PORT EQU 2\r
-SCSI_Out_DBx__7__PRT EQU CYREG_PRT2_PRT\r
-SCSI_Out_DBx__7__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
-SCSI_Out_DBx__7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
-SCSI_Out_DBx__7__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
-SCSI_Out_DBx__7__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
-SCSI_Out_DBx__7__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
-SCSI_Out_DBx__7__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
-SCSI_Out_DBx__7__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
-SCSI_Out_DBx__7__PS EQU CYREG_PRT2_PS\r
-SCSI_Out_DBx__7__SHIFT EQU 2\r
-SCSI_Out_DBx__7__SLW EQU CYREG_PRT2_SLW\r
-SCSI_Out_DBx__DB0__AG EQU CYREG_PRT5_AG\r
-SCSI_Out_DBx__DB0__AMUX EQU CYREG_PRT5_AMUX\r
-SCSI_Out_DBx__DB0__BIE EQU CYREG_PRT5_BIE\r
-SCSI_Out_DBx__DB0__BIT_MASK EQU CYREG_PRT5_BIT_MASK\r
-SCSI_Out_DBx__DB0__BYP EQU CYREG_PRT5_BYP\r
-SCSI_Out_DBx__DB0__CTL EQU CYREG_PRT5_CTL\r
-SCSI_Out_DBx__DB0__DM0 EQU CYREG_PRT5_DM0\r
-SCSI_Out_DBx__DB0__DM1 EQU CYREG_PRT5_DM1\r
-SCSI_Out_DBx__DB0__DM2 EQU CYREG_PRT5_DM2\r
-SCSI_Out_DBx__DB0__DR EQU CYREG_PRT5_DR\r
-SCSI_Out_DBx__DB0__INP_DIS EQU CYREG_PRT5_INP_DIS\r
-SCSI_Out_DBx__DB0__INTTYPE EQU CYREG_PICU5_INTTYPE1\r
-SCSI_Out_DBx__DB0__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG\r
-SCSI_Out_DBx__DB0__LCD_EN EQU CYREG_PRT5_LCD_EN\r
-SCSI_Out_DBx__DB0__MASK EQU 0x02\r
-SCSI_Out_DBx__DB0__PC EQU CYREG_PRT5_PC1\r
-SCSI_Out_DBx__DB0__PORT EQU 5\r
-SCSI_Out_DBx__DB0__PRT EQU CYREG_PRT5_PRT\r
-SCSI_Out_DBx__DB0__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL\r
-SCSI_Out_DBx__DB0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN\r
-SCSI_Out_DBx__DB0__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0\r
-SCSI_Out_DBx__DB0__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1\r
-SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0\r
-SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1\r
-SCSI_Out_DBx__DB0__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT\r
-SCSI_Out_DBx__DB0__PS EQU CYREG_PRT5_PS\r
-SCSI_Out_DBx__DB0__SHIFT EQU 1\r
-SCSI_Out_DBx__DB0__SLW EQU CYREG_PRT5_SLW\r
-SCSI_Out_DBx__DB1__AG EQU CYREG_PRT5_AG\r
-SCSI_Out_DBx__DB1__AMUX EQU CYREG_PRT5_AMUX\r
-SCSI_Out_DBx__DB1__BIE EQU CYREG_PRT5_BIE\r
-SCSI_Out_DBx__DB1__BIT_MASK EQU CYREG_PRT5_BIT_MASK\r
-SCSI_Out_DBx__DB1__BYP EQU CYREG_PRT5_BYP\r
-SCSI_Out_DBx__DB1__CTL EQU CYREG_PRT5_CTL\r
-SCSI_Out_DBx__DB1__DM0 EQU CYREG_PRT5_DM0\r
-SCSI_Out_DBx__DB1__DM1 EQU CYREG_PRT5_DM1\r
-SCSI_Out_DBx__DB1__DM2 EQU CYREG_PRT5_DM2\r
-SCSI_Out_DBx__DB1__DR EQU CYREG_PRT5_DR\r
-SCSI_Out_DBx__DB1__INP_DIS EQU CYREG_PRT5_INP_DIS\r
-SCSI_Out_DBx__DB1__INTTYPE EQU CYREG_PICU5_INTTYPE0\r
-SCSI_Out_DBx__DB1__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG\r
-SCSI_Out_DBx__DB1__LCD_EN EQU CYREG_PRT5_LCD_EN\r
-SCSI_Out_DBx__DB1__MASK EQU 0x01\r
-SCSI_Out_DBx__DB1__PC EQU CYREG_PRT5_PC0\r
-SCSI_Out_DBx__DB1__PORT EQU 5\r
-SCSI_Out_DBx__DB1__PRT EQU CYREG_PRT5_PRT\r
-SCSI_Out_DBx__DB1__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL\r
-SCSI_Out_DBx__DB1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN\r
-SCSI_Out_DBx__DB1__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0\r
-SCSI_Out_DBx__DB1__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1\r
-SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0\r
-SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1\r
-SCSI_Out_DBx__DB1__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT\r
-SCSI_Out_DBx__DB1__PS EQU CYREG_PRT5_PS\r
-SCSI_Out_DBx__DB1__SHIFT EQU 0\r
-SCSI_Out_DBx__DB1__SLW EQU CYREG_PRT5_SLW\r
-SCSI_Out_DBx__DB2__AG EQU CYREG_PRT6_AG\r
-SCSI_Out_DBx__DB2__AMUX EQU CYREG_PRT6_AMUX\r
-SCSI_Out_DBx__DB2__BIE EQU CYREG_PRT6_BIE\r
-SCSI_Out_DBx__DB2__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
-SCSI_Out_DBx__DB2__BYP EQU CYREG_PRT6_BYP\r
-SCSI_Out_DBx__DB2__CTL EQU CYREG_PRT6_CTL\r
-SCSI_Out_DBx__DB2__DM0 EQU CYREG_PRT6_DM0\r
-SCSI_Out_DBx__DB2__DM1 EQU CYREG_PRT6_DM1\r
-SCSI_Out_DBx__DB2__DM2 EQU CYREG_PRT6_DM2\r
-SCSI_Out_DBx__DB2__DR EQU CYREG_PRT6_DR\r
-SCSI_Out_DBx__DB2__INP_DIS EQU CYREG_PRT6_INP_DIS\r
-SCSI_Out_DBx__DB2__INTTYPE EQU CYREG_PICU6_INTTYPE5\r
-SCSI_Out_DBx__DB2__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
-SCSI_Out_DBx__DB2__LCD_EN EQU CYREG_PRT6_LCD_EN\r
-SCSI_Out_DBx__DB2__MASK EQU 0x20\r
-SCSI_Out_DBx__DB2__PC EQU CYREG_PRT6_PC5\r
-SCSI_Out_DBx__DB2__PORT EQU 6\r
-SCSI_Out_DBx__DB2__PRT EQU CYREG_PRT6_PRT\r
-SCSI_Out_DBx__DB2__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
-SCSI_Out_DBx__DB2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
-SCSI_Out_DBx__DB2__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
-SCSI_Out_DBx__DB2__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
-SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
-SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
-SCSI_Out_DBx__DB2__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
-SCSI_Out_DBx__DB2__PS EQU CYREG_PRT6_PS\r
-SCSI_Out_DBx__DB2__SHIFT EQU 5\r
-SCSI_Out_DBx__DB2__SLW EQU CYREG_PRT6_SLW\r
-SCSI_Out_DBx__DB3__AG EQU CYREG_PRT6_AG\r
-SCSI_Out_DBx__DB3__AMUX EQU CYREG_PRT6_AMUX\r
-SCSI_Out_DBx__DB3__BIE EQU CYREG_PRT6_BIE\r
-SCSI_Out_DBx__DB3__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
-SCSI_Out_DBx__DB3__BYP EQU CYREG_PRT6_BYP\r
-SCSI_Out_DBx__DB3__CTL EQU CYREG_PRT6_CTL\r
-SCSI_Out_DBx__DB3__DM0 EQU CYREG_PRT6_DM0\r
-SCSI_Out_DBx__DB3__DM1 EQU CYREG_PRT6_DM1\r
-SCSI_Out_DBx__DB3__DM2 EQU CYREG_PRT6_DM2\r
-SCSI_Out_DBx__DB3__DR EQU CYREG_PRT6_DR\r
-SCSI_Out_DBx__DB3__INP_DIS EQU CYREG_PRT6_INP_DIS\r
-SCSI_Out_DBx__DB3__INTTYPE EQU CYREG_PICU6_INTTYPE4\r
-SCSI_Out_DBx__DB3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
-SCSI_Out_DBx__DB3__LCD_EN EQU CYREG_PRT6_LCD_EN\r
-SCSI_Out_DBx__DB3__MASK EQU 0x10\r
-SCSI_Out_DBx__DB3__PC EQU CYREG_PRT6_PC4\r
-SCSI_Out_DBx__DB3__PORT EQU 6\r
-SCSI_Out_DBx__DB3__PRT EQU CYREG_PRT6_PRT\r
-SCSI_Out_DBx__DB3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
-SCSI_Out_DBx__DB3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
-SCSI_Out_DBx__DB3__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
-SCSI_Out_DBx__DB3__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
-SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
-SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
-SCSI_Out_DBx__DB3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
-SCSI_Out_DBx__DB3__PS EQU CYREG_PRT6_PS\r
-SCSI_Out_DBx__DB3__SHIFT EQU 4\r
-SCSI_Out_DBx__DB3__SLW EQU CYREG_PRT6_SLW\r
-SCSI_Out_DBx__DB4__AG EQU CYREG_PRT2_AG\r
-SCSI_Out_DBx__DB4__AMUX EQU CYREG_PRT2_AMUX\r
-SCSI_Out_DBx__DB4__BIE EQU CYREG_PRT2_BIE\r
-SCSI_Out_DBx__DB4__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
-SCSI_Out_DBx__DB4__BYP EQU CYREG_PRT2_BYP\r
-SCSI_Out_DBx__DB4__CTL EQU CYREG_PRT2_CTL\r
-SCSI_Out_DBx__DB4__DM0 EQU CYREG_PRT2_DM0\r
-SCSI_Out_DBx__DB4__DM1 EQU CYREG_PRT2_DM1\r
-SCSI_Out_DBx__DB4__DM2 EQU CYREG_PRT2_DM2\r
-SCSI_Out_DBx__DB4__DR EQU CYREG_PRT2_DR\r
-SCSI_Out_DBx__DB4__INP_DIS EQU CYREG_PRT2_INP_DIS\r
-SCSI_Out_DBx__DB4__INTTYPE EQU CYREG_PICU2_INTTYPE7\r
-SCSI_Out_DBx__DB4__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
-SCSI_Out_DBx__DB4__LCD_EN EQU CYREG_PRT2_LCD_EN\r
-SCSI_Out_DBx__DB4__MASK EQU 0x80\r
-SCSI_Out_DBx__DB4__PC EQU CYREG_PRT2_PC7\r
-SCSI_Out_DBx__DB4__PORT EQU 2\r
-SCSI_Out_DBx__DB4__PRT EQU CYREG_PRT2_PRT\r
-SCSI_Out_DBx__DB4__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
-SCSI_Out_DBx__DB4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
-SCSI_Out_DBx__DB4__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
-SCSI_Out_DBx__DB4__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
-SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
-SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
-SCSI_Out_DBx__DB4__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
-SCSI_Out_DBx__DB4__PS EQU CYREG_PRT2_PS\r
-SCSI_Out_DBx__DB4__SHIFT EQU 7\r
-SCSI_Out_DBx__DB4__SLW EQU CYREG_PRT2_SLW\r
-SCSI_Out_DBx__DB5__AG EQU CYREG_PRT2_AG\r
-SCSI_Out_DBx__DB5__AMUX EQU CYREG_PRT2_AMUX\r
-SCSI_Out_DBx__DB5__BIE EQU CYREG_PRT2_BIE\r
-SCSI_Out_DBx__DB5__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
-SCSI_Out_DBx__DB5__BYP EQU CYREG_PRT2_BYP\r
-SCSI_Out_DBx__DB5__CTL EQU CYREG_PRT2_CTL\r
-SCSI_Out_DBx__DB5__DM0 EQU CYREG_PRT2_DM0\r
-SCSI_Out_DBx__DB5__DM1 EQU CYREG_PRT2_DM1\r
-SCSI_Out_DBx__DB5__DM2 EQU CYREG_PRT2_DM2\r
-SCSI_Out_DBx__DB5__DR EQU CYREG_PRT2_DR\r
-SCSI_Out_DBx__DB5__INP_DIS EQU CYREG_PRT2_INP_DIS\r
-SCSI_Out_DBx__DB5__INTTYPE EQU CYREG_PICU2_INTTYPE6\r
-SCSI_Out_DBx__DB5__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
-SCSI_Out_DBx__DB5__LCD_EN EQU CYREG_PRT2_LCD_EN\r
-SCSI_Out_DBx__DB5__MASK EQU 0x40\r
-SCSI_Out_DBx__DB5__PC EQU CYREG_PRT2_PC6\r
-SCSI_Out_DBx__DB5__PORT EQU 2\r
-SCSI_Out_DBx__DB5__PRT EQU CYREG_PRT2_PRT\r
-SCSI_Out_DBx__DB5__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
-SCSI_Out_DBx__DB5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
-SCSI_Out_DBx__DB5__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
-SCSI_Out_DBx__DB5__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
-SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
-SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
-SCSI_Out_DBx__DB5__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
-SCSI_Out_DBx__DB5__PS EQU CYREG_PRT2_PS\r
-SCSI_Out_DBx__DB5__SHIFT EQU 6\r
-SCSI_Out_DBx__DB5__SLW EQU CYREG_PRT2_SLW\r
-SCSI_Out_DBx__DB6__AG EQU CYREG_PRT2_AG\r
-SCSI_Out_DBx__DB6__AMUX EQU CYREG_PRT2_AMUX\r
-SCSI_Out_DBx__DB6__BIE EQU CYREG_PRT2_BIE\r
-SCSI_Out_DBx__DB6__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
-SCSI_Out_DBx__DB6__BYP EQU CYREG_PRT2_BYP\r
-SCSI_Out_DBx__DB6__CTL EQU CYREG_PRT2_CTL\r
-SCSI_Out_DBx__DB6__DM0 EQU CYREG_PRT2_DM0\r
-SCSI_Out_DBx__DB6__DM1 EQU CYREG_PRT2_DM1\r
-SCSI_Out_DBx__DB6__DM2 EQU CYREG_PRT2_DM2\r
-SCSI_Out_DBx__DB6__DR EQU CYREG_PRT2_DR\r
-SCSI_Out_DBx__DB6__INP_DIS EQU CYREG_PRT2_INP_DIS\r
-SCSI_Out_DBx__DB6__INTTYPE EQU CYREG_PICU2_INTTYPE3\r
-SCSI_Out_DBx__DB6__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
-SCSI_Out_DBx__DB6__LCD_EN EQU CYREG_PRT2_LCD_EN\r
-SCSI_Out_DBx__DB6__MASK EQU 0x08\r
-SCSI_Out_DBx__DB6__PC EQU CYREG_PRT2_PC3\r
-SCSI_Out_DBx__DB6__PORT EQU 2\r
-SCSI_Out_DBx__DB6__PRT EQU CYREG_PRT2_PRT\r
-SCSI_Out_DBx__DB6__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
-SCSI_Out_DBx__DB6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
-SCSI_Out_DBx__DB6__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
-SCSI_Out_DBx__DB6__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
-SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
-SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
-SCSI_Out_DBx__DB6__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
-SCSI_Out_DBx__DB6__PS EQU CYREG_PRT2_PS\r
-SCSI_Out_DBx__DB6__SHIFT EQU 3\r
-SCSI_Out_DBx__DB6__SLW EQU CYREG_PRT2_SLW\r
-SCSI_Out_DBx__DB7__AG EQU CYREG_PRT2_AG\r
-SCSI_Out_DBx__DB7__AMUX EQU CYREG_PRT2_AMUX\r
-SCSI_Out_DBx__DB7__BIE EQU CYREG_PRT2_BIE\r
-SCSI_Out_DBx__DB7__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
-SCSI_Out_DBx__DB7__BYP EQU CYREG_PRT2_BYP\r
-SCSI_Out_DBx__DB7__CTL EQU CYREG_PRT2_CTL\r
-SCSI_Out_DBx__DB7__DM0 EQU CYREG_PRT2_DM0\r
-SCSI_Out_DBx__DB7__DM1 EQU CYREG_PRT2_DM1\r
-SCSI_Out_DBx__DB7__DM2 EQU CYREG_PRT2_DM2\r
-SCSI_Out_DBx__DB7__DR EQU CYREG_PRT2_DR\r
-SCSI_Out_DBx__DB7__INP_DIS EQU CYREG_PRT2_INP_DIS\r
-SCSI_Out_DBx__DB7__INTTYPE EQU CYREG_PICU2_INTTYPE2\r
-SCSI_Out_DBx__DB7__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
-SCSI_Out_DBx__DB7__LCD_EN EQU CYREG_PRT2_LCD_EN\r
-SCSI_Out_DBx__DB7__MASK EQU 0x04\r
-SCSI_Out_DBx__DB7__PC EQU CYREG_PRT2_PC2\r
-SCSI_Out_DBx__DB7__PORT EQU 2\r
-SCSI_Out_DBx__DB7__PRT EQU CYREG_PRT2_PRT\r
-SCSI_Out_DBx__DB7__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
-SCSI_Out_DBx__DB7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
-SCSI_Out_DBx__DB7__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
-SCSI_Out_DBx__DB7__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
-SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
-SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
-SCSI_Out_DBx__DB7__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
-SCSI_Out_DBx__DB7__PS EQU CYREG_PRT2_PS\r
-SCSI_Out_DBx__DB7__SHIFT EQU 2\r
-SCSI_Out_DBx__DB7__SLW EQU CYREG_PRT2_SLW\r
-\r
-/* SD_RX_DMA */\r
-SD_RX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0\r
-SD_RX_DMA__DRQ_NUMBER EQU 2\r
-SD_RX_DMA__NUMBEROF_TDS EQU 0\r
-SD_RX_DMA__PRIORITY EQU 0\r
-SD_RX_DMA__TERMIN_EN EQU 0\r
-SD_RX_DMA__TERMIN_SEL EQU 0\r
-SD_RX_DMA__TERMOUT0_EN EQU 1\r
-SD_RX_DMA__TERMOUT0_SEL EQU 2\r
-SD_RX_DMA__TERMOUT1_EN EQU 0\r
-SD_RX_DMA__TERMOUT1_SEL EQU 0\r
-\r
-/* SD_RX_DMA_COMPLETE */\r
-SD_RX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
-SD_RX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
-SD_RX_DMA_COMPLETE__INTC_MASK EQU 0x20\r
-SD_RX_DMA_COMPLETE__INTC_NUMBER EQU 5\r
-SD_RX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7\r
-SD_RX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_5\r
-SD_RX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
-SD_RX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
-\r
-/* SD_TX_DMA */\r
-SD_TX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0\r
-SD_TX_DMA__DRQ_NUMBER EQU 3\r
-SD_TX_DMA__NUMBEROF_TDS EQU 0\r
-SD_TX_DMA__PRIORITY EQU 1\r
-SD_TX_DMA__TERMIN_EN EQU 0\r
-SD_TX_DMA__TERMIN_SEL EQU 0\r
-SD_TX_DMA__TERMOUT0_EN EQU 1\r
-SD_TX_DMA__TERMOUT0_SEL EQU 3\r
-SD_TX_DMA__TERMOUT1_EN EQU 0\r
-SD_TX_DMA__TERMOUT1_SEL EQU 0\r
-\r
-/* SD_TX_DMA_COMPLETE */\r
-SD_TX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
-SD_TX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
-SD_TX_DMA_COMPLETE__INTC_MASK EQU 0x40\r
-SD_TX_DMA_COMPLETE__INTC_NUMBER EQU 6\r
-SD_TX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7\r
-SD_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_6\r
-SD_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
-SD_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
+/* SCSI_In */\r
+SCSI_In__0__AG EQU CYREG_PRT2_AG\r
+SCSI_In__0__AMUX EQU CYREG_PRT2_AMUX\r
+SCSI_In__0__BIE EQU CYREG_PRT2_BIE\r
+SCSI_In__0__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
+SCSI_In__0__BYP EQU CYREG_PRT2_BYP\r
+SCSI_In__0__CTL EQU CYREG_PRT2_CTL\r
+SCSI_In__0__DM0 EQU CYREG_PRT2_DM0\r
+SCSI_In__0__DM1 EQU CYREG_PRT2_DM1\r
+SCSI_In__0__DM2 EQU CYREG_PRT2_DM2\r
+SCSI_In__0__DR EQU CYREG_PRT2_DR\r
+SCSI_In__0__INP_DIS EQU CYREG_PRT2_INP_DIS\r
+SCSI_In__0__INTTYPE EQU CYREG_PICU2_INTTYPE1\r
+SCSI_In__0__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
+SCSI_In__0__LCD_EN EQU CYREG_PRT2_LCD_EN\r
+SCSI_In__0__MASK EQU 0x02\r
+SCSI_In__0__PC EQU CYREG_PRT2_PC1\r
+SCSI_In__0__PORT EQU 2\r
+SCSI_In__0__PRT EQU CYREG_PRT2_PRT\r
+SCSI_In__0__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
+SCSI_In__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
+SCSI_In__0__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
+SCSI_In__0__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
+SCSI_In__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
+SCSI_In__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
+SCSI_In__0__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
+SCSI_In__0__PS EQU CYREG_PRT2_PS\r
+SCSI_In__0__SHIFT EQU 1\r
+SCSI_In__0__SLW EQU CYREG_PRT2_SLW\r
+SCSI_In__1__AG EQU CYREG_PRT4_AG\r
+SCSI_In__1__AMUX EQU CYREG_PRT4_AMUX\r
+SCSI_In__1__BIE EQU CYREG_PRT4_BIE\r
+SCSI_In__1__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
+SCSI_In__1__BYP EQU CYREG_PRT4_BYP\r
+SCSI_In__1__CTL EQU CYREG_PRT4_CTL\r
+SCSI_In__1__DM0 EQU CYREG_PRT4_DM0\r
+SCSI_In__1__DM1 EQU CYREG_PRT4_DM1\r
+SCSI_In__1__DM2 EQU CYREG_PRT4_DM2\r
+SCSI_In__1__DR EQU CYREG_PRT4_DR\r
+SCSI_In__1__INP_DIS EQU CYREG_PRT4_INP_DIS\r
+SCSI_In__1__INTTYPE EQU CYREG_PICU4_INTTYPE6\r
+SCSI_In__1__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
+SCSI_In__1__LCD_EN EQU CYREG_PRT4_LCD_EN\r
+SCSI_In__1__MASK EQU 0x40\r
+SCSI_In__1__PC EQU CYREG_PRT4_PC6\r
+SCSI_In__1__PORT EQU 4\r
+SCSI_In__1__PRT EQU CYREG_PRT4_PRT\r
+SCSI_In__1__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
+SCSI_In__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
+SCSI_In__1__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
+SCSI_In__1__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
+SCSI_In__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
+SCSI_In__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
+SCSI_In__1__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
+SCSI_In__1__PS EQU CYREG_PRT4_PS\r
+SCSI_In__1__SHIFT EQU 6\r
+SCSI_In__1__SLW EQU CYREG_PRT4_SLW\r
+SCSI_In__2__AG EQU CYREG_PRT4_AG\r
+SCSI_In__2__AMUX EQU CYREG_PRT4_AMUX\r
+SCSI_In__2__BIE EQU CYREG_PRT4_BIE\r
+SCSI_In__2__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
+SCSI_In__2__BYP EQU CYREG_PRT4_BYP\r
+SCSI_In__2__CTL EQU CYREG_PRT4_CTL\r
+SCSI_In__2__DM0 EQU CYREG_PRT4_DM0\r
+SCSI_In__2__DM1 EQU CYREG_PRT4_DM1\r
+SCSI_In__2__DM2 EQU CYREG_PRT4_DM2\r
+SCSI_In__2__DR EQU CYREG_PRT4_DR\r
+SCSI_In__2__INP_DIS EQU CYREG_PRT4_INP_DIS\r
+SCSI_In__2__INTTYPE EQU CYREG_PICU4_INTTYPE2\r
+SCSI_In__2__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
+SCSI_In__2__LCD_EN EQU CYREG_PRT4_LCD_EN\r
+SCSI_In__2__MASK EQU 0x04\r
+SCSI_In__2__PC EQU CYREG_PRT4_PC2\r
+SCSI_In__2__PORT EQU 4\r
+SCSI_In__2__PRT EQU CYREG_PRT4_PRT\r
+SCSI_In__2__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
+SCSI_In__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
+SCSI_In__2__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
+SCSI_In__2__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
+SCSI_In__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
+SCSI_In__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
+SCSI_In__2__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
+SCSI_In__2__PS EQU CYREG_PRT4_PS\r
+SCSI_In__2__SHIFT EQU 2\r
+SCSI_In__2__SLW EQU CYREG_PRT4_SLW\r
+SCSI_In__3__AG EQU CYREG_PRT0_AG\r
+SCSI_In__3__AMUX EQU CYREG_PRT0_AMUX\r
+SCSI_In__3__BIE EQU CYREG_PRT0_BIE\r
+SCSI_In__3__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
+SCSI_In__3__BYP EQU CYREG_PRT0_BYP\r
+SCSI_In__3__CTL EQU CYREG_PRT0_CTL\r
+SCSI_In__3__DM0 EQU CYREG_PRT0_DM0\r
+SCSI_In__3__DM1 EQU CYREG_PRT0_DM1\r
+SCSI_In__3__DM2 EQU CYREG_PRT0_DM2\r
+SCSI_In__3__DR EQU CYREG_PRT0_DR\r
+SCSI_In__3__INP_DIS EQU CYREG_PRT0_INP_DIS\r
+SCSI_In__3__INTTYPE EQU CYREG_PICU0_INTTYPE5\r
+SCSI_In__3__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
+SCSI_In__3__LCD_EN EQU CYREG_PRT0_LCD_EN\r
+SCSI_In__3__MASK EQU 0x20\r
+SCSI_In__3__PC EQU CYREG_PRT0_PC5\r
+SCSI_In__3__PORT EQU 0\r
+SCSI_In__3__PRT EQU CYREG_PRT0_PRT\r
+SCSI_In__3__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
+SCSI_In__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
+SCSI_In__3__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
+SCSI_In__3__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
+SCSI_In__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
+SCSI_In__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
+SCSI_In__3__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
+SCSI_In__3__PS EQU CYREG_PRT0_PS\r
+SCSI_In__3__SHIFT EQU 5\r
+SCSI_In__3__SLW EQU CYREG_PRT0_SLW\r
+SCSI_In__4__AG EQU CYREG_PRT0_AG\r
+SCSI_In__4__AMUX EQU CYREG_PRT0_AMUX\r
+SCSI_In__4__BIE EQU CYREG_PRT0_BIE\r
+SCSI_In__4__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
+SCSI_In__4__BYP EQU CYREG_PRT0_BYP\r
+SCSI_In__4__CTL EQU CYREG_PRT0_CTL\r
+SCSI_In__4__DM0 EQU CYREG_PRT0_DM0\r
+SCSI_In__4__DM1 EQU CYREG_PRT0_DM1\r
+SCSI_In__4__DM2 EQU CYREG_PRT0_DM2\r
+SCSI_In__4__DR EQU CYREG_PRT0_DR\r
+SCSI_In__4__INP_DIS EQU CYREG_PRT0_INP_DIS\r
+SCSI_In__4__INTTYPE EQU CYREG_PICU0_INTTYPE4\r
+SCSI_In__4__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
+SCSI_In__4__LCD_EN EQU CYREG_PRT0_LCD_EN\r
+SCSI_In__4__MASK EQU 0x10\r
+SCSI_In__4__PC EQU CYREG_PRT0_PC4\r
+SCSI_In__4__PORT EQU 0\r
+SCSI_In__4__PRT EQU CYREG_PRT0_PRT\r
+SCSI_In__4__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
+SCSI_In__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
+SCSI_In__4__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
+SCSI_In__4__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
+SCSI_In__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
+SCSI_In__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
+SCSI_In__4__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
+SCSI_In__4__PS EQU CYREG_PRT0_PS\r
+SCSI_In__4__SHIFT EQU 4\r
+SCSI_In__4__SLW EQU CYREG_PRT0_SLW\r
+SCSI_In__CD__AG EQU CYREG_PRT4_AG\r
+SCSI_In__CD__AMUX EQU CYREG_PRT4_AMUX\r
+SCSI_In__CD__BIE EQU CYREG_PRT4_BIE\r
+SCSI_In__CD__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
+SCSI_In__CD__BYP EQU CYREG_PRT4_BYP\r
+SCSI_In__CD__CTL EQU CYREG_PRT4_CTL\r
+SCSI_In__CD__DM0 EQU CYREG_PRT4_DM0\r
+SCSI_In__CD__DM1 EQU CYREG_PRT4_DM1\r
+SCSI_In__CD__DM2 EQU CYREG_PRT4_DM2\r
+SCSI_In__CD__DR EQU CYREG_PRT4_DR\r
+SCSI_In__CD__INP_DIS EQU CYREG_PRT4_INP_DIS\r
+SCSI_In__CD__INTTYPE EQU CYREG_PICU4_INTTYPE2\r
+SCSI_In__CD__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
+SCSI_In__CD__LCD_EN EQU CYREG_PRT4_LCD_EN\r
+SCSI_In__CD__MASK EQU 0x04\r
+SCSI_In__CD__PC EQU CYREG_PRT4_PC2\r
+SCSI_In__CD__PORT EQU 4\r
+SCSI_In__CD__PRT EQU CYREG_PRT4_PRT\r
+SCSI_In__CD__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
+SCSI_In__CD__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
+SCSI_In__CD__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
+SCSI_In__CD__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
+SCSI_In__CD__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
+SCSI_In__CD__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
+SCSI_In__CD__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
+SCSI_In__CD__PS EQU CYREG_PRT4_PS\r
+SCSI_In__CD__SHIFT EQU 2\r
+SCSI_In__CD__SLW EQU CYREG_PRT4_SLW\r
+SCSI_In__DBP__AG EQU CYREG_PRT2_AG\r
+SCSI_In__DBP__AMUX EQU CYREG_PRT2_AMUX\r
+SCSI_In__DBP__BIE EQU CYREG_PRT2_BIE\r
+SCSI_In__DBP__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
+SCSI_In__DBP__BYP EQU CYREG_PRT2_BYP\r
+SCSI_In__DBP__CTL EQU CYREG_PRT2_CTL\r
+SCSI_In__DBP__DM0 EQU CYREG_PRT2_DM0\r
+SCSI_In__DBP__DM1 EQU CYREG_PRT2_DM1\r
+SCSI_In__DBP__DM2 EQU CYREG_PRT2_DM2\r
+SCSI_In__DBP__DR EQU CYREG_PRT2_DR\r
+SCSI_In__DBP__INP_DIS EQU CYREG_PRT2_INP_DIS\r
+SCSI_In__DBP__INTTYPE EQU CYREG_PICU2_INTTYPE1\r
+SCSI_In__DBP__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
+SCSI_In__DBP__LCD_EN EQU CYREG_PRT2_LCD_EN\r
+SCSI_In__DBP__MASK EQU 0x02\r
+SCSI_In__DBP__PC EQU CYREG_PRT2_PC1\r
+SCSI_In__DBP__PORT EQU 2\r
+SCSI_In__DBP__PRT EQU CYREG_PRT2_PRT\r
+SCSI_In__DBP__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
+SCSI_In__DBP__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
+SCSI_In__DBP__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
+SCSI_In__DBP__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
+SCSI_In__DBP__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
+SCSI_In__DBP__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
+SCSI_In__DBP__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
+SCSI_In__DBP__PS EQU CYREG_PRT2_PS\r
+SCSI_In__DBP__SHIFT EQU 1\r
+SCSI_In__DBP__SLW EQU CYREG_PRT2_SLW\r
+SCSI_In__IO__AG EQU CYREG_PRT0_AG\r
+SCSI_In__IO__AMUX EQU CYREG_PRT0_AMUX\r
+SCSI_In__IO__BIE EQU CYREG_PRT0_BIE\r
+SCSI_In__IO__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
+SCSI_In__IO__BYP EQU CYREG_PRT0_BYP\r
+SCSI_In__IO__CTL EQU CYREG_PRT0_CTL\r
+SCSI_In__IO__DM0 EQU CYREG_PRT0_DM0\r
+SCSI_In__IO__DM1 EQU CYREG_PRT0_DM1\r
+SCSI_In__IO__DM2 EQU CYREG_PRT0_DM2\r
+SCSI_In__IO__DR EQU CYREG_PRT0_DR\r
+SCSI_In__IO__INP_DIS EQU CYREG_PRT0_INP_DIS\r
+SCSI_In__IO__INTTYPE EQU CYREG_PICU0_INTTYPE4\r
+SCSI_In__IO__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
+SCSI_In__IO__LCD_EN EQU CYREG_PRT0_LCD_EN\r
+SCSI_In__IO__MASK EQU 0x10\r
+SCSI_In__IO__PC EQU CYREG_PRT0_PC4\r
+SCSI_In__IO__PORT EQU 0\r
+SCSI_In__IO__PRT EQU CYREG_PRT0_PRT\r
+SCSI_In__IO__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
+SCSI_In__IO__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
+SCSI_In__IO__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
+SCSI_In__IO__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
+SCSI_In__IO__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
+SCSI_In__IO__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
+SCSI_In__IO__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
+SCSI_In__IO__PS EQU CYREG_PRT0_PS\r
+SCSI_In__IO__SHIFT EQU 4\r
+SCSI_In__IO__SLW EQU CYREG_PRT0_SLW\r
+SCSI_In__MSG__AG EQU CYREG_PRT4_AG\r
+SCSI_In__MSG__AMUX EQU CYREG_PRT4_AMUX\r
+SCSI_In__MSG__BIE EQU CYREG_PRT4_BIE\r
+SCSI_In__MSG__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
+SCSI_In__MSG__BYP EQU CYREG_PRT4_BYP\r
+SCSI_In__MSG__CTL EQU CYREG_PRT4_CTL\r
+SCSI_In__MSG__DM0 EQU CYREG_PRT4_DM0\r
+SCSI_In__MSG__DM1 EQU CYREG_PRT4_DM1\r
+SCSI_In__MSG__DM2 EQU CYREG_PRT4_DM2\r
+SCSI_In__MSG__DR EQU CYREG_PRT4_DR\r
+SCSI_In__MSG__INP_DIS EQU CYREG_PRT4_INP_DIS\r
+SCSI_In__MSG__INTTYPE EQU CYREG_PICU4_INTTYPE6\r
+SCSI_In__MSG__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
+SCSI_In__MSG__LCD_EN EQU CYREG_PRT4_LCD_EN\r
+SCSI_In__MSG__MASK EQU 0x40\r
+SCSI_In__MSG__PC EQU CYREG_PRT4_PC6\r
+SCSI_In__MSG__PORT EQU 4\r
+SCSI_In__MSG__PRT EQU CYREG_PRT4_PRT\r
+SCSI_In__MSG__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
+SCSI_In__MSG__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
+SCSI_In__MSG__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
+SCSI_In__MSG__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
+SCSI_In__MSG__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
+SCSI_In__MSG__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
+SCSI_In__MSG__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
+SCSI_In__MSG__PS EQU CYREG_PRT4_PS\r
+SCSI_In__MSG__SHIFT EQU 6\r
+SCSI_In__MSG__SLW EQU CYREG_PRT4_SLW\r
+SCSI_In__REQ__AG EQU CYREG_PRT0_AG\r
+SCSI_In__REQ__AMUX EQU CYREG_PRT0_AMUX\r
+SCSI_In__REQ__BIE EQU CYREG_PRT0_BIE\r
+SCSI_In__REQ__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
+SCSI_In__REQ__BYP EQU CYREG_PRT0_BYP\r
+SCSI_In__REQ__CTL EQU CYREG_PRT0_CTL\r
+SCSI_In__REQ__DM0 EQU CYREG_PRT0_DM0\r
+SCSI_In__REQ__DM1 EQU CYREG_PRT0_DM1\r
+SCSI_In__REQ__DM2 EQU CYREG_PRT0_DM2\r
+SCSI_In__REQ__DR EQU CYREG_PRT0_DR\r
+SCSI_In__REQ__INP_DIS EQU CYREG_PRT0_INP_DIS\r
+SCSI_In__REQ__INTTYPE EQU CYREG_PICU0_INTTYPE5\r
+SCSI_In__REQ__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
+SCSI_In__REQ__LCD_EN EQU CYREG_PRT0_LCD_EN\r
+SCSI_In__REQ__MASK EQU 0x20\r
+SCSI_In__REQ__PC EQU CYREG_PRT0_PC5\r
+SCSI_In__REQ__PORT EQU 0\r
+SCSI_In__REQ__PRT EQU CYREG_PRT0_PRT\r
+SCSI_In__REQ__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
+SCSI_In__REQ__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
+SCSI_In__REQ__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
+SCSI_In__REQ__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
+SCSI_In__REQ__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
+SCSI_In__REQ__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
+SCSI_In__REQ__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
+SCSI_In__REQ__PS EQU CYREG_PRT0_PS\r
+SCSI_In__REQ__SHIFT EQU 5\r
+SCSI_In__REQ__SLW EQU CYREG_PRT0_SLW\r
+SCSI_In_DBx__0__AG EQU CYREG_PRT5_AG\r
+SCSI_In_DBx__0__AMUX EQU CYREG_PRT5_AMUX\r
+SCSI_In_DBx__0__BIE EQU CYREG_PRT5_BIE\r
+SCSI_In_DBx__0__BIT_MASK EQU CYREG_PRT5_BIT_MASK\r
+SCSI_In_DBx__0__BYP EQU CYREG_PRT5_BYP\r
+SCSI_In_DBx__0__CTL EQU CYREG_PRT5_CTL\r
+SCSI_In_DBx__0__DM0 EQU CYREG_PRT5_DM0\r
+SCSI_In_DBx__0__DM1 EQU CYREG_PRT5_DM1\r
+SCSI_In_DBx__0__DM2 EQU CYREG_PRT5_DM2\r
+SCSI_In_DBx__0__DR EQU CYREG_PRT5_DR\r
+SCSI_In_DBx__0__INP_DIS EQU CYREG_PRT5_INP_DIS\r
+SCSI_In_DBx__0__INTTYPE EQU CYREG_PICU5_INTTYPE3\r
+SCSI_In_DBx__0__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG\r
+SCSI_In_DBx__0__LCD_EN EQU CYREG_PRT5_LCD_EN\r
+SCSI_In_DBx__0__MASK EQU 0x08\r
+SCSI_In_DBx__0__PC EQU CYREG_PRT5_PC3\r
+SCSI_In_DBx__0__PORT EQU 5\r
+SCSI_In_DBx__0__PRT EQU CYREG_PRT5_PRT\r
+SCSI_In_DBx__0__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL\r
+SCSI_In_DBx__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN\r
+SCSI_In_DBx__0__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0\r
+SCSI_In_DBx__0__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1\r
+SCSI_In_DBx__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0\r
+SCSI_In_DBx__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1\r
+SCSI_In_DBx__0__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT\r
+SCSI_In_DBx__0__PS EQU CYREG_PRT5_PS\r
+SCSI_In_DBx__0__SHIFT EQU 3\r
+SCSI_In_DBx__0__SLW EQU CYREG_PRT5_SLW\r
+SCSI_In_DBx__1__AG EQU CYREG_PRT5_AG\r
+SCSI_In_DBx__1__AMUX EQU CYREG_PRT5_AMUX\r
+SCSI_In_DBx__1__BIE EQU CYREG_PRT5_BIE\r
+SCSI_In_DBx__1__BIT_MASK EQU CYREG_PRT5_BIT_MASK\r
+SCSI_In_DBx__1__BYP EQU CYREG_PRT5_BYP\r
+SCSI_In_DBx__1__CTL EQU CYREG_PRT5_CTL\r
+SCSI_In_DBx__1__DM0 EQU CYREG_PRT5_DM0\r
+SCSI_In_DBx__1__DM1 EQU CYREG_PRT5_DM1\r
+SCSI_In_DBx__1__DM2 EQU CYREG_PRT5_DM2\r
+SCSI_In_DBx__1__DR EQU CYREG_PRT5_DR\r
+SCSI_In_DBx__1__INP_DIS EQU CYREG_PRT5_INP_DIS\r
+SCSI_In_DBx__1__INTTYPE EQU CYREG_PICU5_INTTYPE2\r
+SCSI_In_DBx__1__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG\r
+SCSI_In_DBx__1__LCD_EN EQU CYREG_PRT5_LCD_EN\r
+SCSI_In_DBx__1__MASK EQU 0x04\r
+SCSI_In_DBx__1__PC EQU CYREG_PRT5_PC2\r
+SCSI_In_DBx__1__PORT EQU 5\r
+SCSI_In_DBx__1__PRT EQU CYREG_PRT5_PRT\r
+SCSI_In_DBx__1__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL\r
+SCSI_In_DBx__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN\r
+SCSI_In_DBx__1__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0\r
+SCSI_In_DBx__1__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1\r
+SCSI_In_DBx__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0\r
+SCSI_In_DBx__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1\r
+SCSI_In_DBx__1__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT\r
+SCSI_In_DBx__1__PS EQU CYREG_PRT5_PS\r
+SCSI_In_DBx__1__SHIFT EQU 2\r
+SCSI_In_DBx__1__SLW EQU CYREG_PRT5_SLW\r
+SCSI_In_DBx__2__AG EQU CYREG_PRT6_AG\r
+SCSI_In_DBx__2__AMUX EQU CYREG_PRT6_AMUX\r
+SCSI_In_DBx__2__BIE EQU CYREG_PRT6_BIE\r
+SCSI_In_DBx__2__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
+SCSI_In_DBx__2__BYP EQU CYREG_PRT6_BYP\r
+SCSI_In_DBx__2__CTL EQU CYREG_PRT6_CTL\r
+SCSI_In_DBx__2__DM0 EQU CYREG_PRT6_DM0\r
+SCSI_In_DBx__2__DM1 EQU CYREG_PRT6_DM1\r
+SCSI_In_DBx__2__DM2 EQU CYREG_PRT6_DM2\r
+SCSI_In_DBx__2__DR EQU CYREG_PRT6_DR\r
+SCSI_In_DBx__2__INP_DIS EQU CYREG_PRT6_INP_DIS\r
+SCSI_In_DBx__2__INTTYPE EQU CYREG_PICU6_INTTYPE7\r
+SCSI_In_DBx__2__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
+SCSI_In_DBx__2__LCD_EN EQU CYREG_PRT6_LCD_EN\r
+SCSI_In_DBx__2__MASK EQU 0x80\r
+SCSI_In_DBx__2__PC EQU CYREG_PRT6_PC7\r
+SCSI_In_DBx__2__PORT EQU 6\r
+SCSI_In_DBx__2__PRT EQU CYREG_PRT6_PRT\r
+SCSI_In_DBx__2__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
+SCSI_In_DBx__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
+SCSI_In_DBx__2__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
+SCSI_In_DBx__2__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
+SCSI_In_DBx__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
+SCSI_In_DBx__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
+SCSI_In_DBx__2__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
+SCSI_In_DBx__2__PS EQU CYREG_PRT6_PS\r
+SCSI_In_DBx__2__SHIFT EQU 7\r
+SCSI_In_DBx__2__SLW EQU CYREG_PRT6_SLW\r
+SCSI_In_DBx__3__AG EQU CYREG_PRT6_AG\r
+SCSI_In_DBx__3__AMUX EQU CYREG_PRT6_AMUX\r
+SCSI_In_DBx__3__BIE EQU CYREG_PRT6_BIE\r
+SCSI_In_DBx__3__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
+SCSI_In_DBx__3__BYP EQU CYREG_PRT6_BYP\r
+SCSI_In_DBx__3__CTL EQU CYREG_PRT6_CTL\r
+SCSI_In_DBx__3__DM0 EQU CYREG_PRT6_DM0\r
+SCSI_In_DBx__3__DM1 EQU CYREG_PRT6_DM1\r
+SCSI_In_DBx__3__DM2 EQU CYREG_PRT6_DM2\r
+SCSI_In_DBx__3__DR EQU CYREG_PRT6_DR\r
+SCSI_In_DBx__3__INP_DIS EQU CYREG_PRT6_INP_DIS\r
+SCSI_In_DBx__3__INTTYPE EQU CYREG_PICU6_INTTYPE6\r
+SCSI_In_DBx__3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
+SCSI_In_DBx__3__LCD_EN EQU CYREG_PRT6_LCD_EN\r
+SCSI_In_DBx__3__MASK EQU 0x40\r
+SCSI_In_DBx__3__PC EQU CYREG_PRT6_PC6\r
+SCSI_In_DBx__3__PORT EQU 6\r
+SCSI_In_DBx__3__PRT EQU CYREG_PRT6_PRT\r
+SCSI_In_DBx__3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
+SCSI_In_DBx__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
+SCSI_In_DBx__3__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
+SCSI_In_DBx__3__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
+SCSI_In_DBx__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
+SCSI_In_DBx__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
+SCSI_In_DBx__3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
+SCSI_In_DBx__3__PS EQU CYREG_PRT6_PS\r
+SCSI_In_DBx__3__SHIFT EQU 6\r
+SCSI_In_DBx__3__SLW EQU CYREG_PRT6_SLW\r
+SCSI_In_DBx__4__AG EQU CYREG_PRT12_AG\r
+SCSI_In_DBx__4__BIE EQU CYREG_PRT12_BIE\r
+SCSI_In_DBx__4__BIT_MASK EQU CYREG_PRT12_BIT_MASK\r
+SCSI_In_DBx__4__BYP EQU CYREG_PRT12_BYP\r
+SCSI_In_DBx__4__DM0 EQU CYREG_PRT12_DM0\r
+SCSI_In_DBx__4__DM1 EQU CYREG_PRT12_DM1\r
+SCSI_In_DBx__4__DM2 EQU CYREG_PRT12_DM2\r
+SCSI_In_DBx__4__DR EQU CYREG_PRT12_DR\r
+SCSI_In_DBx__4__INP_DIS EQU CYREG_PRT12_INP_DIS\r
+SCSI_In_DBx__4__INTTYPE EQU CYREG_PICU12_INTTYPE5\r
+SCSI_In_DBx__4__MASK EQU 0x20\r
+SCSI_In_DBx__4__PC EQU CYREG_PRT12_PC5\r
+SCSI_In_DBx__4__PORT EQU 12\r
+SCSI_In_DBx__4__PRT EQU CYREG_PRT12_PRT\r
+SCSI_In_DBx__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN\r
+SCSI_In_DBx__4__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0\r
+SCSI_In_DBx__4__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1\r
+SCSI_In_DBx__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0\r
+SCSI_In_DBx__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1\r
+SCSI_In_DBx__4__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT\r
+SCSI_In_DBx__4__PS EQU CYREG_PRT12_PS\r
+SCSI_In_DBx__4__SHIFT EQU 5\r
+SCSI_In_DBx__4__SIO_CFG EQU CYREG_PRT12_SIO_CFG\r
+SCSI_In_DBx__4__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF\r
+SCSI_In_DBx__4__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN\r
+SCSI_In_DBx__4__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ\r
+SCSI_In_DBx__4__SLW EQU CYREG_PRT12_SLW\r
+SCSI_In_DBx__5__AG EQU CYREG_PRT12_AG\r
+SCSI_In_DBx__5__BIE EQU CYREG_PRT12_BIE\r
+SCSI_In_DBx__5__BIT_MASK EQU CYREG_PRT12_BIT_MASK\r
+SCSI_In_DBx__5__BYP EQU CYREG_PRT12_BYP\r
+SCSI_In_DBx__5__DM0 EQU CYREG_PRT12_DM0\r
+SCSI_In_DBx__5__DM1 EQU CYREG_PRT12_DM1\r
+SCSI_In_DBx__5__DM2 EQU CYREG_PRT12_DM2\r
+SCSI_In_DBx__5__DR EQU CYREG_PRT12_DR\r
+SCSI_In_DBx__5__INP_DIS EQU CYREG_PRT12_INP_DIS\r
+SCSI_In_DBx__5__INTTYPE EQU CYREG_PICU12_INTTYPE4\r
+SCSI_In_DBx__5__MASK EQU 0x10\r
+SCSI_In_DBx__5__PC EQU CYREG_PRT12_PC4\r
+SCSI_In_DBx__5__PORT EQU 12\r
+SCSI_In_DBx__5__PRT EQU CYREG_PRT12_PRT\r
+SCSI_In_DBx__5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN\r
+SCSI_In_DBx__5__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0\r
+SCSI_In_DBx__5__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1\r
+SCSI_In_DBx__5__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0\r
+SCSI_In_DBx__5__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1\r
+SCSI_In_DBx__5__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT\r
+SCSI_In_DBx__5__PS EQU CYREG_PRT12_PS\r
+SCSI_In_DBx__5__SHIFT EQU 4\r
+SCSI_In_DBx__5__SIO_CFG EQU CYREG_PRT12_SIO_CFG\r
+SCSI_In_DBx__5__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF\r
+SCSI_In_DBx__5__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN\r
+SCSI_In_DBx__5__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ\r
+SCSI_In_DBx__5__SLW EQU CYREG_PRT12_SLW\r
+SCSI_In_DBx__6__AG EQU CYREG_PRT2_AG\r
+SCSI_In_DBx__6__AMUX EQU CYREG_PRT2_AMUX\r
+SCSI_In_DBx__6__BIE EQU CYREG_PRT2_BIE\r
+SCSI_In_DBx__6__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
+SCSI_In_DBx__6__BYP EQU CYREG_PRT2_BYP\r
+SCSI_In_DBx__6__CTL EQU CYREG_PRT2_CTL\r
+SCSI_In_DBx__6__DM0 EQU CYREG_PRT2_DM0\r
+SCSI_In_DBx__6__DM1 EQU CYREG_PRT2_DM1\r
+SCSI_In_DBx__6__DM2 EQU CYREG_PRT2_DM2\r
+SCSI_In_DBx__6__DR EQU CYREG_PRT2_DR\r
+SCSI_In_DBx__6__INP_DIS EQU CYREG_PRT2_INP_DIS\r
+SCSI_In_DBx__6__INTTYPE EQU CYREG_PICU2_INTTYPE5\r
+SCSI_In_DBx__6__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
+SCSI_In_DBx__6__LCD_EN EQU CYREG_PRT2_LCD_EN\r
+SCSI_In_DBx__6__MASK EQU 0x20\r
+SCSI_In_DBx__6__PC EQU CYREG_PRT2_PC5\r
+SCSI_In_DBx__6__PORT EQU 2\r
+SCSI_In_DBx__6__PRT EQU CYREG_PRT2_PRT\r
+SCSI_In_DBx__6__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
+SCSI_In_DBx__6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
+SCSI_In_DBx__6__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
+SCSI_In_DBx__6__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
+SCSI_In_DBx__6__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
+SCSI_In_DBx__6__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
+SCSI_In_DBx__6__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
+SCSI_In_DBx__6__PS EQU CYREG_PRT2_PS\r
+SCSI_In_DBx__6__SHIFT EQU 5\r
+SCSI_In_DBx__6__SLW EQU CYREG_PRT2_SLW\r
+SCSI_In_DBx__7__AG EQU CYREG_PRT2_AG\r
+SCSI_In_DBx__7__AMUX EQU CYREG_PRT2_AMUX\r
+SCSI_In_DBx__7__BIE EQU CYREG_PRT2_BIE\r
+SCSI_In_DBx__7__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
+SCSI_In_DBx__7__BYP EQU CYREG_PRT2_BYP\r
+SCSI_In_DBx__7__CTL EQU CYREG_PRT2_CTL\r
+SCSI_In_DBx__7__DM0 EQU CYREG_PRT2_DM0\r
+SCSI_In_DBx__7__DM1 EQU CYREG_PRT2_DM1\r
+SCSI_In_DBx__7__DM2 EQU CYREG_PRT2_DM2\r
+SCSI_In_DBx__7__DR EQU CYREG_PRT2_DR\r
+SCSI_In_DBx__7__INP_DIS EQU CYREG_PRT2_INP_DIS\r
+SCSI_In_DBx__7__INTTYPE EQU CYREG_PICU2_INTTYPE4\r
+SCSI_In_DBx__7__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
+SCSI_In_DBx__7__LCD_EN EQU CYREG_PRT2_LCD_EN\r
+SCSI_In_DBx__7__MASK EQU 0x10\r
+SCSI_In_DBx__7__PC EQU CYREG_PRT2_PC4\r
+SCSI_In_DBx__7__PORT EQU 2\r
+SCSI_In_DBx__7__PRT EQU CYREG_PRT2_PRT\r
+SCSI_In_DBx__7__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
+SCSI_In_DBx__7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
+SCSI_In_DBx__7__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
+SCSI_In_DBx__7__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
+SCSI_In_DBx__7__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
+SCSI_In_DBx__7__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
+SCSI_In_DBx__7__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
+SCSI_In_DBx__7__PS EQU CYREG_PRT2_PS\r
+SCSI_In_DBx__7__SHIFT EQU 4\r
+SCSI_In_DBx__7__SLW EQU CYREG_PRT2_SLW\r
+SCSI_In_DBx__DB0__AG EQU CYREG_PRT5_AG\r
+SCSI_In_DBx__DB0__AMUX EQU CYREG_PRT5_AMUX\r
+SCSI_In_DBx__DB0__BIE EQU CYREG_PRT5_BIE\r
+SCSI_In_DBx__DB0__BIT_MASK EQU CYREG_PRT5_BIT_MASK\r
+SCSI_In_DBx__DB0__BYP EQU CYREG_PRT5_BYP\r
+SCSI_In_DBx__DB0__CTL EQU CYREG_PRT5_CTL\r
+SCSI_In_DBx__DB0__DM0 EQU CYREG_PRT5_DM0\r
+SCSI_In_DBx__DB0__DM1 EQU CYREG_PRT5_DM1\r
+SCSI_In_DBx__DB0__DM2 EQU CYREG_PRT5_DM2\r
+SCSI_In_DBx__DB0__DR EQU CYREG_PRT5_DR\r
+SCSI_In_DBx__DB0__INP_DIS EQU CYREG_PRT5_INP_DIS\r
+SCSI_In_DBx__DB0__INTTYPE EQU CYREG_PICU5_INTTYPE3\r
+SCSI_In_DBx__DB0__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG\r
+SCSI_In_DBx__DB0__LCD_EN EQU CYREG_PRT5_LCD_EN\r
+SCSI_In_DBx__DB0__MASK EQU 0x08\r
+SCSI_In_DBx__DB0__PC EQU CYREG_PRT5_PC3\r
+SCSI_In_DBx__DB0__PORT EQU 5\r
+SCSI_In_DBx__DB0__PRT EQU CYREG_PRT5_PRT\r
+SCSI_In_DBx__DB0__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL\r
+SCSI_In_DBx__DB0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN\r
+SCSI_In_DBx__DB0__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0\r
+SCSI_In_DBx__DB0__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1\r
+SCSI_In_DBx__DB0__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0\r
+SCSI_In_DBx__DB0__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1\r
+SCSI_In_DBx__DB0__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT\r
+SCSI_In_DBx__DB0__PS EQU CYREG_PRT5_PS\r
+SCSI_In_DBx__DB0__SHIFT EQU 3\r
+SCSI_In_DBx__DB0__SLW EQU CYREG_PRT5_SLW\r
+SCSI_In_DBx__DB1__AG EQU CYREG_PRT5_AG\r
+SCSI_In_DBx__DB1__AMUX EQU CYREG_PRT5_AMUX\r
+SCSI_In_DBx__DB1__BIE EQU CYREG_PRT5_BIE\r
+SCSI_In_DBx__DB1__BIT_MASK EQU CYREG_PRT5_BIT_MASK\r
+SCSI_In_DBx__DB1__BYP EQU CYREG_PRT5_BYP\r
+SCSI_In_DBx__DB1__CTL EQU CYREG_PRT5_CTL\r
+SCSI_In_DBx__DB1__DM0 EQU CYREG_PRT5_DM0\r
+SCSI_In_DBx__DB1__DM1 EQU CYREG_PRT5_DM1\r
+SCSI_In_DBx__DB1__DM2 EQU CYREG_PRT5_DM2\r
+SCSI_In_DBx__DB1__DR EQU CYREG_PRT5_DR\r
+SCSI_In_DBx__DB1__INP_DIS EQU CYREG_PRT5_INP_DIS\r
+SCSI_In_DBx__DB1__INTTYPE EQU CYREG_PICU5_INTTYPE2\r
+SCSI_In_DBx__DB1__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG\r
+SCSI_In_DBx__DB1__LCD_EN EQU CYREG_PRT5_LCD_EN\r
+SCSI_In_DBx__DB1__MASK EQU 0x04\r
+SCSI_In_DBx__DB1__PC EQU CYREG_PRT5_PC2\r
+SCSI_In_DBx__DB1__PORT EQU 5\r
+SCSI_In_DBx__DB1__PRT EQU CYREG_PRT5_PRT\r
+SCSI_In_DBx__DB1__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL\r
+SCSI_In_DBx__DB1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN\r
+SCSI_In_DBx__DB1__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0\r
+SCSI_In_DBx__DB1__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1\r
+SCSI_In_DBx__DB1__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0\r
+SCSI_In_DBx__DB1__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1\r
+SCSI_In_DBx__DB1__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT\r
+SCSI_In_DBx__DB1__PS EQU CYREG_PRT5_PS\r
+SCSI_In_DBx__DB1__SHIFT EQU 2\r
+SCSI_In_DBx__DB1__SLW EQU CYREG_PRT5_SLW\r
+SCSI_In_DBx__DB2__AG EQU CYREG_PRT6_AG\r
+SCSI_In_DBx__DB2__AMUX EQU CYREG_PRT6_AMUX\r
+SCSI_In_DBx__DB2__BIE EQU CYREG_PRT6_BIE\r
+SCSI_In_DBx__DB2__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
+SCSI_In_DBx__DB2__BYP EQU CYREG_PRT6_BYP\r
+SCSI_In_DBx__DB2__CTL EQU CYREG_PRT6_CTL\r
+SCSI_In_DBx__DB2__DM0 EQU CYREG_PRT6_DM0\r
+SCSI_In_DBx__DB2__DM1 EQU CYREG_PRT6_DM1\r
+SCSI_In_DBx__DB2__DM2 EQU CYREG_PRT6_DM2\r
+SCSI_In_DBx__DB2__DR EQU CYREG_PRT6_DR\r
+SCSI_In_DBx__DB2__INP_DIS EQU CYREG_PRT6_INP_DIS\r
+SCSI_In_DBx__DB2__INTTYPE EQU CYREG_PICU6_INTTYPE7\r
+SCSI_In_DBx__DB2__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
+SCSI_In_DBx__DB2__LCD_EN EQU CYREG_PRT6_LCD_EN\r
+SCSI_In_DBx__DB2__MASK EQU 0x80\r
+SCSI_In_DBx__DB2__PC EQU CYREG_PRT6_PC7\r
+SCSI_In_DBx__DB2__PORT EQU 6\r
+SCSI_In_DBx__DB2__PRT EQU CYREG_PRT6_PRT\r
+SCSI_In_DBx__DB2__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
+SCSI_In_DBx__DB2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
+SCSI_In_DBx__DB2__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
+SCSI_In_DBx__DB2__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
+SCSI_In_DBx__DB2__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
+SCSI_In_DBx__DB2__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
+SCSI_In_DBx__DB2__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
+SCSI_In_DBx__DB2__PS EQU CYREG_PRT6_PS\r
+SCSI_In_DBx__DB2__SHIFT EQU 7\r
+SCSI_In_DBx__DB2__SLW EQU CYREG_PRT6_SLW\r
+SCSI_In_DBx__DB3__AG EQU CYREG_PRT6_AG\r
+SCSI_In_DBx__DB3__AMUX EQU CYREG_PRT6_AMUX\r
+SCSI_In_DBx__DB3__BIE EQU CYREG_PRT6_BIE\r
+SCSI_In_DBx__DB3__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
+SCSI_In_DBx__DB3__BYP EQU CYREG_PRT6_BYP\r
+SCSI_In_DBx__DB3__CTL EQU CYREG_PRT6_CTL\r
+SCSI_In_DBx__DB3__DM0 EQU CYREG_PRT6_DM0\r
+SCSI_In_DBx__DB3__DM1 EQU CYREG_PRT6_DM1\r
+SCSI_In_DBx__DB3__DM2 EQU CYREG_PRT6_DM2\r
+SCSI_In_DBx__DB3__DR EQU CYREG_PRT6_DR\r
+SCSI_In_DBx__DB3__INP_DIS EQU CYREG_PRT6_INP_DIS\r
+SCSI_In_DBx__DB3__INTTYPE EQU CYREG_PICU6_INTTYPE6\r
+SCSI_In_DBx__DB3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
+SCSI_In_DBx__DB3__LCD_EN EQU CYREG_PRT6_LCD_EN\r
+SCSI_In_DBx__DB3__MASK EQU 0x40\r
+SCSI_In_DBx__DB3__PC EQU CYREG_PRT6_PC6\r
+SCSI_In_DBx__DB3__PORT EQU 6\r
+SCSI_In_DBx__DB3__PRT EQU CYREG_PRT6_PRT\r
+SCSI_In_DBx__DB3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
+SCSI_In_DBx__DB3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
+SCSI_In_DBx__DB3__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
+SCSI_In_DBx__DB3__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
+SCSI_In_DBx__DB3__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
+SCSI_In_DBx__DB3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
+SCSI_In_DBx__DB3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
+SCSI_In_DBx__DB3__PS EQU CYREG_PRT6_PS\r
+SCSI_In_DBx__DB3__SHIFT EQU 6\r
+SCSI_In_DBx__DB3__SLW EQU CYREG_PRT6_SLW\r
+SCSI_In_DBx__DB4__AG EQU CYREG_PRT12_AG\r
+SCSI_In_DBx__DB4__BIE EQU CYREG_PRT12_BIE\r
+SCSI_In_DBx__DB4__BIT_MASK EQU CYREG_PRT12_BIT_MASK\r
+SCSI_In_DBx__DB4__BYP EQU CYREG_PRT12_BYP\r
+SCSI_In_DBx__DB4__DM0 EQU CYREG_PRT12_DM0\r
+SCSI_In_DBx__DB4__DM1 EQU CYREG_PRT12_DM1\r
+SCSI_In_DBx__DB4__DM2 EQU CYREG_PRT12_DM2\r
+SCSI_In_DBx__DB4__DR EQU CYREG_PRT12_DR\r
+SCSI_In_DBx__DB4__INP_DIS EQU CYREG_PRT12_INP_DIS\r
+SCSI_In_DBx__DB4__INTTYPE EQU CYREG_PICU12_INTTYPE5\r
+SCSI_In_DBx__DB4__MASK EQU 0x20\r
+SCSI_In_DBx__DB4__PC EQU CYREG_PRT12_PC5\r
+SCSI_In_DBx__DB4__PORT EQU 12\r
+SCSI_In_DBx__DB4__PRT EQU CYREG_PRT12_PRT\r
+SCSI_In_DBx__DB4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN\r
+SCSI_In_DBx__DB4__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0\r
+SCSI_In_DBx__DB4__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1\r
+SCSI_In_DBx__DB4__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0\r
+SCSI_In_DBx__DB4__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1\r
+SCSI_In_DBx__DB4__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT\r
+SCSI_In_DBx__DB4__PS EQU CYREG_PRT12_PS\r
+SCSI_In_DBx__DB4__SHIFT EQU 5\r
+SCSI_In_DBx__DB4__SIO_CFG EQU CYREG_PRT12_SIO_CFG\r
+SCSI_In_DBx__DB4__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF\r
+SCSI_In_DBx__DB4__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN\r
+SCSI_In_DBx__DB4__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ\r
+SCSI_In_DBx__DB4__SLW EQU CYREG_PRT12_SLW\r
+SCSI_In_DBx__DB5__AG EQU CYREG_PRT12_AG\r
+SCSI_In_DBx__DB5__BIE EQU CYREG_PRT12_BIE\r
+SCSI_In_DBx__DB5__BIT_MASK EQU CYREG_PRT12_BIT_MASK\r
+SCSI_In_DBx__DB5__BYP EQU CYREG_PRT12_BYP\r
+SCSI_In_DBx__DB5__DM0 EQU CYREG_PRT12_DM0\r
+SCSI_In_DBx__DB5__DM1 EQU CYREG_PRT12_DM1\r
+SCSI_In_DBx__DB5__DM2 EQU CYREG_PRT12_DM2\r
+SCSI_In_DBx__DB5__DR EQU CYREG_PRT12_DR\r
+SCSI_In_DBx__DB5__INP_DIS EQU CYREG_PRT12_INP_DIS\r
+SCSI_In_DBx__DB5__INTTYPE EQU CYREG_PICU12_INTTYPE4\r
+SCSI_In_DBx__DB5__MASK EQU 0x10\r
+SCSI_In_DBx__DB5__PC EQU CYREG_PRT12_PC4\r
+SCSI_In_DBx__DB5__PORT EQU 12\r
+SCSI_In_DBx__DB5__PRT EQU CYREG_PRT12_PRT\r
+SCSI_In_DBx__DB5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN\r
+SCSI_In_DBx__DB5__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0\r
+SCSI_In_DBx__DB5__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1\r
+SCSI_In_DBx__DB5__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0\r
+SCSI_In_DBx__DB5__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1\r
+SCSI_In_DBx__DB5__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT\r
+SCSI_In_DBx__DB5__PS EQU CYREG_PRT12_PS\r
+SCSI_In_DBx__DB5__SHIFT EQU 4\r
+SCSI_In_DBx__DB5__SIO_CFG EQU CYREG_PRT12_SIO_CFG\r
+SCSI_In_DBx__DB5__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF\r
+SCSI_In_DBx__DB5__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN\r
+SCSI_In_DBx__DB5__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ\r
+SCSI_In_DBx__DB5__SLW EQU CYREG_PRT12_SLW\r
+SCSI_In_DBx__DB6__AG EQU CYREG_PRT2_AG\r
+SCSI_In_DBx__DB6__AMUX EQU CYREG_PRT2_AMUX\r
+SCSI_In_DBx__DB6__BIE EQU CYREG_PRT2_BIE\r
+SCSI_In_DBx__DB6__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
+SCSI_In_DBx__DB6__BYP EQU CYREG_PRT2_BYP\r
+SCSI_In_DBx__DB6__CTL EQU CYREG_PRT2_CTL\r
+SCSI_In_DBx__DB6__DM0 EQU CYREG_PRT2_DM0\r
+SCSI_In_DBx__DB6__DM1 EQU CYREG_PRT2_DM1\r
+SCSI_In_DBx__DB6__DM2 EQU CYREG_PRT2_DM2\r
+SCSI_In_DBx__DB6__DR EQU CYREG_PRT2_DR\r
+SCSI_In_DBx__DB6__INP_DIS EQU CYREG_PRT2_INP_DIS\r
+SCSI_In_DBx__DB6__INTTYPE EQU CYREG_PICU2_INTTYPE5\r
+SCSI_In_DBx__DB6__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
+SCSI_In_DBx__DB6__LCD_EN EQU CYREG_PRT2_LCD_EN\r
+SCSI_In_DBx__DB6__MASK EQU 0x20\r
+SCSI_In_DBx__DB6__PC EQU CYREG_PRT2_PC5\r
+SCSI_In_DBx__DB6__PORT EQU 2\r
+SCSI_In_DBx__DB6__PRT EQU CYREG_PRT2_PRT\r
+SCSI_In_DBx__DB6__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
+SCSI_In_DBx__DB6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
+SCSI_In_DBx__DB6__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
+SCSI_In_DBx__DB6__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
+SCSI_In_DBx__DB6__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
+SCSI_In_DBx__DB6__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
+SCSI_In_DBx__DB6__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
+SCSI_In_DBx__DB6__PS EQU CYREG_PRT2_PS\r
+SCSI_In_DBx__DB6__SHIFT EQU 5\r
+SCSI_In_DBx__DB6__SLW EQU CYREG_PRT2_SLW\r
+SCSI_In_DBx__DB7__AG EQU CYREG_PRT2_AG\r
+SCSI_In_DBx__DB7__AMUX EQU CYREG_PRT2_AMUX\r
+SCSI_In_DBx__DB7__BIE EQU CYREG_PRT2_BIE\r
+SCSI_In_DBx__DB7__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
+SCSI_In_DBx__DB7__BYP EQU CYREG_PRT2_BYP\r
+SCSI_In_DBx__DB7__CTL EQU CYREG_PRT2_CTL\r
+SCSI_In_DBx__DB7__DM0 EQU CYREG_PRT2_DM0\r
+SCSI_In_DBx__DB7__DM1 EQU CYREG_PRT2_DM1\r
+SCSI_In_DBx__DB7__DM2 EQU CYREG_PRT2_DM2\r
+SCSI_In_DBx__DB7__DR EQU CYREG_PRT2_DR\r
+SCSI_In_DBx__DB7__INP_DIS EQU CYREG_PRT2_INP_DIS\r
+SCSI_In_DBx__DB7__INTTYPE EQU CYREG_PICU2_INTTYPE4\r
+SCSI_In_DBx__DB7__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
+SCSI_In_DBx__DB7__LCD_EN EQU CYREG_PRT2_LCD_EN\r
+SCSI_In_DBx__DB7__MASK EQU 0x10\r
+SCSI_In_DBx__DB7__PC EQU CYREG_PRT2_PC4\r
+SCSI_In_DBx__DB7__PORT EQU 2\r
+SCSI_In_DBx__DB7__PRT EQU CYREG_PRT2_PRT\r
+SCSI_In_DBx__DB7__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
+SCSI_In_DBx__DB7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
+SCSI_In_DBx__DB7__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
+SCSI_In_DBx__DB7__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
+SCSI_In_DBx__DB7__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
+SCSI_In_DBx__DB7__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
+SCSI_In_DBx__DB7__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
+SCSI_In_DBx__DB7__PS EQU CYREG_PRT2_PS\r
+SCSI_In_DBx__DB7__SHIFT EQU 4\r
+SCSI_In_DBx__DB7__SLW EQU CYREG_PRT2_SLW\r
 \r
 /* SCSI_Noise */\r
 SCSI_Noise__0__AG EQU CYREG_PRT2_AG\r
@@ -2735,6 +1199,1698 @@ SCSI_Noise__SEL__PS EQU CYREG_PRT4_PS
 SCSI_Noise__SEL__SHIFT EQU 3\r
 SCSI_Noise__SEL__SLW EQU CYREG_PRT4_SLW\r
 \r
+/* SCSI_Out */\r
+SCSI_Out__0__AG EQU CYREG_PRT15_AG\r
+SCSI_Out__0__AMUX EQU CYREG_PRT15_AMUX\r
+SCSI_Out__0__BIE EQU CYREG_PRT15_BIE\r
+SCSI_Out__0__BIT_MASK EQU CYREG_PRT15_BIT_MASK\r
+SCSI_Out__0__BYP EQU CYREG_PRT15_BYP\r
+SCSI_Out__0__CTL EQU CYREG_PRT15_CTL\r
+SCSI_Out__0__DM0 EQU CYREG_PRT15_DM0\r
+SCSI_Out__0__DM1 EQU CYREG_PRT15_DM1\r
+SCSI_Out__0__DM2 EQU CYREG_PRT15_DM2\r
+SCSI_Out__0__DR EQU CYREG_PRT15_DR\r
+SCSI_Out__0__INP_DIS EQU CYREG_PRT15_INP_DIS\r
+SCSI_Out__0__INTTYPE EQU CYREG_PICU15_INTTYPE5\r
+SCSI_Out__0__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG\r
+SCSI_Out__0__LCD_EN EQU CYREG_PRT15_LCD_EN\r
+SCSI_Out__0__MASK EQU 0x20\r
+SCSI_Out__0__PC EQU CYREG_IO_PC_PRT15_PC5\r
+SCSI_Out__0__PORT EQU 15\r
+SCSI_Out__0__PRT EQU CYREG_PRT15_PRT\r
+SCSI_Out__0__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL\r
+SCSI_Out__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN\r
+SCSI_Out__0__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0\r
+SCSI_Out__0__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1\r
+SCSI_Out__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0\r
+SCSI_Out__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1\r
+SCSI_Out__0__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT\r
+SCSI_Out__0__PS EQU CYREG_PRT15_PS\r
+SCSI_Out__0__SHIFT EQU 5\r
+SCSI_Out__0__SLW EQU CYREG_PRT15_SLW\r
+SCSI_Out__1__AG EQU CYREG_PRT15_AG\r
+SCSI_Out__1__AMUX EQU CYREG_PRT15_AMUX\r
+SCSI_Out__1__BIE EQU CYREG_PRT15_BIE\r
+SCSI_Out__1__BIT_MASK EQU CYREG_PRT15_BIT_MASK\r
+SCSI_Out__1__BYP EQU CYREG_PRT15_BYP\r
+SCSI_Out__1__CTL EQU CYREG_PRT15_CTL\r
+SCSI_Out__1__DM0 EQU CYREG_PRT15_DM0\r
+SCSI_Out__1__DM1 EQU CYREG_PRT15_DM1\r
+SCSI_Out__1__DM2 EQU CYREG_PRT15_DM2\r
+SCSI_Out__1__DR EQU CYREG_PRT15_DR\r
+SCSI_Out__1__INP_DIS EQU CYREG_PRT15_INP_DIS\r
+SCSI_Out__1__INTTYPE EQU CYREG_PICU15_INTTYPE4\r
+SCSI_Out__1__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG\r
+SCSI_Out__1__LCD_EN EQU CYREG_PRT15_LCD_EN\r
+SCSI_Out__1__MASK EQU 0x10\r
+SCSI_Out__1__PC EQU CYREG_IO_PC_PRT15_PC4\r
+SCSI_Out__1__PORT EQU 15\r
+SCSI_Out__1__PRT EQU CYREG_PRT15_PRT\r
+SCSI_Out__1__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL\r
+SCSI_Out__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN\r
+SCSI_Out__1__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0\r
+SCSI_Out__1__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1\r
+SCSI_Out__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0\r
+SCSI_Out__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1\r
+SCSI_Out__1__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT\r
+SCSI_Out__1__PS EQU CYREG_PRT15_PS\r
+SCSI_Out__1__SHIFT EQU 4\r
+SCSI_Out__1__SLW EQU CYREG_PRT15_SLW\r
+SCSI_Out__2__AG EQU CYREG_PRT6_AG\r
+SCSI_Out__2__AMUX EQU CYREG_PRT6_AMUX\r
+SCSI_Out__2__BIE EQU CYREG_PRT6_BIE\r
+SCSI_Out__2__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
+SCSI_Out__2__BYP EQU CYREG_PRT6_BYP\r
+SCSI_Out__2__CTL EQU CYREG_PRT6_CTL\r
+SCSI_Out__2__DM0 EQU CYREG_PRT6_DM0\r
+SCSI_Out__2__DM1 EQU CYREG_PRT6_DM1\r
+SCSI_Out__2__DM2 EQU CYREG_PRT6_DM2\r
+SCSI_Out__2__DR EQU CYREG_PRT6_DR\r
+SCSI_Out__2__INP_DIS EQU CYREG_PRT6_INP_DIS\r
+SCSI_Out__2__INTTYPE EQU CYREG_PICU6_INTTYPE1\r
+SCSI_Out__2__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
+SCSI_Out__2__LCD_EN EQU CYREG_PRT6_LCD_EN\r
+SCSI_Out__2__MASK EQU 0x02\r
+SCSI_Out__2__PC EQU CYREG_PRT6_PC1\r
+SCSI_Out__2__PORT EQU 6\r
+SCSI_Out__2__PRT EQU CYREG_PRT6_PRT\r
+SCSI_Out__2__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
+SCSI_Out__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
+SCSI_Out__2__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
+SCSI_Out__2__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
+SCSI_Out__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
+SCSI_Out__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
+SCSI_Out__2__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
+SCSI_Out__2__PS EQU CYREG_PRT6_PS\r
+SCSI_Out__2__SHIFT EQU 1\r
+SCSI_Out__2__SLW EQU CYREG_PRT6_SLW\r
+SCSI_Out__3__AG EQU CYREG_PRT6_AG\r
+SCSI_Out__3__AMUX EQU CYREG_PRT6_AMUX\r
+SCSI_Out__3__BIE EQU CYREG_PRT6_BIE\r
+SCSI_Out__3__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
+SCSI_Out__3__BYP EQU CYREG_PRT6_BYP\r
+SCSI_Out__3__CTL EQU CYREG_PRT6_CTL\r
+SCSI_Out__3__DM0 EQU CYREG_PRT6_DM0\r
+SCSI_Out__3__DM1 EQU CYREG_PRT6_DM1\r
+SCSI_Out__3__DM2 EQU CYREG_PRT6_DM2\r
+SCSI_Out__3__DR EQU CYREG_PRT6_DR\r
+SCSI_Out__3__INP_DIS EQU CYREG_PRT6_INP_DIS\r
+SCSI_Out__3__INTTYPE EQU CYREG_PICU6_INTTYPE0\r
+SCSI_Out__3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
+SCSI_Out__3__LCD_EN EQU CYREG_PRT6_LCD_EN\r
+SCSI_Out__3__MASK EQU 0x01\r
+SCSI_Out__3__PC EQU CYREG_PRT6_PC0\r
+SCSI_Out__3__PORT EQU 6\r
+SCSI_Out__3__PRT EQU CYREG_PRT6_PRT\r
+SCSI_Out__3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
+SCSI_Out__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
+SCSI_Out__3__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
+SCSI_Out__3__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
+SCSI_Out__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
+SCSI_Out__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
+SCSI_Out__3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
+SCSI_Out__3__PS EQU CYREG_PRT6_PS\r
+SCSI_Out__3__SHIFT EQU 0\r
+SCSI_Out__3__SLW EQU CYREG_PRT6_SLW\r
+SCSI_Out__4__AG EQU CYREG_PRT4_AG\r
+SCSI_Out__4__AMUX EQU CYREG_PRT4_AMUX\r
+SCSI_Out__4__BIE EQU CYREG_PRT4_BIE\r
+SCSI_Out__4__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
+SCSI_Out__4__BYP EQU CYREG_PRT4_BYP\r
+SCSI_Out__4__CTL EQU CYREG_PRT4_CTL\r
+SCSI_Out__4__DM0 EQU CYREG_PRT4_DM0\r
+SCSI_Out__4__DM1 EQU CYREG_PRT4_DM1\r
+SCSI_Out__4__DM2 EQU CYREG_PRT4_DM2\r
+SCSI_Out__4__DR EQU CYREG_PRT4_DR\r
+SCSI_Out__4__INP_DIS EQU CYREG_PRT4_INP_DIS\r
+SCSI_Out__4__INTTYPE EQU CYREG_PICU4_INTTYPE5\r
+SCSI_Out__4__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
+SCSI_Out__4__LCD_EN EQU CYREG_PRT4_LCD_EN\r
+SCSI_Out__4__MASK EQU 0x20\r
+SCSI_Out__4__PC EQU CYREG_PRT4_PC5\r
+SCSI_Out__4__PORT EQU 4\r
+SCSI_Out__4__PRT EQU CYREG_PRT4_PRT\r
+SCSI_Out__4__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
+SCSI_Out__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
+SCSI_Out__4__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
+SCSI_Out__4__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
+SCSI_Out__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
+SCSI_Out__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
+SCSI_Out__4__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
+SCSI_Out__4__PS EQU CYREG_PRT4_PS\r
+SCSI_Out__4__SHIFT EQU 5\r
+SCSI_Out__4__SLW EQU CYREG_PRT4_SLW\r
+SCSI_Out__5__AG EQU CYREG_PRT4_AG\r
+SCSI_Out__5__AMUX EQU CYREG_PRT4_AMUX\r
+SCSI_Out__5__BIE EQU CYREG_PRT4_BIE\r
+SCSI_Out__5__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
+SCSI_Out__5__BYP EQU CYREG_PRT4_BYP\r
+SCSI_Out__5__CTL EQU CYREG_PRT4_CTL\r
+SCSI_Out__5__DM0 EQU CYREG_PRT4_DM0\r
+SCSI_Out__5__DM1 EQU CYREG_PRT4_DM1\r
+SCSI_Out__5__DM2 EQU CYREG_PRT4_DM2\r
+SCSI_Out__5__DR EQU CYREG_PRT4_DR\r
+SCSI_Out__5__INP_DIS EQU CYREG_PRT4_INP_DIS\r
+SCSI_Out__5__INTTYPE EQU CYREG_PICU4_INTTYPE4\r
+SCSI_Out__5__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
+SCSI_Out__5__LCD_EN EQU CYREG_PRT4_LCD_EN\r
+SCSI_Out__5__MASK EQU 0x10\r
+SCSI_Out__5__PC EQU CYREG_PRT4_PC4\r
+SCSI_Out__5__PORT EQU 4\r
+SCSI_Out__5__PRT EQU CYREG_PRT4_PRT\r
+SCSI_Out__5__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
+SCSI_Out__5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
+SCSI_Out__5__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
+SCSI_Out__5__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
+SCSI_Out__5__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
+SCSI_Out__5__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
+SCSI_Out__5__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
+SCSI_Out__5__PS EQU CYREG_PRT4_PS\r
+SCSI_Out__5__SHIFT EQU 4\r
+SCSI_Out__5__SLW EQU CYREG_PRT4_SLW\r
+SCSI_Out__6__AG EQU CYREG_PRT0_AG\r
+SCSI_Out__6__AMUX EQU CYREG_PRT0_AMUX\r
+SCSI_Out__6__BIE EQU CYREG_PRT0_BIE\r
+SCSI_Out__6__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
+SCSI_Out__6__BYP EQU CYREG_PRT0_BYP\r
+SCSI_Out__6__CTL EQU CYREG_PRT0_CTL\r
+SCSI_Out__6__DM0 EQU CYREG_PRT0_DM0\r
+SCSI_Out__6__DM1 EQU CYREG_PRT0_DM1\r
+SCSI_Out__6__DM2 EQU CYREG_PRT0_DM2\r
+SCSI_Out__6__DR EQU CYREG_PRT0_DR\r
+SCSI_Out__6__INP_DIS EQU CYREG_PRT0_INP_DIS\r
+SCSI_Out__6__INTTYPE EQU CYREG_PICU0_INTTYPE7\r
+SCSI_Out__6__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
+SCSI_Out__6__LCD_EN EQU CYREG_PRT0_LCD_EN\r
+SCSI_Out__6__MASK EQU 0x80\r
+SCSI_Out__6__PC EQU CYREG_PRT0_PC7\r
+SCSI_Out__6__PORT EQU 0\r
+SCSI_Out__6__PRT EQU CYREG_PRT0_PRT\r
+SCSI_Out__6__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
+SCSI_Out__6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
+SCSI_Out__6__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
+SCSI_Out__6__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
+SCSI_Out__6__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
+SCSI_Out__6__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
+SCSI_Out__6__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
+SCSI_Out__6__PS EQU CYREG_PRT0_PS\r
+SCSI_Out__6__SHIFT EQU 7\r
+SCSI_Out__6__SLW EQU CYREG_PRT0_SLW\r
+SCSI_Out__7__AG EQU CYREG_PRT0_AG\r
+SCSI_Out__7__AMUX EQU CYREG_PRT0_AMUX\r
+SCSI_Out__7__BIE EQU CYREG_PRT0_BIE\r
+SCSI_Out__7__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
+SCSI_Out__7__BYP EQU CYREG_PRT0_BYP\r
+SCSI_Out__7__CTL EQU CYREG_PRT0_CTL\r
+SCSI_Out__7__DM0 EQU CYREG_PRT0_DM0\r
+SCSI_Out__7__DM1 EQU CYREG_PRT0_DM1\r
+SCSI_Out__7__DM2 EQU CYREG_PRT0_DM2\r
+SCSI_Out__7__DR EQU CYREG_PRT0_DR\r
+SCSI_Out__7__INP_DIS EQU CYREG_PRT0_INP_DIS\r
+SCSI_Out__7__INTTYPE EQU CYREG_PICU0_INTTYPE6\r
+SCSI_Out__7__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
+SCSI_Out__7__LCD_EN EQU CYREG_PRT0_LCD_EN\r
+SCSI_Out__7__MASK EQU 0x40\r
+SCSI_Out__7__PC EQU CYREG_PRT0_PC6\r
+SCSI_Out__7__PORT EQU 0\r
+SCSI_Out__7__PRT EQU CYREG_PRT0_PRT\r
+SCSI_Out__7__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
+SCSI_Out__7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
+SCSI_Out__7__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
+SCSI_Out__7__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
+SCSI_Out__7__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
+SCSI_Out__7__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
+SCSI_Out__7__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
+SCSI_Out__7__PS EQU CYREG_PRT0_PS\r
+SCSI_Out__7__SHIFT EQU 6\r
+SCSI_Out__7__SLW EQU CYREG_PRT0_SLW\r
+SCSI_Out__8__AG EQU CYREG_PRT0_AG\r
+SCSI_Out__8__AMUX EQU CYREG_PRT0_AMUX\r
+SCSI_Out__8__BIE EQU CYREG_PRT0_BIE\r
+SCSI_Out__8__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
+SCSI_Out__8__BYP EQU CYREG_PRT0_BYP\r
+SCSI_Out__8__CTL EQU CYREG_PRT0_CTL\r
+SCSI_Out__8__DM0 EQU CYREG_PRT0_DM0\r
+SCSI_Out__8__DM1 EQU CYREG_PRT0_DM1\r
+SCSI_Out__8__DM2 EQU CYREG_PRT0_DM2\r
+SCSI_Out__8__DR EQU CYREG_PRT0_DR\r
+SCSI_Out__8__INP_DIS EQU CYREG_PRT0_INP_DIS\r
+SCSI_Out__8__INTTYPE EQU CYREG_PICU0_INTTYPE3\r
+SCSI_Out__8__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
+SCSI_Out__8__LCD_EN EQU CYREG_PRT0_LCD_EN\r
+SCSI_Out__8__MASK EQU 0x08\r
+SCSI_Out__8__PC EQU CYREG_PRT0_PC3\r
+SCSI_Out__8__PORT EQU 0\r
+SCSI_Out__8__PRT EQU CYREG_PRT0_PRT\r
+SCSI_Out__8__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
+SCSI_Out__8__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
+SCSI_Out__8__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
+SCSI_Out__8__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
+SCSI_Out__8__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
+SCSI_Out__8__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
+SCSI_Out__8__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
+SCSI_Out__8__PS EQU CYREG_PRT0_PS\r
+SCSI_Out__8__SHIFT EQU 3\r
+SCSI_Out__8__SLW EQU CYREG_PRT0_SLW\r
+SCSI_Out__9__AG EQU CYREG_PRT0_AG\r
+SCSI_Out__9__AMUX EQU CYREG_PRT0_AMUX\r
+SCSI_Out__9__BIE EQU CYREG_PRT0_BIE\r
+SCSI_Out__9__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
+SCSI_Out__9__BYP EQU CYREG_PRT0_BYP\r
+SCSI_Out__9__CTL EQU CYREG_PRT0_CTL\r
+SCSI_Out__9__DM0 EQU CYREG_PRT0_DM0\r
+SCSI_Out__9__DM1 EQU CYREG_PRT0_DM1\r
+SCSI_Out__9__DM2 EQU CYREG_PRT0_DM2\r
+SCSI_Out__9__DR EQU CYREG_PRT0_DR\r
+SCSI_Out__9__INP_DIS EQU CYREG_PRT0_INP_DIS\r
+SCSI_Out__9__INTTYPE EQU CYREG_PICU0_INTTYPE2\r
+SCSI_Out__9__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
+SCSI_Out__9__LCD_EN EQU CYREG_PRT0_LCD_EN\r
+SCSI_Out__9__MASK EQU 0x04\r
+SCSI_Out__9__PC EQU CYREG_PRT0_PC2\r
+SCSI_Out__9__PORT EQU 0\r
+SCSI_Out__9__PRT EQU CYREG_PRT0_PRT\r
+SCSI_Out__9__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
+SCSI_Out__9__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
+SCSI_Out__9__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
+SCSI_Out__9__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
+SCSI_Out__9__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
+SCSI_Out__9__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
+SCSI_Out__9__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
+SCSI_Out__9__PS EQU CYREG_PRT0_PS\r
+SCSI_Out__9__SHIFT EQU 2\r
+SCSI_Out__9__SLW EQU CYREG_PRT0_SLW\r
+SCSI_Out__ACK__AG EQU CYREG_PRT6_AG\r
+SCSI_Out__ACK__AMUX EQU CYREG_PRT6_AMUX\r
+SCSI_Out__ACK__BIE EQU CYREG_PRT6_BIE\r
+SCSI_Out__ACK__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
+SCSI_Out__ACK__BYP EQU CYREG_PRT6_BYP\r
+SCSI_Out__ACK__CTL EQU CYREG_PRT6_CTL\r
+SCSI_Out__ACK__DM0 EQU CYREG_PRT6_DM0\r
+SCSI_Out__ACK__DM1 EQU CYREG_PRT6_DM1\r
+SCSI_Out__ACK__DM2 EQU CYREG_PRT6_DM2\r
+SCSI_Out__ACK__DR EQU CYREG_PRT6_DR\r
+SCSI_Out__ACK__INP_DIS EQU CYREG_PRT6_INP_DIS\r
+SCSI_Out__ACK__INTTYPE EQU CYREG_PICU6_INTTYPE0\r
+SCSI_Out__ACK__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
+SCSI_Out__ACK__LCD_EN EQU CYREG_PRT6_LCD_EN\r
+SCSI_Out__ACK__MASK EQU 0x01\r
+SCSI_Out__ACK__PC EQU CYREG_PRT6_PC0\r
+SCSI_Out__ACK__PORT EQU 6\r
+SCSI_Out__ACK__PRT EQU CYREG_PRT6_PRT\r
+SCSI_Out__ACK__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
+SCSI_Out__ACK__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
+SCSI_Out__ACK__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
+SCSI_Out__ACK__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
+SCSI_Out__ACK__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
+SCSI_Out__ACK__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
+SCSI_Out__ACK__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
+SCSI_Out__ACK__PS EQU CYREG_PRT6_PS\r
+SCSI_Out__ACK__SHIFT EQU 0\r
+SCSI_Out__ACK__SLW EQU CYREG_PRT6_SLW\r
+SCSI_Out__ATN__AG EQU CYREG_PRT15_AG\r
+SCSI_Out__ATN__AMUX EQU CYREG_PRT15_AMUX\r
+SCSI_Out__ATN__BIE EQU CYREG_PRT15_BIE\r
+SCSI_Out__ATN__BIT_MASK EQU CYREG_PRT15_BIT_MASK\r
+SCSI_Out__ATN__BYP EQU CYREG_PRT15_BYP\r
+SCSI_Out__ATN__CTL EQU CYREG_PRT15_CTL\r
+SCSI_Out__ATN__DM0 EQU CYREG_PRT15_DM0\r
+SCSI_Out__ATN__DM1 EQU CYREG_PRT15_DM1\r
+SCSI_Out__ATN__DM2 EQU CYREG_PRT15_DM2\r
+SCSI_Out__ATN__DR EQU CYREG_PRT15_DR\r
+SCSI_Out__ATN__INP_DIS EQU CYREG_PRT15_INP_DIS\r
+SCSI_Out__ATN__INTTYPE EQU CYREG_PICU15_INTTYPE4\r
+SCSI_Out__ATN__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG\r
+SCSI_Out__ATN__LCD_EN EQU CYREG_PRT15_LCD_EN\r
+SCSI_Out__ATN__MASK EQU 0x10\r
+SCSI_Out__ATN__PC EQU CYREG_IO_PC_PRT15_PC4\r
+SCSI_Out__ATN__PORT EQU 15\r
+SCSI_Out__ATN__PRT EQU CYREG_PRT15_PRT\r
+SCSI_Out__ATN__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL\r
+SCSI_Out__ATN__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN\r
+SCSI_Out__ATN__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0\r
+SCSI_Out__ATN__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1\r
+SCSI_Out__ATN__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0\r
+SCSI_Out__ATN__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1\r
+SCSI_Out__ATN__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT\r
+SCSI_Out__ATN__PS EQU CYREG_PRT15_PS\r
+SCSI_Out__ATN__SHIFT EQU 4\r
+SCSI_Out__ATN__SLW EQU CYREG_PRT15_SLW\r
+SCSI_Out__BSY__AG EQU CYREG_PRT6_AG\r
+SCSI_Out__BSY__AMUX EQU CYREG_PRT6_AMUX\r
+SCSI_Out__BSY__BIE EQU CYREG_PRT6_BIE\r
+SCSI_Out__BSY__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
+SCSI_Out__BSY__BYP EQU CYREG_PRT6_BYP\r
+SCSI_Out__BSY__CTL EQU CYREG_PRT6_CTL\r
+SCSI_Out__BSY__DM0 EQU CYREG_PRT6_DM0\r
+SCSI_Out__BSY__DM1 EQU CYREG_PRT6_DM1\r
+SCSI_Out__BSY__DM2 EQU CYREG_PRT6_DM2\r
+SCSI_Out__BSY__DR EQU CYREG_PRT6_DR\r
+SCSI_Out__BSY__INP_DIS EQU CYREG_PRT6_INP_DIS\r
+SCSI_Out__BSY__INTTYPE EQU CYREG_PICU6_INTTYPE1\r
+SCSI_Out__BSY__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
+SCSI_Out__BSY__LCD_EN EQU CYREG_PRT6_LCD_EN\r
+SCSI_Out__BSY__MASK EQU 0x02\r
+SCSI_Out__BSY__PC EQU CYREG_PRT6_PC1\r
+SCSI_Out__BSY__PORT EQU 6\r
+SCSI_Out__BSY__PRT EQU CYREG_PRT6_PRT\r
+SCSI_Out__BSY__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
+SCSI_Out__BSY__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
+SCSI_Out__BSY__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
+SCSI_Out__BSY__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
+SCSI_Out__BSY__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
+SCSI_Out__BSY__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
+SCSI_Out__BSY__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
+SCSI_Out__BSY__PS EQU CYREG_PRT6_PS\r
+SCSI_Out__BSY__SHIFT EQU 1\r
+SCSI_Out__BSY__SLW EQU CYREG_PRT6_SLW\r
+SCSI_Out__CD_raw__AG EQU CYREG_PRT0_AG\r
+SCSI_Out__CD_raw__AMUX EQU CYREG_PRT0_AMUX\r
+SCSI_Out__CD_raw__BIE EQU CYREG_PRT0_BIE\r
+SCSI_Out__CD_raw__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
+SCSI_Out__CD_raw__BYP EQU CYREG_PRT0_BYP\r
+SCSI_Out__CD_raw__CTL EQU CYREG_PRT0_CTL\r
+SCSI_Out__CD_raw__DM0 EQU CYREG_PRT0_DM0\r
+SCSI_Out__CD_raw__DM1 EQU CYREG_PRT0_DM1\r
+SCSI_Out__CD_raw__DM2 EQU CYREG_PRT0_DM2\r
+SCSI_Out__CD_raw__DR EQU CYREG_PRT0_DR\r
+SCSI_Out__CD_raw__INP_DIS EQU CYREG_PRT0_INP_DIS\r
+SCSI_Out__CD_raw__INTTYPE EQU CYREG_PICU0_INTTYPE6\r
+SCSI_Out__CD_raw__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
+SCSI_Out__CD_raw__LCD_EN EQU CYREG_PRT0_LCD_EN\r
+SCSI_Out__CD_raw__MASK EQU 0x40\r
+SCSI_Out__CD_raw__PC EQU CYREG_PRT0_PC6\r
+SCSI_Out__CD_raw__PORT EQU 0\r
+SCSI_Out__CD_raw__PRT EQU CYREG_PRT0_PRT\r
+SCSI_Out__CD_raw__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
+SCSI_Out__CD_raw__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
+SCSI_Out__CD_raw__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
+SCSI_Out__CD_raw__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
+SCSI_Out__CD_raw__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
+SCSI_Out__CD_raw__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
+SCSI_Out__CD_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
+SCSI_Out__CD_raw__PS EQU CYREG_PRT0_PS\r
+SCSI_Out__CD_raw__SHIFT EQU 6\r
+SCSI_Out__CD_raw__SLW EQU CYREG_PRT0_SLW\r
+SCSI_Out__DBP_raw__AG EQU CYREG_PRT15_AG\r
+SCSI_Out__DBP_raw__AMUX EQU CYREG_PRT15_AMUX\r
+SCSI_Out__DBP_raw__BIE EQU CYREG_PRT15_BIE\r
+SCSI_Out__DBP_raw__BIT_MASK EQU CYREG_PRT15_BIT_MASK\r
+SCSI_Out__DBP_raw__BYP EQU CYREG_PRT15_BYP\r
+SCSI_Out__DBP_raw__CTL EQU CYREG_PRT15_CTL\r
+SCSI_Out__DBP_raw__DM0 EQU CYREG_PRT15_DM0\r
+SCSI_Out__DBP_raw__DM1 EQU CYREG_PRT15_DM1\r
+SCSI_Out__DBP_raw__DM2 EQU CYREG_PRT15_DM2\r
+SCSI_Out__DBP_raw__DR EQU CYREG_PRT15_DR\r
+SCSI_Out__DBP_raw__INP_DIS EQU CYREG_PRT15_INP_DIS\r
+SCSI_Out__DBP_raw__INTTYPE EQU CYREG_PICU15_INTTYPE5\r
+SCSI_Out__DBP_raw__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG\r
+SCSI_Out__DBP_raw__LCD_EN EQU CYREG_PRT15_LCD_EN\r
+SCSI_Out__DBP_raw__MASK EQU 0x20\r
+SCSI_Out__DBP_raw__PC EQU CYREG_IO_PC_PRT15_PC5\r
+SCSI_Out__DBP_raw__PORT EQU 15\r
+SCSI_Out__DBP_raw__PRT EQU CYREG_PRT15_PRT\r
+SCSI_Out__DBP_raw__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL\r
+SCSI_Out__DBP_raw__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN\r
+SCSI_Out__DBP_raw__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0\r
+SCSI_Out__DBP_raw__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1\r
+SCSI_Out__DBP_raw__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0\r
+SCSI_Out__DBP_raw__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1\r
+SCSI_Out__DBP_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT\r
+SCSI_Out__DBP_raw__PS EQU CYREG_PRT15_PS\r
+SCSI_Out__DBP_raw__SHIFT EQU 5\r
+SCSI_Out__DBP_raw__SLW EQU CYREG_PRT15_SLW\r
+SCSI_Out__IO_raw__AG EQU CYREG_PRT0_AG\r
+SCSI_Out__IO_raw__AMUX EQU CYREG_PRT0_AMUX\r
+SCSI_Out__IO_raw__BIE EQU CYREG_PRT0_BIE\r
+SCSI_Out__IO_raw__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
+SCSI_Out__IO_raw__BYP EQU CYREG_PRT0_BYP\r
+SCSI_Out__IO_raw__CTL EQU CYREG_PRT0_CTL\r
+SCSI_Out__IO_raw__DM0 EQU CYREG_PRT0_DM0\r
+SCSI_Out__IO_raw__DM1 EQU CYREG_PRT0_DM1\r
+SCSI_Out__IO_raw__DM2 EQU CYREG_PRT0_DM2\r
+SCSI_Out__IO_raw__DR EQU CYREG_PRT0_DR\r
+SCSI_Out__IO_raw__INP_DIS EQU CYREG_PRT0_INP_DIS\r
+SCSI_Out__IO_raw__INTTYPE EQU CYREG_PICU0_INTTYPE2\r
+SCSI_Out__IO_raw__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
+SCSI_Out__IO_raw__LCD_EN EQU CYREG_PRT0_LCD_EN\r
+SCSI_Out__IO_raw__MASK EQU 0x04\r
+SCSI_Out__IO_raw__PC EQU CYREG_PRT0_PC2\r
+SCSI_Out__IO_raw__PORT EQU 0\r
+SCSI_Out__IO_raw__PRT EQU CYREG_PRT0_PRT\r
+SCSI_Out__IO_raw__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
+SCSI_Out__IO_raw__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
+SCSI_Out__IO_raw__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
+SCSI_Out__IO_raw__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
+SCSI_Out__IO_raw__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
+SCSI_Out__IO_raw__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
+SCSI_Out__IO_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
+SCSI_Out__IO_raw__PS EQU CYREG_PRT0_PS\r
+SCSI_Out__IO_raw__SHIFT EQU 2\r
+SCSI_Out__IO_raw__SLW EQU CYREG_PRT0_SLW\r
+SCSI_Out__MSG_raw__AG EQU CYREG_PRT4_AG\r
+SCSI_Out__MSG_raw__AMUX EQU CYREG_PRT4_AMUX\r
+SCSI_Out__MSG_raw__BIE EQU CYREG_PRT4_BIE\r
+SCSI_Out__MSG_raw__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
+SCSI_Out__MSG_raw__BYP EQU CYREG_PRT4_BYP\r
+SCSI_Out__MSG_raw__CTL EQU CYREG_PRT4_CTL\r
+SCSI_Out__MSG_raw__DM0 EQU CYREG_PRT4_DM0\r
+SCSI_Out__MSG_raw__DM1 EQU CYREG_PRT4_DM1\r
+SCSI_Out__MSG_raw__DM2 EQU CYREG_PRT4_DM2\r
+SCSI_Out__MSG_raw__DR EQU CYREG_PRT4_DR\r
+SCSI_Out__MSG_raw__INP_DIS EQU CYREG_PRT4_INP_DIS\r
+SCSI_Out__MSG_raw__INTTYPE EQU CYREG_PICU4_INTTYPE4\r
+SCSI_Out__MSG_raw__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
+SCSI_Out__MSG_raw__LCD_EN EQU CYREG_PRT4_LCD_EN\r
+SCSI_Out__MSG_raw__MASK EQU 0x10\r
+SCSI_Out__MSG_raw__PC EQU CYREG_PRT4_PC4\r
+SCSI_Out__MSG_raw__PORT EQU 4\r
+SCSI_Out__MSG_raw__PRT EQU CYREG_PRT4_PRT\r
+SCSI_Out__MSG_raw__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
+SCSI_Out__MSG_raw__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
+SCSI_Out__MSG_raw__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
+SCSI_Out__MSG_raw__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
+SCSI_Out__MSG_raw__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
+SCSI_Out__MSG_raw__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
+SCSI_Out__MSG_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
+SCSI_Out__MSG_raw__PS EQU CYREG_PRT4_PS\r
+SCSI_Out__MSG_raw__SHIFT EQU 4\r
+SCSI_Out__MSG_raw__SLW EQU CYREG_PRT4_SLW\r
+SCSI_Out__REQ__AG EQU CYREG_PRT0_AG\r
+SCSI_Out__REQ__AMUX EQU CYREG_PRT0_AMUX\r
+SCSI_Out__REQ__BIE EQU CYREG_PRT0_BIE\r
+SCSI_Out__REQ__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
+SCSI_Out__REQ__BYP EQU CYREG_PRT0_BYP\r
+SCSI_Out__REQ__CTL EQU CYREG_PRT0_CTL\r
+SCSI_Out__REQ__DM0 EQU CYREG_PRT0_DM0\r
+SCSI_Out__REQ__DM1 EQU CYREG_PRT0_DM1\r
+SCSI_Out__REQ__DM2 EQU CYREG_PRT0_DM2\r
+SCSI_Out__REQ__DR EQU CYREG_PRT0_DR\r
+SCSI_Out__REQ__INP_DIS EQU CYREG_PRT0_INP_DIS\r
+SCSI_Out__REQ__INTTYPE EQU CYREG_PICU0_INTTYPE3\r
+SCSI_Out__REQ__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
+SCSI_Out__REQ__LCD_EN EQU CYREG_PRT0_LCD_EN\r
+SCSI_Out__REQ__MASK EQU 0x08\r
+SCSI_Out__REQ__PC EQU CYREG_PRT0_PC3\r
+SCSI_Out__REQ__PORT EQU 0\r
+SCSI_Out__REQ__PRT EQU CYREG_PRT0_PRT\r
+SCSI_Out__REQ__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
+SCSI_Out__REQ__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
+SCSI_Out__REQ__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
+SCSI_Out__REQ__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
+SCSI_Out__REQ__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
+SCSI_Out__REQ__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
+SCSI_Out__REQ__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
+SCSI_Out__REQ__PS EQU CYREG_PRT0_PS\r
+SCSI_Out__REQ__SHIFT EQU 3\r
+SCSI_Out__REQ__SLW EQU CYREG_PRT0_SLW\r
+SCSI_Out__RST__AG EQU CYREG_PRT4_AG\r
+SCSI_Out__RST__AMUX EQU CYREG_PRT4_AMUX\r
+SCSI_Out__RST__BIE EQU CYREG_PRT4_BIE\r
+SCSI_Out__RST__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
+SCSI_Out__RST__BYP EQU CYREG_PRT4_BYP\r
+SCSI_Out__RST__CTL EQU CYREG_PRT4_CTL\r
+SCSI_Out__RST__DM0 EQU CYREG_PRT4_DM0\r
+SCSI_Out__RST__DM1 EQU CYREG_PRT4_DM1\r
+SCSI_Out__RST__DM2 EQU CYREG_PRT4_DM2\r
+SCSI_Out__RST__DR EQU CYREG_PRT4_DR\r
+SCSI_Out__RST__INP_DIS EQU CYREG_PRT4_INP_DIS\r
+SCSI_Out__RST__INTTYPE EQU CYREG_PICU4_INTTYPE5\r
+SCSI_Out__RST__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
+SCSI_Out__RST__LCD_EN EQU CYREG_PRT4_LCD_EN\r
+SCSI_Out__RST__MASK EQU 0x20\r
+SCSI_Out__RST__PC EQU CYREG_PRT4_PC5\r
+SCSI_Out__RST__PORT EQU 4\r
+SCSI_Out__RST__PRT EQU CYREG_PRT4_PRT\r
+SCSI_Out__RST__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
+SCSI_Out__RST__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
+SCSI_Out__RST__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
+SCSI_Out__RST__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
+SCSI_Out__RST__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
+SCSI_Out__RST__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
+SCSI_Out__RST__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
+SCSI_Out__RST__PS EQU CYREG_PRT4_PS\r
+SCSI_Out__RST__SHIFT EQU 5\r
+SCSI_Out__RST__SLW EQU CYREG_PRT4_SLW\r
+SCSI_Out__SEL__AG EQU CYREG_PRT0_AG\r
+SCSI_Out__SEL__AMUX EQU CYREG_PRT0_AMUX\r
+SCSI_Out__SEL__BIE EQU CYREG_PRT0_BIE\r
+SCSI_Out__SEL__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
+SCSI_Out__SEL__BYP EQU CYREG_PRT0_BYP\r
+SCSI_Out__SEL__CTL EQU CYREG_PRT0_CTL\r
+SCSI_Out__SEL__DM0 EQU CYREG_PRT0_DM0\r
+SCSI_Out__SEL__DM1 EQU CYREG_PRT0_DM1\r
+SCSI_Out__SEL__DM2 EQU CYREG_PRT0_DM2\r
+SCSI_Out__SEL__DR EQU CYREG_PRT0_DR\r
+SCSI_Out__SEL__INP_DIS EQU CYREG_PRT0_INP_DIS\r
+SCSI_Out__SEL__INTTYPE EQU CYREG_PICU0_INTTYPE7\r
+SCSI_Out__SEL__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
+SCSI_Out__SEL__LCD_EN EQU CYREG_PRT0_LCD_EN\r
+SCSI_Out__SEL__MASK EQU 0x80\r
+SCSI_Out__SEL__PC EQU CYREG_PRT0_PC7\r
+SCSI_Out__SEL__PORT EQU 0\r
+SCSI_Out__SEL__PRT EQU CYREG_PRT0_PRT\r
+SCSI_Out__SEL__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
+SCSI_Out__SEL__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
+SCSI_Out__SEL__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
+SCSI_Out__SEL__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
+SCSI_Out__SEL__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
+SCSI_Out__SEL__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
+SCSI_Out__SEL__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
+SCSI_Out__SEL__PS EQU CYREG_PRT0_PS\r
+SCSI_Out__SEL__SHIFT EQU 7\r
+SCSI_Out__SEL__SLW EQU CYREG_PRT0_SLW\r
+SCSI_Out_Bits_Sync_ctrl_reg__0__MASK EQU 0x01\r
+SCSI_Out_Bits_Sync_ctrl_reg__0__POS EQU 0\r
+SCSI_Out_Bits_Sync_ctrl_reg__1__MASK EQU 0x02\r
+SCSI_Out_Bits_Sync_ctrl_reg__1__POS EQU 1\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB14_15_ACTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB14_15_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB14_15_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB14_15_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB14_15_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB14_15_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB14_15_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB14_15_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB14_15_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__2__MASK EQU 0x04\r
+SCSI_Out_Bits_Sync_ctrl_reg__2__POS EQU 2\r
+SCSI_Out_Bits_Sync_ctrl_reg__3__MASK EQU 0x08\r
+SCSI_Out_Bits_Sync_ctrl_reg__3__POS EQU 3\r
+SCSI_Out_Bits_Sync_ctrl_reg__4__MASK EQU 0x10\r
+SCSI_Out_Bits_Sync_ctrl_reg__4__POS EQU 4\r
+SCSI_Out_Bits_Sync_ctrl_reg__5__MASK EQU 0x20\r
+SCSI_Out_Bits_Sync_ctrl_reg__5__POS EQU 5\r
+SCSI_Out_Bits_Sync_ctrl_reg__6__MASK EQU 0x40\r
+SCSI_Out_Bits_Sync_ctrl_reg__6__POS EQU 6\r
+SCSI_Out_Bits_Sync_ctrl_reg__7__MASK EQU 0x80\r
+SCSI_Out_Bits_Sync_ctrl_reg__7__POS EQU 7\r
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB14_ACTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB14_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB14_ST_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB14_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB14_ST_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__MASK EQU 0xFF\r
+SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB14_MSK_ACTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB14_MSK_ACTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB14_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01\r
+SCSI_Out_Ctl_Sync_ctrl_reg__0__POS EQU 0\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB12_13_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB12_13_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB12_13_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB12_13_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB12_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB12_ST_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB12_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB12_ST_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__MASK EQU 0x01\r
+SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB12_MSK\r
+SCSI_Out_DBx__0__AG EQU CYREG_PRT5_AG\r
+SCSI_Out_DBx__0__AMUX EQU CYREG_PRT5_AMUX\r
+SCSI_Out_DBx__0__BIE EQU CYREG_PRT5_BIE\r
+SCSI_Out_DBx__0__BIT_MASK EQU CYREG_PRT5_BIT_MASK\r
+SCSI_Out_DBx__0__BYP EQU CYREG_PRT5_BYP\r
+SCSI_Out_DBx__0__CTL EQU CYREG_PRT5_CTL\r
+SCSI_Out_DBx__0__DM0 EQU CYREG_PRT5_DM0\r
+SCSI_Out_DBx__0__DM1 EQU CYREG_PRT5_DM1\r
+SCSI_Out_DBx__0__DM2 EQU CYREG_PRT5_DM2\r
+SCSI_Out_DBx__0__DR EQU CYREG_PRT5_DR\r
+SCSI_Out_DBx__0__INP_DIS EQU CYREG_PRT5_INP_DIS\r
+SCSI_Out_DBx__0__INTTYPE EQU CYREG_PICU5_INTTYPE1\r
+SCSI_Out_DBx__0__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG\r
+SCSI_Out_DBx__0__LCD_EN EQU CYREG_PRT5_LCD_EN\r
+SCSI_Out_DBx__0__MASK EQU 0x02\r
+SCSI_Out_DBx__0__PC EQU CYREG_PRT5_PC1\r
+SCSI_Out_DBx__0__PORT EQU 5\r
+SCSI_Out_DBx__0__PRT EQU CYREG_PRT5_PRT\r
+SCSI_Out_DBx__0__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL\r
+SCSI_Out_DBx__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN\r
+SCSI_Out_DBx__0__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0\r
+SCSI_Out_DBx__0__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1\r
+SCSI_Out_DBx__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0\r
+SCSI_Out_DBx__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1\r
+SCSI_Out_DBx__0__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT\r
+SCSI_Out_DBx__0__PS EQU CYREG_PRT5_PS\r
+SCSI_Out_DBx__0__SHIFT EQU 1\r
+SCSI_Out_DBx__0__SLW EQU CYREG_PRT5_SLW\r
+SCSI_Out_DBx__1__AG EQU CYREG_PRT5_AG\r
+SCSI_Out_DBx__1__AMUX EQU CYREG_PRT5_AMUX\r
+SCSI_Out_DBx__1__BIE EQU CYREG_PRT5_BIE\r
+SCSI_Out_DBx__1__BIT_MASK EQU CYREG_PRT5_BIT_MASK\r
+SCSI_Out_DBx__1__BYP EQU CYREG_PRT5_BYP\r
+SCSI_Out_DBx__1__CTL EQU CYREG_PRT5_CTL\r
+SCSI_Out_DBx__1__DM0 EQU CYREG_PRT5_DM0\r
+SCSI_Out_DBx__1__DM1 EQU CYREG_PRT5_DM1\r
+SCSI_Out_DBx__1__DM2 EQU CYREG_PRT5_DM2\r
+SCSI_Out_DBx__1__DR EQU CYREG_PRT5_DR\r
+SCSI_Out_DBx__1__INP_DIS EQU CYREG_PRT5_INP_DIS\r
+SCSI_Out_DBx__1__INTTYPE EQU CYREG_PICU5_INTTYPE0\r
+SCSI_Out_DBx__1__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG\r
+SCSI_Out_DBx__1__LCD_EN EQU CYREG_PRT5_LCD_EN\r
+SCSI_Out_DBx__1__MASK EQU 0x01\r
+SCSI_Out_DBx__1__PC EQU CYREG_PRT5_PC0\r
+SCSI_Out_DBx__1__PORT EQU 5\r
+SCSI_Out_DBx__1__PRT EQU CYREG_PRT5_PRT\r
+SCSI_Out_DBx__1__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL\r
+SCSI_Out_DBx__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN\r
+SCSI_Out_DBx__1__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0\r
+SCSI_Out_DBx__1__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1\r
+SCSI_Out_DBx__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0\r
+SCSI_Out_DBx__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1\r
+SCSI_Out_DBx__1__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT\r
+SCSI_Out_DBx__1__PS EQU CYREG_PRT5_PS\r
+SCSI_Out_DBx__1__SHIFT EQU 0\r
+SCSI_Out_DBx__1__SLW EQU CYREG_PRT5_SLW\r
+SCSI_Out_DBx__2__AG EQU CYREG_PRT6_AG\r
+SCSI_Out_DBx__2__AMUX EQU CYREG_PRT6_AMUX\r
+SCSI_Out_DBx__2__BIE EQU CYREG_PRT6_BIE\r
+SCSI_Out_DBx__2__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
+SCSI_Out_DBx__2__BYP EQU CYREG_PRT6_BYP\r
+SCSI_Out_DBx__2__CTL EQU CYREG_PRT6_CTL\r
+SCSI_Out_DBx__2__DM0 EQU CYREG_PRT6_DM0\r
+SCSI_Out_DBx__2__DM1 EQU CYREG_PRT6_DM1\r
+SCSI_Out_DBx__2__DM2 EQU CYREG_PRT6_DM2\r
+SCSI_Out_DBx__2__DR EQU CYREG_PRT6_DR\r
+SCSI_Out_DBx__2__INP_DIS EQU CYREG_PRT6_INP_DIS\r
+SCSI_Out_DBx__2__INTTYPE EQU CYREG_PICU6_INTTYPE5\r
+SCSI_Out_DBx__2__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
+SCSI_Out_DBx__2__LCD_EN EQU CYREG_PRT6_LCD_EN\r
+SCSI_Out_DBx__2__MASK EQU 0x20\r
+SCSI_Out_DBx__2__PC EQU CYREG_PRT6_PC5\r
+SCSI_Out_DBx__2__PORT EQU 6\r
+SCSI_Out_DBx__2__PRT EQU CYREG_PRT6_PRT\r
+SCSI_Out_DBx__2__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
+SCSI_Out_DBx__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
+SCSI_Out_DBx__2__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
+SCSI_Out_DBx__2__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
+SCSI_Out_DBx__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
+SCSI_Out_DBx__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
+SCSI_Out_DBx__2__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
+SCSI_Out_DBx__2__PS EQU CYREG_PRT6_PS\r
+SCSI_Out_DBx__2__SHIFT EQU 5\r
+SCSI_Out_DBx__2__SLW EQU CYREG_PRT6_SLW\r
+SCSI_Out_DBx__3__AG EQU CYREG_PRT6_AG\r
+SCSI_Out_DBx__3__AMUX EQU CYREG_PRT6_AMUX\r
+SCSI_Out_DBx__3__BIE EQU CYREG_PRT6_BIE\r
+SCSI_Out_DBx__3__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
+SCSI_Out_DBx__3__BYP EQU CYREG_PRT6_BYP\r
+SCSI_Out_DBx__3__CTL EQU CYREG_PRT6_CTL\r
+SCSI_Out_DBx__3__DM0 EQU CYREG_PRT6_DM0\r
+SCSI_Out_DBx__3__DM1 EQU CYREG_PRT6_DM1\r
+SCSI_Out_DBx__3__DM2 EQU CYREG_PRT6_DM2\r
+SCSI_Out_DBx__3__DR EQU CYREG_PRT6_DR\r
+SCSI_Out_DBx__3__INP_DIS EQU CYREG_PRT6_INP_DIS\r
+SCSI_Out_DBx__3__INTTYPE EQU CYREG_PICU6_INTTYPE4\r
+SCSI_Out_DBx__3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
+SCSI_Out_DBx__3__LCD_EN EQU CYREG_PRT6_LCD_EN\r
+SCSI_Out_DBx__3__MASK EQU 0x10\r
+SCSI_Out_DBx__3__PC EQU CYREG_PRT6_PC4\r
+SCSI_Out_DBx__3__PORT EQU 6\r
+SCSI_Out_DBx__3__PRT EQU CYREG_PRT6_PRT\r
+SCSI_Out_DBx__3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
+SCSI_Out_DBx__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
+SCSI_Out_DBx__3__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
+SCSI_Out_DBx__3__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
+SCSI_Out_DBx__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
+SCSI_Out_DBx__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
+SCSI_Out_DBx__3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
+SCSI_Out_DBx__3__PS EQU CYREG_PRT6_PS\r
+SCSI_Out_DBx__3__SHIFT EQU 4\r
+SCSI_Out_DBx__3__SLW EQU CYREG_PRT6_SLW\r
+SCSI_Out_DBx__4__AG EQU CYREG_PRT2_AG\r
+SCSI_Out_DBx__4__AMUX EQU CYREG_PRT2_AMUX\r
+SCSI_Out_DBx__4__BIE EQU CYREG_PRT2_BIE\r
+SCSI_Out_DBx__4__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
+SCSI_Out_DBx__4__BYP EQU CYREG_PRT2_BYP\r
+SCSI_Out_DBx__4__CTL EQU CYREG_PRT2_CTL\r
+SCSI_Out_DBx__4__DM0 EQU CYREG_PRT2_DM0\r
+SCSI_Out_DBx__4__DM1 EQU CYREG_PRT2_DM1\r
+SCSI_Out_DBx__4__DM2 EQU CYREG_PRT2_DM2\r
+SCSI_Out_DBx__4__DR EQU CYREG_PRT2_DR\r
+SCSI_Out_DBx__4__INP_DIS EQU CYREG_PRT2_INP_DIS\r
+SCSI_Out_DBx__4__INTTYPE EQU CYREG_PICU2_INTTYPE7\r
+SCSI_Out_DBx__4__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
+SCSI_Out_DBx__4__LCD_EN EQU CYREG_PRT2_LCD_EN\r
+SCSI_Out_DBx__4__MASK EQU 0x80\r
+SCSI_Out_DBx__4__PC EQU CYREG_PRT2_PC7\r
+SCSI_Out_DBx__4__PORT EQU 2\r
+SCSI_Out_DBx__4__PRT EQU CYREG_PRT2_PRT\r
+SCSI_Out_DBx__4__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
+SCSI_Out_DBx__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
+SCSI_Out_DBx__4__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
+SCSI_Out_DBx__4__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
+SCSI_Out_DBx__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
+SCSI_Out_DBx__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
+SCSI_Out_DBx__4__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
+SCSI_Out_DBx__4__PS EQU CYREG_PRT2_PS\r
+SCSI_Out_DBx__4__SHIFT EQU 7\r
+SCSI_Out_DBx__4__SLW EQU CYREG_PRT2_SLW\r
+SCSI_Out_DBx__5__AG EQU CYREG_PRT2_AG\r
+SCSI_Out_DBx__5__AMUX EQU CYREG_PRT2_AMUX\r
+SCSI_Out_DBx__5__BIE EQU CYREG_PRT2_BIE\r
+SCSI_Out_DBx__5__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
+SCSI_Out_DBx__5__BYP EQU CYREG_PRT2_BYP\r
+SCSI_Out_DBx__5__CTL EQU CYREG_PRT2_CTL\r
+SCSI_Out_DBx__5__DM0 EQU CYREG_PRT2_DM0\r
+SCSI_Out_DBx__5__DM1 EQU CYREG_PRT2_DM1\r
+SCSI_Out_DBx__5__DM2 EQU CYREG_PRT2_DM2\r
+SCSI_Out_DBx__5__DR EQU CYREG_PRT2_DR\r
+SCSI_Out_DBx__5__INP_DIS EQU CYREG_PRT2_INP_DIS\r
+SCSI_Out_DBx__5__INTTYPE EQU CYREG_PICU2_INTTYPE6\r
+SCSI_Out_DBx__5__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
+SCSI_Out_DBx__5__LCD_EN EQU CYREG_PRT2_LCD_EN\r
+SCSI_Out_DBx__5__MASK EQU 0x40\r
+SCSI_Out_DBx__5__PC EQU CYREG_PRT2_PC6\r
+SCSI_Out_DBx__5__PORT EQU 2\r
+SCSI_Out_DBx__5__PRT EQU CYREG_PRT2_PRT\r
+SCSI_Out_DBx__5__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
+SCSI_Out_DBx__5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
+SCSI_Out_DBx__5__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
+SCSI_Out_DBx__5__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
+SCSI_Out_DBx__5__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
+SCSI_Out_DBx__5__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
+SCSI_Out_DBx__5__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
+SCSI_Out_DBx__5__PS EQU CYREG_PRT2_PS\r
+SCSI_Out_DBx__5__SHIFT EQU 6\r
+SCSI_Out_DBx__5__SLW EQU CYREG_PRT2_SLW\r
+SCSI_Out_DBx__6__AG EQU CYREG_PRT2_AG\r
+SCSI_Out_DBx__6__AMUX EQU CYREG_PRT2_AMUX\r
+SCSI_Out_DBx__6__BIE EQU CYREG_PRT2_BIE\r
+SCSI_Out_DBx__6__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
+SCSI_Out_DBx__6__BYP EQU CYREG_PRT2_BYP\r
+SCSI_Out_DBx__6__CTL EQU CYREG_PRT2_CTL\r
+SCSI_Out_DBx__6__DM0 EQU CYREG_PRT2_DM0\r
+SCSI_Out_DBx__6__DM1 EQU CYREG_PRT2_DM1\r
+SCSI_Out_DBx__6__DM2 EQU CYREG_PRT2_DM2\r
+SCSI_Out_DBx__6__DR EQU CYREG_PRT2_DR\r
+SCSI_Out_DBx__6__INP_DIS EQU CYREG_PRT2_INP_DIS\r
+SCSI_Out_DBx__6__INTTYPE EQU CYREG_PICU2_INTTYPE3\r
+SCSI_Out_DBx__6__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
+SCSI_Out_DBx__6__LCD_EN EQU CYREG_PRT2_LCD_EN\r
+SCSI_Out_DBx__6__MASK EQU 0x08\r
+SCSI_Out_DBx__6__PC EQU CYREG_PRT2_PC3\r
+SCSI_Out_DBx__6__PORT EQU 2\r
+SCSI_Out_DBx__6__PRT EQU CYREG_PRT2_PRT\r
+SCSI_Out_DBx__6__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
+SCSI_Out_DBx__6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
+SCSI_Out_DBx__6__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
+SCSI_Out_DBx__6__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
+SCSI_Out_DBx__6__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
+SCSI_Out_DBx__6__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
+SCSI_Out_DBx__6__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
+SCSI_Out_DBx__6__PS EQU CYREG_PRT2_PS\r
+SCSI_Out_DBx__6__SHIFT EQU 3\r
+SCSI_Out_DBx__6__SLW EQU CYREG_PRT2_SLW\r
+SCSI_Out_DBx__7__AG EQU CYREG_PRT2_AG\r
+SCSI_Out_DBx__7__AMUX EQU CYREG_PRT2_AMUX\r
+SCSI_Out_DBx__7__BIE EQU CYREG_PRT2_BIE\r
+SCSI_Out_DBx__7__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
+SCSI_Out_DBx__7__BYP EQU CYREG_PRT2_BYP\r
+SCSI_Out_DBx__7__CTL EQU CYREG_PRT2_CTL\r
+SCSI_Out_DBx__7__DM0 EQU CYREG_PRT2_DM0\r
+SCSI_Out_DBx__7__DM1 EQU CYREG_PRT2_DM1\r
+SCSI_Out_DBx__7__DM2 EQU CYREG_PRT2_DM2\r
+SCSI_Out_DBx__7__DR EQU CYREG_PRT2_DR\r
+SCSI_Out_DBx__7__INP_DIS EQU CYREG_PRT2_INP_DIS\r
+SCSI_Out_DBx__7__INTTYPE EQU CYREG_PICU2_INTTYPE2\r
+SCSI_Out_DBx__7__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
+SCSI_Out_DBx__7__LCD_EN EQU CYREG_PRT2_LCD_EN\r
+SCSI_Out_DBx__7__MASK EQU 0x04\r
+SCSI_Out_DBx__7__PC EQU CYREG_PRT2_PC2\r
+SCSI_Out_DBx__7__PORT EQU 2\r
+SCSI_Out_DBx__7__PRT EQU CYREG_PRT2_PRT\r
+SCSI_Out_DBx__7__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
+SCSI_Out_DBx__7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
+SCSI_Out_DBx__7__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
+SCSI_Out_DBx__7__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
+SCSI_Out_DBx__7__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
+SCSI_Out_DBx__7__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
+SCSI_Out_DBx__7__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
+SCSI_Out_DBx__7__PS EQU CYREG_PRT2_PS\r
+SCSI_Out_DBx__7__SHIFT EQU 2\r
+SCSI_Out_DBx__7__SLW EQU CYREG_PRT2_SLW\r
+SCSI_Out_DBx__DB0__AG EQU CYREG_PRT5_AG\r
+SCSI_Out_DBx__DB0__AMUX EQU CYREG_PRT5_AMUX\r
+SCSI_Out_DBx__DB0__BIE EQU CYREG_PRT5_BIE\r
+SCSI_Out_DBx__DB0__BIT_MASK EQU CYREG_PRT5_BIT_MASK\r
+SCSI_Out_DBx__DB0__BYP EQU CYREG_PRT5_BYP\r
+SCSI_Out_DBx__DB0__CTL EQU CYREG_PRT5_CTL\r
+SCSI_Out_DBx__DB0__DM0 EQU CYREG_PRT5_DM0\r
+SCSI_Out_DBx__DB0__DM1 EQU CYREG_PRT5_DM1\r
+SCSI_Out_DBx__DB0__DM2 EQU CYREG_PRT5_DM2\r
+SCSI_Out_DBx__DB0__DR EQU CYREG_PRT5_DR\r
+SCSI_Out_DBx__DB0__INP_DIS EQU CYREG_PRT5_INP_DIS\r
+SCSI_Out_DBx__DB0__INTTYPE EQU CYREG_PICU5_INTTYPE1\r
+SCSI_Out_DBx__DB0__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG\r
+SCSI_Out_DBx__DB0__LCD_EN EQU CYREG_PRT5_LCD_EN\r
+SCSI_Out_DBx__DB0__MASK EQU 0x02\r
+SCSI_Out_DBx__DB0__PC EQU CYREG_PRT5_PC1\r
+SCSI_Out_DBx__DB0__PORT EQU 5\r
+SCSI_Out_DBx__DB0__PRT EQU CYREG_PRT5_PRT\r
+SCSI_Out_DBx__DB0__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL\r
+SCSI_Out_DBx__DB0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN\r
+SCSI_Out_DBx__DB0__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0\r
+SCSI_Out_DBx__DB0__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1\r
+SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0\r
+SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1\r
+SCSI_Out_DBx__DB0__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT\r
+SCSI_Out_DBx__DB0__PS EQU CYREG_PRT5_PS\r
+SCSI_Out_DBx__DB0__SHIFT EQU 1\r
+SCSI_Out_DBx__DB0__SLW EQU CYREG_PRT5_SLW\r
+SCSI_Out_DBx__DB1__AG EQU CYREG_PRT5_AG\r
+SCSI_Out_DBx__DB1__AMUX EQU CYREG_PRT5_AMUX\r
+SCSI_Out_DBx__DB1__BIE EQU CYREG_PRT5_BIE\r
+SCSI_Out_DBx__DB1__BIT_MASK EQU CYREG_PRT5_BIT_MASK\r
+SCSI_Out_DBx__DB1__BYP EQU CYREG_PRT5_BYP\r
+SCSI_Out_DBx__DB1__CTL EQU CYREG_PRT5_CTL\r
+SCSI_Out_DBx__DB1__DM0 EQU CYREG_PRT5_DM0\r
+SCSI_Out_DBx__DB1__DM1 EQU CYREG_PRT5_DM1\r
+SCSI_Out_DBx__DB1__DM2 EQU CYREG_PRT5_DM2\r
+SCSI_Out_DBx__DB1__DR EQU CYREG_PRT5_DR\r
+SCSI_Out_DBx__DB1__INP_DIS EQU CYREG_PRT5_INP_DIS\r
+SCSI_Out_DBx__DB1__INTTYPE EQU CYREG_PICU5_INTTYPE0\r
+SCSI_Out_DBx__DB1__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG\r
+SCSI_Out_DBx__DB1__LCD_EN EQU CYREG_PRT5_LCD_EN\r
+SCSI_Out_DBx__DB1__MASK EQU 0x01\r
+SCSI_Out_DBx__DB1__PC EQU CYREG_PRT5_PC0\r
+SCSI_Out_DBx__DB1__PORT EQU 5\r
+SCSI_Out_DBx__DB1__PRT EQU CYREG_PRT5_PRT\r
+SCSI_Out_DBx__DB1__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL\r
+SCSI_Out_DBx__DB1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN\r
+SCSI_Out_DBx__DB1__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0\r
+SCSI_Out_DBx__DB1__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1\r
+SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0\r
+SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1\r
+SCSI_Out_DBx__DB1__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT\r
+SCSI_Out_DBx__DB1__PS EQU CYREG_PRT5_PS\r
+SCSI_Out_DBx__DB1__SHIFT EQU 0\r
+SCSI_Out_DBx__DB1__SLW EQU CYREG_PRT5_SLW\r
+SCSI_Out_DBx__DB2__AG EQU CYREG_PRT6_AG\r
+SCSI_Out_DBx__DB2__AMUX EQU CYREG_PRT6_AMUX\r
+SCSI_Out_DBx__DB2__BIE EQU CYREG_PRT6_BIE\r
+SCSI_Out_DBx__DB2__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
+SCSI_Out_DBx__DB2__BYP EQU CYREG_PRT6_BYP\r
+SCSI_Out_DBx__DB2__CTL EQU CYREG_PRT6_CTL\r
+SCSI_Out_DBx__DB2__DM0 EQU CYREG_PRT6_DM0\r
+SCSI_Out_DBx__DB2__DM1 EQU CYREG_PRT6_DM1\r
+SCSI_Out_DBx__DB2__DM2 EQU CYREG_PRT6_DM2\r
+SCSI_Out_DBx__DB2__DR EQU CYREG_PRT6_DR\r
+SCSI_Out_DBx__DB2__INP_DIS EQU CYREG_PRT6_INP_DIS\r
+SCSI_Out_DBx__DB2__INTTYPE EQU CYREG_PICU6_INTTYPE5\r
+SCSI_Out_DBx__DB2__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
+SCSI_Out_DBx__DB2__LCD_EN EQU CYREG_PRT6_LCD_EN\r
+SCSI_Out_DBx__DB2__MASK EQU 0x20\r
+SCSI_Out_DBx__DB2__PC EQU CYREG_PRT6_PC5\r
+SCSI_Out_DBx__DB2__PORT EQU 6\r
+SCSI_Out_DBx__DB2__PRT EQU CYREG_PRT6_PRT\r
+SCSI_Out_DBx__DB2__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
+SCSI_Out_DBx__DB2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
+SCSI_Out_DBx__DB2__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
+SCSI_Out_DBx__DB2__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
+SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
+SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
+SCSI_Out_DBx__DB2__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
+SCSI_Out_DBx__DB2__PS EQU CYREG_PRT6_PS\r
+SCSI_Out_DBx__DB2__SHIFT EQU 5\r
+SCSI_Out_DBx__DB2__SLW EQU CYREG_PRT6_SLW\r
+SCSI_Out_DBx__DB3__AG EQU CYREG_PRT6_AG\r
+SCSI_Out_DBx__DB3__AMUX EQU CYREG_PRT6_AMUX\r
+SCSI_Out_DBx__DB3__BIE EQU CYREG_PRT6_BIE\r
+SCSI_Out_DBx__DB3__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
+SCSI_Out_DBx__DB3__BYP EQU CYREG_PRT6_BYP\r
+SCSI_Out_DBx__DB3__CTL EQU CYREG_PRT6_CTL\r
+SCSI_Out_DBx__DB3__DM0 EQU CYREG_PRT6_DM0\r
+SCSI_Out_DBx__DB3__DM1 EQU CYREG_PRT6_DM1\r
+SCSI_Out_DBx__DB3__DM2 EQU CYREG_PRT6_DM2\r
+SCSI_Out_DBx__DB3__DR EQU CYREG_PRT6_DR\r
+SCSI_Out_DBx__DB3__INP_DIS EQU CYREG_PRT6_INP_DIS\r
+SCSI_Out_DBx__DB3__INTTYPE EQU CYREG_PICU6_INTTYPE4\r
+SCSI_Out_DBx__DB3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
+SCSI_Out_DBx__DB3__LCD_EN EQU CYREG_PRT6_LCD_EN\r
+SCSI_Out_DBx__DB3__MASK EQU 0x10\r
+SCSI_Out_DBx__DB3__PC EQU CYREG_PRT6_PC4\r
+SCSI_Out_DBx__DB3__PORT EQU 6\r
+SCSI_Out_DBx__DB3__PRT EQU CYREG_PRT6_PRT\r
+SCSI_Out_DBx__DB3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
+SCSI_Out_DBx__DB3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
+SCSI_Out_DBx__DB3__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
+SCSI_Out_DBx__DB3__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
+SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
+SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
+SCSI_Out_DBx__DB3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
+SCSI_Out_DBx__DB3__PS EQU CYREG_PRT6_PS\r
+SCSI_Out_DBx__DB3__SHIFT EQU 4\r
+SCSI_Out_DBx__DB3__SLW EQU CYREG_PRT6_SLW\r
+SCSI_Out_DBx__DB4__AG EQU CYREG_PRT2_AG\r
+SCSI_Out_DBx__DB4__AMUX EQU CYREG_PRT2_AMUX\r
+SCSI_Out_DBx__DB4__BIE EQU CYREG_PRT2_BIE\r
+SCSI_Out_DBx__DB4__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
+SCSI_Out_DBx__DB4__BYP EQU CYREG_PRT2_BYP\r
+SCSI_Out_DBx__DB4__CTL EQU CYREG_PRT2_CTL\r
+SCSI_Out_DBx__DB4__DM0 EQU CYREG_PRT2_DM0\r
+SCSI_Out_DBx__DB4__DM1 EQU CYREG_PRT2_DM1\r
+SCSI_Out_DBx__DB4__DM2 EQU CYREG_PRT2_DM2\r
+SCSI_Out_DBx__DB4__DR EQU CYREG_PRT2_DR\r
+SCSI_Out_DBx__DB4__INP_DIS EQU CYREG_PRT2_INP_DIS\r
+SCSI_Out_DBx__DB4__INTTYPE EQU CYREG_PICU2_INTTYPE7\r
+SCSI_Out_DBx__DB4__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
+SCSI_Out_DBx__DB4__LCD_EN EQU CYREG_PRT2_LCD_EN\r
+SCSI_Out_DBx__DB4__MASK EQU 0x80\r
+SCSI_Out_DBx__DB4__PC EQU CYREG_PRT2_PC7\r
+SCSI_Out_DBx__DB4__PORT EQU 2\r
+SCSI_Out_DBx__DB4__PRT EQU CYREG_PRT2_PRT\r
+SCSI_Out_DBx__DB4__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
+SCSI_Out_DBx__DB4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
+SCSI_Out_DBx__DB4__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
+SCSI_Out_DBx__DB4__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
+SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
+SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
+SCSI_Out_DBx__DB4__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
+SCSI_Out_DBx__DB4__PS EQU CYREG_PRT2_PS\r
+SCSI_Out_DBx__DB4__SHIFT EQU 7\r
+SCSI_Out_DBx__DB4__SLW EQU CYREG_PRT2_SLW\r
+SCSI_Out_DBx__DB5__AG EQU CYREG_PRT2_AG\r
+SCSI_Out_DBx__DB5__AMUX EQU CYREG_PRT2_AMUX\r
+SCSI_Out_DBx__DB5__BIE EQU CYREG_PRT2_BIE\r
+SCSI_Out_DBx__DB5__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
+SCSI_Out_DBx__DB5__BYP EQU CYREG_PRT2_BYP\r
+SCSI_Out_DBx__DB5__CTL EQU CYREG_PRT2_CTL\r
+SCSI_Out_DBx__DB5__DM0 EQU CYREG_PRT2_DM0\r
+SCSI_Out_DBx__DB5__DM1 EQU CYREG_PRT2_DM1\r
+SCSI_Out_DBx__DB5__DM2 EQU CYREG_PRT2_DM2\r
+SCSI_Out_DBx__DB5__DR EQU CYREG_PRT2_DR\r
+SCSI_Out_DBx__DB5__INP_DIS EQU CYREG_PRT2_INP_DIS\r
+SCSI_Out_DBx__DB5__INTTYPE EQU CYREG_PICU2_INTTYPE6\r
+SCSI_Out_DBx__DB5__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
+SCSI_Out_DBx__DB5__LCD_EN EQU CYREG_PRT2_LCD_EN\r
+SCSI_Out_DBx__DB5__MASK EQU 0x40\r
+SCSI_Out_DBx__DB5__PC EQU CYREG_PRT2_PC6\r
+SCSI_Out_DBx__DB5__PORT EQU 2\r
+SCSI_Out_DBx__DB5__PRT EQU CYREG_PRT2_PRT\r
+SCSI_Out_DBx__DB5__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
+SCSI_Out_DBx__DB5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
+SCSI_Out_DBx__DB5__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
+SCSI_Out_DBx__DB5__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
+SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
+SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
+SCSI_Out_DBx__DB5__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
+SCSI_Out_DBx__DB5__PS EQU CYREG_PRT2_PS\r
+SCSI_Out_DBx__DB5__SHIFT EQU 6\r
+SCSI_Out_DBx__DB5__SLW EQU CYREG_PRT2_SLW\r
+SCSI_Out_DBx__DB6__AG EQU CYREG_PRT2_AG\r
+SCSI_Out_DBx__DB6__AMUX EQU CYREG_PRT2_AMUX\r
+SCSI_Out_DBx__DB6__BIE EQU CYREG_PRT2_BIE\r
+SCSI_Out_DBx__DB6__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
+SCSI_Out_DBx__DB6__BYP EQU CYREG_PRT2_BYP\r
+SCSI_Out_DBx__DB6__CTL EQU CYREG_PRT2_CTL\r
+SCSI_Out_DBx__DB6__DM0 EQU CYREG_PRT2_DM0\r
+SCSI_Out_DBx__DB6__DM1 EQU CYREG_PRT2_DM1\r
+SCSI_Out_DBx__DB6__DM2 EQU CYREG_PRT2_DM2\r
+SCSI_Out_DBx__DB6__DR EQU CYREG_PRT2_DR\r
+SCSI_Out_DBx__DB6__INP_DIS EQU CYREG_PRT2_INP_DIS\r
+SCSI_Out_DBx__DB6__INTTYPE EQU CYREG_PICU2_INTTYPE3\r
+SCSI_Out_DBx__DB6__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
+SCSI_Out_DBx__DB6__LCD_EN EQU CYREG_PRT2_LCD_EN\r
+SCSI_Out_DBx__DB6__MASK EQU 0x08\r
+SCSI_Out_DBx__DB6__PC EQU CYREG_PRT2_PC3\r
+SCSI_Out_DBx__DB6__PORT EQU 2\r
+SCSI_Out_DBx__DB6__PRT EQU CYREG_PRT2_PRT\r
+SCSI_Out_DBx__DB6__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
+SCSI_Out_DBx__DB6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
+SCSI_Out_DBx__DB6__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
+SCSI_Out_DBx__DB6__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
+SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
+SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
+SCSI_Out_DBx__DB6__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
+SCSI_Out_DBx__DB6__PS EQU CYREG_PRT2_PS\r
+SCSI_Out_DBx__DB6__SHIFT EQU 3\r
+SCSI_Out_DBx__DB6__SLW EQU CYREG_PRT2_SLW\r
+SCSI_Out_DBx__DB7__AG EQU CYREG_PRT2_AG\r
+SCSI_Out_DBx__DB7__AMUX EQU CYREG_PRT2_AMUX\r
+SCSI_Out_DBx__DB7__BIE EQU CYREG_PRT2_BIE\r
+SCSI_Out_DBx__DB7__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
+SCSI_Out_DBx__DB7__BYP EQU CYREG_PRT2_BYP\r
+SCSI_Out_DBx__DB7__CTL EQU CYREG_PRT2_CTL\r
+SCSI_Out_DBx__DB7__DM0 EQU CYREG_PRT2_DM0\r
+SCSI_Out_DBx__DB7__DM1 EQU CYREG_PRT2_DM1\r
+SCSI_Out_DBx__DB7__DM2 EQU CYREG_PRT2_DM2\r
+SCSI_Out_DBx__DB7__DR EQU CYREG_PRT2_DR\r
+SCSI_Out_DBx__DB7__INP_DIS EQU CYREG_PRT2_INP_DIS\r
+SCSI_Out_DBx__DB7__INTTYPE EQU CYREG_PICU2_INTTYPE2\r
+SCSI_Out_DBx__DB7__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
+SCSI_Out_DBx__DB7__LCD_EN EQU CYREG_PRT2_LCD_EN\r
+SCSI_Out_DBx__DB7__MASK EQU 0x04\r
+SCSI_Out_DBx__DB7__PC EQU CYREG_PRT2_PC2\r
+SCSI_Out_DBx__DB7__PORT EQU 2\r
+SCSI_Out_DBx__DB7__PRT EQU CYREG_PRT2_PRT\r
+SCSI_Out_DBx__DB7__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
+SCSI_Out_DBx__DB7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
+SCSI_Out_DBx__DB7__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
+SCSI_Out_DBx__DB7__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
+SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
+SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
+SCSI_Out_DBx__DB7__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
+SCSI_Out_DBx__DB7__PS EQU CYREG_PRT2_PS\r
+SCSI_Out_DBx__DB7__SHIFT EQU 2\r
+SCSI_Out_DBx__DB7__SLW EQU CYREG_PRT2_SLW\r
+\r
+/* SCSI_Parity_Error */\r
+SCSI_Parity_Error_sts_sts_reg__0__MASK EQU 0x01\r
+SCSI_Parity_Error_sts_sts_reg__0__POS EQU 0\r
+SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL\r
+SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB05_06_ST\r
+SCSI_Parity_Error_sts_sts_reg__MASK EQU 0x01\r
+SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB05_MSK\r
+SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL\r
+SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB05_ST\r
+\r
+/* SCSI_RST_ISR */\r
+SCSI_RST_ISR__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
+SCSI_RST_ISR__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
+SCSI_RST_ISR__INTC_MASK EQU 0x02\r
+SCSI_RST_ISR__INTC_NUMBER EQU 1\r
+SCSI_RST_ISR__INTC_PRIOR_NUM EQU 7\r
+SCSI_RST_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_1\r
+SCSI_RST_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
+SCSI_RST_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
+\r
+/* SCSI_RX_DMA */\r
+SCSI_RX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0\r
+SCSI_RX_DMA__DRQ_NUMBER EQU 0\r
+SCSI_RX_DMA__NUMBEROF_TDS EQU 0\r
+SCSI_RX_DMA__PRIORITY EQU 2\r
+SCSI_RX_DMA__TERMIN_EN EQU 0\r
+SCSI_RX_DMA__TERMIN_SEL EQU 0\r
+SCSI_RX_DMA__TERMOUT0_EN EQU 1\r
+SCSI_RX_DMA__TERMOUT0_SEL EQU 0\r
+SCSI_RX_DMA__TERMOUT1_EN EQU 0\r
+SCSI_RX_DMA__TERMOUT1_SEL EQU 0\r
+SCSI_RX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
+SCSI_RX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
+SCSI_RX_DMA_COMPLETE__INTC_MASK EQU 0x04\r
+SCSI_RX_DMA_COMPLETE__INTC_NUMBER EQU 2\r
+SCSI_RX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7\r
+SCSI_RX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_2\r
+SCSI_RX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
+SCSI_RX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
+\r
+/* SCSI_SEL_ISR */\r
+SCSI_SEL_ISR__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
+SCSI_SEL_ISR__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
+SCSI_SEL_ISR__INTC_MASK EQU 0x08\r
+SCSI_SEL_ISR__INTC_NUMBER EQU 3\r
+SCSI_SEL_ISR__INTC_PRIOR_NUM EQU 7\r
+SCSI_SEL_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_3\r
+SCSI_SEL_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
+SCSI_SEL_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
+\r
+/* SCSI_TX_DMA */\r
+SCSI_TX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0\r
+SCSI_TX_DMA__DRQ_NUMBER EQU 1\r
+SCSI_TX_DMA__NUMBEROF_TDS EQU 0\r
+SCSI_TX_DMA__PRIORITY EQU 2\r
+SCSI_TX_DMA__TERMIN_EN EQU 0\r
+SCSI_TX_DMA__TERMIN_SEL EQU 0\r
+SCSI_TX_DMA__TERMOUT0_EN EQU 1\r
+SCSI_TX_DMA__TERMOUT0_SEL EQU 1\r
+SCSI_TX_DMA__TERMOUT1_EN EQU 0\r
+SCSI_TX_DMA__TERMOUT1_SEL EQU 0\r
+SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
+SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
+SCSI_TX_DMA_COMPLETE__INTC_MASK EQU 0x10\r
+SCSI_TX_DMA_COMPLETE__INTC_NUMBER EQU 4\r
+SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7\r
+SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_4\r
+SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
+SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
+\r
+/* SDCard_BSPIM */\r
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB05_06_ACTL\r
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB05_06_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB05_06_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB05_06_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB05_06_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB05_06_MSK\r
+SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB05_06_MSK\r
+SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB05_06_MSK\r
+SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB05_06_MSK\r
+SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB05_ACTL\r
+SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB05_CTL\r
+SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB05_ST_CTL\r
+SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB05_CTL\r
+SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB05_ST_CTL\r
+SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL\r
+SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL\r
+SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB05_MSK\r
+SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB05_06_ACTL\r
+SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB05_06_ST\r
+SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB05_MSK\r
+SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL\r
+SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB05_ACTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB05_ST_CTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB05_ST_CTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB05_ST\r
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL\r
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST\r
+SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10\r
+SDCard_BSPIM_RxStsReg__4__POS EQU 4\r
+SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20\r
+SDCard_BSPIM_RxStsReg__5__POS EQU 5\r
+SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40\r
+SDCard_BSPIM_RxStsReg__6__POS EQU 6\r
+SDCard_BSPIM_RxStsReg__MASK EQU 0x70\r
+SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB07_MSK\r
+SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL\r
+SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB07_ST\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB04_05_A0\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB04_05_A1\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B1_UDB04_05_D0\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B1_UDB04_05_D1\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B1_UDB04_05_F0\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B1_UDB04_05_F1\r
+SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B1_UDB04_A0_A1\r
+SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B1_UDB04_A0\r
+SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B1_UDB04_A1\r
+SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B1_UDB04_D0_D1\r
+SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B1_UDB04_D0\r
+SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B1_UDB04_D1\r
+SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL\r
+SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B1_UDB04_F0_F1\r
+SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B1_UDB04_F0\r
+SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B1_UDB04_F1\r
+SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01\r
+SDCard_BSPIM_TxStsReg__0__POS EQU 0\r
+SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02\r
+SDCard_BSPIM_TxStsReg__1__POS EQU 1\r
+SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL\r
+SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB06_07_ST\r
+SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04\r
+SDCard_BSPIM_TxStsReg__2__POS EQU 2\r
+SDCard_BSPIM_TxStsReg__3__MASK EQU 0x08\r
+SDCard_BSPIM_TxStsReg__3__POS EQU 3\r
+SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10\r
+SDCard_BSPIM_TxStsReg__4__POS EQU 4\r
+SDCard_BSPIM_TxStsReg__MASK EQU 0x1F\r
+SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB06_MSK\r
+SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL\r
+SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB06_ST\r
+\r
+/* SD_CD */\r
+SD_CD__0__INTTYPE EQU CYREG_PICU3_INTTYPE5\r
+SD_CD__0__MASK EQU 0x20\r
+SD_CD__0__PC EQU CYREG_PRT3_PC5\r
+SD_CD__0__PORT EQU 3\r
+SD_CD__0__SHIFT EQU 5\r
+SD_CD__AG EQU CYREG_PRT3_AG\r
+SD_CD__AMUX EQU CYREG_PRT3_AMUX\r
+SD_CD__BIE EQU CYREG_PRT3_BIE\r
+SD_CD__BIT_MASK EQU CYREG_PRT3_BIT_MASK\r
+SD_CD__BYP EQU CYREG_PRT3_BYP\r
+SD_CD__CTL EQU CYREG_PRT3_CTL\r
+SD_CD__DM0 EQU CYREG_PRT3_DM0\r
+SD_CD__DM1 EQU CYREG_PRT3_DM1\r
+SD_CD__DM2 EQU CYREG_PRT3_DM2\r
+SD_CD__DR EQU CYREG_PRT3_DR\r
+SD_CD__INP_DIS EQU CYREG_PRT3_INP_DIS\r
+SD_CD__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE\r
+SD_CD__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG\r
+SD_CD__LCD_EN EQU CYREG_PRT3_LCD_EN\r
+SD_CD__MASK EQU 0x20\r
+SD_CD__PORT EQU 3\r
+SD_CD__PRT EQU CYREG_PRT3_PRT\r
+SD_CD__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL\r
+SD_CD__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN\r
+SD_CD__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0\r
+SD_CD__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1\r
+SD_CD__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0\r
+SD_CD__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1\r
+SD_CD__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT\r
+SD_CD__PS EQU CYREG_PRT3_PS\r
+SD_CD__SHIFT EQU 5\r
+SD_CD__SLW EQU CYREG_PRT3_SLW\r
+\r
+/* SD_CS */\r
+SD_CS__0__INTTYPE EQU CYREG_PICU3_INTTYPE4\r
+SD_CS__0__MASK EQU 0x10\r
+SD_CS__0__PC EQU CYREG_PRT3_PC4\r
+SD_CS__0__PORT EQU 3\r
+SD_CS__0__SHIFT EQU 4\r
+SD_CS__AG EQU CYREG_PRT3_AG\r
+SD_CS__AMUX EQU CYREG_PRT3_AMUX\r
+SD_CS__BIE EQU CYREG_PRT3_BIE\r
+SD_CS__BIT_MASK EQU CYREG_PRT3_BIT_MASK\r
+SD_CS__BYP EQU CYREG_PRT3_BYP\r
+SD_CS__CTL EQU CYREG_PRT3_CTL\r
+SD_CS__DM0 EQU CYREG_PRT3_DM0\r
+SD_CS__DM1 EQU CYREG_PRT3_DM1\r
+SD_CS__DM2 EQU CYREG_PRT3_DM2\r
+SD_CS__DR EQU CYREG_PRT3_DR\r
+SD_CS__INP_DIS EQU CYREG_PRT3_INP_DIS\r
+SD_CS__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE\r
+SD_CS__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG\r
+SD_CS__LCD_EN EQU CYREG_PRT3_LCD_EN\r
+SD_CS__MASK EQU 0x10\r
+SD_CS__PORT EQU 3\r
+SD_CS__PRT EQU CYREG_PRT3_PRT\r
+SD_CS__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL\r
+SD_CS__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN\r
+SD_CS__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0\r
+SD_CS__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1\r
+SD_CS__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0\r
+SD_CS__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1\r
+SD_CS__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT\r
+SD_CS__PS EQU CYREG_PRT3_PS\r
+SD_CS__SHIFT EQU 4\r
+SD_CS__SLW EQU CYREG_PRT3_SLW\r
+\r
+/* SD_Data_Clk */\r
+SD_Data_Clk__CFG0 EQU CYREG_CLKDIST_DCFG0_CFG0\r
+SD_Data_Clk__CFG1 EQU CYREG_CLKDIST_DCFG0_CFG1\r
+SD_Data_Clk__CFG2 EQU CYREG_CLKDIST_DCFG0_CFG2\r
+SD_Data_Clk__CFG2_SRC_SEL_MASK EQU 0x07\r
+SD_Data_Clk__INDEX EQU 0x00\r
+SD_Data_Clk__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2\r
+SD_Data_Clk__PM_ACT_MSK EQU 0x01\r
+SD_Data_Clk__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2\r
+SD_Data_Clk__PM_STBY_MSK EQU 0x01\r
+\r
+/* SD_MISO */\r
+SD_MISO__0__INTTYPE EQU CYREG_PICU3_INTTYPE1\r
+SD_MISO__0__MASK EQU 0x02\r
+SD_MISO__0__PC EQU CYREG_PRT3_PC1\r
+SD_MISO__0__PORT EQU 3\r
+SD_MISO__0__SHIFT EQU 1\r
+SD_MISO__AG EQU CYREG_PRT3_AG\r
+SD_MISO__AMUX EQU CYREG_PRT3_AMUX\r
+SD_MISO__BIE EQU CYREG_PRT3_BIE\r
+SD_MISO__BIT_MASK EQU CYREG_PRT3_BIT_MASK\r
+SD_MISO__BYP EQU CYREG_PRT3_BYP\r
+SD_MISO__CTL EQU CYREG_PRT3_CTL\r
+SD_MISO__DM0 EQU CYREG_PRT3_DM0\r
+SD_MISO__DM1 EQU CYREG_PRT3_DM1\r
+SD_MISO__DM2 EQU CYREG_PRT3_DM2\r
+SD_MISO__DR EQU CYREG_PRT3_DR\r
+SD_MISO__INP_DIS EQU CYREG_PRT3_INP_DIS\r
+SD_MISO__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE\r
+SD_MISO__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG\r
+SD_MISO__LCD_EN EQU CYREG_PRT3_LCD_EN\r
+SD_MISO__MASK EQU 0x02\r
+SD_MISO__PORT EQU 3\r
+SD_MISO__PRT EQU CYREG_PRT3_PRT\r
+SD_MISO__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL\r
+SD_MISO__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN\r
+SD_MISO__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0\r
+SD_MISO__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1\r
+SD_MISO__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0\r
+SD_MISO__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1\r
+SD_MISO__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT\r
+SD_MISO__PS EQU CYREG_PRT3_PS\r
+SD_MISO__SHIFT EQU 1\r
+SD_MISO__SLW EQU CYREG_PRT3_SLW\r
+\r
+/* SD_MOSI */\r
+SD_MOSI__0__INTTYPE EQU CYREG_PICU3_INTTYPE3\r
+SD_MOSI__0__MASK EQU 0x08\r
+SD_MOSI__0__PC EQU CYREG_PRT3_PC3\r
+SD_MOSI__0__PORT EQU 3\r
+SD_MOSI__0__SHIFT EQU 3\r
+SD_MOSI__AG EQU CYREG_PRT3_AG\r
+SD_MOSI__AMUX EQU CYREG_PRT3_AMUX\r
+SD_MOSI__BIE EQU CYREG_PRT3_BIE\r
+SD_MOSI__BIT_MASK EQU CYREG_PRT3_BIT_MASK\r
+SD_MOSI__BYP EQU CYREG_PRT3_BYP\r
+SD_MOSI__CTL EQU CYREG_PRT3_CTL\r
+SD_MOSI__DM0 EQU CYREG_PRT3_DM0\r
+SD_MOSI__DM1 EQU CYREG_PRT3_DM1\r
+SD_MOSI__DM2 EQU CYREG_PRT3_DM2\r
+SD_MOSI__DR EQU CYREG_PRT3_DR\r
+SD_MOSI__INP_DIS EQU CYREG_PRT3_INP_DIS\r
+SD_MOSI__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE\r
+SD_MOSI__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG\r
+SD_MOSI__LCD_EN EQU CYREG_PRT3_LCD_EN\r
+SD_MOSI__MASK EQU 0x08\r
+SD_MOSI__PORT EQU 3\r
+SD_MOSI__PRT EQU CYREG_PRT3_PRT\r
+SD_MOSI__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL\r
+SD_MOSI__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN\r
+SD_MOSI__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0\r
+SD_MOSI__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1\r
+SD_MOSI__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0\r
+SD_MOSI__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1\r
+SD_MOSI__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT\r
+SD_MOSI__PS EQU CYREG_PRT3_PS\r
+SD_MOSI__SHIFT EQU 3\r
+SD_MOSI__SLW EQU CYREG_PRT3_SLW\r
+\r
+/* SD_RX_DMA */\r
+SD_RX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0\r
+SD_RX_DMA__DRQ_NUMBER EQU 2\r
+SD_RX_DMA__NUMBEROF_TDS EQU 0\r
+SD_RX_DMA__PRIORITY EQU 0\r
+SD_RX_DMA__TERMIN_EN EQU 0\r
+SD_RX_DMA__TERMIN_SEL EQU 0\r
+SD_RX_DMA__TERMOUT0_EN EQU 1\r
+SD_RX_DMA__TERMOUT0_SEL EQU 2\r
+SD_RX_DMA__TERMOUT1_EN EQU 0\r
+SD_RX_DMA__TERMOUT1_SEL EQU 0\r
+SD_RX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
+SD_RX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
+SD_RX_DMA_COMPLETE__INTC_MASK EQU 0x20\r
+SD_RX_DMA_COMPLETE__INTC_NUMBER EQU 5\r
+SD_RX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7\r
+SD_RX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_5\r
+SD_RX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
+SD_RX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
+\r
+/* SD_SCK */\r
+SD_SCK__0__INTTYPE EQU CYREG_PICU3_INTTYPE2\r
+SD_SCK__0__MASK EQU 0x04\r
+SD_SCK__0__PC EQU CYREG_PRT3_PC2\r
+SD_SCK__0__PORT EQU 3\r
+SD_SCK__0__SHIFT EQU 2\r
+SD_SCK__AG EQU CYREG_PRT3_AG\r
+SD_SCK__AMUX EQU CYREG_PRT3_AMUX\r
+SD_SCK__BIE EQU CYREG_PRT3_BIE\r
+SD_SCK__BIT_MASK EQU CYREG_PRT3_BIT_MASK\r
+SD_SCK__BYP EQU CYREG_PRT3_BYP\r
+SD_SCK__CTL EQU CYREG_PRT3_CTL\r
+SD_SCK__DM0 EQU CYREG_PRT3_DM0\r
+SD_SCK__DM1 EQU CYREG_PRT3_DM1\r
+SD_SCK__DM2 EQU CYREG_PRT3_DM2\r
+SD_SCK__DR EQU CYREG_PRT3_DR\r
+SD_SCK__INP_DIS EQU CYREG_PRT3_INP_DIS\r
+SD_SCK__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE\r
+SD_SCK__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG\r
+SD_SCK__LCD_EN EQU CYREG_PRT3_LCD_EN\r
+SD_SCK__MASK EQU 0x04\r
+SD_SCK__PORT EQU 3\r
+SD_SCK__PRT EQU CYREG_PRT3_PRT\r
+SD_SCK__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL\r
+SD_SCK__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN\r
+SD_SCK__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0\r
+SD_SCK__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1\r
+SD_SCK__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0\r
+SD_SCK__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1\r
+SD_SCK__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT\r
+SD_SCK__PS EQU CYREG_PRT3_PS\r
+SD_SCK__SHIFT EQU 2\r
+SD_SCK__SLW EQU CYREG_PRT3_SLW\r
+\r
+/* SD_TX_DMA */\r
+SD_TX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0\r
+SD_TX_DMA__DRQ_NUMBER EQU 3\r
+SD_TX_DMA__NUMBEROF_TDS EQU 0\r
+SD_TX_DMA__PRIORITY EQU 1\r
+SD_TX_DMA__TERMIN_EN EQU 0\r
+SD_TX_DMA__TERMIN_SEL EQU 0\r
+SD_TX_DMA__TERMOUT0_EN EQU 1\r
+SD_TX_DMA__TERMOUT0_SEL EQU 3\r
+SD_TX_DMA__TERMOUT1_EN EQU 0\r
+SD_TX_DMA__TERMOUT1_SEL EQU 0\r
+SD_TX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
+SD_TX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
+SD_TX_DMA_COMPLETE__INTC_MASK EQU 0x40\r
+SD_TX_DMA_COMPLETE__INTC_NUMBER EQU 6\r
+SD_TX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7\r
+SD_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_6\r
+SD_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
+SD_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
+\r
+/* USBFS */\r
+USBFS_arb_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
+USBFS_arb_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
+USBFS_arb_int__INTC_MASK EQU 0x400000\r
+USBFS_arb_int__INTC_NUMBER EQU 22\r
+USBFS_arb_int__INTC_PRIOR_NUM EQU 6\r
+USBFS_arb_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_22\r
+USBFS_arb_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
+USBFS_arb_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
+USBFS_bus_reset__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
+USBFS_bus_reset__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
+USBFS_bus_reset__INTC_MASK EQU 0x800000\r
+USBFS_bus_reset__INTC_NUMBER EQU 23\r
+USBFS_bus_reset__INTC_PRIOR_NUM EQU 7\r
+USBFS_bus_reset__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_23\r
+USBFS_bus_reset__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
+USBFS_bus_reset__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
+USBFS_Dm__0__INTTYPE EQU CYREG_PICU15_INTTYPE7\r
+USBFS_Dm__0__MASK EQU 0x80\r
+USBFS_Dm__0__PC EQU CYREG_IO_PC_PRT15_7_6_PC1\r
+USBFS_Dm__0__PORT EQU 15\r
+USBFS_Dm__0__SHIFT EQU 7\r
+USBFS_Dm__AG EQU CYREG_PRT15_AG\r
+USBFS_Dm__AMUX EQU CYREG_PRT15_AMUX\r
+USBFS_Dm__BIE EQU CYREG_PRT15_BIE\r
+USBFS_Dm__BIT_MASK EQU CYREG_PRT15_BIT_MASK\r
+USBFS_Dm__BYP EQU CYREG_PRT15_BYP\r
+USBFS_Dm__CTL EQU CYREG_PRT15_CTL\r
+USBFS_Dm__DM0 EQU CYREG_PRT15_DM0\r
+USBFS_Dm__DM1 EQU CYREG_PRT15_DM1\r
+USBFS_Dm__DM2 EQU CYREG_PRT15_DM2\r
+USBFS_Dm__DR EQU CYREG_PRT15_DR\r
+USBFS_Dm__INP_DIS EQU CYREG_PRT15_INP_DIS\r
+USBFS_Dm__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU15_BASE\r
+USBFS_Dm__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG\r
+USBFS_Dm__LCD_EN EQU CYREG_PRT15_LCD_EN\r
+USBFS_Dm__MASK EQU 0x80\r
+USBFS_Dm__PORT EQU 15\r
+USBFS_Dm__PRT EQU CYREG_PRT15_PRT\r
+USBFS_Dm__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL\r
+USBFS_Dm__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN\r
+USBFS_Dm__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0\r
+USBFS_Dm__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1\r
+USBFS_Dm__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0\r
+USBFS_Dm__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1\r
+USBFS_Dm__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT\r
+USBFS_Dm__PS EQU CYREG_PRT15_PS\r
+USBFS_Dm__SHIFT EQU 7\r
+USBFS_Dm__SLW EQU CYREG_PRT15_SLW\r
+USBFS_Dp__0__INTTYPE EQU CYREG_PICU15_INTTYPE6\r
+USBFS_Dp__0__MASK EQU 0x40\r
+USBFS_Dp__0__PC EQU CYREG_IO_PC_PRT15_7_6_PC0\r
+USBFS_Dp__0__PORT EQU 15\r
+USBFS_Dp__0__SHIFT EQU 6\r
+USBFS_Dp__AG EQU CYREG_PRT15_AG\r
+USBFS_Dp__AMUX EQU CYREG_PRT15_AMUX\r
+USBFS_Dp__BIE EQU CYREG_PRT15_BIE\r
+USBFS_Dp__BIT_MASK EQU CYREG_PRT15_BIT_MASK\r
+USBFS_Dp__BYP EQU CYREG_PRT15_BYP\r
+USBFS_Dp__CTL EQU CYREG_PRT15_CTL\r
+USBFS_Dp__DM0 EQU CYREG_PRT15_DM0\r
+USBFS_Dp__DM1 EQU CYREG_PRT15_DM1\r
+USBFS_Dp__DM2 EQU CYREG_PRT15_DM2\r
+USBFS_Dp__DR EQU CYREG_PRT15_DR\r
+USBFS_Dp__INP_DIS EQU CYREG_PRT15_INP_DIS\r
+USBFS_Dp__INTSTAT EQU CYREG_PICU15_INTSTAT\r
+USBFS_Dp__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU15_BASE\r
+USBFS_Dp__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG\r
+USBFS_Dp__LCD_EN EQU CYREG_PRT15_LCD_EN\r
+USBFS_Dp__MASK EQU 0x40\r
+USBFS_Dp__PORT EQU 15\r
+USBFS_Dp__PRT EQU CYREG_PRT15_PRT\r
+USBFS_Dp__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL\r
+USBFS_Dp__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN\r
+USBFS_Dp__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0\r
+USBFS_Dp__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1\r
+USBFS_Dp__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0\r
+USBFS_Dp__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1\r
+USBFS_Dp__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT\r
+USBFS_Dp__PS EQU CYREG_PRT15_PS\r
+USBFS_Dp__SHIFT EQU 6\r
+USBFS_Dp__SLW EQU CYREG_PRT15_SLW\r
+USBFS_Dp__SNAP EQU CYREG_PICU_15_SNAP_15\r
+USBFS_dp_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
+USBFS_dp_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
+USBFS_dp_int__INTC_MASK EQU 0x1000\r
+USBFS_dp_int__INTC_NUMBER EQU 12\r
+USBFS_dp_int__INTC_PRIOR_NUM EQU 7\r
+USBFS_dp_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_12\r
+USBFS_dp_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
+USBFS_dp_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
+USBFS_ep_0__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
+USBFS_ep_0__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
+USBFS_ep_0__INTC_MASK EQU 0x1000000\r
+USBFS_ep_0__INTC_NUMBER EQU 24\r
+USBFS_ep_0__INTC_PRIOR_NUM EQU 7\r
+USBFS_ep_0__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_24\r
+USBFS_ep_0__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
+USBFS_ep_0__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
+USBFS_ep_1__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
+USBFS_ep_1__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
+USBFS_ep_1__INTC_MASK EQU 0x80\r
+USBFS_ep_1__INTC_NUMBER EQU 7\r
+USBFS_ep_1__INTC_PRIOR_NUM EQU 7\r
+USBFS_ep_1__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_7\r
+USBFS_ep_1__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
+USBFS_ep_1__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
+USBFS_ep_2__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
+USBFS_ep_2__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
+USBFS_ep_2__INTC_MASK EQU 0x100\r
+USBFS_ep_2__INTC_NUMBER EQU 8\r
+USBFS_ep_2__INTC_PRIOR_NUM EQU 7\r
+USBFS_ep_2__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_8\r
+USBFS_ep_2__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
+USBFS_ep_2__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
+USBFS_ep_3__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
+USBFS_ep_3__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
+USBFS_ep_3__INTC_MASK EQU 0x200\r
+USBFS_ep_3__INTC_NUMBER EQU 9\r
+USBFS_ep_3__INTC_PRIOR_NUM EQU 7\r
+USBFS_ep_3__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_9\r
+USBFS_ep_3__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
+USBFS_ep_3__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
+USBFS_ep_4__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
+USBFS_ep_4__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
+USBFS_ep_4__INTC_MASK EQU 0x400\r
+USBFS_ep_4__INTC_NUMBER EQU 10\r
+USBFS_ep_4__INTC_PRIOR_NUM EQU 7\r
+USBFS_ep_4__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_10\r
+USBFS_ep_4__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
+USBFS_ep_4__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
+USBFS_sof_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
+USBFS_sof_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
+USBFS_sof_int__INTC_MASK EQU 0x200000\r
+USBFS_sof_int__INTC_NUMBER EQU 21\r
+USBFS_sof_int__INTC_PRIOR_NUM EQU 7\r
+USBFS_sof_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_21\r
+USBFS_sof_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
+USBFS_sof_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
+USBFS_USB__ARB_CFG EQU CYREG_USB_ARB_CFG\r
+USBFS_USB__ARB_EP1_CFG EQU CYREG_USB_ARB_EP1_CFG\r
+USBFS_USB__ARB_EP1_INT_EN EQU CYREG_USB_ARB_EP1_INT_EN\r
+USBFS_USB__ARB_EP1_SR EQU CYREG_USB_ARB_EP1_SR\r
+USBFS_USB__ARB_EP2_CFG EQU CYREG_USB_ARB_EP2_CFG\r
+USBFS_USB__ARB_EP2_INT_EN EQU CYREG_USB_ARB_EP2_INT_EN\r
+USBFS_USB__ARB_EP2_SR EQU CYREG_USB_ARB_EP2_SR\r
+USBFS_USB__ARB_EP3_CFG EQU CYREG_USB_ARB_EP3_CFG\r
+USBFS_USB__ARB_EP3_INT_EN EQU CYREG_USB_ARB_EP3_INT_EN\r
+USBFS_USB__ARB_EP3_SR EQU CYREG_USB_ARB_EP3_SR\r
+USBFS_USB__ARB_EP4_CFG EQU CYREG_USB_ARB_EP4_CFG\r
+USBFS_USB__ARB_EP4_INT_EN EQU CYREG_USB_ARB_EP4_INT_EN\r
+USBFS_USB__ARB_EP4_SR EQU CYREG_USB_ARB_EP4_SR\r
+USBFS_USB__ARB_EP5_CFG EQU CYREG_USB_ARB_EP5_CFG\r
+USBFS_USB__ARB_EP5_INT_EN EQU CYREG_USB_ARB_EP5_INT_EN\r
+USBFS_USB__ARB_EP5_SR EQU CYREG_USB_ARB_EP5_SR\r
+USBFS_USB__ARB_EP6_CFG EQU CYREG_USB_ARB_EP6_CFG\r
+USBFS_USB__ARB_EP6_INT_EN EQU CYREG_USB_ARB_EP6_INT_EN\r
+USBFS_USB__ARB_EP6_SR EQU CYREG_USB_ARB_EP6_SR\r
+USBFS_USB__ARB_EP7_CFG EQU CYREG_USB_ARB_EP7_CFG\r
+USBFS_USB__ARB_EP7_INT_EN EQU CYREG_USB_ARB_EP7_INT_EN\r
+USBFS_USB__ARB_EP7_SR EQU CYREG_USB_ARB_EP7_SR\r
+USBFS_USB__ARB_EP8_CFG EQU CYREG_USB_ARB_EP8_CFG\r
+USBFS_USB__ARB_EP8_INT_EN EQU CYREG_USB_ARB_EP8_INT_EN\r
+USBFS_USB__ARB_EP8_SR EQU CYREG_USB_ARB_EP8_SR\r
+USBFS_USB__ARB_INT_EN EQU CYREG_USB_ARB_INT_EN\r
+USBFS_USB__ARB_INT_SR EQU CYREG_USB_ARB_INT_SR\r
+USBFS_USB__ARB_RW1_DR EQU CYREG_USB_ARB_RW1_DR\r
+USBFS_USB__ARB_RW1_RA EQU CYREG_USB_ARB_RW1_RA\r
+USBFS_USB__ARB_RW1_RA_MSB EQU CYREG_USB_ARB_RW1_RA_MSB\r
+USBFS_USB__ARB_RW1_WA EQU CYREG_USB_ARB_RW1_WA\r
+USBFS_USB__ARB_RW1_WA_MSB EQU CYREG_USB_ARB_RW1_WA_MSB\r
+USBFS_USB__ARB_RW2_DR EQU CYREG_USB_ARB_RW2_DR\r
+USBFS_USB__ARB_RW2_RA EQU CYREG_USB_ARB_RW2_RA\r
+USBFS_USB__ARB_RW2_RA_MSB EQU CYREG_USB_ARB_RW2_RA_MSB\r
+USBFS_USB__ARB_RW2_WA EQU CYREG_USB_ARB_RW2_WA\r
+USBFS_USB__ARB_RW2_WA_MSB EQU CYREG_USB_ARB_RW2_WA_MSB\r
+USBFS_USB__ARB_RW3_DR EQU CYREG_USB_ARB_RW3_DR\r
+USBFS_USB__ARB_RW3_RA EQU CYREG_USB_ARB_RW3_RA\r
+USBFS_USB__ARB_RW3_RA_MSB EQU CYREG_USB_ARB_RW3_RA_MSB\r
+USBFS_USB__ARB_RW3_WA EQU CYREG_USB_ARB_RW3_WA\r
+USBFS_USB__ARB_RW3_WA_MSB EQU CYREG_USB_ARB_RW3_WA_MSB\r
+USBFS_USB__ARB_RW4_DR EQU CYREG_USB_ARB_RW4_DR\r
+USBFS_USB__ARB_RW4_RA EQU CYREG_USB_ARB_RW4_RA\r
+USBFS_USB__ARB_RW4_RA_MSB EQU CYREG_USB_ARB_RW4_RA_MSB\r
+USBFS_USB__ARB_RW4_WA EQU CYREG_USB_ARB_RW4_WA\r
+USBFS_USB__ARB_RW4_WA_MSB EQU CYREG_USB_ARB_RW4_WA_MSB\r
+USBFS_USB__ARB_RW5_DR EQU CYREG_USB_ARB_RW5_DR\r
+USBFS_USB__ARB_RW5_RA EQU CYREG_USB_ARB_RW5_RA\r
+USBFS_USB__ARB_RW5_RA_MSB EQU CYREG_USB_ARB_RW5_RA_MSB\r
+USBFS_USB__ARB_RW5_WA EQU CYREG_USB_ARB_RW5_WA\r
+USBFS_USB__ARB_RW5_WA_MSB EQU CYREG_USB_ARB_RW5_WA_MSB\r
+USBFS_USB__ARB_RW6_DR EQU CYREG_USB_ARB_RW6_DR\r
+USBFS_USB__ARB_RW6_RA EQU CYREG_USB_ARB_RW6_RA\r
+USBFS_USB__ARB_RW6_RA_MSB EQU CYREG_USB_ARB_RW6_RA_MSB\r
+USBFS_USB__ARB_RW6_WA EQU CYREG_USB_ARB_RW6_WA\r
+USBFS_USB__ARB_RW6_WA_MSB EQU CYREG_USB_ARB_RW6_WA_MSB\r
+USBFS_USB__ARB_RW7_DR EQU CYREG_USB_ARB_RW7_DR\r
+USBFS_USB__ARB_RW7_RA EQU CYREG_USB_ARB_RW7_RA\r
+USBFS_USB__ARB_RW7_RA_MSB EQU CYREG_USB_ARB_RW7_RA_MSB\r
+USBFS_USB__ARB_RW7_WA EQU CYREG_USB_ARB_RW7_WA\r
+USBFS_USB__ARB_RW7_WA_MSB EQU CYREG_USB_ARB_RW7_WA_MSB\r
+USBFS_USB__ARB_RW8_DR EQU CYREG_USB_ARB_RW8_DR\r
+USBFS_USB__ARB_RW8_RA EQU CYREG_USB_ARB_RW8_RA\r
+USBFS_USB__ARB_RW8_RA_MSB EQU CYREG_USB_ARB_RW8_RA_MSB\r
+USBFS_USB__ARB_RW8_WA EQU CYREG_USB_ARB_RW8_WA\r
+USBFS_USB__ARB_RW8_WA_MSB EQU CYREG_USB_ARB_RW8_WA_MSB\r
+USBFS_USB__BUF_SIZE EQU CYREG_USB_BUF_SIZE\r
+USBFS_USB__BUS_RST_CNT EQU CYREG_USB_BUS_RST_CNT\r
+USBFS_USB__CR0 EQU CYREG_USB_CR0\r
+USBFS_USB__CR1 EQU CYREG_USB_CR1\r
+USBFS_USB__CWA EQU CYREG_USB_CWA\r
+USBFS_USB__CWA_MSB EQU CYREG_USB_CWA_MSB\r
+USBFS_USB__DMA_THRES EQU CYREG_USB_DMA_THRES\r
+USBFS_USB__DMA_THRES_MSB EQU CYREG_USB_DMA_THRES_MSB\r
+USBFS_USB__DYN_RECONFIG EQU CYREG_USB_DYN_RECONFIG\r
+USBFS_USB__EP_ACTIVE EQU CYREG_USB_EP_ACTIVE\r
+USBFS_USB__EP_TYPE EQU CYREG_USB_EP_TYPE\r
+USBFS_USB__EP0_CNT EQU CYREG_USB_EP0_CNT\r
+USBFS_USB__EP0_CR EQU CYREG_USB_EP0_CR\r
+USBFS_USB__EP0_DR0 EQU CYREG_USB_EP0_DR0\r
+USBFS_USB__EP0_DR1 EQU CYREG_USB_EP0_DR1\r
+USBFS_USB__EP0_DR2 EQU CYREG_USB_EP0_DR2\r
+USBFS_USB__EP0_DR3 EQU CYREG_USB_EP0_DR3\r
+USBFS_USB__EP0_DR4 EQU CYREG_USB_EP0_DR4\r
+USBFS_USB__EP0_DR5 EQU CYREG_USB_EP0_DR5\r
+USBFS_USB__EP0_DR6 EQU CYREG_USB_EP0_DR6\r
+USBFS_USB__EP0_DR7 EQU CYREG_USB_EP0_DR7\r
+USBFS_USB__MEM_DATA EQU CYREG_USB_MEM_DATA_MBASE\r
+USBFS_USB__PM_ACT_CFG EQU CYREG_PM_ACT_CFG5\r
+USBFS_USB__PM_ACT_MSK EQU 0x01\r
+USBFS_USB__PM_STBY_CFG EQU CYREG_PM_STBY_CFG5\r
+USBFS_USB__PM_STBY_MSK EQU 0x01\r
+USBFS_USB__SIE_EP_INT_EN EQU CYREG_USB_SIE_EP_INT_EN\r
+USBFS_USB__SIE_EP_INT_SR EQU CYREG_USB_SIE_EP_INT_SR\r
+USBFS_USB__SIE_EP1_CNT0 EQU CYREG_USB_SIE_EP1_CNT0\r
+USBFS_USB__SIE_EP1_CNT1 EQU CYREG_USB_SIE_EP1_CNT1\r
+USBFS_USB__SIE_EP1_CR0 EQU CYREG_USB_SIE_EP1_CR0\r
+USBFS_USB__SIE_EP2_CNT0 EQU CYREG_USB_SIE_EP2_CNT0\r
+USBFS_USB__SIE_EP2_CNT1 EQU CYREG_USB_SIE_EP2_CNT1\r
+USBFS_USB__SIE_EP2_CR0 EQU CYREG_USB_SIE_EP2_CR0\r
+USBFS_USB__SIE_EP3_CNT0 EQU CYREG_USB_SIE_EP3_CNT0\r
+USBFS_USB__SIE_EP3_CNT1 EQU CYREG_USB_SIE_EP3_CNT1\r
+USBFS_USB__SIE_EP3_CR0 EQU CYREG_USB_SIE_EP3_CR0\r
+USBFS_USB__SIE_EP4_CNT0 EQU CYREG_USB_SIE_EP4_CNT0\r
+USBFS_USB__SIE_EP4_CNT1 EQU CYREG_USB_SIE_EP4_CNT1\r
+USBFS_USB__SIE_EP4_CR0 EQU CYREG_USB_SIE_EP4_CR0\r
+USBFS_USB__SIE_EP5_CNT0 EQU CYREG_USB_SIE_EP5_CNT0\r
+USBFS_USB__SIE_EP5_CNT1 EQU CYREG_USB_SIE_EP5_CNT1\r
+USBFS_USB__SIE_EP5_CR0 EQU CYREG_USB_SIE_EP5_CR0\r
+USBFS_USB__SIE_EP6_CNT0 EQU CYREG_USB_SIE_EP6_CNT0\r
+USBFS_USB__SIE_EP6_CNT1 EQU CYREG_USB_SIE_EP6_CNT1\r
+USBFS_USB__SIE_EP6_CR0 EQU CYREG_USB_SIE_EP6_CR0\r
+USBFS_USB__SIE_EP7_CNT0 EQU CYREG_USB_SIE_EP7_CNT0\r
+USBFS_USB__SIE_EP7_CNT1 EQU CYREG_USB_SIE_EP7_CNT1\r
+USBFS_USB__SIE_EP7_CR0 EQU CYREG_USB_SIE_EP7_CR0\r
+USBFS_USB__SIE_EP8_CNT0 EQU CYREG_USB_SIE_EP8_CNT0\r
+USBFS_USB__SIE_EP8_CNT1 EQU CYREG_USB_SIE_EP8_CNT1\r
+USBFS_USB__SIE_EP8_CR0 EQU CYREG_USB_SIE_EP8_CR0\r
+USBFS_USB__SOF0 EQU CYREG_USB_SOF0\r
+USBFS_USB__SOF1 EQU CYREG_USB_SOF1\r
+USBFS_USB__USB_CLK_EN EQU CYREG_USB_USB_CLK_EN\r
+USBFS_USB__USBIO_CR0 EQU CYREG_USB_USBIO_CR0\r
+USBFS_USB__USBIO_CR1 EQU CYREG_USB_USBIO_CR1\r
+\r
 /* scsiTarget */\r
 scsiTarget_datapath__16BIT_A0_REG EQU CYREG_B0_UDB00_01_A0\r
 scsiTarget_datapath__16BIT_A1_REG EQU CYREG_B0_UDB00_01_A1\r
@@ -2798,89 +2954,6 @@ scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB02_MSK
 scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL\r
 scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB02_ST\r
 \r
-/* Debug_Timer_Interrupt */\r
-Debug_Timer_Interrupt__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
-Debug_Timer_Interrupt__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
-Debug_Timer_Interrupt__INTC_MASK EQU 0x02\r
-Debug_Timer_Interrupt__INTC_NUMBER EQU 1\r
-Debug_Timer_Interrupt__INTC_PRIOR_NUM EQU 7\r
-Debug_Timer_Interrupt__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_1\r
-Debug_Timer_Interrupt__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
-Debug_Timer_Interrupt__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
-\r
-/* Debug_Timer_TimerHW */\r
-Debug_Timer_TimerHW__CAP0 EQU CYREG_TMR0_CAP0\r
-Debug_Timer_TimerHW__CAP1 EQU CYREG_TMR0_CAP1\r
-Debug_Timer_TimerHW__CFG0 EQU CYREG_TMR0_CFG0\r
-Debug_Timer_TimerHW__CFG1 EQU CYREG_TMR0_CFG1\r
-Debug_Timer_TimerHW__CFG2 EQU CYREG_TMR0_CFG2\r
-Debug_Timer_TimerHW__CNT_CMP0 EQU CYREG_TMR0_CNT_CMP0\r
-Debug_Timer_TimerHW__CNT_CMP1 EQU CYREG_TMR0_CNT_CMP1\r
-Debug_Timer_TimerHW__PER0 EQU CYREG_TMR0_PER0\r
-Debug_Timer_TimerHW__PER1 EQU CYREG_TMR0_PER1\r
-Debug_Timer_TimerHW__PM_ACT_CFG EQU CYREG_PM_ACT_CFG3\r
-Debug_Timer_TimerHW__PM_ACT_MSK EQU 0x01\r
-Debug_Timer_TimerHW__PM_STBY_CFG EQU CYREG_PM_STBY_CFG3\r
-Debug_Timer_TimerHW__PM_STBY_MSK EQU 0x01\r
-Debug_Timer_TimerHW__RT0 EQU CYREG_TMR0_RT0\r
-Debug_Timer_TimerHW__RT1 EQU CYREG_TMR0_RT1\r
-Debug_Timer_TimerHW__SR0 EQU CYREG_TMR0_SR0\r
-\r
-/* SCSI_RX_DMA */\r
-SCSI_RX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0\r
-SCSI_RX_DMA__DRQ_NUMBER EQU 0\r
-SCSI_RX_DMA__NUMBEROF_TDS EQU 0\r
-SCSI_RX_DMA__PRIORITY EQU 2\r
-SCSI_RX_DMA__TERMIN_EN EQU 0\r
-SCSI_RX_DMA__TERMIN_SEL EQU 0\r
-SCSI_RX_DMA__TERMOUT0_EN EQU 1\r
-SCSI_RX_DMA__TERMOUT0_SEL EQU 0\r
-SCSI_RX_DMA__TERMOUT1_EN EQU 0\r
-SCSI_RX_DMA__TERMOUT1_SEL EQU 0\r
-\r
-/* SCSI_RX_DMA_COMPLETE */\r
-SCSI_RX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
-SCSI_RX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
-SCSI_RX_DMA_COMPLETE__INTC_MASK EQU 0x01\r
-SCSI_RX_DMA_COMPLETE__INTC_NUMBER EQU 0\r
-SCSI_RX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7\r
-SCSI_RX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_0\r
-SCSI_RX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
-SCSI_RX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
-\r
-/* SCSI_TX_DMA */\r
-SCSI_TX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0\r
-SCSI_TX_DMA__DRQ_NUMBER EQU 1\r
-SCSI_TX_DMA__NUMBEROF_TDS EQU 0\r
-SCSI_TX_DMA__PRIORITY EQU 2\r
-SCSI_TX_DMA__TERMIN_EN EQU 0\r
-SCSI_TX_DMA__TERMIN_SEL EQU 0\r
-SCSI_TX_DMA__TERMOUT0_EN EQU 1\r
-SCSI_TX_DMA__TERMOUT0_SEL EQU 1\r
-SCSI_TX_DMA__TERMOUT1_EN EQU 0\r
-SCSI_TX_DMA__TERMOUT1_SEL EQU 0\r
-\r
-/* SCSI_TX_DMA_COMPLETE */\r
-SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
-SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
-SCSI_TX_DMA_COMPLETE__INTC_MASK EQU 0x10\r
-SCSI_TX_DMA_COMPLETE__INTC_NUMBER EQU 4\r
-SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7\r
-SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_4\r
-SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
-SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
-\r
-/* SD_Data_Clk */\r
-SD_Data_Clk__CFG0 EQU CYREG_CLKDIST_DCFG0_CFG0\r
-SD_Data_Clk__CFG1 EQU CYREG_CLKDIST_DCFG0_CFG1\r
-SD_Data_Clk__CFG2 EQU CYREG_CLKDIST_DCFG0_CFG2\r
-SD_Data_Clk__CFG2_SRC_SEL_MASK EQU 0x07\r
-SD_Data_Clk__INDEX EQU 0x00\r
-SD_Data_Clk__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2\r
-SD_Data_Clk__PM_ACT_MSK EQU 0x01\r
-SD_Data_Clk__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2\r
-SD_Data_Clk__PM_STBY_MSK EQU 0x01\r
-\r
 /* timer_clock */\r
 timer_clock__CFG0 EQU CYREG_CLKDIST_DCFG2_CFG0\r
 timer_clock__CFG1 EQU CYREG_CLKDIST_DCFG2_CFG1\r
@@ -2892,146 +2965,53 @@ timer_clock__PM_ACT_MSK EQU 0x04
 timer_clock__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2\r
 timer_clock__PM_STBY_MSK EQU 0x04\r
 \r
-/* SCSI_RST_ISR */\r
-SCSI_RST_ISR__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
-SCSI_RST_ISR__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
-SCSI_RST_ISR__INTC_MASK EQU 0x04\r
-SCSI_RST_ISR__INTC_NUMBER EQU 2\r
-SCSI_RST_ISR__INTC_PRIOR_NUM EQU 7\r
-SCSI_RST_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_2\r
-SCSI_RST_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
-SCSI_RST_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
-\r
-/* SCSI_SEL_ISR */\r
-SCSI_SEL_ISR__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
-SCSI_SEL_ISR__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
-SCSI_SEL_ISR__INTC_MASK EQU 0x08\r
-SCSI_SEL_ISR__INTC_NUMBER EQU 3\r
-SCSI_SEL_ISR__INTC_PRIOR_NUM EQU 7\r
-SCSI_SEL_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_3\r
-SCSI_SEL_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
-SCSI_SEL_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
-\r
-/* SCSI_Filtered */\r
-SCSI_Filtered_sts_sts_reg__0__MASK EQU 0x01\r
-SCSI_Filtered_sts_sts_reg__0__POS EQU 0\r
-SCSI_Filtered_sts_sts_reg__1__MASK EQU 0x02\r
-SCSI_Filtered_sts_sts_reg__1__POS EQU 1\r
-SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL\r
-SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB11_12_ST\r
-SCSI_Filtered_sts_sts_reg__2__MASK EQU 0x04\r
-SCSI_Filtered_sts_sts_reg__2__POS EQU 2\r
-SCSI_Filtered_sts_sts_reg__3__MASK EQU 0x08\r
-SCSI_Filtered_sts_sts_reg__3__POS EQU 3\r
-SCSI_Filtered_sts_sts_reg__4__MASK EQU 0x10\r
-SCSI_Filtered_sts_sts_reg__4__POS EQU 4\r
-SCSI_Filtered_sts_sts_reg__MASK EQU 0x1F\r
-SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB11_MSK\r
-SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL\r
-SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB11_ST\r
-\r
-/* SCSI_CTL_PHASE */\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS EQU 0\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK EQU 0x02\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS EQU 1\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB06_07_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB06_07_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB06_07_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB06_07_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB06_07_MSK\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB06_07_MSK\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB06_07_MSK\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB06_07_MSK\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK EQU 0x04\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS EQU 2\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB06_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB06_ST_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB06_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB06_ST_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__MASK EQU 0x07\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB06_MSK\r
-\r
-/* SCSI_Glitch_Ctl */\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS EQU 0\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB04_05_CTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB04_05_CTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB04_05_MSK\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB04_05_MSK\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB04_CTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB04_ST_CTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB04_CTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB04_ST_CTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK EQU 0x01\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB04_MSK\r
-\r
-/* SCSI_Parity_Error */\r
-SCSI_Parity_Error_sts_sts_reg__0__MASK EQU 0x01\r
-SCSI_Parity_Error_sts_sts_reg__0__POS EQU 0\r
-SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL\r
-SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB05_06_ST\r
-SCSI_Parity_Error_sts_sts_reg__MASK EQU 0x01\r
-SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB05_MSK\r
-SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL\r
-SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB05_ST\r
-\r
 /* Miscellaneous */\r
 BCLK__BUS_CLK__HZ EQU 50000000\r
 BCLK__BUS_CLK__KHZ EQU 50000\r
 BCLK__BUS_CLK__MHZ EQU 50\r
 CYDEV_CHIP_DIE_LEOPARD EQU 1\r
-CYDEV_CHIP_DIE_PSOC4A EQU 12\r
-CYDEV_CHIP_DIE_PSOC5LP EQU 19\r
-CYDEV_CHIP_DIE_PSOC5TM EQU 20\r
-CYDEV_CHIP_DIE_TMA4 EQU 2\r
+CYDEV_CHIP_DIE_PSOC4A EQU 16\r
+CYDEV_CHIP_DIE_PSOC5LP EQU 2\r
+CYDEV_CHIP_DIE_PSOC5TM EQU 3\r
+CYDEV_CHIP_DIE_TMA4 EQU 4\r
 CYDEV_CHIP_DIE_UNKNOWN EQU 0\r
-CYDEV_CHIP_FAMILY_FM0P EQU 4\r
-CYDEV_CHIP_FAMILY_FM3 EQU 5\r
-CYDEV_CHIP_FAMILY_FM4 EQU 6\r
+CYDEV_CHIP_FAMILY_FM0P EQU 5\r
+CYDEV_CHIP_FAMILY_FM3 EQU 6\r
+CYDEV_CHIP_FAMILY_FM4 EQU 7\r
 CYDEV_CHIP_FAMILY_PSOC3 EQU 1\r
 CYDEV_CHIP_FAMILY_PSOC4 EQU 2\r
 CYDEV_CHIP_FAMILY_PSOC5 EQU 3\r
+CYDEV_CHIP_FAMILY_PSOC6 EQU 4\r
 CYDEV_CHIP_FAMILY_UNKNOWN EQU 0\r
 CYDEV_CHIP_FAMILY_USED EQU CYDEV_CHIP_FAMILY_PSOC5\r
 CYDEV_CHIP_JTAG_ID EQU 0x2E133069\r
 CYDEV_CHIP_MEMBER_3A EQU 1\r
-CYDEV_CHIP_MEMBER_4A EQU 12\r
-CYDEV_CHIP_MEMBER_4C EQU 18\r
-CYDEV_CHIP_MEMBER_4D EQU 8\r
-CYDEV_CHIP_MEMBER_4E EQU 4\r
-CYDEV_CHIP_MEMBER_4F EQU 13\r
-CYDEV_CHIP_MEMBER_4G EQU 2\r
-CYDEV_CHIP_MEMBER_4H EQU 11\r
-CYDEV_CHIP_MEMBER_4I EQU 17\r
-CYDEV_CHIP_MEMBER_4J EQU 9\r
-CYDEV_CHIP_MEMBER_4K EQU 10\r
-CYDEV_CHIP_MEMBER_4L EQU 16\r
-CYDEV_CHIP_MEMBER_4M EQU 15\r
-CYDEV_CHIP_MEMBER_4N EQU 6\r
-CYDEV_CHIP_MEMBER_4O EQU 5\r
-CYDEV_CHIP_MEMBER_4P EQU 14\r
-CYDEV_CHIP_MEMBER_4Q EQU 7\r
-CYDEV_CHIP_MEMBER_4U EQU 3\r
-CYDEV_CHIP_MEMBER_5A EQU 20\r
-CYDEV_CHIP_MEMBER_5B EQU 19\r
-CYDEV_CHIP_MEMBER_FM3 EQU 24\r
-CYDEV_CHIP_MEMBER_FM4 EQU 25\r
-CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE1 EQU 21\r
-CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE2 EQU 22\r
-CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE3 EQU 23\r
+CYDEV_CHIP_MEMBER_4A EQU 16\r
+CYDEV_CHIP_MEMBER_4D EQU 12\r
+CYDEV_CHIP_MEMBER_4E EQU 6\r
+CYDEV_CHIP_MEMBER_4F EQU 17\r
+CYDEV_CHIP_MEMBER_4G EQU 4\r
+CYDEV_CHIP_MEMBER_4H EQU 15\r
+CYDEV_CHIP_MEMBER_4I EQU 21\r
+CYDEV_CHIP_MEMBER_4J EQU 13\r
+CYDEV_CHIP_MEMBER_4K EQU 14\r
+CYDEV_CHIP_MEMBER_4L EQU 20\r
+CYDEV_CHIP_MEMBER_4M EQU 19\r
+CYDEV_CHIP_MEMBER_4N EQU 9\r
+CYDEV_CHIP_MEMBER_4O EQU 7\r
+CYDEV_CHIP_MEMBER_4P EQU 18\r
+CYDEV_CHIP_MEMBER_4Q EQU 11\r
+CYDEV_CHIP_MEMBER_4R EQU 8\r
+CYDEV_CHIP_MEMBER_4S EQU 10\r
+CYDEV_CHIP_MEMBER_4U EQU 5\r
+CYDEV_CHIP_MEMBER_5A EQU 3\r
+CYDEV_CHIP_MEMBER_5B EQU 2\r
+CYDEV_CHIP_MEMBER_6A EQU 22\r
+CYDEV_CHIP_MEMBER_FM3 EQU 26\r
+CYDEV_CHIP_MEMBER_FM4 EQU 27\r
+CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE1 EQU 23\r
+CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE2 EQU 24\r
+CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE3 EQU 25\r
 CYDEV_CHIP_MEMBER_UNKNOWN EQU 0\r
 CYDEV_CHIP_MEMBER_USED EQU CYDEV_CHIP_MEMBER_5B\r
 CYDEV_CHIP_DIE_EXPECT EQU CYDEV_CHIP_MEMBER_USED\r
@@ -3056,7 +3036,6 @@ CYDEV_CHIP_REVISION_3A_ES3 EQU 3
 CYDEV_CHIP_REVISION_3A_PRODUCTION EQU 3\r
 CYDEV_CHIP_REVISION_4A_ES0 EQU 17\r
 CYDEV_CHIP_REVISION_4A_PRODUCTION EQU 17\r
-CYDEV_CHIP_REVISION_4C_PRODUCTION EQU 0\r
 CYDEV_CHIP_REVISION_4D_PRODUCTION EQU 0\r
 CYDEV_CHIP_REVISION_4E_PRODUCTION EQU 0\r
 CYDEV_CHIP_REVISION_4F_PRODUCTION EQU 0\r
@@ -3075,12 +3054,16 @@ CYDEV_CHIP_REVISION_4N_PRODUCTION EQU 0
 CYDEV_CHIP_REVISION_4O_PRODUCTION EQU 0\r
 CYDEV_CHIP_REVISION_4P_PRODUCTION EQU 0\r
 CYDEV_CHIP_REVISION_4Q_PRODUCTION EQU 0\r
+CYDEV_CHIP_REVISION_4R_PRODUCTION EQU 0\r
+CYDEV_CHIP_REVISION_4S_PRODUCTION EQU 0\r
 CYDEV_CHIP_REVISION_4U_PRODUCTION EQU 0\r
 CYDEV_CHIP_REVISION_5A_ES0 EQU 0\r
 CYDEV_CHIP_REVISION_5A_ES1 EQU 1\r
 CYDEV_CHIP_REVISION_5A_PRODUCTION EQU 1\r
 CYDEV_CHIP_REVISION_5B_ES0 EQU 0\r
 CYDEV_CHIP_REVISION_5B_PRODUCTION EQU 0\r
+CYDEV_CHIP_REVISION_6A_NO_UDB EQU 0\r
+CYDEV_CHIP_REVISION_6A_PRODUCTION EQU 0\r
 CYDEV_CHIP_REVISION_FM3_PRODUCTION EQU 0\r
 CYDEV_CHIP_REVISION_FM4_PRODUCTION EQU 0\r
 CYDEV_CHIP_REVISION_PDL_FM0P_TYPE1_PRODUCTION EQU 0\r
@@ -3112,7 +3095,7 @@ CYDEV_DMA_CHANNELS_AVAILABLE EQU 24
 CYDEV_ECC_ENABLE EQU 0\r
 CYDEV_HEAP_SIZE EQU 0x0400\r
 CYDEV_INSTRUCT_CACHE_ENABLED EQU 1\r
-CYDEV_INTR_RISING EQU 0x0000007E\r
+CYDEV_INTR_RISING EQU 0x0000007F\r
 CYDEV_IS_EXPORTING_CODE EQU 0\r
 CYDEV_IS_IMPORTING_CODE EQU 0\r
 CYDEV_PROJ_TYPE EQU 2\r

diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitterrv.inc b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitterrv.inc
index 85be674dbaa066f32b806ccd36f06d1a821c6802..a3484aa7d46100eb94f3bac144acaceddaf3a5a4 100755 (executable)
--- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitterrv.inc
+++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitterrv.inc
@@ -1,8 +1,85 @@
+;\r
+; File Name: cyfitterrv.inc\r
+; \r
+; PSoC Creator  4.1\r
+;\r
+; Description:\r
+; \r
+;\r
+;-------------------------------------------------------------------------------\r
+; Copyright (c) 2007-2017 Cypress Semiconductor.  All rights reserved.\r
+; You may use this file only in accordance with the license, terms, conditions, \r
+; disclaimers, and limitations in the end user license agreement accompanying \r
+; the software package with which this file was provided.\r
+;-------------------------------------------------------------------------------\r
+\r
     IF :LNOT::DEF:INCLUDED_CYFITTERRV_INC\r
 INCLUDED_CYFITTERRV_INC EQU 1\r
     GET cydevicerv.inc\r
     GET cydevicerv_trm.inc\r
 \r
+; Debug_Timer_Interrupt\r
+Debug_Timer_Interrupt__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
+Debug_Timer_Interrupt__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
+Debug_Timer_Interrupt__INTC_MASK EQU 0x01\r
+Debug_Timer_Interrupt__INTC_NUMBER EQU 0\r
+Debug_Timer_Interrupt__INTC_PRIOR_NUM EQU 7\r
+Debug_Timer_Interrupt__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_0\r
+Debug_Timer_Interrupt__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
+Debug_Timer_Interrupt__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
+\r
+; Debug_Timer_TimerHW\r
+Debug_Timer_TimerHW__CAP0 EQU CYREG_TMR0_CAP0\r
+Debug_Timer_TimerHW__CAP1 EQU CYREG_TMR0_CAP1\r
+Debug_Timer_TimerHW__CFG0 EQU CYREG_TMR0_CFG0\r
+Debug_Timer_TimerHW__CFG1 EQU CYREG_TMR0_CFG1\r
+Debug_Timer_TimerHW__CFG2 EQU CYREG_TMR0_CFG2\r
+Debug_Timer_TimerHW__CNT_CMP0 EQU CYREG_TMR0_CNT_CMP0\r
+Debug_Timer_TimerHW__CNT_CMP1 EQU CYREG_TMR0_CNT_CMP1\r
+Debug_Timer_TimerHW__PER0 EQU CYREG_TMR0_PER0\r
+Debug_Timer_TimerHW__PER1 EQU CYREG_TMR0_PER1\r
+Debug_Timer_TimerHW__PM_ACT_CFG EQU CYREG_PM_ACT_CFG3\r
+Debug_Timer_TimerHW__PM_ACT_MSK EQU 0x01\r
+Debug_Timer_TimerHW__PM_STBY_CFG EQU CYREG_PM_STBY_CFG3\r
+Debug_Timer_TimerHW__PM_STBY_MSK EQU 0x01\r
+Debug_Timer_TimerHW__RT0 EQU CYREG_TMR0_RT0\r
+Debug_Timer_TimerHW__RT1 EQU CYREG_TMR0_RT1\r
+Debug_Timer_TimerHW__SR0 EQU CYREG_TMR0_SR0\r
+\r
+; EXTLED\r
+EXTLED__0__INTTYPE EQU CYREG_PICU0_INTTYPE0\r
+EXTLED__0__MASK EQU 0x01\r
+EXTLED__0__PC EQU CYREG_PRT0_PC0\r
+EXTLED__0__PORT EQU 0\r
+EXTLED__0__SHIFT EQU 0\r
+EXTLED__AG EQU CYREG_PRT0_AG\r
+EXTLED__AMUX EQU CYREG_PRT0_AMUX\r
+EXTLED__BIE EQU CYREG_PRT0_BIE\r
+EXTLED__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
+EXTLED__BYP EQU CYREG_PRT0_BYP\r
+EXTLED__CTL EQU CYREG_PRT0_CTL\r
+EXTLED__DM0 EQU CYREG_PRT0_DM0\r
+EXTLED__DM1 EQU CYREG_PRT0_DM1\r
+EXTLED__DM2 EQU CYREG_PRT0_DM2\r
+EXTLED__DR EQU CYREG_PRT0_DR\r
+EXTLED__INP_DIS EQU CYREG_PRT0_INP_DIS\r
+EXTLED__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU0_BASE\r
+EXTLED__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
+EXTLED__LCD_EN EQU CYREG_PRT0_LCD_EN\r
+EXTLED__MASK EQU 0x01\r
+EXTLED__PORT EQU 0\r
+EXTLED__PRT EQU CYREG_PRT0_PRT\r
+EXTLED__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
+EXTLED__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
+EXTLED__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
+EXTLED__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
+EXTLED__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
+EXTLED__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
+EXTLED__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
+EXTLED__PS EQU CYREG_PRT0_PS\r
+EXTLED__SHIFT EQU 0\r
+EXTLED__SLW EQU CYREG_PRT0_SLW\r
+\r
 ; LED1\r
 LED1__0__INTTYPE EQU CYREG_PICU0_INTTYPE1\r
 LED1__0__MASK EQU 0x02\r
@@ -37,2421 +114,808 @@ LED1__PS EQU CYREG_PRT0_PS
 LED1__SHIFT EQU 1\r
 LED1__SLW EQU CYREG_PRT0_SLW\r
 \r
-; SD_CD\r
-SD_CD__0__INTTYPE EQU CYREG_PICU3_INTTYPE5\r
-SD_CD__0__MASK EQU 0x20\r
-SD_CD__0__PC EQU CYREG_PRT3_PC5\r
-SD_CD__0__PORT EQU 3\r
-SD_CD__0__SHIFT EQU 5\r
-SD_CD__AG EQU CYREG_PRT3_AG\r
-SD_CD__AMUX EQU CYREG_PRT3_AMUX\r
-SD_CD__BIE EQU CYREG_PRT3_BIE\r
-SD_CD__BIT_MASK EQU CYREG_PRT3_BIT_MASK\r
-SD_CD__BYP EQU CYREG_PRT3_BYP\r
-SD_CD__CTL EQU CYREG_PRT3_CTL\r
-SD_CD__DM0 EQU CYREG_PRT3_DM0\r
-SD_CD__DM1 EQU CYREG_PRT3_DM1\r
-SD_CD__DM2 EQU CYREG_PRT3_DM2\r
-SD_CD__DR EQU CYREG_PRT3_DR\r
-SD_CD__INP_DIS EQU CYREG_PRT3_INP_DIS\r
-SD_CD__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE\r
-SD_CD__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG\r
-SD_CD__LCD_EN EQU CYREG_PRT3_LCD_EN\r
-SD_CD__MASK EQU 0x20\r
-SD_CD__PORT EQU 3\r
-SD_CD__PRT EQU CYREG_PRT3_PRT\r
-SD_CD__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL\r
-SD_CD__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN\r
-SD_CD__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0\r
-SD_CD__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1\r
-SD_CD__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0\r
-SD_CD__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1\r
-SD_CD__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT\r
-SD_CD__PS EQU CYREG_PRT3_PS\r
-SD_CD__SHIFT EQU 5\r
-SD_CD__SLW EQU CYREG_PRT3_SLW\r
-\r
-; SD_CS\r
-SD_CS__0__INTTYPE EQU CYREG_PICU3_INTTYPE4\r
-SD_CS__0__MASK EQU 0x10\r
-SD_CS__0__PC EQU CYREG_PRT3_PC4\r
-SD_CS__0__PORT EQU 3\r
-SD_CS__0__SHIFT EQU 4\r
-SD_CS__AG EQU CYREG_PRT3_AG\r
-SD_CS__AMUX EQU CYREG_PRT3_AMUX\r
-SD_CS__BIE EQU CYREG_PRT3_BIE\r
-SD_CS__BIT_MASK EQU CYREG_PRT3_BIT_MASK\r
-SD_CS__BYP EQU CYREG_PRT3_BYP\r
-SD_CS__CTL EQU CYREG_PRT3_CTL\r
-SD_CS__DM0 EQU CYREG_PRT3_DM0\r
-SD_CS__DM1 EQU CYREG_PRT3_DM1\r
-SD_CS__DM2 EQU CYREG_PRT3_DM2\r
-SD_CS__DR EQU CYREG_PRT3_DR\r
-SD_CS__INP_DIS EQU CYREG_PRT3_INP_DIS\r
-SD_CS__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE\r
-SD_CS__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG\r
-SD_CS__LCD_EN EQU CYREG_PRT3_LCD_EN\r
-SD_CS__MASK EQU 0x10\r
-SD_CS__PORT EQU 3\r
-SD_CS__PRT EQU CYREG_PRT3_PRT\r
-SD_CS__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL\r
-SD_CS__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN\r
-SD_CS__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0\r
-SD_CS__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1\r
-SD_CS__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0\r
-SD_CS__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1\r
-SD_CS__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT\r
-SD_CS__PS EQU CYREG_PRT3_PS\r
-SD_CS__SHIFT EQU 4\r
-SD_CS__SLW EQU CYREG_PRT3_SLW\r
+; SCSI_CLK\r
+SCSI_CLK__CFG0 EQU CYREG_CLKDIST_DCFG1_CFG0\r
+SCSI_CLK__CFG1 EQU CYREG_CLKDIST_DCFG1_CFG1\r
+SCSI_CLK__CFG2 EQU CYREG_CLKDIST_DCFG1_CFG2\r
+SCSI_CLK__CFG2_SRC_SEL_MASK EQU 0x07\r
+SCSI_CLK__INDEX EQU 0x01\r
+SCSI_CLK__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2\r
+SCSI_CLK__PM_ACT_MSK EQU 0x02\r
+SCSI_CLK__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2\r
+SCSI_CLK__PM_STBY_MSK EQU 0x02\r
 \r
-; USBFS_arb_int\r
-USBFS_arb_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
-USBFS_arb_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
-USBFS_arb_int__INTC_MASK EQU 0x400000\r
-USBFS_arb_int__INTC_NUMBER EQU 22\r
-USBFS_arb_int__INTC_PRIOR_NUM EQU 6\r
-USBFS_arb_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_22\r
-USBFS_arb_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
-USBFS_arb_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
+; SCSI_CTL_PHASE\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS EQU 0\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK EQU 0x02\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS EQU 1\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB06_07_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB06_07_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB06_07_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB06_07_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB06_07_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB06_07_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB06_07_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB06_07_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK EQU 0x04\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS EQU 2\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB06_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB06_ST_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB06_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB06_ST_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__MASK EQU 0x07\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB06_MSK\r
 \r
-; USBFS_bus_reset\r
-USBFS_bus_reset__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
-USBFS_bus_reset__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
-USBFS_bus_reset__INTC_MASK EQU 0x800000\r
-USBFS_bus_reset__INTC_NUMBER EQU 23\r
-USBFS_bus_reset__INTC_PRIOR_NUM EQU 7\r
-USBFS_bus_reset__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_23\r
-USBFS_bus_reset__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
-USBFS_bus_reset__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
+; SCSI_Filtered\r
+SCSI_Filtered_sts_sts_reg__0__MASK EQU 0x01\r
+SCSI_Filtered_sts_sts_reg__0__POS EQU 0\r
+SCSI_Filtered_sts_sts_reg__1__MASK EQU 0x02\r
+SCSI_Filtered_sts_sts_reg__1__POS EQU 1\r
+SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL\r
+SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB11_12_ST\r
+SCSI_Filtered_sts_sts_reg__2__MASK EQU 0x04\r
+SCSI_Filtered_sts_sts_reg__2__POS EQU 2\r
+SCSI_Filtered_sts_sts_reg__3__MASK EQU 0x08\r
+SCSI_Filtered_sts_sts_reg__3__POS EQU 3\r
+SCSI_Filtered_sts_sts_reg__4__MASK EQU 0x10\r
+SCSI_Filtered_sts_sts_reg__4__POS EQU 4\r
+SCSI_Filtered_sts_sts_reg__MASK EQU 0x1F\r
+SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB11_MSK\r
+SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL\r
+SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB11_ST\r
 \r
-; USBFS_Dm\r
-USBFS_Dm__0__INTTYPE EQU CYREG_PICU15_INTTYPE7\r
-USBFS_Dm__0__MASK EQU 0x80\r
-USBFS_Dm__0__PC EQU CYREG_IO_PC_PRT15_7_6_PC1\r
-USBFS_Dm__0__PORT EQU 15\r
-USBFS_Dm__0__SHIFT EQU 7\r
-USBFS_Dm__AG EQU CYREG_PRT15_AG\r
-USBFS_Dm__AMUX EQU CYREG_PRT15_AMUX\r
-USBFS_Dm__BIE EQU CYREG_PRT15_BIE\r
-USBFS_Dm__BIT_MASK EQU CYREG_PRT15_BIT_MASK\r
-USBFS_Dm__BYP EQU CYREG_PRT15_BYP\r
-USBFS_Dm__CTL EQU CYREG_PRT15_CTL\r
-USBFS_Dm__DM0 EQU CYREG_PRT15_DM0\r
-USBFS_Dm__DM1 EQU CYREG_PRT15_DM1\r
-USBFS_Dm__DM2 EQU CYREG_PRT15_DM2\r
-USBFS_Dm__DR EQU CYREG_PRT15_DR\r
-USBFS_Dm__INP_DIS EQU CYREG_PRT15_INP_DIS\r
-USBFS_Dm__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU15_BASE\r
-USBFS_Dm__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG\r
-USBFS_Dm__LCD_EN EQU CYREG_PRT15_LCD_EN\r
-USBFS_Dm__MASK EQU 0x80\r
-USBFS_Dm__PORT EQU 15\r
-USBFS_Dm__PRT EQU CYREG_PRT15_PRT\r
-USBFS_Dm__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL\r
-USBFS_Dm__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN\r
-USBFS_Dm__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0\r
-USBFS_Dm__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1\r
-USBFS_Dm__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0\r
-USBFS_Dm__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1\r
-USBFS_Dm__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT\r
-USBFS_Dm__PS EQU CYREG_PRT15_PS\r
-USBFS_Dm__SHIFT EQU 7\r
-USBFS_Dm__SLW EQU CYREG_PRT15_SLW\r
+; SCSI_Glitch_Ctl\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS EQU 0\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB04_05_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB04_05_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB04_05_MSK\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB04_05_MSK\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB04_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB04_ST_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB04_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB04_ST_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK EQU 0x01\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB04_MSK\r
 \r
-; USBFS_Dp\r
-USBFS_Dp__0__INTTYPE EQU CYREG_PICU15_INTTYPE6\r
-USBFS_Dp__0__MASK EQU 0x40\r
-USBFS_Dp__0__PC EQU CYREG_IO_PC_PRT15_7_6_PC0\r
-USBFS_Dp__0__PORT EQU 15\r
-USBFS_Dp__0__SHIFT EQU 6\r
-USBFS_Dp__AG EQU CYREG_PRT15_AG\r
-USBFS_Dp__AMUX EQU CYREG_PRT15_AMUX\r
-USBFS_Dp__BIE EQU CYREG_PRT15_BIE\r
-USBFS_Dp__BIT_MASK EQU CYREG_PRT15_BIT_MASK\r
-USBFS_Dp__BYP EQU CYREG_PRT15_BYP\r
-USBFS_Dp__CTL EQU CYREG_PRT15_CTL\r
-USBFS_Dp__DM0 EQU CYREG_PRT15_DM0\r
-USBFS_Dp__DM1 EQU CYREG_PRT15_DM1\r
-USBFS_Dp__DM2 EQU CYREG_PRT15_DM2\r
-USBFS_Dp__DR EQU CYREG_PRT15_DR\r
-USBFS_Dp__INP_DIS EQU CYREG_PRT15_INP_DIS\r
-USBFS_Dp__INTSTAT EQU CYREG_PICU15_INTSTAT\r
-USBFS_Dp__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU15_BASE\r
-USBFS_Dp__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG\r
-USBFS_Dp__LCD_EN EQU CYREG_PRT15_LCD_EN\r
-USBFS_Dp__MASK EQU 0x40\r
-USBFS_Dp__PORT EQU 15\r
-USBFS_Dp__PRT EQU CYREG_PRT15_PRT\r
-USBFS_Dp__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL\r
-USBFS_Dp__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN\r
-USBFS_Dp__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0\r
-USBFS_Dp__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1\r
-USBFS_Dp__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0\r
-USBFS_Dp__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1\r
-USBFS_Dp__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT\r
-USBFS_Dp__PS EQU CYREG_PRT15_PS\r
-USBFS_Dp__SHIFT EQU 6\r
-USBFS_Dp__SLW EQU CYREG_PRT15_SLW\r
-USBFS_Dp__SNAP EQU CYREG_PICU_15_SNAP_15\r
-\r
-; USBFS_dp_int\r
-USBFS_dp_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
-USBFS_dp_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
-USBFS_dp_int__INTC_MASK EQU 0x1000\r
-USBFS_dp_int__INTC_NUMBER EQU 12\r
-USBFS_dp_int__INTC_PRIOR_NUM EQU 7\r
-USBFS_dp_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_12\r
-USBFS_dp_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
-USBFS_dp_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
-\r
-; USBFS_ep_0\r
-USBFS_ep_0__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
-USBFS_ep_0__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
-USBFS_ep_0__INTC_MASK EQU 0x1000000\r
-USBFS_ep_0__INTC_NUMBER EQU 24\r
-USBFS_ep_0__INTC_PRIOR_NUM EQU 7\r
-USBFS_ep_0__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_24\r
-USBFS_ep_0__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
-USBFS_ep_0__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
-\r
-; USBFS_ep_1\r
-USBFS_ep_1__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
-USBFS_ep_1__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
-USBFS_ep_1__INTC_MASK EQU 0x80\r
-USBFS_ep_1__INTC_NUMBER EQU 7\r
-USBFS_ep_1__INTC_PRIOR_NUM EQU 7\r
-USBFS_ep_1__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_7\r
-USBFS_ep_1__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
-USBFS_ep_1__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
-\r
-; USBFS_ep_2\r
-USBFS_ep_2__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
-USBFS_ep_2__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
-USBFS_ep_2__INTC_MASK EQU 0x100\r
-USBFS_ep_2__INTC_NUMBER EQU 8\r
-USBFS_ep_2__INTC_PRIOR_NUM EQU 7\r
-USBFS_ep_2__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_8\r
-USBFS_ep_2__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
-USBFS_ep_2__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
-\r
-; USBFS_ep_3\r
-USBFS_ep_3__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
-USBFS_ep_3__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
-USBFS_ep_3__INTC_MASK EQU 0x200\r
-USBFS_ep_3__INTC_NUMBER EQU 9\r
-USBFS_ep_3__INTC_PRIOR_NUM EQU 7\r
-USBFS_ep_3__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_9\r
-USBFS_ep_3__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
-USBFS_ep_3__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
-\r
-; USBFS_ep_4\r
-USBFS_ep_4__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
-USBFS_ep_4__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
-USBFS_ep_4__INTC_MASK EQU 0x400\r
-USBFS_ep_4__INTC_NUMBER EQU 10\r
-USBFS_ep_4__INTC_PRIOR_NUM EQU 7\r
-USBFS_ep_4__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_10\r
-USBFS_ep_4__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
-USBFS_ep_4__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
-\r
-; USBFS_sof_int\r
-USBFS_sof_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
-USBFS_sof_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
-USBFS_sof_int__INTC_MASK EQU 0x200000\r
-USBFS_sof_int__INTC_NUMBER EQU 21\r
-USBFS_sof_int__INTC_PRIOR_NUM EQU 7\r
-USBFS_sof_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_21\r
-USBFS_sof_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
-USBFS_sof_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
-\r
-; USBFS_USB\r
-USBFS_USB__ARB_CFG EQU CYREG_USB_ARB_CFG\r
-USBFS_USB__ARB_EP1_CFG EQU CYREG_USB_ARB_EP1_CFG\r
-USBFS_USB__ARB_EP1_INT_EN EQU CYREG_USB_ARB_EP1_INT_EN\r
-USBFS_USB__ARB_EP1_SR EQU CYREG_USB_ARB_EP1_SR\r
-USBFS_USB__ARB_EP2_CFG EQU CYREG_USB_ARB_EP2_CFG\r
-USBFS_USB__ARB_EP2_INT_EN EQU CYREG_USB_ARB_EP2_INT_EN\r
-USBFS_USB__ARB_EP2_SR EQU CYREG_USB_ARB_EP2_SR\r
-USBFS_USB__ARB_EP3_CFG EQU CYREG_USB_ARB_EP3_CFG\r
-USBFS_USB__ARB_EP3_INT_EN EQU CYREG_USB_ARB_EP3_INT_EN\r
-USBFS_USB__ARB_EP3_SR EQU CYREG_USB_ARB_EP3_SR\r
-USBFS_USB__ARB_EP4_CFG EQU CYREG_USB_ARB_EP4_CFG\r
-USBFS_USB__ARB_EP4_INT_EN EQU CYREG_USB_ARB_EP4_INT_EN\r
-USBFS_USB__ARB_EP4_SR EQU CYREG_USB_ARB_EP4_SR\r
-USBFS_USB__ARB_EP5_CFG EQU CYREG_USB_ARB_EP5_CFG\r
-USBFS_USB__ARB_EP5_INT_EN EQU CYREG_USB_ARB_EP5_INT_EN\r
-USBFS_USB__ARB_EP5_SR EQU CYREG_USB_ARB_EP5_SR\r
-USBFS_USB__ARB_EP6_CFG EQU CYREG_USB_ARB_EP6_CFG\r
-USBFS_USB__ARB_EP6_INT_EN EQU CYREG_USB_ARB_EP6_INT_EN\r
-USBFS_USB__ARB_EP6_SR EQU CYREG_USB_ARB_EP6_SR\r
-USBFS_USB__ARB_EP7_CFG EQU CYREG_USB_ARB_EP7_CFG\r
-USBFS_USB__ARB_EP7_INT_EN EQU CYREG_USB_ARB_EP7_INT_EN\r
-USBFS_USB__ARB_EP7_SR EQU CYREG_USB_ARB_EP7_SR\r
-USBFS_USB__ARB_EP8_CFG EQU CYREG_USB_ARB_EP8_CFG\r
-USBFS_USB__ARB_EP8_INT_EN EQU CYREG_USB_ARB_EP8_INT_EN\r
-USBFS_USB__ARB_EP8_SR EQU CYREG_USB_ARB_EP8_SR\r
-USBFS_USB__ARB_INT_EN EQU CYREG_USB_ARB_INT_EN\r
-USBFS_USB__ARB_INT_SR EQU CYREG_USB_ARB_INT_SR\r
-USBFS_USB__ARB_RW1_DR EQU CYREG_USB_ARB_RW1_DR\r
-USBFS_USB__ARB_RW1_RA EQU CYREG_USB_ARB_RW1_RA\r
-USBFS_USB__ARB_RW1_RA_MSB EQU CYREG_USB_ARB_RW1_RA_MSB\r
-USBFS_USB__ARB_RW1_WA EQU CYREG_USB_ARB_RW1_WA\r
-USBFS_USB__ARB_RW1_WA_MSB EQU CYREG_USB_ARB_RW1_WA_MSB\r
-USBFS_USB__ARB_RW2_DR EQU CYREG_USB_ARB_RW2_DR\r
-USBFS_USB__ARB_RW2_RA EQU CYREG_USB_ARB_RW2_RA\r
-USBFS_USB__ARB_RW2_RA_MSB EQU CYREG_USB_ARB_RW2_RA_MSB\r
-USBFS_USB__ARB_RW2_WA EQU CYREG_USB_ARB_RW2_WA\r
-USBFS_USB__ARB_RW2_WA_MSB EQU CYREG_USB_ARB_RW2_WA_MSB\r
-USBFS_USB__ARB_RW3_DR EQU CYREG_USB_ARB_RW3_DR\r
-USBFS_USB__ARB_RW3_RA EQU CYREG_USB_ARB_RW3_RA\r
-USBFS_USB__ARB_RW3_RA_MSB EQU CYREG_USB_ARB_RW3_RA_MSB\r
-USBFS_USB__ARB_RW3_WA EQU CYREG_USB_ARB_RW3_WA\r
-USBFS_USB__ARB_RW3_WA_MSB EQU CYREG_USB_ARB_RW3_WA_MSB\r
-USBFS_USB__ARB_RW4_DR EQU CYREG_USB_ARB_RW4_DR\r
-USBFS_USB__ARB_RW4_RA EQU CYREG_USB_ARB_RW4_RA\r
-USBFS_USB__ARB_RW4_RA_MSB EQU CYREG_USB_ARB_RW4_RA_MSB\r
-USBFS_USB__ARB_RW4_WA EQU CYREG_USB_ARB_RW4_WA\r
-USBFS_USB__ARB_RW4_WA_MSB EQU CYREG_USB_ARB_RW4_WA_MSB\r
-USBFS_USB__ARB_RW5_DR EQU CYREG_USB_ARB_RW5_DR\r
-USBFS_USB__ARB_RW5_RA EQU CYREG_USB_ARB_RW5_RA\r
-USBFS_USB__ARB_RW5_RA_MSB EQU CYREG_USB_ARB_RW5_RA_MSB\r
-USBFS_USB__ARB_RW5_WA EQU CYREG_USB_ARB_RW5_WA\r
-USBFS_USB__ARB_RW5_WA_MSB EQU CYREG_USB_ARB_RW5_WA_MSB\r
-USBFS_USB__ARB_RW6_DR EQU CYREG_USB_ARB_RW6_DR\r
-USBFS_USB__ARB_RW6_RA EQU CYREG_USB_ARB_RW6_RA\r
-USBFS_USB__ARB_RW6_RA_MSB EQU CYREG_USB_ARB_RW6_RA_MSB\r
-USBFS_USB__ARB_RW6_WA EQU CYREG_USB_ARB_RW6_WA\r
-USBFS_USB__ARB_RW6_WA_MSB EQU CYREG_USB_ARB_RW6_WA_MSB\r
-USBFS_USB__ARB_RW7_DR EQU CYREG_USB_ARB_RW7_DR\r
-USBFS_USB__ARB_RW7_RA EQU CYREG_USB_ARB_RW7_RA\r
-USBFS_USB__ARB_RW7_RA_MSB EQU CYREG_USB_ARB_RW7_RA_MSB\r
-USBFS_USB__ARB_RW7_WA EQU CYREG_USB_ARB_RW7_WA\r
-USBFS_USB__ARB_RW7_WA_MSB EQU CYREG_USB_ARB_RW7_WA_MSB\r
-USBFS_USB__ARB_RW8_DR EQU CYREG_USB_ARB_RW8_DR\r
-USBFS_USB__ARB_RW8_RA EQU CYREG_USB_ARB_RW8_RA\r
-USBFS_USB__ARB_RW8_RA_MSB EQU CYREG_USB_ARB_RW8_RA_MSB\r
-USBFS_USB__ARB_RW8_WA EQU CYREG_USB_ARB_RW8_WA\r
-USBFS_USB__ARB_RW8_WA_MSB EQU CYREG_USB_ARB_RW8_WA_MSB\r
-USBFS_USB__BUF_SIZE EQU CYREG_USB_BUF_SIZE\r
-USBFS_USB__BUS_RST_CNT EQU CYREG_USB_BUS_RST_CNT\r
-USBFS_USB__CR0 EQU CYREG_USB_CR0\r
-USBFS_USB__CR1 EQU CYREG_USB_CR1\r
-USBFS_USB__CWA EQU CYREG_USB_CWA\r
-USBFS_USB__CWA_MSB EQU CYREG_USB_CWA_MSB\r
-USBFS_USB__DMA_THRES EQU CYREG_USB_DMA_THRES\r
-USBFS_USB__DMA_THRES_MSB EQU CYREG_USB_DMA_THRES_MSB\r
-USBFS_USB__DYN_RECONFIG EQU CYREG_USB_DYN_RECONFIG\r
-USBFS_USB__EP_ACTIVE EQU CYREG_USB_EP_ACTIVE\r
-USBFS_USB__EP_TYPE EQU CYREG_USB_EP_TYPE\r
-USBFS_USB__EP0_CNT EQU CYREG_USB_EP0_CNT\r
-USBFS_USB__EP0_CR EQU CYREG_USB_EP0_CR\r
-USBFS_USB__EP0_DR0 EQU CYREG_USB_EP0_DR0\r
-USBFS_USB__EP0_DR1 EQU CYREG_USB_EP0_DR1\r
-USBFS_USB__EP0_DR2 EQU CYREG_USB_EP0_DR2\r
-USBFS_USB__EP0_DR3 EQU CYREG_USB_EP0_DR3\r
-USBFS_USB__EP0_DR4 EQU CYREG_USB_EP0_DR4\r
-USBFS_USB__EP0_DR5 EQU CYREG_USB_EP0_DR5\r
-USBFS_USB__EP0_DR6 EQU CYREG_USB_EP0_DR6\r
-USBFS_USB__EP0_DR7 EQU CYREG_USB_EP0_DR7\r
-USBFS_USB__MEM_DATA EQU CYREG_USB_MEM_DATA_MBASE\r
-USBFS_USB__PM_ACT_CFG EQU CYREG_PM_ACT_CFG5\r
-USBFS_USB__PM_ACT_MSK EQU 0x01\r
-USBFS_USB__PM_STBY_CFG EQU CYREG_PM_STBY_CFG5\r
-USBFS_USB__PM_STBY_MSK EQU 0x01\r
-USBFS_USB__SIE_EP_INT_EN EQU CYREG_USB_SIE_EP_INT_EN\r
-USBFS_USB__SIE_EP_INT_SR EQU CYREG_USB_SIE_EP_INT_SR\r
-USBFS_USB__SIE_EP1_CNT0 EQU CYREG_USB_SIE_EP1_CNT0\r
-USBFS_USB__SIE_EP1_CNT1 EQU CYREG_USB_SIE_EP1_CNT1\r
-USBFS_USB__SIE_EP1_CR0 EQU CYREG_USB_SIE_EP1_CR0\r
-USBFS_USB__SIE_EP2_CNT0 EQU CYREG_USB_SIE_EP2_CNT0\r
-USBFS_USB__SIE_EP2_CNT1 EQU CYREG_USB_SIE_EP2_CNT1\r
-USBFS_USB__SIE_EP2_CR0 EQU CYREG_USB_SIE_EP2_CR0\r
-USBFS_USB__SIE_EP3_CNT0 EQU CYREG_USB_SIE_EP3_CNT0\r
-USBFS_USB__SIE_EP3_CNT1 EQU CYREG_USB_SIE_EP3_CNT1\r
-USBFS_USB__SIE_EP3_CR0 EQU CYREG_USB_SIE_EP3_CR0\r
-USBFS_USB__SIE_EP4_CNT0 EQU CYREG_USB_SIE_EP4_CNT0\r
-USBFS_USB__SIE_EP4_CNT1 EQU CYREG_USB_SIE_EP4_CNT1\r
-USBFS_USB__SIE_EP4_CR0 EQU CYREG_USB_SIE_EP4_CR0\r
-USBFS_USB__SIE_EP5_CNT0 EQU CYREG_USB_SIE_EP5_CNT0\r
-USBFS_USB__SIE_EP5_CNT1 EQU CYREG_USB_SIE_EP5_CNT1\r
-USBFS_USB__SIE_EP5_CR0 EQU CYREG_USB_SIE_EP5_CR0\r
-USBFS_USB__SIE_EP6_CNT0 EQU CYREG_USB_SIE_EP6_CNT0\r
-USBFS_USB__SIE_EP6_CNT1 EQU CYREG_USB_SIE_EP6_CNT1\r
-USBFS_USB__SIE_EP6_CR0 EQU CYREG_USB_SIE_EP6_CR0\r
-USBFS_USB__SIE_EP7_CNT0 EQU CYREG_USB_SIE_EP7_CNT0\r
-USBFS_USB__SIE_EP7_CNT1 EQU CYREG_USB_SIE_EP7_CNT1\r
-USBFS_USB__SIE_EP7_CR0 EQU CYREG_USB_SIE_EP7_CR0\r
-USBFS_USB__SIE_EP8_CNT0 EQU CYREG_USB_SIE_EP8_CNT0\r
-USBFS_USB__SIE_EP8_CNT1 EQU CYREG_USB_SIE_EP8_CNT1\r
-USBFS_USB__SIE_EP8_CR0 EQU CYREG_USB_SIE_EP8_CR0\r
-USBFS_USB__SOF0 EQU CYREG_USB_SOF0\r
-USBFS_USB__SOF1 EQU CYREG_USB_SOF1\r
-USBFS_USB__USB_CLK_EN EQU CYREG_USB_USB_CLK_EN\r
-USBFS_USB__USBIO_CR0 EQU CYREG_USB_USBIO_CR0\r
-USBFS_USB__USBIO_CR1 EQU CYREG_USB_USBIO_CR1\r
-\r
-; EXTLED\r
-EXTLED__0__INTTYPE EQU CYREG_PICU0_INTTYPE0\r
-EXTLED__0__MASK EQU 0x01\r
-EXTLED__0__PC EQU CYREG_PRT0_PC0\r
-EXTLED__0__PORT EQU 0\r
-EXTLED__0__SHIFT EQU 0\r
-EXTLED__AG EQU CYREG_PRT0_AG\r
-EXTLED__AMUX EQU CYREG_PRT0_AMUX\r
-EXTLED__BIE EQU CYREG_PRT0_BIE\r
-EXTLED__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
-EXTLED__BYP EQU CYREG_PRT0_BYP\r
-EXTLED__CTL EQU CYREG_PRT0_CTL\r
-EXTLED__DM0 EQU CYREG_PRT0_DM0\r
-EXTLED__DM1 EQU CYREG_PRT0_DM1\r
-EXTLED__DM2 EQU CYREG_PRT0_DM2\r
-EXTLED__DR EQU CYREG_PRT0_DR\r
-EXTLED__INP_DIS EQU CYREG_PRT0_INP_DIS\r
-EXTLED__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU0_BASE\r
-EXTLED__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
-EXTLED__LCD_EN EQU CYREG_PRT0_LCD_EN\r
-EXTLED__MASK EQU 0x01\r
-EXTLED__PORT EQU 0\r
-EXTLED__PRT EQU CYREG_PRT0_PRT\r
-EXTLED__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
-EXTLED__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
-EXTLED__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
-EXTLED__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
-EXTLED__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
-EXTLED__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
-EXTLED__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
-EXTLED__PS EQU CYREG_PRT0_PS\r
-EXTLED__SHIFT EQU 0\r
-EXTLED__SLW EQU CYREG_PRT0_SLW\r
-\r
-; SDCard_BSPIM\r
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB05_06_ACTL\r
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB05_06_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB05_06_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB05_06_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB05_06_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB05_06_MSK\r
-SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB05_06_MSK\r
-SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB05_06_MSK\r
-SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB05_06_MSK\r
-SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB05_ACTL\r
-SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB05_CTL\r
-SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB05_ST_CTL\r
-SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB05_CTL\r
-SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB05_ST_CTL\r
-SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL\r
-SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL\r
-SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB05_MSK\r
-SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB05_06_ACTL\r
-SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB05_06_ST\r
-SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB05_MSK\r
-SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL\r
-SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB05_ACTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB05_ST_CTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB05_ST_CTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB05_ST\r
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL\r
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST\r
-SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10\r
-SDCard_BSPIM_RxStsReg__4__POS EQU 4\r
-SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20\r
-SDCard_BSPIM_RxStsReg__5__POS EQU 5\r
-SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40\r
-SDCard_BSPIM_RxStsReg__6__POS EQU 6\r
-SDCard_BSPIM_RxStsReg__MASK EQU 0x70\r
-SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB07_MSK\r
-SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL\r
-SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB07_ST\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB04_05_A0\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB04_05_A1\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B1_UDB04_05_D0\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B1_UDB04_05_D1\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B1_UDB04_05_F0\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B1_UDB04_05_F1\r
-SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B1_UDB04_A0_A1\r
-SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B1_UDB04_A0\r
-SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B1_UDB04_A1\r
-SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B1_UDB04_D0_D1\r
-SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B1_UDB04_D0\r
-SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B1_UDB04_D1\r
-SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL\r
-SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B1_UDB04_F0_F1\r
-SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B1_UDB04_F0\r
-SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B1_UDB04_F1\r
-SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01\r
-SDCard_BSPIM_TxStsReg__0__POS EQU 0\r
-SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02\r
-SDCard_BSPIM_TxStsReg__1__POS EQU 1\r
-SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL\r
-SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB06_07_ST\r
-SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04\r
-SDCard_BSPIM_TxStsReg__2__POS EQU 2\r
-SDCard_BSPIM_TxStsReg__3__MASK EQU 0x08\r
-SDCard_BSPIM_TxStsReg__3__POS EQU 3\r
-SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10\r
-SDCard_BSPIM_TxStsReg__4__POS EQU 4\r
-SDCard_BSPIM_TxStsReg__MASK EQU 0x1F\r
-SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB06_MSK\r
-SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL\r
-SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB06_ST\r
-\r
-; SD_SCK\r
-SD_SCK__0__INTTYPE EQU CYREG_PICU3_INTTYPE2\r
-SD_SCK__0__MASK EQU 0x04\r
-SD_SCK__0__PC EQU CYREG_PRT3_PC2\r
-SD_SCK__0__PORT EQU 3\r
-SD_SCK__0__SHIFT EQU 2\r
-SD_SCK__AG EQU CYREG_PRT3_AG\r
-SD_SCK__AMUX EQU CYREG_PRT3_AMUX\r
-SD_SCK__BIE EQU CYREG_PRT3_BIE\r
-SD_SCK__BIT_MASK EQU CYREG_PRT3_BIT_MASK\r
-SD_SCK__BYP EQU CYREG_PRT3_BYP\r
-SD_SCK__CTL EQU CYREG_PRT3_CTL\r
-SD_SCK__DM0 EQU CYREG_PRT3_DM0\r
-SD_SCK__DM1 EQU CYREG_PRT3_DM1\r
-SD_SCK__DM2 EQU CYREG_PRT3_DM2\r
-SD_SCK__DR EQU CYREG_PRT3_DR\r
-SD_SCK__INP_DIS EQU CYREG_PRT3_INP_DIS\r
-SD_SCK__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE\r
-SD_SCK__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG\r
-SD_SCK__LCD_EN EQU CYREG_PRT3_LCD_EN\r
-SD_SCK__MASK EQU 0x04\r
-SD_SCK__PORT EQU 3\r
-SD_SCK__PRT EQU CYREG_PRT3_PRT\r
-SD_SCK__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL\r
-SD_SCK__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN\r
-SD_SCK__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0\r
-SD_SCK__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1\r
-SD_SCK__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0\r
-SD_SCK__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1\r
-SD_SCK__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT\r
-SD_SCK__PS EQU CYREG_PRT3_PS\r
-SD_SCK__SHIFT EQU 2\r
-SD_SCK__SLW EQU CYREG_PRT3_SLW\r
-\r
-; SCSI_In\r
-SCSI_In__0__AG EQU CYREG_PRT2_AG\r
-SCSI_In__0__AMUX EQU CYREG_PRT2_AMUX\r
-SCSI_In__0__BIE EQU CYREG_PRT2_BIE\r
-SCSI_In__0__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
-SCSI_In__0__BYP EQU CYREG_PRT2_BYP\r
-SCSI_In__0__CTL EQU CYREG_PRT2_CTL\r
-SCSI_In__0__DM0 EQU CYREG_PRT2_DM0\r
-SCSI_In__0__DM1 EQU CYREG_PRT2_DM1\r
-SCSI_In__0__DM2 EQU CYREG_PRT2_DM2\r
-SCSI_In__0__DR EQU CYREG_PRT2_DR\r
-SCSI_In__0__INP_DIS EQU CYREG_PRT2_INP_DIS\r
-SCSI_In__0__INTTYPE EQU CYREG_PICU2_INTTYPE1\r
-SCSI_In__0__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
-SCSI_In__0__LCD_EN EQU CYREG_PRT2_LCD_EN\r
-SCSI_In__0__MASK EQU 0x02\r
-SCSI_In__0__PC EQU CYREG_PRT2_PC1\r
-SCSI_In__0__PORT EQU 2\r
-SCSI_In__0__PRT EQU CYREG_PRT2_PRT\r
-SCSI_In__0__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
-SCSI_In__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
-SCSI_In__0__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
-SCSI_In__0__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
-SCSI_In__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
-SCSI_In__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
-SCSI_In__0__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
-SCSI_In__0__PS EQU CYREG_PRT2_PS\r
-SCSI_In__0__SHIFT EQU 1\r
-SCSI_In__0__SLW EQU CYREG_PRT2_SLW\r
-SCSI_In__1__AG EQU CYREG_PRT4_AG\r
-SCSI_In__1__AMUX EQU CYREG_PRT4_AMUX\r
-SCSI_In__1__BIE EQU CYREG_PRT4_BIE\r
-SCSI_In__1__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
-SCSI_In__1__BYP EQU CYREG_PRT4_BYP\r
-SCSI_In__1__CTL EQU CYREG_PRT4_CTL\r
-SCSI_In__1__DM0 EQU CYREG_PRT4_DM0\r
-SCSI_In__1__DM1 EQU CYREG_PRT4_DM1\r
-SCSI_In__1__DM2 EQU CYREG_PRT4_DM2\r
-SCSI_In__1__DR EQU CYREG_PRT4_DR\r
-SCSI_In__1__INP_DIS EQU CYREG_PRT4_INP_DIS\r
-SCSI_In__1__INTTYPE EQU CYREG_PICU4_INTTYPE6\r
-SCSI_In__1__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
-SCSI_In__1__LCD_EN EQU CYREG_PRT4_LCD_EN\r
-SCSI_In__1__MASK EQU 0x40\r
-SCSI_In__1__PC EQU CYREG_PRT4_PC6\r
-SCSI_In__1__PORT EQU 4\r
-SCSI_In__1__PRT EQU CYREG_PRT4_PRT\r
-SCSI_In__1__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
-SCSI_In__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
-SCSI_In__1__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
-SCSI_In__1__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
-SCSI_In__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
-SCSI_In__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
-SCSI_In__1__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
-SCSI_In__1__PS EQU CYREG_PRT4_PS\r
-SCSI_In__1__SHIFT EQU 6\r
-SCSI_In__1__SLW EQU CYREG_PRT4_SLW\r
-SCSI_In__2__AG EQU CYREG_PRT4_AG\r
-SCSI_In__2__AMUX EQU CYREG_PRT4_AMUX\r
-SCSI_In__2__BIE EQU CYREG_PRT4_BIE\r
-SCSI_In__2__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
-SCSI_In__2__BYP EQU CYREG_PRT4_BYP\r
-SCSI_In__2__CTL EQU CYREG_PRT4_CTL\r
-SCSI_In__2__DM0 EQU CYREG_PRT4_DM0\r
-SCSI_In__2__DM1 EQU CYREG_PRT4_DM1\r
-SCSI_In__2__DM2 EQU CYREG_PRT4_DM2\r
-SCSI_In__2__DR EQU CYREG_PRT4_DR\r
-SCSI_In__2__INP_DIS EQU CYREG_PRT4_INP_DIS\r
-SCSI_In__2__INTTYPE EQU CYREG_PICU4_INTTYPE2\r
-SCSI_In__2__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
-SCSI_In__2__LCD_EN EQU CYREG_PRT4_LCD_EN\r
-SCSI_In__2__MASK EQU 0x04\r
-SCSI_In__2__PC EQU CYREG_PRT4_PC2\r
-SCSI_In__2__PORT EQU 4\r
-SCSI_In__2__PRT EQU CYREG_PRT4_PRT\r
-SCSI_In__2__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
-SCSI_In__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
-SCSI_In__2__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
-SCSI_In__2__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
-SCSI_In__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
-SCSI_In__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
-SCSI_In__2__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
-SCSI_In__2__PS EQU CYREG_PRT4_PS\r
-SCSI_In__2__SHIFT EQU 2\r
-SCSI_In__2__SLW EQU CYREG_PRT4_SLW\r
-SCSI_In__3__AG EQU CYREG_PRT0_AG\r
-SCSI_In__3__AMUX EQU CYREG_PRT0_AMUX\r
-SCSI_In__3__BIE EQU CYREG_PRT0_BIE\r
-SCSI_In__3__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
-SCSI_In__3__BYP EQU CYREG_PRT0_BYP\r
-SCSI_In__3__CTL EQU CYREG_PRT0_CTL\r
-SCSI_In__3__DM0 EQU CYREG_PRT0_DM0\r
-SCSI_In__3__DM1 EQU CYREG_PRT0_DM1\r
-SCSI_In__3__DM2 EQU CYREG_PRT0_DM2\r
-SCSI_In__3__DR EQU CYREG_PRT0_DR\r
-SCSI_In__3__INP_DIS EQU CYREG_PRT0_INP_DIS\r
-SCSI_In__3__INTTYPE EQU CYREG_PICU0_INTTYPE5\r
-SCSI_In__3__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
-SCSI_In__3__LCD_EN EQU CYREG_PRT0_LCD_EN\r
-SCSI_In__3__MASK EQU 0x20\r
-SCSI_In__3__PC EQU CYREG_PRT0_PC5\r
-SCSI_In__3__PORT EQU 0\r
-SCSI_In__3__PRT EQU CYREG_PRT0_PRT\r
-SCSI_In__3__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
-SCSI_In__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
-SCSI_In__3__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
-SCSI_In__3__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
-SCSI_In__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
-SCSI_In__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
-SCSI_In__3__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
-SCSI_In__3__PS EQU CYREG_PRT0_PS\r
-SCSI_In__3__SHIFT EQU 5\r
-SCSI_In__3__SLW EQU CYREG_PRT0_SLW\r
-SCSI_In__4__AG EQU CYREG_PRT0_AG\r
-SCSI_In__4__AMUX EQU CYREG_PRT0_AMUX\r
-SCSI_In__4__BIE EQU CYREG_PRT0_BIE\r
-SCSI_In__4__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
-SCSI_In__4__BYP EQU CYREG_PRT0_BYP\r
-SCSI_In__4__CTL EQU CYREG_PRT0_CTL\r
-SCSI_In__4__DM0 EQU CYREG_PRT0_DM0\r
-SCSI_In__4__DM1 EQU CYREG_PRT0_DM1\r
-SCSI_In__4__DM2 EQU CYREG_PRT0_DM2\r
-SCSI_In__4__DR EQU CYREG_PRT0_DR\r
-SCSI_In__4__INP_DIS EQU CYREG_PRT0_INP_DIS\r
-SCSI_In__4__INTTYPE EQU CYREG_PICU0_INTTYPE4\r
-SCSI_In__4__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
-SCSI_In__4__LCD_EN EQU CYREG_PRT0_LCD_EN\r
-SCSI_In__4__MASK EQU 0x10\r
-SCSI_In__4__PC EQU CYREG_PRT0_PC4\r
-SCSI_In__4__PORT EQU 0\r
-SCSI_In__4__PRT EQU CYREG_PRT0_PRT\r
-SCSI_In__4__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
-SCSI_In__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
-SCSI_In__4__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
-SCSI_In__4__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
-SCSI_In__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
-SCSI_In__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
-SCSI_In__4__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
-SCSI_In__4__PS EQU CYREG_PRT0_PS\r
-SCSI_In__4__SHIFT EQU 4\r
-SCSI_In__4__SLW EQU CYREG_PRT0_SLW\r
-SCSI_In__CD__AG EQU CYREG_PRT4_AG\r
-SCSI_In__CD__AMUX EQU CYREG_PRT4_AMUX\r
-SCSI_In__CD__BIE EQU CYREG_PRT4_BIE\r
-SCSI_In__CD__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
-SCSI_In__CD__BYP EQU CYREG_PRT4_BYP\r
-SCSI_In__CD__CTL EQU CYREG_PRT4_CTL\r
-SCSI_In__CD__DM0 EQU CYREG_PRT4_DM0\r
-SCSI_In__CD__DM1 EQU CYREG_PRT4_DM1\r
-SCSI_In__CD__DM2 EQU CYREG_PRT4_DM2\r
-SCSI_In__CD__DR EQU CYREG_PRT4_DR\r
-SCSI_In__CD__INP_DIS EQU CYREG_PRT4_INP_DIS\r
-SCSI_In__CD__INTTYPE EQU CYREG_PICU4_INTTYPE2\r
-SCSI_In__CD__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
-SCSI_In__CD__LCD_EN EQU CYREG_PRT4_LCD_EN\r
-SCSI_In__CD__MASK EQU 0x04\r
-SCSI_In__CD__PC EQU CYREG_PRT4_PC2\r
-SCSI_In__CD__PORT EQU 4\r
-SCSI_In__CD__PRT EQU CYREG_PRT4_PRT\r
-SCSI_In__CD__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
-SCSI_In__CD__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
-SCSI_In__CD__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
-SCSI_In__CD__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
-SCSI_In__CD__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
-SCSI_In__CD__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
-SCSI_In__CD__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
-SCSI_In__CD__PS EQU CYREG_PRT4_PS\r
-SCSI_In__CD__SHIFT EQU 2\r
-SCSI_In__CD__SLW EQU CYREG_PRT4_SLW\r
-SCSI_In__DBP__AG EQU CYREG_PRT2_AG\r
-SCSI_In__DBP__AMUX EQU CYREG_PRT2_AMUX\r
-SCSI_In__DBP__BIE EQU CYREG_PRT2_BIE\r
-SCSI_In__DBP__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
-SCSI_In__DBP__BYP EQU CYREG_PRT2_BYP\r
-SCSI_In__DBP__CTL EQU CYREG_PRT2_CTL\r
-SCSI_In__DBP__DM0 EQU CYREG_PRT2_DM0\r
-SCSI_In__DBP__DM1 EQU CYREG_PRT2_DM1\r
-SCSI_In__DBP__DM2 EQU CYREG_PRT2_DM2\r
-SCSI_In__DBP__DR EQU CYREG_PRT2_DR\r
-SCSI_In__DBP__INP_DIS EQU CYREG_PRT2_INP_DIS\r
-SCSI_In__DBP__INTTYPE EQU CYREG_PICU2_INTTYPE1\r
-SCSI_In__DBP__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
-SCSI_In__DBP__LCD_EN EQU CYREG_PRT2_LCD_EN\r
-SCSI_In__DBP__MASK EQU 0x02\r
-SCSI_In__DBP__PC EQU CYREG_PRT2_PC1\r
-SCSI_In__DBP__PORT EQU 2\r
-SCSI_In__DBP__PRT EQU CYREG_PRT2_PRT\r
-SCSI_In__DBP__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
-SCSI_In__DBP__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
-SCSI_In__DBP__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
-SCSI_In__DBP__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
-SCSI_In__DBP__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
-SCSI_In__DBP__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
-SCSI_In__DBP__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
-SCSI_In__DBP__PS EQU CYREG_PRT2_PS\r
-SCSI_In__DBP__SHIFT EQU 1\r
-SCSI_In__DBP__SLW EQU CYREG_PRT2_SLW\r
-SCSI_In__IO__AG EQU CYREG_PRT0_AG\r
-SCSI_In__IO__AMUX EQU CYREG_PRT0_AMUX\r
-SCSI_In__IO__BIE EQU CYREG_PRT0_BIE\r
-SCSI_In__IO__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
-SCSI_In__IO__BYP EQU CYREG_PRT0_BYP\r
-SCSI_In__IO__CTL EQU CYREG_PRT0_CTL\r
-SCSI_In__IO__DM0 EQU CYREG_PRT0_DM0\r
-SCSI_In__IO__DM1 EQU CYREG_PRT0_DM1\r
-SCSI_In__IO__DM2 EQU CYREG_PRT0_DM2\r
-SCSI_In__IO__DR EQU CYREG_PRT0_DR\r
-SCSI_In__IO__INP_DIS EQU CYREG_PRT0_INP_DIS\r
-SCSI_In__IO__INTTYPE EQU CYREG_PICU0_INTTYPE4\r
-SCSI_In__IO__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
-SCSI_In__IO__LCD_EN EQU CYREG_PRT0_LCD_EN\r
-SCSI_In__IO__MASK EQU 0x10\r
-SCSI_In__IO__PC EQU CYREG_PRT0_PC4\r
-SCSI_In__IO__PORT EQU 0\r
-SCSI_In__IO__PRT EQU CYREG_PRT0_PRT\r
-SCSI_In__IO__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
-SCSI_In__IO__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
-SCSI_In__IO__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
-SCSI_In__IO__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
-SCSI_In__IO__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
-SCSI_In__IO__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
-SCSI_In__IO__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
-SCSI_In__IO__PS EQU CYREG_PRT0_PS\r
-SCSI_In__IO__SHIFT EQU 4\r
-SCSI_In__IO__SLW EQU CYREG_PRT0_SLW\r
-SCSI_In__MSG__AG EQU CYREG_PRT4_AG\r
-SCSI_In__MSG__AMUX EQU CYREG_PRT4_AMUX\r
-SCSI_In__MSG__BIE EQU CYREG_PRT4_BIE\r
-SCSI_In__MSG__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
-SCSI_In__MSG__BYP EQU CYREG_PRT4_BYP\r
-SCSI_In__MSG__CTL EQU CYREG_PRT4_CTL\r
-SCSI_In__MSG__DM0 EQU CYREG_PRT4_DM0\r
-SCSI_In__MSG__DM1 EQU CYREG_PRT4_DM1\r
-SCSI_In__MSG__DM2 EQU CYREG_PRT4_DM2\r
-SCSI_In__MSG__DR EQU CYREG_PRT4_DR\r
-SCSI_In__MSG__INP_DIS EQU CYREG_PRT4_INP_DIS\r
-SCSI_In__MSG__INTTYPE EQU CYREG_PICU4_INTTYPE6\r
-SCSI_In__MSG__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
-SCSI_In__MSG__LCD_EN EQU CYREG_PRT4_LCD_EN\r
-SCSI_In__MSG__MASK EQU 0x40\r
-SCSI_In__MSG__PC EQU CYREG_PRT4_PC6\r
-SCSI_In__MSG__PORT EQU 4\r
-SCSI_In__MSG__PRT EQU CYREG_PRT4_PRT\r
-SCSI_In__MSG__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
-SCSI_In__MSG__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
-SCSI_In__MSG__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
-SCSI_In__MSG__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
-SCSI_In__MSG__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
-SCSI_In__MSG__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
-SCSI_In__MSG__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
-SCSI_In__MSG__PS EQU CYREG_PRT4_PS\r
-SCSI_In__MSG__SHIFT EQU 6\r
-SCSI_In__MSG__SLW EQU CYREG_PRT4_SLW\r
-SCSI_In__REQ__AG EQU CYREG_PRT0_AG\r
-SCSI_In__REQ__AMUX EQU CYREG_PRT0_AMUX\r
-SCSI_In__REQ__BIE EQU CYREG_PRT0_BIE\r
-SCSI_In__REQ__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
-SCSI_In__REQ__BYP EQU CYREG_PRT0_BYP\r
-SCSI_In__REQ__CTL EQU CYREG_PRT0_CTL\r
-SCSI_In__REQ__DM0 EQU CYREG_PRT0_DM0\r
-SCSI_In__REQ__DM1 EQU CYREG_PRT0_DM1\r
-SCSI_In__REQ__DM2 EQU CYREG_PRT0_DM2\r
-SCSI_In__REQ__DR EQU CYREG_PRT0_DR\r
-SCSI_In__REQ__INP_DIS EQU CYREG_PRT0_INP_DIS\r
-SCSI_In__REQ__INTTYPE EQU CYREG_PICU0_INTTYPE5\r
-SCSI_In__REQ__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
-SCSI_In__REQ__LCD_EN EQU CYREG_PRT0_LCD_EN\r
-SCSI_In__REQ__MASK EQU 0x20\r
-SCSI_In__REQ__PC EQU CYREG_PRT0_PC5\r
-SCSI_In__REQ__PORT EQU 0\r
-SCSI_In__REQ__PRT EQU CYREG_PRT0_PRT\r
-SCSI_In__REQ__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
-SCSI_In__REQ__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
-SCSI_In__REQ__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
-SCSI_In__REQ__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
-SCSI_In__REQ__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
-SCSI_In__REQ__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
-SCSI_In__REQ__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
-SCSI_In__REQ__PS EQU CYREG_PRT0_PS\r
-SCSI_In__REQ__SHIFT EQU 5\r
-SCSI_In__REQ__SLW EQU CYREG_PRT0_SLW\r
-\r
-; SCSI_In_DBx\r
-SCSI_In_DBx__0__AG EQU CYREG_PRT5_AG\r
-SCSI_In_DBx__0__AMUX EQU CYREG_PRT5_AMUX\r
-SCSI_In_DBx__0__BIE EQU CYREG_PRT5_BIE\r
-SCSI_In_DBx__0__BIT_MASK EQU CYREG_PRT5_BIT_MASK\r
-SCSI_In_DBx__0__BYP EQU CYREG_PRT5_BYP\r
-SCSI_In_DBx__0__CTL EQU CYREG_PRT5_CTL\r
-SCSI_In_DBx__0__DM0 EQU CYREG_PRT5_DM0\r
-SCSI_In_DBx__0__DM1 EQU CYREG_PRT5_DM1\r
-SCSI_In_DBx__0__DM2 EQU CYREG_PRT5_DM2\r
-SCSI_In_DBx__0__DR EQU CYREG_PRT5_DR\r
-SCSI_In_DBx__0__INP_DIS EQU CYREG_PRT5_INP_DIS\r
-SCSI_In_DBx__0__INTTYPE EQU CYREG_PICU5_INTTYPE3\r
-SCSI_In_DBx__0__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG\r
-SCSI_In_DBx__0__LCD_EN EQU CYREG_PRT5_LCD_EN\r
-SCSI_In_DBx__0__MASK EQU 0x08\r
-SCSI_In_DBx__0__PC EQU CYREG_PRT5_PC3\r
-SCSI_In_DBx__0__PORT EQU 5\r
-SCSI_In_DBx__0__PRT EQU CYREG_PRT5_PRT\r
-SCSI_In_DBx__0__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL\r
-SCSI_In_DBx__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN\r
-SCSI_In_DBx__0__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0\r
-SCSI_In_DBx__0__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1\r
-SCSI_In_DBx__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0\r
-SCSI_In_DBx__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1\r
-SCSI_In_DBx__0__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT\r
-SCSI_In_DBx__0__PS EQU CYREG_PRT5_PS\r
-SCSI_In_DBx__0__SHIFT EQU 3\r
-SCSI_In_DBx__0__SLW EQU CYREG_PRT5_SLW\r
-SCSI_In_DBx__1__AG EQU CYREG_PRT5_AG\r
-SCSI_In_DBx__1__AMUX EQU CYREG_PRT5_AMUX\r
-SCSI_In_DBx__1__BIE EQU CYREG_PRT5_BIE\r
-SCSI_In_DBx__1__BIT_MASK EQU CYREG_PRT5_BIT_MASK\r
-SCSI_In_DBx__1__BYP EQU CYREG_PRT5_BYP\r
-SCSI_In_DBx__1__CTL EQU CYREG_PRT5_CTL\r
-SCSI_In_DBx__1__DM0 EQU CYREG_PRT5_DM0\r
-SCSI_In_DBx__1__DM1 EQU CYREG_PRT5_DM1\r
-SCSI_In_DBx__1__DM2 EQU CYREG_PRT5_DM2\r
-SCSI_In_DBx__1__DR EQU CYREG_PRT5_DR\r
-SCSI_In_DBx__1__INP_DIS EQU CYREG_PRT5_INP_DIS\r
-SCSI_In_DBx__1__INTTYPE EQU CYREG_PICU5_INTTYPE2\r
-SCSI_In_DBx__1__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG\r
-SCSI_In_DBx__1__LCD_EN EQU CYREG_PRT5_LCD_EN\r
-SCSI_In_DBx__1__MASK EQU 0x04\r
-SCSI_In_DBx__1__PC EQU CYREG_PRT5_PC2\r
-SCSI_In_DBx__1__PORT EQU 5\r
-SCSI_In_DBx__1__PRT EQU CYREG_PRT5_PRT\r
-SCSI_In_DBx__1__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL\r
-SCSI_In_DBx__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN\r
-SCSI_In_DBx__1__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0\r
-SCSI_In_DBx__1__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1\r
-SCSI_In_DBx__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0\r
-SCSI_In_DBx__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1\r
-SCSI_In_DBx__1__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT\r
-SCSI_In_DBx__1__PS EQU CYREG_PRT5_PS\r
-SCSI_In_DBx__1__SHIFT EQU 2\r
-SCSI_In_DBx__1__SLW EQU CYREG_PRT5_SLW\r
-SCSI_In_DBx__2__AG EQU CYREG_PRT6_AG\r
-SCSI_In_DBx__2__AMUX EQU CYREG_PRT6_AMUX\r
-SCSI_In_DBx__2__BIE EQU CYREG_PRT6_BIE\r
-SCSI_In_DBx__2__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
-SCSI_In_DBx__2__BYP EQU CYREG_PRT6_BYP\r
-SCSI_In_DBx__2__CTL EQU CYREG_PRT6_CTL\r
-SCSI_In_DBx__2__DM0 EQU CYREG_PRT6_DM0\r
-SCSI_In_DBx__2__DM1 EQU CYREG_PRT6_DM1\r
-SCSI_In_DBx__2__DM2 EQU CYREG_PRT6_DM2\r
-SCSI_In_DBx__2__DR EQU CYREG_PRT6_DR\r
-SCSI_In_DBx__2__INP_DIS EQU CYREG_PRT6_INP_DIS\r
-SCSI_In_DBx__2__INTTYPE EQU CYREG_PICU6_INTTYPE7\r
-SCSI_In_DBx__2__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
-SCSI_In_DBx__2__LCD_EN EQU CYREG_PRT6_LCD_EN\r
-SCSI_In_DBx__2__MASK EQU 0x80\r
-SCSI_In_DBx__2__PC EQU CYREG_PRT6_PC7\r
-SCSI_In_DBx__2__PORT EQU 6\r
-SCSI_In_DBx__2__PRT EQU CYREG_PRT6_PRT\r
-SCSI_In_DBx__2__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
-SCSI_In_DBx__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
-SCSI_In_DBx__2__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
-SCSI_In_DBx__2__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
-SCSI_In_DBx__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
-SCSI_In_DBx__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
-SCSI_In_DBx__2__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
-SCSI_In_DBx__2__PS EQU CYREG_PRT6_PS\r
-SCSI_In_DBx__2__SHIFT EQU 7\r
-SCSI_In_DBx__2__SLW EQU CYREG_PRT6_SLW\r
-SCSI_In_DBx__3__AG EQU CYREG_PRT6_AG\r
-SCSI_In_DBx__3__AMUX EQU CYREG_PRT6_AMUX\r
-SCSI_In_DBx__3__BIE EQU CYREG_PRT6_BIE\r
-SCSI_In_DBx__3__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
-SCSI_In_DBx__3__BYP EQU CYREG_PRT6_BYP\r
-SCSI_In_DBx__3__CTL EQU CYREG_PRT6_CTL\r
-SCSI_In_DBx__3__DM0 EQU CYREG_PRT6_DM0\r
-SCSI_In_DBx__3__DM1 EQU CYREG_PRT6_DM1\r
-SCSI_In_DBx__3__DM2 EQU CYREG_PRT6_DM2\r
-SCSI_In_DBx__3__DR EQU CYREG_PRT6_DR\r
-SCSI_In_DBx__3__INP_DIS EQU CYREG_PRT6_INP_DIS\r
-SCSI_In_DBx__3__INTTYPE EQU CYREG_PICU6_INTTYPE6\r
-SCSI_In_DBx__3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
-SCSI_In_DBx__3__LCD_EN EQU CYREG_PRT6_LCD_EN\r
-SCSI_In_DBx__3__MASK EQU 0x40\r
-SCSI_In_DBx__3__PC EQU CYREG_PRT6_PC6\r
-SCSI_In_DBx__3__PORT EQU 6\r
-SCSI_In_DBx__3__PRT EQU CYREG_PRT6_PRT\r
-SCSI_In_DBx__3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
-SCSI_In_DBx__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
-SCSI_In_DBx__3__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
-SCSI_In_DBx__3__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
-SCSI_In_DBx__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
-SCSI_In_DBx__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
-SCSI_In_DBx__3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
-SCSI_In_DBx__3__PS EQU CYREG_PRT6_PS\r
-SCSI_In_DBx__3__SHIFT EQU 6\r
-SCSI_In_DBx__3__SLW EQU CYREG_PRT6_SLW\r
-SCSI_In_DBx__4__AG EQU CYREG_PRT12_AG\r
-SCSI_In_DBx__4__BIE EQU CYREG_PRT12_BIE\r
-SCSI_In_DBx__4__BIT_MASK EQU CYREG_PRT12_BIT_MASK\r
-SCSI_In_DBx__4__BYP EQU CYREG_PRT12_BYP\r
-SCSI_In_DBx__4__DM0 EQU CYREG_PRT12_DM0\r
-SCSI_In_DBx__4__DM1 EQU CYREG_PRT12_DM1\r
-SCSI_In_DBx__4__DM2 EQU CYREG_PRT12_DM2\r
-SCSI_In_DBx__4__DR EQU CYREG_PRT12_DR\r
-SCSI_In_DBx__4__INP_DIS EQU CYREG_PRT12_INP_DIS\r
-SCSI_In_DBx__4__INTTYPE EQU CYREG_PICU12_INTTYPE5\r
-SCSI_In_DBx__4__MASK EQU 0x20\r
-SCSI_In_DBx__4__PC EQU CYREG_PRT12_PC5\r
-SCSI_In_DBx__4__PORT EQU 12\r
-SCSI_In_DBx__4__PRT EQU CYREG_PRT12_PRT\r
-SCSI_In_DBx__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN\r
-SCSI_In_DBx__4__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0\r
-SCSI_In_DBx__4__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1\r
-SCSI_In_DBx__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0\r
-SCSI_In_DBx__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1\r
-SCSI_In_DBx__4__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT\r
-SCSI_In_DBx__4__PS EQU CYREG_PRT12_PS\r
-SCSI_In_DBx__4__SHIFT EQU 5\r
-SCSI_In_DBx__4__SIO_CFG EQU CYREG_PRT12_SIO_CFG\r
-SCSI_In_DBx__4__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF\r
-SCSI_In_DBx__4__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN\r
-SCSI_In_DBx__4__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ\r
-SCSI_In_DBx__4__SLW EQU CYREG_PRT12_SLW\r
-SCSI_In_DBx__5__AG EQU CYREG_PRT12_AG\r
-SCSI_In_DBx__5__BIE EQU CYREG_PRT12_BIE\r
-SCSI_In_DBx__5__BIT_MASK EQU CYREG_PRT12_BIT_MASK\r
-SCSI_In_DBx__5__BYP EQU CYREG_PRT12_BYP\r
-SCSI_In_DBx__5__DM0 EQU CYREG_PRT12_DM0\r
-SCSI_In_DBx__5__DM1 EQU CYREG_PRT12_DM1\r
-SCSI_In_DBx__5__DM2 EQU CYREG_PRT12_DM2\r
-SCSI_In_DBx__5__DR EQU CYREG_PRT12_DR\r
-SCSI_In_DBx__5__INP_DIS EQU CYREG_PRT12_INP_DIS\r
-SCSI_In_DBx__5__INTTYPE EQU CYREG_PICU12_INTTYPE4\r
-SCSI_In_DBx__5__MASK EQU 0x10\r
-SCSI_In_DBx__5__PC EQU CYREG_PRT12_PC4\r
-SCSI_In_DBx__5__PORT EQU 12\r
-SCSI_In_DBx__5__PRT EQU CYREG_PRT12_PRT\r
-SCSI_In_DBx__5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN\r
-SCSI_In_DBx__5__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0\r
-SCSI_In_DBx__5__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1\r
-SCSI_In_DBx__5__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0\r
-SCSI_In_DBx__5__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1\r
-SCSI_In_DBx__5__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT\r
-SCSI_In_DBx__5__PS EQU CYREG_PRT12_PS\r
-SCSI_In_DBx__5__SHIFT EQU 4\r
-SCSI_In_DBx__5__SIO_CFG EQU CYREG_PRT12_SIO_CFG\r
-SCSI_In_DBx__5__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF\r
-SCSI_In_DBx__5__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN\r
-SCSI_In_DBx__5__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ\r
-SCSI_In_DBx__5__SLW EQU CYREG_PRT12_SLW\r
-SCSI_In_DBx__6__AG EQU CYREG_PRT2_AG\r
-SCSI_In_DBx__6__AMUX EQU CYREG_PRT2_AMUX\r
-SCSI_In_DBx__6__BIE EQU CYREG_PRT2_BIE\r
-SCSI_In_DBx__6__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
-SCSI_In_DBx__6__BYP EQU CYREG_PRT2_BYP\r
-SCSI_In_DBx__6__CTL EQU CYREG_PRT2_CTL\r
-SCSI_In_DBx__6__DM0 EQU CYREG_PRT2_DM0\r
-SCSI_In_DBx__6__DM1 EQU CYREG_PRT2_DM1\r
-SCSI_In_DBx__6__DM2 EQU CYREG_PRT2_DM2\r
-SCSI_In_DBx__6__DR EQU CYREG_PRT2_DR\r
-SCSI_In_DBx__6__INP_DIS EQU CYREG_PRT2_INP_DIS\r
-SCSI_In_DBx__6__INTTYPE EQU CYREG_PICU2_INTTYPE5\r
-SCSI_In_DBx__6__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
-SCSI_In_DBx__6__LCD_EN EQU CYREG_PRT2_LCD_EN\r
-SCSI_In_DBx__6__MASK EQU 0x20\r
-SCSI_In_DBx__6__PC EQU CYREG_PRT2_PC5\r
-SCSI_In_DBx__6__PORT EQU 2\r
-SCSI_In_DBx__6__PRT EQU CYREG_PRT2_PRT\r
-SCSI_In_DBx__6__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
-SCSI_In_DBx__6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
-SCSI_In_DBx__6__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
-SCSI_In_DBx__6__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
-SCSI_In_DBx__6__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
-SCSI_In_DBx__6__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
-SCSI_In_DBx__6__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
-SCSI_In_DBx__6__PS EQU CYREG_PRT2_PS\r
-SCSI_In_DBx__6__SHIFT EQU 5\r
-SCSI_In_DBx__6__SLW EQU CYREG_PRT2_SLW\r
-SCSI_In_DBx__7__AG EQU CYREG_PRT2_AG\r
-SCSI_In_DBx__7__AMUX EQU CYREG_PRT2_AMUX\r
-SCSI_In_DBx__7__BIE EQU CYREG_PRT2_BIE\r
-SCSI_In_DBx__7__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
-SCSI_In_DBx__7__BYP EQU CYREG_PRT2_BYP\r
-SCSI_In_DBx__7__CTL EQU CYREG_PRT2_CTL\r
-SCSI_In_DBx__7__DM0 EQU CYREG_PRT2_DM0\r
-SCSI_In_DBx__7__DM1 EQU CYREG_PRT2_DM1\r
-SCSI_In_DBx__7__DM2 EQU CYREG_PRT2_DM2\r
-SCSI_In_DBx__7__DR EQU CYREG_PRT2_DR\r
-SCSI_In_DBx__7__INP_DIS EQU CYREG_PRT2_INP_DIS\r
-SCSI_In_DBx__7__INTTYPE EQU CYREG_PICU2_INTTYPE4\r
-SCSI_In_DBx__7__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
-SCSI_In_DBx__7__LCD_EN EQU CYREG_PRT2_LCD_EN\r
-SCSI_In_DBx__7__MASK EQU 0x10\r
-SCSI_In_DBx__7__PC EQU CYREG_PRT2_PC4\r
-SCSI_In_DBx__7__PORT EQU 2\r
-SCSI_In_DBx__7__PRT EQU CYREG_PRT2_PRT\r
-SCSI_In_DBx__7__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
-SCSI_In_DBx__7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
-SCSI_In_DBx__7__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
-SCSI_In_DBx__7__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
-SCSI_In_DBx__7__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
-SCSI_In_DBx__7__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
-SCSI_In_DBx__7__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
-SCSI_In_DBx__7__PS EQU CYREG_PRT2_PS\r
-SCSI_In_DBx__7__SHIFT EQU 4\r
-SCSI_In_DBx__7__SLW EQU CYREG_PRT2_SLW\r
-SCSI_In_DBx__DB0__AG EQU CYREG_PRT5_AG\r
-SCSI_In_DBx__DB0__AMUX EQU CYREG_PRT5_AMUX\r
-SCSI_In_DBx__DB0__BIE EQU CYREG_PRT5_BIE\r
-SCSI_In_DBx__DB0__BIT_MASK EQU CYREG_PRT5_BIT_MASK\r
-SCSI_In_DBx__DB0__BYP EQU CYREG_PRT5_BYP\r
-SCSI_In_DBx__DB0__CTL EQU CYREG_PRT5_CTL\r
-SCSI_In_DBx__DB0__DM0 EQU CYREG_PRT5_DM0\r
-SCSI_In_DBx__DB0__DM1 EQU CYREG_PRT5_DM1\r
-SCSI_In_DBx__DB0__DM2 EQU CYREG_PRT5_DM2\r
-SCSI_In_DBx__DB0__DR EQU CYREG_PRT5_DR\r
-SCSI_In_DBx__DB0__INP_DIS EQU CYREG_PRT5_INP_DIS\r
-SCSI_In_DBx__DB0__INTTYPE EQU CYREG_PICU5_INTTYPE3\r
-SCSI_In_DBx__DB0__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG\r
-SCSI_In_DBx__DB0__LCD_EN EQU CYREG_PRT5_LCD_EN\r
-SCSI_In_DBx__DB0__MASK EQU 0x08\r
-SCSI_In_DBx__DB0__PC EQU CYREG_PRT5_PC3\r
-SCSI_In_DBx__DB0__PORT EQU 5\r
-SCSI_In_DBx__DB0__PRT EQU CYREG_PRT5_PRT\r
-SCSI_In_DBx__DB0__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL\r
-SCSI_In_DBx__DB0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN\r
-SCSI_In_DBx__DB0__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0\r
-SCSI_In_DBx__DB0__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1\r
-SCSI_In_DBx__DB0__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0\r
-SCSI_In_DBx__DB0__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1\r
-SCSI_In_DBx__DB0__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT\r
-SCSI_In_DBx__DB0__PS EQU CYREG_PRT5_PS\r
-SCSI_In_DBx__DB0__SHIFT EQU 3\r
-SCSI_In_DBx__DB0__SLW EQU CYREG_PRT5_SLW\r
-SCSI_In_DBx__DB1__AG EQU CYREG_PRT5_AG\r
-SCSI_In_DBx__DB1__AMUX EQU CYREG_PRT5_AMUX\r
-SCSI_In_DBx__DB1__BIE EQU CYREG_PRT5_BIE\r
-SCSI_In_DBx__DB1__BIT_MASK EQU CYREG_PRT5_BIT_MASK\r
-SCSI_In_DBx__DB1__BYP EQU CYREG_PRT5_BYP\r
-SCSI_In_DBx__DB1__CTL EQU CYREG_PRT5_CTL\r
-SCSI_In_DBx__DB1__DM0 EQU CYREG_PRT5_DM0\r
-SCSI_In_DBx__DB1__DM1 EQU CYREG_PRT5_DM1\r
-SCSI_In_DBx__DB1__DM2 EQU CYREG_PRT5_DM2\r
-SCSI_In_DBx__DB1__DR EQU CYREG_PRT5_DR\r
-SCSI_In_DBx__DB1__INP_DIS EQU CYREG_PRT5_INP_DIS\r
-SCSI_In_DBx__DB1__INTTYPE EQU CYREG_PICU5_INTTYPE2\r
-SCSI_In_DBx__DB1__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG\r
-SCSI_In_DBx__DB1__LCD_EN EQU CYREG_PRT5_LCD_EN\r
-SCSI_In_DBx__DB1__MASK EQU 0x04\r
-SCSI_In_DBx__DB1__PC EQU CYREG_PRT5_PC2\r
-SCSI_In_DBx__DB1__PORT EQU 5\r
-SCSI_In_DBx__DB1__PRT EQU CYREG_PRT5_PRT\r
-SCSI_In_DBx__DB1__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL\r
-SCSI_In_DBx__DB1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN\r
-SCSI_In_DBx__DB1__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0\r
-SCSI_In_DBx__DB1__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1\r
-SCSI_In_DBx__DB1__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0\r
-SCSI_In_DBx__DB1__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1\r
-SCSI_In_DBx__DB1__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT\r
-SCSI_In_DBx__DB1__PS EQU CYREG_PRT5_PS\r
-SCSI_In_DBx__DB1__SHIFT EQU 2\r
-SCSI_In_DBx__DB1__SLW EQU CYREG_PRT5_SLW\r
-SCSI_In_DBx__DB2__AG EQU CYREG_PRT6_AG\r
-SCSI_In_DBx__DB2__AMUX EQU CYREG_PRT6_AMUX\r
-SCSI_In_DBx__DB2__BIE EQU CYREG_PRT6_BIE\r
-SCSI_In_DBx__DB2__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
-SCSI_In_DBx__DB2__BYP EQU CYREG_PRT6_BYP\r
-SCSI_In_DBx__DB2__CTL EQU CYREG_PRT6_CTL\r
-SCSI_In_DBx__DB2__DM0 EQU CYREG_PRT6_DM0\r
-SCSI_In_DBx__DB2__DM1 EQU CYREG_PRT6_DM1\r
-SCSI_In_DBx__DB2__DM2 EQU CYREG_PRT6_DM2\r
-SCSI_In_DBx__DB2__DR EQU CYREG_PRT6_DR\r
-SCSI_In_DBx__DB2__INP_DIS EQU CYREG_PRT6_INP_DIS\r
-SCSI_In_DBx__DB2__INTTYPE EQU CYREG_PICU6_INTTYPE7\r
-SCSI_In_DBx__DB2__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
-SCSI_In_DBx__DB2__LCD_EN EQU CYREG_PRT6_LCD_EN\r
-SCSI_In_DBx__DB2__MASK EQU 0x80\r
-SCSI_In_DBx__DB2__PC EQU CYREG_PRT6_PC7\r
-SCSI_In_DBx__DB2__PORT EQU 6\r
-SCSI_In_DBx__DB2__PRT EQU CYREG_PRT6_PRT\r
-SCSI_In_DBx__DB2__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
-SCSI_In_DBx__DB2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
-SCSI_In_DBx__DB2__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
-SCSI_In_DBx__DB2__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
-SCSI_In_DBx__DB2__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
-SCSI_In_DBx__DB2__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
-SCSI_In_DBx__DB2__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
-SCSI_In_DBx__DB2__PS EQU CYREG_PRT6_PS\r
-SCSI_In_DBx__DB2__SHIFT EQU 7\r
-SCSI_In_DBx__DB2__SLW EQU CYREG_PRT6_SLW\r
-SCSI_In_DBx__DB3__AG EQU CYREG_PRT6_AG\r
-SCSI_In_DBx__DB3__AMUX EQU CYREG_PRT6_AMUX\r
-SCSI_In_DBx__DB3__BIE EQU CYREG_PRT6_BIE\r
-SCSI_In_DBx__DB3__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
-SCSI_In_DBx__DB3__BYP EQU CYREG_PRT6_BYP\r
-SCSI_In_DBx__DB3__CTL EQU CYREG_PRT6_CTL\r
-SCSI_In_DBx__DB3__DM0 EQU CYREG_PRT6_DM0\r
-SCSI_In_DBx__DB3__DM1 EQU CYREG_PRT6_DM1\r
-SCSI_In_DBx__DB3__DM2 EQU CYREG_PRT6_DM2\r
-SCSI_In_DBx__DB3__DR EQU CYREG_PRT6_DR\r
-SCSI_In_DBx__DB3__INP_DIS EQU CYREG_PRT6_INP_DIS\r
-SCSI_In_DBx__DB3__INTTYPE EQU CYREG_PICU6_INTTYPE6\r
-SCSI_In_DBx__DB3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
-SCSI_In_DBx__DB3__LCD_EN EQU CYREG_PRT6_LCD_EN\r
-SCSI_In_DBx__DB3__MASK EQU 0x40\r
-SCSI_In_DBx__DB3__PC EQU CYREG_PRT6_PC6\r
-SCSI_In_DBx__DB3__PORT EQU 6\r
-SCSI_In_DBx__DB3__PRT EQU CYREG_PRT6_PRT\r
-SCSI_In_DBx__DB3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
-SCSI_In_DBx__DB3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
-SCSI_In_DBx__DB3__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
-SCSI_In_DBx__DB3__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
-SCSI_In_DBx__DB3__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
-SCSI_In_DBx__DB3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
-SCSI_In_DBx__DB3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
-SCSI_In_DBx__DB3__PS EQU CYREG_PRT6_PS\r
-SCSI_In_DBx__DB3__SHIFT EQU 6\r
-SCSI_In_DBx__DB3__SLW EQU CYREG_PRT6_SLW\r
-SCSI_In_DBx__DB4__AG EQU CYREG_PRT12_AG\r
-SCSI_In_DBx__DB4__BIE EQU CYREG_PRT12_BIE\r
-SCSI_In_DBx__DB4__BIT_MASK EQU CYREG_PRT12_BIT_MASK\r
-SCSI_In_DBx__DB4__BYP EQU CYREG_PRT12_BYP\r
-SCSI_In_DBx__DB4__DM0 EQU CYREG_PRT12_DM0\r
-SCSI_In_DBx__DB4__DM1 EQU CYREG_PRT12_DM1\r
-SCSI_In_DBx__DB4__DM2 EQU CYREG_PRT12_DM2\r
-SCSI_In_DBx__DB4__DR EQU CYREG_PRT12_DR\r
-SCSI_In_DBx__DB4__INP_DIS EQU CYREG_PRT12_INP_DIS\r
-SCSI_In_DBx__DB4__INTTYPE EQU CYREG_PICU12_INTTYPE5\r
-SCSI_In_DBx__DB4__MASK EQU 0x20\r
-SCSI_In_DBx__DB4__PC EQU CYREG_PRT12_PC5\r
-SCSI_In_DBx__DB4__PORT EQU 12\r
-SCSI_In_DBx__DB4__PRT EQU CYREG_PRT12_PRT\r
-SCSI_In_DBx__DB4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN\r
-SCSI_In_DBx__DB4__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0\r
-SCSI_In_DBx__DB4__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1\r
-SCSI_In_DBx__DB4__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0\r
-SCSI_In_DBx__DB4__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1\r
-SCSI_In_DBx__DB4__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT\r
-SCSI_In_DBx__DB4__PS EQU CYREG_PRT12_PS\r
-SCSI_In_DBx__DB4__SHIFT EQU 5\r
-SCSI_In_DBx__DB4__SIO_CFG EQU CYREG_PRT12_SIO_CFG\r
-SCSI_In_DBx__DB4__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF\r
-SCSI_In_DBx__DB4__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN\r
-SCSI_In_DBx__DB4__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ\r
-SCSI_In_DBx__DB4__SLW EQU CYREG_PRT12_SLW\r
-SCSI_In_DBx__DB5__AG EQU CYREG_PRT12_AG\r
-SCSI_In_DBx__DB5__BIE EQU CYREG_PRT12_BIE\r
-SCSI_In_DBx__DB5__BIT_MASK EQU CYREG_PRT12_BIT_MASK\r
-SCSI_In_DBx__DB5__BYP EQU CYREG_PRT12_BYP\r
-SCSI_In_DBx__DB5__DM0 EQU CYREG_PRT12_DM0\r
-SCSI_In_DBx__DB5__DM1 EQU CYREG_PRT12_DM1\r
-SCSI_In_DBx__DB5__DM2 EQU CYREG_PRT12_DM2\r
-SCSI_In_DBx__DB5__DR EQU CYREG_PRT12_DR\r
-SCSI_In_DBx__DB5__INP_DIS EQU CYREG_PRT12_INP_DIS\r
-SCSI_In_DBx__DB5__INTTYPE EQU CYREG_PICU12_INTTYPE4\r
-SCSI_In_DBx__DB5__MASK EQU 0x10\r
-SCSI_In_DBx__DB5__PC EQU CYREG_PRT12_PC4\r
-SCSI_In_DBx__DB5__PORT EQU 12\r
-SCSI_In_DBx__DB5__PRT EQU CYREG_PRT12_PRT\r
-SCSI_In_DBx__DB5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN\r
-SCSI_In_DBx__DB5__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0\r
-SCSI_In_DBx__DB5__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1\r
-SCSI_In_DBx__DB5__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0\r
-SCSI_In_DBx__DB5__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1\r
-SCSI_In_DBx__DB5__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT\r
-SCSI_In_DBx__DB5__PS EQU CYREG_PRT12_PS\r
-SCSI_In_DBx__DB5__SHIFT EQU 4\r
-SCSI_In_DBx__DB5__SIO_CFG EQU CYREG_PRT12_SIO_CFG\r
-SCSI_In_DBx__DB5__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF\r
-SCSI_In_DBx__DB5__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN\r
-SCSI_In_DBx__DB5__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ\r
-SCSI_In_DBx__DB5__SLW EQU CYREG_PRT12_SLW\r
-SCSI_In_DBx__DB6__AG EQU CYREG_PRT2_AG\r
-SCSI_In_DBx__DB6__AMUX EQU CYREG_PRT2_AMUX\r
-SCSI_In_DBx__DB6__BIE EQU CYREG_PRT2_BIE\r
-SCSI_In_DBx__DB6__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
-SCSI_In_DBx__DB6__BYP EQU CYREG_PRT2_BYP\r
-SCSI_In_DBx__DB6__CTL EQU CYREG_PRT2_CTL\r
-SCSI_In_DBx__DB6__DM0 EQU CYREG_PRT2_DM0\r
-SCSI_In_DBx__DB6__DM1 EQU CYREG_PRT2_DM1\r
-SCSI_In_DBx__DB6__DM2 EQU CYREG_PRT2_DM2\r
-SCSI_In_DBx__DB6__DR EQU CYREG_PRT2_DR\r
-SCSI_In_DBx__DB6__INP_DIS EQU CYREG_PRT2_INP_DIS\r
-SCSI_In_DBx__DB6__INTTYPE EQU CYREG_PICU2_INTTYPE5\r
-SCSI_In_DBx__DB6__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
-SCSI_In_DBx__DB6__LCD_EN EQU CYREG_PRT2_LCD_EN\r
-SCSI_In_DBx__DB6__MASK EQU 0x20\r
-SCSI_In_DBx__DB6__PC EQU CYREG_PRT2_PC5\r
-SCSI_In_DBx__DB6__PORT EQU 2\r
-SCSI_In_DBx__DB6__PRT EQU CYREG_PRT2_PRT\r
-SCSI_In_DBx__DB6__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
-SCSI_In_DBx__DB6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
-SCSI_In_DBx__DB6__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
-SCSI_In_DBx__DB6__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
-SCSI_In_DBx__DB6__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
-SCSI_In_DBx__DB6__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
-SCSI_In_DBx__DB6__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
-SCSI_In_DBx__DB6__PS EQU CYREG_PRT2_PS\r
-SCSI_In_DBx__DB6__SHIFT EQU 5\r
-SCSI_In_DBx__DB6__SLW EQU CYREG_PRT2_SLW\r
-SCSI_In_DBx__DB7__AG EQU CYREG_PRT2_AG\r
-SCSI_In_DBx__DB7__AMUX EQU CYREG_PRT2_AMUX\r
-SCSI_In_DBx__DB7__BIE EQU CYREG_PRT2_BIE\r
-SCSI_In_DBx__DB7__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
-SCSI_In_DBx__DB7__BYP EQU CYREG_PRT2_BYP\r
-SCSI_In_DBx__DB7__CTL EQU CYREG_PRT2_CTL\r
-SCSI_In_DBx__DB7__DM0 EQU CYREG_PRT2_DM0\r
-SCSI_In_DBx__DB7__DM1 EQU CYREG_PRT2_DM1\r
-SCSI_In_DBx__DB7__DM2 EQU CYREG_PRT2_DM2\r
-SCSI_In_DBx__DB7__DR EQU CYREG_PRT2_DR\r
-SCSI_In_DBx__DB7__INP_DIS EQU CYREG_PRT2_INP_DIS\r
-SCSI_In_DBx__DB7__INTTYPE EQU CYREG_PICU2_INTTYPE4\r
-SCSI_In_DBx__DB7__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
-SCSI_In_DBx__DB7__LCD_EN EQU CYREG_PRT2_LCD_EN\r
-SCSI_In_DBx__DB7__MASK EQU 0x10\r
-SCSI_In_DBx__DB7__PC EQU CYREG_PRT2_PC4\r
-SCSI_In_DBx__DB7__PORT EQU 2\r
-SCSI_In_DBx__DB7__PRT EQU CYREG_PRT2_PRT\r
-SCSI_In_DBx__DB7__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
-SCSI_In_DBx__DB7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
-SCSI_In_DBx__DB7__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
-SCSI_In_DBx__DB7__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
-SCSI_In_DBx__DB7__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
-SCSI_In_DBx__DB7__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
-SCSI_In_DBx__DB7__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
-SCSI_In_DBx__DB7__PS EQU CYREG_PRT2_PS\r
-SCSI_In_DBx__DB7__SHIFT EQU 4\r
-SCSI_In_DBx__DB7__SLW EQU CYREG_PRT2_SLW\r
-\r
-; SD_MISO\r
-SD_MISO__0__INTTYPE EQU CYREG_PICU3_INTTYPE1\r
-SD_MISO__0__MASK EQU 0x02\r
-SD_MISO__0__PC EQU CYREG_PRT3_PC1\r
-SD_MISO__0__PORT EQU 3\r
-SD_MISO__0__SHIFT EQU 1\r
-SD_MISO__AG EQU CYREG_PRT3_AG\r
-SD_MISO__AMUX EQU CYREG_PRT3_AMUX\r
-SD_MISO__BIE EQU CYREG_PRT3_BIE\r
-SD_MISO__BIT_MASK EQU CYREG_PRT3_BIT_MASK\r
-SD_MISO__BYP EQU CYREG_PRT3_BYP\r
-SD_MISO__CTL EQU CYREG_PRT3_CTL\r
-SD_MISO__DM0 EQU CYREG_PRT3_DM0\r
-SD_MISO__DM1 EQU CYREG_PRT3_DM1\r
-SD_MISO__DM2 EQU CYREG_PRT3_DM2\r
-SD_MISO__DR EQU CYREG_PRT3_DR\r
-SD_MISO__INP_DIS EQU CYREG_PRT3_INP_DIS\r
-SD_MISO__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE\r
-SD_MISO__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG\r
-SD_MISO__LCD_EN EQU CYREG_PRT3_LCD_EN\r
-SD_MISO__MASK EQU 0x02\r
-SD_MISO__PORT EQU 3\r
-SD_MISO__PRT EQU CYREG_PRT3_PRT\r
-SD_MISO__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL\r
-SD_MISO__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN\r
-SD_MISO__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0\r
-SD_MISO__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1\r
-SD_MISO__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0\r
-SD_MISO__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1\r
-SD_MISO__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT\r
-SD_MISO__PS EQU CYREG_PRT3_PS\r
-SD_MISO__SHIFT EQU 1\r
-SD_MISO__SLW EQU CYREG_PRT3_SLW\r
-\r
-; SD_MOSI\r
-SD_MOSI__0__INTTYPE EQU CYREG_PICU3_INTTYPE3\r
-SD_MOSI__0__MASK EQU 0x08\r
-SD_MOSI__0__PC EQU CYREG_PRT3_PC3\r
-SD_MOSI__0__PORT EQU 3\r
-SD_MOSI__0__SHIFT EQU 3\r
-SD_MOSI__AG EQU CYREG_PRT3_AG\r
-SD_MOSI__AMUX EQU CYREG_PRT3_AMUX\r
-SD_MOSI__BIE EQU CYREG_PRT3_BIE\r
-SD_MOSI__BIT_MASK EQU CYREG_PRT3_BIT_MASK\r
-SD_MOSI__BYP EQU CYREG_PRT3_BYP\r
-SD_MOSI__CTL EQU CYREG_PRT3_CTL\r
-SD_MOSI__DM0 EQU CYREG_PRT3_DM0\r
-SD_MOSI__DM1 EQU CYREG_PRT3_DM1\r
-SD_MOSI__DM2 EQU CYREG_PRT3_DM2\r
-SD_MOSI__DR EQU CYREG_PRT3_DR\r
-SD_MOSI__INP_DIS EQU CYREG_PRT3_INP_DIS\r
-SD_MOSI__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE\r
-SD_MOSI__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG\r
-SD_MOSI__LCD_EN EQU CYREG_PRT3_LCD_EN\r
-SD_MOSI__MASK EQU 0x08\r
-SD_MOSI__PORT EQU 3\r
-SD_MOSI__PRT EQU CYREG_PRT3_PRT\r
-SD_MOSI__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL\r
-SD_MOSI__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN\r
-SD_MOSI__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0\r
-SD_MOSI__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1\r
-SD_MOSI__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0\r
-SD_MOSI__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1\r
-SD_MOSI__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT\r
-SD_MOSI__PS EQU CYREG_PRT3_PS\r
-SD_MOSI__SHIFT EQU 3\r
-SD_MOSI__SLW EQU CYREG_PRT3_SLW\r
-\r
-; SCSI_CLK\r
-SCSI_CLK__CFG0 EQU CYREG_CLKDIST_DCFG1_CFG0\r
-SCSI_CLK__CFG1 EQU CYREG_CLKDIST_DCFG1_CFG1\r
-SCSI_CLK__CFG2 EQU CYREG_CLKDIST_DCFG1_CFG2\r
-SCSI_CLK__CFG2_SRC_SEL_MASK EQU 0x07\r
-SCSI_CLK__INDEX EQU 0x01\r
-SCSI_CLK__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2\r
-SCSI_CLK__PM_ACT_MSK EQU 0x02\r
-SCSI_CLK__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2\r
-SCSI_CLK__PM_STBY_MSK EQU 0x02\r
-\r
-; SCSI_Out\r
-SCSI_Out__0__AG EQU CYREG_PRT15_AG\r
-SCSI_Out__0__AMUX EQU CYREG_PRT15_AMUX\r
-SCSI_Out__0__BIE EQU CYREG_PRT15_BIE\r
-SCSI_Out__0__BIT_MASK EQU CYREG_PRT15_BIT_MASK\r
-SCSI_Out__0__BYP EQU CYREG_PRT15_BYP\r
-SCSI_Out__0__CTL EQU CYREG_PRT15_CTL\r
-SCSI_Out__0__DM0 EQU CYREG_PRT15_DM0\r
-SCSI_Out__0__DM1 EQU CYREG_PRT15_DM1\r
-SCSI_Out__0__DM2 EQU CYREG_PRT15_DM2\r
-SCSI_Out__0__DR EQU CYREG_PRT15_DR\r
-SCSI_Out__0__INP_DIS EQU CYREG_PRT15_INP_DIS\r
-SCSI_Out__0__INTTYPE EQU CYREG_PICU15_INTTYPE5\r
-SCSI_Out__0__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG\r
-SCSI_Out__0__LCD_EN EQU CYREG_PRT15_LCD_EN\r
-SCSI_Out__0__MASK EQU 0x20\r
-SCSI_Out__0__PC EQU CYREG_IO_PC_PRT15_PC5\r
-SCSI_Out__0__PORT EQU 15\r
-SCSI_Out__0__PRT EQU CYREG_PRT15_PRT\r
-SCSI_Out__0__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL\r
-SCSI_Out__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN\r
-SCSI_Out__0__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0\r
-SCSI_Out__0__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1\r
-SCSI_Out__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0\r
-SCSI_Out__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1\r
-SCSI_Out__0__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT\r
-SCSI_Out__0__PS EQU CYREG_PRT15_PS\r
-SCSI_Out__0__SHIFT EQU 5\r
-SCSI_Out__0__SLW EQU CYREG_PRT15_SLW\r
-SCSI_Out__1__AG EQU CYREG_PRT15_AG\r
-SCSI_Out__1__AMUX EQU CYREG_PRT15_AMUX\r
-SCSI_Out__1__BIE EQU CYREG_PRT15_BIE\r
-SCSI_Out__1__BIT_MASK EQU CYREG_PRT15_BIT_MASK\r
-SCSI_Out__1__BYP EQU CYREG_PRT15_BYP\r
-SCSI_Out__1__CTL EQU CYREG_PRT15_CTL\r
-SCSI_Out__1__DM0 EQU CYREG_PRT15_DM0\r
-SCSI_Out__1__DM1 EQU CYREG_PRT15_DM1\r
-SCSI_Out__1__DM2 EQU CYREG_PRT15_DM2\r
-SCSI_Out__1__DR EQU CYREG_PRT15_DR\r
-SCSI_Out__1__INP_DIS EQU CYREG_PRT15_INP_DIS\r
-SCSI_Out__1__INTTYPE EQU CYREG_PICU15_INTTYPE4\r
-SCSI_Out__1__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG\r
-SCSI_Out__1__LCD_EN EQU CYREG_PRT15_LCD_EN\r
-SCSI_Out__1__MASK EQU 0x10\r
-SCSI_Out__1__PC EQU CYREG_IO_PC_PRT15_PC4\r
-SCSI_Out__1__PORT EQU 15\r
-SCSI_Out__1__PRT EQU CYREG_PRT15_PRT\r
-SCSI_Out__1__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL\r
-SCSI_Out__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN\r
-SCSI_Out__1__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0\r
-SCSI_Out__1__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1\r
-SCSI_Out__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0\r
-SCSI_Out__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1\r
-SCSI_Out__1__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT\r
-SCSI_Out__1__PS EQU CYREG_PRT15_PS\r
-SCSI_Out__1__SHIFT EQU 4\r
-SCSI_Out__1__SLW EQU CYREG_PRT15_SLW\r
-SCSI_Out__2__AG EQU CYREG_PRT6_AG\r
-SCSI_Out__2__AMUX EQU CYREG_PRT6_AMUX\r
-SCSI_Out__2__BIE EQU CYREG_PRT6_BIE\r
-SCSI_Out__2__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
-SCSI_Out__2__BYP EQU CYREG_PRT6_BYP\r
-SCSI_Out__2__CTL EQU CYREG_PRT6_CTL\r
-SCSI_Out__2__DM0 EQU CYREG_PRT6_DM0\r
-SCSI_Out__2__DM1 EQU CYREG_PRT6_DM1\r
-SCSI_Out__2__DM2 EQU CYREG_PRT6_DM2\r
-SCSI_Out__2__DR EQU CYREG_PRT6_DR\r
-SCSI_Out__2__INP_DIS EQU CYREG_PRT6_INP_DIS\r
-SCSI_Out__2__INTTYPE EQU CYREG_PICU6_INTTYPE1\r
-SCSI_Out__2__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
-SCSI_Out__2__LCD_EN EQU CYREG_PRT6_LCD_EN\r
-SCSI_Out__2__MASK EQU 0x02\r
-SCSI_Out__2__PC EQU CYREG_PRT6_PC1\r
-SCSI_Out__2__PORT EQU 6\r
-SCSI_Out__2__PRT EQU CYREG_PRT6_PRT\r
-SCSI_Out__2__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
-SCSI_Out__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
-SCSI_Out__2__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
-SCSI_Out__2__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
-SCSI_Out__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
-SCSI_Out__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
-SCSI_Out__2__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
-SCSI_Out__2__PS EQU CYREG_PRT6_PS\r
-SCSI_Out__2__SHIFT EQU 1\r
-SCSI_Out__2__SLW EQU CYREG_PRT6_SLW\r
-SCSI_Out__3__AG EQU CYREG_PRT6_AG\r
-SCSI_Out__3__AMUX EQU CYREG_PRT6_AMUX\r
-SCSI_Out__3__BIE EQU CYREG_PRT6_BIE\r
-SCSI_Out__3__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
-SCSI_Out__3__BYP EQU CYREG_PRT6_BYP\r
-SCSI_Out__3__CTL EQU CYREG_PRT6_CTL\r
-SCSI_Out__3__DM0 EQU CYREG_PRT6_DM0\r
-SCSI_Out__3__DM1 EQU CYREG_PRT6_DM1\r
-SCSI_Out__3__DM2 EQU CYREG_PRT6_DM2\r
-SCSI_Out__3__DR EQU CYREG_PRT6_DR\r
-SCSI_Out__3__INP_DIS EQU CYREG_PRT6_INP_DIS\r
-SCSI_Out__3__INTTYPE EQU CYREG_PICU6_INTTYPE0\r
-SCSI_Out__3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
-SCSI_Out__3__LCD_EN EQU CYREG_PRT6_LCD_EN\r
-SCSI_Out__3__MASK EQU 0x01\r
-SCSI_Out__3__PC EQU CYREG_PRT6_PC0\r
-SCSI_Out__3__PORT EQU 6\r
-SCSI_Out__3__PRT EQU CYREG_PRT6_PRT\r
-SCSI_Out__3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
-SCSI_Out__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
-SCSI_Out__3__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
-SCSI_Out__3__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
-SCSI_Out__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
-SCSI_Out__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
-SCSI_Out__3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
-SCSI_Out__3__PS EQU CYREG_PRT6_PS\r
-SCSI_Out__3__SHIFT EQU 0\r
-SCSI_Out__3__SLW EQU CYREG_PRT6_SLW\r
-SCSI_Out__4__AG EQU CYREG_PRT4_AG\r
-SCSI_Out__4__AMUX EQU CYREG_PRT4_AMUX\r
-SCSI_Out__4__BIE EQU CYREG_PRT4_BIE\r
-SCSI_Out__4__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
-SCSI_Out__4__BYP EQU CYREG_PRT4_BYP\r
-SCSI_Out__4__CTL EQU CYREG_PRT4_CTL\r
-SCSI_Out__4__DM0 EQU CYREG_PRT4_DM0\r
-SCSI_Out__4__DM1 EQU CYREG_PRT4_DM1\r
-SCSI_Out__4__DM2 EQU CYREG_PRT4_DM2\r
-SCSI_Out__4__DR EQU CYREG_PRT4_DR\r
-SCSI_Out__4__INP_DIS EQU CYREG_PRT4_INP_DIS\r
-SCSI_Out__4__INTTYPE EQU CYREG_PICU4_INTTYPE5\r
-SCSI_Out__4__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
-SCSI_Out__4__LCD_EN EQU CYREG_PRT4_LCD_EN\r
-SCSI_Out__4__MASK EQU 0x20\r
-SCSI_Out__4__PC EQU CYREG_PRT4_PC5\r
-SCSI_Out__4__PORT EQU 4\r
-SCSI_Out__4__PRT EQU CYREG_PRT4_PRT\r
-SCSI_Out__4__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
-SCSI_Out__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
-SCSI_Out__4__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
-SCSI_Out__4__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
-SCSI_Out__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
-SCSI_Out__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
-SCSI_Out__4__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
-SCSI_Out__4__PS EQU CYREG_PRT4_PS\r
-SCSI_Out__4__SHIFT EQU 5\r
-SCSI_Out__4__SLW EQU CYREG_PRT4_SLW\r
-SCSI_Out__5__AG EQU CYREG_PRT4_AG\r
-SCSI_Out__5__AMUX EQU CYREG_PRT4_AMUX\r
-SCSI_Out__5__BIE EQU CYREG_PRT4_BIE\r
-SCSI_Out__5__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
-SCSI_Out__5__BYP EQU CYREG_PRT4_BYP\r
-SCSI_Out__5__CTL EQU CYREG_PRT4_CTL\r
-SCSI_Out__5__DM0 EQU CYREG_PRT4_DM0\r
-SCSI_Out__5__DM1 EQU CYREG_PRT4_DM1\r
-SCSI_Out__5__DM2 EQU CYREG_PRT4_DM2\r
-SCSI_Out__5__DR EQU CYREG_PRT4_DR\r
-SCSI_Out__5__INP_DIS EQU CYREG_PRT4_INP_DIS\r
-SCSI_Out__5__INTTYPE EQU CYREG_PICU4_INTTYPE4\r
-SCSI_Out__5__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
-SCSI_Out__5__LCD_EN EQU CYREG_PRT4_LCD_EN\r
-SCSI_Out__5__MASK EQU 0x10\r
-SCSI_Out__5__PC EQU CYREG_PRT4_PC4\r
-SCSI_Out__5__PORT EQU 4\r
-SCSI_Out__5__PRT EQU CYREG_PRT4_PRT\r
-SCSI_Out__5__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
-SCSI_Out__5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
-SCSI_Out__5__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
-SCSI_Out__5__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
-SCSI_Out__5__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
-SCSI_Out__5__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
-SCSI_Out__5__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
-SCSI_Out__5__PS EQU CYREG_PRT4_PS\r
-SCSI_Out__5__SHIFT EQU 4\r
-SCSI_Out__5__SLW EQU CYREG_PRT4_SLW\r
-SCSI_Out__6__AG EQU CYREG_PRT0_AG\r
-SCSI_Out__6__AMUX EQU CYREG_PRT0_AMUX\r
-SCSI_Out__6__BIE EQU CYREG_PRT0_BIE\r
-SCSI_Out__6__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
-SCSI_Out__6__BYP EQU CYREG_PRT0_BYP\r
-SCSI_Out__6__CTL EQU CYREG_PRT0_CTL\r
-SCSI_Out__6__DM0 EQU CYREG_PRT0_DM0\r
-SCSI_Out__6__DM1 EQU CYREG_PRT0_DM1\r
-SCSI_Out__6__DM2 EQU CYREG_PRT0_DM2\r
-SCSI_Out__6__DR EQU CYREG_PRT0_DR\r
-SCSI_Out__6__INP_DIS EQU CYREG_PRT0_INP_DIS\r
-SCSI_Out__6__INTTYPE EQU CYREG_PICU0_INTTYPE7\r
-SCSI_Out__6__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
-SCSI_Out__6__LCD_EN EQU CYREG_PRT0_LCD_EN\r
-SCSI_Out__6__MASK EQU 0x80\r
-SCSI_Out__6__PC EQU CYREG_PRT0_PC7\r
-SCSI_Out__6__PORT EQU 0\r
-SCSI_Out__6__PRT EQU CYREG_PRT0_PRT\r
-SCSI_Out__6__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
-SCSI_Out__6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
-SCSI_Out__6__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
-SCSI_Out__6__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
-SCSI_Out__6__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
-SCSI_Out__6__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
-SCSI_Out__6__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
-SCSI_Out__6__PS EQU CYREG_PRT0_PS\r
-SCSI_Out__6__SHIFT EQU 7\r
-SCSI_Out__6__SLW EQU CYREG_PRT0_SLW\r
-SCSI_Out__7__AG EQU CYREG_PRT0_AG\r
-SCSI_Out__7__AMUX EQU CYREG_PRT0_AMUX\r
-SCSI_Out__7__BIE EQU CYREG_PRT0_BIE\r
-SCSI_Out__7__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
-SCSI_Out__7__BYP EQU CYREG_PRT0_BYP\r
-SCSI_Out__7__CTL EQU CYREG_PRT0_CTL\r
-SCSI_Out__7__DM0 EQU CYREG_PRT0_DM0\r
-SCSI_Out__7__DM1 EQU CYREG_PRT0_DM1\r
-SCSI_Out__7__DM2 EQU CYREG_PRT0_DM2\r
-SCSI_Out__7__DR EQU CYREG_PRT0_DR\r
-SCSI_Out__7__INP_DIS EQU CYREG_PRT0_INP_DIS\r
-SCSI_Out__7__INTTYPE EQU CYREG_PICU0_INTTYPE6\r
-SCSI_Out__7__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
-SCSI_Out__7__LCD_EN EQU CYREG_PRT0_LCD_EN\r
-SCSI_Out__7__MASK EQU 0x40\r
-SCSI_Out__7__PC EQU CYREG_PRT0_PC6\r
-SCSI_Out__7__PORT EQU 0\r
-SCSI_Out__7__PRT EQU CYREG_PRT0_PRT\r
-SCSI_Out__7__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
-SCSI_Out__7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
-SCSI_Out__7__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
-SCSI_Out__7__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
-SCSI_Out__7__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
-SCSI_Out__7__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
-SCSI_Out__7__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
-SCSI_Out__7__PS EQU CYREG_PRT0_PS\r
-SCSI_Out__7__SHIFT EQU 6\r
-SCSI_Out__7__SLW EQU CYREG_PRT0_SLW\r
-SCSI_Out__8__AG EQU CYREG_PRT0_AG\r
-SCSI_Out__8__AMUX EQU CYREG_PRT0_AMUX\r
-SCSI_Out__8__BIE EQU CYREG_PRT0_BIE\r
-SCSI_Out__8__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
-SCSI_Out__8__BYP EQU CYREG_PRT0_BYP\r
-SCSI_Out__8__CTL EQU CYREG_PRT0_CTL\r
-SCSI_Out__8__DM0 EQU CYREG_PRT0_DM0\r
-SCSI_Out__8__DM1 EQU CYREG_PRT0_DM1\r
-SCSI_Out__8__DM2 EQU CYREG_PRT0_DM2\r
-SCSI_Out__8__DR EQU CYREG_PRT0_DR\r
-SCSI_Out__8__INP_DIS EQU CYREG_PRT0_INP_DIS\r
-SCSI_Out__8__INTTYPE EQU CYREG_PICU0_INTTYPE3\r
-SCSI_Out__8__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
-SCSI_Out__8__LCD_EN EQU CYREG_PRT0_LCD_EN\r
-SCSI_Out__8__MASK EQU 0x08\r
-SCSI_Out__8__PC EQU CYREG_PRT0_PC3\r
-SCSI_Out__8__PORT EQU 0\r
-SCSI_Out__8__PRT EQU CYREG_PRT0_PRT\r
-SCSI_Out__8__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
-SCSI_Out__8__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
-SCSI_Out__8__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
-SCSI_Out__8__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
-SCSI_Out__8__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
-SCSI_Out__8__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
-SCSI_Out__8__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
-SCSI_Out__8__PS EQU CYREG_PRT0_PS\r
-SCSI_Out__8__SHIFT EQU 3\r
-SCSI_Out__8__SLW EQU CYREG_PRT0_SLW\r
-SCSI_Out__9__AG EQU CYREG_PRT0_AG\r
-SCSI_Out__9__AMUX EQU CYREG_PRT0_AMUX\r
-SCSI_Out__9__BIE EQU CYREG_PRT0_BIE\r
-SCSI_Out__9__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
-SCSI_Out__9__BYP EQU CYREG_PRT0_BYP\r
-SCSI_Out__9__CTL EQU CYREG_PRT0_CTL\r
-SCSI_Out__9__DM0 EQU CYREG_PRT0_DM0\r
-SCSI_Out__9__DM1 EQU CYREG_PRT0_DM1\r
-SCSI_Out__9__DM2 EQU CYREG_PRT0_DM2\r
-SCSI_Out__9__DR EQU CYREG_PRT0_DR\r
-SCSI_Out__9__INP_DIS EQU CYREG_PRT0_INP_DIS\r
-SCSI_Out__9__INTTYPE EQU CYREG_PICU0_INTTYPE2\r
-SCSI_Out__9__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
-SCSI_Out__9__LCD_EN EQU CYREG_PRT0_LCD_EN\r
-SCSI_Out__9__MASK EQU 0x04\r
-SCSI_Out__9__PC EQU CYREG_PRT0_PC2\r
-SCSI_Out__9__PORT EQU 0\r
-SCSI_Out__9__PRT EQU CYREG_PRT0_PRT\r
-SCSI_Out__9__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
-SCSI_Out__9__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
-SCSI_Out__9__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
-SCSI_Out__9__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
-SCSI_Out__9__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
-SCSI_Out__9__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
-SCSI_Out__9__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
-SCSI_Out__9__PS EQU CYREG_PRT0_PS\r
-SCSI_Out__9__SHIFT EQU 2\r
-SCSI_Out__9__SLW EQU CYREG_PRT0_SLW\r
-SCSI_Out__ACK__AG EQU CYREG_PRT6_AG\r
-SCSI_Out__ACK__AMUX EQU CYREG_PRT6_AMUX\r
-SCSI_Out__ACK__BIE EQU CYREG_PRT6_BIE\r
-SCSI_Out__ACK__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
-SCSI_Out__ACK__BYP EQU CYREG_PRT6_BYP\r
-SCSI_Out__ACK__CTL EQU CYREG_PRT6_CTL\r
-SCSI_Out__ACK__DM0 EQU CYREG_PRT6_DM0\r
-SCSI_Out__ACK__DM1 EQU CYREG_PRT6_DM1\r
-SCSI_Out__ACK__DM2 EQU CYREG_PRT6_DM2\r
-SCSI_Out__ACK__DR EQU CYREG_PRT6_DR\r
-SCSI_Out__ACK__INP_DIS EQU CYREG_PRT6_INP_DIS\r
-SCSI_Out__ACK__INTTYPE EQU CYREG_PICU6_INTTYPE0\r
-SCSI_Out__ACK__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
-SCSI_Out__ACK__LCD_EN EQU CYREG_PRT6_LCD_EN\r
-SCSI_Out__ACK__MASK EQU 0x01\r
-SCSI_Out__ACK__PC EQU CYREG_PRT6_PC0\r
-SCSI_Out__ACK__PORT EQU 6\r
-SCSI_Out__ACK__PRT EQU CYREG_PRT6_PRT\r
-SCSI_Out__ACK__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
-SCSI_Out__ACK__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
-SCSI_Out__ACK__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
-SCSI_Out__ACK__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
-SCSI_Out__ACK__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
-SCSI_Out__ACK__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
-SCSI_Out__ACK__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
-SCSI_Out__ACK__PS EQU CYREG_PRT6_PS\r
-SCSI_Out__ACK__SHIFT EQU 0\r
-SCSI_Out__ACK__SLW EQU CYREG_PRT6_SLW\r
-SCSI_Out__ATN__AG EQU CYREG_PRT15_AG\r
-SCSI_Out__ATN__AMUX EQU CYREG_PRT15_AMUX\r
-SCSI_Out__ATN__BIE EQU CYREG_PRT15_BIE\r
-SCSI_Out__ATN__BIT_MASK EQU CYREG_PRT15_BIT_MASK\r
-SCSI_Out__ATN__BYP EQU CYREG_PRT15_BYP\r
-SCSI_Out__ATN__CTL EQU CYREG_PRT15_CTL\r
-SCSI_Out__ATN__DM0 EQU CYREG_PRT15_DM0\r
-SCSI_Out__ATN__DM1 EQU CYREG_PRT15_DM1\r
-SCSI_Out__ATN__DM2 EQU CYREG_PRT15_DM2\r
-SCSI_Out__ATN__DR EQU CYREG_PRT15_DR\r
-SCSI_Out__ATN__INP_DIS EQU CYREG_PRT15_INP_DIS\r
-SCSI_Out__ATN__INTTYPE EQU CYREG_PICU15_INTTYPE4\r
-SCSI_Out__ATN__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG\r
-SCSI_Out__ATN__LCD_EN EQU CYREG_PRT15_LCD_EN\r
-SCSI_Out__ATN__MASK EQU 0x10\r
-SCSI_Out__ATN__PC EQU CYREG_IO_PC_PRT15_PC4\r
-SCSI_Out__ATN__PORT EQU 15\r
-SCSI_Out__ATN__PRT EQU CYREG_PRT15_PRT\r
-SCSI_Out__ATN__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL\r
-SCSI_Out__ATN__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN\r
-SCSI_Out__ATN__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0\r
-SCSI_Out__ATN__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1\r
-SCSI_Out__ATN__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0\r
-SCSI_Out__ATN__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1\r
-SCSI_Out__ATN__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT\r
-SCSI_Out__ATN__PS EQU CYREG_PRT15_PS\r
-SCSI_Out__ATN__SHIFT EQU 4\r
-SCSI_Out__ATN__SLW EQU CYREG_PRT15_SLW\r
-SCSI_Out__BSY__AG EQU CYREG_PRT6_AG\r
-SCSI_Out__BSY__AMUX EQU CYREG_PRT6_AMUX\r
-SCSI_Out__BSY__BIE EQU CYREG_PRT6_BIE\r
-SCSI_Out__BSY__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
-SCSI_Out__BSY__BYP EQU CYREG_PRT6_BYP\r
-SCSI_Out__BSY__CTL EQU CYREG_PRT6_CTL\r
-SCSI_Out__BSY__DM0 EQU CYREG_PRT6_DM0\r
-SCSI_Out__BSY__DM1 EQU CYREG_PRT6_DM1\r
-SCSI_Out__BSY__DM2 EQU CYREG_PRT6_DM2\r
-SCSI_Out__BSY__DR EQU CYREG_PRT6_DR\r
-SCSI_Out__BSY__INP_DIS EQU CYREG_PRT6_INP_DIS\r
-SCSI_Out__BSY__INTTYPE EQU CYREG_PICU6_INTTYPE1\r
-SCSI_Out__BSY__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
-SCSI_Out__BSY__LCD_EN EQU CYREG_PRT6_LCD_EN\r
-SCSI_Out__BSY__MASK EQU 0x02\r
-SCSI_Out__BSY__PC EQU CYREG_PRT6_PC1\r
-SCSI_Out__BSY__PORT EQU 6\r
-SCSI_Out__BSY__PRT EQU CYREG_PRT6_PRT\r
-SCSI_Out__BSY__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
-SCSI_Out__BSY__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
-SCSI_Out__BSY__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
-SCSI_Out__BSY__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
-SCSI_Out__BSY__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
-SCSI_Out__BSY__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
-SCSI_Out__BSY__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
-SCSI_Out__BSY__PS EQU CYREG_PRT6_PS\r
-SCSI_Out__BSY__SHIFT EQU 1\r
-SCSI_Out__BSY__SLW EQU CYREG_PRT6_SLW\r
-SCSI_Out__CD_raw__AG EQU CYREG_PRT0_AG\r
-SCSI_Out__CD_raw__AMUX EQU CYREG_PRT0_AMUX\r
-SCSI_Out__CD_raw__BIE EQU CYREG_PRT0_BIE\r
-SCSI_Out__CD_raw__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
-SCSI_Out__CD_raw__BYP EQU CYREG_PRT0_BYP\r
-SCSI_Out__CD_raw__CTL EQU CYREG_PRT0_CTL\r
-SCSI_Out__CD_raw__DM0 EQU CYREG_PRT0_DM0\r
-SCSI_Out__CD_raw__DM1 EQU CYREG_PRT0_DM1\r
-SCSI_Out__CD_raw__DM2 EQU CYREG_PRT0_DM2\r
-SCSI_Out__CD_raw__DR EQU CYREG_PRT0_DR\r
-SCSI_Out__CD_raw__INP_DIS EQU CYREG_PRT0_INP_DIS\r
-SCSI_Out__CD_raw__INTTYPE EQU CYREG_PICU0_INTTYPE6\r
-SCSI_Out__CD_raw__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
-SCSI_Out__CD_raw__LCD_EN EQU CYREG_PRT0_LCD_EN\r
-SCSI_Out__CD_raw__MASK EQU 0x40\r
-SCSI_Out__CD_raw__PC EQU CYREG_PRT0_PC6\r
-SCSI_Out__CD_raw__PORT EQU 0\r
-SCSI_Out__CD_raw__PRT EQU CYREG_PRT0_PRT\r
-SCSI_Out__CD_raw__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
-SCSI_Out__CD_raw__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
-SCSI_Out__CD_raw__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
-SCSI_Out__CD_raw__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
-SCSI_Out__CD_raw__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
-SCSI_Out__CD_raw__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
-SCSI_Out__CD_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
-SCSI_Out__CD_raw__PS EQU CYREG_PRT0_PS\r
-SCSI_Out__CD_raw__SHIFT EQU 6\r
-SCSI_Out__CD_raw__SLW EQU CYREG_PRT0_SLW\r
-SCSI_Out__DBP_raw__AG EQU CYREG_PRT15_AG\r
-SCSI_Out__DBP_raw__AMUX EQU CYREG_PRT15_AMUX\r
-SCSI_Out__DBP_raw__BIE EQU CYREG_PRT15_BIE\r
-SCSI_Out__DBP_raw__BIT_MASK EQU CYREG_PRT15_BIT_MASK\r
-SCSI_Out__DBP_raw__BYP EQU CYREG_PRT15_BYP\r
-SCSI_Out__DBP_raw__CTL EQU CYREG_PRT15_CTL\r
-SCSI_Out__DBP_raw__DM0 EQU CYREG_PRT15_DM0\r
-SCSI_Out__DBP_raw__DM1 EQU CYREG_PRT15_DM1\r
-SCSI_Out__DBP_raw__DM2 EQU CYREG_PRT15_DM2\r
-SCSI_Out__DBP_raw__DR EQU CYREG_PRT15_DR\r
-SCSI_Out__DBP_raw__INP_DIS EQU CYREG_PRT15_INP_DIS\r
-SCSI_Out__DBP_raw__INTTYPE EQU CYREG_PICU15_INTTYPE5\r
-SCSI_Out__DBP_raw__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG\r
-SCSI_Out__DBP_raw__LCD_EN EQU CYREG_PRT15_LCD_EN\r
-SCSI_Out__DBP_raw__MASK EQU 0x20\r
-SCSI_Out__DBP_raw__PC EQU CYREG_IO_PC_PRT15_PC5\r
-SCSI_Out__DBP_raw__PORT EQU 15\r
-SCSI_Out__DBP_raw__PRT EQU CYREG_PRT15_PRT\r
-SCSI_Out__DBP_raw__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL\r
-SCSI_Out__DBP_raw__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN\r
-SCSI_Out__DBP_raw__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0\r
-SCSI_Out__DBP_raw__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1\r
-SCSI_Out__DBP_raw__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0\r
-SCSI_Out__DBP_raw__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1\r
-SCSI_Out__DBP_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT\r
-SCSI_Out__DBP_raw__PS EQU CYREG_PRT15_PS\r
-SCSI_Out__DBP_raw__SHIFT EQU 5\r
-SCSI_Out__DBP_raw__SLW EQU CYREG_PRT15_SLW\r
-SCSI_Out__IO_raw__AG EQU CYREG_PRT0_AG\r
-SCSI_Out__IO_raw__AMUX EQU CYREG_PRT0_AMUX\r
-SCSI_Out__IO_raw__BIE EQU CYREG_PRT0_BIE\r
-SCSI_Out__IO_raw__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
-SCSI_Out__IO_raw__BYP EQU CYREG_PRT0_BYP\r
-SCSI_Out__IO_raw__CTL EQU CYREG_PRT0_CTL\r
-SCSI_Out__IO_raw__DM0 EQU CYREG_PRT0_DM0\r
-SCSI_Out__IO_raw__DM1 EQU CYREG_PRT0_DM1\r
-SCSI_Out__IO_raw__DM2 EQU CYREG_PRT0_DM2\r
-SCSI_Out__IO_raw__DR EQU CYREG_PRT0_DR\r
-SCSI_Out__IO_raw__INP_DIS EQU CYREG_PRT0_INP_DIS\r
-SCSI_Out__IO_raw__INTTYPE EQU CYREG_PICU0_INTTYPE2\r
-SCSI_Out__IO_raw__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
-SCSI_Out__IO_raw__LCD_EN EQU CYREG_PRT0_LCD_EN\r
-SCSI_Out__IO_raw__MASK EQU 0x04\r
-SCSI_Out__IO_raw__PC EQU CYREG_PRT0_PC2\r
-SCSI_Out__IO_raw__PORT EQU 0\r
-SCSI_Out__IO_raw__PRT EQU CYREG_PRT0_PRT\r
-SCSI_Out__IO_raw__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
-SCSI_Out__IO_raw__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
-SCSI_Out__IO_raw__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
-SCSI_Out__IO_raw__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
-SCSI_Out__IO_raw__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
-SCSI_Out__IO_raw__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
-SCSI_Out__IO_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
-SCSI_Out__IO_raw__PS EQU CYREG_PRT0_PS\r
-SCSI_Out__IO_raw__SHIFT EQU 2\r
-SCSI_Out__IO_raw__SLW EQU CYREG_PRT0_SLW\r
-SCSI_Out__MSG_raw__AG EQU CYREG_PRT4_AG\r
-SCSI_Out__MSG_raw__AMUX EQU CYREG_PRT4_AMUX\r
-SCSI_Out__MSG_raw__BIE EQU CYREG_PRT4_BIE\r
-SCSI_Out__MSG_raw__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
-SCSI_Out__MSG_raw__BYP EQU CYREG_PRT4_BYP\r
-SCSI_Out__MSG_raw__CTL EQU CYREG_PRT4_CTL\r
-SCSI_Out__MSG_raw__DM0 EQU CYREG_PRT4_DM0\r
-SCSI_Out__MSG_raw__DM1 EQU CYREG_PRT4_DM1\r
-SCSI_Out__MSG_raw__DM2 EQU CYREG_PRT4_DM2\r
-SCSI_Out__MSG_raw__DR EQU CYREG_PRT4_DR\r
-SCSI_Out__MSG_raw__INP_DIS EQU CYREG_PRT4_INP_DIS\r
-SCSI_Out__MSG_raw__INTTYPE EQU CYREG_PICU4_INTTYPE4\r
-SCSI_Out__MSG_raw__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
-SCSI_Out__MSG_raw__LCD_EN EQU CYREG_PRT4_LCD_EN\r
-SCSI_Out__MSG_raw__MASK EQU 0x10\r
-SCSI_Out__MSG_raw__PC EQU CYREG_PRT4_PC4\r
-SCSI_Out__MSG_raw__PORT EQU 4\r
-SCSI_Out__MSG_raw__PRT EQU CYREG_PRT4_PRT\r
-SCSI_Out__MSG_raw__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
-SCSI_Out__MSG_raw__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
-SCSI_Out__MSG_raw__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
-SCSI_Out__MSG_raw__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
-SCSI_Out__MSG_raw__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
-SCSI_Out__MSG_raw__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
-SCSI_Out__MSG_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
-SCSI_Out__MSG_raw__PS EQU CYREG_PRT4_PS\r
-SCSI_Out__MSG_raw__SHIFT EQU 4\r
-SCSI_Out__MSG_raw__SLW EQU CYREG_PRT4_SLW\r
-SCSI_Out__REQ__AG EQU CYREG_PRT0_AG\r
-SCSI_Out__REQ__AMUX EQU CYREG_PRT0_AMUX\r
-SCSI_Out__REQ__BIE EQU CYREG_PRT0_BIE\r
-SCSI_Out__REQ__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
-SCSI_Out__REQ__BYP EQU CYREG_PRT0_BYP\r
-SCSI_Out__REQ__CTL EQU CYREG_PRT0_CTL\r
-SCSI_Out__REQ__DM0 EQU CYREG_PRT0_DM0\r
-SCSI_Out__REQ__DM1 EQU CYREG_PRT0_DM1\r
-SCSI_Out__REQ__DM2 EQU CYREG_PRT0_DM2\r
-SCSI_Out__REQ__DR EQU CYREG_PRT0_DR\r
-SCSI_Out__REQ__INP_DIS EQU CYREG_PRT0_INP_DIS\r
-SCSI_Out__REQ__INTTYPE EQU CYREG_PICU0_INTTYPE3\r
-SCSI_Out__REQ__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
-SCSI_Out__REQ__LCD_EN EQU CYREG_PRT0_LCD_EN\r
-SCSI_Out__REQ__MASK EQU 0x08\r
-SCSI_Out__REQ__PC EQU CYREG_PRT0_PC3\r
-SCSI_Out__REQ__PORT EQU 0\r
-SCSI_Out__REQ__PRT EQU CYREG_PRT0_PRT\r
-SCSI_Out__REQ__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
-SCSI_Out__REQ__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
-SCSI_Out__REQ__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
-SCSI_Out__REQ__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
-SCSI_Out__REQ__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
-SCSI_Out__REQ__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
-SCSI_Out__REQ__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
-SCSI_Out__REQ__PS EQU CYREG_PRT0_PS\r
-SCSI_Out__REQ__SHIFT EQU 3\r
-SCSI_Out__REQ__SLW EQU CYREG_PRT0_SLW\r
-SCSI_Out__RST__AG EQU CYREG_PRT4_AG\r
-SCSI_Out__RST__AMUX EQU CYREG_PRT4_AMUX\r
-SCSI_Out__RST__BIE EQU CYREG_PRT4_BIE\r
-SCSI_Out__RST__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
-SCSI_Out__RST__BYP EQU CYREG_PRT4_BYP\r
-SCSI_Out__RST__CTL EQU CYREG_PRT4_CTL\r
-SCSI_Out__RST__DM0 EQU CYREG_PRT4_DM0\r
-SCSI_Out__RST__DM1 EQU CYREG_PRT4_DM1\r
-SCSI_Out__RST__DM2 EQU CYREG_PRT4_DM2\r
-SCSI_Out__RST__DR EQU CYREG_PRT4_DR\r
-SCSI_Out__RST__INP_DIS EQU CYREG_PRT4_INP_DIS\r
-SCSI_Out__RST__INTTYPE EQU CYREG_PICU4_INTTYPE5\r
-SCSI_Out__RST__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
-SCSI_Out__RST__LCD_EN EQU CYREG_PRT4_LCD_EN\r
-SCSI_Out__RST__MASK EQU 0x20\r
-SCSI_Out__RST__PC EQU CYREG_PRT4_PC5\r
-SCSI_Out__RST__PORT EQU 4\r
-SCSI_Out__RST__PRT EQU CYREG_PRT4_PRT\r
-SCSI_Out__RST__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
-SCSI_Out__RST__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
-SCSI_Out__RST__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
-SCSI_Out__RST__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
-SCSI_Out__RST__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
-SCSI_Out__RST__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
-SCSI_Out__RST__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
-SCSI_Out__RST__PS EQU CYREG_PRT4_PS\r
-SCSI_Out__RST__SHIFT EQU 5\r
-SCSI_Out__RST__SLW EQU CYREG_PRT4_SLW\r
-SCSI_Out__SEL__AG EQU CYREG_PRT0_AG\r
-SCSI_Out__SEL__AMUX EQU CYREG_PRT0_AMUX\r
-SCSI_Out__SEL__BIE EQU CYREG_PRT0_BIE\r
-SCSI_Out__SEL__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
-SCSI_Out__SEL__BYP EQU CYREG_PRT0_BYP\r
-SCSI_Out__SEL__CTL EQU CYREG_PRT0_CTL\r
-SCSI_Out__SEL__DM0 EQU CYREG_PRT0_DM0\r
-SCSI_Out__SEL__DM1 EQU CYREG_PRT0_DM1\r
-SCSI_Out__SEL__DM2 EQU CYREG_PRT0_DM2\r
-SCSI_Out__SEL__DR EQU CYREG_PRT0_DR\r
-SCSI_Out__SEL__INP_DIS EQU CYREG_PRT0_INP_DIS\r
-SCSI_Out__SEL__INTTYPE EQU CYREG_PICU0_INTTYPE7\r
-SCSI_Out__SEL__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
-SCSI_Out__SEL__LCD_EN EQU CYREG_PRT0_LCD_EN\r
-SCSI_Out__SEL__MASK EQU 0x80\r
-SCSI_Out__SEL__PC EQU CYREG_PRT0_PC7\r
-SCSI_Out__SEL__PORT EQU 0\r
-SCSI_Out__SEL__PRT EQU CYREG_PRT0_PRT\r
-SCSI_Out__SEL__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
-SCSI_Out__SEL__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
-SCSI_Out__SEL__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
-SCSI_Out__SEL__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
-SCSI_Out__SEL__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
-SCSI_Out__SEL__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
-SCSI_Out__SEL__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
-SCSI_Out__SEL__PS EQU CYREG_PRT0_PS\r
-SCSI_Out__SEL__SHIFT EQU 7\r
-SCSI_Out__SEL__SLW EQU CYREG_PRT0_SLW\r
-\r
-; SCSI_Out_Bits\r
-SCSI_Out_Bits_Sync_ctrl_reg__0__MASK EQU 0x01\r
-SCSI_Out_Bits_Sync_ctrl_reg__0__POS EQU 0\r
-SCSI_Out_Bits_Sync_ctrl_reg__1__MASK EQU 0x02\r
-SCSI_Out_Bits_Sync_ctrl_reg__1__POS EQU 1\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB14_15_ACTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB14_15_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB14_15_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB14_15_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB14_15_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB14_15_MSK\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB14_15_MSK\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB14_15_MSK\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB14_15_MSK\r
-SCSI_Out_Bits_Sync_ctrl_reg__2__MASK EQU 0x04\r
-SCSI_Out_Bits_Sync_ctrl_reg__2__POS EQU 2\r
-SCSI_Out_Bits_Sync_ctrl_reg__3__MASK EQU 0x08\r
-SCSI_Out_Bits_Sync_ctrl_reg__3__POS EQU 3\r
-SCSI_Out_Bits_Sync_ctrl_reg__4__MASK EQU 0x10\r
-SCSI_Out_Bits_Sync_ctrl_reg__4__POS EQU 4\r
-SCSI_Out_Bits_Sync_ctrl_reg__5__MASK EQU 0x20\r
-SCSI_Out_Bits_Sync_ctrl_reg__5__POS EQU 5\r
-SCSI_Out_Bits_Sync_ctrl_reg__6__MASK EQU 0x40\r
-SCSI_Out_Bits_Sync_ctrl_reg__6__POS EQU 6\r
-SCSI_Out_Bits_Sync_ctrl_reg__7__MASK EQU 0x80\r
-SCSI_Out_Bits_Sync_ctrl_reg__7__POS EQU 7\r
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB14_ACTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB14_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB14_ST_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB14_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB14_ST_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__MASK EQU 0xFF\r
-SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB14_MSK_ACTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB14_MSK_ACTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB14_MSK\r
-\r
-; SCSI_Out_Ctl\r
-SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01\r
-SCSI_Out_Ctl_Sync_ctrl_reg__0__POS EQU 0\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB12_13_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB12_13_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB12_13_MSK\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB12_13_MSK\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK\r
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB12_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB12_ST_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB12_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB12_ST_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__MASK EQU 0x01\r
-SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB12_MSK\r
-\r
-; SCSI_Out_DBx\r
-SCSI_Out_DBx__0__AG EQU CYREG_PRT5_AG\r
-SCSI_Out_DBx__0__AMUX EQU CYREG_PRT5_AMUX\r
-SCSI_Out_DBx__0__BIE EQU CYREG_PRT5_BIE\r
-SCSI_Out_DBx__0__BIT_MASK EQU CYREG_PRT5_BIT_MASK\r
-SCSI_Out_DBx__0__BYP EQU CYREG_PRT5_BYP\r
-SCSI_Out_DBx__0__CTL EQU CYREG_PRT5_CTL\r
-SCSI_Out_DBx__0__DM0 EQU CYREG_PRT5_DM0\r
-SCSI_Out_DBx__0__DM1 EQU CYREG_PRT5_DM1\r
-SCSI_Out_DBx__0__DM2 EQU CYREG_PRT5_DM2\r
-SCSI_Out_DBx__0__DR EQU CYREG_PRT5_DR\r
-SCSI_Out_DBx__0__INP_DIS EQU CYREG_PRT5_INP_DIS\r
-SCSI_Out_DBx__0__INTTYPE EQU CYREG_PICU5_INTTYPE1\r
-SCSI_Out_DBx__0__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG\r
-SCSI_Out_DBx__0__LCD_EN EQU CYREG_PRT5_LCD_EN\r
-SCSI_Out_DBx__0__MASK EQU 0x02\r
-SCSI_Out_DBx__0__PC EQU CYREG_PRT5_PC1\r
-SCSI_Out_DBx__0__PORT EQU 5\r
-SCSI_Out_DBx__0__PRT EQU CYREG_PRT5_PRT\r
-SCSI_Out_DBx__0__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL\r
-SCSI_Out_DBx__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN\r
-SCSI_Out_DBx__0__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0\r
-SCSI_Out_DBx__0__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1\r
-SCSI_Out_DBx__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0\r
-SCSI_Out_DBx__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1\r
-SCSI_Out_DBx__0__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT\r
-SCSI_Out_DBx__0__PS EQU CYREG_PRT5_PS\r
-SCSI_Out_DBx__0__SHIFT EQU 1\r
-SCSI_Out_DBx__0__SLW EQU CYREG_PRT5_SLW\r
-SCSI_Out_DBx__1__AG EQU CYREG_PRT5_AG\r
-SCSI_Out_DBx__1__AMUX EQU CYREG_PRT5_AMUX\r
-SCSI_Out_DBx__1__BIE EQU CYREG_PRT5_BIE\r
-SCSI_Out_DBx__1__BIT_MASK EQU CYREG_PRT5_BIT_MASK\r
-SCSI_Out_DBx__1__BYP EQU CYREG_PRT5_BYP\r
-SCSI_Out_DBx__1__CTL EQU CYREG_PRT5_CTL\r
-SCSI_Out_DBx__1__DM0 EQU CYREG_PRT5_DM0\r
-SCSI_Out_DBx__1__DM1 EQU CYREG_PRT5_DM1\r
-SCSI_Out_DBx__1__DM2 EQU CYREG_PRT5_DM2\r
-SCSI_Out_DBx__1__DR EQU CYREG_PRT5_DR\r
-SCSI_Out_DBx__1__INP_DIS EQU CYREG_PRT5_INP_DIS\r
-SCSI_Out_DBx__1__INTTYPE EQU CYREG_PICU5_INTTYPE0\r
-SCSI_Out_DBx__1__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG\r
-SCSI_Out_DBx__1__LCD_EN EQU CYREG_PRT5_LCD_EN\r
-SCSI_Out_DBx__1__MASK EQU 0x01\r
-SCSI_Out_DBx__1__PC EQU CYREG_PRT5_PC0\r
-SCSI_Out_DBx__1__PORT EQU 5\r
-SCSI_Out_DBx__1__PRT EQU CYREG_PRT5_PRT\r
-SCSI_Out_DBx__1__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL\r
-SCSI_Out_DBx__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN\r
-SCSI_Out_DBx__1__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0\r
-SCSI_Out_DBx__1__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1\r
-SCSI_Out_DBx__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0\r
-SCSI_Out_DBx__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1\r
-SCSI_Out_DBx__1__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT\r
-SCSI_Out_DBx__1__PS EQU CYREG_PRT5_PS\r
-SCSI_Out_DBx__1__SHIFT EQU 0\r
-SCSI_Out_DBx__1__SLW EQU CYREG_PRT5_SLW\r
-SCSI_Out_DBx__2__AG EQU CYREG_PRT6_AG\r
-SCSI_Out_DBx__2__AMUX EQU CYREG_PRT6_AMUX\r
-SCSI_Out_DBx__2__BIE EQU CYREG_PRT6_BIE\r
-SCSI_Out_DBx__2__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
-SCSI_Out_DBx__2__BYP EQU CYREG_PRT6_BYP\r
-SCSI_Out_DBx__2__CTL EQU CYREG_PRT6_CTL\r
-SCSI_Out_DBx__2__DM0 EQU CYREG_PRT6_DM0\r
-SCSI_Out_DBx__2__DM1 EQU CYREG_PRT6_DM1\r
-SCSI_Out_DBx__2__DM2 EQU CYREG_PRT6_DM2\r
-SCSI_Out_DBx__2__DR EQU CYREG_PRT6_DR\r
-SCSI_Out_DBx__2__INP_DIS EQU CYREG_PRT6_INP_DIS\r
-SCSI_Out_DBx__2__INTTYPE EQU CYREG_PICU6_INTTYPE5\r
-SCSI_Out_DBx__2__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
-SCSI_Out_DBx__2__LCD_EN EQU CYREG_PRT6_LCD_EN\r
-SCSI_Out_DBx__2__MASK EQU 0x20\r
-SCSI_Out_DBx__2__PC EQU CYREG_PRT6_PC5\r
-SCSI_Out_DBx__2__PORT EQU 6\r
-SCSI_Out_DBx__2__PRT EQU CYREG_PRT6_PRT\r
-SCSI_Out_DBx__2__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
-SCSI_Out_DBx__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
-SCSI_Out_DBx__2__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
-SCSI_Out_DBx__2__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
-SCSI_Out_DBx__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
-SCSI_Out_DBx__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
-SCSI_Out_DBx__2__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
-SCSI_Out_DBx__2__PS EQU CYREG_PRT6_PS\r
-SCSI_Out_DBx__2__SHIFT EQU 5\r
-SCSI_Out_DBx__2__SLW EQU CYREG_PRT6_SLW\r
-SCSI_Out_DBx__3__AG EQU CYREG_PRT6_AG\r
-SCSI_Out_DBx__3__AMUX EQU CYREG_PRT6_AMUX\r
-SCSI_Out_DBx__3__BIE EQU CYREG_PRT6_BIE\r
-SCSI_Out_DBx__3__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
-SCSI_Out_DBx__3__BYP EQU CYREG_PRT6_BYP\r
-SCSI_Out_DBx__3__CTL EQU CYREG_PRT6_CTL\r
-SCSI_Out_DBx__3__DM0 EQU CYREG_PRT6_DM0\r
-SCSI_Out_DBx__3__DM1 EQU CYREG_PRT6_DM1\r
-SCSI_Out_DBx__3__DM2 EQU CYREG_PRT6_DM2\r
-SCSI_Out_DBx__3__DR EQU CYREG_PRT6_DR\r
-SCSI_Out_DBx__3__INP_DIS EQU CYREG_PRT6_INP_DIS\r
-SCSI_Out_DBx__3__INTTYPE EQU CYREG_PICU6_INTTYPE4\r
-SCSI_Out_DBx__3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
-SCSI_Out_DBx__3__LCD_EN EQU CYREG_PRT6_LCD_EN\r
-SCSI_Out_DBx__3__MASK EQU 0x10\r
-SCSI_Out_DBx__3__PC EQU CYREG_PRT6_PC4\r
-SCSI_Out_DBx__3__PORT EQU 6\r
-SCSI_Out_DBx__3__PRT EQU CYREG_PRT6_PRT\r
-SCSI_Out_DBx__3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
-SCSI_Out_DBx__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
-SCSI_Out_DBx__3__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
-SCSI_Out_DBx__3__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
-SCSI_Out_DBx__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
-SCSI_Out_DBx__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
-SCSI_Out_DBx__3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
-SCSI_Out_DBx__3__PS EQU CYREG_PRT6_PS\r
-SCSI_Out_DBx__3__SHIFT EQU 4\r
-SCSI_Out_DBx__3__SLW EQU CYREG_PRT6_SLW\r
-SCSI_Out_DBx__4__AG EQU CYREG_PRT2_AG\r
-SCSI_Out_DBx__4__AMUX EQU CYREG_PRT2_AMUX\r
-SCSI_Out_DBx__4__BIE EQU CYREG_PRT2_BIE\r
-SCSI_Out_DBx__4__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
-SCSI_Out_DBx__4__BYP EQU CYREG_PRT2_BYP\r
-SCSI_Out_DBx__4__CTL EQU CYREG_PRT2_CTL\r
-SCSI_Out_DBx__4__DM0 EQU CYREG_PRT2_DM0\r
-SCSI_Out_DBx__4__DM1 EQU CYREG_PRT2_DM1\r
-SCSI_Out_DBx__4__DM2 EQU CYREG_PRT2_DM2\r
-SCSI_Out_DBx__4__DR EQU CYREG_PRT2_DR\r
-SCSI_Out_DBx__4__INP_DIS EQU CYREG_PRT2_INP_DIS\r
-SCSI_Out_DBx__4__INTTYPE EQU CYREG_PICU2_INTTYPE7\r
-SCSI_Out_DBx__4__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
-SCSI_Out_DBx__4__LCD_EN EQU CYREG_PRT2_LCD_EN\r
-SCSI_Out_DBx__4__MASK EQU 0x80\r
-SCSI_Out_DBx__4__PC EQU CYREG_PRT2_PC7\r
-SCSI_Out_DBx__4__PORT EQU 2\r
-SCSI_Out_DBx__4__PRT EQU CYREG_PRT2_PRT\r
-SCSI_Out_DBx__4__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
-SCSI_Out_DBx__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
-SCSI_Out_DBx__4__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
-SCSI_Out_DBx__4__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
-SCSI_Out_DBx__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
-SCSI_Out_DBx__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
-SCSI_Out_DBx__4__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
-SCSI_Out_DBx__4__PS EQU CYREG_PRT2_PS\r
-SCSI_Out_DBx__4__SHIFT EQU 7\r
-SCSI_Out_DBx__4__SLW EQU CYREG_PRT2_SLW\r
-SCSI_Out_DBx__5__AG EQU CYREG_PRT2_AG\r
-SCSI_Out_DBx__5__AMUX EQU CYREG_PRT2_AMUX\r
-SCSI_Out_DBx__5__BIE EQU CYREG_PRT2_BIE\r
-SCSI_Out_DBx__5__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
-SCSI_Out_DBx__5__BYP EQU CYREG_PRT2_BYP\r
-SCSI_Out_DBx__5__CTL EQU CYREG_PRT2_CTL\r
-SCSI_Out_DBx__5__DM0 EQU CYREG_PRT2_DM0\r
-SCSI_Out_DBx__5__DM1 EQU CYREG_PRT2_DM1\r
-SCSI_Out_DBx__5__DM2 EQU CYREG_PRT2_DM2\r
-SCSI_Out_DBx__5__DR EQU CYREG_PRT2_DR\r
-SCSI_Out_DBx__5__INP_DIS EQU CYREG_PRT2_INP_DIS\r
-SCSI_Out_DBx__5__INTTYPE EQU CYREG_PICU2_INTTYPE6\r
-SCSI_Out_DBx__5__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
-SCSI_Out_DBx__5__LCD_EN EQU CYREG_PRT2_LCD_EN\r
-SCSI_Out_DBx__5__MASK EQU 0x40\r
-SCSI_Out_DBx__5__PC EQU CYREG_PRT2_PC6\r
-SCSI_Out_DBx__5__PORT EQU 2\r
-SCSI_Out_DBx__5__PRT EQU CYREG_PRT2_PRT\r
-SCSI_Out_DBx__5__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
-SCSI_Out_DBx__5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
-SCSI_Out_DBx__5__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
-SCSI_Out_DBx__5__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
-SCSI_Out_DBx__5__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
-SCSI_Out_DBx__5__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
-SCSI_Out_DBx__5__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
-SCSI_Out_DBx__5__PS EQU CYREG_PRT2_PS\r
-SCSI_Out_DBx__5__SHIFT EQU 6\r
-SCSI_Out_DBx__5__SLW EQU CYREG_PRT2_SLW\r
-SCSI_Out_DBx__6__AG EQU CYREG_PRT2_AG\r
-SCSI_Out_DBx__6__AMUX EQU CYREG_PRT2_AMUX\r
-SCSI_Out_DBx__6__BIE EQU CYREG_PRT2_BIE\r
-SCSI_Out_DBx__6__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
-SCSI_Out_DBx__6__BYP EQU CYREG_PRT2_BYP\r
-SCSI_Out_DBx__6__CTL EQU CYREG_PRT2_CTL\r
-SCSI_Out_DBx__6__DM0 EQU CYREG_PRT2_DM0\r
-SCSI_Out_DBx__6__DM1 EQU CYREG_PRT2_DM1\r
-SCSI_Out_DBx__6__DM2 EQU CYREG_PRT2_DM2\r
-SCSI_Out_DBx__6__DR EQU CYREG_PRT2_DR\r
-SCSI_Out_DBx__6__INP_DIS EQU CYREG_PRT2_INP_DIS\r
-SCSI_Out_DBx__6__INTTYPE EQU CYREG_PICU2_INTTYPE3\r
-SCSI_Out_DBx__6__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
-SCSI_Out_DBx__6__LCD_EN EQU CYREG_PRT2_LCD_EN\r
-SCSI_Out_DBx__6__MASK EQU 0x08\r
-SCSI_Out_DBx__6__PC EQU CYREG_PRT2_PC3\r
-SCSI_Out_DBx__6__PORT EQU 2\r
-SCSI_Out_DBx__6__PRT EQU CYREG_PRT2_PRT\r
-SCSI_Out_DBx__6__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
-SCSI_Out_DBx__6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
-SCSI_Out_DBx__6__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
-SCSI_Out_DBx__6__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
-SCSI_Out_DBx__6__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
-SCSI_Out_DBx__6__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
-SCSI_Out_DBx__6__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
-SCSI_Out_DBx__6__PS EQU CYREG_PRT2_PS\r
-SCSI_Out_DBx__6__SHIFT EQU 3\r
-SCSI_Out_DBx__6__SLW EQU CYREG_PRT2_SLW\r
-SCSI_Out_DBx__7__AG EQU CYREG_PRT2_AG\r
-SCSI_Out_DBx__7__AMUX EQU CYREG_PRT2_AMUX\r
-SCSI_Out_DBx__7__BIE EQU CYREG_PRT2_BIE\r
-SCSI_Out_DBx__7__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
-SCSI_Out_DBx__7__BYP EQU CYREG_PRT2_BYP\r
-SCSI_Out_DBx__7__CTL EQU CYREG_PRT2_CTL\r
-SCSI_Out_DBx__7__DM0 EQU CYREG_PRT2_DM0\r
-SCSI_Out_DBx__7__DM1 EQU CYREG_PRT2_DM1\r
-SCSI_Out_DBx__7__DM2 EQU CYREG_PRT2_DM2\r
-SCSI_Out_DBx__7__DR EQU CYREG_PRT2_DR\r
-SCSI_Out_DBx__7__INP_DIS EQU CYREG_PRT2_INP_DIS\r
-SCSI_Out_DBx__7__INTTYPE EQU CYREG_PICU2_INTTYPE2\r
-SCSI_Out_DBx__7__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
-SCSI_Out_DBx__7__LCD_EN EQU CYREG_PRT2_LCD_EN\r
-SCSI_Out_DBx__7__MASK EQU 0x04\r
-SCSI_Out_DBx__7__PC EQU CYREG_PRT2_PC2\r
-SCSI_Out_DBx__7__PORT EQU 2\r
-SCSI_Out_DBx__7__PRT EQU CYREG_PRT2_PRT\r
-SCSI_Out_DBx__7__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
-SCSI_Out_DBx__7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
-SCSI_Out_DBx__7__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
-SCSI_Out_DBx__7__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
-SCSI_Out_DBx__7__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
-SCSI_Out_DBx__7__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
-SCSI_Out_DBx__7__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
-SCSI_Out_DBx__7__PS EQU CYREG_PRT2_PS\r
-SCSI_Out_DBx__7__SHIFT EQU 2\r
-SCSI_Out_DBx__7__SLW EQU CYREG_PRT2_SLW\r
-SCSI_Out_DBx__DB0__AG EQU CYREG_PRT5_AG\r
-SCSI_Out_DBx__DB0__AMUX EQU CYREG_PRT5_AMUX\r
-SCSI_Out_DBx__DB0__BIE EQU CYREG_PRT5_BIE\r
-SCSI_Out_DBx__DB0__BIT_MASK EQU CYREG_PRT5_BIT_MASK\r
-SCSI_Out_DBx__DB0__BYP EQU CYREG_PRT5_BYP\r
-SCSI_Out_DBx__DB0__CTL EQU CYREG_PRT5_CTL\r
-SCSI_Out_DBx__DB0__DM0 EQU CYREG_PRT5_DM0\r
-SCSI_Out_DBx__DB0__DM1 EQU CYREG_PRT5_DM1\r
-SCSI_Out_DBx__DB0__DM2 EQU CYREG_PRT5_DM2\r
-SCSI_Out_DBx__DB0__DR EQU CYREG_PRT5_DR\r
-SCSI_Out_DBx__DB0__INP_DIS EQU CYREG_PRT5_INP_DIS\r
-SCSI_Out_DBx__DB0__INTTYPE EQU CYREG_PICU5_INTTYPE1\r
-SCSI_Out_DBx__DB0__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG\r
-SCSI_Out_DBx__DB0__LCD_EN EQU CYREG_PRT5_LCD_EN\r
-SCSI_Out_DBx__DB0__MASK EQU 0x02\r
-SCSI_Out_DBx__DB0__PC EQU CYREG_PRT5_PC1\r
-SCSI_Out_DBx__DB0__PORT EQU 5\r
-SCSI_Out_DBx__DB0__PRT EQU CYREG_PRT5_PRT\r
-SCSI_Out_DBx__DB0__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL\r
-SCSI_Out_DBx__DB0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN\r
-SCSI_Out_DBx__DB0__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0\r
-SCSI_Out_DBx__DB0__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1\r
-SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0\r
-SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1\r
-SCSI_Out_DBx__DB0__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT\r
-SCSI_Out_DBx__DB0__PS EQU CYREG_PRT5_PS\r
-SCSI_Out_DBx__DB0__SHIFT EQU 1\r
-SCSI_Out_DBx__DB0__SLW EQU CYREG_PRT5_SLW\r
-SCSI_Out_DBx__DB1__AG EQU CYREG_PRT5_AG\r
-SCSI_Out_DBx__DB1__AMUX EQU CYREG_PRT5_AMUX\r
-SCSI_Out_DBx__DB1__BIE EQU CYREG_PRT5_BIE\r
-SCSI_Out_DBx__DB1__BIT_MASK EQU CYREG_PRT5_BIT_MASK\r
-SCSI_Out_DBx__DB1__BYP EQU CYREG_PRT5_BYP\r
-SCSI_Out_DBx__DB1__CTL EQU CYREG_PRT5_CTL\r
-SCSI_Out_DBx__DB1__DM0 EQU CYREG_PRT5_DM0\r
-SCSI_Out_DBx__DB1__DM1 EQU CYREG_PRT5_DM1\r
-SCSI_Out_DBx__DB1__DM2 EQU CYREG_PRT5_DM2\r
-SCSI_Out_DBx__DB1__DR EQU CYREG_PRT5_DR\r
-SCSI_Out_DBx__DB1__INP_DIS EQU CYREG_PRT5_INP_DIS\r
-SCSI_Out_DBx__DB1__INTTYPE EQU CYREG_PICU5_INTTYPE0\r
-SCSI_Out_DBx__DB1__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG\r
-SCSI_Out_DBx__DB1__LCD_EN EQU CYREG_PRT5_LCD_EN\r
-SCSI_Out_DBx__DB1__MASK EQU 0x01\r
-SCSI_Out_DBx__DB1__PC EQU CYREG_PRT5_PC0\r
-SCSI_Out_DBx__DB1__PORT EQU 5\r
-SCSI_Out_DBx__DB1__PRT EQU CYREG_PRT5_PRT\r
-SCSI_Out_DBx__DB1__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL\r
-SCSI_Out_DBx__DB1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN\r
-SCSI_Out_DBx__DB1__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0\r
-SCSI_Out_DBx__DB1__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1\r
-SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0\r
-SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1\r
-SCSI_Out_DBx__DB1__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT\r
-SCSI_Out_DBx__DB1__PS EQU CYREG_PRT5_PS\r
-SCSI_Out_DBx__DB1__SHIFT EQU 0\r
-SCSI_Out_DBx__DB1__SLW EQU CYREG_PRT5_SLW\r
-SCSI_Out_DBx__DB2__AG EQU CYREG_PRT6_AG\r
-SCSI_Out_DBx__DB2__AMUX EQU CYREG_PRT6_AMUX\r
-SCSI_Out_DBx__DB2__BIE EQU CYREG_PRT6_BIE\r
-SCSI_Out_DBx__DB2__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
-SCSI_Out_DBx__DB2__BYP EQU CYREG_PRT6_BYP\r
-SCSI_Out_DBx__DB2__CTL EQU CYREG_PRT6_CTL\r
-SCSI_Out_DBx__DB2__DM0 EQU CYREG_PRT6_DM0\r
-SCSI_Out_DBx__DB2__DM1 EQU CYREG_PRT6_DM1\r
-SCSI_Out_DBx__DB2__DM2 EQU CYREG_PRT6_DM2\r
-SCSI_Out_DBx__DB2__DR EQU CYREG_PRT6_DR\r
-SCSI_Out_DBx__DB2__INP_DIS EQU CYREG_PRT6_INP_DIS\r
-SCSI_Out_DBx__DB2__INTTYPE EQU CYREG_PICU6_INTTYPE5\r
-SCSI_Out_DBx__DB2__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
-SCSI_Out_DBx__DB2__LCD_EN EQU CYREG_PRT6_LCD_EN\r
-SCSI_Out_DBx__DB2__MASK EQU 0x20\r
-SCSI_Out_DBx__DB2__PC EQU CYREG_PRT6_PC5\r
-SCSI_Out_DBx__DB2__PORT EQU 6\r
-SCSI_Out_DBx__DB2__PRT EQU CYREG_PRT6_PRT\r
-SCSI_Out_DBx__DB2__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
-SCSI_Out_DBx__DB2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
-SCSI_Out_DBx__DB2__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
-SCSI_Out_DBx__DB2__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
-SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
-SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
-SCSI_Out_DBx__DB2__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
-SCSI_Out_DBx__DB2__PS EQU CYREG_PRT6_PS\r
-SCSI_Out_DBx__DB2__SHIFT EQU 5\r
-SCSI_Out_DBx__DB2__SLW EQU CYREG_PRT6_SLW\r
-SCSI_Out_DBx__DB3__AG EQU CYREG_PRT6_AG\r
-SCSI_Out_DBx__DB3__AMUX EQU CYREG_PRT6_AMUX\r
-SCSI_Out_DBx__DB3__BIE EQU CYREG_PRT6_BIE\r
-SCSI_Out_DBx__DB3__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
-SCSI_Out_DBx__DB3__BYP EQU CYREG_PRT6_BYP\r
-SCSI_Out_DBx__DB3__CTL EQU CYREG_PRT6_CTL\r
-SCSI_Out_DBx__DB3__DM0 EQU CYREG_PRT6_DM0\r
-SCSI_Out_DBx__DB3__DM1 EQU CYREG_PRT6_DM1\r
-SCSI_Out_DBx__DB3__DM2 EQU CYREG_PRT6_DM2\r
-SCSI_Out_DBx__DB3__DR EQU CYREG_PRT6_DR\r
-SCSI_Out_DBx__DB3__INP_DIS EQU CYREG_PRT6_INP_DIS\r
-SCSI_Out_DBx__DB3__INTTYPE EQU CYREG_PICU6_INTTYPE4\r
-SCSI_Out_DBx__DB3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
-SCSI_Out_DBx__DB3__LCD_EN EQU CYREG_PRT6_LCD_EN\r
-SCSI_Out_DBx__DB3__MASK EQU 0x10\r
-SCSI_Out_DBx__DB3__PC EQU CYREG_PRT6_PC4\r
-SCSI_Out_DBx__DB3__PORT EQU 6\r
-SCSI_Out_DBx__DB3__PRT EQU CYREG_PRT6_PRT\r
-SCSI_Out_DBx__DB3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
-SCSI_Out_DBx__DB3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
-SCSI_Out_DBx__DB3__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
-SCSI_Out_DBx__DB3__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
-SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
-SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
-SCSI_Out_DBx__DB3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
-SCSI_Out_DBx__DB3__PS EQU CYREG_PRT6_PS\r
-SCSI_Out_DBx__DB3__SHIFT EQU 4\r
-SCSI_Out_DBx__DB3__SLW EQU CYREG_PRT6_SLW\r
-SCSI_Out_DBx__DB4__AG EQU CYREG_PRT2_AG\r
-SCSI_Out_DBx__DB4__AMUX EQU CYREG_PRT2_AMUX\r
-SCSI_Out_DBx__DB4__BIE EQU CYREG_PRT2_BIE\r
-SCSI_Out_DBx__DB4__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
-SCSI_Out_DBx__DB4__BYP EQU CYREG_PRT2_BYP\r
-SCSI_Out_DBx__DB4__CTL EQU CYREG_PRT2_CTL\r
-SCSI_Out_DBx__DB4__DM0 EQU CYREG_PRT2_DM0\r
-SCSI_Out_DBx__DB4__DM1 EQU CYREG_PRT2_DM1\r
-SCSI_Out_DBx__DB4__DM2 EQU CYREG_PRT2_DM2\r
-SCSI_Out_DBx__DB4__DR EQU CYREG_PRT2_DR\r
-SCSI_Out_DBx__DB4__INP_DIS EQU CYREG_PRT2_INP_DIS\r
-SCSI_Out_DBx__DB4__INTTYPE EQU CYREG_PICU2_INTTYPE7\r
-SCSI_Out_DBx__DB4__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
-SCSI_Out_DBx__DB4__LCD_EN EQU CYREG_PRT2_LCD_EN\r
-SCSI_Out_DBx__DB4__MASK EQU 0x80\r
-SCSI_Out_DBx__DB4__PC EQU CYREG_PRT2_PC7\r
-SCSI_Out_DBx__DB4__PORT EQU 2\r
-SCSI_Out_DBx__DB4__PRT EQU CYREG_PRT2_PRT\r
-SCSI_Out_DBx__DB4__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
-SCSI_Out_DBx__DB4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
-SCSI_Out_DBx__DB4__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
-SCSI_Out_DBx__DB4__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
-SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
-SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
-SCSI_Out_DBx__DB4__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
-SCSI_Out_DBx__DB4__PS EQU CYREG_PRT2_PS\r
-SCSI_Out_DBx__DB4__SHIFT EQU 7\r
-SCSI_Out_DBx__DB4__SLW EQU CYREG_PRT2_SLW\r
-SCSI_Out_DBx__DB5__AG EQU CYREG_PRT2_AG\r
-SCSI_Out_DBx__DB5__AMUX EQU CYREG_PRT2_AMUX\r
-SCSI_Out_DBx__DB5__BIE EQU CYREG_PRT2_BIE\r
-SCSI_Out_DBx__DB5__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
-SCSI_Out_DBx__DB5__BYP EQU CYREG_PRT2_BYP\r
-SCSI_Out_DBx__DB5__CTL EQU CYREG_PRT2_CTL\r
-SCSI_Out_DBx__DB5__DM0 EQU CYREG_PRT2_DM0\r
-SCSI_Out_DBx__DB5__DM1 EQU CYREG_PRT2_DM1\r
-SCSI_Out_DBx__DB5__DM2 EQU CYREG_PRT2_DM2\r
-SCSI_Out_DBx__DB5__DR EQU CYREG_PRT2_DR\r
-SCSI_Out_DBx__DB5__INP_DIS EQU CYREG_PRT2_INP_DIS\r
-SCSI_Out_DBx__DB5__INTTYPE EQU CYREG_PICU2_INTTYPE6\r
-SCSI_Out_DBx__DB5__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
-SCSI_Out_DBx__DB5__LCD_EN EQU CYREG_PRT2_LCD_EN\r
-SCSI_Out_DBx__DB5__MASK EQU 0x40\r
-SCSI_Out_DBx__DB5__PC EQU CYREG_PRT2_PC6\r
-SCSI_Out_DBx__DB5__PORT EQU 2\r
-SCSI_Out_DBx__DB5__PRT EQU CYREG_PRT2_PRT\r
-SCSI_Out_DBx__DB5__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
-SCSI_Out_DBx__DB5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
-SCSI_Out_DBx__DB5__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
-SCSI_Out_DBx__DB5__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
-SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
-SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
-SCSI_Out_DBx__DB5__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
-SCSI_Out_DBx__DB5__PS EQU CYREG_PRT2_PS\r
-SCSI_Out_DBx__DB5__SHIFT EQU 6\r
-SCSI_Out_DBx__DB5__SLW EQU CYREG_PRT2_SLW\r
-SCSI_Out_DBx__DB6__AG EQU CYREG_PRT2_AG\r
-SCSI_Out_DBx__DB6__AMUX EQU CYREG_PRT2_AMUX\r
-SCSI_Out_DBx__DB6__BIE EQU CYREG_PRT2_BIE\r
-SCSI_Out_DBx__DB6__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
-SCSI_Out_DBx__DB6__BYP EQU CYREG_PRT2_BYP\r
-SCSI_Out_DBx__DB6__CTL EQU CYREG_PRT2_CTL\r
-SCSI_Out_DBx__DB6__DM0 EQU CYREG_PRT2_DM0\r
-SCSI_Out_DBx__DB6__DM1 EQU CYREG_PRT2_DM1\r
-SCSI_Out_DBx__DB6__DM2 EQU CYREG_PRT2_DM2\r
-SCSI_Out_DBx__DB6__DR EQU CYREG_PRT2_DR\r
-SCSI_Out_DBx__DB6__INP_DIS EQU CYREG_PRT2_INP_DIS\r
-SCSI_Out_DBx__DB6__INTTYPE EQU CYREG_PICU2_INTTYPE3\r
-SCSI_Out_DBx__DB6__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
-SCSI_Out_DBx__DB6__LCD_EN EQU CYREG_PRT2_LCD_EN\r
-SCSI_Out_DBx__DB6__MASK EQU 0x08\r
-SCSI_Out_DBx__DB6__PC EQU CYREG_PRT2_PC3\r
-SCSI_Out_DBx__DB6__PORT EQU 2\r
-SCSI_Out_DBx__DB6__PRT EQU CYREG_PRT2_PRT\r
-SCSI_Out_DBx__DB6__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
-SCSI_Out_DBx__DB6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
-SCSI_Out_DBx__DB6__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
-SCSI_Out_DBx__DB6__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
-SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
-SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
-SCSI_Out_DBx__DB6__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
-SCSI_Out_DBx__DB6__PS EQU CYREG_PRT2_PS\r
-SCSI_Out_DBx__DB6__SHIFT EQU 3\r
-SCSI_Out_DBx__DB6__SLW EQU CYREG_PRT2_SLW\r
-SCSI_Out_DBx__DB7__AG EQU CYREG_PRT2_AG\r
-SCSI_Out_DBx__DB7__AMUX EQU CYREG_PRT2_AMUX\r
-SCSI_Out_DBx__DB7__BIE EQU CYREG_PRT2_BIE\r
-SCSI_Out_DBx__DB7__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
-SCSI_Out_DBx__DB7__BYP EQU CYREG_PRT2_BYP\r
-SCSI_Out_DBx__DB7__CTL EQU CYREG_PRT2_CTL\r
-SCSI_Out_DBx__DB7__DM0 EQU CYREG_PRT2_DM0\r
-SCSI_Out_DBx__DB7__DM1 EQU CYREG_PRT2_DM1\r
-SCSI_Out_DBx__DB7__DM2 EQU CYREG_PRT2_DM2\r
-SCSI_Out_DBx__DB7__DR EQU CYREG_PRT2_DR\r
-SCSI_Out_DBx__DB7__INP_DIS EQU CYREG_PRT2_INP_DIS\r
-SCSI_Out_DBx__DB7__INTTYPE EQU CYREG_PICU2_INTTYPE2\r
-SCSI_Out_DBx__DB7__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
-SCSI_Out_DBx__DB7__LCD_EN EQU CYREG_PRT2_LCD_EN\r
-SCSI_Out_DBx__DB7__MASK EQU 0x04\r
-SCSI_Out_DBx__DB7__PC EQU CYREG_PRT2_PC2\r
-SCSI_Out_DBx__DB7__PORT EQU 2\r
-SCSI_Out_DBx__DB7__PRT EQU CYREG_PRT2_PRT\r
-SCSI_Out_DBx__DB7__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
-SCSI_Out_DBx__DB7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
-SCSI_Out_DBx__DB7__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
-SCSI_Out_DBx__DB7__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
-SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
-SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
-SCSI_Out_DBx__DB7__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
-SCSI_Out_DBx__DB7__PS EQU CYREG_PRT2_PS\r
-SCSI_Out_DBx__DB7__SHIFT EQU 2\r
-SCSI_Out_DBx__DB7__SLW EQU CYREG_PRT2_SLW\r
-\r
-; SD_RX_DMA\r
-SD_RX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0\r
-SD_RX_DMA__DRQ_NUMBER EQU 2\r
-SD_RX_DMA__NUMBEROF_TDS EQU 0\r
-SD_RX_DMA__PRIORITY EQU 0\r
-SD_RX_DMA__TERMIN_EN EQU 0\r
-SD_RX_DMA__TERMIN_SEL EQU 0\r
-SD_RX_DMA__TERMOUT0_EN EQU 1\r
-SD_RX_DMA__TERMOUT0_SEL EQU 2\r
-SD_RX_DMA__TERMOUT1_EN EQU 0\r
-SD_RX_DMA__TERMOUT1_SEL EQU 0\r
-\r
-; SD_RX_DMA_COMPLETE\r
-SD_RX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
-SD_RX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
-SD_RX_DMA_COMPLETE__INTC_MASK EQU 0x20\r
-SD_RX_DMA_COMPLETE__INTC_NUMBER EQU 5\r
-SD_RX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7\r
-SD_RX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_5\r
-SD_RX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
-SD_RX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
-\r
-; SD_TX_DMA\r
-SD_TX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0\r
-SD_TX_DMA__DRQ_NUMBER EQU 3\r
-SD_TX_DMA__NUMBEROF_TDS EQU 0\r
-SD_TX_DMA__PRIORITY EQU 1\r
-SD_TX_DMA__TERMIN_EN EQU 0\r
-SD_TX_DMA__TERMIN_SEL EQU 0\r
-SD_TX_DMA__TERMOUT0_EN EQU 1\r
-SD_TX_DMA__TERMOUT0_SEL EQU 3\r
-SD_TX_DMA__TERMOUT1_EN EQU 0\r
-SD_TX_DMA__TERMOUT1_SEL EQU 0\r
-\r
-; SD_TX_DMA_COMPLETE\r
-SD_TX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
-SD_TX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
-SD_TX_DMA_COMPLETE__INTC_MASK EQU 0x40\r
-SD_TX_DMA_COMPLETE__INTC_NUMBER EQU 6\r
-SD_TX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7\r
-SD_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_6\r
-SD_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
-SD_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
+; SCSI_In\r
+SCSI_In__0__AG EQU CYREG_PRT2_AG\r
+SCSI_In__0__AMUX EQU CYREG_PRT2_AMUX\r
+SCSI_In__0__BIE EQU CYREG_PRT2_BIE\r
+SCSI_In__0__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
+SCSI_In__0__BYP EQU CYREG_PRT2_BYP\r
+SCSI_In__0__CTL EQU CYREG_PRT2_CTL\r
+SCSI_In__0__DM0 EQU CYREG_PRT2_DM0\r
+SCSI_In__0__DM1 EQU CYREG_PRT2_DM1\r
+SCSI_In__0__DM2 EQU CYREG_PRT2_DM2\r
+SCSI_In__0__DR EQU CYREG_PRT2_DR\r
+SCSI_In__0__INP_DIS EQU CYREG_PRT2_INP_DIS\r
+SCSI_In__0__INTTYPE EQU CYREG_PICU2_INTTYPE1\r
+SCSI_In__0__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
+SCSI_In__0__LCD_EN EQU CYREG_PRT2_LCD_EN\r
+SCSI_In__0__MASK EQU 0x02\r
+SCSI_In__0__PC EQU CYREG_PRT2_PC1\r
+SCSI_In__0__PORT EQU 2\r
+SCSI_In__0__PRT EQU CYREG_PRT2_PRT\r
+SCSI_In__0__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
+SCSI_In__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
+SCSI_In__0__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
+SCSI_In__0__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
+SCSI_In__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
+SCSI_In__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
+SCSI_In__0__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
+SCSI_In__0__PS EQU CYREG_PRT2_PS\r
+SCSI_In__0__SHIFT EQU 1\r
+SCSI_In__0__SLW EQU CYREG_PRT2_SLW\r
+SCSI_In__1__AG EQU CYREG_PRT4_AG\r
+SCSI_In__1__AMUX EQU CYREG_PRT4_AMUX\r
+SCSI_In__1__BIE EQU CYREG_PRT4_BIE\r
+SCSI_In__1__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
+SCSI_In__1__BYP EQU CYREG_PRT4_BYP\r
+SCSI_In__1__CTL EQU CYREG_PRT4_CTL\r
+SCSI_In__1__DM0 EQU CYREG_PRT4_DM0\r
+SCSI_In__1__DM1 EQU CYREG_PRT4_DM1\r
+SCSI_In__1__DM2 EQU CYREG_PRT4_DM2\r
+SCSI_In__1__DR EQU CYREG_PRT4_DR\r
+SCSI_In__1__INP_DIS EQU CYREG_PRT4_INP_DIS\r
+SCSI_In__1__INTTYPE EQU CYREG_PICU4_INTTYPE6\r
+SCSI_In__1__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
+SCSI_In__1__LCD_EN EQU CYREG_PRT4_LCD_EN\r
+SCSI_In__1__MASK EQU 0x40\r
+SCSI_In__1__PC EQU CYREG_PRT4_PC6\r
+SCSI_In__1__PORT EQU 4\r
+SCSI_In__1__PRT EQU CYREG_PRT4_PRT\r
+SCSI_In__1__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
+SCSI_In__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
+SCSI_In__1__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
+SCSI_In__1__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
+SCSI_In__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
+SCSI_In__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
+SCSI_In__1__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
+SCSI_In__1__PS EQU CYREG_PRT4_PS\r
+SCSI_In__1__SHIFT EQU 6\r
+SCSI_In__1__SLW EQU CYREG_PRT4_SLW\r
+SCSI_In__2__AG EQU CYREG_PRT4_AG\r
+SCSI_In__2__AMUX EQU CYREG_PRT4_AMUX\r
+SCSI_In__2__BIE EQU CYREG_PRT4_BIE\r
+SCSI_In__2__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
+SCSI_In__2__BYP EQU CYREG_PRT4_BYP\r
+SCSI_In__2__CTL EQU CYREG_PRT4_CTL\r
+SCSI_In__2__DM0 EQU CYREG_PRT4_DM0\r
+SCSI_In__2__DM1 EQU CYREG_PRT4_DM1\r
+SCSI_In__2__DM2 EQU CYREG_PRT4_DM2\r
+SCSI_In__2__DR EQU CYREG_PRT4_DR\r
+SCSI_In__2__INP_DIS EQU CYREG_PRT4_INP_DIS\r
+SCSI_In__2__INTTYPE EQU CYREG_PICU4_INTTYPE2\r
+SCSI_In__2__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
+SCSI_In__2__LCD_EN EQU CYREG_PRT4_LCD_EN\r
+SCSI_In__2__MASK EQU 0x04\r
+SCSI_In__2__PC EQU CYREG_PRT4_PC2\r
+SCSI_In__2__PORT EQU 4\r
+SCSI_In__2__PRT EQU CYREG_PRT4_PRT\r
+SCSI_In__2__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
+SCSI_In__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
+SCSI_In__2__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
+SCSI_In__2__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
+SCSI_In__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
+SCSI_In__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
+SCSI_In__2__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
+SCSI_In__2__PS EQU CYREG_PRT4_PS\r
+SCSI_In__2__SHIFT EQU 2\r
+SCSI_In__2__SLW EQU CYREG_PRT4_SLW\r
+SCSI_In__3__AG EQU CYREG_PRT0_AG\r
+SCSI_In__3__AMUX EQU CYREG_PRT0_AMUX\r
+SCSI_In__3__BIE EQU CYREG_PRT0_BIE\r
+SCSI_In__3__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
+SCSI_In__3__BYP EQU CYREG_PRT0_BYP\r
+SCSI_In__3__CTL EQU CYREG_PRT0_CTL\r
+SCSI_In__3__DM0 EQU CYREG_PRT0_DM0\r
+SCSI_In__3__DM1 EQU CYREG_PRT0_DM1\r
+SCSI_In__3__DM2 EQU CYREG_PRT0_DM2\r
+SCSI_In__3__DR EQU CYREG_PRT0_DR\r
+SCSI_In__3__INP_DIS EQU CYREG_PRT0_INP_DIS\r
+SCSI_In__3__INTTYPE EQU CYREG_PICU0_INTTYPE5\r
+SCSI_In__3__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
+SCSI_In__3__LCD_EN EQU CYREG_PRT0_LCD_EN\r
+SCSI_In__3__MASK EQU 0x20\r
+SCSI_In__3__PC EQU CYREG_PRT0_PC5\r
+SCSI_In__3__PORT EQU 0\r
+SCSI_In__3__PRT EQU CYREG_PRT0_PRT\r
+SCSI_In__3__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
+SCSI_In__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
+SCSI_In__3__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
+SCSI_In__3__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
+SCSI_In__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
+SCSI_In__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
+SCSI_In__3__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
+SCSI_In__3__PS EQU CYREG_PRT0_PS\r
+SCSI_In__3__SHIFT EQU 5\r
+SCSI_In__3__SLW EQU CYREG_PRT0_SLW\r
+SCSI_In__4__AG EQU CYREG_PRT0_AG\r
+SCSI_In__4__AMUX EQU CYREG_PRT0_AMUX\r
+SCSI_In__4__BIE EQU CYREG_PRT0_BIE\r
+SCSI_In__4__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
+SCSI_In__4__BYP EQU CYREG_PRT0_BYP\r
+SCSI_In__4__CTL EQU CYREG_PRT0_CTL\r
+SCSI_In__4__DM0 EQU CYREG_PRT0_DM0\r
+SCSI_In__4__DM1 EQU CYREG_PRT0_DM1\r
+SCSI_In__4__DM2 EQU CYREG_PRT0_DM2\r
+SCSI_In__4__DR EQU CYREG_PRT0_DR\r
+SCSI_In__4__INP_DIS EQU CYREG_PRT0_INP_DIS\r
+SCSI_In__4__INTTYPE EQU CYREG_PICU0_INTTYPE4\r
+SCSI_In__4__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
+SCSI_In__4__LCD_EN EQU CYREG_PRT0_LCD_EN\r
+SCSI_In__4__MASK EQU 0x10\r
+SCSI_In__4__PC EQU CYREG_PRT0_PC4\r
+SCSI_In__4__PORT EQU 0\r
+SCSI_In__4__PRT EQU CYREG_PRT0_PRT\r
+SCSI_In__4__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
+SCSI_In__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
+SCSI_In__4__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
+SCSI_In__4__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
+SCSI_In__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
+SCSI_In__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
+SCSI_In__4__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
+SCSI_In__4__PS EQU CYREG_PRT0_PS\r
+SCSI_In__4__SHIFT EQU 4\r
+SCSI_In__4__SLW EQU CYREG_PRT0_SLW\r
+SCSI_In__CD__AG EQU CYREG_PRT4_AG\r
+SCSI_In__CD__AMUX EQU CYREG_PRT4_AMUX\r
+SCSI_In__CD__BIE EQU CYREG_PRT4_BIE\r
+SCSI_In__CD__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
+SCSI_In__CD__BYP EQU CYREG_PRT4_BYP\r
+SCSI_In__CD__CTL EQU CYREG_PRT4_CTL\r
+SCSI_In__CD__DM0 EQU CYREG_PRT4_DM0\r
+SCSI_In__CD__DM1 EQU CYREG_PRT4_DM1\r
+SCSI_In__CD__DM2 EQU CYREG_PRT4_DM2\r
+SCSI_In__CD__DR EQU CYREG_PRT4_DR\r
+SCSI_In__CD__INP_DIS EQU CYREG_PRT4_INP_DIS\r
+SCSI_In__CD__INTTYPE EQU CYREG_PICU4_INTTYPE2\r
+SCSI_In__CD__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
+SCSI_In__CD__LCD_EN EQU CYREG_PRT4_LCD_EN\r
+SCSI_In__CD__MASK EQU 0x04\r
+SCSI_In__CD__PC EQU CYREG_PRT4_PC2\r
+SCSI_In__CD__PORT EQU 4\r
+SCSI_In__CD__PRT EQU CYREG_PRT4_PRT\r
+SCSI_In__CD__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
+SCSI_In__CD__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
+SCSI_In__CD__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
+SCSI_In__CD__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
+SCSI_In__CD__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
+SCSI_In__CD__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
+SCSI_In__CD__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
+SCSI_In__CD__PS EQU CYREG_PRT4_PS\r
+SCSI_In__CD__SHIFT EQU 2\r
+SCSI_In__CD__SLW EQU CYREG_PRT4_SLW\r
+SCSI_In__DBP__AG EQU CYREG_PRT2_AG\r
+SCSI_In__DBP__AMUX EQU CYREG_PRT2_AMUX\r
+SCSI_In__DBP__BIE EQU CYREG_PRT2_BIE\r
+SCSI_In__DBP__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
+SCSI_In__DBP__BYP EQU CYREG_PRT2_BYP\r
+SCSI_In__DBP__CTL EQU CYREG_PRT2_CTL\r
+SCSI_In__DBP__DM0 EQU CYREG_PRT2_DM0\r
+SCSI_In__DBP__DM1 EQU CYREG_PRT2_DM1\r
+SCSI_In__DBP__DM2 EQU CYREG_PRT2_DM2\r
+SCSI_In__DBP__DR EQU CYREG_PRT2_DR\r
+SCSI_In__DBP__INP_DIS EQU CYREG_PRT2_INP_DIS\r
+SCSI_In__DBP__INTTYPE EQU CYREG_PICU2_INTTYPE1\r
+SCSI_In__DBP__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
+SCSI_In__DBP__LCD_EN EQU CYREG_PRT2_LCD_EN\r
+SCSI_In__DBP__MASK EQU 0x02\r
+SCSI_In__DBP__PC EQU CYREG_PRT2_PC1\r
+SCSI_In__DBP__PORT EQU 2\r
+SCSI_In__DBP__PRT EQU CYREG_PRT2_PRT\r
+SCSI_In__DBP__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
+SCSI_In__DBP__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
+SCSI_In__DBP__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
+SCSI_In__DBP__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
+SCSI_In__DBP__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
+SCSI_In__DBP__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
+SCSI_In__DBP__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
+SCSI_In__DBP__PS EQU CYREG_PRT2_PS\r
+SCSI_In__DBP__SHIFT EQU 1\r
+SCSI_In__DBP__SLW EQU CYREG_PRT2_SLW\r
+SCSI_In__IO__AG EQU CYREG_PRT0_AG\r
+SCSI_In__IO__AMUX EQU CYREG_PRT0_AMUX\r
+SCSI_In__IO__BIE EQU CYREG_PRT0_BIE\r
+SCSI_In__IO__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
+SCSI_In__IO__BYP EQU CYREG_PRT0_BYP\r
+SCSI_In__IO__CTL EQU CYREG_PRT0_CTL\r
+SCSI_In__IO__DM0 EQU CYREG_PRT0_DM0\r
+SCSI_In__IO__DM1 EQU CYREG_PRT0_DM1\r
+SCSI_In__IO__DM2 EQU CYREG_PRT0_DM2\r
+SCSI_In__IO__DR EQU CYREG_PRT0_DR\r
+SCSI_In__IO__INP_DIS EQU CYREG_PRT0_INP_DIS\r
+SCSI_In__IO__INTTYPE EQU CYREG_PICU0_INTTYPE4\r
+SCSI_In__IO__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
+SCSI_In__IO__LCD_EN EQU CYREG_PRT0_LCD_EN\r
+SCSI_In__IO__MASK EQU 0x10\r
+SCSI_In__IO__PC EQU CYREG_PRT0_PC4\r
+SCSI_In__IO__PORT EQU 0\r
+SCSI_In__IO__PRT EQU CYREG_PRT0_PRT\r
+SCSI_In__IO__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
+SCSI_In__IO__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
+SCSI_In__IO__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
+SCSI_In__IO__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
+SCSI_In__IO__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
+SCSI_In__IO__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
+SCSI_In__IO__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
+SCSI_In__IO__PS EQU CYREG_PRT0_PS\r
+SCSI_In__IO__SHIFT EQU 4\r
+SCSI_In__IO__SLW EQU CYREG_PRT0_SLW\r
+SCSI_In__MSG__AG EQU CYREG_PRT4_AG\r
+SCSI_In__MSG__AMUX EQU CYREG_PRT4_AMUX\r
+SCSI_In__MSG__BIE EQU CYREG_PRT4_BIE\r
+SCSI_In__MSG__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
+SCSI_In__MSG__BYP EQU CYREG_PRT4_BYP\r
+SCSI_In__MSG__CTL EQU CYREG_PRT4_CTL\r
+SCSI_In__MSG__DM0 EQU CYREG_PRT4_DM0\r
+SCSI_In__MSG__DM1 EQU CYREG_PRT4_DM1\r
+SCSI_In__MSG__DM2 EQU CYREG_PRT4_DM2\r
+SCSI_In__MSG__DR EQU CYREG_PRT4_DR\r
+SCSI_In__MSG__INP_DIS EQU CYREG_PRT4_INP_DIS\r
+SCSI_In__MSG__INTTYPE EQU CYREG_PICU4_INTTYPE6\r
+SCSI_In__MSG__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
+SCSI_In__MSG__LCD_EN EQU CYREG_PRT4_LCD_EN\r
+SCSI_In__MSG__MASK EQU 0x40\r
+SCSI_In__MSG__PC EQU CYREG_PRT4_PC6\r
+SCSI_In__MSG__PORT EQU 4\r
+SCSI_In__MSG__PRT EQU CYREG_PRT4_PRT\r
+SCSI_In__MSG__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
+SCSI_In__MSG__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
+SCSI_In__MSG__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
+SCSI_In__MSG__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
+SCSI_In__MSG__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
+SCSI_In__MSG__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
+SCSI_In__MSG__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
+SCSI_In__MSG__PS EQU CYREG_PRT4_PS\r
+SCSI_In__MSG__SHIFT EQU 6\r
+SCSI_In__MSG__SLW EQU CYREG_PRT4_SLW\r
+SCSI_In__REQ__AG EQU CYREG_PRT0_AG\r
+SCSI_In__REQ__AMUX EQU CYREG_PRT0_AMUX\r
+SCSI_In__REQ__BIE EQU CYREG_PRT0_BIE\r
+SCSI_In__REQ__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
+SCSI_In__REQ__BYP EQU CYREG_PRT0_BYP\r
+SCSI_In__REQ__CTL EQU CYREG_PRT0_CTL\r
+SCSI_In__REQ__DM0 EQU CYREG_PRT0_DM0\r
+SCSI_In__REQ__DM1 EQU CYREG_PRT0_DM1\r
+SCSI_In__REQ__DM2 EQU CYREG_PRT0_DM2\r
+SCSI_In__REQ__DR EQU CYREG_PRT0_DR\r
+SCSI_In__REQ__INP_DIS EQU CYREG_PRT0_INP_DIS\r
+SCSI_In__REQ__INTTYPE EQU CYREG_PICU0_INTTYPE5\r
+SCSI_In__REQ__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
+SCSI_In__REQ__LCD_EN EQU CYREG_PRT0_LCD_EN\r
+SCSI_In__REQ__MASK EQU 0x20\r
+SCSI_In__REQ__PC EQU CYREG_PRT0_PC5\r
+SCSI_In__REQ__PORT EQU 0\r
+SCSI_In__REQ__PRT EQU CYREG_PRT0_PRT\r
+SCSI_In__REQ__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
+SCSI_In__REQ__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
+SCSI_In__REQ__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
+SCSI_In__REQ__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
+SCSI_In__REQ__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
+SCSI_In__REQ__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
+SCSI_In__REQ__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
+SCSI_In__REQ__PS EQU CYREG_PRT0_PS\r
+SCSI_In__REQ__SHIFT EQU 5\r
+SCSI_In__REQ__SLW EQU CYREG_PRT0_SLW\r
+SCSI_In_DBx__0__AG EQU CYREG_PRT5_AG\r
+SCSI_In_DBx__0__AMUX EQU CYREG_PRT5_AMUX\r
+SCSI_In_DBx__0__BIE EQU CYREG_PRT5_BIE\r
+SCSI_In_DBx__0__BIT_MASK EQU CYREG_PRT5_BIT_MASK\r
+SCSI_In_DBx__0__BYP EQU CYREG_PRT5_BYP\r
+SCSI_In_DBx__0__CTL EQU CYREG_PRT5_CTL\r
+SCSI_In_DBx__0__DM0 EQU CYREG_PRT5_DM0\r
+SCSI_In_DBx__0__DM1 EQU CYREG_PRT5_DM1\r
+SCSI_In_DBx__0__DM2 EQU CYREG_PRT5_DM2\r
+SCSI_In_DBx__0__DR EQU CYREG_PRT5_DR\r
+SCSI_In_DBx__0__INP_DIS EQU CYREG_PRT5_INP_DIS\r
+SCSI_In_DBx__0__INTTYPE EQU CYREG_PICU5_INTTYPE3\r
+SCSI_In_DBx__0__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG\r
+SCSI_In_DBx__0__LCD_EN EQU CYREG_PRT5_LCD_EN\r
+SCSI_In_DBx__0__MASK EQU 0x08\r
+SCSI_In_DBx__0__PC EQU CYREG_PRT5_PC3\r
+SCSI_In_DBx__0__PORT EQU 5\r
+SCSI_In_DBx__0__PRT EQU CYREG_PRT5_PRT\r
+SCSI_In_DBx__0__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL\r
+SCSI_In_DBx__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN\r
+SCSI_In_DBx__0__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0\r
+SCSI_In_DBx__0__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1\r
+SCSI_In_DBx__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0\r
+SCSI_In_DBx__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1\r
+SCSI_In_DBx__0__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT\r
+SCSI_In_DBx__0__PS EQU CYREG_PRT5_PS\r
+SCSI_In_DBx__0__SHIFT EQU 3\r
+SCSI_In_DBx__0__SLW EQU CYREG_PRT5_SLW\r
+SCSI_In_DBx__1__AG EQU CYREG_PRT5_AG\r
+SCSI_In_DBx__1__AMUX EQU CYREG_PRT5_AMUX\r
+SCSI_In_DBx__1__BIE EQU CYREG_PRT5_BIE\r
+SCSI_In_DBx__1__BIT_MASK EQU CYREG_PRT5_BIT_MASK\r
+SCSI_In_DBx__1__BYP EQU CYREG_PRT5_BYP\r
+SCSI_In_DBx__1__CTL EQU CYREG_PRT5_CTL\r
+SCSI_In_DBx__1__DM0 EQU CYREG_PRT5_DM0\r
+SCSI_In_DBx__1__DM1 EQU CYREG_PRT5_DM1\r
+SCSI_In_DBx__1__DM2 EQU CYREG_PRT5_DM2\r
+SCSI_In_DBx__1__DR EQU CYREG_PRT5_DR\r
+SCSI_In_DBx__1__INP_DIS EQU CYREG_PRT5_INP_DIS\r
+SCSI_In_DBx__1__INTTYPE EQU CYREG_PICU5_INTTYPE2\r
+SCSI_In_DBx__1__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG\r
+SCSI_In_DBx__1__LCD_EN EQU CYREG_PRT5_LCD_EN\r
+SCSI_In_DBx__1__MASK EQU 0x04\r
+SCSI_In_DBx__1__PC EQU CYREG_PRT5_PC2\r
+SCSI_In_DBx__1__PORT EQU 5\r
+SCSI_In_DBx__1__PRT EQU CYREG_PRT5_PRT\r
+SCSI_In_DBx__1__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL\r
+SCSI_In_DBx__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN\r
+SCSI_In_DBx__1__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0\r
+SCSI_In_DBx__1__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1\r
+SCSI_In_DBx__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0\r
+SCSI_In_DBx__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1\r
+SCSI_In_DBx__1__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT\r
+SCSI_In_DBx__1__PS EQU CYREG_PRT5_PS\r
+SCSI_In_DBx__1__SHIFT EQU 2\r
+SCSI_In_DBx__1__SLW EQU CYREG_PRT5_SLW\r
+SCSI_In_DBx__2__AG EQU CYREG_PRT6_AG\r
+SCSI_In_DBx__2__AMUX EQU CYREG_PRT6_AMUX\r
+SCSI_In_DBx__2__BIE EQU CYREG_PRT6_BIE\r
+SCSI_In_DBx__2__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
+SCSI_In_DBx__2__BYP EQU CYREG_PRT6_BYP\r
+SCSI_In_DBx__2__CTL EQU CYREG_PRT6_CTL\r
+SCSI_In_DBx__2__DM0 EQU CYREG_PRT6_DM0\r
+SCSI_In_DBx__2__DM1 EQU CYREG_PRT6_DM1\r
+SCSI_In_DBx__2__DM2 EQU CYREG_PRT6_DM2\r
+SCSI_In_DBx__2__DR EQU CYREG_PRT6_DR\r
+SCSI_In_DBx__2__INP_DIS EQU CYREG_PRT6_INP_DIS\r
+SCSI_In_DBx__2__INTTYPE EQU CYREG_PICU6_INTTYPE7\r
+SCSI_In_DBx__2__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
+SCSI_In_DBx__2__LCD_EN EQU CYREG_PRT6_LCD_EN\r
+SCSI_In_DBx__2__MASK EQU 0x80\r
+SCSI_In_DBx__2__PC EQU CYREG_PRT6_PC7\r
+SCSI_In_DBx__2__PORT EQU 6\r
+SCSI_In_DBx__2__PRT EQU CYREG_PRT6_PRT\r
+SCSI_In_DBx__2__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
+SCSI_In_DBx__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
+SCSI_In_DBx__2__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
+SCSI_In_DBx__2__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
+SCSI_In_DBx__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
+SCSI_In_DBx__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
+SCSI_In_DBx__2__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
+SCSI_In_DBx__2__PS EQU CYREG_PRT6_PS\r
+SCSI_In_DBx__2__SHIFT EQU 7\r
+SCSI_In_DBx__2__SLW EQU CYREG_PRT6_SLW\r
+SCSI_In_DBx__3__AG EQU CYREG_PRT6_AG\r
+SCSI_In_DBx__3__AMUX EQU CYREG_PRT6_AMUX\r
+SCSI_In_DBx__3__BIE EQU CYREG_PRT6_BIE\r
+SCSI_In_DBx__3__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
+SCSI_In_DBx__3__BYP EQU CYREG_PRT6_BYP\r
+SCSI_In_DBx__3__CTL EQU CYREG_PRT6_CTL\r
+SCSI_In_DBx__3__DM0 EQU CYREG_PRT6_DM0\r
+SCSI_In_DBx__3__DM1 EQU CYREG_PRT6_DM1\r
+SCSI_In_DBx__3__DM2 EQU CYREG_PRT6_DM2\r
+SCSI_In_DBx__3__DR EQU CYREG_PRT6_DR\r
+SCSI_In_DBx__3__INP_DIS EQU CYREG_PRT6_INP_DIS\r
+SCSI_In_DBx__3__INTTYPE EQU CYREG_PICU6_INTTYPE6\r
+SCSI_In_DBx__3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
+SCSI_In_DBx__3__LCD_EN EQU CYREG_PRT6_LCD_EN\r
+SCSI_In_DBx__3__MASK EQU 0x40\r
+SCSI_In_DBx__3__PC EQU CYREG_PRT6_PC6\r
+SCSI_In_DBx__3__PORT EQU 6\r
+SCSI_In_DBx__3__PRT EQU CYREG_PRT6_PRT\r
+SCSI_In_DBx__3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
+SCSI_In_DBx__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
+SCSI_In_DBx__3__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
+SCSI_In_DBx__3__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
+SCSI_In_DBx__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
+SCSI_In_DBx__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
+SCSI_In_DBx__3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
+SCSI_In_DBx__3__PS EQU CYREG_PRT6_PS\r
+SCSI_In_DBx__3__SHIFT EQU 6\r
+SCSI_In_DBx__3__SLW EQU CYREG_PRT6_SLW\r
+SCSI_In_DBx__4__AG EQU CYREG_PRT12_AG\r
+SCSI_In_DBx__4__BIE EQU CYREG_PRT12_BIE\r
+SCSI_In_DBx__4__BIT_MASK EQU CYREG_PRT12_BIT_MASK\r
+SCSI_In_DBx__4__BYP EQU CYREG_PRT12_BYP\r
+SCSI_In_DBx__4__DM0 EQU CYREG_PRT12_DM0\r
+SCSI_In_DBx__4__DM1 EQU CYREG_PRT12_DM1\r
+SCSI_In_DBx__4__DM2 EQU CYREG_PRT12_DM2\r
+SCSI_In_DBx__4__DR EQU CYREG_PRT12_DR\r
+SCSI_In_DBx__4__INP_DIS EQU CYREG_PRT12_INP_DIS\r
+SCSI_In_DBx__4__INTTYPE EQU CYREG_PICU12_INTTYPE5\r
+SCSI_In_DBx__4__MASK EQU 0x20\r
+SCSI_In_DBx__4__PC EQU CYREG_PRT12_PC5\r
+SCSI_In_DBx__4__PORT EQU 12\r
+SCSI_In_DBx__4__PRT EQU CYREG_PRT12_PRT\r
+SCSI_In_DBx__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN\r
+SCSI_In_DBx__4__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0\r
+SCSI_In_DBx__4__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1\r
+SCSI_In_DBx__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0\r
+SCSI_In_DBx__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1\r
+SCSI_In_DBx__4__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT\r
+SCSI_In_DBx__4__PS EQU CYREG_PRT12_PS\r
+SCSI_In_DBx__4__SHIFT EQU 5\r
+SCSI_In_DBx__4__SIO_CFG EQU CYREG_PRT12_SIO_CFG\r
+SCSI_In_DBx__4__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF\r
+SCSI_In_DBx__4__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN\r
+SCSI_In_DBx__4__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ\r
+SCSI_In_DBx__4__SLW EQU CYREG_PRT12_SLW\r
+SCSI_In_DBx__5__AG EQU CYREG_PRT12_AG\r
+SCSI_In_DBx__5__BIE EQU CYREG_PRT12_BIE\r
+SCSI_In_DBx__5__BIT_MASK EQU CYREG_PRT12_BIT_MASK\r
+SCSI_In_DBx__5__BYP EQU CYREG_PRT12_BYP\r
+SCSI_In_DBx__5__DM0 EQU CYREG_PRT12_DM0\r
+SCSI_In_DBx__5__DM1 EQU CYREG_PRT12_DM1\r
+SCSI_In_DBx__5__DM2 EQU CYREG_PRT12_DM2\r
+SCSI_In_DBx__5__DR EQU CYREG_PRT12_DR\r
+SCSI_In_DBx__5__INP_DIS EQU CYREG_PRT12_INP_DIS\r
+SCSI_In_DBx__5__INTTYPE EQU CYREG_PICU12_INTTYPE4\r
+SCSI_In_DBx__5__MASK EQU 0x10\r
+SCSI_In_DBx__5__PC EQU CYREG_PRT12_PC4\r
+SCSI_In_DBx__5__PORT EQU 12\r
+SCSI_In_DBx__5__PRT EQU CYREG_PRT12_PRT\r
+SCSI_In_DBx__5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN\r
+SCSI_In_DBx__5__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0\r
+SCSI_In_DBx__5__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1\r
+SCSI_In_DBx__5__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0\r
+SCSI_In_DBx__5__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1\r
+SCSI_In_DBx__5__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT\r
+SCSI_In_DBx__5__PS EQU CYREG_PRT12_PS\r
+SCSI_In_DBx__5__SHIFT EQU 4\r
+SCSI_In_DBx__5__SIO_CFG EQU CYREG_PRT12_SIO_CFG\r
+SCSI_In_DBx__5__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF\r
+SCSI_In_DBx__5__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN\r
+SCSI_In_DBx__5__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ\r
+SCSI_In_DBx__5__SLW EQU CYREG_PRT12_SLW\r
+SCSI_In_DBx__6__AG EQU CYREG_PRT2_AG\r
+SCSI_In_DBx__6__AMUX EQU CYREG_PRT2_AMUX\r
+SCSI_In_DBx__6__BIE EQU CYREG_PRT2_BIE\r
+SCSI_In_DBx__6__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
+SCSI_In_DBx__6__BYP EQU CYREG_PRT2_BYP\r
+SCSI_In_DBx__6__CTL EQU CYREG_PRT2_CTL\r
+SCSI_In_DBx__6__DM0 EQU CYREG_PRT2_DM0\r
+SCSI_In_DBx__6__DM1 EQU CYREG_PRT2_DM1\r
+SCSI_In_DBx__6__DM2 EQU CYREG_PRT2_DM2\r
+SCSI_In_DBx__6__DR EQU CYREG_PRT2_DR\r
+SCSI_In_DBx__6__INP_DIS EQU CYREG_PRT2_INP_DIS\r
+SCSI_In_DBx__6__INTTYPE EQU CYREG_PICU2_INTTYPE5\r
+SCSI_In_DBx__6__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
+SCSI_In_DBx__6__LCD_EN EQU CYREG_PRT2_LCD_EN\r
+SCSI_In_DBx__6__MASK EQU 0x20\r
+SCSI_In_DBx__6__PC EQU CYREG_PRT2_PC5\r
+SCSI_In_DBx__6__PORT EQU 2\r
+SCSI_In_DBx__6__PRT EQU CYREG_PRT2_PRT\r
+SCSI_In_DBx__6__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
+SCSI_In_DBx__6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
+SCSI_In_DBx__6__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
+SCSI_In_DBx__6__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
+SCSI_In_DBx__6__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
+SCSI_In_DBx__6__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
+SCSI_In_DBx__6__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
+SCSI_In_DBx__6__PS EQU CYREG_PRT2_PS\r
+SCSI_In_DBx__6__SHIFT EQU 5\r
+SCSI_In_DBx__6__SLW EQU CYREG_PRT2_SLW\r
+SCSI_In_DBx__7__AG EQU CYREG_PRT2_AG\r
+SCSI_In_DBx__7__AMUX EQU CYREG_PRT2_AMUX\r
+SCSI_In_DBx__7__BIE EQU CYREG_PRT2_BIE\r
+SCSI_In_DBx__7__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
+SCSI_In_DBx__7__BYP EQU CYREG_PRT2_BYP\r
+SCSI_In_DBx__7__CTL EQU CYREG_PRT2_CTL\r
+SCSI_In_DBx__7__DM0 EQU CYREG_PRT2_DM0\r
+SCSI_In_DBx__7__DM1 EQU CYREG_PRT2_DM1\r
+SCSI_In_DBx__7__DM2 EQU CYREG_PRT2_DM2\r
+SCSI_In_DBx__7__DR EQU CYREG_PRT2_DR\r
+SCSI_In_DBx__7__INP_DIS EQU CYREG_PRT2_INP_DIS\r
+SCSI_In_DBx__7__INTTYPE EQU CYREG_PICU2_INTTYPE4\r
+SCSI_In_DBx__7__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
+SCSI_In_DBx__7__LCD_EN EQU CYREG_PRT2_LCD_EN\r
+SCSI_In_DBx__7__MASK EQU 0x10\r
+SCSI_In_DBx__7__PC EQU CYREG_PRT2_PC4\r
+SCSI_In_DBx__7__PORT EQU 2\r
+SCSI_In_DBx__7__PRT EQU CYREG_PRT2_PRT\r
+SCSI_In_DBx__7__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
+SCSI_In_DBx__7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
+SCSI_In_DBx__7__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
+SCSI_In_DBx__7__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
+SCSI_In_DBx__7__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
+SCSI_In_DBx__7__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
+SCSI_In_DBx__7__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
+SCSI_In_DBx__7__PS EQU CYREG_PRT2_PS\r
+SCSI_In_DBx__7__SHIFT EQU 4\r
+SCSI_In_DBx__7__SLW EQU CYREG_PRT2_SLW\r
+SCSI_In_DBx__DB0__AG EQU CYREG_PRT5_AG\r
+SCSI_In_DBx__DB0__AMUX EQU CYREG_PRT5_AMUX\r
+SCSI_In_DBx__DB0__BIE EQU CYREG_PRT5_BIE\r
+SCSI_In_DBx__DB0__BIT_MASK EQU CYREG_PRT5_BIT_MASK\r
+SCSI_In_DBx__DB0__BYP EQU CYREG_PRT5_BYP\r
+SCSI_In_DBx__DB0__CTL EQU CYREG_PRT5_CTL\r
+SCSI_In_DBx__DB0__DM0 EQU CYREG_PRT5_DM0\r
+SCSI_In_DBx__DB0__DM1 EQU CYREG_PRT5_DM1\r
+SCSI_In_DBx__DB0__DM2 EQU CYREG_PRT5_DM2\r
+SCSI_In_DBx__DB0__DR EQU CYREG_PRT5_DR\r
+SCSI_In_DBx__DB0__INP_DIS EQU CYREG_PRT5_INP_DIS\r
+SCSI_In_DBx__DB0__INTTYPE EQU CYREG_PICU5_INTTYPE3\r
+SCSI_In_DBx__DB0__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG\r
+SCSI_In_DBx__DB0__LCD_EN EQU CYREG_PRT5_LCD_EN\r
+SCSI_In_DBx__DB0__MASK EQU 0x08\r
+SCSI_In_DBx__DB0__PC EQU CYREG_PRT5_PC3\r
+SCSI_In_DBx__DB0__PORT EQU 5\r
+SCSI_In_DBx__DB0__PRT EQU CYREG_PRT5_PRT\r
+SCSI_In_DBx__DB0__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL\r
+SCSI_In_DBx__DB0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN\r
+SCSI_In_DBx__DB0__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0\r
+SCSI_In_DBx__DB0__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1\r
+SCSI_In_DBx__DB0__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0\r
+SCSI_In_DBx__DB0__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1\r
+SCSI_In_DBx__DB0__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT\r
+SCSI_In_DBx__DB0__PS EQU CYREG_PRT5_PS\r
+SCSI_In_DBx__DB0__SHIFT EQU 3\r
+SCSI_In_DBx__DB0__SLW EQU CYREG_PRT5_SLW\r
+SCSI_In_DBx__DB1__AG EQU CYREG_PRT5_AG\r
+SCSI_In_DBx__DB1__AMUX EQU CYREG_PRT5_AMUX\r
+SCSI_In_DBx__DB1__BIE EQU CYREG_PRT5_BIE\r
+SCSI_In_DBx__DB1__BIT_MASK EQU CYREG_PRT5_BIT_MASK\r
+SCSI_In_DBx__DB1__BYP EQU CYREG_PRT5_BYP\r
+SCSI_In_DBx__DB1__CTL EQU CYREG_PRT5_CTL\r
+SCSI_In_DBx__DB1__DM0 EQU CYREG_PRT5_DM0\r
+SCSI_In_DBx__DB1__DM1 EQU CYREG_PRT5_DM1\r
+SCSI_In_DBx__DB1__DM2 EQU CYREG_PRT5_DM2\r
+SCSI_In_DBx__DB1__DR EQU CYREG_PRT5_DR\r
+SCSI_In_DBx__DB1__INP_DIS EQU CYREG_PRT5_INP_DIS\r
+SCSI_In_DBx__DB1__INTTYPE EQU CYREG_PICU5_INTTYPE2\r
+SCSI_In_DBx__DB1__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG\r
+SCSI_In_DBx__DB1__LCD_EN EQU CYREG_PRT5_LCD_EN\r
+SCSI_In_DBx__DB1__MASK EQU 0x04\r
+SCSI_In_DBx__DB1__PC EQU CYREG_PRT5_PC2\r
+SCSI_In_DBx__DB1__PORT EQU 5\r
+SCSI_In_DBx__DB1__PRT EQU CYREG_PRT5_PRT\r
+SCSI_In_DBx__DB1__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL\r
+SCSI_In_DBx__DB1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN\r
+SCSI_In_DBx__DB1__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0\r
+SCSI_In_DBx__DB1__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1\r
+SCSI_In_DBx__DB1__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0\r
+SCSI_In_DBx__DB1__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1\r
+SCSI_In_DBx__DB1__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT\r
+SCSI_In_DBx__DB1__PS EQU CYREG_PRT5_PS\r
+SCSI_In_DBx__DB1__SHIFT EQU 2\r
+SCSI_In_DBx__DB1__SLW EQU CYREG_PRT5_SLW\r
+SCSI_In_DBx__DB2__AG EQU CYREG_PRT6_AG\r
+SCSI_In_DBx__DB2__AMUX EQU CYREG_PRT6_AMUX\r
+SCSI_In_DBx__DB2__BIE EQU CYREG_PRT6_BIE\r
+SCSI_In_DBx__DB2__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
+SCSI_In_DBx__DB2__BYP EQU CYREG_PRT6_BYP\r
+SCSI_In_DBx__DB2__CTL EQU CYREG_PRT6_CTL\r
+SCSI_In_DBx__DB2__DM0 EQU CYREG_PRT6_DM0\r
+SCSI_In_DBx__DB2__DM1 EQU CYREG_PRT6_DM1\r
+SCSI_In_DBx__DB2__DM2 EQU CYREG_PRT6_DM2\r
+SCSI_In_DBx__DB2__DR EQU CYREG_PRT6_DR\r
+SCSI_In_DBx__DB2__INP_DIS EQU CYREG_PRT6_INP_DIS\r
+SCSI_In_DBx__DB2__INTTYPE EQU CYREG_PICU6_INTTYPE7\r
+SCSI_In_DBx__DB2__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
+SCSI_In_DBx__DB2__LCD_EN EQU CYREG_PRT6_LCD_EN\r
+SCSI_In_DBx__DB2__MASK EQU 0x80\r
+SCSI_In_DBx__DB2__PC EQU CYREG_PRT6_PC7\r
+SCSI_In_DBx__DB2__PORT EQU 6\r
+SCSI_In_DBx__DB2__PRT EQU CYREG_PRT6_PRT\r
+SCSI_In_DBx__DB2__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
+SCSI_In_DBx__DB2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
+SCSI_In_DBx__DB2__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
+SCSI_In_DBx__DB2__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
+SCSI_In_DBx__DB2__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
+SCSI_In_DBx__DB2__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
+SCSI_In_DBx__DB2__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
+SCSI_In_DBx__DB2__PS EQU CYREG_PRT6_PS\r
+SCSI_In_DBx__DB2__SHIFT EQU 7\r
+SCSI_In_DBx__DB2__SLW EQU CYREG_PRT6_SLW\r
+SCSI_In_DBx__DB3__AG EQU CYREG_PRT6_AG\r
+SCSI_In_DBx__DB3__AMUX EQU CYREG_PRT6_AMUX\r
+SCSI_In_DBx__DB3__BIE EQU CYREG_PRT6_BIE\r
+SCSI_In_DBx__DB3__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
+SCSI_In_DBx__DB3__BYP EQU CYREG_PRT6_BYP\r
+SCSI_In_DBx__DB3__CTL EQU CYREG_PRT6_CTL\r
+SCSI_In_DBx__DB3__DM0 EQU CYREG_PRT6_DM0\r
+SCSI_In_DBx__DB3__DM1 EQU CYREG_PRT6_DM1\r
+SCSI_In_DBx__DB3__DM2 EQU CYREG_PRT6_DM2\r
+SCSI_In_DBx__DB3__DR EQU CYREG_PRT6_DR\r
+SCSI_In_DBx__DB3__INP_DIS EQU CYREG_PRT6_INP_DIS\r
+SCSI_In_DBx__DB3__INTTYPE EQU CYREG_PICU6_INTTYPE6\r
+SCSI_In_DBx__DB3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
+SCSI_In_DBx__DB3__LCD_EN EQU CYREG_PRT6_LCD_EN\r
+SCSI_In_DBx__DB3__MASK EQU 0x40\r
+SCSI_In_DBx__DB3__PC EQU CYREG_PRT6_PC6\r
+SCSI_In_DBx__DB3__PORT EQU 6\r
+SCSI_In_DBx__DB3__PRT EQU CYREG_PRT6_PRT\r
+SCSI_In_DBx__DB3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
+SCSI_In_DBx__DB3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
+SCSI_In_DBx__DB3__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
+SCSI_In_DBx__DB3__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
+SCSI_In_DBx__DB3__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
+SCSI_In_DBx__DB3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
+SCSI_In_DBx__DB3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
+SCSI_In_DBx__DB3__PS EQU CYREG_PRT6_PS\r
+SCSI_In_DBx__DB3__SHIFT EQU 6\r
+SCSI_In_DBx__DB3__SLW EQU CYREG_PRT6_SLW\r
+SCSI_In_DBx__DB4__AG EQU CYREG_PRT12_AG\r
+SCSI_In_DBx__DB4__BIE EQU CYREG_PRT12_BIE\r
+SCSI_In_DBx__DB4__BIT_MASK EQU CYREG_PRT12_BIT_MASK\r
+SCSI_In_DBx__DB4__BYP EQU CYREG_PRT12_BYP\r
+SCSI_In_DBx__DB4__DM0 EQU CYREG_PRT12_DM0\r
+SCSI_In_DBx__DB4__DM1 EQU CYREG_PRT12_DM1\r
+SCSI_In_DBx__DB4__DM2 EQU CYREG_PRT12_DM2\r
+SCSI_In_DBx__DB4__DR EQU CYREG_PRT12_DR\r
+SCSI_In_DBx__DB4__INP_DIS EQU CYREG_PRT12_INP_DIS\r
+SCSI_In_DBx__DB4__INTTYPE EQU CYREG_PICU12_INTTYPE5\r
+SCSI_In_DBx__DB4__MASK EQU 0x20\r
+SCSI_In_DBx__DB4__PC EQU CYREG_PRT12_PC5\r
+SCSI_In_DBx__DB4__PORT EQU 12\r
+SCSI_In_DBx__DB4__PRT EQU CYREG_PRT12_PRT\r
+SCSI_In_DBx__DB4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN\r
+SCSI_In_DBx__DB4__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0\r
+SCSI_In_DBx__DB4__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1\r
+SCSI_In_DBx__DB4__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0\r
+SCSI_In_DBx__DB4__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1\r
+SCSI_In_DBx__DB4__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT\r
+SCSI_In_DBx__DB4__PS EQU CYREG_PRT12_PS\r
+SCSI_In_DBx__DB4__SHIFT EQU 5\r
+SCSI_In_DBx__DB4__SIO_CFG EQU CYREG_PRT12_SIO_CFG\r
+SCSI_In_DBx__DB4__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF\r
+SCSI_In_DBx__DB4__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN\r
+SCSI_In_DBx__DB4__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ\r
+SCSI_In_DBx__DB4__SLW EQU CYREG_PRT12_SLW\r
+SCSI_In_DBx__DB5__AG EQU CYREG_PRT12_AG\r
+SCSI_In_DBx__DB5__BIE EQU CYREG_PRT12_BIE\r
+SCSI_In_DBx__DB5__BIT_MASK EQU CYREG_PRT12_BIT_MASK\r
+SCSI_In_DBx__DB5__BYP EQU CYREG_PRT12_BYP\r
+SCSI_In_DBx__DB5__DM0 EQU CYREG_PRT12_DM0\r
+SCSI_In_DBx__DB5__DM1 EQU CYREG_PRT12_DM1\r
+SCSI_In_DBx__DB5__DM2 EQU CYREG_PRT12_DM2\r
+SCSI_In_DBx__DB5__DR EQU CYREG_PRT12_DR\r
+SCSI_In_DBx__DB5__INP_DIS EQU CYREG_PRT12_INP_DIS\r
+SCSI_In_DBx__DB5__INTTYPE EQU CYREG_PICU12_INTTYPE4\r
+SCSI_In_DBx__DB5__MASK EQU 0x10\r
+SCSI_In_DBx__DB5__PC EQU CYREG_PRT12_PC4\r
+SCSI_In_DBx__DB5__PORT EQU 12\r
+SCSI_In_DBx__DB5__PRT EQU CYREG_PRT12_PRT\r
+SCSI_In_DBx__DB5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN\r
+SCSI_In_DBx__DB5__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0\r
+SCSI_In_DBx__DB5__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1\r
+SCSI_In_DBx__DB5__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0\r
+SCSI_In_DBx__DB5__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1\r
+SCSI_In_DBx__DB5__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT\r
+SCSI_In_DBx__DB5__PS EQU CYREG_PRT12_PS\r
+SCSI_In_DBx__DB5__SHIFT EQU 4\r
+SCSI_In_DBx__DB5__SIO_CFG EQU CYREG_PRT12_SIO_CFG\r
+SCSI_In_DBx__DB5__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF\r
+SCSI_In_DBx__DB5__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN\r
+SCSI_In_DBx__DB5__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ\r
+SCSI_In_DBx__DB5__SLW EQU CYREG_PRT12_SLW\r
+SCSI_In_DBx__DB6__AG EQU CYREG_PRT2_AG\r
+SCSI_In_DBx__DB6__AMUX EQU CYREG_PRT2_AMUX\r
+SCSI_In_DBx__DB6__BIE EQU CYREG_PRT2_BIE\r
+SCSI_In_DBx__DB6__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
+SCSI_In_DBx__DB6__BYP EQU CYREG_PRT2_BYP\r
+SCSI_In_DBx__DB6__CTL EQU CYREG_PRT2_CTL\r
+SCSI_In_DBx__DB6__DM0 EQU CYREG_PRT2_DM0\r
+SCSI_In_DBx__DB6__DM1 EQU CYREG_PRT2_DM1\r
+SCSI_In_DBx__DB6__DM2 EQU CYREG_PRT2_DM2\r
+SCSI_In_DBx__DB6__DR EQU CYREG_PRT2_DR\r
+SCSI_In_DBx__DB6__INP_DIS EQU CYREG_PRT2_INP_DIS\r
+SCSI_In_DBx__DB6__INTTYPE EQU CYREG_PICU2_INTTYPE5\r
+SCSI_In_DBx__DB6__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
+SCSI_In_DBx__DB6__LCD_EN EQU CYREG_PRT2_LCD_EN\r
+SCSI_In_DBx__DB6__MASK EQU 0x20\r
+SCSI_In_DBx__DB6__PC EQU CYREG_PRT2_PC5\r
+SCSI_In_DBx__DB6__PORT EQU 2\r
+SCSI_In_DBx__DB6__PRT EQU CYREG_PRT2_PRT\r
+SCSI_In_DBx__DB6__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
+SCSI_In_DBx__DB6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
+SCSI_In_DBx__DB6__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
+SCSI_In_DBx__DB6__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
+SCSI_In_DBx__DB6__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
+SCSI_In_DBx__DB6__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
+SCSI_In_DBx__DB6__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
+SCSI_In_DBx__DB6__PS EQU CYREG_PRT2_PS\r
+SCSI_In_DBx__DB6__SHIFT EQU 5\r
+SCSI_In_DBx__DB6__SLW EQU CYREG_PRT2_SLW\r
+SCSI_In_DBx__DB7__AG EQU CYREG_PRT2_AG\r
+SCSI_In_DBx__DB7__AMUX EQU CYREG_PRT2_AMUX\r
+SCSI_In_DBx__DB7__BIE EQU CYREG_PRT2_BIE\r
+SCSI_In_DBx__DB7__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
+SCSI_In_DBx__DB7__BYP EQU CYREG_PRT2_BYP\r
+SCSI_In_DBx__DB7__CTL EQU CYREG_PRT2_CTL\r
+SCSI_In_DBx__DB7__DM0 EQU CYREG_PRT2_DM0\r
+SCSI_In_DBx__DB7__DM1 EQU CYREG_PRT2_DM1\r
+SCSI_In_DBx__DB7__DM2 EQU CYREG_PRT2_DM2\r
+SCSI_In_DBx__DB7__DR EQU CYREG_PRT2_DR\r
+SCSI_In_DBx__DB7__INP_DIS EQU CYREG_PRT2_INP_DIS\r
+SCSI_In_DBx__DB7__INTTYPE EQU CYREG_PICU2_INTTYPE4\r
+SCSI_In_DBx__DB7__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
+SCSI_In_DBx__DB7__LCD_EN EQU CYREG_PRT2_LCD_EN\r
+SCSI_In_DBx__DB7__MASK EQU 0x10\r
+SCSI_In_DBx__DB7__PC EQU CYREG_PRT2_PC4\r
+SCSI_In_DBx__DB7__PORT EQU 2\r
+SCSI_In_DBx__DB7__PRT EQU CYREG_PRT2_PRT\r
+SCSI_In_DBx__DB7__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
+SCSI_In_DBx__DB7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
+SCSI_In_DBx__DB7__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
+SCSI_In_DBx__DB7__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
+SCSI_In_DBx__DB7__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
+SCSI_In_DBx__DB7__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
+SCSI_In_DBx__DB7__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
+SCSI_In_DBx__DB7__PS EQU CYREG_PRT2_PS\r
+SCSI_In_DBx__DB7__SHIFT EQU 4\r
+SCSI_In_DBx__DB7__SLW EQU CYREG_PRT2_SLW\r
 \r
 ; SCSI_Noise\r
 SCSI_Noise__0__AG EQU CYREG_PRT2_AG\r
@@ -2735,6 +1199,1698 @@ SCSI_Noise__SEL__PS EQU CYREG_PRT4_PS
 SCSI_Noise__SEL__SHIFT EQU 3\r
 SCSI_Noise__SEL__SLW EQU CYREG_PRT4_SLW\r
 \r
+; SCSI_Out\r
+SCSI_Out__0__AG EQU CYREG_PRT15_AG\r
+SCSI_Out__0__AMUX EQU CYREG_PRT15_AMUX\r
+SCSI_Out__0__BIE EQU CYREG_PRT15_BIE\r
+SCSI_Out__0__BIT_MASK EQU CYREG_PRT15_BIT_MASK\r
+SCSI_Out__0__BYP EQU CYREG_PRT15_BYP\r
+SCSI_Out__0__CTL EQU CYREG_PRT15_CTL\r
+SCSI_Out__0__DM0 EQU CYREG_PRT15_DM0\r
+SCSI_Out__0__DM1 EQU CYREG_PRT15_DM1\r
+SCSI_Out__0__DM2 EQU CYREG_PRT15_DM2\r
+SCSI_Out__0__DR EQU CYREG_PRT15_DR\r
+SCSI_Out__0__INP_DIS EQU CYREG_PRT15_INP_DIS\r
+SCSI_Out__0__INTTYPE EQU CYREG_PICU15_INTTYPE5\r
+SCSI_Out__0__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG\r
+SCSI_Out__0__LCD_EN EQU CYREG_PRT15_LCD_EN\r
+SCSI_Out__0__MASK EQU 0x20\r
+SCSI_Out__0__PC EQU CYREG_IO_PC_PRT15_PC5\r
+SCSI_Out__0__PORT EQU 15\r
+SCSI_Out__0__PRT EQU CYREG_PRT15_PRT\r
+SCSI_Out__0__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL\r
+SCSI_Out__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN\r
+SCSI_Out__0__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0\r
+SCSI_Out__0__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1\r
+SCSI_Out__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0\r
+SCSI_Out__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1\r
+SCSI_Out__0__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT\r
+SCSI_Out__0__PS EQU CYREG_PRT15_PS\r
+SCSI_Out__0__SHIFT EQU 5\r
+SCSI_Out__0__SLW EQU CYREG_PRT15_SLW\r
+SCSI_Out__1__AG EQU CYREG_PRT15_AG\r
+SCSI_Out__1__AMUX EQU CYREG_PRT15_AMUX\r
+SCSI_Out__1__BIE EQU CYREG_PRT15_BIE\r
+SCSI_Out__1__BIT_MASK EQU CYREG_PRT15_BIT_MASK\r
+SCSI_Out__1__BYP EQU CYREG_PRT15_BYP\r
+SCSI_Out__1__CTL EQU CYREG_PRT15_CTL\r
+SCSI_Out__1__DM0 EQU CYREG_PRT15_DM0\r
+SCSI_Out__1__DM1 EQU CYREG_PRT15_DM1\r
+SCSI_Out__1__DM2 EQU CYREG_PRT15_DM2\r
+SCSI_Out__1__DR EQU CYREG_PRT15_DR\r
+SCSI_Out__1__INP_DIS EQU CYREG_PRT15_INP_DIS\r
+SCSI_Out__1__INTTYPE EQU CYREG_PICU15_INTTYPE4\r
+SCSI_Out__1__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG\r
+SCSI_Out__1__LCD_EN EQU CYREG_PRT15_LCD_EN\r
+SCSI_Out__1__MASK EQU 0x10\r
+SCSI_Out__1__PC EQU CYREG_IO_PC_PRT15_PC4\r
+SCSI_Out__1__PORT EQU 15\r
+SCSI_Out__1__PRT EQU CYREG_PRT15_PRT\r
+SCSI_Out__1__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL\r
+SCSI_Out__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN\r
+SCSI_Out__1__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0\r
+SCSI_Out__1__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1\r
+SCSI_Out__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0\r
+SCSI_Out__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1\r
+SCSI_Out__1__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT\r
+SCSI_Out__1__PS EQU CYREG_PRT15_PS\r
+SCSI_Out__1__SHIFT EQU 4\r
+SCSI_Out__1__SLW EQU CYREG_PRT15_SLW\r
+SCSI_Out__2__AG EQU CYREG_PRT6_AG\r
+SCSI_Out__2__AMUX EQU CYREG_PRT6_AMUX\r
+SCSI_Out__2__BIE EQU CYREG_PRT6_BIE\r
+SCSI_Out__2__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
+SCSI_Out__2__BYP EQU CYREG_PRT6_BYP\r
+SCSI_Out__2__CTL EQU CYREG_PRT6_CTL\r
+SCSI_Out__2__DM0 EQU CYREG_PRT6_DM0\r
+SCSI_Out__2__DM1 EQU CYREG_PRT6_DM1\r
+SCSI_Out__2__DM2 EQU CYREG_PRT6_DM2\r
+SCSI_Out__2__DR EQU CYREG_PRT6_DR\r
+SCSI_Out__2__INP_DIS EQU CYREG_PRT6_INP_DIS\r
+SCSI_Out__2__INTTYPE EQU CYREG_PICU6_INTTYPE1\r
+SCSI_Out__2__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
+SCSI_Out__2__LCD_EN EQU CYREG_PRT6_LCD_EN\r
+SCSI_Out__2__MASK EQU 0x02\r
+SCSI_Out__2__PC EQU CYREG_PRT6_PC1\r
+SCSI_Out__2__PORT EQU 6\r
+SCSI_Out__2__PRT EQU CYREG_PRT6_PRT\r
+SCSI_Out__2__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
+SCSI_Out__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
+SCSI_Out__2__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
+SCSI_Out__2__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
+SCSI_Out__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
+SCSI_Out__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
+SCSI_Out__2__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
+SCSI_Out__2__PS EQU CYREG_PRT6_PS\r
+SCSI_Out__2__SHIFT EQU 1\r
+SCSI_Out__2__SLW EQU CYREG_PRT6_SLW\r
+SCSI_Out__3__AG EQU CYREG_PRT6_AG\r
+SCSI_Out__3__AMUX EQU CYREG_PRT6_AMUX\r
+SCSI_Out__3__BIE EQU CYREG_PRT6_BIE\r
+SCSI_Out__3__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
+SCSI_Out__3__BYP EQU CYREG_PRT6_BYP\r
+SCSI_Out__3__CTL EQU CYREG_PRT6_CTL\r
+SCSI_Out__3__DM0 EQU CYREG_PRT6_DM0\r
+SCSI_Out__3__DM1 EQU CYREG_PRT6_DM1\r
+SCSI_Out__3__DM2 EQU CYREG_PRT6_DM2\r
+SCSI_Out__3__DR EQU CYREG_PRT6_DR\r
+SCSI_Out__3__INP_DIS EQU CYREG_PRT6_INP_DIS\r
+SCSI_Out__3__INTTYPE EQU CYREG_PICU6_INTTYPE0\r
+SCSI_Out__3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
+SCSI_Out__3__LCD_EN EQU CYREG_PRT6_LCD_EN\r
+SCSI_Out__3__MASK EQU 0x01\r
+SCSI_Out__3__PC EQU CYREG_PRT6_PC0\r
+SCSI_Out__3__PORT EQU 6\r
+SCSI_Out__3__PRT EQU CYREG_PRT6_PRT\r
+SCSI_Out__3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
+SCSI_Out__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
+SCSI_Out__3__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
+SCSI_Out__3__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
+SCSI_Out__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
+SCSI_Out__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
+SCSI_Out__3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
+SCSI_Out__3__PS EQU CYREG_PRT6_PS\r
+SCSI_Out__3__SHIFT EQU 0\r
+SCSI_Out__3__SLW EQU CYREG_PRT6_SLW\r
+SCSI_Out__4__AG EQU CYREG_PRT4_AG\r
+SCSI_Out__4__AMUX EQU CYREG_PRT4_AMUX\r
+SCSI_Out__4__BIE EQU CYREG_PRT4_BIE\r
+SCSI_Out__4__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
+SCSI_Out__4__BYP EQU CYREG_PRT4_BYP\r
+SCSI_Out__4__CTL EQU CYREG_PRT4_CTL\r
+SCSI_Out__4__DM0 EQU CYREG_PRT4_DM0\r
+SCSI_Out__4__DM1 EQU CYREG_PRT4_DM1\r
+SCSI_Out__4__DM2 EQU CYREG_PRT4_DM2\r
+SCSI_Out__4__DR EQU CYREG_PRT4_DR\r
+SCSI_Out__4__INP_DIS EQU CYREG_PRT4_INP_DIS\r
+SCSI_Out__4__INTTYPE EQU CYREG_PICU4_INTTYPE5\r
+SCSI_Out__4__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
+SCSI_Out__4__LCD_EN EQU CYREG_PRT4_LCD_EN\r
+SCSI_Out__4__MASK EQU 0x20\r
+SCSI_Out__4__PC EQU CYREG_PRT4_PC5\r
+SCSI_Out__4__PORT EQU 4\r
+SCSI_Out__4__PRT EQU CYREG_PRT4_PRT\r
+SCSI_Out__4__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
+SCSI_Out__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
+SCSI_Out__4__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
+SCSI_Out__4__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
+SCSI_Out__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
+SCSI_Out__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
+SCSI_Out__4__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
+SCSI_Out__4__PS EQU CYREG_PRT4_PS\r
+SCSI_Out__4__SHIFT EQU 5\r
+SCSI_Out__4__SLW EQU CYREG_PRT4_SLW\r
+SCSI_Out__5__AG EQU CYREG_PRT4_AG\r
+SCSI_Out__5__AMUX EQU CYREG_PRT4_AMUX\r
+SCSI_Out__5__BIE EQU CYREG_PRT4_BIE\r
+SCSI_Out__5__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
+SCSI_Out__5__BYP EQU CYREG_PRT4_BYP\r
+SCSI_Out__5__CTL EQU CYREG_PRT4_CTL\r
+SCSI_Out__5__DM0 EQU CYREG_PRT4_DM0\r
+SCSI_Out__5__DM1 EQU CYREG_PRT4_DM1\r
+SCSI_Out__5__DM2 EQU CYREG_PRT4_DM2\r
+SCSI_Out__5__DR EQU CYREG_PRT4_DR\r
+SCSI_Out__5__INP_DIS EQU CYREG_PRT4_INP_DIS\r
+SCSI_Out__5__INTTYPE EQU CYREG_PICU4_INTTYPE4\r
+SCSI_Out__5__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
+SCSI_Out__5__LCD_EN EQU CYREG_PRT4_LCD_EN\r
+SCSI_Out__5__MASK EQU 0x10\r
+SCSI_Out__5__PC EQU CYREG_PRT4_PC4\r
+SCSI_Out__5__PORT EQU 4\r
+SCSI_Out__5__PRT EQU CYREG_PRT4_PRT\r
+SCSI_Out__5__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
+SCSI_Out__5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
+SCSI_Out__5__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
+SCSI_Out__5__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
+SCSI_Out__5__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
+SCSI_Out__5__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
+SCSI_Out__5__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
+SCSI_Out__5__PS EQU CYREG_PRT4_PS\r
+SCSI_Out__5__SHIFT EQU 4\r
+SCSI_Out__5__SLW EQU CYREG_PRT4_SLW\r
+SCSI_Out__6__AG EQU CYREG_PRT0_AG\r
+SCSI_Out__6__AMUX EQU CYREG_PRT0_AMUX\r
+SCSI_Out__6__BIE EQU CYREG_PRT0_BIE\r
+SCSI_Out__6__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
+SCSI_Out__6__BYP EQU CYREG_PRT0_BYP\r
+SCSI_Out__6__CTL EQU CYREG_PRT0_CTL\r
+SCSI_Out__6__DM0 EQU CYREG_PRT0_DM0\r
+SCSI_Out__6__DM1 EQU CYREG_PRT0_DM1\r
+SCSI_Out__6__DM2 EQU CYREG_PRT0_DM2\r
+SCSI_Out__6__DR EQU CYREG_PRT0_DR\r
+SCSI_Out__6__INP_DIS EQU CYREG_PRT0_INP_DIS\r
+SCSI_Out__6__INTTYPE EQU CYREG_PICU0_INTTYPE7\r
+SCSI_Out__6__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
+SCSI_Out__6__LCD_EN EQU CYREG_PRT0_LCD_EN\r
+SCSI_Out__6__MASK EQU 0x80\r
+SCSI_Out__6__PC EQU CYREG_PRT0_PC7\r
+SCSI_Out__6__PORT EQU 0\r
+SCSI_Out__6__PRT EQU CYREG_PRT0_PRT\r
+SCSI_Out__6__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
+SCSI_Out__6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
+SCSI_Out__6__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
+SCSI_Out__6__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
+SCSI_Out__6__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
+SCSI_Out__6__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
+SCSI_Out__6__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
+SCSI_Out__6__PS EQU CYREG_PRT0_PS\r
+SCSI_Out__6__SHIFT EQU 7\r
+SCSI_Out__6__SLW EQU CYREG_PRT0_SLW\r
+SCSI_Out__7__AG EQU CYREG_PRT0_AG\r
+SCSI_Out__7__AMUX EQU CYREG_PRT0_AMUX\r
+SCSI_Out__7__BIE EQU CYREG_PRT0_BIE\r
+SCSI_Out__7__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
+SCSI_Out__7__BYP EQU CYREG_PRT0_BYP\r
+SCSI_Out__7__CTL EQU CYREG_PRT0_CTL\r
+SCSI_Out__7__DM0 EQU CYREG_PRT0_DM0\r
+SCSI_Out__7__DM1 EQU CYREG_PRT0_DM1\r
+SCSI_Out__7__DM2 EQU CYREG_PRT0_DM2\r
+SCSI_Out__7__DR EQU CYREG_PRT0_DR\r
+SCSI_Out__7__INP_DIS EQU CYREG_PRT0_INP_DIS\r
+SCSI_Out__7__INTTYPE EQU CYREG_PICU0_INTTYPE6\r
+SCSI_Out__7__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
+SCSI_Out__7__LCD_EN EQU CYREG_PRT0_LCD_EN\r
+SCSI_Out__7__MASK EQU 0x40\r
+SCSI_Out__7__PC EQU CYREG_PRT0_PC6\r
+SCSI_Out__7__PORT EQU 0\r
+SCSI_Out__7__PRT EQU CYREG_PRT0_PRT\r
+SCSI_Out__7__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
+SCSI_Out__7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
+SCSI_Out__7__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
+SCSI_Out__7__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
+SCSI_Out__7__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
+SCSI_Out__7__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
+SCSI_Out__7__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
+SCSI_Out__7__PS EQU CYREG_PRT0_PS\r
+SCSI_Out__7__SHIFT EQU 6\r
+SCSI_Out__7__SLW EQU CYREG_PRT0_SLW\r
+SCSI_Out__8__AG EQU CYREG_PRT0_AG\r
+SCSI_Out__8__AMUX EQU CYREG_PRT0_AMUX\r
+SCSI_Out__8__BIE EQU CYREG_PRT0_BIE\r
+SCSI_Out__8__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
+SCSI_Out__8__BYP EQU CYREG_PRT0_BYP\r
+SCSI_Out__8__CTL EQU CYREG_PRT0_CTL\r
+SCSI_Out__8__DM0 EQU CYREG_PRT0_DM0\r
+SCSI_Out__8__DM1 EQU CYREG_PRT0_DM1\r
+SCSI_Out__8__DM2 EQU CYREG_PRT0_DM2\r
+SCSI_Out__8__DR EQU CYREG_PRT0_DR\r
+SCSI_Out__8__INP_DIS EQU CYREG_PRT0_INP_DIS\r
+SCSI_Out__8__INTTYPE EQU CYREG_PICU0_INTTYPE3\r
+SCSI_Out__8__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
+SCSI_Out__8__LCD_EN EQU CYREG_PRT0_LCD_EN\r
+SCSI_Out__8__MASK EQU 0x08\r
+SCSI_Out__8__PC EQU CYREG_PRT0_PC3\r
+SCSI_Out__8__PORT EQU 0\r
+SCSI_Out__8__PRT EQU CYREG_PRT0_PRT\r
+SCSI_Out__8__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
+SCSI_Out__8__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
+SCSI_Out__8__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
+SCSI_Out__8__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
+SCSI_Out__8__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
+SCSI_Out__8__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
+SCSI_Out__8__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
+SCSI_Out__8__PS EQU CYREG_PRT0_PS\r
+SCSI_Out__8__SHIFT EQU 3\r
+SCSI_Out__8__SLW EQU CYREG_PRT0_SLW\r
+SCSI_Out__9__AG EQU CYREG_PRT0_AG\r
+SCSI_Out__9__AMUX EQU CYREG_PRT0_AMUX\r
+SCSI_Out__9__BIE EQU CYREG_PRT0_BIE\r
+SCSI_Out__9__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
+SCSI_Out__9__BYP EQU CYREG_PRT0_BYP\r
+SCSI_Out__9__CTL EQU CYREG_PRT0_CTL\r
+SCSI_Out__9__DM0 EQU CYREG_PRT0_DM0\r
+SCSI_Out__9__DM1 EQU CYREG_PRT0_DM1\r
+SCSI_Out__9__DM2 EQU CYREG_PRT0_DM2\r
+SCSI_Out__9__DR EQU CYREG_PRT0_DR\r
+SCSI_Out__9__INP_DIS EQU CYREG_PRT0_INP_DIS\r
+SCSI_Out__9__INTTYPE EQU CYREG_PICU0_INTTYPE2\r
+SCSI_Out__9__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
+SCSI_Out__9__LCD_EN EQU CYREG_PRT0_LCD_EN\r
+SCSI_Out__9__MASK EQU 0x04\r
+SCSI_Out__9__PC EQU CYREG_PRT0_PC2\r
+SCSI_Out__9__PORT EQU 0\r
+SCSI_Out__9__PRT EQU CYREG_PRT0_PRT\r
+SCSI_Out__9__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
+SCSI_Out__9__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
+SCSI_Out__9__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
+SCSI_Out__9__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
+SCSI_Out__9__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
+SCSI_Out__9__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
+SCSI_Out__9__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
+SCSI_Out__9__PS EQU CYREG_PRT0_PS\r
+SCSI_Out__9__SHIFT EQU 2\r
+SCSI_Out__9__SLW EQU CYREG_PRT0_SLW\r
+SCSI_Out__ACK__AG EQU CYREG_PRT6_AG\r
+SCSI_Out__ACK__AMUX EQU CYREG_PRT6_AMUX\r
+SCSI_Out__ACK__BIE EQU CYREG_PRT6_BIE\r
+SCSI_Out__ACK__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
+SCSI_Out__ACK__BYP EQU CYREG_PRT6_BYP\r
+SCSI_Out__ACK__CTL EQU CYREG_PRT6_CTL\r
+SCSI_Out__ACK__DM0 EQU CYREG_PRT6_DM0\r
+SCSI_Out__ACK__DM1 EQU CYREG_PRT6_DM1\r
+SCSI_Out__ACK__DM2 EQU CYREG_PRT6_DM2\r
+SCSI_Out__ACK__DR EQU CYREG_PRT6_DR\r
+SCSI_Out__ACK__INP_DIS EQU CYREG_PRT6_INP_DIS\r
+SCSI_Out__ACK__INTTYPE EQU CYREG_PICU6_INTTYPE0\r
+SCSI_Out__ACK__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
+SCSI_Out__ACK__LCD_EN EQU CYREG_PRT6_LCD_EN\r
+SCSI_Out__ACK__MASK EQU 0x01\r
+SCSI_Out__ACK__PC EQU CYREG_PRT6_PC0\r
+SCSI_Out__ACK__PORT EQU 6\r
+SCSI_Out__ACK__PRT EQU CYREG_PRT6_PRT\r
+SCSI_Out__ACK__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
+SCSI_Out__ACK__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
+SCSI_Out__ACK__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
+SCSI_Out__ACK__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
+SCSI_Out__ACK__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
+SCSI_Out__ACK__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
+SCSI_Out__ACK__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
+SCSI_Out__ACK__PS EQU CYREG_PRT6_PS\r
+SCSI_Out__ACK__SHIFT EQU 0\r
+SCSI_Out__ACK__SLW EQU CYREG_PRT6_SLW\r
+SCSI_Out__ATN__AG EQU CYREG_PRT15_AG\r
+SCSI_Out__ATN__AMUX EQU CYREG_PRT15_AMUX\r
+SCSI_Out__ATN__BIE EQU CYREG_PRT15_BIE\r
+SCSI_Out__ATN__BIT_MASK EQU CYREG_PRT15_BIT_MASK\r
+SCSI_Out__ATN__BYP EQU CYREG_PRT15_BYP\r
+SCSI_Out__ATN__CTL EQU CYREG_PRT15_CTL\r
+SCSI_Out__ATN__DM0 EQU CYREG_PRT15_DM0\r
+SCSI_Out__ATN__DM1 EQU CYREG_PRT15_DM1\r
+SCSI_Out__ATN__DM2 EQU CYREG_PRT15_DM2\r
+SCSI_Out__ATN__DR EQU CYREG_PRT15_DR\r
+SCSI_Out__ATN__INP_DIS EQU CYREG_PRT15_INP_DIS\r
+SCSI_Out__ATN__INTTYPE EQU CYREG_PICU15_INTTYPE4\r
+SCSI_Out__ATN__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG\r
+SCSI_Out__ATN__LCD_EN EQU CYREG_PRT15_LCD_EN\r
+SCSI_Out__ATN__MASK EQU 0x10\r
+SCSI_Out__ATN__PC EQU CYREG_IO_PC_PRT15_PC4\r
+SCSI_Out__ATN__PORT EQU 15\r
+SCSI_Out__ATN__PRT EQU CYREG_PRT15_PRT\r
+SCSI_Out__ATN__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL\r
+SCSI_Out__ATN__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN\r
+SCSI_Out__ATN__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0\r
+SCSI_Out__ATN__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1\r
+SCSI_Out__ATN__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0\r
+SCSI_Out__ATN__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1\r
+SCSI_Out__ATN__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT\r
+SCSI_Out__ATN__PS EQU CYREG_PRT15_PS\r
+SCSI_Out__ATN__SHIFT EQU 4\r
+SCSI_Out__ATN__SLW EQU CYREG_PRT15_SLW\r
+SCSI_Out__BSY__AG EQU CYREG_PRT6_AG\r
+SCSI_Out__BSY__AMUX EQU CYREG_PRT6_AMUX\r
+SCSI_Out__BSY__BIE EQU CYREG_PRT6_BIE\r
+SCSI_Out__BSY__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
+SCSI_Out__BSY__BYP EQU CYREG_PRT6_BYP\r
+SCSI_Out__BSY__CTL EQU CYREG_PRT6_CTL\r
+SCSI_Out__BSY__DM0 EQU CYREG_PRT6_DM0\r
+SCSI_Out__BSY__DM1 EQU CYREG_PRT6_DM1\r
+SCSI_Out__BSY__DM2 EQU CYREG_PRT6_DM2\r
+SCSI_Out__BSY__DR EQU CYREG_PRT6_DR\r
+SCSI_Out__BSY__INP_DIS EQU CYREG_PRT6_INP_DIS\r
+SCSI_Out__BSY__INTTYPE EQU CYREG_PICU6_INTTYPE1\r
+SCSI_Out__BSY__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
+SCSI_Out__BSY__LCD_EN EQU CYREG_PRT6_LCD_EN\r
+SCSI_Out__BSY__MASK EQU 0x02\r
+SCSI_Out__BSY__PC EQU CYREG_PRT6_PC1\r
+SCSI_Out__BSY__PORT EQU 6\r
+SCSI_Out__BSY__PRT EQU CYREG_PRT6_PRT\r
+SCSI_Out__BSY__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
+SCSI_Out__BSY__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
+SCSI_Out__BSY__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
+SCSI_Out__BSY__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
+SCSI_Out__BSY__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
+SCSI_Out__BSY__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
+SCSI_Out__BSY__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
+SCSI_Out__BSY__PS EQU CYREG_PRT6_PS\r
+SCSI_Out__BSY__SHIFT EQU 1\r
+SCSI_Out__BSY__SLW EQU CYREG_PRT6_SLW\r
+SCSI_Out__CD_raw__AG EQU CYREG_PRT0_AG\r
+SCSI_Out__CD_raw__AMUX EQU CYREG_PRT0_AMUX\r
+SCSI_Out__CD_raw__BIE EQU CYREG_PRT0_BIE\r
+SCSI_Out__CD_raw__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
+SCSI_Out__CD_raw__BYP EQU CYREG_PRT0_BYP\r
+SCSI_Out__CD_raw__CTL EQU CYREG_PRT0_CTL\r
+SCSI_Out__CD_raw__DM0 EQU CYREG_PRT0_DM0\r
+SCSI_Out__CD_raw__DM1 EQU CYREG_PRT0_DM1\r
+SCSI_Out__CD_raw__DM2 EQU CYREG_PRT0_DM2\r
+SCSI_Out__CD_raw__DR EQU CYREG_PRT0_DR\r
+SCSI_Out__CD_raw__INP_DIS EQU CYREG_PRT0_INP_DIS\r
+SCSI_Out__CD_raw__INTTYPE EQU CYREG_PICU0_INTTYPE6\r
+SCSI_Out__CD_raw__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
+SCSI_Out__CD_raw__LCD_EN EQU CYREG_PRT0_LCD_EN\r
+SCSI_Out__CD_raw__MASK EQU 0x40\r
+SCSI_Out__CD_raw__PC EQU CYREG_PRT0_PC6\r
+SCSI_Out__CD_raw__PORT EQU 0\r
+SCSI_Out__CD_raw__PRT EQU CYREG_PRT0_PRT\r
+SCSI_Out__CD_raw__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
+SCSI_Out__CD_raw__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
+SCSI_Out__CD_raw__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
+SCSI_Out__CD_raw__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
+SCSI_Out__CD_raw__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
+SCSI_Out__CD_raw__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
+SCSI_Out__CD_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
+SCSI_Out__CD_raw__PS EQU CYREG_PRT0_PS\r
+SCSI_Out__CD_raw__SHIFT EQU 6\r
+SCSI_Out__CD_raw__SLW EQU CYREG_PRT0_SLW\r
+SCSI_Out__DBP_raw__AG EQU CYREG_PRT15_AG\r
+SCSI_Out__DBP_raw__AMUX EQU CYREG_PRT15_AMUX\r
+SCSI_Out__DBP_raw__BIE EQU CYREG_PRT15_BIE\r
+SCSI_Out__DBP_raw__BIT_MASK EQU CYREG_PRT15_BIT_MASK\r
+SCSI_Out__DBP_raw__BYP EQU CYREG_PRT15_BYP\r
+SCSI_Out__DBP_raw__CTL EQU CYREG_PRT15_CTL\r
+SCSI_Out__DBP_raw__DM0 EQU CYREG_PRT15_DM0\r
+SCSI_Out__DBP_raw__DM1 EQU CYREG_PRT15_DM1\r
+SCSI_Out__DBP_raw__DM2 EQU CYREG_PRT15_DM2\r
+SCSI_Out__DBP_raw__DR EQU CYREG_PRT15_DR\r
+SCSI_Out__DBP_raw__INP_DIS EQU CYREG_PRT15_INP_DIS\r
+SCSI_Out__DBP_raw__INTTYPE EQU CYREG_PICU15_INTTYPE5\r
+SCSI_Out__DBP_raw__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG\r
+SCSI_Out__DBP_raw__LCD_EN EQU CYREG_PRT15_LCD_EN\r
+SCSI_Out__DBP_raw__MASK EQU 0x20\r
+SCSI_Out__DBP_raw__PC EQU CYREG_IO_PC_PRT15_PC5\r
+SCSI_Out__DBP_raw__PORT EQU 15\r
+SCSI_Out__DBP_raw__PRT EQU CYREG_PRT15_PRT\r
+SCSI_Out__DBP_raw__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL\r
+SCSI_Out__DBP_raw__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN\r
+SCSI_Out__DBP_raw__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0\r
+SCSI_Out__DBP_raw__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1\r
+SCSI_Out__DBP_raw__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0\r
+SCSI_Out__DBP_raw__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1\r
+SCSI_Out__DBP_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT\r
+SCSI_Out__DBP_raw__PS EQU CYREG_PRT15_PS\r
+SCSI_Out__DBP_raw__SHIFT EQU 5\r
+SCSI_Out__DBP_raw__SLW EQU CYREG_PRT15_SLW\r
+SCSI_Out__IO_raw__AG EQU CYREG_PRT0_AG\r
+SCSI_Out__IO_raw__AMUX EQU CYREG_PRT0_AMUX\r
+SCSI_Out__IO_raw__BIE EQU CYREG_PRT0_BIE\r
+SCSI_Out__IO_raw__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
+SCSI_Out__IO_raw__BYP EQU CYREG_PRT0_BYP\r
+SCSI_Out__IO_raw__CTL EQU CYREG_PRT0_CTL\r
+SCSI_Out__IO_raw__DM0 EQU CYREG_PRT0_DM0\r
+SCSI_Out__IO_raw__DM1 EQU CYREG_PRT0_DM1\r
+SCSI_Out__IO_raw__DM2 EQU CYREG_PRT0_DM2\r
+SCSI_Out__IO_raw__DR EQU CYREG_PRT0_DR\r
+SCSI_Out__IO_raw__INP_DIS EQU CYREG_PRT0_INP_DIS\r
+SCSI_Out__IO_raw__INTTYPE EQU CYREG_PICU0_INTTYPE2\r
+SCSI_Out__IO_raw__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
+SCSI_Out__IO_raw__LCD_EN EQU CYREG_PRT0_LCD_EN\r
+SCSI_Out__IO_raw__MASK EQU 0x04\r
+SCSI_Out__IO_raw__PC EQU CYREG_PRT0_PC2\r
+SCSI_Out__IO_raw__PORT EQU 0\r
+SCSI_Out__IO_raw__PRT EQU CYREG_PRT0_PRT\r
+SCSI_Out__IO_raw__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
+SCSI_Out__IO_raw__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
+SCSI_Out__IO_raw__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
+SCSI_Out__IO_raw__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
+SCSI_Out__IO_raw__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
+SCSI_Out__IO_raw__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
+SCSI_Out__IO_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
+SCSI_Out__IO_raw__PS EQU CYREG_PRT0_PS\r
+SCSI_Out__IO_raw__SHIFT EQU 2\r
+SCSI_Out__IO_raw__SLW EQU CYREG_PRT0_SLW\r
+SCSI_Out__MSG_raw__AG EQU CYREG_PRT4_AG\r
+SCSI_Out__MSG_raw__AMUX EQU CYREG_PRT4_AMUX\r
+SCSI_Out__MSG_raw__BIE EQU CYREG_PRT4_BIE\r
+SCSI_Out__MSG_raw__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
+SCSI_Out__MSG_raw__BYP EQU CYREG_PRT4_BYP\r
+SCSI_Out__MSG_raw__CTL EQU CYREG_PRT4_CTL\r
+SCSI_Out__MSG_raw__DM0 EQU CYREG_PRT4_DM0\r
+SCSI_Out__MSG_raw__DM1 EQU CYREG_PRT4_DM1\r
+SCSI_Out__MSG_raw__DM2 EQU CYREG_PRT4_DM2\r
+SCSI_Out__MSG_raw__DR EQU CYREG_PRT4_DR\r
+SCSI_Out__MSG_raw__INP_DIS EQU CYREG_PRT4_INP_DIS\r
+SCSI_Out__MSG_raw__INTTYPE EQU CYREG_PICU4_INTTYPE4\r
+SCSI_Out__MSG_raw__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
+SCSI_Out__MSG_raw__LCD_EN EQU CYREG_PRT4_LCD_EN\r
+SCSI_Out__MSG_raw__MASK EQU 0x10\r
+SCSI_Out__MSG_raw__PC EQU CYREG_PRT4_PC4\r
+SCSI_Out__MSG_raw__PORT EQU 4\r
+SCSI_Out__MSG_raw__PRT EQU CYREG_PRT4_PRT\r
+SCSI_Out__MSG_raw__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
+SCSI_Out__MSG_raw__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
+SCSI_Out__MSG_raw__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
+SCSI_Out__MSG_raw__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
+SCSI_Out__MSG_raw__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
+SCSI_Out__MSG_raw__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
+SCSI_Out__MSG_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
+SCSI_Out__MSG_raw__PS EQU CYREG_PRT4_PS\r
+SCSI_Out__MSG_raw__SHIFT EQU 4\r
+SCSI_Out__MSG_raw__SLW EQU CYREG_PRT4_SLW\r
+SCSI_Out__REQ__AG EQU CYREG_PRT0_AG\r
+SCSI_Out__REQ__AMUX EQU CYREG_PRT0_AMUX\r
+SCSI_Out__REQ__BIE EQU CYREG_PRT0_BIE\r
+SCSI_Out__REQ__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
+SCSI_Out__REQ__BYP EQU CYREG_PRT0_BYP\r
+SCSI_Out__REQ__CTL EQU CYREG_PRT0_CTL\r
+SCSI_Out__REQ__DM0 EQU CYREG_PRT0_DM0\r
+SCSI_Out__REQ__DM1 EQU CYREG_PRT0_DM1\r
+SCSI_Out__REQ__DM2 EQU CYREG_PRT0_DM2\r
+SCSI_Out__REQ__DR EQU CYREG_PRT0_DR\r
+SCSI_Out__REQ__INP_DIS EQU CYREG_PRT0_INP_DIS\r
+SCSI_Out__REQ__INTTYPE EQU CYREG_PICU0_INTTYPE3\r
+SCSI_Out__REQ__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
+SCSI_Out__REQ__LCD_EN EQU CYREG_PRT0_LCD_EN\r
+SCSI_Out__REQ__MASK EQU 0x08\r
+SCSI_Out__REQ__PC EQU CYREG_PRT0_PC3\r
+SCSI_Out__REQ__PORT EQU 0\r
+SCSI_Out__REQ__PRT EQU CYREG_PRT0_PRT\r
+SCSI_Out__REQ__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
+SCSI_Out__REQ__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
+SCSI_Out__REQ__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
+SCSI_Out__REQ__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
+SCSI_Out__REQ__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
+SCSI_Out__REQ__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
+SCSI_Out__REQ__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
+SCSI_Out__REQ__PS EQU CYREG_PRT0_PS\r
+SCSI_Out__REQ__SHIFT EQU 3\r
+SCSI_Out__REQ__SLW EQU CYREG_PRT0_SLW\r
+SCSI_Out__RST__AG EQU CYREG_PRT4_AG\r
+SCSI_Out__RST__AMUX EQU CYREG_PRT4_AMUX\r
+SCSI_Out__RST__BIE EQU CYREG_PRT4_BIE\r
+SCSI_Out__RST__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
+SCSI_Out__RST__BYP EQU CYREG_PRT4_BYP\r
+SCSI_Out__RST__CTL EQU CYREG_PRT4_CTL\r
+SCSI_Out__RST__DM0 EQU CYREG_PRT4_DM0\r
+SCSI_Out__RST__DM1 EQU CYREG_PRT4_DM1\r
+SCSI_Out__RST__DM2 EQU CYREG_PRT4_DM2\r
+SCSI_Out__RST__DR EQU CYREG_PRT4_DR\r
+SCSI_Out__RST__INP_DIS EQU CYREG_PRT4_INP_DIS\r
+SCSI_Out__RST__INTTYPE EQU CYREG_PICU4_INTTYPE5\r
+SCSI_Out__RST__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
+SCSI_Out__RST__LCD_EN EQU CYREG_PRT4_LCD_EN\r
+SCSI_Out__RST__MASK EQU 0x20\r
+SCSI_Out__RST__PC EQU CYREG_PRT4_PC5\r
+SCSI_Out__RST__PORT EQU 4\r
+SCSI_Out__RST__PRT EQU CYREG_PRT4_PRT\r
+SCSI_Out__RST__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
+SCSI_Out__RST__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
+SCSI_Out__RST__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
+SCSI_Out__RST__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
+SCSI_Out__RST__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
+SCSI_Out__RST__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
+SCSI_Out__RST__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
+SCSI_Out__RST__PS EQU CYREG_PRT4_PS\r
+SCSI_Out__RST__SHIFT EQU 5\r
+SCSI_Out__RST__SLW EQU CYREG_PRT4_SLW\r
+SCSI_Out__SEL__AG EQU CYREG_PRT0_AG\r
+SCSI_Out__SEL__AMUX EQU CYREG_PRT0_AMUX\r
+SCSI_Out__SEL__BIE EQU CYREG_PRT0_BIE\r
+SCSI_Out__SEL__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
+SCSI_Out__SEL__BYP EQU CYREG_PRT0_BYP\r
+SCSI_Out__SEL__CTL EQU CYREG_PRT0_CTL\r
+SCSI_Out__SEL__DM0 EQU CYREG_PRT0_DM0\r
+SCSI_Out__SEL__DM1 EQU CYREG_PRT0_DM1\r
+SCSI_Out__SEL__DM2 EQU CYREG_PRT0_DM2\r
+SCSI_Out__SEL__DR EQU CYREG_PRT0_DR\r
+SCSI_Out__SEL__INP_DIS EQU CYREG_PRT0_INP_DIS\r
+SCSI_Out__SEL__INTTYPE EQU CYREG_PICU0_INTTYPE7\r
+SCSI_Out__SEL__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
+SCSI_Out__SEL__LCD_EN EQU CYREG_PRT0_LCD_EN\r
+SCSI_Out__SEL__MASK EQU 0x80\r
+SCSI_Out__SEL__PC EQU CYREG_PRT0_PC7\r
+SCSI_Out__SEL__PORT EQU 0\r
+SCSI_Out__SEL__PRT EQU CYREG_PRT0_PRT\r
+SCSI_Out__SEL__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
+SCSI_Out__SEL__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
+SCSI_Out__SEL__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
+SCSI_Out__SEL__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
+SCSI_Out__SEL__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
+SCSI_Out__SEL__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
+SCSI_Out__SEL__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
+SCSI_Out__SEL__PS EQU CYREG_PRT0_PS\r
+SCSI_Out__SEL__SHIFT EQU 7\r
+SCSI_Out__SEL__SLW EQU CYREG_PRT0_SLW\r
+SCSI_Out_Bits_Sync_ctrl_reg__0__MASK EQU 0x01\r
+SCSI_Out_Bits_Sync_ctrl_reg__0__POS EQU 0\r
+SCSI_Out_Bits_Sync_ctrl_reg__1__MASK EQU 0x02\r
+SCSI_Out_Bits_Sync_ctrl_reg__1__POS EQU 1\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB14_15_ACTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB14_15_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB14_15_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB14_15_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB14_15_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB14_15_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB14_15_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB14_15_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB14_15_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__2__MASK EQU 0x04\r
+SCSI_Out_Bits_Sync_ctrl_reg__2__POS EQU 2\r
+SCSI_Out_Bits_Sync_ctrl_reg__3__MASK EQU 0x08\r
+SCSI_Out_Bits_Sync_ctrl_reg__3__POS EQU 3\r
+SCSI_Out_Bits_Sync_ctrl_reg__4__MASK EQU 0x10\r
+SCSI_Out_Bits_Sync_ctrl_reg__4__POS EQU 4\r
+SCSI_Out_Bits_Sync_ctrl_reg__5__MASK EQU 0x20\r
+SCSI_Out_Bits_Sync_ctrl_reg__5__POS EQU 5\r
+SCSI_Out_Bits_Sync_ctrl_reg__6__MASK EQU 0x40\r
+SCSI_Out_Bits_Sync_ctrl_reg__6__POS EQU 6\r
+SCSI_Out_Bits_Sync_ctrl_reg__7__MASK EQU 0x80\r
+SCSI_Out_Bits_Sync_ctrl_reg__7__POS EQU 7\r
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB14_ACTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB14_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB14_ST_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB14_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB14_ST_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__MASK EQU 0xFF\r
+SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB14_MSK_ACTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB14_MSK_ACTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB14_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01\r
+SCSI_Out_Ctl_Sync_ctrl_reg__0__POS EQU 0\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB12_13_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB12_13_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB12_13_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB12_13_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB12_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB12_ST_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB12_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB12_ST_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__MASK EQU 0x01\r
+SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB12_MSK\r
+SCSI_Out_DBx__0__AG EQU CYREG_PRT5_AG\r
+SCSI_Out_DBx__0__AMUX EQU CYREG_PRT5_AMUX\r
+SCSI_Out_DBx__0__BIE EQU CYREG_PRT5_BIE\r
+SCSI_Out_DBx__0__BIT_MASK EQU CYREG_PRT5_BIT_MASK\r
+SCSI_Out_DBx__0__BYP EQU CYREG_PRT5_BYP\r
+SCSI_Out_DBx__0__CTL EQU CYREG_PRT5_CTL\r
+SCSI_Out_DBx__0__DM0 EQU CYREG_PRT5_DM0\r
+SCSI_Out_DBx__0__DM1 EQU CYREG_PRT5_DM1\r
+SCSI_Out_DBx__0__DM2 EQU CYREG_PRT5_DM2\r
+SCSI_Out_DBx__0__DR EQU CYREG_PRT5_DR\r
+SCSI_Out_DBx__0__INP_DIS EQU CYREG_PRT5_INP_DIS\r
+SCSI_Out_DBx__0__INTTYPE EQU CYREG_PICU5_INTTYPE1\r
+SCSI_Out_DBx__0__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG\r
+SCSI_Out_DBx__0__LCD_EN EQU CYREG_PRT5_LCD_EN\r
+SCSI_Out_DBx__0__MASK EQU 0x02\r
+SCSI_Out_DBx__0__PC EQU CYREG_PRT5_PC1\r
+SCSI_Out_DBx__0__PORT EQU 5\r
+SCSI_Out_DBx__0__PRT EQU CYREG_PRT5_PRT\r
+SCSI_Out_DBx__0__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL\r
+SCSI_Out_DBx__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN\r
+SCSI_Out_DBx__0__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0\r
+SCSI_Out_DBx__0__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1\r
+SCSI_Out_DBx__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0\r
+SCSI_Out_DBx__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1\r
+SCSI_Out_DBx__0__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT\r
+SCSI_Out_DBx__0__PS EQU CYREG_PRT5_PS\r
+SCSI_Out_DBx__0__SHIFT EQU 1\r
+SCSI_Out_DBx__0__SLW EQU CYREG_PRT5_SLW\r
+SCSI_Out_DBx__1__AG EQU CYREG_PRT5_AG\r
+SCSI_Out_DBx__1__AMUX EQU CYREG_PRT5_AMUX\r
+SCSI_Out_DBx__1__BIE EQU CYREG_PRT5_BIE\r
+SCSI_Out_DBx__1__BIT_MASK EQU CYREG_PRT5_BIT_MASK\r
+SCSI_Out_DBx__1__BYP EQU CYREG_PRT5_BYP\r
+SCSI_Out_DBx__1__CTL EQU CYREG_PRT5_CTL\r
+SCSI_Out_DBx__1__DM0 EQU CYREG_PRT5_DM0\r
+SCSI_Out_DBx__1__DM1 EQU CYREG_PRT5_DM1\r
+SCSI_Out_DBx__1__DM2 EQU CYREG_PRT5_DM2\r
+SCSI_Out_DBx__1__DR EQU CYREG_PRT5_DR\r
+SCSI_Out_DBx__1__INP_DIS EQU CYREG_PRT5_INP_DIS\r
+SCSI_Out_DBx__1__INTTYPE EQU CYREG_PICU5_INTTYPE0\r
+SCSI_Out_DBx__1__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG\r
+SCSI_Out_DBx__1__LCD_EN EQU CYREG_PRT5_LCD_EN\r
+SCSI_Out_DBx__1__MASK EQU 0x01\r
+SCSI_Out_DBx__1__PC EQU CYREG_PRT5_PC0\r
+SCSI_Out_DBx__1__PORT EQU 5\r
+SCSI_Out_DBx__1__PRT EQU CYREG_PRT5_PRT\r
+SCSI_Out_DBx__1__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL\r
+SCSI_Out_DBx__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN\r
+SCSI_Out_DBx__1__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0\r
+SCSI_Out_DBx__1__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1\r
+SCSI_Out_DBx__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0\r
+SCSI_Out_DBx__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1\r
+SCSI_Out_DBx__1__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT\r
+SCSI_Out_DBx__1__PS EQU CYREG_PRT5_PS\r
+SCSI_Out_DBx__1__SHIFT EQU 0\r
+SCSI_Out_DBx__1__SLW EQU CYREG_PRT5_SLW\r
+SCSI_Out_DBx__2__AG EQU CYREG_PRT6_AG\r
+SCSI_Out_DBx__2__AMUX EQU CYREG_PRT6_AMUX\r
+SCSI_Out_DBx__2__BIE EQU CYREG_PRT6_BIE\r
+SCSI_Out_DBx__2__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
+SCSI_Out_DBx__2__BYP EQU CYREG_PRT6_BYP\r
+SCSI_Out_DBx__2__CTL EQU CYREG_PRT6_CTL\r
+SCSI_Out_DBx__2__DM0 EQU CYREG_PRT6_DM0\r
+SCSI_Out_DBx__2__DM1 EQU CYREG_PRT6_DM1\r
+SCSI_Out_DBx__2__DM2 EQU CYREG_PRT6_DM2\r
+SCSI_Out_DBx__2__DR EQU CYREG_PRT6_DR\r
+SCSI_Out_DBx__2__INP_DIS EQU CYREG_PRT6_INP_DIS\r
+SCSI_Out_DBx__2__INTTYPE EQU CYREG_PICU6_INTTYPE5\r
+SCSI_Out_DBx__2__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
+SCSI_Out_DBx__2__LCD_EN EQU CYREG_PRT6_LCD_EN\r
+SCSI_Out_DBx__2__MASK EQU 0x20\r
+SCSI_Out_DBx__2__PC EQU CYREG_PRT6_PC5\r
+SCSI_Out_DBx__2__PORT EQU 6\r
+SCSI_Out_DBx__2__PRT EQU CYREG_PRT6_PRT\r
+SCSI_Out_DBx__2__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
+SCSI_Out_DBx__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
+SCSI_Out_DBx__2__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
+SCSI_Out_DBx__2__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
+SCSI_Out_DBx__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
+SCSI_Out_DBx__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
+SCSI_Out_DBx__2__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
+SCSI_Out_DBx__2__PS EQU CYREG_PRT6_PS\r
+SCSI_Out_DBx__2__SHIFT EQU 5\r
+SCSI_Out_DBx__2__SLW EQU CYREG_PRT6_SLW\r
+SCSI_Out_DBx__3__AG EQU CYREG_PRT6_AG\r
+SCSI_Out_DBx__3__AMUX EQU CYREG_PRT6_AMUX\r
+SCSI_Out_DBx__3__BIE EQU CYREG_PRT6_BIE\r
+SCSI_Out_DBx__3__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
+SCSI_Out_DBx__3__BYP EQU CYREG_PRT6_BYP\r
+SCSI_Out_DBx__3__CTL EQU CYREG_PRT6_CTL\r
+SCSI_Out_DBx__3__DM0 EQU CYREG_PRT6_DM0\r
+SCSI_Out_DBx__3__DM1 EQU CYREG_PRT6_DM1\r
+SCSI_Out_DBx__3__DM2 EQU CYREG_PRT6_DM2\r
+SCSI_Out_DBx__3__DR EQU CYREG_PRT6_DR\r
+SCSI_Out_DBx__3__INP_DIS EQU CYREG_PRT6_INP_DIS\r
+SCSI_Out_DBx__3__INTTYPE EQU CYREG_PICU6_INTTYPE4\r
+SCSI_Out_DBx__3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
+SCSI_Out_DBx__3__LCD_EN EQU CYREG_PRT6_LCD_EN\r
+SCSI_Out_DBx__3__MASK EQU 0x10\r
+SCSI_Out_DBx__3__PC EQU CYREG_PRT6_PC4\r
+SCSI_Out_DBx__3__PORT EQU 6\r
+SCSI_Out_DBx__3__PRT EQU CYREG_PRT6_PRT\r
+SCSI_Out_DBx__3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
+SCSI_Out_DBx__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
+SCSI_Out_DBx__3__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
+SCSI_Out_DBx__3__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
+SCSI_Out_DBx__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
+SCSI_Out_DBx__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
+SCSI_Out_DBx__3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
+SCSI_Out_DBx__3__PS EQU CYREG_PRT6_PS\r
+SCSI_Out_DBx__3__SHIFT EQU 4\r
+SCSI_Out_DBx__3__SLW EQU CYREG_PRT6_SLW\r
+SCSI_Out_DBx__4__AG EQU CYREG_PRT2_AG\r
+SCSI_Out_DBx__4__AMUX EQU CYREG_PRT2_AMUX\r
+SCSI_Out_DBx__4__BIE EQU CYREG_PRT2_BIE\r
+SCSI_Out_DBx__4__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
+SCSI_Out_DBx__4__BYP EQU CYREG_PRT2_BYP\r
+SCSI_Out_DBx__4__CTL EQU CYREG_PRT2_CTL\r
+SCSI_Out_DBx__4__DM0 EQU CYREG_PRT2_DM0\r
+SCSI_Out_DBx__4__DM1 EQU CYREG_PRT2_DM1\r
+SCSI_Out_DBx__4__DM2 EQU CYREG_PRT2_DM2\r
+SCSI_Out_DBx__4__DR EQU CYREG_PRT2_DR\r
+SCSI_Out_DBx__4__INP_DIS EQU CYREG_PRT2_INP_DIS\r
+SCSI_Out_DBx__4__INTTYPE EQU CYREG_PICU2_INTTYPE7\r
+SCSI_Out_DBx__4__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
+SCSI_Out_DBx__4__LCD_EN EQU CYREG_PRT2_LCD_EN\r
+SCSI_Out_DBx__4__MASK EQU 0x80\r
+SCSI_Out_DBx__4__PC EQU CYREG_PRT2_PC7\r
+SCSI_Out_DBx__4__PORT EQU 2\r
+SCSI_Out_DBx__4__PRT EQU CYREG_PRT2_PRT\r
+SCSI_Out_DBx__4__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
+SCSI_Out_DBx__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
+SCSI_Out_DBx__4__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
+SCSI_Out_DBx__4__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
+SCSI_Out_DBx__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
+SCSI_Out_DBx__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
+SCSI_Out_DBx__4__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
+SCSI_Out_DBx__4__PS EQU CYREG_PRT2_PS\r
+SCSI_Out_DBx__4__SHIFT EQU 7\r
+SCSI_Out_DBx__4__SLW EQU CYREG_PRT2_SLW\r
+SCSI_Out_DBx__5__AG EQU CYREG_PRT2_AG\r
+SCSI_Out_DBx__5__AMUX EQU CYREG_PRT2_AMUX\r
+SCSI_Out_DBx__5__BIE EQU CYREG_PRT2_BIE\r
+SCSI_Out_DBx__5__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
+SCSI_Out_DBx__5__BYP EQU CYREG_PRT2_BYP\r
+SCSI_Out_DBx__5__CTL EQU CYREG_PRT2_CTL\r
+SCSI_Out_DBx__5__DM0 EQU CYREG_PRT2_DM0\r
+SCSI_Out_DBx__5__DM1 EQU CYREG_PRT2_DM1\r
+SCSI_Out_DBx__5__DM2 EQU CYREG_PRT2_DM2\r
+SCSI_Out_DBx__5__DR EQU CYREG_PRT2_DR\r
+SCSI_Out_DBx__5__INP_DIS EQU CYREG_PRT2_INP_DIS\r
+SCSI_Out_DBx__5__INTTYPE EQU CYREG_PICU2_INTTYPE6\r
+SCSI_Out_DBx__5__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
+SCSI_Out_DBx__5__LCD_EN EQU CYREG_PRT2_LCD_EN\r
+SCSI_Out_DBx__5__MASK EQU 0x40\r
+SCSI_Out_DBx__5__PC EQU CYREG_PRT2_PC6\r
+SCSI_Out_DBx__5__PORT EQU 2\r
+SCSI_Out_DBx__5__PRT EQU CYREG_PRT2_PRT\r
+SCSI_Out_DBx__5__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
+SCSI_Out_DBx__5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
+SCSI_Out_DBx__5__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
+SCSI_Out_DBx__5__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
+SCSI_Out_DBx__5__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
+SCSI_Out_DBx__5__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
+SCSI_Out_DBx__5__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
+SCSI_Out_DBx__5__PS EQU CYREG_PRT2_PS\r
+SCSI_Out_DBx__5__SHIFT EQU 6\r
+SCSI_Out_DBx__5__SLW EQU CYREG_PRT2_SLW\r
+SCSI_Out_DBx__6__AG EQU CYREG_PRT2_AG\r
+SCSI_Out_DBx__6__AMUX EQU CYREG_PRT2_AMUX\r
+SCSI_Out_DBx__6__BIE EQU CYREG_PRT2_BIE\r
+SCSI_Out_DBx__6__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
+SCSI_Out_DBx__6__BYP EQU CYREG_PRT2_BYP\r
+SCSI_Out_DBx__6__CTL EQU CYREG_PRT2_CTL\r
+SCSI_Out_DBx__6__DM0 EQU CYREG_PRT2_DM0\r
+SCSI_Out_DBx__6__DM1 EQU CYREG_PRT2_DM1\r
+SCSI_Out_DBx__6__DM2 EQU CYREG_PRT2_DM2\r
+SCSI_Out_DBx__6__DR EQU CYREG_PRT2_DR\r
+SCSI_Out_DBx__6__INP_DIS EQU CYREG_PRT2_INP_DIS\r
+SCSI_Out_DBx__6__INTTYPE EQU CYREG_PICU2_INTTYPE3\r
+SCSI_Out_DBx__6__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
+SCSI_Out_DBx__6__LCD_EN EQU CYREG_PRT2_LCD_EN\r
+SCSI_Out_DBx__6__MASK EQU 0x08\r
+SCSI_Out_DBx__6__PC EQU CYREG_PRT2_PC3\r
+SCSI_Out_DBx__6__PORT EQU 2\r
+SCSI_Out_DBx__6__PRT EQU CYREG_PRT2_PRT\r
+SCSI_Out_DBx__6__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
+SCSI_Out_DBx__6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
+SCSI_Out_DBx__6__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
+SCSI_Out_DBx__6__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
+SCSI_Out_DBx__6__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
+SCSI_Out_DBx__6__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
+SCSI_Out_DBx__6__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
+SCSI_Out_DBx__6__PS EQU CYREG_PRT2_PS\r
+SCSI_Out_DBx__6__SHIFT EQU 3\r
+SCSI_Out_DBx__6__SLW EQU CYREG_PRT2_SLW\r
+SCSI_Out_DBx__7__AG EQU CYREG_PRT2_AG\r
+SCSI_Out_DBx__7__AMUX EQU CYREG_PRT2_AMUX\r
+SCSI_Out_DBx__7__BIE EQU CYREG_PRT2_BIE\r
+SCSI_Out_DBx__7__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
+SCSI_Out_DBx__7__BYP EQU CYREG_PRT2_BYP\r
+SCSI_Out_DBx__7__CTL EQU CYREG_PRT2_CTL\r
+SCSI_Out_DBx__7__DM0 EQU CYREG_PRT2_DM0\r
+SCSI_Out_DBx__7__DM1 EQU CYREG_PRT2_DM1\r
+SCSI_Out_DBx__7__DM2 EQU CYREG_PRT2_DM2\r
+SCSI_Out_DBx__7__DR EQU CYREG_PRT2_DR\r
+SCSI_Out_DBx__7__INP_DIS EQU CYREG_PRT2_INP_DIS\r
+SCSI_Out_DBx__7__INTTYPE EQU CYREG_PICU2_INTTYPE2\r
+SCSI_Out_DBx__7__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
+SCSI_Out_DBx__7__LCD_EN EQU CYREG_PRT2_LCD_EN\r
+SCSI_Out_DBx__7__MASK EQU 0x04\r
+SCSI_Out_DBx__7__PC EQU CYREG_PRT2_PC2\r
+SCSI_Out_DBx__7__PORT EQU 2\r
+SCSI_Out_DBx__7__PRT EQU CYREG_PRT2_PRT\r
+SCSI_Out_DBx__7__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
+SCSI_Out_DBx__7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
+SCSI_Out_DBx__7__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
+SCSI_Out_DBx__7__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
+SCSI_Out_DBx__7__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
+SCSI_Out_DBx__7__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
+SCSI_Out_DBx__7__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
+SCSI_Out_DBx__7__PS EQU CYREG_PRT2_PS\r
+SCSI_Out_DBx__7__SHIFT EQU 2\r
+SCSI_Out_DBx__7__SLW EQU CYREG_PRT2_SLW\r
+SCSI_Out_DBx__DB0__AG EQU CYREG_PRT5_AG\r
+SCSI_Out_DBx__DB0__AMUX EQU CYREG_PRT5_AMUX\r
+SCSI_Out_DBx__DB0__BIE EQU CYREG_PRT5_BIE\r
+SCSI_Out_DBx__DB0__BIT_MASK EQU CYREG_PRT5_BIT_MASK\r
+SCSI_Out_DBx__DB0__BYP EQU CYREG_PRT5_BYP\r
+SCSI_Out_DBx__DB0__CTL EQU CYREG_PRT5_CTL\r
+SCSI_Out_DBx__DB0__DM0 EQU CYREG_PRT5_DM0\r
+SCSI_Out_DBx__DB0__DM1 EQU CYREG_PRT5_DM1\r
+SCSI_Out_DBx__DB0__DM2 EQU CYREG_PRT5_DM2\r
+SCSI_Out_DBx__DB0__DR EQU CYREG_PRT5_DR\r
+SCSI_Out_DBx__DB0__INP_DIS EQU CYREG_PRT5_INP_DIS\r
+SCSI_Out_DBx__DB0__INTTYPE EQU CYREG_PICU5_INTTYPE1\r
+SCSI_Out_DBx__DB0__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG\r
+SCSI_Out_DBx__DB0__LCD_EN EQU CYREG_PRT5_LCD_EN\r
+SCSI_Out_DBx__DB0__MASK EQU 0x02\r
+SCSI_Out_DBx__DB0__PC EQU CYREG_PRT5_PC1\r
+SCSI_Out_DBx__DB0__PORT EQU 5\r
+SCSI_Out_DBx__DB0__PRT EQU CYREG_PRT5_PRT\r
+SCSI_Out_DBx__DB0__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL\r
+SCSI_Out_DBx__DB0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN\r
+SCSI_Out_DBx__DB0__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0\r
+SCSI_Out_DBx__DB0__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1\r
+SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0\r
+SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1\r
+SCSI_Out_DBx__DB0__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT\r
+SCSI_Out_DBx__DB0__PS EQU CYREG_PRT5_PS\r
+SCSI_Out_DBx__DB0__SHIFT EQU 1\r
+SCSI_Out_DBx__DB0__SLW EQU CYREG_PRT5_SLW\r
+SCSI_Out_DBx__DB1__AG EQU CYREG_PRT5_AG\r
+SCSI_Out_DBx__DB1__AMUX EQU CYREG_PRT5_AMUX\r
+SCSI_Out_DBx__DB1__BIE EQU CYREG_PRT5_BIE\r
+SCSI_Out_DBx__DB1__BIT_MASK EQU CYREG_PRT5_BIT_MASK\r
+SCSI_Out_DBx__DB1__BYP EQU CYREG_PRT5_BYP\r
+SCSI_Out_DBx__DB1__CTL EQU CYREG_PRT5_CTL\r
+SCSI_Out_DBx__DB1__DM0 EQU CYREG_PRT5_DM0\r
+SCSI_Out_DBx__DB1__DM1 EQU CYREG_PRT5_DM1\r
+SCSI_Out_DBx__DB1__DM2 EQU CYREG_PRT5_DM2\r
+SCSI_Out_DBx__DB1__DR EQU CYREG_PRT5_DR\r
+SCSI_Out_DBx__DB1__INP_DIS EQU CYREG_PRT5_INP_DIS\r
+SCSI_Out_DBx__DB1__INTTYPE EQU CYREG_PICU5_INTTYPE0\r
+SCSI_Out_DBx__DB1__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG\r
+SCSI_Out_DBx__DB1__LCD_EN EQU CYREG_PRT5_LCD_EN\r
+SCSI_Out_DBx__DB1__MASK EQU 0x01\r
+SCSI_Out_DBx__DB1__PC EQU CYREG_PRT5_PC0\r
+SCSI_Out_DBx__DB1__PORT EQU 5\r
+SCSI_Out_DBx__DB1__PRT EQU CYREG_PRT5_PRT\r
+SCSI_Out_DBx__DB1__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL\r
+SCSI_Out_DBx__DB1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN\r
+SCSI_Out_DBx__DB1__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0\r
+SCSI_Out_DBx__DB1__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1\r
+SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0\r
+SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1\r
+SCSI_Out_DBx__DB1__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT\r
+SCSI_Out_DBx__DB1__PS EQU CYREG_PRT5_PS\r
+SCSI_Out_DBx__DB1__SHIFT EQU 0\r
+SCSI_Out_DBx__DB1__SLW EQU CYREG_PRT5_SLW\r
+SCSI_Out_DBx__DB2__AG EQU CYREG_PRT6_AG\r
+SCSI_Out_DBx__DB2__AMUX EQU CYREG_PRT6_AMUX\r
+SCSI_Out_DBx__DB2__BIE EQU CYREG_PRT6_BIE\r
+SCSI_Out_DBx__DB2__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
+SCSI_Out_DBx__DB2__BYP EQU CYREG_PRT6_BYP\r
+SCSI_Out_DBx__DB2__CTL EQU CYREG_PRT6_CTL\r
+SCSI_Out_DBx__DB2__DM0 EQU CYREG_PRT6_DM0\r
+SCSI_Out_DBx__DB2__DM1 EQU CYREG_PRT6_DM1\r
+SCSI_Out_DBx__DB2__DM2 EQU CYREG_PRT6_DM2\r
+SCSI_Out_DBx__DB2__DR EQU CYREG_PRT6_DR\r
+SCSI_Out_DBx__DB2__INP_DIS EQU CYREG_PRT6_INP_DIS\r
+SCSI_Out_DBx__DB2__INTTYPE EQU CYREG_PICU6_INTTYPE5\r
+SCSI_Out_DBx__DB2__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
+SCSI_Out_DBx__DB2__LCD_EN EQU CYREG_PRT6_LCD_EN\r
+SCSI_Out_DBx__DB2__MASK EQU 0x20\r
+SCSI_Out_DBx__DB2__PC EQU CYREG_PRT6_PC5\r
+SCSI_Out_DBx__DB2__PORT EQU 6\r
+SCSI_Out_DBx__DB2__PRT EQU CYREG_PRT6_PRT\r
+SCSI_Out_DBx__DB2__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
+SCSI_Out_DBx__DB2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
+SCSI_Out_DBx__DB2__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
+SCSI_Out_DBx__DB2__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
+SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
+SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
+SCSI_Out_DBx__DB2__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
+SCSI_Out_DBx__DB2__PS EQU CYREG_PRT6_PS\r
+SCSI_Out_DBx__DB2__SHIFT EQU 5\r
+SCSI_Out_DBx__DB2__SLW EQU CYREG_PRT6_SLW\r
+SCSI_Out_DBx__DB3__AG EQU CYREG_PRT6_AG\r
+SCSI_Out_DBx__DB3__AMUX EQU CYREG_PRT6_AMUX\r
+SCSI_Out_DBx__DB3__BIE EQU CYREG_PRT6_BIE\r
+SCSI_Out_DBx__DB3__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
+SCSI_Out_DBx__DB3__BYP EQU CYREG_PRT6_BYP\r
+SCSI_Out_DBx__DB3__CTL EQU CYREG_PRT6_CTL\r
+SCSI_Out_DBx__DB3__DM0 EQU CYREG_PRT6_DM0\r
+SCSI_Out_DBx__DB3__DM1 EQU CYREG_PRT6_DM1\r
+SCSI_Out_DBx__DB3__DM2 EQU CYREG_PRT6_DM2\r
+SCSI_Out_DBx__DB3__DR EQU CYREG_PRT6_DR\r
+SCSI_Out_DBx__DB3__INP_DIS EQU CYREG_PRT6_INP_DIS\r
+SCSI_Out_DBx__DB3__INTTYPE EQU CYREG_PICU6_INTTYPE4\r
+SCSI_Out_DBx__DB3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
+SCSI_Out_DBx__DB3__LCD_EN EQU CYREG_PRT6_LCD_EN\r
+SCSI_Out_DBx__DB3__MASK EQU 0x10\r
+SCSI_Out_DBx__DB3__PC EQU CYREG_PRT6_PC4\r
+SCSI_Out_DBx__DB3__PORT EQU 6\r
+SCSI_Out_DBx__DB3__PRT EQU CYREG_PRT6_PRT\r
+SCSI_Out_DBx__DB3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
+SCSI_Out_DBx__DB3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
+SCSI_Out_DBx__DB3__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
+SCSI_Out_DBx__DB3__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
+SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
+SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
+SCSI_Out_DBx__DB3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
+SCSI_Out_DBx__DB3__PS EQU CYREG_PRT6_PS\r
+SCSI_Out_DBx__DB3__SHIFT EQU 4\r
+SCSI_Out_DBx__DB3__SLW EQU CYREG_PRT6_SLW\r
+SCSI_Out_DBx__DB4__AG EQU CYREG_PRT2_AG\r
+SCSI_Out_DBx__DB4__AMUX EQU CYREG_PRT2_AMUX\r
+SCSI_Out_DBx__DB4__BIE EQU CYREG_PRT2_BIE\r
+SCSI_Out_DBx__DB4__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
+SCSI_Out_DBx__DB4__BYP EQU CYREG_PRT2_BYP\r
+SCSI_Out_DBx__DB4__CTL EQU CYREG_PRT2_CTL\r
+SCSI_Out_DBx__DB4__DM0 EQU CYREG_PRT2_DM0\r
+SCSI_Out_DBx__DB4__DM1 EQU CYREG_PRT2_DM1\r
+SCSI_Out_DBx__DB4__DM2 EQU CYREG_PRT2_DM2\r
+SCSI_Out_DBx__DB4__DR EQU CYREG_PRT2_DR\r
+SCSI_Out_DBx__DB4__INP_DIS EQU CYREG_PRT2_INP_DIS\r
+SCSI_Out_DBx__DB4__INTTYPE EQU CYREG_PICU2_INTTYPE7\r
+SCSI_Out_DBx__DB4__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
+SCSI_Out_DBx__DB4__LCD_EN EQU CYREG_PRT2_LCD_EN\r
+SCSI_Out_DBx__DB4__MASK EQU 0x80\r
+SCSI_Out_DBx__DB4__PC EQU CYREG_PRT2_PC7\r
+SCSI_Out_DBx__DB4__PORT EQU 2\r
+SCSI_Out_DBx__DB4__PRT EQU CYREG_PRT2_PRT\r
+SCSI_Out_DBx__DB4__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
+SCSI_Out_DBx__DB4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
+SCSI_Out_DBx__DB4__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
+SCSI_Out_DBx__DB4__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
+SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
+SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
+SCSI_Out_DBx__DB4__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
+SCSI_Out_DBx__DB4__PS EQU CYREG_PRT2_PS\r
+SCSI_Out_DBx__DB4__SHIFT EQU 7\r
+SCSI_Out_DBx__DB4__SLW EQU CYREG_PRT2_SLW\r
+SCSI_Out_DBx__DB5__AG EQU CYREG_PRT2_AG\r
+SCSI_Out_DBx__DB5__AMUX EQU CYREG_PRT2_AMUX\r
+SCSI_Out_DBx__DB5__BIE EQU CYREG_PRT2_BIE\r
+SCSI_Out_DBx__DB5__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
+SCSI_Out_DBx__DB5__BYP EQU CYREG_PRT2_BYP\r
+SCSI_Out_DBx__DB5__CTL EQU CYREG_PRT2_CTL\r
+SCSI_Out_DBx__DB5__DM0 EQU CYREG_PRT2_DM0\r
+SCSI_Out_DBx__DB5__DM1 EQU CYREG_PRT2_DM1\r
+SCSI_Out_DBx__DB5__DM2 EQU CYREG_PRT2_DM2\r
+SCSI_Out_DBx__DB5__DR EQU CYREG_PRT2_DR\r
+SCSI_Out_DBx__DB5__INP_DIS EQU CYREG_PRT2_INP_DIS\r
+SCSI_Out_DBx__DB5__INTTYPE EQU CYREG_PICU2_INTTYPE6\r
+SCSI_Out_DBx__DB5__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
+SCSI_Out_DBx__DB5__LCD_EN EQU CYREG_PRT2_LCD_EN\r
+SCSI_Out_DBx__DB5__MASK EQU 0x40\r
+SCSI_Out_DBx__DB5__PC EQU CYREG_PRT2_PC6\r
+SCSI_Out_DBx__DB5__PORT EQU 2\r
+SCSI_Out_DBx__DB5__PRT EQU CYREG_PRT2_PRT\r
+SCSI_Out_DBx__DB5__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
+SCSI_Out_DBx__DB5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
+SCSI_Out_DBx__DB5__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
+SCSI_Out_DBx__DB5__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
+SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
+SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
+SCSI_Out_DBx__DB5__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
+SCSI_Out_DBx__DB5__PS EQU CYREG_PRT2_PS\r
+SCSI_Out_DBx__DB5__SHIFT EQU 6\r
+SCSI_Out_DBx__DB5__SLW EQU CYREG_PRT2_SLW\r
+SCSI_Out_DBx__DB6__AG EQU CYREG_PRT2_AG\r
+SCSI_Out_DBx__DB6__AMUX EQU CYREG_PRT2_AMUX\r
+SCSI_Out_DBx__DB6__BIE EQU CYREG_PRT2_BIE\r
+SCSI_Out_DBx__DB6__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
+SCSI_Out_DBx__DB6__BYP EQU CYREG_PRT2_BYP\r
+SCSI_Out_DBx__DB6__CTL EQU CYREG_PRT2_CTL\r
+SCSI_Out_DBx__DB6__DM0 EQU CYREG_PRT2_DM0\r
+SCSI_Out_DBx__DB6__DM1 EQU CYREG_PRT2_DM1\r
+SCSI_Out_DBx__DB6__DM2 EQU CYREG_PRT2_DM2\r
+SCSI_Out_DBx__DB6__DR EQU CYREG_PRT2_DR\r
+SCSI_Out_DBx__DB6__INP_DIS EQU CYREG_PRT2_INP_DIS\r
+SCSI_Out_DBx__DB6__INTTYPE EQU CYREG_PICU2_INTTYPE3\r
+SCSI_Out_DBx__DB6__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
+SCSI_Out_DBx__DB6__LCD_EN EQU CYREG_PRT2_LCD_EN\r
+SCSI_Out_DBx__DB6__MASK EQU 0x08\r
+SCSI_Out_DBx__DB6__PC EQU CYREG_PRT2_PC3\r
+SCSI_Out_DBx__DB6__PORT EQU 2\r
+SCSI_Out_DBx__DB6__PRT EQU CYREG_PRT2_PRT\r
+SCSI_Out_DBx__DB6__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
+SCSI_Out_DBx__DB6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
+SCSI_Out_DBx__DB6__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
+SCSI_Out_DBx__DB6__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
+SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
+SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
+SCSI_Out_DBx__DB6__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
+SCSI_Out_DBx__DB6__PS EQU CYREG_PRT2_PS\r
+SCSI_Out_DBx__DB6__SHIFT EQU 3\r
+SCSI_Out_DBx__DB6__SLW EQU CYREG_PRT2_SLW\r
+SCSI_Out_DBx__DB7__AG EQU CYREG_PRT2_AG\r
+SCSI_Out_DBx__DB7__AMUX EQU CYREG_PRT2_AMUX\r
+SCSI_Out_DBx__DB7__BIE EQU CYREG_PRT2_BIE\r
+SCSI_Out_DBx__DB7__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
+SCSI_Out_DBx__DB7__BYP EQU CYREG_PRT2_BYP\r
+SCSI_Out_DBx__DB7__CTL EQU CYREG_PRT2_CTL\r
+SCSI_Out_DBx__DB7__DM0 EQU CYREG_PRT2_DM0\r
+SCSI_Out_DBx__DB7__DM1 EQU CYREG_PRT2_DM1\r
+SCSI_Out_DBx__DB7__DM2 EQU CYREG_PRT2_DM2\r
+SCSI_Out_DBx__DB7__DR EQU CYREG_PRT2_DR\r
+SCSI_Out_DBx__DB7__INP_DIS EQU CYREG_PRT2_INP_DIS\r
+SCSI_Out_DBx__DB7__INTTYPE EQU CYREG_PICU2_INTTYPE2\r
+SCSI_Out_DBx__DB7__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
+SCSI_Out_DBx__DB7__LCD_EN EQU CYREG_PRT2_LCD_EN\r
+SCSI_Out_DBx__DB7__MASK EQU 0x04\r
+SCSI_Out_DBx__DB7__PC EQU CYREG_PRT2_PC2\r
+SCSI_Out_DBx__DB7__PORT EQU 2\r
+SCSI_Out_DBx__DB7__PRT EQU CYREG_PRT2_PRT\r
+SCSI_Out_DBx__DB7__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
+SCSI_Out_DBx__DB7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
+SCSI_Out_DBx__DB7__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
+SCSI_Out_DBx__DB7__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
+SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
+SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
+SCSI_Out_DBx__DB7__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
+SCSI_Out_DBx__DB7__PS EQU CYREG_PRT2_PS\r
+SCSI_Out_DBx__DB7__SHIFT EQU 2\r
+SCSI_Out_DBx__DB7__SLW EQU CYREG_PRT2_SLW\r
+\r
+; SCSI_Parity_Error\r
+SCSI_Parity_Error_sts_sts_reg__0__MASK EQU 0x01\r
+SCSI_Parity_Error_sts_sts_reg__0__POS EQU 0\r
+SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL\r
+SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB05_06_ST\r
+SCSI_Parity_Error_sts_sts_reg__MASK EQU 0x01\r
+SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB05_MSK\r
+SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL\r
+SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB05_ST\r
+\r
+; SCSI_RST_ISR\r
+SCSI_RST_ISR__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
+SCSI_RST_ISR__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
+SCSI_RST_ISR__INTC_MASK EQU 0x02\r
+SCSI_RST_ISR__INTC_NUMBER EQU 1\r
+SCSI_RST_ISR__INTC_PRIOR_NUM EQU 7\r
+SCSI_RST_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_1\r
+SCSI_RST_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
+SCSI_RST_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
+\r
+; SCSI_RX_DMA\r
+SCSI_RX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0\r
+SCSI_RX_DMA__DRQ_NUMBER EQU 0\r
+SCSI_RX_DMA__NUMBEROF_TDS EQU 0\r
+SCSI_RX_DMA__PRIORITY EQU 2\r
+SCSI_RX_DMA__TERMIN_EN EQU 0\r
+SCSI_RX_DMA__TERMIN_SEL EQU 0\r
+SCSI_RX_DMA__TERMOUT0_EN EQU 1\r
+SCSI_RX_DMA__TERMOUT0_SEL EQU 0\r
+SCSI_RX_DMA__TERMOUT1_EN EQU 0\r
+SCSI_RX_DMA__TERMOUT1_SEL EQU 0\r
+SCSI_RX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
+SCSI_RX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
+SCSI_RX_DMA_COMPLETE__INTC_MASK EQU 0x04\r
+SCSI_RX_DMA_COMPLETE__INTC_NUMBER EQU 2\r
+SCSI_RX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7\r
+SCSI_RX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_2\r
+SCSI_RX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
+SCSI_RX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
+\r
+; SCSI_SEL_ISR\r
+SCSI_SEL_ISR__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
+SCSI_SEL_ISR__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
+SCSI_SEL_ISR__INTC_MASK EQU 0x08\r
+SCSI_SEL_ISR__INTC_NUMBER EQU 3\r
+SCSI_SEL_ISR__INTC_PRIOR_NUM EQU 7\r
+SCSI_SEL_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_3\r
+SCSI_SEL_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
+SCSI_SEL_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
+\r
+; SCSI_TX_DMA\r
+SCSI_TX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0\r
+SCSI_TX_DMA__DRQ_NUMBER EQU 1\r
+SCSI_TX_DMA__NUMBEROF_TDS EQU 0\r
+SCSI_TX_DMA__PRIORITY EQU 2\r
+SCSI_TX_DMA__TERMIN_EN EQU 0\r
+SCSI_TX_DMA__TERMIN_SEL EQU 0\r
+SCSI_TX_DMA__TERMOUT0_EN EQU 1\r
+SCSI_TX_DMA__TERMOUT0_SEL EQU 1\r
+SCSI_TX_DMA__TERMOUT1_EN EQU 0\r
+SCSI_TX_DMA__TERMOUT1_SEL EQU 0\r
+SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
+SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
+SCSI_TX_DMA_COMPLETE__INTC_MASK EQU 0x10\r
+SCSI_TX_DMA_COMPLETE__INTC_NUMBER EQU 4\r
+SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7\r
+SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_4\r
+SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
+SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
+\r
+; SDCard_BSPIM\r
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB05_06_ACTL\r
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB05_06_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB05_06_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB05_06_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB05_06_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB05_06_MSK\r
+SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB05_06_MSK\r
+SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB05_06_MSK\r
+SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB05_06_MSK\r
+SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB05_ACTL\r
+SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB05_CTL\r
+SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB05_ST_CTL\r
+SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB05_CTL\r
+SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB05_ST_CTL\r
+SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL\r
+SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL\r
+SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB05_MSK\r
+SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB05_06_ACTL\r
+SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB05_06_ST\r
+SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB05_MSK\r
+SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL\r
+SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB05_ACTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB05_ST_CTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB05_ST_CTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB05_ST\r
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL\r
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST\r
+SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10\r
+SDCard_BSPIM_RxStsReg__4__POS EQU 4\r
+SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20\r
+SDCard_BSPIM_RxStsReg__5__POS EQU 5\r
+SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40\r
+SDCard_BSPIM_RxStsReg__6__POS EQU 6\r
+SDCard_BSPIM_RxStsReg__MASK EQU 0x70\r
+SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB07_MSK\r
+SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL\r
+SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB07_ST\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB04_05_A0\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB04_05_A1\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B1_UDB04_05_D0\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B1_UDB04_05_D1\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B1_UDB04_05_F0\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B1_UDB04_05_F1\r
+SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B1_UDB04_A0_A1\r
+SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B1_UDB04_A0\r
+SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B1_UDB04_A1\r
+SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B1_UDB04_D0_D1\r
+SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B1_UDB04_D0\r
+SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B1_UDB04_D1\r
+SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL\r
+SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B1_UDB04_F0_F1\r
+SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B1_UDB04_F0\r
+SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B1_UDB04_F1\r
+SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01\r
+SDCard_BSPIM_TxStsReg__0__POS EQU 0\r
+SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02\r
+SDCard_BSPIM_TxStsReg__1__POS EQU 1\r
+SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL\r
+SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB06_07_ST\r
+SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04\r
+SDCard_BSPIM_TxStsReg__2__POS EQU 2\r
+SDCard_BSPIM_TxStsReg__3__MASK EQU 0x08\r
+SDCard_BSPIM_TxStsReg__3__POS EQU 3\r
+SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10\r
+SDCard_BSPIM_TxStsReg__4__POS EQU 4\r
+SDCard_BSPIM_TxStsReg__MASK EQU 0x1F\r
+SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB06_MSK\r
+SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL\r
+SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB06_ST\r
+\r
+; SD_CD\r
+SD_CD__0__INTTYPE EQU CYREG_PICU3_INTTYPE5\r
+SD_CD__0__MASK EQU 0x20\r
+SD_CD__0__PC EQU CYREG_PRT3_PC5\r
+SD_CD__0__PORT EQU 3\r
+SD_CD__0__SHIFT EQU 5\r
+SD_CD__AG EQU CYREG_PRT3_AG\r
+SD_CD__AMUX EQU CYREG_PRT3_AMUX\r
+SD_CD__BIE EQU CYREG_PRT3_BIE\r
+SD_CD__BIT_MASK EQU CYREG_PRT3_BIT_MASK\r
+SD_CD__BYP EQU CYREG_PRT3_BYP\r
+SD_CD__CTL EQU CYREG_PRT3_CTL\r
+SD_CD__DM0 EQU CYREG_PRT3_DM0\r
+SD_CD__DM1 EQU CYREG_PRT3_DM1\r
+SD_CD__DM2 EQU CYREG_PRT3_DM2\r
+SD_CD__DR EQU CYREG_PRT3_DR\r
+SD_CD__INP_DIS EQU CYREG_PRT3_INP_DIS\r
+SD_CD__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE\r
+SD_CD__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG\r
+SD_CD__LCD_EN EQU CYREG_PRT3_LCD_EN\r
+SD_CD__MASK EQU 0x20\r
+SD_CD__PORT EQU 3\r
+SD_CD__PRT EQU CYREG_PRT3_PRT\r
+SD_CD__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL\r
+SD_CD__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN\r
+SD_CD__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0\r
+SD_CD__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1\r
+SD_CD__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0\r
+SD_CD__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1\r
+SD_CD__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT\r
+SD_CD__PS EQU CYREG_PRT3_PS\r
+SD_CD__SHIFT EQU 5\r
+SD_CD__SLW EQU CYREG_PRT3_SLW\r
+\r
+; SD_CS\r
+SD_CS__0__INTTYPE EQU CYREG_PICU3_INTTYPE4\r
+SD_CS__0__MASK EQU 0x10\r
+SD_CS__0__PC EQU CYREG_PRT3_PC4\r
+SD_CS__0__PORT EQU 3\r
+SD_CS__0__SHIFT EQU 4\r
+SD_CS__AG EQU CYREG_PRT3_AG\r
+SD_CS__AMUX EQU CYREG_PRT3_AMUX\r
+SD_CS__BIE EQU CYREG_PRT3_BIE\r
+SD_CS__BIT_MASK EQU CYREG_PRT3_BIT_MASK\r
+SD_CS__BYP EQU CYREG_PRT3_BYP\r
+SD_CS__CTL EQU CYREG_PRT3_CTL\r
+SD_CS__DM0 EQU CYREG_PRT3_DM0\r
+SD_CS__DM1 EQU CYREG_PRT3_DM1\r
+SD_CS__DM2 EQU CYREG_PRT3_DM2\r
+SD_CS__DR EQU CYREG_PRT3_DR\r
+SD_CS__INP_DIS EQU CYREG_PRT3_INP_DIS\r
+SD_CS__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE\r
+SD_CS__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG\r
+SD_CS__LCD_EN EQU CYREG_PRT3_LCD_EN\r
+SD_CS__MASK EQU 0x10\r
+SD_CS__PORT EQU 3\r
+SD_CS__PRT EQU CYREG_PRT3_PRT\r
+SD_CS__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL\r
+SD_CS__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN\r
+SD_CS__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0\r
+SD_CS__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1\r
+SD_CS__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0\r
+SD_CS__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1\r
+SD_CS__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT\r
+SD_CS__PS EQU CYREG_PRT3_PS\r
+SD_CS__SHIFT EQU 4\r
+SD_CS__SLW EQU CYREG_PRT3_SLW\r
+\r
+; SD_Data_Clk\r
+SD_Data_Clk__CFG0 EQU CYREG_CLKDIST_DCFG0_CFG0\r
+SD_Data_Clk__CFG1 EQU CYREG_CLKDIST_DCFG0_CFG1\r
+SD_Data_Clk__CFG2 EQU CYREG_CLKDIST_DCFG0_CFG2\r
+SD_Data_Clk__CFG2_SRC_SEL_MASK EQU 0x07\r
+SD_Data_Clk__INDEX EQU 0x00\r
+SD_Data_Clk__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2\r
+SD_Data_Clk__PM_ACT_MSK EQU 0x01\r
+SD_Data_Clk__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2\r
+SD_Data_Clk__PM_STBY_MSK EQU 0x01\r
+\r
+; SD_MISO\r
+SD_MISO__0__INTTYPE EQU CYREG_PICU3_INTTYPE1\r
+SD_MISO__0__MASK EQU 0x02\r
+SD_MISO__0__PC EQU CYREG_PRT3_PC1\r
+SD_MISO__0__PORT EQU 3\r
+SD_MISO__0__SHIFT EQU 1\r
+SD_MISO__AG EQU CYREG_PRT3_AG\r
+SD_MISO__AMUX EQU CYREG_PRT3_AMUX\r
+SD_MISO__BIE EQU CYREG_PRT3_BIE\r
+SD_MISO__BIT_MASK EQU CYREG_PRT3_BIT_MASK\r
+SD_MISO__BYP EQU CYREG_PRT3_BYP\r
+SD_MISO__CTL EQU CYREG_PRT3_CTL\r
+SD_MISO__DM0 EQU CYREG_PRT3_DM0\r
+SD_MISO__DM1 EQU CYREG_PRT3_DM1\r
+SD_MISO__DM2 EQU CYREG_PRT3_DM2\r
+SD_MISO__DR EQU CYREG_PRT3_DR\r
+SD_MISO__INP_DIS EQU CYREG_PRT3_INP_DIS\r
+SD_MISO__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE\r
+SD_MISO__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG\r
+SD_MISO__LCD_EN EQU CYREG_PRT3_LCD_EN\r
+SD_MISO__MASK EQU 0x02\r
+SD_MISO__PORT EQU 3\r
+SD_MISO__PRT EQU CYREG_PRT3_PRT\r
+SD_MISO__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL\r
+SD_MISO__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN\r
+SD_MISO__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0\r
+SD_MISO__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1\r
+SD_MISO__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0\r
+SD_MISO__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1\r
+SD_MISO__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT\r
+SD_MISO__PS EQU CYREG_PRT3_PS\r
+SD_MISO__SHIFT EQU 1\r
+SD_MISO__SLW EQU CYREG_PRT3_SLW\r
+\r
+; SD_MOSI\r
+SD_MOSI__0__INTTYPE EQU CYREG_PICU3_INTTYPE3\r
+SD_MOSI__0__MASK EQU 0x08\r
+SD_MOSI__0__PC EQU CYREG_PRT3_PC3\r
+SD_MOSI__0__PORT EQU 3\r
+SD_MOSI__0__SHIFT EQU 3\r
+SD_MOSI__AG EQU CYREG_PRT3_AG\r
+SD_MOSI__AMUX EQU CYREG_PRT3_AMUX\r
+SD_MOSI__BIE EQU CYREG_PRT3_BIE\r
+SD_MOSI__BIT_MASK EQU CYREG_PRT3_BIT_MASK\r
+SD_MOSI__BYP EQU CYREG_PRT3_BYP\r
+SD_MOSI__CTL EQU CYREG_PRT3_CTL\r
+SD_MOSI__DM0 EQU CYREG_PRT3_DM0\r
+SD_MOSI__DM1 EQU CYREG_PRT3_DM1\r
+SD_MOSI__DM2 EQU CYREG_PRT3_DM2\r
+SD_MOSI__DR EQU CYREG_PRT3_DR\r
+SD_MOSI__INP_DIS EQU CYREG_PRT3_INP_DIS\r
+SD_MOSI__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE\r
+SD_MOSI__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG\r
+SD_MOSI__LCD_EN EQU CYREG_PRT3_LCD_EN\r
+SD_MOSI__MASK EQU 0x08\r
+SD_MOSI__PORT EQU 3\r
+SD_MOSI__PRT EQU CYREG_PRT3_PRT\r
+SD_MOSI__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL\r
+SD_MOSI__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN\r
+SD_MOSI__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0\r
+SD_MOSI__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1\r
+SD_MOSI__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0\r
+SD_MOSI__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1\r
+SD_MOSI__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT\r
+SD_MOSI__PS EQU CYREG_PRT3_PS\r
+SD_MOSI__SHIFT EQU 3\r
+SD_MOSI__SLW EQU CYREG_PRT3_SLW\r
+\r
+; SD_RX_DMA\r
+SD_RX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0\r
+SD_RX_DMA__DRQ_NUMBER EQU 2\r
+SD_RX_DMA__NUMBEROF_TDS EQU 0\r
+SD_RX_DMA__PRIORITY EQU 0\r
+SD_RX_DMA__TERMIN_EN EQU 0\r
+SD_RX_DMA__TERMIN_SEL EQU 0\r
+SD_RX_DMA__TERMOUT0_EN EQU 1\r
+SD_RX_DMA__TERMOUT0_SEL EQU 2\r
+SD_RX_DMA__TERMOUT1_EN EQU 0\r
+SD_RX_DMA__TERMOUT1_SEL EQU 0\r
+SD_RX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
+SD_RX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
+SD_RX_DMA_COMPLETE__INTC_MASK EQU 0x20\r
+SD_RX_DMA_COMPLETE__INTC_NUMBER EQU 5\r
+SD_RX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7\r
+SD_RX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_5\r
+SD_RX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
+SD_RX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
+\r
+; SD_SCK\r
+SD_SCK__0__INTTYPE EQU CYREG_PICU3_INTTYPE2\r
+SD_SCK__0__MASK EQU 0x04\r
+SD_SCK__0__PC EQU CYREG_PRT3_PC2\r
+SD_SCK__0__PORT EQU 3\r
+SD_SCK__0__SHIFT EQU 2\r
+SD_SCK__AG EQU CYREG_PRT3_AG\r
+SD_SCK__AMUX EQU CYREG_PRT3_AMUX\r
+SD_SCK__BIE EQU CYREG_PRT3_BIE\r
+SD_SCK__BIT_MASK EQU CYREG_PRT3_BIT_MASK\r
+SD_SCK__BYP EQU CYREG_PRT3_BYP\r
+SD_SCK__CTL EQU CYREG_PRT3_CTL\r
+SD_SCK__DM0 EQU CYREG_PRT3_DM0\r
+SD_SCK__DM1 EQU CYREG_PRT3_DM1\r
+SD_SCK__DM2 EQU CYREG_PRT3_DM2\r
+SD_SCK__DR EQU CYREG_PRT3_DR\r
+SD_SCK__INP_DIS EQU CYREG_PRT3_INP_DIS\r
+SD_SCK__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE\r
+SD_SCK__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG\r
+SD_SCK__LCD_EN EQU CYREG_PRT3_LCD_EN\r
+SD_SCK__MASK EQU 0x04\r
+SD_SCK__PORT EQU 3\r
+SD_SCK__PRT EQU CYREG_PRT3_PRT\r
+SD_SCK__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL\r
+SD_SCK__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN\r
+SD_SCK__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0\r
+SD_SCK__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1\r
+SD_SCK__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0\r
+SD_SCK__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1\r
+SD_SCK__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT\r
+SD_SCK__PS EQU CYREG_PRT3_PS\r
+SD_SCK__SHIFT EQU 2\r
+SD_SCK__SLW EQU CYREG_PRT3_SLW\r
+\r
+; SD_TX_DMA\r
+SD_TX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0\r
+SD_TX_DMA__DRQ_NUMBER EQU 3\r
+SD_TX_DMA__NUMBEROF_TDS EQU 0\r
+SD_TX_DMA__PRIORITY EQU 1\r
+SD_TX_DMA__TERMIN_EN EQU 0\r
+SD_TX_DMA__TERMIN_SEL EQU 0\r
+SD_TX_DMA__TERMOUT0_EN EQU 1\r
+SD_TX_DMA__TERMOUT0_SEL EQU 3\r
+SD_TX_DMA__TERMOUT1_EN EQU 0\r
+SD_TX_DMA__TERMOUT1_SEL EQU 0\r
+SD_TX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
+SD_TX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
+SD_TX_DMA_COMPLETE__INTC_MASK EQU 0x40\r
+SD_TX_DMA_COMPLETE__INTC_NUMBER EQU 6\r
+SD_TX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7\r
+SD_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_6\r
+SD_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
+SD_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
+\r
+; USBFS\r
+USBFS_arb_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
+USBFS_arb_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
+USBFS_arb_int__INTC_MASK EQU 0x400000\r
+USBFS_arb_int__INTC_NUMBER EQU 22\r
+USBFS_arb_int__INTC_PRIOR_NUM EQU 6\r
+USBFS_arb_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_22\r
+USBFS_arb_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
+USBFS_arb_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
+USBFS_bus_reset__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
+USBFS_bus_reset__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
+USBFS_bus_reset__INTC_MASK EQU 0x800000\r
+USBFS_bus_reset__INTC_NUMBER EQU 23\r
+USBFS_bus_reset__INTC_PRIOR_NUM EQU 7\r
+USBFS_bus_reset__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_23\r
+USBFS_bus_reset__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
+USBFS_bus_reset__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
+USBFS_Dm__0__INTTYPE EQU CYREG_PICU15_INTTYPE7\r
+USBFS_Dm__0__MASK EQU 0x80\r
+USBFS_Dm__0__PC EQU CYREG_IO_PC_PRT15_7_6_PC1\r
+USBFS_Dm__0__PORT EQU 15\r
+USBFS_Dm__0__SHIFT EQU 7\r
+USBFS_Dm__AG EQU CYREG_PRT15_AG\r
+USBFS_Dm__AMUX EQU CYREG_PRT15_AMUX\r
+USBFS_Dm__BIE EQU CYREG_PRT15_BIE\r
+USBFS_Dm__BIT_MASK EQU CYREG_PRT15_BIT_MASK\r
+USBFS_Dm__BYP EQU CYREG_PRT15_BYP\r
+USBFS_Dm__CTL EQU CYREG_PRT15_CTL\r
+USBFS_Dm__DM0 EQU CYREG_PRT15_DM0\r
+USBFS_Dm__DM1 EQU CYREG_PRT15_DM1\r
+USBFS_Dm__DM2 EQU CYREG_PRT15_DM2\r
+USBFS_Dm__DR EQU CYREG_PRT15_DR\r
+USBFS_Dm__INP_DIS EQU CYREG_PRT15_INP_DIS\r
+USBFS_Dm__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU15_BASE\r
+USBFS_Dm__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG\r
+USBFS_Dm__LCD_EN EQU CYREG_PRT15_LCD_EN\r
+USBFS_Dm__MASK EQU 0x80\r
+USBFS_Dm__PORT EQU 15\r
+USBFS_Dm__PRT EQU CYREG_PRT15_PRT\r
+USBFS_Dm__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL\r
+USBFS_Dm__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN\r
+USBFS_Dm__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0\r
+USBFS_Dm__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1\r
+USBFS_Dm__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0\r
+USBFS_Dm__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1\r
+USBFS_Dm__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT\r
+USBFS_Dm__PS EQU CYREG_PRT15_PS\r
+USBFS_Dm__SHIFT EQU 7\r
+USBFS_Dm__SLW EQU CYREG_PRT15_SLW\r
+USBFS_Dp__0__INTTYPE EQU CYREG_PICU15_INTTYPE6\r
+USBFS_Dp__0__MASK EQU 0x40\r
+USBFS_Dp__0__PC EQU CYREG_IO_PC_PRT15_7_6_PC0\r
+USBFS_Dp__0__PORT EQU 15\r
+USBFS_Dp__0__SHIFT EQU 6\r
+USBFS_Dp__AG EQU CYREG_PRT15_AG\r
+USBFS_Dp__AMUX EQU CYREG_PRT15_AMUX\r
+USBFS_Dp__BIE EQU CYREG_PRT15_BIE\r
+USBFS_Dp__BIT_MASK EQU CYREG_PRT15_BIT_MASK\r
+USBFS_Dp__BYP EQU CYREG_PRT15_BYP\r
+USBFS_Dp__CTL EQU CYREG_PRT15_CTL\r
+USBFS_Dp__DM0 EQU CYREG_PRT15_DM0\r
+USBFS_Dp__DM1 EQU CYREG_PRT15_DM1\r
+USBFS_Dp__DM2 EQU CYREG_PRT15_DM2\r
+USBFS_Dp__DR EQU CYREG_PRT15_DR\r
+USBFS_Dp__INP_DIS EQU CYREG_PRT15_INP_DIS\r
+USBFS_Dp__INTSTAT EQU CYREG_PICU15_INTSTAT\r
+USBFS_Dp__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU15_BASE\r
+USBFS_Dp__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG\r
+USBFS_Dp__LCD_EN EQU CYREG_PRT15_LCD_EN\r
+USBFS_Dp__MASK EQU 0x40\r
+USBFS_Dp__PORT EQU 15\r
+USBFS_Dp__PRT EQU CYREG_PRT15_PRT\r
+USBFS_Dp__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL\r
+USBFS_Dp__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN\r
+USBFS_Dp__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0\r
+USBFS_Dp__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1\r
+USBFS_Dp__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0\r
+USBFS_Dp__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1\r
+USBFS_Dp__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT\r
+USBFS_Dp__PS EQU CYREG_PRT15_PS\r
+USBFS_Dp__SHIFT EQU 6\r
+USBFS_Dp__SLW EQU CYREG_PRT15_SLW\r
+USBFS_Dp__SNAP EQU CYREG_PICU_15_SNAP_15\r
+USBFS_dp_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
+USBFS_dp_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
+USBFS_dp_int__INTC_MASK EQU 0x1000\r
+USBFS_dp_int__INTC_NUMBER EQU 12\r
+USBFS_dp_int__INTC_PRIOR_NUM EQU 7\r
+USBFS_dp_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_12\r
+USBFS_dp_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
+USBFS_dp_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
+USBFS_ep_0__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
+USBFS_ep_0__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
+USBFS_ep_0__INTC_MASK EQU 0x1000000\r
+USBFS_ep_0__INTC_NUMBER EQU 24\r
+USBFS_ep_0__INTC_PRIOR_NUM EQU 7\r
+USBFS_ep_0__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_24\r
+USBFS_ep_0__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
+USBFS_ep_0__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
+USBFS_ep_1__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
+USBFS_ep_1__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
+USBFS_ep_1__INTC_MASK EQU 0x80\r
+USBFS_ep_1__INTC_NUMBER EQU 7\r
+USBFS_ep_1__INTC_PRIOR_NUM EQU 7\r
+USBFS_ep_1__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_7\r
+USBFS_ep_1__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
+USBFS_ep_1__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
+USBFS_ep_2__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
+USBFS_ep_2__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
+USBFS_ep_2__INTC_MASK EQU 0x100\r
+USBFS_ep_2__INTC_NUMBER EQU 8\r
+USBFS_ep_2__INTC_PRIOR_NUM EQU 7\r
+USBFS_ep_2__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_8\r
+USBFS_ep_2__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
+USBFS_ep_2__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
+USBFS_ep_3__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
+USBFS_ep_3__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
+USBFS_ep_3__INTC_MASK EQU 0x200\r
+USBFS_ep_3__INTC_NUMBER EQU 9\r
+USBFS_ep_3__INTC_PRIOR_NUM EQU 7\r
+USBFS_ep_3__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_9\r
+USBFS_ep_3__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
+USBFS_ep_3__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
+USBFS_ep_4__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
+USBFS_ep_4__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
+USBFS_ep_4__INTC_MASK EQU 0x400\r
+USBFS_ep_4__INTC_NUMBER EQU 10\r
+USBFS_ep_4__INTC_PRIOR_NUM EQU 7\r
+USBFS_ep_4__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_10\r
+USBFS_ep_4__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
+USBFS_ep_4__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
+USBFS_sof_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
+USBFS_sof_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
+USBFS_sof_int__INTC_MASK EQU 0x200000\r
+USBFS_sof_int__INTC_NUMBER EQU 21\r
+USBFS_sof_int__INTC_PRIOR_NUM EQU 7\r
+USBFS_sof_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_21\r
+USBFS_sof_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
+USBFS_sof_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
+USBFS_USB__ARB_CFG EQU CYREG_USB_ARB_CFG\r
+USBFS_USB__ARB_EP1_CFG EQU CYREG_USB_ARB_EP1_CFG\r
+USBFS_USB__ARB_EP1_INT_EN EQU CYREG_USB_ARB_EP1_INT_EN\r
+USBFS_USB__ARB_EP1_SR EQU CYREG_USB_ARB_EP1_SR\r
+USBFS_USB__ARB_EP2_CFG EQU CYREG_USB_ARB_EP2_CFG\r
+USBFS_USB__ARB_EP2_INT_EN EQU CYREG_USB_ARB_EP2_INT_EN\r
+USBFS_USB__ARB_EP2_SR EQU CYREG_USB_ARB_EP2_SR\r
+USBFS_USB__ARB_EP3_CFG EQU CYREG_USB_ARB_EP3_CFG\r
+USBFS_USB__ARB_EP3_INT_EN EQU CYREG_USB_ARB_EP3_INT_EN\r
+USBFS_USB__ARB_EP3_SR EQU CYREG_USB_ARB_EP3_SR\r
+USBFS_USB__ARB_EP4_CFG EQU CYREG_USB_ARB_EP4_CFG\r
+USBFS_USB__ARB_EP4_INT_EN EQU CYREG_USB_ARB_EP4_INT_EN\r
+USBFS_USB__ARB_EP4_SR EQU CYREG_USB_ARB_EP4_SR\r
+USBFS_USB__ARB_EP5_CFG EQU CYREG_USB_ARB_EP5_CFG\r
+USBFS_USB__ARB_EP5_INT_EN EQU CYREG_USB_ARB_EP5_INT_EN\r
+USBFS_USB__ARB_EP5_SR EQU CYREG_USB_ARB_EP5_SR\r
+USBFS_USB__ARB_EP6_CFG EQU CYREG_USB_ARB_EP6_CFG\r
+USBFS_USB__ARB_EP6_INT_EN EQU CYREG_USB_ARB_EP6_INT_EN\r
+USBFS_USB__ARB_EP6_SR EQU CYREG_USB_ARB_EP6_SR\r
+USBFS_USB__ARB_EP7_CFG EQU CYREG_USB_ARB_EP7_CFG\r
+USBFS_USB__ARB_EP7_INT_EN EQU CYREG_USB_ARB_EP7_INT_EN\r
+USBFS_USB__ARB_EP7_SR EQU CYREG_USB_ARB_EP7_SR\r
+USBFS_USB__ARB_EP8_CFG EQU CYREG_USB_ARB_EP8_CFG\r
+USBFS_USB__ARB_EP8_INT_EN EQU CYREG_USB_ARB_EP8_INT_EN\r
+USBFS_USB__ARB_EP8_SR EQU CYREG_USB_ARB_EP8_SR\r
+USBFS_USB__ARB_INT_EN EQU CYREG_USB_ARB_INT_EN\r
+USBFS_USB__ARB_INT_SR EQU CYREG_USB_ARB_INT_SR\r
+USBFS_USB__ARB_RW1_DR EQU CYREG_USB_ARB_RW1_DR\r
+USBFS_USB__ARB_RW1_RA EQU CYREG_USB_ARB_RW1_RA\r
+USBFS_USB__ARB_RW1_RA_MSB EQU CYREG_USB_ARB_RW1_RA_MSB\r
+USBFS_USB__ARB_RW1_WA EQU CYREG_USB_ARB_RW1_WA\r
+USBFS_USB__ARB_RW1_WA_MSB EQU CYREG_USB_ARB_RW1_WA_MSB\r
+USBFS_USB__ARB_RW2_DR EQU CYREG_USB_ARB_RW2_DR\r
+USBFS_USB__ARB_RW2_RA EQU CYREG_USB_ARB_RW2_RA\r
+USBFS_USB__ARB_RW2_RA_MSB EQU CYREG_USB_ARB_RW2_RA_MSB\r
+USBFS_USB__ARB_RW2_WA EQU CYREG_USB_ARB_RW2_WA\r
+USBFS_USB__ARB_RW2_WA_MSB EQU CYREG_USB_ARB_RW2_WA_MSB\r
+USBFS_USB__ARB_RW3_DR EQU CYREG_USB_ARB_RW3_DR\r
+USBFS_USB__ARB_RW3_RA EQU CYREG_USB_ARB_RW3_RA\r
+USBFS_USB__ARB_RW3_RA_MSB EQU CYREG_USB_ARB_RW3_RA_MSB\r
+USBFS_USB__ARB_RW3_WA EQU CYREG_USB_ARB_RW3_WA\r
+USBFS_USB__ARB_RW3_WA_MSB EQU CYREG_USB_ARB_RW3_WA_MSB\r
+USBFS_USB__ARB_RW4_DR EQU CYREG_USB_ARB_RW4_DR\r
+USBFS_USB__ARB_RW4_RA EQU CYREG_USB_ARB_RW4_RA\r
+USBFS_USB__ARB_RW4_RA_MSB EQU CYREG_USB_ARB_RW4_RA_MSB\r
+USBFS_USB__ARB_RW4_WA EQU CYREG_USB_ARB_RW4_WA\r
+USBFS_USB__ARB_RW4_WA_MSB EQU CYREG_USB_ARB_RW4_WA_MSB\r
+USBFS_USB__ARB_RW5_DR EQU CYREG_USB_ARB_RW5_DR\r
+USBFS_USB__ARB_RW5_RA EQU CYREG_USB_ARB_RW5_RA\r
+USBFS_USB__ARB_RW5_RA_MSB EQU CYREG_USB_ARB_RW5_RA_MSB\r
+USBFS_USB__ARB_RW5_WA EQU CYREG_USB_ARB_RW5_WA\r
+USBFS_USB__ARB_RW5_WA_MSB EQU CYREG_USB_ARB_RW5_WA_MSB\r
+USBFS_USB__ARB_RW6_DR EQU CYREG_USB_ARB_RW6_DR\r
+USBFS_USB__ARB_RW6_RA EQU CYREG_USB_ARB_RW6_RA\r
+USBFS_USB__ARB_RW6_RA_MSB EQU CYREG_USB_ARB_RW6_RA_MSB\r
+USBFS_USB__ARB_RW6_WA EQU CYREG_USB_ARB_RW6_WA\r
+USBFS_USB__ARB_RW6_WA_MSB EQU CYREG_USB_ARB_RW6_WA_MSB\r
+USBFS_USB__ARB_RW7_DR EQU CYREG_USB_ARB_RW7_DR\r
+USBFS_USB__ARB_RW7_RA EQU CYREG_USB_ARB_RW7_RA\r
+USBFS_USB__ARB_RW7_RA_MSB EQU CYREG_USB_ARB_RW7_RA_MSB\r
+USBFS_USB__ARB_RW7_WA EQU CYREG_USB_ARB_RW7_WA\r
+USBFS_USB__ARB_RW7_WA_MSB EQU CYREG_USB_ARB_RW7_WA_MSB\r
+USBFS_USB__ARB_RW8_DR EQU CYREG_USB_ARB_RW8_DR\r
+USBFS_USB__ARB_RW8_RA EQU CYREG_USB_ARB_RW8_RA\r
+USBFS_USB__ARB_RW8_RA_MSB EQU CYREG_USB_ARB_RW8_RA_MSB\r
+USBFS_USB__ARB_RW8_WA EQU CYREG_USB_ARB_RW8_WA\r
+USBFS_USB__ARB_RW8_WA_MSB EQU CYREG_USB_ARB_RW8_WA_MSB\r
+USBFS_USB__BUF_SIZE EQU CYREG_USB_BUF_SIZE\r
+USBFS_USB__BUS_RST_CNT EQU CYREG_USB_BUS_RST_CNT\r
+USBFS_USB__CR0 EQU CYREG_USB_CR0\r
+USBFS_USB__CR1 EQU CYREG_USB_CR1\r
+USBFS_USB__CWA EQU CYREG_USB_CWA\r
+USBFS_USB__CWA_MSB EQU CYREG_USB_CWA_MSB\r
+USBFS_USB__DMA_THRES EQU CYREG_USB_DMA_THRES\r
+USBFS_USB__DMA_THRES_MSB EQU CYREG_USB_DMA_THRES_MSB\r
+USBFS_USB__DYN_RECONFIG EQU CYREG_USB_DYN_RECONFIG\r
+USBFS_USB__EP_ACTIVE EQU CYREG_USB_EP_ACTIVE\r
+USBFS_USB__EP_TYPE EQU CYREG_USB_EP_TYPE\r
+USBFS_USB__EP0_CNT EQU CYREG_USB_EP0_CNT\r
+USBFS_USB__EP0_CR EQU CYREG_USB_EP0_CR\r
+USBFS_USB__EP0_DR0 EQU CYREG_USB_EP0_DR0\r
+USBFS_USB__EP0_DR1 EQU CYREG_USB_EP0_DR1\r
+USBFS_USB__EP0_DR2 EQU CYREG_USB_EP0_DR2\r
+USBFS_USB__EP0_DR3 EQU CYREG_USB_EP0_DR3\r
+USBFS_USB__EP0_DR4 EQU CYREG_USB_EP0_DR4\r
+USBFS_USB__EP0_DR5 EQU CYREG_USB_EP0_DR5\r
+USBFS_USB__EP0_DR6 EQU CYREG_USB_EP0_DR6\r
+USBFS_USB__EP0_DR7 EQU CYREG_USB_EP0_DR7\r
+USBFS_USB__MEM_DATA EQU CYREG_USB_MEM_DATA_MBASE\r
+USBFS_USB__PM_ACT_CFG EQU CYREG_PM_ACT_CFG5\r
+USBFS_USB__PM_ACT_MSK EQU 0x01\r
+USBFS_USB__PM_STBY_CFG EQU CYREG_PM_STBY_CFG5\r
+USBFS_USB__PM_STBY_MSK EQU 0x01\r
+USBFS_USB__SIE_EP_INT_EN EQU CYREG_USB_SIE_EP_INT_EN\r
+USBFS_USB__SIE_EP_INT_SR EQU CYREG_USB_SIE_EP_INT_SR\r
+USBFS_USB__SIE_EP1_CNT0 EQU CYREG_USB_SIE_EP1_CNT0\r
+USBFS_USB__SIE_EP1_CNT1 EQU CYREG_USB_SIE_EP1_CNT1\r
+USBFS_USB__SIE_EP1_CR0 EQU CYREG_USB_SIE_EP1_CR0\r
+USBFS_USB__SIE_EP2_CNT0 EQU CYREG_USB_SIE_EP2_CNT0\r
+USBFS_USB__SIE_EP2_CNT1 EQU CYREG_USB_SIE_EP2_CNT1\r
+USBFS_USB__SIE_EP2_CR0 EQU CYREG_USB_SIE_EP2_CR0\r
+USBFS_USB__SIE_EP3_CNT0 EQU CYREG_USB_SIE_EP3_CNT0\r
+USBFS_USB__SIE_EP3_CNT1 EQU CYREG_USB_SIE_EP3_CNT1\r
+USBFS_USB__SIE_EP3_CR0 EQU CYREG_USB_SIE_EP3_CR0\r
+USBFS_USB__SIE_EP4_CNT0 EQU CYREG_USB_SIE_EP4_CNT0\r
+USBFS_USB__SIE_EP4_CNT1 EQU CYREG_USB_SIE_EP4_CNT1\r
+USBFS_USB__SIE_EP4_CR0 EQU CYREG_USB_SIE_EP4_CR0\r
+USBFS_USB__SIE_EP5_CNT0 EQU CYREG_USB_SIE_EP5_CNT0\r
+USBFS_USB__SIE_EP5_CNT1 EQU CYREG_USB_SIE_EP5_CNT1\r
+USBFS_USB__SIE_EP5_CR0 EQU CYREG_USB_SIE_EP5_CR0\r
+USBFS_USB__SIE_EP6_CNT0 EQU CYREG_USB_SIE_EP6_CNT0\r
+USBFS_USB__SIE_EP6_CNT1 EQU CYREG_USB_SIE_EP6_CNT1\r
+USBFS_USB__SIE_EP6_CR0 EQU CYREG_USB_SIE_EP6_CR0\r
+USBFS_USB__SIE_EP7_CNT0 EQU CYREG_USB_SIE_EP7_CNT0\r
+USBFS_USB__SIE_EP7_CNT1 EQU CYREG_USB_SIE_EP7_CNT1\r
+USBFS_USB__SIE_EP7_CR0 EQU CYREG_USB_SIE_EP7_CR0\r
+USBFS_USB__SIE_EP8_CNT0 EQU CYREG_USB_SIE_EP8_CNT0\r
+USBFS_USB__SIE_EP8_CNT1 EQU CYREG_USB_SIE_EP8_CNT1\r
+USBFS_USB__SIE_EP8_CR0 EQU CYREG_USB_SIE_EP8_CR0\r
+USBFS_USB__SOF0 EQU CYREG_USB_SOF0\r
+USBFS_USB__SOF1 EQU CYREG_USB_SOF1\r
+USBFS_USB__USB_CLK_EN EQU CYREG_USB_USB_CLK_EN\r
+USBFS_USB__USBIO_CR0 EQU CYREG_USB_USBIO_CR0\r
+USBFS_USB__USBIO_CR1 EQU CYREG_USB_USBIO_CR1\r
+\r
 ; scsiTarget\r
 scsiTarget_datapath__16BIT_A0_REG EQU CYREG_B0_UDB00_01_A0\r
 scsiTarget_datapath__16BIT_A1_REG EQU CYREG_B0_UDB00_01_A1\r
@@ -2798,89 +2954,6 @@ scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB02_MSK
 scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL\r
 scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB02_ST\r
 \r
-; Debug_Timer_Interrupt\r
-Debug_Timer_Interrupt__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
-Debug_Timer_Interrupt__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
-Debug_Timer_Interrupt__INTC_MASK EQU 0x02\r
-Debug_Timer_Interrupt__INTC_NUMBER EQU 1\r
-Debug_Timer_Interrupt__INTC_PRIOR_NUM EQU 7\r
-Debug_Timer_Interrupt__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_1\r
-Debug_Timer_Interrupt__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
-Debug_Timer_Interrupt__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
-\r
-; Debug_Timer_TimerHW\r
-Debug_Timer_TimerHW__CAP0 EQU CYREG_TMR0_CAP0\r
-Debug_Timer_TimerHW__CAP1 EQU CYREG_TMR0_CAP1\r
-Debug_Timer_TimerHW__CFG0 EQU CYREG_TMR0_CFG0\r
-Debug_Timer_TimerHW__CFG1 EQU CYREG_TMR0_CFG1\r
-Debug_Timer_TimerHW__CFG2 EQU CYREG_TMR0_CFG2\r
-Debug_Timer_TimerHW__CNT_CMP0 EQU CYREG_TMR0_CNT_CMP0\r
-Debug_Timer_TimerHW__CNT_CMP1 EQU CYREG_TMR0_CNT_CMP1\r
-Debug_Timer_TimerHW__PER0 EQU CYREG_TMR0_PER0\r
-Debug_Timer_TimerHW__PER1 EQU CYREG_TMR0_PER1\r
-Debug_Timer_TimerHW__PM_ACT_CFG EQU CYREG_PM_ACT_CFG3\r
-Debug_Timer_TimerHW__PM_ACT_MSK EQU 0x01\r
-Debug_Timer_TimerHW__PM_STBY_CFG EQU CYREG_PM_STBY_CFG3\r
-Debug_Timer_TimerHW__PM_STBY_MSK EQU 0x01\r
-Debug_Timer_TimerHW__RT0 EQU CYREG_TMR0_RT0\r
-Debug_Timer_TimerHW__RT1 EQU CYREG_TMR0_RT1\r
-Debug_Timer_TimerHW__SR0 EQU CYREG_TMR0_SR0\r
-\r
-; SCSI_RX_DMA\r
-SCSI_RX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0\r
-SCSI_RX_DMA__DRQ_NUMBER EQU 0\r
-SCSI_RX_DMA__NUMBEROF_TDS EQU 0\r
-SCSI_RX_DMA__PRIORITY EQU 2\r
-SCSI_RX_DMA__TERMIN_EN EQU 0\r
-SCSI_RX_DMA__TERMIN_SEL EQU 0\r
-SCSI_RX_DMA__TERMOUT0_EN EQU 1\r
-SCSI_RX_DMA__TERMOUT0_SEL EQU 0\r
-SCSI_RX_DMA__TERMOUT1_EN EQU 0\r
-SCSI_RX_DMA__TERMOUT1_SEL EQU 0\r
-\r
-; SCSI_RX_DMA_COMPLETE\r
-SCSI_RX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
-SCSI_RX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
-SCSI_RX_DMA_COMPLETE__INTC_MASK EQU 0x01\r
-SCSI_RX_DMA_COMPLETE__INTC_NUMBER EQU 0\r
-SCSI_RX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7\r
-SCSI_RX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_0\r
-SCSI_RX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
-SCSI_RX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
-\r
-; SCSI_TX_DMA\r
-SCSI_TX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0\r
-SCSI_TX_DMA__DRQ_NUMBER EQU 1\r
-SCSI_TX_DMA__NUMBEROF_TDS EQU 0\r
-SCSI_TX_DMA__PRIORITY EQU 2\r
-SCSI_TX_DMA__TERMIN_EN EQU 0\r
-SCSI_TX_DMA__TERMIN_SEL EQU 0\r
-SCSI_TX_DMA__TERMOUT0_EN EQU 1\r
-SCSI_TX_DMA__TERMOUT0_SEL EQU 1\r
-SCSI_TX_DMA__TERMOUT1_EN EQU 0\r
-SCSI_TX_DMA__TERMOUT1_SEL EQU 0\r
-\r
-; SCSI_TX_DMA_COMPLETE\r
-SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
-SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
-SCSI_TX_DMA_COMPLETE__INTC_MASK EQU 0x10\r
-SCSI_TX_DMA_COMPLETE__INTC_NUMBER EQU 4\r
-SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7\r
-SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_4\r
-SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
-SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
-\r
-; SD_Data_Clk\r
-SD_Data_Clk__CFG0 EQU CYREG_CLKDIST_DCFG0_CFG0\r
-SD_Data_Clk__CFG1 EQU CYREG_CLKDIST_DCFG0_CFG1\r
-SD_Data_Clk__CFG2 EQU CYREG_CLKDIST_DCFG0_CFG2\r
-SD_Data_Clk__CFG2_SRC_SEL_MASK EQU 0x07\r
-SD_Data_Clk__INDEX EQU 0x00\r
-SD_Data_Clk__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2\r
-SD_Data_Clk__PM_ACT_MSK EQU 0x01\r
-SD_Data_Clk__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2\r
-SD_Data_Clk__PM_STBY_MSK EQU 0x01\r
-\r
 ; timer_clock\r
 timer_clock__CFG0 EQU CYREG_CLKDIST_DCFG2_CFG0\r
 timer_clock__CFG1 EQU CYREG_CLKDIST_DCFG2_CFG1\r
@@ -2892,146 +2965,53 @@ timer_clock__PM_ACT_MSK EQU 0x04
 timer_clock__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2\r
 timer_clock__PM_STBY_MSK EQU 0x04\r
 \r
-; SCSI_RST_ISR\r
-SCSI_RST_ISR__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
-SCSI_RST_ISR__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
-SCSI_RST_ISR__INTC_MASK EQU 0x04\r
-SCSI_RST_ISR__INTC_NUMBER EQU 2\r
-SCSI_RST_ISR__INTC_PRIOR_NUM EQU 7\r
-SCSI_RST_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_2\r
-SCSI_RST_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
-SCSI_RST_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
-\r
-; SCSI_SEL_ISR\r
-SCSI_SEL_ISR__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
-SCSI_SEL_ISR__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
-SCSI_SEL_ISR__INTC_MASK EQU 0x08\r
-SCSI_SEL_ISR__INTC_NUMBER EQU 3\r
-SCSI_SEL_ISR__INTC_PRIOR_NUM EQU 7\r
-SCSI_SEL_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_3\r
-SCSI_SEL_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
-SCSI_SEL_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
-\r
-; SCSI_Filtered\r
-SCSI_Filtered_sts_sts_reg__0__MASK EQU 0x01\r
-SCSI_Filtered_sts_sts_reg__0__POS EQU 0\r
-SCSI_Filtered_sts_sts_reg__1__MASK EQU 0x02\r
-SCSI_Filtered_sts_sts_reg__1__POS EQU 1\r
-SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL\r
-SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB11_12_ST\r
-SCSI_Filtered_sts_sts_reg__2__MASK EQU 0x04\r
-SCSI_Filtered_sts_sts_reg__2__POS EQU 2\r
-SCSI_Filtered_sts_sts_reg__3__MASK EQU 0x08\r
-SCSI_Filtered_sts_sts_reg__3__POS EQU 3\r
-SCSI_Filtered_sts_sts_reg__4__MASK EQU 0x10\r
-SCSI_Filtered_sts_sts_reg__4__POS EQU 4\r
-SCSI_Filtered_sts_sts_reg__MASK EQU 0x1F\r
-SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB11_MSK\r
-SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL\r
-SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB11_ST\r
-\r
-; SCSI_CTL_PHASE\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS EQU 0\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK EQU 0x02\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS EQU 1\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB06_07_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB06_07_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB06_07_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB06_07_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB06_07_MSK\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB06_07_MSK\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB06_07_MSK\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB06_07_MSK\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK EQU 0x04\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS EQU 2\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB06_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB06_ST_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB06_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB06_ST_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__MASK EQU 0x07\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB06_MSK\r
-\r
-; SCSI_Glitch_Ctl\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS EQU 0\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB04_05_CTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB04_05_CTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB04_05_MSK\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB04_05_MSK\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB04_CTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB04_ST_CTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB04_CTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB04_ST_CTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK EQU 0x01\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB04_MSK\r
-\r
-; SCSI_Parity_Error\r
-SCSI_Parity_Error_sts_sts_reg__0__MASK EQU 0x01\r
-SCSI_Parity_Error_sts_sts_reg__0__POS EQU 0\r
-SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL\r
-SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB05_06_ST\r
-SCSI_Parity_Error_sts_sts_reg__MASK EQU 0x01\r
-SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB05_MSK\r
-SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL\r
-SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB05_ST\r
-\r
 ; Miscellaneous\r
 BCLK__BUS_CLK__HZ EQU 50000000\r
 BCLK__BUS_CLK__KHZ EQU 50000\r
 BCLK__BUS_CLK__MHZ EQU 50\r
 CYDEV_CHIP_DIE_LEOPARD EQU 1\r
-CYDEV_CHIP_DIE_PSOC4A EQU 12\r
-CYDEV_CHIP_DIE_PSOC5LP EQU 19\r
-CYDEV_CHIP_DIE_PSOC5TM EQU 20\r
-CYDEV_CHIP_DIE_TMA4 EQU 2\r
+CYDEV_CHIP_DIE_PSOC4A EQU 16\r
+CYDEV_CHIP_DIE_PSOC5LP EQU 2\r
+CYDEV_CHIP_DIE_PSOC5TM EQU 3\r
+CYDEV_CHIP_DIE_TMA4 EQU 4\r
 CYDEV_CHIP_DIE_UNKNOWN EQU 0\r
-CYDEV_CHIP_FAMILY_FM0P EQU 4\r
-CYDEV_CHIP_FAMILY_FM3 EQU 5\r
-CYDEV_CHIP_FAMILY_FM4 EQU 6\r
+CYDEV_CHIP_FAMILY_FM0P EQU 5\r
+CYDEV_CHIP_FAMILY_FM3 EQU 6\r
+CYDEV_CHIP_FAMILY_FM4 EQU 7\r
 CYDEV_CHIP_FAMILY_PSOC3 EQU 1\r
 CYDEV_CHIP_FAMILY_PSOC4 EQU 2\r
 CYDEV_CHIP_FAMILY_PSOC5 EQU 3\r
+CYDEV_CHIP_FAMILY_PSOC6 EQU 4\r
 CYDEV_CHIP_FAMILY_UNKNOWN EQU 0\r
 CYDEV_CHIP_FAMILY_USED EQU CYDEV_CHIP_FAMILY_PSOC5\r
 CYDEV_CHIP_JTAG_ID EQU 0x2E133069\r
 CYDEV_CHIP_MEMBER_3A EQU 1\r
-CYDEV_CHIP_MEMBER_4A EQU 12\r
-CYDEV_CHIP_MEMBER_4C EQU 18\r
-CYDEV_CHIP_MEMBER_4D EQU 8\r
-CYDEV_CHIP_MEMBER_4E EQU 4\r
-CYDEV_CHIP_MEMBER_4F EQU 13\r
-CYDEV_CHIP_MEMBER_4G EQU 2\r
-CYDEV_CHIP_MEMBER_4H EQU 11\r
-CYDEV_CHIP_MEMBER_4I EQU 17\r
-CYDEV_CHIP_MEMBER_4J EQU 9\r
-CYDEV_CHIP_MEMBER_4K EQU 10\r
-CYDEV_CHIP_MEMBER_4L EQU 16\r
-CYDEV_CHIP_MEMBER_4M EQU 15\r
-CYDEV_CHIP_MEMBER_4N EQU 6\r
-CYDEV_CHIP_MEMBER_4O EQU 5\r
-CYDEV_CHIP_MEMBER_4P EQU 14\r
-CYDEV_CHIP_MEMBER_4Q EQU 7\r
-CYDEV_CHIP_MEMBER_4U EQU 3\r
-CYDEV_CHIP_MEMBER_5A EQU 20\r
-CYDEV_CHIP_MEMBER_5B EQU 19\r
-CYDEV_CHIP_MEMBER_FM3 EQU 24\r
-CYDEV_CHIP_MEMBER_FM4 EQU 25\r
-CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE1 EQU 21\r
-CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE2 EQU 22\r
-CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE3 EQU 23\r
+CYDEV_CHIP_MEMBER_4A EQU 16\r
+CYDEV_CHIP_MEMBER_4D EQU 12\r
+CYDEV_CHIP_MEMBER_4E EQU 6\r
+CYDEV_CHIP_MEMBER_4F EQU 17\r
+CYDEV_CHIP_MEMBER_4G EQU 4\r
+CYDEV_CHIP_MEMBER_4H EQU 15\r
+CYDEV_CHIP_MEMBER_4I EQU 21\r
+CYDEV_CHIP_MEMBER_4J EQU 13\r
+CYDEV_CHIP_MEMBER_4K EQU 14\r
+CYDEV_CHIP_MEMBER_4L EQU 20\r
+CYDEV_CHIP_MEMBER_4M EQU 19\r
+CYDEV_CHIP_MEMBER_4N EQU 9\r
+CYDEV_CHIP_MEMBER_4O EQU 7\r
+CYDEV_CHIP_MEMBER_4P EQU 18\r
+CYDEV_CHIP_MEMBER_4Q EQU 11\r
+CYDEV_CHIP_MEMBER_4R EQU 8\r
+CYDEV_CHIP_MEMBER_4S EQU 10\r
+CYDEV_CHIP_MEMBER_4U EQU 5\r
+CYDEV_CHIP_MEMBER_5A EQU 3\r
+CYDEV_CHIP_MEMBER_5B EQU 2\r
+CYDEV_CHIP_MEMBER_6A EQU 22\r
+CYDEV_CHIP_MEMBER_FM3 EQU 26\r
+CYDEV_CHIP_MEMBER_FM4 EQU 27\r
+CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE1 EQU 23\r
+CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE2 EQU 24\r
+CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE3 EQU 25\r
 CYDEV_CHIP_MEMBER_UNKNOWN EQU 0\r
 CYDEV_CHIP_MEMBER_USED EQU CYDEV_CHIP_MEMBER_5B\r
 CYDEV_CHIP_DIE_EXPECT EQU CYDEV_CHIP_MEMBER_USED\r
@@ -3056,7 +3036,6 @@ CYDEV_CHIP_REVISION_3A_ES3 EQU 3
 CYDEV_CHIP_REVISION_3A_PRODUCTION EQU 3\r
 CYDEV_CHIP_REVISION_4A_ES0 EQU 17\r
 CYDEV_CHIP_REVISION_4A_PRODUCTION EQU 17\r
-CYDEV_CHIP_REVISION_4C_PRODUCTION EQU 0\r
 CYDEV_CHIP_REVISION_4D_PRODUCTION EQU 0\r
 CYDEV_CHIP_REVISION_4E_PRODUCTION EQU 0\r
 CYDEV_CHIP_REVISION_4F_PRODUCTION EQU 0\r
@@ -3075,12 +3054,16 @@ CYDEV_CHIP_REVISION_4N_PRODUCTION EQU 0
 CYDEV_CHIP_REVISION_4O_PRODUCTION EQU 0\r
 CYDEV_CHIP_REVISION_4P_PRODUCTION EQU 0\r
 CYDEV_CHIP_REVISION_4Q_PRODUCTION EQU 0\r
+CYDEV_CHIP_REVISION_4R_PRODUCTION EQU 0\r
+CYDEV_CHIP_REVISION_4S_PRODUCTION EQU 0\r
 CYDEV_CHIP_REVISION_4U_PRODUCTION EQU 0\r
 CYDEV_CHIP_REVISION_5A_ES0 EQU 0\r
 CYDEV_CHIP_REVISION_5A_ES1 EQU 1\r
 CYDEV_CHIP_REVISION_5A_PRODUCTION EQU 1\r
 CYDEV_CHIP_REVISION_5B_ES0 EQU 0\r
 CYDEV_CHIP_REVISION_5B_PRODUCTION EQU 0\r
+CYDEV_CHIP_REVISION_6A_NO_UDB EQU 0\r
+CYDEV_CHIP_REVISION_6A_PRODUCTION EQU 0\r
 CYDEV_CHIP_REVISION_FM3_PRODUCTION EQU 0\r
 CYDEV_CHIP_REVISION_FM4_PRODUCTION EQU 0\r
 CYDEV_CHIP_REVISION_PDL_FM0P_TYPE1_PRODUCTION EQU 0\r
@@ -3112,7 +3095,7 @@ CYDEV_DMA_CHANNELS_AVAILABLE EQU 24
 CYDEV_ECC_ENABLE EQU 0\r
 CYDEV_HEAP_SIZE EQU 0x0400\r
 CYDEV_INSTRUCT_CACHE_ENABLED EQU 1\r
-CYDEV_INTR_RISING EQU 0x0000007E\r
+CYDEV_INTR_RISING EQU 0x0000007F\r
 CYDEV_IS_EXPORTING_CODE EQU 0\r
 CYDEV_IS_IMPORTING_CODE EQU 0\r
 CYDEV_PROJ_TYPE EQU 2\r

diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cymetadata.c b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cymetadata.c
index 8638ffbb4537e60745ae3609052c798a45935a74..e8e92b1cf9a07ac2bbd7af856de309ca9a17ed7d 100755 (executable)
--- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cymetadata.c
+++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cymetadata.c
@@ -1,21 +1,21 @@
 /*******************************************************************************\r
 * File Name: cymetadata.c\r
 * \r
-* PSoC Creator  4.0 Update 1\r
+* PSoC Creator  4.1\r
 *\r
 * Description:\r
 * This file defines all extra memory spaces that need to be included.\r
 * This file is automatically generated by PSoC Creator.\r
 *\r
 ********************************************************************************\r
-* Copyright (c) 2007-2016 Cypress Semiconductor.  All rights reserved.\r
+* Copyright (c) 2007-2017 Cypress Semiconductor.  All rights reserved.\r
 * You may use this file only in accordance with the license, terms, conditions, \r
 * disclaimers, and limitations in the end user license agreement accompanying \r
 * the software package with which this file was provided.\r
 ********************************************************************************/\r
 \r
 \r
-#include "cytypes.h"\r
+#include "stdint.h"\r
 \r
 \r
 #if defined(__GNUC__) || defined(__ARMCC_VERSION)\r
@@ -28,7 +28,7 @@ CY_LOADABLE_META_SECTION
 #else\r
 #error "Unsupported toolchain"\r
 #endif\r
-const uint8 cy_meta_loadable[] = {\r
+const uint8_t cy_meta_loadable[] = {\r
     0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,\r
     0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,\r
     0x00u, 0x00u, 0x00u, 0x00u, 0x5Cu, 0xD1u, 0x71u, 0x04u,\r
@@ -49,6 +49,6 @@ CY_CONFIG_ECC_SECTION
 #else\r
 #error "Unsupported toolchain"\r
 #endif\r
-const uint8 cy_meta_configecc[] = {\r
+const uint8_t cy_meta_configecc[] = {\r
     0x00u\r
 };\r

diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/project.h b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/project.h
index 90728b217ce1b4c037710c442fba63a078bc22af..9e44652252f381a386ccc0e0d9b07a22c0b49a79 100755 (executable)
--- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/project.h
+++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/project.h
@@ -1,14 +1,14 @@
 /*******************************************************************************\r
 * File Name: project.h\r
 * \r
-* PSoC Creator  4.0 Update 1\r
+* PSoC Creator  4.1\r
 *\r
 * Description:\r
 * It contains references to all generated header files and should not be modified.\r
 * This file is automatically generated by PSoC Creator.\r
 *\r
 ********************************************************************************\r
-* Copyright (c) 2007-2016 Cypress Semiconductor.  All rights reserved.\r
+* Copyright (c) 2007-2017 Cypress Semiconductor.  All rights reserved.\r
 * You may use this file only in accordance with the license, terms, conditions, \r
 * disclaimers, and limitations in the end user license agreement accompanying \r
 * the software package with which this file was provided.\r

diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/SCSI2SD.cyfit b/software/SCSI2SD/v4/SCSI2SD.cydsn/SCSI2SD.cyfit
index 69c23d7cf0fcd472fd0ad5d7f7587f6a158a3789..62ea486a2c0d08b99a10bbeae34ec42951a84959 100644 (file)
Binary files a/software/SCSI2SD/v4/SCSI2SD.cydsn/SCSI2SD.cyfit and b/software/SCSI2SD/v4/SCSI2SD.cydsn/SCSI2SD.cyfit differ

diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/SCSI2SD.cyprj b/software/SCSI2SD/v4/SCSI2SD.cydsn/SCSI2SD.cyprj
index 23db925f47ac68b6d1860a01dfaec56f468b5093..c18637dc65ae5fdeb35757794bd60c8e75542b8e 100755 (executable)
--- a/software/SCSI2SD/v4/SCSI2SD.cydsn/SCSI2SD.cyprj
+++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/SCSI2SD.cyprj
@@ -4,14 +4,14 @@
 <!--Due to this, there is no schema for this file.-->\r
 <CyGuid_fec8f9e8-2365-4bdb-96d3-a4380222e01b type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtProjectPSoCExeSerialize" version="4">\r
 <CyGuid_60697ce6-dce2-4816-8680-4de0635742eb type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtProjectExeSerialize" version="3">\r
-<CyGuid_49cfd574-032a-4a64-b7be-d4eeeaf25e43 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtProjectSerialize" version="7" xml_contents_version="1">\r
+<CyGuid_49cfd574-032a-4a64-b7be-d4eeeaf25e43 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtProjectSerialize" version="8" xml_contents_version="1">\r
 <CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtBaseContainerSerialize" version="1">\r
 <CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItemSerialize" version="2" name="SCSI2SD" persistent="SCSI2SD.cyprj">\r
 <Hidden v="False" />\r
 </CyGuid_31768f72-0253-412b-af77-e7dba74d1330>\r
 <CyGuid_0820c2e7-528d-4137-9a08-97257b946089 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItemListSerialize" version="2">\r
 <dependencies>\r
-<CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFolderSerialize" version="2">\r
+<CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFolderSerialize" version="3">\r
 <CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtBaseContainerSerialize" version="1">\r
 <CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItemSerialize" version="2" name="Source Files" persistent="">\r
 <Hidden v="False" />\r
@@ -161,7 +161,7 @@
 <filter v="a51" />\r
 </filters>\r
 </CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0>\r
-<CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFolderSerialize" version="2">\r
+<CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFolderSerialize" version="3">\r
 <CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtBaseContainerSerialize" version="1">\r
 <CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItemSerialize" version="2" name="Header Files" persistent="">\r
 <Hidden v="False" />\r
@@ -331,7 +331,7 @@
 </CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0>\r
 <CyGuid_4429d4ed-fe84-42d0-9e9f-19aee0ff4e7e type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtComponentSerialize" version="1">\r
 <CyGuid_813b8d13-518a-4dc8-91ba-cda6042dfb52 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtPhysicalFolderSerialize" version="1">\r
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@@ -557,7 +557,7 @@
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 <Hidden v="False" />\r
@@ -2024,7 +2024,7 @@
 </CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8>\r
 <filters />\r
 </CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0>\r
-<CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFolderSerialize" version="2">\r
+<CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFolderSerialize" version="3">\r
 <CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtBaseContainerSerialize" version="1">\r
 <CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItemSerialize" version="2" name="SCSI_Filtered" persistent="">\r
 <Hidden v="False" />\r
@@ -2050,7 +2050,7 @@
 </CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8>\r
 <filters />\r
 </CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0>\r
-<CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFolderSerialize" version="2">\r
+<CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFolderSerialize" version="3">\r
 <CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtBaseContainerSerialize" version="1">\r
 <CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItemSerialize" version="2" name="SCSI_SEL_ISR" persistent="">\r
 <Hidden v="False" />\r
@@ -2076,7 +2076,7 @@
 </CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8>\r
 <filters />\r
 </CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0>\r
-<CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFolderSerialize" version="2">\r
+<CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFolderSerialize" version="3">\r
 <CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtBaseContainerSerialize" version="1">\r
 <CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItemSerialize" version="2" name="SCSI_Glitch_Ctrl" persistent="">\r
 <Hidden v="True" />\r
@@ -2102,7 +2102,7 @@
 </CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8>\r
 <filters />\r
 </CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0>\r
-<CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFolderSerialize" version="2">\r
+<CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFolderSerialize" version="3">\r
 <CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtBaseContainerSerialize" version="1">\r
 <CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItemSerialize" version="2" name="SCSI_Glitch_Ctl" persistent="">\r
 <Hidden v="False" />\r
@@ -2172,7 +2172,7 @@
 </CyGuid_d8451a8e-a4ea-4e21-aba8-966eaa7ea07d>\r
 <CyGuid_4429d4ed-fe84-42d0-9e9f-19aee0ff4e7e type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtComponentSerialize" version="1">\r
 <CyGuid_813b8d13-518a-4dc8-91ba-cda6042dfb52 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtPhysicalFolderSerialize" version="1">\r
-<CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFolderSerialize" version="2">\r
+<CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFolderSerialize" version="3">\r
 <CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtBaseContainerSerialize" version="1">\r
 <CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItemSerialize" version="2" name="OddParityGen" persistent="OddParityGen">\r
 <Hidden v="False" />\r
@@ -2202,7 +2202,7 @@
 </CyGuid_4429d4ed-fe84-42d0-9e9f-19aee0ff4e7e>\r
 <CyGuid_4429d4ed-fe84-42d0-9e9f-19aee0ff4e7e type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtComponentSerialize" version="1">\r
 <CyGuid_813b8d13-518a-4dc8-91ba-cda6042dfb52 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtPhysicalFolderSerialize" version="1">\r
-<CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFolderSerialize" version="2">\r
+<CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFolderSerialize" version="3">\r
 <CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtBaseContainerSerialize" version="1">\r
 <CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItemSerialize" version="2" name="scsiTarget" persistent="scsiTarget">\r
 <Hidden v="False" />\r
@@ -2281,10 +2281,10 @@
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@C/C++@General@Struct Return Method" v="System Default" />\r
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@C/C++@General@Verbose Asm" v="False" />\r
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@C/C++@Optimization@Remove Unused Functions" v="True" />\r
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@C/C++@Optimization@Fat LTO objects" v="True" />\r
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@C/C++@Optimization@Inline Functions" v="False" />\r
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@C/C++@Optimization@Optimization Level" v="None" />\r
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@C/C++@Optimization@Link Time Optimization" v="False" />\r
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@C/C++@Optimization@Fat LTO objects" v="True" />\r
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@C/C++@Optimization@Optimization Level" v="None" />\r
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@C/C++@Command Line@Command Line" v="" />\r
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Library Generation@Command Line@Command Line" v="" />\r
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Linker@General@Additional Libraries" v="" />\r
@@ -2297,6 +2297,15 @@
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Linker@General@Enable Float printf" v="False" />\r
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Linker@Optimization@Remove Unused Functions" v="True" />\r
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Linker@Command Line@Command Line" v="" />\r
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Linker@Optimization@SHARED Generate Debugging Information" v="" />\r
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Linker@Optimization@SHARED Struct Return Method" v="" />\r
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Linker@Optimization@SHARED Remove Unused Functions" v="" />\r
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Linker@Optimization@SHARED Inline Functions" v="" />\r
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Linker@Optimization@SHARED Optimization Level" v="" />\r
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Linker@Optimization@SHARED Link Time Optimization" v="" />\r
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Linker@Optimization@SHARED Fat LTO objects" v="" />\r
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@User Commands@General@Pre Build Commands" v="" />\r
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@User Commands@General@Post Build Commands" v="" />\r
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@General@Output Directory" v="${ProjectDir}\${ProcessorType}\${Platform}\${Config}" />\r
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@Assembly@General@Additional Include Directories" v="" />\r
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@Assembly@General@Create Listing File" v="True" />\r
@@ -2315,10 +2324,10 @@
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@C/C++@General@Struct Return Method" v="System Default" />\r
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@C/C++@General@Verbose Asm" v="False" />\r
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@C/C++@Optimization@Remove Unused Functions" v="True" />\r
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@C/C++@Optimization@Fat LTO objects" v="True" />\r
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@C/C++@Optimization@Inline Functions" v="False" />\r
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@C/C++@Optimization@Optimization Level" v="Size" />\r
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@C/C++@Optimization@Link Time Optimization" v="False" />\r
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@C/C++@Optimization@Fat LTO objects" v="True" />\r
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@C/C++@Optimization@Optimization Level" v="Size" />\r
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@C/C++@Command Line@Command Line" v="" />\r
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@Library Generation@Command Line@Command Line" v="" />\r
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@Linker@General@Additional Libraries" v="" />\r
@@ -2331,6 +2340,15 @@
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@Linker@General@Enable Float printf" v="False" />\r
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@Linker@Optimization@Remove Unused Functions" v="True" />\r
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@Linker@Command Line@Command Line" v="" />\r
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@Linker@Optimization@SHARED Generate Debugging Information" v="" />\r
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@Linker@Optimization@SHARED Struct Return Method" v="" />\r
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@Linker@Optimization@SHARED Remove Unused Functions" v="" />\r
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@Linker@Optimization@SHARED Inline Functions" v="" />\r
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@Linker@Optimization@SHARED Optimization Level" v="" />\r
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@Linker@Optimization@SHARED Link Time Optimization" v="" />\r
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@Linker@Optimization@SHARED Fat LTO objects" v="" />\r
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@User Commands@General@Pre Build Commands" v="" />\r
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@User Commands@General@Post Build Commands" v="" />\r
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@General@Output Directory" v="${ProjectDir}\${ProcessorType}\${Platform}\${Config}" />\r
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@Assembly@General@Additional Include Directories" v="" />\r
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@Assembly@General@Create Listing File" v="True" />\r
@@ -2349,10 +2367,10 @@
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@C/C++@General@Struct Return Method" v="System Default" />\r
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@C/C++@General@Verbose Asm" v="False" />\r
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@C/C++@Optimization@Remove Unused Functions" v="True" />\r
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@C/C++@Optimization@Fat LTO objects" v="True" />\r
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@C/C++@Optimization@Inline Functions" v="False" />\r
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@C/C++@Optimization@Optimization Level" v="None" />\r
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@C/C++@Optimization@Link Time Optimization" v="False" />\r
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@C/C++@Optimization@Fat LTO objects" v="True" />\r
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@C/C++@Optimization@Optimization Level" v="None" />\r
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@C/C++@Command Line@Command Line" v="" />\r
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@Library Generation@Command Line@Command Line" v="" />\r
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@Linker@General@Additional Libraries" v="" />\r
@@ -2365,6 +2383,15 @@
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@Linker@General@Enable Float printf" v="False" />\r
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@Linker@Optimization@Remove Unused Functions" v="True" />\r
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@Linker@Command Line@Command Line" v="" />\r
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@Linker@Optimization@SHARED Generate Debugging Information" v="" />\r
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@Linker@Optimization@SHARED Struct Return Method" v="" />\r
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@Linker@Optimization@SHARED Remove Unused Functions" v="" />\r
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@Linker@Optimization@SHARED Inline Functions" v="" />\r
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@Linker@Optimization@SHARED Optimization Level" v="" />\r
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@Linker@Optimization@SHARED Link Time Optimization" v="" />\r
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@Linker@Optimization@SHARED Fat LTO objects" v="" />\r
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@User Commands@General@Pre Build Commands" v="" />\r
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@User Commands@General@Post Build Commands" v="" />\r
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@General@Output Directory" v="${ProjectDir}\${ProcessorType}\${Platform}\${Config}" />\r
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@Assembly@General@Additional Include Directories" v="" />\r
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@Assembly@General@Create Listing File" v="True" />\r
@@ -2383,10 +2410,10 @@
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@C/C++@General@Struct Return Method" v="System Default" />\r
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@C/C++@General@Verbose Asm" v="False" />\r
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@C/C++@Optimization@Remove Unused Functions" v="True" />\r
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@C/C++@Optimization@Fat LTO objects" v="True" />\r
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@C/C++@Optimization@Inline Functions" v="True" />\r
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@C/C++@Optimization@Optimization Level" v="Size" />\r
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@C/C++@Optimization@Link Time Optimization" v="False" />\r
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@C/C++@Optimization@Fat LTO objects" v="True" />\r
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@C/C++@Optimization@Optimization Level" v="Size" />\r
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@C/C++@Command Line@Command Line" v="" />\r
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@Library Generation@Command Line@Command Line" v="" />\r
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@Linker@General@Additional Libraries" v="" />\r
@@ -2399,6 +2426,15 @@
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@Linker@General@Enable Float printf" v="False" />\r
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@Linker@Optimization@Remove Unused Functions" v="True" />\r
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@Linker@Command Line@Command Line" v="" />\r
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@Linker@Optimization@SHARED Generate Debugging Information" v="" />\r
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@Linker@Optimization@SHARED Struct Return Method" v="" />\r
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@Linker@Optimization@SHARED Remove Unused Functions" v="" />\r
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@Linker@Optimization@SHARED Inline Functions" v="" />\r
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@Linker@Optimization@SHARED Optimization Level" v="" />\r
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@Linker@Optimization@SHARED Link Time Optimization" v="" />\r
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@Linker@Optimization@SHARED Fat LTO objects" v="" />\r
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@User Commands@General@Pre Build Commands" v="" />\r
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@User Commands@General@Post Build Commands" v="" />\r
 </name>\r
 </platform>\r
 <platform>\r
@@ -2421,10 +2457,10 @@
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM0@C/C++@General@Struct Return Method" v="System Default" />\r
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM0@C/C++@General@Verbose Asm" v="False" />\r
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM0@C/C++@Optimization@Remove Unused Functions" v="True" />\r
+<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM0@C/C++@Optimization@Fat LTO objects" v="True" />\r
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM0@C/C++@Optimization@Inline Functions" v="False" />\r
-<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM0@C/C++@Optimization@Optimization Level" v="None" />\r
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM0@C/C++@Optimization@Link Time Optimization" v="False" />\r
-<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM0@C/C++@Optimization@Fat LTO objects" v="True" />\r
+<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM0@C/C++@Optimization@Optimization Level" v="None" />\r
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM0@C/C++@Command Line@Command Line" v="" />\r
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM0@Library Generation@Command Line@Command Line" v="" />\r
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM0@Linker@General@Additional Libraries" v="" />\r
@@ -2437,6 +2473,15 @@
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM0@Linker@General@Enable Float printf" v="False" />\r
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM0@Linker@Optimization@Remove Unused Functions" v="True" />\r
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM0@Linker@Command Line@Command Line" v="" />\r
+<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM0@Linker@Optimization@SHARED Generate Debugging Information" v="" />\r
+<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM0@Linker@Optimization@SHARED Struct Return Method" v="" />\r
+<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM0@Linker@Optimization@SHARED Remove Unused Functions" v="" />\r
+<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM0@Linker@Optimization@SHARED Inline Functions" v="" />\r
+<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM0@Linker@Optimization@SHARED Optimization Level" v="" />\r
+<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM0@Linker@Optimization@SHARED Link Time Optimization" v="" />\r
+<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM0@Linker@Optimization@SHARED Fat LTO objects" v="" />\r
+<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM0@User Commands@General@Pre Build Commands" v="" />\r
+<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM0@User Commands@General@Post Build Commands" v="" />\r
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM0@General@Output Directory" v="${ProjectDir}\${ProcessorType}\${Platform}\${Config}" />\r
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM0@Assembly@General@Additional Include Directories" v="" />\r
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM0@Assembly@General@Create Listing File" v="True" />\r
@@ -2455,10 +2500,10 @@
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM0@C/C++@General@Struct Return Method" v="System Default" />\r
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM0@C/C++@General@Verbose Asm" v="False" />\r
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM0@C/C++@Optimization@Remove Unused Functions" v="True" />\r
+<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM0@C/C++@Optimization@Fat LTO objects" v="True" />\r
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM0@C/C++@Optimization@Inline Functions" v="False" />\r
-<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM0@C/C++@Optimization@Optimization Level" v="Size" />\r
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM0@C/C++@Optimization@Link Time Optimization" v="False" />\r
-<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM0@C/C++@Optimization@Fat LTO objects" v="True" />\r
+<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM0@C/C++@Optimization@Optimization Level" v="Size" />\r
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM0@C/C++@Command Line@Command Line" v="" />\r
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM0@Library Generation@Command Line@Command Line" v="" />\r
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM0@Linker@General@Additional Libraries" v="" />\r
@@ -2471,6 +2516,15 @@
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM0@Linker@General@Enable Float printf" v="False" />\r
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM0@Linker@Optimization@Remove Unused Functions" v="True" />\r
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM0@Linker@Command Line@Command Line" v="" />\r
+<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM0@Linker@Optimization@SHARED Generate Debugging Information" v="" />\r
+<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM0@Linker@Optimization@SHARED Struct Return Method" v="" />\r
+<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM0@Linker@Optimization@SHARED Remove Unused Functions" v="" />\r
+<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM0@Linker@Optimization@SHARED Inline Functions" v="" />\r
+<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM0@Linker@Optimization@SHARED Optimization Level" v="" />\r
+<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM0@Linker@Optimization@SHARED Link Time Optimization" v="" />\r
+<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM0@Linker@Optimization@SHARED Fat LTO objects" v="" />\r
+<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM0@User Commands@General@Pre Build Commands" v="" />\r
+<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM0@User Commands@General@Post Build Commands" v="" />\r
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM3@General@Output Directory" v="${ProjectDir}\${ProcessorType}\${Platform}\${Config}" />\r
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM3@Assembly@General@Additional Include Directories" v="" />\r
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM3@Assembly@General@Create Listing File" v="True" />\r
@@ -2489,10 +2543,10 @@
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM3@C/C++@General@Struct Return Method" v="System Default" />\r
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM3@C/C++@General@Verbose Asm" v="False" />\r
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM3@C/C++@Optimization@Remove Unused Functions" v="True" />\r
+<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM3@C/C++@Optimization@Fat LTO objects" v="True" />\r
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM3@C/C++@Optimization@Inline Functions" v="False" />\r
-<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM3@C/C++@Optimization@Optimization Level" v="None" />\r
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM3@C/C++@Optimization@Link Time Optimization" v="False" />\r
-<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM3@C/C++@Optimization@Fat LTO objects" v="True" />\r
+<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM3@C/C++@Optimization@Optimization Level" v="None" />\r
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM3@C/C++@Command Line@Command Line" v="" />\r
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM3@Library Generation@Command Line@Command Line" v="" />\r
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM3@Linker@General@Additional Libraries" v="" />\r
@@ -2505,6 +2559,15 @@
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM3@Linker@General@Enable Float printf" v="False" />\r
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM3@Linker@Optimization@Remove Unused Functions" v="True" />\r
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM3@Linker@Command Line@Command Line" v="" />\r
+<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM3@Linker@Optimization@SHARED Generate Debugging Information" v="" />\r
+<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM3@Linker@Optimization@SHARED Struct Return Method" v="" />\r
+<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM3@Linker@Optimization@SHARED Remove Unused Functions" v="" />\r
+<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM3@Linker@Optimization@SHARED Inline Functions" v="" />\r
+<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM3@Linker@Optimization@SHARED Optimization Level" v="" />\r
+<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM3@Linker@Optimization@SHARED Link Time Optimization" v="" />\r
+<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM3@Linker@Optimization@SHARED Fat LTO objects" v="" />\r
+<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM3@User Commands@General@Pre Build Commands" v="" />\r
+<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM3@User Commands@General@Post Build Commands" v="" />\r
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM3@General@Output Directory" v="${ProjectDir}\${ProcessorType}\${Platform}\${Config}" />\r
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM3@Assembly@General@Additional Include Directories" v="" />\r
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM3@Assembly@General@Create Listing File" v="True" />\r
@@ -2523,10 +2586,10 @@
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM3@C/C++@General@Struct Return Method" v="System Default" />\r
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM3@C/C++@General@Verbose Asm" v="False" />\r
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM3@C/C++@Optimization@Remove Unused Functions" v="True" />\r
+<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM3@C/C++@Optimization@Fat LTO objects" v="True" />\r
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM3@C/C++@Optimization@Inline Functions" v="False" />\r
-<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM3@C/C++@Optimization@Optimization Level" v="Size" />\r
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM3@C/C++@Optimization@Link Time Optimization" v="False" />\r
-<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM3@C/C++@Optimization@Fat LTO objects" v="True" />\r
+<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM3@C/C++@Optimization@Optimization Level" v="Size" />\r
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM3@C/C++@Command Line@Command Line" v="" />\r
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM3@Library Generation@Command Line@Command Line" v="" />\r
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM3@Linker@General@Additional Libraries" v="" />\r
@@ -2539,14 +2602,31 @@
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM3@Linker@General@Enable Float printf" v="False" />\r
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM3@Linker@Optimization@Remove Unused Functions" v="True" />\r
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM3@Linker@Command Line@Command Line" v="" />\r
+<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM3@Linker@Optimization@SHARED Generate Debugging Information" v="" />\r
+<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM3@Linker@Optimization@SHARED Struct Return Method" v="" />\r
+<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM3@Linker@Optimization@SHARED Remove Unused Functions" v="" />\r
+<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM3@Linker@Optimization@SHARED Inline Functions" v="" />\r
+<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM3@Linker@Optimization@SHARED Optimization Level" v="" />\r
+<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM3@Linker@Optimization@SHARED Link Time Optimization" v="" />\r
+<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM3@Linker@Optimization@SHARED Fat LTO objects" v="" />\r
+<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM3@User Commands@General@Pre Build Commands" v="" />\r
+<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM3@User Commands@General@Post Build Commands" v="" />\r
 </name>\r
 </platform>\r
 <platform>\r
 <name v="5bca58cd-5542-421c-b08d-9513dbb687fd">\r
 <name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Debug@CortexM0@General@Output Directory" v="${ProjectDir}\${ProcessorType}\${Platform}\${Config}" />\r
+<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Debug@CortexM0@User Commands@General@Pre Build Commands" v="" />\r
+<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Debug@CortexM0@User Commands@General@Post Build Commands" v="" />\r
 <name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Release@CortexM0@General@Output Directory" v="${ProjectDir}\${ProcessorType}\${Platform}\${Config}" />\r
+<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Release@CortexM0@User Commands@General@Pre Build Commands" v="" />\r
+<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Release@CortexM0@User Commands@General@Post Build Commands" v="" />\r
 <name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Debug@CortexM3@General@Output Directory" v="${ProjectDir}\${ProcessorType}\${Platform}\${Config}" />\r
+<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Debug@CortexM3@User Commands@General@Pre Build Commands" v="" />\r
+<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Debug@CortexM3@User Commands@General@Post Build Commands" v="" />\r
 <name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Release@CortexM3@General@Output Directory" v="${ProjectDir}\${ProcessorType}\${Platform}\${Config}" />\r
+<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Release@CortexM3@User Commands@General@Pre Build Commands" v="" />\r
+<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Release@CortexM3@User Commands@General@Post Build Commands" v="" />\r
 </name>\r
 </platform>\r
 <platform>\r
@@ -2557,6 +2637,7 @@
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM0@Assembly@General@Suppress Warnings" v="False" />\r
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM0@Assembly@General@Generate List Files" v="True" />\r
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM0@Assembly@Command Line@Command Line" v="" />\r
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM0@Assembly@General@SHARED Use MicroLib" v="" />\r
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM0@C/C++@General@Additional Include Directories" v="" />\r
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM0@C/C++@General@Generate List Files" v="True" />\r
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM0@C/C++@General@Default Char Unsigned" v="False" />\r
@@ -2567,6 +2648,7 @@
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM0@C/C++@Optimization@Optimization Level" v="None" />\r
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM0@C/C++@Optimization@Split Sections" v="True" />\r
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM0@C/C++@Command Line@Command Line" v="" />\r
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM0@C/C++@General@SHARED Use MicroLib" v="" />\r
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM0@Library Generation@Command Line@Command Line" v="" />\r
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM0@Linker@General@Additional Libraries" v="" />\r
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM0@Linker@General@Additional Library Directories" v="" />\r
@@ -2576,12 +2658,15 @@
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM0@Linker@General@Generate Debugging Information" v="True" />\r
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM0@Linker@General@Use Default Libs" v="True" />\r
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM0@Linker@Command Line@Command Line" v="" />\r
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM0@User Commands@General@Pre Build Commands" v="" />\r
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM0@User Commands@General@Post Build Commands" v="" />\r
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM0@General@Output Directory" v="${ProjectDir}\${ProcessorType}\${Platform}\${Config}" />\r
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM0@Assembly@General@Additional Include Directories" v="" />\r
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM0@Assembly@General@Generate Debugging Information" v="True" />\r
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM0@Assembly@General@Suppress Warnings" v="False" />\r
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM0@Assembly@General@Generate List Files" v="True" />\r
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM0@Assembly@Command Line@Command Line" v="" />\r
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM0@Assembly@General@SHARED Use MicroLib" v="" />\r
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM0@C/C++@General@Additional Include Directories" v="" />\r
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM0@C/C++@General@Generate List Files" v="True" />\r
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM0@C/C++@General@Default Char Unsigned" v="False" />\r
@@ -2592,6 +2677,7 @@
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM0@C/C++@Optimization@Optimization Level" v="Size" />\r
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM0@C/C++@Optimization@Split Sections" v="True" />\r
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM0@C/C++@Command Line@Command Line" v="" />\r
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM0@C/C++@General@SHARED Use MicroLib" v="" />\r
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM0@Library Generation@Command Line@Command Line" v="" />\r
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM0@Linker@General@Additional Libraries" v="" />\r
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM0@Linker@General@Additional Library Directories" v="" />\r
@@ -2601,12 +2687,15 @@
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM0@Linker@General@Generate Debugging Information" v="True" />\r
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM0@Linker@General@Use Default Libs" v="True" />\r
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM0@Linker@Command Line@Command Line" v="" />\r
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM0@User Commands@General@Pre Build Commands" v="" />\r
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM0@User Commands@General@Post Build Commands" v="" />\r
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM3@General@Output Directory" v="${ProjectDir}\${ProcessorType}\${Platform}\${Config}" />\r
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM3@Assembly@General@Additional Include Directories" v="" />\r
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM3@Assembly@General@Generate Debugging Information" v="True" />\r
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM3@Assembly@General@Suppress Warnings" v="False" />\r
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM3@Assembly@General@Generate List Files" v="True" />\r
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM3@Assembly@Command Line@Command Line" v="" />\r
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM3@Assembly@General@SHARED Use MicroLib" v="" />\r
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM3@C/C++@General@Additional Include Directories" v="" />\r
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM3@C/C++@General@Generate List Files" v="True" />\r
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM3@C/C++@General@Default Char Unsigned" v="False" />\r
@@ -2617,6 +2706,7 @@
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM3@C/C++@Optimization@Optimization Level" v="None" />\r
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM3@C/C++@Optimization@Split Sections" v="True" />\r
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM3@C/C++@Command Line@Command Line" v="" />\r
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM3@C/C++@General@SHARED Use MicroLib" v="" />\r
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM3@Library Generation@Command Line@Command Line" v="" />\r
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM3@Linker@General@Additional Libraries" v="" />\r
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM3@Linker@General@Additional Library Directories" v="" />\r
@@ -2626,12 +2716,15 @@
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM3@Linker@General@Generate Debugging Information" v="True" />\r
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM3@Linker@General@Use Default Libs" v="True" />\r
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM3@Linker@Command Line@Command Line" v="" />\r
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM3@User Commands@General@Pre Build Commands" v="" />\r
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM3@User Commands@General@Post Build Commands" v="" />\r
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@General@Output Directory" v="${ProjectDir}\${ProcessorType}\${Platform}\${Config}" />\r
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@Assembly@General@Additional Include Directories" v="" />\r
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@Assembly@General@Generate Debugging Information" v="True" />\r
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@Assembly@General@Suppress Warnings" v="False" />\r
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@Assembly@General@Generate List Files" v="True" />\r
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@Assembly@Command Line@Command Line" v="" />\r
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@Assembly@General@SHARED Use MicroLib" v="" />\r
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@C/C++@General@Additional Include Directories" v="" />\r
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@C/C++@General@Generate List Files" v="True" />\r
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@C/C++@General@Default Char Unsigned" v="False" />\r
@@ -2642,6 +2735,7 @@
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@C/C++@Optimization@Optimization Level" v="Size" />\r
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@C/C++@Optimization@Split Sections" v="True" />\r
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@C/C++@Command Line@Command Line" v="" />\r
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@C/C++@General@SHARED Use MicroLib" v="" />\r
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@Library Generation@Command Line@Command Line" v="" />\r
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@Linker@General@Additional Libraries" v="" />\r
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@Linker@General@Additional Library Directories" v="" />\r
@@ -2651,31 +2745,33 @@
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@Linker@General@Generate Debugging Information" v="True" />\r
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@Linker@General@Use Default Libs" v="True" />\r
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@Linker@Command Line@Command Line" v="" />\r
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@User Commands@General@Pre Build Commands" v="" />\r
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@User Commands@General@Post Build Commands" v="" />\r
 </name>\r
 </platform>\r
 <platform>\r
 <name v="e9305a93-d091-4da5-bdc7-2813049dcdbf">\r
 <name_val_pair name="e9305a93-d091-4da5-bdc7-2813049dcdbf@Release@CortexM3@General@Output Directory" v="${ProjectDir}\${ProcessorType}\${Platform}\${Config}" />\r
 <name_val_pair name="e9305a93-d091-4da5-bdc7-2813049dcdbf@Release@CortexM3@Assembly@Command Line@Command Line" v="-s+ -M&lt;&gt; -w+ -r -DNDEBUG --fpu None" />\r
+<name_val_pair name="e9305a93-d091-4da5-bdc7-2813049dcdbf@Release@CortexM3@C/C++@General@Preprocessor Definitions" v="-D NDEBUG -D CY_CORE_ID=0" />\r
 <name_val_pair name="e9305a93-d091-4da5-bdc7-2813049dcdbf@Release@CortexM3@C/C++@Command Line@Command Line" v="-D NDEBUG --debug --endian=little -e --fpu=None --no_wrap_diagnostics" />\r
 <name_val_pair name="e9305a93-d091-4da5-bdc7-2813049dcdbf@Release@CortexM3@Library Generation@Command Line@Command Line" v="" />\r
 <name_val_pair name="e9305a93-d091-4da5-bdc7-2813049dcdbf@Release@CortexM3@Linker@Command Line@Command Line" v="--semihosting --entry __iar_program_start --vfe" />\r
+<name_val_pair name="e9305a93-d091-4da5-bdc7-2813049dcdbf@Release@CortexM3@User Commands@General@Pre Build Commands" v="" />\r
+<name_val_pair name="e9305a93-d091-4da5-bdc7-2813049dcdbf@Release@CortexM3@User Commands@General@Post Build Commands" v="" />\r
 </name>\r
 </platform>\r
 </platforms>\r
 <project_current_platform v="c9323d49-d323-40b8-9b59-cc008d68a989" />\r
-<project_current_processor v="CortexM3" />\r
 <last_selected_tab v="Cypress" />\r
-<WriteAppVersionLastSavedWith v="4.0.0.432" />\r
-<WriteAppMarketingVersionLastSavedWith v=" 4.0 Update 1" />\r
+<WriteAppVersionLastSavedWith v="4.1.0.2686" />\r
+<WriteAppMarketingVersionLastSavedWith v=" 4.1" />\r
 <project_id v="6e1f5cbb-a0ca-4f55-a1fa-7b20c5be3a3e" />\r
 <GenerateDescriptionFiles v="False" />\r
 </CyGuid_49cfd574-032a-4a64-b7be-d4eeeaf25e43>\r
 </CyGuid_60697ce6-dce2-4816-8680-4de0635742eb>\r
 <top_block v="TopDesign" />\r
 <selected_device v="CY8C5267AXI-LP051" />\r
-<pdl_path v="" />\r
-<include_paths />\r
 <CyGuid_495451fe-d201-4d01-b22d-5d3f5609ac37 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtComponentMgrSerialize" version="4" xml_contents_version="1">\r
 <library_deps>\r
 <library_dep persistent="${CyRoot}\psoc\content\default\CyAnnotationLibrary\CyAnnotationLibrary.cylib\CyAnnotationLibrary.cyprj" />\r

diff --git a/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CTL_PHASE.h b/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CTL_PHASE.h
index f9748551151276e172401d2eb196b069693766d5..4db2bae2d67bc7f1f49cde9b264bf6df036ad2b0 100755 (executable)
--- a/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CTL_PHASE.h
+++ b/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CTL_PHASE.h
@@ -17,7 +17,15 @@
 #if !defined(CY_CONTROL_REG_SCSI_CTL_PHASE_H) /* CY_CONTROL_REG_SCSI_CTL_PHASE_H */
 #define CY_CONTROL_REG_SCSI_CTL_PHASE_H
 
-#include "cytypes.h"
+#include "cyfitter.h"
+
+#if ((CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC3) || \
+     (CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC4) || \
+     (CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC5))
+    #include "cytypes.h"
+#else
+    #include "syslib/cy_syslib.h"
+#endif
 
     
 /***************************************

diff --git a/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Filtered.h b/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Filtered.h
index 87326f5b9c0558d53984d7d43565d6510ee5bdf8..c64ec62a4167a08ccbd95d16c2e4f9e19def34aa 100755 (executable)
--- a/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Filtered.h
+++ b/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Filtered.h
@@ -17,8 +17,16 @@
 #if !defined(CY_STATUS_REG_SCSI_Filtered_H) /* CY_STATUS_REG_SCSI_Filtered_H */
 #define CY_STATUS_REG_SCSI_Filtered_H
 
-#include "cytypes.h"
-#include "CyLib.h"
+#include "cyfitter.h"
+
+#if ((CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC3) || \
+     (CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC4) || \
+     (CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC5))
+    #include "cytypes.h"
+    #include "CyLib.h"
+#else
+    #include "syslib/cy_syslib.h"
+#endif
 
     
 /***************************************

diff --git a/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Glitch_Ctl.h b/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Glitch_Ctl.h
index d6c0d240f3f5f6986309bf10cc36ae4e4b00bbf8..88e1557e06da80895969e4fbea60768f173f2201 100755 (executable)
--- a/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Glitch_Ctl.h
+++ b/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Glitch_Ctl.h
@@ -17,7 +17,15 @@
 #if !defined(CY_CONTROL_REG_SCSI_Glitch_Ctl_H) /* CY_CONTROL_REG_SCSI_Glitch_Ctl_H */
 #define CY_CONTROL_REG_SCSI_Glitch_Ctl_H
 
-#include "cytypes.h"
+#include "cyfitter.h"
+
+#if ((CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC3) || \
+     (CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC4) || \
+     (CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC5))
+    #include "cytypes.h"
+#else
+    #include "syslib/cy_syslib.h"
+#endif
 
     
 /***************************************

diff --git a/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Out_Bits.h b/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Out_Bits.h
index 94ea62a85602fa1c20e5c7b7d654b1dab6b40546..1ada4ee13b054306079fe830d6e4caa3e98c29f1 100755 (executable)
--- a/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Out_Bits.h
+++ b/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Out_Bits.h
@@ -17,7 +17,15 @@
 #if !defined(CY_CONTROL_REG_SCSI_Out_Bits_H) /* CY_CONTROL_REG_SCSI_Out_Bits_H */
 #define CY_CONTROL_REG_SCSI_Out_Bits_H
 
-#include "cytypes.h"
+#include "cyfitter.h"
+
+#if ((CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC3) || \
+     (CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC4) || \
+     (CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC5))
+    #include "cytypes.h"
+#else
+    #include "syslib/cy_syslib.h"
+#endif
 
     
 /***************************************

diff --git a/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Out_Ctl.h b/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Out_Ctl.h
index e473a95f80eddb25f8d1e881fadbebf320ef9918..725873f0df1b011ffe20f96c9ea6043f816fee3f 100755 (executable)
--- a/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Out_Ctl.h
+++ b/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Out_Ctl.h
@@ -17,7 +17,15 @@
 #if !defined(CY_CONTROL_REG_SCSI_Out_Ctl_H) /* CY_CONTROL_REG_SCSI_Out_Ctl_H */
 #define CY_CONTROL_REG_SCSI_Out_Ctl_H
 
-#include "cytypes.h"
+#include "cyfitter.h"
+
+#if ((CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC3) || \
+     (CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC4) || \
+     (CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC5))
+    #include "cytypes.h"
+#else
+    #include "syslib/cy_syslib.h"
+#endif
 
     
 /***************************************

diff --git a/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Parity_Error.h b/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Parity_Error.h
index 532aff3b0a44489c7b4adbafe7bc145c33f05b20..de1ddc80b54289e90ed11265c478f24012072bc7 100755 (executable)
--- a/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Parity_Error.h
+++ b/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Parity_Error.h
@@ -17,8 +17,16 @@
 #if !defined(CY_STATUS_REG_SCSI_Parity_Error_H) /* CY_STATUS_REG_SCSI_Parity_Error_H */
 #define CY_STATUS_REG_SCSI_Parity_Error_H
 
-#include "cytypes.h"
-#include "CyLib.h"
+#include "cyfitter.h"
+
+#if ((CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC3) || \
+     (CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC4) || \
+     (CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC5))
+    #include "cytypes.h"
+    #include "CyLib.h"
+#else
+    #include "syslib/cy_syslib.h"
+#endif
 
     
 /***************************************

diff --git a/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/SDCard.h b/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/SDCard.h
index b209145db93ea53e7b3e50de50dbfc9a543d58ff..45b000ebed88ec6c0282e69d8d5b7f4dce07b4b0 100755 (executable)
--- a/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/SDCard.h
+++ b/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/SDCard.h
@@ -19,15 +19,9 @@
 #if !defined(CY_SPIM_SDCard_H)
 #define CY_SPIM_SDCard_H
 
-#include "cytypes.h"
 #include "cyfitter.h"
-#include "CyLib.h"
-
-/* Check to see if required defines such as CY_PSOC5A are available */
-/* They are defined starting with cy_boot v3.0 */
-#if !defined (CY_PSOC5A)
-    #error Component SPI_Master_v2_50 requires cy_boot v3.0 or later
-#endif /* (CY_PSOC5A) */
+#include "cytypes.h"
+#include "CyLib.h" /* For CyEnterCriticalSection() and CyExitCriticalSection() functions */
 
 
 /***************************************

diff --git a/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevice.h b/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevice.h
index 952bd9d33cb149ad472f7cd7cdd8234ad7000bc8..0cccfc8eebe34c685a25b0ea8f706e117586cee9 100755 (executable)
--- a/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevice.h
+++ b/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevice.h
@@ -1,14 +1,14 @@
 /*******************************************************************************
 * File Name: cydevice.h
 * OBSOLETE: Do not use this file. Use the _trm version instead.
-* PSoC Creator  4.0 Update 1
+* PSoC Creator  4.1
 *
 * Description:
 * This file provides all of the address values for the entire PSoC device.
 * This file is automatically generated by PSoC Creator.
 *
 ********************************************************************************
-* Copyright (c) 2007-2016 Cypress Semiconductor.  All rights reserved.
+* Copyright (c) 2007-2017 Cypress Semiconductor.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions, 
 * disclaimers, and limitations in the end user license agreement accompanying 
 * the software package with which this file was provided.

diff --git a/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevice_trm.h b/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevice_trm.h
index 89243eadaa7d3c777050bd99b6845bd0ebfca0bf..67ddde72c9682e728f27deb822ce5b6d6376e95c 100755 (executable)
--- a/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevice_trm.h
+++ b/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevice_trm.h
@@ -1,14 +1,14 @@
 /*******************************************************************************
 * File Name: cydevice_trm.h
 * 
-* PSoC Creator  4.0 Update 1
+* PSoC Creator  4.1
 *
 * Description:
 * This file provides all of the address values for the entire PSoC device.
 * This file is automatically generated by PSoC Creator.
 *
 ********************************************************************************
-* Copyright (c) 2007-2016 Cypress Semiconductor.  All rights reserved.
+* Copyright (c) 2007-2017 Cypress Semiconductor.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions, 
 * disclaimers, and limitations in the end user license agreement accompanying 
 * the software package with which this file was provided.

diff --git a/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicegnu.inc b/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicegnu.inc
index a80cb2bd52cd374cfb7104c92af3e1e42b1a815e..250050aff0585bcf85885eb2df94fee1e2e634dd 100755 (executable)
--- a/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicegnu.inc
+++ b/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicegnu.inc
@@ -1,14 +1,14 @@
 /*******************************************************************************
 * File Name: cydevicegnu.inc
 * OBSOLETE: Do not use this file. Use the _trm version instead.
-* PSoC Creator  4.0 Update 1
+* PSoC Creator  4.1
 *
 * Description:
 * This file provides all of the address values for the entire PSoC device.
 * This file is automatically generated by PSoC Creator.
 *
 ********************************************************************************
-* Copyright (c) 2007-2016 Cypress Semiconductor.  All rights reserved.
+* Copyright (c) 2007-2017 Cypress Semiconductor.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions, 
 * disclaimers, and limitations in the end user license agreement accompanying 
 * the software package with which this file was provided.

diff --git a/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicegnu_trm.inc b/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicegnu_trm.inc
index cd2972d98777489589c7260b7f455c467d047cb5..e8bf75df76a151b23a25dfc2510a6a411d3b456f 100755 (executable)
--- a/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicegnu_trm.inc
+++ b/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicegnu_trm.inc
@@ -1,14 +1,14 @@
 /*******************************************************************************
 * File Name: cydevicegnu_trm.inc
 * 
-* PSoC Creator  4.0 Update 1
+* PSoC Creator  4.1
 *
 * Description:
 * This file provides all of the address values for the entire PSoC device.
 * This file is automatically generated by PSoC Creator.
 *
 ********************************************************************************
-* Copyright (c) 2007-2016 Cypress Semiconductor.  All rights reserved.
+* Copyright (c) 2007-2017 Cypress Semiconductor.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions, 
 * disclaimers, and limitations in the end user license agreement accompanying 
 * the software package with which this file was provided.

diff --git a/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/cydeviceiar.inc b/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/cydeviceiar.inc
index 78618eaf4ca13fd64127456e626e973f1c35cb84..e6ddc72fb3c2493616bf0205980c4b3840b8fd97 100755 (executable)
--- a/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/cydeviceiar.inc
+++ b/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/cydeviceiar.inc
@@ -1,13 +1,13 @@
 ;
 ; File Name: cydeviceiar.inc
 ; OBSOLETE: Do not use this file. Use the _trm version instead.
-; PSoC Creator  4.0 Update 1
+; PSoC Creator  4.1
 ;
 ; Description:
 ; This file provides all of the address values for the entire PSoC device.
 ;
 ;-------------------------------------------------------------------------------
-; Copyright (c) 2007-2016 Cypress Semiconductor.  All rights reserved.
+; Copyright (c) 2007-2017 Cypress Semiconductor.  All rights reserved.
 ; You may use this file only in accordance with the license, terms, conditions, 
 ; disclaimers, and limitations in the end user license agreement accompanying 
 ; the software package with which this file was provided.

diff --git a/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/cydeviceiar_trm.inc b/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/cydeviceiar_trm.inc
index 5a152e43803952be8c1abf9f24afba473c2afc82..8b2eb9110c6b5267cb1da11723a498c7a1a4f00e 100755 (executable)
--- a/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/cydeviceiar_trm.inc
+++ b/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/cydeviceiar_trm.inc
@@ -1,13 +1,13 @@
 ;
 ; File Name: cydeviceiar_trm.inc
 ; 
-; PSoC Creator  4.0 Update 1
+; PSoC Creator  4.1
 ;
 ; Description:
 ; This file provides all of the address values for the entire PSoC device.
 ;
 ;-------------------------------------------------------------------------------
-; Copyright (c) 2007-2016 Cypress Semiconductor.  All rights reserved.
+; Copyright (c) 2007-2017 Cypress Semiconductor.  All rights reserved.
 ; You may use this file only in accordance with the license, terms, conditions, 
 ; disclaimers, and limitations in the end user license agreement accompanying 
 ; the software package with which this file was provided.

diff --git a/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicerv.inc b/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicerv.inc
index 44f36d2cc7bd997e38fe1c7f47336c586ade64f2..66261a1c57ed8e5bf7cdbfb58154eff235f522cb 100755 (executable)
--- a/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicerv.inc
+++ b/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicerv.inc
@@ -1,13 +1,13 @@
 ;
 ; File Name: cydevicerv.inc
 ; OBSOLETE: Do not use this file. Use the _trm version instead.
-; PSoC Creator  4.0 Update 1
+; PSoC Creator  4.1
 ;
 ; Description:
 ; This file provides all of the address values for the entire PSoC device.
 ;
 ;-------------------------------------------------------------------------------
-; Copyright (c) 2007-2016 Cypress Semiconductor.  All rights reserved.
+; Copyright (c) 2007-2017 Cypress Semiconductor.  All rights reserved.
 ; You may use this file only in accordance with the license, terms, conditions, 
 ; disclaimers, and limitations in the end user license agreement accompanying 
 ; the software package with which this file was provided.

diff --git a/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicerv_trm.inc b/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicerv_trm.inc
index 77f5e53f7ee8a93f1e4ef4f4a816d3401d06477e..cc1c32426e6811de40baa38c840d05b3a1a2ae54 100755 (executable)
--- a/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicerv_trm.inc
+++ b/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicerv_trm.inc
@@ -1,13 +1,13 @@
 ;
 ; File Name: cydevicerv_trm.inc
 ; 
-; PSoC Creator  4.0 Update 1
+; PSoC Creator  4.1
 ;
 ; Description:
 ; This file provides all of the address values for the entire PSoC device.
 ;
 ;-------------------------------------------------------------------------------
-; Copyright (c) 2007-2016 Cypress Semiconductor.  All rights reserved.
+; Copyright (c) 2007-2017 Cypress Semiconductor.  All rights reserved.
 ; You may use this file only in accordance with the license, terms, conditions, 
 ; disclaimers, and limitations in the end user license agreement accompanying 
 ; the software package with which this file was provided.

diff --git a/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter.h b/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter.h
index 4d9d0a2dea45b48230e8e70992834191cc8a85ed..cc0e752816a81ddf6db8102a04f37f525744430c 100755 (executable)
--- a/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter.h
+++ b/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter.h
@@ -1,8 +1,52 @@
+/*******************************************************************************
+* File Name: cyfitter.h
+* 
+* PSoC Creator  4.1
+*
+* Description:
+* 
+* This file is automatically generated by PSoC Creator.
+*
+********************************************************************************
+* Copyright (c) 2007-2017 Cypress Semiconductor.  All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions, 
+* disclaimers, and limitations in the end user license agreement accompanying 
+* the software package with which this file was provided.
+********************************************************************************/
+
 #ifndef INCLUDED_CYFITTER_H
 #define INCLUDED_CYFITTER_H
 #include "cydevice.h"
 #include "cydevice_trm.h"
 
+/* Debug_Timer_Interrupt */
+#define Debug_Timer_Interrupt__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
+#define Debug_Timer_Interrupt__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
+#define Debug_Timer_Interrupt__INTC_MASK 0x01u
+#define Debug_Timer_Interrupt__INTC_NUMBER 0u
+#define Debug_Timer_Interrupt__INTC_PRIOR_NUM 7u
+#define Debug_Timer_Interrupt__INTC_PRIOR_REG CYREG_NVIC_PRI_0
+#define Debug_Timer_Interrupt__INTC_SET_EN_REG CYREG_NVIC_SETENA0
+#define Debug_Timer_Interrupt__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
+
+/* Debug_Timer_TimerHW */
+#define Debug_Timer_TimerHW__CAP0 CYREG_TMR0_CAP0
+#define Debug_Timer_TimerHW__CAP1 CYREG_TMR0_CAP1
+#define Debug_Timer_TimerHW__CFG0 CYREG_TMR0_CFG0
+#define Debug_Timer_TimerHW__CFG1 CYREG_TMR0_CFG1
+#define Debug_Timer_TimerHW__CFG2 CYREG_TMR0_CFG2
+#define Debug_Timer_TimerHW__CNT_CMP0 CYREG_TMR0_CNT_CMP0
+#define Debug_Timer_TimerHW__CNT_CMP1 CYREG_TMR0_CNT_CMP1
+#define Debug_Timer_TimerHW__PER0 CYREG_TMR0_PER0
+#define Debug_Timer_TimerHW__PER1 CYREG_TMR0_PER1
+#define Debug_Timer_TimerHW__PM_ACT_CFG CYREG_PM_ACT_CFG3
+#define Debug_Timer_TimerHW__PM_ACT_MSK 0x01u
+#define Debug_Timer_TimerHW__PM_STBY_CFG CYREG_PM_STBY_CFG3
+#define Debug_Timer_TimerHW__PM_STBY_MSK 0x01u
+#define Debug_Timer_TimerHW__RT0 CYREG_TMR0_RT0
+#define Debug_Timer_TimerHW__RT1 CYREG_TMR0_RT1
+#define Debug_Timer_TimerHW__SR0 CYREG_TMR0_SR0
+
 /* LED1 */
 #define LED1__0__INTTYPE CYREG_PICU12_INTTYPE0
 #define LED1__0__MASK 0x01u
@@ -41,2036 +85,571 @@
 #define LED1__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ
 #define LED1__SLW CYREG_PRT12_SLW
 
-/* SD_CS */
-#define SD_CS__0__INTTYPE CYREG_PICU3_INTTYPE5
-#define SD_CS__0__MASK 0x20u
-#define SD_CS__0__PC CYREG_PRT3_PC5
-#define SD_CS__0__PORT 3u
-#define SD_CS__0__SHIFT 5u
-#define SD_CS__AG CYREG_PRT3_AG
-#define SD_CS__AMUX CYREG_PRT3_AMUX
-#define SD_CS__BIE CYREG_PRT3_BIE
-#define SD_CS__BIT_MASK CYREG_PRT3_BIT_MASK
-#define SD_CS__BYP CYREG_PRT3_BYP
-#define SD_CS__CTL CYREG_PRT3_CTL
-#define SD_CS__DM0 CYREG_PRT3_DM0
-#define SD_CS__DM1 CYREG_PRT3_DM1
-#define SD_CS__DM2 CYREG_PRT3_DM2
-#define SD_CS__DR CYREG_PRT3_DR
-#define SD_CS__INP_DIS CYREG_PRT3_INP_DIS
-#define SD_CS__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU3_BASE
-#define SD_CS__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG
-#define SD_CS__LCD_EN CYREG_PRT3_LCD_EN
-#define SD_CS__MASK 0x20u
-#define SD_CS__PORT 3u
-#define SD_CS__PRT CYREG_PRT3_PRT
-#define SD_CS__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL
-#define SD_CS__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN
-#define SD_CS__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0
-#define SD_CS__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1
-#define SD_CS__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0
-#define SD_CS__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1
-#define SD_CS__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT
-#define SD_CS__PS CYREG_PRT3_PS
-#define SD_CS__SHIFT 5u
-#define SD_CS__SLW CYREG_PRT3_SLW
-
-/* USBFS_arb_int */
-#define USBFS_arb_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
-#define USBFS_arb_int__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
-#define USBFS_arb_int__INTC_MASK 0x400000u
-#define USBFS_arb_int__INTC_NUMBER 22u
-#define USBFS_arb_int__INTC_PRIOR_NUM 6u
-#define USBFS_arb_int__INTC_PRIOR_REG CYREG_NVIC_PRI_22
-#define USBFS_arb_int__INTC_SET_EN_REG CYREG_NVIC_SETENA0
-#define USBFS_arb_int__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
-
-/* USBFS_bus_reset */
-#define USBFS_bus_reset__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
-#define USBFS_bus_reset__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
-#define USBFS_bus_reset__INTC_MASK 0x800000u
-#define USBFS_bus_reset__INTC_NUMBER 23u
-#define USBFS_bus_reset__INTC_PRIOR_NUM 7u
-#define USBFS_bus_reset__INTC_PRIOR_REG CYREG_NVIC_PRI_23
-#define USBFS_bus_reset__INTC_SET_EN_REG CYREG_NVIC_SETENA0
-#define USBFS_bus_reset__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
-
-/* USBFS_Dm */
-#define USBFS_Dm__0__INTTYPE CYREG_PICU15_INTTYPE7
-#define USBFS_Dm__0__MASK 0x80u
-#define USBFS_Dm__0__PC CYREG_IO_PC_PRT15_7_6_PC1
-#define USBFS_Dm__0__PORT 15u
-#define USBFS_Dm__0__SHIFT 7u
-#define USBFS_Dm__AG CYREG_PRT15_AG
-#define USBFS_Dm__AMUX CYREG_PRT15_AMUX
-#define USBFS_Dm__BIE CYREG_PRT15_BIE
-#define USBFS_Dm__BIT_MASK CYREG_PRT15_BIT_MASK
-#define USBFS_Dm__BYP CYREG_PRT15_BYP
-#define USBFS_Dm__CTL CYREG_PRT15_CTL
-#define USBFS_Dm__DM0 CYREG_PRT15_DM0
-#define USBFS_Dm__DM1 CYREG_PRT15_DM1
-#define USBFS_Dm__DM2 CYREG_PRT15_DM2
-#define USBFS_Dm__DR CYREG_PRT15_DR
-#define USBFS_Dm__INP_DIS CYREG_PRT15_INP_DIS
-#define USBFS_Dm__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU15_BASE
-#define USBFS_Dm__LCD_COM_SEG CYREG_PRT15_LCD_COM_SEG
-#define USBFS_Dm__LCD_EN CYREG_PRT15_LCD_EN
-#define USBFS_Dm__MASK 0x80u
-#define USBFS_Dm__PORT 15u
-#define USBFS_Dm__PRT CYREG_PRT15_PRT
-#define USBFS_Dm__PRTDSI__CAPS_SEL CYREG_PRT15_CAPS_SEL
-#define USBFS_Dm__PRTDSI__DBL_SYNC_IN CYREG_PRT15_DBL_SYNC_IN
-#define USBFS_Dm__PRTDSI__OE_SEL0 CYREG_PRT15_OE_SEL0
-#define USBFS_Dm__PRTDSI__OE_SEL1 CYREG_PRT15_OE_SEL1
-#define USBFS_Dm__PRTDSI__OUT_SEL0 CYREG_PRT15_OUT_SEL0
-#define USBFS_Dm__PRTDSI__OUT_SEL1 CYREG_PRT15_OUT_SEL1
-#define USBFS_Dm__PRTDSI__SYNC_OUT CYREG_PRT15_SYNC_OUT
-#define USBFS_Dm__PS CYREG_PRT15_PS
-#define USBFS_Dm__SHIFT 7u
-#define USBFS_Dm__SLW CYREG_PRT15_SLW
-
-/* USBFS_Dp */
-#define USBFS_Dp__0__INTTYPE CYREG_PICU15_INTTYPE6
-#define USBFS_Dp__0__MASK 0x40u
-#define USBFS_Dp__0__PC CYREG_IO_PC_PRT15_7_6_PC0
-#define USBFS_Dp__0__PORT 15u
-#define USBFS_Dp__0__SHIFT 6u
-#define USBFS_Dp__AG CYREG_PRT15_AG
-#define USBFS_Dp__AMUX CYREG_PRT15_AMUX
-#define USBFS_Dp__BIE CYREG_PRT15_BIE
-#define USBFS_Dp__BIT_MASK CYREG_PRT15_BIT_MASK
-#define USBFS_Dp__BYP CYREG_PRT15_BYP
-#define USBFS_Dp__CTL CYREG_PRT15_CTL
-#define USBFS_Dp__DM0 CYREG_PRT15_DM0
-#define USBFS_Dp__DM1 CYREG_PRT15_DM1
-#define USBFS_Dp__DM2 CYREG_PRT15_DM2
-#define USBFS_Dp__DR CYREG_PRT15_DR
-#define USBFS_Dp__INP_DIS CYREG_PRT15_INP_DIS
-#define USBFS_Dp__INTSTAT CYREG_PICU15_INTSTAT
-#define USBFS_Dp__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU15_BASE
-#define USBFS_Dp__LCD_COM_SEG CYREG_PRT15_LCD_COM_SEG
-#define USBFS_Dp__LCD_EN CYREG_PRT15_LCD_EN
-#define USBFS_Dp__MASK 0x40u
-#define USBFS_Dp__PORT 15u
-#define USBFS_Dp__PRT CYREG_PRT15_PRT
-#define USBFS_Dp__PRTDSI__CAPS_SEL CYREG_PRT15_CAPS_SEL
-#define USBFS_Dp__PRTDSI__DBL_SYNC_IN CYREG_PRT15_DBL_SYNC_IN
-#define USBFS_Dp__PRTDSI__OE_SEL0 CYREG_PRT15_OE_SEL0
-#define USBFS_Dp__PRTDSI__OE_SEL1 CYREG_PRT15_OE_SEL1
-#define USBFS_Dp__PRTDSI__OUT_SEL0 CYREG_PRT15_OUT_SEL0
-#define USBFS_Dp__PRTDSI__OUT_SEL1 CYREG_PRT15_OUT_SEL1
-#define USBFS_Dp__PRTDSI__SYNC_OUT CYREG_PRT15_SYNC_OUT
-#define USBFS_Dp__PS CYREG_PRT15_PS
-#define USBFS_Dp__SHIFT 6u
-#define USBFS_Dp__SLW CYREG_PRT15_SLW
-#define USBFS_Dp__SNAP CYREG_PICU_15_SNAP_15
-
-/* USBFS_dp_int */
-#define USBFS_dp_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
-#define USBFS_dp_int__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
-#define USBFS_dp_int__INTC_MASK 0x1000u
-#define USBFS_dp_int__INTC_NUMBER 12u
-#define USBFS_dp_int__INTC_PRIOR_NUM 7u
-#define USBFS_dp_int__INTC_PRIOR_REG CYREG_NVIC_PRI_12
-#define USBFS_dp_int__INTC_SET_EN_REG CYREG_NVIC_SETENA0
-#define USBFS_dp_int__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
+/* SCSI_CLK */
+#define SCSI_CLK__CFG0 CYREG_CLKDIST_DCFG1_CFG0
+#define SCSI_CLK__CFG1 CYREG_CLKDIST_DCFG1_CFG1
+#define SCSI_CLK__CFG2 CYREG_CLKDIST_DCFG1_CFG2
+#define SCSI_CLK__CFG2_SRC_SEL_MASK 0x07u
+#define SCSI_CLK__INDEX 0x01u
+#define SCSI_CLK__PM_ACT_CFG CYREG_PM_ACT_CFG2
+#define SCSI_CLK__PM_ACT_MSK 0x02u
+#define SCSI_CLK__PM_STBY_CFG CYREG_PM_STBY_CFG2
+#define SCSI_CLK__PM_STBY_MSK 0x02u
 
-/* USBFS_ep_0 */
-#define USBFS_ep_0__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
-#define USBFS_ep_0__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
-#define USBFS_ep_0__INTC_MASK 0x1000000u
-#define USBFS_ep_0__INTC_NUMBER 24u
-#define USBFS_ep_0__INTC_PRIOR_NUM 7u
-#define USBFS_ep_0__INTC_PRIOR_REG CYREG_NVIC_PRI_24
-#define USBFS_ep_0__INTC_SET_EN_REG CYREG_NVIC_SETENA0
-#define USBFS_ep_0__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
+/* SCSI_CTL_PHASE */
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK 0x01u
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS 0
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK 0x02u
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS 1
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB02_03_ACTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB02_03_CTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB02_03_CTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB02_03_CTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB02_03_CTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB02_03_MSK
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB02_03_MSK
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB02_03_MSK
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB02_03_MSK
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK 0x04u
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS 2
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB02_ACTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB02_CTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB02_ST_CTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB02_CTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB02_ST_CTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK 0x07u
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB02_MSK_ACTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB02_MSK_ACTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB02_MSK
 
-/* USBFS_ep_1 */
-#define USBFS_ep_1__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
-#define USBFS_ep_1__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
-#define USBFS_ep_1__INTC_MASK 0x80u
-#define USBFS_ep_1__INTC_NUMBER 7u
-#define USBFS_ep_1__INTC_PRIOR_NUM 7u
-#define USBFS_ep_1__INTC_PRIOR_REG CYREG_NVIC_PRI_7
-#define USBFS_ep_1__INTC_SET_EN_REG CYREG_NVIC_SETENA0
-#define USBFS_ep_1__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
+/* SCSI_Filtered */
+#define SCSI_Filtered_sts_sts_reg__0__MASK 0x01u
+#define SCSI_Filtered_sts_sts_reg__0__POS 0
+#define SCSI_Filtered_sts_sts_reg__1__MASK 0x02u
+#define SCSI_Filtered_sts_sts_reg__1__POS 1
+#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB11_12_ACTL
+#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB11_12_ST
+#define SCSI_Filtered_sts_sts_reg__2__MASK 0x04u
+#define SCSI_Filtered_sts_sts_reg__2__POS 2
+#define SCSI_Filtered_sts_sts_reg__3__MASK 0x08u
+#define SCSI_Filtered_sts_sts_reg__3__POS 3
+#define SCSI_Filtered_sts_sts_reg__4__MASK 0x10u
+#define SCSI_Filtered_sts_sts_reg__4__POS 4
+#define SCSI_Filtered_sts_sts_reg__MASK 0x1Fu
+#define SCSI_Filtered_sts_sts_reg__MASK_REG CYREG_B0_UDB11_MSK
+#define SCSI_Filtered_sts_sts_reg__MASK_ST_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL
+#define SCSI_Filtered_sts_sts_reg__PER_ST_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL
+#define SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB11_ACTL
+#define SCSI_Filtered_sts_sts_reg__STATUS_CNT_REG CYREG_B0_UDB11_ST_CTL
+#define SCSI_Filtered_sts_sts_reg__STATUS_CONTROL_REG CYREG_B0_UDB11_ST_CTL
+#define SCSI_Filtered_sts_sts_reg__STATUS_REG CYREG_B0_UDB11_ST
 
-/* USBFS_ep_2 */
-#define USBFS_ep_2__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
-#define USBFS_ep_2__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
-#define USBFS_ep_2__INTC_MASK 0x100u
-#define USBFS_ep_2__INTC_NUMBER 8u
-#define USBFS_ep_2__INTC_PRIOR_NUM 7u
-#define USBFS_ep_2__INTC_PRIOR_REG CYREG_NVIC_PRI_8
-#define USBFS_ep_2__INTC_SET_EN_REG CYREG_NVIC_SETENA0
-#define USBFS_ep_2__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
+/* SCSI_Glitch_Ctl */
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK 0x01u
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS 0
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB05_06_ACTL
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB05_06_CTL
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB05_06_CTL
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB05_06_CTL
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB05_06_CTL
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB05_06_MSK
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB05_06_MSK
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB05_06_MSK
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB05_06_MSK
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB05_ACTL
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB05_CTL
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB05_ST_CTL
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB05_CTL
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB05_ST_CTL
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK 0x01u
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB05_MSK
 
-/* USBFS_ep_3 */
-#define USBFS_ep_3__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
-#define USBFS_ep_3__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
-#define USBFS_ep_3__INTC_MASK 0x200u
-#define USBFS_ep_3__INTC_NUMBER 9u
-#define USBFS_ep_3__INTC_PRIOR_NUM 7u
-#define USBFS_ep_3__INTC_PRIOR_REG CYREG_NVIC_PRI_9
-#define USBFS_ep_3__INTC_SET_EN_REG CYREG_NVIC_SETENA0
-#define USBFS_ep_3__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
-
-/* USBFS_ep_4 */
-#define USBFS_ep_4__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
-#define USBFS_ep_4__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
-#define USBFS_ep_4__INTC_MASK 0x400u
-#define USBFS_ep_4__INTC_NUMBER 10u
-#define USBFS_ep_4__INTC_PRIOR_NUM 7u
-#define USBFS_ep_4__INTC_PRIOR_REG CYREG_NVIC_PRI_10
-#define USBFS_ep_4__INTC_SET_EN_REG CYREG_NVIC_SETENA0
-#define USBFS_ep_4__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
-
-/* USBFS_sof_int */
-#define USBFS_sof_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
-#define USBFS_sof_int__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
-#define USBFS_sof_int__INTC_MASK 0x200000u
-#define USBFS_sof_int__INTC_NUMBER 21u
-#define USBFS_sof_int__INTC_PRIOR_NUM 7u
-#define USBFS_sof_int__INTC_PRIOR_REG CYREG_NVIC_PRI_21
-#define USBFS_sof_int__INTC_SET_EN_REG CYREG_NVIC_SETENA0
-#define USBFS_sof_int__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
-
-/* USBFS_USB */
-#define USBFS_USB__ARB_CFG CYREG_USB_ARB_CFG
-#define USBFS_USB__ARB_EP1_CFG CYREG_USB_ARB_EP1_CFG
-#define USBFS_USB__ARB_EP1_INT_EN CYREG_USB_ARB_EP1_INT_EN
-#define USBFS_USB__ARB_EP1_SR CYREG_USB_ARB_EP1_SR
-#define USBFS_USB__ARB_EP2_CFG CYREG_USB_ARB_EP2_CFG
-#define USBFS_USB__ARB_EP2_INT_EN CYREG_USB_ARB_EP2_INT_EN
-#define USBFS_USB__ARB_EP2_SR CYREG_USB_ARB_EP2_SR
-#define USBFS_USB__ARB_EP3_CFG CYREG_USB_ARB_EP3_CFG
-#define USBFS_USB__ARB_EP3_INT_EN CYREG_USB_ARB_EP3_INT_EN
-#define USBFS_USB__ARB_EP3_SR CYREG_USB_ARB_EP3_SR
-#define USBFS_USB__ARB_EP4_CFG CYREG_USB_ARB_EP4_CFG
-#define USBFS_USB__ARB_EP4_INT_EN CYREG_USB_ARB_EP4_INT_EN
-#define USBFS_USB__ARB_EP4_SR CYREG_USB_ARB_EP4_SR
-#define USBFS_USB__ARB_EP5_CFG CYREG_USB_ARB_EP5_CFG
-#define USBFS_USB__ARB_EP5_INT_EN CYREG_USB_ARB_EP5_INT_EN
-#define USBFS_USB__ARB_EP5_SR CYREG_USB_ARB_EP5_SR
-#define USBFS_USB__ARB_EP6_CFG CYREG_USB_ARB_EP6_CFG
-#define USBFS_USB__ARB_EP6_INT_EN CYREG_USB_ARB_EP6_INT_EN
-#define USBFS_USB__ARB_EP6_SR CYREG_USB_ARB_EP6_SR
-#define USBFS_USB__ARB_EP7_CFG CYREG_USB_ARB_EP7_CFG
-#define USBFS_USB__ARB_EP7_INT_EN CYREG_USB_ARB_EP7_INT_EN
-#define USBFS_USB__ARB_EP7_SR CYREG_USB_ARB_EP7_SR
-#define USBFS_USB__ARB_EP8_CFG CYREG_USB_ARB_EP8_CFG
-#define USBFS_USB__ARB_EP8_INT_EN CYREG_USB_ARB_EP8_INT_EN
-#define USBFS_USB__ARB_EP8_SR CYREG_USB_ARB_EP8_SR
-#define USBFS_USB__ARB_INT_EN CYREG_USB_ARB_INT_EN
-#define USBFS_USB__ARB_INT_SR CYREG_USB_ARB_INT_SR
-#define USBFS_USB__ARB_RW1_DR CYREG_USB_ARB_RW1_DR
-#define USBFS_USB__ARB_RW1_RA CYREG_USB_ARB_RW1_RA
-#define USBFS_USB__ARB_RW1_RA_MSB CYREG_USB_ARB_RW1_RA_MSB
-#define USBFS_USB__ARB_RW1_WA CYREG_USB_ARB_RW1_WA
-#define USBFS_USB__ARB_RW1_WA_MSB CYREG_USB_ARB_RW1_WA_MSB
-#define USBFS_USB__ARB_RW2_DR CYREG_USB_ARB_RW2_DR
-#define USBFS_USB__ARB_RW2_RA CYREG_USB_ARB_RW2_RA
-#define USBFS_USB__ARB_RW2_RA_MSB CYREG_USB_ARB_RW2_RA_MSB
-#define USBFS_USB__ARB_RW2_WA CYREG_USB_ARB_RW2_WA
-#define USBFS_USB__ARB_RW2_WA_MSB CYREG_USB_ARB_RW2_WA_MSB
-#define USBFS_USB__ARB_RW3_DR CYREG_USB_ARB_RW3_DR
-#define USBFS_USB__ARB_RW3_RA CYREG_USB_ARB_RW3_RA
-#define USBFS_USB__ARB_RW3_RA_MSB CYREG_USB_ARB_RW3_RA_MSB
-#define USBFS_USB__ARB_RW3_WA CYREG_USB_ARB_RW3_WA
-#define USBFS_USB__ARB_RW3_WA_MSB CYREG_USB_ARB_RW3_WA_MSB
-#define USBFS_USB__ARB_RW4_DR CYREG_USB_ARB_RW4_DR
-#define USBFS_USB__ARB_RW4_RA CYREG_USB_ARB_RW4_RA
-#define USBFS_USB__ARB_RW4_RA_MSB CYREG_USB_ARB_RW4_RA_MSB
-#define USBFS_USB__ARB_RW4_WA CYREG_USB_ARB_RW4_WA
-#define USBFS_USB__ARB_RW4_WA_MSB CYREG_USB_ARB_RW4_WA_MSB
-#define USBFS_USB__ARB_RW5_DR CYREG_USB_ARB_RW5_DR
-#define USBFS_USB__ARB_RW5_RA CYREG_USB_ARB_RW5_RA
-#define USBFS_USB__ARB_RW5_RA_MSB CYREG_USB_ARB_RW5_RA_MSB
-#define USBFS_USB__ARB_RW5_WA CYREG_USB_ARB_RW5_WA
-#define USBFS_USB__ARB_RW5_WA_MSB CYREG_USB_ARB_RW5_WA_MSB
-#define USBFS_USB__ARB_RW6_DR CYREG_USB_ARB_RW6_DR
-#define USBFS_USB__ARB_RW6_RA CYREG_USB_ARB_RW6_RA
-#define USBFS_USB__ARB_RW6_RA_MSB CYREG_USB_ARB_RW6_RA_MSB
-#define USBFS_USB__ARB_RW6_WA CYREG_USB_ARB_RW6_WA
-#define USBFS_USB__ARB_RW6_WA_MSB CYREG_USB_ARB_RW6_WA_MSB
-#define USBFS_USB__ARB_RW7_DR CYREG_USB_ARB_RW7_DR
-#define USBFS_USB__ARB_RW7_RA CYREG_USB_ARB_RW7_RA
-#define USBFS_USB__ARB_RW7_RA_MSB CYREG_USB_ARB_RW7_RA_MSB
-#define USBFS_USB__ARB_RW7_WA CYREG_USB_ARB_RW7_WA
-#define USBFS_USB__ARB_RW7_WA_MSB CYREG_USB_ARB_RW7_WA_MSB
-#define USBFS_USB__ARB_RW8_DR CYREG_USB_ARB_RW8_DR
-#define USBFS_USB__ARB_RW8_RA CYREG_USB_ARB_RW8_RA
-#define USBFS_USB__ARB_RW8_RA_MSB CYREG_USB_ARB_RW8_RA_MSB
-#define USBFS_USB__ARB_RW8_WA CYREG_USB_ARB_RW8_WA
-#define USBFS_USB__ARB_RW8_WA_MSB CYREG_USB_ARB_RW8_WA_MSB
-#define USBFS_USB__BUF_SIZE CYREG_USB_BUF_SIZE
-#define USBFS_USB__BUS_RST_CNT CYREG_USB_BUS_RST_CNT
-#define USBFS_USB__CR0 CYREG_USB_CR0
-#define USBFS_USB__CR1 CYREG_USB_CR1
-#define USBFS_USB__CWA CYREG_USB_CWA
-#define USBFS_USB__CWA_MSB CYREG_USB_CWA_MSB
-#define USBFS_USB__DMA_THRES CYREG_USB_DMA_THRES
-#define USBFS_USB__DMA_THRES_MSB CYREG_USB_DMA_THRES_MSB
-#define USBFS_USB__DYN_RECONFIG CYREG_USB_DYN_RECONFIG
-#define USBFS_USB__EP_ACTIVE CYREG_USB_EP_ACTIVE
-#define USBFS_USB__EP_TYPE CYREG_USB_EP_TYPE
-#define USBFS_USB__EP0_CNT CYREG_USB_EP0_CNT
-#define USBFS_USB__EP0_CR CYREG_USB_EP0_CR
-#define USBFS_USB__EP0_DR0 CYREG_USB_EP0_DR0
-#define USBFS_USB__EP0_DR1 CYREG_USB_EP0_DR1
-#define USBFS_USB__EP0_DR2 CYREG_USB_EP0_DR2
-#define USBFS_USB__EP0_DR3 CYREG_USB_EP0_DR3
-#define USBFS_USB__EP0_DR4 CYREG_USB_EP0_DR4
-#define USBFS_USB__EP0_DR5 CYREG_USB_EP0_DR5
-#define USBFS_USB__EP0_DR6 CYREG_USB_EP0_DR6
-#define USBFS_USB__EP0_DR7 CYREG_USB_EP0_DR7
-#define USBFS_USB__MEM_DATA CYREG_USB_MEM_DATA_MBASE
-#define USBFS_USB__PM_ACT_CFG CYREG_PM_ACT_CFG5
-#define USBFS_USB__PM_ACT_MSK 0x01u
-#define USBFS_USB__PM_STBY_CFG CYREG_PM_STBY_CFG5
-#define USBFS_USB__PM_STBY_MSK 0x01u
-#define USBFS_USB__SIE_EP_INT_EN CYREG_USB_SIE_EP_INT_EN
-#define USBFS_USB__SIE_EP_INT_SR CYREG_USB_SIE_EP_INT_SR
-#define USBFS_USB__SIE_EP1_CNT0 CYREG_USB_SIE_EP1_CNT0
-#define USBFS_USB__SIE_EP1_CNT1 CYREG_USB_SIE_EP1_CNT1
-#define USBFS_USB__SIE_EP1_CR0 CYREG_USB_SIE_EP1_CR0
-#define USBFS_USB__SIE_EP2_CNT0 CYREG_USB_SIE_EP2_CNT0
-#define USBFS_USB__SIE_EP2_CNT1 CYREG_USB_SIE_EP2_CNT1
-#define USBFS_USB__SIE_EP2_CR0 CYREG_USB_SIE_EP2_CR0
-#define USBFS_USB__SIE_EP3_CNT0 CYREG_USB_SIE_EP3_CNT0
-#define USBFS_USB__SIE_EP3_CNT1 CYREG_USB_SIE_EP3_CNT1
-#define USBFS_USB__SIE_EP3_CR0 CYREG_USB_SIE_EP3_CR0
-#define USBFS_USB__SIE_EP4_CNT0 CYREG_USB_SIE_EP4_CNT0
-#define USBFS_USB__SIE_EP4_CNT1 CYREG_USB_SIE_EP4_CNT1
-#define USBFS_USB__SIE_EP4_CR0 CYREG_USB_SIE_EP4_CR0
-#define USBFS_USB__SIE_EP5_CNT0 CYREG_USB_SIE_EP5_CNT0
-#define USBFS_USB__SIE_EP5_CNT1 CYREG_USB_SIE_EP5_CNT1
-#define USBFS_USB__SIE_EP5_CR0 CYREG_USB_SIE_EP5_CR0
-#define USBFS_USB__SIE_EP6_CNT0 CYREG_USB_SIE_EP6_CNT0
-#define USBFS_USB__SIE_EP6_CNT1 CYREG_USB_SIE_EP6_CNT1
-#define USBFS_USB__SIE_EP6_CR0 CYREG_USB_SIE_EP6_CR0
-#define USBFS_USB__SIE_EP7_CNT0 CYREG_USB_SIE_EP7_CNT0
-#define USBFS_USB__SIE_EP7_CNT1 CYREG_USB_SIE_EP7_CNT1
-#define USBFS_USB__SIE_EP7_CR0 CYREG_USB_SIE_EP7_CR0
-#define USBFS_USB__SIE_EP8_CNT0 CYREG_USB_SIE_EP8_CNT0
-#define USBFS_USB__SIE_EP8_CNT1 CYREG_USB_SIE_EP8_CNT1
-#define USBFS_USB__SIE_EP8_CR0 CYREG_USB_SIE_EP8_CR0
-#define USBFS_USB__SOF0 CYREG_USB_SOF0
-#define USBFS_USB__SOF1 CYREG_USB_SOF1
-#define USBFS_USB__USB_CLK_EN CYREG_USB_USB_CLK_EN
-#define USBFS_USB__USBIO_CR0 CYREG_USB_USBIO_CR0
-#define USBFS_USB__USBIO_CR1 CYREG_USB_USBIO_CR1
-
-/* SDCard_BSPIM */
-#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB04_05_ACTL
-#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB04_05_CTL
-#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB04_05_CTL
-#define SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB04_05_CTL
-#define SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B1_UDB04_05_CTL
-#define SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B1_UDB04_05_MSK
-#define SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B1_UDB04_05_MSK
-#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B1_UDB04_05_MSK
-#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB04_05_MSK
-#define SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B1_UDB04_ACTL
-#define SDCard_BSPIM_BitCounter__CONTROL_REG CYREG_B1_UDB04_CTL
-#define SDCard_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B1_UDB04_ST_CTL
-#define SDCard_BSPIM_BitCounter__COUNT_REG CYREG_B1_UDB04_CTL
-#define SDCard_BSPIM_BitCounter__COUNT_ST_REG CYREG_B1_UDB04_ST_CTL
-#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL
-#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL
-#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B1_UDB04_MSK
-#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB04_05_ACTL
-#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B1_UDB04_05_ST
-#define SDCard_BSPIM_BitCounter_ST__MASK_REG CYREG_B1_UDB04_MSK
-#define SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL
-#define SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL
-#define SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B1_UDB04_ACTL
-#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B1_UDB04_ST_CTL
-#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B1_UDB04_ST_CTL
-#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B1_UDB04_ST
-#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB07_08_ACTL
-#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B0_UDB07_08_ST
-#define SDCard_BSPIM_RxStsReg__4__MASK 0x10u
-#define SDCard_BSPIM_RxStsReg__4__POS 4
-#define SDCard_BSPIM_RxStsReg__5__MASK 0x20u
-#define SDCard_BSPIM_RxStsReg__5__POS 5
-#define SDCard_BSPIM_RxStsReg__6__MASK 0x40u
-#define SDCard_BSPIM_RxStsReg__6__POS 6
-#define SDCard_BSPIM_RxStsReg__MASK 0x70u
-#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B0_UDB07_MSK
-#define SDCard_BSPIM_RxStsReg__MASK_ST_AUX_CTL_REG CYREG_B0_UDB07_MSK_ACTL
-#define SDCard_BSPIM_RxStsReg__PER_ST_AUX_CTL_REG CYREG_B0_UDB07_MSK_ACTL
-#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB07_ACTL
-#define SDCard_BSPIM_RxStsReg__STATUS_CNT_REG CYREG_B0_UDB07_ST_CTL
-#define SDCard_BSPIM_RxStsReg__STATUS_CONTROL_REG CYREG_B0_UDB07_ST_CTL
-#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B0_UDB07_ST
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B1_UDB04_05_A0
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B1_UDB04_05_A1
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG CYREG_B1_UDB04_05_D0
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG CYREG_B1_UDB04_05_D1
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG CYREG_B1_UDB04_05_ACTL
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG CYREG_B1_UDB04_05_F0
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG CYREG_B1_UDB04_05_F1
-#define SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG CYREG_B1_UDB04_A0_A1
-#define SDCard_BSPIM_sR8_Dp_u0__A0_REG CYREG_B1_UDB04_A0
-#define SDCard_BSPIM_sR8_Dp_u0__A1_REG CYREG_B1_UDB04_A1
-#define SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG CYREG_B1_UDB04_D0_D1
-#define SDCard_BSPIM_sR8_Dp_u0__D0_REG CYREG_B1_UDB04_D0
-#define SDCard_BSPIM_sR8_Dp_u0__D1_REG CYREG_B1_UDB04_D1
-#define SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG CYREG_B1_UDB04_ACTL
-#define SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG CYREG_B1_UDB04_F0_F1
-#define SDCard_BSPIM_sR8_Dp_u0__F0_REG CYREG_B1_UDB04_F0
-#define SDCard_BSPIM_sR8_Dp_u0__F1_REG CYREG_B1_UDB04_F1
-#define SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL
-#define SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL
-#define SDCard_BSPIM_TxStsReg__0__MASK 0x01u
-#define SDCard_BSPIM_TxStsReg__0__POS 0
-#define SDCard_BSPIM_TxStsReg__1__MASK 0x02u
-#define SDCard_BSPIM_TxStsReg__1__POS 1
-#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB07_08_ACTL
-#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B1_UDB07_08_ST
-#define SDCard_BSPIM_TxStsReg__2__MASK 0x04u
-#define SDCard_BSPIM_TxStsReg__2__POS 2
-#define SDCard_BSPIM_TxStsReg__3__MASK 0x08u
-#define SDCard_BSPIM_TxStsReg__3__POS 3
-#define SDCard_BSPIM_TxStsReg__4__MASK 0x10u
-#define SDCard_BSPIM_TxStsReg__4__POS 4
-#define SDCard_BSPIM_TxStsReg__MASK 0x1Fu
-#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B1_UDB07_MSK
-#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB07_ACTL
-#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B1_UDB07_ST
-
-/* SD_SCK */
-#define SD_SCK__0__INTTYPE CYREG_PICU3_INTTYPE3
-#define SD_SCK__0__MASK 0x08u
-#define SD_SCK__0__PC CYREG_PRT3_PC3
-#define SD_SCK__0__PORT 3u
-#define SD_SCK__0__SHIFT 3u
-#define SD_SCK__AG CYREG_PRT3_AG
-#define SD_SCK__AMUX CYREG_PRT3_AMUX
-#define SD_SCK__BIE CYREG_PRT3_BIE
-#define SD_SCK__BIT_MASK CYREG_PRT3_BIT_MASK
-#define SD_SCK__BYP CYREG_PRT3_BYP
-#define SD_SCK__CTL CYREG_PRT3_CTL
-#define SD_SCK__DM0 CYREG_PRT3_DM0
-#define SD_SCK__DM1 CYREG_PRT3_DM1
-#define SD_SCK__DM2 CYREG_PRT3_DM2
-#define SD_SCK__DR CYREG_PRT3_DR
-#define SD_SCK__INP_DIS CYREG_PRT3_INP_DIS
-#define SD_SCK__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU3_BASE
-#define SD_SCK__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG
-#define SD_SCK__LCD_EN CYREG_PRT3_LCD_EN
-#define SD_SCK__MASK 0x08u
-#define SD_SCK__PORT 3u
-#define SD_SCK__PRT CYREG_PRT3_PRT
-#define SD_SCK__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL
-#define SD_SCK__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN
-#define SD_SCK__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0
-#define SD_SCK__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1
-#define SD_SCK__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0
-#define SD_SCK__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1
-#define SD_SCK__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT
-#define SD_SCK__PS CYREG_PRT3_PS
-#define SD_SCK__SHIFT 3u
-#define SD_SCK__SLW CYREG_PRT3_SLW
-
-/* SCSI_In */
-#define SCSI_In__0__INTTYPE CYREG_PICU6_INTTYPE1
-#define SCSI_In__0__MASK 0x02u
-#define SCSI_In__0__PC CYREG_PRT6_PC1
-#define SCSI_In__0__PORT 6u
-#define SCSI_In__0__SHIFT 1u
-#define SCSI_In__AG CYREG_PRT6_AG
-#define SCSI_In__AMUX CYREG_PRT6_AMUX
-#define SCSI_In__BIE CYREG_PRT6_BIE
-#define SCSI_In__BIT_MASK CYREG_PRT6_BIT_MASK
-#define SCSI_In__BYP CYREG_PRT6_BYP
-#define SCSI_In__CTL CYREG_PRT6_CTL
-#define SCSI_In__DBP__INTTYPE CYREG_PICU6_INTTYPE1
-#define SCSI_In__DBP__MASK 0x02u
-#define SCSI_In__DBP__PC CYREG_PRT6_PC1
-#define SCSI_In__DBP__PORT 6u
-#define SCSI_In__DBP__SHIFT 1u
-#define SCSI_In__DM0 CYREG_PRT6_DM0
-#define SCSI_In__DM1 CYREG_PRT6_DM1
-#define SCSI_In__DM2 CYREG_PRT6_DM2
-#define SCSI_In__DR CYREG_PRT6_DR
-#define SCSI_In__INP_DIS CYREG_PRT6_INP_DIS
-#define SCSI_In__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU6_BASE
-#define SCSI_In__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
-#define SCSI_In__LCD_EN CYREG_PRT6_LCD_EN
-#define SCSI_In__MASK 0x02u
-#define SCSI_In__PORT 6u
-#define SCSI_In__PRT CYREG_PRT6_PRT
-#define SCSI_In__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
-#define SCSI_In__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
-#define SCSI_In__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
-#define SCSI_In__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
-#define SCSI_In__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
-#define SCSI_In__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
-#define SCSI_In__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
-#define SCSI_In__PS CYREG_PRT6_PS
-#define SCSI_In__SHIFT 1u
-#define SCSI_In__SLW CYREG_PRT6_SLW
-
-/* SCSI_In_DBx */
-#define SCSI_In_DBx__0__AG CYREG_PRT6_AG
-#define SCSI_In_DBx__0__AMUX CYREG_PRT6_AMUX
-#define SCSI_In_DBx__0__BIE CYREG_PRT6_BIE
-#define SCSI_In_DBx__0__BIT_MASK CYREG_PRT6_BIT_MASK
-#define SCSI_In_DBx__0__BYP CYREG_PRT6_BYP
-#define SCSI_In_DBx__0__CTL CYREG_PRT6_CTL
-#define SCSI_In_DBx__0__DM0 CYREG_PRT6_DM0
-#define SCSI_In_DBx__0__DM1 CYREG_PRT6_DM1
-#define SCSI_In_DBx__0__DM2 CYREG_PRT6_DM2
-#define SCSI_In_DBx__0__DR CYREG_PRT6_DR
-#define SCSI_In_DBx__0__INP_DIS CYREG_PRT6_INP_DIS
-#define SCSI_In_DBx__0__INTTYPE CYREG_PICU6_INTTYPE6
-#define SCSI_In_DBx__0__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
-#define SCSI_In_DBx__0__LCD_EN CYREG_PRT6_LCD_EN
-#define SCSI_In_DBx__0__MASK 0x40u
-#define SCSI_In_DBx__0__PC CYREG_PRT6_PC6
-#define SCSI_In_DBx__0__PORT 6u
-#define SCSI_In_DBx__0__PRT CYREG_PRT6_PRT
-#define SCSI_In_DBx__0__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
-#define SCSI_In_DBx__0__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
-#define SCSI_In_DBx__0__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
-#define SCSI_In_DBx__0__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
-#define SCSI_In_DBx__0__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
-#define SCSI_In_DBx__0__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
-#define SCSI_In_DBx__0__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
-#define SCSI_In_DBx__0__PS CYREG_PRT6_PS
-#define SCSI_In_DBx__0__SHIFT 6u
-#define SCSI_In_DBx__0__SLW CYREG_PRT6_SLW
-#define SCSI_In_DBx__1__AG CYREG_PRT6_AG
-#define SCSI_In_DBx__1__AMUX CYREG_PRT6_AMUX
-#define SCSI_In_DBx__1__BIE CYREG_PRT6_BIE
-#define SCSI_In_DBx__1__BIT_MASK CYREG_PRT6_BIT_MASK
-#define SCSI_In_DBx__1__BYP CYREG_PRT6_BYP
-#define SCSI_In_DBx__1__CTL CYREG_PRT6_CTL
-#define SCSI_In_DBx__1__DM0 CYREG_PRT6_DM0
-#define SCSI_In_DBx__1__DM1 CYREG_PRT6_DM1
-#define SCSI_In_DBx__1__DM2 CYREG_PRT6_DM2
-#define SCSI_In_DBx__1__DR CYREG_PRT6_DR
-#define SCSI_In_DBx__1__INP_DIS CYREG_PRT6_INP_DIS
-#define SCSI_In_DBx__1__INTTYPE CYREG_PICU6_INTTYPE4
-#define SCSI_In_DBx__1__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
-#define SCSI_In_DBx__1__LCD_EN CYREG_PRT6_LCD_EN
-#define SCSI_In_DBx__1__MASK 0x10u
-#define SCSI_In_DBx__1__PC CYREG_PRT6_PC4
-#define SCSI_In_DBx__1__PORT 6u
-#define SCSI_In_DBx__1__PRT CYREG_PRT6_PRT
-#define SCSI_In_DBx__1__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
-#define SCSI_In_DBx__1__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
-#define SCSI_In_DBx__1__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
-#define SCSI_In_DBx__1__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
-#define SCSI_In_DBx__1__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
-#define SCSI_In_DBx__1__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
-#define SCSI_In_DBx__1__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
-#define SCSI_In_DBx__1__PS CYREG_PRT6_PS
-#define SCSI_In_DBx__1__SHIFT 4u
-#define SCSI_In_DBx__1__SLW CYREG_PRT6_SLW
-#define SCSI_In_DBx__2__AG CYREG_PRT12_AG
-#define SCSI_In_DBx__2__BIE CYREG_PRT12_BIE
-#define SCSI_In_DBx__2__BIT_MASK CYREG_PRT12_BIT_MASK
-#define SCSI_In_DBx__2__BYP CYREG_PRT12_BYP
-#define SCSI_In_DBx__2__DM0 CYREG_PRT12_DM0
-#define SCSI_In_DBx__2__DM1 CYREG_PRT12_DM1
-#define SCSI_In_DBx__2__DM2 CYREG_PRT12_DM2
-#define SCSI_In_DBx__2__DR CYREG_PRT12_DR
-#define SCSI_In_DBx__2__INP_DIS CYREG_PRT12_INP_DIS
-#define SCSI_In_DBx__2__INTTYPE CYREG_PICU12_INTTYPE4
-#define SCSI_In_DBx__2__MASK 0x10u
-#define SCSI_In_DBx__2__PC CYREG_PRT12_PC4
-#define SCSI_In_DBx__2__PORT 12u
-#define SCSI_In_DBx__2__PRT CYREG_PRT12_PRT
-#define SCSI_In_DBx__2__PRTDSI__DBL_SYNC_IN CYREG_PRT12_DBL_SYNC_IN
-#define SCSI_In_DBx__2__PRTDSI__OE_SEL0 CYREG_PRT12_OE_SEL0
-#define SCSI_In_DBx__2__PRTDSI__OE_SEL1 CYREG_PRT12_OE_SEL1
-#define SCSI_In_DBx__2__PRTDSI__OUT_SEL0 CYREG_PRT12_OUT_SEL0
-#define SCSI_In_DBx__2__PRTDSI__OUT_SEL1 CYREG_PRT12_OUT_SEL1
-#define SCSI_In_DBx__2__PRTDSI__SYNC_OUT CYREG_PRT12_SYNC_OUT
-#define SCSI_In_DBx__2__PS CYREG_PRT12_PS
-#define SCSI_In_DBx__2__SHIFT 4u
-#define SCSI_In_DBx__2__SIO_CFG CYREG_PRT12_SIO_CFG
-#define SCSI_In_DBx__2__SIO_DIFF CYREG_PRT12_SIO_DIFF
-#define SCSI_In_DBx__2__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN
-#define SCSI_In_DBx__2__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ
-#define SCSI_In_DBx__2__SLW CYREG_PRT12_SLW
-#define SCSI_In_DBx__3__AG CYREG_PRT2_AG
-#define SCSI_In_DBx__3__AMUX CYREG_PRT2_AMUX
-#define SCSI_In_DBx__3__BIE CYREG_PRT2_BIE
-#define SCSI_In_DBx__3__BIT_MASK CYREG_PRT2_BIT_MASK
-#define SCSI_In_DBx__3__BYP CYREG_PRT2_BYP
-#define SCSI_In_DBx__3__CTL CYREG_PRT2_CTL
-#define SCSI_In_DBx__3__DM0 CYREG_PRT2_DM0
-#define SCSI_In_DBx__3__DM1 CYREG_PRT2_DM1
-#define SCSI_In_DBx__3__DM2 CYREG_PRT2_DM2
-#define SCSI_In_DBx__3__DR CYREG_PRT2_DR
-#define SCSI_In_DBx__3__INP_DIS CYREG_PRT2_INP_DIS
-#define SCSI_In_DBx__3__INTTYPE CYREG_PICU2_INTTYPE6
-#define SCSI_In_DBx__3__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
-#define SCSI_In_DBx__3__LCD_EN CYREG_PRT2_LCD_EN
-#define SCSI_In_DBx__3__MASK 0x40u
-#define SCSI_In_DBx__3__PC CYREG_PRT2_PC6
-#define SCSI_In_DBx__3__PORT 2u
-#define SCSI_In_DBx__3__PRT CYREG_PRT2_PRT
-#define SCSI_In_DBx__3__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
-#define SCSI_In_DBx__3__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
-#define SCSI_In_DBx__3__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
-#define SCSI_In_DBx__3__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
-#define SCSI_In_DBx__3__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
-#define SCSI_In_DBx__3__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
-#define SCSI_In_DBx__3__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
-#define SCSI_In_DBx__3__PS CYREG_PRT2_PS
-#define SCSI_In_DBx__3__SHIFT 6u
-#define SCSI_In_DBx__3__SLW CYREG_PRT2_SLW
-#define SCSI_In_DBx__4__AG CYREG_PRT2_AG
-#define SCSI_In_DBx__4__AMUX CYREG_PRT2_AMUX
-#define SCSI_In_DBx__4__BIE CYREG_PRT2_BIE
-#define SCSI_In_DBx__4__BIT_MASK CYREG_PRT2_BIT_MASK
-#define SCSI_In_DBx__4__BYP CYREG_PRT2_BYP
-#define SCSI_In_DBx__4__CTL CYREG_PRT2_CTL
-#define SCSI_In_DBx__4__DM0 CYREG_PRT2_DM0
-#define SCSI_In_DBx__4__DM1 CYREG_PRT2_DM1
-#define SCSI_In_DBx__4__DM2 CYREG_PRT2_DM2
-#define SCSI_In_DBx__4__DR CYREG_PRT2_DR
-#define SCSI_In_DBx__4__INP_DIS CYREG_PRT2_INP_DIS
-#define SCSI_In_DBx__4__INTTYPE CYREG_PICU2_INTTYPE4
-#define SCSI_In_DBx__4__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
-#define SCSI_In_DBx__4__LCD_EN CYREG_PRT2_LCD_EN
-#define SCSI_In_DBx__4__MASK 0x10u
-#define SCSI_In_DBx__4__PC CYREG_PRT2_PC4
-#define SCSI_In_DBx__4__PORT 2u
-#define SCSI_In_DBx__4__PRT CYREG_PRT2_PRT
-#define SCSI_In_DBx__4__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
-#define SCSI_In_DBx__4__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
-#define SCSI_In_DBx__4__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
-#define SCSI_In_DBx__4__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
-#define SCSI_In_DBx__4__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
-#define SCSI_In_DBx__4__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
-#define SCSI_In_DBx__4__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
-#define SCSI_In_DBx__4__PS CYREG_PRT2_PS
-#define SCSI_In_DBx__4__SHIFT 4u
-#define SCSI_In_DBx__4__SLW CYREG_PRT2_SLW
-#define SCSI_In_DBx__5__AG CYREG_PRT2_AG
-#define SCSI_In_DBx__5__AMUX CYREG_PRT2_AMUX
-#define SCSI_In_DBx__5__BIE CYREG_PRT2_BIE
-#define SCSI_In_DBx__5__BIT_MASK CYREG_PRT2_BIT_MASK
-#define SCSI_In_DBx__5__BYP CYREG_PRT2_BYP
-#define SCSI_In_DBx__5__CTL CYREG_PRT2_CTL
-#define SCSI_In_DBx__5__DM0 CYREG_PRT2_DM0
-#define SCSI_In_DBx__5__DM1 CYREG_PRT2_DM1
-#define SCSI_In_DBx__5__DM2 CYREG_PRT2_DM2
-#define SCSI_In_DBx__5__DR CYREG_PRT2_DR
-#define SCSI_In_DBx__5__INP_DIS CYREG_PRT2_INP_DIS
-#define SCSI_In_DBx__5__INTTYPE CYREG_PICU2_INTTYPE2
-#define SCSI_In_DBx__5__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
-#define SCSI_In_DBx__5__LCD_EN CYREG_PRT2_LCD_EN
-#define SCSI_In_DBx__5__MASK 0x04u
-#define SCSI_In_DBx__5__PC CYREG_PRT2_PC2
-#define SCSI_In_DBx__5__PORT 2u
-#define SCSI_In_DBx__5__PRT CYREG_PRT2_PRT
-#define SCSI_In_DBx__5__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
-#define SCSI_In_DBx__5__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
-#define SCSI_In_DBx__5__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
-#define SCSI_In_DBx__5__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
-#define SCSI_In_DBx__5__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
-#define SCSI_In_DBx__5__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
-#define SCSI_In_DBx__5__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
-#define SCSI_In_DBx__5__PS CYREG_PRT2_PS
-#define SCSI_In_DBx__5__SHIFT 2u
-#define SCSI_In_DBx__5__SLW CYREG_PRT2_SLW
-#define SCSI_In_DBx__6__AG CYREG_PRT2_AG
-#define SCSI_In_DBx__6__AMUX CYREG_PRT2_AMUX
-#define SCSI_In_DBx__6__BIE CYREG_PRT2_BIE
-#define SCSI_In_DBx__6__BIT_MASK CYREG_PRT2_BIT_MASK
-#define SCSI_In_DBx__6__BYP CYREG_PRT2_BYP
-#define SCSI_In_DBx__6__CTL CYREG_PRT2_CTL
-#define SCSI_In_DBx__6__DM0 CYREG_PRT2_DM0
-#define SCSI_In_DBx__6__DM1 CYREG_PRT2_DM1
-#define SCSI_In_DBx__6__DM2 CYREG_PRT2_DM2
-#define SCSI_In_DBx__6__DR CYREG_PRT2_DR
-#define SCSI_In_DBx__6__INP_DIS CYREG_PRT2_INP_DIS
-#define SCSI_In_DBx__6__INTTYPE CYREG_PICU2_INTTYPE0
-#define SCSI_In_DBx__6__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
-#define SCSI_In_DBx__6__LCD_EN CYREG_PRT2_LCD_EN
-#define SCSI_In_DBx__6__MASK 0x01u
-#define SCSI_In_DBx__6__PC CYREG_PRT2_PC0
-#define SCSI_In_DBx__6__PORT 2u
-#define SCSI_In_DBx__6__PRT CYREG_PRT2_PRT
-#define SCSI_In_DBx__6__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
-#define SCSI_In_DBx__6__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
-#define SCSI_In_DBx__6__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
-#define SCSI_In_DBx__6__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
-#define SCSI_In_DBx__6__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
-#define SCSI_In_DBx__6__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
-#define SCSI_In_DBx__6__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
-#define SCSI_In_DBx__6__PS CYREG_PRT2_PS
-#define SCSI_In_DBx__6__SHIFT 0u
-#define SCSI_In_DBx__6__SLW CYREG_PRT2_SLW
-#define SCSI_In_DBx__7__AG CYREG_PRT6_AG
-#define SCSI_In_DBx__7__AMUX CYREG_PRT6_AMUX
-#define SCSI_In_DBx__7__BIE CYREG_PRT6_BIE
-#define SCSI_In_DBx__7__BIT_MASK CYREG_PRT6_BIT_MASK
-#define SCSI_In_DBx__7__BYP CYREG_PRT6_BYP
-#define SCSI_In_DBx__7__CTL CYREG_PRT6_CTL
-#define SCSI_In_DBx__7__DM0 CYREG_PRT6_DM0
-#define SCSI_In_DBx__7__DM1 CYREG_PRT6_DM1
-#define SCSI_In_DBx__7__DM2 CYREG_PRT6_DM2
-#define SCSI_In_DBx__7__DR CYREG_PRT6_DR
-#define SCSI_In_DBx__7__INP_DIS CYREG_PRT6_INP_DIS
-#define SCSI_In_DBx__7__INTTYPE CYREG_PICU6_INTTYPE3
-#define SCSI_In_DBx__7__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
-#define SCSI_In_DBx__7__LCD_EN CYREG_PRT6_LCD_EN
-#define SCSI_In_DBx__7__MASK 0x08u
-#define SCSI_In_DBx__7__PC CYREG_PRT6_PC3
-#define SCSI_In_DBx__7__PORT 6u
-#define SCSI_In_DBx__7__PRT CYREG_PRT6_PRT
-#define SCSI_In_DBx__7__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
-#define SCSI_In_DBx__7__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
-#define SCSI_In_DBx__7__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
-#define SCSI_In_DBx__7__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
-#define SCSI_In_DBx__7__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
-#define SCSI_In_DBx__7__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
-#define SCSI_In_DBx__7__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
-#define SCSI_In_DBx__7__PS CYREG_PRT6_PS
-#define SCSI_In_DBx__7__SHIFT 3u
-#define SCSI_In_DBx__7__SLW CYREG_PRT6_SLW
-#define SCSI_In_DBx__DB0__AG CYREG_PRT6_AG
-#define SCSI_In_DBx__DB0__AMUX CYREG_PRT6_AMUX
-#define SCSI_In_DBx__DB0__BIE CYREG_PRT6_BIE
-#define SCSI_In_DBx__DB0__BIT_MASK CYREG_PRT6_BIT_MASK
-#define SCSI_In_DBx__DB0__BYP CYREG_PRT6_BYP
-#define SCSI_In_DBx__DB0__CTL CYREG_PRT6_CTL
-#define SCSI_In_DBx__DB0__DM0 CYREG_PRT6_DM0
-#define SCSI_In_DBx__DB0__DM1 CYREG_PRT6_DM1
-#define SCSI_In_DBx__DB0__DM2 CYREG_PRT6_DM2
-#define SCSI_In_DBx__DB0__DR CYREG_PRT6_DR
-#define SCSI_In_DBx__DB0__INP_DIS CYREG_PRT6_INP_DIS
-#define SCSI_In_DBx__DB0__INTTYPE CYREG_PICU6_INTTYPE6
-#define SCSI_In_DBx__DB0__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
-#define SCSI_In_DBx__DB0__LCD_EN CYREG_PRT6_LCD_EN
-#define SCSI_In_DBx__DB0__MASK 0x40u
-#define SCSI_In_DBx__DB0__PC CYREG_PRT6_PC6
-#define SCSI_In_DBx__DB0__PORT 6u
-#define SCSI_In_DBx__DB0__PRT CYREG_PRT6_PRT
-#define SCSI_In_DBx__DB0__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
-#define SCSI_In_DBx__DB0__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
-#define SCSI_In_DBx__DB0__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
-#define SCSI_In_DBx__DB0__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
-#define SCSI_In_DBx__DB0__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
-#define SCSI_In_DBx__DB0__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
-#define SCSI_In_DBx__DB0__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
-#define SCSI_In_DBx__DB0__PS CYREG_PRT6_PS
-#define SCSI_In_DBx__DB0__SHIFT 6u
-#define SCSI_In_DBx__DB0__SLW CYREG_PRT6_SLW
-#define SCSI_In_DBx__DB1__AG CYREG_PRT6_AG
-#define SCSI_In_DBx__DB1__AMUX CYREG_PRT6_AMUX
-#define SCSI_In_DBx__DB1__BIE CYREG_PRT6_BIE
-#define SCSI_In_DBx__DB1__BIT_MASK CYREG_PRT6_BIT_MASK
-#define SCSI_In_DBx__DB1__BYP CYREG_PRT6_BYP
-#define SCSI_In_DBx__DB1__CTL CYREG_PRT6_CTL
-#define SCSI_In_DBx__DB1__DM0 CYREG_PRT6_DM0
-#define SCSI_In_DBx__DB1__DM1 CYREG_PRT6_DM1
-#define SCSI_In_DBx__DB1__DM2 CYREG_PRT6_DM2
-#define SCSI_In_DBx__DB1__DR CYREG_PRT6_DR
-#define SCSI_In_DBx__DB1__INP_DIS CYREG_PRT6_INP_DIS
-#define SCSI_In_DBx__DB1__INTTYPE CYREG_PICU6_INTTYPE4
-#define SCSI_In_DBx__DB1__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
-#define SCSI_In_DBx__DB1__LCD_EN CYREG_PRT6_LCD_EN
-#define SCSI_In_DBx__DB1__MASK 0x10u
-#define SCSI_In_DBx__DB1__PC CYREG_PRT6_PC4
-#define SCSI_In_DBx__DB1__PORT 6u
-#define SCSI_In_DBx__DB1__PRT CYREG_PRT6_PRT
-#define SCSI_In_DBx__DB1__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
-#define SCSI_In_DBx__DB1__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
-#define SCSI_In_DBx__DB1__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
-#define SCSI_In_DBx__DB1__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
-#define SCSI_In_DBx__DB1__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
-#define SCSI_In_DBx__DB1__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
-#define SCSI_In_DBx__DB1__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
-#define SCSI_In_DBx__DB1__PS CYREG_PRT6_PS
-#define SCSI_In_DBx__DB1__SHIFT 4u
-#define SCSI_In_DBx__DB1__SLW CYREG_PRT6_SLW
-#define SCSI_In_DBx__DB2__AG CYREG_PRT12_AG
-#define SCSI_In_DBx__DB2__BIE CYREG_PRT12_BIE
-#define SCSI_In_DBx__DB2__BIT_MASK CYREG_PRT12_BIT_MASK
-#define SCSI_In_DBx__DB2__BYP CYREG_PRT12_BYP
-#define SCSI_In_DBx__DB2__DM0 CYREG_PRT12_DM0
-#define SCSI_In_DBx__DB2__DM1 CYREG_PRT12_DM1
-#define SCSI_In_DBx__DB2__DM2 CYREG_PRT12_DM2
-#define SCSI_In_DBx__DB2__DR CYREG_PRT12_DR
-#define SCSI_In_DBx__DB2__INP_DIS CYREG_PRT12_INP_DIS
-#define SCSI_In_DBx__DB2__INTTYPE CYREG_PICU12_INTTYPE4
-#define SCSI_In_DBx__DB2__MASK 0x10u
-#define SCSI_In_DBx__DB2__PC CYREG_PRT12_PC4
-#define SCSI_In_DBx__DB2__PORT 12u
-#define SCSI_In_DBx__DB2__PRT CYREG_PRT12_PRT
-#define SCSI_In_DBx__DB2__PRTDSI__DBL_SYNC_IN CYREG_PRT12_DBL_SYNC_IN
-#define SCSI_In_DBx__DB2__PRTDSI__OE_SEL0 CYREG_PRT12_OE_SEL0
-#define SCSI_In_DBx__DB2__PRTDSI__OE_SEL1 CYREG_PRT12_OE_SEL1
-#define SCSI_In_DBx__DB2__PRTDSI__OUT_SEL0 CYREG_PRT12_OUT_SEL0
-#define SCSI_In_DBx__DB2__PRTDSI__OUT_SEL1 CYREG_PRT12_OUT_SEL1
-#define SCSI_In_DBx__DB2__PRTDSI__SYNC_OUT CYREG_PRT12_SYNC_OUT
-#define SCSI_In_DBx__DB2__PS CYREG_PRT12_PS
-#define SCSI_In_DBx__DB2__SHIFT 4u
-#define SCSI_In_DBx__DB2__SIO_CFG CYREG_PRT12_SIO_CFG
-#define SCSI_In_DBx__DB2__SIO_DIFF CYREG_PRT12_SIO_DIFF
-#define SCSI_In_DBx__DB2__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN
-#define SCSI_In_DBx__DB2__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ
-#define SCSI_In_DBx__DB2__SLW CYREG_PRT12_SLW
-#define SCSI_In_DBx__DB3__AG CYREG_PRT2_AG
-#define SCSI_In_DBx__DB3__AMUX CYREG_PRT2_AMUX
-#define SCSI_In_DBx__DB3__BIE CYREG_PRT2_BIE
-#define SCSI_In_DBx__DB3__BIT_MASK CYREG_PRT2_BIT_MASK
-#define SCSI_In_DBx__DB3__BYP CYREG_PRT2_BYP
-#define SCSI_In_DBx__DB3__CTL CYREG_PRT2_CTL
-#define SCSI_In_DBx__DB3__DM0 CYREG_PRT2_DM0
-#define SCSI_In_DBx__DB3__DM1 CYREG_PRT2_DM1
-#define SCSI_In_DBx__DB3__DM2 CYREG_PRT2_DM2
-#define SCSI_In_DBx__DB3__DR CYREG_PRT2_DR
-#define SCSI_In_DBx__DB3__INP_DIS CYREG_PRT2_INP_DIS
-#define SCSI_In_DBx__DB3__INTTYPE CYREG_PICU2_INTTYPE6
-#define SCSI_In_DBx__DB3__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
-#define SCSI_In_DBx__DB3__LCD_EN CYREG_PRT2_LCD_EN
-#define SCSI_In_DBx__DB3__MASK 0x40u
-#define SCSI_In_DBx__DB3__PC CYREG_PRT2_PC6
-#define SCSI_In_DBx__DB3__PORT 2u
-#define SCSI_In_DBx__DB3__PRT CYREG_PRT2_PRT
-#define SCSI_In_DBx__DB3__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
-#define SCSI_In_DBx__DB3__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
-#define SCSI_In_DBx__DB3__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
-#define SCSI_In_DBx__DB3__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
-#define SCSI_In_DBx__DB3__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
-#define SCSI_In_DBx__DB3__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
-#define SCSI_In_DBx__DB3__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
-#define SCSI_In_DBx__DB3__PS CYREG_PRT2_PS
-#define SCSI_In_DBx__DB3__SHIFT 6u
-#define SCSI_In_DBx__DB3__SLW CYREG_PRT2_SLW
-#define SCSI_In_DBx__DB4__AG CYREG_PRT2_AG
-#define SCSI_In_DBx__DB4__AMUX CYREG_PRT2_AMUX
-#define SCSI_In_DBx__DB4__BIE CYREG_PRT2_BIE
-#define SCSI_In_DBx__DB4__BIT_MASK CYREG_PRT2_BIT_MASK
-#define SCSI_In_DBx__DB4__BYP CYREG_PRT2_BYP
-#define SCSI_In_DBx__DB4__CTL CYREG_PRT2_CTL
-#define SCSI_In_DBx__DB4__DM0 CYREG_PRT2_DM0
-#define SCSI_In_DBx__DB4__DM1 CYREG_PRT2_DM1
-#define SCSI_In_DBx__DB4__DM2 CYREG_PRT2_DM2
-#define SCSI_In_DBx__DB4__DR CYREG_PRT2_DR
-#define SCSI_In_DBx__DB4__INP_DIS CYREG_PRT2_INP_DIS
-#define SCSI_In_DBx__DB4__INTTYPE CYREG_PICU2_INTTYPE4
-#define SCSI_In_DBx__DB4__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
-#define SCSI_In_DBx__DB4__LCD_EN CYREG_PRT2_LCD_EN
-#define SCSI_In_DBx__DB4__MASK 0x10u
-#define SCSI_In_DBx__DB4__PC CYREG_PRT2_PC4
-#define SCSI_In_DBx__DB4__PORT 2u
-#define SCSI_In_DBx__DB4__PRT CYREG_PRT2_PRT
-#define SCSI_In_DBx__DB4__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
-#define SCSI_In_DBx__DB4__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
-#define SCSI_In_DBx__DB4__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
-#define SCSI_In_DBx__DB4__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
-#define SCSI_In_DBx__DB4__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
-#define SCSI_In_DBx__DB4__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
-#define SCSI_In_DBx__DB4__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
-#define SCSI_In_DBx__DB4__PS CYREG_PRT2_PS
-#define SCSI_In_DBx__DB4__SHIFT 4u
-#define SCSI_In_DBx__DB4__SLW CYREG_PRT2_SLW
-#define SCSI_In_DBx__DB5__AG CYREG_PRT2_AG
-#define SCSI_In_DBx__DB5__AMUX CYREG_PRT2_AMUX
-#define SCSI_In_DBx__DB5__BIE CYREG_PRT2_BIE
-#define SCSI_In_DBx__DB5__BIT_MASK CYREG_PRT2_BIT_MASK
-#define SCSI_In_DBx__DB5__BYP CYREG_PRT2_BYP
-#define SCSI_In_DBx__DB5__CTL CYREG_PRT2_CTL
-#define SCSI_In_DBx__DB5__DM0 CYREG_PRT2_DM0
-#define SCSI_In_DBx__DB5__DM1 CYREG_PRT2_DM1
-#define SCSI_In_DBx__DB5__DM2 CYREG_PRT2_DM2
-#define SCSI_In_DBx__DB5__DR CYREG_PRT2_DR
-#define SCSI_In_DBx__DB5__INP_DIS CYREG_PRT2_INP_DIS
-#define SCSI_In_DBx__DB5__INTTYPE CYREG_PICU2_INTTYPE2
-#define SCSI_In_DBx__DB5__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
-#define SCSI_In_DBx__DB5__LCD_EN CYREG_PRT2_LCD_EN
-#define SCSI_In_DBx__DB5__MASK 0x04u
-#define SCSI_In_DBx__DB5__PC CYREG_PRT2_PC2
-#define SCSI_In_DBx__DB5__PORT 2u
-#define SCSI_In_DBx__DB5__PRT CYREG_PRT2_PRT
-#define SCSI_In_DBx__DB5__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
-#define SCSI_In_DBx__DB5__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
-#define SCSI_In_DBx__DB5__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
-#define SCSI_In_DBx__DB5__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
-#define SCSI_In_DBx__DB5__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
-#define SCSI_In_DBx__DB5__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
-#define SCSI_In_DBx__DB5__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
-#define SCSI_In_DBx__DB5__PS CYREG_PRT2_PS
-#define SCSI_In_DBx__DB5__SHIFT 2u
-#define SCSI_In_DBx__DB5__SLW CYREG_PRT2_SLW
-#define SCSI_In_DBx__DB6__AG CYREG_PRT2_AG
-#define SCSI_In_DBx__DB6__AMUX CYREG_PRT2_AMUX
-#define SCSI_In_DBx__DB6__BIE CYREG_PRT2_BIE
-#define SCSI_In_DBx__DB6__BIT_MASK CYREG_PRT2_BIT_MASK
-#define SCSI_In_DBx__DB6__BYP CYREG_PRT2_BYP
-#define SCSI_In_DBx__DB6__CTL CYREG_PRT2_CTL
-#define SCSI_In_DBx__DB6__DM0 CYREG_PRT2_DM0
-#define SCSI_In_DBx__DB6__DM1 CYREG_PRT2_DM1
-#define SCSI_In_DBx__DB6__DM2 CYREG_PRT2_DM2
-#define SCSI_In_DBx__DB6__DR CYREG_PRT2_DR
-#define SCSI_In_DBx__DB6__INP_DIS CYREG_PRT2_INP_DIS
-#define SCSI_In_DBx__DB6__INTTYPE CYREG_PICU2_INTTYPE0
-#define SCSI_In_DBx__DB6__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
-#define SCSI_In_DBx__DB6__LCD_EN CYREG_PRT2_LCD_EN
-#define SCSI_In_DBx__DB6__MASK 0x01u
-#define SCSI_In_DBx__DB6__PC CYREG_PRT2_PC0
-#define SCSI_In_DBx__DB6__PORT 2u
-#define SCSI_In_DBx__DB6__PRT CYREG_PRT2_PRT
-#define SCSI_In_DBx__DB6__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
-#define SCSI_In_DBx__DB6__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
-#define SCSI_In_DBx__DB6__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
-#define SCSI_In_DBx__DB6__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
-#define SCSI_In_DBx__DB6__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
-#define SCSI_In_DBx__DB6__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
-#define SCSI_In_DBx__DB6__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
-#define SCSI_In_DBx__DB6__PS CYREG_PRT2_PS
-#define SCSI_In_DBx__DB6__SHIFT 0u
-#define SCSI_In_DBx__DB6__SLW CYREG_PRT2_SLW
-#define SCSI_In_DBx__DB7__AG CYREG_PRT6_AG
-#define SCSI_In_DBx__DB7__AMUX CYREG_PRT6_AMUX
-#define SCSI_In_DBx__DB7__BIE CYREG_PRT6_BIE
-#define SCSI_In_DBx__DB7__BIT_MASK CYREG_PRT6_BIT_MASK
-#define SCSI_In_DBx__DB7__BYP CYREG_PRT6_BYP
-#define SCSI_In_DBx__DB7__CTL CYREG_PRT6_CTL
-#define SCSI_In_DBx__DB7__DM0 CYREG_PRT6_DM0
-#define SCSI_In_DBx__DB7__DM1 CYREG_PRT6_DM1
-#define SCSI_In_DBx__DB7__DM2 CYREG_PRT6_DM2
-#define SCSI_In_DBx__DB7__DR CYREG_PRT6_DR
-#define SCSI_In_DBx__DB7__INP_DIS CYREG_PRT6_INP_DIS
-#define SCSI_In_DBx__DB7__INTTYPE CYREG_PICU6_INTTYPE3
-#define SCSI_In_DBx__DB7__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
-#define SCSI_In_DBx__DB7__LCD_EN CYREG_PRT6_LCD_EN
-#define SCSI_In_DBx__DB7__MASK 0x08u
-#define SCSI_In_DBx__DB7__PC CYREG_PRT6_PC3
-#define SCSI_In_DBx__DB7__PORT 6u
-#define SCSI_In_DBx__DB7__PRT CYREG_PRT6_PRT
-#define SCSI_In_DBx__DB7__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
-#define SCSI_In_DBx__DB7__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
-#define SCSI_In_DBx__DB7__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
-#define SCSI_In_DBx__DB7__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
-#define SCSI_In_DBx__DB7__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
-#define SCSI_In_DBx__DB7__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
-#define SCSI_In_DBx__DB7__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
-#define SCSI_In_DBx__DB7__PS CYREG_PRT6_PS
-#define SCSI_In_DBx__DB7__SHIFT 3u
-#define SCSI_In_DBx__DB7__SLW CYREG_PRT6_SLW
-
-/* SD_MISO */
-#define SD_MISO__0__INTTYPE CYREG_PICU3_INTTYPE2
-#define SD_MISO__0__MASK 0x04u
-#define SD_MISO__0__PC CYREG_PRT3_PC2
-#define SD_MISO__0__PORT 3u
-#define SD_MISO__0__SHIFT 2u
-#define SD_MISO__AG CYREG_PRT3_AG
-#define SD_MISO__AMUX CYREG_PRT3_AMUX
-#define SD_MISO__BIE CYREG_PRT3_BIE
-#define SD_MISO__BIT_MASK CYREG_PRT3_BIT_MASK
-#define SD_MISO__BYP CYREG_PRT3_BYP
-#define SD_MISO__CTL CYREG_PRT3_CTL
-#define SD_MISO__DM0 CYREG_PRT3_DM0
-#define SD_MISO__DM1 CYREG_PRT3_DM1
-#define SD_MISO__DM2 CYREG_PRT3_DM2
-#define SD_MISO__DR CYREG_PRT3_DR
-#define SD_MISO__INP_DIS CYREG_PRT3_INP_DIS
-#define SD_MISO__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU3_BASE
-#define SD_MISO__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG
-#define SD_MISO__LCD_EN CYREG_PRT3_LCD_EN
-#define SD_MISO__MASK 0x04u
-#define SD_MISO__PORT 3u
-#define SD_MISO__PRT CYREG_PRT3_PRT
-#define SD_MISO__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL
-#define SD_MISO__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN
-#define SD_MISO__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0
-#define SD_MISO__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1
-#define SD_MISO__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0
-#define SD_MISO__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1
-#define SD_MISO__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT
-#define SD_MISO__PS CYREG_PRT3_PS
-#define SD_MISO__SHIFT 2u
-#define SD_MISO__SLW CYREG_PRT3_SLW
-
-/* SD_MOSI */
-#define SD_MOSI__0__INTTYPE CYREG_PICU3_INTTYPE4
-#define SD_MOSI__0__MASK 0x10u
-#define SD_MOSI__0__PC CYREG_PRT3_PC4
-#define SD_MOSI__0__PORT 3u
-#define SD_MOSI__0__SHIFT 4u
-#define SD_MOSI__AG CYREG_PRT3_AG
-#define SD_MOSI__AMUX CYREG_PRT3_AMUX
-#define SD_MOSI__BIE CYREG_PRT3_BIE
-#define SD_MOSI__BIT_MASK CYREG_PRT3_BIT_MASK
-#define SD_MOSI__BYP CYREG_PRT3_BYP
-#define SD_MOSI__CTL CYREG_PRT3_CTL
-#define SD_MOSI__DM0 CYREG_PRT3_DM0
-#define SD_MOSI__DM1 CYREG_PRT3_DM1
-#define SD_MOSI__DM2 CYREG_PRT3_DM2
-#define SD_MOSI__DR CYREG_PRT3_DR
-#define SD_MOSI__INP_DIS CYREG_PRT3_INP_DIS
-#define SD_MOSI__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU3_BASE
-#define SD_MOSI__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG
-#define SD_MOSI__LCD_EN CYREG_PRT3_LCD_EN
-#define SD_MOSI__MASK 0x10u
-#define SD_MOSI__PORT 3u
-#define SD_MOSI__PRT CYREG_PRT3_PRT
-#define SD_MOSI__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL
-#define SD_MOSI__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN
-#define SD_MOSI__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0
-#define SD_MOSI__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1
-#define SD_MOSI__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0
-#define SD_MOSI__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1
-#define SD_MOSI__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT
-#define SD_MOSI__PS CYREG_PRT3_PS
-#define SD_MOSI__SHIFT 4u
-#define SD_MOSI__SLW CYREG_PRT3_SLW
-
-/* TERM_EN */
-#define TERM_EN__0__INTTYPE CYREG_PICU15_INTTYPE3
-#define TERM_EN__0__MASK 0x08u
-#define TERM_EN__0__PC CYREG_IO_PC_PRT15_PC3
-#define TERM_EN__0__PORT 15u
-#define TERM_EN__0__SHIFT 3u
-#define TERM_EN__AG CYREG_PRT15_AG
-#define TERM_EN__AMUX CYREG_PRT15_AMUX
-#define TERM_EN__BIE CYREG_PRT15_BIE
-#define TERM_EN__BIT_MASK CYREG_PRT15_BIT_MASK
-#define TERM_EN__BYP CYREG_PRT15_BYP
-#define TERM_EN__CTL CYREG_PRT15_CTL
-#define TERM_EN__DM0 CYREG_PRT15_DM0
-#define TERM_EN__DM1 CYREG_PRT15_DM1
-#define TERM_EN__DM2 CYREG_PRT15_DM2
-#define TERM_EN__DR CYREG_PRT15_DR
-#define TERM_EN__INP_DIS CYREG_PRT15_INP_DIS
-#define TERM_EN__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU15_BASE
-#define TERM_EN__LCD_COM_SEG CYREG_PRT15_LCD_COM_SEG
-#define TERM_EN__LCD_EN CYREG_PRT15_LCD_EN
-#define TERM_EN__MASK 0x08u
-#define TERM_EN__PORT 15u
-#define TERM_EN__PRT CYREG_PRT15_PRT
-#define TERM_EN__PRTDSI__CAPS_SEL CYREG_PRT15_CAPS_SEL
-#define TERM_EN__PRTDSI__DBL_SYNC_IN CYREG_PRT15_DBL_SYNC_IN
-#define TERM_EN__PRTDSI__OE_SEL0 CYREG_PRT15_OE_SEL0
-#define TERM_EN__PRTDSI__OE_SEL1 CYREG_PRT15_OE_SEL1
-#define TERM_EN__PRTDSI__OUT_SEL0 CYREG_PRT15_OUT_SEL0
-#define TERM_EN__PRTDSI__OUT_SEL1 CYREG_PRT15_OUT_SEL1
-#define TERM_EN__PRTDSI__SYNC_OUT CYREG_PRT15_SYNC_OUT
-#define TERM_EN__PS CYREG_PRT15_PS
-#define TERM_EN__SHIFT 3u
-#define TERM_EN__SLW CYREG_PRT15_SLW
-
-/* SCSI_CLK */
-#define SCSI_CLK__CFG0 CYREG_CLKDIST_DCFG1_CFG0
-#define SCSI_CLK__CFG1 CYREG_CLKDIST_DCFG1_CFG1
-#define SCSI_CLK__CFG2 CYREG_CLKDIST_DCFG1_CFG2
-#define SCSI_CLK__CFG2_SRC_SEL_MASK 0x07u
-#define SCSI_CLK__INDEX 0x01u
-#define SCSI_CLK__PM_ACT_CFG CYREG_PM_ACT_CFG2
-#define SCSI_CLK__PM_ACT_MSK 0x02u
-#define SCSI_CLK__PM_STBY_CFG CYREG_PM_STBY_CFG2
-#define SCSI_CLK__PM_STBY_MSK 0x02u
-
-/* SCSI_Out */
-#define SCSI_Out__0__AG CYREG_PRT6_AG
-#define SCSI_Out__0__AMUX CYREG_PRT6_AMUX
-#define SCSI_Out__0__BIE CYREG_PRT6_BIE
-#define SCSI_Out__0__BIT_MASK CYREG_PRT6_BIT_MASK
-#define SCSI_Out__0__BYP CYREG_PRT6_BYP
-#define SCSI_Out__0__CTL CYREG_PRT6_CTL
-#define SCSI_Out__0__DM0 CYREG_PRT6_DM0
-#define SCSI_Out__0__DM1 CYREG_PRT6_DM1
-#define SCSI_Out__0__DM2 CYREG_PRT6_DM2
-#define SCSI_Out__0__DR CYREG_PRT6_DR
-#define SCSI_Out__0__INP_DIS CYREG_PRT6_INP_DIS
-#define SCSI_Out__0__INTTYPE CYREG_PICU6_INTTYPE2
-#define SCSI_Out__0__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
-#define SCSI_Out__0__LCD_EN CYREG_PRT6_LCD_EN
-#define SCSI_Out__0__MASK 0x04u
-#define SCSI_Out__0__PC CYREG_PRT6_PC2
-#define SCSI_Out__0__PORT 6u
-#define SCSI_Out__0__PRT CYREG_PRT6_PRT
-#define SCSI_Out__0__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
-#define SCSI_Out__0__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
-#define SCSI_Out__0__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
-#define SCSI_Out__0__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
-#define SCSI_Out__0__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
-#define SCSI_Out__0__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
-#define SCSI_Out__0__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
-#define SCSI_Out__0__PS CYREG_PRT6_PS
-#define SCSI_Out__0__SHIFT 2u
-#define SCSI_Out__0__SLW CYREG_PRT6_SLW
-#define SCSI_Out__1__AG CYREG_PRT4_AG
-#define SCSI_Out__1__AMUX CYREG_PRT4_AMUX
-#define SCSI_Out__1__BIE CYREG_PRT4_BIE
-#define SCSI_Out__1__BIT_MASK CYREG_PRT4_BIT_MASK
-#define SCSI_Out__1__BYP CYREG_PRT4_BYP
-#define SCSI_Out__1__CTL CYREG_PRT4_CTL
-#define SCSI_Out__1__DM0 CYREG_PRT4_DM0
-#define SCSI_Out__1__DM1 CYREG_PRT4_DM1
-#define SCSI_Out__1__DM2 CYREG_PRT4_DM2
-#define SCSI_Out__1__DR CYREG_PRT4_DR
-#define SCSI_Out__1__INP_DIS CYREG_PRT4_INP_DIS
-#define SCSI_Out__1__INTTYPE CYREG_PICU4_INTTYPE6
-#define SCSI_Out__1__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG
-#define SCSI_Out__1__LCD_EN CYREG_PRT4_LCD_EN
-#define SCSI_Out__1__MASK 0x40u
-#define SCSI_Out__1__PC CYREG_PRT4_PC6
-#define SCSI_Out__1__PORT 4u
-#define SCSI_Out__1__PRT CYREG_PRT4_PRT
-#define SCSI_Out__1__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL
-#define SCSI_Out__1__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN
-#define SCSI_Out__1__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0
-#define SCSI_Out__1__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1
-#define SCSI_Out__1__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0
-#define SCSI_Out__1__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1
-#define SCSI_Out__1__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT
-#define SCSI_Out__1__PS CYREG_PRT4_PS
-#define SCSI_Out__1__SHIFT 6u
-#define SCSI_Out__1__SLW CYREG_PRT4_SLW
-#define SCSI_Out__2__AG CYREG_PRT0_AG
-#define SCSI_Out__2__AMUX CYREG_PRT0_AMUX
-#define SCSI_Out__2__BIE CYREG_PRT0_BIE
-#define SCSI_Out__2__BIT_MASK CYREG_PRT0_BIT_MASK
-#define SCSI_Out__2__BYP CYREG_PRT0_BYP
-#define SCSI_Out__2__CTL CYREG_PRT0_CTL
-#define SCSI_Out__2__DM0 CYREG_PRT0_DM0
-#define SCSI_Out__2__DM1 CYREG_PRT0_DM1
-#define SCSI_Out__2__DM2 CYREG_PRT0_DM2
-#define SCSI_Out__2__DR CYREG_PRT0_DR
-#define SCSI_Out__2__INP_DIS CYREG_PRT0_INP_DIS
-#define SCSI_Out__2__INTTYPE CYREG_PICU0_INTTYPE7
-#define SCSI_Out__2__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG
-#define SCSI_Out__2__LCD_EN CYREG_PRT0_LCD_EN
-#define SCSI_Out__2__MASK 0x80u
-#define SCSI_Out__2__PC CYREG_PRT0_PC7
-#define SCSI_Out__2__PORT 0u
-#define SCSI_Out__2__PRT CYREG_PRT0_PRT
-#define SCSI_Out__2__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL
-#define SCSI_Out__2__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN
-#define SCSI_Out__2__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0
-#define SCSI_Out__2__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1
-#define SCSI_Out__2__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0
-#define SCSI_Out__2__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1
-#define SCSI_Out__2__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT
-#define SCSI_Out__2__PS CYREG_PRT0_PS
-#define SCSI_Out__2__SHIFT 7u
-#define SCSI_Out__2__SLW CYREG_PRT0_SLW
-#define SCSI_Out__3__AG CYREG_PRT0_AG
-#define SCSI_Out__3__AMUX CYREG_PRT0_AMUX
-#define SCSI_Out__3__BIE CYREG_PRT0_BIE
-#define SCSI_Out__3__BIT_MASK CYREG_PRT0_BIT_MASK
-#define SCSI_Out__3__BYP CYREG_PRT0_BYP
-#define SCSI_Out__3__CTL CYREG_PRT0_CTL
-#define SCSI_Out__3__DM0 CYREG_PRT0_DM0
-#define SCSI_Out__3__DM1 CYREG_PRT0_DM1
-#define SCSI_Out__3__DM2 CYREG_PRT0_DM2
-#define SCSI_Out__3__DR CYREG_PRT0_DR
-#define SCSI_Out__3__INP_DIS CYREG_PRT0_INP_DIS
-#define SCSI_Out__3__INTTYPE CYREG_PICU0_INTTYPE5
-#define SCSI_Out__3__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG
-#define SCSI_Out__3__LCD_EN CYREG_PRT0_LCD_EN
-#define SCSI_Out__3__MASK 0x20u
-#define SCSI_Out__3__PC CYREG_PRT0_PC5
-#define SCSI_Out__3__PORT 0u
-#define SCSI_Out__3__PRT CYREG_PRT0_PRT
-#define SCSI_Out__3__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL
-#define SCSI_Out__3__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN
-#define SCSI_Out__3__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0
-#define SCSI_Out__3__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1
-#define SCSI_Out__3__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0
-#define SCSI_Out__3__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1
-#define SCSI_Out__3__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT
-#define SCSI_Out__3__PS CYREG_PRT0_PS
-#define SCSI_Out__3__SHIFT 5u
-#define SCSI_Out__3__SLW CYREG_PRT0_SLW
-#define SCSI_Out__4__AG CYREG_PRT0_AG
-#define SCSI_Out__4__AMUX CYREG_PRT0_AMUX
-#define SCSI_Out__4__BIE CYREG_PRT0_BIE
-#define SCSI_Out__4__BIT_MASK CYREG_PRT0_BIT_MASK
-#define SCSI_Out__4__BYP CYREG_PRT0_BYP
-#define SCSI_Out__4__CTL CYREG_PRT0_CTL
-#define SCSI_Out__4__DM0 CYREG_PRT0_DM0
-#define SCSI_Out__4__DM1 CYREG_PRT0_DM1
-#define SCSI_Out__4__DM2 CYREG_PRT0_DM2
-#define SCSI_Out__4__DR CYREG_PRT0_DR
-#define SCSI_Out__4__INP_DIS CYREG_PRT0_INP_DIS
-#define SCSI_Out__4__INTTYPE CYREG_PICU0_INTTYPE3
-#define SCSI_Out__4__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG
-#define SCSI_Out__4__LCD_EN CYREG_PRT0_LCD_EN
-#define SCSI_Out__4__MASK 0x08u
-#define SCSI_Out__4__PC CYREG_PRT0_PC3
-#define SCSI_Out__4__PORT 0u
-#define SCSI_Out__4__PRT CYREG_PRT0_PRT
-#define SCSI_Out__4__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL
-#define SCSI_Out__4__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN
-#define SCSI_Out__4__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0
-#define SCSI_Out__4__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1
-#define SCSI_Out__4__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0
-#define SCSI_Out__4__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1
-#define SCSI_Out__4__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT
-#define SCSI_Out__4__PS CYREG_PRT0_PS
-#define SCSI_Out__4__SHIFT 3u
-#define SCSI_Out__4__SLW CYREG_PRT0_SLW
-#define SCSI_Out__5__AG CYREG_PRT0_AG
-#define SCSI_Out__5__AMUX CYREG_PRT0_AMUX
-#define SCSI_Out__5__BIE CYREG_PRT0_BIE
-#define SCSI_Out__5__BIT_MASK CYREG_PRT0_BIT_MASK
-#define SCSI_Out__5__BYP CYREG_PRT0_BYP
-#define SCSI_Out__5__CTL CYREG_PRT0_CTL
-#define SCSI_Out__5__DM0 CYREG_PRT0_DM0
-#define SCSI_Out__5__DM1 CYREG_PRT0_DM1
-#define SCSI_Out__5__DM2 CYREG_PRT0_DM2
-#define SCSI_Out__5__DR CYREG_PRT0_DR
-#define SCSI_Out__5__INP_DIS CYREG_PRT0_INP_DIS
-#define SCSI_Out__5__INTTYPE CYREG_PICU0_INTTYPE1
-#define SCSI_Out__5__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG
-#define SCSI_Out__5__LCD_EN CYREG_PRT0_LCD_EN
-#define SCSI_Out__5__MASK 0x02u
-#define SCSI_Out__5__PC CYREG_PRT0_PC1
-#define SCSI_Out__5__PORT 0u
-#define SCSI_Out__5__PRT CYREG_PRT0_PRT
-#define SCSI_Out__5__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL
-#define SCSI_Out__5__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN
-#define SCSI_Out__5__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0
-#define SCSI_Out__5__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1
-#define SCSI_Out__5__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0
-#define SCSI_Out__5__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1
-#define SCSI_Out__5__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT
-#define SCSI_Out__5__PS CYREG_PRT0_PS
-#define SCSI_Out__5__SHIFT 1u
-#define SCSI_Out__5__SLW CYREG_PRT0_SLW
-#define SCSI_Out__6__AG CYREG_PRT4_AG
-#define SCSI_Out__6__AMUX CYREG_PRT4_AMUX
-#define SCSI_Out__6__BIE CYREG_PRT4_BIE
-#define SCSI_Out__6__BIT_MASK CYREG_PRT4_BIT_MASK
-#define SCSI_Out__6__BYP CYREG_PRT4_BYP
-#define SCSI_Out__6__CTL CYREG_PRT4_CTL
-#define SCSI_Out__6__DM0 CYREG_PRT4_DM0
-#define SCSI_Out__6__DM1 CYREG_PRT4_DM1
-#define SCSI_Out__6__DM2 CYREG_PRT4_DM2
-#define SCSI_Out__6__DR CYREG_PRT4_DR
-#define SCSI_Out__6__INP_DIS CYREG_PRT4_INP_DIS
-#define SCSI_Out__6__INTTYPE CYREG_PICU4_INTTYPE1
-#define SCSI_Out__6__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG
-#define SCSI_Out__6__LCD_EN CYREG_PRT4_LCD_EN
-#define SCSI_Out__6__MASK 0x02u
-#define SCSI_Out__6__PC CYREG_PRT4_PC1
-#define SCSI_Out__6__PORT 4u
-#define SCSI_Out__6__PRT CYREG_PRT4_PRT
-#define SCSI_Out__6__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL
-#define SCSI_Out__6__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN
-#define SCSI_Out__6__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0
-#define SCSI_Out__6__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1
-#define SCSI_Out__6__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0
-#define SCSI_Out__6__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1
-#define SCSI_Out__6__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT
-#define SCSI_Out__6__PS CYREG_PRT4_PS
-#define SCSI_Out__6__SHIFT 1u
-#define SCSI_Out__6__SLW CYREG_PRT4_SLW
-#define SCSI_Out__7__AG CYREG_PRT12_AG
-#define SCSI_Out__7__BIE CYREG_PRT12_BIE
-#define SCSI_Out__7__BIT_MASK CYREG_PRT12_BIT_MASK
-#define SCSI_Out__7__BYP CYREG_PRT12_BYP
-#define SCSI_Out__7__DM0 CYREG_PRT12_DM0
-#define SCSI_Out__7__DM1 CYREG_PRT12_DM1
-#define SCSI_Out__7__DM2 CYREG_PRT12_DM2
-#define SCSI_Out__7__DR CYREG_PRT12_DR
-#define SCSI_Out__7__INP_DIS CYREG_PRT12_INP_DIS
-#define SCSI_Out__7__INTTYPE CYREG_PICU12_INTTYPE3
-#define SCSI_Out__7__MASK 0x08u
-#define SCSI_Out__7__PC CYREG_PRT12_PC3
-#define SCSI_Out__7__PORT 12u
-#define SCSI_Out__7__PRT CYREG_PRT12_PRT
-#define SCSI_Out__7__PRTDSI__DBL_SYNC_IN CYREG_PRT12_DBL_SYNC_IN
-#define SCSI_Out__7__PRTDSI__OE_SEL0 CYREG_PRT12_OE_SEL0
-#define SCSI_Out__7__PRTDSI__OE_SEL1 CYREG_PRT12_OE_SEL1
-#define SCSI_Out__7__PRTDSI__OUT_SEL0 CYREG_PRT12_OUT_SEL0
-#define SCSI_Out__7__PRTDSI__OUT_SEL1 CYREG_PRT12_OUT_SEL1
-#define SCSI_Out__7__PRTDSI__SYNC_OUT CYREG_PRT12_SYNC_OUT
-#define SCSI_Out__7__PS CYREG_PRT12_PS
-#define SCSI_Out__7__SHIFT 3u
-#define SCSI_Out__7__SIO_CFG CYREG_PRT12_SIO_CFG
-#define SCSI_Out__7__SIO_DIFF CYREG_PRT12_SIO_DIFF
-#define SCSI_Out__7__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN
-#define SCSI_Out__7__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ
-#define SCSI_Out__7__SLW CYREG_PRT12_SLW
-#define SCSI_Out__BSY__AG CYREG_PRT4_AG
-#define SCSI_Out__BSY__AMUX CYREG_PRT4_AMUX
-#define SCSI_Out__BSY__BIE CYREG_PRT4_BIE
-#define SCSI_Out__BSY__BIT_MASK CYREG_PRT4_BIT_MASK
-#define SCSI_Out__BSY__BYP CYREG_PRT4_BYP
-#define SCSI_Out__BSY__CTL CYREG_PRT4_CTL
-#define SCSI_Out__BSY__DM0 CYREG_PRT4_DM0
-#define SCSI_Out__BSY__DM1 CYREG_PRT4_DM1
-#define SCSI_Out__BSY__DM2 CYREG_PRT4_DM2
-#define SCSI_Out__BSY__DR CYREG_PRT4_DR
-#define SCSI_Out__BSY__INP_DIS CYREG_PRT4_INP_DIS
-#define SCSI_Out__BSY__INTTYPE CYREG_PICU4_INTTYPE6
-#define SCSI_Out__BSY__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG
-#define SCSI_Out__BSY__LCD_EN CYREG_PRT4_LCD_EN
-#define SCSI_Out__BSY__MASK 0x40u
-#define SCSI_Out__BSY__PC CYREG_PRT4_PC6
-#define SCSI_Out__BSY__PORT 4u
-#define SCSI_Out__BSY__PRT CYREG_PRT4_PRT
-#define SCSI_Out__BSY__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL
-#define SCSI_Out__BSY__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN
-#define SCSI_Out__BSY__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0
-#define SCSI_Out__BSY__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1
-#define SCSI_Out__BSY__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0
-#define SCSI_Out__BSY__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1
-#define SCSI_Out__BSY__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT
-#define SCSI_Out__BSY__PS CYREG_PRT4_PS
-#define SCSI_Out__BSY__SHIFT 6u
-#define SCSI_Out__BSY__SLW CYREG_PRT4_SLW
-#define SCSI_Out__CD_raw__AG CYREG_PRT0_AG
-#define SCSI_Out__CD_raw__AMUX CYREG_PRT0_AMUX
-#define SCSI_Out__CD_raw__BIE CYREG_PRT0_BIE
-#define SCSI_Out__CD_raw__BIT_MASK CYREG_PRT0_BIT_MASK
-#define SCSI_Out__CD_raw__BYP CYREG_PRT0_BYP
-#define SCSI_Out__CD_raw__CTL CYREG_PRT0_CTL
-#define SCSI_Out__CD_raw__DM0 CYREG_PRT0_DM0
-#define SCSI_Out__CD_raw__DM1 CYREG_PRT0_DM1
-#define SCSI_Out__CD_raw__DM2 CYREG_PRT0_DM2
-#define SCSI_Out__CD_raw__DR CYREG_PRT0_DR
-#define SCSI_Out__CD_raw__INP_DIS CYREG_PRT0_INP_DIS
-#define SCSI_Out__CD_raw__INTTYPE CYREG_PICU0_INTTYPE1
-#define SCSI_Out__CD_raw__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG
-#define SCSI_Out__CD_raw__LCD_EN CYREG_PRT0_LCD_EN
-#define SCSI_Out__CD_raw__MASK 0x02u
-#define SCSI_Out__CD_raw__PC CYREG_PRT0_PC1
-#define SCSI_Out__CD_raw__PORT 0u
-#define SCSI_Out__CD_raw__PRT CYREG_PRT0_PRT
-#define SCSI_Out__CD_raw__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL
-#define SCSI_Out__CD_raw__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN
-#define SCSI_Out__CD_raw__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0
-#define SCSI_Out__CD_raw__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1
-#define SCSI_Out__CD_raw__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0
-#define SCSI_Out__CD_raw__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1
-#define SCSI_Out__CD_raw__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT
-#define SCSI_Out__CD_raw__PS CYREG_PRT0_PS
-#define SCSI_Out__CD_raw__SHIFT 1u
-#define SCSI_Out__CD_raw__SLW CYREG_PRT0_SLW
-#define SCSI_Out__DBP_raw__AG CYREG_PRT6_AG
-#define SCSI_Out__DBP_raw__AMUX CYREG_PRT6_AMUX
-#define SCSI_Out__DBP_raw__BIE CYREG_PRT6_BIE
-#define SCSI_Out__DBP_raw__BIT_MASK CYREG_PRT6_BIT_MASK
-#define SCSI_Out__DBP_raw__BYP CYREG_PRT6_BYP
-#define SCSI_Out__DBP_raw__CTL CYREG_PRT6_CTL
-#define SCSI_Out__DBP_raw__DM0 CYREG_PRT6_DM0
-#define SCSI_Out__DBP_raw__DM1 CYREG_PRT6_DM1
-#define SCSI_Out__DBP_raw__DM2 CYREG_PRT6_DM2
-#define SCSI_Out__DBP_raw__DR CYREG_PRT6_DR
-#define SCSI_Out__DBP_raw__INP_DIS CYREG_PRT6_INP_DIS
-#define SCSI_Out__DBP_raw__INTTYPE CYREG_PICU6_INTTYPE2
-#define SCSI_Out__DBP_raw__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
-#define SCSI_Out__DBP_raw__LCD_EN CYREG_PRT6_LCD_EN
-#define SCSI_Out__DBP_raw__MASK 0x04u
-#define SCSI_Out__DBP_raw__PC CYREG_PRT6_PC2
-#define SCSI_Out__DBP_raw__PORT 6u
-#define SCSI_Out__DBP_raw__PRT CYREG_PRT6_PRT
-#define SCSI_Out__DBP_raw__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
-#define SCSI_Out__DBP_raw__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
-#define SCSI_Out__DBP_raw__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
-#define SCSI_Out__DBP_raw__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
-#define SCSI_Out__DBP_raw__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
-#define SCSI_Out__DBP_raw__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
-#define SCSI_Out__DBP_raw__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
-#define SCSI_Out__DBP_raw__PS CYREG_PRT6_PS
-#define SCSI_Out__DBP_raw__SHIFT 2u
-#define SCSI_Out__DBP_raw__SLW CYREG_PRT6_SLW
-#define SCSI_Out__IO_raw__AG CYREG_PRT12_AG
-#define SCSI_Out__IO_raw__BIE CYREG_PRT12_BIE
-#define SCSI_Out__IO_raw__BIT_MASK CYREG_PRT12_BIT_MASK
-#define SCSI_Out__IO_raw__BYP CYREG_PRT12_BYP
-#define SCSI_Out__IO_raw__DM0 CYREG_PRT12_DM0
-#define SCSI_Out__IO_raw__DM1 CYREG_PRT12_DM1
-#define SCSI_Out__IO_raw__DM2 CYREG_PRT12_DM2
-#define SCSI_Out__IO_raw__DR CYREG_PRT12_DR
-#define SCSI_Out__IO_raw__INP_DIS CYREG_PRT12_INP_DIS
-#define SCSI_Out__IO_raw__INTTYPE CYREG_PICU12_INTTYPE3
-#define SCSI_Out__IO_raw__MASK 0x08u
-#define SCSI_Out__IO_raw__PC CYREG_PRT12_PC3
-#define SCSI_Out__IO_raw__PORT 12u
-#define SCSI_Out__IO_raw__PRT CYREG_PRT12_PRT
-#define SCSI_Out__IO_raw__PRTDSI__DBL_SYNC_IN CYREG_PRT12_DBL_SYNC_IN
-#define SCSI_Out__IO_raw__PRTDSI__OE_SEL0 CYREG_PRT12_OE_SEL0
-#define SCSI_Out__IO_raw__PRTDSI__OE_SEL1 CYREG_PRT12_OE_SEL1
-#define SCSI_Out__IO_raw__PRTDSI__OUT_SEL0 CYREG_PRT12_OUT_SEL0
-#define SCSI_Out__IO_raw__PRTDSI__OUT_SEL1 CYREG_PRT12_OUT_SEL1
-#define SCSI_Out__IO_raw__PRTDSI__SYNC_OUT CYREG_PRT12_SYNC_OUT
-#define SCSI_Out__IO_raw__PS CYREG_PRT12_PS
-#define SCSI_Out__IO_raw__SHIFT 3u
-#define SCSI_Out__IO_raw__SIO_CFG CYREG_PRT12_SIO_CFG
-#define SCSI_Out__IO_raw__SIO_DIFF CYREG_PRT12_SIO_DIFF
-#define SCSI_Out__IO_raw__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN
-#define SCSI_Out__IO_raw__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ
-#define SCSI_Out__IO_raw__SLW CYREG_PRT12_SLW
-#define SCSI_Out__MSG_raw__AG CYREG_PRT0_AG
-#define SCSI_Out__MSG_raw__AMUX CYREG_PRT0_AMUX
-#define SCSI_Out__MSG_raw__BIE CYREG_PRT0_BIE
-#define SCSI_Out__MSG_raw__BIT_MASK CYREG_PRT0_BIT_MASK
-#define SCSI_Out__MSG_raw__BYP CYREG_PRT0_BYP
-#define SCSI_Out__MSG_raw__CTL CYREG_PRT0_CTL
-#define SCSI_Out__MSG_raw__DM0 CYREG_PRT0_DM0
-#define SCSI_Out__MSG_raw__DM1 CYREG_PRT0_DM1
-#define SCSI_Out__MSG_raw__DM2 CYREG_PRT0_DM2
-#define SCSI_Out__MSG_raw__DR CYREG_PRT0_DR
-#define SCSI_Out__MSG_raw__INP_DIS CYREG_PRT0_INP_DIS
-#define SCSI_Out__MSG_raw__INTTYPE CYREG_PICU0_INTTYPE5
-#define SCSI_Out__MSG_raw__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG
-#define SCSI_Out__MSG_raw__LCD_EN CYREG_PRT0_LCD_EN
-#define SCSI_Out__MSG_raw__MASK 0x20u
-#define SCSI_Out__MSG_raw__PC CYREG_PRT0_PC5
-#define SCSI_Out__MSG_raw__PORT 0u
-#define SCSI_Out__MSG_raw__PRT CYREG_PRT0_PRT
-#define SCSI_Out__MSG_raw__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL
-#define SCSI_Out__MSG_raw__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN
-#define SCSI_Out__MSG_raw__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0
-#define SCSI_Out__MSG_raw__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1
-#define SCSI_Out__MSG_raw__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0
-#define SCSI_Out__MSG_raw__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1
-#define SCSI_Out__MSG_raw__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT
-#define SCSI_Out__MSG_raw__PS CYREG_PRT0_PS
-#define SCSI_Out__MSG_raw__SHIFT 5u
-#define SCSI_Out__MSG_raw__SLW CYREG_PRT0_SLW
-#define SCSI_Out__REQ__AG CYREG_PRT4_AG
-#define SCSI_Out__REQ__AMUX CYREG_PRT4_AMUX
-#define SCSI_Out__REQ__BIE CYREG_PRT4_BIE
-#define SCSI_Out__REQ__BIT_MASK CYREG_PRT4_BIT_MASK
-#define SCSI_Out__REQ__BYP CYREG_PRT4_BYP
-#define SCSI_Out__REQ__CTL CYREG_PRT4_CTL
-#define SCSI_Out__REQ__DM0 CYREG_PRT4_DM0
-#define SCSI_Out__REQ__DM1 CYREG_PRT4_DM1
-#define SCSI_Out__REQ__DM2 CYREG_PRT4_DM2
-#define SCSI_Out__REQ__DR CYREG_PRT4_DR
-#define SCSI_Out__REQ__INP_DIS CYREG_PRT4_INP_DIS
-#define SCSI_Out__REQ__INTTYPE CYREG_PICU4_INTTYPE1
-#define SCSI_Out__REQ__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG
-#define SCSI_Out__REQ__LCD_EN CYREG_PRT4_LCD_EN
-#define SCSI_Out__REQ__MASK 0x02u
-#define SCSI_Out__REQ__PC CYREG_PRT4_PC1
-#define SCSI_Out__REQ__PORT 4u
-#define SCSI_Out__REQ__PRT CYREG_PRT4_PRT
-#define SCSI_Out__REQ__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL
-#define SCSI_Out__REQ__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN
-#define SCSI_Out__REQ__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0
-#define SCSI_Out__REQ__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1
-#define SCSI_Out__REQ__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0
-#define SCSI_Out__REQ__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1
-#define SCSI_Out__REQ__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT
-#define SCSI_Out__REQ__PS CYREG_PRT4_PS
-#define SCSI_Out__REQ__SHIFT 1u
-#define SCSI_Out__REQ__SLW CYREG_PRT4_SLW
-#define SCSI_Out__RST__AG CYREG_PRT0_AG
-#define SCSI_Out__RST__AMUX CYREG_PRT0_AMUX
-#define SCSI_Out__RST__BIE CYREG_PRT0_BIE
-#define SCSI_Out__RST__BIT_MASK CYREG_PRT0_BIT_MASK
-#define SCSI_Out__RST__BYP CYREG_PRT0_BYP
-#define SCSI_Out__RST__CTL CYREG_PRT0_CTL
-#define SCSI_Out__RST__DM0 CYREG_PRT0_DM0
-#define SCSI_Out__RST__DM1 CYREG_PRT0_DM1
-#define SCSI_Out__RST__DM2 CYREG_PRT0_DM2
-#define SCSI_Out__RST__DR CYREG_PRT0_DR
-#define SCSI_Out__RST__INP_DIS CYREG_PRT0_INP_DIS
-#define SCSI_Out__RST__INTTYPE CYREG_PICU0_INTTYPE7
-#define SCSI_Out__RST__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG
-#define SCSI_Out__RST__LCD_EN CYREG_PRT0_LCD_EN
-#define SCSI_Out__RST__MASK 0x80u
-#define SCSI_Out__RST__PC CYREG_PRT0_PC7
-#define SCSI_Out__RST__PORT 0u
-#define SCSI_Out__RST__PRT CYREG_PRT0_PRT
-#define SCSI_Out__RST__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL
-#define SCSI_Out__RST__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN
-#define SCSI_Out__RST__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0
-#define SCSI_Out__RST__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1
-#define SCSI_Out__RST__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0
-#define SCSI_Out__RST__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1
-#define SCSI_Out__RST__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT
-#define SCSI_Out__RST__PS CYREG_PRT0_PS
-#define SCSI_Out__RST__SHIFT 7u
-#define SCSI_Out__RST__SLW CYREG_PRT0_SLW
-#define SCSI_Out__SEL__AG CYREG_PRT0_AG
-#define SCSI_Out__SEL__AMUX CYREG_PRT0_AMUX
-#define SCSI_Out__SEL__BIE CYREG_PRT0_BIE
-#define SCSI_Out__SEL__BIT_MASK CYREG_PRT0_BIT_MASK
-#define SCSI_Out__SEL__BYP CYREG_PRT0_BYP
-#define SCSI_Out__SEL__CTL CYREG_PRT0_CTL
-#define SCSI_Out__SEL__DM0 CYREG_PRT0_DM0
-#define SCSI_Out__SEL__DM1 CYREG_PRT0_DM1
-#define SCSI_Out__SEL__DM2 CYREG_PRT0_DM2
-#define SCSI_Out__SEL__DR CYREG_PRT0_DR
-#define SCSI_Out__SEL__INP_DIS CYREG_PRT0_INP_DIS
-#define SCSI_Out__SEL__INTTYPE CYREG_PICU0_INTTYPE3
-#define SCSI_Out__SEL__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG
-#define SCSI_Out__SEL__LCD_EN CYREG_PRT0_LCD_EN
-#define SCSI_Out__SEL__MASK 0x08u
-#define SCSI_Out__SEL__PC CYREG_PRT0_PC3
-#define SCSI_Out__SEL__PORT 0u
-#define SCSI_Out__SEL__PRT CYREG_PRT0_PRT
-#define SCSI_Out__SEL__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL
-#define SCSI_Out__SEL__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN
-#define SCSI_Out__SEL__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0
-#define SCSI_Out__SEL__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1
-#define SCSI_Out__SEL__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0
-#define SCSI_Out__SEL__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1
-#define SCSI_Out__SEL__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT
-#define SCSI_Out__SEL__PS CYREG_PRT0_PS
-#define SCSI_Out__SEL__SHIFT 3u
-#define SCSI_Out__SEL__SLW CYREG_PRT0_SLW
-
-/* SCSI_Out_Bits */
-#define SCSI_Out_Bits_Sync_ctrl_reg__0__MASK 0x01u
-#define SCSI_Out_Bits_Sync_ctrl_reg__0__POS 0
-#define SCSI_Out_Bits_Sync_ctrl_reg__1__MASK 0x02u
-#define SCSI_Out_Bits_Sync_ctrl_reg__1__POS 1
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB07_08_ACTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB07_08_CTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB07_08_CTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB07_08_CTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB07_08_CTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB07_08_MSK
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB07_08_MSK
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB07_08_MSK
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB07_08_MSK
-#define SCSI_Out_Bits_Sync_ctrl_reg__2__MASK 0x04u
-#define SCSI_Out_Bits_Sync_ctrl_reg__2__POS 2
-#define SCSI_Out_Bits_Sync_ctrl_reg__3__MASK 0x08u
-#define SCSI_Out_Bits_Sync_ctrl_reg__3__POS 3
-#define SCSI_Out_Bits_Sync_ctrl_reg__4__MASK 0x10u
-#define SCSI_Out_Bits_Sync_ctrl_reg__4__POS 4
-#define SCSI_Out_Bits_Sync_ctrl_reg__5__MASK 0x20u
-#define SCSI_Out_Bits_Sync_ctrl_reg__5__POS 5
-#define SCSI_Out_Bits_Sync_ctrl_reg__6__MASK 0x40u
-#define SCSI_Out_Bits_Sync_ctrl_reg__6__POS 6
-#define SCSI_Out_Bits_Sync_ctrl_reg__7__MASK 0x80u
-#define SCSI_Out_Bits_Sync_ctrl_reg__7__POS 7
-#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB07_ACTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB07_CTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB07_ST_CTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB07_CTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB07_ST_CTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__MASK 0xFFu
-#define SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB07_MSK_ACTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB07_MSK_ACTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB07_MSK
-
-/* SCSI_Out_Ctl */
-#define SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK 0x01u
-#define SCSI_Out_Ctl_Sync_ctrl_reg__0__POS 0
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB11_12_ACTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB11_12_CTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB11_12_CTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB11_12_CTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB11_12_CTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB11_12_MSK
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB11_12_MSK
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB11_12_MSK
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB11_12_MSK
-#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB11_ACTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB11_CTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB11_ST_CTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB11_CTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB11_ST_CTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK 0x01u
-#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB11_MSK
-
-/* SCSI_Out_DBx */
-#define SCSI_Out_DBx__0__AG CYREG_PRT6_AG
-#define SCSI_Out_DBx__0__AMUX CYREG_PRT6_AMUX
-#define SCSI_Out_DBx__0__BIE CYREG_PRT6_BIE
-#define SCSI_Out_DBx__0__BIT_MASK CYREG_PRT6_BIT_MASK
-#define SCSI_Out_DBx__0__BYP CYREG_PRT6_BYP
-#define SCSI_Out_DBx__0__CTL CYREG_PRT6_CTL
-#define SCSI_Out_DBx__0__DM0 CYREG_PRT6_DM0
-#define SCSI_Out_DBx__0__DM1 CYREG_PRT6_DM1
-#define SCSI_Out_DBx__0__DM2 CYREG_PRT6_DM2
-#define SCSI_Out_DBx__0__DR CYREG_PRT6_DR
-#define SCSI_Out_DBx__0__INP_DIS CYREG_PRT6_INP_DIS
-#define SCSI_Out_DBx__0__INTTYPE CYREG_PICU6_INTTYPE7
-#define SCSI_Out_DBx__0__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
-#define SCSI_Out_DBx__0__LCD_EN CYREG_PRT6_LCD_EN
-#define SCSI_Out_DBx__0__MASK 0x80u
-#define SCSI_Out_DBx__0__PC CYREG_PRT6_PC7
-#define SCSI_Out_DBx__0__PORT 6u
-#define SCSI_Out_DBx__0__PRT CYREG_PRT6_PRT
-#define SCSI_Out_DBx__0__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
-#define SCSI_Out_DBx__0__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
-#define SCSI_Out_DBx__0__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
-#define SCSI_Out_DBx__0__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
-#define SCSI_Out_DBx__0__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
-#define SCSI_Out_DBx__0__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
-#define SCSI_Out_DBx__0__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
-#define SCSI_Out_DBx__0__PS CYREG_PRT6_PS
-#define SCSI_Out_DBx__0__SHIFT 7u
-#define SCSI_Out_DBx__0__SLW CYREG_PRT6_SLW
-#define SCSI_Out_DBx__1__AG CYREG_PRT6_AG
-#define SCSI_Out_DBx__1__AMUX CYREG_PRT6_AMUX
-#define SCSI_Out_DBx__1__BIE CYREG_PRT6_BIE
-#define SCSI_Out_DBx__1__BIT_MASK CYREG_PRT6_BIT_MASK
-#define SCSI_Out_DBx__1__BYP CYREG_PRT6_BYP
-#define SCSI_Out_DBx__1__CTL CYREG_PRT6_CTL
-#define SCSI_Out_DBx__1__DM0 CYREG_PRT6_DM0
-#define SCSI_Out_DBx__1__DM1 CYREG_PRT6_DM1
-#define SCSI_Out_DBx__1__DM2 CYREG_PRT6_DM2
-#define SCSI_Out_DBx__1__DR CYREG_PRT6_DR
-#define SCSI_Out_DBx__1__INP_DIS CYREG_PRT6_INP_DIS
-#define SCSI_Out_DBx__1__INTTYPE CYREG_PICU6_INTTYPE5
-#define SCSI_Out_DBx__1__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
-#define SCSI_Out_DBx__1__LCD_EN CYREG_PRT6_LCD_EN
-#define SCSI_Out_DBx__1__MASK 0x20u
-#define SCSI_Out_DBx__1__PC CYREG_PRT6_PC5
-#define SCSI_Out_DBx__1__PORT 6u
-#define SCSI_Out_DBx__1__PRT CYREG_PRT6_PRT
-#define SCSI_Out_DBx__1__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
-#define SCSI_Out_DBx__1__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
-#define SCSI_Out_DBx__1__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
-#define SCSI_Out_DBx__1__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
-#define SCSI_Out_DBx__1__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
-#define SCSI_Out_DBx__1__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
-#define SCSI_Out_DBx__1__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
-#define SCSI_Out_DBx__1__PS CYREG_PRT6_PS
-#define SCSI_Out_DBx__1__SHIFT 5u
-#define SCSI_Out_DBx__1__SLW CYREG_PRT6_SLW
-#define SCSI_Out_DBx__2__AG CYREG_PRT12_AG
-#define SCSI_Out_DBx__2__BIE CYREG_PRT12_BIE
-#define SCSI_Out_DBx__2__BIT_MASK CYREG_PRT12_BIT_MASK
-#define SCSI_Out_DBx__2__BYP CYREG_PRT12_BYP
-#define SCSI_Out_DBx__2__DM0 CYREG_PRT12_DM0
-#define SCSI_Out_DBx__2__DM1 CYREG_PRT12_DM1
-#define SCSI_Out_DBx__2__DM2 CYREG_PRT12_DM2
-#define SCSI_Out_DBx__2__DR CYREG_PRT12_DR
-#define SCSI_Out_DBx__2__INP_DIS CYREG_PRT12_INP_DIS
-#define SCSI_Out_DBx__2__INTTYPE CYREG_PICU12_INTTYPE5
-#define SCSI_Out_DBx__2__MASK 0x20u
-#define SCSI_Out_DBx__2__PC CYREG_PRT12_PC5
-#define SCSI_Out_DBx__2__PORT 12u
-#define SCSI_Out_DBx__2__PRT CYREG_PRT12_PRT
-#define SCSI_Out_DBx__2__PRTDSI__DBL_SYNC_IN CYREG_PRT12_DBL_SYNC_IN
-#define SCSI_Out_DBx__2__PRTDSI__OE_SEL0 CYREG_PRT12_OE_SEL0
-#define SCSI_Out_DBx__2__PRTDSI__OE_SEL1 CYREG_PRT12_OE_SEL1
-#define SCSI_Out_DBx__2__PRTDSI__OUT_SEL0 CYREG_PRT12_OUT_SEL0
-#define SCSI_Out_DBx__2__PRTDSI__OUT_SEL1 CYREG_PRT12_OUT_SEL1
-#define SCSI_Out_DBx__2__PRTDSI__SYNC_OUT CYREG_PRT12_SYNC_OUT
-#define SCSI_Out_DBx__2__PS CYREG_PRT12_PS
-#define SCSI_Out_DBx__2__SHIFT 5u
-#define SCSI_Out_DBx__2__SIO_CFG CYREG_PRT12_SIO_CFG
-#define SCSI_Out_DBx__2__SIO_DIFF CYREG_PRT12_SIO_DIFF
-#define SCSI_Out_DBx__2__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN
-#define SCSI_Out_DBx__2__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ
-#define SCSI_Out_DBx__2__SLW CYREG_PRT12_SLW
-#define SCSI_Out_DBx__3__AG CYREG_PRT2_AG
-#define SCSI_Out_DBx__3__AMUX CYREG_PRT2_AMUX
-#define SCSI_Out_DBx__3__BIE CYREG_PRT2_BIE
-#define SCSI_Out_DBx__3__BIT_MASK CYREG_PRT2_BIT_MASK
-#define SCSI_Out_DBx__3__BYP CYREG_PRT2_BYP
-#define SCSI_Out_DBx__3__CTL CYREG_PRT2_CTL
-#define SCSI_Out_DBx__3__DM0 CYREG_PRT2_DM0
-#define SCSI_Out_DBx__3__DM1 CYREG_PRT2_DM1
-#define SCSI_Out_DBx__3__DM2 CYREG_PRT2_DM2
-#define SCSI_Out_DBx__3__DR CYREG_PRT2_DR
-#define SCSI_Out_DBx__3__INP_DIS CYREG_PRT2_INP_DIS
-#define SCSI_Out_DBx__3__INTTYPE CYREG_PICU2_INTTYPE7
-#define SCSI_Out_DBx__3__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
-#define SCSI_Out_DBx__3__LCD_EN CYREG_PRT2_LCD_EN
-#define SCSI_Out_DBx__3__MASK 0x80u
-#define SCSI_Out_DBx__3__PC CYREG_PRT2_PC7
-#define SCSI_Out_DBx__3__PORT 2u
-#define SCSI_Out_DBx__3__PRT CYREG_PRT2_PRT
-#define SCSI_Out_DBx__3__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
-#define SCSI_Out_DBx__3__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
-#define SCSI_Out_DBx__3__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
-#define SCSI_Out_DBx__3__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
-#define SCSI_Out_DBx__3__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
-#define SCSI_Out_DBx__3__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
-#define SCSI_Out_DBx__3__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
-#define SCSI_Out_DBx__3__PS CYREG_PRT2_PS
-#define SCSI_Out_DBx__3__SHIFT 7u
-#define SCSI_Out_DBx__3__SLW CYREG_PRT2_SLW
-#define SCSI_Out_DBx__4__AG CYREG_PRT2_AG
-#define SCSI_Out_DBx__4__AMUX CYREG_PRT2_AMUX
-#define SCSI_Out_DBx__4__BIE CYREG_PRT2_BIE
-#define SCSI_Out_DBx__4__BIT_MASK CYREG_PRT2_BIT_MASK
-#define SCSI_Out_DBx__4__BYP CYREG_PRT2_BYP
-#define SCSI_Out_DBx__4__CTL CYREG_PRT2_CTL
-#define SCSI_Out_DBx__4__DM0 CYREG_PRT2_DM0
-#define SCSI_Out_DBx__4__DM1 CYREG_PRT2_DM1
-#define SCSI_Out_DBx__4__DM2 CYREG_PRT2_DM2
-#define SCSI_Out_DBx__4__DR CYREG_PRT2_DR
-#define SCSI_Out_DBx__4__INP_DIS CYREG_PRT2_INP_DIS
-#define SCSI_Out_DBx__4__INTTYPE CYREG_PICU2_INTTYPE5
-#define SCSI_Out_DBx__4__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
-#define SCSI_Out_DBx__4__LCD_EN CYREG_PRT2_LCD_EN
-#define SCSI_Out_DBx__4__MASK 0x20u
-#define SCSI_Out_DBx__4__PC CYREG_PRT2_PC5
-#define SCSI_Out_DBx__4__PORT 2u
-#define SCSI_Out_DBx__4__PRT CYREG_PRT2_PRT
-#define SCSI_Out_DBx__4__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
-#define SCSI_Out_DBx__4__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
-#define SCSI_Out_DBx__4__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
-#define SCSI_Out_DBx__4__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
-#define SCSI_Out_DBx__4__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
-#define SCSI_Out_DBx__4__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
-#define SCSI_Out_DBx__4__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
-#define SCSI_Out_DBx__4__PS CYREG_PRT2_PS
-#define SCSI_Out_DBx__4__SHIFT 5u
-#define SCSI_Out_DBx__4__SLW CYREG_PRT2_SLW
-#define SCSI_Out_DBx__5__AG CYREG_PRT2_AG
-#define SCSI_Out_DBx__5__AMUX CYREG_PRT2_AMUX
-#define SCSI_Out_DBx__5__BIE CYREG_PRT2_BIE
-#define SCSI_Out_DBx__5__BIT_MASK CYREG_PRT2_BIT_MASK
-#define SCSI_Out_DBx__5__BYP CYREG_PRT2_BYP
-#define SCSI_Out_DBx__5__CTL CYREG_PRT2_CTL
-#define SCSI_Out_DBx__5__DM0 CYREG_PRT2_DM0
-#define SCSI_Out_DBx__5__DM1 CYREG_PRT2_DM1
-#define SCSI_Out_DBx__5__DM2 CYREG_PRT2_DM2
-#define SCSI_Out_DBx__5__DR CYREG_PRT2_DR
-#define SCSI_Out_DBx__5__INP_DIS CYREG_PRT2_INP_DIS
-#define SCSI_Out_DBx__5__INTTYPE CYREG_PICU2_INTTYPE3
-#define SCSI_Out_DBx__5__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
-#define SCSI_Out_DBx__5__LCD_EN CYREG_PRT2_LCD_EN
-#define SCSI_Out_DBx__5__MASK 0x08u
-#define SCSI_Out_DBx__5__PC CYREG_PRT2_PC3
-#define SCSI_Out_DBx__5__PORT 2u
-#define SCSI_Out_DBx__5__PRT CYREG_PRT2_PRT
-#define SCSI_Out_DBx__5__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
-#define SCSI_Out_DBx__5__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
-#define SCSI_Out_DBx__5__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
-#define SCSI_Out_DBx__5__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
-#define SCSI_Out_DBx__5__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
-#define SCSI_Out_DBx__5__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
-#define SCSI_Out_DBx__5__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
-#define SCSI_Out_DBx__5__PS CYREG_PRT2_PS
-#define SCSI_Out_DBx__5__SHIFT 3u
-#define SCSI_Out_DBx__5__SLW CYREG_PRT2_SLW
-#define SCSI_Out_DBx__6__AG CYREG_PRT2_AG
-#define SCSI_Out_DBx__6__AMUX CYREG_PRT2_AMUX
-#define SCSI_Out_DBx__6__BIE CYREG_PRT2_BIE
-#define SCSI_Out_DBx__6__BIT_MASK CYREG_PRT2_BIT_MASK
-#define SCSI_Out_DBx__6__BYP CYREG_PRT2_BYP
-#define SCSI_Out_DBx__6__CTL CYREG_PRT2_CTL
-#define SCSI_Out_DBx__6__DM0 CYREG_PRT2_DM0
-#define SCSI_Out_DBx__6__DM1 CYREG_PRT2_DM1
-#define SCSI_Out_DBx__6__DM2 CYREG_PRT2_DM2
-#define SCSI_Out_DBx__6__DR CYREG_PRT2_DR
-#define SCSI_Out_DBx__6__INP_DIS CYREG_PRT2_INP_DIS
-#define SCSI_Out_DBx__6__INTTYPE CYREG_PICU2_INTTYPE1
-#define SCSI_Out_DBx__6__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
-#define SCSI_Out_DBx__6__LCD_EN CYREG_PRT2_LCD_EN
-#define SCSI_Out_DBx__6__MASK 0x02u
-#define SCSI_Out_DBx__6__PC CYREG_PRT2_PC1
-#define SCSI_Out_DBx__6__PORT 2u
-#define SCSI_Out_DBx__6__PRT CYREG_PRT2_PRT
-#define SCSI_Out_DBx__6__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
-#define SCSI_Out_DBx__6__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
-#define SCSI_Out_DBx__6__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
-#define SCSI_Out_DBx__6__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
-#define SCSI_Out_DBx__6__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
-#define SCSI_Out_DBx__6__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
-#define SCSI_Out_DBx__6__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
-#define SCSI_Out_DBx__6__PS CYREG_PRT2_PS
-#define SCSI_Out_DBx__6__SHIFT 1u
-#define SCSI_Out_DBx__6__SLW CYREG_PRT2_SLW
-#define SCSI_Out_DBx__7__AG CYREG_PRT15_AG
-#define SCSI_Out_DBx__7__AMUX CYREG_PRT15_AMUX
-#define SCSI_Out_DBx__7__BIE CYREG_PRT15_BIE
-#define SCSI_Out_DBx__7__BIT_MASK CYREG_PRT15_BIT_MASK
-#define SCSI_Out_DBx__7__BYP CYREG_PRT15_BYP
-#define SCSI_Out_DBx__7__CTL CYREG_PRT15_CTL
-#define SCSI_Out_DBx__7__DM0 CYREG_PRT15_DM0
-#define SCSI_Out_DBx__7__DM1 CYREG_PRT15_DM1
-#define SCSI_Out_DBx__7__DM2 CYREG_PRT15_DM2
-#define SCSI_Out_DBx__7__DR CYREG_PRT15_DR
-#define SCSI_Out_DBx__7__INP_DIS CYREG_PRT15_INP_DIS
-#define SCSI_Out_DBx__7__INTTYPE CYREG_PICU15_INTTYPE5
-#define SCSI_Out_DBx__7__LCD_COM_SEG CYREG_PRT15_LCD_COM_SEG
-#define SCSI_Out_DBx__7__LCD_EN CYREG_PRT15_LCD_EN
-#define SCSI_Out_DBx__7__MASK 0x20u
-#define SCSI_Out_DBx__7__PC CYREG_IO_PC_PRT15_PC5
-#define SCSI_Out_DBx__7__PORT 15u
-#define SCSI_Out_DBx__7__PRT CYREG_PRT15_PRT
-#define SCSI_Out_DBx__7__PRTDSI__CAPS_SEL CYREG_PRT15_CAPS_SEL
-#define SCSI_Out_DBx__7__PRTDSI__DBL_SYNC_IN CYREG_PRT15_DBL_SYNC_IN
-#define SCSI_Out_DBx__7__PRTDSI__OE_SEL0 CYREG_PRT15_OE_SEL0
-#define SCSI_Out_DBx__7__PRTDSI__OE_SEL1 CYREG_PRT15_OE_SEL1
-#define SCSI_Out_DBx__7__PRTDSI__OUT_SEL0 CYREG_PRT15_OUT_SEL0
-#define SCSI_Out_DBx__7__PRTDSI__OUT_SEL1 CYREG_PRT15_OUT_SEL1
-#define SCSI_Out_DBx__7__PRTDSI__SYNC_OUT CYREG_PRT15_SYNC_OUT
-#define SCSI_Out_DBx__7__PS CYREG_PRT15_PS
-#define SCSI_Out_DBx__7__SHIFT 5u
-#define SCSI_Out_DBx__7__SLW CYREG_PRT15_SLW
-#define SCSI_Out_DBx__DB0__AG CYREG_PRT6_AG
-#define SCSI_Out_DBx__DB0__AMUX CYREG_PRT6_AMUX
-#define SCSI_Out_DBx__DB0__BIE CYREG_PRT6_BIE
-#define SCSI_Out_DBx__DB0__BIT_MASK CYREG_PRT6_BIT_MASK
-#define SCSI_Out_DBx__DB0__BYP CYREG_PRT6_BYP
-#define SCSI_Out_DBx__DB0__CTL CYREG_PRT6_CTL
-#define SCSI_Out_DBx__DB0__DM0 CYREG_PRT6_DM0
-#define SCSI_Out_DBx__DB0__DM1 CYREG_PRT6_DM1
-#define SCSI_Out_DBx__DB0__DM2 CYREG_PRT6_DM2
-#define SCSI_Out_DBx__DB0__DR CYREG_PRT6_DR
-#define SCSI_Out_DBx__DB0__INP_DIS CYREG_PRT6_INP_DIS
-#define SCSI_Out_DBx__DB0__INTTYPE CYREG_PICU6_INTTYPE7
-#define SCSI_Out_DBx__DB0__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
-#define SCSI_Out_DBx__DB0__LCD_EN CYREG_PRT6_LCD_EN
-#define SCSI_Out_DBx__DB0__MASK 0x80u
-#define SCSI_Out_DBx__DB0__PC CYREG_PRT6_PC7
-#define SCSI_Out_DBx__DB0__PORT 6u
-#define SCSI_Out_DBx__DB0__PRT CYREG_PRT6_PRT
-#define SCSI_Out_DBx__DB0__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
-#define SCSI_Out_DBx__DB0__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
-#define SCSI_Out_DBx__DB0__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
-#define SCSI_Out_DBx__DB0__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
-#define SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
-#define SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
-#define SCSI_Out_DBx__DB0__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
-#define SCSI_Out_DBx__DB0__PS CYREG_PRT6_PS
-#define SCSI_Out_DBx__DB0__SHIFT 7u
-#define SCSI_Out_DBx__DB0__SLW CYREG_PRT6_SLW
-#define SCSI_Out_DBx__DB1__AG CYREG_PRT6_AG
-#define SCSI_Out_DBx__DB1__AMUX CYREG_PRT6_AMUX
-#define SCSI_Out_DBx__DB1__BIE CYREG_PRT6_BIE
-#define SCSI_Out_DBx__DB1__BIT_MASK CYREG_PRT6_BIT_MASK
-#define SCSI_Out_DBx__DB1__BYP CYREG_PRT6_BYP
-#define SCSI_Out_DBx__DB1__CTL CYREG_PRT6_CTL
-#define SCSI_Out_DBx__DB1__DM0 CYREG_PRT6_DM0
-#define SCSI_Out_DBx__DB1__DM1 CYREG_PRT6_DM1
-#define SCSI_Out_DBx__DB1__DM2 CYREG_PRT6_DM2
-#define SCSI_Out_DBx__DB1__DR CYREG_PRT6_DR
-#define SCSI_Out_DBx__DB1__INP_DIS CYREG_PRT6_INP_DIS
-#define SCSI_Out_DBx__DB1__INTTYPE CYREG_PICU6_INTTYPE5
-#define SCSI_Out_DBx__DB1__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
-#define SCSI_Out_DBx__DB1__LCD_EN CYREG_PRT6_LCD_EN
-#define SCSI_Out_DBx__DB1__MASK 0x20u
-#define SCSI_Out_DBx__DB1__PC CYREG_PRT6_PC5
-#define SCSI_Out_DBx__DB1__PORT 6u
-#define SCSI_Out_DBx__DB1__PRT CYREG_PRT6_PRT
-#define SCSI_Out_DBx__DB1__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
-#define SCSI_Out_DBx__DB1__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
-#define SCSI_Out_DBx__DB1__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
-#define SCSI_Out_DBx__DB1__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
-#define SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
-#define SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
-#define SCSI_Out_DBx__DB1__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
-#define SCSI_Out_DBx__DB1__PS CYREG_PRT6_PS
-#define SCSI_Out_DBx__DB1__SHIFT 5u
-#define SCSI_Out_DBx__DB1__SLW CYREG_PRT6_SLW
-#define SCSI_Out_DBx__DB2__AG CYREG_PRT12_AG
-#define SCSI_Out_DBx__DB2__BIE CYREG_PRT12_BIE
-#define SCSI_Out_DBx__DB2__BIT_MASK CYREG_PRT12_BIT_MASK
-#define SCSI_Out_DBx__DB2__BYP CYREG_PRT12_BYP
-#define SCSI_Out_DBx__DB2__DM0 CYREG_PRT12_DM0
-#define SCSI_Out_DBx__DB2__DM1 CYREG_PRT12_DM1
-#define SCSI_Out_DBx__DB2__DM2 CYREG_PRT12_DM2
-#define SCSI_Out_DBx__DB2__DR CYREG_PRT12_DR
-#define SCSI_Out_DBx__DB2__INP_DIS CYREG_PRT12_INP_DIS
-#define SCSI_Out_DBx__DB2__INTTYPE CYREG_PICU12_INTTYPE5
-#define SCSI_Out_DBx__DB2__MASK 0x20u
-#define SCSI_Out_DBx__DB2__PC CYREG_PRT12_PC5
-#define SCSI_Out_DBx__DB2__PORT 12u
-#define SCSI_Out_DBx__DB2__PRT CYREG_PRT12_PRT
-#define SCSI_Out_DBx__DB2__PRTDSI__DBL_SYNC_IN CYREG_PRT12_DBL_SYNC_IN
-#define SCSI_Out_DBx__DB2__PRTDSI__OE_SEL0 CYREG_PRT12_OE_SEL0
-#define SCSI_Out_DBx__DB2__PRTDSI__OE_SEL1 CYREG_PRT12_OE_SEL1
-#define SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL0 CYREG_PRT12_OUT_SEL0
-#define SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL1 CYREG_PRT12_OUT_SEL1
-#define SCSI_Out_DBx__DB2__PRTDSI__SYNC_OUT CYREG_PRT12_SYNC_OUT
-#define SCSI_Out_DBx__DB2__PS CYREG_PRT12_PS
-#define SCSI_Out_DBx__DB2__SHIFT 5u
-#define SCSI_Out_DBx__DB2__SIO_CFG CYREG_PRT12_SIO_CFG
-#define SCSI_Out_DBx__DB2__SIO_DIFF CYREG_PRT12_SIO_DIFF
-#define SCSI_Out_DBx__DB2__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN
-#define SCSI_Out_DBx__DB2__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ
-#define SCSI_Out_DBx__DB2__SLW CYREG_PRT12_SLW
-#define SCSI_Out_DBx__DB3__AG CYREG_PRT2_AG
-#define SCSI_Out_DBx__DB3__AMUX CYREG_PRT2_AMUX
-#define SCSI_Out_DBx__DB3__BIE CYREG_PRT2_BIE
-#define SCSI_Out_DBx__DB3__BIT_MASK CYREG_PRT2_BIT_MASK
-#define SCSI_Out_DBx__DB3__BYP CYREG_PRT2_BYP
-#define SCSI_Out_DBx__DB3__CTL CYREG_PRT2_CTL
-#define SCSI_Out_DBx__DB3__DM0 CYREG_PRT2_DM0
-#define SCSI_Out_DBx__DB3__DM1 CYREG_PRT2_DM1
-#define SCSI_Out_DBx__DB3__DM2 CYREG_PRT2_DM2
-#define SCSI_Out_DBx__DB3__DR CYREG_PRT2_DR
-#define SCSI_Out_DBx__DB3__INP_DIS CYREG_PRT2_INP_DIS
-#define SCSI_Out_DBx__DB3__INTTYPE CYREG_PICU2_INTTYPE7
-#define SCSI_Out_DBx__DB3__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
-#define SCSI_Out_DBx__DB3__LCD_EN CYREG_PRT2_LCD_EN
-#define SCSI_Out_DBx__DB3__MASK 0x80u
-#define SCSI_Out_DBx__DB3__PC CYREG_PRT2_PC7
-#define SCSI_Out_DBx__DB3__PORT 2u
-#define SCSI_Out_DBx__DB3__PRT CYREG_PRT2_PRT
-#define SCSI_Out_DBx__DB3__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
-#define SCSI_Out_DBx__DB3__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
-#define SCSI_Out_DBx__DB3__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
-#define SCSI_Out_DBx__DB3__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
-#define SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
-#define SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
-#define SCSI_Out_DBx__DB3__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
-#define SCSI_Out_DBx__DB3__PS CYREG_PRT2_PS
-#define SCSI_Out_DBx__DB3__SHIFT 7u
-#define SCSI_Out_DBx__DB3__SLW CYREG_PRT2_SLW
-#define SCSI_Out_DBx__DB4__AG CYREG_PRT2_AG
-#define SCSI_Out_DBx__DB4__AMUX CYREG_PRT2_AMUX
-#define SCSI_Out_DBx__DB4__BIE CYREG_PRT2_BIE
-#define SCSI_Out_DBx__DB4__BIT_MASK CYREG_PRT2_BIT_MASK
-#define SCSI_Out_DBx__DB4__BYP CYREG_PRT2_BYP
-#define SCSI_Out_DBx__DB4__CTL CYREG_PRT2_CTL
-#define SCSI_Out_DBx__DB4__DM0 CYREG_PRT2_DM0
-#define SCSI_Out_DBx__DB4__DM1 CYREG_PRT2_DM1
-#define SCSI_Out_DBx__DB4__DM2 CYREG_PRT2_DM2
-#define SCSI_Out_DBx__DB4__DR CYREG_PRT2_DR
-#define SCSI_Out_DBx__DB4__INP_DIS CYREG_PRT2_INP_DIS
-#define SCSI_Out_DBx__DB4__INTTYPE CYREG_PICU2_INTTYPE5
-#define SCSI_Out_DBx__DB4__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
-#define SCSI_Out_DBx__DB4__LCD_EN CYREG_PRT2_LCD_EN
-#define SCSI_Out_DBx__DB4__MASK 0x20u
-#define SCSI_Out_DBx__DB4__PC CYREG_PRT2_PC5
-#define SCSI_Out_DBx__DB4__PORT 2u
-#define SCSI_Out_DBx__DB4__PRT CYREG_PRT2_PRT
-#define SCSI_Out_DBx__DB4__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
-#define SCSI_Out_DBx__DB4__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
-#define SCSI_Out_DBx__DB4__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
-#define SCSI_Out_DBx__DB4__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
-#define SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
-#define SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
-#define SCSI_Out_DBx__DB4__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
-#define SCSI_Out_DBx__DB4__PS CYREG_PRT2_PS
-#define SCSI_Out_DBx__DB4__SHIFT 5u
-#define SCSI_Out_DBx__DB4__SLW CYREG_PRT2_SLW
-#define SCSI_Out_DBx__DB5__AG CYREG_PRT2_AG
-#define SCSI_Out_DBx__DB5__AMUX CYREG_PRT2_AMUX
-#define SCSI_Out_DBx__DB5__BIE CYREG_PRT2_BIE
-#define SCSI_Out_DBx__DB5__BIT_MASK CYREG_PRT2_BIT_MASK
-#define SCSI_Out_DBx__DB5__BYP CYREG_PRT2_BYP
-#define SCSI_Out_DBx__DB5__CTL CYREG_PRT2_CTL
-#define SCSI_Out_DBx__DB5__DM0 CYREG_PRT2_DM0
-#define SCSI_Out_DBx__DB5__DM1 CYREG_PRT2_DM1
-#define SCSI_Out_DBx__DB5__DM2 CYREG_PRT2_DM2
-#define SCSI_Out_DBx__DB5__DR CYREG_PRT2_DR
-#define SCSI_Out_DBx__DB5__INP_DIS CYREG_PRT2_INP_DIS
-#define SCSI_Out_DBx__DB5__INTTYPE CYREG_PICU2_INTTYPE3
-#define SCSI_Out_DBx__DB5__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
-#define SCSI_Out_DBx__DB5__LCD_EN CYREG_PRT2_LCD_EN
-#define SCSI_Out_DBx__DB5__MASK 0x08u
-#define SCSI_Out_DBx__DB5__PC CYREG_PRT2_PC3
-#define SCSI_Out_DBx__DB5__PORT 2u
-#define SCSI_Out_DBx__DB5__PRT CYREG_PRT2_PRT
-#define SCSI_Out_DBx__DB5__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
-#define SCSI_Out_DBx__DB5__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
-#define SCSI_Out_DBx__DB5__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
-#define SCSI_Out_DBx__DB5__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
-#define SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
-#define SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
-#define SCSI_Out_DBx__DB5__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
-#define SCSI_Out_DBx__DB5__PS CYREG_PRT2_PS
-#define SCSI_Out_DBx__DB5__SHIFT 3u
-#define SCSI_Out_DBx__DB5__SLW CYREG_PRT2_SLW
-#define SCSI_Out_DBx__DB6__AG CYREG_PRT2_AG
-#define SCSI_Out_DBx__DB6__AMUX CYREG_PRT2_AMUX
-#define SCSI_Out_DBx__DB6__BIE CYREG_PRT2_BIE
-#define SCSI_Out_DBx__DB6__BIT_MASK CYREG_PRT2_BIT_MASK
-#define SCSI_Out_DBx__DB6__BYP CYREG_PRT2_BYP
-#define SCSI_Out_DBx__DB6__CTL CYREG_PRT2_CTL
-#define SCSI_Out_DBx__DB6__DM0 CYREG_PRT2_DM0
-#define SCSI_Out_DBx__DB6__DM1 CYREG_PRT2_DM1
-#define SCSI_Out_DBx__DB6__DM2 CYREG_PRT2_DM2
-#define SCSI_Out_DBx__DB6__DR CYREG_PRT2_DR
-#define SCSI_Out_DBx__DB6__INP_DIS CYREG_PRT2_INP_DIS
-#define SCSI_Out_DBx__DB6__INTTYPE CYREG_PICU2_INTTYPE1
-#define SCSI_Out_DBx__DB6__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
-#define SCSI_Out_DBx__DB6__LCD_EN CYREG_PRT2_LCD_EN
-#define SCSI_Out_DBx__DB6__MASK 0x02u
-#define SCSI_Out_DBx__DB6__PC CYREG_PRT2_PC1
-#define SCSI_Out_DBx__DB6__PORT 2u
-#define SCSI_Out_DBx__DB6__PRT CYREG_PRT2_PRT
-#define SCSI_Out_DBx__DB6__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
-#define SCSI_Out_DBx__DB6__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
-#define SCSI_Out_DBx__DB6__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
-#define SCSI_Out_DBx__DB6__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
-#define SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
-#define SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
-#define SCSI_Out_DBx__DB6__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
-#define SCSI_Out_DBx__DB6__PS CYREG_PRT2_PS
-#define SCSI_Out_DBx__DB6__SHIFT 1u
-#define SCSI_Out_DBx__DB6__SLW CYREG_PRT2_SLW
-#define SCSI_Out_DBx__DB7__AG CYREG_PRT15_AG
-#define SCSI_Out_DBx__DB7__AMUX CYREG_PRT15_AMUX
-#define SCSI_Out_DBx__DB7__BIE CYREG_PRT15_BIE
-#define SCSI_Out_DBx__DB7__BIT_MASK CYREG_PRT15_BIT_MASK
-#define SCSI_Out_DBx__DB7__BYP CYREG_PRT15_BYP
-#define SCSI_Out_DBx__DB7__CTL CYREG_PRT15_CTL
-#define SCSI_Out_DBx__DB7__DM0 CYREG_PRT15_DM0
-#define SCSI_Out_DBx__DB7__DM1 CYREG_PRT15_DM1
-#define SCSI_Out_DBx__DB7__DM2 CYREG_PRT15_DM2
-#define SCSI_Out_DBx__DB7__DR CYREG_PRT15_DR
-#define SCSI_Out_DBx__DB7__INP_DIS CYREG_PRT15_INP_DIS
-#define SCSI_Out_DBx__DB7__INTTYPE CYREG_PICU15_INTTYPE5
-#define SCSI_Out_DBx__DB7__LCD_COM_SEG CYREG_PRT15_LCD_COM_SEG
-#define SCSI_Out_DBx__DB7__LCD_EN CYREG_PRT15_LCD_EN
-#define SCSI_Out_DBx__DB7__MASK 0x20u
-#define SCSI_Out_DBx__DB7__PC CYREG_IO_PC_PRT15_PC5
-#define SCSI_Out_DBx__DB7__PORT 15u
-#define SCSI_Out_DBx__DB7__PRT CYREG_PRT15_PRT
-#define SCSI_Out_DBx__DB7__PRTDSI__CAPS_SEL CYREG_PRT15_CAPS_SEL
-#define SCSI_Out_DBx__DB7__PRTDSI__DBL_SYNC_IN CYREG_PRT15_DBL_SYNC_IN
-#define SCSI_Out_DBx__DB7__PRTDSI__OE_SEL0 CYREG_PRT15_OE_SEL0
-#define SCSI_Out_DBx__DB7__PRTDSI__OE_SEL1 CYREG_PRT15_OE_SEL1
-#define SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL0 CYREG_PRT15_OUT_SEL0
-#define SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL1 CYREG_PRT15_OUT_SEL1
-#define SCSI_Out_DBx__DB7__PRTDSI__SYNC_OUT CYREG_PRT15_SYNC_OUT
-#define SCSI_Out_DBx__DB7__PS CYREG_PRT15_PS
-#define SCSI_Out_DBx__DB7__SHIFT 5u
-#define SCSI_Out_DBx__DB7__SLW CYREG_PRT15_SLW
-
-/* SD_RX_DMA */
-#define SD_RX_DMA__DRQ_CTL CYREG_IDMUX_DRQ_CTL0
-#define SD_RX_DMA__DRQ_NUMBER 2u
-#define SD_RX_DMA__NUMBEROF_TDS 0u
-#define SD_RX_DMA__PRIORITY 0u
-#define SD_RX_DMA__TERMIN_EN 0u
-#define SD_RX_DMA__TERMIN_SEL 0u
-#define SD_RX_DMA__TERMOUT0_EN 1u
-#define SD_RX_DMA__TERMOUT0_SEL 2u
-#define SD_RX_DMA__TERMOUT1_EN 0u
-#define SD_RX_DMA__TERMOUT1_SEL 0u
-
-/* SD_RX_DMA_COMPLETE */
-#define SD_RX_DMA_COMPLETE__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
-#define SD_RX_DMA_COMPLETE__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
-#define SD_RX_DMA_COMPLETE__INTC_MASK 0x20u
-#define SD_RX_DMA_COMPLETE__INTC_NUMBER 5u
-#define SD_RX_DMA_COMPLETE__INTC_PRIOR_NUM 7u
-#define SD_RX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_5
-#define SD_RX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0
-#define SD_RX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
-
-/* SD_TX_DMA */
-#define SD_TX_DMA__DRQ_CTL CYREG_IDMUX_DRQ_CTL0
-#define SD_TX_DMA__DRQ_NUMBER 3u
-#define SD_TX_DMA__NUMBEROF_TDS 0u
-#define SD_TX_DMA__PRIORITY 1u
-#define SD_TX_DMA__TERMIN_EN 0u
-#define SD_TX_DMA__TERMIN_SEL 0u
-#define SD_TX_DMA__TERMOUT0_EN 1u
-#define SD_TX_DMA__TERMOUT0_SEL 3u
-#define SD_TX_DMA__TERMOUT1_EN 0u
-#define SD_TX_DMA__TERMOUT1_SEL 0u
-
-/* SD_TX_DMA_COMPLETE */
-#define SD_TX_DMA_COMPLETE__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
-#define SD_TX_DMA_COMPLETE__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
-#define SD_TX_DMA_COMPLETE__INTC_MASK 0x40u
-#define SD_TX_DMA_COMPLETE__INTC_NUMBER 6u
-#define SD_TX_DMA_COMPLETE__INTC_PRIOR_NUM 7u
-#define SD_TX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_6
-#define SD_TX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0
-#define SD_TX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
+/* SCSI_In */
+#define SCSI_In__0__INTTYPE CYREG_PICU6_INTTYPE1
+#define SCSI_In__0__MASK 0x02u
+#define SCSI_In__0__PC CYREG_PRT6_PC1
+#define SCSI_In__0__PORT 6u
+#define SCSI_In__0__SHIFT 1u
+#define SCSI_In__AG CYREG_PRT6_AG
+#define SCSI_In__AMUX CYREG_PRT6_AMUX
+#define SCSI_In__BIE CYREG_PRT6_BIE
+#define SCSI_In__BIT_MASK CYREG_PRT6_BIT_MASK
+#define SCSI_In__BYP CYREG_PRT6_BYP
+#define SCSI_In__CTL CYREG_PRT6_CTL
+#define SCSI_In__DBP__INTTYPE CYREG_PICU6_INTTYPE1
+#define SCSI_In__DBP__MASK 0x02u
+#define SCSI_In__DBP__PC CYREG_PRT6_PC1
+#define SCSI_In__DBP__PORT 6u
+#define SCSI_In__DBP__SHIFT 1u
+#define SCSI_In__DM0 CYREG_PRT6_DM0
+#define SCSI_In__DM1 CYREG_PRT6_DM1
+#define SCSI_In__DM2 CYREG_PRT6_DM2
+#define SCSI_In__DR CYREG_PRT6_DR
+#define SCSI_In__INP_DIS CYREG_PRT6_INP_DIS
+#define SCSI_In__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU6_BASE
+#define SCSI_In__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
+#define SCSI_In__LCD_EN CYREG_PRT6_LCD_EN
+#define SCSI_In__MASK 0x02u
+#define SCSI_In__PORT 6u
+#define SCSI_In__PRT CYREG_PRT6_PRT
+#define SCSI_In__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
+#define SCSI_In__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
+#define SCSI_In__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
+#define SCSI_In__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
+#define SCSI_In__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
+#define SCSI_In__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
+#define SCSI_In__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
+#define SCSI_In__PS CYREG_PRT6_PS
+#define SCSI_In__SHIFT 1u
+#define SCSI_In__SLW CYREG_PRT6_SLW
+#define SCSI_In_DBx__0__AG CYREG_PRT6_AG
+#define SCSI_In_DBx__0__AMUX CYREG_PRT6_AMUX
+#define SCSI_In_DBx__0__BIE CYREG_PRT6_BIE
+#define SCSI_In_DBx__0__BIT_MASK CYREG_PRT6_BIT_MASK
+#define SCSI_In_DBx__0__BYP CYREG_PRT6_BYP
+#define SCSI_In_DBx__0__CTL CYREG_PRT6_CTL
+#define SCSI_In_DBx__0__DM0 CYREG_PRT6_DM0
+#define SCSI_In_DBx__0__DM1 CYREG_PRT6_DM1
+#define SCSI_In_DBx__0__DM2 CYREG_PRT6_DM2
+#define SCSI_In_DBx__0__DR CYREG_PRT6_DR
+#define SCSI_In_DBx__0__INP_DIS CYREG_PRT6_INP_DIS
+#define SCSI_In_DBx__0__INTTYPE CYREG_PICU6_INTTYPE6
+#define SCSI_In_DBx__0__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
+#define SCSI_In_DBx__0__LCD_EN CYREG_PRT6_LCD_EN
+#define SCSI_In_DBx__0__MASK 0x40u
+#define SCSI_In_DBx__0__PC CYREG_PRT6_PC6
+#define SCSI_In_DBx__0__PORT 6u
+#define SCSI_In_DBx__0__PRT CYREG_PRT6_PRT
+#define SCSI_In_DBx__0__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
+#define SCSI_In_DBx__0__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
+#define SCSI_In_DBx__0__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
+#define SCSI_In_DBx__0__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
+#define SCSI_In_DBx__0__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
+#define SCSI_In_DBx__0__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
+#define SCSI_In_DBx__0__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
+#define SCSI_In_DBx__0__PS CYREG_PRT6_PS
+#define SCSI_In_DBx__0__SHIFT 6u
+#define SCSI_In_DBx__0__SLW CYREG_PRT6_SLW
+#define SCSI_In_DBx__1__AG CYREG_PRT6_AG
+#define SCSI_In_DBx__1__AMUX CYREG_PRT6_AMUX
+#define SCSI_In_DBx__1__BIE CYREG_PRT6_BIE
+#define SCSI_In_DBx__1__BIT_MASK CYREG_PRT6_BIT_MASK
+#define SCSI_In_DBx__1__BYP CYREG_PRT6_BYP
+#define SCSI_In_DBx__1__CTL CYREG_PRT6_CTL
+#define SCSI_In_DBx__1__DM0 CYREG_PRT6_DM0
+#define SCSI_In_DBx__1__DM1 CYREG_PRT6_DM1
+#define SCSI_In_DBx__1__DM2 CYREG_PRT6_DM2
+#define SCSI_In_DBx__1__DR CYREG_PRT6_DR
+#define SCSI_In_DBx__1__INP_DIS CYREG_PRT6_INP_DIS
+#define SCSI_In_DBx__1__INTTYPE CYREG_PICU6_INTTYPE4
+#define SCSI_In_DBx__1__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
+#define SCSI_In_DBx__1__LCD_EN CYREG_PRT6_LCD_EN
+#define SCSI_In_DBx__1__MASK 0x10u
+#define SCSI_In_DBx__1__PC CYREG_PRT6_PC4
+#define SCSI_In_DBx__1__PORT 6u
+#define SCSI_In_DBx__1__PRT CYREG_PRT6_PRT
+#define SCSI_In_DBx__1__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
+#define SCSI_In_DBx__1__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
+#define SCSI_In_DBx__1__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
+#define SCSI_In_DBx__1__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
+#define SCSI_In_DBx__1__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
+#define SCSI_In_DBx__1__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
+#define SCSI_In_DBx__1__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
+#define SCSI_In_DBx__1__PS CYREG_PRT6_PS
+#define SCSI_In_DBx__1__SHIFT 4u
+#define SCSI_In_DBx__1__SLW CYREG_PRT6_SLW
+#define SCSI_In_DBx__2__AG CYREG_PRT12_AG
+#define SCSI_In_DBx__2__BIE CYREG_PRT12_BIE
+#define SCSI_In_DBx__2__BIT_MASK CYREG_PRT12_BIT_MASK
+#define SCSI_In_DBx__2__BYP CYREG_PRT12_BYP
+#define SCSI_In_DBx__2__DM0 CYREG_PRT12_DM0
+#define SCSI_In_DBx__2__DM1 CYREG_PRT12_DM1
+#define SCSI_In_DBx__2__DM2 CYREG_PRT12_DM2
+#define SCSI_In_DBx__2__DR CYREG_PRT12_DR
+#define SCSI_In_DBx__2__INP_DIS CYREG_PRT12_INP_DIS
+#define SCSI_In_DBx__2__INTTYPE CYREG_PICU12_INTTYPE4
+#define SCSI_In_DBx__2__MASK 0x10u
+#define SCSI_In_DBx__2__PC CYREG_PRT12_PC4
+#define SCSI_In_DBx__2__PORT 12u
+#define SCSI_In_DBx__2__PRT CYREG_PRT12_PRT
+#define SCSI_In_DBx__2__PRTDSI__DBL_SYNC_IN CYREG_PRT12_DBL_SYNC_IN
+#define SCSI_In_DBx__2__PRTDSI__OE_SEL0 CYREG_PRT12_OE_SEL0
+#define SCSI_In_DBx__2__PRTDSI__OE_SEL1 CYREG_PRT12_OE_SEL1
+#define SCSI_In_DBx__2__PRTDSI__OUT_SEL0 CYREG_PRT12_OUT_SEL0
+#define SCSI_In_DBx__2__PRTDSI__OUT_SEL1 CYREG_PRT12_OUT_SEL1
+#define SCSI_In_DBx__2__PRTDSI__SYNC_OUT CYREG_PRT12_SYNC_OUT
+#define SCSI_In_DBx__2__PS CYREG_PRT12_PS
+#define SCSI_In_DBx__2__SHIFT 4u
+#define SCSI_In_DBx__2__SIO_CFG CYREG_PRT12_SIO_CFG
+#define SCSI_In_DBx__2__SIO_DIFF CYREG_PRT12_SIO_DIFF
+#define SCSI_In_DBx__2__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN
+#define SCSI_In_DBx__2__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ
+#define SCSI_In_DBx__2__SLW CYREG_PRT12_SLW
+#define SCSI_In_DBx__3__AG CYREG_PRT2_AG
+#define SCSI_In_DBx__3__AMUX CYREG_PRT2_AMUX
+#define SCSI_In_DBx__3__BIE CYREG_PRT2_BIE
+#define SCSI_In_DBx__3__BIT_MASK CYREG_PRT2_BIT_MASK
+#define SCSI_In_DBx__3__BYP CYREG_PRT2_BYP
+#define SCSI_In_DBx__3__CTL CYREG_PRT2_CTL
+#define SCSI_In_DBx__3__DM0 CYREG_PRT2_DM0
+#define SCSI_In_DBx__3__DM1 CYREG_PRT2_DM1
+#define SCSI_In_DBx__3__DM2 CYREG_PRT2_DM2
+#define SCSI_In_DBx__3__DR CYREG_PRT2_DR
+#define SCSI_In_DBx__3__INP_DIS CYREG_PRT2_INP_DIS
+#define SCSI_In_DBx__3__INTTYPE CYREG_PICU2_INTTYPE6
+#define SCSI_In_DBx__3__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
+#define SCSI_In_DBx__3__LCD_EN CYREG_PRT2_LCD_EN
+#define SCSI_In_DBx__3__MASK 0x40u
+#define SCSI_In_DBx__3__PC CYREG_PRT2_PC6
+#define SCSI_In_DBx__3__PORT 2u
+#define SCSI_In_DBx__3__PRT CYREG_PRT2_PRT
+#define SCSI_In_DBx__3__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
+#define SCSI_In_DBx__3__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
+#define SCSI_In_DBx__3__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
+#define SCSI_In_DBx__3__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
+#define SCSI_In_DBx__3__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
+#define SCSI_In_DBx__3__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
+#define SCSI_In_DBx__3__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
+#define SCSI_In_DBx__3__PS CYREG_PRT2_PS
+#define SCSI_In_DBx__3__SHIFT 6u
+#define SCSI_In_DBx__3__SLW CYREG_PRT2_SLW
+#define SCSI_In_DBx__4__AG CYREG_PRT2_AG
+#define SCSI_In_DBx__4__AMUX CYREG_PRT2_AMUX
+#define SCSI_In_DBx__4__BIE CYREG_PRT2_BIE
+#define SCSI_In_DBx__4__BIT_MASK CYREG_PRT2_BIT_MASK
+#define SCSI_In_DBx__4__BYP CYREG_PRT2_BYP
+#define SCSI_In_DBx__4__CTL CYREG_PRT2_CTL
+#define SCSI_In_DBx__4__DM0 CYREG_PRT2_DM0
+#define SCSI_In_DBx__4__DM1 CYREG_PRT2_DM1
+#define SCSI_In_DBx__4__DM2 CYREG_PRT2_DM2
+#define SCSI_In_DBx__4__DR CYREG_PRT2_DR
+#define SCSI_In_DBx__4__INP_DIS CYREG_PRT2_INP_DIS
+#define SCSI_In_DBx__4__INTTYPE CYREG_PICU2_INTTYPE4
+#define SCSI_In_DBx__4__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
+#define SCSI_In_DBx__4__LCD_EN CYREG_PRT2_LCD_EN
+#define SCSI_In_DBx__4__MASK 0x10u
+#define SCSI_In_DBx__4__PC CYREG_PRT2_PC4
+#define SCSI_In_DBx__4__PORT 2u
+#define SCSI_In_DBx__4__PRT CYREG_PRT2_PRT
+#define SCSI_In_DBx__4__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
+#define SCSI_In_DBx__4__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
+#define SCSI_In_DBx__4__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
+#define SCSI_In_DBx__4__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
+#define SCSI_In_DBx__4__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
+#define SCSI_In_DBx__4__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
+#define SCSI_In_DBx__4__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
+#define SCSI_In_DBx__4__PS CYREG_PRT2_PS
+#define SCSI_In_DBx__4__SHIFT 4u
+#define SCSI_In_DBx__4__SLW CYREG_PRT2_SLW
+#define SCSI_In_DBx__5__AG CYREG_PRT2_AG
+#define SCSI_In_DBx__5__AMUX CYREG_PRT2_AMUX
+#define SCSI_In_DBx__5__BIE CYREG_PRT2_BIE
+#define SCSI_In_DBx__5__BIT_MASK CYREG_PRT2_BIT_MASK
+#define SCSI_In_DBx__5__BYP CYREG_PRT2_BYP
+#define SCSI_In_DBx__5__CTL CYREG_PRT2_CTL
+#define SCSI_In_DBx__5__DM0 CYREG_PRT2_DM0
+#define SCSI_In_DBx__5__DM1 CYREG_PRT2_DM1
+#define SCSI_In_DBx__5__DM2 CYREG_PRT2_DM2
+#define SCSI_In_DBx__5__DR CYREG_PRT2_DR
+#define SCSI_In_DBx__5__INP_DIS CYREG_PRT2_INP_DIS
+#define SCSI_In_DBx__5__INTTYPE CYREG_PICU2_INTTYPE2
+#define SCSI_In_DBx__5__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
+#define SCSI_In_DBx__5__LCD_EN CYREG_PRT2_LCD_EN
+#define SCSI_In_DBx__5__MASK 0x04u
+#define SCSI_In_DBx__5__PC CYREG_PRT2_PC2
+#define SCSI_In_DBx__5__PORT 2u
+#define SCSI_In_DBx__5__PRT CYREG_PRT2_PRT
+#define SCSI_In_DBx__5__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
+#define SCSI_In_DBx__5__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
+#define SCSI_In_DBx__5__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
+#define SCSI_In_DBx__5__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
+#define SCSI_In_DBx__5__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
+#define SCSI_In_DBx__5__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
+#define SCSI_In_DBx__5__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
+#define SCSI_In_DBx__5__PS CYREG_PRT2_PS
+#define SCSI_In_DBx__5__SHIFT 2u
+#define SCSI_In_DBx__5__SLW CYREG_PRT2_SLW
+#define SCSI_In_DBx__6__AG CYREG_PRT2_AG
+#define SCSI_In_DBx__6__AMUX CYREG_PRT2_AMUX
+#define SCSI_In_DBx__6__BIE CYREG_PRT2_BIE
+#define SCSI_In_DBx__6__BIT_MASK CYREG_PRT2_BIT_MASK
+#define SCSI_In_DBx__6__BYP CYREG_PRT2_BYP
+#define SCSI_In_DBx__6__CTL CYREG_PRT2_CTL
+#define SCSI_In_DBx__6__DM0 CYREG_PRT2_DM0
+#define SCSI_In_DBx__6__DM1 CYREG_PRT2_DM1
+#define SCSI_In_DBx__6__DM2 CYREG_PRT2_DM2
+#define SCSI_In_DBx__6__DR CYREG_PRT2_DR
+#define SCSI_In_DBx__6__INP_DIS CYREG_PRT2_INP_DIS
+#define SCSI_In_DBx__6__INTTYPE CYREG_PICU2_INTTYPE0
+#define SCSI_In_DBx__6__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
+#define SCSI_In_DBx__6__LCD_EN CYREG_PRT2_LCD_EN
+#define SCSI_In_DBx__6__MASK 0x01u
+#define SCSI_In_DBx__6__PC CYREG_PRT2_PC0
+#define SCSI_In_DBx__6__PORT 2u
+#define SCSI_In_DBx__6__PRT CYREG_PRT2_PRT
+#define SCSI_In_DBx__6__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
+#define SCSI_In_DBx__6__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
+#define SCSI_In_DBx__6__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
+#define SCSI_In_DBx__6__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
+#define SCSI_In_DBx__6__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
+#define SCSI_In_DBx__6__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
+#define SCSI_In_DBx__6__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
+#define SCSI_In_DBx__6__PS CYREG_PRT2_PS
+#define SCSI_In_DBx__6__SHIFT 0u
+#define SCSI_In_DBx__6__SLW CYREG_PRT2_SLW
+#define SCSI_In_DBx__7__AG CYREG_PRT6_AG
+#define SCSI_In_DBx__7__AMUX CYREG_PRT6_AMUX
+#define SCSI_In_DBx__7__BIE CYREG_PRT6_BIE
+#define SCSI_In_DBx__7__BIT_MASK CYREG_PRT6_BIT_MASK
+#define SCSI_In_DBx__7__BYP CYREG_PRT6_BYP
+#define SCSI_In_DBx__7__CTL CYREG_PRT6_CTL
+#define SCSI_In_DBx__7__DM0 CYREG_PRT6_DM0
+#define SCSI_In_DBx__7__DM1 CYREG_PRT6_DM1
+#define SCSI_In_DBx__7__DM2 CYREG_PRT6_DM2
+#define SCSI_In_DBx__7__DR CYREG_PRT6_DR
+#define SCSI_In_DBx__7__INP_DIS CYREG_PRT6_INP_DIS
+#define SCSI_In_DBx__7__INTTYPE CYREG_PICU6_INTTYPE3
+#define SCSI_In_DBx__7__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
+#define SCSI_In_DBx__7__LCD_EN CYREG_PRT6_LCD_EN
+#define SCSI_In_DBx__7__MASK 0x08u
+#define SCSI_In_DBx__7__PC CYREG_PRT6_PC3
+#define SCSI_In_DBx__7__PORT 6u
+#define SCSI_In_DBx__7__PRT CYREG_PRT6_PRT
+#define SCSI_In_DBx__7__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
+#define SCSI_In_DBx__7__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
+#define SCSI_In_DBx__7__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
+#define SCSI_In_DBx__7__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
+#define SCSI_In_DBx__7__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
+#define SCSI_In_DBx__7__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
+#define SCSI_In_DBx__7__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
+#define SCSI_In_DBx__7__PS CYREG_PRT6_PS
+#define SCSI_In_DBx__7__SHIFT 3u
+#define SCSI_In_DBx__7__SLW CYREG_PRT6_SLW
+#define SCSI_In_DBx__DB0__AG CYREG_PRT6_AG
+#define SCSI_In_DBx__DB0__AMUX CYREG_PRT6_AMUX
+#define SCSI_In_DBx__DB0__BIE CYREG_PRT6_BIE
+#define SCSI_In_DBx__DB0__BIT_MASK CYREG_PRT6_BIT_MASK
+#define SCSI_In_DBx__DB0__BYP CYREG_PRT6_BYP
+#define SCSI_In_DBx__DB0__CTL CYREG_PRT6_CTL
+#define SCSI_In_DBx__DB0__DM0 CYREG_PRT6_DM0
+#define SCSI_In_DBx__DB0__DM1 CYREG_PRT6_DM1
+#define SCSI_In_DBx__DB0__DM2 CYREG_PRT6_DM2
+#define SCSI_In_DBx__DB0__DR CYREG_PRT6_DR
+#define SCSI_In_DBx__DB0__INP_DIS CYREG_PRT6_INP_DIS
+#define SCSI_In_DBx__DB0__INTTYPE CYREG_PICU6_INTTYPE6
+#define SCSI_In_DBx__DB0__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
+#define SCSI_In_DBx__DB0__LCD_EN CYREG_PRT6_LCD_EN
+#define SCSI_In_DBx__DB0__MASK 0x40u
+#define SCSI_In_DBx__DB0__PC CYREG_PRT6_PC6
+#define SCSI_In_DBx__DB0__PORT 6u
+#define SCSI_In_DBx__DB0__PRT CYREG_PRT6_PRT
+#define SCSI_In_DBx__DB0__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
+#define SCSI_In_DBx__DB0__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
+#define SCSI_In_DBx__DB0__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
+#define SCSI_In_DBx__DB0__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
+#define SCSI_In_DBx__DB0__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
+#define SCSI_In_DBx__DB0__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
+#define SCSI_In_DBx__DB0__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
+#define SCSI_In_DBx__DB0__PS CYREG_PRT6_PS
+#define SCSI_In_DBx__DB0__SHIFT 6u
+#define SCSI_In_DBx__DB0__SLW CYREG_PRT6_SLW
+#define SCSI_In_DBx__DB1__AG CYREG_PRT6_AG
+#define SCSI_In_DBx__DB1__AMUX CYREG_PRT6_AMUX
+#define SCSI_In_DBx__DB1__BIE CYREG_PRT6_BIE
+#define SCSI_In_DBx__DB1__BIT_MASK CYREG_PRT6_BIT_MASK
+#define SCSI_In_DBx__DB1__BYP CYREG_PRT6_BYP
+#define SCSI_In_DBx__DB1__CTL CYREG_PRT6_CTL
+#define SCSI_In_DBx__DB1__DM0 CYREG_PRT6_DM0
+#define SCSI_In_DBx__DB1__DM1 CYREG_PRT6_DM1
+#define SCSI_In_DBx__DB1__DM2 CYREG_PRT6_DM2
+#define SCSI_In_DBx__DB1__DR CYREG_PRT6_DR
+#define SCSI_In_DBx__DB1__INP_DIS CYREG_PRT6_INP_DIS
+#define SCSI_In_DBx__DB1__INTTYPE CYREG_PICU6_INTTYPE4
+#define SCSI_In_DBx__DB1__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
+#define SCSI_In_DBx__DB1__LCD_EN CYREG_PRT6_LCD_EN
+#define SCSI_In_DBx__DB1__MASK 0x10u
+#define SCSI_In_DBx__DB1__PC CYREG_PRT6_PC4
+#define SCSI_In_DBx__DB1__PORT 6u
+#define SCSI_In_DBx__DB1__PRT CYREG_PRT6_PRT
+#define SCSI_In_DBx__DB1__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
+#define SCSI_In_DBx__DB1__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
+#define SCSI_In_DBx__DB1__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
+#define SCSI_In_DBx__DB1__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
+#define SCSI_In_DBx__DB1__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
+#define SCSI_In_DBx__DB1__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
+#define SCSI_In_DBx__DB1__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
+#define SCSI_In_DBx__DB1__PS CYREG_PRT6_PS
+#define SCSI_In_DBx__DB1__SHIFT 4u
+#define SCSI_In_DBx__DB1__SLW CYREG_PRT6_SLW
+#define SCSI_In_DBx__DB2__AG CYREG_PRT12_AG
+#define SCSI_In_DBx__DB2__BIE CYREG_PRT12_BIE
+#define SCSI_In_DBx__DB2__BIT_MASK CYREG_PRT12_BIT_MASK
+#define SCSI_In_DBx__DB2__BYP CYREG_PRT12_BYP
+#define SCSI_In_DBx__DB2__DM0 CYREG_PRT12_DM0
+#define SCSI_In_DBx__DB2__DM1 CYREG_PRT12_DM1
+#define SCSI_In_DBx__DB2__DM2 CYREG_PRT12_DM2
+#define SCSI_In_DBx__DB2__DR CYREG_PRT12_DR
+#define SCSI_In_DBx__DB2__INP_DIS CYREG_PRT12_INP_DIS
+#define SCSI_In_DBx__DB2__INTTYPE CYREG_PICU12_INTTYPE4
+#define SCSI_In_DBx__DB2__MASK 0x10u
+#define SCSI_In_DBx__DB2__PC CYREG_PRT12_PC4
+#define SCSI_In_DBx__DB2__PORT 12u
+#define SCSI_In_DBx__DB2__PRT CYREG_PRT12_PRT
+#define SCSI_In_DBx__DB2__PRTDSI__DBL_SYNC_IN CYREG_PRT12_DBL_SYNC_IN
+#define SCSI_In_DBx__DB2__PRTDSI__OE_SEL0 CYREG_PRT12_OE_SEL0
+#define SCSI_In_DBx__DB2__PRTDSI__OE_SEL1 CYREG_PRT12_OE_SEL1
+#define SCSI_In_DBx__DB2__PRTDSI__OUT_SEL0 CYREG_PRT12_OUT_SEL0
+#define SCSI_In_DBx__DB2__PRTDSI__OUT_SEL1 CYREG_PRT12_OUT_SEL1
+#define SCSI_In_DBx__DB2__PRTDSI__SYNC_OUT CYREG_PRT12_SYNC_OUT
+#define SCSI_In_DBx__DB2__PS CYREG_PRT12_PS
+#define SCSI_In_DBx__DB2__SHIFT 4u
+#define SCSI_In_DBx__DB2__SIO_CFG CYREG_PRT12_SIO_CFG
+#define SCSI_In_DBx__DB2__SIO_DIFF CYREG_PRT12_SIO_DIFF
+#define SCSI_In_DBx__DB2__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN
+#define SCSI_In_DBx__DB2__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ
+#define SCSI_In_DBx__DB2__SLW CYREG_PRT12_SLW
+#define SCSI_In_DBx__DB3__AG CYREG_PRT2_AG
+#define SCSI_In_DBx__DB3__AMUX CYREG_PRT2_AMUX
+#define SCSI_In_DBx__DB3__BIE CYREG_PRT2_BIE
+#define SCSI_In_DBx__DB3__BIT_MASK CYREG_PRT2_BIT_MASK
+#define SCSI_In_DBx__DB3__BYP CYREG_PRT2_BYP
+#define SCSI_In_DBx__DB3__CTL CYREG_PRT2_CTL
+#define SCSI_In_DBx__DB3__DM0 CYREG_PRT2_DM0
+#define SCSI_In_DBx__DB3__DM1 CYREG_PRT2_DM1
+#define SCSI_In_DBx__DB3__DM2 CYREG_PRT2_DM2
+#define SCSI_In_DBx__DB3__DR CYREG_PRT2_DR
+#define SCSI_In_DBx__DB3__INP_DIS CYREG_PRT2_INP_DIS
+#define SCSI_In_DBx__DB3__INTTYPE CYREG_PICU2_INTTYPE6
+#define SCSI_In_DBx__DB3__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
+#define SCSI_In_DBx__DB3__LCD_EN CYREG_PRT2_LCD_EN
+#define SCSI_In_DBx__DB3__MASK 0x40u
+#define SCSI_In_DBx__DB3__PC CYREG_PRT2_PC6
+#define SCSI_In_DBx__DB3__PORT 2u
+#define SCSI_In_DBx__DB3__PRT CYREG_PRT2_PRT
+#define SCSI_In_DBx__DB3__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
+#define SCSI_In_DBx__DB3__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
+#define SCSI_In_DBx__DB3__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
+#define SCSI_In_DBx__DB3__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
+#define SCSI_In_DBx__DB3__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
+#define SCSI_In_DBx__DB3__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
+#define SCSI_In_DBx__DB3__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
+#define SCSI_In_DBx__DB3__PS CYREG_PRT2_PS
+#define SCSI_In_DBx__DB3__SHIFT 6u
+#define SCSI_In_DBx__DB3__SLW CYREG_PRT2_SLW
+#define SCSI_In_DBx__DB4__AG CYREG_PRT2_AG
+#define SCSI_In_DBx__DB4__AMUX CYREG_PRT2_AMUX
+#define SCSI_In_DBx__DB4__BIE CYREG_PRT2_BIE
+#define SCSI_In_DBx__DB4__BIT_MASK CYREG_PRT2_BIT_MASK
+#define SCSI_In_DBx__DB4__BYP CYREG_PRT2_BYP
+#define SCSI_In_DBx__DB4__CTL CYREG_PRT2_CTL
+#define SCSI_In_DBx__DB4__DM0 CYREG_PRT2_DM0
+#define SCSI_In_DBx__DB4__DM1 CYREG_PRT2_DM1
+#define SCSI_In_DBx__DB4__DM2 CYREG_PRT2_DM2
+#define SCSI_In_DBx__DB4__DR CYREG_PRT2_DR
+#define SCSI_In_DBx__DB4__INP_DIS CYREG_PRT2_INP_DIS
+#define SCSI_In_DBx__DB4__INTTYPE CYREG_PICU2_INTTYPE4
+#define SCSI_In_DBx__DB4__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
+#define SCSI_In_DBx__DB4__LCD_EN CYREG_PRT2_LCD_EN
+#define SCSI_In_DBx__DB4__MASK 0x10u
+#define SCSI_In_DBx__DB4__PC CYREG_PRT2_PC4
+#define SCSI_In_DBx__DB4__PORT 2u
+#define SCSI_In_DBx__DB4__PRT CYREG_PRT2_PRT
+#define SCSI_In_DBx__DB4__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
+#define SCSI_In_DBx__DB4__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
+#define SCSI_In_DBx__DB4__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
+#define SCSI_In_DBx__DB4__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
+#define SCSI_In_DBx__DB4__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
+#define SCSI_In_DBx__DB4__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
+#define SCSI_In_DBx__DB4__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
+#define SCSI_In_DBx__DB4__PS CYREG_PRT2_PS
+#define SCSI_In_DBx__DB4__SHIFT 4u
+#define SCSI_In_DBx__DB4__SLW CYREG_PRT2_SLW
+#define SCSI_In_DBx__DB5__AG CYREG_PRT2_AG
+#define SCSI_In_DBx__DB5__AMUX CYREG_PRT2_AMUX
+#define SCSI_In_DBx__DB5__BIE CYREG_PRT2_BIE
+#define SCSI_In_DBx__DB5__BIT_MASK CYREG_PRT2_BIT_MASK
+#define SCSI_In_DBx__DB5__BYP CYREG_PRT2_BYP
+#define SCSI_In_DBx__DB5__CTL CYREG_PRT2_CTL
+#define SCSI_In_DBx__DB5__DM0 CYREG_PRT2_DM0
+#define SCSI_In_DBx__DB5__DM1 CYREG_PRT2_DM1
+#define SCSI_In_DBx__DB5__DM2 CYREG_PRT2_DM2
+#define SCSI_In_DBx__DB5__DR CYREG_PRT2_DR
+#define SCSI_In_DBx__DB5__INP_DIS CYREG_PRT2_INP_DIS
+#define SCSI_In_DBx__DB5__INTTYPE CYREG_PICU2_INTTYPE2
+#define SCSI_In_DBx__DB5__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
+#define SCSI_In_DBx__DB5__LCD_EN CYREG_PRT2_LCD_EN
+#define SCSI_In_DBx__DB5__MASK 0x04u
+#define SCSI_In_DBx__DB5__PC CYREG_PRT2_PC2
+#define SCSI_In_DBx__DB5__PORT 2u
+#define SCSI_In_DBx__DB5__PRT CYREG_PRT2_PRT
+#define SCSI_In_DBx__DB5__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
+#define SCSI_In_DBx__DB5__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
+#define SCSI_In_DBx__DB5__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
+#define SCSI_In_DBx__DB5__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
+#define SCSI_In_DBx__DB5__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
+#define SCSI_In_DBx__DB5__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
+#define SCSI_In_DBx__DB5__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
+#define SCSI_In_DBx__DB5__PS CYREG_PRT2_PS
+#define SCSI_In_DBx__DB5__SHIFT 2u
+#define SCSI_In_DBx__DB5__SLW CYREG_PRT2_SLW
+#define SCSI_In_DBx__DB6__AG CYREG_PRT2_AG
+#define SCSI_In_DBx__DB6__AMUX CYREG_PRT2_AMUX
+#define SCSI_In_DBx__DB6__BIE CYREG_PRT2_BIE
+#define SCSI_In_DBx__DB6__BIT_MASK CYREG_PRT2_BIT_MASK
+#define SCSI_In_DBx__DB6__BYP CYREG_PRT2_BYP
+#define SCSI_In_DBx__DB6__CTL CYREG_PRT2_CTL
+#define SCSI_In_DBx__DB6__DM0 CYREG_PRT2_DM0
+#define SCSI_In_DBx__DB6__DM1 CYREG_PRT2_DM1
+#define SCSI_In_DBx__DB6__DM2 CYREG_PRT2_DM2
+#define SCSI_In_DBx__DB6__DR CYREG_PRT2_DR
+#define SCSI_In_DBx__DB6__INP_DIS CYREG_PRT2_INP_DIS
+#define SCSI_In_DBx__DB6__INTTYPE CYREG_PICU2_INTTYPE0
+#define SCSI_In_DBx__DB6__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
+#define SCSI_In_DBx__DB6__LCD_EN CYREG_PRT2_LCD_EN
+#define SCSI_In_DBx__DB6__MASK 0x01u
+#define SCSI_In_DBx__DB6__PC CYREG_PRT2_PC0
+#define SCSI_In_DBx__DB6__PORT 2u
+#define SCSI_In_DBx__DB6__PRT CYREG_PRT2_PRT
+#define SCSI_In_DBx__DB6__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
+#define SCSI_In_DBx__DB6__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
+#define SCSI_In_DBx__DB6__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
+#define SCSI_In_DBx__DB6__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
+#define SCSI_In_DBx__DB6__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
+#define SCSI_In_DBx__DB6__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
+#define SCSI_In_DBx__DB6__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
+#define SCSI_In_DBx__DB6__PS CYREG_PRT2_PS
+#define SCSI_In_DBx__DB6__SHIFT 0u
+#define SCSI_In_DBx__DB6__SLW CYREG_PRT2_SLW
+#define SCSI_In_DBx__DB7__AG CYREG_PRT6_AG
+#define SCSI_In_DBx__DB7__AMUX CYREG_PRT6_AMUX
+#define SCSI_In_DBx__DB7__BIE CYREG_PRT6_BIE
+#define SCSI_In_DBx__DB7__BIT_MASK CYREG_PRT6_BIT_MASK
+#define SCSI_In_DBx__DB7__BYP CYREG_PRT6_BYP
+#define SCSI_In_DBx__DB7__CTL CYREG_PRT6_CTL
+#define SCSI_In_DBx__DB7__DM0 CYREG_PRT6_DM0
+#define SCSI_In_DBx__DB7__DM1 CYREG_PRT6_DM1
+#define SCSI_In_DBx__DB7__DM2 CYREG_PRT6_DM2
+#define SCSI_In_DBx__DB7__DR CYREG_PRT6_DR
+#define SCSI_In_DBx__DB7__INP_DIS CYREG_PRT6_INP_DIS
+#define SCSI_In_DBx__DB7__INTTYPE CYREG_PICU6_INTTYPE3
+#define SCSI_In_DBx__DB7__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
+#define SCSI_In_DBx__DB7__LCD_EN CYREG_PRT6_LCD_EN
+#define SCSI_In_DBx__DB7__MASK 0x08u
+#define SCSI_In_DBx__DB7__PC CYREG_PRT6_PC3
+#define SCSI_In_DBx__DB7__PORT 6u
+#define SCSI_In_DBx__DB7__PRT CYREG_PRT6_PRT
+#define SCSI_In_DBx__DB7__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
+#define SCSI_In_DBx__DB7__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
+#define SCSI_In_DBx__DB7__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
+#define SCSI_In_DBx__DB7__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
+#define SCSI_In_DBx__DB7__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
+#define SCSI_In_DBx__DB7__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
+#define SCSI_In_DBx__DB7__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
+#define SCSI_In_DBx__DB7__PS CYREG_PRT6_PS
+#define SCSI_In_DBx__DB7__SHIFT 3u
+#define SCSI_In_DBx__DB7__SLW CYREG_PRT6_SLW
 
 /* SCSI_Noise */
 #define SCSI_Noise__0__AG CYREG_PRT4_AG
@@ -2354,6 +933,1592 @@
 #define SCSI_Noise__SEL__SHIFT 2u
 #define SCSI_Noise__SEL__SLW CYREG_PRT0_SLW
 
+/* SCSI_Out */
+#define SCSI_Out__0__AG CYREG_PRT6_AG
+#define SCSI_Out__0__AMUX CYREG_PRT6_AMUX
+#define SCSI_Out__0__BIE CYREG_PRT6_BIE
+#define SCSI_Out__0__BIT_MASK CYREG_PRT6_BIT_MASK
+#define SCSI_Out__0__BYP CYREG_PRT6_BYP
+#define SCSI_Out__0__CTL CYREG_PRT6_CTL
+#define SCSI_Out__0__DM0 CYREG_PRT6_DM0
+#define SCSI_Out__0__DM1 CYREG_PRT6_DM1
+#define SCSI_Out__0__DM2 CYREG_PRT6_DM2
+#define SCSI_Out__0__DR CYREG_PRT6_DR
+#define SCSI_Out__0__INP_DIS CYREG_PRT6_INP_DIS
+#define SCSI_Out__0__INTTYPE CYREG_PICU6_INTTYPE2
+#define SCSI_Out__0__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
+#define SCSI_Out__0__LCD_EN CYREG_PRT6_LCD_EN
+#define SCSI_Out__0__MASK 0x04u
+#define SCSI_Out__0__PC CYREG_PRT6_PC2
+#define SCSI_Out__0__PORT 6u
+#define SCSI_Out__0__PRT CYREG_PRT6_PRT
+#define SCSI_Out__0__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
+#define SCSI_Out__0__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
+#define SCSI_Out__0__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
+#define SCSI_Out__0__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
+#define SCSI_Out__0__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
+#define SCSI_Out__0__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
+#define SCSI_Out__0__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
+#define SCSI_Out__0__PS CYREG_PRT6_PS
+#define SCSI_Out__0__SHIFT 2u
+#define SCSI_Out__0__SLW CYREG_PRT6_SLW
+#define SCSI_Out__1__AG CYREG_PRT4_AG
+#define SCSI_Out__1__AMUX CYREG_PRT4_AMUX
+#define SCSI_Out__1__BIE CYREG_PRT4_BIE
+#define SCSI_Out__1__BIT_MASK CYREG_PRT4_BIT_MASK
+#define SCSI_Out__1__BYP CYREG_PRT4_BYP
+#define SCSI_Out__1__CTL CYREG_PRT4_CTL
+#define SCSI_Out__1__DM0 CYREG_PRT4_DM0
+#define SCSI_Out__1__DM1 CYREG_PRT4_DM1
+#define SCSI_Out__1__DM2 CYREG_PRT4_DM2
+#define SCSI_Out__1__DR CYREG_PRT4_DR
+#define SCSI_Out__1__INP_DIS CYREG_PRT4_INP_DIS
+#define SCSI_Out__1__INTTYPE CYREG_PICU4_INTTYPE6
+#define SCSI_Out__1__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG
+#define SCSI_Out__1__LCD_EN CYREG_PRT4_LCD_EN
+#define SCSI_Out__1__MASK 0x40u
+#define SCSI_Out__1__PC CYREG_PRT4_PC6
+#define SCSI_Out__1__PORT 4u
+#define SCSI_Out__1__PRT CYREG_PRT4_PRT
+#define SCSI_Out__1__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL
+#define SCSI_Out__1__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN
+#define SCSI_Out__1__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0
+#define SCSI_Out__1__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1
+#define SCSI_Out__1__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0
+#define SCSI_Out__1__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1
+#define SCSI_Out__1__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT
+#define SCSI_Out__1__PS CYREG_PRT4_PS
+#define SCSI_Out__1__SHIFT 6u
+#define SCSI_Out__1__SLW CYREG_PRT4_SLW
+#define SCSI_Out__2__AG CYREG_PRT0_AG
+#define SCSI_Out__2__AMUX CYREG_PRT0_AMUX
+#define SCSI_Out__2__BIE CYREG_PRT0_BIE
+#define SCSI_Out__2__BIT_MASK CYREG_PRT0_BIT_MASK
+#define SCSI_Out__2__BYP CYREG_PRT0_BYP
+#define SCSI_Out__2__CTL CYREG_PRT0_CTL
+#define SCSI_Out__2__DM0 CYREG_PRT0_DM0
+#define SCSI_Out__2__DM1 CYREG_PRT0_DM1
+#define SCSI_Out__2__DM2 CYREG_PRT0_DM2
+#define SCSI_Out__2__DR CYREG_PRT0_DR
+#define SCSI_Out__2__INP_DIS CYREG_PRT0_INP_DIS
+#define SCSI_Out__2__INTTYPE CYREG_PICU0_INTTYPE7
+#define SCSI_Out__2__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG
+#define SCSI_Out__2__LCD_EN CYREG_PRT0_LCD_EN
+#define SCSI_Out__2__MASK 0x80u
+#define SCSI_Out__2__PC CYREG_PRT0_PC7
+#define SCSI_Out__2__PORT 0u
+#define SCSI_Out__2__PRT CYREG_PRT0_PRT
+#define SCSI_Out__2__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL
+#define SCSI_Out__2__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN
+#define SCSI_Out__2__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0
+#define SCSI_Out__2__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1
+#define SCSI_Out__2__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0
+#define SCSI_Out__2__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1
+#define SCSI_Out__2__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT
+#define SCSI_Out__2__PS CYREG_PRT0_PS
+#define SCSI_Out__2__SHIFT 7u
+#define SCSI_Out__2__SLW CYREG_PRT0_SLW
+#define SCSI_Out__3__AG CYREG_PRT0_AG
+#define SCSI_Out__3__AMUX CYREG_PRT0_AMUX
+#define SCSI_Out__3__BIE CYREG_PRT0_BIE
+#define SCSI_Out__3__BIT_MASK CYREG_PRT0_BIT_MASK
+#define SCSI_Out__3__BYP CYREG_PRT0_BYP
+#define SCSI_Out__3__CTL CYREG_PRT0_CTL
+#define SCSI_Out__3__DM0 CYREG_PRT0_DM0
+#define SCSI_Out__3__DM1 CYREG_PRT0_DM1
+#define SCSI_Out__3__DM2 CYREG_PRT0_DM2
+#define SCSI_Out__3__DR CYREG_PRT0_DR
+#define SCSI_Out__3__INP_DIS CYREG_PRT0_INP_DIS
+#define SCSI_Out__3__INTTYPE CYREG_PICU0_INTTYPE5
+#define SCSI_Out__3__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG
+#define SCSI_Out__3__LCD_EN CYREG_PRT0_LCD_EN
+#define SCSI_Out__3__MASK 0x20u
+#define SCSI_Out__3__PC CYREG_PRT0_PC5
+#define SCSI_Out__3__PORT 0u
+#define SCSI_Out__3__PRT CYREG_PRT0_PRT
+#define SCSI_Out__3__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL
+#define SCSI_Out__3__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN
+#define SCSI_Out__3__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0
+#define SCSI_Out__3__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1
+#define SCSI_Out__3__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0
+#define SCSI_Out__3__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1
+#define SCSI_Out__3__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT
+#define SCSI_Out__3__PS CYREG_PRT0_PS
+#define SCSI_Out__3__SHIFT 5u
+#define SCSI_Out__3__SLW CYREG_PRT0_SLW
+#define SCSI_Out__4__AG CYREG_PRT0_AG
+#define SCSI_Out__4__AMUX CYREG_PRT0_AMUX
+#define SCSI_Out__4__BIE CYREG_PRT0_BIE
+#define SCSI_Out__4__BIT_MASK CYREG_PRT0_BIT_MASK
+#define SCSI_Out__4__BYP CYREG_PRT0_BYP
+#define SCSI_Out__4__CTL CYREG_PRT0_CTL
+#define SCSI_Out__4__DM0 CYREG_PRT0_DM0
+#define SCSI_Out__4__DM1 CYREG_PRT0_DM1
+#define SCSI_Out__4__DM2 CYREG_PRT0_DM2
+#define SCSI_Out__4__DR CYREG_PRT0_DR
+#define SCSI_Out__4__INP_DIS CYREG_PRT0_INP_DIS
+#define SCSI_Out__4__INTTYPE CYREG_PICU0_INTTYPE3
+#define SCSI_Out__4__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG
+#define SCSI_Out__4__LCD_EN CYREG_PRT0_LCD_EN
+#define SCSI_Out__4__MASK 0x08u
+#define SCSI_Out__4__PC CYREG_PRT0_PC3
+#define SCSI_Out__4__PORT 0u
+#define SCSI_Out__4__PRT CYREG_PRT0_PRT
+#define SCSI_Out__4__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL
+#define SCSI_Out__4__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN
+#define SCSI_Out__4__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0
+#define SCSI_Out__4__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1
+#define SCSI_Out__4__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0
+#define SCSI_Out__4__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1
+#define SCSI_Out__4__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT
+#define SCSI_Out__4__PS CYREG_PRT0_PS
+#define SCSI_Out__4__SHIFT 3u
+#define SCSI_Out__4__SLW CYREG_PRT0_SLW
+#define SCSI_Out__5__AG CYREG_PRT0_AG
+#define SCSI_Out__5__AMUX CYREG_PRT0_AMUX
+#define SCSI_Out__5__BIE CYREG_PRT0_BIE
+#define SCSI_Out__5__BIT_MASK CYREG_PRT0_BIT_MASK
+#define SCSI_Out__5__BYP CYREG_PRT0_BYP
+#define SCSI_Out__5__CTL CYREG_PRT0_CTL
+#define SCSI_Out__5__DM0 CYREG_PRT0_DM0
+#define SCSI_Out__5__DM1 CYREG_PRT0_DM1
+#define SCSI_Out__5__DM2 CYREG_PRT0_DM2
+#define SCSI_Out__5__DR CYREG_PRT0_DR
+#define SCSI_Out__5__INP_DIS CYREG_PRT0_INP_DIS
+#define SCSI_Out__5__INTTYPE CYREG_PICU0_INTTYPE1
+#define SCSI_Out__5__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG
+#define SCSI_Out__5__LCD_EN CYREG_PRT0_LCD_EN
+#define SCSI_Out__5__MASK 0x02u
+#define SCSI_Out__5__PC CYREG_PRT0_PC1
+#define SCSI_Out__5__PORT 0u
+#define SCSI_Out__5__PRT CYREG_PRT0_PRT
+#define SCSI_Out__5__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL
+#define SCSI_Out__5__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN
+#define SCSI_Out__5__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0
+#define SCSI_Out__5__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1
+#define SCSI_Out__5__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0
+#define SCSI_Out__5__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1
+#define SCSI_Out__5__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT
+#define SCSI_Out__5__PS CYREG_PRT0_PS
+#define SCSI_Out__5__SHIFT 1u
+#define SCSI_Out__5__SLW CYREG_PRT0_SLW
+#define SCSI_Out__6__AG CYREG_PRT4_AG
+#define SCSI_Out__6__AMUX CYREG_PRT4_AMUX
+#define SCSI_Out__6__BIE CYREG_PRT4_BIE
+#define SCSI_Out__6__BIT_MASK CYREG_PRT4_BIT_MASK
+#define SCSI_Out__6__BYP CYREG_PRT4_BYP
+#define SCSI_Out__6__CTL CYREG_PRT4_CTL
+#define SCSI_Out__6__DM0 CYREG_PRT4_DM0
+#define SCSI_Out__6__DM1 CYREG_PRT4_DM1
+#define SCSI_Out__6__DM2 CYREG_PRT4_DM2
+#define SCSI_Out__6__DR CYREG_PRT4_DR
+#define SCSI_Out__6__INP_DIS CYREG_PRT4_INP_DIS
+#define SCSI_Out__6__INTTYPE CYREG_PICU4_INTTYPE1
+#define SCSI_Out__6__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG
+#define SCSI_Out__6__LCD_EN CYREG_PRT4_LCD_EN
+#define SCSI_Out__6__MASK 0x02u
+#define SCSI_Out__6__PC CYREG_PRT4_PC1
+#define SCSI_Out__6__PORT 4u
+#define SCSI_Out__6__PRT CYREG_PRT4_PRT
+#define SCSI_Out__6__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL
+#define SCSI_Out__6__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN
+#define SCSI_Out__6__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0
+#define SCSI_Out__6__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1
+#define SCSI_Out__6__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0
+#define SCSI_Out__6__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1
+#define SCSI_Out__6__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT
+#define SCSI_Out__6__PS CYREG_PRT4_PS
+#define SCSI_Out__6__SHIFT 1u
+#define SCSI_Out__6__SLW CYREG_PRT4_SLW
+#define SCSI_Out__7__AG CYREG_PRT12_AG
+#define SCSI_Out__7__BIE CYREG_PRT12_BIE
+#define SCSI_Out__7__BIT_MASK CYREG_PRT12_BIT_MASK
+#define SCSI_Out__7__BYP CYREG_PRT12_BYP
+#define SCSI_Out__7__DM0 CYREG_PRT12_DM0
+#define SCSI_Out__7__DM1 CYREG_PRT12_DM1
+#define SCSI_Out__7__DM2 CYREG_PRT12_DM2
+#define SCSI_Out__7__DR CYREG_PRT12_DR
+#define SCSI_Out__7__INP_DIS CYREG_PRT12_INP_DIS
+#define SCSI_Out__7__INTTYPE CYREG_PICU12_INTTYPE3
+#define SCSI_Out__7__MASK 0x08u
+#define SCSI_Out__7__PC CYREG_PRT12_PC3
+#define SCSI_Out__7__PORT 12u
+#define SCSI_Out__7__PRT CYREG_PRT12_PRT
+#define SCSI_Out__7__PRTDSI__DBL_SYNC_IN CYREG_PRT12_DBL_SYNC_IN
+#define SCSI_Out__7__PRTDSI__OE_SEL0 CYREG_PRT12_OE_SEL0
+#define SCSI_Out__7__PRTDSI__OE_SEL1 CYREG_PRT12_OE_SEL1
+#define SCSI_Out__7__PRTDSI__OUT_SEL0 CYREG_PRT12_OUT_SEL0
+#define SCSI_Out__7__PRTDSI__OUT_SEL1 CYREG_PRT12_OUT_SEL1
+#define SCSI_Out__7__PRTDSI__SYNC_OUT CYREG_PRT12_SYNC_OUT
+#define SCSI_Out__7__PS CYREG_PRT12_PS
+#define SCSI_Out__7__SHIFT 3u
+#define SCSI_Out__7__SIO_CFG CYREG_PRT12_SIO_CFG
+#define SCSI_Out__7__SIO_DIFF CYREG_PRT12_SIO_DIFF
+#define SCSI_Out__7__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN
+#define SCSI_Out__7__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ
+#define SCSI_Out__7__SLW CYREG_PRT12_SLW
+#define SCSI_Out__BSY__AG CYREG_PRT4_AG
+#define SCSI_Out__BSY__AMUX CYREG_PRT4_AMUX
+#define SCSI_Out__BSY__BIE CYREG_PRT4_BIE
+#define SCSI_Out__BSY__BIT_MASK CYREG_PRT4_BIT_MASK
+#define SCSI_Out__BSY__BYP CYREG_PRT4_BYP
+#define SCSI_Out__BSY__CTL CYREG_PRT4_CTL
+#define SCSI_Out__BSY__DM0 CYREG_PRT4_DM0
+#define SCSI_Out__BSY__DM1 CYREG_PRT4_DM1
+#define SCSI_Out__BSY__DM2 CYREG_PRT4_DM2
+#define SCSI_Out__BSY__DR CYREG_PRT4_DR
+#define SCSI_Out__BSY__INP_DIS CYREG_PRT4_INP_DIS
+#define SCSI_Out__BSY__INTTYPE CYREG_PICU4_INTTYPE6
+#define SCSI_Out__BSY__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG
+#define SCSI_Out__BSY__LCD_EN CYREG_PRT4_LCD_EN
+#define SCSI_Out__BSY__MASK 0x40u
+#define SCSI_Out__BSY__PC CYREG_PRT4_PC6
+#define SCSI_Out__BSY__PORT 4u
+#define SCSI_Out__BSY__PRT CYREG_PRT4_PRT
+#define SCSI_Out__BSY__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL
+#define SCSI_Out__BSY__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN
+#define SCSI_Out__BSY__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0
+#define SCSI_Out__BSY__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1
+#define SCSI_Out__BSY__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0
+#define SCSI_Out__BSY__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1
+#define SCSI_Out__BSY__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT
+#define SCSI_Out__BSY__PS CYREG_PRT4_PS
+#define SCSI_Out__BSY__SHIFT 6u
+#define SCSI_Out__BSY__SLW CYREG_PRT4_SLW
+#define SCSI_Out__CD_raw__AG CYREG_PRT0_AG
+#define SCSI_Out__CD_raw__AMUX CYREG_PRT0_AMUX
+#define SCSI_Out__CD_raw__BIE CYREG_PRT0_BIE
+#define SCSI_Out__CD_raw__BIT_MASK CYREG_PRT0_BIT_MASK
+#define SCSI_Out__CD_raw__BYP CYREG_PRT0_BYP
+#define SCSI_Out__CD_raw__CTL CYREG_PRT0_CTL
+#define SCSI_Out__CD_raw__DM0 CYREG_PRT0_DM0
+#define SCSI_Out__CD_raw__DM1 CYREG_PRT0_DM1
+#define SCSI_Out__CD_raw__DM2 CYREG_PRT0_DM2
+#define SCSI_Out__CD_raw__DR CYREG_PRT0_DR
+#define SCSI_Out__CD_raw__INP_DIS CYREG_PRT0_INP_DIS
+#define SCSI_Out__CD_raw__INTTYPE CYREG_PICU0_INTTYPE1
+#define SCSI_Out__CD_raw__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG
+#define SCSI_Out__CD_raw__LCD_EN CYREG_PRT0_LCD_EN
+#define SCSI_Out__CD_raw__MASK 0x02u
+#define SCSI_Out__CD_raw__PC CYREG_PRT0_PC1
+#define SCSI_Out__CD_raw__PORT 0u
+#define SCSI_Out__CD_raw__PRT CYREG_PRT0_PRT
+#define SCSI_Out__CD_raw__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL
+#define SCSI_Out__CD_raw__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN
+#define SCSI_Out__CD_raw__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0
+#define SCSI_Out__CD_raw__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1
+#define SCSI_Out__CD_raw__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0
+#define SCSI_Out__CD_raw__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1
+#define SCSI_Out__CD_raw__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT
+#define SCSI_Out__CD_raw__PS CYREG_PRT0_PS
+#define SCSI_Out__CD_raw__SHIFT 1u
+#define SCSI_Out__CD_raw__SLW CYREG_PRT0_SLW
+#define SCSI_Out__DBP_raw__AG CYREG_PRT6_AG
+#define SCSI_Out__DBP_raw__AMUX CYREG_PRT6_AMUX
+#define SCSI_Out__DBP_raw__BIE CYREG_PRT6_BIE
+#define SCSI_Out__DBP_raw__BIT_MASK CYREG_PRT6_BIT_MASK
+#define SCSI_Out__DBP_raw__BYP CYREG_PRT6_BYP
+#define SCSI_Out__DBP_raw__CTL CYREG_PRT6_CTL
+#define SCSI_Out__DBP_raw__DM0 CYREG_PRT6_DM0
+#define SCSI_Out__DBP_raw__DM1 CYREG_PRT6_DM1
+#define SCSI_Out__DBP_raw__DM2 CYREG_PRT6_DM2
+#define SCSI_Out__DBP_raw__DR CYREG_PRT6_DR
+#define SCSI_Out__DBP_raw__INP_DIS CYREG_PRT6_INP_DIS
+#define SCSI_Out__DBP_raw__INTTYPE CYREG_PICU6_INTTYPE2
+#define SCSI_Out__DBP_raw__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
+#define SCSI_Out__DBP_raw__LCD_EN CYREG_PRT6_LCD_EN
+#define SCSI_Out__DBP_raw__MASK 0x04u
+#define SCSI_Out__DBP_raw__PC CYREG_PRT6_PC2
+#define SCSI_Out__DBP_raw__PORT 6u
+#define SCSI_Out__DBP_raw__PRT CYREG_PRT6_PRT
+#define SCSI_Out__DBP_raw__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
+#define SCSI_Out__DBP_raw__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
+#define SCSI_Out__DBP_raw__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
+#define SCSI_Out__DBP_raw__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
+#define SCSI_Out__DBP_raw__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
+#define SCSI_Out__DBP_raw__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
+#define SCSI_Out__DBP_raw__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
+#define SCSI_Out__DBP_raw__PS CYREG_PRT6_PS
+#define SCSI_Out__DBP_raw__SHIFT 2u
+#define SCSI_Out__DBP_raw__SLW CYREG_PRT6_SLW
+#define SCSI_Out__IO_raw__AG CYREG_PRT12_AG
+#define SCSI_Out__IO_raw__BIE CYREG_PRT12_BIE
+#define SCSI_Out__IO_raw__BIT_MASK CYREG_PRT12_BIT_MASK
+#define SCSI_Out__IO_raw__BYP CYREG_PRT12_BYP
+#define SCSI_Out__IO_raw__DM0 CYREG_PRT12_DM0
+#define SCSI_Out__IO_raw__DM1 CYREG_PRT12_DM1
+#define SCSI_Out__IO_raw__DM2 CYREG_PRT12_DM2
+#define SCSI_Out__IO_raw__DR CYREG_PRT12_DR
+#define SCSI_Out__IO_raw__INP_DIS CYREG_PRT12_INP_DIS
+#define SCSI_Out__IO_raw__INTTYPE CYREG_PICU12_INTTYPE3
+#define SCSI_Out__IO_raw__MASK 0x08u
+#define SCSI_Out__IO_raw__PC CYREG_PRT12_PC3
+#define SCSI_Out__IO_raw__PORT 12u
+#define SCSI_Out__IO_raw__PRT CYREG_PRT12_PRT
+#define SCSI_Out__IO_raw__PRTDSI__DBL_SYNC_IN CYREG_PRT12_DBL_SYNC_IN
+#define SCSI_Out__IO_raw__PRTDSI__OE_SEL0 CYREG_PRT12_OE_SEL0
+#define SCSI_Out__IO_raw__PRTDSI__OE_SEL1 CYREG_PRT12_OE_SEL1
+#define SCSI_Out__IO_raw__PRTDSI__OUT_SEL0 CYREG_PRT12_OUT_SEL0
+#define SCSI_Out__IO_raw__PRTDSI__OUT_SEL1 CYREG_PRT12_OUT_SEL1
+#define SCSI_Out__IO_raw__PRTDSI__SYNC_OUT CYREG_PRT12_SYNC_OUT
+#define SCSI_Out__IO_raw__PS CYREG_PRT12_PS
+#define SCSI_Out__IO_raw__SHIFT 3u
+#define SCSI_Out__IO_raw__SIO_CFG CYREG_PRT12_SIO_CFG
+#define SCSI_Out__IO_raw__SIO_DIFF CYREG_PRT12_SIO_DIFF
+#define SCSI_Out__IO_raw__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN
+#define SCSI_Out__IO_raw__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ
+#define SCSI_Out__IO_raw__SLW CYREG_PRT12_SLW
+#define SCSI_Out__MSG_raw__AG CYREG_PRT0_AG
+#define SCSI_Out__MSG_raw__AMUX CYREG_PRT0_AMUX
+#define SCSI_Out__MSG_raw__BIE CYREG_PRT0_BIE
+#define SCSI_Out__MSG_raw__BIT_MASK CYREG_PRT0_BIT_MASK
+#define SCSI_Out__MSG_raw__BYP CYREG_PRT0_BYP
+#define SCSI_Out__MSG_raw__CTL CYREG_PRT0_CTL
+#define SCSI_Out__MSG_raw__DM0 CYREG_PRT0_DM0
+#define SCSI_Out__MSG_raw__DM1 CYREG_PRT0_DM1
+#define SCSI_Out__MSG_raw__DM2 CYREG_PRT0_DM2
+#define SCSI_Out__MSG_raw__DR CYREG_PRT0_DR
+#define SCSI_Out__MSG_raw__INP_DIS CYREG_PRT0_INP_DIS
+#define SCSI_Out__MSG_raw__INTTYPE CYREG_PICU0_INTTYPE5
+#define SCSI_Out__MSG_raw__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG
+#define SCSI_Out__MSG_raw__LCD_EN CYREG_PRT0_LCD_EN
+#define SCSI_Out__MSG_raw__MASK 0x20u
+#define SCSI_Out__MSG_raw__PC CYREG_PRT0_PC5
+#define SCSI_Out__MSG_raw__PORT 0u
+#define SCSI_Out__MSG_raw__PRT CYREG_PRT0_PRT
+#define SCSI_Out__MSG_raw__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL
+#define SCSI_Out__MSG_raw__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN
+#define SCSI_Out__MSG_raw__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0
+#define SCSI_Out__MSG_raw__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1
+#define SCSI_Out__MSG_raw__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0
+#define SCSI_Out__MSG_raw__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1
+#define SCSI_Out__MSG_raw__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT
+#define SCSI_Out__MSG_raw__PS CYREG_PRT0_PS
+#define SCSI_Out__MSG_raw__SHIFT 5u
+#define SCSI_Out__MSG_raw__SLW CYREG_PRT0_SLW
+#define SCSI_Out__REQ__AG CYREG_PRT4_AG
+#define SCSI_Out__REQ__AMUX CYREG_PRT4_AMUX
+#define SCSI_Out__REQ__BIE CYREG_PRT4_BIE
+#define SCSI_Out__REQ__BIT_MASK CYREG_PRT4_BIT_MASK
+#define SCSI_Out__REQ__BYP CYREG_PRT4_BYP
+#define SCSI_Out__REQ__CTL CYREG_PRT4_CTL
+#define SCSI_Out__REQ__DM0 CYREG_PRT4_DM0
+#define SCSI_Out__REQ__DM1 CYREG_PRT4_DM1
+#define SCSI_Out__REQ__DM2 CYREG_PRT4_DM2
+#define SCSI_Out__REQ__DR CYREG_PRT4_DR
+#define SCSI_Out__REQ__INP_DIS CYREG_PRT4_INP_DIS
+#define SCSI_Out__REQ__INTTYPE CYREG_PICU4_INTTYPE1
+#define SCSI_Out__REQ__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG
+#define SCSI_Out__REQ__LCD_EN CYREG_PRT4_LCD_EN
+#define SCSI_Out__REQ__MASK 0x02u
+#define SCSI_Out__REQ__PC CYREG_PRT4_PC1
+#define SCSI_Out__REQ__PORT 4u
+#define SCSI_Out__REQ__PRT CYREG_PRT4_PRT
+#define SCSI_Out__REQ__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL
+#define SCSI_Out__REQ__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN
+#define SCSI_Out__REQ__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0
+#define SCSI_Out__REQ__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1
+#define SCSI_Out__REQ__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0
+#define SCSI_Out__REQ__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1
+#define SCSI_Out__REQ__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT
+#define SCSI_Out__REQ__PS CYREG_PRT4_PS
+#define SCSI_Out__REQ__SHIFT 1u
+#define SCSI_Out__REQ__SLW CYREG_PRT4_SLW
+#define SCSI_Out__RST__AG CYREG_PRT0_AG
+#define SCSI_Out__RST__AMUX CYREG_PRT0_AMUX
+#define SCSI_Out__RST__BIE CYREG_PRT0_BIE
+#define SCSI_Out__RST__BIT_MASK CYREG_PRT0_BIT_MASK
+#define SCSI_Out__RST__BYP CYREG_PRT0_BYP
+#define SCSI_Out__RST__CTL CYREG_PRT0_CTL
+#define SCSI_Out__RST__DM0 CYREG_PRT0_DM0
+#define SCSI_Out__RST__DM1 CYREG_PRT0_DM1
+#define SCSI_Out__RST__DM2 CYREG_PRT0_DM2
+#define SCSI_Out__RST__DR CYREG_PRT0_DR
+#define SCSI_Out__RST__INP_DIS CYREG_PRT0_INP_DIS
+#define SCSI_Out__RST__INTTYPE CYREG_PICU0_INTTYPE7
+#define SCSI_Out__RST__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG
+#define SCSI_Out__RST__LCD_EN CYREG_PRT0_LCD_EN
+#define SCSI_Out__RST__MASK 0x80u
+#define SCSI_Out__RST__PC CYREG_PRT0_PC7
+#define SCSI_Out__RST__PORT 0u
+#define SCSI_Out__RST__PRT CYREG_PRT0_PRT
+#define SCSI_Out__RST__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL
+#define SCSI_Out__RST__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN
+#define SCSI_Out__RST__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0
+#define SCSI_Out__RST__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1
+#define SCSI_Out__RST__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0
+#define SCSI_Out__RST__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1
+#define SCSI_Out__RST__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT
+#define SCSI_Out__RST__PS CYREG_PRT0_PS
+#define SCSI_Out__RST__SHIFT 7u
+#define SCSI_Out__RST__SLW CYREG_PRT0_SLW
+#define SCSI_Out__SEL__AG CYREG_PRT0_AG
+#define SCSI_Out__SEL__AMUX CYREG_PRT0_AMUX
+#define SCSI_Out__SEL__BIE CYREG_PRT0_BIE
+#define SCSI_Out__SEL__BIT_MASK CYREG_PRT0_BIT_MASK
+#define SCSI_Out__SEL__BYP CYREG_PRT0_BYP
+#define SCSI_Out__SEL__CTL CYREG_PRT0_CTL
+#define SCSI_Out__SEL__DM0 CYREG_PRT0_DM0
+#define SCSI_Out__SEL__DM1 CYREG_PRT0_DM1
+#define SCSI_Out__SEL__DM2 CYREG_PRT0_DM2
+#define SCSI_Out__SEL__DR CYREG_PRT0_DR
+#define SCSI_Out__SEL__INP_DIS CYREG_PRT0_INP_DIS
+#define SCSI_Out__SEL__INTTYPE CYREG_PICU0_INTTYPE3
+#define SCSI_Out__SEL__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG
+#define SCSI_Out__SEL__LCD_EN CYREG_PRT0_LCD_EN
+#define SCSI_Out__SEL__MASK 0x08u
+#define SCSI_Out__SEL__PC CYREG_PRT0_PC3
+#define SCSI_Out__SEL__PORT 0u
+#define SCSI_Out__SEL__PRT CYREG_PRT0_PRT
+#define SCSI_Out__SEL__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL
+#define SCSI_Out__SEL__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN
+#define SCSI_Out__SEL__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0
+#define SCSI_Out__SEL__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1
+#define SCSI_Out__SEL__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0
+#define SCSI_Out__SEL__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1
+#define SCSI_Out__SEL__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT
+#define SCSI_Out__SEL__PS CYREG_PRT0_PS
+#define SCSI_Out__SEL__SHIFT 3u
+#define SCSI_Out__SEL__SLW CYREG_PRT0_SLW
+#define SCSI_Out_Bits_Sync_ctrl_reg__0__MASK 0x01u
+#define SCSI_Out_Bits_Sync_ctrl_reg__0__POS 0
+#define SCSI_Out_Bits_Sync_ctrl_reg__1__MASK 0x02u
+#define SCSI_Out_Bits_Sync_ctrl_reg__1__POS 1
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB07_08_ACTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB07_08_CTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB07_08_CTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB07_08_CTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB07_08_CTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB07_08_MSK
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB07_08_MSK
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB07_08_MSK
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB07_08_MSK
+#define SCSI_Out_Bits_Sync_ctrl_reg__2__MASK 0x04u
+#define SCSI_Out_Bits_Sync_ctrl_reg__2__POS 2
+#define SCSI_Out_Bits_Sync_ctrl_reg__3__MASK 0x08u
+#define SCSI_Out_Bits_Sync_ctrl_reg__3__POS 3
+#define SCSI_Out_Bits_Sync_ctrl_reg__4__MASK 0x10u
+#define SCSI_Out_Bits_Sync_ctrl_reg__4__POS 4
+#define SCSI_Out_Bits_Sync_ctrl_reg__5__MASK 0x20u
+#define SCSI_Out_Bits_Sync_ctrl_reg__5__POS 5
+#define SCSI_Out_Bits_Sync_ctrl_reg__6__MASK 0x40u
+#define SCSI_Out_Bits_Sync_ctrl_reg__6__POS 6
+#define SCSI_Out_Bits_Sync_ctrl_reg__7__MASK 0x80u
+#define SCSI_Out_Bits_Sync_ctrl_reg__7__POS 7
+#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB07_ACTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB07_CTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB07_ST_CTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB07_CTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB07_ST_CTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__MASK 0xFFu
+#define SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB07_MSK_ACTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB07_MSK_ACTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB07_MSK
+#define SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK 0x01u
+#define SCSI_Out_Ctl_Sync_ctrl_reg__0__POS 0
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB11_12_ACTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB11_12_CTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB11_12_CTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB11_12_CTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB11_12_CTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB11_12_MSK
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB11_12_MSK
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB11_12_MSK
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB11_12_MSK
+#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB11_ACTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB11_CTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB11_ST_CTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB11_CTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB11_ST_CTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK 0x01u
+#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB11_MSK
+#define SCSI_Out_DBx__0__AG CYREG_PRT6_AG
+#define SCSI_Out_DBx__0__AMUX CYREG_PRT6_AMUX
+#define SCSI_Out_DBx__0__BIE CYREG_PRT6_BIE
+#define SCSI_Out_DBx__0__BIT_MASK CYREG_PRT6_BIT_MASK
+#define SCSI_Out_DBx__0__BYP CYREG_PRT6_BYP
+#define SCSI_Out_DBx__0__CTL CYREG_PRT6_CTL
+#define SCSI_Out_DBx__0__DM0 CYREG_PRT6_DM0
+#define SCSI_Out_DBx__0__DM1 CYREG_PRT6_DM1
+#define SCSI_Out_DBx__0__DM2 CYREG_PRT6_DM2
+#define SCSI_Out_DBx__0__DR CYREG_PRT6_DR
+#define SCSI_Out_DBx__0__INP_DIS CYREG_PRT6_INP_DIS
+#define SCSI_Out_DBx__0__INTTYPE CYREG_PICU6_INTTYPE7
+#define SCSI_Out_DBx__0__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
+#define SCSI_Out_DBx__0__LCD_EN CYREG_PRT6_LCD_EN
+#define SCSI_Out_DBx__0__MASK 0x80u
+#define SCSI_Out_DBx__0__PC CYREG_PRT6_PC7
+#define SCSI_Out_DBx__0__PORT 6u
+#define SCSI_Out_DBx__0__PRT CYREG_PRT6_PRT
+#define SCSI_Out_DBx__0__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
+#define SCSI_Out_DBx__0__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
+#define SCSI_Out_DBx__0__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
+#define SCSI_Out_DBx__0__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
+#define SCSI_Out_DBx__0__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
+#define SCSI_Out_DBx__0__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
+#define SCSI_Out_DBx__0__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
+#define SCSI_Out_DBx__0__PS CYREG_PRT6_PS
+#define SCSI_Out_DBx__0__SHIFT 7u
+#define SCSI_Out_DBx__0__SLW CYREG_PRT6_SLW
+#define SCSI_Out_DBx__1__AG CYREG_PRT6_AG
+#define SCSI_Out_DBx__1__AMUX CYREG_PRT6_AMUX
+#define SCSI_Out_DBx__1__BIE CYREG_PRT6_BIE
+#define SCSI_Out_DBx__1__BIT_MASK CYREG_PRT6_BIT_MASK
+#define SCSI_Out_DBx__1__BYP CYREG_PRT6_BYP
+#define SCSI_Out_DBx__1__CTL CYREG_PRT6_CTL
+#define SCSI_Out_DBx__1__DM0 CYREG_PRT6_DM0
+#define SCSI_Out_DBx__1__DM1 CYREG_PRT6_DM1
+#define SCSI_Out_DBx__1__DM2 CYREG_PRT6_DM2
+#define SCSI_Out_DBx__1__DR CYREG_PRT6_DR
+#define SCSI_Out_DBx__1__INP_DIS CYREG_PRT6_INP_DIS
+#define SCSI_Out_DBx__1__INTTYPE CYREG_PICU6_INTTYPE5
+#define SCSI_Out_DBx__1__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
+#define SCSI_Out_DBx__1__LCD_EN CYREG_PRT6_LCD_EN
+#define SCSI_Out_DBx__1__MASK 0x20u
+#define SCSI_Out_DBx__1__PC CYREG_PRT6_PC5
+#define SCSI_Out_DBx__1__PORT 6u
+#define SCSI_Out_DBx__1__PRT CYREG_PRT6_PRT
+#define SCSI_Out_DBx__1__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
+#define SCSI_Out_DBx__1__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
+#define SCSI_Out_DBx__1__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
+#define SCSI_Out_DBx__1__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
+#define SCSI_Out_DBx__1__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
+#define SCSI_Out_DBx__1__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
+#define SCSI_Out_DBx__1__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
+#define SCSI_Out_DBx__1__PS CYREG_PRT6_PS
+#define SCSI_Out_DBx__1__SHIFT 5u
+#define SCSI_Out_DBx__1__SLW CYREG_PRT6_SLW
+#define SCSI_Out_DBx__2__AG CYREG_PRT12_AG
+#define SCSI_Out_DBx__2__BIE CYREG_PRT12_BIE
+#define SCSI_Out_DBx__2__BIT_MASK CYREG_PRT12_BIT_MASK
+#define SCSI_Out_DBx__2__BYP CYREG_PRT12_BYP
+#define SCSI_Out_DBx__2__DM0 CYREG_PRT12_DM0
+#define SCSI_Out_DBx__2__DM1 CYREG_PRT12_DM1
+#define SCSI_Out_DBx__2__DM2 CYREG_PRT12_DM2
+#define SCSI_Out_DBx__2__DR CYREG_PRT12_DR
+#define SCSI_Out_DBx__2__INP_DIS CYREG_PRT12_INP_DIS
+#define SCSI_Out_DBx__2__INTTYPE CYREG_PICU12_INTTYPE5
+#define SCSI_Out_DBx__2__MASK 0x20u
+#define SCSI_Out_DBx__2__PC CYREG_PRT12_PC5
+#define SCSI_Out_DBx__2__PORT 12u
+#define SCSI_Out_DBx__2__PRT CYREG_PRT12_PRT
+#define SCSI_Out_DBx__2__PRTDSI__DBL_SYNC_IN CYREG_PRT12_DBL_SYNC_IN
+#define SCSI_Out_DBx__2__PRTDSI__OE_SEL0 CYREG_PRT12_OE_SEL0
+#define SCSI_Out_DBx__2__PRTDSI__OE_SEL1 CYREG_PRT12_OE_SEL1
+#define SCSI_Out_DBx__2__PRTDSI__OUT_SEL0 CYREG_PRT12_OUT_SEL0
+#define SCSI_Out_DBx__2__PRTDSI__OUT_SEL1 CYREG_PRT12_OUT_SEL1
+#define SCSI_Out_DBx__2__PRTDSI__SYNC_OUT CYREG_PRT12_SYNC_OUT
+#define SCSI_Out_DBx__2__PS CYREG_PRT12_PS
+#define SCSI_Out_DBx__2__SHIFT 5u
+#define SCSI_Out_DBx__2__SIO_CFG CYREG_PRT12_SIO_CFG
+#define SCSI_Out_DBx__2__SIO_DIFF CYREG_PRT12_SIO_DIFF
+#define SCSI_Out_DBx__2__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN
+#define SCSI_Out_DBx__2__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ
+#define SCSI_Out_DBx__2__SLW CYREG_PRT12_SLW
+#define SCSI_Out_DBx__3__AG CYREG_PRT2_AG
+#define SCSI_Out_DBx__3__AMUX CYREG_PRT2_AMUX
+#define SCSI_Out_DBx__3__BIE CYREG_PRT2_BIE
+#define SCSI_Out_DBx__3__BIT_MASK CYREG_PRT2_BIT_MASK
+#define SCSI_Out_DBx__3__BYP CYREG_PRT2_BYP
+#define SCSI_Out_DBx__3__CTL CYREG_PRT2_CTL
+#define SCSI_Out_DBx__3__DM0 CYREG_PRT2_DM0
+#define SCSI_Out_DBx__3__DM1 CYREG_PRT2_DM1
+#define SCSI_Out_DBx__3__DM2 CYREG_PRT2_DM2
+#define SCSI_Out_DBx__3__DR CYREG_PRT2_DR
+#define SCSI_Out_DBx__3__INP_DIS CYREG_PRT2_INP_DIS
+#define SCSI_Out_DBx__3__INTTYPE CYREG_PICU2_INTTYPE7
+#define SCSI_Out_DBx__3__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
+#define SCSI_Out_DBx__3__LCD_EN CYREG_PRT2_LCD_EN
+#define SCSI_Out_DBx__3__MASK 0x80u
+#define SCSI_Out_DBx__3__PC CYREG_PRT2_PC7
+#define SCSI_Out_DBx__3__PORT 2u
+#define SCSI_Out_DBx__3__PRT CYREG_PRT2_PRT
+#define SCSI_Out_DBx__3__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
+#define SCSI_Out_DBx__3__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
+#define SCSI_Out_DBx__3__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
+#define SCSI_Out_DBx__3__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
+#define SCSI_Out_DBx__3__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
+#define SCSI_Out_DBx__3__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
+#define SCSI_Out_DBx__3__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
+#define SCSI_Out_DBx__3__PS CYREG_PRT2_PS
+#define SCSI_Out_DBx__3__SHIFT 7u
+#define SCSI_Out_DBx__3__SLW CYREG_PRT2_SLW
+#define SCSI_Out_DBx__4__AG CYREG_PRT2_AG
+#define SCSI_Out_DBx__4__AMUX CYREG_PRT2_AMUX
+#define SCSI_Out_DBx__4__BIE CYREG_PRT2_BIE
+#define SCSI_Out_DBx__4__BIT_MASK CYREG_PRT2_BIT_MASK
+#define SCSI_Out_DBx__4__BYP CYREG_PRT2_BYP
+#define SCSI_Out_DBx__4__CTL CYREG_PRT2_CTL
+#define SCSI_Out_DBx__4__DM0 CYREG_PRT2_DM0
+#define SCSI_Out_DBx__4__DM1 CYREG_PRT2_DM1
+#define SCSI_Out_DBx__4__DM2 CYREG_PRT2_DM2
+#define SCSI_Out_DBx__4__DR CYREG_PRT2_DR
+#define SCSI_Out_DBx__4__INP_DIS CYREG_PRT2_INP_DIS
+#define SCSI_Out_DBx__4__INTTYPE CYREG_PICU2_INTTYPE5
+#define SCSI_Out_DBx__4__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
+#define SCSI_Out_DBx__4__LCD_EN CYREG_PRT2_LCD_EN
+#define SCSI_Out_DBx__4__MASK 0x20u
+#define SCSI_Out_DBx__4__PC CYREG_PRT2_PC5
+#define SCSI_Out_DBx__4__PORT 2u
+#define SCSI_Out_DBx__4__PRT CYREG_PRT2_PRT
+#define SCSI_Out_DBx__4__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
+#define SCSI_Out_DBx__4__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
+#define SCSI_Out_DBx__4__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
+#define SCSI_Out_DBx__4__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
+#define SCSI_Out_DBx__4__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
+#define SCSI_Out_DBx__4__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
+#define SCSI_Out_DBx__4__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
+#define SCSI_Out_DBx__4__PS CYREG_PRT2_PS
+#define SCSI_Out_DBx__4__SHIFT 5u
+#define SCSI_Out_DBx__4__SLW CYREG_PRT2_SLW
+#define SCSI_Out_DBx__5__AG CYREG_PRT2_AG
+#define SCSI_Out_DBx__5__AMUX CYREG_PRT2_AMUX
+#define SCSI_Out_DBx__5__BIE CYREG_PRT2_BIE
+#define SCSI_Out_DBx__5__BIT_MASK CYREG_PRT2_BIT_MASK
+#define SCSI_Out_DBx__5__BYP CYREG_PRT2_BYP
+#define SCSI_Out_DBx__5__CTL CYREG_PRT2_CTL
+#define SCSI_Out_DBx__5__DM0 CYREG_PRT2_DM0
+#define SCSI_Out_DBx__5__DM1 CYREG_PRT2_DM1
+#define SCSI_Out_DBx__5__DM2 CYREG_PRT2_DM2
+#define SCSI_Out_DBx__5__DR CYREG_PRT2_DR
+#define SCSI_Out_DBx__5__INP_DIS CYREG_PRT2_INP_DIS
+#define SCSI_Out_DBx__5__INTTYPE CYREG_PICU2_INTTYPE3
+#define SCSI_Out_DBx__5__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
+#define SCSI_Out_DBx__5__LCD_EN CYREG_PRT2_LCD_EN
+#define SCSI_Out_DBx__5__MASK 0x08u
+#define SCSI_Out_DBx__5__PC CYREG_PRT2_PC3
+#define SCSI_Out_DBx__5__PORT 2u
+#define SCSI_Out_DBx__5__PRT CYREG_PRT2_PRT
+#define SCSI_Out_DBx__5__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
+#define SCSI_Out_DBx__5__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
+#define SCSI_Out_DBx__5__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
+#define SCSI_Out_DBx__5__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
+#define SCSI_Out_DBx__5__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
+#define SCSI_Out_DBx__5__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
+#define SCSI_Out_DBx__5__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
+#define SCSI_Out_DBx__5__PS CYREG_PRT2_PS
+#define SCSI_Out_DBx__5__SHIFT 3u
+#define SCSI_Out_DBx__5__SLW CYREG_PRT2_SLW
+#define SCSI_Out_DBx__6__AG CYREG_PRT2_AG
+#define SCSI_Out_DBx__6__AMUX CYREG_PRT2_AMUX
+#define SCSI_Out_DBx__6__BIE CYREG_PRT2_BIE
+#define SCSI_Out_DBx__6__BIT_MASK CYREG_PRT2_BIT_MASK
+#define SCSI_Out_DBx__6__BYP CYREG_PRT2_BYP
+#define SCSI_Out_DBx__6__CTL CYREG_PRT2_CTL
+#define SCSI_Out_DBx__6__DM0 CYREG_PRT2_DM0
+#define SCSI_Out_DBx__6__DM1 CYREG_PRT2_DM1
+#define SCSI_Out_DBx__6__DM2 CYREG_PRT2_DM2
+#define SCSI_Out_DBx__6__DR CYREG_PRT2_DR
+#define SCSI_Out_DBx__6__INP_DIS CYREG_PRT2_INP_DIS
+#define SCSI_Out_DBx__6__INTTYPE CYREG_PICU2_INTTYPE1
+#define SCSI_Out_DBx__6__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
+#define SCSI_Out_DBx__6__LCD_EN CYREG_PRT2_LCD_EN
+#define SCSI_Out_DBx__6__MASK 0x02u
+#define SCSI_Out_DBx__6__PC CYREG_PRT2_PC1
+#define SCSI_Out_DBx__6__PORT 2u
+#define SCSI_Out_DBx__6__PRT CYREG_PRT2_PRT
+#define SCSI_Out_DBx__6__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
+#define SCSI_Out_DBx__6__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
+#define SCSI_Out_DBx__6__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
+#define SCSI_Out_DBx__6__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
+#define SCSI_Out_DBx__6__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
+#define SCSI_Out_DBx__6__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
+#define SCSI_Out_DBx__6__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
+#define SCSI_Out_DBx__6__PS CYREG_PRT2_PS
+#define SCSI_Out_DBx__6__SHIFT 1u
+#define SCSI_Out_DBx__6__SLW CYREG_PRT2_SLW
+#define SCSI_Out_DBx__7__AG CYREG_PRT15_AG
+#define SCSI_Out_DBx__7__AMUX CYREG_PRT15_AMUX
+#define SCSI_Out_DBx__7__BIE CYREG_PRT15_BIE
+#define SCSI_Out_DBx__7__BIT_MASK CYREG_PRT15_BIT_MASK
+#define SCSI_Out_DBx__7__BYP CYREG_PRT15_BYP
+#define SCSI_Out_DBx__7__CTL CYREG_PRT15_CTL
+#define SCSI_Out_DBx__7__DM0 CYREG_PRT15_DM0
+#define SCSI_Out_DBx__7__DM1 CYREG_PRT15_DM1
+#define SCSI_Out_DBx__7__DM2 CYREG_PRT15_DM2
+#define SCSI_Out_DBx__7__DR CYREG_PRT15_DR
+#define SCSI_Out_DBx__7__INP_DIS CYREG_PRT15_INP_DIS
+#define SCSI_Out_DBx__7__INTTYPE CYREG_PICU15_INTTYPE5
+#define SCSI_Out_DBx__7__LCD_COM_SEG CYREG_PRT15_LCD_COM_SEG
+#define SCSI_Out_DBx__7__LCD_EN CYREG_PRT15_LCD_EN
+#define SCSI_Out_DBx__7__MASK 0x20u
+#define SCSI_Out_DBx__7__PC CYREG_IO_PC_PRT15_PC5
+#define SCSI_Out_DBx__7__PORT 15u
+#define SCSI_Out_DBx__7__PRT CYREG_PRT15_PRT
+#define SCSI_Out_DBx__7__PRTDSI__CAPS_SEL CYREG_PRT15_CAPS_SEL
+#define SCSI_Out_DBx__7__PRTDSI__DBL_SYNC_IN CYREG_PRT15_DBL_SYNC_IN
+#define SCSI_Out_DBx__7__PRTDSI__OE_SEL0 CYREG_PRT15_OE_SEL0
+#define SCSI_Out_DBx__7__PRTDSI__OE_SEL1 CYREG_PRT15_OE_SEL1
+#define SCSI_Out_DBx__7__PRTDSI__OUT_SEL0 CYREG_PRT15_OUT_SEL0
+#define SCSI_Out_DBx__7__PRTDSI__OUT_SEL1 CYREG_PRT15_OUT_SEL1
+#define SCSI_Out_DBx__7__PRTDSI__SYNC_OUT CYREG_PRT15_SYNC_OUT
+#define SCSI_Out_DBx__7__PS CYREG_PRT15_PS
+#define SCSI_Out_DBx__7__SHIFT 5u
+#define SCSI_Out_DBx__7__SLW CYREG_PRT15_SLW
+#define SCSI_Out_DBx__DB0__AG CYREG_PRT6_AG
+#define SCSI_Out_DBx__DB0__AMUX CYREG_PRT6_AMUX
+#define SCSI_Out_DBx__DB0__BIE CYREG_PRT6_BIE
+#define SCSI_Out_DBx__DB0__BIT_MASK CYREG_PRT6_BIT_MASK
+#define SCSI_Out_DBx__DB0__BYP CYREG_PRT6_BYP
+#define SCSI_Out_DBx__DB0__CTL CYREG_PRT6_CTL
+#define SCSI_Out_DBx__DB0__DM0 CYREG_PRT6_DM0
+#define SCSI_Out_DBx__DB0__DM1 CYREG_PRT6_DM1
+#define SCSI_Out_DBx__DB0__DM2 CYREG_PRT6_DM2
+#define SCSI_Out_DBx__DB0__DR CYREG_PRT6_DR
+#define SCSI_Out_DBx__DB0__INP_DIS CYREG_PRT6_INP_DIS
+#define SCSI_Out_DBx__DB0__INTTYPE CYREG_PICU6_INTTYPE7
+#define SCSI_Out_DBx__DB0__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
+#define SCSI_Out_DBx__DB0__LCD_EN CYREG_PRT6_LCD_EN
+#define SCSI_Out_DBx__DB0__MASK 0x80u
+#define SCSI_Out_DBx__DB0__PC CYREG_PRT6_PC7
+#define SCSI_Out_DBx__DB0__PORT 6u
+#define SCSI_Out_DBx__DB0__PRT CYREG_PRT6_PRT
+#define SCSI_Out_DBx__DB0__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
+#define SCSI_Out_DBx__DB0__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
+#define SCSI_Out_DBx__DB0__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
+#define SCSI_Out_DBx__DB0__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
+#define SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
+#define SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
+#define SCSI_Out_DBx__DB0__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
+#define SCSI_Out_DBx__DB0__PS CYREG_PRT6_PS
+#define SCSI_Out_DBx__DB0__SHIFT 7u
+#define SCSI_Out_DBx__DB0__SLW CYREG_PRT6_SLW
+#define SCSI_Out_DBx__DB1__AG CYREG_PRT6_AG
+#define SCSI_Out_DBx__DB1__AMUX CYREG_PRT6_AMUX
+#define SCSI_Out_DBx__DB1__BIE CYREG_PRT6_BIE
+#define SCSI_Out_DBx__DB1__BIT_MASK CYREG_PRT6_BIT_MASK
+#define SCSI_Out_DBx__DB1__BYP CYREG_PRT6_BYP
+#define SCSI_Out_DBx__DB1__CTL CYREG_PRT6_CTL
+#define SCSI_Out_DBx__DB1__DM0 CYREG_PRT6_DM0
+#define SCSI_Out_DBx__DB1__DM1 CYREG_PRT6_DM1
+#define SCSI_Out_DBx__DB1__DM2 CYREG_PRT6_DM2
+#define SCSI_Out_DBx__DB1__DR CYREG_PRT6_DR
+#define SCSI_Out_DBx__DB1__INP_DIS CYREG_PRT6_INP_DIS
+#define SCSI_Out_DBx__DB1__INTTYPE CYREG_PICU6_INTTYPE5
+#define SCSI_Out_DBx__DB1__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
+#define SCSI_Out_DBx__DB1__LCD_EN CYREG_PRT6_LCD_EN
+#define SCSI_Out_DBx__DB1__MASK 0x20u
+#define SCSI_Out_DBx__DB1__PC CYREG_PRT6_PC5
+#define SCSI_Out_DBx__DB1__PORT 6u
+#define SCSI_Out_DBx__DB1__PRT CYREG_PRT6_PRT
+#define SCSI_Out_DBx__DB1__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
+#define SCSI_Out_DBx__DB1__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
+#define SCSI_Out_DBx__DB1__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
+#define SCSI_Out_DBx__DB1__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
+#define SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
+#define SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
+#define SCSI_Out_DBx__DB1__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
+#define SCSI_Out_DBx__DB1__PS CYREG_PRT6_PS
+#define SCSI_Out_DBx__DB1__SHIFT 5u
+#define SCSI_Out_DBx__DB1__SLW CYREG_PRT6_SLW
+#define SCSI_Out_DBx__DB2__AG CYREG_PRT12_AG
+#define SCSI_Out_DBx__DB2__BIE CYREG_PRT12_BIE
+#define SCSI_Out_DBx__DB2__BIT_MASK CYREG_PRT12_BIT_MASK
+#define SCSI_Out_DBx__DB2__BYP CYREG_PRT12_BYP
+#define SCSI_Out_DBx__DB2__DM0 CYREG_PRT12_DM0
+#define SCSI_Out_DBx__DB2__DM1 CYREG_PRT12_DM1
+#define SCSI_Out_DBx__DB2__DM2 CYREG_PRT12_DM2
+#define SCSI_Out_DBx__DB2__DR CYREG_PRT12_DR
+#define SCSI_Out_DBx__DB2__INP_DIS CYREG_PRT12_INP_DIS
+#define SCSI_Out_DBx__DB2__INTTYPE CYREG_PICU12_INTTYPE5
+#define SCSI_Out_DBx__DB2__MASK 0x20u
+#define SCSI_Out_DBx__DB2__PC CYREG_PRT12_PC5
+#define SCSI_Out_DBx__DB2__PORT 12u
+#define SCSI_Out_DBx__DB2__PRT CYREG_PRT12_PRT
+#define SCSI_Out_DBx__DB2__PRTDSI__DBL_SYNC_IN CYREG_PRT12_DBL_SYNC_IN
+#define SCSI_Out_DBx__DB2__PRTDSI__OE_SEL0 CYREG_PRT12_OE_SEL0
+#define SCSI_Out_DBx__DB2__PRTDSI__OE_SEL1 CYREG_PRT12_OE_SEL1
+#define SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL0 CYREG_PRT12_OUT_SEL0
+#define SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL1 CYREG_PRT12_OUT_SEL1
+#define SCSI_Out_DBx__DB2__PRTDSI__SYNC_OUT CYREG_PRT12_SYNC_OUT
+#define SCSI_Out_DBx__DB2__PS CYREG_PRT12_PS
+#define SCSI_Out_DBx__DB2__SHIFT 5u
+#define SCSI_Out_DBx__DB2__SIO_CFG CYREG_PRT12_SIO_CFG
+#define SCSI_Out_DBx__DB2__SIO_DIFF CYREG_PRT12_SIO_DIFF
+#define SCSI_Out_DBx__DB2__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN
+#define SCSI_Out_DBx__DB2__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ
+#define SCSI_Out_DBx__DB2__SLW CYREG_PRT12_SLW
+#define SCSI_Out_DBx__DB3__AG CYREG_PRT2_AG
+#define SCSI_Out_DBx__DB3__AMUX CYREG_PRT2_AMUX
+#define SCSI_Out_DBx__DB3__BIE CYREG_PRT2_BIE
+#define SCSI_Out_DBx__DB3__BIT_MASK CYREG_PRT2_BIT_MASK
+#define SCSI_Out_DBx__DB3__BYP CYREG_PRT2_BYP
+#define SCSI_Out_DBx__DB3__CTL CYREG_PRT2_CTL
+#define SCSI_Out_DBx__DB3__DM0 CYREG_PRT2_DM0
+#define SCSI_Out_DBx__DB3__DM1 CYREG_PRT2_DM1
+#define SCSI_Out_DBx__DB3__DM2 CYREG_PRT2_DM2
+#define SCSI_Out_DBx__DB3__DR CYREG_PRT2_DR
+#define SCSI_Out_DBx__DB3__INP_DIS CYREG_PRT2_INP_DIS
+#define SCSI_Out_DBx__DB3__INTTYPE CYREG_PICU2_INTTYPE7
+#define SCSI_Out_DBx__DB3__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
+#define SCSI_Out_DBx__DB3__LCD_EN CYREG_PRT2_LCD_EN
+#define SCSI_Out_DBx__DB3__MASK 0x80u
+#define SCSI_Out_DBx__DB3__PC CYREG_PRT2_PC7
+#define SCSI_Out_DBx__DB3__PORT 2u
+#define SCSI_Out_DBx__DB3__PRT CYREG_PRT2_PRT
+#define SCSI_Out_DBx__DB3__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
+#define SCSI_Out_DBx__DB3__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
+#define SCSI_Out_DBx__DB3__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
+#define SCSI_Out_DBx__DB3__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
+#define SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
+#define SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
+#define SCSI_Out_DBx__DB3__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
+#define SCSI_Out_DBx__DB3__PS CYREG_PRT2_PS
+#define SCSI_Out_DBx__DB3__SHIFT 7u
+#define SCSI_Out_DBx__DB3__SLW CYREG_PRT2_SLW
+#define SCSI_Out_DBx__DB4__AG CYREG_PRT2_AG
+#define SCSI_Out_DBx__DB4__AMUX CYREG_PRT2_AMUX
+#define SCSI_Out_DBx__DB4__BIE CYREG_PRT2_BIE
+#define SCSI_Out_DBx__DB4__BIT_MASK CYREG_PRT2_BIT_MASK
+#define SCSI_Out_DBx__DB4__BYP CYREG_PRT2_BYP
+#define SCSI_Out_DBx__DB4__CTL CYREG_PRT2_CTL
+#define SCSI_Out_DBx__DB4__DM0 CYREG_PRT2_DM0
+#define SCSI_Out_DBx__DB4__DM1 CYREG_PRT2_DM1
+#define SCSI_Out_DBx__DB4__DM2 CYREG_PRT2_DM2
+#define SCSI_Out_DBx__DB4__DR CYREG_PRT2_DR
+#define SCSI_Out_DBx__DB4__INP_DIS CYREG_PRT2_INP_DIS
+#define SCSI_Out_DBx__DB4__INTTYPE CYREG_PICU2_INTTYPE5
+#define SCSI_Out_DBx__DB4__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
+#define SCSI_Out_DBx__DB4__LCD_EN CYREG_PRT2_LCD_EN
+#define SCSI_Out_DBx__DB4__MASK 0x20u
+#define SCSI_Out_DBx__DB4__PC CYREG_PRT2_PC5
+#define SCSI_Out_DBx__DB4__PORT 2u
+#define SCSI_Out_DBx__DB4__PRT CYREG_PRT2_PRT
+#define SCSI_Out_DBx__DB4__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
+#define SCSI_Out_DBx__DB4__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
+#define SCSI_Out_DBx__DB4__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
+#define SCSI_Out_DBx__DB4__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
+#define SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
+#define SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
+#define SCSI_Out_DBx__DB4__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
+#define SCSI_Out_DBx__DB4__PS CYREG_PRT2_PS
+#define SCSI_Out_DBx__DB4__SHIFT 5u
+#define SCSI_Out_DBx__DB4__SLW CYREG_PRT2_SLW
+#define SCSI_Out_DBx__DB5__AG CYREG_PRT2_AG
+#define SCSI_Out_DBx__DB5__AMUX CYREG_PRT2_AMUX
+#define SCSI_Out_DBx__DB5__BIE CYREG_PRT2_BIE
+#define SCSI_Out_DBx__DB5__BIT_MASK CYREG_PRT2_BIT_MASK
+#define SCSI_Out_DBx__DB5__BYP CYREG_PRT2_BYP
+#define SCSI_Out_DBx__DB5__CTL CYREG_PRT2_CTL
+#define SCSI_Out_DBx__DB5__DM0 CYREG_PRT2_DM0
+#define SCSI_Out_DBx__DB5__DM1 CYREG_PRT2_DM1
+#define SCSI_Out_DBx__DB5__DM2 CYREG_PRT2_DM2
+#define SCSI_Out_DBx__DB5__DR CYREG_PRT2_DR
+#define SCSI_Out_DBx__DB5__INP_DIS CYREG_PRT2_INP_DIS
+#define SCSI_Out_DBx__DB5__INTTYPE CYREG_PICU2_INTTYPE3
+#define SCSI_Out_DBx__DB5__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
+#define SCSI_Out_DBx__DB5__LCD_EN CYREG_PRT2_LCD_EN
+#define SCSI_Out_DBx__DB5__MASK 0x08u
+#define SCSI_Out_DBx__DB5__PC CYREG_PRT2_PC3
+#define SCSI_Out_DBx__DB5__PORT 2u
+#define SCSI_Out_DBx__DB5__PRT CYREG_PRT2_PRT
+#define SCSI_Out_DBx__DB5__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
+#define SCSI_Out_DBx__DB5__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
+#define SCSI_Out_DBx__DB5__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
+#define SCSI_Out_DBx__DB5__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
+#define SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
+#define SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
+#define SCSI_Out_DBx__DB5__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
+#define SCSI_Out_DBx__DB5__PS CYREG_PRT2_PS
+#define SCSI_Out_DBx__DB5__SHIFT 3u
+#define SCSI_Out_DBx__DB5__SLW CYREG_PRT2_SLW
+#define SCSI_Out_DBx__DB6__AG CYREG_PRT2_AG
+#define SCSI_Out_DBx__DB6__AMUX CYREG_PRT2_AMUX
+#define SCSI_Out_DBx__DB6__BIE CYREG_PRT2_BIE
+#define SCSI_Out_DBx__DB6__BIT_MASK CYREG_PRT2_BIT_MASK
+#define SCSI_Out_DBx__DB6__BYP CYREG_PRT2_BYP
+#define SCSI_Out_DBx__DB6__CTL CYREG_PRT2_CTL
+#define SCSI_Out_DBx__DB6__DM0 CYREG_PRT2_DM0
+#define SCSI_Out_DBx__DB6__DM1 CYREG_PRT2_DM1
+#define SCSI_Out_DBx__DB6__DM2 CYREG_PRT2_DM2
+#define SCSI_Out_DBx__DB6__DR CYREG_PRT2_DR
+#define SCSI_Out_DBx__DB6__INP_DIS CYREG_PRT2_INP_DIS
+#define SCSI_Out_DBx__DB6__INTTYPE CYREG_PICU2_INTTYPE1
+#define SCSI_Out_DBx__DB6__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
+#define SCSI_Out_DBx__DB6__LCD_EN CYREG_PRT2_LCD_EN
+#define SCSI_Out_DBx__DB6__MASK 0x02u
+#define SCSI_Out_DBx__DB6__PC CYREG_PRT2_PC1
+#define SCSI_Out_DBx__DB6__PORT 2u
+#define SCSI_Out_DBx__DB6__PRT CYREG_PRT2_PRT
+#define SCSI_Out_DBx__DB6__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
+#define SCSI_Out_DBx__DB6__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
+#define SCSI_Out_DBx__DB6__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
+#define SCSI_Out_DBx__DB6__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
+#define SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
+#define SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
+#define SCSI_Out_DBx__DB6__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
+#define SCSI_Out_DBx__DB6__PS CYREG_PRT2_PS
+#define SCSI_Out_DBx__DB6__SHIFT 1u
+#define SCSI_Out_DBx__DB6__SLW CYREG_PRT2_SLW
+#define SCSI_Out_DBx__DB7__AG CYREG_PRT15_AG
+#define SCSI_Out_DBx__DB7__AMUX CYREG_PRT15_AMUX
+#define SCSI_Out_DBx__DB7__BIE CYREG_PRT15_BIE
+#define SCSI_Out_DBx__DB7__BIT_MASK CYREG_PRT15_BIT_MASK
+#define SCSI_Out_DBx__DB7__BYP CYREG_PRT15_BYP
+#define SCSI_Out_DBx__DB7__CTL CYREG_PRT15_CTL
+#define SCSI_Out_DBx__DB7__DM0 CYREG_PRT15_DM0
+#define SCSI_Out_DBx__DB7__DM1 CYREG_PRT15_DM1
+#define SCSI_Out_DBx__DB7__DM2 CYREG_PRT15_DM2
+#define SCSI_Out_DBx__DB7__DR CYREG_PRT15_DR
+#define SCSI_Out_DBx__DB7__INP_DIS CYREG_PRT15_INP_DIS
+#define SCSI_Out_DBx__DB7__INTTYPE CYREG_PICU15_INTTYPE5
+#define SCSI_Out_DBx__DB7__LCD_COM_SEG CYREG_PRT15_LCD_COM_SEG
+#define SCSI_Out_DBx__DB7__LCD_EN CYREG_PRT15_LCD_EN
+#define SCSI_Out_DBx__DB7__MASK 0x20u
+#define SCSI_Out_DBx__DB7__PC CYREG_IO_PC_PRT15_PC5
+#define SCSI_Out_DBx__DB7__PORT 15u
+#define SCSI_Out_DBx__DB7__PRT CYREG_PRT15_PRT
+#define SCSI_Out_DBx__DB7__PRTDSI__CAPS_SEL CYREG_PRT15_CAPS_SEL
+#define SCSI_Out_DBx__DB7__PRTDSI__DBL_SYNC_IN CYREG_PRT15_DBL_SYNC_IN
+#define SCSI_Out_DBx__DB7__PRTDSI__OE_SEL0 CYREG_PRT15_OE_SEL0
+#define SCSI_Out_DBx__DB7__PRTDSI__OE_SEL1 CYREG_PRT15_OE_SEL1
+#define SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL0 CYREG_PRT15_OUT_SEL0
+#define SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL1 CYREG_PRT15_OUT_SEL1
+#define SCSI_Out_DBx__DB7__PRTDSI__SYNC_OUT CYREG_PRT15_SYNC_OUT
+#define SCSI_Out_DBx__DB7__PS CYREG_PRT15_PS
+#define SCSI_Out_DBx__DB7__SHIFT 5u
+#define SCSI_Out_DBx__DB7__SLW CYREG_PRT15_SLW
+
+/* SCSI_Parity_Error */
+#define SCSI_Parity_Error_sts_sts_reg__0__MASK 0x01u
+#define SCSI_Parity_Error_sts_sts_reg__0__POS 0
+#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB02_03_ACTL
+#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB02_03_ST
+#define SCSI_Parity_Error_sts_sts_reg__MASK 0x01u
+#define SCSI_Parity_Error_sts_sts_reg__MASK_REG CYREG_B0_UDB02_MSK
+#define SCSI_Parity_Error_sts_sts_reg__MASK_ST_AUX_CTL_REG CYREG_B0_UDB02_MSK_ACTL
+#define SCSI_Parity_Error_sts_sts_reg__PER_ST_AUX_CTL_REG CYREG_B0_UDB02_MSK_ACTL
+#define SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB02_ACTL
+#define SCSI_Parity_Error_sts_sts_reg__STATUS_CNT_REG CYREG_B0_UDB02_ST_CTL
+#define SCSI_Parity_Error_sts_sts_reg__STATUS_CONTROL_REG CYREG_B0_UDB02_ST_CTL
+#define SCSI_Parity_Error_sts_sts_reg__STATUS_REG CYREG_B0_UDB02_ST
+
+/* SCSI_RST_ISR */
+#define SCSI_RST_ISR__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
+#define SCSI_RST_ISR__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
+#define SCSI_RST_ISR__INTC_MASK 0x02u
+#define SCSI_RST_ISR__INTC_NUMBER 1u
+#define SCSI_RST_ISR__INTC_PRIOR_NUM 7u
+#define SCSI_RST_ISR__INTC_PRIOR_REG CYREG_NVIC_PRI_1
+#define SCSI_RST_ISR__INTC_SET_EN_REG CYREG_NVIC_SETENA0
+#define SCSI_RST_ISR__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
+
+/* SCSI_RX_DMA */
+#define SCSI_RX_DMA__DRQ_CTL CYREG_IDMUX_DRQ_CTL0
+#define SCSI_RX_DMA__DRQ_NUMBER 0u
+#define SCSI_RX_DMA__NUMBEROF_TDS 0u
+#define SCSI_RX_DMA__PRIORITY 2u
+#define SCSI_RX_DMA__TERMIN_EN 0u
+#define SCSI_RX_DMA__TERMIN_SEL 0u
+#define SCSI_RX_DMA__TERMOUT0_EN 1u
+#define SCSI_RX_DMA__TERMOUT0_SEL 0u
+#define SCSI_RX_DMA__TERMOUT1_EN 0u
+#define SCSI_RX_DMA__TERMOUT1_SEL 0u
+#define SCSI_RX_DMA_COMPLETE__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
+#define SCSI_RX_DMA_COMPLETE__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
+#define SCSI_RX_DMA_COMPLETE__INTC_MASK 0x04u
+#define SCSI_RX_DMA_COMPLETE__INTC_NUMBER 2u
+#define SCSI_RX_DMA_COMPLETE__INTC_PRIOR_NUM 7u
+#define SCSI_RX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_2
+#define SCSI_RX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0
+#define SCSI_RX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
+
+/* SCSI_SEL_ISR */
+#define SCSI_SEL_ISR__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
+#define SCSI_SEL_ISR__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
+#define SCSI_SEL_ISR__INTC_MASK 0x08u
+#define SCSI_SEL_ISR__INTC_NUMBER 3u
+#define SCSI_SEL_ISR__INTC_PRIOR_NUM 7u
+#define SCSI_SEL_ISR__INTC_PRIOR_REG CYREG_NVIC_PRI_3
+#define SCSI_SEL_ISR__INTC_SET_EN_REG CYREG_NVIC_SETENA0
+#define SCSI_SEL_ISR__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
+
+/* SCSI_TX_DMA */
+#define SCSI_TX_DMA__DRQ_CTL CYREG_IDMUX_DRQ_CTL0
+#define SCSI_TX_DMA__DRQ_NUMBER 1u
+#define SCSI_TX_DMA__NUMBEROF_TDS 0u
+#define SCSI_TX_DMA__PRIORITY 2u
+#define SCSI_TX_DMA__TERMIN_EN 0u
+#define SCSI_TX_DMA__TERMIN_SEL 0u
+#define SCSI_TX_DMA__TERMOUT0_EN 1u
+#define SCSI_TX_DMA__TERMOUT0_SEL 1u
+#define SCSI_TX_DMA__TERMOUT1_EN 0u
+#define SCSI_TX_DMA__TERMOUT1_SEL 0u
+#define SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
+#define SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
+#define SCSI_TX_DMA_COMPLETE__INTC_MASK 0x10u
+#define SCSI_TX_DMA_COMPLETE__INTC_NUMBER 4u
+#define SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM 7u
+#define SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_4
+#define SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0
+#define SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
+
+/* SDCard_BSPIM */
+#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB04_05_ACTL
+#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB04_05_CTL
+#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB04_05_CTL
+#define SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB04_05_CTL
+#define SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B1_UDB04_05_CTL
+#define SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B1_UDB04_05_MSK
+#define SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B1_UDB04_05_MSK
+#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B1_UDB04_05_MSK
+#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB04_05_MSK
+#define SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B1_UDB04_ACTL
+#define SDCard_BSPIM_BitCounter__CONTROL_REG CYREG_B1_UDB04_CTL
+#define SDCard_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B1_UDB04_ST_CTL
+#define SDCard_BSPIM_BitCounter__COUNT_REG CYREG_B1_UDB04_CTL
+#define SDCard_BSPIM_BitCounter__COUNT_ST_REG CYREG_B1_UDB04_ST_CTL
+#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL
+#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL
+#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B1_UDB04_MSK
+#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB04_05_ACTL
+#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B1_UDB04_05_ST
+#define SDCard_BSPIM_BitCounter_ST__MASK_REG CYREG_B1_UDB04_MSK
+#define SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL
+#define SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL
+#define SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B1_UDB04_ACTL
+#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B1_UDB04_ST_CTL
+#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B1_UDB04_ST_CTL
+#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B1_UDB04_ST
+#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB07_08_ACTL
+#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B0_UDB07_08_ST
+#define SDCard_BSPIM_RxStsReg__4__MASK 0x10u
+#define SDCard_BSPIM_RxStsReg__4__POS 4
+#define SDCard_BSPIM_RxStsReg__5__MASK 0x20u
+#define SDCard_BSPIM_RxStsReg__5__POS 5
+#define SDCard_BSPIM_RxStsReg__6__MASK 0x40u
+#define SDCard_BSPIM_RxStsReg__6__POS 6
+#define SDCard_BSPIM_RxStsReg__MASK 0x70u
+#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B0_UDB07_MSK
+#define SDCard_BSPIM_RxStsReg__MASK_ST_AUX_CTL_REG CYREG_B0_UDB07_MSK_ACTL
+#define SDCard_BSPIM_RxStsReg__PER_ST_AUX_CTL_REG CYREG_B0_UDB07_MSK_ACTL
+#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB07_ACTL
+#define SDCard_BSPIM_RxStsReg__STATUS_CNT_REG CYREG_B0_UDB07_ST_CTL
+#define SDCard_BSPIM_RxStsReg__STATUS_CONTROL_REG CYREG_B0_UDB07_ST_CTL
+#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B0_UDB07_ST
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B1_UDB04_05_A0
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B1_UDB04_05_A1
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG CYREG_B1_UDB04_05_D0
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG CYREG_B1_UDB04_05_D1
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG CYREG_B1_UDB04_05_ACTL
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG CYREG_B1_UDB04_05_F0
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG CYREG_B1_UDB04_05_F1
+#define SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG CYREG_B1_UDB04_A0_A1
+#define SDCard_BSPIM_sR8_Dp_u0__A0_REG CYREG_B1_UDB04_A0
+#define SDCard_BSPIM_sR8_Dp_u0__A1_REG CYREG_B1_UDB04_A1
+#define SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG CYREG_B1_UDB04_D0_D1
+#define SDCard_BSPIM_sR8_Dp_u0__D0_REG CYREG_B1_UDB04_D0
+#define SDCard_BSPIM_sR8_Dp_u0__D1_REG CYREG_B1_UDB04_D1
+#define SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG CYREG_B1_UDB04_ACTL
+#define SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG CYREG_B1_UDB04_F0_F1
+#define SDCard_BSPIM_sR8_Dp_u0__F0_REG CYREG_B1_UDB04_F0
+#define SDCard_BSPIM_sR8_Dp_u0__F1_REG CYREG_B1_UDB04_F1
+#define SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL
+#define SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL
+#define SDCard_BSPIM_TxStsReg__0__MASK 0x01u
+#define SDCard_BSPIM_TxStsReg__0__POS 0
+#define SDCard_BSPIM_TxStsReg__1__MASK 0x02u
+#define SDCard_BSPIM_TxStsReg__1__POS 1
+#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB07_08_ACTL
+#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B1_UDB07_08_ST
+#define SDCard_BSPIM_TxStsReg__2__MASK 0x04u
+#define SDCard_BSPIM_TxStsReg__2__POS 2
+#define SDCard_BSPIM_TxStsReg__3__MASK 0x08u
+#define SDCard_BSPIM_TxStsReg__3__POS 3
+#define SDCard_BSPIM_TxStsReg__4__MASK 0x10u
+#define SDCard_BSPIM_TxStsReg__4__POS 4
+#define SDCard_BSPIM_TxStsReg__MASK 0x1Fu
+#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B1_UDB07_MSK
+#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB07_ACTL
+#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B1_UDB07_ST
+
+/* SD_CS */
+#define SD_CS__0__INTTYPE CYREG_PICU3_INTTYPE5
+#define SD_CS__0__MASK 0x20u
+#define SD_CS__0__PC CYREG_PRT3_PC5
+#define SD_CS__0__PORT 3u
+#define SD_CS__0__SHIFT 5u
+#define SD_CS__AG CYREG_PRT3_AG
+#define SD_CS__AMUX CYREG_PRT3_AMUX
+#define SD_CS__BIE CYREG_PRT3_BIE
+#define SD_CS__BIT_MASK CYREG_PRT3_BIT_MASK
+#define SD_CS__BYP CYREG_PRT3_BYP
+#define SD_CS__CTL CYREG_PRT3_CTL
+#define SD_CS__DM0 CYREG_PRT3_DM0
+#define SD_CS__DM1 CYREG_PRT3_DM1
+#define SD_CS__DM2 CYREG_PRT3_DM2
+#define SD_CS__DR CYREG_PRT3_DR
+#define SD_CS__INP_DIS CYREG_PRT3_INP_DIS
+#define SD_CS__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU3_BASE
+#define SD_CS__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG
+#define SD_CS__LCD_EN CYREG_PRT3_LCD_EN
+#define SD_CS__MASK 0x20u
+#define SD_CS__PORT 3u
+#define SD_CS__PRT CYREG_PRT3_PRT
+#define SD_CS__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL
+#define SD_CS__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN
+#define SD_CS__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0
+#define SD_CS__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1
+#define SD_CS__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0
+#define SD_CS__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1
+#define SD_CS__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT
+#define SD_CS__PS CYREG_PRT3_PS
+#define SD_CS__SHIFT 5u
+#define SD_CS__SLW CYREG_PRT3_SLW
+
+/* SD_Data_Clk */
+#define SD_Data_Clk__CFG0 CYREG_CLKDIST_DCFG0_CFG0
+#define SD_Data_Clk__CFG1 CYREG_CLKDIST_DCFG0_CFG1
+#define SD_Data_Clk__CFG2 CYREG_CLKDIST_DCFG0_CFG2
+#define SD_Data_Clk__CFG2_SRC_SEL_MASK 0x07u
+#define SD_Data_Clk__INDEX 0x00u
+#define SD_Data_Clk__PM_ACT_CFG CYREG_PM_ACT_CFG2
+#define SD_Data_Clk__PM_ACT_MSK 0x01u
+#define SD_Data_Clk__PM_STBY_CFG CYREG_PM_STBY_CFG2
+#define SD_Data_Clk__PM_STBY_MSK 0x01u
+
+/* SD_MISO */
+#define SD_MISO__0__INTTYPE CYREG_PICU3_INTTYPE2
+#define SD_MISO__0__MASK 0x04u
+#define SD_MISO__0__PC CYREG_PRT3_PC2
+#define SD_MISO__0__PORT 3u
+#define SD_MISO__0__SHIFT 2u
+#define SD_MISO__AG CYREG_PRT3_AG
+#define SD_MISO__AMUX CYREG_PRT3_AMUX
+#define SD_MISO__BIE CYREG_PRT3_BIE
+#define SD_MISO__BIT_MASK CYREG_PRT3_BIT_MASK
+#define SD_MISO__BYP CYREG_PRT3_BYP
+#define SD_MISO__CTL CYREG_PRT3_CTL
+#define SD_MISO__DM0 CYREG_PRT3_DM0
+#define SD_MISO__DM1 CYREG_PRT3_DM1
+#define SD_MISO__DM2 CYREG_PRT3_DM2
+#define SD_MISO__DR CYREG_PRT3_DR
+#define SD_MISO__INP_DIS CYREG_PRT3_INP_DIS
+#define SD_MISO__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU3_BASE
+#define SD_MISO__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG
+#define SD_MISO__LCD_EN CYREG_PRT3_LCD_EN
+#define SD_MISO__MASK 0x04u
+#define SD_MISO__PORT 3u
+#define SD_MISO__PRT CYREG_PRT3_PRT
+#define SD_MISO__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL
+#define SD_MISO__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN
+#define SD_MISO__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0
+#define SD_MISO__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1
+#define SD_MISO__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0
+#define SD_MISO__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1
+#define SD_MISO__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT
+#define SD_MISO__PS CYREG_PRT3_PS
+#define SD_MISO__SHIFT 2u
+#define SD_MISO__SLW CYREG_PRT3_SLW
+
+/* SD_MOSI */
+#define SD_MOSI__0__INTTYPE CYREG_PICU3_INTTYPE4
+#define SD_MOSI__0__MASK 0x10u
+#define SD_MOSI__0__PC CYREG_PRT3_PC4
+#define SD_MOSI__0__PORT 3u
+#define SD_MOSI__0__SHIFT 4u
+#define SD_MOSI__AG CYREG_PRT3_AG
+#define SD_MOSI__AMUX CYREG_PRT3_AMUX
+#define SD_MOSI__BIE CYREG_PRT3_BIE
+#define SD_MOSI__BIT_MASK CYREG_PRT3_BIT_MASK
+#define SD_MOSI__BYP CYREG_PRT3_BYP
+#define SD_MOSI__CTL CYREG_PRT3_CTL
+#define SD_MOSI__DM0 CYREG_PRT3_DM0
+#define SD_MOSI__DM1 CYREG_PRT3_DM1
+#define SD_MOSI__DM2 CYREG_PRT3_DM2
+#define SD_MOSI__DR CYREG_PRT3_DR
+#define SD_MOSI__INP_DIS CYREG_PRT3_INP_DIS
+#define SD_MOSI__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU3_BASE
+#define SD_MOSI__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG
+#define SD_MOSI__LCD_EN CYREG_PRT3_LCD_EN
+#define SD_MOSI__MASK 0x10u
+#define SD_MOSI__PORT 3u
+#define SD_MOSI__PRT CYREG_PRT3_PRT
+#define SD_MOSI__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL
+#define SD_MOSI__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN
+#define SD_MOSI__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0
+#define SD_MOSI__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1
+#define SD_MOSI__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0
+#define SD_MOSI__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1
+#define SD_MOSI__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT
+#define SD_MOSI__PS CYREG_PRT3_PS
+#define SD_MOSI__SHIFT 4u
+#define SD_MOSI__SLW CYREG_PRT3_SLW
+
+/* SD_RX_DMA */
+#define SD_RX_DMA__DRQ_CTL CYREG_IDMUX_DRQ_CTL0
+#define SD_RX_DMA__DRQ_NUMBER 2u
+#define SD_RX_DMA__NUMBEROF_TDS 0u
+#define SD_RX_DMA__PRIORITY 0u
+#define SD_RX_DMA__TERMIN_EN 0u
+#define SD_RX_DMA__TERMIN_SEL 0u
+#define SD_RX_DMA__TERMOUT0_EN 1u
+#define SD_RX_DMA__TERMOUT0_SEL 2u
+#define SD_RX_DMA__TERMOUT1_EN 0u
+#define SD_RX_DMA__TERMOUT1_SEL 0u
+#define SD_RX_DMA_COMPLETE__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
+#define SD_RX_DMA_COMPLETE__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
+#define SD_RX_DMA_COMPLETE__INTC_MASK 0x20u
+#define SD_RX_DMA_COMPLETE__INTC_NUMBER 5u
+#define SD_RX_DMA_COMPLETE__INTC_PRIOR_NUM 7u
+#define SD_RX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_5
+#define SD_RX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0
+#define SD_RX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
+
+/* SD_SCK */
+#define SD_SCK__0__INTTYPE CYREG_PICU3_INTTYPE3
+#define SD_SCK__0__MASK 0x08u
+#define SD_SCK__0__PC CYREG_PRT3_PC3
+#define SD_SCK__0__PORT 3u
+#define SD_SCK__0__SHIFT 3u
+#define SD_SCK__AG CYREG_PRT3_AG
+#define SD_SCK__AMUX CYREG_PRT3_AMUX
+#define SD_SCK__BIE CYREG_PRT3_BIE
+#define SD_SCK__BIT_MASK CYREG_PRT3_BIT_MASK
+#define SD_SCK__BYP CYREG_PRT3_BYP
+#define SD_SCK__CTL CYREG_PRT3_CTL
+#define SD_SCK__DM0 CYREG_PRT3_DM0
+#define SD_SCK__DM1 CYREG_PRT3_DM1
+#define SD_SCK__DM2 CYREG_PRT3_DM2
+#define SD_SCK__DR CYREG_PRT3_DR
+#define SD_SCK__INP_DIS CYREG_PRT3_INP_DIS
+#define SD_SCK__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU3_BASE
+#define SD_SCK__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG
+#define SD_SCK__LCD_EN CYREG_PRT3_LCD_EN
+#define SD_SCK__MASK 0x08u
+#define SD_SCK__PORT 3u
+#define SD_SCK__PRT CYREG_PRT3_PRT
+#define SD_SCK__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL
+#define SD_SCK__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN
+#define SD_SCK__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0
+#define SD_SCK__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1
+#define SD_SCK__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0
+#define SD_SCK__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1
+#define SD_SCK__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT
+#define SD_SCK__PS CYREG_PRT3_PS
+#define SD_SCK__SHIFT 3u
+#define SD_SCK__SLW CYREG_PRT3_SLW
+
+/* SD_TX_DMA */
+#define SD_TX_DMA__DRQ_CTL CYREG_IDMUX_DRQ_CTL0
+#define SD_TX_DMA__DRQ_NUMBER 3u
+#define SD_TX_DMA__NUMBEROF_TDS 0u
+#define SD_TX_DMA__PRIORITY 1u
+#define SD_TX_DMA__TERMIN_EN 0u
+#define SD_TX_DMA__TERMIN_SEL 0u
+#define SD_TX_DMA__TERMOUT0_EN 1u
+#define SD_TX_DMA__TERMOUT0_SEL 3u
+#define SD_TX_DMA__TERMOUT1_EN 0u
+#define SD_TX_DMA__TERMOUT1_SEL 0u
+#define SD_TX_DMA_COMPLETE__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
+#define SD_TX_DMA_COMPLETE__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
+#define SD_TX_DMA_COMPLETE__INTC_MASK 0x40u
+#define SD_TX_DMA_COMPLETE__INTC_NUMBER 6u
+#define SD_TX_DMA_COMPLETE__INTC_PRIOR_NUM 7u
+#define SD_TX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_6
+#define SD_TX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0
+#define SD_TX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
+
+/* TERM_EN */
+#define TERM_EN__0__INTTYPE CYREG_PICU15_INTTYPE3
+#define TERM_EN__0__MASK 0x08u
+#define TERM_EN__0__PC CYREG_IO_PC_PRT15_PC3
+#define TERM_EN__0__PORT 15u
+#define TERM_EN__0__SHIFT 3u
+#define TERM_EN__AG CYREG_PRT15_AG
+#define TERM_EN__AMUX CYREG_PRT15_AMUX
+#define TERM_EN__BIE CYREG_PRT15_BIE
+#define TERM_EN__BIT_MASK CYREG_PRT15_BIT_MASK
+#define TERM_EN__BYP CYREG_PRT15_BYP
+#define TERM_EN__CTL CYREG_PRT15_CTL
+#define TERM_EN__DM0 CYREG_PRT15_DM0
+#define TERM_EN__DM1 CYREG_PRT15_DM1
+#define TERM_EN__DM2 CYREG_PRT15_DM2
+#define TERM_EN__DR CYREG_PRT15_DR
+#define TERM_EN__INP_DIS CYREG_PRT15_INP_DIS
+#define TERM_EN__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU15_BASE
+#define TERM_EN__LCD_COM_SEG CYREG_PRT15_LCD_COM_SEG
+#define TERM_EN__LCD_EN CYREG_PRT15_LCD_EN
+#define TERM_EN__MASK 0x08u
+#define TERM_EN__PORT 15u
+#define TERM_EN__PRT CYREG_PRT15_PRT
+#define TERM_EN__PRTDSI__CAPS_SEL CYREG_PRT15_CAPS_SEL
+#define TERM_EN__PRTDSI__DBL_SYNC_IN CYREG_PRT15_DBL_SYNC_IN
+#define TERM_EN__PRTDSI__OE_SEL0 CYREG_PRT15_OE_SEL0
+#define TERM_EN__PRTDSI__OE_SEL1 CYREG_PRT15_OE_SEL1
+#define TERM_EN__PRTDSI__OUT_SEL0 CYREG_PRT15_OUT_SEL0
+#define TERM_EN__PRTDSI__OUT_SEL1 CYREG_PRT15_OUT_SEL1
+#define TERM_EN__PRTDSI__SYNC_OUT CYREG_PRT15_SYNC_OUT
+#define TERM_EN__PS CYREG_PRT15_PS
+#define TERM_EN__SHIFT 3u
+#define TERM_EN__SLW CYREG_PRT15_SLW
+
+/* USBFS */
+#define USBFS_arb_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
+#define USBFS_arb_int__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
+#define USBFS_arb_int__INTC_MASK 0x400000u
+#define USBFS_arb_int__INTC_NUMBER 22u
+#define USBFS_arb_int__INTC_PRIOR_NUM 6u
+#define USBFS_arb_int__INTC_PRIOR_REG CYREG_NVIC_PRI_22
+#define USBFS_arb_int__INTC_SET_EN_REG CYREG_NVIC_SETENA0
+#define USBFS_arb_int__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
+#define USBFS_bus_reset__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
+#define USBFS_bus_reset__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
+#define USBFS_bus_reset__INTC_MASK 0x800000u
+#define USBFS_bus_reset__INTC_NUMBER 23u
+#define USBFS_bus_reset__INTC_PRIOR_NUM 7u
+#define USBFS_bus_reset__INTC_PRIOR_REG CYREG_NVIC_PRI_23
+#define USBFS_bus_reset__INTC_SET_EN_REG CYREG_NVIC_SETENA0
+#define USBFS_bus_reset__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
+#define USBFS_Dm__0__INTTYPE CYREG_PICU15_INTTYPE7
+#define USBFS_Dm__0__MASK 0x80u
+#define USBFS_Dm__0__PC CYREG_IO_PC_PRT15_7_6_PC1
+#define USBFS_Dm__0__PORT 15u
+#define USBFS_Dm__0__SHIFT 7u
+#define USBFS_Dm__AG CYREG_PRT15_AG
+#define USBFS_Dm__AMUX CYREG_PRT15_AMUX
+#define USBFS_Dm__BIE CYREG_PRT15_BIE
+#define USBFS_Dm__BIT_MASK CYREG_PRT15_BIT_MASK
+#define USBFS_Dm__BYP CYREG_PRT15_BYP
+#define USBFS_Dm__CTL CYREG_PRT15_CTL
+#define USBFS_Dm__DM0 CYREG_PRT15_DM0
+#define USBFS_Dm__DM1 CYREG_PRT15_DM1
+#define USBFS_Dm__DM2 CYREG_PRT15_DM2
+#define USBFS_Dm__DR CYREG_PRT15_DR
+#define USBFS_Dm__INP_DIS CYREG_PRT15_INP_DIS
+#define USBFS_Dm__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU15_BASE
+#define USBFS_Dm__LCD_COM_SEG CYREG_PRT15_LCD_COM_SEG
+#define USBFS_Dm__LCD_EN CYREG_PRT15_LCD_EN
+#define USBFS_Dm__MASK 0x80u
+#define USBFS_Dm__PORT 15u
+#define USBFS_Dm__PRT CYREG_PRT15_PRT
+#define USBFS_Dm__PRTDSI__CAPS_SEL CYREG_PRT15_CAPS_SEL
+#define USBFS_Dm__PRTDSI__DBL_SYNC_IN CYREG_PRT15_DBL_SYNC_IN
+#define USBFS_Dm__PRTDSI__OE_SEL0 CYREG_PRT15_OE_SEL0
+#define USBFS_Dm__PRTDSI__OE_SEL1 CYREG_PRT15_OE_SEL1
+#define USBFS_Dm__PRTDSI__OUT_SEL0 CYREG_PRT15_OUT_SEL0
+#define USBFS_Dm__PRTDSI__OUT_SEL1 CYREG_PRT15_OUT_SEL1
+#define USBFS_Dm__PRTDSI__SYNC_OUT CYREG_PRT15_SYNC_OUT
+#define USBFS_Dm__PS CYREG_PRT15_PS
+#define USBFS_Dm__SHIFT 7u
+#define USBFS_Dm__SLW CYREG_PRT15_SLW
+#define USBFS_Dp__0__INTTYPE CYREG_PICU15_INTTYPE6
+#define USBFS_Dp__0__MASK 0x40u
+#define USBFS_Dp__0__PC CYREG_IO_PC_PRT15_7_6_PC0
+#define USBFS_Dp__0__PORT 15u
+#define USBFS_Dp__0__SHIFT 6u
+#define USBFS_Dp__AG CYREG_PRT15_AG
+#define USBFS_Dp__AMUX CYREG_PRT15_AMUX
+#define USBFS_Dp__BIE CYREG_PRT15_BIE
+#define USBFS_Dp__BIT_MASK CYREG_PRT15_BIT_MASK
+#define USBFS_Dp__BYP CYREG_PRT15_BYP
+#define USBFS_Dp__CTL CYREG_PRT15_CTL
+#define USBFS_Dp__DM0 CYREG_PRT15_DM0
+#define USBFS_Dp__DM1 CYREG_PRT15_DM1
+#define USBFS_Dp__DM2 CYREG_PRT15_DM2
+#define USBFS_Dp__DR CYREG_PRT15_DR
+#define USBFS_Dp__INP_DIS CYREG_PRT15_INP_DIS
+#define USBFS_Dp__INTSTAT CYREG_PICU15_INTSTAT
+#define USBFS_Dp__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU15_BASE
+#define USBFS_Dp__LCD_COM_SEG CYREG_PRT15_LCD_COM_SEG
+#define USBFS_Dp__LCD_EN CYREG_PRT15_LCD_EN
+#define USBFS_Dp__MASK 0x40u
+#define USBFS_Dp__PORT 15u
+#define USBFS_Dp__PRT CYREG_PRT15_PRT
+#define USBFS_Dp__PRTDSI__CAPS_SEL CYREG_PRT15_CAPS_SEL
+#define USBFS_Dp__PRTDSI__DBL_SYNC_IN CYREG_PRT15_DBL_SYNC_IN
+#define USBFS_Dp__PRTDSI__OE_SEL0 CYREG_PRT15_OE_SEL0
+#define USBFS_Dp__PRTDSI__OE_SEL1 CYREG_PRT15_OE_SEL1
+#define USBFS_Dp__PRTDSI__OUT_SEL0 CYREG_PRT15_OUT_SEL0
+#define USBFS_Dp__PRTDSI__OUT_SEL1 CYREG_PRT15_OUT_SEL1
+#define USBFS_Dp__PRTDSI__SYNC_OUT CYREG_PRT15_SYNC_OUT
+#define USBFS_Dp__PS CYREG_PRT15_PS
+#define USBFS_Dp__SHIFT 6u
+#define USBFS_Dp__SLW CYREG_PRT15_SLW
+#define USBFS_Dp__SNAP CYREG_PICU_15_SNAP_15
+#define USBFS_dp_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
+#define USBFS_dp_int__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
+#define USBFS_dp_int__INTC_MASK 0x1000u
+#define USBFS_dp_int__INTC_NUMBER 12u
+#define USBFS_dp_int__INTC_PRIOR_NUM 7u
+#define USBFS_dp_int__INTC_PRIOR_REG CYREG_NVIC_PRI_12
+#define USBFS_dp_int__INTC_SET_EN_REG CYREG_NVIC_SETENA0
+#define USBFS_dp_int__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
+#define USBFS_ep_0__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
+#define USBFS_ep_0__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
+#define USBFS_ep_0__INTC_MASK 0x1000000u
+#define USBFS_ep_0__INTC_NUMBER 24u
+#define USBFS_ep_0__INTC_PRIOR_NUM 7u
+#define USBFS_ep_0__INTC_PRIOR_REG CYREG_NVIC_PRI_24
+#define USBFS_ep_0__INTC_SET_EN_REG CYREG_NVIC_SETENA0
+#define USBFS_ep_0__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
+#define USBFS_ep_1__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
+#define USBFS_ep_1__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
+#define USBFS_ep_1__INTC_MASK 0x80u
+#define USBFS_ep_1__INTC_NUMBER 7u
+#define USBFS_ep_1__INTC_PRIOR_NUM 7u
+#define USBFS_ep_1__INTC_PRIOR_REG CYREG_NVIC_PRI_7
+#define USBFS_ep_1__INTC_SET_EN_REG CYREG_NVIC_SETENA0
+#define USBFS_ep_1__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
+#define USBFS_ep_2__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
+#define USBFS_ep_2__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
+#define USBFS_ep_2__INTC_MASK 0x100u
+#define USBFS_ep_2__INTC_NUMBER 8u
+#define USBFS_ep_2__INTC_PRIOR_NUM 7u
+#define USBFS_ep_2__INTC_PRIOR_REG CYREG_NVIC_PRI_8
+#define USBFS_ep_2__INTC_SET_EN_REG CYREG_NVIC_SETENA0
+#define USBFS_ep_2__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
+#define USBFS_ep_3__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
+#define USBFS_ep_3__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
+#define USBFS_ep_3__INTC_MASK 0x200u
+#define USBFS_ep_3__INTC_NUMBER 9u
+#define USBFS_ep_3__INTC_PRIOR_NUM 7u
+#define USBFS_ep_3__INTC_PRIOR_REG CYREG_NVIC_PRI_9
+#define USBFS_ep_3__INTC_SET_EN_REG CYREG_NVIC_SETENA0
+#define USBFS_ep_3__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
+#define USBFS_ep_4__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
+#define USBFS_ep_4__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
+#define USBFS_ep_4__INTC_MASK 0x400u
+#define USBFS_ep_4__INTC_NUMBER 10u
+#define USBFS_ep_4__INTC_PRIOR_NUM 7u
+#define USBFS_ep_4__INTC_PRIOR_REG CYREG_NVIC_PRI_10
+#define USBFS_ep_4__INTC_SET_EN_REG CYREG_NVIC_SETENA0
+#define USBFS_ep_4__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
+#define USBFS_sof_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
+#define USBFS_sof_int__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
+#define USBFS_sof_int__INTC_MASK 0x200000u
+#define USBFS_sof_int__INTC_NUMBER 21u
+#define USBFS_sof_int__INTC_PRIOR_NUM 7u
+#define USBFS_sof_int__INTC_PRIOR_REG CYREG_NVIC_PRI_21
+#define USBFS_sof_int__INTC_SET_EN_REG CYREG_NVIC_SETENA0
+#define USBFS_sof_int__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
+#define USBFS_USB__ARB_CFG CYREG_USB_ARB_CFG
+#define USBFS_USB__ARB_EP1_CFG CYREG_USB_ARB_EP1_CFG
+#define USBFS_USB__ARB_EP1_INT_EN CYREG_USB_ARB_EP1_INT_EN
+#define USBFS_USB__ARB_EP1_SR CYREG_USB_ARB_EP1_SR
+#define USBFS_USB__ARB_EP2_CFG CYREG_USB_ARB_EP2_CFG
+#define USBFS_USB__ARB_EP2_INT_EN CYREG_USB_ARB_EP2_INT_EN
+#define USBFS_USB__ARB_EP2_SR CYREG_USB_ARB_EP2_SR
+#define USBFS_USB__ARB_EP3_CFG CYREG_USB_ARB_EP3_CFG
+#define USBFS_USB__ARB_EP3_INT_EN CYREG_USB_ARB_EP3_INT_EN
+#define USBFS_USB__ARB_EP3_SR CYREG_USB_ARB_EP3_SR
+#define USBFS_USB__ARB_EP4_CFG CYREG_USB_ARB_EP4_CFG
+#define USBFS_USB__ARB_EP4_INT_EN CYREG_USB_ARB_EP4_INT_EN
+#define USBFS_USB__ARB_EP4_SR CYREG_USB_ARB_EP4_SR
+#define USBFS_USB__ARB_EP5_CFG CYREG_USB_ARB_EP5_CFG
+#define USBFS_USB__ARB_EP5_INT_EN CYREG_USB_ARB_EP5_INT_EN
+#define USBFS_USB__ARB_EP5_SR CYREG_USB_ARB_EP5_SR
+#define USBFS_USB__ARB_EP6_CFG CYREG_USB_ARB_EP6_CFG
+#define USBFS_USB__ARB_EP6_INT_EN CYREG_USB_ARB_EP6_INT_EN
+#define USBFS_USB__ARB_EP6_SR CYREG_USB_ARB_EP6_SR
+#define USBFS_USB__ARB_EP7_CFG CYREG_USB_ARB_EP7_CFG
+#define USBFS_USB__ARB_EP7_INT_EN CYREG_USB_ARB_EP7_INT_EN
+#define USBFS_USB__ARB_EP7_SR CYREG_USB_ARB_EP7_SR
+#define USBFS_USB__ARB_EP8_CFG CYREG_USB_ARB_EP8_CFG
+#define USBFS_USB__ARB_EP8_INT_EN CYREG_USB_ARB_EP8_INT_EN
+#define USBFS_USB__ARB_EP8_SR CYREG_USB_ARB_EP8_SR
+#define USBFS_USB__ARB_INT_EN CYREG_USB_ARB_INT_EN
+#define USBFS_USB__ARB_INT_SR CYREG_USB_ARB_INT_SR
+#define USBFS_USB__ARB_RW1_DR CYREG_USB_ARB_RW1_DR
+#define USBFS_USB__ARB_RW1_RA CYREG_USB_ARB_RW1_RA
+#define USBFS_USB__ARB_RW1_RA_MSB CYREG_USB_ARB_RW1_RA_MSB
+#define USBFS_USB__ARB_RW1_WA CYREG_USB_ARB_RW1_WA
+#define USBFS_USB__ARB_RW1_WA_MSB CYREG_USB_ARB_RW1_WA_MSB
+#define USBFS_USB__ARB_RW2_DR CYREG_USB_ARB_RW2_DR
+#define USBFS_USB__ARB_RW2_RA CYREG_USB_ARB_RW2_RA
+#define USBFS_USB__ARB_RW2_RA_MSB CYREG_USB_ARB_RW2_RA_MSB
+#define USBFS_USB__ARB_RW2_WA CYREG_USB_ARB_RW2_WA
+#define USBFS_USB__ARB_RW2_WA_MSB CYREG_USB_ARB_RW2_WA_MSB
+#define USBFS_USB__ARB_RW3_DR CYREG_USB_ARB_RW3_DR
+#define USBFS_USB__ARB_RW3_RA CYREG_USB_ARB_RW3_RA
+#define USBFS_USB__ARB_RW3_RA_MSB CYREG_USB_ARB_RW3_RA_MSB
+#define USBFS_USB__ARB_RW3_WA CYREG_USB_ARB_RW3_WA
+#define USBFS_USB__ARB_RW3_WA_MSB CYREG_USB_ARB_RW3_WA_MSB
+#define USBFS_USB__ARB_RW4_DR CYREG_USB_ARB_RW4_DR
+#define USBFS_USB__ARB_RW4_RA CYREG_USB_ARB_RW4_RA
+#define USBFS_USB__ARB_RW4_RA_MSB CYREG_USB_ARB_RW4_RA_MSB
+#define USBFS_USB__ARB_RW4_WA CYREG_USB_ARB_RW4_WA
+#define USBFS_USB__ARB_RW4_WA_MSB CYREG_USB_ARB_RW4_WA_MSB
+#define USBFS_USB__ARB_RW5_DR CYREG_USB_ARB_RW5_DR
+#define USBFS_USB__ARB_RW5_RA CYREG_USB_ARB_RW5_RA
+#define USBFS_USB__ARB_RW5_RA_MSB CYREG_USB_ARB_RW5_RA_MSB
+#define USBFS_USB__ARB_RW5_WA CYREG_USB_ARB_RW5_WA
+#define USBFS_USB__ARB_RW5_WA_MSB CYREG_USB_ARB_RW5_WA_MSB
+#define USBFS_USB__ARB_RW6_DR CYREG_USB_ARB_RW6_DR
+#define USBFS_USB__ARB_RW6_RA CYREG_USB_ARB_RW6_RA
+#define USBFS_USB__ARB_RW6_RA_MSB CYREG_USB_ARB_RW6_RA_MSB
+#define USBFS_USB__ARB_RW6_WA CYREG_USB_ARB_RW6_WA
+#define USBFS_USB__ARB_RW6_WA_MSB CYREG_USB_ARB_RW6_WA_MSB
+#define USBFS_USB__ARB_RW7_DR CYREG_USB_ARB_RW7_DR
+#define USBFS_USB__ARB_RW7_RA CYREG_USB_ARB_RW7_RA
+#define USBFS_USB__ARB_RW7_RA_MSB CYREG_USB_ARB_RW7_RA_MSB
+#define USBFS_USB__ARB_RW7_WA CYREG_USB_ARB_RW7_WA
+#define USBFS_USB__ARB_RW7_WA_MSB CYREG_USB_ARB_RW7_WA_MSB
+#define USBFS_USB__ARB_RW8_DR CYREG_USB_ARB_RW8_DR
+#define USBFS_USB__ARB_RW8_RA CYREG_USB_ARB_RW8_RA
+#define USBFS_USB__ARB_RW8_RA_MSB CYREG_USB_ARB_RW8_RA_MSB
+#define USBFS_USB__ARB_RW8_WA CYREG_USB_ARB_RW8_WA
+#define USBFS_USB__ARB_RW8_WA_MSB CYREG_USB_ARB_RW8_WA_MSB
+#define USBFS_USB__BUF_SIZE CYREG_USB_BUF_SIZE
+#define USBFS_USB__BUS_RST_CNT CYREG_USB_BUS_RST_CNT
+#define USBFS_USB__CR0 CYREG_USB_CR0
+#define USBFS_USB__CR1 CYREG_USB_CR1
+#define USBFS_USB__CWA CYREG_USB_CWA
+#define USBFS_USB__CWA_MSB CYREG_USB_CWA_MSB
+#define USBFS_USB__DMA_THRES CYREG_USB_DMA_THRES
+#define USBFS_USB__DMA_THRES_MSB CYREG_USB_DMA_THRES_MSB
+#define USBFS_USB__DYN_RECONFIG CYREG_USB_DYN_RECONFIG
+#define USBFS_USB__EP_ACTIVE CYREG_USB_EP_ACTIVE
+#define USBFS_USB__EP_TYPE CYREG_USB_EP_TYPE
+#define USBFS_USB__EP0_CNT CYREG_USB_EP0_CNT
+#define USBFS_USB__EP0_CR CYREG_USB_EP0_CR
+#define USBFS_USB__EP0_DR0 CYREG_USB_EP0_DR0
+#define USBFS_USB__EP0_DR1 CYREG_USB_EP0_DR1
+#define USBFS_USB__EP0_DR2 CYREG_USB_EP0_DR2
+#define USBFS_USB__EP0_DR3 CYREG_USB_EP0_DR3
+#define USBFS_USB__EP0_DR4 CYREG_USB_EP0_DR4
+#define USBFS_USB__EP0_DR5 CYREG_USB_EP0_DR5
+#define USBFS_USB__EP0_DR6 CYREG_USB_EP0_DR6
+#define USBFS_USB__EP0_DR7 CYREG_USB_EP0_DR7
+#define USBFS_USB__MEM_DATA CYREG_USB_MEM_DATA_MBASE
+#define USBFS_USB__PM_ACT_CFG CYREG_PM_ACT_CFG5
+#define USBFS_USB__PM_ACT_MSK 0x01u
+#define USBFS_USB__PM_STBY_CFG CYREG_PM_STBY_CFG5
+#define USBFS_USB__PM_STBY_MSK 0x01u
+#define USBFS_USB__SIE_EP_INT_EN CYREG_USB_SIE_EP_INT_EN
+#define USBFS_USB__SIE_EP_INT_SR CYREG_USB_SIE_EP_INT_SR
+#define USBFS_USB__SIE_EP1_CNT0 CYREG_USB_SIE_EP1_CNT0
+#define USBFS_USB__SIE_EP1_CNT1 CYREG_USB_SIE_EP1_CNT1
+#define USBFS_USB__SIE_EP1_CR0 CYREG_USB_SIE_EP1_CR0
+#define USBFS_USB__SIE_EP2_CNT0 CYREG_USB_SIE_EP2_CNT0
+#define USBFS_USB__SIE_EP2_CNT1 CYREG_USB_SIE_EP2_CNT1
+#define USBFS_USB__SIE_EP2_CR0 CYREG_USB_SIE_EP2_CR0
+#define USBFS_USB__SIE_EP3_CNT0 CYREG_USB_SIE_EP3_CNT0
+#define USBFS_USB__SIE_EP3_CNT1 CYREG_USB_SIE_EP3_CNT1
+#define USBFS_USB__SIE_EP3_CR0 CYREG_USB_SIE_EP3_CR0
+#define USBFS_USB__SIE_EP4_CNT0 CYREG_USB_SIE_EP4_CNT0
+#define USBFS_USB__SIE_EP4_CNT1 CYREG_USB_SIE_EP4_CNT1
+#define USBFS_USB__SIE_EP4_CR0 CYREG_USB_SIE_EP4_CR0
+#define USBFS_USB__SIE_EP5_CNT0 CYREG_USB_SIE_EP5_CNT0
+#define USBFS_USB__SIE_EP5_CNT1 CYREG_USB_SIE_EP5_CNT1
+#define USBFS_USB__SIE_EP5_CR0 CYREG_USB_SIE_EP5_CR0
+#define USBFS_USB__SIE_EP6_CNT0 CYREG_USB_SIE_EP6_CNT0
+#define USBFS_USB__SIE_EP6_CNT1 CYREG_USB_SIE_EP6_CNT1
+#define USBFS_USB__SIE_EP6_CR0 CYREG_USB_SIE_EP6_CR0
+#define USBFS_USB__SIE_EP7_CNT0 CYREG_USB_SIE_EP7_CNT0
+#define USBFS_USB__SIE_EP7_CNT1 CYREG_USB_SIE_EP7_CNT1
+#define USBFS_USB__SIE_EP7_CR0 CYREG_USB_SIE_EP7_CR0
+#define USBFS_USB__SIE_EP8_CNT0 CYREG_USB_SIE_EP8_CNT0
+#define USBFS_USB__SIE_EP8_CNT1 CYREG_USB_SIE_EP8_CNT1
+#define USBFS_USB__SIE_EP8_CR0 CYREG_USB_SIE_EP8_CR0
+#define USBFS_USB__SOF0 CYREG_USB_SOF0
+#define USBFS_USB__SOF1 CYREG_USB_SOF1
+#define USBFS_USB__USB_CLK_EN CYREG_USB_USB_CLK_EN
+#define USBFS_USB__USBIO_CR0 CYREG_USB_USBIO_CR0
+#define USBFS_USB__USBIO_CR1 CYREG_USB_USBIO_CR1
+
 /* scsiTarget */
 #define scsiTarget_datapath__16BIT_A0_REG CYREG_B0_UDB00_01_A0
 #define scsiTarget_datapath__16BIT_A1_REG CYREG_B0_UDB00_01_A1
@@ -2415,89 +2580,6 @@
 #define scsiTarget_StatusReg__STATUS_AUX_CTL_REG CYREG_B0_UDB15_ACTL
 #define scsiTarget_StatusReg__STATUS_REG CYREG_B0_UDB15_ST
 
-/* Debug_Timer_Interrupt */
-#define Debug_Timer_Interrupt__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
-#define Debug_Timer_Interrupt__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
-#define Debug_Timer_Interrupt__INTC_MASK 0x02u
-#define Debug_Timer_Interrupt__INTC_NUMBER 1u
-#define Debug_Timer_Interrupt__INTC_PRIOR_NUM 7u
-#define Debug_Timer_Interrupt__INTC_PRIOR_REG CYREG_NVIC_PRI_1
-#define Debug_Timer_Interrupt__INTC_SET_EN_REG CYREG_NVIC_SETENA0
-#define Debug_Timer_Interrupt__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
-
-/* Debug_Timer_TimerHW */
-#define Debug_Timer_TimerHW__CAP0 CYREG_TMR0_CAP0
-#define Debug_Timer_TimerHW__CAP1 CYREG_TMR0_CAP1
-#define Debug_Timer_TimerHW__CFG0 CYREG_TMR0_CFG0
-#define Debug_Timer_TimerHW__CFG1 CYREG_TMR0_CFG1
-#define Debug_Timer_TimerHW__CFG2 CYREG_TMR0_CFG2
-#define Debug_Timer_TimerHW__CNT_CMP0 CYREG_TMR0_CNT_CMP0
-#define Debug_Timer_TimerHW__CNT_CMP1 CYREG_TMR0_CNT_CMP1
-#define Debug_Timer_TimerHW__PER0 CYREG_TMR0_PER0
-#define Debug_Timer_TimerHW__PER1 CYREG_TMR0_PER1
-#define Debug_Timer_TimerHW__PM_ACT_CFG CYREG_PM_ACT_CFG3
-#define Debug_Timer_TimerHW__PM_ACT_MSK 0x01u
-#define Debug_Timer_TimerHW__PM_STBY_CFG CYREG_PM_STBY_CFG3
-#define Debug_Timer_TimerHW__PM_STBY_MSK 0x01u
-#define Debug_Timer_TimerHW__RT0 CYREG_TMR0_RT0
-#define Debug_Timer_TimerHW__RT1 CYREG_TMR0_RT1
-#define Debug_Timer_TimerHW__SR0 CYREG_TMR0_SR0
-
-/* SCSI_RX_DMA */
-#define SCSI_RX_DMA__DRQ_CTL CYREG_IDMUX_DRQ_CTL0
-#define SCSI_RX_DMA__DRQ_NUMBER 0u
-#define SCSI_RX_DMA__NUMBEROF_TDS 0u
-#define SCSI_RX_DMA__PRIORITY 2u
-#define SCSI_RX_DMA__TERMIN_EN 0u
-#define SCSI_RX_DMA__TERMIN_SEL 0u
-#define SCSI_RX_DMA__TERMOUT0_EN 1u
-#define SCSI_RX_DMA__TERMOUT0_SEL 0u
-#define SCSI_RX_DMA__TERMOUT1_EN 0u
-#define SCSI_RX_DMA__TERMOUT1_SEL 0u
-
-/* SCSI_RX_DMA_COMPLETE */
-#define SCSI_RX_DMA_COMPLETE__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
-#define SCSI_RX_DMA_COMPLETE__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
-#define SCSI_RX_DMA_COMPLETE__INTC_MASK 0x01u
-#define SCSI_RX_DMA_COMPLETE__INTC_NUMBER 0u
-#define SCSI_RX_DMA_COMPLETE__INTC_PRIOR_NUM 7u
-#define SCSI_RX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_0
-#define SCSI_RX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0
-#define SCSI_RX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
-
-/* SCSI_TX_DMA */
-#define SCSI_TX_DMA__DRQ_CTL CYREG_IDMUX_DRQ_CTL0
-#define SCSI_TX_DMA__DRQ_NUMBER 1u
-#define SCSI_TX_DMA__NUMBEROF_TDS 0u
-#define SCSI_TX_DMA__PRIORITY 2u
-#define SCSI_TX_DMA__TERMIN_EN 0u
-#define SCSI_TX_DMA__TERMIN_SEL 0u
-#define SCSI_TX_DMA__TERMOUT0_EN 1u
-#define SCSI_TX_DMA__TERMOUT0_SEL 1u
-#define SCSI_TX_DMA__TERMOUT1_EN 0u
-#define SCSI_TX_DMA__TERMOUT1_SEL 0u
-
-/* SCSI_TX_DMA_COMPLETE */
-#define SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
-#define SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
-#define SCSI_TX_DMA_COMPLETE__INTC_MASK 0x10u
-#define SCSI_TX_DMA_COMPLETE__INTC_NUMBER 4u
-#define SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM 7u
-#define SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_4
-#define SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0
-#define SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
-
-/* SD_Data_Clk */
-#define SD_Data_Clk__CFG0 CYREG_CLKDIST_DCFG0_CFG0
-#define SD_Data_Clk__CFG1 CYREG_CLKDIST_DCFG0_CFG1
-#define SD_Data_Clk__CFG2 CYREG_CLKDIST_DCFG0_CFG2
-#define SD_Data_Clk__CFG2_SRC_SEL_MASK 0x07u
-#define SD_Data_Clk__INDEX 0x00u
-#define SD_Data_Clk__PM_ACT_CFG CYREG_PM_ACT_CFG2
-#define SD_Data_Clk__PM_ACT_MSK 0x01u
-#define SD_Data_Clk__PM_STBY_CFG CYREG_PM_STBY_CFG2
-#define SD_Data_Clk__PM_STBY_MSK 0x01u
-
 /* timer_clock */
 #define timer_clock__CFG0 CYREG_CLKDIST_DCFG2_CFG0
 #define timer_clock__CFG1 CYREG_CLKDIST_DCFG2_CFG1
@@ -2509,156 +2591,55 @@
 #define timer_clock__PM_STBY_CFG CYREG_PM_STBY_CFG2
 #define timer_clock__PM_STBY_MSK 0x04u
 
-/* SCSI_RST_ISR */
-#define SCSI_RST_ISR__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
-#define SCSI_RST_ISR__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
-#define SCSI_RST_ISR__INTC_MASK 0x04u
-#define SCSI_RST_ISR__INTC_NUMBER 2u
-#define SCSI_RST_ISR__INTC_PRIOR_NUM 7u
-#define SCSI_RST_ISR__INTC_PRIOR_REG CYREG_NVIC_PRI_2
-#define SCSI_RST_ISR__INTC_SET_EN_REG CYREG_NVIC_SETENA0
-#define SCSI_RST_ISR__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
-
-/* SCSI_SEL_ISR */
-#define SCSI_SEL_ISR__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
-#define SCSI_SEL_ISR__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
-#define SCSI_SEL_ISR__INTC_MASK 0x08u
-#define SCSI_SEL_ISR__INTC_NUMBER 3u
-#define SCSI_SEL_ISR__INTC_PRIOR_NUM 7u
-#define SCSI_SEL_ISR__INTC_PRIOR_REG CYREG_NVIC_PRI_3
-#define SCSI_SEL_ISR__INTC_SET_EN_REG CYREG_NVIC_SETENA0
-#define SCSI_SEL_ISR__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
-
-/* SCSI_Filtered */
-#define SCSI_Filtered_sts_sts_reg__0__MASK 0x01u
-#define SCSI_Filtered_sts_sts_reg__0__POS 0
-#define SCSI_Filtered_sts_sts_reg__1__MASK 0x02u
-#define SCSI_Filtered_sts_sts_reg__1__POS 1
-#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB11_12_ACTL
-#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB11_12_ST
-#define SCSI_Filtered_sts_sts_reg__2__MASK 0x04u
-#define SCSI_Filtered_sts_sts_reg__2__POS 2
-#define SCSI_Filtered_sts_sts_reg__3__MASK 0x08u
-#define SCSI_Filtered_sts_sts_reg__3__POS 3
-#define SCSI_Filtered_sts_sts_reg__4__MASK 0x10u
-#define SCSI_Filtered_sts_sts_reg__4__POS 4
-#define SCSI_Filtered_sts_sts_reg__MASK 0x1Fu
-#define SCSI_Filtered_sts_sts_reg__MASK_REG CYREG_B0_UDB11_MSK
-#define SCSI_Filtered_sts_sts_reg__MASK_ST_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL
-#define SCSI_Filtered_sts_sts_reg__PER_ST_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL
-#define SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB11_ACTL
-#define SCSI_Filtered_sts_sts_reg__STATUS_CNT_REG CYREG_B0_UDB11_ST_CTL
-#define SCSI_Filtered_sts_sts_reg__STATUS_CONTROL_REG CYREG_B0_UDB11_ST_CTL
-#define SCSI_Filtered_sts_sts_reg__STATUS_REG CYREG_B0_UDB11_ST
-
-/* SCSI_CTL_PHASE */
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK 0x01u
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS 0
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK 0x02u
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS 1
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB02_03_ACTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB02_03_CTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB02_03_CTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB02_03_CTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB02_03_CTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB02_03_MSK
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB02_03_MSK
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB02_03_MSK
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB02_03_MSK
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK 0x04u
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS 2
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB02_ACTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB02_CTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB02_ST_CTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB02_CTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB02_ST_CTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK 0x07u
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB02_MSK_ACTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB02_MSK_ACTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB02_MSK
-
-/* SCSI_Glitch_Ctl */
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK 0x01u
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS 0
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB05_06_ACTL
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB05_06_CTL
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB05_06_CTL
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB05_06_CTL
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB05_06_CTL
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB05_06_MSK
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB05_06_MSK
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB05_06_MSK
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB05_06_MSK
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB05_ACTL
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB05_CTL
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB05_ST_CTL
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB05_CTL
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB05_ST_CTL
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK 0x01u
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB05_MSK
-
-/* SCSI_Parity_Error */
-#define SCSI_Parity_Error_sts_sts_reg__0__MASK 0x01u
-#define SCSI_Parity_Error_sts_sts_reg__0__POS 0
-#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB02_03_ACTL
-#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB02_03_ST
-#define SCSI_Parity_Error_sts_sts_reg__MASK 0x01u
-#define SCSI_Parity_Error_sts_sts_reg__MASK_REG CYREG_B0_UDB02_MSK
-#define SCSI_Parity_Error_sts_sts_reg__MASK_ST_AUX_CTL_REG CYREG_B0_UDB02_MSK_ACTL
-#define SCSI_Parity_Error_sts_sts_reg__PER_ST_AUX_CTL_REG CYREG_B0_UDB02_MSK_ACTL
-#define SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB02_ACTL
-#define SCSI_Parity_Error_sts_sts_reg__STATUS_CNT_REG CYREG_B0_UDB02_ST_CTL
-#define SCSI_Parity_Error_sts_sts_reg__STATUS_CONTROL_REG CYREG_B0_UDB02_ST_CTL
-#define SCSI_Parity_Error_sts_sts_reg__STATUS_REG CYREG_B0_UDB02_ST
-
 /* Miscellaneous */
 #define BCLK__BUS_CLK__HZ 50000000U
 #define BCLK__BUS_CLK__KHZ 50000U
 #define BCLK__BUS_CLK__MHZ 50U
 #define CY_PROJECT_NAME "SCSI2SD"
-#define CY_VERSION "PSoC Creator  4.0 Update 1"
+#define CY_VERSION "PSoC Creator  4.1"
 #define CYDEV_CHIP_DIE_LEOPARD 1u
-#define CYDEV_CHIP_DIE_PSOC4A 12u
-#define CYDEV_CHIP_DIE_PSOC5LP 19u
-#define CYDEV_CHIP_DIE_PSOC5TM 20u
-#define CYDEV_CHIP_DIE_TMA4 2u
+#define CYDEV_CHIP_DIE_PSOC4A 16u
+#define CYDEV_CHIP_DIE_PSOC5LP 2u
+#define CYDEV_CHIP_DIE_PSOC5TM 3u
+#define CYDEV_CHIP_DIE_TMA4 4u
 #define CYDEV_CHIP_DIE_UNKNOWN 0u
-#define CYDEV_CHIP_FAMILY_FM0P 4u
-#define CYDEV_CHIP_FAMILY_FM3 5u
-#define CYDEV_CHIP_FAMILY_FM4 6u
+#define CYDEV_CHIP_FAMILY_FM0P 5u
+#define CYDEV_CHIP_FAMILY_FM3 6u
+#define CYDEV_CHIP_FAMILY_FM4 7u
 #define CYDEV_CHIP_FAMILY_PSOC3 1u
 #define CYDEV_CHIP_FAMILY_PSOC4 2u
 #define CYDEV_CHIP_FAMILY_PSOC5 3u
+#define CYDEV_CHIP_FAMILY_PSOC6 4u
 #define CYDEV_CHIP_FAMILY_UNKNOWN 0u
 #define CYDEV_CHIP_FAMILY_USED CYDEV_CHIP_FAMILY_PSOC5
 #define CYDEV_CHIP_JTAG_ID 0x2E133069u
 #define CYDEV_CHIP_MEMBER_3A 1u
-#define CYDEV_CHIP_MEMBER_4A 12u
-#define CYDEV_CHIP_MEMBER_4C 18u
-#define CYDEV_CHIP_MEMBER_4D 8u
-#define CYDEV_CHIP_MEMBER_4E 4u
-#define CYDEV_CHIP_MEMBER_4F 13u
-#define CYDEV_CHIP_MEMBER_4G 2u
-#define CYDEV_CHIP_MEMBER_4H 11u
-#define CYDEV_CHIP_MEMBER_4I 17u
-#define CYDEV_CHIP_MEMBER_4J 9u
-#define CYDEV_CHIP_MEMBER_4K 10u
-#define CYDEV_CHIP_MEMBER_4L 16u
-#define CYDEV_CHIP_MEMBER_4M 15u
-#define CYDEV_CHIP_MEMBER_4N 6u
-#define CYDEV_CHIP_MEMBER_4O 5u
-#define CYDEV_CHIP_MEMBER_4P 14u
-#define CYDEV_CHIP_MEMBER_4Q 7u
-#define CYDEV_CHIP_MEMBER_4U 3u
-#define CYDEV_CHIP_MEMBER_5A 20u
-#define CYDEV_CHIP_MEMBER_5B 19u
-#define CYDEV_CHIP_MEMBER_FM3 24u
-#define CYDEV_CHIP_MEMBER_FM4 25u
-#define CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE1 21u
-#define CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE2 22u
-#define CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE3 23u
+#define CYDEV_CHIP_MEMBER_4A 16u
+#define CYDEV_CHIP_MEMBER_4D 12u
+#define CYDEV_CHIP_MEMBER_4E 6u
+#define CYDEV_CHIP_MEMBER_4F 17u
+#define CYDEV_CHIP_MEMBER_4G 4u
+#define CYDEV_CHIP_MEMBER_4H 15u
+#define CYDEV_CHIP_MEMBER_4I 21u
+#define CYDEV_CHIP_MEMBER_4J 13u
+#define CYDEV_CHIP_MEMBER_4K 14u
+#define CYDEV_CHIP_MEMBER_4L 20u
+#define CYDEV_CHIP_MEMBER_4M 19u
+#define CYDEV_CHIP_MEMBER_4N 9u
+#define CYDEV_CHIP_MEMBER_4O 7u
+#define CYDEV_CHIP_MEMBER_4P 18u
+#define CYDEV_CHIP_MEMBER_4Q 11u
+#define CYDEV_CHIP_MEMBER_4R 8u
+#define CYDEV_CHIP_MEMBER_4S 10u
+#define CYDEV_CHIP_MEMBER_4U 5u
+#define CYDEV_CHIP_MEMBER_5A 3u
+#define CYDEV_CHIP_MEMBER_5B 2u
+#define CYDEV_CHIP_MEMBER_6A 22u
+#define CYDEV_CHIP_MEMBER_FM3 26u
+#define CYDEV_CHIP_MEMBER_FM4 27u
+#define CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE1 23u
+#define CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE2 24u
+#define CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE3 25u
 #define CYDEV_CHIP_MEMBER_UNKNOWN 0u
 #define CYDEV_CHIP_MEMBER_USED CYDEV_CHIP_MEMBER_5B
 #define CYDEV_CHIP_DIE_EXPECT CYDEV_CHIP_MEMBER_USED
@@ -2683,7 +2664,6 @@
 #define CYDEV_CHIP_REVISION_3A_PRODUCTION 3u
 #define CYDEV_CHIP_REVISION_4A_ES0 17u
 #define CYDEV_CHIP_REVISION_4A_PRODUCTION 17u
-#define CYDEV_CHIP_REVISION_4C_PRODUCTION 0u
 #define CYDEV_CHIP_REVISION_4D_PRODUCTION 0u
 #define CYDEV_CHIP_REVISION_4E_PRODUCTION 0u
 #define CYDEV_CHIP_REVISION_4F_PRODUCTION 0u
@@ -2702,12 +2682,16 @@
 #define CYDEV_CHIP_REVISION_4O_PRODUCTION 0u
 #define CYDEV_CHIP_REVISION_4P_PRODUCTION 0u
 #define CYDEV_CHIP_REVISION_4Q_PRODUCTION 0u
+#define CYDEV_CHIP_REVISION_4R_PRODUCTION 0u
+#define CYDEV_CHIP_REVISION_4S_PRODUCTION 0u
 #define CYDEV_CHIP_REVISION_4U_PRODUCTION 0u
 #define CYDEV_CHIP_REVISION_5A_ES0 0u
 #define CYDEV_CHIP_REVISION_5A_ES1 1u
 #define CYDEV_CHIP_REVISION_5A_PRODUCTION 1u
 #define CYDEV_CHIP_REVISION_5B_ES0 0u
 #define CYDEV_CHIP_REVISION_5B_PRODUCTION 0u
+#define CYDEV_CHIP_REVISION_6A_NO_UDB 0u
+#define CYDEV_CHIP_REVISION_6A_PRODUCTION 0u
 #define CYDEV_CHIP_REVISION_FM3_PRODUCTION 0u
 #define CYDEV_CHIP_REVISION_FM4_PRODUCTION 0u
 #define CYDEV_CHIP_REVISION_PDL_FM0P_TYPE1_PRODUCTION 0u
@@ -2739,7 +2723,7 @@
 #define CYDEV_ECC_ENABLE 0
 #define CYDEV_HEAP_SIZE 0x0400
 #define CYDEV_INSTRUCT_CACHE_ENABLED 1
-#define CYDEV_INTR_RISING 0x0000007Eu
+#define CYDEV_INTR_RISING 0x0000007Fu
 #define CYDEV_IS_EXPORTING_CODE 0
 #define CYDEV_IS_IMPORTING_CODE 0
 #define CYDEV_PROJ_TYPE 2

diff --git a/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c b/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c
index 43b624442172de67c9faeb49531184a97576a3a5..ebdbdfec1f4ece89a94da3c9388410d9eabfc84f 100755 (executable)
--- a/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c
+++ b/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c
@@ -1,7 +1,8 @@
+
 /*******************************************************************************
 * File Name: cyfitter_cfg.c
 * 
-* PSoC Creator  4.0 Update 1
+* PSoC Creator  4.1
 *
 * Description:
 * This file contains device initialization code.
@@ -9,7 +10,7 @@
 * This file is automatically generated by PSoC Creator.
 *
 ********************************************************************************
-* Copyright (c) 2007-2016 Cypress Semiconductor.  All rights reserved.
+* Copyright (c) 2007-2017 Cypress Semiconductor.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions, 
 * disclaimers, and limitations in the end user license agreement accompanying 
 * the software package with which this file was provided.
@@ -55,6 +56,19 @@
     #error Unsupported toolchain
 #endif
 
+#ifndef CYCODE
+    #define CYCODE
+#endif
+#ifndef CYDATA
+    #define CYDATA
+#endif
+#ifndef CYFAR
+    #define CYFAR
+#endif
+#ifndef CYXDATA
+    #define CYXDATA
+#endif
+
 
 CY_CFG_UNUSED
 static void CYMEMZERO(void *s, size_t n);
@@ -86,6 +100,7 @@ static void CYCONFIGCPYCODE(void *dest, const void *src, size_t n)
 #define CYCLOCKSTART_XTAL_ERROR  1u
 #define CYCLOCKSTART_32KHZ_ERROR 2u
 #define CYCLOCKSTART_PLL_ERROR   3u
+#define CYCLOCKSTART_FLL_ERROR   4u
 
 
 #ifdef CY_NEED_CYCLOCKSTARTUPERROR
@@ -109,17 +124,21 @@ static void CyClockStartupError(uint8 errorCode);
 CY_CFG_UNUSED
 static void CyClockStartupError(uint8 errorCode)
 {
-    /* To remove the compiler warning if errorCode not used.                */
+    /* To remove the compiler warning if errorCode not used. */
+#if defined(CY_PSOC3) && (CY_PSOC3)
     errorCode = errorCode;
+#else
+    (void)errorCode;
+#endif /* CY_PSOC3 */
 
     /* If we have a clock startup error (bad MHz crystal, PLL lock, etc.),  */
     /* we will end up here to allow the customer to implement something to  */
     /* deal with the clock condition.                                       */
 
 #ifdef CY_CFG_CLOCK_STARTUP_ERROR_CALLBACK
-       CY_CFG_Clock_Startup_ErrorCallback();
+    CY_CFG_Clock_Startup_ErrorCallback();
 #else
-       /*  If not using CY_CFG_CLOCK_STARTUP_ERROR_CALLBACK, place your clock startup code here. */
+    /*  If not using CY_CFG_CLOCK_STARTUP_ERROR_CALLBACK, place your clock startup code here. */
     /* `#START CyClockStartupError` */
 
     /* If we have a clock startup error (bad MHz crystal, PLL lock, etc.),  */
@@ -128,10 +147,8 @@ static void CyClockStartupError(uint8 errorCode)
 
     /* `#END` */
 
-    /* If nothing else, stop here since the clocks have not started         */
-    /* correctly.                                                           */
     while(1) {}
-#endif /* CY_CFG_CLOCK_STARTUP_ERROR_CALLBACK */ 
+#endif /* CY_CFG_CLOCK_STARTUP_ERROR_CALLBACK */
 }
 #endif
 
@@ -170,7 +187,7 @@ static void cfg_write_bytes32(const uint32 addr_table[], const cy_cfg_addrvalue_
                baseAddr &= 0xFFFFFF00u;
                while (count != 0u)
                {
-                       CY_SET_XTND_REG8((void CYFAR *)(baseAddr + data_table[j].offset), data_table[j].value);
+                       CY_SET_REG8((void *)(baseAddr + data_table[j].offset), data_table[j].value);
                        j++;
                        count--;
                }
@@ -205,8 +222,8 @@ static void ClockSetup(void)
        CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_DCFG0_CFG0 + 0x2u), 0x58u);
        CY_SET_XTND_REG16((void CYFAR *)(CYREG_CLKDIST_DCFG1_CFG0), 0x0001u);
        CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_DCFG1_CFG0 + 0x2u), 0x18u);
-       CY_SET_XTND_REG16((void CYFAR *)(CYREG_CLKDIST_DCFG2_CFG0), 0x0017u);
-       CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_DCFG2_CFG0 + 0x2u), 0x19u);
+       CY_SET_XTND_REG16((void CYFAR *)(CYREG_CLKDIST_DCFG2_CFG0), 0x0031u);
+       CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_DCFG2_CFG0 + 0x2u), 0x18u);
 
        /* Configure ILO based on settings from Clock DWR */
        CY_SET_XTND_REG8((void CYFAR *)(CYREG_SLOWCLK_ILO_CR0), 0x06u);
@@ -305,7 +322,7 @@ void SetAnalogRoutingPumps(uint8 enabled)
        CY_SET_XTND_REG8((void CYFAR *)CYREG_PUMP_CR0, regValue);
 }
 
-#define CY_AMUX_UNUSED CYREG_BOOST_SR
+
 
 
 /*******************************************************************************
@@ -317,7 +334,7 @@ void SetAnalogRoutingPumps(uint8 enabled)
 *  settings.  This includes settings from the Design Wide Resources (DWR) such
 *  as Clocks and Pins as well as any component configuration that is necessary.
 *
-* Parameters:  
+* Parameters:
 *   void
 *
 * Return:
@@ -394,39 +411,39 @@ void cyfitter_cfg(void)
                static const uint32 CYCODE cy_cfg_addr_table[] = {
                        0x40004501u, /* Base address: 0x40004500 Count: 1 */
                        0x40004F02u, /* Base address: 0x40004F00 Count: 2 */
-                       0x4000520Cu, /* Base address: 0x40005200 Count: 12 */
+                       0x4000520Bu, /* Base address: 0x40005200 Count: 11 */
                        0x40006401u, /* Base address: 0x40006400 Count: 1 */
                        0x40006501u, /* Base address: 0x40006500 Count: 1 */
                        0x40010047u, /* Base address: 0x40010000 Count: 71 */
-                       0x4001013Cu, /* Base address: 0x40010100 Count: 60 */
+                       0x4001013Fu, /* Base address: 0x40010100 Count: 63 */
                        0x4001025Fu, /* Base address: 0x40010200 Count: 95 */
-                       0x40010362u, /* Base address: 0x40010300 Count: 98 */
+                       0x4001035Eu, /* Base address: 0x40010300 Count: 94 */
                        0x4001044Du, /* Base address: 0x40010400 Count: 77 */
-                       0x4001055Eu, /* Base address: 0x40010500 Count: 94 */
+                       0x4001055Au, /* Base address: 0x40010500 Count: 90 */
                        0x40010650u, /* Base address: 0x40010600 Count: 80 */
-                       0x40010761u, /* Base address: 0x40010700 Count: 97 */
+                       0x40010758u, /* Base address: 0x40010700 Count: 88 */
                        0x40010918u, /* Base address: 0x40010900 Count: 24 */
                        0x40010A4Eu, /* Base address: 0x40010A00 Count: 78 */
-                       0x40010B51u, /* Base address: 0x40010B00 Count: 81 */
+                       0x40010B50u, /* Base address: 0x40010B00 Count: 80 */
                        0x40010C50u, /* Base address: 0x40010C00 Count: 80 */
-                       0x40010D53u, /* Base address: 0x40010D00 Count: 83 */
+                       0x40010D57u, /* Base address: 0x40010D00 Count: 87 */
                        0x40010E4Au, /* Base address: 0x40010E00 Count: 74 */
-                       0x40010F3Eu, /* Base address: 0x40010F00 Count: 62 */
+                       0x40010F3Au, /* Base address: 0x40010F00 Count: 58 */
                        0x40011414u, /* Base address: 0x40011400 Count: 20 */
-                       0x40011548u, /* Base address: 0x40011500 Count: 72 */
+                       0x4001154Cu, /* Base address: 0x40011500 Count: 76 */
                        0x4001164Fu, /* Base address: 0x40011600 Count: 79 */
-                       0x40011755u, /* Base address: 0x40011700 Count: 85 */
-                       0x4001190Au, /* Base address: 0x40011900 Count: 10 */
-                       0x40011B04u, /* Base address: 0x40011B00 Count: 4 */
-                       0x4001401Cu, /* Base address: 0x40014000 Count: 28 */
-                       0x4001411Au, /* Base address: 0x40014100 Count: 26 */
+                       0x40011759u, /* Base address: 0x40011700 Count: 89 */
+                       0x4001190Cu, /* Base address: 0x40011900 Count: 12 */
+                       0x40011B02u, /* Base address: 0x40011B00 Count: 2 */
+                       0x40014020u, /* Base address: 0x40014000 Count: 32 */
+                       0x40014119u, /* Base address: 0x40014100 Count: 25 */
                        0x40014217u, /* Base address: 0x40014200 Count: 23 */
-                       0x40014311u, /* Base address: 0x40014300 Count: 17 */
-                       0x40014414u, /* Base address: 0x40014400 Count: 20 */
-                       0x40014518u, /* Base address: 0x40014500 Count: 24 */
+                       0x4001430Du, /* Base address: 0x40014300 Count: 13 */
+                       0x40014413u, /* Base address: 0x40014400 Count: 19 */
+                       0x4001451Au, /* Base address: 0x40014500 Count: 26 */
                        0x40014612u, /* Base address: 0x40014600 Count: 18 */
                        0x4001470Cu, /* Base address: 0x40014700 Count: 12 */
-                       0x40014808u, /* Base address: 0x40014800 Count: 8 */
+                       0x4001480Au, /* Base address: 0x40014800 Count: 10 */
                        0x4001490Eu, /* Base address: 0x40014900 Count: 14 */
                        0x40015004u, /* Base address: 0x40015000 Count: 4 */
                        0x40015104u, /* Base address: 0x40015100 Count: 4 */
@@ -436,10 +453,9 @@ void cyfitter_cfg(void)
                        {0x7Eu, 0x02u},
                        {0x01u, 0x20u},
                        {0x0Au, 0x4Bu},
-                       {0x00u, 0x20u},
-                       {0x01u, 0x02u},
-                       {0x10u, 0x88u},
-                       {0x11u, 0x22u},
+                       {0x01u, 0x22u},
+                       {0x10u, 0x28u},
+                       {0x11u, 0x02u},
                        {0x18u, 0x10u},
                        {0x19u, 0x08u},
                        {0x1Cu, 0x20u},
@@ -450,33 +466,33 @@ void cyfitter_cfg(void)
                        {0x7Cu, 0x40u},
                        {0x20u, 0x01u},
                        {0x84u, 0x0Fu},
-                       {0x01u, 0x0Bu},
-                       {0x03u, 0x34u},
-                       {0x04u, 0x11u},
-                       {0x05u, 0x11u},
-                       {0x06u, 0x02u},
-                       {0x07u, 0x2Cu},
-                       {0x08u, 0x13u},
+                       {0x01u, 0x11u},
+                       {0x03u, 0x2Cu},
+                       {0x05u, 0x0Bu},
+                       {0x07u, 0x34u},
                        {0x09u, 0x06u},
-                       {0x0Au, 0x2Cu},
+                       {0x0Fu, 0x10u},
                        {0x10u, 0x02u},
                        {0x11u, 0x20u},
                        {0x12u, 0x01u},
+                       {0x14u, 0x11u},
+                       {0x16u, 0x02u},
+                       {0x18u, 0x13u},
                        {0x19u, 0x01u},
-                       {0x1Cu, 0x24u},
-                       {0x1Eu, 0x08u},
+                       {0x1Au, 0x2Cu},
+                       {0x1Du, 0x0Au},
+                       {0x1Fu, 0x15u},
                        {0x20u, 0x08u},
                        {0x22u, 0x04u},
                        {0x23u, 0x3Fu},
-                       {0x29u, 0x0Au},
-                       {0x2Bu, 0x15u},
-                       {0x2Fu, 0x10u},
-                       {0x32u, 0x30u},
-                       {0x35u, 0x3Fu},
+                       {0x2Cu, 0x24u},
+                       {0x2Eu, 0x08u},
+                       {0x30u, 0x30u},
                        {0x36u, 0x0Fu},
-                       {0x3Eu, 0x44u},
-                       {0x40u, 0x32u},
-                       {0x41u, 0x04u},
+                       {0x37u, 0x3Fu},
+                       {0x3Eu, 0x41u},
+                       {0x40u, 0x45u},
+                       {0x41u, 0x03u},
                        {0x42u, 0x60u},
                        {0x45u, 0xF2u},
                        {0x46u, 0xCDu},
@@ -500,127 +516,130 @@ void cyfitter_cfg(void)
                        {0x68u, 0x40u},
                        {0x69u, 0x40u},
                        {0x6Eu, 0x08u},
-                       {0x82u, 0xFFu},
-                       {0x88u, 0x0Fu},
-                       {0x8Au, 0xF0u},
+                       {0x80u, 0xFFu},
                        {0x8Cu, 0xFFu},
                        {0x92u, 0xFFu},
                        {0x96u, 0xFFu},
+                       {0x98u, 0x0Fu},
+                       {0x9Au, 0xF0u},
                        {0x9Cu, 0x33u},
                        {0x9Eu, 0xCCu},
                        {0xA0u, 0x55u},
                        {0xA2u, 0xAAu},
                        {0xA4u, 0x69u},
                        {0xA6u, 0x96u},
-                       {0xA8u, 0xFFu},
-                       {0xB2u, 0xFFu},
-                       {0xBAu, 0x08u},
+                       {0xAEu, 0xFFu},
+                       {0xB6u, 0xFFu},
+                       {0xBAu, 0x80u},
                        {0xD6u, 0x08u},
                        {0xD8u, 0x04u},
                        {0xDBu, 0x04u},
                        {0xDCu, 0x01u},
                        {0xDDu, 0x90u},
                        {0xDFu, 0x01u},
-                       {0x00u, 0x20u},
-                       {0x03u, 0x10u},
-                       {0x04u, 0x90u},
-                       {0x05u, 0x01u},
-                       {0x0Bu, 0x82u},
-                       {0x0Du, 0x06u},
-                       {0x0Fu, 0x02u},
+                       {0x07u, 0x82u},
+                       {0x09u, 0x08u},
+                       {0x0Au, 0x04u},
+                       {0x0Bu, 0x80u},
+                       {0x0Du, 0x01u},
+                       {0x0Eu, 0x10u},
+                       {0x0Fu, 0x0Au},
+                       {0x10u, 0x01u},
                        {0x11u, 0x01u},
-                       {0x15u, 0x20u},
-                       {0x16u, 0xA0u},
+                       {0x16u, 0xA1u},
+                       {0x18u, 0x40u},
                        {0x1Au, 0x02u},
-                       {0x1Bu, 0x04u},
-                       {0x1Cu, 0x10u},
-                       {0x1Fu, 0x04u},
-                       {0x21u, 0x10u},
-                       {0x28u, 0x08u},
-                       {0x29u, 0x01u},
-                       {0x2Au, 0x41u},
+                       {0x1Fu, 0x80u},
+                       {0x20u, 0x02u},
+                       {0x22u, 0x40u},
+                       {0x23u, 0x02u},
+                       {0x2Au, 0x01u},
                        {0x2Cu, 0x40u},
                        {0x2Eu, 0x01u},
                        {0x30u, 0x20u},
-                       {0x32u, 0x02u},
+                       {0x32u, 0x42u},
                        {0x38u, 0x20u},
-                       {0x39u, 0x0Au},
-                       {0x40u, 0x08u},
-                       {0x41u, 0x17u},
-                       {0x49u, 0x20u},
+                       {0x39u, 0x02u},
+                       {0x3Au, 0x40u},
+                       {0x3Bu, 0x08u},
+                       {0x41u, 0x01u},
+                       {0x42u, 0x10u},
+                       {0x48u, 0x01u},
+                       {0x49u, 0x28u},
                        {0x4Au, 0xA0u},
                        {0x50u, 0x10u},
                        {0x52u, 0x40u},
                        {0x53u, 0x08u},
-                       {0x59u, 0x42u},
+                       {0x59u, 0x82u},
                        {0x5Au, 0x28u},
                        {0x5Cu, 0xA0u},
                        {0x61u, 0x10u},
                        {0x63u, 0xA1u},
                        {0x66u, 0xA0u},
                        {0x68u, 0x84u},
-                       {0x6Bu, 0x21u},
-                       {0x71u, 0x24u},
+                       {0x69u, 0x80u},
+                       {0x6Bu, 0x20u},
+                       {0x71u, 0x25u},
                        {0x72u, 0x01u},
-                       {0x73u, 0x40u},
+                       {0x80u, 0x40u},
                        {0x81u, 0x04u},
-                       {0x82u, 0xC0u},
+                       {0x82u, 0x40u},
                        {0x85u, 0x20u},
                        {0x87u, 0x08u},
                        {0x8Cu, 0x10u},
-                       {0x8Fu, 0x04u},
-                       {0xC0u, 0xD6u},
-                       {0xC2u, 0xB9u},
-                       {0xC4u, 0x78u},
-                       {0xCAu, 0x0Du},
-                       {0xCCu, 0x05u},
-                       {0xCEu, 0x07u},
-                       {0xD0u, 0x07u},
-                       {0xD2u, 0x04u},
+                       {0x8Fu, 0x84u},
+                       {0xC0u, 0x90u},
+                       {0xC2u, 0xFEu},
+                       {0xC4u, 0xB9u},
+                       {0xCAu, 0x01u},
+                       {0xCCu, 0x0Du},
+                       {0xCEu, 0x0Fu},
+                       {0xD0u, 0x03u},
+                       {0xD2u, 0x0Cu},
                        {0xD6u, 0x3Fu},
                        {0xD8u, 0x3Fu},
                        {0xE0u, 0x18u},
-                       {0xE4u, 0x03u},
-                       {0x00u, 0xF0u},
-                       {0x02u, 0x08u},
+                       {0xE4u, 0x07u},
+                       {0x00u, 0x10u},
+                       {0x02u, 0x20u},
                        {0x04u, 0x40u},
                        {0x05u, 0x03u},
                        {0x06u, 0x80u},
                        {0x07u, 0x0Cu},
                        {0x09u, 0x80u},
                        {0x0Cu, 0x02u},
-                       {0x0Du, 0x06u},
+                       {0x0Du, 0x40u},
                        {0x0Eu, 0xF0u},
-                       {0x0Fu, 0x09u},
-                       {0x10u, 0x05u},
-                       {0x11u, 0x10u},
+                       {0x0Fu, 0x1Fu},
+                       {0x10u, 0x01u},
+                       {0x11u, 0x20u},
                        {0x12u, 0xF8u},
-                       {0x13u, 0x2Fu},
-                       {0x14u, 0x01u},
-                       {0x15u, 0x40u},
+                       {0x13u, 0x4Fu},
+                       {0x14u, 0x05u},
+                       {0x15u, 0x06u},
                        {0x16u, 0xF8u},
-                       {0x17u, 0x1Fu},
-                       {0x19u, 0x20u},
+                       {0x17u, 0x09u},
                        {0x1Au, 0x01u},
-                       {0x1Bu, 0x4Fu},
                        {0x1Cu, 0x10u},
                        {0x1Eu, 0x20u},
                        {0x1Fu, 0x70u},
-                       {0x20u, 0x10u},
-                       {0x22u, 0x20u},
+                       {0x20u, 0xF4u},
+                       {0x21u, 0x05u},
+                       {0x22u, 0x08u},
+                       {0x23u, 0x0Au},
                        {0x24u, 0x40u},
                        {0x25u, 0x0Fu},
                        {0x26u, 0x80u},
-                       {0x28u, 0xF4u},
-                       {0x29u, 0x05u},
-                       {0x2Au, 0x08u},
-                       {0x2Bu, 0x0Au},
-                       {0x30u, 0x0Fu},
+                       {0x29u, 0x10u},
+                       {0x2Bu, 0x2Fu},
+                       {0x2Cu, 0xF0u},
+                       {0x2Eu, 0x08u},
                        {0x31u, 0x7Fu},
+                       {0x32u, 0x0Fu},
                        {0x34u, 0xC0u},
                        {0x35u, 0x80u},
                        {0x36u, 0x30u},
-                       {0x38u, 0x02u},
+                       {0x38u, 0x08u},
                        {0x3Au, 0xA0u},
                        {0x3Fu, 0x10u},
                        {0x54u, 0x01u},
@@ -630,14 +649,13 @@ void cyfitter_cfg(void)
                        {0x5Cu, 0x11u},
                        {0x5Du, 0x10u},
                        {0x5Fu, 0x01u},
+                       {0x80u, 0x3Fu},
                        {0x83u, 0x7Fu},
                        {0x84u, 0x01u},
-                       {0x85u, 0x20u},
+                       {0x85u, 0x01u},
                        {0x86u, 0x02u},
-                       {0x87u, 0x40u},
-                       {0x88u, 0x3Fu},
-                       {0x89u, 0x78u},
-                       {0x8Bu, 0x03u},
+                       {0x87u, 0x6Eu},
+                       {0x8Au, 0x3Fu},
                        {0x8Cu, 0x10u},
                        {0x8Du, 0x02u},
                        {0x8Eu, 0x20u},
@@ -645,11 +663,10 @@ void cyfitter_cfg(void)
                        {0x91u, 0x64u},
                        {0x92u, 0x20u},
                        {0x95u, 0x03u},
-                       {0x96u, 0x3Fu},
                        {0x97u, 0x74u},
-                       {0x99u, 0x80u},
+                       {0x99u, 0x20u},
                        {0x9Au, 0x3Fu},
-                       {0x9Bu, 0x01u},
+                       {0x9Bu, 0x40u},
                        {0x9Cu, 0x04u},
                        {0x9Eu, 0x08u},
                        {0xA0u, 0x3Fu},
@@ -657,139 +674,137 @@ void cyfitter_cfg(void)
                        {0xA3u, 0x40u},
                        {0xA4u, 0x01u},
                        {0xA6u, 0x02u},
+                       {0xA7u, 0x08u},
                        {0xA8u, 0x04u},
+                       {0xA9u, 0x80u},
                        {0xAAu, 0x08u},
-                       {0xABu, 0x08u},
-                       {0xADu, 0x01u},
+                       {0xABu, 0x01u},
+                       {0xADu, 0x78u},
                        {0xAEu, 0x3Fu},
-                       {0xAFu, 0x6Eu},
+                       {0xAFu, 0x03u},
                        {0xB0u, 0x30u},
-                       {0xB1u, 0x80u},
-                       {0xB3u, 0x1Fu},
+                       {0xB1u, 0x1Fu},
                        {0xB4u, 0x03u},
                        {0xB5u, 0x60u},
                        {0xB6u, 0x0Cu},
+                       {0xB7u, 0x80u},
                        {0xBAu, 0xA2u},
                        {0xBBu, 0x20u},
-                       {0xBFu, 0x01u},
+                       {0xBFu, 0x40u},
                        {0xD8u, 0x04u},
                        {0xD9u, 0x04u},
                        {0xDCu, 0x11u},
                        {0xDFu, 0x01u},
-                       {0x01u, 0x10u},
-                       {0x03u, 0x22u},
+                       {0x00u, 0x02u},
+                       {0x03u, 0x2Au},
                        {0x04u, 0x04u},
-                       {0x06u, 0x01u},
-                       {0x07u, 0x80u},
+                       {0x06u, 0x81u},
                        {0x08u, 0x02u},
-                       {0x09u, 0x08u},
-                       {0x0Au, 0x05u},
-                       {0x0Cu, 0x21u},
-                       {0x0Du, 0x0Au},
-                       {0x0Eu, 0x02u},
-                       {0x10u, 0x04u},
+                       {0x0Au, 0x01u},
+                       {0x0Bu, 0x08u},
+                       {0x0Cu, 0x20u},
+                       {0x0Eu, 0x12u},
+                       {0x0Fu, 0x48u},
                        {0x11u, 0x02u},
-                       {0x12u, 0x01u},
+                       {0x12u, 0x09u},
                        {0x13u, 0x08u},
-                       {0x15u, 0x30u},
-                       {0x16u, 0xA0u},
-                       {0x19u, 0x42u},
+                       {0x16u, 0x20u},
+                       {0x17u, 0x82u},
+                       {0x19u, 0x82u},
                        {0x1Au, 0x01u},
                        {0x1Bu, 0x32u},
                        {0x1Cu, 0x04u},
-                       {0x1Du, 0x12u},
-                       {0x1Eu, 0x02u},
-                       {0x20u, 0x80u},
-                       {0x21u, 0x0Cu},
-                       {0x22u, 0x18u},
-                       {0x23u, 0x04u},
+                       {0x1Du, 0x10u},
+                       {0x1Eu, 0x12u},
+                       {0x1Fu, 0x04u},
+                       {0x21u, 0x01u},
+                       {0x22u, 0x90u},
+                       {0x23u, 0x40u},
                        {0x26u, 0x10u},
                        {0x27u, 0x40u},
-                       {0x28u, 0x09u},
+                       {0x29u, 0x48u},
                        {0x2Au, 0x02u},
+                       {0x2Bu, 0x04u},
                        {0x2Cu, 0x20u},
-                       {0x2Fu, 0x04u},
-                       {0x30u, 0x20u},
-                       {0x31u, 0x08u},
-                       {0x32u, 0x02u},
-                       {0x34u, 0x01u},
-                       {0x36u, 0x48u},
-                       {0x37u, 0x60u},
-                       {0x39u, 0x20u},
+                       {0x2Fu, 0x84u},
+                       {0x32u, 0x12u},
+                       {0x33u, 0x08u},
+                       {0x34u, 0x08u},
+                       {0x36u, 0x40u},
+                       {0x37u, 0x42u},
                        {0x3Au, 0x41u},
-                       {0x3Bu, 0x04u},
-                       {0x3Du, 0xA8u},
-                       {0x59u, 0x01u},
-                       {0x5Bu, 0x01u},
+                       {0x3Bu, 0x08u},
+                       {0x3Du, 0x28u},
+                       {0x3Fu, 0x40u},
+                       {0x58u, 0x04u},
+                       {0x5Au, 0x04u},
                        {0x5Eu, 0x82u},
                        {0x5Fu, 0x01u},
-                       {0x60u, 0x08u},
-                       {0x62u, 0x20u},
                        {0x6Cu, 0x22u},
                        {0x6Du, 0x20u},
                        {0x80u, 0x04u},
                        {0x82u, 0x02u},
-                       {0x84u, 0x10u},
-                       {0x85u, 0x90u},
-                       {0x87u, 0x20u},
-                       {0x88u, 0x04u},
-                       {0x89u, 0x40u},
-                       {0x91u, 0x20u},
+                       {0x86u, 0x18u},
+                       {0x88u, 0x08u},
+                       {0x89u, 0x04u},
+                       {0x8Au, 0x08u},
+                       {0x8Bu, 0x48u},
+                       {0x8Eu, 0x10u},
+                       {0x91u, 0x80u},
                        {0x92u, 0x42u},
-                       {0x93u, 0x48u},
-                       {0x94u, 0x80u},
-                       {0x95u, 0x09u},
-                       {0x96u, 0x28u},
-                       {0x97u, 0x83u},
+                       {0x95u, 0x03u},
+                       {0x96u, 0x3Cu},
+                       {0x97u, 0x89u},
                        {0x98u, 0x50u},
+                       {0x99u, 0x09u},
                        {0x9Au, 0xE0u},
-                       {0x9Bu, 0x01u},
-                       {0x9Cu, 0x20u},
-                       {0x9Du, 0x72u},
+                       {0x9Bu, 0x02u},
+                       {0x9Cu, 0x21u},
+                       {0x9Du, 0xB2u},
                        {0x9Eu, 0x01u},
-                       {0x9Fu, 0x10u},
-                       {0xA0u, 0x80u},
+                       {0x9Fu, 0x80u},
+                       {0xA0u, 0x81u},
                        {0xA2u, 0x20u},
-                       {0xA4u, 0x30u},
-                       {0xA5u, 0x02u},
+                       {0xA3u, 0x80u},
+                       {0xA4u, 0x20u},
+                       {0xA5u, 0x08u},
                        {0xA6u, 0x02u},
                        {0xA7u, 0x51u},
                        {0xA8u, 0x80u},
                        {0xABu, 0x20u},
                        {0xACu, 0x04u},
-                       {0xADu, 0x14u},
                        {0xB0u, 0x10u},
                        {0xB2u, 0xC0u},
-                       {0xC0u, 0xB7u},
-                       {0xC2u, 0xFFu},
-                       {0xC4u, 0x7Fu},
-                       {0xCAu, 0x6Du},
-                       {0xCCu, 0xF7u},
-                       {0xCEu, 0x7Fu},
+                       {0xB6u, 0x80u},
+                       {0xC0u, 0xBFu},
+                       {0xC2u, 0xFBu},
+                       {0xC4u, 0xBFu},
+                       {0xCAu, 0xEFu},
+                       {0xCCu, 0xD7u},
+                       {0xCEu, 0x7Bu},
                        {0xD6u, 0x10u},
-                       {0xE0u, 0x02u},
-                       {0xE2u, 0x0Cu},
                        {0xE4u, 0x01u},
-                       {0xE6u, 0x0Cu},
-                       {0xE8u, 0x0Bu},
+                       {0xE6u, 0x26u},
+                       {0xE8u, 0x01u},
+                       {0xEAu, 0x40u},
                        {0xECu, 0x02u},
                        {0xEEu, 0x01u},
+                       {0x02u, 0x20u},
+                       {0x05u, 0x24u},
+                       {0x07u, 0x09u},
                        {0x0Au, 0x10u},
                        {0x0Bu, 0x18u},
-                       {0x0Cu, 0x05u},
-                       {0x0Eu, 0x0Au},
-                       {0x0Fu, 0x20u},
+                       {0x0Fu, 0x04u},
                        {0x10u, 0x04u},
-                       {0x11u, 0x24u},
-                       {0x13u, 0x09u},
                        {0x14u, 0x01u},
-                       {0x17u, 0x24u},
-                       {0x1Au, 0x20u},
                        {0x1Bu, 0x03u},
                        {0x20u, 0x08u},
-                       {0x23u, 0x04u},
-                       {0x29u, 0x24u},
-                       {0x2Bu, 0x12u},
+                       {0x23u, 0x20u},
+                       {0x25u, 0x24u},
+                       {0x27u, 0x12u},
+                       {0x28u, 0x05u},
+                       {0x2Au, 0x0Au},
+                       {0x2Bu, 0x24u},
                        {0x2Cu, 0x02u},
                        {0x30u, 0x10u},
                        {0x32u, 0x20u},
@@ -805,17 +820,17 @@ void cyfitter_cfg(void)
                        {0x5Cu, 0x11u},
                        {0x5Du, 0x90u},
                        {0x5Fu, 0x01u},
-                       {0x80u, 0x17u},
+                       {0x80u, 0x04u},
                        {0x81u, 0x02u},
-                       {0x82u, 0x28u},
                        {0x83u, 0x15u},
-                       {0x84u, 0x29u},
-                       {0x86u, 0x46u},
-                       {0x88u, 0x02u},
+                       {0x88u, 0x29u},
+                       {0x89u, 0x02u},
+                       {0x8Au, 0x46u},
+                       {0x8Bu, 0x01u},
                        {0x8Cu, 0xD6u},
-                       {0x8Du, 0x02u},
-                       {0x8Fu, 0x21u},
+                       {0x90u, 0x17u},
                        {0x91u, 0x08u},
+                       {0x92u, 0x28u},
                        {0x93u, 0x10u},
                        {0x94u, 0xD0u},
                        {0x95u, 0x01u},
@@ -824,23 +839,23 @@ void cyfitter_cfg(void)
                        {0x98u, 0xD2u},
                        {0x99u, 0x02u},
                        {0x9Au, 0x04u},
-                       {0x9Bu, 0x01u},
+                       {0x9Bu, 0x21u},
                        {0x9Cu, 0x20u},
+                       {0x9Du, 0x02u},
                        {0x9Eu, 0xD0u},
+                       {0x9Fu, 0x01u},
                        {0xA0u, 0xD6u},
                        {0xA4u, 0x21u},
-                       {0xA5u, 0x02u},
                        {0xA6u, 0x8Eu},
-                       {0xA7u, 0x01u},
-                       {0xA8u, 0x04u},
+                       {0xA8u, 0x02u},
                        {0xACu, 0xD6u},
                        {0xB1u, 0x18u},
-                       {0xB2u, 0x0Fu},
                        {0xB3u, 0x03u},
-                       {0xB5u, 0x20u},
+                       {0xB4u, 0x0Fu},
+                       {0xB5u, 0x04u},
                        {0xB6u, 0xF0u},
-                       {0xB7u, 0x04u},
-                       {0xB8u, 0x08u},
+                       {0xB7u, 0x20u},
+                       {0xB8u, 0x20u},
                        {0xBAu, 0x80u},
                        {0xBBu, 0x08u},
                        {0xBFu, 0x01u},
@@ -852,44 +867,42 @@ void cyfitter_cfg(void)
                        {0xDDu, 0x90u},
                        {0xDFu, 0x01u},
                        {0x00u, 0x20u},
-                       {0x01u, 0x80u},
-                       {0x04u, 0x20u},
-                       {0x05u, 0x44u},
-                       {0x07u, 0x40u},
-                       {0x09u, 0x10u},
+                       {0x02u, 0x80u},
+                       {0x05u, 0x52u},
                        {0x0Bu, 0xA0u},
                        {0x0Cu, 0x28u},
+                       {0x0Du, 0x02u},
                        {0x0Eu, 0x02u},
-                       {0x10u, 0x01u},
+                       {0x10u, 0x04u},
                        {0x11u, 0x01u},
-                       {0x16u, 0x86u},
-                       {0x17u, 0x04u},
-                       {0x19u, 0x0Au},
-                       {0x1Au, 0x02u},
-                       {0x1Bu, 0x10u},
-                       {0x1Du, 0x04u},
+                       {0x13u, 0x40u},
+                       {0x16u, 0x80u},
+                       {0x17u, 0x54u},
+                       {0x18u, 0x80u},
+                       {0x1Au, 0x12u},
+                       {0x1Bu, 0x20u},
+                       {0x1Cu, 0x08u},
+                       {0x1Du, 0x10u},
                        {0x1Eu, 0x02u},
-                       {0x1Fu, 0x08u},
                        {0x20u, 0x10u},
                        {0x22u, 0x10u},
-                       {0x24u, 0x80u},
-                       {0x25u, 0x51u},
-                       {0x26u, 0x1Au},
+                       {0x25u, 0x01u},
+                       {0x26u, 0x9Au},
                        {0x27u, 0x80u},
-                       {0x28u, 0x04u},
+                       {0x28u, 0x20u},
                        {0x29u, 0x01u},
-                       {0x2Du, 0x08u},
-                       {0x31u, 0x0Au},
+                       {0x2Bu, 0x08u},
                        {0x32u, 0x10u},
-                       {0x36u, 0x18u},
+                       {0x36u, 0x98u},
                        {0x37u, 0x01u},
                        {0x38u, 0x10u},
+                       {0x39u, 0x80u},
                        {0x3Au, 0x20u},
-                       {0x3Bu, 0x60u},
-                       {0x3Du, 0x80u},
+                       {0x3Bu, 0x28u},
+                       {0x3Eu, 0x10u},
                        {0x3Fu, 0x01u},
-                       {0x44u, 0x04u},
-                       {0x47u, 0x20u},
+                       {0x44u, 0x01u},
+                       {0x46u, 0x02u},
                        {0x58u, 0x90u},
                        {0x5Eu, 0x40u},
                        {0x5Fu, 0x10u},
@@ -897,63 +910,65 @@ void cyfitter_cfg(void)
                        {0x63u, 0x02u},
                        {0x67u, 0x05u},
                        {0x6Fu, 0x01u},
-                       {0x81u, 0x40u},
-                       {0x83u, 0x08u},
                        {0x86u, 0x01u},
-                       {0x88u, 0x80u},
+                       {0x87u, 0x20u},
+                       {0x88u, 0xA1u},
                        {0x89u, 0x04u},
                        {0x8Du, 0x04u},
-                       {0x8Fu, 0x10u},
-                       {0x92u, 0x44u},
-                       {0x93u, 0x50u},
-                       {0x94u, 0x88u},
+                       {0x8Eu, 0x08u},
+                       {0x91u, 0x84u},
+                       {0x92u, 0x40u},
+                       {0x93u, 0x18u},
+                       {0x94u, 0x08u},
                        {0x95u, 0x01u},
                        {0x96u, 0x08u},
-                       {0x97u, 0x82u},
-                       {0x98u, 0x50u},
-                       {0x99u, 0x81u},
+                       {0x97u, 0x80u},
+                       {0x98u, 0x54u},
+                       {0x99u, 0x01u},
                        {0x9Au, 0x48u},
-                       {0x9Bu, 0x20u},
-                       {0x9Cu, 0x02u},
+                       {0x9Cu, 0x03u},
                        {0x9Du, 0x20u},
                        {0x9Eu, 0x01u},
-                       {0x9Fu, 0x98u},
-                       {0xA0u, 0xC2u},
-                       {0xA1u, 0x0Au},
+                       {0x9Fu, 0x88u},
+                       {0xA0u, 0x83u},
                        {0xA2u, 0x20u},
-                       {0xA5u, 0x05u},
+                       {0xA3u, 0x08u},
+                       {0xA5u, 0x0Du},
                        {0xA6u, 0x02u},
                        {0xA7u, 0x41u},
                        {0xACu, 0x20u},
-                       {0xAEu, 0x01u},
+                       {0xAEu, 0x81u},
                        {0xAFu, 0x10u},
-                       {0xB1u, 0x02u},
-                       {0xB2u, 0x14u},
+                       {0xB0u, 0x01u},
+                       {0xB1u, 0x41u},
+                       {0xB2u, 0x04u},
                        {0xB4u, 0x20u},
-                       {0xB6u, 0x08u},
-                       {0xC0u, 0xF3u},
-                       {0xC2u, 0xEEu},
-                       {0xC4u, 0xF9u},
-                       {0xCAu, 0x45u},
-                       {0xCCu, 0xE7u},
-                       {0xCEu, 0x9Cu},
+                       {0xC0u, 0xDAu},
+                       {0xC2u, 0xFCu},
+                       {0xC4u, 0xFBu},
+                       {0xCAu, 0x07u},
+                       {0xCCu, 0xF4u},
+                       {0xCEu, 0xAEu},
                        {0xD6u, 0x3Cu},
                        {0xD8u, 0x3Cu},
-                       {0xE0u, 0x01u},
-                       {0xE4u, 0x03u},
+                       {0xE2u, 0x02u},
+                       {0xE4u, 0x0Au},
                        {0xE6u, 0x20u},
                        {0xE8u, 0x02u},
-                       {0xEAu, 0x80u},
                        {0xECu, 0x42u},
                        {0x01u, 0x02u},
+                       {0x02u, 0x12u},
                        {0x03u, 0x01u},
                        {0x05u, 0x02u},
                        {0x06u, 0x01u},
                        {0x07u, 0x11u},
+                       {0x08u, 0x04u},
                        {0x09u, 0x02u},
+                       {0x0Au, 0x43u},
                        {0x0Bu, 0x05u},
+                       {0x10u, 0x21u},
                        {0x11u, 0x01u},
-                       {0x12u, 0x12u},
+                       {0x12u, 0x02u},
                        {0x13u, 0x02u},
                        {0x15u, 0x02u},
                        {0x17u, 0x09u},
@@ -961,10 +976,6 @@ void cyfitter_cfg(void)
                        {0x20u, 0xE0u},
                        {0x24u, 0x88u},
                        {0x26u, 0x03u},
-                       {0x28u, 0x04u},
-                       {0x2Au, 0x43u},
-                       {0x2Cu, 0x21u},
-                       {0x2Eu, 0x02u},
                        {0x31u, 0x04u},
                        {0x32u, 0x10u},
                        {0x33u, 0x10u},
@@ -978,29 +989,31 @@ void cyfitter_cfg(void)
                        {0x59u, 0x04u},
                        {0x5Cu, 0x10u},
                        {0x5Fu, 0x01u},
-                       {0x80u, 0x02u},
+                       {0x80u, 0xFDu},
+                       {0x82u, 0x02u},
                        {0x84u, 0x10u},
                        {0x85u, 0x50u},
                        {0x86u, 0x20u},
                        {0x87u, 0xA0u},
-                       {0x88u, 0xFDu},
-                       {0x8Au, 0x02u},
-                       {0x8Eu, 0xF7u},
+                       {0x88u, 0x0Bu},
+                       {0x89u, 0x60u},
+                       {0x8Au, 0xF4u},
+                       {0x8Bu, 0x90u},
+                       {0x8Cu, 0xF4u},
+                       {0x8Du, 0x30u},
+                       {0x8Fu, 0xC0u},
                        {0x90u, 0x03u},
-                       {0x91u, 0x30u},
                        {0x92u, 0x0Cu},
-                       {0x93u, 0xC0u},
-                       {0x94u, 0x0Bu},
-                       {0x96u, 0xF4u},
+                       {0x94u, 0x40u},
+                       {0x95u, 0x0Fu},
+                       {0x96u, 0x80u},
+                       {0x97u, 0xF0u},
                        {0x98u, 0x08u},
-                       {0x99u, 0x60u},
                        {0x9Au, 0xF7u},
-                       {0x9Bu, 0x90u},
                        {0x9Cu, 0x40u},
                        {0x9Eu, 0x80u},
-                       {0xA0u, 0x40u},
+                       {0xA0u, 0x02u},
                        {0xA1u, 0x05u},
-                       {0xA2u, 0x80u},
                        {0xA3u, 0x0Au},
                        {0xA5u, 0x06u},
                        {0xA6u, 0x01u},
@@ -1009,9 +1022,7 @@ void cyfitter_cfg(void)
                        {0xA9u, 0x03u},
                        {0xAAu, 0x20u},
                        {0xABu, 0x0Cu},
-                       {0xACu, 0xF4u},
-                       {0xADu, 0x0Fu},
-                       {0xAFu, 0xF0u},
+                       {0xAEu, 0xF7u},
                        {0xB0u, 0x0Fu},
                        {0xB3u, 0xFFu},
                        {0xB4u, 0x30u},
@@ -1025,24 +1036,24 @@ void cyfitter_cfg(void)
                        {0xDBu, 0x04u},
                        {0xDCu, 0x01u},
                        {0xDFu, 0x01u},
-                       {0x00u, 0x14u},
-                       {0x02u, 0x40u},
-                       {0x03u, 0x01u},
-                       {0x05u, 0x04u},
+                       {0x00u, 0x06u},
+                       {0x02u, 0x02u},
+                       {0x03u, 0x08u},
+                       {0x04u, 0x02u},
+                       {0x05u, 0x14u},
                        {0x06u, 0x01u},
                        {0x07u, 0x01u},
-                       {0x09u, 0x08u},
-                       {0x0Au, 0x46u},
+                       {0x08u, 0x08u},
+                       {0x0Au, 0x42u},
+                       {0x0Bu, 0x08u},
                        {0x0Du, 0x02u},
                        {0x0Eu, 0x02u},
                        {0x11u, 0x10u},
-                       {0x12u, 0x22u},
-                       {0x13u, 0x02u},
-                       {0x14u, 0x04u},
+                       {0x12u, 0x61u},
                        {0x15u, 0x02u},
-                       {0x17u, 0x44u},
+                       {0x17u, 0x04u},
                        {0x1Au, 0x4Au},
-                       {0x1Bu, 0x41u},
+                       {0x1Bu, 0x40u},
                        {0x1Du, 0x04u},
                        {0x1Eu, 0x02u},
                        {0x1Fu, 0x10u},
@@ -1051,109 +1062,100 @@ void cyfitter_cfg(void)
                        {0x26u, 0x04u},
                        {0x27u, 0x01u},
                        {0x28u, 0x80u},
-                       {0x29u, 0x80u},
                        {0x2Au, 0x28u},
-                       {0x2Cu, 0x04u},
-                       {0x2Fu, 0x08u},
-                       {0x30u, 0x01u},
-                       {0x31u, 0x11u},
+                       {0x30u, 0x04u},
                        {0x36u, 0x04u},
                        {0x37u, 0x01u},
-                       {0x38u, 0x08u},
+                       {0x38u, 0x28u},
+                       {0x3Bu, 0x40u},
                        {0x3Du, 0x22u},
                        {0x3Fu, 0x04u},
-                       {0x40u, 0x02u},
-                       {0x43u, 0x80u},
                        {0x4Du, 0x10u},
                        {0x4Eu, 0x04u},
-                       {0x5Cu, 0x10u},
-                       {0x5Fu, 0x20u},
-                       {0x60u, 0x02u},
-                       {0x62u, 0x18u},
-                       {0x63u, 0x40u},
-                       {0x67u, 0x03u},
-                       {0x69u, 0x89u},
+                       {0x60u, 0x40u},
+                       {0x62u, 0x98u},
+                       {0x69u, 0x09u},
                        {0x6Au, 0x20u},
-                       {0x70u, 0x04u},
-                       {0x71u, 0x11u},
-                       {0x73u, 0x01u},
+                       {0x6Bu, 0x02u},
+                       {0x70u, 0x14u},
+                       {0x72u, 0x02u},
+                       {0x73u, 0x40u},
                        {0x80u, 0x80u},
-                       {0x84u, 0x04u},
-                       {0x86u, 0x10u},
-                       {0x8Bu, 0x51u},
-                       {0x8Du, 0x10u},
-                       {0x90u, 0x04u},
-                       {0x92u, 0x04u},
-                       {0x93u, 0x04u},
-                       {0x94u, 0x28u},
-                       {0x95u, 0x89u},
+                       {0x87u, 0x02u},
+                       {0x8Bu, 0x10u},
+                       {0x8Cu, 0x40u},
+                       {0x90u, 0x84u},
+                       {0x91u, 0x04u},
+                       {0x93u, 0x0Cu},
+                       {0x94u, 0x08u},
+                       {0x95u, 0x09u},
                        {0x96u, 0x08u},
-                       {0x97u, 0x82u},
-                       {0x98u, 0x40u},
-                       {0x99u, 0x82u},
+                       {0x97u, 0xC0u},
+                       {0x98u, 0x4Cu},
+                       {0x99u, 0x10u},
                        {0x9Au, 0x68u},
-                       {0x9Bu, 0x22u},
-                       {0x9Cu, 0x01u},
-                       {0x9Du, 0x60u},
-                       {0x9Eu, 0x87u},
+                       {0x9Du, 0x62u},
+                       {0x9Eu, 0x83u},
                        {0x9Fu, 0x54u},
-                       {0xA0u, 0x82u},
-                       {0xA1u, 0x08u},
+                       {0xA0u, 0x87u},
                        {0xA2u, 0x22u},
-                       {0xA3u, 0x08u},
+                       {0xA3u, 0x18u},
                        {0xA4u, 0x38u},
+                       {0xA5u, 0x0Au},
                        {0xA7u, 0x40u},
                        {0xAAu, 0x10u},
-                       {0xABu, 0x08u},
-                       {0xACu, 0x40u},
-                       {0xAFu, 0x02u},
+                       {0xABu, 0x10u},
+                       {0xAFu, 0x08u},
+                       {0xB0u, 0x08u},
                        {0xB2u, 0x08u},
                        {0xB4u, 0x04u},
+                       {0xB5u, 0x10u},
                        {0xB6u, 0x02u},
-                       {0xC0u, 0x2Fu},
+                       {0xC0u, 0x7Fu},
                        {0xC2u, 0x9Fu},
-                       {0xC4u, 0xFFu},
-                       {0xCAu, 0x0Fu},
-                       {0xCCu, 0xC5u},
-                       {0xCEu, 0xE2u},
+                       {0xC4u, 0x3Fu},
+                       {0xCAu, 0x07u},
+                       {0xCCu, 0xC2u},
+                       {0xCEu, 0xEEu},
                        {0xD8u, 0x0Fu},
-                       {0xE2u, 0x2Au},
-                       {0xE6u, 0x41u},
-                       {0xEAu, 0x04u},
+                       {0xE2u, 0x48u},
+                       {0xE4u, 0x02u},
+                       {0xE6u, 0x01u},
+                       {0xEAu, 0x0Au},
                        {0xECu, 0x04u},
-                       {0xEEu, 0x02u},
+                       {0xEEu, 0x03u},
                        {0x82u, 0x01u},
-                       {0x89u, 0x40u},
+                       {0x84u, 0x02u},
                        {0x8Bu, 0x40u},
-                       {0x8Du, 0x40u},
-                       {0x90u, 0x20u},
-                       {0x95u, 0x44u},
-                       {0x97u, 0x80u},
-                       {0x9Du, 0x40u},
-                       {0x9Eu, 0x08u},
+                       {0x94u, 0x01u},
+                       {0x95u, 0x04u},
+                       {0x97u, 0x84u},
+                       {0x9Cu, 0x02u},
                        {0xA2u, 0x01u},
-                       {0xA5u, 0x18u},
+                       {0xA4u, 0xA0u},
+                       {0xA5u, 0x14u},
                        {0xA7u, 0x20u},
-                       {0xA8u, 0x01u},
-                       {0xA9u, 0x28u},
+                       {0xA8u, 0x10u},
                        {0xAAu, 0x04u},
-                       {0xACu, 0x02u},
-                       {0xB1u, 0x80u},
-                       {0xB4u, 0xA0u},
-                       {0xB7u, 0x28u},
-                       {0xE0u, 0xC0u},
-                       {0xE2u, 0x0Au},
+                       {0xADu, 0x20u},
+                       {0xAEu, 0x01u},
+                       {0xB1u, 0xC0u},
+                       {0xB4u, 0x80u},
+                       {0xB6u, 0x82u},
+                       {0xB7u, 0x08u},
+                       {0xE2u, 0x08u},
                        {0xE4u, 0x80u},
-                       {0xE6u, 0x40u},
+                       {0xE8u, 0x40u},
+                       {0xEAu, 0x82u},
                        {0xECu, 0xD0u},
+                       {0x00u, 0x02u},
                        {0x01u, 0x02u},
+                       {0x02u, 0x05u},
                        {0x03u, 0x01u},
                        {0x04u, 0x01u},
                        {0x06u, 0x02u},
                        {0x0Du, 0x01u},
                        {0x0Fu, 0x02u},
-                       {0x10u, 0x02u},
-                       {0x12u, 0x05u},
                        {0x14u, 0x02u},
                        {0x15u, 0x02u},
                        {0x16u, 0x11u},
@@ -1183,32 +1185,32 @@ void cyfitter_cfg(void)
                        {0x5Cu, 0x11u},
                        {0x5Du, 0x90u},
                        {0x5Fu, 0x01u},
+                       {0x80u, 0xFFu},
                        {0x81u, 0x03u},
                        {0x83u, 0x04u},
                        {0x84u, 0x33u},
-                       {0x85u, 0x10u},
+                       {0x85u, 0x08u},
                        {0x86u, 0xCCu},
                        {0x88u, 0x69u},
                        {0x89u, 0x05u},
                        {0x8Au, 0x96u},
                        {0x8Bu, 0x02u},
-                       {0x8Du, 0x20u},
+                       {0x8Du, 0x50u},
+                       {0x8Eu, 0xFFu},
+                       {0x8Fu, 0xA0u},
                        {0x90u, 0x0Fu},
-                       {0x91u, 0x50u},
+                       {0x91u, 0x80u},
                        {0x92u, 0xF0u},
-                       {0x93u, 0xA0u},
                        {0x95u, 0x40u},
-                       {0x96u, 0xFFu},
-                       {0x98u, 0xFFu},
                        {0x99u, 0x04u},
+                       {0x9Au, 0xFFu},
                        {0x9Bu, 0x03u},
-                       {0x9Du, 0x08u},
-                       {0xA2u, 0xFFu},
+                       {0x9Cu, 0xFFu},
+                       {0xA1u, 0x20u},
                        {0xA5u, 0x01u},
                        {0xA6u, 0xFFu},
                        {0xA7u, 0x06u},
-                       {0xA8u, 0xFFu},
-                       {0xA9u, 0x80u},
+                       {0xA9u, 0x10u},
                        {0xACu, 0x55u},
                        {0xAEu, 0xAAu},
                        {0xB0u, 0xFFu},
@@ -1224,118 +1226,117 @@ void cyfitter_cfg(void)
                        {0xDBu, 0x04u},
                        {0xDCu, 0x01u},
                        {0xDFu, 0x01u},
-                       {0x01u, 0x08u},
-                       {0x06u, 0x20u},
+                       {0x01u, 0x0Au},
+                       {0x04u, 0x80u},
+                       {0x06u, 0xA0u},
                        {0x07u, 0x08u},
                        {0x08u, 0x08u},
-                       {0x0Au, 0x85u},
-                       {0x0Cu, 0x20u},
-                       {0x0Du, 0x08u},
+                       {0x0Au, 0x05u},
                        {0x0Eu, 0x40u},
-                       {0x14u, 0x01u},
-                       {0x15u, 0x01u},
-                       {0x16u, 0x10u},
-                       {0x17u, 0x20u},
-                       {0x19u, 0x08u},
-                       {0x1Au, 0x95u},
+                       {0x0Fu, 0x06u},
+                       {0x14u, 0x11u},
+                       {0x19u, 0x0Au},
+                       {0x1Au, 0x15u},
                        {0x1Eu, 0x40u},
                        {0x21u, 0x41u},
                        {0x22u, 0x14u},
-                       {0x24u, 0x20u},
+                       {0x24u, 0x10u},
                        {0x26u, 0x02u},
-                       {0x27u, 0x16u},
-                       {0x2Cu, 0x08u},
-                       {0x2Eu, 0x08u},
+                       {0x27u, 0x26u},
+                       {0x2Cu, 0xA0u},
+                       {0x2Fu, 0x08u},
                        {0x31u, 0x80u},
                        {0x32u, 0x14u},
-                       {0x35u, 0x40u},
+                       {0x34u, 0x02u},
                        {0x36u, 0x04u},
-                       {0x37u, 0x11u},
+                       {0x37u, 0x20u},
                        {0x38u, 0x40u},
                        {0x39u, 0x82u},
-                       {0x3Cu, 0x04u},
-                       {0x3Du, 0x62u},
-                       {0x58u, 0xA0u},
+                       {0x3Du, 0xA8u},
+                       {0x3Eu, 0x02u},
+                       {0x58u, 0x80u},
+                       {0x59u, 0x20u},
                        {0x5Cu, 0x41u},
                        {0x5Du, 0x04u},
                        {0x5Eu, 0x10u},
-                       {0x60u, 0x02u},
-                       {0x61u, 0x30u},
-                       {0x62u, 0x40u},
+                       {0x61u, 0x70u},
                        {0x65u, 0x80u},
-                       {0x6Fu, 0x03u},
-                       {0x80u, 0x08u},
-                       {0x81u, 0x01u},
+                       {0x6Du, 0x80u},
+                       {0x81u, 0x20u},
+                       {0x88u, 0x04u},
                        {0x8Au, 0x0Au},
+                       {0x8Bu, 0x01u},
                        {0x8Eu, 0x40u},
-                       {0x90u, 0x04u},
-                       {0x91u, 0x01u},
-                       {0x97u, 0x80u},
-                       {0x98u, 0x09u},
-                       {0x9Au, 0x30u},
-                       {0x9Du, 0x10u},
-                       {0x9Eu, 0x40u},
-                       {0x9Fu, 0x26u},
-                       {0xA0u, 0x20u},
+                       {0x8Fu, 0x0Cu},
+                       {0x90u, 0x80u},
+                       {0x92u, 0x02u},
+                       {0x97u, 0x84u},
+                       {0x98u, 0x19u},
+                       {0x9Au, 0x20u},
+                       {0x9Cu, 0x04u},
+                       {0x9Du, 0x50u},
+                       {0x9Eu, 0x80u},
+                       {0x9Fu, 0x02u},
                        {0xA1u, 0x80u},
                        {0xA2u, 0x01u},
-                       {0xA5u, 0x08u},
+                       {0xA5u, 0x40u},
                        {0xA6u, 0x08u},
-                       {0xA7u, 0x22u},
+                       {0xA7u, 0x20u},
                        {0xA8u, 0x10u},
                        {0xADu, 0xB0u},
                        {0xAEu, 0x04u},
                        {0xAFu, 0x10u},
-                       {0xB1u, 0x40u},
-                       {0xB2u, 0x10u},
-                       {0xB6u, 0x20u},
-                       {0xB7u, 0x14u},
-                       {0xC0u, 0x64u},
-                       {0xC2u, 0x7Fu},
-                       {0xC4u, 0xF0u},
-                       {0xCAu, 0x60u},
-                       {0xCCu, 0xFEu},
+                       {0xB0u, 0x10u},
+                       {0xB1u, 0x50u},
+                       {0xB3u, 0x40u},
+                       {0xB7u, 0x10u},
+                       {0xC0u, 0xFCu},
+                       {0xC2u, 0xD7u},
+                       {0xC4u, 0xA0u},
+                       {0xCAu, 0xE0u},
+                       {0xCCu, 0xEEu},
                        {0xCEu, 0xF9u},
                        {0xD6u, 0xFCu},
                        {0xD8u, 0x1Cu},
-                       {0xE0u, 0x10u},
-                       {0xE2u, 0x20u},
-                       {0xE4u, 0x82u},
-                       {0xE6u, 0x60u},
-                       {0xE8u, 0x04u},
-                       {0xEAu, 0x58u},
-                       {0xECu, 0x60u},
-                       {0x03u, 0x24u},
-                       {0x04u, 0xFFu},
+                       {0xE0u, 0x90u},
+                       {0xE2u, 0x22u},
+                       {0xE4u, 0x8Au},
+                       {0xE6u, 0x61u},
+                       {0xE8u, 0xA4u},
+                       {0xEAu, 0x48u},
+                       {0xECu, 0x40u},
+                       {0xEEu, 0x20u},
+                       {0x00u, 0xFFu},
+                       {0x01u, 0x24u},
+                       {0x03u, 0x09u},
                        {0x07u, 0x20u},
                        {0x08u, 0x33u},
-                       {0x09u, 0x40u},
+                       {0x09u, 0x24u},
                        {0x0Au, 0xCCu},
-                       {0x0Bu, 0x80u},
-                       {0x0Du, 0x24u},
-                       {0x0Fu, 0x09u},
-                       {0x10u, 0x0Fu},
+                       {0x0Bu, 0x12u},
+                       {0x0Cu, 0x55u},
+                       {0x0Du, 0x40u},
+                       {0x0Eu, 0xAAu},
+                       {0x0Fu, 0x80u},
                        {0x11u, 0x40u},
-                       {0x12u, 0xF0u},
+                       {0x12u, 0xFFu},
                        {0x13u, 0x18u},
-                       {0x16u, 0xFFu},
+                       {0x14u, 0x0Fu},
+                       {0x16u, 0xF0u},
                        {0x17u, 0x04u},
-                       {0x18u, 0xFFu},
+                       {0x1Au, 0xFFu},
                        {0x1Bu, 0x03u},
                        {0x1Cu, 0x96u},
                        {0x1Eu, 0x69u},
-                       {0x20u, 0x55u},
-                       {0x22u, 0xAAu},
-                       {0x25u, 0x24u},
                        {0x26u, 0xFFu},
-                       {0x27u, 0x12u},
+                       {0x27u, 0x24u},
+                       {0x28u, 0xFFu},
                        {0x29u, 0x80u},
-                       {0x2Eu, 0xFFu},
-                       {0x30u, 0xFFu},
                        {0x31u, 0x38u},
+                       {0x32u, 0xFFu},
                        {0x33u, 0xC0u},
                        {0x35u, 0x07u},
-                       {0x3Au, 0x02u},
+                       {0x3Au, 0x08u},
                        {0x3Fu, 0x04u},
                        {0x56u, 0x08u},
                        {0x58u, 0x04u},
@@ -1344,81 +1345,87 @@ void cyfitter_cfg(void)
                        {0x5Cu, 0x11u},
                        {0x5Du, 0x90u},
                        {0x5Fu, 0x01u},
+                       {0x81u, 0x11u},
+                       {0x83u, 0x22u},
                        {0x84u, 0x48u},
-                       {0x85u, 0x21u},
                        {0x86u, 0x84u},
-                       {0x87u, 0x12u},
                        {0x88u, 0x44u},
                        {0x8Au, 0x88u},
                        {0x8Bu, 0xFFu},
-                       {0x8Cu, 0x33u},
                        {0x8Du, 0x0Fu},
-                       {0x8Eu, 0xCCu},
                        {0x8Fu, 0xF0u},
                        {0x90u, 0x0Fu},
-                       {0x91u, 0x11u},
                        {0x92u, 0xF0u},
-                       {0x93u, 0x22u},
-                       {0x95u, 0x44u},
+                       {0x95u, 0x21u},
                        {0x96u, 0xFFu},
-                       {0x97u, 0x88u},
+                       {0x97u, 0x12u},
                        {0x9Au, 0xFFu},
                        {0x9Bu, 0xFFu},
+                       {0x9Cu, 0x33u},
                        {0x9Du, 0xFFu},
+                       {0x9Eu, 0xCCu},
+                       {0xA1u, 0x33u},
                        {0xA2u, 0xFFu},
+                       {0xA3u, 0xCCu},
                        {0xA4u, 0x12u},
                        {0xA5u, 0x84u},
                        {0xA6u, 0x21u},
                        {0xA7u, 0x48u},
+                       {0xA9u, 0x44u},
+                       {0xABu, 0x88u},
                        {0xACu, 0x11u},
-                       {0xADu, 0x33u},
                        {0xAEu, 0x22u},
-                       {0xAFu, 0xCCu},
                        {0xB0u, 0xFFu},
                        {0xB3u, 0xFFu},
-                       {0xB9u, 0x20u},
+                       {0xB9u, 0x02u},
                        {0xBEu, 0x01u},
-                       {0xBFu, 0x14u},
+                       {0xBFu, 0x05u},
                        {0xD6u, 0x08u},
                        {0xD8u, 0x04u},
                        {0xD9u, 0x04u},
                        {0xDBu, 0x04u},
                        {0xDDu, 0x90u},
                        {0xDFu, 0x01u},
-                       {0x01u, 0x14u},
+                       {0x01u, 0x04u},
                        {0x02u, 0x08u},
-                       {0x03u, 0x22u},
-                       {0x05u, 0x10u},
-                       {0x07u, 0x20u},
-                       {0x08u, 0x02u},
+                       {0x03u, 0x20u},
+                       {0x05u, 0x50u},
+                       {0x06u, 0x80u},
+                       {0x08u, 0x42u},
+                       {0x09u, 0x40u},
                        {0x0Au, 0x24u},
                        {0x0Bu, 0xA0u},
-                       {0x0Cu, 0x20u},
-                       {0x0Du, 0x0Au},
-                       {0x0Fu, 0x02u},
+                       {0x0Du, 0x02u},
+                       {0x0Eu, 0x20u},
+                       {0x0Fu, 0x06u},
                        {0x10u, 0x80u},
                        {0x11u, 0x08u},
-                       {0x12u, 0x02u},
-                       {0x13u, 0x06u},
-                       {0x16u, 0x52u},
+                       {0x12u, 0x03u},
+                       {0x13u, 0x02u},
+                       {0x14u, 0x10u},
+                       {0x15u, 0x10u},
                        {0x1Au, 0x40u},
-                       {0x1Du, 0x02u},
+                       {0x1Eu, 0x20u},
+                       {0x1Fu, 0x04u},
                        {0x20u, 0x20u},
-                       {0x21u, 0x20u},
-                       {0x24u, 0x24u},
+                       {0x22u, 0x01u},
+                       {0x24u, 0x20u},
                        {0x26u, 0x21u},
-                       {0x2Bu, 0x22u},
-                       {0x2Cu, 0x20u},
+                       {0x28u, 0x44u},
+                       {0x2Bu, 0x20u},
+                       {0x2Cu, 0x10u},
                        {0x2Fu, 0x08u},
                        {0x30u, 0x80u},
-                       {0x32u, 0x1Au},
+                       {0x31u, 0x08u},
+                       {0x32u, 0x10u},
                        {0x36u, 0x21u},
                        {0x37u, 0x08u},
                        {0x39u, 0x20u},
-                       {0x3Bu, 0x84u},
-                       {0x3Du, 0x81u},
-                       {0x3Eu, 0x0Au},
-                       {0x3Fu, 0x10u},
+                       {0x3Au, 0x01u},
+                       {0x3Bu, 0x80u},
+                       {0x3Du, 0x90u},
+                       {0x3Eu, 0x08u},
+                       {0x3Fu, 0x01u},
                        {0x5Bu, 0x50u},
                        {0x5Cu, 0x20u},
                        {0x5Du, 0x80u},
@@ -1427,43 +1434,41 @@ void cyfitter_cfg(void)
                        {0x64u, 0x01u},
                        {0x66u, 0x20u},
                        {0x67u, 0x02u},
-                       {0x81u, 0x20u},
                        {0x83u, 0x09u},
-                       {0x84u, 0x20u},
-                       {0x87u, 0x12u},
-                       {0x89u, 0x02u},
+                       {0x86u, 0x20u},
                        {0x8Au, 0x20u},
-                       {0x8Bu, 0x02u},
-                       {0x91u, 0x01u},
+                       {0x8Bu, 0x06u},
+                       {0x8Cu, 0x40u},
+                       {0x8Du, 0x02u},
+                       {0x8Fu, 0x01u},
                        {0x95u, 0x34u},
                        {0x96u, 0x44u},
-                       {0x97u, 0x10u},
+                       {0x97u, 0x41u},
                        {0x98u, 0x20u},
                        {0x9Au, 0x08u},
                        {0x9Bu, 0x48u},
-                       {0x9Cu, 0x02u},
+                       {0x9Cu, 0x46u},
                        {0x9Du, 0x20u},
                        {0x9Fu, 0x02u},
-                       {0xA1u, 0x04u},
+                       {0xA1u, 0x0Cu},
                        {0xA2u, 0x02u},
                        {0xA3u, 0x01u},
                        {0xA4u, 0x10u},
-                       {0xA5u, 0x40u},
                        {0xA8u, 0x20u},
-                       {0xADu, 0x01u},
                        {0xAEu, 0x24u},
-                       {0xAFu, 0x04u},
                        {0xB2u, 0x11u},
                        {0xB4u, 0x20u},
-                       {0xC0u, 0x67u},
-                       {0xC2u, 0xFEu},
-                       {0xC4u, 0xBDu},
-                       {0xCAu, 0x6Au},
-                       {0xCCu, 0xEFu},
-                       {0xCEu, 0xFEu},
+                       {0xC0u, 0xD6u},
+                       {0xC2u, 0xFFu},
+                       {0xC4u, 0x6Du},
+                       {0xCAu, 0x67u},
+                       {0xCCu, 0xEEu},
+                       {0xCEu, 0xFDu},
                        {0xD6u, 0x3Cu},
                        {0xD8u, 0x3Cu},
-                       {0xE6u, 0xA8u},
+                       {0xE2u, 0x80u},
+                       {0xE4u, 0x10u},
+                       {0xE6u, 0xA0u},
                        {0xE8u, 0x80u},
                        {0xEAu, 0x20u},
                        {0xECu, 0x88u},
@@ -1476,19 +1481,19 @@ void cyfitter_cfg(void)
                        {0x08u, 0x01u},
                        {0x0Bu, 0xFFu},
                        {0x0Cu, 0x01u},
+                       {0x0Du, 0x11u},
+                       {0x0Fu, 0x22u},
                        {0x10u, 0x01u},
                        {0x13u, 0xFFu},
                        {0x14u, 0x02u},
                        {0x15u, 0x21u},
                        {0x17u, 0x12u},
                        {0x18u, 0x01u},
-                       {0x19u, 0x33u},
-                       {0x1Bu, 0xCCu},
-                       {0x21u, 0x11u},
-                       {0x23u, 0x22u},
-                       {0x24u, 0x0Au},
+                       {0x20u, 0x0Au},
+                       {0x21u, 0x33u},
+                       {0x22u, 0x14u},
+                       {0x23u, 0xCCu},
                        {0x25u, 0xFFu},
-                       {0x26u, 0x14u},
                        {0x28u, 0x10u},
                        {0x29u, 0x44u},
                        {0x2Bu, 0x88u},
@@ -1505,30 +1510,30 @@ void cyfitter_cfg(void)
                        {0x5Bu, 0x04u},
                        {0x5Du, 0x90u},
                        {0x5Fu, 0x01u},
-                       {0x81u, 0x40u},
-                       {0x83u, 0x24u},
+                       {0x81u, 0x64u},
+                       {0x83u, 0x09u},
                        {0x84u, 0x12u},
-                       {0x85u, 0x64u},
                        {0x86u, 0x21u},
-                       {0x87u, 0x12u},
                        {0x88u, 0xFFu},
                        {0x8Cu, 0xFFu},
-                       {0x8Du, 0x64u},
-                       {0x8Fu, 0x09u},
+                       {0x8Du, 0x40u},
+                       {0x8Fu, 0x24u},
                        {0x93u, 0x18u},
-                       {0x94u, 0x33u},
-                       {0x96u, 0xCCu},
+                       {0x94u, 0x44u},
+                       {0x96u, 0x88u},
                        {0x97u, 0x03u},
                        {0x9Au, 0xFFu},
                        {0x9Bu, 0x04u},
                        {0x9Cu, 0x11u},
                        {0x9Eu, 0x22u},
+                       {0xA0u, 0x33u},
+                       {0xA2u, 0xCCu},
                        {0xA3u, 0x40u},
                        {0xA4u, 0x48u},
                        {0xA6u, 0x84u},
                        {0xA7u, 0x20u},
-                       {0xA8u, 0x44u},
-                       {0xAAu, 0x88u},
+                       {0xA9u, 0x64u},
+                       {0xABu, 0x12u},
                        {0xACu, 0x0Fu},
                        {0xAEu, 0xF0u},
                        {0xB0u, 0xFFu},
@@ -1550,40 +1555,36 @@ void cyfitter_cfg(void)
                        {0x07u, 0x13u},
                        {0x09u, 0x24u},
                        {0x0Au, 0x40u},
+                       {0x0Cu, 0x04u},
+                       {0x0Du, 0x40u},
                        {0x0Eu, 0x06u},
-                       {0x0Fu, 0x10u},
-                       {0x10u, 0x10u},
-                       {0x11u, 0x10u},
+                       {0x10u, 0x44u},
                        {0x12u, 0x02u},
-                       {0x14u, 0x0Au},
-                       {0x15u, 0x14u},
+                       {0x14u, 0x42u},
+                       {0x15u, 0x04u},
                        {0x16u, 0x01u},
                        {0x1Au, 0x18u},
                        {0x1Bu, 0x80u},
                        {0x1Fu, 0x02u},
                        {0x21u, 0x20u},
-                       {0x25u, 0x04u},
+                       {0x25u, 0x0Cu},
                        {0x26u, 0x8Bu},
                        {0x27u, 0x10u},
-                       {0x28u, 0x08u},
-                       {0x29u, 0x01u},
+                       {0x28u, 0x44u},
                        {0x2Au, 0x04u},
                        {0x2Cu, 0xA0u},
-                       {0x30u, 0x10u},
+                       {0x2Du, 0x10u},
                        {0x32u, 0x08u},
                        {0x33u, 0x01u},
-                       {0x35u, 0x01u},
                        {0x36u, 0x2Au},
-                       {0x39u, 0x24u},
+                       {0x39u, 0xA4u},
                        {0x3Au, 0x01u},
-                       {0x3Du, 0x81u},
-                       {0x3Fu, 0x04u},
+                       {0x3Fu, 0x41u},
                        {0x59u, 0x80u},
                        {0x5Cu, 0x04u},
                        {0x5Eu, 0xA1u},
                        {0x63u, 0x02u},
-                       {0x64u, 0x11u},
-                       {0x67u, 0x10u},
+                       {0x64u, 0x01u},
                        {0x78u, 0x01u},
                        {0x7Au, 0x80u},
                        {0x81u, 0x80u},
@@ -1595,17 +1596,17 @@ void cyfitter_cfg(void)
                        {0x8Fu, 0x40u},
                        {0xC0u, 0xE7u},
                        {0xC2u, 0xEEu},
-                       {0xC4u, 0xE7u},
-                       {0xCAu, 0xC7u},
-                       {0xCCu, 0xE7u},
-                       {0xCEu, 0xD7u},
+                       {0xC4u, 0xBBu},
+                       {0xCAu, 0xE7u},
+                       {0xCCu, 0xE3u},
+                       {0xCEu, 0x9Fu},
                        {0xD6u, 0xF8u},
                        {0xD8u, 0x18u},
-                       {0xE0u, 0x50u},
+                       {0xE0u, 0x10u},
                        {0xE2u, 0x04u},
-                       {0xE4u, 0x48u},
-                       {0x80u, 0x02u},
-                       {0x82u, 0x05u},
+                       {0xE4u, 0x4Cu},
+                       {0x8Cu, 0x02u},
+                       {0x8Eu, 0x05u},
                        {0x94u, 0x02u},
                        {0x96u, 0x01u},
                        {0x98u, 0x01u},
@@ -1615,21 +1616,22 @@ void cyfitter_cfg(void)
                        {0xA5u, 0x01u},
                        {0xACu, 0x02u},
                        {0xAEu, 0x09u},
+                       {0xB1u, 0x01u},
                        {0xB2u, 0x08u},
                        {0xB4u, 0x03u},
                        {0xB6u, 0x04u},
-                       {0xB7u, 0x01u},
                        {0xBAu, 0x20u},
                        {0xD8u, 0x04u},
                        {0xD9u, 0x04u},
                        {0xDCu, 0x91u},
                        {0xDFu, 0x01u},
-                       {0x00u, 0x04u},
+                       {0x00u, 0x08u},
                        {0x01u, 0x01u},
-                       {0x03u, 0x0Au},
-                       {0x05u, 0x02u},
-                       {0x09u, 0x15u},
-                       {0x0Eu, 0x26u},
+                       {0x03u, 0x06u},
+                       {0x04u, 0x80u},
+                       {0x09u, 0x06u},
+                       {0x0Au, 0x08u},
+                       {0x0Eu, 0x2Au},
                        {0x10u, 0x28u},
                        {0x11u, 0x40u},
                        {0x13u, 0x01u},
@@ -1638,91 +1640,94 @@ void cyfitter_cfg(void)
                        {0x16u, 0x40u},
                        {0x19u, 0x08u},
                        {0x1Cu, 0x20u},
-                       {0x1Eu, 0x26u},
+                       {0x1Eu, 0x2Au},
                        {0x1Fu, 0x30u},
-                       {0x20u, 0x14u},
-                       {0x21u, 0x01u},
-                       {0x22u, 0x40u},
-                       {0x27u, 0x01u},
-                       {0x29u, 0x48u},
-                       {0x2Bu, 0x48u},
+                       {0x21u, 0x05u},
+                       {0x22u, 0x54u},
+                       {0x25u, 0x01u},
+                       {0x29u, 0x58u},
+                       {0x2Au, 0x01u},
                        {0x2Fu, 0x20u},
-                       {0x30u, 0x20u},
-                       {0x33u, 0x46u},
-                       {0x38u, 0x14u},
-                       {0x39u, 0x41u},
-                       {0x40u, 0x40u},
-                       {0x41u, 0x60u},
-                       {0x43u, 0x08u},
-                       {0x49u, 0x04u},
+                       {0x31u, 0x82u},
+                       {0x32u, 0x10u},
+                       {0x33u, 0x04u},
+                       {0x38u, 0x20u},
+                       {0x39u, 0x49u},
+                       {0x41u, 0x42u},
+                       {0x43u, 0x04u},
+                       {0x48u, 0x04u},
+                       {0x49u, 0x06u},
                        {0x4Au, 0x02u},
-                       {0x4Bu, 0x02u},
-                       {0x51u, 0x02u},
-                       {0x52u, 0x14u},
+                       {0x50u, 0x01u},
+                       {0x52u, 0x91u},
                        {0x53u, 0x82u},
-                       {0x61u, 0x01u},
+                       {0x63u, 0x20u},
                        {0x68u, 0x28u},
-                       {0x69u, 0x41u},
+                       {0x69u, 0x45u},
+                       {0x6Bu, 0x40u},
                        {0x71u, 0x40u},
                        {0x73u, 0x01u},
-                       {0x87u, 0x11u},
+                       {0x81u, 0x01u},
+                       {0x87u, 0x10u},
+                       {0x89u, 0x84u},
                        {0x8Au, 0x02u},
-                       {0x90u, 0x40u},
+                       {0x90u, 0xA0u},
                        {0x91u, 0x80u},
+                       {0x94u, 0x02u},
                        {0x95u, 0x41u},
                        {0x96u, 0x80u},
-                       {0x97u, 0x02u},
                        {0x98u, 0x01u},
-                       {0x99u, 0x03u},
-                       {0x9Bu, 0x44u},
-                       {0x9Du, 0x44u},
-                       {0x9Eu, 0x54u},
-                       {0xA1u, 0x35u},
-                       {0xA3u, 0x48u},
+                       {0x99u, 0x10u},
+                       {0x9Bu, 0x04u},
+                       {0x9Du, 0x46u},
+                       {0x9Eu, 0x50u},
+                       {0x9Fu, 0x40u},
+                       {0xA0u, 0x04u},
+                       {0xA1u, 0x06u},
+                       {0xA3u, 0x10u},
                        {0xA4u, 0x38u},
-                       {0xA5u, 0x02u},
+                       {0xA6u, 0x80u},
                        {0xA7u, 0x80u},
-                       {0xA9u, 0x04u},
-                       {0xABu, 0x40u},
-                       {0xADu, 0x10u},
-                       {0xB7u, 0x40u},
-                       {0xC0u, 0x1Fu},
+                       {0xA8u, 0x20u},
+                       {0xAAu, 0x02u},
+                       {0xAFu, 0x10u},
+                       {0xC0u, 0x8Fu},
                        {0xC2u, 0xEEu},
                        {0xC4u, 0x8Fu},
                        {0xCAu, 0x4Fu},
                        {0xCCu, 0x0Fu},
                        {0xCEu, 0x0Fu},
-                       {0xD0u, 0x0Fu},
-                       {0xD2u, 0x08u},
-                       {0xD8u, 0x01u},
+                       {0xD0u, 0x0Bu},
+                       {0xD2u, 0x0Cu},
+                       {0xD8u, 0x02u},
                        {0xE4u, 0x22u},
-                       {0x01u, 0x71u},
-                       {0x03u, 0x82u},
-                       {0x05u, 0xA4u},
-                       {0x07u, 0x40u},
-                       {0x09u, 0x91u},
-                       {0x0Bu, 0x4Eu},
+                       {0x01u, 0x6Cu},
+                       {0x05u, 0x91u},
+                       {0x07u, 0x4Eu},
                        {0x0Cu, 0x01u},
                        {0x0Du, 0x2Cu},
                        {0x0Fu, 0x40u},
                        {0x10u, 0x02u},
+                       {0x11u, 0x71u},
+                       {0x13u, 0x82u},
                        {0x15u, 0xC0u},
                        {0x17u, 0x2Fu},
+                       {0x19u, 0xA4u},
+                       {0x1Bu, 0x40u},
                        {0x1Du, 0x6Cu},
-                       {0x21u, 0x6Cu},
+                       {0x21u, 0x08u},
+                       {0x23u, 0x10u},
                        {0x25u, 0x64u},
                        {0x27u, 0x08u},
                        {0x29u, 0x40u},
                        {0x2Bu, 0x2Cu},
-                       {0x2Du, 0x08u},
-                       {0x2Fu, 0x10u},
+                       {0x30u, 0x01u},
                        {0x31u, 0x0Fu},
-                       {0x32u, 0x02u},
                        {0x33u, 0xC0u},
-                       {0x34u, 0x01u},
+                       {0x34u, 0x02u},
                        {0x35u, 0x31u},
                        {0x3Bu, 0x38u},
-                       {0x3Eu, 0x04u},
+                       {0x3Eu, 0x10u},
                        {0x56u, 0x08u},
                        {0x58u, 0x04u},
                        {0x59u, 0x04u},
@@ -1730,9 +1735,12 @@ void cyfitter_cfg(void)
                        {0x5Cu, 0x09u},
                        {0x5Du, 0x90u},
                        {0x5Fu, 0x01u},
+                       {0x80u, 0x90u},
                        {0x81u, 0x11u},
+                       {0x82u, 0x49u},
+                       {0x84u, 0x02u},
                        {0x85u, 0xC4u},
-                       {0x86u, 0x0Cu},
+                       {0x86u, 0x91u},
                        {0x87u, 0x02u},
                        {0x88u, 0x01u},
                        {0x8Au, 0x02u},
@@ -1741,20 +1749,17 @@ void cyfitter_cfg(void)
                        {0x8Fu, 0x11u},
                        {0x91u, 0x0Cu},
                        {0x92u, 0x60u},
-                       {0x94u, 0x02u},
                        {0x95u, 0x11u},
-                       {0x96u, 0x91u},
+                       {0x96u, 0x0Cu},
                        {0x98u, 0x92u},
                        {0x99u, 0x11u},
                        {0x9Au, 0x25u},
-                       {0x9Du, 0x02u},
                        {0x9Eu, 0x10u},
-                       {0x9Fu, 0x64u},
                        {0xA2u, 0x80u},
                        {0xA3u, 0x01u},
-                       {0xA8u, 0x90u},
+                       {0xA5u, 0x02u},
+                       {0xA7u, 0x64u},
                        {0xA9u, 0x02u},
-                       {0xAAu, 0x49u},
                        {0xABu, 0xA8u},
                        {0xADu, 0x11u},
                        {0xAEu, 0x01u},
@@ -1775,48 +1780,45 @@ void cyfitter_cfg(void)
                        {0xDBu, 0x04u},
                        {0xDCu, 0x01u},
                        {0xDFu, 0x01u},
-                       {0x01u, 0x28u},
+                       {0x00u, 0x02u},
+                       {0x01u, 0x24u},
                        {0x02u, 0x02u},
-                       {0x03u, 0x10u},
                        {0x07u, 0x01u},
                        {0x08u, 0x40u},
                        {0x09u, 0x08u},
-                       {0x0Au, 0x44u},
-                       {0x0Bu, 0x80u},
+                       {0x0Au, 0x50u},
+                       {0x0Bu, 0x88u},
                        {0x0Cu, 0x02u},
                        {0x10u, 0x80u},
                        {0x12u, 0x01u},
-                       {0x13u, 0x20u},
-                       {0x19u, 0x28u},
-                       {0x1Au, 0x40u},
-                       {0x1Cu, 0x08u},
-                       {0x1Eu, 0x20u},
+                       {0x19u, 0x20u},
+                       {0x1Au, 0x50u},
+                       {0x1Eu, 0x80u},
+                       {0x1Fu, 0x10u},
                        {0x21u, 0x51u},
                        {0x22u, 0x09u},
                        {0x23u, 0x02u},
-                       {0x24u, 0x64u},
-                       {0x25u, 0x35u},
-                       {0x27u, 0x44u},
-                       {0x28u, 0x10u},
-                       {0x29u, 0x40u},
+                       {0x24u, 0x24u},
+                       {0x25u, 0x06u},
+                       {0x26u, 0x01u},
+                       {0x27u, 0x14u},
+                       {0x29u, 0x50u},
                        {0x2Au, 0x04u},
-                       {0x2Bu, 0x88u},
+                       {0x2Bu, 0x80u},
                        {0x2Cu, 0x28u},
-                       {0x2Du, 0x01u},
-                       {0x2Fu, 0x01u},
+                       {0x2Du, 0x02u},
+                       {0x2Eu, 0x02u},
                        {0x30u, 0x28u},
                        {0x32u, 0x01u},
-                       {0x33u, 0x40u},
                        {0x35u, 0x40u},
-                       {0x37u, 0x04u},
+                       {0x36u, 0x01u},
+                       {0x37u, 0x14u},
                        {0x38u, 0x04u},
                        {0x39u, 0x61u},
-                       {0x3Au, 0x82u},
-                       {0x3Du, 0x4Au},
-                       {0x3Eu, 0x20u},
-                       {0x42u, 0x20u},
-                       {0x43u, 0x08u},
-                       {0x58u, 0x10u},
+                       {0x3Au, 0x80u},
+                       {0x3Cu, 0x08u},
+                       {0x3Du, 0x41u},
+                       {0x58u, 0x20u},
                        {0x59u, 0x04u},
                        {0x5Au, 0x80u},
                        {0x5Bu, 0x02u},
@@ -1824,150 +1826,156 @@ void cyfitter_cfg(void)
                        {0x62u, 0x40u},
                        {0x63u, 0x40u},
                        {0x64u, 0x01u},
-                       {0x81u, 0x01u},
                        {0x83u, 0x04u},
                        {0x87u, 0x40u},
+                       {0x89u, 0x10u},
+                       {0x8Au, 0x40u},
                        {0x8Cu, 0x80u},
-                       {0x92u, 0x04u},
-                       {0x94u, 0x20u},
+                       {0x8Du, 0x02u},
+                       {0x8Eu, 0x04u},
+                       {0x90u, 0x80u},
+                       {0x91u, 0x04u},
+                       {0x93u, 0x08u},
+                       {0x94u, 0x02u},
                        {0x95u, 0x02u},
                        {0x97u, 0x80u},
                        {0x98u, 0x40u},
-                       {0x99u, 0x02u},
+                       {0x99u, 0x10u},
                        {0x9Au, 0x01u},
-                       {0x9Bu, 0x21u},
-                       {0x9Du, 0x60u},
-                       {0x9Eu, 0x96u},
+                       {0x9Bu, 0x01u},
+                       {0x9Du, 0x62u},
+                       {0x9Eu, 0x90u},
                        {0x9Fu, 0x54u},
-                       {0xA0u, 0x82u},
-                       {0xA1u, 0x08u},
+                       {0xA0u, 0x87u},
                        {0xA2u, 0x02u},
-                       {0xA3u, 0x08u},
-                       {0xA4u, 0x3Cu},
-                       {0xA5u, 0x02u},
-                       {0xA6u, 0x18u},
-                       {0xA7u, 0x80u},
+                       {0xA3u, 0x10u},
+                       {0xA4u, 0x38u},
+                       {0xA5u, 0x0Au},
+                       {0xA6u, 0x88u},
+                       {0xAAu, 0x40u},
                        {0xB3u, 0x11u},
+                       {0xB4u, 0x10u},
                        {0xB6u, 0x10u},
-                       {0xC0u, 0x87u},
+                       {0xC0u, 0x8Fu},
                        {0xC2u, 0x1Fu},
-                       {0xC4u, 0x0Bu},
-                       {0xCAu, 0xFDu},
-                       {0xCCu, 0x5Fu},
-                       {0xCEu, 0xFFu},
+                       {0xC4u, 0x09u},
+                       {0xCAu, 0xEFu},
+                       {0xCCu, 0xF7u},
+                       {0xCEu, 0xDFu},
                        {0xD6u, 0x1Fu},
                        {0xD8u, 0x19u},
                        {0xE0u, 0x11u},
-                       {0xE2u, 0x04u},
+                       {0xE2u, 0x20u},
+                       {0xE6u, 0x20u},
+                       {0xE8u, 0x04u},
                        {0xEAu, 0x20u},
-                       {0x80u, 0x10u},
                        {0x81u, 0x10u},
-                       {0x90u, 0x20u},
+                       {0x8Cu, 0x20u},
                        {0x95u, 0x04u},
-                       {0x9Eu, 0x08u},
+                       {0xA4u, 0x20u},
                        {0xA5u, 0x10u},
-                       {0xB1u, 0x08u},
-                       {0xB7u, 0x20u},
+                       {0xA9u, 0x04u},
+                       {0xB3u, 0x84u},
+                       {0xB4u, 0x81u},
+                       {0xB7u, 0xA0u},
+                       {0xE4u, 0x10u},
                        {0xE8u, 0x40u},
-                       {0xECu, 0x20u},
+                       {0xECu, 0x60u},
                        {0x85u, 0x04u},
                        {0x95u, 0x04u},
-                       {0xB6u, 0x08u},
-                       {0xE8u, 0x10u},
                        {0x07u, 0x08u},
                        {0x0Du, 0x80u},
                        {0x0Eu, 0x40u},
-                       {0x13u, 0x20u},
+                       {0x11u, 0x08u},
+                       {0x12u, 0x02u},
                        {0x16u, 0x80u},
-                       {0x17u, 0x40u},
-                       {0x32u, 0x01u},
-                       {0x34u, 0x01u},
-                       {0x36u, 0x80u},
+                       {0x17u, 0x20u},
+                       {0x30u, 0x10u},
+                       {0x33u, 0x02u},
+                       {0x36u, 0x21u},
                        {0x39u, 0x02u},
                        {0x3Au, 0x80u},
-                       {0x3Cu, 0x08u},
                        {0x3Du, 0x40u},
+                       {0x3Fu, 0x08u},
                        {0x42u, 0x08u},
-                       {0x50u, 0x20u},
-                       {0x81u, 0x40u},
+                       {0x52u, 0x10u},
+                       {0x6Du, 0x08u},
+                       {0x6Fu, 0x02u},
+                       {0x77u, 0x10u},
+                       {0x7Eu, 0x02u},
                        {0x83u, 0x08u},
                        {0x85u, 0x01u},
                        {0x8Du, 0x80u},
                        {0xC0u, 0x80u},
                        {0xC2u, 0xA0u},
-                       {0xC4u, 0xE0u},
-                       {0xCCu, 0xE0u},
+                       {0xC4u, 0xF0u},
+                       {0xCCu, 0xF0u},
                        {0xCEu, 0xF0u},
                        {0xD0u, 0x10u},
                        {0xD4u, 0x20u},
                        {0xE0u, 0x20u},
-                       {0xE6u, 0x60u},
+                       {0xE6u, 0x40u},
                        {0x00u, 0x10u},
                        {0x0Au, 0x01u},
-                       {0x31u, 0x08u},
+                       {0x30u, 0x08u},
                        {0x33u, 0x10u},
-                       {0x37u, 0x48u},
-                       {0x39u, 0x10u},
+                       {0x34u, 0x01u},
+                       {0x37u, 0x20u},
+                       {0x3Au, 0x80u},
                        {0x58u, 0x40u},
-                       {0x5Du, 0x02u},
-                       {0x6Bu, 0x30u},
-                       {0x81u, 0x01u},
-                       {0x85u, 0x10u},
+                       {0x63u, 0x40u},
+                       {0x84u, 0x40u},
+                       {0x88u, 0x08u},
                        {0x92u, 0x40u},
-                       {0x96u, 0x02u},
-                       {0x9Bu, 0x60u},
-                       {0x9Cu, 0x01u},
-                       {0x9Eu, 0x08u},
-                       {0xA4u, 0x24u},
-                       {0xA6u, 0x80u},
+                       {0x9Bu, 0x30u},
+                       {0x9Cu, 0x10u},
+                       {0x9Eu, 0x18u},
+                       {0xA6u, 0x21u},
+                       {0xA7u, 0x04u},
+                       {0xB5u, 0x40u},
                        {0xC0u, 0x40u},
                        {0xC2u, 0x40u},
                        {0xCCu, 0xF0u},
                        {0xCEu, 0x10u},
                        {0xD4u, 0x80u},
-                       {0xD6u, 0x80u},
-                       {0xE2u, 0x20u},
+                       {0xD8u, 0x40u},
                        {0xE6u, 0x10u},
-                       {0x12u, 0x80u},
+                       {0x10u, 0x10u},
                        {0x30u, 0x80u},
-                       {0x52u, 0x10u},
-                       {0x59u, 0x01u},
-                       {0x88u, 0x20u},
+                       {0x53u, 0x04u},
+                       {0x5Au, 0x02u},
+                       {0x86u, 0x80u},
+                       {0x8Au, 0x10u},
                        {0x90u, 0x10u},
-                       {0x96u, 0x02u},
-                       {0x99u, 0x01u},
-                       {0x9Cu, 0x01u},
-                       {0x9Du, 0x02u},
-                       {0x9Eu, 0x08u},
-                       {0x9Fu, 0x08u},
-                       {0xA4u, 0x24u},
-                       {0xA5u, 0x08u},
-                       {0xA6u, 0x80u},
+                       {0x93u, 0x08u},
+                       {0x97u, 0x40u},
+                       {0x9Cu, 0x11u},
+                       {0x9Eu, 0x98u},
+                       {0xA6u, 0x21u},
+                       {0xA7u, 0x04u},
                        {0xAEu, 0x01u},
-                       {0xB0u, 0x40u},
+                       {0xAFu, 0x04u},
                        {0xB6u, 0x40u},
                        {0xC4u, 0x10u},
                        {0xCCu, 0x10u},
                        {0xD4u, 0x20u},
                        {0xD6u, 0x40u},
+                       {0xE2u, 0x40u},
                        {0xE8u, 0x10u},
+                       {0xEEu, 0x10u},
                        {0x84u, 0x80u},
-                       {0x85u, 0x0Au},
-                       {0x86u, 0x01u},
-                       {0x88u, 0x04u},
-                       {0x8Fu, 0x08u},
+                       {0x8Fu, 0x04u},
                        {0x90u, 0x10u},
-                       {0x96u, 0x02u},
-                       {0x9Cu, 0x01u},
-                       {0x9Du, 0x02u},
+                       {0x97u, 0x40u},
                        {0x9Eu, 0x08u},
-                       {0x9Fu, 0x08u},
-                       {0xA4u, 0x84u},
-                       {0xA5u, 0x08u},
-                       {0xAEu, 0x10u},
-                       {0xE2u, 0x50u},
-                       {0xE6u, 0x50u},
+                       {0xA4u, 0x80u},
+                       {0xA6u, 0x21u},
+                       {0xA7u, 0x04u},
+                       {0xACu, 0x01u},
+                       {0xAEu, 0x01u},
+                       {0xE2u, 0x10u},
                        {0xEAu, 0x40u},
+                       {0xEEu, 0x40u},
                        {0x04u, 0x10u},
                        {0x05u, 0x01u},
                        {0x08u, 0x04u},
@@ -1977,98 +1985,101 @@ void cyfitter_cfg(void)
                        {0x63u, 0x40u},
                        {0x67u, 0x08u},
                        {0x70u, 0x08u},
-                       {0x81u, 0x01u},
+                       {0x81u, 0x03u},
                        {0x84u, 0x40u},
-                       {0x8Cu, 0x28u},
+                       {0x8Cu, 0x08u},
                        {0xC0u, 0x05u},
                        {0xC2u, 0x0Au},
                        {0xC4u, 0x08u},
                        {0xD4u, 0x01u},
                        {0xD8u, 0x03u},
                        {0xDCu, 0x01u},
-                       {0xE0u, 0x02u},
                        {0xE4u, 0x08u},
-                       {0x01u, 0x42u},
+                       {0x01u, 0x40u},
+                       {0x02u, 0x20u},
                        {0x08u, 0x80u},
-                       {0x0Au, 0x80u},
+                       {0x09u, 0x01u},
                        {0x56u, 0x80u},
                        {0x5Au, 0x40u},
-                       {0x5Fu, 0x02u},
-                       {0x60u, 0x20u},
-                       {0x87u, 0x04u},
+                       {0x5Du, 0x02u},
+                       {0x63u, 0x02u},
+                       {0x88u, 0x01u},
                        {0x8Bu, 0x40u},
                        {0x90u, 0x10u},
-                       {0x96u, 0x80u},
                        {0x97u, 0x40u},
-                       {0x98u, 0x24u},
-                       {0xAAu, 0x40u},
+                       {0x98u, 0x04u},
+                       {0x99u, 0x02u},
+                       {0xA5u, 0x01u},
+                       {0xA9u, 0x01u},
                        {0xAFu, 0x04u},
                        {0xB0u, 0x10u},
                        {0xB7u, 0x01u},
                        {0xC0u, 0x0Au},
                        {0xC2u, 0x0Au},
                        {0xD4u, 0x03u},
-                       {0xD6u, 0x01u},
-                       {0xD8u, 0x02u},
+                       {0xD6u, 0x03u},
                        {0xE0u, 0x04u},
+                       {0xE6u, 0x04u},
                        {0xEAu, 0x06u},
                        {0x57u, 0x08u},
-                       {0x87u, 0x08u},
+                       {0x82u, 0x20u},
+                       {0x87u, 0x0Du},
                        {0x88u, 0x80u},
-                       {0x8Fu, 0x02u},
+                       {0x8Eu, 0x80u},
                        {0x90u, 0x10u},
-                       {0x97u, 0x08u},
                        {0x98u, 0x80u},
-                       {0x99u, 0x02u},
-                       {0x9Fu, 0x02u},
+                       {0x9Cu, 0x01u},
+                       {0x9Eu, 0x80u},
+                       {0xA2u, 0x20u},
+                       {0xA7u, 0x01u},
                        {0xAAu, 0x40u},
                        {0xACu, 0x04u},
                        {0xB5u, 0x40u},
-                       {0xB6u, 0x80u},
                        {0xD4u, 0x02u},
-                       {0xE0u, 0x08u},
                        {0xE2u, 0x04u},
+                       {0xE4u, 0x08u},
                        {0xEAu, 0x02u},
-                       {0xECu, 0x08u},
-                       {0x09u, 0x02u},
-                       {0x0Bu, 0x08u},
-                       {0x0Eu, 0x41u},
-                       {0x85u, 0x02u},
+                       {0x08u, 0x01u},
+                       {0x0Bu, 0x04u},
+                       {0x0Du, 0x02u},
+                       {0x0Eu, 0x01u},
                        {0x86u, 0x01u},
-                       {0x8Eu, 0x40u},
-                       {0x97u, 0x08u},
+                       {0x97u, 0x04u},
+                       {0x9Cu, 0x01u},
+                       {0xA5u, 0x02u},
+                       {0xADu, 0x02u},
                        {0xB4u, 0x10u},
-                       {0xB5u, 0x02u},
                        {0xC2u, 0x0Fu},
-                       {0xE6u, 0x02u},
-                       {0xEAu, 0x0Au},
+                       {0xEAu, 0x08u},
                        {0x86u, 0x08u},
+                       {0x8Au, 0x22u},
                        {0x8Cu, 0x10u},
                        {0x90u, 0x10u},
+                       {0x97u, 0x40u},
                        {0x98u, 0x02u},
-                       {0x9Cu, 0x01u},
                        {0x9Eu, 0x08u},
+                       {0xA6u, 0x21u},
                        {0xB0u, 0x02u},
                        {0xE6u, 0x40u},
                        {0x00u, 0x80u},
                        {0x52u, 0x02u},
                        {0x5Cu, 0x02u},
-                       {0x84u, 0x01u},
+                       {0x82u, 0x01u},
                        {0x88u, 0x40u},
                        {0x98u, 0x02u},
-                       {0x9Cu, 0x01u},
                        {0xA2u, 0x02u},
-                       {0xAEu, 0x02u},
+                       {0xA6u, 0x01u},
+                       {0xAFu, 0x40u},
                        {0xC0u, 0x40u},
                        {0xD4u, 0x80u},
                        {0xD6u, 0x80u},
-                       {0xE2u, 0x40u},
-                       {0xEAu, 0x40u},
+                       {0xE6u, 0x80u},
+                       {0xEEu, 0x40u},
                        {0x10u, 0x03u},
                        {0x11u, 0x01u},
                        {0x1Au, 0x03u},
                        {0x1Bu, 0x01u},
-                       {0x00u, 0xFDu},
+                       {0x00u, 0xFFu},
                        {0x01u, 0xBFu},
                        {0x02u, 0x2Au},
                        {0x10u, 0x95u},
@@ -2088,7 +2099,7 @@ void cyfitter_cfg(void)
                        uint16 size;
                } CYPACKED_ATTR cfg_memcpy_t;
 
-               static const cfg_memset_t CYCODE cfg_memset_list [] = {
+               static const cfg_memset_t CYCODE cfg_memset_list[] = {
                        /* address, size */
                        {(void CYFAR *)(CYREG_TMR0_CFG0), 12u},
                        {(void CYFAR *)(CYREG_PRT5_DR), 16u},
@@ -2101,12 +2112,12 @@ void cyfitter_cfg(void)
 
                /* UDB_1_0_0_CONFIG Address: CYDEV_UCFG_B1_P2_U0_BASE Size (bytes): 128 */
                static const uint8 CYCODE BS_UDB_1_0_0_CONFIG_VAL[] = {
-                       0xC0u, 0x01u, 0x02u, 0x00u, 0x00u, 0x04u, 0x60u, 0x00u, 0x00u, 0x40u, 0xFFu, 0x00u, 0x00u, 0x01u, 0x9Fu, 0x00u, 
-                       0x1Fu, 0x10u, 0x20u, 0x00u, 0x80u, 0xA2u, 0x00u, 0x08u, 0x7Fu, 0x01u, 0x80u, 0x00u, 0x00u, 0x87u, 0x00u, 0x18u, 
-                       0xC0u, 0x01u, 0x01u, 0x00u, 0xC0u, 0x40u, 0x04u, 0x00u, 0xC0u, 0x88u, 0x08u, 0x21u, 0x90u, 0x01u, 0x40u, 0x00u, 
-                       0x00u, 0x80u, 0xFFu, 0x3Fu, 0x00u, 0x40u, 0x00u, 0x08u, 0x00u, 0x28u, 0x00u, 0x00u, 0x00u, 0x00u, 0x04u, 0x45u, 
-                       0x32u, 0x04u, 0x10u, 0x00u, 0x05u, 0xCEu, 0xFDu, 0xBCu, 0x3Fu, 0xFFu, 0xFFu, 0xFFu, 0x22u, 0x00u, 0xF0u, 0x08u, 
-                       0x04u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x2Cu, 0x04u, 0x04u, 0x04u, 0x04u, 0x00u, 0x00u, 0x00u, 0x01u, 
+                       0xC0u, 0x01u, 0x02u, 0x00u, 0x00u, 0x04u, 0xFFu, 0x00u, 0x7Fu, 0x01u, 0x80u, 0x00u, 0x00u, 0x01u, 0x9Fu, 0x00u, 
+                       0x1Fu, 0x87u, 0x20u, 0x18u, 0x80u, 0xA2u, 0x00u, 0x08u, 0x00u, 0x40u, 0x60u, 0x00u, 0x00u, 0x01u, 0x00u, 0x00u, 
+                       0xC0u, 0x10u, 0x01u, 0x00u, 0xC0u, 0x40u, 0x04u, 0x00u, 0xC0u, 0x88u, 0x08u, 0x21u, 0x90u, 0x01u, 0x40u, 0x00u, 
+                       0x00u, 0x80u, 0xFFu, 0x40u, 0x00u, 0x3Fu, 0x00u, 0x08u, 0x00u, 0x28u, 0x00u, 0x00u, 0x00u, 0x00u, 0x04u, 0x51u, 
+                       0x63u, 0x04u, 0x10u, 0x00u, 0x05u, 0xCEu, 0xFDu, 0xB0u, 0x2Fu, 0xFFu, 0xFFu, 0xFFu, 0x22u, 0x00u, 0xF0u, 0x08u, 
+                       0x04u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x28u, 0x04u, 0x04u, 0x04u, 0x04u, 0x00u, 0x00u, 0x00u, 0x01u, 
                        0x00u, 0x00u, 0xC0u, 0x00u, 0x40u, 0x01u, 0x10u, 0x11u, 0xC0u, 0x01u, 0x00u, 0x11u, 0x40u, 0x01u, 0x40u, 0x01u, 
                        0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u};
 

diff --git a/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.h b/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.h
index 17e8d5b73581f475b74994a715a85196fc782f2f..b0406f894b9c38b2db618187b745fe6a5b5d0899 100755 (executable)
--- a/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.h
+++ b/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.h
@@ -1,14 +1,14 @@
 /*******************************************************************************
 * File Name: cyfitter_cfg.h
 * 
-* PSoC Creator  4.0 Update 1
+* PSoC Creator  4.1
 *
 * Description:
-* This file provides basic startup and mux configration settings
+* This file provides basic startup and mux configuration settings
 * This file is automatically generated by PSoC Creator.
 *
 ********************************************************************************
-* Copyright (c) 2007-2016 Cypress Semiconductor.  All rights reserved.
+* Copyright (c) 2007-2017 Cypress Semiconductor.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions, 
 * disclaimers, and limitations in the end user license agreement accompanying 
 * the software package with which this file was provided.

diff --git a/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfittergnu.inc b/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfittergnu.inc
index 876e1fb36987453a182d3717d3ebb2e441f6f5d6..b997c4616514470cdb42b344eb740e47fff52e0d 100755 (executable)
--- a/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfittergnu.inc
+++ b/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfittergnu.inc
@@ -1,8 +1,52 @@
+/*******************************************************************************
+* File Name: cyfittergnu.inc
+* 
+* PSoC Creator  4.1
+*
+* Description:
+* 
+* This file is automatically generated by PSoC Creator.
+*
+********************************************************************************
+* Copyright (c) 2007-2017 Cypress Semiconductor.  All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions, 
+* disclaimers, and limitations in the end user license agreement accompanying 
+* the software package with which this file was provided.
+********************************************************************************/
+
 .ifndef INCLUDED_CYFITTERGNU_INC
 .set INCLUDED_CYFITTERGNU_INC, 1
 .include "cydevicegnu.inc"
 .include "cydevicegnu_trm.inc"
 
+/* Debug_Timer_Interrupt */
+.set Debug_Timer_Interrupt__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
+.set Debug_Timer_Interrupt__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
+.set Debug_Timer_Interrupt__INTC_MASK, 0x01
+.set Debug_Timer_Interrupt__INTC_NUMBER, 0
+.set Debug_Timer_Interrupt__INTC_PRIOR_NUM, 7
+.set Debug_Timer_Interrupt__INTC_PRIOR_REG, CYREG_NVIC_PRI_0
+.set Debug_Timer_Interrupt__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
+.set Debug_Timer_Interrupt__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
+
+/* Debug_Timer_TimerHW */
+.set Debug_Timer_TimerHW__CAP0, CYREG_TMR0_CAP0
+.set Debug_Timer_TimerHW__CAP1, CYREG_TMR0_CAP1
+.set Debug_Timer_TimerHW__CFG0, CYREG_TMR0_CFG0
+.set Debug_Timer_TimerHW__CFG1, CYREG_TMR0_CFG1
+.set Debug_Timer_TimerHW__CFG2, CYREG_TMR0_CFG2
+.set Debug_Timer_TimerHW__CNT_CMP0, CYREG_TMR0_CNT_CMP0
+.set Debug_Timer_TimerHW__CNT_CMP1, CYREG_TMR0_CNT_CMP1
+.set Debug_Timer_TimerHW__PER0, CYREG_TMR0_PER0
+.set Debug_Timer_TimerHW__PER1, CYREG_TMR0_PER1
+.set Debug_Timer_TimerHW__PM_ACT_CFG, CYREG_PM_ACT_CFG3
+.set Debug_Timer_TimerHW__PM_ACT_MSK, 0x01
+.set Debug_Timer_TimerHW__PM_STBY_CFG, CYREG_PM_STBY_CFG3
+.set Debug_Timer_TimerHW__PM_STBY_MSK, 0x01
+.set Debug_Timer_TimerHW__RT0, CYREG_TMR0_RT0
+.set Debug_Timer_TimerHW__RT1, CYREG_TMR0_RT1
+.set Debug_Timer_TimerHW__SR0, CYREG_TMR0_SR0
+
 /* LED1 */
 .set LED1__0__INTTYPE, CYREG_PICU12_INTTYPE0
 .set LED1__0__MASK, 0x01
@@ -41,2036 +85,571 @@
 .set LED1__SIO_REG_HIFREQ, CYREG_PRT12_SIO_REG_HIFREQ
 .set LED1__SLW, CYREG_PRT12_SLW
 
-/* SD_CS */
-.set SD_CS__0__INTTYPE, CYREG_PICU3_INTTYPE5
-.set SD_CS__0__MASK, 0x20
-.set SD_CS__0__PC, CYREG_PRT3_PC5
-.set SD_CS__0__PORT, 3
-.set SD_CS__0__SHIFT, 5
-.set SD_CS__AG, CYREG_PRT3_AG
-.set SD_CS__AMUX, CYREG_PRT3_AMUX
-.set SD_CS__BIE, CYREG_PRT3_BIE
-.set SD_CS__BIT_MASK, CYREG_PRT3_BIT_MASK
-.set SD_CS__BYP, CYREG_PRT3_BYP
-.set SD_CS__CTL, CYREG_PRT3_CTL
-.set SD_CS__DM0, CYREG_PRT3_DM0
-.set SD_CS__DM1, CYREG_PRT3_DM1
-.set SD_CS__DM2, CYREG_PRT3_DM2
-.set SD_CS__DR, CYREG_PRT3_DR
-.set SD_CS__INP_DIS, CYREG_PRT3_INP_DIS
-.set SD_CS__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU3_BASE
-.set SD_CS__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG
-.set SD_CS__LCD_EN, CYREG_PRT3_LCD_EN
-.set SD_CS__MASK, 0x20
-.set SD_CS__PORT, 3
-.set SD_CS__PRT, CYREG_PRT3_PRT
-.set SD_CS__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL
-.set SD_CS__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN
-.set SD_CS__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0
-.set SD_CS__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1
-.set SD_CS__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0
-.set SD_CS__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1
-.set SD_CS__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT
-.set SD_CS__PS, CYREG_PRT3_PS
-.set SD_CS__SHIFT, 5
-.set SD_CS__SLW, CYREG_PRT3_SLW
-
-/* USBFS_arb_int */
-.set USBFS_arb_int__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
-.set USBFS_arb_int__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
-.set USBFS_arb_int__INTC_MASK, 0x400000
-.set USBFS_arb_int__INTC_NUMBER, 22
-.set USBFS_arb_int__INTC_PRIOR_NUM, 6
-.set USBFS_arb_int__INTC_PRIOR_REG, CYREG_NVIC_PRI_22
-.set USBFS_arb_int__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
-.set USBFS_arb_int__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
-
-/* USBFS_bus_reset */
-.set USBFS_bus_reset__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
-.set USBFS_bus_reset__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
-.set USBFS_bus_reset__INTC_MASK, 0x800000
-.set USBFS_bus_reset__INTC_NUMBER, 23
-.set USBFS_bus_reset__INTC_PRIOR_NUM, 7
-.set USBFS_bus_reset__INTC_PRIOR_REG, CYREG_NVIC_PRI_23
-.set USBFS_bus_reset__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
-.set USBFS_bus_reset__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
-
-/* USBFS_Dm */
-.set USBFS_Dm__0__INTTYPE, CYREG_PICU15_INTTYPE7
-.set USBFS_Dm__0__MASK, 0x80
-.set USBFS_Dm__0__PC, CYREG_IO_PC_PRT15_7_6_PC1
-.set USBFS_Dm__0__PORT, 15
-.set USBFS_Dm__0__SHIFT, 7
-.set USBFS_Dm__AG, CYREG_PRT15_AG
-.set USBFS_Dm__AMUX, CYREG_PRT15_AMUX
-.set USBFS_Dm__BIE, CYREG_PRT15_BIE
-.set USBFS_Dm__BIT_MASK, CYREG_PRT15_BIT_MASK
-.set USBFS_Dm__BYP, CYREG_PRT15_BYP
-.set USBFS_Dm__CTL, CYREG_PRT15_CTL
-.set USBFS_Dm__DM0, CYREG_PRT15_DM0
-.set USBFS_Dm__DM1, CYREG_PRT15_DM1
-.set USBFS_Dm__DM2, CYREG_PRT15_DM2
-.set USBFS_Dm__DR, CYREG_PRT15_DR
-.set USBFS_Dm__INP_DIS, CYREG_PRT15_INP_DIS
-.set USBFS_Dm__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU15_BASE
-.set USBFS_Dm__LCD_COM_SEG, CYREG_PRT15_LCD_COM_SEG
-.set USBFS_Dm__LCD_EN, CYREG_PRT15_LCD_EN
-.set USBFS_Dm__MASK, 0x80
-.set USBFS_Dm__PORT, 15
-.set USBFS_Dm__PRT, CYREG_PRT15_PRT
-.set USBFS_Dm__PRTDSI__CAPS_SEL, CYREG_PRT15_CAPS_SEL
-.set USBFS_Dm__PRTDSI__DBL_SYNC_IN, CYREG_PRT15_DBL_SYNC_IN
-.set USBFS_Dm__PRTDSI__OE_SEL0, CYREG_PRT15_OE_SEL0
-.set USBFS_Dm__PRTDSI__OE_SEL1, CYREG_PRT15_OE_SEL1
-.set USBFS_Dm__PRTDSI__OUT_SEL0, CYREG_PRT15_OUT_SEL0
-.set USBFS_Dm__PRTDSI__OUT_SEL1, CYREG_PRT15_OUT_SEL1
-.set USBFS_Dm__PRTDSI__SYNC_OUT, CYREG_PRT15_SYNC_OUT
-.set USBFS_Dm__PS, CYREG_PRT15_PS
-.set USBFS_Dm__SHIFT, 7
-.set USBFS_Dm__SLW, CYREG_PRT15_SLW
-
-/* USBFS_Dp */
-.set USBFS_Dp__0__INTTYPE, CYREG_PICU15_INTTYPE6
-.set USBFS_Dp__0__MASK, 0x40
-.set USBFS_Dp__0__PC, CYREG_IO_PC_PRT15_7_6_PC0
-.set USBFS_Dp__0__PORT, 15
-.set USBFS_Dp__0__SHIFT, 6
-.set USBFS_Dp__AG, CYREG_PRT15_AG
-.set USBFS_Dp__AMUX, CYREG_PRT15_AMUX
-.set USBFS_Dp__BIE, CYREG_PRT15_BIE
-.set USBFS_Dp__BIT_MASK, CYREG_PRT15_BIT_MASK
-.set USBFS_Dp__BYP, CYREG_PRT15_BYP
-.set USBFS_Dp__CTL, CYREG_PRT15_CTL
-.set USBFS_Dp__DM0, CYREG_PRT15_DM0
-.set USBFS_Dp__DM1, CYREG_PRT15_DM1
-.set USBFS_Dp__DM2, CYREG_PRT15_DM2
-.set USBFS_Dp__DR, CYREG_PRT15_DR
-.set USBFS_Dp__INP_DIS, CYREG_PRT15_INP_DIS
-.set USBFS_Dp__INTSTAT, CYREG_PICU15_INTSTAT
-.set USBFS_Dp__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU15_BASE
-.set USBFS_Dp__LCD_COM_SEG, CYREG_PRT15_LCD_COM_SEG
-.set USBFS_Dp__LCD_EN, CYREG_PRT15_LCD_EN
-.set USBFS_Dp__MASK, 0x40
-.set USBFS_Dp__PORT, 15
-.set USBFS_Dp__PRT, CYREG_PRT15_PRT
-.set USBFS_Dp__PRTDSI__CAPS_SEL, CYREG_PRT15_CAPS_SEL
-.set USBFS_Dp__PRTDSI__DBL_SYNC_IN, CYREG_PRT15_DBL_SYNC_IN
-.set USBFS_Dp__PRTDSI__OE_SEL0, CYREG_PRT15_OE_SEL0
-.set USBFS_Dp__PRTDSI__OE_SEL1, CYREG_PRT15_OE_SEL1
-.set USBFS_Dp__PRTDSI__OUT_SEL0, CYREG_PRT15_OUT_SEL0
-.set USBFS_Dp__PRTDSI__OUT_SEL1, CYREG_PRT15_OUT_SEL1
-.set USBFS_Dp__PRTDSI__SYNC_OUT, CYREG_PRT15_SYNC_OUT
-.set USBFS_Dp__PS, CYREG_PRT15_PS
-.set USBFS_Dp__SHIFT, 6
-.set USBFS_Dp__SLW, CYREG_PRT15_SLW
-.set USBFS_Dp__SNAP, CYREG_PICU_15_SNAP_15
-
-/* USBFS_dp_int */
-.set USBFS_dp_int__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
-.set USBFS_dp_int__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
-.set USBFS_dp_int__INTC_MASK, 0x1000
-.set USBFS_dp_int__INTC_NUMBER, 12
-.set USBFS_dp_int__INTC_PRIOR_NUM, 7
-.set USBFS_dp_int__INTC_PRIOR_REG, CYREG_NVIC_PRI_12
-.set USBFS_dp_int__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
-.set USBFS_dp_int__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
+/* SCSI_CLK */
+.set SCSI_CLK__CFG0, CYREG_CLKDIST_DCFG1_CFG0
+.set SCSI_CLK__CFG1, CYREG_CLKDIST_DCFG1_CFG1
+.set SCSI_CLK__CFG2, CYREG_CLKDIST_DCFG1_CFG2
+.set SCSI_CLK__CFG2_SRC_SEL_MASK, 0x07
+.set SCSI_CLK__INDEX, 0x01
+.set SCSI_CLK__PM_ACT_CFG, CYREG_PM_ACT_CFG2
+.set SCSI_CLK__PM_ACT_MSK, 0x02
+.set SCSI_CLK__PM_STBY_CFG, CYREG_PM_STBY_CFG2
+.set SCSI_CLK__PM_STBY_MSK, 0x02
 
-/* USBFS_ep_0 */
-.set USBFS_ep_0__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
-.set USBFS_ep_0__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
-.set USBFS_ep_0__INTC_MASK, 0x1000000
-.set USBFS_ep_0__INTC_NUMBER, 24
-.set USBFS_ep_0__INTC_PRIOR_NUM, 7
-.set USBFS_ep_0__INTC_PRIOR_REG, CYREG_NVIC_PRI_24
-.set USBFS_ep_0__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
-.set USBFS_ep_0__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
+/* SCSI_CTL_PHASE */
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK, 0x01
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS, 0
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK, 0x02
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS, 1
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB02_03_ACTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB02_03_CTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB02_03_CTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB02_03_CTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB02_03_CTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB02_03_MSK
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB02_03_MSK
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB02_03_MSK
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB02_03_MSK
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK, 0x04
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS, 2
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB02_ACTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB02_CTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB02_ST_CTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB02_CTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB02_ST_CTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK, 0x07
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB02_MSK_ACTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB02_MSK_ACTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB02_MSK
 
-/* USBFS_ep_1 */
-.set USBFS_ep_1__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
-.set USBFS_ep_1__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
-.set USBFS_ep_1__INTC_MASK, 0x80
-.set USBFS_ep_1__INTC_NUMBER, 7
-.set USBFS_ep_1__INTC_PRIOR_NUM, 7
-.set USBFS_ep_1__INTC_PRIOR_REG, CYREG_NVIC_PRI_7
-.set USBFS_ep_1__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
-.set USBFS_ep_1__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
+/* SCSI_Filtered */
+.set SCSI_Filtered_sts_sts_reg__0__MASK, 0x01
+.set SCSI_Filtered_sts_sts_reg__0__POS, 0
+.set SCSI_Filtered_sts_sts_reg__1__MASK, 0x02
+.set SCSI_Filtered_sts_sts_reg__1__POS, 1
+.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB11_12_ACTL
+.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB11_12_ST
+.set SCSI_Filtered_sts_sts_reg__2__MASK, 0x04
+.set SCSI_Filtered_sts_sts_reg__2__POS, 2
+.set SCSI_Filtered_sts_sts_reg__3__MASK, 0x08
+.set SCSI_Filtered_sts_sts_reg__3__POS, 3
+.set SCSI_Filtered_sts_sts_reg__4__MASK, 0x10
+.set SCSI_Filtered_sts_sts_reg__4__POS, 4
+.set SCSI_Filtered_sts_sts_reg__MASK, 0x1F
+.set SCSI_Filtered_sts_sts_reg__MASK_REG, CYREG_B0_UDB11_MSK
+.set SCSI_Filtered_sts_sts_reg__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL
+.set SCSI_Filtered_sts_sts_reg__PER_ST_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL
+.set SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB11_ACTL
+.set SCSI_Filtered_sts_sts_reg__STATUS_CNT_REG, CYREG_B0_UDB11_ST_CTL
+.set SCSI_Filtered_sts_sts_reg__STATUS_CONTROL_REG, CYREG_B0_UDB11_ST_CTL
+.set SCSI_Filtered_sts_sts_reg__STATUS_REG, CYREG_B0_UDB11_ST
 
-/* USBFS_ep_2 */
-.set USBFS_ep_2__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
-.set USBFS_ep_2__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
-.set USBFS_ep_2__INTC_MASK, 0x100
-.set USBFS_ep_2__INTC_NUMBER, 8
-.set USBFS_ep_2__INTC_PRIOR_NUM, 7
-.set USBFS_ep_2__INTC_PRIOR_REG, CYREG_NVIC_PRI_8
-.set USBFS_ep_2__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
-.set USBFS_ep_2__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
+/* SCSI_Glitch_Ctl */
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK, 0x01
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS, 0
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB05_06_ACTL
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB05_06_CTL
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB05_06_CTL
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB05_06_CTL
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB05_06_CTL
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB05_06_MSK
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB05_06_MSK
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB05_06_MSK
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB05_06_MSK
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB05_ACTL
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB05_CTL
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB05_ST_CTL
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB05_CTL
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB05_ST_CTL
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK, 0x01
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB05_MSK_ACTL
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB05_MSK_ACTL
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB05_MSK
 
-/* USBFS_ep_3 */
-.set USBFS_ep_3__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
-.set USBFS_ep_3__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
-.set USBFS_ep_3__INTC_MASK, 0x200
-.set USBFS_ep_3__INTC_NUMBER, 9
-.set USBFS_ep_3__INTC_PRIOR_NUM, 7
-.set USBFS_ep_3__INTC_PRIOR_REG, CYREG_NVIC_PRI_9
-.set USBFS_ep_3__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
-.set USBFS_ep_3__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
-
-/* USBFS_ep_4 */
-.set USBFS_ep_4__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
-.set USBFS_ep_4__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
-.set USBFS_ep_4__INTC_MASK, 0x400
-.set USBFS_ep_4__INTC_NUMBER, 10
-.set USBFS_ep_4__INTC_PRIOR_NUM, 7
-.set USBFS_ep_4__INTC_PRIOR_REG, CYREG_NVIC_PRI_10
-.set USBFS_ep_4__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
-.set USBFS_ep_4__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
-
-/* USBFS_sof_int */
-.set USBFS_sof_int__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
-.set USBFS_sof_int__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
-.set USBFS_sof_int__INTC_MASK, 0x200000
-.set USBFS_sof_int__INTC_NUMBER, 21
-.set USBFS_sof_int__INTC_PRIOR_NUM, 7
-.set USBFS_sof_int__INTC_PRIOR_REG, CYREG_NVIC_PRI_21
-.set USBFS_sof_int__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
-.set USBFS_sof_int__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
-
-/* USBFS_USB */
-.set USBFS_USB__ARB_CFG, CYREG_USB_ARB_CFG
-.set USBFS_USB__ARB_EP1_CFG, CYREG_USB_ARB_EP1_CFG
-.set USBFS_USB__ARB_EP1_INT_EN, CYREG_USB_ARB_EP1_INT_EN
-.set USBFS_USB__ARB_EP1_SR, CYREG_USB_ARB_EP1_SR
-.set USBFS_USB__ARB_EP2_CFG, CYREG_USB_ARB_EP2_CFG
-.set USBFS_USB__ARB_EP2_INT_EN, CYREG_USB_ARB_EP2_INT_EN
-.set USBFS_USB__ARB_EP2_SR, CYREG_USB_ARB_EP2_SR
-.set USBFS_USB__ARB_EP3_CFG, CYREG_USB_ARB_EP3_CFG
-.set USBFS_USB__ARB_EP3_INT_EN, CYREG_USB_ARB_EP3_INT_EN
-.set USBFS_USB__ARB_EP3_SR, CYREG_USB_ARB_EP3_SR
-.set USBFS_USB__ARB_EP4_CFG, CYREG_USB_ARB_EP4_CFG
-.set USBFS_USB__ARB_EP4_INT_EN, CYREG_USB_ARB_EP4_INT_EN
-.set USBFS_USB__ARB_EP4_SR, CYREG_USB_ARB_EP4_SR
-.set USBFS_USB__ARB_EP5_CFG, CYREG_USB_ARB_EP5_CFG
-.set USBFS_USB__ARB_EP5_INT_EN, CYREG_USB_ARB_EP5_INT_EN
-.set USBFS_USB__ARB_EP5_SR, CYREG_USB_ARB_EP5_SR
-.set USBFS_USB__ARB_EP6_CFG, CYREG_USB_ARB_EP6_CFG
-.set USBFS_USB__ARB_EP6_INT_EN, CYREG_USB_ARB_EP6_INT_EN
-.set USBFS_USB__ARB_EP6_SR, CYREG_USB_ARB_EP6_SR
-.set USBFS_USB__ARB_EP7_CFG, CYREG_USB_ARB_EP7_CFG
-.set USBFS_USB__ARB_EP7_INT_EN, CYREG_USB_ARB_EP7_INT_EN
-.set USBFS_USB__ARB_EP7_SR, CYREG_USB_ARB_EP7_SR
-.set USBFS_USB__ARB_EP8_CFG, CYREG_USB_ARB_EP8_CFG
-.set USBFS_USB__ARB_EP8_INT_EN, CYREG_USB_ARB_EP8_INT_EN
-.set USBFS_USB__ARB_EP8_SR, CYREG_USB_ARB_EP8_SR
-.set USBFS_USB__ARB_INT_EN, CYREG_USB_ARB_INT_EN
-.set USBFS_USB__ARB_INT_SR, CYREG_USB_ARB_INT_SR
-.set USBFS_USB__ARB_RW1_DR, CYREG_USB_ARB_RW1_DR
-.set USBFS_USB__ARB_RW1_RA, CYREG_USB_ARB_RW1_RA
-.set USBFS_USB__ARB_RW1_RA_MSB, CYREG_USB_ARB_RW1_RA_MSB
-.set USBFS_USB__ARB_RW1_WA, CYREG_USB_ARB_RW1_WA
-.set USBFS_USB__ARB_RW1_WA_MSB, CYREG_USB_ARB_RW1_WA_MSB
-.set USBFS_USB__ARB_RW2_DR, CYREG_USB_ARB_RW2_DR
-.set USBFS_USB__ARB_RW2_RA, CYREG_USB_ARB_RW2_RA
-.set USBFS_USB__ARB_RW2_RA_MSB, CYREG_USB_ARB_RW2_RA_MSB
-.set USBFS_USB__ARB_RW2_WA, CYREG_USB_ARB_RW2_WA
-.set USBFS_USB__ARB_RW2_WA_MSB, CYREG_USB_ARB_RW2_WA_MSB
-.set USBFS_USB__ARB_RW3_DR, CYREG_USB_ARB_RW3_DR
-.set USBFS_USB__ARB_RW3_RA, CYREG_USB_ARB_RW3_RA
-.set USBFS_USB__ARB_RW3_RA_MSB, CYREG_USB_ARB_RW3_RA_MSB
-.set USBFS_USB__ARB_RW3_WA, CYREG_USB_ARB_RW3_WA
-.set USBFS_USB__ARB_RW3_WA_MSB, CYREG_USB_ARB_RW3_WA_MSB
-.set USBFS_USB__ARB_RW4_DR, CYREG_USB_ARB_RW4_DR
-.set USBFS_USB__ARB_RW4_RA, CYREG_USB_ARB_RW4_RA
-.set USBFS_USB__ARB_RW4_RA_MSB, CYREG_USB_ARB_RW4_RA_MSB
-.set USBFS_USB__ARB_RW4_WA, CYREG_USB_ARB_RW4_WA
-.set USBFS_USB__ARB_RW4_WA_MSB, CYREG_USB_ARB_RW4_WA_MSB
-.set USBFS_USB__ARB_RW5_DR, CYREG_USB_ARB_RW5_DR
-.set USBFS_USB__ARB_RW5_RA, CYREG_USB_ARB_RW5_RA
-.set USBFS_USB__ARB_RW5_RA_MSB, CYREG_USB_ARB_RW5_RA_MSB
-.set USBFS_USB__ARB_RW5_WA, CYREG_USB_ARB_RW5_WA
-.set USBFS_USB__ARB_RW5_WA_MSB, CYREG_USB_ARB_RW5_WA_MSB
-.set USBFS_USB__ARB_RW6_DR, CYREG_USB_ARB_RW6_DR
-.set USBFS_USB__ARB_RW6_RA, CYREG_USB_ARB_RW6_RA
-.set USBFS_USB__ARB_RW6_RA_MSB, CYREG_USB_ARB_RW6_RA_MSB
-.set USBFS_USB__ARB_RW6_WA, CYREG_USB_ARB_RW6_WA
-.set USBFS_USB__ARB_RW6_WA_MSB, CYREG_USB_ARB_RW6_WA_MSB
-.set USBFS_USB__ARB_RW7_DR, CYREG_USB_ARB_RW7_DR
-.set USBFS_USB__ARB_RW7_RA, CYREG_USB_ARB_RW7_RA
-.set USBFS_USB__ARB_RW7_RA_MSB, CYREG_USB_ARB_RW7_RA_MSB
-.set USBFS_USB__ARB_RW7_WA, CYREG_USB_ARB_RW7_WA
-.set USBFS_USB__ARB_RW7_WA_MSB, CYREG_USB_ARB_RW7_WA_MSB
-.set USBFS_USB__ARB_RW8_DR, CYREG_USB_ARB_RW8_DR
-.set USBFS_USB__ARB_RW8_RA, CYREG_USB_ARB_RW8_RA
-.set USBFS_USB__ARB_RW8_RA_MSB, CYREG_USB_ARB_RW8_RA_MSB
-.set USBFS_USB__ARB_RW8_WA, CYREG_USB_ARB_RW8_WA
-.set USBFS_USB__ARB_RW8_WA_MSB, CYREG_USB_ARB_RW8_WA_MSB
-.set USBFS_USB__BUF_SIZE, CYREG_USB_BUF_SIZE
-.set USBFS_USB__BUS_RST_CNT, CYREG_USB_BUS_RST_CNT
-.set USBFS_USB__CR0, CYREG_USB_CR0
-.set USBFS_USB__CR1, CYREG_USB_CR1
-.set USBFS_USB__CWA, CYREG_USB_CWA
-.set USBFS_USB__CWA_MSB, CYREG_USB_CWA_MSB
-.set USBFS_USB__DMA_THRES, CYREG_USB_DMA_THRES
-.set USBFS_USB__DMA_THRES_MSB, CYREG_USB_DMA_THRES_MSB
-.set USBFS_USB__DYN_RECONFIG, CYREG_USB_DYN_RECONFIG
-.set USBFS_USB__EP_ACTIVE, CYREG_USB_EP_ACTIVE
-.set USBFS_USB__EP_TYPE, CYREG_USB_EP_TYPE
-.set USBFS_USB__EP0_CNT, CYREG_USB_EP0_CNT
-.set USBFS_USB__EP0_CR, CYREG_USB_EP0_CR
-.set USBFS_USB__EP0_DR0, CYREG_USB_EP0_DR0
-.set USBFS_USB__EP0_DR1, CYREG_USB_EP0_DR1
-.set USBFS_USB__EP0_DR2, CYREG_USB_EP0_DR2
-.set USBFS_USB__EP0_DR3, CYREG_USB_EP0_DR3
-.set USBFS_USB__EP0_DR4, CYREG_USB_EP0_DR4
-.set USBFS_USB__EP0_DR5, CYREG_USB_EP0_DR5
-.set USBFS_USB__EP0_DR6, CYREG_USB_EP0_DR6
-.set USBFS_USB__EP0_DR7, CYREG_USB_EP0_DR7
-.set USBFS_USB__MEM_DATA, CYREG_USB_MEM_DATA_MBASE
-.set USBFS_USB__PM_ACT_CFG, CYREG_PM_ACT_CFG5
-.set USBFS_USB__PM_ACT_MSK, 0x01
-.set USBFS_USB__PM_STBY_CFG, CYREG_PM_STBY_CFG5
-.set USBFS_USB__PM_STBY_MSK, 0x01
-.set USBFS_USB__SIE_EP_INT_EN, CYREG_USB_SIE_EP_INT_EN
-.set USBFS_USB__SIE_EP_INT_SR, CYREG_USB_SIE_EP_INT_SR
-.set USBFS_USB__SIE_EP1_CNT0, CYREG_USB_SIE_EP1_CNT0
-.set USBFS_USB__SIE_EP1_CNT1, CYREG_USB_SIE_EP1_CNT1
-.set USBFS_USB__SIE_EP1_CR0, CYREG_USB_SIE_EP1_CR0
-.set USBFS_USB__SIE_EP2_CNT0, CYREG_USB_SIE_EP2_CNT0
-.set USBFS_USB__SIE_EP2_CNT1, CYREG_USB_SIE_EP2_CNT1
-.set USBFS_USB__SIE_EP2_CR0, CYREG_USB_SIE_EP2_CR0
-.set USBFS_USB__SIE_EP3_CNT0, CYREG_USB_SIE_EP3_CNT0
-.set USBFS_USB__SIE_EP3_CNT1, CYREG_USB_SIE_EP3_CNT1
-.set USBFS_USB__SIE_EP3_CR0, CYREG_USB_SIE_EP3_CR0
-.set USBFS_USB__SIE_EP4_CNT0, CYREG_USB_SIE_EP4_CNT0
-.set USBFS_USB__SIE_EP4_CNT1, CYREG_USB_SIE_EP4_CNT1
-.set USBFS_USB__SIE_EP4_CR0, CYREG_USB_SIE_EP4_CR0
-.set USBFS_USB__SIE_EP5_CNT0, CYREG_USB_SIE_EP5_CNT0
-.set USBFS_USB__SIE_EP5_CNT1, CYREG_USB_SIE_EP5_CNT1
-.set USBFS_USB__SIE_EP5_CR0, CYREG_USB_SIE_EP5_CR0
-.set USBFS_USB__SIE_EP6_CNT0, CYREG_USB_SIE_EP6_CNT0
-.set USBFS_USB__SIE_EP6_CNT1, CYREG_USB_SIE_EP6_CNT1
-.set USBFS_USB__SIE_EP6_CR0, CYREG_USB_SIE_EP6_CR0
-.set USBFS_USB__SIE_EP7_CNT0, CYREG_USB_SIE_EP7_CNT0
-.set USBFS_USB__SIE_EP7_CNT1, CYREG_USB_SIE_EP7_CNT1
-.set USBFS_USB__SIE_EP7_CR0, CYREG_USB_SIE_EP7_CR0
-.set USBFS_USB__SIE_EP8_CNT0, CYREG_USB_SIE_EP8_CNT0
-.set USBFS_USB__SIE_EP8_CNT1, CYREG_USB_SIE_EP8_CNT1
-.set USBFS_USB__SIE_EP8_CR0, CYREG_USB_SIE_EP8_CR0
-.set USBFS_USB__SOF0, CYREG_USB_SOF0
-.set USBFS_USB__SOF1, CYREG_USB_SOF1
-.set USBFS_USB__USB_CLK_EN, CYREG_USB_USB_CLK_EN
-.set USBFS_USB__USBIO_CR0, CYREG_USB_USBIO_CR0
-.set USBFS_USB__USBIO_CR1, CYREG_USB_USBIO_CR1
-
-/* SDCard_BSPIM */
-.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB04_05_ACTL
-.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB04_05_CTL
-.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB04_05_CTL
-.set SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB04_05_CTL
-.set SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB04_05_CTL
-.set SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B1_UDB04_05_MSK
-.set SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB04_05_MSK
-.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB04_05_MSK
-.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB04_05_MSK
-.set SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B1_UDB04_ACTL
-.set SDCard_BSPIM_BitCounter__CONTROL_REG, CYREG_B1_UDB04_CTL
-.set SDCard_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B1_UDB04_ST_CTL
-.set SDCard_BSPIM_BitCounter__COUNT_REG, CYREG_B1_UDB04_CTL
-.set SDCard_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B1_UDB04_ST_CTL
-.set SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL
-.set SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL
-.set SDCard_BSPIM_BitCounter__PERIOD_REG, CYREG_B1_UDB04_MSK
-.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB04_05_ACTL
-.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B1_UDB04_05_ST
-.set SDCard_BSPIM_BitCounter_ST__MASK_REG, CYREG_B1_UDB04_MSK
-.set SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL
-.set SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL
-.set SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B1_UDB04_ACTL
-.set SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B1_UDB04_ST_CTL
-.set SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B1_UDB04_ST_CTL
-.set SDCard_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B1_UDB04_ST
-.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB07_08_ACTL
-.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB07_08_ST
-.set SDCard_BSPIM_RxStsReg__4__MASK, 0x10
-.set SDCard_BSPIM_RxStsReg__4__POS, 4
-.set SDCard_BSPIM_RxStsReg__5__MASK, 0x20
-.set SDCard_BSPIM_RxStsReg__5__POS, 5
-.set SDCard_BSPIM_RxStsReg__6__MASK, 0x40
-.set SDCard_BSPIM_RxStsReg__6__POS, 6
-.set SDCard_BSPIM_RxStsReg__MASK, 0x70
-.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B0_UDB07_MSK
-.set SDCard_BSPIM_RxStsReg__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB07_MSK_ACTL
-.set SDCard_BSPIM_RxStsReg__PER_ST_AUX_CTL_REG, CYREG_B0_UDB07_MSK_ACTL
-.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB07_ACTL
-.set SDCard_BSPIM_RxStsReg__STATUS_CNT_REG, CYREG_B0_UDB07_ST_CTL
-.set SDCard_BSPIM_RxStsReg__STATUS_CONTROL_REG, CYREG_B0_UDB07_ST_CTL
-.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B0_UDB07_ST
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG, CYREG_B1_UDB04_05_A0
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG, CYREG_B1_UDB04_05_A1
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG, CYREG_B1_UDB04_05_D0
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG, CYREG_B1_UDB04_05_D1
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG, CYREG_B1_UDB04_05_ACTL
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG, CYREG_B1_UDB04_05_F0
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG, CYREG_B1_UDB04_05_F1
-.set SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG, CYREG_B1_UDB04_A0_A1
-.set SDCard_BSPIM_sR8_Dp_u0__A0_REG, CYREG_B1_UDB04_A0
-.set SDCard_BSPIM_sR8_Dp_u0__A1_REG, CYREG_B1_UDB04_A1
-.set SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG, CYREG_B1_UDB04_D0_D1
-.set SDCard_BSPIM_sR8_Dp_u0__D0_REG, CYREG_B1_UDB04_D0
-.set SDCard_BSPIM_sR8_Dp_u0__D1_REG, CYREG_B1_UDB04_D1
-.set SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG, CYREG_B1_UDB04_ACTL
-.set SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG, CYREG_B1_UDB04_F0_F1
-.set SDCard_BSPIM_sR8_Dp_u0__F0_REG, CYREG_B1_UDB04_F0
-.set SDCard_BSPIM_sR8_Dp_u0__F1_REG, CYREG_B1_UDB04_F1
-.set SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL
-.set SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL
-.set SDCard_BSPIM_TxStsReg__0__MASK, 0x01
-.set SDCard_BSPIM_TxStsReg__0__POS, 0
-.set SDCard_BSPIM_TxStsReg__1__MASK, 0x02
-.set SDCard_BSPIM_TxStsReg__1__POS, 1
-.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB07_08_ACTL
-.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB07_08_ST
-.set SDCard_BSPIM_TxStsReg__2__MASK, 0x04
-.set SDCard_BSPIM_TxStsReg__2__POS, 2
-.set SDCard_BSPIM_TxStsReg__3__MASK, 0x08
-.set SDCard_BSPIM_TxStsReg__3__POS, 3
-.set SDCard_BSPIM_TxStsReg__4__MASK, 0x10
-.set SDCard_BSPIM_TxStsReg__4__POS, 4
-.set SDCard_BSPIM_TxStsReg__MASK, 0x1F
-.set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B1_UDB07_MSK
-.set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB07_ACTL
-.set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B1_UDB07_ST
-
-/* SD_SCK */
-.set SD_SCK__0__INTTYPE, CYREG_PICU3_INTTYPE3
-.set SD_SCK__0__MASK, 0x08
-.set SD_SCK__0__PC, CYREG_PRT3_PC3
-.set SD_SCK__0__PORT, 3
-.set SD_SCK__0__SHIFT, 3
-.set SD_SCK__AG, CYREG_PRT3_AG
-.set SD_SCK__AMUX, CYREG_PRT3_AMUX
-.set SD_SCK__BIE, CYREG_PRT3_BIE
-.set SD_SCK__BIT_MASK, CYREG_PRT3_BIT_MASK
-.set SD_SCK__BYP, CYREG_PRT3_BYP
-.set SD_SCK__CTL, CYREG_PRT3_CTL
-.set SD_SCK__DM0, CYREG_PRT3_DM0
-.set SD_SCK__DM1, CYREG_PRT3_DM1
-.set SD_SCK__DM2, CYREG_PRT3_DM2
-.set SD_SCK__DR, CYREG_PRT3_DR
-.set SD_SCK__INP_DIS, CYREG_PRT3_INP_DIS
-.set SD_SCK__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU3_BASE
-.set SD_SCK__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG
-.set SD_SCK__LCD_EN, CYREG_PRT3_LCD_EN
-.set SD_SCK__MASK, 0x08
-.set SD_SCK__PORT, 3
-.set SD_SCK__PRT, CYREG_PRT3_PRT
-.set SD_SCK__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL
-.set SD_SCK__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN
-.set SD_SCK__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0
-.set SD_SCK__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1
-.set SD_SCK__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0
-.set SD_SCK__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1
-.set SD_SCK__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT
-.set SD_SCK__PS, CYREG_PRT3_PS
-.set SD_SCK__SHIFT, 3
-.set SD_SCK__SLW, CYREG_PRT3_SLW
-
-/* SCSI_In */
-.set SCSI_In__0__INTTYPE, CYREG_PICU6_INTTYPE1
-.set SCSI_In__0__MASK, 0x02
-.set SCSI_In__0__PC, CYREG_PRT6_PC1
-.set SCSI_In__0__PORT, 6
-.set SCSI_In__0__SHIFT, 1
-.set SCSI_In__AG, CYREG_PRT6_AG
-.set SCSI_In__AMUX, CYREG_PRT6_AMUX
-.set SCSI_In__BIE, CYREG_PRT6_BIE
-.set SCSI_In__BIT_MASK, CYREG_PRT6_BIT_MASK
-.set SCSI_In__BYP, CYREG_PRT6_BYP
-.set SCSI_In__CTL, CYREG_PRT6_CTL
-.set SCSI_In__DBP__INTTYPE, CYREG_PICU6_INTTYPE1
-.set SCSI_In__DBP__MASK, 0x02
-.set SCSI_In__DBP__PC, CYREG_PRT6_PC1
-.set SCSI_In__DBP__PORT, 6
-.set SCSI_In__DBP__SHIFT, 1
-.set SCSI_In__DM0, CYREG_PRT6_DM0
-.set SCSI_In__DM1, CYREG_PRT6_DM1
-.set SCSI_In__DM2, CYREG_PRT6_DM2
-.set SCSI_In__DR, CYREG_PRT6_DR
-.set SCSI_In__INP_DIS, CYREG_PRT6_INP_DIS
-.set SCSI_In__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU6_BASE
-.set SCSI_In__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
-.set SCSI_In__LCD_EN, CYREG_PRT6_LCD_EN
-.set SCSI_In__MASK, 0x02
-.set SCSI_In__PORT, 6
-.set SCSI_In__PRT, CYREG_PRT6_PRT
-.set SCSI_In__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL
-.set SCSI_In__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN
-.set SCSI_In__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0
-.set SCSI_In__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1
-.set SCSI_In__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0
-.set SCSI_In__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1
-.set SCSI_In__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT
-.set SCSI_In__PS, CYREG_PRT6_PS
-.set SCSI_In__SHIFT, 1
-.set SCSI_In__SLW, CYREG_PRT6_SLW
-
-/* SCSI_In_DBx */
-.set SCSI_In_DBx__0__AG, CYREG_PRT6_AG
-.set SCSI_In_DBx__0__AMUX, CYREG_PRT6_AMUX
-.set SCSI_In_DBx__0__BIE, CYREG_PRT6_BIE
-.set SCSI_In_DBx__0__BIT_MASK, CYREG_PRT6_BIT_MASK
-.set SCSI_In_DBx__0__BYP, CYREG_PRT6_BYP
-.set SCSI_In_DBx__0__CTL, CYREG_PRT6_CTL
-.set SCSI_In_DBx__0__DM0, CYREG_PRT6_DM0
-.set SCSI_In_DBx__0__DM1, CYREG_PRT6_DM1
-.set SCSI_In_DBx__0__DM2, CYREG_PRT6_DM2
-.set SCSI_In_DBx__0__DR, CYREG_PRT6_DR
-.set SCSI_In_DBx__0__INP_DIS, CYREG_PRT6_INP_DIS
-.set SCSI_In_DBx__0__INTTYPE, CYREG_PICU6_INTTYPE6
-.set SCSI_In_DBx__0__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
-.set SCSI_In_DBx__0__LCD_EN, CYREG_PRT6_LCD_EN
-.set SCSI_In_DBx__0__MASK, 0x40
-.set SCSI_In_DBx__0__PC, CYREG_PRT6_PC6
-.set SCSI_In_DBx__0__PORT, 6
-.set SCSI_In_DBx__0__PRT, CYREG_PRT6_PRT
-.set SCSI_In_DBx__0__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL
-.set SCSI_In_DBx__0__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN
-.set SCSI_In_DBx__0__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0
-.set SCSI_In_DBx__0__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1
-.set SCSI_In_DBx__0__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0
-.set SCSI_In_DBx__0__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1
-.set SCSI_In_DBx__0__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT
-.set SCSI_In_DBx__0__PS, CYREG_PRT6_PS
-.set SCSI_In_DBx__0__SHIFT, 6
-.set SCSI_In_DBx__0__SLW, CYREG_PRT6_SLW
-.set SCSI_In_DBx__1__AG, CYREG_PRT6_AG
-.set SCSI_In_DBx__1__AMUX, CYREG_PRT6_AMUX
-.set SCSI_In_DBx__1__BIE, CYREG_PRT6_BIE
-.set SCSI_In_DBx__1__BIT_MASK, CYREG_PRT6_BIT_MASK
-.set SCSI_In_DBx__1__BYP, CYREG_PRT6_BYP
-.set SCSI_In_DBx__1__CTL, CYREG_PRT6_CTL
-.set SCSI_In_DBx__1__DM0, CYREG_PRT6_DM0
-.set SCSI_In_DBx__1__DM1, CYREG_PRT6_DM1
-.set SCSI_In_DBx__1__DM2, CYREG_PRT6_DM2
-.set SCSI_In_DBx__1__DR, CYREG_PRT6_DR
-.set SCSI_In_DBx__1__INP_DIS, CYREG_PRT6_INP_DIS
-.set SCSI_In_DBx__1__INTTYPE, CYREG_PICU6_INTTYPE4
-.set SCSI_In_DBx__1__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
-.set SCSI_In_DBx__1__LCD_EN, CYREG_PRT6_LCD_EN
-.set SCSI_In_DBx__1__MASK, 0x10
-.set SCSI_In_DBx__1__PC, CYREG_PRT6_PC4
-.set SCSI_In_DBx__1__PORT, 6
-.set SCSI_In_DBx__1__PRT, CYREG_PRT6_PRT
-.set SCSI_In_DBx__1__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL
-.set SCSI_In_DBx__1__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN
-.set SCSI_In_DBx__1__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0
-.set SCSI_In_DBx__1__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1
-.set SCSI_In_DBx__1__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0
-.set SCSI_In_DBx__1__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1
-.set SCSI_In_DBx__1__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT
-.set SCSI_In_DBx__1__PS, CYREG_PRT6_PS
-.set SCSI_In_DBx__1__SHIFT, 4
-.set SCSI_In_DBx__1__SLW, CYREG_PRT6_SLW
-.set SCSI_In_DBx__2__AG, CYREG_PRT12_AG
-.set SCSI_In_DBx__2__BIE, CYREG_PRT12_BIE
-.set SCSI_In_DBx__2__BIT_MASK, CYREG_PRT12_BIT_MASK
-.set SCSI_In_DBx__2__BYP, CYREG_PRT12_BYP
-.set SCSI_In_DBx__2__DM0, CYREG_PRT12_DM0
-.set SCSI_In_DBx__2__DM1, CYREG_PRT12_DM1
-.set SCSI_In_DBx__2__DM2, CYREG_PRT12_DM2
-.set SCSI_In_DBx__2__DR, CYREG_PRT12_DR
-.set SCSI_In_DBx__2__INP_DIS, CYREG_PRT12_INP_DIS
-.set SCSI_In_DBx__2__INTTYPE, CYREG_PICU12_INTTYPE4
-.set SCSI_In_DBx__2__MASK, 0x10
-.set SCSI_In_DBx__2__PC, CYREG_PRT12_PC4
-.set SCSI_In_DBx__2__PORT, 12
-.set SCSI_In_DBx__2__PRT, CYREG_PRT12_PRT
-.set SCSI_In_DBx__2__PRTDSI__DBL_SYNC_IN, CYREG_PRT12_DBL_SYNC_IN
-.set SCSI_In_DBx__2__PRTDSI__OE_SEL0, CYREG_PRT12_OE_SEL0
-.set SCSI_In_DBx__2__PRTDSI__OE_SEL1, CYREG_PRT12_OE_SEL1
-.set SCSI_In_DBx__2__PRTDSI__OUT_SEL0, CYREG_PRT12_OUT_SEL0
-.set SCSI_In_DBx__2__PRTDSI__OUT_SEL1, CYREG_PRT12_OUT_SEL1
-.set SCSI_In_DBx__2__PRTDSI__SYNC_OUT, CYREG_PRT12_SYNC_OUT
-.set SCSI_In_DBx__2__PS, CYREG_PRT12_PS
-.set SCSI_In_DBx__2__SHIFT, 4
-.set SCSI_In_DBx__2__SIO_CFG, CYREG_PRT12_SIO_CFG
-.set SCSI_In_DBx__2__SIO_DIFF, CYREG_PRT12_SIO_DIFF
-.set SCSI_In_DBx__2__SIO_HYST_EN, CYREG_PRT12_SIO_HYST_EN
-.set SCSI_In_DBx__2__SIO_REG_HIFREQ, CYREG_PRT12_SIO_REG_HIFREQ
-.set SCSI_In_DBx__2__SLW, CYREG_PRT12_SLW
-.set SCSI_In_DBx__3__AG, CYREG_PRT2_AG
-.set SCSI_In_DBx__3__AMUX, CYREG_PRT2_AMUX
-.set SCSI_In_DBx__3__BIE, CYREG_PRT2_BIE
-.set SCSI_In_DBx__3__BIT_MASK, CYREG_PRT2_BIT_MASK
-.set SCSI_In_DBx__3__BYP, CYREG_PRT2_BYP
-.set SCSI_In_DBx__3__CTL, CYREG_PRT2_CTL
-.set SCSI_In_DBx__3__DM0, CYREG_PRT2_DM0
-.set SCSI_In_DBx__3__DM1, CYREG_PRT2_DM1
-.set SCSI_In_DBx__3__DM2, CYREG_PRT2_DM2
-.set SCSI_In_DBx__3__DR, CYREG_PRT2_DR
-.set SCSI_In_DBx__3__INP_DIS, CYREG_PRT2_INP_DIS
-.set SCSI_In_DBx__3__INTTYPE, CYREG_PICU2_INTTYPE6
-.set SCSI_In_DBx__3__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG
-.set SCSI_In_DBx__3__LCD_EN, CYREG_PRT2_LCD_EN
-.set SCSI_In_DBx__3__MASK, 0x40
-.set SCSI_In_DBx__3__PC, CYREG_PRT2_PC6
-.set SCSI_In_DBx__3__PORT, 2
-.set SCSI_In_DBx__3__PRT, CYREG_PRT2_PRT
-.set SCSI_In_DBx__3__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL
-.set SCSI_In_DBx__3__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN
-.set SCSI_In_DBx__3__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0
-.set SCSI_In_DBx__3__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1
-.set SCSI_In_DBx__3__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0
-.set SCSI_In_DBx__3__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1
-.set SCSI_In_DBx__3__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT
-.set SCSI_In_DBx__3__PS, CYREG_PRT2_PS
-.set SCSI_In_DBx__3__SHIFT, 6
-.set SCSI_In_DBx__3__SLW, CYREG_PRT2_SLW
-.set SCSI_In_DBx__4__AG, CYREG_PRT2_AG
-.set SCSI_In_DBx__4__AMUX, CYREG_PRT2_AMUX
-.set SCSI_In_DBx__4__BIE, CYREG_PRT2_BIE
-.set SCSI_In_DBx__4__BIT_MASK, CYREG_PRT2_BIT_MASK
-.set SCSI_In_DBx__4__BYP, CYREG_PRT2_BYP
-.set SCSI_In_DBx__4__CTL, CYREG_PRT2_CTL
-.set SCSI_In_DBx__4__DM0, CYREG_PRT2_DM0
-.set SCSI_In_DBx__4__DM1, CYREG_PRT2_DM1
-.set SCSI_In_DBx__4__DM2, CYREG_PRT2_DM2
-.set SCSI_In_DBx__4__DR, CYREG_PRT2_DR
-.set SCSI_In_DBx__4__INP_DIS, CYREG_PRT2_INP_DIS
-.set SCSI_In_DBx__4__INTTYPE, CYREG_PICU2_INTTYPE4
-.set SCSI_In_DBx__4__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG
-.set SCSI_In_DBx__4__LCD_EN, CYREG_PRT2_LCD_EN
-.set SCSI_In_DBx__4__MASK, 0x10
-.set SCSI_In_DBx__4__PC, CYREG_PRT2_PC4
-.set SCSI_In_DBx__4__PORT, 2
-.set SCSI_In_DBx__4__PRT, CYREG_PRT2_PRT
-.set SCSI_In_DBx__4__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL
-.set SCSI_In_DBx__4__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN
-.set SCSI_In_DBx__4__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0
-.set SCSI_In_DBx__4__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1
-.set SCSI_In_DBx__4__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0
-.set SCSI_In_DBx__4__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1
-.set SCSI_In_DBx__4__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT
-.set SCSI_In_DBx__4__PS, CYREG_PRT2_PS
-.set SCSI_In_DBx__4__SHIFT, 4
-.set SCSI_In_DBx__4__SLW, CYREG_PRT2_SLW
-.set SCSI_In_DBx__5__AG, CYREG_PRT2_AG
-.set SCSI_In_DBx__5__AMUX, CYREG_PRT2_AMUX
-.set SCSI_In_DBx__5__BIE, CYREG_PRT2_BIE
-.set SCSI_In_DBx__5__BIT_MASK, CYREG_PRT2_BIT_MASK
-.set SCSI_In_DBx__5__BYP, CYREG_PRT2_BYP
-.set SCSI_In_DBx__5__CTL, CYREG_PRT2_CTL
-.set SCSI_In_DBx__5__DM0, CYREG_PRT2_DM0
-.set SCSI_In_DBx__5__DM1, CYREG_PRT2_DM1
-.set SCSI_In_DBx__5__DM2, CYREG_PRT2_DM2
-.set SCSI_In_DBx__5__DR, CYREG_PRT2_DR
-.set SCSI_In_DBx__5__INP_DIS, CYREG_PRT2_INP_DIS
-.set SCSI_In_DBx__5__INTTYPE, CYREG_PICU2_INTTYPE2
-.set SCSI_In_DBx__5__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG
-.set SCSI_In_DBx__5__LCD_EN, CYREG_PRT2_LCD_EN
-.set SCSI_In_DBx__5__MASK, 0x04
-.set SCSI_In_DBx__5__PC, CYREG_PRT2_PC2
-.set SCSI_In_DBx__5__PORT, 2
-.set SCSI_In_DBx__5__PRT, CYREG_PRT2_PRT
-.set SCSI_In_DBx__5__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL
-.set SCSI_In_DBx__5__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN
-.set SCSI_In_DBx__5__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0
-.set SCSI_In_DBx__5__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1
-.set SCSI_In_DBx__5__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0
-.set SCSI_In_DBx__5__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1
-.set SCSI_In_DBx__5__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT
-.set SCSI_In_DBx__5__PS, CYREG_PRT2_PS
-.set SCSI_In_DBx__5__SHIFT, 2
-.set SCSI_In_DBx__5__SLW, CYREG_PRT2_SLW
-.set SCSI_In_DBx__6__AG, CYREG_PRT2_AG
-.set SCSI_In_DBx__6__AMUX, CYREG_PRT2_AMUX
-.set SCSI_In_DBx__6__BIE, CYREG_PRT2_BIE
-.set SCSI_In_DBx__6__BIT_MASK, CYREG_PRT2_BIT_MASK
-.set SCSI_In_DBx__6__BYP, CYREG_PRT2_BYP
-.set SCSI_In_DBx__6__CTL, CYREG_PRT2_CTL
-.set SCSI_In_DBx__6__DM0, CYREG_PRT2_DM0
-.set SCSI_In_DBx__6__DM1, CYREG_PRT2_DM1
-.set SCSI_In_DBx__6__DM2, CYREG_PRT2_DM2
-.set SCSI_In_DBx__6__DR, CYREG_PRT2_DR
-.set SCSI_In_DBx__6__INP_DIS, CYREG_PRT2_INP_DIS
-.set SCSI_In_DBx__6__INTTYPE, CYREG_PICU2_INTTYPE0
-.set SCSI_In_DBx__6__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG
-.set SCSI_In_DBx__6__LCD_EN, CYREG_PRT2_LCD_EN
-.set SCSI_In_DBx__6__MASK, 0x01
-.set SCSI_In_DBx__6__PC, CYREG_PRT2_PC0
-.set SCSI_In_DBx__6__PORT, 2
-.set SCSI_In_DBx__6__PRT, CYREG_PRT2_PRT
-.set SCSI_In_DBx__6__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL
-.set SCSI_In_DBx__6__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN
-.set SCSI_In_DBx__6__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0
-.set SCSI_In_DBx__6__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1
-.set SCSI_In_DBx__6__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0
-.set SCSI_In_DBx__6__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1
-.set SCSI_In_DBx__6__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT
-.set SCSI_In_DBx__6__PS, CYREG_PRT2_PS
-.set SCSI_In_DBx__6__SHIFT, 0
-.set SCSI_In_DBx__6__SLW, CYREG_PRT2_SLW
-.set SCSI_In_DBx__7__AG, CYREG_PRT6_AG
-.set SCSI_In_DBx__7__AMUX, CYREG_PRT6_AMUX
-.set SCSI_In_DBx__7__BIE, CYREG_PRT6_BIE
-.set SCSI_In_DBx__7__BIT_MASK, CYREG_PRT6_BIT_MASK
-.set SCSI_In_DBx__7__BYP, CYREG_PRT6_BYP
-.set SCSI_In_DBx__7__CTL, CYREG_PRT6_CTL
-.set SCSI_In_DBx__7__DM0, CYREG_PRT6_DM0
-.set SCSI_In_DBx__7__DM1, CYREG_PRT6_DM1
-.set SCSI_In_DBx__7__DM2, CYREG_PRT6_DM2
-.set SCSI_In_DBx__7__DR, CYREG_PRT6_DR
-.set SCSI_In_DBx__7__INP_DIS, CYREG_PRT6_INP_DIS
-.set SCSI_In_DBx__7__INTTYPE, CYREG_PICU6_INTTYPE3
-.set SCSI_In_DBx__7__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
-.set SCSI_In_DBx__7__LCD_EN, CYREG_PRT6_LCD_EN
-.set SCSI_In_DBx__7__MASK, 0x08
-.set SCSI_In_DBx__7__PC, CYREG_PRT6_PC3
-.set SCSI_In_DBx__7__PORT, 6
-.set SCSI_In_DBx__7__PRT, CYREG_PRT6_PRT
-.set SCSI_In_DBx__7__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL
-.set SCSI_In_DBx__7__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN
-.set SCSI_In_DBx__7__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0
-.set SCSI_In_DBx__7__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1
-.set SCSI_In_DBx__7__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0
-.set SCSI_In_DBx__7__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1
-.set SCSI_In_DBx__7__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT
-.set SCSI_In_DBx__7__PS, CYREG_PRT6_PS
-.set SCSI_In_DBx__7__SHIFT, 3
-.set SCSI_In_DBx__7__SLW, CYREG_PRT6_SLW
-.set SCSI_In_DBx__DB0__AG, CYREG_PRT6_AG
-.set SCSI_In_DBx__DB0__AMUX, CYREG_PRT6_AMUX
-.set SCSI_In_DBx__DB0__BIE, CYREG_PRT6_BIE
-.set SCSI_In_DBx__DB0__BIT_MASK, CYREG_PRT6_BIT_MASK
-.set SCSI_In_DBx__DB0__BYP, CYREG_PRT6_BYP
-.set SCSI_In_DBx__DB0__CTL, CYREG_PRT6_CTL
-.set SCSI_In_DBx__DB0__DM0, CYREG_PRT6_DM0
-.set SCSI_In_DBx__DB0__DM1, CYREG_PRT6_DM1
-.set SCSI_In_DBx__DB0__DM2, CYREG_PRT6_DM2
-.set SCSI_In_DBx__DB0__DR, CYREG_PRT6_DR
-.set SCSI_In_DBx__DB0__INP_DIS, CYREG_PRT6_INP_DIS
-.set SCSI_In_DBx__DB0__INTTYPE, CYREG_PICU6_INTTYPE6
-.set SCSI_In_DBx__DB0__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
-.set SCSI_In_DBx__DB0__LCD_EN, CYREG_PRT6_LCD_EN
-.set SCSI_In_DBx__DB0__MASK, 0x40
-.set SCSI_In_DBx__DB0__PC, CYREG_PRT6_PC6
-.set SCSI_In_DBx__DB0__PORT, 6
-.set SCSI_In_DBx__DB0__PRT, CYREG_PRT6_PRT
-.set SCSI_In_DBx__DB0__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL
-.set SCSI_In_DBx__DB0__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN
-.set SCSI_In_DBx__DB0__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0
-.set SCSI_In_DBx__DB0__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1
-.set SCSI_In_DBx__DB0__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0
-.set SCSI_In_DBx__DB0__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1
-.set SCSI_In_DBx__DB0__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT
-.set SCSI_In_DBx__DB0__PS, CYREG_PRT6_PS
-.set SCSI_In_DBx__DB0__SHIFT, 6
-.set SCSI_In_DBx__DB0__SLW, CYREG_PRT6_SLW
-.set SCSI_In_DBx__DB1__AG, CYREG_PRT6_AG
-.set SCSI_In_DBx__DB1__AMUX, CYREG_PRT6_AMUX
-.set SCSI_In_DBx__DB1__BIE, CYREG_PRT6_BIE
-.set SCSI_In_DBx__DB1__BIT_MASK, CYREG_PRT6_BIT_MASK
-.set SCSI_In_DBx__DB1__BYP, CYREG_PRT6_BYP
-.set SCSI_In_DBx__DB1__CTL, CYREG_PRT6_CTL
-.set SCSI_In_DBx__DB1__DM0, CYREG_PRT6_DM0
-.set SCSI_In_DBx__DB1__DM1, CYREG_PRT6_DM1
-.set SCSI_In_DBx__DB1__DM2, CYREG_PRT6_DM2
-.set SCSI_In_DBx__DB1__DR, CYREG_PRT6_DR
-.set SCSI_In_DBx__DB1__INP_DIS, CYREG_PRT6_INP_DIS
-.set SCSI_In_DBx__DB1__INTTYPE, CYREG_PICU6_INTTYPE4
-.set SCSI_In_DBx__DB1__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
-.set SCSI_In_DBx__DB1__LCD_EN, CYREG_PRT6_LCD_EN
-.set SCSI_In_DBx__DB1__MASK, 0x10
-.set SCSI_In_DBx__DB1__PC, CYREG_PRT6_PC4
-.set SCSI_In_DBx__DB1__PORT, 6
-.set SCSI_In_DBx__DB1__PRT, CYREG_PRT6_PRT
-.set SCSI_In_DBx__DB1__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL
-.set SCSI_In_DBx__DB1__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN
-.set SCSI_In_DBx__DB1__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0
-.set SCSI_In_DBx__DB1__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1
-.set SCSI_In_DBx__DB1__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0
-.set SCSI_In_DBx__DB1__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1
-.set SCSI_In_DBx__DB1__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT
-.set SCSI_In_DBx__DB1__PS, CYREG_PRT6_PS
-.set SCSI_In_DBx__DB1__SHIFT, 4
-.set SCSI_In_DBx__DB1__SLW, CYREG_PRT6_SLW
-.set SCSI_In_DBx__DB2__AG, CYREG_PRT12_AG
-.set SCSI_In_DBx__DB2__BIE, CYREG_PRT12_BIE
-.set SCSI_In_DBx__DB2__BIT_MASK, CYREG_PRT12_BIT_MASK
-.set SCSI_In_DBx__DB2__BYP, CYREG_PRT12_BYP
-.set SCSI_In_DBx__DB2__DM0, CYREG_PRT12_DM0
-.set SCSI_In_DBx__DB2__DM1, CYREG_PRT12_DM1
-.set SCSI_In_DBx__DB2__DM2, CYREG_PRT12_DM2
-.set SCSI_In_DBx__DB2__DR, CYREG_PRT12_DR
-.set SCSI_In_DBx__DB2__INP_DIS, CYREG_PRT12_INP_DIS
-.set SCSI_In_DBx__DB2__INTTYPE, CYREG_PICU12_INTTYPE4
-.set SCSI_In_DBx__DB2__MASK, 0x10
-.set SCSI_In_DBx__DB2__PC, CYREG_PRT12_PC4
-.set SCSI_In_DBx__DB2__PORT, 12
-.set SCSI_In_DBx__DB2__PRT, CYREG_PRT12_PRT
-.set SCSI_In_DBx__DB2__PRTDSI__DBL_SYNC_IN, CYREG_PRT12_DBL_SYNC_IN
-.set SCSI_In_DBx__DB2__PRTDSI__OE_SEL0, CYREG_PRT12_OE_SEL0
-.set SCSI_In_DBx__DB2__PRTDSI__OE_SEL1, CYREG_PRT12_OE_SEL1
-.set SCSI_In_DBx__DB2__PRTDSI__OUT_SEL0, CYREG_PRT12_OUT_SEL0
-.set SCSI_In_DBx__DB2__PRTDSI__OUT_SEL1, CYREG_PRT12_OUT_SEL1
-.set SCSI_In_DBx__DB2__PRTDSI__SYNC_OUT, CYREG_PRT12_SYNC_OUT
-.set SCSI_In_DBx__DB2__PS, CYREG_PRT12_PS
-.set SCSI_In_DBx__DB2__SHIFT, 4
-.set SCSI_In_DBx__DB2__SIO_CFG, CYREG_PRT12_SIO_CFG
-.set SCSI_In_DBx__DB2__SIO_DIFF, CYREG_PRT12_SIO_DIFF
-.set SCSI_In_DBx__DB2__SIO_HYST_EN, CYREG_PRT12_SIO_HYST_EN
-.set SCSI_In_DBx__DB2__SIO_REG_HIFREQ, CYREG_PRT12_SIO_REG_HIFREQ
-.set SCSI_In_DBx__DB2__SLW, CYREG_PRT12_SLW
-.set SCSI_In_DBx__DB3__AG, CYREG_PRT2_AG
-.set SCSI_In_DBx__DB3__AMUX, CYREG_PRT2_AMUX
-.set SCSI_In_DBx__DB3__BIE, CYREG_PRT2_BIE
-.set SCSI_In_DBx__DB3__BIT_MASK, CYREG_PRT2_BIT_MASK
-.set SCSI_In_DBx__DB3__BYP, CYREG_PRT2_BYP
-.set SCSI_In_DBx__DB3__CTL, CYREG_PRT2_CTL
-.set SCSI_In_DBx__DB3__DM0, CYREG_PRT2_DM0
-.set SCSI_In_DBx__DB3__DM1, CYREG_PRT2_DM1
-.set SCSI_In_DBx__DB3__DM2, CYREG_PRT2_DM2
-.set SCSI_In_DBx__DB3__DR, CYREG_PRT2_DR
-.set SCSI_In_DBx__DB3__INP_DIS, CYREG_PRT2_INP_DIS
-.set SCSI_In_DBx__DB3__INTTYPE, CYREG_PICU2_INTTYPE6
-.set SCSI_In_DBx__DB3__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG
-.set SCSI_In_DBx__DB3__LCD_EN, CYREG_PRT2_LCD_EN
-.set SCSI_In_DBx__DB3__MASK, 0x40
-.set SCSI_In_DBx__DB3__PC, CYREG_PRT2_PC6
-.set SCSI_In_DBx__DB3__PORT, 2
-.set SCSI_In_DBx__DB3__PRT, CYREG_PRT2_PRT
-.set SCSI_In_DBx__DB3__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL
-.set SCSI_In_DBx__DB3__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN
-.set SCSI_In_DBx__DB3__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0
-.set SCSI_In_DBx__DB3__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1
-.set SCSI_In_DBx__DB3__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0
-.set SCSI_In_DBx__DB3__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1
-.set SCSI_In_DBx__DB3__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT
-.set SCSI_In_DBx__DB3__PS, CYREG_PRT2_PS
-.set SCSI_In_DBx__DB3__SHIFT, 6
-.set SCSI_In_DBx__DB3__SLW, CYREG_PRT2_SLW
-.set SCSI_In_DBx__DB4__AG, CYREG_PRT2_AG
-.set SCSI_In_DBx__DB4__AMUX, CYREG_PRT2_AMUX
-.set SCSI_In_DBx__DB4__BIE, CYREG_PRT2_BIE
-.set SCSI_In_DBx__DB4__BIT_MASK, CYREG_PRT2_BIT_MASK
-.set SCSI_In_DBx__DB4__BYP, CYREG_PRT2_BYP
-.set SCSI_In_DBx__DB4__CTL, CYREG_PRT2_CTL
-.set SCSI_In_DBx__DB4__DM0, CYREG_PRT2_DM0
-.set SCSI_In_DBx__DB4__DM1, CYREG_PRT2_DM1
-.set SCSI_In_DBx__DB4__DM2, CYREG_PRT2_DM2
-.set SCSI_In_DBx__DB4__DR, CYREG_PRT2_DR
-.set SCSI_In_DBx__DB4__INP_DIS, CYREG_PRT2_INP_DIS
-.set SCSI_In_DBx__DB4__INTTYPE, CYREG_PICU2_INTTYPE4
-.set SCSI_In_DBx__DB4__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG
-.set SCSI_In_DBx__DB4__LCD_EN, CYREG_PRT2_LCD_EN
-.set SCSI_In_DBx__DB4__MASK, 0x10
-.set SCSI_In_DBx__DB4__PC, CYREG_PRT2_PC4
-.set SCSI_In_DBx__DB4__PORT, 2
-.set SCSI_In_DBx__DB4__PRT, CYREG_PRT2_PRT
-.set SCSI_In_DBx__DB4__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL
-.set SCSI_In_DBx__DB4__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN
-.set SCSI_In_DBx__DB4__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0
-.set SCSI_In_DBx__DB4__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1
-.set SCSI_In_DBx__DB4__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0
-.set SCSI_In_DBx__DB4__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1
-.set SCSI_In_DBx__DB4__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT
-.set SCSI_In_DBx__DB4__PS, CYREG_PRT2_PS
-.set SCSI_In_DBx__DB4__SHIFT, 4
-.set SCSI_In_DBx__DB4__SLW, CYREG_PRT2_SLW
-.set SCSI_In_DBx__DB5__AG, CYREG_PRT2_AG
-.set SCSI_In_DBx__DB5__AMUX, CYREG_PRT2_AMUX
-.set SCSI_In_DBx__DB5__BIE, CYREG_PRT2_BIE
-.set SCSI_In_DBx__DB5__BIT_MASK, CYREG_PRT2_BIT_MASK
-.set SCSI_In_DBx__DB5__BYP, CYREG_PRT2_BYP
-.set SCSI_In_DBx__DB5__CTL, CYREG_PRT2_CTL
-.set SCSI_In_DBx__DB5__DM0, CYREG_PRT2_DM0
-.set SCSI_In_DBx__DB5__DM1, CYREG_PRT2_DM1
-.set SCSI_In_DBx__DB5__DM2, CYREG_PRT2_DM2
-.set SCSI_In_DBx__DB5__DR, CYREG_PRT2_DR
-.set SCSI_In_DBx__DB5__INP_DIS, CYREG_PRT2_INP_DIS
-.set SCSI_In_DBx__DB5__INTTYPE, CYREG_PICU2_INTTYPE2
-.set SCSI_In_DBx__DB5__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG
-.set SCSI_In_DBx__DB5__LCD_EN, CYREG_PRT2_LCD_EN
-.set SCSI_In_DBx__DB5__MASK, 0x04
-.set SCSI_In_DBx__DB5__PC, CYREG_PRT2_PC2
-.set SCSI_In_DBx__DB5__PORT, 2
-.set SCSI_In_DBx__DB5__PRT, CYREG_PRT2_PRT
-.set SCSI_In_DBx__DB5__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL
-.set SCSI_In_DBx__DB5__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN
-.set SCSI_In_DBx__DB5__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0
-.set SCSI_In_DBx__DB5__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1
-.set SCSI_In_DBx__DB5__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0
-.set SCSI_In_DBx__DB5__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1
-.set SCSI_In_DBx__DB5__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT
-.set SCSI_In_DBx__DB5__PS, CYREG_PRT2_PS
-.set SCSI_In_DBx__DB5__SHIFT, 2
-.set SCSI_In_DBx__DB5__SLW, CYREG_PRT2_SLW
-.set SCSI_In_DBx__DB6__AG, CYREG_PRT2_AG
-.set SCSI_In_DBx__DB6__AMUX, CYREG_PRT2_AMUX
-.set SCSI_In_DBx__DB6__BIE, CYREG_PRT2_BIE
-.set SCSI_In_DBx__DB6__BIT_MASK, CYREG_PRT2_BIT_MASK
-.set SCSI_In_DBx__DB6__BYP, CYREG_PRT2_BYP
-.set SCSI_In_DBx__DB6__CTL, CYREG_PRT2_CTL
-.set SCSI_In_DBx__DB6__DM0, CYREG_PRT2_DM0
-.set SCSI_In_DBx__DB6__DM1, CYREG_PRT2_DM1
-.set SCSI_In_DBx__DB6__DM2, CYREG_PRT2_DM2
-.set SCSI_In_DBx__DB6__DR, CYREG_PRT2_DR
-.set SCSI_In_DBx__DB6__INP_DIS, CYREG_PRT2_INP_DIS
-.set SCSI_In_DBx__DB6__INTTYPE, CYREG_PICU2_INTTYPE0
-.set SCSI_In_DBx__DB6__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG
-.set SCSI_In_DBx__DB6__LCD_EN, CYREG_PRT2_LCD_EN
-.set SCSI_In_DBx__DB6__MASK, 0x01
-.set SCSI_In_DBx__DB6__PC, CYREG_PRT2_PC0
-.set SCSI_In_DBx__DB6__PORT, 2
-.set SCSI_In_DBx__DB6__PRT, CYREG_PRT2_PRT
-.set SCSI_In_DBx__DB6__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL
-.set SCSI_In_DBx__DB6__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN
-.set SCSI_In_DBx__DB6__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0
-.set SCSI_In_DBx__DB6__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1
-.set SCSI_In_DBx__DB6__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0
-.set SCSI_In_DBx__DB6__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1
-.set SCSI_In_DBx__DB6__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT
-.set SCSI_In_DBx__DB6__PS, CYREG_PRT2_PS
-.set SCSI_In_DBx__DB6__SHIFT, 0
-.set SCSI_In_DBx__DB6__SLW, CYREG_PRT2_SLW
-.set SCSI_In_DBx__DB7__AG, CYREG_PRT6_AG
-.set SCSI_In_DBx__DB7__AMUX, CYREG_PRT6_AMUX
-.set SCSI_In_DBx__DB7__BIE, CYREG_PRT6_BIE
-.set SCSI_In_DBx__DB7__BIT_MASK, CYREG_PRT6_BIT_MASK
-.set SCSI_In_DBx__DB7__BYP, CYREG_PRT6_BYP
-.set SCSI_In_DBx__DB7__CTL, CYREG_PRT6_CTL
-.set SCSI_In_DBx__DB7__DM0, CYREG_PRT6_DM0
-.set SCSI_In_DBx__DB7__DM1, CYREG_PRT6_DM1
-.set SCSI_In_DBx__DB7__DM2, CYREG_PRT6_DM2
-.set SCSI_In_DBx__DB7__DR, CYREG_PRT6_DR
-.set SCSI_In_DBx__DB7__INP_DIS, CYREG_PRT6_INP_DIS
-.set SCSI_In_DBx__DB7__INTTYPE, CYREG_PICU6_INTTYPE3
-.set SCSI_In_DBx__DB7__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
-.set SCSI_In_DBx__DB7__LCD_EN, CYREG_PRT6_LCD_EN
-.set SCSI_In_DBx__DB7__MASK, 0x08
-.set SCSI_In_DBx__DB7__PC, CYREG_PRT6_PC3
-.set SCSI_In_DBx__DB7__PORT, 6
-.set SCSI_In_DBx__DB7__PRT, CYREG_PRT6_PRT
-.set SCSI_In_DBx__DB7__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL
-.set SCSI_In_DBx__DB7__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN
-.set SCSI_In_DBx__DB7__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0
-.set SCSI_In_DBx__DB7__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1
-.set SCSI_In_DBx__DB7__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0
-.set SCSI_In_DBx__DB7__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1
-.set SCSI_In_DBx__DB7__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT
-.set SCSI_In_DBx__DB7__PS, CYREG_PRT6_PS
-.set SCSI_In_DBx__DB7__SHIFT, 3
-.set SCSI_In_DBx__DB7__SLW, CYREG_PRT6_SLW
-
-/* SD_MISO */
-.set SD_MISO__0__INTTYPE, CYREG_PICU3_INTTYPE2
-.set SD_MISO__0__MASK, 0x04
-.set SD_MISO__0__PC, CYREG_PRT3_PC2
-.set SD_MISO__0__PORT, 3
-.set SD_MISO__0__SHIFT, 2
-.set SD_MISO__AG, CYREG_PRT3_AG
-.set SD_MISO__AMUX, CYREG_PRT3_AMUX
-.set SD_MISO__BIE, CYREG_PRT3_BIE
-.set SD_MISO__BIT_MASK, CYREG_PRT3_BIT_MASK
-.set SD_MISO__BYP, CYREG_PRT3_BYP
-.set SD_MISO__CTL, CYREG_PRT3_CTL
-.set SD_MISO__DM0, CYREG_PRT3_DM0
-.set SD_MISO__DM1, CYREG_PRT3_DM1
-.set SD_MISO__DM2, CYREG_PRT3_DM2
-.set SD_MISO__DR, CYREG_PRT3_DR
-.set SD_MISO__INP_DIS, CYREG_PRT3_INP_DIS
-.set SD_MISO__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU3_BASE
-.set SD_MISO__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG
-.set SD_MISO__LCD_EN, CYREG_PRT3_LCD_EN
-.set SD_MISO__MASK, 0x04
-.set SD_MISO__PORT, 3
-.set SD_MISO__PRT, CYREG_PRT3_PRT
-.set SD_MISO__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL
-.set SD_MISO__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN
-.set SD_MISO__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0
-.set SD_MISO__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1
-.set SD_MISO__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0
-.set SD_MISO__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1
-.set SD_MISO__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT
-.set SD_MISO__PS, CYREG_PRT3_PS
-.set SD_MISO__SHIFT, 2
-.set SD_MISO__SLW, CYREG_PRT3_SLW
-
-/* SD_MOSI */
-.set SD_MOSI__0__INTTYPE, CYREG_PICU3_INTTYPE4
-.set SD_MOSI__0__MASK, 0x10
-.set SD_MOSI__0__PC, CYREG_PRT3_PC4
-.set SD_MOSI__0__PORT, 3
-.set SD_MOSI__0__SHIFT, 4
-.set SD_MOSI__AG, CYREG_PRT3_AG
-.set SD_MOSI__AMUX, CYREG_PRT3_AMUX
-.set SD_MOSI__BIE, CYREG_PRT3_BIE
-.set SD_MOSI__BIT_MASK, CYREG_PRT3_BIT_MASK
-.set SD_MOSI__BYP, CYREG_PRT3_BYP
-.set SD_MOSI__CTL, CYREG_PRT3_CTL
-.set SD_MOSI__DM0, CYREG_PRT3_DM0
-.set SD_MOSI__DM1, CYREG_PRT3_DM1
-.set SD_MOSI__DM2, CYREG_PRT3_DM2
-.set SD_MOSI__DR, CYREG_PRT3_DR
-.set SD_MOSI__INP_DIS, CYREG_PRT3_INP_DIS
-.set SD_MOSI__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU3_BASE
-.set SD_MOSI__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG
-.set SD_MOSI__LCD_EN, CYREG_PRT3_LCD_EN
-.set SD_MOSI__MASK, 0x10
-.set SD_MOSI__PORT, 3
-.set SD_MOSI__PRT, CYREG_PRT3_PRT
-.set SD_MOSI__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL
-.set SD_MOSI__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN
-.set SD_MOSI__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0
-.set SD_MOSI__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1
-.set SD_MOSI__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0
-.set SD_MOSI__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1
-.set SD_MOSI__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT
-.set SD_MOSI__PS, CYREG_PRT3_PS
-.set SD_MOSI__SHIFT, 4
-.set SD_MOSI__SLW, CYREG_PRT3_SLW
-
-/* TERM_EN */
-.set TERM_EN__0__INTTYPE, CYREG_PICU15_INTTYPE3
-.set TERM_EN__0__MASK, 0x08
-.set TERM_EN__0__PC, CYREG_IO_PC_PRT15_PC3
-.set TERM_EN__0__PORT, 15
-.set TERM_EN__0__SHIFT, 3
-.set TERM_EN__AG, CYREG_PRT15_AG
-.set TERM_EN__AMUX, CYREG_PRT15_AMUX
-.set TERM_EN__BIE, CYREG_PRT15_BIE
-.set TERM_EN__BIT_MASK, CYREG_PRT15_BIT_MASK
-.set TERM_EN__BYP, CYREG_PRT15_BYP
-.set TERM_EN__CTL, CYREG_PRT15_CTL
-.set TERM_EN__DM0, CYREG_PRT15_DM0
-.set TERM_EN__DM1, CYREG_PRT15_DM1
-.set TERM_EN__DM2, CYREG_PRT15_DM2
-.set TERM_EN__DR, CYREG_PRT15_DR
-.set TERM_EN__INP_DIS, CYREG_PRT15_INP_DIS
-.set TERM_EN__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU15_BASE
-.set TERM_EN__LCD_COM_SEG, CYREG_PRT15_LCD_COM_SEG
-.set TERM_EN__LCD_EN, CYREG_PRT15_LCD_EN
-.set TERM_EN__MASK, 0x08
-.set TERM_EN__PORT, 15
-.set TERM_EN__PRT, CYREG_PRT15_PRT
-.set TERM_EN__PRTDSI__CAPS_SEL, CYREG_PRT15_CAPS_SEL
-.set TERM_EN__PRTDSI__DBL_SYNC_IN, CYREG_PRT15_DBL_SYNC_IN
-.set TERM_EN__PRTDSI__OE_SEL0, CYREG_PRT15_OE_SEL0
-.set TERM_EN__PRTDSI__OE_SEL1, CYREG_PRT15_OE_SEL1
-.set TERM_EN__PRTDSI__OUT_SEL0, CYREG_PRT15_OUT_SEL0
-.set TERM_EN__PRTDSI__OUT_SEL1, CYREG_PRT15_OUT_SEL1
-.set TERM_EN__PRTDSI__SYNC_OUT, CYREG_PRT15_SYNC_OUT
-.set TERM_EN__PS, CYREG_PRT15_PS
-.set TERM_EN__SHIFT, 3
-.set TERM_EN__SLW, CYREG_PRT15_SLW
-
-/* SCSI_CLK */
-.set SCSI_CLK__CFG0, CYREG_CLKDIST_DCFG1_CFG0
-.set SCSI_CLK__CFG1, CYREG_CLKDIST_DCFG1_CFG1
-.set SCSI_CLK__CFG2, CYREG_CLKDIST_DCFG1_CFG2
-.set SCSI_CLK__CFG2_SRC_SEL_MASK, 0x07
-.set SCSI_CLK__INDEX, 0x01
-.set SCSI_CLK__PM_ACT_CFG, CYREG_PM_ACT_CFG2
-.set SCSI_CLK__PM_ACT_MSK, 0x02
-.set SCSI_CLK__PM_STBY_CFG, CYREG_PM_STBY_CFG2
-.set SCSI_CLK__PM_STBY_MSK, 0x02
-
-/* SCSI_Out */
-.set SCSI_Out__0__AG, CYREG_PRT6_AG
-.set SCSI_Out__0__AMUX, CYREG_PRT6_AMUX
-.set SCSI_Out__0__BIE, CYREG_PRT6_BIE
-.set SCSI_Out__0__BIT_MASK, CYREG_PRT6_BIT_MASK
-.set SCSI_Out__0__BYP, CYREG_PRT6_BYP
-.set SCSI_Out__0__CTL, CYREG_PRT6_CTL
-.set SCSI_Out__0__DM0, CYREG_PRT6_DM0
-.set SCSI_Out__0__DM1, CYREG_PRT6_DM1
-.set SCSI_Out__0__DM2, CYREG_PRT6_DM2
-.set SCSI_Out__0__DR, CYREG_PRT6_DR
-.set SCSI_Out__0__INP_DIS, CYREG_PRT6_INP_DIS
-.set SCSI_Out__0__INTTYPE, CYREG_PICU6_INTTYPE2
-.set SCSI_Out__0__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
-.set SCSI_Out__0__LCD_EN, CYREG_PRT6_LCD_EN
-.set SCSI_Out__0__MASK, 0x04
-.set SCSI_Out__0__PC, CYREG_PRT6_PC2
-.set SCSI_Out__0__PORT, 6
-.set SCSI_Out__0__PRT, CYREG_PRT6_PRT
-.set SCSI_Out__0__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL
-.set SCSI_Out__0__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN
-.set SCSI_Out__0__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0
-.set SCSI_Out__0__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1
-.set SCSI_Out__0__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0
-.set SCSI_Out__0__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1
-.set SCSI_Out__0__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT
-.set SCSI_Out__0__PS, CYREG_PRT6_PS
-.set SCSI_Out__0__SHIFT, 2
-.set SCSI_Out__0__SLW, CYREG_PRT6_SLW
-.set SCSI_Out__1__AG, CYREG_PRT4_AG
-.set SCSI_Out__1__AMUX, CYREG_PRT4_AMUX
-.set SCSI_Out__1__BIE, CYREG_PRT4_BIE
-.set SCSI_Out__1__BIT_MASK, CYREG_PRT4_BIT_MASK
-.set SCSI_Out__1__BYP, CYREG_PRT4_BYP
-.set SCSI_Out__1__CTL, CYREG_PRT4_CTL
-.set SCSI_Out__1__DM0, CYREG_PRT4_DM0
-.set SCSI_Out__1__DM1, CYREG_PRT4_DM1
-.set SCSI_Out__1__DM2, CYREG_PRT4_DM2
-.set SCSI_Out__1__DR, CYREG_PRT4_DR
-.set SCSI_Out__1__INP_DIS, CYREG_PRT4_INP_DIS
-.set SCSI_Out__1__INTTYPE, CYREG_PICU4_INTTYPE6
-.set SCSI_Out__1__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG
-.set SCSI_Out__1__LCD_EN, CYREG_PRT4_LCD_EN
-.set SCSI_Out__1__MASK, 0x40
-.set SCSI_Out__1__PC, CYREG_PRT4_PC6
-.set SCSI_Out__1__PORT, 4
-.set SCSI_Out__1__PRT, CYREG_PRT4_PRT
-.set SCSI_Out__1__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL
-.set SCSI_Out__1__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN
-.set SCSI_Out__1__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0
-.set SCSI_Out__1__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1
-.set SCSI_Out__1__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0
-.set SCSI_Out__1__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1
-.set SCSI_Out__1__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT
-.set SCSI_Out__1__PS, CYREG_PRT4_PS
-.set SCSI_Out__1__SHIFT, 6
-.set SCSI_Out__1__SLW, CYREG_PRT4_SLW
-.set SCSI_Out__2__AG, CYREG_PRT0_AG
-.set SCSI_Out__2__AMUX, CYREG_PRT0_AMUX
-.set SCSI_Out__2__BIE, CYREG_PRT0_BIE
-.set SCSI_Out__2__BIT_MASK, CYREG_PRT0_BIT_MASK
-.set SCSI_Out__2__BYP, CYREG_PRT0_BYP
-.set SCSI_Out__2__CTL, CYREG_PRT0_CTL
-.set SCSI_Out__2__DM0, CYREG_PRT0_DM0
-.set SCSI_Out__2__DM1, CYREG_PRT0_DM1
-.set SCSI_Out__2__DM2, CYREG_PRT0_DM2
-.set SCSI_Out__2__DR, CYREG_PRT0_DR
-.set SCSI_Out__2__INP_DIS, CYREG_PRT0_INP_DIS
-.set SCSI_Out__2__INTTYPE, CYREG_PICU0_INTTYPE7
-.set SCSI_Out__2__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG
-.set SCSI_Out__2__LCD_EN, CYREG_PRT0_LCD_EN
-.set SCSI_Out__2__MASK, 0x80
-.set SCSI_Out__2__PC, CYREG_PRT0_PC7
-.set SCSI_Out__2__PORT, 0
-.set SCSI_Out__2__PRT, CYREG_PRT0_PRT
-.set SCSI_Out__2__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL
-.set SCSI_Out__2__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN
-.set SCSI_Out__2__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0
-.set SCSI_Out__2__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1
-.set SCSI_Out__2__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0
-.set SCSI_Out__2__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1
-.set SCSI_Out__2__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT
-.set SCSI_Out__2__PS, CYREG_PRT0_PS
-.set SCSI_Out__2__SHIFT, 7
-.set SCSI_Out__2__SLW, CYREG_PRT0_SLW
-.set SCSI_Out__3__AG, CYREG_PRT0_AG
-.set SCSI_Out__3__AMUX, CYREG_PRT0_AMUX
-.set SCSI_Out__3__BIE, CYREG_PRT0_BIE
-.set SCSI_Out__3__BIT_MASK, CYREG_PRT0_BIT_MASK
-.set SCSI_Out__3__BYP, CYREG_PRT0_BYP
-.set SCSI_Out__3__CTL, CYREG_PRT0_CTL
-.set SCSI_Out__3__DM0, CYREG_PRT0_DM0
-.set SCSI_Out__3__DM1, CYREG_PRT0_DM1
-.set SCSI_Out__3__DM2, CYREG_PRT0_DM2
-.set SCSI_Out__3__DR, CYREG_PRT0_DR
-.set SCSI_Out__3__INP_DIS, CYREG_PRT0_INP_DIS
-.set SCSI_Out__3__INTTYPE, CYREG_PICU0_INTTYPE5
-.set SCSI_Out__3__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG
-.set SCSI_Out__3__LCD_EN, CYREG_PRT0_LCD_EN
-.set SCSI_Out__3__MASK, 0x20
-.set SCSI_Out__3__PC, CYREG_PRT0_PC5
-.set SCSI_Out__3__PORT, 0
-.set SCSI_Out__3__PRT, CYREG_PRT0_PRT
-.set SCSI_Out__3__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL
-.set SCSI_Out__3__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN
-.set SCSI_Out__3__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0
-.set SCSI_Out__3__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1
-.set SCSI_Out__3__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0
-.set SCSI_Out__3__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1
-.set SCSI_Out__3__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT
-.set SCSI_Out__3__PS, CYREG_PRT0_PS
-.set SCSI_Out__3__SHIFT, 5
-.set SCSI_Out__3__SLW, CYREG_PRT0_SLW
-.set SCSI_Out__4__AG, CYREG_PRT0_AG
-.set SCSI_Out__4__AMUX, CYREG_PRT0_AMUX
-.set SCSI_Out__4__BIE, CYREG_PRT0_BIE
-.set SCSI_Out__4__BIT_MASK, CYREG_PRT0_BIT_MASK
-.set SCSI_Out__4__BYP, CYREG_PRT0_BYP
-.set SCSI_Out__4__CTL, CYREG_PRT0_CTL
-.set SCSI_Out__4__DM0, CYREG_PRT0_DM0
-.set SCSI_Out__4__DM1, CYREG_PRT0_DM1
-.set SCSI_Out__4__DM2, CYREG_PRT0_DM2
-.set SCSI_Out__4__DR, CYREG_PRT0_DR
-.set SCSI_Out__4__INP_DIS, CYREG_PRT0_INP_DIS
-.set SCSI_Out__4__INTTYPE, CYREG_PICU0_INTTYPE3
-.set SCSI_Out__4__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG
-.set SCSI_Out__4__LCD_EN, CYREG_PRT0_LCD_EN
-.set SCSI_Out__4__MASK, 0x08
-.set SCSI_Out__4__PC, CYREG_PRT0_PC3
-.set SCSI_Out__4__PORT, 0
-.set SCSI_Out__4__PRT, CYREG_PRT0_PRT
-.set SCSI_Out__4__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL
-.set SCSI_Out__4__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN
-.set SCSI_Out__4__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0
-.set SCSI_Out__4__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1
-.set SCSI_Out__4__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0
-.set SCSI_Out__4__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1
-.set SCSI_Out__4__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT
-.set SCSI_Out__4__PS, CYREG_PRT0_PS
-.set SCSI_Out__4__SHIFT, 3
-.set SCSI_Out__4__SLW, CYREG_PRT0_SLW
-.set SCSI_Out__5__AG, CYREG_PRT0_AG
-.set SCSI_Out__5__AMUX, CYREG_PRT0_AMUX
-.set SCSI_Out__5__BIE, CYREG_PRT0_BIE
-.set SCSI_Out__5__BIT_MASK, CYREG_PRT0_BIT_MASK
-.set SCSI_Out__5__BYP, CYREG_PRT0_BYP
-.set SCSI_Out__5__CTL, CYREG_PRT0_CTL
-.set SCSI_Out__5__DM0, CYREG_PRT0_DM0
-.set SCSI_Out__5__DM1, CYREG_PRT0_DM1
-.set SCSI_Out__5__DM2, CYREG_PRT0_DM2
-.set SCSI_Out__5__DR, CYREG_PRT0_DR
-.set SCSI_Out__5__INP_DIS, CYREG_PRT0_INP_DIS
-.set SCSI_Out__5__INTTYPE, CYREG_PICU0_INTTYPE1
-.set SCSI_Out__5__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG
-.set SCSI_Out__5__LCD_EN, CYREG_PRT0_LCD_EN
-.set SCSI_Out__5__MASK, 0x02
-.set SCSI_Out__5__PC, CYREG_PRT0_PC1
-.set SCSI_Out__5__PORT, 0
-.set SCSI_Out__5__PRT, CYREG_PRT0_PRT
-.set SCSI_Out__5__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL
-.set SCSI_Out__5__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN
-.set SCSI_Out__5__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0
-.set SCSI_Out__5__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1
-.set SCSI_Out__5__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0
-.set SCSI_Out__5__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1
-.set SCSI_Out__5__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT
-.set SCSI_Out__5__PS, CYREG_PRT0_PS
-.set SCSI_Out__5__SHIFT, 1
-.set SCSI_Out__5__SLW, CYREG_PRT0_SLW
-.set SCSI_Out__6__AG, CYREG_PRT4_AG
-.set SCSI_Out__6__AMUX, CYREG_PRT4_AMUX
-.set SCSI_Out__6__BIE, CYREG_PRT4_BIE
-.set SCSI_Out__6__BIT_MASK, CYREG_PRT4_BIT_MASK
-.set SCSI_Out__6__BYP, CYREG_PRT4_BYP
-.set SCSI_Out__6__CTL, CYREG_PRT4_CTL
-.set SCSI_Out__6__DM0, CYREG_PRT4_DM0
-.set SCSI_Out__6__DM1, CYREG_PRT4_DM1
-.set SCSI_Out__6__DM2, CYREG_PRT4_DM2
-.set SCSI_Out__6__DR, CYREG_PRT4_DR
-.set SCSI_Out__6__INP_DIS, CYREG_PRT4_INP_DIS
-.set SCSI_Out__6__INTTYPE, CYREG_PICU4_INTTYPE1
-.set SCSI_Out__6__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG
-.set SCSI_Out__6__LCD_EN, CYREG_PRT4_LCD_EN
-.set SCSI_Out__6__MASK, 0x02
-.set SCSI_Out__6__PC, CYREG_PRT4_PC1
-.set SCSI_Out__6__PORT, 4
-.set SCSI_Out__6__PRT, CYREG_PRT4_PRT
-.set SCSI_Out__6__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL
-.set SCSI_Out__6__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN
-.set SCSI_Out__6__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0
-.set SCSI_Out__6__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1
-.set SCSI_Out__6__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0
-.set SCSI_Out__6__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1
-.set SCSI_Out__6__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT
-.set SCSI_Out__6__PS, CYREG_PRT4_PS
-.set SCSI_Out__6__SHIFT, 1
-.set SCSI_Out__6__SLW, CYREG_PRT4_SLW
-.set SCSI_Out__7__AG, CYREG_PRT12_AG
-.set SCSI_Out__7__BIE, CYREG_PRT12_BIE
-.set SCSI_Out__7__BIT_MASK, CYREG_PRT12_BIT_MASK
-.set SCSI_Out__7__BYP, CYREG_PRT12_BYP
-.set SCSI_Out__7__DM0, CYREG_PRT12_DM0
-.set SCSI_Out__7__DM1, CYREG_PRT12_DM1
-.set SCSI_Out__7__DM2, CYREG_PRT12_DM2
-.set SCSI_Out__7__DR, CYREG_PRT12_DR
-.set SCSI_Out__7__INP_DIS, CYREG_PRT12_INP_DIS
-.set SCSI_Out__7__INTTYPE, CYREG_PICU12_INTTYPE3
-.set SCSI_Out__7__MASK, 0x08
-.set SCSI_Out__7__PC, CYREG_PRT12_PC3
-.set SCSI_Out__7__PORT, 12
-.set SCSI_Out__7__PRT, CYREG_PRT12_PRT
-.set SCSI_Out__7__PRTDSI__DBL_SYNC_IN, CYREG_PRT12_DBL_SYNC_IN
-.set SCSI_Out__7__PRTDSI__OE_SEL0, CYREG_PRT12_OE_SEL0
-.set SCSI_Out__7__PRTDSI__OE_SEL1, CYREG_PRT12_OE_SEL1
-.set SCSI_Out__7__PRTDSI__OUT_SEL0, CYREG_PRT12_OUT_SEL0
-.set SCSI_Out__7__PRTDSI__OUT_SEL1, CYREG_PRT12_OUT_SEL1
-.set SCSI_Out__7__PRTDSI__SYNC_OUT, CYREG_PRT12_SYNC_OUT
-.set SCSI_Out__7__PS, CYREG_PRT12_PS
-.set SCSI_Out__7__SHIFT, 3
-.set SCSI_Out__7__SIO_CFG, CYREG_PRT12_SIO_CFG
-.set SCSI_Out__7__SIO_DIFF, CYREG_PRT12_SIO_DIFF
-.set SCSI_Out__7__SIO_HYST_EN, CYREG_PRT12_SIO_HYST_EN
-.set SCSI_Out__7__SIO_REG_HIFREQ, CYREG_PRT12_SIO_REG_HIFREQ
-.set SCSI_Out__7__SLW, CYREG_PRT12_SLW
-.set SCSI_Out__BSY__AG, CYREG_PRT4_AG
-.set SCSI_Out__BSY__AMUX, CYREG_PRT4_AMUX
-.set SCSI_Out__BSY__BIE, CYREG_PRT4_BIE
-.set SCSI_Out__BSY__BIT_MASK, CYREG_PRT4_BIT_MASK
-.set SCSI_Out__BSY__BYP, CYREG_PRT4_BYP
-.set SCSI_Out__BSY__CTL, CYREG_PRT4_CTL
-.set SCSI_Out__BSY__DM0, CYREG_PRT4_DM0
-.set SCSI_Out__BSY__DM1, CYREG_PRT4_DM1
-.set SCSI_Out__BSY__DM2, CYREG_PRT4_DM2
-.set SCSI_Out__BSY__DR, CYREG_PRT4_DR
-.set SCSI_Out__BSY__INP_DIS, CYREG_PRT4_INP_DIS
-.set SCSI_Out__BSY__INTTYPE, CYREG_PICU4_INTTYPE6
-.set SCSI_Out__BSY__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG
-.set SCSI_Out__BSY__LCD_EN, CYREG_PRT4_LCD_EN
-.set SCSI_Out__BSY__MASK, 0x40
-.set SCSI_Out__BSY__PC, CYREG_PRT4_PC6
-.set SCSI_Out__BSY__PORT, 4
-.set SCSI_Out__BSY__PRT, CYREG_PRT4_PRT
-.set SCSI_Out__BSY__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL
-.set SCSI_Out__BSY__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN
-.set SCSI_Out__BSY__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0
-.set SCSI_Out__BSY__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1
-.set SCSI_Out__BSY__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0
-.set SCSI_Out__BSY__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1
-.set SCSI_Out__BSY__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT
-.set SCSI_Out__BSY__PS, CYREG_PRT4_PS
-.set SCSI_Out__BSY__SHIFT, 6
-.set SCSI_Out__BSY__SLW, CYREG_PRT4_SLW
-.set SCSI_Out__CD_raw__AG, CYREG_PRT0_AG
-.set SCSI_Out__CD_raw__AMUX, CYREG_PRT0_AMUX
-.set SCSI_Out__CD_raw__BIE, CYREG_PRT0_BIE
-.set SCSI_Out__CD_raw__BIT_MASK, CYREG_PRT0_BIT_MASK
-.set SCSI_Out__CD_raw__BYP, CYREG_PRT0_BYP
-.set SCSI_Out__CD_raw__CTL, CYREG_PRT0_CTL
-.set SCSI_Out__CD_raw__DM0, CYREG_PRT0_DM0
-.set SCSI_Out__CD_raw__DM1, CYREG_PRT0_DM1
-.set SCSI_Out__CD_raw__DM2, CYREG_PRT0_DM2
-.set SCSI_Out__CD_raw__DR, CYREG_PRT0_DR
-.set SCSI_Out__CD_raw__INP_DIS, CYREG_PRT0_INP_DIS
-.set SCSI_Out__CD_raw__INTTYPE, CYREG_PICU0_INTTYPE1
-.set SCSI_Out__CD_raw__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG
-.set SCSI_Out__CD_raw__LCD_EN, CYREG_PRT0_LCD_EN
-.set SCSI_Out__CD_raw__MASK, 0x02
-.set SCSI_Out__CD_raw__PC, CYREG_PRT0_PC1
-.set SCSI_Out__CD_raw__PORT, 0
-.set SCSI_Out__CD_raw__PRT, CYREG_PRT0_PRT
-.set SCSI_Out__CD_raw__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL
-.set SCSI_Out__CD_raw__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN
-.set SCSI_Out__CD_raw__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0
-.set SCSI_Out__CD_raw__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1
-.set SCSI_Out__CD_raw__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0
-.set SCSI_Out__CD_raw__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1
-.set SCSI_Out__CD_raw__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT
-.set SCSI_Out__CD_raw__PS, CYREG_PRT0_PS
-.set SCSI_Out__CD_raw__SHIFT, 1
-.set SCSI_Out__CD_raw__SLW, CYREG_PRT0_SLW
-.set SCSI_Out__DBP_raw__AG, CYREG_PRT6_AG
-.set SCSI_Out__DBP_raw__AMUX, CYREG_PRT6_AMUX
-.set SCSI_Out__DBP_raw__BIE, CYREG_PRT6_BIE
-.set SCSI_Out__DBP_raw__BIT_MASK, CYREG_PRT6_BIT_MASK
-.set SCSI_Out__DBP_raw__BYP, CYREG_PRT6_BYP
-.set SCSI_Out__DBP_raw__CTL, CYREG_PRT6_CTL
-.set SCSI_Out__DBP_raw__DM0, CYREG_PRT6_DM0
-.set SCSI_Out__DBP_raw__DM1, CYREG_PRT6_DM1
-.set SCSI_Out__DBP_raw__DM2, CYREG_PRT6_DM2
-.set SCSI_Out__DBP_raw__DR, CYREG_PRT6_DR
-.set SCSI_Out__DBP_raw__INP_DIS, CYREG_PRT6_INP_DIS
-.set SCSI_Out__DBP_raw__INTTYPE, CYREG_PICU6_INTTYPE2
-.set SCSI_Out__DBP_raw__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
-.set SCSI_Out__DBP_raw__LCD_EN, CYREG_PRT6_LCD_EN
-.set SCSI_Out__DBP_raw__MASK, 0x04
-.set SCSI_Out__DBP_raw__PC, CYREG_PRT6_PC2
-.set SCSI_Out__DBP_raw__PORT, 6
-.set SCSI_Out__DBP_raw__PRT, CYREG_PRT6_PRT
-.set SCSI_Out__DBP_raw__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL
-.set SCSI_Out__DBP_raw__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN
-.set SCSI_Out__DBP_raw__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0
-.set SCSI_Out__DBP_raw__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1
-.set SCSI_Out__DBP_raw__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0
-.set SCSI_Out__DBP_raw__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1
-.set SCSI_Out__DBP_raw__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT
-.set SCSI_Out__DBP_raw__PS, CYREG_PRT6_PS
-.set SCSI_Out__DBP_raw__SHIFT, 2
-.set SCSI_Out__DBP_raw__SLW, CYREG_PRT6_SLW
-.set SCSI_Out__IO_raw__AG, CYREG_PRT12_AG
-.set SCSI_Out__IO_raw__BIE, CYREG_PRT12_BIE
-.set SCSI_Out__IO_raw__BIT_MASK, CYREG_PRT12_BIT_MASK
-.set SCSI_Out__IO_raw__BYP, CYREG_PRT12_BYP
-.set SCSI_Out__IO_raw__DM0, CYREG_PRT12_DM0
-.set SCSI_Out__IO_raw__DM1, CYREG_PRT12_DM1
-.set SCSI_Out__IO_raw__DM2, CYREG_PRT12_DM2
-.set SCSI_Out__IO_raw__DR, CYREG_PRT12_DR
-.set SCSI_Out__IO_raw__INP_DIS, CYREG_PRT12_INP_DIS
-.set SCSI_Out__IO_raw__INTTYPE, CYREG_PICU12_INTTYPE3
-.set SCSI_Out__IO_raw__MASK, 0x08
-.set SCSI_Out__IO_raw__PC, CYREG_PRT12_PC3
-.set SCSI_Out__IO_raw__PORT, 12
-.set SCSI_Out__IO_raw__PRT, CYREG_PRT12_PRT
-.set SCSI_Out__IO_raw__PRTDSI__DBL_SYNC_IN, CYREG_PRT12_DBL_SYNC_IN
-.set SCSI_Out__IO_raw__PRTDSI__OE_SEL0, CYREG_PRT12_OE_SEL0
-.set SCSI_Out__IO_raw__PRTDSI__OE_SEL1, CYREG_PRT12_OE_SEL1
-.set SCSI_Out__IO_raw__PRTDSI__OUT_SEL0, CYREG_PRT12_OUT_SEL0
-.set SCSI_Out__IO_raw__PRTDSI__OUT_SEL1, CYREG_PRT12_OUT_SEL1
-.set SCSI_Out__IO_raw__PRTDSI__SYNC_OUT, CYREG_PRT12_SYNC_OUT
-.set SCSI_Out__IO_raw__PS, CYREG_PRT12_PS
-.set SCSI_Out__IO_raw__SHIFT, 3
-.set SCSI_Out__IO_raw__SIO_CFG, CYREG_PRT12_SIO_CFG
-.set SCSI_Out__IO_raw__SIO_DIFF, CYREG_PRT12_SIO_DIFF
-.set SCSI_Out__IO_raw__SIO_HYST_EN, CYREG_PRT12_SIO_HYST_EN
-.set SCSI_Out__IO_raw__SIO_REG_HIFREQ, CYREG_PRT12_SIO_REG_HIFREQ
-.set SCSI_Out__IO_raw__SLW, CYREG_PRT12_SLW
-.set SCSI_Out__MSG_raw__AG, CYREG_PRT0_AG
-.set SCSI_Out__MSG_raw__AMUX, CYREG_PRT0_AMUX
-.set SCSI_Out__MSG_raw__BIE, CYREG_PRT0_BIE
-.set SCSI_Out__MSG_raw__BIT_MASK, CYREG_PRT0_BIT_MASK
-.set SCSI_Out__MSG_raw__BYP, CYREG_PRT0_BYP
-.set SCSI_Out__MSG_raw__CTL, CYREG_PRT0_CTL
-.set SCSI_Out__MSG_raw__DM0, CYREG_PRT0_DM0
-.set SCSI_Out__MSG_raw__DM1, CYREG_PRT0_DM1
-.set SCSI_Out__MSG_raw__DM2, CYREG_PRT0_DM2
-.set SCSI_Out__MSG_raw__DR, CYREG_PRT0_DR
-.set SCSI_Out__MSG_raw__INP_DIS, CYREG_PRT0_INP_DIS
-.set SCSI_Out__MSG_raw__INTTYPE, CYREG_PICU0_INTTYPE5
-.set SCSI_Out__MSG_raw__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG
-.set SCSI_Out__MSG_raw__LCD_EN, CYREG_PRT0_LCD_EN
-.set SCSI_Out__MSG_raw__MASK, 0x20
-.set SCSI_Out__MSG_raw__PC, CYREG_PRT0_PC5
-.set SCSI_Out__MSG_raw__PORT, 0
-.set SCSI_Out__MSG_raw__PRT, CYREG_PRT0_PRT
-.set SCSI_Out__MSG_raw__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL
-.set SCSI_Out__MSG_raw__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN
-.set SCSI_Out__MSG_raw__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0
-.set SCSI_Out__MSG_raw__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1
-.set SCSI_Out__MSG_raw__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0
-.set SCSI_Out__MSG_raw__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1
-.set SCSI_Out__MSG_raw__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT
-.set SCSI_Out__MSG_raw__PS, CYREG_PRT0_PS
-.set SCSI_Out__MSG_raw__SHIFT, 5
-.set SCSI_Out__MSG_raw__SLW, CYREG_PRT0_SLW
-.set SCSI_Out__REQ__AG, CYREG_PRT4_AG
-.set SCSI_Out__REQ__AMUX, CYREG_PRT4_AMUX
-.set SCSI_Out__REQ__BIE, CYREG_PRT4_BIE
-.set SCSI_Out__REQ__BIT_MASK, CYREG_PRT4_BIT_MASK
-.set SCSI_Out__REQ__BYP, CYREG_PRT4_BYP
-.set SCSI_Out__REQ__CTL, CYREG_PRT4_CTL
-.set SCSI_Out__REQ__DM0, CYREG_PRT4_DM0
-.set SCSI_Out__REQ__DM1, CYREG_PRT4_DM1
-.set SCSI_Out__REQ__DM2, CYREG_PRT4_DM2
-.set SCSI_Out__REQ__DR, CYREG_PRT4_DR
-.set SCSI_Out__REQ__INP_DIS, CYREG_PRT4_INP_DIS
-.set SCSI_Out__REQ__INTTYPE, CYREG_PICU4_INTTYPE1
-.set SCSI_Out__REQ__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG
-.set SCSI_Out__REQ__LCD_EN, CYREG_PRT4_LCD_EN
-.set SCSI_Out__REQ__MASK, 0x02
-.set SCSI_Out__REQ__PC, CYREG_PRT4_PC1
-.set SCSI_Out__REQ__PORT, 4
-.set SCSI_Out__REQ__PRT, CYREG_PRT4_PRT
-.set SCSI_Out__REQ__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL
-.set SCSI_Out__REQ__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN
-.set SCSI_Out__REQ__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0
-.set SCSI_Out__REQ__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1
-.set SCSI_Out__REQ__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0
-.set SCSI_Out__REQ__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1
-.set SCSI_Out__REQ__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT
-.set SCSI_Out__REQ__PS, CYREG_PRT4_PS
-.set SCSI_Out__REQ__SHIFT, 1
-.set SCSI_Out__REQ__SLW, CYREG_PRT4_SLW
-.set SCSI_Out__RST__AG, CYREG_PRT0_AG
-.set SCSI_Out__RST__AMUX, CYREG_PRT0_AMUX
-.set SCSI_Out__RST__BIE, CYREG_PRT0_BIE
-.set SCSI_Out__RST__BIT_MASK, CYREG_PRT0_BIT_MASK
-.set SCSI_Out__RST__BYP, CYREG_PRT0_BYP
-.set SCSI_Out__RST__CTL, CYREG_PRT0_CTL
-.set SCSI_Out__RST__DM0, CYREG_PRT0_DM0
-.set SCSI_Out__RST__DM1, CYREG_PRT0_DM1
-.set SCSI_Out__RST__DM2, CYREG_PRT0_DM2
-.set SCSI_Out__RST__DR, CYREG_PRT0_DR
-.set SCSI_Out__RST__INP_DIS, CYREG_PRT0_INP_DIS
-.set SCSI_Out__RST__INTTYPE, CYREG_PICU0_INTTYPE7
-.set SCSI_Out__RST__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG
-.set SCSI_Out__RST__LCD_EN, CYREG_PRT0_LCD_EN
-.set SCSI_Out__RST__MASK, 0x80
-.set SCSI_Out__RST__PC, CYREG_PRT0_PC7
-.set SCSI_Out__RST__PORT, 0
-.set SCSI_Out__RST__PRT, CYREG_PRT0_PRT
-.set SCSI_Out__RST__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL
-.set SCSI_Out__RST__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN
-.set SCSI_Out__RST__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0
-.set SCSI_Out__RST__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1
-.set SCSI_Out__RST__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0
-.set SCSI_Out__RST__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1
-.set SCSI_Out__RST__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT
-.set SCSI_Out__RST__PS, CYREG_PRT0_PS
-.set SCSI_Out__RST__SHIFT, 7
-.set SCSI_Out__RST__SLW, CYREG_PRT0_SLW
-.set SCSI_Out__SEL__AG, CYREG_PRT0_AG
-.set SCSI_Out__SEL__AMUX, CYREG_PRT0_AMUX
-.set SCSI_Out__SEL__BIE, CYREG_PRT0_BIE
-.set SCSI_Out__SEL__BIT_MASK, CYREG_PRT0_BIT_MASK
-.set SCSI_Out__SEL__BYP, CYREG_PRT0_BYP
-.set SCSI_Out__SEL__CTL, CYREG_PRT0_CTL
-.set SCSI_Out__SEL__DM0, CYREG_PRT0_DM0
-.set SCSI_Out__SEL__DM1, CYREG_PRT0_DM1
-.set SCSI_Out__SEL__DM2, CYREG_PRT0_DM2
-.set SCSI_Out__SEL__DR, CYREG_PRT0_DR
-.set SCSI_Out__SEL__INP_DIS, CYREG_PRT0_INP_DIS
-.set SCSI_Out__SEL__INTTYPE, CYREG_PICU0_INTTYPE3
-.set SCSI_Out__SEL__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG
-.set SCSI_Out__SEL__LCD_EN, CYREG_PRT0_LCD_EN
-.set SCSI_Out__SEL__MASK, 0x08
-.set SCSI_Out__SEL__PC, CYREG_PRT0_PC3
-.set SCSI_Out__SEL__PORT, 0
-.set SCSI_Out__SEL__PRT, CYREG_PRT0_PRT
-.set SCSI_Out__SEL__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL
-.set SCSI_Out__SEL__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN
-.set SCSI_Out__SEL__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0
-.set SCSI_Out__SEL__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1
-.set SCSI_Out__SEL__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0
-.set SCSI_Out__SEL__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1
-.set SCSI_Out__SEL__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT
-.set SCSI_Out__SEL__PS, CYREG_PRT0_PS
-.set SCSI_Out__SEL__SHIFT, 3
-.set SCSI_Out__SEL__SLW, CYREG_PRT0_SLW
-
-/* SCSI_Out_Bits */
-.set SCSI_Out_Bits_Sync_ctrl_reg__0__MASK, 0x01
-.set SCSI_Out_Bits_Sync_ctrl_reg__0__POS, 0
-.set SCSI_Out_Bits_Sync_ctrl_reg__1__MASK, 0x02
-.set SCSI_Out_Bits_Sync_ctrl_reg__1__POS, 1
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB07_08_ACTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB07_08_CTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB07_08_CTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB07_08_CTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB07_08_CTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB07_08_MSK
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB07_08_MSK
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB07_08_MSK
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB07_08_MSK
-.set SCSI_Out_Bits_Sync_ctrl_reg__2__MASK, 0x04
-.set SCSI_Out_Bits_Sync_ctrl_reg__2__POS, 2
-.set SCSI_Out_Bits_Sync_ctrl_reg__3__MASK, 0x08
-.set SCSI_Out_Bits_Sync_ctrl_reg__3__POS, 3
-.set SCSI_Out_Bits_Sync_ctrl_reg__4__MASK, 0x10
-.set SCSI_Out_Bits_Sync_ctrl_reg__4__POS, 4
-.set SCSI_Out_Bits_Sync_ctrl_reg__5__MASK, 0x20
-.set SCSI_Out_Bits_Sync_ctrl_reg__5__POS, 5
-.set SCSI_Out_Bits_Sync_ctrl_reg__6__MASK, 0x40
-.set SCSI_Out_Bits_Sync_ctrl_reg__6__POS, 6
-.set SCSI_Out_Bits_Sync_ctrl_reg__7__MASK, 0x80
-.set SCSI_Out_Bits_Sync_ctrl_reg__7__POS, 7
-.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB07_ACTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB07_CTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB07_ST_CTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB07_CTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB07_ST_CTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__MASK, 0xFF
-.set SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB07_MSK_ACTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB07_MSK_ACTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB07_MSK
-
-/* SCSI_Out_Ctl */
-.set SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK, 0x01
-.set SCSI_Out_Ctl_Sync_ctrl_reg__0__POS, 0
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB11_12_ACTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB11_12_CTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB11_12_CTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB11_12_CTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB11_12_CTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB11_12_MSK
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB11_12_MSK
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB11_12_MSK
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB11_12_MSK
-.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB11_ACTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB11_CTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB11_ST_CTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB11_CTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB11_ST_CTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK, 0x01
-.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB11_MSK
-
-/* SCSI_Out_DBx */
-.set SCSI_Out_DBx__0__AG, CYREG_PRT6_AG
-.set SCSI_Out_DBx__0__AMUX, CYREG_PRT6_AMUX
-.set SCSI_Out_DBx__0__BIE, CYREG_PRT6_BIE
-.set SCSI_Out_DBx__0__BIT_MASK, CYREG_PRT6_BIT_MASK
-.set SCSI_Out_DBx__0__BYP, CYREG_PRT6_BYP
-.set SCSI_Out_DBx__0__CTL, CYREG_PRT6_CTL
-.set SCSI_Out_DBx__0__DM0, CYREG_PRT6_DM0
-.set SCSI_Out_DBx__0__DM1, CYREG_PRT6_DM1
-.set SCSI_Out_DBx__0__DM2, CYREG_PRT6_DM2
-.set SCSI_Out_DBx__0__DR, CYREG_PRT6_DR
-.set SCSI_Out_DBx__0__INP_DIS, CYREG_PRT6_INP_DIS
-.set SCSI_Out_DBx__0__INTTYPE, CYREG_PICU6_INTTYPE7
-.set SCSI_Out_DBx__0__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
-.set SCSI_Out_DBx__0__LCD_EN, CYREG_PRT6_LCD_EN
-.set SCSI_Out_DBx__0__MASK, 0x80
-.set SCSI_Out_DBx__0__PC, CYREG_PRT6_PC7
-.set SCSI_Out_DBx__0__PORT, 6
-.set SCSI_Out_DBx__0__PRT, CYREG_PRT6_PRT
-.set SCSI_Out_DBx__0__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL
-.set SCSI_Out_DBx__0__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN
-.set SCSI_Out_DBx__0__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0
-.set SCSI_Out_DBx__0__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1
-.set SCSI_Out_DBx__0__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0
-.set SCSI_Out_DBx__0__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1
-.set SCSI_Out_DBx__0__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT
-.set SCSI_Out_DBx__0__PS, CYREG_PRT6_PS
-.set SCSI_Out_DBx__0__SHIFT, 7
-.set SCSI_Out_DBx__0__SLW, CYREG_PRT6_SLW
-.set SCSI_Out_DBx__1__AG, CYREG_PRT6_AG
-.set SCSI_Out_DBx__1__AMUX, CYREG_PRT6_AMUX
-.set SCSI_Out_DBx__1__BIE, CYREG_PRT6_BIE
-.set SCSI_Out_DBx__1__BIT_MASK, CYREG_PRT6_BIT_MASK
-.set SCSI_Out_DBx__1__BYP, CYREG_PRT6_BYP
-.set SCSI_Out_DBx__1__CTL, CYREG_PRT6_CTL
-.set SCSI_Out_DBx__1__DM0, CYREG_PRT6_DM0
-.set SCSI_Out_DBx__1__DM1, CYREG_PRT6_DM1
-.set SCSI_Out_DBx__1__DM2, CYREG_PRT6_DM2
-.set SCSI_Out_DBx__1__DR, CYREG_PRT6_DR
-.set SCSI_Out_DBx__1__INP_DIS, CYREG_PRT6_INP_DIS
-.set SCSI_Out_DBx__1__INTTYPE, CYREG_PICU6_INTTYPE5
-.set SCSI_Out_DBx__1__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
-.set SCSI_Out_DBx__1__LCD_EN, CYREG_PRT6_LCD_EN
-.set SCSI_Out_DBx__1__MASK, 0x20
-.set SCSI_Out_DBx__1__PC, CYREG_PRT6_PC5
-.set SCSI_Out_DBx__1__PORT, 6
-.set SCSI_Out_DBx__1__PRT, CYREG_PRT6_PRT
-.set SCSI_Out_DBx__1__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL
-.set SCSI_Out_DBx__1__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN
-.set SCSI_Out_DBx__1__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0
-.set SCSI_Out_DBx__1__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1
-.set SCSI_Out_DBx__1__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0
-.set SCSI_Out_DBx__1__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1
-.set SCSI_Out_DBx__1__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT
-.set SCSI_Out_DBx__1__PS, CYREG_PRT6_PS
-.set SCSI_Out_DBx__1__SHIFT, 5
-.set SCSI_Out_DBx__1__SLW, CYREG_PRT6_SLW
-.set SCSI_Out_DBx__2__AG, CYREG_PRT12_AG
-.set SCSI_Out_DBx__2__BIE, CYREG_PRT12_BIE
-.set SCSI_Out_DBx__2__BIT_MASK, CYREG_PRT12_BIT_MASK
-.set SCSI_Out_DBx__2__BYP, CYREG_PRT12_BYP
-.set SCSI_Out_DBx__2__DM0, CYREG_PRT12_DM0
-.set SCSI_Out_DBx__2__DM1, CYREG_PRT12_DM1
-.set SCSI_Out_DBx__2__DM2, CYREG_PRT12_DM2
-.set SCSI_Out_DBx__2__DR, CYREG_PRT12_DR
-.set SCSI_Out_DBx__2__INP_DIS, CYREG_PRT12_INP_DIS
-.set SCSI_Out_DBx__2__INTTYPE, CYREG_PICU12_INTTYPE5
-.set SCSI_Out_DBx__2__MASK, 0x20
-.set SCSI_Out_DBx__2__PC, CYREG_PRT12_PC5
-.set SCSI_Out_DBx__2__PORT, 12
-.set SCSI_Out_DBx__2__PRT, CYREG_PRT12_PRT
-.set SCSI_Out_DBx__2__PRTDSI__DBL_SYNC_IN, CYREG_PRT12_DBL_SYNC_IN
-.set SCSI_Out_DBx__2__PRTDSI__OE_SEL0, CYREG_PRT12_OE_SEL0
-.set SCSI_Out_DBx__2__PRTDSI__OE_SEL1, CYREG_PRT12_OE_SEL1
-.set SCSI_Out_DBx__2__PRTDSI__OUT_SEL0, CYREG_PRT12_OUT_SEL0
-.set SCSI_Out_DBx__2__PRTDSI__OUT_SEL1, CYREG_PRT12_OUT_SEL1
-.set SCSI_Out_DBx__2__PRTDSI__SYNC_OUT, CYREG_PRT12_SYNC_OUT
-.set SCSI_Out_DBx__2__PS, CYREG_PRT12_PS
-.set SCSI_Out_DBx__2__SHIFT, 5
-.set SCSI_Out_DBx__2__SIO_CFG, CYREG_PRT12_SIO_CFG
-.set SCSI_Out_DBx__2__SIO_DIFF, CYREG_PRT12_SIO_DIFF
-.set SCSI_Out_DBx__2__SIO_HYST_EN, CYREG_PRT12_SIO_HYST_EN
-.set SCSI_Out_DBx__2__SIO_REG_HIFREQ, CYREG_PRT12_SIO_REG_HIFREQ
-.set SCSI_Out_DBx__2__SLW, CYREG_PRT12_SLW
-.set SCSI_Out_DBx__3__AG, CYREG_PRT2_AG
-.set SCSI_Out_DBx__3__AMUX, CYREG_PRT2_AMUX
-.set SCSI_Out_DBx__3__BIE, CYREG_PRT2_BIE
-.set SCSI_Out_DBx__3__BIT_MASK, CYREG_PRT2_BIT_MASK
-.set SCSI_Out_DBx__3__BYP, CYREG_PRT2_BYP
-.set SCSI_Out_DBx__3__CTL, CYREG_PRT2_CTL
-.set SCSI_Out_DBx__3__DM0, CYREG_PRT2_DM0
-.set SCSI_Out_DBx__3__DM1, CYREG_PRT2_DM1
-.set SCSI_Out_DBx__3__DM2, CYREG_PRT2_DM2
-.set SCSI_Out_DBx__3__DR, CYREG_PRT2_DR
-.set SCSI_Out_DBx__3__INP_DIS, CYREG_PRT2_INP_DIS
-.set SCSI_Out_DBx__3__INTTYPE, CYREG_PICU2_INTTYPE7
-.set SCSI_Out_DBx__3__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG
-.set SCSI_Out_DBx__3__LCD_EN, CYREG_PRT2_LCD_EN
-.set SCSI_Out_DBx__3__MASK, 0x80
-.set SCSI_Out_DBx__3__PC, CYREG_PRT2_PC7
-.set SCSI_Out_DBx__3__PORT, 2
-.set SCSI_Out_DBx__3__PRT, CYREG_PRT2_PRT
-.set SCSI_Out_DBx__3__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL
-.set SCSI_Out_DBx__3__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN
-.set SCSI_Out_DBx__3__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0
-.set SCSI_Out_DBx__3__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1
-.set SCSI_Out_DBx__3__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0
-.set SCSI_Out_DBx__3__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1
-.set SCSI_Out_DBx__3__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT
-.set SCSI_Out_DBx__3__PS, CYREG_PRT2_PS
-.set SCSI_Out_DBx__3__SHIFT, 7
-.set SCSI_Out_DBx__3__SLW, CYREG_PRT2_SLW
-.set SCSI_Out_DBx__4__AG, CYREG_PRT2_AG
-.set SCSI_Out_DBx__4__AMUX, CYREG_PRT2_AMUX
-.set SCSI_Out_DBx__4__BIE, CYREG_PRT2_BIE
-.set SCSI_Out_DBx__4__BIT_MASK, CYREG_PRT2_BIT_MASK
-.set SCSI_Out_DBx__4__BYP, CYREG_PRT2_BYP
-.set SCSI_Out_DBx__4__CTL, CYREG_PRT2_CTL
-.set SCSI_Out_DBx__4__DM0, CYREG_PRT2_DM0
-.set SCSI_Out_DBx__4__DM1, CYREG_PRT2_DM1
-.set SCSI_Out_DBx__4__DM2, CYREG_PRT2_DM2
-.set SCSI_Out_DBx__4__DR, CYREG_PRT2_DR
-.set SCSI_Out_DBx__4__INP_DIS, CYREG_PRT2_INP_DIS
-.set SCSI_Out_DBx__4__INTTYPE, CYREG_PICU2_INTTYPE5
-.set SCSI_Out_DBx__4__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG
-.set SCSI_Out_DBx__4__LCD_EN, CYREG_PRT2_LCD_EN
-.set SCSI_Out_DBx__4__MASK, 0x20
-.set SCSI_Out_DBx__4__PC, CYREG_PRT2_PC5
-.set SCSI_Out_DBx__4__PORT, 2
-.set SCSI_Out_DBx__4__PRT, CYREG_PRT2_PRT
-.set SCSI_Out_DBx__4__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL
-.set SCSI_Out_DBx__4__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN
-.set SCSI_Out_DBx__4__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0
-.set SCSI_Out_DBx__4__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1
-.set SCSI_Out_DBx__4__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0
-.set SCSI_Out_DBx__4__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1
-.set SCSI_Out_DBx__4__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT
-.set SCSI_Out_DBx__4__PS, CYREG_PRT2_PS
-.set SCSI_Out_DBx__4__SHIFT, 5
-.set SCSI_Out_DBx__4__SLW, CYREG_PRT2_SLW
-.set SCSI_Out_DBx__5__AG, CYREG_PRT2_AG
-.set SCSI_Out_DBx__5__AMUX, CYREG_PRT2_AMUX
-.set SCSI_Out_DBx__5__BIE, CYREG_PRT2_BIE
-.set SCSI_Out_DBx__5__BIT_MASK, CYREG_PRT2_BIT_MASK
-.set SCSI_Out_DBx__5__BYP, CYREG_PRT2_BYP
-.set SCSI_Out_DBx__5__CTL, CYREG_PRT2_CTL
-.set SCSI_Out_DBx__5__DM0, CYREG_PRT2_DM0
-.set SCSI_Out_DBx__5__DM1, CYREG_PRT2_DM1
-.set SCSI_Out_DBx__5__DM2, CYREG_PRT2_DM2
-.set SCSI_Out_DBx__5__DR, CYREG_PRT2_DR
-.set SCSI_Out_DBx__5__INP_DIS, CYREG_PRT2_INP_DIS
-.set SCSI_Out_DBx__5__INTTYPE, CYREG_PICU2_INTTYPE3
-.set SCSI_Out_DBx__5__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG
-.set SCSI_Out_DBx__5__LCD_EN, CYREG_PRT2_LCD_EN
-.set SCSI_Out_DBx__5__MASK, 0x08
-.set SCSI_Out_DBx__5__PC, CYREG_PRT2_PC3
-.set SCSI_Out_DBx__5__PORT, 2
-.set SCSI_Out_DBx__5__PRT, CYREG_PRT2_PRT
-.set SCSI_Out_DBx__5__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL
-.set SCSI_Out_DBx__5__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN
-.set SCSI_Out_DBx__5__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0
-.set SCSI_Out_DBx__5__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1
-.set SCSI_Out_DBx__5__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0
-.set SCSI_Out_DBx__5__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1
-.set SCSI_Out_DBx__5__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT
-.set SCSI_Out_DBx__5__PS, CYREG_PRT2_PS
-.set SCSI_Out_DBx__5__SHIFT, 3
-.set SCSI_Out_DBx__5__SLW, CYREG_PRT2_SLW
-.set SCSI_Out_DBx__6__AG, CYREG_PRT2_AG
-.set SCSI_Out_DBx__6__AMUX, CYREG_PRT2_AMUX
-.set SCSI_Out_DBx__6__BIE, CYREG_PRT2_BIE
-.set SCSI_Out_DBx__6__BIT_MASK, CYREG_PRT2_BIT_MASK
-.set SCSI_Out_DBx__6__BYP, CYREG_PRT2_BYP
-.set SCSI_Out_DBx__6__CTL, CYREG_PRT2_CTL
-.set SCSI_Out_DBx__6__DM0, CYREG_PRT2_DM0
-.set SCSI_Out_DBx__6__DM1, CYREG_PRT2_DM1
-.set SCSI_Out_DBx__6__DM2, CYREG_PRT2_DM2
-.set SCSI_Out_DBx__6__DR, CYREG_PRT2_DR
-.set SCSI_Out_DBx__6__INP_DIS, CYREG_PRT2_INP_DIS
-.set SCSI_Out_DBx__6__INTTYPE, CYREG_PICU2_INTTYPE1
-.set SCSI_Out_DBx__6__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG
-.set SCSI_Out_DBx__6__LCD_EN, CYREG_PRT2_LCD_EN
-.set SCSI_Out_DBx__6__MASK, 0x02
-.set SCSI_Out_DBx__6__PC, CYREG_PRT2_PC1
-.set SCSI_Out_DBx__6__PORT, 2
-.set SCSI_Out_DBx__6__PRT, CYREG_PRT2_PRT
-.set SCSI_Out_DBx__6__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL
-.set SCSI_Out_DBx__6__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN
-.set SCSI_Out_DBx__6__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0
-.set SCSI_Out_DBx__6__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1
-.set SCSI_Out_DBx__6__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0
-.set SCSI_Out_DBx__6__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1
-.set SCSI_Out_DBx__6__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT
-.set SCSI_Out_DBx__6__PS, CYREG_PRT2_PS
-.set SCSI_Out_DBx__6__SHIFT, 1
-.set SCSI_Out_DBx__6__SLW, CYREG_PRT2_SLW
-.set SCSI_Out_DBx__7__AG, CYREG_PRT15_AG
-.set SCSI_Out_DBx__7__AMUX, CYREG_PRT15_AMUX
-.set SCSI_Out_DBx__7__BIE, CYREG_PRT15_BIE
-.set SCSI_Out_DBx__7__BIT_MASK, CYREG_PRT15_BIT_MASK
-.set SCSI_Out_DBx__7__BYP, CYREG_PRT15_BYP
-.set SCSI_Out_DBx__7__CTL, CYREG_PRT15_CTL
-.set SCSI_Out_DBx__7__DM0, CYREG_PRT15_DM0
-.set SCSI_Out_DBx__7__DM1, CYREG_PRT15_DM1
-.set SCSI_Out_DBx__7__DM2, CYREG_PRT15_DM2
-.set SCSI_Out_DBx__7__DR, CYREG_PRT15_DR
-.set SCSI_Out_DBx__7__INP_DIS, CYREG_PRT15_INP_DIS
-.set SCSI_Out_DBx__7__INTTYPE, CYREG_PICU15_INTTYPE5
-.set SCSI_Out_DBx__7__LCD_COM_SEG, CYREG_PRT15_LCD_COM_SEG
-.set SCSI_Out_DBx__7__LCD_EN, CYREG_PRT15_LCD_EN
-.set SCSI_Out_DBx__7__MASK, 0x20
-.set SCSI_Out_DBx__7__PC, CYREG_IO_PC_PRT15_PC5
-.set SCSI_Out_DBx__7__PORT, 15
-.set SCSI_Out_DBx__7__PRT, CYREG_PRT15_PRT
-.set SCSI_Out_DBx__7__PRTDSI__CAPS_SEL, CYREG_PRT15_CAPS_SEL
-.set SCSI_Out_DBx__7__PRTDSI__DBL_SYNC_IN, CYREG_PRT15_DBL_SYNC_IN
-.set SCSI_Out_DBx__7__PRTDSI__OE_SEL0, CYREG_PRT15_OE_SEL0
-.set SCSI_Out_DBx__7__PRTDSI__OE_SEL1, CYREG_PRT15_OE_SEL1
-.set SCSI_Out_DBx__7__PRTDSI__OUT_SEL0, CYREG_PRT15_OUT_SEL0
-.set SCSI_Out_DBx__7__PRTDSI__OUT_SEL1, CYREG_PRT15_OUT_SEL1
-.set SCSI_Out_DBx__7__PRTDSI__SYNC_OUT, CYREG_PRT15_SYNC_OUT
-.set SCSI_Out_DBx__7__PS, CYREG_PRT15_PS
-.set SCSI_Out_DBx__7__SHIFT, 5
-.set SCSI_Out_DBx__7__SLW, CYREG_PRT15_SLW
-.set SCSI_Out_DBx__DB0__AG, CYREG_PRT6_AG
-.set SCSI_Out_DBx__DB0__AMUX, CYREG_PRT6_AMUX
-.set SCSI_Out_DBx__DB0__BIE, CYREG_PRT6_BIE
-.set SCSI_Out_DBx__DB0__BIT_MASK, CYREG_PRT6_BIT_MASK
-.set SCSI_Out_DBx__DB0__BYP, CYREG_PRT6_BYP
-.set SCSI_Out_DBx__DB0__CTL, CYREG_PRT6_CTL
-.set SCSI_Out_DBx__DB0__DM0, CYREG_PRT6_DM0
-.set SCSI_Out_DBx__DB0__DM1, CYREG_PRT6_DM1
-.set SCSI_Out_DBx__DB0__DM2, CYREG_PRT6_DM2
-.set SCSI_Out_DBx__DB0__DR, CYREG_PRT6_DR
-.set SCSI_Out_DBx__DB0__INP_DIS, CYREG_PRT6_INP_DIS
-.set SCSI_Out_DBx__DB0__INTTYPE, CYREG_PICU6_INTTYPE7
-.set SCSI_Out_DBx__DB0__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
-.set SCSI_Out_DBx__DB0__LCD_EN, CYREG_PRT6_LCD_EN
-.set SCSI_Out_DBx__DB0__MASK, 0x80
-.set SCSI_Out_DBx__DB0__PC, CYREG_PRT6_PC7
-.set SCSI_Out_DBx__DB0__PORT, 6
-.set SCSI_Out_DBx__DB0__PRT, CYREG_PRT6_PRT
-.set SCSI_Out_DBx__DB0__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL
-.set SCSI_Out_DBx__DB0__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN
-.set SCSI_Out_DBx__DB0__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0
-.set SCSI_Out_DBx__DB0__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1
-.set SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0
-.set SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1
-.set SCSI_Out_DBx__DB0__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT
-.set SCSI_Out_DBx__DB0__PS, CYREG_PRT6_PS
-.set SCSI_Out_DBx__DB0__SHIFT, 7
-.set SCSI_Out_DBx__DB0__SLW, CYREG_PRT6_SLW
-.set SCSI_Out_DBx__DB1__AG, CYREG_PRT6_AG
-.set SCSI_Out_DBx__DB1__AMUX, CYREG_PRT6_AMUX
-.set SCSI_Out_DBx__DB1__BIE, CYREG_PRT6_BIE
-.set SCSI_Out_DBx__DB1__BIT_MASK, CYREG_PRT6_BIT_MASK
-.set SCSI_Out_DBx__DB1__BYP, CYREG_PRT6_BYP
-.set SCSI_Out_DBx__DB1__CTL, CYREG_PRT6_CTL
-.set SCSI_Out_DBx__DB1__DM0, CYREG_PRT6_DM0
-.set SCSI_Out_DBx__DB1__DM1, CYREG_PRT6_DM1
-.set SCSI_Out_DBx__DB1__DM2, CYREG_PRT6_DM2
-.set SCSI_Out_DBx__DB1__DR, CYREG_PRT6_DR
-.set SCSI_Out_DBx__DB1__INP_DIS, CYREG_PRT6_INP_DIS
-.set SCSI_Out_DBx__DB1__INTTYPE, CYREG_PICU6_INTTYPE5
-.set SCSI_Out_DBx__DB1__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
-.set SCSI_Out_DBx__DB1__LCD_EN, CYREG_PRT6_LCD_EN
-.set SCSI_Out_DBx__DB1__MASK, 0x20
-.set SCSI_Out_DBx__DB1__PC, CYREG_PRT6_PC5
-.set SCSI_Out_DBx__DB1__PORT, 6
-.set SCSI_Out_DBx__DB1__PRT, CYREG_PRT6_PRT
-.set SCSI_Out_DBx__DB1__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL
-.set SCSI_Out_DBx__DB1__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN
-.set SCSI_Out_DBx__DB1__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0
-.set SCSI_Out_DBx__DB1__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1
-.set SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0
-.set SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1
-.set SCSI_Out_DBx__DB1__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT
-.set SCSI_Out_DBx__DB1__PS, CYREG_PRT6_PS
-.set SCSI_Out_DBx__DB1__SHIFT, 5
-.set SCSI_Out_DBx__DB1__SLW, CYREG_PRT6_SLW
-.set SCSI_Out_DBx__DB2__AG, CYREG_PRT12_AG
-.set SCSI_Out_DBx__DB2__BIE, CYREG_PRT12_BIE
-.set SCSI_Out_DBx__DB2__BIT_MASK, CYREG_PRT12_BIT_MASK
-.set SCSI_Out_DBx__DB2__BYP, CYREG_PRT12_BYP
-.set SCSI_Out_DBx__DB2__DM0, CYREG_PRT12_DM0
-.set SCSI_Out_DBx__DB2__DM1, CYREG_PRT12_DM1
-.set SCSI_Out_DBx__DB2__DM2, CYREG_PRT12_DM2
-.set SCSI_Out_DBx__DB2__DR, CYREG_PRT12_DR
-.set SCSI_Out_DBx__DB2__INP_DIS, CYREG_PRT12_INP_DIS
-.set SCSI_Out_DBx__DB2__INTTYPE, CYREG_PICU12_INTTYPE5
-.set SCSI_Out_DBx__DB2__MASK, 0x20
-.set SCSI_Out_DBx__DB2__PC, CYREG_PRT12_PC5
-.set SCSI_Out_DBx__DB2__PORT, 12
-.set SCSI_Out_DBx__DB2__PRT, CYREG_PRT12_PRT
-.set SCSI_Out_DBx__DB2__PRTDSI__DBL_SYNC_IN, CYREG_PRT12_DBL_SYNC_IN
-.set SCSI_Out_DBx__DB2__PRTDSI__OE_SEL0, CYREG_PRT12_OE_SEL0
-.set SCSI_Out_DBx__DB2__PRTDSI__OE_SEL1, CYREG_PRT12_OE_SEL1
-.set SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL0, CYREG_PRT12_OUT_SEL0
-.set SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL1, CYREG_PRT12_OUT_SEL1
-.set SCSI_Out_DBx__DB2__PRTDSI__SYNC_OUT, CYREG_PRT12_SYNC_OUT
-.set SCSI_Out_DBx__DB2__PS, CYREG_PRT12_PS
-.set SCSI_Out_DBx__DB2__SHIFT, 5
-.set SCSI_Out_DBx__DB2__SIO_CFG, CYREG_PRT12_SIO_CFG
-.set SCSI_Out_DBx__DB2__SIO_DIFF, CYREG_PRT12_SIO_DIFF
-.set SCSI_Out_DBx__DB2__SIO_HYST_EN, CYREG_PRT12_SIO_HYST_EN
-.set SCSI_Out_DBx__DB2__SIO_REG_HIFREQ, CYREG_PRT12_SIO_REG_HIFREQ
-.set SCSI_Out_DBx__DB2__SLW, CYREG_PRT12_SLW
-.set SCSI_Out_DBx__DB3__AG, CYREG_PRT2_AG
-.set SCSI_Out_DBx__DB3__AMUX, CYREG_PRT2_AMUX
-.set SCSI_Out_DBx__DB3__BIE, CYREG_PRT2_BIE
-.set SCSI_Out_DBx__DB3__BIT_MASK, CYREG_PRT2_BIT_MASK
-.set SCSI_Out_DBx__DB3__BYP, CYREG_PRT2_BYP
-.set SCSI_Out_DBx__DB3__CTL, CYREG_PRT2_CTL
-.set SCSI_Out_DBx__DB3__DM0, CYREG_PRT2_DM0
-.set SCSI_Out_DBx__DB3__DM1, CYREG_PRT2_DM1
-.set SCSI_Out_DBx__DB3__DM2, CYREG_PRT2_DM2
-.set SCSI_Out_DBx__DB3__DR, CYREG_PRT2_DR
-.set SCSI_Out_DBx__DB3__INP_DIS, CYREG_PRT2_INP_DIS
-.set SCSI_Out_DBx__DB3__INTTYPE, CYREG_PICU2_INTTYPE7
-.set SCSI_Out_DBx__DB3__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG
-.set SCSI_Out_DBx__DB3__LCD_EN, CYREG_PRT2_LCD_EN
-.set SCSI_Out_DBx__DB3__MASK, 0x80
-.set SCSI_Out_DBx__DB3__PC, CYREG_PRT2_PC7
-.set SCSI_Out_DBx__DB3__PORT, 2
-.set SCSI_Out_DBx__DB3__PRT, CYREG_PRT2_PRT
-.set SCSI_Out_DBx__DB3__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL
-.set SCSI_Out_DBx__DB3__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN
-.set SCSI_Out_DBx__DB3__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0
-.set SCSI_Out_DBx__DB3__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1
-.set SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0
-.set SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1
-.set SCSI_Out_DBx__DB3__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT
-.set SCSI_Out_DBx__DB3__PS, CYREG_PRT2_PS
-.set SCSI_Out_DBx__DB3__SHIFT, 7
-.set SCSI_Out_DBx__DB3__SLW, CYREG_PRT2_SLW
-.set SCSI_Out_DBx__DB4__AG, CYREG_PRT2_AG
-.set SCSI_Out_DBx__DB4__AMUX, CYREG_PRT2_AMUX
-.set SCSI_Out_DBx__DB4__BIE, CYREG_PRT2_BIE
-.set SCSI_Out_DBx__DB4__BIT_MASK, CYREG_PRT2_BIT_MASK
-.set SCSI_Out_DBx__DB4__BYP, CYREG_PRT2_BYP
-.set SCSI_Out_DBx__DB4__CTL, CYREG_PRT2_CTL
-.set SCSI_Out_DBx__DB4__DM0, CYREG_PRT2_DM0
-.set SCSI_Out_DBx__DB4__DM1, CYREG_PRT2_DM1
-.set SCSI_Out_DBx__DB4__DM2, CYREG_PRT2_DM2
-.set SCSI_Out_DBx__DB4__DR, CYREG_PRT2_DR
-.set SCSI_Out_DBx__DB4__INP_DIS, CYREG_PRT2_INP_DIS
-.set SCSI_Out_DBx__DB4__INTTYPE, CYREG_PICU2_INTTYPE5
-.set SCSI_Out_DBx__DB4__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG
-.set SCSI_Out_DBx__DB4__LCD_EN, CYREG_PRT2_LCD_EN
-.set SCSI_Out_DBx__DB4__MASK, 0x20
-.set SCSI_Out_DBx__DB4__PC, CYREG_PRT2_PC5
-.set SCSI_Out_DBx__DB4__PORT, 2
-.set SCSI_Out_DBx__DB4__PRT, CYREG_PRT2_PRT
-.set SCSI_Out_DBx__DB4__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL
-.set SCSI_Out_DBx__DB4__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN
-.set SCSI_Out_DBx__DB4__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0
-.set SCSI_Out_DBx__DB4__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1
-.set SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0
-.set SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1
-.set SCSI_Out_DBx__DB4__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT
-.set SCSI_Out_DBx__DB4__PS, CYREG_PRT2_PS
-.set SCSI_Out_DBx__DB4__SHIFT, 5
-.set SCSI_Out_DBx__DB4__SLW, CYREG_PRT2_SLW
-.set SCSI_Out_DBx__DB5__AG, CYREG_PRT2_AG
-.set SCSI_Out_DBx__DB5__AMUX, CYREG_PRT2_AMUX
-.set SCSI_Out_DBx__DB5__BIE, CYREG_PRT2_BIE
-.set SCSI_Out_DBx__DB5__BIT_MASK, CYREG_PRT2_BIT_MASK
-.set SCSI_Out_DBx__DB5__BYP, CYREG_PRT2_BYP
-.set SCSI_Out_DBx__DB5__CTL, CYREG_PRT2_CTL
-.set SCSI_Out_DBx__DB5__DM0, CYREG_PRT2_DM0
-.set SCSI_Out_DBx__DB5__DM1, CYREG_PRT2_DM1
-.set SCSI_Out_DBx__DB5__DM2, CYREG_PRT2_DM2
-.set SCSI_Out_DBx__DB5__DR, CYREG_PRT2_DR
-.set SCSI_Out_DBx__DB5__INP_DIS, CYREG_PRT2_INP_DIS
-.set SCSI_Out_DBx__DB5__INTTYPE, CYREG_PICU2_INTTYPE3
-.set SCSI_Out_DBx__DB5__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG
-.set SCSI_Out_DBx__DB5__LCD_EN, CYREG_PRT2_LCD_EN
-.set SCSI_Out_DBx__DB5__MASK, 0x08
-.set SCSI_Out_DBx__DB5__PC, CYREG_PRT2_PC3
-.set SCSI_Out_DBx__DB5__PORT, 2
-.set SCSI_Out_DBx__DB5__PRT, CYREG_PRT2_PRT
-.set SCSI_Out_DBx__DB5__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL
-.set SCSI_Out_DBx__DB5__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN
-.set SCSI_Out_DBx__DB5__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0
-.set SCSI_Out_DBx__DB5__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1
-.set SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0
-.set SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1
-.set SCSI_Out_DBx__DB5__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT
-.set SCSI_Out_DBx__DB5__PS, CYREG_PRT2_PS
-.set SCSI_Out_DBx__DB5__SHIFT, 3
-.set SCSI_Out_DBx__DB5__SLW, CYREG_PRT2_SLW
-.set SCSI_Out_DBx__DB6__AG, CYREG_PRT2_AG
-.set SCSI_Out_DBx__DB6__AMUX, CYREG_PRT2_AMUX
-.set SCSI_Out_DBx__DB6__BIE, CYREG_PRT2_BIE
-.set SCSI_Out_DBx__DB6__BIT_MASK, CYREG_PRT2_BIT_MASK
-.set SCSI_Out_DBx__DB6__BYP, CYREG_PRT2_BYP
-.set SCSI_Out_DBx__DB6__CTL, CYREG_PRT2_CTL
-.set SCSI_Out_DBx__DB6__DM0, CYREG_PRT2_DM0
-.set SCSI_Out_DBx__DB6__DM1, CYREG_PRT2_DM1
-.set SCSI_Out_DBx__DB6__DM2, CYREG_PRT2_DM2
-.set SCSI_Out_DBx__DB6__DR, CYREG_PRT2_DR
-.set SCSI_Out_DBx__DB6__INP_DIS, CYREG_PRT2_INP_DIS
-.set SCSI_Out_DBx__DB6__INTTYPE, CYREG_PICU2_INTTYPE1
-.set SCSI_Out_DBx__DB6__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG
-.set SCSI_Out_DBx__DB6__LCD_EN, CYREG_PRT2_LCD_EN
-.set SCSI_Out_DBx__DB6__MASK, 0x02
-.set SCSI_Out_DBx__DB6__PC, CYREG_PRT2_PC1
-.set SCSI_Out_DBx__DB6__PORT, 2
-.set SCSI_Out_DBx__DB6__PRT, CYREG_PRT2_PRT
-.set SCSI_Out_DBx__DB6__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL
-.set SCSI_Out_DBx__DB6__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN
-.set SCSI_Out_DBx__DB6__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0
-.set SCSI_Out_DBx__DB6__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1
-.set SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0
-.set SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1
-.set SCSI_Out_DBx__DB6__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT
-.set SCSI_Out_DBx__DB6__PS, CYREG_PRT2_PS
-.set SCSI_Out_DBx__DB6__SHIFT, 1
-.set SCSI_Out_DBx__DB6__SLW, CYREG_PRT2_SLW
-.set SCSI_Out_DBx__DB7__AG, CYREG_PRT15_AG
-.set SCSI_Out_DBx__DB7__AMUX, CYREG_PRT15_AMUX
-.set SCSI_Out_DBx__DB7__BIE, CYREG_PRT15_BIE
-.set SCSI_Out_DBx__DB7__BIT_MASK, CYREG_PRT15_BIT_MASK
-.set SCSI_Out_DBx__DB7__BYP, CYREG_PRT15_BYP
-.set SCSI_Out_DBx__DB7__CTL, CYREG_PRT15_CTL
-.set SCSI_Out_DBx__DB7__DM0, CYREG_PRT15_DM0
-.set SCSI_Out_DBx__DB7__DM1, CYREG_PRT15_DM1
-.set SCSI_Out_DBx__DB7__DM2, CYREG_PRT15_DM2
-.set SCSI_Out_DBx__DB7__DR, CYREG_PRT15_DR
-.set SCSI_Out_DBx__DB7__INP_DIS, CYREG_PRT15_INP_DIS
-.set SCSI_Out_DBx__DB7__INTTYPE, CYREG_PICU15_INTTYPE5
-.set SCSI_Out_DBx__DB7__LCD_COM_SEG, CYREG_PRT15_LCD_COM_SEG
-.set SCSI_Out_DBx__DB7__LCD_EN, CYREG_PRT15_LCD_EN
-.set SCSI_Out_DBx__DB7__MASK, 0x20
-.set SCSI_Out_DBx__DB7__PC, CYREG_IO_PC_PRT15_PC5
-.set SCSI_Out_DBx__DB7__PORT, 15
-.set SCSI_Out_DBx__DB7__PRT, CYREG_PRT15_PRT
-.set SCSI_Out_DBx__DB7__PRTDSI__CAPS_SEL, CYREG_PRT15_CAPS_SEL
-.set SCSI_Out_DBx__DB7__PRTDSI__DBL_SYNC_IN, CYREG_PRT15_DBL_SYNC_IN
-.set SCSI_Out_DBx__DB7__PRTDSI__OE_SEL0, CYREG_PRT15_OE_SEL0
-.set SCSI_Out_DBx__DB7__PRTDSI__OE_SEL1, CYREG_PRT15_OE_SEL1
-.set SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL0, CYREG_PRT15_OUT_SEL0
-.set SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL1, CYREG_PRT15_OUT_SEL1
-.set SCSI_Out_DBx__DB7__PRTDSI__SYNC_OUT, CYREG_PRT15_SYNC_OUT
-.set SCSI_Out_DBx__DB7__PS, CYREG_PRT15_PS
-.set SCSI_Out_DBx__DB7__SHIFT, 5
-.set SCSI_Out_DBx__DB7__SLW, CYREG_PRT15_SLW
-
-/* SD_RX_DMA */
-.set SD_RX_DMA__DRQ_CTL, CYREG_IDMUX_DRQ_CTL0
-.set SD_RX_DMA__DRQ_NUMBER, 2
-.set SD_RX_DMA__NUMBEROF_TDS, 0
-.set SD_RX_DMA__PRIORITY, 0
-.set SD_RX_DMA__TERMIN_EN, 0
-.set SD_RX_DMA__TERMIN_SEL, 0
-.set SD_RX_DMA__TERMOUT0_EN, 1
-.set SD_RX_DMA__TERMOUT0_SEL, 2
-.set SD_RX_DMA__TERMOUT1_EN, 0
-.set SD_RX_DMA__TERMOUT1_SEL, 0
-
-/* SD_RX_DMA_COMPLETE */
-.set SD_RX_DMA_COMPLETE__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
-.set SD_RX_DMA_COMPLETE__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
-.set SD_RX_DMA_COMPLETE__INTC_MASK, 0x20
-.set SD_RX_DMA_COMPLETE__INTC_NUMBER, 5
-.set SD_RX_DMA_COMPLETE__INTC_PRIOR_NUM, 7
-.set SD_RX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_5
-.set SD_RX_DMA_COMPLETE__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
-.set SD_RX_DMA_COMPLETE__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
-
-/* SD_TX_DMA */
-.set SD_TX_DMA__DRQ_CTL, CYREG_IDMUX_DRQ_CTL0
-.set SD_TX_DMA__DRQ_NUMBER, 3
-.set SD_TX_DMA__NUMBEROF_TDS, 0
-.set SD_TX_DMA__PRIORITY, 1
-.set SD_TX_DMA__TERMIN_EN, 0
-.set SD_TX_DMA__TERMIN_SEL, 0
-.set SD_TX_DMA__TERMOUT0_EN, 1
-.set SD_TX_DMA__TERMOUT0_SEL, 3
-.set SD_TX_DMA__TERMOUT1_EN, 0
-.set SD_TX_DMA__TERMOUT1_SEL, 0
-
-/* SD_TX_DMA_COMPLETE */
-.set SD_TX_DMA_COMPLETE__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
-.set SD_TX_DMA_COMPLETE__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
-.set SD_TX_DMA_COMPLETE__INTC_MASK, 0x40
-.set SD_TX_DMA_COMPLETE__INTC_NUMBER, 6
-.set SD_TX_DMA_COMPLETE__INTC_PRIOR_NUM, 7
-.set SD_TX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_6
-.set SD_TX_DMA_COMPLETE__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
-.set SD_TX_DMA_COMPLETE__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
+/* SCSI_In */
+.set SCSI_In__0__INTTYPE, CYREG_PICU6_INTTYPE1
+.set SCSI_In__0__MASK, 0x02
+.set SCSI_In__0__PC, CYREG_PRT6_PC1
+.set SCSI_In__0__PORT, 6
+.set SCSI_In__0__SHIFT, 1
+.set SCSI_In__AG, CYREG_PRT6_AG
+.set SCSI_In__AMUX, CYREG_PRT6_AMUX
+.set SCSI_In__BIE, CYREG_PRT6_BIE
+.set SCSI_In__BIT_MASK, CYREG_PRT6_BIT_MASK
+.set SCSI_In__BYP, CYREG_PRT6_BYP
+.set SCSI_In__CTL, CYREG_PRT6_CTL
+.set SCSI_In__DBP__INTTYPE, CYREG_PICU6_INTTYPE1
+.set SCSI_In__DBP__MASK, 0x02
+.set SCSI_In__DBP__PC, CYREG_PRT6_PC1
+.set SCSI_In__DBP__PORT, 6
+.set SCSI_In__DBP__SHIFT, 1
+.set SCSI_In__DM0, CYREG_PRT6_DM0
+.set SCSI_In__DM1, CYREG_PRT6_DM1
+.set SCSI_In__DM2, CYREG_PRT6_DM2
+.set SCSI_In__DR, CYREG_PRT6_DR
+.set SCSI_In__INP_DIS, CYREG_PRT6_INP_DIS
+.set SCSI_In__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU6_BASE
+.set SCSI_In__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
+.set SCSI_In__LCD_EN, CYREG_PRT6_LCD_EN
+.set SCSI_In__MASK, 0x02
+.set SCSI_In__PORT, 6
+.set SCSI_In__PRT, CYREG_PRT6_PRT
+.set SCSI_In__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL
+.set SCSI_In__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN
+.set SCSI_In__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0
+.set SCSI_In__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1
+.set SCSI_In__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0
+.set SCSI_In__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1
+.set SCSI_In__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT
+.set SCSI_In__PS, CYREG_PRT6_PS
+.set SCSI_In__SHIFT, 1
+.set SCSI_In__SLW, CYREG_PRT6_SLW
+.set SCSI_In_DBx__0__AG, CYREG_PRT6_AG
+.set SCSI_In_DBx__0__AMUX, CYREG_PRT6_AMUX
+.set SCSI_In_DBx__0__BIE, CYREG_PRT6_BIE
+.set SCSI_In_DBx__0__BIT_MASK, CYREG_PRT6_BIT_MASK
+.set SCSI_In_DBx__0__BYP, CYREG_PRT6_BYP
+.set SCSI_In_DBx__0__CTL, CYREG_PRT6_CTL
+.set SCSI_In_DBx__0__DM0, CYREG_PRT6_DM0
+.set SCSI_In_DBx__0__DM1, CYREG_PRT6_DM1
+.set SCSI_In_DBx__0__DM2, CYREG_PRT6_DM2
+.set SCSI_In_DBx__0__DR, CYREG_PRT6_DR
+.set SCSI_In_DBx__0__INP_DIS, CYREG_PRT6_INP_DIS
+.set SCSI_In_DBx__0__INTTYPE, CYREG_PICU6_INTTYPE6
+.set SCSI_In_DBx__0__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
+.set SCSI_In_DBx__0__LCD_EN, CYREG_PRT6_LCD_EN
+.set SCSI_In_DBx__0__MASK, 0x40
+.set SCSI_In_DBx__0__PC, CYREG_PRT6_PC6
+.set SCSI_In_DBx__0__PORT, 6
+.set SCSI_In_DBx__0__PRT, CYREG_PRT6_PRT
+.set SCSI_In_DBx__0__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL
+.set SCSI_In_DBx__0__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN
+.set SCSI_In_DBx__0__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0
+.set SCSI_In_DBx__0__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1
+.set SCSI_In_DBx__0__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0
+.set SCSI_In_DBx__0__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1
+.set SCSI_In_DBx__0__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT
+.set SCSI_In_DBx__0__PS, CYREG_PRT6_PS
+.set SCSI_In_DBx__0__SHIFT, 6
+.set SCSI_In_DBx__0__SLW, CYREG_PRT6_SLW
+.set SCSI_In_DBx__1__AG, CYREG_PRT6_AG
+.set SCSI_In_DBx__1__AMUX, CYREG_PRT6_AMUX
+.set SCSI_In_DBx__1__BIE, CYREG_PRT6_BIE
+.set SCSI_In_DBx__1__BIT_MASK, CYREG_PRT6_BIT_MASK
+.set SCSI_In_DBx__1__BYP, CYREG_PRT6_BYP
+.set SCSI_In_DBx__1__CTL, CYREG_PRT6_CTL
+.set SCSI_In_DBx__1__DM0, CYREG_PRT6_DM0
+.set SCSI_In_DBx__1__DM1, CYREG_PRT6_DM1
+.set SCSI_In_DBx__1__DM2, CYREG_PRT6_DM2
+.set SCSI_In_DBx__1__DR, CYREG_PRT6_DR
+.set SCSI_In_DBx__1__INP_DIS, CYREG_PRT6_INP_DIS
+.set SCSI_In_DBx__1__INTTYPE, CYREG_PICU6_INTTYPE4
+.set SCSI_In_DBx__1__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
+.set SCSI_In_DBx__1__LCD_EN, CYREG_PRT6_LCD_EN
+.set SCSI_In_DBx__1__MASK, 0x10
+.set SCSI_In_DBx__1__PC, CYREG_PRT6_PC4
+.set SCSI_In_DBx__1__PORT, 6
+.set SCSI_In_DBx__1__PRT, CYREG_PRT6_PRT
+.set SCSI_In_DBx__1__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL
+.set SCSI_In_DBx__1__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN
+.set SCSI_In_DBx__1__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0
+.set SCSI_In_DBx__1__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1
+.set SCSI_In_DBx__1__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0
+.set SCSI_In_DBx__1__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1
+.set SCSI_In_DBx__1__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT
+.set SCSI_In_DBx__1__PS, CYREG_PRT6_PS
+.set SCSI_In_DBx__1__SHIFT, 4
+.set SCSI_In_DBx__1__SLW, CYREG_PRT6_SLW
+.set SCSI_In_DBx__2__AG, CYREG_PRT12_AG
+.set SCSI_In_DBx__2__BIE, CYREG_PRT12_BIE
+.set SCSI_In_DBx__2__BIT_MASK, CYREG_PRT12_BIT_MASK
+.set SCSI_In_DBx__2__BYP, CYREG_PRT12_BYP
+.set SCSI_In_DBx__2__DM0, CYREG_PRT12_DM0
+.set SCSI_In_DBx__2__DM1, CYREG_PRT12_DM1
+.set SCSI_In_DBx__2__DM2, CYREG_PRT12_DM2
+.set SCSI_In_DBx__2__DR, CYREG_PRT12_DR
+.set SCSI_In_DBx__2__INP_DIS, CYREG_PRT12_INP_DIS
+.set SCSI_In_DBx__2__INTTYPE, CYREG_PICU12_INTTYPE4
+.set SCSI_In_DBx__2__MASK, 0x10
+.set SCSI_In_DBx__2__PC, CYREG_PRT12_PC4
+.set SCSI_In_DBx__2__PORT, 12
+.set SCSI_In_DBx__2__PRT, CYREG_PRT12_PRT
+.set SCSI_In_DBx__2__PRTDSI__DBL_SYNC_IN, CYREG_PRT12_DBL_SYNC_IN
+.set SCSI_In_DBx__2__PRTDSI__OE_SEL0, CYREG_PRT12_OE_SEL0
+.set SCSI_In_DBx__2__PRTDSI__OE_SEL1, CYREG_PRT12_OE_SEL1
+.set SCSI_In_DBx__2__PRTDSI__OUT_SEL0, CYREG_PRT12_OUT_SEL0
+.set SCSI_In_DBx__2__PRTDSI__OUT_SEL1, CYREG_PRT12_OUT_SEL1
+.set SCSI_In_DBx__2__PRTDSI__SYNC_OUT, CYREG_PRT12_SYNC_OUT
+.set SCSI_In_DBx__2__PS, CYREG_PRT12_PS
+.set SCSI_In_DBx__2__SHIFT, 4
+.set SCSI_In_DBx__2__SIO_CFG, CYREG_PRT12_SIO_CFG
+.set SCSI_In_DBx__2__SIO_DIFF, CYREG_PRT12_SIO_DIFF
+.set SCSI_In_DBx__2__SIO_HYST_EN, CYREG_PRT12_SIO_HYST_EN
+.set SCSI_In_DBx__2__SIO_REG_HIFREQ, CYREG_PRT12_SIO_REG_HIFREQ
+.set SCSI_In_DBx__2__SLW, CYREG_PRT12_SLW
+.set SCSI_In_DBx__3__AG, CYREG_PRT2_AG
+.set SCSI_In_DBx__3__AMUX, CYREG_PRT2_AMUX
+.set SCSI_In_DBx__3__BIE, CYREG_PRT2_BIE
+.set SCSI_In_DBx__3__BIT_MASK, CYREG_PRT2_BIT_MASK
+.set SCSI_In_DBx__3__BYP, CYREG_PRT2_BYP
+.set SCSI_In_DBx__3__CTL, CYREG_PRT2_CTL
+.set SCSI_In_DBx__3__DM0, CYREG_PRT2_DM0
+.set SCSI_In_DBx__3__DM1, CYREG_PRT2_DM1
+.set SCSI_In_DBx__3__DM2, CYREG_PRT2_DM2
+.set SCSI_In_DBx__3__DR, CYREG_PRT2_DR
+.set SCSI_In_DBx__3__INP_DIS, CYREG_PRT2_INP_DIS
+.set SCSI_In_DBx__3__INTTYPE, CYREG_PICU2_INTTYPE6
+.set SCSI_In_DBx__3__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG
+.set SCSI_In_DBx__3__LCD_EN, CYREG_PRT2_LCD_EN
+.set SCSI_In_DBx__3__MASK, 0x40
+.set SCSI_In_DBx__3__PC, CYREG_PRT2_PC6
+.set SCSI_In_DBx__3__PORT, 2
+.set SCSI_In_DBx__3__PRT, CYREG_PRT2_PRT
+.set SCSI_In_DBx__3__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL
+.set SCSI_In_DBx__3__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN
+.set SCSI_In_DBx__3__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0
+.set SCSI_In_DBx__3__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1
+.set SCSI_In_DBx__3__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0
+.set SCSI_In_DBx__3__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1
+.set SCSI_In_DBx__3__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT
+.set SCSI_In_DBx__3__PS, CYREG_PRT2_PS
+.set SCSI_In_DBx__3__SHIFT, 6
+.set SCSI_In_DBx__3__SLW, CYREG_PRT2_SLW
+.set SCSI_In_DBx__4__AG, CYREG_PRT2_AG
+.set SCSI_In_DBx__4__AMUX, CYREG_PRT2_AMUX
+.set SCSI_In_DBx__4__BIE, CYREG_PRT2_BIE
+.set SCSI_In_DBx__4__BIT_MASK, CYREG_PRT2_BIT_MASK
+.set SCSI_In_DBx__4__BYP, CYREG_PRT2_BYP
+.set SCSI_In_DBx__4__CTL, CYREG_PRT2_CTL
+.set SCSI_In_DBx__4__DM0, CYREG_PRT2_DM0
+.set SCSI_In_DBx__4__DM1, CYREG_PRT2_DM1
+.set SCSI_In_DBx__4__DM2, CYREG_PRT2_DM2
+.set SCSI_In_DBx__4__DR, CYREG_PRT2_DR
+.set SCSI_In_DBx__4__INP_DIS, CYREG_PRT2_INP_DIS
+.set SCSI_In_DBx__4__INTTYPE, CYREG_PICU2_INTTYPE4
+.set SCSI_In_DBx__4__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG
+.set SCSI_In_DBx__4__LCD_EN, CYREG_PRT2_LCD_EN
+.set SCSI_In_DBx__4__MASK, 0x10
+.set SCSI_In_DBx__4__PC, CYREG_PRT2_PC4
+.set SCSI_In_DBx__4__PORT, 2
+.set SCSI_In_DBx__4__PRT, CYREG_PRT2_PRT
+.set SCSI_In_DBx__4__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL
+.set SCSI_In_DBx__4__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN
+.set SCSI_In_DBx__4__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0
+.set SCSI_In_DBx__4__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1
+.set SCSI_In_DBx__4__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0
+.set SCSI_In_DBx__4__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1
+.set SCSI_In_DBx__4__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT
+.set SCSI_In_DBx__4__PS, CYREG_PRT2_PS
+.set SCSI_In_DBx__4__SHIFT, 4
+.set SCSI_In_DBx__4__SLW, CYREG_PRT2_SLW
+.set SCSI_In_DBx__5__AG, CYREG_PRT2_AG
+.set SCSI_In_DBx__5__AMUX, CYREG_PRT2_AMUX
+.set SCSI_In_DBx__5__BIE, CYREG_PRT2_BIE
+.set SCSI_In_DBx__5__BIT_MASK, CYREG_PRT2_BIT_MASK
+.set SCSI_In_DBx__5__BYP, CYREG_PRT2_BYP
+.set SCSI_In_DBx__5__CTL, CYREG_PRT2_CTL
+.set SCSI_In_DBx__5__DM0, CYREG_PRT2_DM0
+.set SCSI_In_DBx__5__DM1, CYREG_PRT2_DM1
+.set SCSI_In_DBx__5__DM2, CYREG_PRT2_DM2
+.set SCSI_In_DBx__5__DR, CYREG_PRT2_DR
+.set SCSI_In_DBx__5__INP_DIS, CYREG_PRT2_INP_DIS
+.set SCSI_In_DBx__5__INTTYPE, CYREG_PICU2_INTTYPE2
+.set SCSI_In_DBx__5__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG
+.set SCSI_In_DBx__5__LCD_EN, CYREG_PRT2_LCD_EN
+.set SCSI_In_DBx__5__MASK, 0x04
+.set SCSI_In_DBx__5__PC, CYREG_PRT2_PC2
+.set SCSI_In_DBx__5__PORT, 2
+.set SCSI_In_DBx__5__PRT, CYREG_PRT2_PRT
+.set SCSI_In_DBx__5__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL
+.set SCSI_In_DBx__5__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN
+.set SCSI_In_DBx__5__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0
+.set SCSI_In_DBx__5__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1
+.set SCSI_In_DBx__5__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0
+.set SCSI_In_DBx__5__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1
+.set SCSI_In_DBx__5__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT
+.set SCSI_In_DBx__5__PS, CYREG_PRT2_PS
+.set SCSI_In_DBx__5__SHIFT, 2
+.set SCSI_In_DBx__5__SLW, CYREG_PRT2_SLW
+.set SCSI_In_DBx__6__AG, CYREG_PRT2_AG
+.set SCSI_In_DBx__6__AMUX, CYREG_PRT2_AMUX
+.set SCSI_In_DBx__6__BIE, CYREG_PRT2_BIE
+.set SCSI_In_DBx__6__BIT_MASK, CYREG_PRT2_BIT_MASK
+.set SCSI_In_DBx__6__BYP, CYREG_PRT2_BYP
+.set SCSI_In_DBx__6__CTL, CYREG_PRT2_CTL
+.set SCSI_In_DBx__6__DM0, CYREG_PRT2_DM0
+.set SCSI_In_DBx__6__DM1, CYREG_PRT2_DM1
+.set SCSI_In_DBx__6__DM2, CYREG_PRT2_DM2
+.set SCSI_In_DBx__6__DR, CYREG_PRT2_DR
+.set SCSI_In_DBx__6__INP_DIS, CYREG_PRT2_INP_DIS
+.set SCSI_In_DBx__6__INTTYPE, CYREG_PICU2_INTTYPE0
+.set SCSI_In_DBx__6__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG
+.set SCSI_In_DBx__6__LCD_EN, CYREG_PRT2_LCD_EN
+.set SCSI_In_DBx__6__MASK, 0x01
+.set SCSI_In_DBx__6__PC, CYREG_PRT2_PC0
+.set SCSI_In_DBx__6__PORT, 2
+.set SCSI_In_DBx__6__PRT, CYREG_PRT2_PRT
+.set SCSI_In_DBx__6__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL
+.set SCSI_In_DBx__6__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN
+.set SCSI_In_DBx__6__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0
+.set SCSI_In_DBx__6__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1
+.set SCSI_In_DBx__6__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0
+.set SCSI_In_DBx__6__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1
+.set SCSI_In_DBx__6__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT
+.set SCSI_In_DBx__6__PS, CYREG_PRT2_PS
+.set SCSI_In_DBx__6__SHIFT, 0
+.set SCSI_In_DBx__6__SLW, CYREG_PRT2_SLW
+.set SCSI_In_DBx__7__AG, CYREG_PRT6_AG
+.set SCSI_In_DBx__7__AMUX, CYREG_PRT6_AMUX
+.set SCSI_In_DBx__7__BIE, CYREG_PRT6_BIE
+.set SCSI_In_DBx__7__BIT_MASK, CYREG_PRT6_BIT_MASK
+.set SCSI_In_DBx__7__BYP, CYREG_PRT6_BYP
+.set SCSI_In_DBx__7__CTL, CYREG_PRT6_CTL
+.set SCSI_In_DBx__7__DM0, CYREG_PRT6_DM0
+.set SCSI_In_DBx__7__DM1, CYREG_PRT6_DM1
+.set SCSI_In_DBx__7__DM2, CYREG_PRT6_DM2
+.set SCSI_In_DBx__7__DR, CYREG_PRT6_DR
+.set SCSI_In_DBx__7__INP_DIS, CYREG_PRT6_INP_DIS
+.set SCSI_In_DBx__7__INTTYPE, CYREG_PICU6_INTTYPE3
+.set SCSI_In_DBx__7__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
+.set SCSI_In_DBx__7__LCD_EN, CYREG_PRT6_LCD_EN
+.set SCSI_In_DBx__7__MASK, 0x08
+.set SCSI_In_DBx__7__PC, CYREG_PRT6_PC3
+.set SCSI_In_DBx__7__PORT, 6
+.set SCSI_In_DBx__7__PRT, CYREG_PRT6_PRT
+.set SCSI_In_DBx__7__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL
+.set SCSI_In_DBx__7__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN
+.set SCSI_In_DBx__7__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0
+.set SCSI_In_DBx__7__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1
+.set SCSI_In_DBx__7__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0
+.set SCSI_In_DBx__7__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1
+.set SCSI_In_DBx__7__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT
+.set SCSI_In_DBx__7__PS, CYREG_PRT6_PS
+.set SCSI_In_DBx__7__SHIFT, 3
+.set SCSI_In_DBx__7__SLW, CYREG_PRT6_SLW
+.set SCSI_In_DBx__DB0__AG, CYREG_PRT6_AG
+.set SCSI_In_DBx__DB0__AMUX, CYREG_PRT6_AMUX
+.set SCSI_In_DBx__DB0__BIE, CYREG_PRT6_BIE
+.set SCSI_In_DBx__DB0__BIT_MASK, CYREG_PRT6_BIT_MASK
+.set SCSI_In_DBx__DB0__BYP, CYREG_PRT6_BYP
+.set SCSI_In_DBx__DB0__CTL, CYREG_PRT6_CTL
+.set SCSI_In_DBx__DB0__DM0, CYREG_PRT6_DM0
+.set SCSI_In_DBx__DB0__DM1, CYREG_PRT6_DM1
+.set SCSI_In_DBx__DB0__DM2, CYREG_PRT6_DM2
+.set SCSI_In_DBx__DB0__DR, CYREG_PRT6_DR
+.set SCSI_In_DBx__DB0__INP_DIS, CYREG_PRT6_INP_DIS
+.set SCSI_In_DBx__DB0__INTTYPE, CYREG_PICU6_INTTYPE6
+.set SCSI_In_DBx__DB0__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
+.set SCSI_In_DBx__DB0__LCD_EN, CYREG_PRT6_LCD_EN
+.set SCSI_In_DBx__DB0__MASK, 0x40
+.set SCSI_In_DBx__DB0__PC, CYREG_PRT6_PC6
+.set SCSI_In_DBx__DB0__PORT, 6
+.set SCSI_In_DBx__DB0__PRT, CYREG_PRT6_PRT
+.set SCSI_In_DBx__DB0__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL
+.set SCSI_In_DBx__DB0__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN
+.set SCSI_In_DBx__DB0__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0
+.set SCSI_In_DBx__DB0__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1
+.set SCSI_In_DBx__DB0__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0
+.set SCSI_In_DBx__DB0__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1
+.set SCSI_In_DBx__DB0__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT
+.set SCSI_In_DBx__DB0__PS, CYREG_PRT6_PS
+.set SCSI_In_DBx__DB0__SHIFT, 6
+.set SCSI_In_DBx__DB0__SLW, CYREG_PRT6_SLW
+.set SCSI_In_DBx__DB1__AG, CYREG_PRT6_AG
+.set SCSI_In_DBx__DB1__AMUX, CYREG_PRT6_AMUX
+.set SCSI_In_DBx__DB1__BIE, CYREG_PRT6_BIE
+.set SCSI_In_DBx__DB1__BIT_MASK, CYREG_PRT6_BIT_MASK
+.set SCSI_In_DBx__DB1__BYP, CYREG_PRT6_BYP
+.set SCSI_In_DBx__DB1__CTL, CYREG_PRT6_CTL
+.set SCSI_In_DBx__DB1__DM0, CYREG_PRT6_DM0
+.set SCSI_In_DBx__DB1__DM1, CYREG_PRT6_DM1
+.set SCSI_In_DBx__DB1__DM2, CYREG_PRT6_DM2
+.set SCSI_In_DBx__DB1__DR, CYREG_PRT6_DR
+.set SCSI_In_DBx__DB1__INP_DIS, CYREG_PRT6_INP_DIS
+.set SCSI_In_DBx__DB1__INTTYPE, CYREG_PICU6_INTTYPE4
+.set SCSI_In_DBx__DB1__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
+.set SCSI_In_DBx__DB1__LCD_EN, CYREG_PRT6_LCD_EN
+.set SCSI_In_DBx__DB1__MASK, 0x10
+.set SCSI_In_DBx__DB1__PC, CYREG_PRT6_PC4
+.set SCSI_In_DBx__DB1__PORT, 6
+.set SCSI_In_DBx__DB1__PRT, CYREG_PRT6_PRT
+.set SCSI_In_DBx__DB1__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL
+.set SCSI_In_DBx__DB1__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN
+.set SCSI_In_DBx__DB1__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0
+.set SCSI_In_DBx__DB1__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1
+.set SCSI_In_DBx__DB1__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0
+.set SCSI_In_DBx__DB1__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1
+.set SCSI_In_DBx__DB1__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT
+.set SCSI_In_DBx__DB1__PS, CYREG_PRT6_PS
+.set SCSI_In_DBx__DB1__SHIFT, 4
+.set SCSI_In_DBx__DB1__SLW, CYREG_PRT6_SLW
+.set SCSI_In_DBx__DB2__AG, CYREG_PRT12_AG
+.set SCSI_In_DBx__DB2__BIE, CYREG_PRT12_BIE
+.set SCSI_In_DBx__DB2__BIT_MASK, CYREG_PRT12_BIT_MASK
+.set SCSI_In_DBx__DB2__BYP, CYREG_PRT12_BYP
+.set SCSI_In_DBx__DB2__DM0, CYREG_PRT12_DM0
+.set SCSI_In_DBx__DB2__DM1, CYREG_PRT12_DM1
+.set SCSI_In_DBx__DB2__DM2, CYREG_PRT12_DM2
+.set SCSI_In_DBx__DB2__DR, CYREG_PRT12_DR
+.set SCSI_In_DBx__DB2__INP_DIS, CYREG_PRT12_INP_DIS
+.set SCSI_In_DBx__DB2__INTTYPE, CYREG_PICU12_INTTYPE4
+.set SCSI_In_DBx__DB2__MASK, 0x10
+.set SCSI_In_DBx__DB2__PC, CYREG_PRT12_PC4
+.set SCSI_In_DBx__DB2__PORT, 12
+.set SCSI_In_DBx__DB2__PRT, CYREG_PRT12_PRT
+.set SCSI_In_DBx__DB2__PRTDSI__DBL_SYNC_IN, CYREG_PRT12_DBL_SYNC_IN
+.set SCSI_In_DBx__DB2__PRTDSI__OE_SEL0, CYREG_PRT12_OE_SEL0
+.set SCSI_In_DBx__DB2__PRTDSI__OE_SEL1, CYREG_PRT12_OE_SEL1
+.set SCSI_In_DBx__DB2__PRTDSI__OUT_SEL0, CYREG_PRT12_OUT_SEL0
+.set SCSI_In_DBx__DB2__PRTDSI__OUT_SEL1, CYREG_PRT12_OUT_SEL1
+.set SCSI_In_DBx__DB2__PRTDSI__SYNC_OUT, CYREG_PRT12_SYNC_OUT
+.set SCSI_In_DBx__DB2__PS, CYREG_PRT12_PS
+.set SCSI_In_DBx__DB2__SHIFT, 4
+.set SCSI_In_DBx__DB2__SIO_CFG, CYREG_PRT12_SIO_CFG
+.set SCSI_In_DBx__DB2__SIO_DIFF, CYREG_PRT12_SIO_DIFF
+.set SCSI_In_DBx__DB2__SIO_HYST_EN, CYREG_PRT12_SIO_HYST_EN
+.set SCSI_In_DBx__DB2__SIO_REG_HIFREQ, CYREG_PRT12_SIO_REG_HIFREQ
+.set SCSI_In_DBx__DB2__SLW, CYREG_PRT12_SLW
+.set SCSI_In_DBx__DB3__AG, CYREG_PRT2_AG
+.set SCSI_In_DBx__DB3__AMUX, CYREG_PRT2_AMUX
+.set SCSI_In_DBx__DB3__BIE, CYREG_PRT2_BIE
+.set SCSI_In_DBx__DB3__BIT_MASK, CYREG_PRT2_BIT_MASK
+.set SCSI_In_DBx__DB3__BYP, CYREG_PRT2_BYP
+.set SCSI_In_DBx__DB3__CTL, CYREG_PRT2_CTL
+.set SCSI_In_DBx__DB3__DM0, CYREG_PRT2_DM0
+.set SCSI_In_DBx__DB3__DM1, CYREG_PRT2_DM1
+.set SCSI_In_DBx__DB3__DM2, CYREG_PRT2_DM2
+.set SCSI_In_DBx__DB3__DR, CYREG_PRT2_DR
+.set SCSI_In_DBx__DB3__INP_DIS, CYREG_PRT2_INP_DIS
+.set SCSI_In_DBx__DB3__INTTYPE, CYREG_PICU2_INTTYPE6
+.set SCSI_In_DBx__DB3__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG
+.set SCSI_In_DBx__DB3__LCD_EN, CYREG_PRT2_LCD_EN
+.set SCSI_In_DBx__DB3__MASK, 0x40
+.set SCSI_In_DBx__DB3__PC, CYREG_PRT2_PC6
+.set SCSI_In_DBx__DB3__PORT, 2
+.set SCSI_In_DBx__DB3__PRT, CYREG_PRT2_PRT
+.set SCSI_In_DBx__DB3__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL
+.set SCSI_In_DBx__DB3__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN
+.set SCSI_In_DBx__DB3__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0
+.set SCSI_In_DBx__DB3__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1
+.set SCSI_In_DBx__DB3__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0
+.set SCSI_In_DBx__DB3__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1
+.set SCSI_In_DBx__DB3__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT
+.set SCSI_In_DBx__DB3__PS, CYREG_PRT2_PS
+.set SCSI_In_DBx__DB3__SHIFT, 6
+.set SCSI_In_DBx__DB3__SLW, CYREG_PRT2_SLW
+.set SCSI_In_DBx__DB4__AG, CYREG_PRT2_AG
+.set SCSI_In_DBx__DB4__AMUX, CYREG_PRT2_AMUX
+.set SCSI_In_DBx__DB4__BIE, CYREG_PRT2_BIE
+.set SCSI_In_DBx__DB4__BIT_MASK, CYREG_PRT2_BIT_MASK
+.set SCSI_In_DBx__DB4__BYP, CYREG_PRT2_BYP
+.set SCSI_In_DBx__DB4__CTL, CYREG_PRT2_CTL
+.set SCSI_In_DBx__DB4__DM0, CYREG_PRT2_DM0
+.set SCSI_In_DBx__DB4__DM1, CYREG_PRT2_DM1
+.set SCSI_In_DBx__DB4__DM2, CYREG_PRT2_DM2
+.set SCSI_In_DBx__DB4__DR, CYREG_PRT2_DR
+.set SCSI_In_DBx__DB4__INP_DIS, CYREG_PRT2_INP_DIS
+.set SCSI_In_DBx__DB4__INTTYPE, CYREG_PICU2_INTTYPE4
+.set SCSI_In_DBx__DB4__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG
+.set SCSI_In_DBx__DB4__LCD_EN, CYREG_PRT2_LCD_EN
+.set SCSI_In_DBx__DB4__MASK, 0x10
+.set SCSI_In_DBx__DB4__PC, CYREG_PRT2_PC4
+.set SCSI_In_DBx__DB4__PORT, 2
+.set SCSI_In_DBx__DB4__PRT, CYREG_PRT2_PRT
+.set SCSI_In_DBx__DB4__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL
+.set SCSI_In_DBx__DB4__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN
+.set SCSI_In_DBx__DB4__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0
+.set SCSI_In_DBx__DB4__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1
+.set SCSI_In_DBx__DB4__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0
+.set SCSI_In_DBx__DB4__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1
+.set SCSI_In_DBx__DB4__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT
+.set SCSI_In_DBx__DB4__PS, CYREG_PRT2_PS
+.set SCSI_In_DBx__DB4__SHIFT, 4
+.set SCSI_In_DBx__DB4__SLW, CYREG_PRT2_SLW
+.set SCSI_In_DBx__DB5__AG, CYREG_PRT2_AG
+.set SCSI_In_DBx__DB5__AMUX, CYREG_PRT2_AMUX
+.set SCSI_In_DBx__DB5__BIE, CYREG_PRT2_BIE
+.set SCSI_In_DBx__DB5__BIT_MASK, CYREG_PRT2_BIT_MASK
+.set SCSI_In_DBx__DB5__BYP, CYREG_PRT2_BYP
+.set SCSI_In_DBx__DB5__CTL, CYREG_PRT2_CTL
+.set SCSI_In_DBx__DB5__DM0, CYREG_PRT2_DM0
+.set SCSI_In_DBx__DB5__DM1, CYREG_PRT2_DM1
+.set SCSI_In_DBx__DB5__DM2, CYREG_PRT2_DM2
+.set SCSI_In_DBx__DB5__DR, CYREG_PRT2_DR
+.set SCSI_In_DBx__DB5__INP_DIS, CYREG_PRT2_INP_DIS
+.set SCSI_In_DBx__DB5__INTTYPE, CYREG_PICU2_INTTYPE2
+.set SCSI_In_DBx__DB5__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG
+.set SCSI_In_DBx__DB5__LCD_EN, CYREG_PRT2_LCD_EN
+.set SCSI_In_DBx__DB5__MASK, 0x04
+.set SCSI_In_DBx__DB5__PC, CYREG_PRT2_PC2
+.set SCSI_In_DBx__DB5__PORT, 2
+.set SCSI_In_DBx__DB5__PRT, CYREG_PRT2_PRT
+.set SCSI_In_DBx__DB5__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL
+.set SCSI_In_DBx__DB5__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN
+.set SCSI_In_DBx__DB5__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0
+.set SCSI_In_DBx__DB5__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1
+.set SCSI_In_DBx__DB5__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0
+.set SCSI_In_DBx__DB5__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1
+.set SCSI_In_DBx__DB5__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT
+.set SCSI_In_DBx__DB5__PS, CYREG_PRT2_PS
+.set SCSI_In_DBx__DB5__SHIFT, 2
+.set SCSI_In_DBx__DB5__SLW, CYREG_PRT2_SLW
+.set SCSI_In_DBx__DB6__AG, CYREG_PRT2_AG
+.set SCSI_In_DBx__DB6__AMUX, CYREG_PRT2_AMUX
+.set SCSI_In_DBx__DB6__BIE, CYREG_PRT2_BIE
+.set SCSI_In_DBx__DB6__BIT_MASK, CYREG_PRT2_BIT_MASK
+.set SCSI_In_DBx__DB6__BYP, CYREG_PRT2_BYP
+.set SCSI_In_DBx__DB6__CTL, CYREG_PRT2_CTL
+.set SCSI_In_DBx__DB6__DM0, CYREG_PRT2_DM0
+.set SCSI_In_DBx__DB6__DM1, CYREG_PRT2_DM1
+.set SCSI_In_DBx__DB6__DM2, CYREG_PRT2_DM2
+.set SCSI_In_DBx__DB6__DR, CYREG_PRT2_DR
+.set SCSI_In_DBx__DB6__INP_DIS, CYREG_PRT2_INP_DIS
+.set SCSI_In_DBx__DB6__INTTYPE, CYREG_PICU2_INTTYPE0
+.set SCSI_In_DBx__DB6__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG
+.set SCSI_In_DBx__DB6__LCD_EN, CYREG_PRT2_LCD_EN
+.set SCSI_In_DBx__DB6__MASK, 0x01
+.set SCSI_In_DBx__DB6__PC, CYREG_PRT2_PC0
+.set SCSI_In_DBx__DB6__PORT, 2
+.set SCSI_In_DBx__DB6__PRT, CYREG_PRT2_PRT
+.set SCSI_In_DBx__DB6__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL
+.set SCSI_In_DBx__DB6__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN
+.set SCSI_In_DBx__DB6__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0
+.set SCSI_In_DBx__DB6__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1
+.set SCSI_In_DBx__DB6__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0
+.set SCSI_In_DBx__DB6__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1
+.set SCSI_In_DBx__DB6__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT
+.set SCSI_In_DBx__DB6__PS, CYREG_PRT2_PS
+.set SCSI_In_DBx__DB6__SHIFT, 0
+.set SCSI_In_DBx__DB6__SLW, CYREG_PRT2_SLW
+.set SCSI_In_DBx__DB7__AG, CYREG_PRT6_AG
+.set SCSI_In_DBx__DB7__AMUX, CYREG_PRT6_AMUX
+.set SCSI_In_DBx__DB7__BIE, CYREG_PRT6_BIE
+.set SCSI_In_DBx__DB7__BIT_MASK, CYREG_PRT6_BIT_MASK
+.set SCSI_In_DBx__DB7__BYP, CYREG_PRT6_BYP
+.set SCSI_In_DBx__DB7__CTL, CYREG_PRT6_CTL
+.set SCSI_In_DBx__DB7__DM0, CYREG_PRT6_DM0
+.set SCSI_In_DBx__DB7__DM1, CYREG_PRT6_DM1
+.set SCSI_In_DBx__DB7__DM2, CYREG_PRT6_DM2
+.set SCSI_In_DBx__DB7__DR, CYREG_PRT6_DR
+.set SCSI_In_DBx__DB7__INP_DIS, CYREG_PRT6_INP_DIS
+.set SCSI_In_DBx__DB7__INTTYPE, CYREG_PICU6_INTTYPE3
+.set SCSI_In_DBx__DB7__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
+.set SCSI_In_DBx__DB7__LCD_EN, CYREG_PRT6_LCD_EN
+.set SCSI_In_DBx__DB7__MASK, 0x08
+.set SCSI_In_DBx__DB7__PC, CYREG_PRT6_PC3
+.set SCSI_In_DBx__DB7__PORT, 6
+.set SCSI_In_DBx__DB7__PRT, CYREG_PRT6_PRT
+.set SCSI_In_DBx__DB7__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL
+.set SCSI_In_DBx__DB7__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN
+.set SCSI_In_DBx__DB7__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0
+.set SCSI_In_DBx__DB7__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1
+.set SCSI_In_DBx__DB7__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0
+.set SCSI_In_DBx__DB7__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1
+.set SCSI_In_DBx__DB7__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT
+.set SCSI_In_DBx__DB7__PS, CYREG_PRT6_PS
+.set SCSI_In_DBx__DB7__SHIFT, 3
+.set SCSI_In_DBx__DB7__SLW, CYREG_PRT6_SLW
 
 /* SCSI_Noise */
 .set SCSI_Noise__0__AG, CYREG_PRT4_AG
@@ -2354,6 +933,1592 @@
 .set SCSI_Noise__SEL__SHIFT, 2
 .set SCSI_Noise__SEL__SLW, CYREG_PRT0_SLW
 
+/* SCSI_Out */
+.set SCSI_Out__0__AG, CYREG_PRT6_AG
+.set SCSI_Out__0__AMUX, CYREG_PRT6_AMUX
+.set SCSI_Out__0__BIE, CYREG_PRT6_BIE
+.set SCSI_Out__0__BIT_MASK, CYREG_PRT6_BIT_MASK
+.set SCSI_Out__0__BYP, CYREG_PRT6_BYP
+.set SCSI_Out__0__CTL, CYREG_PRT6_CTL
+.set SCSI_Out__0__DM0, CYREG_PRT6_DM0
+.set SCSI_Out__0__DM1, CYREG_PRT6_DM1
+.set SCSI_Out__0__DM2, CYREG_PRT6_DM2
+.set SCSI_Out__0__DR, CYREG_PRT6_DR
+.set SCSI_Out__0__INP_DIS, CYREG_PRT6_INP_DIS
+.set SCSI_Out__0__INTTYPE, CYREG_PICU6_INTTYPE2
+.set SCSI_Out__0__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
+.set SCSI_Out__0__LCD_EN, CYREG_PRT6_LCD_EN
+.set SCSI_Out__0__MASK, 0x04
+.set SCSI_Out__0__PC, CYREG_PRT6_PC2
+.set SCSI_Out__0__PORT, 6
+.set SCSI_Out__0__PRT, CYREG_PRT6_PRT
+.set SCSI_Out__0__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL
+.set SCSI_Out__0__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN
+.set SCSI_Out__0__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0
+.set SCSI_Out__0__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1
+.set SCSI_Out__0__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0
+.set SCSI_Out__0__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1
+.set SCSI_Out__0__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT
+.set SCSI_Out__0__PS, CYREG_PRT6_PS
+.set SCSI_Out__0__SHIFT, 2
+.set SCSI_Out__0__SLW, CYREG_PRT6_SLW
+.set SCSI_Out__1__AG, CYREG_PRT4_AG
+.set SCSI_Out__1__AMUX, CYREG_PRT4_AMUX
+.set SCSI_Out__1__BIE, CYREG_PRT4_BIE
+.set SCSI_Out__1__BIT_MASK, CYREG_PRT4_BIT_MASK
+.set SCSI_Out__1__BYP, CYREG_PRT4_BYP
+.set SCSI_Out__1__CTL, CYREG_PRT4_CTL
+.set SCSI_Out__1__DM0, CYREG_PRT4_DM0
+.set SCSI_Out__1__DM1, CYREG_PRT4_DM1
+.set SCSI_Out__1__DM2, CYREG_PRT4_DM2
+.set SCSI_Out__1__DR, CYREG_PRT4_DR
+.set SCSI_Out__1__INP_DIS, CYREG_PRT4_INP_DIS
+.set SCSI_Out__1__INTTYPE, CYREG_PICU4_INTTYPE6
+.set SCSI_Out__1__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG
+.set SCSI_Out__1__LCD_EN, CYREG_PRT4_LCD_EN
+.set SCSI_Out__1__MASK, 0x40
+.set SCSI_Out__1__PC, CYREG_PRT4_PC6
+.set SCSI_Out__1__PORT, 4
+.set SCSI_Out__1__PRT, CYREG_PRT4_PRT
+.set SCSI_Out__1__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL
+.set SCSI_Out__1__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN
+.set SCSI_Out__1__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0
+.set SCSI_Out__1__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1
+.set SCSI_Out__1__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0
+.set SCSI_Out__1__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1
+.set SCSI_Out__1__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT
+.set SCSI_Out__1__PS, CYREG_PRT4_PS
+.set SCSI_Out__1__SHIFT, 6
+.set SCSI_Out__1__SLW, CYREG_PRT4_SLW
+.set SCSI_Out__2__AG, CYREG_PRT0_AG
+.set SCSI_Out__2__AMUX, CYREG_PRT0_AMUX
+.set SCSI_Out__2__BIE, CYREG_PRT0_BIE
+.set SCSI_Out__2__BIT_MASK, CYREG_PRT0_BIT_MASK
+.set SCSI_Out__2__BYP, CYREG_PRT0_BYP
+.set SCSI_Out__2__CTL, CYREG_PRT0_CTL
+.set SCSI_Out__2__DM0, CYREG_PRT0_DM0
+.set SCSI_Out__2__DM1, CYREG_PRT0_DM1
+.set SCSI_Out__2__DM2, CYREG_PRT0_DM2
+.set SCSI_Out__2__DR, CYREG_PRT0_DR
+.set SCSI_Out__2__INP_DIS, CYREG_PRT0_INP_DIS
+.set SCSI_Out__2__INTTYPE, CYREG_PICU0_INTTYPE7
+.set SCSI_Out__2__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG
+.set SCSI_Out__2__LCD_EN, CYREG_PRT0_LCD_EN
+.set SCSI_Out__2__MASK, 0x80
+.set SCSI_Out__2__PC, CYREG_PRT0_PC7
+.set SCSI_Out__2__PORT, 0
+.set SCSI_Out__2__PRT, CYREG_PRT0_PRT
+.set SCSI_Out__2__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL
+.set SCSI_Out__2__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN
+.set SCSI_Out__2__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0
+.set SCSI_Out__2__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1
+.set SCSI_Out__2__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0
+.set SCSI_Out__2__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1
+.set SCSI_Out__2__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT
+.set SCSI_Out__2__PS, CYREG_PRT0_PS
+.set SCSI_Out__2__SHIFT, 7
+.set SCSI_Out__2__SLW, CYREG_PRT0_SLW
+.set SCSI_Out__3__AG, CYREG_PRT0_AG
+.set SCSI_Out__3__AMUX, CYREG_PRT0_AMUX
+.set SCSI_Out__3__BIE, CYREG_PRT0_BIE
+.set SCSI_Out__3__BIT_MASK, CYREG_PRT0_BIT_MASK
+.set SCSI_Out__3__BYP, CYREG_PRT0_BYP
+.set SCSI_Out__3__CTL, CYREG_PRT0_CTL
+.set SCSI_Out__3__DM0, CYREG_PRT0_DM0
+.set SCSI_Out__3__DM1, CYREG_PRT0_DM1
+.set SCSI_Out__3__DM2, CYREG_PRT0_DM2
+.set SCSI_Out__3__DR, CYREG_PRT0_DR
+.set SCSI_Out__3__INP_DIS, CYREG_PRT0_INP_DIS
+.set SCSI_Out__3__INTTYPE, CYREG_PICU0_INTTYPE5
+.set SCSI_Out__3__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG
+.set SCSI_Out__3__LCD_EN, CYREG_PRT0_LCD_EN
+.set SCSI_Out__3__MASK, 0x20
+.set SCSI_Out__3__PC, CYREG_PRT0_PC5
+.set SCSI_Out__3__PORT, 0
+.set SCSI_Out__3__PRT, CYREG_PRT0_PRT
+.set SCSI_Out__3__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL
+.set SCSI_Out__3__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN
+.set SCSI_Out__3__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0
+.set SCSI_Out__3__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1
+.set SCSI_Out__3__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0
+.set SCSI_Out__3__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1
+.set SCSI_Out__3__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT
+.set SCSI_Out__3__PS, CYREG_PRT0_PS
+.set SCSI_Out__3__SHIFT, 5
+.set SCSI_Out__3__SLW, CYREG_PRT0_SLW
+.set SCSI_Out__4__AG, CYREG_PRT0_AG
+.set SCSI_Out__4__AMUX, CYREG_PRT0_AMUX
+.set SCSI_Out__4__BIE, CYREG_PRT0_BIE
+.set SCSI_Out__4__BIT_MASK, CYREG_PRT0_BIT_MASK
+.set SCSI_Out__4__BYP, CYREG_PRT0_BYP
+.set SCSI_Out__4__CTL, CYREG_PRT0_CTL
+.set SCSI_Out__4__DM0, CYREG_PRT0_DM0
+.set SCSI_Out__4__DM1, CYREG_PRT0_DM1
+.set SCSI_Out__4__DM2, CYREG_PRT0_DM2
+.set SCSI_Out__4__DR, CYREG_PRT0_DR
+.set SCSI_Out__4__INP_DIS, CYREG_PRT0_INP_DIS
+.set SCSI_Out__4__INTTYPE, CYREG_PICU0_INTTYPE3
+.set SCSI_Out__4__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG
+.set SCSI_Out__4__LCD_EN, CYREG_PRT0_LCD_EN
+.set SCSI_Out__4__MASK, 0x08
+.set SCSI_Out__4__PC, CYREG_PRT0_PC3
+.set SCSI_Out__4__PORT, 0
+.set SCSI_Out__4__PRT, CYREG_PRT0_PRT
+.set SCSI_Out__4__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL
+.set SCSI_Out__4__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN
+.set SCSI_Out__4__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0
+.set SCSI_Out__4__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1
+.set SCSI_Out__4__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0
+.set SCSI_Out__4__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1
+.set SCSI_Out__4__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT
+.set SCSI_Out__4__PS, CYREG_PRT0_PS
+.set SCSI_Out__4__SHIFT, 3
+.set SCSI_Out__4__SLW, CYREG_PRT0_SLW
+.set SCSI_Out__5__AG, CYREG_PRT0_AG
+.set SCSI_Out__5__AMUX, CYREG_PRT0_AMUX
+.set SCSI_Out__5__BIE, CYREG_PRT0_BIE
+.set SCSI_Out__5__BIT_MASK, CYREG_PRT0_BIT_MASK
+.set SCSI_Out__5__BYP, CYREG_PRT0_BYP
+.set SCSI_Out__5__CTL, CYREG_PRT0_CTL
+.set SCSI_Out__5__DM0, CYREG_PRT0_DM0
+.set SCSI_Out__5__DM1, CYREG_PRT0_DM1
+.set SCSI_Out__5__DM2, CYREG_PRT0_DM2
+.set SCSI_Out__5__DR, CYREG_PRT0_DR
+.set SCSI_Out__5__INP_DIS, CYREG_PRT0_INP_DIS
+.set SCSI_Out__5__INTTYPE, CYREG_PICU0_INTTYPE1
+.set SCSI_Out__5__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG
+.set SCSI_Out__5__LCD_EN, CYREG_PRT0_LCD_EN
+.set SCSI_Out__5__MASK, 0x02
+.set SCSI_Out__5__PC, CYREG_PRT0_PC1
+.set SCSI_Out__5__PORT, 0
+.set SCSI_Out__5__PRT, CYREG_PRT0_PRT
+.set SCSI_Out__5__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL
+.set SCSI_Out__5__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN
+.set SCSI_Out__5__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0
+.set SCSI_Out__5__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1
+.set SCSI_Out__5__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0
+.set SCSI_Out__5__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1
+.set SCSI_Out__5__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT
+.set SCSI_Out__5__PS, CYREG_PRT0_PS
+.set SCSI_Out__5__SHIFT, 1
+.set SCSI_Out__5__SLW, CYREG_PRT0_SLW
+.set SCSI_Out__6__AG, CYREG_PRT4_AG
+.set SCSI_Out__6__AMUX, CYREG_PRT4_AMUX
+.set SCSI_Out__6__BIE, CYREG_PRT4_BIE
+.set SCSI_Out__6__BIT_MASK, CYREG_PRT4_BIT_MASK
+.set SCSI_Out__6__BYP, CYREG_PRT4_BYP
+.set SCSI_Out__6__CTL, CYREG_PRT4_CTL
+.set SCSI_Out__6__DM0, CYREG_PRT4_DM0
+.set SCSI_Out__6__DM1, CYREG_PRT4_DM1
+.set SCSI_Out__6__DM2, CYREG_PRT4_DM2
+.set SCSI_Out__6__DR, CYREG_PRT4_DR
+.set SCSI_Out__6__INP_DIS, CYREG_PRT4_INP_DIS
+.set SCSI_Out__6__INTTYPE, CYREG_PICU4_INTTYPE1
+.set SCSI_Out__6__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG
+.set SCSI_Out__6__LCD_EN, CYREG_PRT4_LCD_EN
+.set SCSI_Out__6__MASK, 0x02
+.set SCSI_Out__6__PC, CYREG_PRT4_PC1
+.set SCSI_Out__6__PORT, 4
+.set SCSI_Out__6__PRT, CYREG_PRT4_PRT
+.set SCSI_Out__6__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL
+.set SCSI_Out__6__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN
+.set SCSI_Out__6__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0
+.set SCSI_Out__6__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1
+.set SCSI_Out__6__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0
+.set SCSI_Out__6__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1
+.set SCSI_Out__6__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT
+.set SCSI_Out__6__PS, CYREG_PRT4_PS
+.set SCSI_Out__6__SHIFT, 1
+.set SCSI_Out__6__SLW, CYREG_PRT4_SLW
+.set SCSI_Out__7__AG, CYREG_PRT12_AG
+.set SCSI_Out__7__BIE, CYREG_PRT12_BIE
+.set SCSI_Out__7__BIT_MASK, CYREG_PRT12_BIT_MASK
+.set SCSI_Out__7__BYP, CYREG_PRT12_BYP
+.set SCSI_Out__7__DM0, CYREG_PRT12_DM0
+.set SCSI_Out__7__DM1, CYREG_PRT12_DM1
+.set SCSI_Out__7__DM2, CYREG_PRT12_DM2
+.set SCSI_Out__7__DR, CYREG_PRT12_DR
+.set SCSI_Out__7__INP_DIS, CYREG_PRT12_INP_DIS
+.set SCSI_Out__7__INTTYPE, CYREG_PICU12_INTTYPE3
+.set SCSI_Out__7__MASK, 0x08
+.set SCSI_Out__7__PC, CYREG_PRT12_PC3
+.set SCSI_Out__7__PORT, 12
+.set SCSI_Out__7__PRT, CYREG_PRT12_PRT
+.set SCSI_Out__7__PRTDSI__DBL_SYNC_IN, CYREG_PRT12_DBL_SYNC_IN
+.set SCSI_Out__7__PRTDSI__OE_SEL0, CYREG_PRT12_OE_SEL0
+.set SCSI_Out__7__PRTDSI__OE_SEL1, CYREG_PRT12_OE_SEL1
+.set SCSI_Out__7__PRTDSI__OUT_SEL0, CYREG_PRT12_OUT_SEL0
+.set SCSI_Out__7__PRTDSI__OUT_SEL1, CYREG_PRT12_OUT_SEL1
+.set SCSI_Out__7__PRTDSI__SYNC_OUT, CYREG_PRT12_SYNC_OUT
+.set SCSI_Out__7__PS, CYREG_PRT12_PS
+.set SCSI_Out__7__SHIFT, 3
+.set SCSI_Out__7__SIO_CFG, CYREG_PRT12_SIO_CFG
+.set SCSI_Out__7__SIO_DIFF, CYREG_PRT12_SIO_DIFF
+.set SCSI_Out__7__SIO_HYST_EN, CYREG_PRT12_SIO_HYST_EN
+.set SCSI_Out__7__SIO_REG_HIFREQ, CYREG_PRT12_SIO_REG_HIFREQ
+.set SCSI_Out__7__SLW, CYREG_PRT12_SLW
+.set SCSI_Out__BSY__AG, CYREG_PRT4_AG
+.set SCSI_Out__BSY__AMUX, CYREG_PRT4_AMUX
+.set SCSI_Out__BSY__BIE, CYREG_PRT4_BIE
+.set SCSI_Out__BSY__BIT_MASK, CYREG_PRT4_BIT_MASK
+.set SCSI_Out__BSY__BYP, CYREG_PRT4_BYP
+.set SCSI_Out__BSY__CTL, CYREG_PRT4_CTL
+.set SCSI_Out__BSY__DM0, CYREG_PRT4_DM0
+.set SCSI_Out__BSY__DM1, CYREG_PRT4_DM1
+.set SCSI_Out__BSY__DM2, CYREG_PRT4_DM2
+.set SCSI_Out__BSY__DR, CYREG_PRT4_DR
+.set SCSI_Out__BSY__INP_DIS, CYREG_PRT4_INP_DIS
+.set SCSI_Out__BSY__INTTYPE, CYREG_PICU4_INTTYPE6
+.set SCSI_Out__BSY__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG
+.set SCSI_Out__BSY__LCD_EN, CYREG_PRT4_LCD_EN
+.set SCSI_Out__BSY__MASK, 0x40
+.set SCSI_Out__BSY__PC, CYREG_PRT4_PC6
+.set SCSI_Out__BSY__PORT, 4
+.set SCSI_Out__BSY__PRT, CYREG_PRT4_PRT
+.set SCSI_Out__BSY__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL
+.set SCSI_Out__BSY__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN
+.set SCSI_Out__BSY__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0
+.set SCSI_Out__BSY__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1
+.set SCSI_Out__BSY__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0
+.set SCSI_Out__BSY__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1
+.set SCSI_Out__BSY__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT
+.set SCSI_Out__BSY__PS, CYREG_PRT4_PS
+.set SCSI_Out__BSY__SHIFT, 6
+.set SCSI_Out__BSY__SLW, CYREG_PRT4_SLW
+.set SCSI_Out__CD_raw__AG, CYREG_PRT0_AG
+.set SCSI_Out__CD_raw__AMUX, CYREG_PRT0_AMUX
+.set SCSI_Out__CD_raw__BIE, CYREG_PRT0_BIE
+.set SCSI_Out__CD_raw__BIT_MASK, CYREG_PRT0_BIT_MASK
+.set SCSI_Out__CD_raw__BYP, CYREG_PRT0_BYP
+.set SCSI_Out__CD_raw__CTL, CYREG_PRT0_CTL
+.set SCSI_Out__CD_raw__DM0, CYREG_PRT0_DM0
+.set SCSI_Out__CD_raw__DM1, CYREG_PRT0_DM1
+.set SCSI_Out__CD_raw__DM2, CYREG_PRT0_DM2
+.set SCSI_Out__CD_raw__DR, CYREG_PRT0_DR
+.set SCSI_Out__CD_raw__INP_DIS, CYREG_PRT0_INP_DIS
+.set SCSI_Out__CD_raw__INTTYPE, CYREG_PICU0_INTTYPE1
+.set SCSI_Out__CD_raw__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG
+.set SCSI_Out__CD_raw__LCD_EN, CYREG_PRT0_LCD_EN
+.set SCSI_Out__CD_raw__MASK, 0x02
+.set SCSI_Out__CD_raw__PC, CYREG_PRT0_PC1
+.set SCSI_Out__CD_raw__PORT, 0
+.set SCSI_Out__CD_raw__PRT, CYREG_PRT0_PRT
+.set SCSI_Out__CD_raw__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL
+.set SCSI_Out__CD_raw__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN
+.set SCSI_Out__CD_raw__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0
+.set SCSI_Out__CD_raw__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1
+.set SCSI_Out__CD_raw__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0
+.set SCSI_Out__CD_raw__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1
+.set SCSI_Out__CD_raw__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT
+.set SCSI_Out__CD_raw__PS, CYREG_PRT0_PS
+.set SCSI_Out__CD_raw__SHIFT, 1
+.set SCSI_Out__CD_raw__SLW, CYREG_PRT0_SLW
+.set SCSI_Out__DBP_raw__AG, CYREG_PRT6_AG
+.set SCSI_Out__DBP_raw__AMUX, CYREG_PRT6_AMUX
+.set SCSI_Out__DBP_raw__BIE, CYREG_PRT6_BIE
+.set SCSI_Out__DBP_raw__BIT_MASK, CYREG_PRT6_BIT_MASK
+.set SCSI_Out__DBP_raw__BYP, CYREG_PRT6_BYP
+.set SCSI_Out__DBP_raw__CTL, CYREG_PRT6_CTL
+.set SCSI_Out__DBP_raw__DM0, CYREG_PRT6_DM0
+.set SCSI_Out__DBP_raw__DM1, CYREG_PRT6_DM1
+.set SCSI_Out__DBP_raw__DM2, CYREG_PRT6_DM2
+.set SCSI_Out__DBP_raw__DR, CYREG_PRT6_DR
+.set SCSI_Out__DBP_raw__INP_DIS, CYREG_PRT6_INP_DIS
+.set SCSI_Out__DBP_raw__INTTYPE, CYREG_PICU6_INTTYPE2
+.set SCSI_Out__DBP_raw__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
+.set SCSI_Out__DBP_raw__LCD_EN, CYREG_PRT6_LCD_EN
+.set SCSI_Out__DBP_raw__MASK, 0x04
+.set SCSI_Out__DBP_raw__PC, CYREG_PRT6_PC2
+.set SCSI_Out__DBP_raw__PORT, 6
+.set SCSI_Out__DBP_raw__PRT, CYREG_PRT6_PRT
+.set SCSI_Out__DBP_raw__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL
+.set SCSI_Out__DBP_raw__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN
+.set SCSI_Out__DBP_raw__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0
+.set SCSI_Out__DBP_raw__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1
+.set SCSI_Out__DBP_raw__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0
+.set SCSI_Out__DBP_raw__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1
+.set SCSI_Out__DBP_raw__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT
+.set SCSI_Out__DBP_raw__PS, CYREG_PRT6_PS
+.set SCSI_Out__DBP_raw__SHIFT, 2
+.set SCSI_Out__DBP_raw__SLW, CYREG_PRT6_SLW
+.set SCSI_Out__IO_raw__AG, CYREG_PRT12_AG
+.set SCSI_Out__IO_raw__BIE, CYREG_PRT12_BIE
+.set SCSI_Out__IO_raw__BIT_MASK, CYREG_PRT12_BIT_MASK
+.set SCSI_Out__IO_raw__BYP, CYREG_PRT12_BYP
+.set SCSI_Out__IO_raw__DM0, CYREG_PRT12_DM0
+.set SCSI_Out__IO_raw__DM1, CYREG_PRT12_DM1
+.set SCSI_Out__IO_raw__DM2, CYREG_PRT12_DM2
+.set SCSI_Out__IO_raw__DR, CYREG_PRT12_DR
+.set SCSI_Out__IO_raw__INP_DIS, CYREG_PRT12_INP_DIS
+.set SCSI_Out__IO_raw__INTTYPE, CYREG_PICU12_INTTYPE3
+.set SCSI_Out__IO_raw__MASK, 0x08
+.set SCSI_Out__IO_raw__PC, CYREG_PRT12_PC3
+.set SCSI_Out__IO_raw__PORT, 12
+.set SCSI_Out__IO_raw__PRT, CYREG_PRT12_PRT
+.set SCSI_Out__IO_raw__PRTDSI__DBL_SYNC_IN, CYREG_PRT12_DBL_SYNC_IN
+.set SCSI_Out__IO_raw__PRTDSI__OE_SEL0, CYREG_PRT12_OE_SEL0
+.set SCSI_Out__IO_raw__PRTDSI__OE_SEL1, CYREG_PRT12_OE_SEL1
+.set SCSI_Out__IO_raw__PRTDSI__OUT_SEL0, CYREG_PRT12_OUT_SEL0
+.set SCSI_Out__IO_raw__PRTDSI__OUT_SEL1, CYREG_PRT12_OUT_SEL1
+.set SCSI_Out__IO_raw__PRTDSI__SYNC_OUT, CYREG_PRT12_SYNC_OUT
+.set SCSI_Out__IO_raw__PS, CYREG_PRT12_PS
+.set SCSI_Out__IO_raw__SHIFT, 3
+.set SCSI_Out__IO_raw__SIO_CFG, CYREG_PRT12_SIO_CFG
+.set SCSI_Out__IO_raw__SIO_DIFF, CYREG_PRT12_SIO_DIFF
+.set SCSI_Out__IO_raw__SIO_HYST_EN, CYREG_PRT12_SIO_HYST_EN
+.set SCSI_Out__IO_raw__SIO_REG_HIFREQ, CYREG_PRT12_SIO_REG_HIFREQ
+.set SCSI_Out__IO_raw__SLW, CYREG_PRT12_SLW
+.set SCSI_Out__MSG_raw__AG, CYREG_PRT0_AG
+.set SCSI_Out__MSG_raw__AMUX, CYREG_PRT0_AMUX
+.set SCSI_Out__MSG_raw__BIE, CYREG_PRT0_BIE
+.set SCSI_Out__MSG_raw__BIT_MASK, CYREG_PRT0_BIT_MASK
+.set SCSI_Out__MSG_raw__BYP, CYREG_PRT0_BYP
+.set SCSI_Out__MSG_raw__CTL, CYREG_PRT0_CTL
+.set SCSI_Out__MSG_raw__DM0, CYREG_PRT0_DM0
+.set SCSI_Out__MSG_raw__DM1, CYREG_PRT0_DM1
+.set SCSI_Out__MSG_raw__DM2, CYREG_PRT0_DM2
+.set SCSI_Out__MSG_raw__DR, CYREG_PRT0_DR
+.set SCSI_Out__MSG_raw__INP_DIS, CYREG_PRT0_INP_DIS
+.set SCSI_Out__MSG_raw__INTTYPE, CYREG_PICU0_INTTYPE5
+.set SCSI_Out__MSG_raw__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG
+.set SCSI_Out__MSG_raw__LCD_EN, CYREG_PRT0_LCD_EN
+.set SCSI_Out__MSG_raw__MASK, 0x20
+.set SCSI_Out__MSG_raw__PC, CYREG_PRT0_PC5
+.set SCSI_Out__MSG_raw__PORT, 0
+.set SCSI_Out__MSG_raw__PRT, CYREG_PRT0_PRT
+.set SCSI_Out__MSG_raw__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL
+.set SCSI_Out__MSG_raw__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN
+.set SCSI_Out__MSG_raw__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0
+.set SCSI_Out__MSG_raw__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1
+.set SCSI_Out__MSG_raw__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0
+.set SCSI_Out__MSG_raw__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1
+.set SCSI_Out__MSG_raw__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT
+.set SCSI_Out__MSG_raw__PS, CYREG_PRT0_PS
+.set SCSI_Out__MSG_raw__SHIFT, 5
+.set SCSI_Out__MSG_raw__SLW, CYREG_PRT0_SLW
+.set SCSI_Out__REQ__AG, CYREG_PRT4_AG
+.set SCSI_Out__REQ__AMUX, CYREG_PRT4_AMUX
+.set SCSI_Out__REQ__BIE, CYREG_PRT4_BIE
+.set SCSI_Out__REQ__BIT_MASK, CYREG_PRT4_BIT_MASK
+.set SCSI_Out__REQ__BYP, CYREG_PRT4_BYP
+.set SCSI_Out__REQ__CTL, CYREG_PRT4_CTL
+.set SCSI_Out__REQ__DM0, CYREG_PRT4_DM0
+.set SCSI_Out__REQ__DM1, CYREG_PRT4_DM1
+.set SCSI_Out__REQ__DM2, CYREG_PRT4_DM2
+.set SCSI_Out__REQ__DR, CYREG_PRT4_DR
+.set SCSI_Out__REQ__INP_DIS, CYREG_PRT4_INP_DIS
+.set SCSI_Out__REQ__INTTYPE, CYREG_PICU4_INTTYPE1
+.set SCSI_Out__REQ__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG
+.set SCSI_Out__REQ__LCD_EN, CYREG_PRT4_LCD_EN
+.set SCSI_Out__REQ__MASK, 0x02
+.set SCSI_Out__REQ__PC, CYREG_PRT4_PC1
+.set SCSI_Out__REQ__PORT, 4
+.set SCSI_Out__REQ__PRT, CYREG_PRT4_PRT
+.set SCSI_Out__REQ__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL
+.set SCSI_Out__REQ__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN
+.set SCSI_Out__REQ__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0
+.set SCSI_Out__REQ__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1
+.set SCSI_Out__REQ__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0
+.set SCSI_Out__REQ__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1
+.set SCSI_Out__REQ__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT
+.set SCSI_Out__REQ__PS, CYREG_PRT4_PS
+.set SCSI_Out__REQ__SHIFT, 1
+.set SCSI_Out__REQ__SLW, CYREG_PRT4_SLW
+.set SCSI_Out__RST__AG, CYREG_PRT0_AG
+.set SCSI_Out__RST__AMUX, CYREG_PRT0_AMUX
+.set SCSI_Out__RST__BIE, CYREG_PRT0_BIE
+.set SCSI_Out__RST__BIT_MASK, CYREG_PRT0_BIT_MASK
+.set SCSI_Out__RST__BYP, CYREG_PRT0_BYP
+.set SCSI_Out__RST__CTL, CYREG_PRT0_CTL
+.set SCSI_Out__RST__DM0, CYREG_PRT0_DM0
+.set SCSI_Out__RST__DM1, CYREG_PRT0_DM1
+.set SCSI_Out__RST__DM2, CYREG_PRT0_DM2
+.set SCSI_Out__RST__DR, CYREG_PRT0_DR
+.set SCSI_Out__RST__INP_DIS, CYREG_PRT0_INP_DIS
+.set SCSI_Out__RST__INTTYPE, CYREG_PICU0_INTTYPE7
+.set SCSI_Out__RST__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG
+.set SCSI_Out__RST__LCD_EN, CYREG_PRT0_LCD_EN
+.set SCSI_Out__RST__MASK, 0x80
+.set SCSI_Out__RST__PC, CYREG_PRT0_PC7
+.set SCSI_Out__RST__PORT, 0
+.set SCSI_Out__RST__PRT, CYREG_PRT0_PRT
+.set SCSI_Out__RST__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL
+.set SCSI_Out__RST__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN
+.set SCSI_Out__RST__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0
+.set SCSI_Out__RST__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1
+.set SCSI_Out__RST__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0
+.set SCSI_Out__RST__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1
+.set SCSI_Out__RST__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT
+.set SCSI_Out__RST__PS, CYREG_PRT0_PS
+.set SCSI_Out__RST__SHIFT, 7
+.set SCSI_Out__RST__SLW, CYREG_PRT0_SLW
+.set SCSI_Out__SEL__AG, CYREG_PRT0_AG
+.set SCSI_Out__SEL__AMUX, CYREG_PRT0_AMUX
+.set SCSI_Out__SEL__BIE, CYREG_PRT0_BIE
+.set SCSI_Out__SEL__BIT_MASK, CYREG_PRT0_BIT_MASK
+.set SCSI_Out__SEL__BYP, CYREG_PRT0_BYP
+.set SCSI_Out__SEL__CTL, CYREG_PRT0_CTL
+.set SCSI_Out__SEL__DM0, CYREG_PRT0_DM0
+.set SCSI_Out__SEL__DM1, CYREG_PRT0_DM1
+.set SCSI_Out__SEL__DM2, CYREG_PRT0_DM2
+.set SCSI_Out__SEL__DR, CYREG_PRT0_DR
+.set SCSI_Out__SEL__INP_DIS, CYREG_PRT0_INP_DIS
+.set SCSI_Out__SEL__INTTYPE, CYREG_PICU0_INTTYPE3
+.set SCSI_Out__SEL__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG
+.set SCSI_Out__SEL__LCD_EN, CYREG_PRT0_LCD_EN
+.set SCSI_Out__SEL__MASK, 0x08
+.set SCSI_Out__SEL__PC, CYREG_PRT0_PC3
+.set SCSI_Out__SEL__PORT, 0
+.set SCSI_Out__SEL__PRT, CYREG_PRT0_PRT
+.set SCSI_Out__SEL__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL
+.set SCSI_Out__SEL__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN
+.set SCSI_Out__SEL__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0
+.set SCSI_Out__SEL__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1
+.set SCSI_Out__SEL__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0
+.set SCSI_Out__SEL__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1
+.set SCSI_Out__SEL__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT
+.set SCSI_Out__SEL__PS, CYREG_PRT0_PS
+.set SCSI_Out__SEL__SHIFT, 3
+.set SCSI_Out__SEL__SLW, CYREG_PRT0_SLW
+.set SCSI_Out_Bits_Sync_ctrl_reg__0__MASK, 0x01
+.set SCSI_Out_Bits_Sync_ctrl_reg__0__POS, 0
+.set SCSI_Out_Bits_Sync_ctrl_reg__1__MASK, 0x02
+.set SCSI_Out_Bits_Sync_ctrl_reg__1__POS, 1
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB07_08_ACTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB07_08_CTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB07_08_CTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB07_08_CTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB07_08_CTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB07_08_MSK
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB07_08_MSK
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB07_08_MSK
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB07_08_MSK
+.set SCSI_Out_Bits_Sync_ctrl_reg__2__MASK, 0x04
+.set SCSI_Out_Bits_Sync_ctrl_reg__2__POS, 2
+.set SCSI_Out_Bits_Sync_ctrl_reg__3__MASK, 0x08
+.set SCSI_Out_Bits_Sync_ctrl_reg__3__POS, 3
+.set SCSI_Out_Bits_Sync_ctrl_reg__4__MASK, 0x10
+.set SCSI_Out_Bits_Sync_ctrl_reg__4__POS, 4
+.set SCSI_Out_Bits_Sync_ctrl_reg__5__MASK, 0x20
+.set SCSI_Out_Bits_Sync_ctrl_reg__5__POS, 5
+.set SCSI_Out_Bits_Sync_ctrl_reg__6__MASK, 0x40
+.set SCSI_Out_Bits_Sync_ctrl_reg__6__POS, 6
+.set SCSI_Out_Bits_Sync_ctrl_reg__7__MASK, 0x80
+.set SCSI_Out_Bits_Sync_ctrl_reg__7__POS, 7
+.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB07_ACTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB07_CTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB07_ST_CTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB07_CTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB07_ST_CTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__MASK, 0xFF
+.set SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB07_MSK_ACTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB07_MSK_ACTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB07_MSK
+.set SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK, 0x01
+.set SCSI_Out_Ctl_Sync_ctrl_reg__0__POS, 0
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB11_12_ACTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB11_12_CTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB11_12_CTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB11_12_CTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB11_12_CTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB11_12_MSK
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB11_12_MSK
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB11_12_MSK
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB11_12_MSK
+.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB11_ACTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB11_CTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB11_ST_CTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB11_CTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB11_ST_CTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK, 0x01
+.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB11_MSK
+.set SCSI_Out_DBx__0__AG, CYREG_PRT6_AG
+.set SCSI_Out_DBx__0__AMUX, CYREG_PRT6_AMUX
+.set SCSI_Out_DBx__0__BIE, CYREG_PRT6_BIE
+.set SCSI_Out_DBx__0__BIT_MASK, CYREG_PRT6_BIT_MASK
+.set SCSI_Out_DBx__0__BYP, CYREG_PRT6_BYP
+.set SCSI_Out_DBx__0__CTL, CYREG_PRT6_CTL
+.set SCSI_Out_DBx__0__DM0, CYREG_PRT6_DM0
+.set SCSI_Out_DBx__0__DM1, CYREG_PRT6_DM1
+.set SCSI_Out_DBx__0__DM2, CYREG_PRT6_DM2
+.set SCSI_Out_DBx__0__DR, CYREG_PRT6_DR
+.set SCSI_Out_DBx__0__INP_DIS, CYREG_PRT6_INP_DIS
+.set SCSI_Out_DBx__0__INTTYPE, CYREG_PICU6_INTTYPE7
+.set SCSI_Out_DBx__0__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
+.set SCSI_Out_DBx__0__LCD_EN, CYREG_PRT6_LCD_EN
+.set SCSI_Out_DBx__0__MASK, 0x80
+.set SCSI_Out_DBx__0__PC, CYREG_PRT6_PC7
+.set SCSI_Out_DBx__0__PORT, 6
+.set SCSI_Out_DBx__0__PRT, CYREG_PRT6_PRT
+.set SCSI_Out_DBx__0__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL
+.set SCSI_Out_DBx__0__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN
+.set SCSI_Out_DBx__0__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0
+.set SCSI_Out_DBx__0__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1
+.set SCSI_Out_DBx__0__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0
+.set SCSI_Out_DBx__0__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1
+.set SCSI_Out_DBx__0__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT
+.set SCSI_Out_DBx__0__PS, CYREG_PRT6_PS
+.set SCSI_Out_DBx__0__SHIFT, 7
+.set SCSI_Out_DBx__0__SLW, CYREG_PRT6_SLW
+.set SCSI_Out_DBx__1__AG, CYREG_PRT6_AG
+.set SCSI_Out_DBx__1__AMUX, CYREG_PRT6_AMUX
+.set SCSI_Out_DBx__1__BIE, CYREG_PRT6_BIE
+.set SCSI_Out_DBx__1__BIT_MASK, CYREG_PRT6_BIT_MASK
+.set SCSI_Out_DBx__1__BYP, CYREG_PRT6_BYP
+.set SCSI_Out_DBx__1__CTL, CYREG_PRT6_CTL
+.set SCSI_Out_DBx__1__DM0, CYREG_PRT6_DM0
+.set SCSI_Out_DBx__1__DM1, CYREG_PRT6_DM1
+.set SCSI_Out_DBx__1__DM2, CYREG_PRT6_DM2
+.set SCSI_Out_DBx__1__DR, CYREG_PRT6_DR
+.set SCSI_Out_DBx__1__INP_DIS, CYREG_PRT6_INP_DIS
+.set SCSI_Out_DBx__1__INTTYPE, CYREG_PICU6_INTTYPE5
+.set SCSI_Out_DBx__1__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
+.set SCSI_Out_DBx__1__LCD_EN, CYREG_PRT6_LCD_EN
+.set SCSI_Out_DBx__1__MASK, 0x20
+.set SCSI_Out_DBx__1__PC, CYREG_PRT6_PC5
+.set SCSI_Out_DBx__1__PORT, 6
+.set SCSI_Out_DBx__1__PRT, CYREG_PRT6_PRT
+.set SCSI_Out_DBx__1__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL
+.set SCSI_Out_DBx__1__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN
+.set SCSI_Out_DBx__1__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0
+.set SCSI_Out_DBx__1__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1
+.set SCSI_Out_DBx__1__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0
+.set SCSI_Out_DBx__1__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1
+.set SCSI_Out_DBx__1__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT
+.set SCSI_Out_DBx__1__PS, CYREG_PRT6_PS
+.set SCSI_Out_DBx__1__SHIFT, 5
+.set SCSI_Out_DBx__1__SLW, CYREG_PRT6_SLW
+.set SCSI_Out_DBx__2__AG, CYREG_PRT12_AG
+.set SCSI_Out_DBx__2__BIE, CYREG_PRT12_BIE
+.set SCSI_Out_DBx__2__BIT_MASK, CYREG_PRT12_BIT_MASK
+.set SCSI_Out_DBx__2__BYP, CYREG_PRT12_BYP
+.set SCSI_Out_DBx__2__DM0, CYREG_PRT12_DM0
+.set SCSI_Out_DBx__2__DM1, CYREG_PRT12_DM1
+.set SCSI_Out_DBx__2__DM2, CYREG_PRT12_DM2
+.set SCSI_Out_DBx__2__DR, CYREG_PRT12_DR
+.set SCSI_Out_DBx__2__INP_DIS, CYREG_PRT12_INP_DIS
+.set SCSI_Out_DBx__2__INTTYPE, CYREG_PICU12_INTTYPE5
+.set SCSI_Out_DBx__2__MASK, 0x20
+.set SCSI_Out_DBx__2__PC, CYREG_PRT12_PC5
+.set SCSI_Out_DBx__2__PORT, 12
+.set SCSI_Out_DBx__2__PRT, CYREG_PRT12_PRT
+.set SCSI_Out_DBx__2__PRTDSI__DBL_SYNC_IN, CYREG_PRT12_DBL_SYNC_IN
+.set SCSI_Out_DBx__2__PRTDSI__OE_SEL0, CYREG_PRT12_OE_SEL0
+.set SCSI_Out_DBx__2__PRTDSI__OE_SEL1, CYREG_PRT12_OE_SEL1
+.set SCSI_Out_DBx__2__PRTDSI__OUT_SEL0, CYREG_PRT12_OUT_SEL0
+.set SCSI_Out_DBx__2__PRTDSI__OUT_SEL1, CYREG_PRT12_OUT_SEL1
+.set SCSI_Out_DBx__2__PRTDSI__SYNC_OUT, CYREG_PRT12_SYNC_OUT
+.set SCSI_Out_DBx__2__PS, CYREG_PRT12_PS
+.set SCSI_Out_DBx__2__SHIFT, 5
+.set SCSI_Out_DBx__2__SIO_CFG, CYREG_PRT12_SIO_CFG
+.set SCSI_Out_DBx__2__SIO_DIFF, CYREG_PRT12_SIO_DIFF
+.set SCSI_Out_DBx__2__SIO_HYST_EN, CYREG_PRT12_SIO_HYST_EN
+.set SCSI_Out_DBx__2__SIO_REG_HIFREQ, CYREG_PRT12_SIO_REG_HIFREQ
+.set SCSI_Out_DBx__2__SLW, CYREG_PRT12_SLW
+.set SCSI_Out_DBx__3__AG, CYREG_PRT2_AG
+.set SCSI_Out_DBx__3__AMUX, CYREG_PRT2_AMUX
+.set SCSI_Out_DBx__3__BIE, CYREG_PRT2_BIE
+.set SCSI_Out_DBx__3__BIT_MASK, CYREG_PRT2_BIT_MASK
+.set SCSI_Out_DBx__3__BYP, CYREG_PRT2_BYP
+.set SCSI_Out_DBx__3__CTL, CYREG_PRT2_CTL
+.set SCSI_Out_DBx__3__DM0, CYREG_PRT2_DM0
+.set SCSI_Out_DBx__3__DM1, CYREG_PRT2_DM1
+.set SCSI_Out_DBx__3__DM2, CYREG_PRT2_DM2
+.set SCSI_Out_DBx__3__DR, CYREG_PRT2_DR
+.set SCSI_Out_DBx__3__INP_DIS, CYREG_PRT2_INP_DIS
+.set SCSI_Out_DBx__3__INTTYPE, CYREG_PICU2_INTTYPE7
+.set SCSI_Out_DBx__3__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG
+.set SCSI_Out_DBx__3__LCD_EN, CYREG_PRT2_LCD_EN
+.set SCSI_Out_DBx__3__MASK, 0x80
+.set SCSI_Out_DBx__3__PC, CYREG_PRT2_PC7
+.set SCSI_Out_DBx__3__PORT, 2
+.set SCSI_Out_DBx__3__PRT, CYREG_PRT2_PRT
+.set SCSI_Out_DBx__3__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL
+.set SCSI_Out_DBx__3__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN
+.set SCSI_Out_DBx__3__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0
+.set SCSI_Out_DBx__3__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1
+.set SCSI_Out_DBx__3__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0
+.set SCSI_Out_DBx__3__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1
+.set SCSI_Out_DBx__3__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT
+.set SCSI_Out_DBx__3__PS, CYREG_PRT2_PS
+.set SCSI_Out_DBx__3__SHIFT, 7
+.set SCSI_Out_DBx__3__SLW, CYREG_PRT2_SLW
+.set SCSI_Out_DBx__4__AG, CYREG_PRT2_AG
+.set SCSI_Out_DBx__4__AMUX, CYREG_PRT2_AMUX
+.set SCSI_Out_DBx__4__BIE, CYREG_PRT2_BIE
+.set SCSI_Out_DBx__4__BIT_MASK, CYREG_PRT2_BIT_MASK
+.set SCSI_Out_DBx__4__BYP, CYREG_PRT2_BYP
+.set SCSI_Out_DBx__4__CTL, CYREG_PRT2_CTL
+.set SCSI_Out_DBx__4__DM0, CYREG_PRT2_DM0
+.set SCSI_Out_DBx__4__DM1, CYREG_PRT2_DM1
+.set SCSI_Out_DBx__4__DM2, CYREG_PRT2_DM2
+.set SCSI_Out_DBx__4__DR, CYREG_PRT2_DR
+.set SCSI_Out_DBx__4__INP_DIS, CYREG_PRT2_INP_DIS
+.set SCSI_Out_DBx__4__INTTYPE, CYREG_PICU2_INTTYPE5
+.set SCSI_Out_DBx__4__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG
+.set SCSI_Out_DBx__4__LCD_EN, CYREG_PRT2_LCD_EN
+.set SCSI_Out_DBx__4__MASK, 0x20
+.set SCSI_Out_DBx__4__PC, CYREG_PRT2_PC5
+.set SCSI_Out_DBx__4__PORT, 2
+.set SCSI_Out_DBx__4__PRT, CYREG_PRT2_PRT
+.set SCSI_Out_DBx__4__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL
+.set SCSI_Out_DBx__4__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN
+.set SCSI_Out_DBx__4__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0
+.set SCSI_Out_DBx__4__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1
+.set SCSI_Out_DBx__4__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0
+.set SCSI_Out_DBx__4__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1
+.set SCSI_Out_DBx__4__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT
+.set SCSI_Out_DBx__4__PS, CYREG_PRT2_PS
+.set SCSI_Out_DBx__4__SHIFT, 5
+.set SCSI_Out_DBx__4__SLW, CYREG_PRT2_SLW
+.set SCSI_Out_DBx__5__AG, CYREG_PRT2_AG
+.set SCSI_Out_DBx__5__AMUX, CYREG_PRT2_AMUX
+.set SCSI_Out_DBx__5__BIE, CYREG_PRT2_BIE
+.set SCSI_Out_DBx__5__BIT_MASK, CYREG_PRT2_BIT_MASK
+.set SCSI_Out_DBx__5__BYP, CYREG_PRT2_BYP
+.set SCSI_Out_DBx__5__CTL, CYREG_PRT2_CTL
+.set SCSI_Out_DBx__5__DM0, CYREG_PRT2_DM0
+.set SCSI_Out_DBx__5__DM1, CYREG_PRT2_DM1
+.set SCSI_Out_DBx__5__DM2, CYREG_PRT2_DM2
+.set SCSI_Out_DBx__5__DR, CYREG_PRT2_DR
+.set SCSI_Out_DBx__5__INP_DIS, CYREG_PRT2_INP_DIS
+.set SCSI_Out_DBx__5__INTTYPE, CYREG_PICU2_INTTYPE3
+.set SCSI_Out_DBx__5__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG
+.set SCSI_Out_DBx__5__LCD_EN, CYREG_PRT2_LCD_EN
+.set SCSI_Out_DBx__5__MASK, 0x08
+.set SCSI_Out_DBx__5__PC, CYREG_PRT2_PC3
+.set SCSI_Out_DBx__5__PORT, 2
+.set SCSI_Out_DBx__5__PRT, CYREG_PRT2_PRT
+.set SCSI_Out_DBx__5__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL
+.set SCSI_Out_DBx__5__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN
+.set SCSI_Out_DBx__5__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0
+.set SCSI_Out_DBx__5__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1
+.set SCSI_Out_DBx__5__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0
+.set SCSI_Out_DBx__5__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1
+.set SCSI_Out_DBx__5__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT
+.set SCSI_Out_DBx__5__PS, CYREG_PRT2_PS
+.set SCSI_Out_DBx__5__SHIFT, 3
+.set SCSI_Out_DBx__5__SLW, CYREG_PRT2_SLW
+.set SCSI_Out_DBx__6__AG, CYREG_PRT2_AG
+.set SCSI_Out_DBx__6__AMUX, CYREG_PRT2_AMUX
+.set SCSI_Out_DBx__6__BIE, CYREG_PRT2_BIE
+.set SCSI_Out_DBx__6__BIT_MASK, CYREG_PRT2_BIT_MASK
+.set SCSI_Out_DBx__6__BYP, CYREG_PRT2_BYP
+.set SCSI_Out_DBx__6__CTL, CYREG_PRT2_CTL
+.set SCSI_Out_DBx__6__DM0, CYREG_PRT2_DM0
+.set SCSI_Out_DBx__6__DM1, CYREG_PRT2_DM1
+.set SCSI_Out_DBx__6__DM2, CYREG_PRT2_DM2
+.set SCSI_Out_DBx__6__DR, CYREG_PRT2_DR
+.set SCSI_Out_DBx__6__INP_DIS, CYREG_PRT2_INP_DIS
+.set SCSI_Out_DBx__6__INTTYPE, CYREG_PICU2_INTTYPE1
+.set SCSI_Out_DBx__6__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG
+.set SCSI_Out_DBx__6__LCD_EN, CYREG_PRT2_LCD_EN
+.set SCSI_Out_DBx__6__MASK, 0x02
+.set SCSI_Out_DBx__6__PC, CYREG_PRT2_PC1
+.set SCSI_Out_DBx__6__PORT, 2
+.set SCSI_Out_DBx__6__PRT, CYREG_PRT2_PRT
+.set SCSI_Out_DBx__6__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL
+.set SCSI_Out_DBx__6__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN
+.set SCSI_Out_DBx__6__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0
+.set SCSI_Out_DBx__6__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1
+.set SCSI_Out_DBx__6__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0
+.set SCSI_Out_DBx__6__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1
+.set SCSI_Out_DBx__6__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT
+.set SCSI_Out_DBx__6__PS, CYREG_PRT2_PS
+.set SCSI_Out_DBx__6__SHIFT, 1
+.set SCSI_Out_DBx__6__SLW, CYREG_PRT2_SLW
+.set SCSI_Out_DBx__7__AG, CYREG_PRT15_AG
+.set SCSI_Out_DBx__7__AMUX, CYREG_PRT15_AMUX
+.set SCSI_Out_DBx__7__BIE, CYREG_PRT15_BIE
+.set SCSI_Out_DBx__7__BIT_MASK, CYREG_PRT15_BIT_MASK
+.set SCSI_Out_DBx__7__BYP, CYREG_PRT15_BYP
+.set SCSI_Out_DBx__7__CTL, CYREG_PRT15_CTL
+.set SCSI_Out_DBx__7__DM0, CYREG_PRT15_DM0
+.set SCSI_Out_DBx__7__DM1, CYREG_PRT15_DM1
+.set SCSI_Out_DBx__7__DM2, CYREG_PRT15_DM2
+.set SCSI_Out_DBx__7__DR, CYREG_PRT15_DR
+.set SCSI_Out_DBx__7__INP_DIS, CYREG_PRT15_INP_DIS
+.set SCSI_Out_DBx__7__INTTYPE, CYREG_PICU15_INTTYPE5
+.set SCSI_Out_DBx__7__LCD_COM_SEG, CYREG_PRT15_LCD_COM_SEG
+.set SCSI_Out_DBx__7__LCD_EN, CYREG_PRT15_LCD_EN
+.set SCSI_Out_DBx__7__MASK, 0x20
+.set SCSI_Out_DBx__7__PC, CYREG_IO_PC_PRT15_PC5
+.set SCSI_Out_DBx__7__PORT, 15
+.set SCSI_Out_DBx__7__PRT, CYREG_PRT15_PRT
+.set SCSI_Out_DBx__7__PRTDSI__CAPS_SEL, CYREG_PRT15_CAPS_SEL
+.set SCSI_Out_DBx__7__PRTDSI__DBL_SYNC_IN, CYREG_PRT15_DBL_SYNC_IN
+.set SCSI_Out_DBx__7__PRTDSI__OE_SEL0, CYREG_PRT15_OE_SEL0
+.set SCSI_Out_DBx__7__PRTDSI__OE_SEL1, CYREG_PRT15_OE_SEL1
+.set SCSI_Out_DBx__7__PRTDSI__OUT_SEL0, CYREG_PRT15_OUT_SEL0
+.set SCSI_Out_DBx__7__PRTDSI__OUT_SEL1, CYREG_PRT15_OUT_SEL1
+.set SCSI_Out_DBx__7__PRTDSI__SYNC_OUT, CYREG_PRT15_SYNC_OUT
+.set SCSI_Out_DBx__7__PS, CYREG_PRT15_PS
+.set SCSI_Out_DBx__7__SHIFT, 5
+.set SCSI_Out_DBx__7__SLW, CYREG_PRT15_SLW
+.set SCSI_Out_DBx__DB0__AG, CYREG_PRT6_AG
+.set SCSI_Out_DBx__DB0__AMUX, CYREG_PRT6_AMUX
+.set SCSI_Out_DBx__DB0__BIE, CYREG_PRT6_BIE
+.set SCSI_Out_DBx__DB0__BIT_MASK, CYREG_PRT6_BIT_MASK
+.set SCSI_Out_DBx__DB0__BYP, CYREG_PRT6_BYP
+.set SCSI_Out_DBx__DB0__CTL, CYREG_PRT6_CTL
+.set SCSI_Out_DBx__DB0__DM0, CYREG_PRT6_DM0
+.set SCSI_Out_DBx__DB0__DM1, CYREG_PRT6_DM1
+.set SCSI_Out_DBx__DB0__DM2, CYREG_PRT6_DM2
+.set SCSI_Out_DBx__DB0__DR, CYREG_PRT6_DR
+.set SCSI_Out_DBx__DB0__INP_DIS, CYREG_PRT6_INP_DIS
+.set SCSI_Out_DBx__DB0__INTTYPE, CYREG_PICU6_INTTYPE7
+.set SCSI_Out_DBx__DB0__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
+.set SCSI_Out_DBx__DB0__LCD_EN, CYREG_PRT6_LCD_EN
+.set SCSI_Out_DBx__DB0__MASK, 0x80
+.set SCSI_Out_DBx__DB0__PC, CYREG_PRT6_PC7
+.set SCSI_Out_DBx__DB0__PORT, 6
+.set SCSI_Out_DBx__DB0__PRT, CYREG_PRT6_PRT
+.set SCSI_Out_DBx__DB0__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL
+.set SCSI_Out_DBx__DB0__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN
+.set SCSI_Out_DBx__DB0__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0
+.set SCSI_Out_DBx__DB0__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1
+.set SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0
+.set SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1
+.set SCSI_Out_DBx__DB0__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT
+.set SCSI_Out_DBx__DB0__PS, CYREG_PRT6_PS
+.set SCSI_Out_DBx__DB0__SHIFT, 7
+.set SCSI_Out_DBx__DB0__SLW, CYREG_PRT6_SLW
+.set SCSI_Out_DBx__DB1__AG, CYREG_PRT6_AG
+.set SCSI_Out_DBx__DB1__AMUX, CYREG_PRT6_AMUX
+.set SCSI_Out_DBx__DB1__BIE, CYREG_PRT6_BIE
+.set SCSI_Out_DBx__DB1__BIT_MASK, CYREG_PRT6_BIT_MASK
+.set SCSI_Out_DBx__DB1__BYP, CYREG_PRT6_BYP
+.set SCSI_Out_DBx__DB1__CTL, CYREG_PRT6_CTL
+.set SCSI_Out_DBx__DB1__DM0, CYREG_PRT6_DM0
+.set SCSI_Out_DBx__DB1__DM1, CYREG_PRT6_DM1
+.set SCSI_Out_DBx__DB1__DM2, CYREG_PRT6_DM2
+.set SCSI_Out_DBx__DB1__DR, CYREG_PRT6_DR
+.set SCSI_Out_DBx__DB1__INP_DIS, CYREG_PRT6_INP_DIS
+.set SCSI_Out_DBx__DB1__INTTYPE, CYREG_PICU6_INTTYPE5
+.set SCSI_Out_DBx__DB1__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
+.set SCSI_Out_DBx__DB1__LCD_EN, CYREG_PRT6_LCD_EN
+.set SCSI_Out_DBx__DB1__MASK, 0x20
+.set SCSI_Out_DBx__DB1__PC, CYREG_PRT6_PC5
+.set SCSI_Out_DBx__DB1__PORT, 6
+.set SCSI_Out_DBx__DB1__PRT, CYREG_PRT6_PRT
+.set SCSI_Out_DBx__DB1__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL
+.set SCSI_Out_DBx__DB1__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN
+.set SCSI_Out_DBx__DB1__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0
+.set SCSI_Out_DBx__DB1__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1
+.set SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0
+.set SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1
+.set SCSI_Out_DBx__DB1__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT
+.set SCSI_Out_DBx__DB1__PS, CYREG_PRT6_PS
+.set SCSI_Out_DBx__DB1__SHIFT, 5
+.set SCSI_Out_DBx__DB1__SLW, CYREG_PRT6_SLW
+.set SCSI_Out_DBx__DB2__AG, CYREG_PRT12_AG
+.set SCSI_Out_DBx__DB2__BIE, CYREG_PRT12_BIE
+.set SCSI_Out_DBx__DB2__BIT_MASK, CYREG_PRT12_BIT_MASK
+.set SCSI_Out_DBx__DB2__BYP, CYREG_PRT12_BYP
+.set SCSI_Out_DBx__DB2__DM0, CYREG_PRT12_DM0
+.set SCSI_Out_DBx__DB2__DM1, CYREG_PRT12_DM1
+.set SCSI_Out_DBx__DB2__DM2, CYREG_PRT12_DM2
+.set SCSI_Out_DBx__DB2__DR, CYREG_PRT12_DR
+.set SCSI_Out_DBx__DB2__INP_DIS, CYREG_PRT12_INP_DIS
+.set SCSI_Out_DBx__DB2__INTTYPE, CYREG_PICU12_INTTYPE5
+.set SCSI_Out_DBx__DB2__MASK, 0x20
+.set SCSI_Out_DBx__DB2__PC, CYREG_PRT12_PC5
+.set SCSI_Out_DBx__DB2__PORT, 12
+.set SCSI_Out_DBx__DB2__PRT, CYREG_PRT12_PRT
+.set SCSI_Out_DBx__DB2__PRTDSI__DBL_SYNC_IN, CYREG_PRT12_DBL_SYNC_IN
+.set SCSI_Out_DBx__DB2__PRTDSI__OE_SEL0, CYREG_PRT12_OE_SEL0
+.set SCSI_Out_DBx__DB2__PRTDSI__OE_SEL1, CYREG_PRT12_OE_SEL1
+.set SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL0, CYREG_PRT12_OUT_SEL0
+.set SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL1, CYREG_PRT12_OUT_SEL1
+.set SCSI_Out_DBx__DB2__PRTDSI__SYNC_OUT, CYREG_PRT12_SYNC_OUT
+.set SCSI_Out_DBx__DB2__PS, CYREG_PRT12_PS
+.set SCSI_Out_DBx__DB2__SHIFT, 5
+.set SCSI_Out_DBx__DB2__SIO_CFG, CYREG_PRT12_SIO_CFG
+.set SCSI_Out_DBx__DB2__SIO_DIFF, CYREG_PRT12_SIO_DIFF
+.set SCSI_Out_DBx__DB2__SIO_HYST_EN, CYREG_PRT12_SIO_HYST_EN
+.set SCSI_Out_DBx__DB2__SIO_REG_HIFREQ, CYREG_PRT12_SIO_REG_HIFREQ
+.set SCSI_Out_DBx__DB2__SLW, CYREG_PRT12_SLW
+.set SCSI_Out_DBx__DB3__AG, CYREG_PRT2_AG
+.set SCSI_Out_DBx__DB3__AMUX, CYREG_PRT2_AMUX
+.set SCSI_Out_DBx__DB3__BIE, CYREG_PRT2_BIE
+.set SCSI_Out_DBx__DB3__BIT_MASK, CYREG_PRT2_BIT_MASK
+.set SCSI_Out_DBx__DB3__BYP, CYREG_PRT2_BYP
+.set SCSI_Out_DBx__DB3__CTL, CYREG_PRT2_CTL
+.set SCSI_Out_DBx__DB3__DM0, CYREG_PRT2_DM0
+.set SCSI_Out_DBx__DB3__DM1, CYREG_PRT2_DM1
+.set SCSI_Out_DBx__DB3__DM2, CYREG_PRT2_DM2
+.set SCSI_Out_DBx__DB3__DR, CYREG_PRT2_DR
+.set SCSI_Out_DBx__DB3__INP_DIS, CYREG_PRT2_INP_DIS
+.set SCSI_Out_DBx__DB3__INTTYPE, CYREG_PICU2_INTTYPE7
+.set SCSI_Out_DBx__DB3__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG
+.set SCSI_Out_DBx__DB3__LCD_EN, CYREG_PRT2_LCD_EN
+.set SCSI_Out_DBx__DB3__MASK, 0x80
+.set SCSI_Out_DBx__DB3__PC, CYREG_PRT2_PC7
+.set SCSI_Out_DBx__DB3__PORT, 2
+.set SCSI_Out_DBx__DB3__PRT, CYREG_PRT2_PRT
+.set SCSI_Out_DBx__DB3__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL
+.set SCSI_Out_DBx__DB3__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN
+.set SCSI_Out_DBx__DB3__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0
+.set SCSI_Out_DBx__DB3__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1
+.set SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0
+.set SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1
+.set SCSI_Out_DBx__DB3__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT
+.set SCSI_Out_DBx__DB3__PS, CYREG_PRT2_PS
+.set SCSI_Out_DBx__DB3__SHIFT, 7
+.set SCSI_Out_DBx__DB3__SLW, CYREG_PRT2_SLW
+.set SCSI_Out_DBx__DB4__AG, CYREG_PRT2_AG
+.set SCSI_Out_DBx__DB4__AMUX, CYREG_PRT2_AMUX
+.set SCSI_Out_DBx__DB4__BIE, CYREG_PRT2_BIE
+.set SCSI_Out_DBx__DB4__BIT_MASK, CYREG_PRT2_BIT_MASK
+.set SCSI_Out_DBx__DB4__BYP, CYREG_PRT2_BYP
+.set SCSI_Out_DBx__DB4__CTL, CYREG_PRT2_CTL
+.set SCSI_Out_DBx__DB4__DM0, CYREG_PRT2_DM0
+.set SCSI_Out_DBx__DB4__DM1, CYREG_PRT2_DM1
+.set SCSI_Out_DBx__DB4__DM2, CYREG_PRT2_DM2
+.set SCSI_Out_DBx__DB4__DR, CYREG_PRT2_DR
+.set SCSI_Out_DBx__DB4__INP_DIS, CYREG_PRT2_INP_DIS
+.set SCSI_Out_DBx__DB4__INTTYPE, CYREG_PICU2_INTTYPE5
+.set SCSI_Out_DBx__DB4__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG
+.set SCSI_Out_DBx__DB4__LCD_EN, CYREG_PRT2_LCD_EN
+.set SCSI_Out_DBx__DB4__MASK, 0x20
+.set SCSI_Out_DBx__DB4__PC, CYREG_PRT2_PC5
+.set SCSI_Out_DBx__DB4__PORT, 2
+.set SCSI_Out_DBx__DB4__PRT, CYREG_PRT2_PRT
+.set SCSI_Out_DBx__DB4__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL
+.set SCSI_Out_DBx__DB4__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN
+.set SCSI_Out_DBx__DB4__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0
+.set SCSI_Out_DBx__DB4__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1
+.set SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0
+.set SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1
+.set SCSI_Out_DBx__DB4__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT
+.set SCSI_Out_DBx__DB4__PS, CYREG_PRT2_PS
+.set SCSI_Out_DBx__DB4__SHIFT, 5
+.set SCSI_Out_DBx__DB4__SLW, CYREG_PRT2_SLW
+.set SCSI_Out_DBx__DB5__AG, CYREG_PRT2_AG
+.set SCSI_Out_DBx__DB5__AMUX, CYREG_PRT2_AMUX
+.set SCSI_Out_DBx__DB5__BIE, CYREG_PRT2_BIE
+.set SCSI_Out_DBx__DB5__BIT_MASK, CYREG_PRT2_BIT_MASK
+.set SCSI_Out_DBx__DB5__BYP, CYREG_PRT2_BYP
+.set SCSI_Out_DBx__DB5__CTL, CYREG_PRT2_CTL
+.set SCSI_Out_DBx__DB5__DM0, CYREG_PRT2_DM0
+.set SCSI_Out_DBx__DB5__DM1, CYREG_PRT2_DM1
+.set SCSI_Out_DBx__DB5__DM2, CYREG_PRT2_DM2
+.set SCSI_Out_DBx__DB5__DR, CYREG_PRT2_DR
+.set SCSI_Out_DBx__DB5__INP_DIS, CYREG_PRT2_INP_DIS
+.set SCSI_Out_DBx__DB5__INTTYPE, CYREG_PICU2_INTTYPE3
+.set SCSI_Out_DBx__DB5__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG
+.set SCSI_Out_DBx__DB5__LCD_EN, CYREG_PRT2_LCD_EN
+.set SCSI_Out_DBx__DB5__MASK, 0x08
+.set SCSI_Out_DBx__DB5__PC, CYREG_PRT2_PC3
+.set SCSI_Out_DBx__DB5__PORT, 2
+.set SCSI_Out_DBx__DB5__PRT, CYREG_PRT2_PRT
+.set SCSI_Out_DBx__DB5__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL
+.set SCSI_Out_DBx__DB5__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN
+.set SCSI_Out_DBx__DB5__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0
+.set SCSI_Out_DBx__DB5__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1
+.set SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0
+.set SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1
+.set SCSI_Out_DBx__DB5__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT
+.set SCSI_Out_DBx__DB5__PS, CYREG_PRT2_PS
+.set SCSI_Out_DBx__DB5__SHIFT, 3
+.set SCSI_Out_DBx__DB5__SLW, CYREG_PRT2_SLW
+.set SCSI_Out_DBx__DB6__AG, CYREG_PRT2_AG
+.set SCSI_Out_DBx__DB6__AMUX, CYREG_PRT2_AMUX
+.set SCSI_Out_DBx__DB6__BIE, CYREG_PRT2_BIE
+.set SCSI_Out_DBx__DB6__BIT_MASK, CYREG_PRT2_BIT_MASK
+.set SCSI_Out_DBx__DB6__BYP, CYREG_PRT2_BYP
+.set SCSI_Out_DBx__DB6__CTL, CYREG_PRT2_CTL
+.set SCSI_Out_DBx__DB6__DM0, CYREG_PRT2_DM0
+.set SCSI_Out_DBx__DB6__DM1, CYREG_PRT2_DM1
+.set SCSI_Out_DBx__DB6__DM2, CYREG_PRT2_DM2
+.set SCSI_Out_DBx__DB6__DR, CYREG_PRT2_DR
+.set SCSI_Out_DBx__DB6__INP_DIS, CYREG_PRT2_INP_DIS
+.set SCSI_Out_DBx__DB6__INTTYPE, CYREG_PICU2_INTTYPE1
+.set SCSI_Out_DBx__DB6__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG
+.set SCSI_Out_DBx__DB6__LCD_EN, CYREG_PRT2_LCD_EN
+.set SCSI_Out_DBx__DB6__MASK, 0x02
+.set SCSI_Out_DBx__DB6__PC, CYREG_PRT2_PC1
+.set SCSI_Out_DBx__DB6__PORT, 2
+.set SCSI_Out_DBx__DB6__PRT, CYREG_PRT2_PRT
+.set SCSI_Out_DBx__DB6__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL
+.set SCSI_Out_DBx__DB6__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN
+.set SCSI_Out_DBx__DB6__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0
+.set SCSI_Out_DBx__DB6__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1
+.set SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0
+.set SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1
+.set SCSI_Out_DBx__DB6__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT
+.set SCSI_Out_DBx__DB6__PS, CYREG_PRT2_PS
+.set SCSI_Out_DBx__DB6__SHIFT, 1
+.set SCSI_Out_DBx__DB6__SLW, CYREG_PRT2_SLW
+.set SCSI_Out_DBx__DB7__AG, CYREG_PRT15_AG
+.set SCSI_Out_DBx__DB7__AMUX, CYREG_PRT15_AMUX
+.set SCSI_Out_DBx__DB7__BIE, CYREG_PRT15_BIE
+.set SCSI_Out_DBx__DB7__BIT_MASK, CYREG_PRT15_BIT_MASK
+.set SCSI_Out_DBx__DB7__BYP, CYREG_PRT15_BYP
+.set SCSI_Out_DBx__DB7__CTL, CYREG_PRT15_CTL
+.set SCSI_Out_DBx__DB7__DM0, CYREG_PRT15_DM0
+.set SCSI_Out_DBx__DB7__DM1, CYREG_PRT15_DM1
+.set SCSI_Out_DBx__DB7__DM2, CYREG_PRT15_DM2
+.set SCSI_Out_DBx__DB7__DR, CYREG_PRT15_DR
+.set SCSI_Out_DBx__DB7__INP_DIS, CYREG_PRT15_INP_DIS
+.set SCSI_Out_DBx__DB7__INTTYPE, CYREG_PICU15_INTTYPE5
+.set SCSI_Out_DBx__DB7__LCD_COM_SEG, CYREG_PRT15_LCD_COM_SEG
+.set SCSI_Out_DBx__DB7__LCD_EN, CYREG_PRT15_LCD_EN
+.set SCSI_Out_DBx__DB7__MASK, 0x20
+.set SCSI_Out_DBx__DB7__PC, CYREG_IO_PC_PRT15_PC5
+.set SCSI_Out_DBx__DB7__PORT, 15
+.set SCSI_Out_DBx__DB7__PRT, CYREG_PRT15_PRT
+.set SCSI_Out_DBx__DB7__PRTDSI__CAPS_SEL, CYREG_PRT15_CAPS_SEL
+.set SCSI_Out_DBx__DB7__PRTDSI__DBL_SYNC_IN, CYREG_PRT15_DBL_SYNC_IN
+.set SCSI_Out_DBx__DB7__PRTDSI__OE_SEL0, CYREG_PRT15_OE_SEL0
+.set SCSI_Out_DBx__DB7__PRTDSI__OE_SEL1, CYREG_PRT15_OE_SEL1
+.set SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL0, CYREG_PRT15_OUT_SEL0
+.set SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL1, CYREG_PRT15_OUT_SEL1
+.set SCSI_Out_DBx__DB7__PRTDSI__SYNC_OUT, CYREG_PRT15_SYNC_OUT
+.set SCSI_Out_DBx__DB7__PS, CYREG_PRT15_PS
+.set SCSI_Out_DBx__DB7__SHIFT, 5
+.set SCSI_Out_DBx__DB7__SLW, CYREG_PRT15_SLW
+
+/* SCSI_Parity_Error */
+.set SCSI_Parity_Error_sts_sts_reg__0__MASK, 0x01
+.set SCSI_Parity_Error_sts_sts_reg__0__POS, 0
+.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB02_03_ACTL
+.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB02_03_ST
+.set SCSI_Parity_Error_sts_sts_reg__MASK, 0x01
+.set SCSI_Parity_Error_sts_sts_reg__MASK_REG, CYREG_B0_UDB02_MSK
+.set SCSI_Parity_Error_sts_sts_reg__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB02_MSK_ACTL
+.set SCSI_Parity_Error_sts_sts_reg__PER_ST_AUX_CTL_REG, CYREG_B0_UDB02_MSK_ACTL
+.set SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB02_ACTL
+.set SCSI_Parity_Error_sts_sts_reg__STATUS_CNT_REG, CYREG_B0_UDB02_ST_CTL
+.set SCSI_Parity_Error_sts_sts_reg__STATUS_CONTROL_REG, CYREG_B0_UDB02_ST_CTL
+.set SCSI_Parity_Error_sts_sts_reg__STATUS_REG, CYREG_B0_UDB02_ST
+
+/* SCSI_RST_ISR */
+.set SCSI_RST_ISR__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
+.set SCSI_RST_ISR__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
+.set SCSI_RST_ISR__INTC_MASK, 0x02
+.set SCSI_RST_ISR__INTC_NUMBER, 1
+.set SCSI_RST_ISR__INTC_PRIOR_NUM, 7
+.set SCSI_RST_ISR__INTC_PRIOR_REG, CYREG_NVIC_PRI_1
+.set SCSI_RST_ISR__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
+.set SCSI_RST_ISR__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
+
+/* SCSI_RX_DMA */
+.set SCSI_RX_DMA__DRQ_CTL, CYREG_IDMUX_DRQ_CTL0
+.set SCSI_RX_DMA__DRQ_NUMBER, 0
+.set SCSI_RX_DMA__NUMBEROF_TDS, 0
+.set SCSI_RX_DMA__PRIORITY, 2
+.set SCSI_RX_DMA__TERMIN_EN, 0
+.set SCSI_RX_DMA__TERMIN_SEL, 0
+.set SCSI_RX_DMA__TERMOUT0_EN, 1
+.set SCSI_RX_DMA__TERMOUT0_SEL, 0
+.set SCSI_RX_DMA__TERMOUT1_EN, 0
+.set SCSI_RX_DMA__TERMOUT1_SEL, 0
+.set SCSI_RX_DMA_COMPLETE__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
+.set SCSI_RX_DMA_COMPLETE__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
+.set SCSI_RX_DMA_COMPLETE__INTC_MASK, 0x04
+.set SCSI_RX_DMA_COMPLETE__INTC_NUMBER, 2
+.set SCSI_RX_DMA_COMPLETE__INTC_PRIOR_NUM, 7
+.set SCSI_RX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_2
+.set SCSI_RX_DMA_COMPLETE__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
+.set SCSI_RX_DMA_COMPLETE__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
+
+/* SCSI_SEL_ISR */
+.set SCSI_SEL_ISR__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
+.set SCSI_SEL_ISR__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
+.set SCSI_SEL_ISR__INTC_MASK, 0x08
+.set SCSI_SEL_ISR__INTC_NUMBER, 3
+.set SCSI_SEL_ISR__INTC_PRIOR_NUM, 7
+.set SCSI_SEL_ISR__INTC_PRIOR_REG, CYREG_NVIC_PRI_3
+.set SCSI_SEL_ISR__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
+.set SCSI_SEL_ISR__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
+
+/* SCSI_TX_DMA */
+.set SCSI_TX_DMA__DRQ_CTL, CYREG_IDMUX_DRQ_CTL0
+.set SCSI_TX_DMA__DRQ_NUMBER, 1
+.set SCSI_TX_DMA__NUMBEROF_TDS, 0
+.set SCSI_TX_DMA__PRIORITY, 2
+.set SCSI_TX_DMA__TERMIN_EN, 0
+.set SCSI_TX_DMA__TERMIN_SEL, 0
+.set SCSI_TX_DMA__TERMOUT0_EN, 1
+.set SCSI_TX_DMA__TERMOUT0_SEL, 1
+.set SCSI_TX_DMA__TERMOUT1_EN, 0
+.set SCSI_TX_DMA__TERMOUT1_SEL, 0
+.set SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
+.set SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
+.set SCSI_TX_DMA_COMPLETE__INTC_MASK, 0x10
+.set SCSI_TX_DMA_COMPLETE__INTC_NUMBER, 4
+.set SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM, 7
+.set SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_4
+.set SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
+.set SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
+
+/* SDCard_BSPIM */
+.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB04_05_ACTL
+.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB04_05_CTL
+.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB04_05_CTL
+.set SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB04_05_CTL
+.set SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB04_05_CTL
+.set SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B1_UDB04_05_MSK
+.set SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB04_05_MSK
+.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB04_05_MSK
+.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB04_05_MSK
+.set SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B1_UDB04_ACTL
+.set SDCard_BSPIM_BitCounter__CONTROL_REG, CYREG_B1_UDB04_CTL
+.set SDCard_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B1_UDB04_ST_CTL
+.set SDCard_BSPIM_BitCounter__COUNT_REG, CYREG_B1_UDB04_CTL
+.set SDCard_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B1_UDB04_ST_CTL
+.set SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL
+.set SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL
+.set SDCard_BSPIM_BitCounter__PERIOD_REG, CYREG_B1_UDB04_MSK
+.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB04_05_ACTL
+.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B1_UDB04_05_ST
+.set SDCard_BSPIM_BitCounter_ST__MASK_REG, CYREG_B1_UDB04_MSK
+.set SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL
+.set SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL
+.set SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B1_UDB04_ACTL
+.set SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B1_UDB04_ST_CTL
+.set SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B1_UDB04_ST_CTL
+.set SDCard_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B1_UDB04_ST
+.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB07_08_ACTL
+.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB07_08_ST
+.set SDCard_BSPIM_RxStsReg__4__MASK, 0x10
+.set SDCard_BSPIM_RxStsReg__4__POS, 4
+.set SDCard_BSPIM_RxStsReg__5__MASK, 0x20
+.set SDCard_BSPIM_RxStsReg__5__POS, 5
+.set SDCard_BSPIM_RxStsReg__6__MASK, 0x40
+.set SDCard_BSPIM_RxStsReg__6__POS, 6
+.set SDCard_BSPIM_RxStsReg__MASK, 0x70
+.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B0_UDB07_MSK
+.set SDCard_BSPIM_RxStsReg__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB07_MSK_ACTL
+.set SDCard_BSPIM_RxStsReg__PER_ST_AUX_CTL_REG, CYREG_B0_UDB07_MSK_ACTL
+.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB07_ACTL
+.set SDCard_BSPIM_RxStsReg__STATUS_CNT_REG, CYREG_B0_UDB07_ST_CTL
+.set SDCard_BSPIM_RxStsReg__STATUS_CONTROL_REG, CYREG_B0_UDB07_ST_CTL
+.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B0_UDB07_ST
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG, CYREG_B1_UDB04_05_A0
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG, CYREG_B1_UDB04_05_A1
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG, CYREG_B1_UDB04_05_D0
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG, CYREG_B1_UDB04_05_D1
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG, CYREG_B1_UDB04_05_ACTL
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG, CYREG_B1_UDB04_05_F0
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG, CYREG_B1_UDB04_05_F1
+.set SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG, CYREG_B1_UDB04_A0_A1
+.set SDCard_BSPIM_sR8_Dp_u0__A0_REG, CYREG_B1_UDB04_A0
+.set SDCard_BSPIM_sR8_Dp_u0__A1_REG, CYREG_B1_UDB04_A1
+.set SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG, CYREG_B1_UDB04_D0_D1
+.set SDCard_BSPIM_sR8_Dp_u0__D0_REG, CYREG_B1_UDB04_D0
+.set SDCard_BSPIM_sR8_Dp_u0__D1_REG, CYREG_B1_UDB04_D1
+.set SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG, CYREG_B1_UDB04_ACTL
+.set SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG, CYREG_B1_UDB04_F0_F1
+.set SDCard_BSPIM_sR8_Dp_u0__F0_REG, CYREG_B1_UDB04_F0
+.set SDCard_BSPIM_sR8_Dp_u0__F1_REG, CYREG_B1_UDB04_F1
+.set SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL
+.set SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL
+.set SDCard_BSPIM_TxStsReg__0__MASK, 0x01
+.set SDCard_BSPIM_TxStsReg__0__POS, 0
+.set SDCard_BSPIM_TxStsReg__1__MASK, 0x02
+.set SDCard_BSPIM_TxStsReg__1__POS, 1
+.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB07_08_ACTL
+.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB07_08_ST
+.set SDCard_BSPIM_TxStsReg__2__MASK, 0x04
+.set SDCard_BSPIM_TxStsReg__2__POS, 2
+.set SDCard_BSPIM_TxStsReg__3__MASK, 0x08
+.set SDCard_BSPIM_TxStsReg__3__POS, 3
+.set SDCard_BSPIM_TxStsReg__4__MASK, 0x10
+.set SDCard_BSPIM_TxStsReg__4__POS, 4
+.set SDCard_BSPIM_TxStsReg__MASK, 0x1F
+.set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B1_UDB07_MSK
+.set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB07_ACTL
+.set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B1_UDB07_ST
+
+/* SD_CS */
+.set SD_CS__0__INTTYPE, CYREG_PICU3_INTTYPE5
+.set SD_CS__0__MASK, 0x20
+.set SD_CS__0__PC, CYREG_PRT3_PC5
+.set SD_CS__0__PORT, 3
+.set SD_CS__0__SHIFT, 5
+.set SD_CS__AG, CYREG_PRT3_AG
+.set SD_CS__AMUX, CYREG_PRT3_AMUX
+.set SD_CS__BIE, CYREG_PRT3_BIE
+.set SD_CS__BIT_MASK, CYREG_PRT3_BIT_MASK
+.set SD_CS__BYP, CYREG_PRT3_BYP
+.set SD_CS__CTL, CYREG_PRT3_CTL
+.set SD_CS__DM0, CYREG_PRT3_DM0
+.set SD_CS__DM1, CYREG_PRT3_DM1
+.set SD_CS__DM2, CYREG_PRT3_DM2
+.set SD_CS__DR, CYREG_PRT3_DR
+.set SD_CS__INP_DIS, CYREG_PRT3_INP_DIS
+.set SD_CS__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU3_BASE
+.set SD_CS__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG
+.set SD_CS__LCD_EN, CYREG_PRT3_LCD_EN
+.set SD_CS__MASK, 0x20
+.set SD_CS__PORT, 3
+.set SD_CS__PRT, CYREG_PRT3_PRT
+.set SD_CS__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL
+.set SD_CS__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN
+.set SD_CS__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0
+.set SD_CS__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1
+.set SD_CS__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0
+.set SD_CS__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1
+.set SD_CS__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT
+.set SD_CS__PS, CYREG_PRT3_PS
+.set SD_CS__SHIFT, 5
+.set SD_CS__SLW, CYREG_PRT3_SLW
+
+/* SD_Data_Clk */
+.set SD_Data_Clk__CFG0, CYREG_CLKDIST_DCFG0_CFG0
+.set SD_Data_Clk__CFG1, CYREG_CLKDIST_DCFG0_CFG1
+.set SD_Data_Clk__CFG2, CYREG_CLKDIST_DCFG0_CFG2
+.set SD_Data_Clk__CFG2_SRC_SEL_MASK, 0x07
+.set SD_Data_Clk__INDEX, 0x00
+.set SD_Data_Clk__PM_ACT_CFG, CYREG_PM_ACT_CFG2
+.set SD_Data_Clk__PM_ACT_MSK, 0x01
+.set SD_Data_Clk__PM_STBY_CFG, CYREG_PM_STBY_CFG2
+.set SD_Data_Clk__PM_STBY_MSK, 0x01
+
+/* SD_MISO */
+.set SD_MISO__0__INTTYPE, CYREG_PICU3_INTTYPE2
+.set SD_MISO__0__MASK, 0x04
+.set SD_MISO__0__PC, CYREG_PRT3_PC2
+.set SD_MISO__0__PORT, 3
+.set SD_MISO__0__SHIFT, 2
+.set SD_MISO__AG, CYREG_PRT3_AG
+.set SD_MISO__AMUX, CYREG_PRT3_AMUX
+.set SD_MISO__BIE, CYREG_PRT3_BIE
+.set SD_MISO__BIT_MASK, CYREG_PRT3_BIT_MASK
+.set SD_MISO__BYP, CYREG_PRT3_BYP
+.set SD_MISO__CTL, CYREG_PRT3_CTL
+.set SD_MISO__DM0, CYREG_PRT3_DM0
+.set SD_MISO__DM1, CYREG_PRT3_DM1
+.set SD_MISO__DM2, CYREG_PRT3_DM2
+.set SD_MISO__DR, CYREG_PRT3_DR
+.set SD_MISO__INP_DIS, CYREG_PRT3_INP_DIS
+.set SD_MISO__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU3_BASE
+.set SD_MISO__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG
+.set SD_MISO__LCD_EN, CYREG_PRT3_LCD_EN
+.set SD_MISO__MASK, 0x04
+.set SD_MISO__PORT, 3
+.set SD_MISO__PRT, CYREG_PRT3_PRT
+.set SD_MISO__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL
+.set SD_MISO__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN
+.set SD_MISO__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0
+.set SD_MISO__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1
+.set SD_MISO__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0
+.set SD_MISO__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1
+.set SD_MISO__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT
+.set SD_MISO__PS, CYREG_PRT3_PS
+.set SD_MISO__SHIFT, 2
+.set SD_MISO__SLW, CYREG_PRT3_SLW
+
+/* SD_MOSI */
+.set SD_MOSI__0__INTTYPE, CYREG_PICU3_INTTYPE4
+.set SD_MOSI__0__MASK, 0x10
+.set SD_MOSI__0__PC, CYREG_PRT3_PC4
+.set SD_MOSI__0__PORT, 3
+.set SD_MOSI__0__SHIFT, 4
+.set SD_MOSI__AG, CYREG_PRT3_AG
+.set SD_MOSI__AMUX, CYREG_PRT3_AMUX
+.set SD_MOSI__BIE, CYREG_PRT3_BIE
+.set SD_MOSI__BIT_MASK, CYREG_PRT3_BIT_MASK
+.set SD_MOSI__BYP, CYREG_PRT3_BYP
+.set SD_MOSI__CTL, CYREG_PRT3_CTL
+.set SD_MOSI__DM0, CYREG_PRT3_DM0
+.set SD_MOSI__DM1, CYREG_PRT3_DM1
+.set SD_MOSI__DM2, CYREG_PRT3_DM2
+.set SD_MOSI__DR, CYREG_PRT3_DR
+.set SD_MOSI__INP_DIS, CYREG_PRT3_INP_DIS
+.set SD_MOSI__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU3_BASE
+.set SD_MOSI__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG
+.set SD_MOSI__LCD_EN, CYREG_PRT3_LCD_EN
+.set SD_MOSI__MASK, 0x10
+.set SD_MOSI__PORT, 3
+.set SD_MOSI__PRT, CYREG_PRT3_PRT
+.set SD_MOSI__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL
+.set SD_MOSI__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN
+.set SD_MOSI__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0
+.set SD_MOSI__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1
+.set SD_MOSI__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0
+.set SD_MOSI__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1
+.set SD_MOSI__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT
+.set SD_MOSI__PS, CYREG_PRT3_PS
+.set SD_MOSI__SHIFT, 4
+.set SD_MOSI__SLW, CYREG_PRT3_SLW
+
+/* SD_RX_DMA */
+.set SD_RX_DMA__DRQ_CTL, CYREG_IDMUX_DRQ_CTL0
+.set SD_RX_DMA__DRQ_NUMBER, 2
+.set SD_RX_DMA__NUMBEROF_TDS, 0
+.set SD_RX_DMA__PRIORITY, 0
+.set SD_RX_DMA__TERMIN_EN, 0
+.set SD_RX_DMA__TERMIN_SEL, 0
+.set SD_RX_DMA__TERMOUT0_EN, 1
+.set SD_RX_DMA__TERMOUT0_SEL, 2
+.set SD_RX_DMA__TERMOUT1_EN, 0
+.set SD_RX_DMA__TERMOUT1_SEL, 0
+.set SD_RX_DMA_COMPLETE__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
+.set SD_RX_DMA_COMPLETE__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
+.set SD_RX_DMA_COMPLETE__INTC_MASK, 0x20
+.set SD_RX_DMA_COMPLETE__INTC_NUMBER, 5
+.set SD_RX_DMA_COMPLETE__INTC_PRIOR_NUM, 7
+.set SD_RX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_5
+.set SD_RX_DMA_COMPLETE__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
+.set SD_RX_DMA_COMPLETE__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
+
+/* SD_SCK */
+.set SD_SCK__0__INTTYPE, CYREG_PICU3_INTTYPE3
+.set SD_SCK__0__MASK, 0x08
+.set SD_SCK__0__PC, CYREG_PRT3_PC3
+.set SD_SCK__0__PORT, 3
+.set SD_SCK__0__SHIFT, 3
+.set SD_SCK__AG, CYREG_PRT3_AG
+.set SD_SCK__AMUX, CYREG_PRT3_AMUX
+.set SD_SCK__BIE, CYREG_PRT3_BIE
+.set SD_SCK__BIT_MASK, CYREG_PRT3_BIT_MASK
+.set SD_SCK__BYP, CYREG_PRT3_BYP
+.set SD_SCK__CTL, CYREG_PRT3_CTL
+.set SD_SCK__DM0, CYREG_PRT3_DM0
+.set SD_SCK__DM1, CYREG_PRT3_DM1
+.set SD_SCK__DM2, CYREG_PRT3_DM2
+.set SD_SCK__DR, CYREG_PRT3_DR
+.set SD_SCK__INP_DIS, CYREG_PRT3_INP_DIS
+.set SD_SCK__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU3_BASE
+.set SD_SCK__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG
+.set SD_SCK__LCD_EN, CYREG_PRT3_LCD_EN
+.set SD_SCK__MASK, 0x08
+.set SD_SCK__PORT, 3
+.set SD_SCK__PRT, CYREG_PRT3_PRT
+.set SD_SCK__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL
+.set SD_SCK__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN
+.set SD_SCK__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0
+.set SD_SCK__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1
+.set SD_SCK__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0
+.set SD_SCK__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1
+.set SD_SCK__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT
+.set SD_SCK__PS, CYREG_PRT3_PS
+.set SD_SCK__SHIFT, 3
+.set SD_SCK__SLW, CYREG_PRT3_SLW
+
+/* SD_TX_DMA */
+.set SD_TX_DMA__DRQ_CTL, CYREG_IDMUX_DRQ_CTL0
+.set SD_TX_DMA__DRQ_NUMBER, 3
+.set SD_TX_DMA__NUMBEROF_TDS, 0
+.set SD_TX_DMA__PRIORITY, 1
+.set SD_TX_DMA__TERMIN_EN, 0
+.set SD_TX_DMA__TERMIN_SEL, 0
+.set SD_TX_DMA__TERMOUT0_EN, 1
+.set SD_TX_DMA__TERMOUT0_SEL, 3
+.set SD_TX_DMA__TERMOUT1_EN, 0
+.set SD_TX_DMA__TERMOUT1_SEL, 0
+.set SD_TX_DMA_COMPLETE__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
+.set SD_TX_DMA_COMPLETE__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
+.set SD_TX_DMA_COMPLETE__INTC_MASK, 0x40
+.set SD_TX_DMA_COMPLETE__INTC_NUMBER, 6
+.set SD_TX_DMA_COMPLETE__INTC_PRIOR_NUM, 7
+.set SD_TX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_6
+.set SD_TX_DMA_COMPLETE__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
+.set SD_TX_DMA_COMPLETE__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
+
+/* TERM_EN */
+.set TERM_EN__0__INTTYPE, CYREG_PICU15_INTTYPE3
+.set TERM_EN__0__MASK, 0x08
+.set TERM_EN__0__PC, CYREG_IO_PC_PRT15_PC3
+.set TERM_EN__0__PORT, 15
+.set TERM_EN__0__SHIFT, 3
+.set TERM_EN__AG, CYREG_PRT15_AG
+.set TERM_EN__AMUX, CYREG_PRT15_AMUX
+.set TERM_EN__BIE, CYREG_PRT15_BIE
+.set TERM_EN__BIT_MASK, CYREG_PRT15_BIT_MASK
+.set TERM_EN__BYP, CYREG_PRT15_BYP
+.set TERM_EN__CTL, CYREG_PRT15_CTL
+.set TERM_EN__DM0, CYREG_PRT15_DM0
+.set TERM_EN__DM1, CYREG_PRT15_DM1
+.set TERM_EN__DM2, CYREG_PRT15_DM2
+.set TERM_EN__DR, CYREG_PRT15_DR
+.set TERM_EN__INP_DIS, CYREG_PRT15_INP_DIS
+.set TERM_EN__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU15_BASE
+.set TERM_EN__LCD_COM_SEG, CYREG_PRT15_LCD_COM_SEG
+.set TERM_EN__LCD_EN, CYREG_PRT15_LCD_EN
+.set TERM_EN__MASK, 0x08
+.set TERM_EN__PORT, 15
+.set TERM_EN__PRT, CYREG_PRT15_PRT
+.set TERM_EN__PRTDSI__CAPS_SEL, CYREG_PRT15_CAPS_SEL
+.set TERM_EN__PRTDSI__DBL_SYNC_IN, CYREG_PRT15_DBL_SYNC_IN
+.set TERM_EN__PRTDSI__OE_SEL0, CYREG_PRT15_OE_SEL0
+.set TERM_EN__PRTDSI__OE_SEL1, CYREG_PRT15_OE_SEL1
+.set TERM_EN__PRTDSI__OUT_SEL0, CYREG_PRT15_OUT_SEL0
+.set TERM_EN__PRTDSI__OUT_SEL1, CYREG_PRT15_OUT_SEL1
+.set TERM_EN__PRTDSI__SYNC_OUT, CYREG_PRT15_SYNC_OUT
+.set TERM_EN__PS, CYREG_PRT15_PS
+.set TERM_EN__SHIFT, 3
+.set TERM_EN__SLW, CYREG_PRT15_SLW
+
+/* USBFS */
+.set USBFS_arb_int__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
+.set USBFS_arb_int__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
+.set USBFS_arb_int__INTC_MASK, 0x400000
+.set USBFS_arb_int__INTC_NUMBER, 22
+.set USBFS_arb_int__INTC_PRIOR_NUM, 6
+.set USBFS_arb_int__INTC_PRIOR_REG, CYREG_NVIC_PRI_22
+.set USBFS_arb_int__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
+.set USBFS_arb_int__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
+.set USBFS_bus_reset__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
+.set USBFS_bus_reset__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
+.set USBFS_bus_reset__INTC_MASK, 0x800000
+.set USBFS_bus_reset__INTC_NUMBER, 23
+.set USBFS_bus_reset__INTC_PRIOR_NUM, 7
+.set USBFS_bus_reset__INTC_PRIOR_REG, CYREG_NVIC_PRI_23
+.set USBFS_bus_reset__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
+.set USBFS_bus_reset__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
+.set USBFS_Dm__0__INTTYPE, CYREG_PICU15_INTTYPE7
+.set USBFS_Dm__0__MASK, 0x80
+.set USBFS_Dm__0__PC, CYREG_IO_PC_PRT15_7_6_PC1
+.set USBFS_Dm__0__PORT, 15
+.set USBFS_Dm__0__SHIFT, 7
+.set USBFS_Dm__AG, CYREG_PRT15_AG
+.set USBFS_Dm__AMUX, CYREG_PRT15_AMUX
+.set USBFS_Dm__BIE, CYREG_PRT15_BIE
+.set USBFS_Dm__BIT_MASK, CYREG_PRT15_BIT_MASK
+.set USBFS_Dm__BYP, CYREG_PRT15_BYP
+.set USBFS_Dm__CTL, CYREG_PRT15_CTL
+.set USBFS_Dm__DM0, CYREG_PRT15_DM0
+.set USBFS_Dm__DM1, CYREG_PRT15_DM1
+.set USBFS_Dm__DM2, CYREG_PRT15_DM2
+.set USBFS_Dm__DR, CYREG_PRT15_DR
+.set USBFS_Dm__INP_DIS, CYREG_PRT15_INP_DIS
+.set USBFS_Dm__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU15_BASE
+.set USBFS_Dm__LCD_COM_SEG, CYREG_PRT15_LCD_COM_SEG
+.set USBFS_Dm__LCD_EN, CYREG_PRT15_LCD_EN
+.set USBFS_Dm__MASK, 0x80
+.set USBFS_Dm__PORT, 15
+.set USBFS_Dm__PRT, CYREG_PRT15_PRT
+.set USBFS_Dm__PRTDSI__CAPS_SEL, CYREG_PRT15_CAPS_SEL
+.set USBFS_Dm__PRTDSI__DBL_SYNC_IN, CYREG_PRT15_DBL_SYNC_IN
+.set USBFS_Dm__PRTDSI__OE_SEL0, CYREG_PRT15_OE_SEL0
+.set USBFS_Dm__PRTDSI__OE_SEL1, CYREG_PRT15_OE_SEL1
+.set USBFS_Dm__PRTDSI__OUT_SEL0, CYREG_PRT15_OUT_SEL0
+.set USBFS_Dm__PRTDSI__OUT_SEL1, CYREG_PRT15_OUT_SEL1
+.set USBFS_Dm__PRTDSI__SYNC_OUT, CYREG_PRT15_SYNC_OUT
+.set USBFS_Dm__PS, CYREG_PRT15_PS
+.set USBFS_Dm__SHIFT, 7
+.set USBFS_Dm__SLW, CYREG_PRT15_SLW
+.set USBFS_Dp__0__INTTYPE, CYREG_PICU15_INTTYPE6
+.set USBFS_Dp__0__MASK, 0x40
+.set USBFS_Dp__0__PC, CYREG_IO_PC_PRT15_7_6_PC0
+.set USBFS_Dp__0__PORT, 15
+.set USBFS_Dp__0__SHIFT, 6
+.set USBFS_Dp__AG, CYREG_PRT15_AG
+.set USBFS_Dp__AMUX, CYREG_PRT15_AMUX
+.set USBFS_Dp__BIE, CYREG_PRT15_BIE
+.set USBFS_Dp__BIT_MASK, CYREG_PRT15_BIT_MASK
+.set USBFS_Dp__BYP, CYREG_PRT15_BYP
+.set USBFS_Dp__CTL, CYREG_PRT15_CTL
+.set USBFS_Dp__DM0, CYREG_PRT15_DM0
+.set USBFS_Dp__DM1, CYREG_PRT15_DM1
+.set USBFS_Dp__DM2, CYREG_PRT15_DM2
+.set USBFS_Dp__DR, CYREG_PRT15_DR
+.set USBFS_Dp__INP_DIS, CYREG_PRT15_INP_DIS
+.set USBFS_Dp__INTSTAT, CYREG_PICU15_INTSTAT
+.set USBFS_Dp__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU15_BASE
+.set USBFS_Dp__LCD_COM_SEG, CYREG_PRT15_LCD_COM_SEG
+.set USBFS_Dp__LCD_EN, CYREG_PRT15_LCD_EN
+.set USBFS_Dp__MASK, 0x40
+.set USBFS_Dp__PORT, 15
+.set USBFS_Dp__PRT, CYREG_PRT15_PRT
+.set USBFS_Dp__PRTDSI__CAPS_SEL, CYREG_PRT15_CAPS_SEL
+.set USBFS_Dp__PRTDSI__DBL_SYNC_IN, CYREG_PRT15_DBL_SYNC_IN
+.set USBFS_Dp__PRTDSI__OE_SEL0, CYREG_PRT15_OE_SEL0
+.set USBFS_Dp__PRTDSI__OE_SEL1, CYREG_PRT15_OE_SEL1
+.set USBFS_Dp__PRTDSI__OUT_SEL0, CYREG_PRT15_OUT_SEL0
+.set USBFS_Dp__PRTDSI__OUT_SEL1, CYREG_PRT15_OUT_SEL1
+.set USBFS_Dp__PRTDSI__SYNC_OUT, CYREG_PRT15_SYNC_OUT
+.set USBFS_Dp__PS, CYREG_PRT15_PS
+.set USBFS_Dp__SHIFT, 6
+.set USBFS_Dp__SLW, CYREG_PRT15_SLW
+.set USBFS_Dp__SNAP, CYREG_PICU_15_SNAP_15
+.set USBFS_dp_int__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
+.set USBFS_dp_int__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
+.set USBFS_dp_int__INTC_MASK, 0x1000
+.set USBFS_dp_int__INTC_NUMBER, 12
+.set USBFS_dp_int__INTC_PRIOR_NUM, 7
+.set USBFS_dp_int__INTC_PRIOR_REG, CYREG_NVIC_PRI_12
+.set USBFS_dp_int__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
+.set USBFS_dp_int__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
+.set USBFS_ep_0__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
+.set USBFS_ep_0__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
+.set USBFS_ep_0__INTC_MASK, 0x1000000
+.set USBFS_ep_0__INTC_NUMBER, 24
+.set USBFS_ep_0__INTC_PRIOR_NUM, 7
+.set USBFS_ep_0__INTC_PRIOR_REG, CYREG_NVIC_PRI_24
+.set USBFS_ep_0__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
+.set USBFS_ep_0__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
+.set USBFS_ep_1__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
+.set USBFS_ep_1__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
+.set USBFS_ep_1__INTC_MASK, 0x80
+.set USBFS_ep_1__INTC_NUMBER, 7
+.set USBFS_ep_1__INTC_PRIOR_NUM, 7
+.set USBFS_ep_1__INTC_PRIOR_REG, CYREG_NVIC_PRI_7
+.set USBFS_ep_1__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
+.set USBFS_ep_1__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
+.set USBFS_ep_2__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
+.set USBFS_ep_2__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
+.set USBFS_ep_2__INTC_MASK, 0x100
+.set USBFS_ep_2__INTC_NUMBER, 8
+.set USBFS_ep_2__INTC_PRIOR_NUM, 7
+.set USBFS_ep_2__INTC_PRIOR_REG, CYREG_NVIC_PRI_8
+.set USBFS_ep_2__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
+.set USBFS_ep_2__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
+.set USBFS_ep_3__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
+.set USBFS_ep_3__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
+.set USBFS_ep_3__INTC_MASK, 0x200
+.set USBFS_ep_3__INTC_NUMBER, 9
+.set USBFS_ep_3__INTC_PRIOR_NUM, 7
+.set USBFS_ep_3__INTC_PRIOR_REG, CYREG_NVIC_PRI_9
+.set USBFS_ep_3__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
+.set USBFS_ep_3__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
+.set USBFS_ep_4__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
+.set USBFS_ep_4__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
+.set USBFS_ep_4__INTC_MASK, 0x400
+.set USBFS_ep_4__INTC_NUMBER, 10
+.set USBFS_ep_4__INTC_PRIOR_NUM, 7
+.set USBFS_ep_4__INTC_PRIOR_REG, CYREG_NVIC_PRI_10
+.set USBFS_ep_4__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
+.set USBFS_ep_4__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
+.set USBFS_sof_int__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
+.set USBFS_sof_int__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
+.set USBFS_sof_int__INTC_MASK, 0x200000
+.set USBFS_sof_int__INTC_NUMBER, 21
+.set USBFS_sof_int__INTC_PRIOR_NUM, 7
+.set USBFS_sof_int__INTC_PRIOR_REG, CYREG_NVIC_PRI_21
+.set USBFS_sof_int__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
+.set USBFS_sof_int__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
+.set USBFS_USB__ARB_CFG, CYREG_USB_ARB_CFG
+.set USBFS_USB__ARB_EP1_CFG, CYREG_USB_ARB_EP1_CFG
+.set USBFS_USB__ARB_EP1_INT_EN, CYREG_USB_ARB_EP1_INT_EN
+.set USBFS_USB__ARB_EP1_SR, CYREG_USB_ARB_EP1_SR
+.set USBFS_USB__ARB_EP2_CFG, CYREG_USB_ARB_EP2_CFG
+.set USBFS_USB__ARB_EP2_INT_EN, CYREG_USB_ARB_EP2_INT_EN
+.set USBFS_USB__ARB_EP2_SR, CYREG_USB_ARB_EP2_SR
+.set USBFS_USB__ARB_EP3_CFG, CYREG_USB_ARB_EP3_CFG
+.set USBFS_USB__ARB_EP3_INT_EN, CYREG_USB_ARB_EP3_INT_EN
+.set USBFS_USB__ARB_EP3_SR, CYREG_USB_ARB_EP3_SR
+.set USBFS_USB__ARB_EP4_CFG, CYREG_USB_ARB_EP4_CFG
+.set USBFS_USB__ARB_EP4_INT_EN, CYREG_USB_ARB_EP4_INT_EN
+.set USBFS_USB__ARB_EP4_SR, CYREG_USB_ARB_EP4_SR
+.set USBFS_USB__ARB_EP5_CFG, CYREG_USB_ARB_EP5_CFG
+.set USBFS_USB__ARB_EP5_INT_EN, CYREG_USB_ARB_EP5_INT_EN
+.set USBFS_USB__ARB_EP5_SR, CYREG_USB_ARB_EP5_SR
+.set USBFS_USB__ARB_EP6_CFG, CYREG_USB_ARB_EP6_CFG
+.set USBFS_USB__ARB_EP6_INT_EN, CYREG_USB_ARB_EP6_INT_EN
+.set USBFS_USB__ARB_EP6_SR, CYREG_USB_ARB_EP6_SR
+.set USBFS_USB__ARB_EP7_CFG, CYREG_USB_ARB_EP7_CFG
+.set USBFS_USB__ARB_EP7_INT_EN, CYREG_USB_ARB_EP7_INT_EN
+.set USBFS_USB__ARB_EP7_SR, CYREG_USB_ARB_EP7_SR
+.set USBFS_USB__ARB_EP8_CFG, CYREG_USB_ARB_EP8_CFG
+.set USBFS_USB__ARB_EP8_INT_EN, CYREG_USB_ARB_EP8_INT_EN
+.set USBFS_USB__ARB_EP8_SR, CYREG_USB_ARB_EP8_SR
+.set USBFS_USB__ARB_INT_EN, CYREG_USB_ARB_INT_EN
+.set USBFS_USB__ARB_INT_SR, CYREG_USB_ARB_INT_SR
+.set USBFS_USB__ARB_RW1_DR, CYREG_USB_ARB_RW1_DR
+.set USBFS_USB__ARB_RW1_RA, CYREG_USB_ARB_RW1_RA
+.set USBFS_USB__ARB_RW1_RA_MSB, CYREG_USB_ARB_RW1_RA_MSB
+.set USBFS_USB__ARB_RW1_WA, CYREG_USB_ARB_RW1_WA
+.set USBFS_USB__ARB_RW1_WA_MSB, CYREG_USB_ARB_RW1_WA_MSB
+.set USBFS_USB__ARB_RW2_DR, CYREG_USB_ARB_RW2_DR
+.set USBFS_USB__ARB_RW2_RA, CYREG_USB_ARB_RW2_RA
+.set USBFS_USB__ARB_RW2_RA_MSB, CYREG_USB_ARB_RW2_RA_MSB
+.set USBFS_USB__ARB_RW2_WA, CYREG_USB_ARB_RW2_WA
+.set USBFS_USB__ARB_RW2_WA_MSB, CYREG_USB_ARB_RW2_WA_MSB
+.set USBFS_USB__ARB_RW3_DR, CYREG_USB_ARB_RW3_DR
+.set USBFS_USB__ARB_RW3_RA, CYREG_USB_ARB_RW3_RA
+.set USBFS_USB__ARB_RW3_RA_MSB, CYREG_USB_ARB_RW3_RA_MSB
+.set USBFS_USB__ARB_RW3_WA, CYREG_USB_ARB_RW3_WA
+.set USBFS_USB__ARB_RW3_WA_MSB, CYREG_USB_ARB_RW3_WA_MSB
+.set USBFS_USB__ARB_RW4_DR, CYREG_USB_ARB_RW4_DR
+.set USBFS_USB__ARB_RW4_RA, CYREG_USB_ARB_RW4_RA
+.set USBFS_USB__ARB_RW4_RA_MSB, CYREG_USB_ARB_RW4_RA_MSB
+.set USBFS_USB__ARB_RW4_WA, CYREG_USB_ARB_RW4_WA
+.set USBFS_USB__ARB_RW4_WA_MSB, CYREG_USB_ARB_RW4_WA_MSB
+.set USBFS_USB__ARB_RW5_DR, CYREG_USB_ARB_RW5_DR
+.set USBFS_USB__ARB_RW5_RA, CYREG_USB_ARB_RW5_RA
+.set USBFS_USB__ARB_RW5_RA_MSB, CYREG_USB_ARB_RW5_RA_MSB
+.set USBFS_USB__ARB_RW5_WA, CYREG_USB_ARB_RW5_WA
+.set USBFS_USB__ARB_RW5_WA_MSB, CYREG_USB_ARB_RW5_WA_MSB
+.set USBFS_USB__ARB_RW6_DR, CYREG_USB_ARB_RW6_DR
+.set USBFS_USB__ARB_RW6_RA, CYREG_USB_ARB_RW6_RA
+.set USBFS_USB__ARB_RW6_RA_MSB, CYREG_USB_ARB_RW6_RA_MSB
+.set USBFS_USB__ARB_RW6_WA, CYREG_USB_ARB_RW6_WA
+.set USBFS_USB__ARB_RW6_WA_MSB, CYREG_USB_ARB_RW6_WA_MSB
+.set USBFS_USB__ARB_RW7_DR, CYREG_USB_ARB_RW7_DR
+.set USBFS_USB__ARB_RW7_RA, CYREG_USB_ARB_RW7_RA
+.set USBFS_USB__ARB_RW7_RA_MSB, CYREG_USB_ARB_RW7_RA_MSB
+.set USBFS_USB__ARB_RW7_WA, CYREG_USB_ARB_RW7_WA
+.set USBFS_USB__ARB_RW7_WA_MSB, CYREG_USB_ARB_RW7_WA_MSB
+.set USBFS_USB__ARB_RW8_DR, CYREG_USB_ARB_RW8_DR
+.set USBFS_USB__ARB_RW8_RA, CYREG_USB_ARB_RW8_RA
+.set USBFS_USB__ARB_RW8_RA_MSB, CYREG_USB_ARB_RW8_RA_MSB
+.set USBFS_USB__ARB_RW8_WA, CYREG_USB_ARB_RW8_WA
+.set USBFS_USB__ARB_RW8_WA_MSB, CYREG_USB_ARB_RW8_WA_MSB
+.set USBFS_USB__BUF_SIZE, CYREG_USB_BUF_SIZE
+.set USBFS_USB__BUS_RST_CNT, CYREG_USB_BUS_RST_CNT
+.set USBFS_USB__CR0, CYREG_USB_CR0
+.set USBFS_USB__CR1, CYREG_USB_CR1
+.set USBFS_USB__CWA, CYREG_USB_CWA
+.set USBFS_USB__CWA_MSB, CYREG_USB_CWA_MSB
+.set USBFS_USB__DMA_THRES, CYREG_USB_DMA_THRES
+.set USBFS_USB__DMA_THRES_MSB, CYREG_USB_DMA_THRES_MSB
+.set USBFS_USB__DYN_RECONFIG, CYREG_USB_DYN_RECONFIG
+.set USBFS_USB__EP_ACTIVE, CYREG_USB_EP_ACTIVE
+.set USBFS_USB__EP_TYPE, CYREG_USB_EP_TYPE
+.set USBFS_USB__EP0_CNT, CYREG_USB_EP0_CNT
+.set USBFS_USB__EP0_CR, CYREG_USB_EP0_CR
+.set USBFS_USB__EP0_DR0, CYREG_USB_EP0_DR0
+.set USBFS_USB__EP0_DR1, CYREG_USB_EP0_DR1
+.set USBFS_USB__EP0_DR2, CYREG_USB_EP0_DR2
+.set USBFS_USB__EP0_DR3, CYREG_USB_EP0_DR3
+.set USBFS_USB__EP0_DR4, CYREG_USB_EP0_DR4
+.set USBFS_USB__EP0_DR5, CYREG_USB_EP0_DR5
+.set USBFS_USB__EP0_DR6, CYREG_USB_EP0_DR6
+.set USBFS_USB__EP0_DR7, CYREG_USB_EP0_DR7
+.set USBFS_USB__MEM_DATA, CYREG_USB_MEM_DATA_MBASE
+.set USBFS_USB__PM_ACT_CFG, CYREG_PM_ACT_CFG5
+.set USBFS_USB__PM_ACT_MSK, 0x01
+.set USBFS_USB__PM_STBY_CFG, CYREG_PM_STBY_CFG5
+.set USBFS_USB__PM_STBY_MSK, 0x01
+.set USBFS_USB__SIE_EP_INT_EN, CYREG_USB_SIE_EP_INT_EN
+.set USBFS_USB__SIE_EP_INT_SR, CYREG_USB_SIE_EP_INT_SR
+.set USBFS_USB__SIE_EP1_CNT0, CYREG_USB_SIE_EP1_CNT0
+.set USBFS_USB__SIE_EP1_CNT1, CYREG_USB_SIE_EP1_CNT1
+.set USBFS_USB__SIE_EP1_CR0, CYREG_USB_SIE_EP1_CR0
+.set USBFS_USB__SIE_EP2_CNT0, CYREG_USB_SIE_EP2_CNT0
+.set USBFS_USB__SIE_EP2_CNT1, CYREG_USB_SIE_EP2_CNT1
+.set USBFS_USB__SIE_EP2_CR0, CYREG_USB_SIE_EP2_CR0
+.set USBFS_USB__SIE_EP3_CNT0, CYREG_USB_SIE_EP3_CNT0
+.set USBFS_USB__SIE_EP3_CNT1, CYREG_USB_SIE_EP3_CNT1
+.set USBFS_USB__SIE_EP3_CR0, CYREG_USB_SIE_EP3_CR0
+.set USBFS_USB__SIE_EP4_CNT0, CYREG_USB_SIE_EP4_CNT0
+.set USBFS_USB__SIE_EP4_CNT1, CYREG_USB_SIE_EP4_CNT1
+.set USBFS_USB__SIE_EP4_CR0, CYREG_USB_SIE_EP4_CR0
+.set USBFS_USB__SIE_EP5_CNT0, CYREG_USB_SIE_EP5_CNT0
+.set USBFS_USB__SIE_EP5_CNT1, CYREG_USB_SIE_EP5_CNT1
+.set USBFS_USB__SIE_EP5_CR0, CYREG_USB_SIE_EP5_CR0
+.set USBFS_USB__SIE_EP6_CNT0, CYREG_USB_SIE_EP6_CNT0
+.set USBFS_USB__SIE_EP6_CNT1, CYREG_USB_SIE_EP6_CNT1
+.set USBFS_USB__SIE_EP6_CR0, CYREG_USB_SIE_EP6_CR0
+.set USBFS_USB__SIE_EP7_CNT0, CYREG_USB_SIE_EP7_CNT0
+.set USBFS_USB__SIE_EP7_CNT1, CYREG_USB_SIE_EP7_CNT1
+.set USBFS_USB__SIE_EP7_CR0, CYREG_USB_SIE_EP7_CR0
+.set USBFS_USB__SIE_EP8_CNT0, CYREG_USB_SIE_EP8_CNT0
+.set USBFS_USB__SIE_EP8_CNT1, CYREG_USB_SIE_EP8_CNT1
+.set USBFS_USB__SIE_EP8_CR0, CYREG_USB_SIE_EP8_CR0
+.set USBFS_USB__SOF0, CYREG_USB_SOF0
+.set USBFS_USB__SOF1, CYREG_USB_SOF1
+.set USBFS_USB__USB_CLK_EN, CYREG_USB_USB_CLK_EN
+.set USBFS_USB__USBIO_CR0, CYREG_USB_USBIO_CR0
+.set USBFS_USB__USBIO_CR1, CYREG_USB_USBIO_CR1
+
 /* scsiTarget */
 .set scsiTarget_datapath__16BIT_A0_REG, CYREG_B0_UDB00_01_A0
 .set scsiTarget_datapath__16BIT_A1_REG, CYREG_B0_UDB00_01_A1
@@ -2415,89 +2580,6 @@
 .set scsiTarget_StatusReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB15_ACTL
 .set scsiTarget_StatusReg__STATUS_REG, CYREG_B0_UDB15_ST
 
-/* Debug_Timer_Interrupt */
-.set Debug_Timer_Interrupt__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
-.set Debug_Timer_Interrupt__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
-.set Debug_Timer_Interrupt__INTC_MASK, 0x02
-.set Debug_Timer_Interrupt__INTC_NUMBER, 1
-.set Debug_Timer_Interrupt__INTC_PRIOR_NUM, 7
-.set Debug_Timer_Interrupt__INTC_PRIOR_REG, CYREG_NVIC_PRI_1
-.set Debug_Timer_Interrupt__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
-.set Debug_Timer_Interrupt__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
-
-/* Debug_Timer_TimerHW */
-.set Debug_Timer_TimerHW__CAP0, CYREG_TMR0_CAP0
-.set Debug_Timer_TimerHW__CAP1, CYREG_TMR0_CAP1
-.set Debug_Timer_TimerHW__CFG0, CYREG_TMR0_CFG0
-.set Debug_Timer_TimerHW__CFG1, CYREG_TMR0_CFG1
-.set Debug_Timer_TimerHW__CFG2, CYREG_TMR0_CFG2
-.set Debug_Timer_TimerHW__CNT_CMP0, CYREG_TMR0_CNT_CMP0
-.set Debug_Timer_TimerHW__CNT_CMP1, CYREG_TMR0_CNT_CMP1
-.set Debug_Timer_TimerHW__PER0, CYREG_TMR0_PER0
-.set Debug_Timer_TimerHW__PER1, CYREG_TMR0_PER1
-.set Debug_Timer_TimerHW__PM_ACT_CFG, CYREG_PM_ACT_CFG3
-.set Debug_Timer_TimerHW__PM_ACT_MSK, 0x01
-.set Debug_Timer_TimerHW__PM_STBY_CFG, CYREG_PM_STBY_CFG3
-.set Debug_Timer_TimerHW__PM_STBY_MSK, 0x01
-.set Debug_Timer_TimerHW__RT0, CYREG_TMR0_RT0
-.set Debug_Timer_TimerHW__RT1, CYREG_TMR0_RT1
-.set Debug_Timer_TimerHW__SR0, CYREG_TMR0_SR0
-
-/* SCSI_RX_DMA */
-.set SCSI_RX_DMA__DRQ_CTL, CYREG_IDMUX_DRQ_CTL0
-.set SCSI_RX_DMA__DRQ_NUMBER, 0
-.set SCSI_RX_DMA__NUMBEROF_TDS, 0
-.set SCSI_RX_DMA__PRIORITY, 2
-.set SCSI_RX_DMA__TERMIN_EN, 0
-.set SCSI_RX_DMA__TERMIN_SEL, 0
-.set SCSI_RX_DMA__TERMOUT0_EN, 1
-.set SCSI_RX_DMA__TERMOUT0_SEL, 0
-.set SCSI_RX_DMA__TERMOUT1_EN, 0
-.set SCSI_RX_DMA__TERMOUT1_SEL, 0
-
-/* SCSI_RX_DMA_COMPLETE */
-.set SCSI_RX_DMA_COMPLETE__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
-.set SCSI_RX_DMA_COMPLETE__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
-.set SCSI_RX_DMA_COMPLETE__INTC_MASK, 0x01
-.set SCSI_RX_DMA_COMPLETE__INTC_NUMBER, 0
-.set SCSI_RX_DMA_COMPLETE__INTC_PRIOR_NUM, 7
-.set SCSI_RX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_0
-.set SCSI_RX_DMA_COMPLETE__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
-.set SCSI_RX_DMA_COMPLETE__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
-
-/* SCSI_TX_DMA */
-.set SCSI_TX_DMA__DRQ_CTL, CYREG_IDMUX_DRQ_CTL0
-.set SCSI_TX_DMA__DRQ_NUMBER, 1
-.set SCSI_TX_DMA__NUMBEROF_TDS, 0
-.set SCSI_TX_DMA__PRIORITY, 2
-.set SCSI_TX_DMA__TERMIN_EN, 0
-.set SCSI_TX_DMA__TERMIN_SEL, 0
-.set SCSI_TX_DMA__TERMOUT0_EN, 1
-.set SCSI_TX_DMA__TERMOUT0_SEL, 1
-.set SCSI_TX_DMA__TERMOUT1_EN, 0
-.set SCSI_TX_DMA__TERMOUT1_SEL, 0
-
-/* SCSI_TX_DMA_COMPLETE */
-.set SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
-.set SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
-.set SCSI_TX_DMA_COMPLETE__INTC_MASK, 0x10
-.set SCSI_TX_DMA_COMPLETE__INTC_NUMBER, 4
-.set SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM, 7
-.set SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_4
-.set SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
-.set SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
-
-/* SD_Data_Clk */
-.set SD_Data_Clk__CFG0, CYREG_CLKDIST_DCFG0_CFG0
-.set SD_Data_Clk__CFG1, CYREG_CLKDIST_DCFG0_CFG1
-.set SD_Data_Clk__CFG2, CYREG_CLKDIST_DCFG0_CFG2
-.set SD_Data_Clk__CFG2_SRC_SEL_MASK, 0x07
-.set SD_Data_Clk__INDEX, 0x00
-.set SD_Data_Clk__PM_ACT_CFG, CYREG_PM_ACT_CFG2
-.set SD_Data_Clk__PM_ACT_MSK, 0x01
-.set SD_Data_Clk__PM_STBY_CFG, CYREG_PM_STBY_CFG2
-.set SD_Data_Clk__PM_STBY_MSK, 0x01
-
 /* timer_clock */
 .set timer_clock__CFG0, CYREG_CLKDIST_DCFG2_CFG0
 .set timer_clock__CFG1, CYREG_CLKDIST_DCFG2_CFG1
@@ -2509,154 +2591,53 @@
 .set timer_clock__PM_STBY_CFG, CYREG_PM_STBY_CFG2
 .set timer_clock__PM_STBY_MSK, 0x04
 
-/* SCSI_RST_ISR */
-.set SCSI_RST_ISR__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
-.set SCSI_RST_ISR__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
-.set SCSI_RST_ISR__INTC_MASK, 0x04
-.set SCSI_RST_ISR__INTC_NUMBER, 2
-.set SCSI_RST_ISR__INTC_PRIOR_NUM, 7
-.set SCSI_RST_ISR__INTC_PRIOR_REG, CYREG_NVIC_PRI_2
-.set SCSI_RST_ISR__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
-.set SCSI_RST_ISR__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
-
-/* SCSI_SEL_ISR */
-.set SCSI_SEL_ISR__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
-.set SCSI_SEL_ISR__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
-.set SCSI_SEL_ISR__INTC_MASK, 0x08
-.set SCSI_SEL_ISR__INTC_NUMBER, 3
-.set SCSI_SEL_ISR__INTC_PRIOR_NUM, 7
-.set SCSI_SEL_ISR__INTC_PRIOR_REG, CYREG_NVIC_PRI_3
-.set SCSI_SEL_ISR__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
-.set SCSI_SEL_ISR__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
-
-/* SCSI_Filtered */
-.set SCSI_Filtered_sts_sts_reg__0__MASK, 0x01
-.set SCSI_Filtered_sts_sts_reg__0__POS, 0
-.set SCSI_Filtered_sts_sts_reg__1__MASK, 0x02
-.set SCSI_Filtered_sts_sts_reg__1__POS, 1
-.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB11_12_ACTL
-.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB11_12_ST
-.set SCSI_Filtered_sts_sts_reg__2__MASK, 0x04
-.set SCSI_Filtered_sts_sts_reg__2__POS, 2
-.set SCSI_Filtered_sts_sts_reg__3__MASK, 0x08
-.set SCSI_Filtered_sts_sts_reg__3__POS, 3
-.set SCSI_Filtered_sts_sts_reg__4__MASK, 0x10
-.set SCSI_Filtered_sts_sts_reg__4__POS, 4
-.set SCSI_Filtered_sts_sts_reg__MASK, 0x1F
-.set SCSI_Filtered_sts_sts_reg__MASK_REG, CYREG_B0_UDB11_MSK
-.set SCSI_Filtered_sts_sts_reg__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL
-.set SCSI_Filtered_sts_sts_reg__PER_ST_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL
-.set SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB11_ACTL
-.set SCSI_Filtered_sts_sts_reg__STATUS_CNT_REG, CYREG_B0_UDB11_ST_CTL
-.set SCSI_Filtered_sts_sts_reg__STATUS_CONTROL_REG, CYREG_B0_UDB11_ST_CTL
-.set SCSI_Filtered_sts_sts_reg__STATUS_REG, CYREG_B0_UDB11_ST
-
-/* SCSI_CTL_PHASE */
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK, 0x01
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS, 0
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK, 0x02
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS, 1
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB02_03_ACTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB02_03_CTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB02_03_CTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB02_03_CTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB02_03_CTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB02_03_MSK
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB02_03_MSK
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB02_03_MSK
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB02_03_MSK
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK, 0x04
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS, 2
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB02_ACTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB02_CTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB02_ST_CTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB02_CTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB02_ST_CTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK, 0x07
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB02_MSK_ACTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB02_MSK_ACTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB02_MSK
-
-/* SCSI_Glitch_Ctl */
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK, 0x01
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS, 0
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB05_06_ACTL
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB05_06_CTL
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB05_06_CTL
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB05_06_CTL
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB05_06_CTL
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB05_06_MSK
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB05_06_MSK
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB05_06_MSK
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB05_06_MSK
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB05_ACTL
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB05_CTL
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB05_ST_CTL
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB05_CTL
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB05_ST_CTL
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK, 0x01
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB05_MSK_ACTL
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB05_MSK_ACTL
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB05_MSK
-
-/* SCSI_Parity_Error */
-.set SCSI_Parity_Error_sts_sts_reg__0__MASK, 0x01
-.set SCSI_Parity_Error_sts_sts_reg__0__POS, 0
-.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB02_03_ACTL
-.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB02_03_ST
-.set SCSI_Parity_Error_sts_sts_reg__MASK, 0x01
-.set SCSI_Parity_Error_sts_sts_reg__MASK_REG, CYREG_B0_UDB02_MSK
-.set SCSI_Parity_Error_sts_sts_reg__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB02_MSK_ACTL
-.set SCSI_Parity_Error_sts_sts_reg__PER_ST_AUX_CTL_REG, CYREG_B0_UDB02_MSK_ACTL
-.set SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB02_ACTL
-.set SCSI_Parity_Error_sts_sts_reg__STATUS_CNT_REG, CYREG_B0_UDB02_ST_CTL
-.set SCSI_Parity_Error_sts_sts_reg__STATUS_CONTROL_REG, CYREG_B0_UDB02_ST_CTL
-.set SCSI_Parity_Error_sts_sts_reg__STATUS_REG, CYREG_B0_UDB02_ST
-
 /* Miscellaneous */
 .set BCLK__BUS_CLK__HZ, 50000000
 .set BCLK__BUS_CLK__KHZ, 50000
 .set BCLK__BUS_CLK__MHZ, 50
 .set CYDEV_CHIP_DIE_LEOPARD, 1
-.set CYDEV_CHIP_DIE_PSOC4A, 12
-.set CYDEV_CHIP_DIE_PSOC5LP, 19
-.set CYDEV_CHIP_DIE_PSOC5TM, 20
-.set CYDEV_CHIP_DIE_TMA4, 2
+.set CYDEV_CHIP_DIE_PSOC4A, 16
+.set CYDEV_CHIP_DIE_PSOC5LP, 2
+.set CYDEV_CHIP_DIE_PSOC5TM, 3
+.set CYDEV_CHIP_DIE_TMA4, 4
 .set CYDEV_CHIP_DIE_UNKNOWN, 0
-.set CYDEV_CHIP_FAMILY_FM0P, 4
-.set CYDEV_CHIP_FAMILY_FM3, 5
-.set CYDEV_CHIP_FAMILY_FM4, 6
+.set CYDEV_CHIP_FAMILY_FM0P, 5
+.set CYDEV_CHIP_FAMILY_FM3, 6
+.set CYDEV_CHIP_FAMILY_FM4, 7
 .set CYDEV_CHIP_FAMILY_PSOC3, 1
 .set CYDEV_CHIP_FAMILY_PSOC4, 2
 .set CYDEV_CHIP_FAMILY_PSOC5, 3
+.set CYDEV_CHIP_FAMILY_PSOC6, 4
 .set CYDEV_CHIP_FAMILY_UNKNOWN, 0
 .set CYDEV_CHIP_FAMILY_USED, CYDEV_CHIP_FAMILY_PSOC5
 .set CYDEV_CHIP_JTAG_ID, 0x2E133069
 .set CYDEV_CHIP_MEMBER_3A, 1
-.set CYDEV_CHIP_MEMBER_4A, 12
-.set CYDEV_CHIP_MEMBER_4C, 18
-.set CYDEV_CHIP_MEMBER_4D, 8
-.set CYDEV_CHIP_MEMBER_4E, 4
-.set CYDEV_CHIP_MEMBER_4F, 13
-.set CYDEV_CHIP_MEMBER_4G, 2
-.set CYDEV_CHIP_MEMBER_4H, 11
-.set CYDEV_CHIP_MEMBER_4I, 17
-.set CYDEV_CHIP_MEMBER_4J, 9
-.set CYDEV_CHIP_MEMBER_4K, 10
-.set CYDEV_CHIP_MEMBER_4L, 16
-.set CYDEV_CHIP_MEMBER_4M, 15
-.set CYDEV_CHIP_MEMBER_4N, 6
-.set CYDEV_CHIP_MEMBER_4O, 5
-.set CYDEV_CHIP_MEMBER_4P, 14
-.set CYDEV_CHIP_MEMBER_4Q, 7
-.set CYDEV_CHIP_MEMBER_4U, 3
-.set CYDEV_CHIP_MEMBER_5A, 20
-.set CYDEV_CHIP_MEMBER_5B, 19
-.set CYDEV_CHIP_MEMBER_FM3, 24
-.set CYDEV_CHIP_MEMBER_FM4, 25
-.set CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE1, 21
-.set CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE2, 22
-.set CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE3, 23
+.set CYDEV_CHIP_MEMBER_4A, 16
+.set CYDEV_CHIP_MEMBER_4D, 12
+.set CYDEV_CHIP_MEMBER_4E, 6
+.set CYDEV_CHIP_MEMBER_4F, 17
+.set CYDEV_CHIP_MEMBER_4G, 4
+.set CYDEV_CHIP_MEMBER_4H, 15
+.set CYDEV_CHIP_MEMBER_4I, 21
+.set CYDEV_CHIP_MEMBER_4J, 13
+.set CYDEV_CHIP_MEMBER_4K, 14
+.set CYDEV_CHIP_MEMBER_4L, 20
+.set CYDEV_CHIP_MEMBER_4M, 19
+.set CYDEV_CHIP_MEMBER_4N, 9
+.set CYDEV_CHIP_MEMBER_4O, 7
+.set CYDEV_CHIP_MEMBER_4P, 18
+.set CYDEV_CHIP_MEMBER_4Q, 11
+.set CYDEV_CHIP_MEMBER_4R, 8
+.set CYDEV_CHIP_MEMBER_4S, 10
+.set CYDEV_CHIP_MEMBER_4U, 5
+.set CYDEV_CHIP_MEMBER_5A, 3
+.set CYDEV_CHIP_MEMBER_5B, 2
+.set CYDEV_CHIP_MEMBER_6A, 22
+.set CYDEV_CHIP_MEMBER_FM3, 26
+.set CYDEV_CHIP_MEMBER_FM4, 27
+.set CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE1, 23
+.set CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE2, 24
+.set CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE3, 25
 .set CYDEV_CHIP_MEMBER_UNKNOWN, 0
 .set CYDEV_CHIP_MEMBER_USED, CYDEV_CHIP_MEMBER_5B
 .set CYDEV_CHIP_DIE_EXPECT, CYDEV_CHIP_MEMBER_USED
@@ -2681,7 +2662,6 @@
 .set CYDEV_CHIP_REVISION_3A_PRODUCTION, 3
 .set CYDEV_CHIP_REVISION_4A_ES0, 17
 .set CYDEV_CHIP_REVISION_4A_PRODUCTION, 17
-.set CYDEV_CHIP_REVISION_4C_PRODUCTION, 0
 .set CYDEV_CHIP_REVISION_4D_PRODUCTION, 0
 .set CYDEV_CHIP_REVISION_4E_PRODUCTION, 0
 .set CYDEV_CHIP_REVISION_4F_PRODUCTION, 0
@@ -2700,12 +2680,16 @@
 .set CYDEV_CHIP_REVISION_4O_PRODUCTION, 0
 .set CYDEV_CHIP_REVISION_4P_PRODUCTION, 0
 .set CYDEV_CHIP_REVISION_4Q_PRODUCTION, 0
+.set CYDEV_CHIP_REVISION_4R_PRODUCTION, 0
+.set CYDEV_CHIP_REVISION_4S_PRODUCTION, 0
 .set CYDEV_CHIP_REVISION_4U_PRODUCTION, 0
 .set CYDEV_CHIP_REVISION_5A_ES0, 0
 .set CYDEV_CHIP_REVISION_5A_ES1, 1
 .set CYDEV_CHIP_REVISION_5A_PRODUCTION, 1
 .set CYDEV_CHIP_REVISION_5B_ES0, 0
 .set CYDEV_CHIP_REVISION_5B_PRODUCTION, 0
+.set CYDEV_CHIP_REVISION_6A_NO_UDB, 0
+.set CYDEV_CHIP_REVISION_6A_PRODUCTION, 0
 .set CYDEV_CHIP_REVISION_FM3_PRODUCTION, 0
 .set CYDEV_CHIP_REVISION_FM4_PRODUCTION, 0
 .set CYDEV_CHIP_REVISION_PDL_FM0P_TYPE1_PRODUCTION, 0
@@ -2737,7 +2721,7 @@
 .set CYDEV_ECC_ENABLE, 0
 .set CYDEV_HEAP_SIZE, 0x0400
 .set CYDEV_INSTRUCT_CACHE_ENABLED, 1
-.set CYDEV_INTR_RISING, 0x0000007E
+.set CYDEV_INTR_RISING, 0x0000007F
 .set CYDEV_IS_EXPORTING_CODE, 0
 .set CYDEV_IS_IMPORTING_CODE, 0
 .set CYDEV_PROJ_TYPE, 2

diff --git a/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitteriar.inc b/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitteriar.inc
index 18c7df3de0dec964833ade7bae0d2d7d61b6b6f3..d5db1af7833e7040c95d742e2b0556f6c0223fd5 100755 (executable)
--- a/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitteriar.inc
+++ b/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitteriar.inc
@@ -1,8 +1,51 @@
+;
+; File Name: cyfitteriar.inc
+; 
+; PSoC Creator  4.1
+;
+; Description:
+; 
+;
+;-------------------------------------------------------------------------------
+; Copyright (c) 2007-2017 Cypress Semiconductor.  All rights reserved.
+; You may use this file only in accordance with the license, terms, conditions, 
+; disclaimers, and limitations in the end user license agreement accompanying 
+; the software package with which this file was provided.
+;-------------------------------------------------------------------------------
+
 #ifndef INCLUDED_CYFITTERIAR_INC
 #define INCLUDED_CYFITTERIAR_INC
     INCLUDE cydeviceiar.inc
     INCLUDE cydeviceiar_trm.inc
 
+/* Debug_Timer_Interrupt */
+Debug_Timer_Interrupt__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
+Debug_Timer_Interrupt__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
+Debug_Timer_Interrupt__INTC_MASK EQU 0x01
+Debug_Timer_Interrupt__INTC_NUMBER EQU 0
+Debug_Timer_Interrupt__INTC_PRIOR_NUM EQU 7
+Debug_Timer_Interrupt__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_0
+Debug_Timer_Interrupt__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
+Debug_Timer_Interrupt__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
+
+/* Debug_Timer_TimerHW */
+Debug_Timer_TimerHW__CAP0 EQU CYREG_TMR0_CAP0
+Debug_Timer_TimerHW__CAP1 EQU CYREG_TMR0_CAP1
+Debug_Timer_TimerHW__CFG0 EQU CYREG_TMR0_CFG0
+Debug_Timer_TimerHW__CFG1 EQU CYREG_TMR0_CFG1
+Debug_Timer_TimerHW__CFG2 EQU CYREG_TMR0_CFG2
+Debug_Timer_TimerHW__CNT_CMP0 EQU CYREG_TMR0_CNT_CMP0
+Debug_Timer_TimerHW__CNT_CMP1 EQU CYREG_TMR0_CNT_CMP1
+Debug_Timer_TimerHW__PER0 EQU CYREG_TMR0_PER0
+Debug_Timer_TimerHW__PER1 EQU CYREG_TMR0_PER1
+Debug_Timer_TimerHW__PM_ACT_CFG EQU CYREG_PM_ACT_CFG3
+Debug_Timer_TimerHW__PM_ACT_MSK EQU 0x01
+Debug_Timer_TimerHW__PM_STBY_CFG EQU CYREG_PM_STBY_CFG3
+Debug_Timer_TimerHW__PM_STBY_MSK EQU 0x01
+Debug_Timer_TimerHW__RT0 EQU CYREG_TMR0_RT0
+Debug_Timer_TimerHW__RT1 EQU CYREG_TMR0_RT1
+Debug_Timer_TimerHW__SR0 EQU CYREG_TMR0_SR0
+
 /* LED1 */
 LED1__0__INTTYPE EQU CYREG_PICU12_INTTYPE0
 LED1__0__MASK EQU 0x01
@@ -41,2036 +84,571 @@ LED1__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN
 LED1__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ
 LED1__SLW EQU CYREG_PRT12_SLW
 
-/* SD_CS */
-SD_CS__0__INTTYPE EQU CYREG_PICU3_INTTYPE5
-SD_CS__0__MASK EQU 0x20
-SD_CS__0__PC EQU CYREG_PRT3_PC5
-SD_CS__0__PORT EQU 3
-SD_CS__0__SHIFT EQU 5
-SD_CS__AG EQU CYREG_PRT3_AG
-SD_CS__AMUX EQU CYREG_PRT3_AMUX
-SD_CS__BIE EQU CYREG_PRT3_BIE
-SD_CS__BIT_MASK EQU CYREG_PRT3_BIT_MASK
-SD_CS__BYP EQU CYREG_PRT3_BYP
-SD_CS__CTL EQU CYREG_PRT3_CTL
-SD_CS__DM0 EQU CYREG_PRT3_DM0
-SD_CS__DM1 EQU CYREG_PRT3_DM1
-SD_CS__DM2 EQU CYREG_PRT3_DM2
-SD_CS__DR EQU CYREG_PRT3_DR
-SD_CS__INP_DIS EQU CYREG_PRT3_INP_DIS
-SD_CS__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE
-SD_CS__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG
-SD_CS__LCD_EN EQU CYREG_PRT3_LCD_EN
-SD_CS__MASK EQU 0x20
-SD_CS__PORT EQU 3
-SD_CS__PRT EQU CYREG_PRT3_PRT
-SD_CS__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL
-SD_CS__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN
-SD_CS__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0
-SD_CS__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1
-SD_CS__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0
-SD_CS__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1
-SD_CS__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT
-SD_CS__PS EQU CYREG_PRT3_PS
-SD_CS__SHIFT EQU 5
-SD_CS__SLW EQU CYREG_PRT3_SLW
-
-/* USBFS_arb_int */
-USBFS_arb_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
-USBFS_arb_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-USBFS_arb_int__INTC_MASK EQU 0x400000
-USBFS_arb_int__INTC_NUMBER EQU 22
-USBFS_arb_int__INTC_PRIOR_NUM EQU 6
-USBFS_arb_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_22
-USBFS_arb_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
-USBFS_arb_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
-
-/* USBFS_bus_reset */
-USBFS_bus_reset__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
-USBFS_bus_reset__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-USBFS_bus_reset__INTC_MASK EQU 0x800000
-USBFS_bus_reset__INTC_NUMBER EQU 23
-USBFS_bus_reset__INTC_PRIOR_NUM EQU 7
-USBFS_bus_reset__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_23
-USBFS_bus_reset__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
-USBFS_bus_reset__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
-
-/* USBFS_Dm */
-USBFS_Dm__0__INTTYPE EQU CYREG_PICU15_INTTYPE7
-USBFS_Dm__0__MASK EQU 0x80
-USBFS_Dm__0__PC EQU CYREG_IO_PC_PRT15_7_6_PC1
-USBFS_Dm__0__PORT EQU 15
-USBFS_Dm__0__SHIFT EQU 7
-USBFS_Dm__AG EQU CYREG_PRT15_AG
-USBFS_Dm__AMUX EQU CYREG_PRT15_AMUX
-USBFS_Dm__BIE EQU CYREG_PRT15_BIE
-USBFS_Dm__BIT_MASK EQU CYREG_PRT15_BIT_MASK
-USBFS_Dm__BYP EQU CYREG_PRT15_BYP
-USBFS_Dm__CTL EQU CYREG_PRT15_CTL
-USBFS_Dm__DM0 EQU CYREG_PRT15_DM0
-USBFS_Dm__DM1 EQU CYREG_PRT15_DM1
-USBFS_Dm__DM2 EQU CYREG_PRT15_DM2
-USBFS_Dm__DR EQU CYREG_PRT15_DR
-USBFS_Dm__INP_DIS EQU CYREG_PRT15_INP_DIS
-USBFS_Dm__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU15_BASE
-USBFS_Dm__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG
-USBFS_Dm__LCD_EN EQU CYREG_PRT15_LCD_EN
-USBFS_Dm__MASK EQU 0x80
-USBFS_Dm__PORT EQU 15
-USBFS_Dm__PRT EQU CYREG_PRT15_PRT
-USBFS_Dm__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL
-USBFS_Dm__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN
-USBFS_Dm__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0
-USBFS_Dm__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1
-USBFS_Dm__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0
-USBFS_Dm__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1
-USBFS_Dm__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT
-USBFS_Dm__PS EQU CYREG_PRT15_PS
-USBFS_Dm__SHIFT EQU 7
-USBFS_Dm__SLW EQU CYREG_PRT15_SLW
-
-/* USBFS_Dp */
-USBFS_Dp__0__INTTYPE EQU CYREG_PICU15_INTTYPE6
-USBFS_Dp__0__MASK EQU 0x40
-USBFS_Dp__0__PC EQU CYREG_IO_PC_PRT15_7_6_PC0
-USBFS_Dp__0__PORT EQU 15
-USBFS_Dp__0__SHIFT EQU 6
-USBFS_Dp__AG EQU CYREG_PRT15_AG
-USBFS_Dp__AMUX EQU CYREG_PRT15_AMUX
-USBFS_Dp__BIE EQU CYREG_PRT15_BIE
-USBFS_Dp__BIT_MASK EQU CYREG_PRT15_BIT_MASK
-USBFS_Dp__BYP EQU CYREG_PRT15_BYP
-USBFS_Dp__CTL EQU CYREG_PRT15_CTL
-USBFS_Dp__DM0 EQU CYREG_PRT15_DM0
-USBFS_Dp__DM1 EQU CYREG_PRT15_DM1
-USBFS_Dp__DM2 EQU CYREG_PRT15_DM2
-USBFS_Dp__DR EQU CYREG_PRT15_DR
-USBFS_Dp__INP_DIS EQU CYREG_PRT15_INP_DIS
-USBFS_Dp__INTSTAT EQU CYREG_PICU15_INTSTAT
-USBFS_Dp__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU15_BASE
-USBFS_Dp__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG
-USBFS_Dp__LCD_EN EQU CYREG_PRT15_LCD_EN
-USBFS_Dp__MASK EQU 0x40
-USBFS_Dp__PORT EQU 15
-USBFS_Dp__PRT EQU CYREG_PRT15_PRT
-USBFS_Dp__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL
-USBFS_Dp__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN
-USBFS_Dp__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0
-USBFS_Dp__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1
-USBFS_Dp__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0
-USBFS_Dp__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1
-USBFS_Dp__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT
-USBFS_Dp__PS EQU CYREG_PRT15_PS
-USBFS_Dp__SHIFT EQU 6
-USBFS_Dp__SLW EQU CYREG_PRT15_SLW
-USBFS_Dp__SNAP EQU CYREG_PICU_15_SNAP_15
-
-/* USBFS_dp_int */
-USBFS_dp_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
-USBFS_dp_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-USBFS_dp_int__INTC_MASK EQU 0x1000
-USBFS_dp_int__INTC_NUMBER EQU 12
-USBFS_dp_int__INTC_PRIOR_NUM EQU 7
-USBFS_dp_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_12
-USBFS_dp_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
-USBFS_dp_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
+/* SCSI_CLK */
+SCSI_CLK__CFG0 EQU CYREG_CLKDIST_DCFG1_CFG0
+SCSI_CLK__CFG1 EQU CYREG_CLKDIST_DCFG1_CFG1
+SCSI_CLK__CFG2 EQU CYREG_CLKDIST_DCFG1_CFG2
+SCSI_CLK__CFG2_SRC_SEL_MASK EQU 0x07
+SCSI_CLK__INDEX EQU 0x01
+SCSI_CLK__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2
+SCSI_CLK__PM_ACT_MSK EQU 0x02
+SCSI_CLK__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2
+SCSI_CLK__PM_STBY_MSK EQU 0x02
 
-/* USBFS_ep_0 */
-USBFS_ep_0__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
-USBFS_ep_0__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-USBFS_ep_0__INTC_MASK EQU 0x1000000
-USBFS_ep_0__INTC_NUMBER EQU 24
-USBFS_ep_0__INTC_PRIOR_NUM EQU 7
-USBFS_ep_0__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_24
-USBFS_ep_0__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
-USBFS_ep_0__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
+/* SCSI_CTL_PHASE */
+SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01
+SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS EQU 0
+SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK EQU 0x02
+SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS EQU 1
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB02_03_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB02_03_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB02_03_MSK
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB02_03_MSK
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK
+SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK EQU 0x04
+SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS EQU 2
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB02_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB02_ST_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB02_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB02_ST_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__MASK EQU 0x07
+SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB02_MSK
 
-/* USBFS_ep_1 */
-USBFS_ep_1__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
-USBFS_ep_1__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-USBFS_ep_1__INTC_MASK EQU 0x80
-USBFS_ep_1__INTC_NUMBER EQU 7
-USBFS_ep_1__INTC_PRIOR_NUM EQU 7
-USBFS_ep_1__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_7
-USBFS_ep_1__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
-USBFS_ep_1__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
+/* SCSI_Filtered */
+SCSI_Filtered_sts_sts_reg__0__MASK EQU 0x01
+SCSI_Filtered_sts_sts_reg__0__POS EQU 0
+SCSI_Filtered_sts_sts_reg__1__MASK EQU 0x02
+SCSI_Filtered_sts_sts_reg__1__POS EQU 1
+SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL
+SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB11_12_ST
+SCSI_Filtered_sts_sts_reg__2__MASK EQU 0x04
+SCSI_Filtered_sts_sts_reg__2__POS EQU 2
+SCSI_Filtered_sts_sts_reg__3__MASK EQU 0x08
+SCSI_Filtered_sts_sts_reg__3__POS EQU 3
+SCSI_Filtered_sts_sts_reg__4__MASK EQU 0x10
+SCSI_Filtered_sts_sts_reg__4__POS EQU 4
+SCSI_Filtered_sts_sts_reg__MASK EQU 0x1F
+SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB11_MSK
+SCSI_Filtered_sts_sts_reg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
+SCSI_Filtered_sts_sts_reg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
+SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL
+SCSI_Filtered_sts_sts_reg__STATUS_CNT_REG EQU CYREG_B0_UDB11_ST_CTL
+SCSI_Filtered_sts_sts_reg__STATUS_CONTROL_REG EQU CYREG_B0_UDB11_ST_CTL
+SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB11_ST
 
-/* USBFS_ep_2 */
-USBFS_ep_2__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
-USBFS_ep_2__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-USBFS_ep_2__INTC_MASK EQU 0x100
-USBFS_ep_2__INTC_NUMBER EQU 8
-USBFS_ep_2__INTC_PRIOR_NUM EQU 7
-USBFS_ep_2__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_8
-USBFS_ep_2__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
-USBFS_ep_2__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
+/* SCSI_Glitch_Ctl */
+SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01
+SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS EQU 0
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB05_06_CTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB05_06_CTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB05_06_MSK
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB05_06_MSK
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK
+SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB05_CTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB05_ST_CTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB05_CTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB05_ST_CTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK EQU 0x01
+SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB05_MSK
 
-/* USBFS_ep_3 */
-USBFS_ep_3__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
-USBFS_ep_3__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-USBFS_ep_3__INTC_MASK EQU 0x200
-USBFS_ep_3__INTC_NUMBER EQU 9
-USBFS_ep_3__INTC_PRIOR_NUM EQU 7
-USBFS_ep_3__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_9
-USBFS_ep_3__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
-USBFS_ep_3__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
-
-/* USBFS_ep_4 */
-USBFS_ep_4__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
-USBFS_ep_4__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-USBFS_ep_4__INTC_MASK EQU 0x400
-USBFS_ep_4__INTC_NUMBER EQU 10
-USBFS_ep_4__INTC_PRIOR_NUM EQU 7
-USBFS_ep_4__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_10
-USBFS_ep_4__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
-USBFS_ep_4__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
-
-/* USBFS_sof_int */
-USBFS_sof_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
-USBFS_sof_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-USBFS_sof_int__INTC_MASK EQU 0x200000
-USBFS_sof_int__INTC_NUMBER EQU 21
-USBFS_sof_int__INTC_PRIOR_NUM EQU 7
-USBFS_sof_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_21
-USBFS_sof_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
-USBFS_sof_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
-
-/* USBFS_USB */
-USBFS_USB__ARB_CFG EQU CYREG_USB_ARB_CFG
-USBFS_USB__ARB_EP1_CFG EQU CYREG_USB_ARB_EP1_CFG
-USBFS_USB__ARB_EP1_INT_EN EQU CYREG_USB_ARB_EP1_INT_EN
-USBFS_USB__ARB_EP1_SR EQU CYREG_USB_ARB_EP1_SR
-USBFS_USB__ARB_EP2_CFG EQU CYREG_USB_ARB_EP2_CFG
-USBFS_USB__ARB_EP2_INT_EN EQU CYREG_USB_ARB_EP2_INT_EN
-USBFS_USB__ARB_EP2_SR EQU CYREG_USB_ARB_EP2_SR
-USBFS_USB__ARB_EP3_CFG EQU CYREG_USB_ARB_EP3_CFG
-USBFS_USB__ARB_EP3_INT_EN EQU CYREG_USB_ARB_EP3_INT_EN
-USBFS_USB__ARB_EP3_SR EQU CYREG_USB_ARB_EP3_SR
-USBFS_USB__ARB_EP4_CFG EQU CYREG_USB_ARB_EP4_CFG
-USBFS_USB__ARB_EP4_INT_EN EQU CYREG_USB_ARB_EP4_INT_EN
-USBFS_USB__ARB_EP4_SR EQU CYREG_USB_ARB_EP4_SR
-USBFS_USB__ARB_EP5_CFG EQU CYREG_USB_ARB_EP5_CFG
-USBFS_USB__ARB_EP5_INT_EN EQU CYREG_USB_ARB_EP5_INT_EN
-USBFS_USB__ARB_EP5_SR EQU CYREG_USB_ARB_EP5_SR
-USBFS_USB__ARB_EP6_CFG EQU CYREG_USB_ARB_EP6_CFG
-USBFS_USB__ARB_EP6_INT_EN EQU CYREG_USB_ARB_EP6_INT_EN
-USBFS_USB__ARB_EP6_SR EQU CYREG_USB_ARB_EP6_SR
-USBFS_USB__ARB_EP7_CFG EQU CYREG_USB_ARB_EP7_CFG
-USBFS_USB__ARB_EP7_INT_EN EQU CYREG_USB_ARB_EP7_INT_EN
-USBFS_USB__ARB_EP7_SR EQU CYREG_USB_ARB_EP7_SR
-USBFS_USB__ARB_EP8_CFG EQU CYREG_USB_ARB_EP8_CFG
-USBFS_USB__ARB_EP8_INT_EN EQU CYREG_USB_ARB_EP8_INT_EN
-USBFS_USB__ARB_EP8_SR EQU CYREG_USB_ARB_EP8_SR
-USBFS_USB__ARB_INT_EN EQU CYREG_USB_ARB_INT_EN
-USBFS_USB__ARB_INT_SR EQU CYREG_USB_ARB_INT_SR
-USBFS_USB__ARB_RW1_DR EQU CYREG_USB_ARB_RW1_DR
-USBFS_USB__ARB_RW1_RA EQU CYREG_USB_ARB_RW1_RA
-USBFS_USB__ARB_RW1_RA_MSB EQU CYREG_USB_ARB_RW1_RA_MSB
-USBFS_USB__ARB_RW1_WA EQU CYREG_USB_ARB_RW1_WA
-USBFS_USB__ARB_RW1_WA_MSB EQU CYREG_USB_ARB_RW1_WA_MSB
-USBFS_USB__ARB_RW2_DR EQU CYREG_USB_ARB_RW2_DR
-USBFS_USB__ARB_RW2_RA EQU CYREG_USB_ARB_RW2_RA
-USBFS_USB__ARB_RW2_RA_MSB EQU CYREG_USB_ARB_RW2_RA_MSB
-USBFS_USB__ARB_RW2_WA EQU CYREG_USB_ARB_RW2_WA
-USBFS_USB__ARB_RW2_WA_MSB EQU CYREG_USB_ARB_RW2_WA_MSB
-USBFS_USB__ARB_RW3_DR EQU CYREG_USB_ARB_RW3_DR
-USBFS_USB__ARB_RW3_RA EQU CYREG_USB_ARB_RW3_RA
-USBFS_USB__ARB_RW3_RA_MSB EQU CYREG_USB_ARB_RW3_RA_MSB
-USBFS_USB__ARB_RW3_WA EQU CYREG_USB_ARB_RW3_WA
-USBFS_USB__ARB_RW3_WA_MSB EQU CYREG_USB_ARB_RW3_WA_MSB
-USBFS_USB__ARB_RW4_DR EQU CYREG_USB_ARB_RW4_DR
-USBFS_USB__ARB_RW4_RA EQU CYREG_USB_ARB_RW4_RA
-USBFS_USB__ARB_RW4_RA_MSB EQU CYREG_USB_ARB_RW4_RA_MSB
-USBFS_USB__ARB_RW4_WA EQU CYREG_USB_ARB_RW4_WA
-USBFS_USB__ARB_RW4_WA_MSB EQU CYREG_USB_ARB_RW4_WA_MSB
-USBFS_USB__ARB_RW5_DR EQU CYREG_USB_ARB_RW5_DR
-USBFS_USB__ARB_RW5_RA EQU CYREG_USB_ARB_RW5_RA
-USBFS_USB__ARB_RW5_RA_MSB EQU CYREG_USB_ARB_RW5_RA_MSB
-USBFS_USB__ARB_RW5_WA EQU CYREG_USB_ARB_RW5_WA
-USBFS_USB__ARB_RW5_WA_MSB EQU CYREG_USB_ARB_RW5_WA_MSB
-USBFS_USB__ARB_RW6_DR EQU CYREG_USB_ARB_RW6_DR
-USBFS_USB__ARB_RW6_RA EQU CYREG_USB_ARB_RW6_RA
-USBFS_USB__ARB_RW6_RA_MSB EQU CYREG_USB_ARB_RW6_RA_MSB
-USBFS_USB__ARB_RW6_WA EQU CYREG_USB_ARB_RW6_WA
-USBFS_USB__ARB_RW6_WA_MSB EQU CYREG_USB_ARB_RW6_WA_MSB
-USBFS_USB__ARB_RW7_DR EQU CYREG_USB_ARB_RW7_DR
-USBFS_USB__ARB_RW7_RA EQU CYREG_USB_ARB_RW7_RA
-USBFS_USB__ARB_RW7_RA_MSB EQU CYREG_USB_ARB_RW7_RA_MSB
-USBFS_USB__ARB_RW7_WA EQU CYREG_USB_ARB_RW7_WA
-USBFS_USB__ARB_RW7_WA_MSB EQU CYREG_USB_ARB_RW7_WA_MSB
-USBFS_USB__ARB_RW8_DR EQU CYREG_USB_ARB_RW8_DR
-USBFS_USB__ARB_RW8_RA EQU CYREG_USB_ARB_RW8_RA
-USBFS_USB__ARB_RW8_RA_MSB EQU CYREG_USB_ARB_RW8_RA_MSB
-USBFS_USB__ARB_RW8_WA EQU CYREG_USB_ARB_RW8_WA
-USBFS_USB__ARB_RW8_WA_MSB EQU CYREG_USB_ARB_RW8_WA_MSB
-USBFS_USB__BUF_SIZE EQU CYREG_USB_BUF_SIZE
-USBFS_USB__BUS_RST_CNT EQU CYREG_USB_BUS_RST_CNT
-USBFS_USB__CR0 EQU CYREG_USB_CR0
-USBFS_USB__CR1 EQU CYREG_USB_CR1
-USBFS_USB__CWA EQU CYREG_USB_CWA
-USBFS_USB__CWA_MSB EQU CYREG_USB_CWA_MSB
-USBFS_USB__DMA_THRES EQU CYREG_USB_DMA_THRES
-USBFS_USB__DMA_THRES_MSB EQU CYREG_USB_DMA_THRES_MSB
-USBFS_USB__DYN_RECONFIG EQU CYREG_USB_DYN_RECONFIG
-USBFS_USB__EP_ACTIVE EQU CYREG_USB_EP_ACTIVE
-USBFS_USB__EP_TYPE EQU CYREG_USB_EP_TYPE
-USBFS_USB__EP0_CNT EQU CYREG_USB_EP0_CNT
-USBFS_USB__EP0_CR EQU CYREG_USB_EP0_CR
-USBFS_USB__EP0_DR0 EQU CYREG_USB_EP0_DR0
-USBFS_USB__EP0_DR1 EQU CYREG_USB_EP0_DR1
-USBFS_USB__EP0_DR2 EQU CYREG_USB_EP0_DR2
-USBFS_USB__EP0_DR3 EQU CYREG_USB_EP0_DR3
-USBFS_USB__EP0_DR4 EQU CYREG_USB_EP0_DR4
-USBFS_USB__EP0_DR5 EQU CYREG_USB_EP0_DR5
-USBFS_USB__EP0_DR6 EQU CYREG_USB_EP0_DR6
-USBFS_USB__EP0_DR7 EQU CYREG_USB_EP0_DR7
-USBFS_USB__MEM_DATA EQU CYREG_USB_MEM_DATA_MBASE
-USBFS_USB__PM_ACT_CFG EQU CYREG_PM_ACT_CFG5
-USBFS_USB__PM_ACT_MSK EQU 0x01
-USBFS_USB__PM_STBY_CFG EQU CYREG_PM_STBY_CFG5
-USBFS_USB__PM_STBY_MSK EQU 0x01
-USBFS_USB__SIE_EP_INT_EN EQU CYREG_USB_SIE_EP_INT_EN
-USBFS_USB__SIE_EP_INT_SR EQU CYREG_USB_SIE_EP_INT_SR
-USBFS_USB__SIE_EP1_CNT0 EQU CYREG_USB_SIE_EP1_CNT0
-USBFS_USB__SIE_EP1_CNT1 EQU CYREG_USB_SIE_EP1_CNT1
-USBFS_USB__SIE_EP1_CR0 EQU CYREG_USB_SIE_EP1_CR0
-USBFS_USB__SIE_EP2_CNT0 EQU CYREG_USB_SIE_EP2_CNT0
-USBFS_USB__SIE_EP2_CNT1 EQU CYREG_USB_SIE_EP2_CNT1
-USBFS_USB__SIE_EP2_CR0 EQU CYREG_USB_SIE_EP2_CR0
-USBFS_USB__SIE_EP3_CNT0 EQU CYREG_USB_SIE_EP3_CNT0
-USBFS_USB__SIE_EP3_CNT1 EQU CYREG_USB_SIE_EP3_CNT1
-USBFS_USB__SIE_EP3_CR0 EQU CYREG_USB_SIE_EP3_CR0
-USBFS_USB__SIE_EP4_CNT0 EQU CYREG_USB_SIE_EP4_CNT0
-USBFS_USB__SIE_EP4_CNT1 EQU CYREG_USB_SIE_EP4_CNT1
-USBFS_USB__SIE_EP4_CR0 EQU CYREG_USB_SIE_EP4_CR0
-USBFS_USB__SIE_EP5_CNT0 EQU CYREG_USB_SIE_EP5_CNT0
-USBFS_USB__SIE_EP5_CNT1 EQU CYREG_USB_SIE_EP5_CNT1
-USBFS_USB__SIE_EP5_CR0 EQU CYREG_USB_SIE_EP5_CR0
-USBFS_USB__SIE_EP6_CNT0 EQU CYREG_USB_SIE_EP6_CNT0
-USBFS_USB__SIE_EP6_CNT1 EQU CYREG_USB_SIE_EP6_CNT1
-USBFS_USB__SIE_EP6_CR0 EQU CYREG_USB_SIE_EP6_CR0
-USBFS_USB__SIE_EP7_CNT0 EQU CYREG_USB_SIE_EP7_CNT0
-USBFS_USB__SIE_EP7_CNT1 EQU CYREG_USB_SIE_EP7_CNT1
-USBFS_USB__SIE_EP7_CR0 EQU CYREG_USB_SIE_EP7_CR0
-USBFS_USB__SIE_EP8_CNT0 EQU CYREG_USB_SIE_EP8_CNT0
-USBFS_USB__SIE_EP8_CNT1 EQU CYREG_USB_SIE_EP8_CNT1
-USBFS_USB__SIE_EP8_CR0 EQU CYREG_USB_SIE_EP8_CR0
-USBFS_USB__SOF0 EQU CYREG_USB_SOF0
-USBFS_USB__SOF1 EQU CYREG_USB_SOF1
-USBFS_USB__USB_CLK_EN EQU CYREG_USB_USB_CLK_EN
-USBFS_USB__USBIO_CR0 EQU CYREG_USB_USBIO_CR0
-USBFS_USB__USBIO_CR1 EQU CYREG_USB_USBIO_CR1
-
-/* SDCard_BSPIM */
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB04_05_CTL
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB04_05_CTL
-SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB04_05_CTL
-SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB04_05_CTL
-SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB04_05_MSK
-SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB04_05_MSK
-SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB04_05_MSK
-SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB04_05_MSK
-SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL
-SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB04_CTL
-SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB04_ST_CTL
-SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB04_CTL
-SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB04_ST_CTL
-SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL
-SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL
-SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB04_MSK
-SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL
-SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB04_05_ST
-SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB04_MSK
-SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL
-SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL
-SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL
-SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB04_ST_CTL
-SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB04_ST_CTL
-SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB04_ST
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB07_08_ST
-SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10
-SDCard_BSPIM_RxStsReg__4__POS EQU 4
-SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20
-SDCard_BSPIM_RxStsReg__5__POS EQU 5
-SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40
-SDCard_BSPIM_RxStsReg__6__POS EQU 6
-SDCard_BSPIM_RxStsReg__MASK EQU 0x70
-SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B0_UDB07_MSK
-SDCard_BSPIM_RxStsReg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL
-SDCard_BSPIM_RxStsReg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL
-SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL
-SDCard_BSPIM_RxStsReg__STATUS_CNT_REG EQU CYREG_B0_UDB07_ST_CTL
-SDCard_BSPIM_RxStsReg__STATUS_CONTROL_REG EQU CYREG_B0_UDB07_ST_CTL
-SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B0_UDB07_ST
-SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB04_05_A0
-SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB04_05_A1
-SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B1_UDB04_05_D0
-SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B1_UDB04_05_D1
-SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL
-SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B1_UDB04_05_F0
-SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B1_UDB04_05_F1
-SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B1_UDB04_A0_A1
-SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B1_UDB04_A0
-SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B1_UDB04_A1
-SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B1_UDB04_D0_D1
-SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B1_UDB04_D0
-SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B1_UDB04_D1
-SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL
-SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B1_UDB04_F0_F1
-SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B1_UDB04_F0
-SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B1_UDB04_F1
-SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL
-SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL
-SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01
-SDCard_BSPIM_TxStsReg__0__POS EQU 0
-SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02
-SDCard_BSPIM_TxStsReg__1__POS EQU 1
-SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL
-SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST
-SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04
-SDCard_BSPIM_TxStsReg__2__POS EQU 2
-SDCard_BSPIM_TxStsReg__3__MASK EQU 0x08
-SDCard_BSPIM_TxStsReg__3__POS EQU 3
-SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10
-SDCard_BSPIM_TxStsReg__4__POS EQU 4
-SDCard_BSPIM_TxStsReg__MASK EQU 0x1F
-SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB07_MSK
-SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL
-SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB07_ST
-
-/* SD_SCK */
-SD_SCK__0__INTTYPE EQU CYREG_PICU3_INTTYPE3
-SD_SCK__0__MASK EQU 0x08
-SD_SCK__0__PC EQU CYREG_PRT3_PC3
-SD_SCK__0__PORT EQU 3
-SD_SCK__0__SHIFT EQU 3
-SD_SCK__AG EQU CYREG_PRT3_AG
-SD_SCK__AMUX EQU CYREG_PRT3_AMUX
-SD_SCK__BIE EQU CYREG_PRT3_BIE
-SD_SCK__BIT_MASK EQU CYREG_PRT3_BIT_MASK
-SD_SCK__BYP EQU CYREG_PRT3_BYP
-SD_SCK__CTL EQU CYREG_PRT3_CTL
-SD_SCK__DM0 EQU CYREG_PRT3_DM0
-SD_SCK__DM1 EQU CYREG_PRT3_DM1
-SD_SCK__DM2 EQU CYREG_PRT3_DM2
-SD_SCK__DR EQU CYREG_PRT3_DR
-SD_SCK__INP_DIS EQU CYREG_PRT3_INP_DIS
-SD_SCK__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE
-SD_SCK__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG
-SD_SCK__LCD_EN EQU CYREG_PRT3_LCD_EN
-SD_SCK__MASK EQU 0x08
-SD_SCK__PORT EQU 3
-SD_SCK__PRT EQU CYREG_PRT3_PRT
-SD_SCK__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL
-SD_SCK__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN
-SD_SCK__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0
-SD_SCK__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1
-SD_SCK__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0
-SD_SCK__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1
-SD_SCK__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT
-SD_SCK__PS EQU CYREG_PRT3_PS
-SD_SCK__SHIFT EQU 3
-SD_SCK__SLW EQU CYREG_PRT3_SLW
-
-/* SCSI_In */
-SCSI_In__0__INTTYPE EQU CYREG_PICU6_INTTYPE1
-SCSI_In__0__MASK EQU 0x02
-SCSI_In__0__PC EQU CYREG_PRT6_PC1
-SCSI_In__0__PORT EQU 6
-SCSI_In__0__SHIFT EQU 1
-SCSI_In__AG EQU CYREG_PRT6_AG
-SCSI_In__AMUX EQU CYREG_PRT6_AMUX
-SCSI_In__BIE EQU CYREG_PRT6_BIE
-SCSI_In__BIT_MASK EQU CYREG_PRT6_BIT_MASK
-SCSI_In__BYP EQU CYREG_PRT6_BYP
-SCSI_In__CTL EQU CYREG_PRT6_CTL
-SCSI_In__DBP__INTTYPE EQU CYREG_PICU6_INTTYPE1
-SCSI_In__DBP__MASK EQU 0x02
-SCSI_In__DBP__PC EQU CYREG_PRT6_PC1
-SCSI_In__DBP__PORT EQU 6
-SCSI_In__DBP__SHIFT EQU 1
-SCSI_In__DM0 EQU CYREG_PRT6_DM0
-SCSI_In__DM1 EQU CYREG_PRT6_DM1
-SCSI_In__DM2 EQU CYREG_PRT6_DM2
-SCSI_In__DR EQU CYREG_PRT6_DR
-SCSI_In__INP_DIS EQU CYREG_PRT6_INP_DIS
-SCSI_In__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU6_BASE
-SCSI_In__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
-SCSI_In__LCD_EN EQU CYREG_PRT6_LCD_EN
-SCSI_In__MASK EQU 0x02
-SCSI_In__PORT EQU 6
-SCSI_In__PRT EQU CYREG_PRT6_PRT
-SCSI_In__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
-SCSI_In__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
-SCSI_In__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
-SCSI_In__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
-SCSI_In__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
-SCSI_In__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
-SCSI_In__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
-SCSI_In__PS EQU CYREG_PRT6_PS
-SCSI_In__SHIFT EQU 1
-SCSI_In__SLW EQU CYREG_PRT6_SLW
-
-/* SCSI_In_DBx */
-SCSI_In_DBx__0__AG EQU CYREG_PRT6_AG
-SCSI_In_DBx__0__AMUX EQU CYREG_PRT6_AMUX
-SCSI_In_DBx__0__BIE EQU CYREG_PRT6_BIE
-SCSI_In_DBx__0__BIT_MASK EQU CYREG_PRT6_BIT_MASK
-SCSI_In_DBx__0__BYP EQU CYREG_PRT6_BYP
-SCSI_In_DBx__0__CTL EQU CYREG_PRT6_CTL
-SCSI_In_DBx__0__DM0 EQU CYREG_PRT6_DM0
-SCSI_In_DBx__0__DM1 EQU CYREG_PRT6_DM1
-SCSI_In_DBx__0__DM2 EQU CYREG_PRT6_DM2
-SCSI_In_DBx__0__DR EQU CYREG_PRT6_DR
-SCSI_In_DBx__0__INP_DIS EQU CYREG_PRT6_INP_DIS
-SCSI_In_DBx__0__INTTYPE EQU CYREG_PICU6_INTTYPE6
-SCSI_In_DBx__0__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
-SCSI_In_DBx__0__LCD_EN EQU CYREG_PRT6_LCD_EN
-SCSI_In_DBx__0__MASK EQU 0x40
-SCSI_In_DBx__0__PC EQU CYREG_PRT6_PC6
-SCSI_In_DBx__0__PORT EQU 6
-SCSI_In_DBx__0__PRT EQU CYREG_PRT6_PRT
-SCSI_In_DBx__0__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
-SCSI_In_DBx__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
-SCSI_In_DBx__0__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
-SCSI_In_DBx__0__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
-SCSI_In_DBx__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
-SCSI_In_DBx__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
-SCSI_In_DBx__0__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
-SCSI_In_DBx__0__PS EQU CYREG_PRT6_PS
-SCSI_In_DBx__0__SHIFT EQU 6
-SCSI_In_DBx__0__SLW EQU CYREG_PRT6_SLW
-SCSI_In_DBx__1__AG EQU CYREG_PRT6_AG
-SCSI_In_DBx__1__AMUX EQU CYREG_PRT6_AMUX
-SCSI_In_DBx__1__BIE EQU CYREG_PRT6_BIE
-SCSI_In_DBx__1__BIT_MASK EQU CYREG_PRT6_BIT_MASK
-SCSI_In_DBx__1__BYP EQU CYREG_PRT6_BYP
-SCSI_In_DBx__1__CTL EQU CYREG_PRT6_CTL
-SCSI_In_DBx__1__DM0 EQU CYREG_PRT6_DM0
-SCSI_In_DBx__1__DM1 EQU CYREG_PRT6_DM1
-SCSI_In_DBx__1__DM2 EQU CYREG_PRT6_DM2
-SCSI_In_DBx__1__DR EQU CYREG_PRT6_DR
-SCSI_In_DBx__1__INP_DIS EQU CYREG_PRT6_INP_DIS
-SCSI_In_DBx__1__INTTYPE EQU CYREG_PICU6_INTTYPE4
-SCSI_In_DBx__1__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
-SCSI_In_DBx__1__LCD_EN EQU CYREG_PRT6_LCD_EN
-SCSI_In_DBx__1__MASK EQU 0x10
-SCSI_In_DBx__1__PC EQU CYREG_PRT6_PC4
-SCSI_In_DBx__1__PORT EQU 6
-SCSI_In_DBx__1__PRT EQU CYREG_PRT6_PRT
-SCSI_In_DBx__1__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
-SCSI_In_DBx__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
-SCSI_In_DBx__1__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
-SCSI_In_DBx__1__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
-SCSI_In_DBx__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
-SCSI_In_DBx__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
-SCSI_In_DBx__1__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
-SCSI_In_DBx__1__PS EQU CYREG_PRT6_PS
-SCSI_In_DBx__1__SHIFT EQU 4
-SCSI_In_DBx__1__SLW EQU CYREG_PRT6_SLW
-SCSI_In_DBx__2__AG EQU CYREG_PRT12_AG
-SCSI_In_DBx__2__BIE EQU CYREG_PRT12_BIE
-SCSI_In_DBx__2__BIT_MASK EQU CYREG_PRT12_BIT_MASK
-SCSI_In_DBx__2__BYP EQU CYREG_PRT12_BYP
-SCSI_In_DBx__2__DM0 EQU CYREG_PRT12_DM0
-SCSI_In_DBx__2__DM1 EQU CYREG_PRT12_DM1
-SCSI_In_DBx__2__DM2 EQU CYREG_PRT12_DM2
-SCSI_In_DBx__2__DR EQU CYREG_PRT12_DR
-SCSI_In_DBx__2__INP_DIS EQU CYREG_PRT12_INP_DIS
-SCSI_In_DBx__2__INTTYPE EQU CYREG_PICU12_INTTYPE4
-SCSI_In_DBx__2__MASK EQU 0x10
-SCSI_In_DBx__2__PC EQU CYREG_PRT12_PC4
-SCSI_In_DBx__2__PORT EQU 12
-SCSI_In_DBx__2__PRT EQU CYREG_PRT12_PRT
-SCSI_In_DBx__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN
-SCSI_In_DBx__2__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0
-SCSI_In_DBx__2__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1
-SCSI_In_DBx__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0
-SCSI_In_DBx__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1
-SCSI_In_DBx__2__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT
-SCSI_In_DBx__2__PS EQU CYREG_PRT12_PS
-SCSI_In_DBx__2__SHIFT EQU 4
-SCSI_In_DBx__2__SIO_CFG EQU CYREG_PRT12_SIO_CFG
-SCSI_In_DBx__2__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF
-SCSI_In_DBx__2__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN
-SCSI_In_DBx__2__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ
-SCSI_In_DBx__2__SLW EQU CYREG_PRT12_SLW
-SCSI_In_DBx__3__AG EQU CYREG_PRT2_AG
-SCSI_In_DBx__3__AMUX EQU CYREG_PRT2_AMUX
-SCSI_In_DBx__3__BIE EQU CYREG_PRT2_BIE
-SCSI_In_DBx__3__BIT_MASK EQU CYREG_PRT2_BIT_MASK
-SCSI_In_DBx__3__BYP EQU CYREG_PRT2_BYP
-SCSI_In_DBx__3__CTL EQU CYREG_PRT2_CTL
-SCSI_In_DBx__3__DM0 EQU CYREG_PRT2_DM0
-SCSI_In_DBx__3__DM1 EQU CYREG_PRT2_DM1
-SCSI_In_DBx__3__DM2 EQU CYREG_PRT2_DM2
-SCSI_In_DBx__3__DR EQU CYREG_PRT2_DR
-SCSI_In_DBx__3__INP_DIS EQU CYREG_PRT2_INP_DIS
-SCSI_In_DBx__3__INTTYPE EQU CYREG_PICU2_INTTYPE6
-SCSI_In_DBx__3__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
-SCSI_In_DBx__3__LCD_EN EQU CYREG_PRT2_LCD_EN
-SCSI_In_DBx__3__MASK EQU 0x40
-SCSI_In_DBx__3__PC EQU CYREG_PRT2_PC6
-SCSI_In_DBx__3__PORT EQU 2
-SCSI_In_DBx__3__PRT EQU CYREG_PRT2_PRT
-SCSI_In_DBx__3__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
-SCSI_In_DBx__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
-SCSI_In_DBx__3__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
-SCSI_In_DBx__3__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
-SCSI_In_DBx__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
-SCSI_In_DBx__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
-SCSI_In_DBx__3__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
-SCSI_In_DBx__3__PS EQU CYREG_PRT2_PS
-SCSI_In_DBx__3__SHIFT EQU 6
-SCSI_In_DBx__3__SLW EQU CYREG_PRT2_SLW
-SCSI_In_DBx__4__AG EQU CYREG_PRT2_AG
-SCSI_In_DBx__4__AMUX EQU CYREG_PRT2_AMUX
-SCSI_In_DBx__4__BIE EQU CYREG_PRT2_BIE
-SCSI_In_DBx__4__BIT_MASK EQU CYREG_PRT2_BIT_MASK
-SCSI_In_DBx__4__BYP EQU CYREG_PRT2_BYP
-SCSI_In_DBx__4__CTL EQU CYREG_PRT2_CTL
-SCSI_In_DBx__4__DM0 EQU CYREG_PRT2_DM0
-SCSI_In_DBx__4__DM1 EQU CYREG_PRT2_DM1
-SCSI_In_DBx__4__DM2 EQU CYREG_PRT2_DM2
-SCSI_In_DBx__4__DR EQU CYREG_PRT2_DR
-SCSI_In_DBx__4__INP_DIS EQU CYREG_PRT2_INP_DIS
-SCSI_In_DBx__4__INTTYPE EQU CYREG_PICU2_INTTYPE4
-SCSI_In_DBx__4__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
-SCSI_In_DBx__4__LCD_EN EQU CYREG_PRT2_LCD_EN
-SCSI_In_DBx__4__MASK EQU 0x10
-SCSI_In_DBx__4__PC EQU CYREG_PRT2_PC4
-SCSI_In_DBx__4__PORT EQU 2
-SCSI_In_DBx__4__PRT EQU CYREG_PRT2_PRT
-SCSI_In_DBx__4__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
-SCSI_In_DBx__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
-SCSI_In_DBx__4__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
-SCSI_In_DBx__4__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
-SCSI_In_DBx__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
-SCSI_In_DBx__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
-SCSI_In_DBx__4__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
-SCSI_In_DBx__4__PS EQU CYREG_PRT2_PS
-SCSI_In_DBx__4__SHIFT EQU 4
-SCSI_In_DBx__4__SLW EQU CYREG_PRT2_SLW
-SCSI_In_DBx__5__AG EQU CYREG_PRT2_AG
-SCSI_In_DBx__5__AMUX EQU CYREG_PRT2_AMUX
-SCSI_In_DBx__5__BIE EQU CYREG_PRT2_BIE
-SCSI_In_DBx__5__BIT_MASK EQU CYREG_PRT2_BIT_MASK
-SCSI_In_DBx__5__BYP EQU CYREG_PRT2_BYP
-SCSI_In_DBx__5__CTL EQU CYREG_PRT2_CTL
-SCSI_In_DBx__5__DM0 EQU CYREG_PRT2_DM0
-SCSI_In_DBx__5__DM1 EQU CYREG_PRT2_DM1
-SCSI_In_DBx__5__DM2 EQU CYREG_PRT2_DM2
-SCSI_In_DBx__5__DR EQU CYREG_PRT2_DR
-SCSI_In_DBx__5__INP_DIS EQU CYREG_PRT2_INP_DIS
-SCSI_In_DBx__5__INTTYPE EQU CYREG_PICU2_INTTYPE2
-SCSI_In_DBx__5__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
-SCSI_In_DBx__5__LCD_EN EQU CYREG_PRT2_LCD_EN
-SCSI_In_DBx__5__MASK EQU 0x04
-SCSI_In_DBx__5__PC EQU CYREG_PRT2_PC2
-SCSI_In_DBx__5__PORT EQU 2
-SCSI_In_DBx__5__PRT EQU CYREG_PRT2_PRT
-SCSI_In_DBx__5__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
-SCSI_In_DBx__5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
-SCSI_In_DBx__5__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
-SCSI_In_DBx__5__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
-SCSI_In_DBx__5__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
-SCSI_In_DBx__5__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
-SCSI_In_DBx__5__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
-SCSI_In_DBx__5__PS EQU CYREG_PRT2_PS
-SCSI_In_DBx__5__SHIFT EQU 2
-SCSI_In_DBx__5__SLW EQU CYREG_PRT2_SLW
-SCSI_In_DBx__6__AG EQU CYREG_PRT2_AG
-SCSI_In_DBx__6__AMUX EQU CYREG_PRT2_AMUX
-SCSI_In_DBx__6__BIE EQU CYREG_PRT2_BIE
-SCSI_In_DBx__6__BIT_MASK EQU CYREG_PRT2_BIT_MASK
-SCSI_In_DBx__6__BYP EQU CYREG_PRT2_BYP
-SCSI_In_DBx__6__CTL EQU CYREG_PRT2_CTL
-SCSI_In_DBx__6__DM0 EQU CYREG_PRT2_DM0
-SCSI_In_DBx__6__DM1 EQU CYREG_PRT2_DM1
-SCSI_In_DBx__6__DM2 EQU CYREG_PRT2_DM2
-SCSI_In_DBx__6__DR EQU CYREG_PRT2_DR
-SCSI_In_DBx__6__INP_DIS EQU CYREG_PRT2_INP_DIS
-SCSI_In_DBx__6__INTTYPE EQU CYREG_PICU2_INTTYPE0
-SCSI_In_DBx__6__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
-SCSI_In_DBx__6__LCD_EN EQU CYREG_PRT2_LCD_EN
-SCSI_In_DBx__6__MASK EQU 0x01
-SCSI_In_DBx__6__PC EQU CYREG_PRT2_PC0
-SCSI_In_DBx__6__PORT EQU 2
-SCSI_In_DBx__6__PRT EQU CYREG_PRT2_PRT
-SCSI_In_DBx__6__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
-SCSI_In_DBx__6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
-SCSI_In_DBx__6__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
-SCSI_In_DBx__6__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
-SCSI_In_DBx__6__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
-SCSI_In_DBx__6__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
-SCSI_In_DBx__6__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
-SCSI_In_DBx__6__PS EQU CYREG_PRT2_PS
-SCSI_In_DBx__6__SHIFT EQU 0
-SCSI_In_DBx__6__SLW EQU CYREG_PRT2_SLW
-SCSI_In_DBx__7__AG EQU CYREG_PRT6_AG
-SCSI_In_DBx__7__AMUX EQU CYREG_PRT6_AMUX
-SCSI_In_DBx__7__BIE EQU CYREG_PRT6_BIE
-SCSI_In_DBx__7__BIT_MASK EQU CYREG_PRT6_BIT_MASK
-SCSI_In_DBx__7__BYP EQU CYREG_PRT6_BYP
-SCSI_In_DBx__7__CTL EQU CYREG_PRT6_CTL
-SCSI_In_DBx__7__DM0 EQU CYREG_PRT6_DM0
-SCSI_In_DBx__7__DM1 EQU CYREG_PRT6_DM1
-SCSI_In_DBx__7__DM2 EQU CYREG_PRT6_DM2
-SCSI_In_DBx__7__DR EQU CYREG_PRT6_DR
-SCSI_In_DBx__7__INP_DIS EQU CYREG_PRT6_INP_DIS
-SCSI_In_DBx__7__INTTYPE EQU CYREG_PICU6_INTTYPE3
-SCSI_In_DBx__7__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
-SCSI_In_DBx__7__LCD_EN EQU CYREG_PRT6_LCD_EN
-SCSI_In_DBx__7__MASK EQU 0x08
-SCSI_In_DBx__7__PC EQU CYREG_PRT6_PC3
-SCSI_In_DBx__7__PORT EQU 6
-SCSI_In_DBx__7__PRT EQU CYREG_PRT6_PRT
-SCSI_In_DBx__7__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
-SCSI_In_DBx__7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
-SCSI_In_DBx__7__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
-SCSI_In_DBx__7__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
-SCSI_In_DBx__7__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
-SCSI_In_DBx__7__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
-SCSI_In_DBx__7__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
-SCSI_In_DBx__7__PS EQU CYREG_PRT6_PS
-SCSI_In_DBx__7__SHIFT EQU 3
-SCSI_In_DBx__7__SLW EQU CYREG_PRT6_SLW
-SCSI_In_DBx__DB0__AG EQU CYREG_PRT6_AG
-SCSI_In_DBx__DB0__AMUX EQU CYREG_PRT6_AMUX
-SCSI_In_DBx__DB0__BIE EQU CYREG_PRT6_BIE
-SCSI_In_DBx__DB0__BIT_MASK EQU CYREG_PRT6_BIT_MASK
-SCSI_In_DBx__DB0__BYP EQU CYREG_PRT6_BYP
-SCSI_In_DBx__DB0__CTL EQU CYREG_PRT6_CTL
-SCSI_In_DBx__DB0__DM0 EQU CYREG_PRT6_DM0
-SCSI_In_DBx__DB0__DM1 EQU CYREG_PRT6_DM1
-SCSI_In_DBx__DB0__DM2 EQU CYREG_PRT6_DM2
-SCSI_In_DBx__DB0__DR EQU CYREG_PRT6_DR
-SCSI_In_DBx__DB0__INP_DIS EQU CYREG_PRT6_INP_DIS
-SCSI_In_DBx__DB0__INTTYPE EQU CYREG_PICU6_INTTYPE6
-SCSI_In_DBx__DB0__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
-SCSI_In_DBx__DB0__LCD_EN EQU CYREG_PRT6_LCD_EN
-SCSI_In_DBx__DB0__MASK EQU 0x40
-SCSI_In_DBx__DB0__PC EQU CYREG_PRT6_PC6
-SCSI_In_DBx__DB0__PORT EQU 6
-SCSI_In_DBx__DB0__PRT EQU CYREG_PRT6_PRT
-SCSI_In_DBx__DB0__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
-SCSI_In_DBx__DB0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
-SCSI_In_DBx__DB0__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
-SCSI_In_DBx__DB0__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
-SCSI_In_DBx__DB0__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
-SCSI_In_DBx__DB0__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
-SCSI_In_DBx__DB0__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
-SCSI_In_DBx__DB0__PS EQU CYREG_PRT6_PS
-SCSI_In_DBx__DB0__SHIFT EQU 6
-SCSI_In_DBx__DB0__SLW EQU CYREG_PRT6_SLW
-SCSI_In_DBx__DB1__AG EQU CYREG_PRT6_AG
-SCSI_In_DBx__DB1__AMUX EQU CYREG_PRT6_AMUX
-SCSI_In_DBx__DB1__BIE EQU CYREG_PRT6_BIE
-SCSI_In_DBx__DB1__BIT_MASK EQU CYREG_PRT6_BIT_MASK
-SCSI_In_DBx__DB1__BYP EQU CYREG_PRT6_BYP
-SCSI_In_DBx__DB1__CTL EQU CYREG_PRT6_CTL
-SCSI_In_DBx__DB1__DM0 EQU CYREG_PRT6_DM0
-SCSI_In_DBx__DB1__DM1 EQU CYREG_PRT6_DM1
-SCSI_In_DBx__DB1__DM2 EQU CYREG_PRT6_DM2
-SCSI_In_DBx__DB1__DR EQU CYREG_PRT6_DR
-SCSI_In_DBx__DB1__INP_DIS EQU CYREG_PRT6_INP_DIS
-SCSI_In_DBx__DB1__INTTYPE EQU CYREG_PICU6_INTTYPE4
-SCSI_In_DBx__DB1__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
-SCSI_In_DBx__DB1__LCD_EN EQU CYREG_PRT6_LCD_EN
-SCSI_In_DBx__DB1__MASK EQU 0x10
-SCSI_In_DBx__DB1__PC EQU CYREG_PRT6_PC4
-SCSI_In_DBx__DB1__PORT EQU 6
-SCSI_In_DBx__DB1__PRT EQU CYREG_PRT6_PRT
-SCSI_In_DBx__DB1__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
-SCSI_In_DBx__DB1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
-SCSI_In_DBx__DB1__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
-SCSI_In_DBx__DB1__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
-SCSI_In_DBx__DB1__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
-SCSI_In_DBx__DB1__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
-SCSI_In_DBx__DB1__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
-SCSI_In_DBx__DB1__PS EQU CYREG_PRT6_PS
-SCSI_In_DBx__DB1__SHIFT EQU 4
-SCSI_In_DBx__DB1__SLW EQU CYREG_PRT6_SLW
-SCSI_In_DBx__DB2__AG EQU CYREG_PRT12_AG
-SCSI_In_DBx__DB2__BIE EQU CYREG_PRT12_BIE
-SCSI_In_DBx__DB2__BIT_MASK EQU CYREG_PRT12_BIT_MASK
-SCSI_In_DBx__DB2__BYP EQU CYREG_PRT12_BYP
-SCSI_In_DBx__DB2__DM0 EQU CYREG_PRT12_DM0
-SCSI_In_DBx__DB2__DM1 EQU CYREG_PRT12_DM1
-SCSI_In_DBx__DB2__DM2 EQU CYREG_PRT12_DM2
-SCSI_In_DBx__DB2__DR EQU CYREG_PRT12_DR
-SCSI_In_DBx__DB2__INP_DIS EQU CYREG_PRT12_INP_DIS
-SCSI_In_DBx__DB2__INTTYPE EQU CYREG_PICU12_INTTYPE4
-SCSI_In_DBx__DB2__MASK EQU 0x10
-SCSI_In_DBx__DB2__PC EQU CYREG_PRT12_PC4
-SCSI_In_DBx__DB2__PORT EQU 12
-SCSI_In_DBx__DB2__PRT EQU CYREG_PRT12_PRT
-SCSI_In_DBx__DB2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN
-SCSI_In_DBx__DB2__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0
-SCSI_In_DBx__DB2__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1
-SCSI_In_DBx__DB2__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0
-SCSI_In_DBx__DB2__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1
-SCSI_In_DBx__DB2__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT
-SCSI_In_DBx__DB2__PS EQU CYREG_PRT12_PS
-SCSI_In_DBx__DB2__SHIFT EQU 4
-SCSI_In_DBx__DB2__SIO_CFG EQU CYREG_PRT12_SIO_CFG
-SCSI_In_DBx__DB2__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF
-SCSI_In_DBx__DB2__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN
-SCSI_In_DBx__DB2__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ
-SCSI_In_DBx__DB2__SLW EQU CYREG_PRT12_SLW
-SCSI_In_DBx__DB3__AG EQU CYREG_PRT2_AG
-SCSI_In_DBx__DB3__AMUX EQU CYREG_PRT2_AMUX
-SCSI_In_DBx__DB3__BIE EQU CYREG_PRT2_BIE
-SCSI_In_DBx__DB3__BIT_MASK EQU CYREG_PRT2_BIT_MASK
-SCSI_In_DBx__DB3__BYP EQU CYREG_PRT2_BYP
-SCSI_In_DBx__DB3__CTL EQU CYREG_PRT2_CTL
-SCSI_In_DBx__DB3__DM0 EQU CYREG_PRT2_DM0
-SCSI_In_DBx__DB3__DM1 EQU CYREG_PRT2_DM1
-SCSI_In_DBx__DB3__DM2 EQU CYREG_PRT2_DM2
-SCSI_In_DBx__DB3__DR EQU CYREG_PRT2_DR
-SCSI_In_DBx__DB3__INP_DIS EQU CYREG_PRT2_INP_DIS
-SCSI_In_DBx__DB3__INTTYPE EQU CYREG_PICU2_INTTYPE6
-SCSI_In_DBx__DB3__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
-SCSI_In_DBx__DB3__LCD_EN EQU CYREG_PRT2_LCD_EN
-SCSI_In_DBx__DB3__MASK EQU 0x40
-SCSI_In_DBx__DB3__PC EQU CYREG_PRT2_PC6
-SCSI_In_DBx__DB3__PORT EQU 2
-SCSI_In_DBx__DB3__PRT EQU CYREG_PRT2_PRT
-SCSI_In_DBx__DB3__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
-SCSI_In_DBx__DB3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
-SCSI_In_DBx__DB3__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
-SCSI_In_DBx__DB3__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
-SCSI_In_DBx__DB3__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
-SCSI_In_DBx__DB3__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
-SCSI_In_DBx__DB3__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
-SCSI_In_DBx__DB3__PS EQU CYREG_PRT2_PS
-SCSI_In_DBx__DB3__SHIFT EQU 6
-SCSI_In_DBx__DB3__SLW EQU CYREG_PRT2_SLW
-SCSI_In_DBx__DB4__AG EQU CYREG_PRT2_AG
-SCSI_In_DBx__DB4__AMUX EQU CYREG_PRT2_AMUX
-SCSI_In_DBx__DB4__BIE EQU CYREG_PRT2_BIE
-SCSI_In_DBx__DB4__BIT_MASK EQU CYREG_PRT2_BIT_MASK
-SCSI_In_DBx__DB4__BYP EQU CYREG_PRT2_BYP
-SCSI_In_DBx__DB4__CTL EQU CYREG_PRT2_CTL
-SCSI_In_DBx__DB4__DM0 EQU CYREG_PRT2_DM0
-SCSI_In_DBx__DB4__DM1 EQU CYREG_PRT2_DM1
-SCSI_In_DBx__DB4__DM2 EQU CYREG_PRT2_DM2
-SCSI_In_DBx__DB4__DR EQU CYREG_PRT2_DR
-SCSI_In_DBx__DB4__INP_DIS EQU CYREG_PRT2_INP_DIS
-SCSI_In_DBx__DB4__INTTYPE EQU CYREG_PICU2_INTTYPE4
-SCSI_In_DBx__DB4__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
-SCSI_In_DBx__DB4__LCD_EN EQU CYREG_PRT2_LCD_EN
-SCSI_In_DBx__DB4__MASK EQU 0x10
-SCSI_In_DBx__DB4__PC EQU CYREG_PRT2_PC4
-SCSI_In_DBx__DB4__PORT EQU 2
-SCSI_In_DBx__DB4__PRT EQU CYREG_PRT2_PRT
-SCSI_In_DBx__DB4__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
-SCSI_In_DBx__DB4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
-SCSI_In_DBx__DB4__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
-SCSI_In_DBx__DB4__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
-SCSI_In_DBx__DB4__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
-SCSI_In_DBx__DB4__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
-SCSI_In_DBx__DB4__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
-SCSI_In_DBx__DB4__PS EQU CYREG_PRT2_PS
-SCSI_In_DBx__DB4__SHIFT EQU 4
-SCSI_In_DBx__DB4__SLW EQU CYREG_PRT2_SLW
-SCSI_In_DBx__DB5__AG EQU CYREG_PRT2_AG
-SCSI_In_DBx__DB5__AMUX EQU CYREG_PRT2_AMUX
-SCSI_In_DBx__DB5__BIE EQU CYREG_PRT2_BIE
-SCSI_In_DBx__DB5__BIT_MASK EQU CYREG_PRT2_BIT_MASK
-SCSI_In_DBx__DB5__BYP EQU CYREG_PRT2_BYP
-SCSI_In_DBx__DB5__CTL EQU CYREG_PRT2_CTL
-SCSI_In_DBx__DB5__DM0 EQU CYREG_PRT2_DM0
-SCSI_In_DBx__DB5__DM1 EQU CYREG_PRT2_DM1
-SCSI_In_DBx__DB5__DM2 EQU CYREG_PRT2_DM2
-SCSI_In_DBx__DB5__DR EQU CYREG_PRT2_DR
-SCSI_In_DBx__DB5__INP_DIS EQU CYREG_PRT2_INP_DIS
-SCSI_In_DBx__DB5__INTTYPE EQU CYREG_PICU2_INTTYPE2
-SCSI_In_DBx__DB5__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
-SCSI_In_DBx__DB5__LCD_EN EQU CYREG_PRT2_LCD_EN
-SCSI_In_DBx__DB5__MASK EQU 0x04
-SCSI_In_DBx__DB5__PC EQU CYREG_PRT2_PC2
-SCSI_In_DBx__DB5__PORT EQU 2
-SCSI_In_DBx__DB5__PRT EQU CYREG_PRT2_PRT
-SCSI_In_DBx__DB5__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
-SCSI_In_DBx__DB5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
-SCSI_In_DBx__DB5__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
-SCSI_In_DBx__DB5__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
-SCSI_In_DBx__DB5__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
-SCSI_In_DBx__DB5__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
-SCSI_In_DBx__DB5__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
-SCSI_In_DBx__DB5__PS EQU CYREG_PRT2_PS
-SCSI_In_DBx__DB5__SHIFT EQU 2
-SCSI_In_DBx__DB5__SLW EQU CYREG_PRT2_SLW
-SCSI_In_DBx__DB6__AG EQU CYREG_PRT2_AG
-SCSI_In_DBx__DB6__AMUX EQU CYREG_PRT2_AMUX
-SCSI_In_DBx__DB6__BIE EQU CYREG_PRT2_BIE
-SCSI_In_DBx__DB6__BIT_MASK EQU CYREG_PRT2_BIT_MASK
-SCSI_In_DBx__DB6__BYP EQU CYREG_PRT2_BYP
-SCSI_In_DBx__DB6__CTL EQU CYREG_PRT2_CTL
-SCSI_In_DBx__DB6__DM0 EQU CYREG_PRT2_DM0
-SCSI_In_DBx__DB6__DM1 EQU CYREG_PRT2_DM1
-SCSI_In_DBx__DB6__DM2 EQU CYREG_PRT2_DM2
-SCSI_In_DBx__DB6__DR EQU CYREG_PRT2_DR
-SCSI_In_DBx__DB6__INP_DIS EQU CYREG_PRT2_INP_DIS
-SCSI_In_DBx__DB6__INTTYPE EQU CYREG_PICU2_INTTYPE0
-SCSI_In_DBx__DB6__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
-SCSI_In_DBx__DB6__LCD_EN EQU CYREG_PRT2_LCD_EN
-SCSI_In_DBx__DB6__MASK EQU 0x01
-SCSI_In_DBx__DB6__PC EQU CYREG_PRT2_PC0
-SCSI_In_DBx__DB6__PORT EQU 2
-SCSI_In_DBx__DB6__PRT EQU CYREG_PRT2_PRT
-SCSI_In_DBx__DB6__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
-SCSI_In_DBx__DB6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
-SCSI_In_DBx__DB6__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
-SCSI_In_DBx__DB6__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
-SCSI_In_DBx__DB6__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
-SCSI_In_DBx__DB6__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
-SCSI_In_DBx__DB6__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
-SCSI_In_DBx__DB6__PS EQU CYREG_PRT2_PS
-SCSI_In_DBx__DB6__SHIFT EQU 0
-SCSI_In_DBx__DB6__SLW EQU CYREG_PRT2_SLW
-SCSI_In_DBx__DB7__AG EQU CYREG_PRT6_AG
-SCSI_In_DBx__DB7__AMUX EQU CYREG_PRT6_AMUX
-SCSI_In_DBx__DB7__BIE EQU CYREG_PRT6_BIE
-SCSI_In_DBx__DB7__BIT_MASK EQU CYREG_PRT6_BIT_MASK
-SCSI_In_DBx__DB7__BYP EQU CYREG_PRT6_BYP
-SCSI_In_DBx__DB7__CTL EQU CYREG_PRT6_CTL
-SCSI_In_DBx__DB7__DM0 EQU CYREG_PRT6_DM0
-SCSI_In_DBx__DB7__DM1 EQU CYREG_PRT6_DM1
-SCSI_In_DBx__DB7__DM2 EQU CYREG_PRT6_DM2
-SCSI_In_DBx__DB7__DR EQU CYREG_PRT6_DR
-SCSI_In_DBx__DB7__INP_DIS EQU CYREG_PRT6_INP_DIS
-SCSI_In_DBx__DB7__INTTYPE EQU CYREG_PICU6_INTTYPE3
-SCSI_In_DBx__DB7__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
-SCSI_In_DBx__DB7__LCD_EN EQU CYREG_PRT6_LCD_EN
-SCSI_In_DBx__DB7__MASK EQU 0x08
-SCSI_In_DBx__DB7__PC EQU CYREG_PRT6_PC3
-SCSI_In_DBx__DB7__PORT EQU 6
-SCSI_In_DBx__DB7__PRT EQU CYREG_PRT6_PRT
-SCSI_In_DBx__DB7__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
-SCSI_In_DBx__DB7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
-SCSI_In_DBx__DB7__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
-SCSI_In_DBx__DB7__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
-SCSI_In_DBx__DB7__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
-SCSI_In_DBx__DB7__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
-SCSI_In_DBx__DB7__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
-SCSI_In_DBx__DB7__PS EQU CYREG_PRT6_PS
-SCSI_In_DBx__DB7__SHIFT EQU 3
-SCSI_In_DBx__DB7__SLW EQU CYREG_PRT6_SLW
-
-/* SD_MISO */
-SD_MISO__0__INTTYPE EQU CYREG_PICU3_INTTYPE2
-SD_MISO__0__MASK EQU 0x04
-SD_MISO__0__PC EQU CYREG_PRT3_PC2
-SD_MISO__0__PORT EQU 3
-SD_MISO__0__SHIFT EQU 2
-SD_MISO__AG EQU CYREG_PRT3_AG
-SD_MISO__AMUX EQU CYREG_PRT3_AMUX
-SD_MISO__BIE EQU CYREG_PRT3_BIE
-SD_MISO__BIT_MASK EQU CYREG_PRT3_BIT_MASK
-SD_MISO__BYP EQU CYREG_PRT3_BYP
-SD_MISO__CTL EQU CYREG_PRT3_CTL
-SD_MISO__DM0 EQU CYREG_PRT3_DM0
-SD_MISO__DM1 EQU CYREG_PRT3_DM1
-SD_MISO__DM2 EQU CYREG_PRT3_DM2
-SD_MISO__DR EQU CYREG_PRT3_DR
-SD_MISO__INP_DIS EQU CYREG_PRT3_INP_DIS
-SD_MISO__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE
-SD_MISO__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG
-SD_MISO__LCD_EN EQU CYREG_PRT3_LCD_EN
-SD_MISO__MASK EQU 0x04
-SD_MISO__PORT EQU 3
-SD_MISO__PRT EQU CYREG_PRT3_PRT
-SD_MISO__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL
-SD_MISO__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN
-SD_MISO__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0
-SD_MISO__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1
-SD_MISO__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0
-SD_MISO__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1
-SD_MISO__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT
-SD_MISO__PS EQU CYREG_PRT3_PS
-SD_MISO__SHIFT EQU 2
-SD_MISO__SLW EQU CYREG_PRT3_SLW
-
-/* SD_MOSI */
-SD_MOSI__0__INTTYPE EQU CYREG_PICU3_INTTYPE4
-SD_MOSI__0__MASK EQU 0x10
-SD_MOSI__0__PC EQU CYREG_PRT3_PC4
-SD_MOSI__0__PORT EQU 3
-SD_MOSI__0__SHIFT EQU 4
-SD_MOSI__AG EQU CYREG_PRT3_AG
-SD_MOSI__AMUX EQU CYREG_PRT3_AMUX
-SD_MOSI__BIE EQU CYREG_PRT3_BIE
-SD_MOSI__BIT_MASK EQU CYREG_PRT3_BIT_MASK
-SD_MOSI__BYP EQU CYREG_PRT3_BYP
-SD_MOSI__CTL EQU CYREG_PRT3_CTL
-SD_MOSI__DM0 EQU CYREG_PRT3_DM0
-SD_MOSI__DM1 EQU CYREG_PRT3_DM1
-SD_MOSI__DM2 EQU CYREG_PRT3_DM2
-SD_MOSI__DR EQU CYREG_PRT3_DR
-SD_MOSI__INP_DIS EQU CYREG_PRT3_INP_DIS
-SD_MOSI__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE
-SD_MOSI__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG
-SD_MOSI__LCD_EN EQU CYREG_PRT3_LCD_EN
-SD_MOSI__MASK EQU 0x10
-SD_MOSI__PORT EQU 3
-SD_MOSI__PRT EQU CYREG_PRT3_PRT
-SD_MOSI__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL
-SD_MOSI__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN
-SD_MOSI__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0
-SD_MOSI__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1
-SD_MOSI__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0
-SD_MOSI__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1
-SD_MOSI__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT
-SD_MOSI__PS EQU CYREG_PRT3_PS
-SD_MOSI__SHIFT EQU 4
-SD_MOSI__SLW EQU CYREG_PRT3_SLW
-
-/* TERM_EN */
-TERM_EN__0__INTTYPE EQU CYREG_PICU15_INTTYPE3
-TERM_EN__0__MASK EQU 0x08
-TERM_EN__0__PC EQU CYREG_IO_PC_PRT15_PC3
-TERM_EN__0__PORT EQU 15
-TERM_EN__0__SHIFT EQU 3
-TERM_EN__AG EQU CYREG_PRT15_AG
-TERM_EN__AMUX EQU CYREG_PRT15_AMUX
-TERM_EN__BIE EQU CYREG_PRT15_BIE
-TERM_EN__BIT_MASK EQU CYREG_PRT15_BIT_MASK
-TERM_EN__BYP EQU CYREG_PRT15_BYP
-TERM_EN__CTL EQU CYREG_PRT15_CTL
-TERM_EN__DM0 EQU CYREG_PRT15_DM0
-TERM_EN__DM1 EQU CYREG_PRT15_DM1
-TERM_EN__DM2 EQU CYREG_PRT15_DM2
-TERM_EN__DR EQU CYREG_PRT15_DR
-TERM_EN__INP_DIS EQU CYREG_PRT15_INP_DIS
-TERM_EN__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU15_BASE
-TERM_EN__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG
-TERM_EN__LCD_EN EQU CYREG_PRT15_LCD_EN
-TERM_EN__MASK EQU 0x08
-TERM_EN__PORT EQU 15
-TERM_EN__PRT EQU CYREG_PRT15_PRT
-TERM_EN__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL
-TERM_EN__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN
-TERM_EN__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0
-TERM_EN__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1
-TERM_EN__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0
-TERM_EN__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1
-TERM_EN__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT
-TERM_EN__PS EQU CYREG_PRT15_PS
-TERM_EN__SHIFT EQU 3
-TERM_EN__SLW EQU CYREG_PRT15_SLW
-
-/* SCSI_CLK */
-SCSI_CLK__CFG0 EQU CYREG_CLKDIST_DCFG1_CFG0
-SCSI_CLK__CFG1 EQU CYREG_CLKDIST_DCFG1_CFG1
-SCSI_CLK__CFG2 EQU CYREG_CLKDIST_DCFG1_CFG2
-SCSI_CLK__CFG2_SRC_SEL_MASK EQU 0x07
-SCSI_CLK__INDEX EQU 0x01
-SCSI_CLK__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2
-SCSI_CLK__PM_ACT_MSK EQU 0x02
-SCSI_CLK__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2
-SCSI_CLK__PM_STBY_MSK EQU 0x02
-
-/* SCSI_Out */
-SCSI_Out__0__AG EQU CYREG_PRT6_AG
-SCSI_Out__0__AMUX EQU CYREG_PRT6_AMUX
-SCSI_Out__0__BIE EQU CYREG_PRT6_BIE
-SCSI_Out__0__BIT_MASK EQU CYREG_PRT6_BIT_MASK
-SCSI_Out__0__BYP EQU CYREG_PRT6_BYP
-SCSI_Out__0__CTL EQU CYREG_PRT6_CTL
-SCSI_Out__0__DM0 EQU CYREG_PRT6_DM0
-SCSI_Out__0__DM1 EQU CYREG_PRT6_DM1
-SCSI_Out__0__DM2 EQU CYREG_PRT6_DM2
-SCSI_Out__0__DR EQU CYREG_PRT6_DR
-SCSI_Out__0__INP_DIS EQU CYREG_PRT6_INP_DIS
-SCSI_Out__0__INTTYPE EQU CYREG_PICU6_INTTYPE2
-SCSI_Out__0__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
-SCSI_Out__0__LCD_EN EQU CYREG_PRT6_LCD_EN
-SCSI_Out__0__MASK EQU 0x04
-SCSI_Out__0__PC EQU CYREG_PRT6_PC2
-SCSI_Out__0__PORT EQU 6
-SCSI_Out__0__PRT EQU CYREG_PRT6_PRT
-SCSI_Out__0__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
-SCSI_Out__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
-SCSI_Out__0__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
-SCSI_Out__0__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
-SCSI_Out__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
-SCSI_Out__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
-SCSI_Out__0__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
-SCSI_Out__0__PS EQU CYREG_PRT6_PS
-SCSI_Out__0__SHIFT EQU 2
-SCSI_Out__0__SLW EQU CYREG_PRT6_SLW
-SCSI_Out__1__AG EQU CYREG_PRT4_AG
-SCSI_Out__1__AMUX EQU CYREG_PRT4_AMUX
-SCSI_Out__1__BIE EQU CYREG_PRT4_BIE
-SCSI_Out__1__BIT_MASK EQU CYREG_PRT4_BIT_MASK
-SCSI_Out__1__BYP EQU CYREG_PRT4_BYP
-SCSI_Out__1__CTL EQU CYREG_PRT4_CTL
-SCSI_Out__1__DM0 EQU CYREG_PRT4_DM0
-SCSI_Out__1__DM1 EQU CYREG_PRT4_DM1
-SCSI_Out__1__DM2 EQU CYREG_PRT4_DM2
-SCSI_Out__1__DR EQU CYREG_PRT4_DR
-SCSI_Out__1__INP_DIS EQU CYREG_PRT4_INP_DIS
-SCSI_Out__1__INTTYPE EQU CYREG_PICU4_INTTYPE6
-SCSI_Out__1__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
-SCSI_Out__1__LCD_EN EQU CYREG_PRT4_LCD_EN
-SCSI_Out__1__MASK EQU 0x40
-SCSI_Out__1__PC EQU CYREG_PRT4_PC6
-SCSI_Out__1__PORT EQU 4
-SCSI_Out__1__PRT EQU CYREG_PRT4_PRT
-SCSI_Out__1__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
-SCSI_Out__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
-SCSI_Out__1__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
-SCSI_Out__1__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
-SCSI_Out__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
-SCSI_Out__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
-SCSI_Out__1__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
-SCSI_Out__1__PS EQU CYREG_PRT4_PS
-SCSI_Out__1__SHIFT EQU 6
-SCSI_Out__1__SLW EQU CYREG_PRT4_SLW
-SCSI_Out__2__AG EQU CYREG_PRT0_AG
-SCSI_Out__2__AMUX EQU CYREG_PRT0_AMUX
-SCSI_Out__2__BIE EQU CYREG_PRT0_BIE
-SCSI_Out__2__BIT_MASK EQU CYREG_PRT0_BIT_MASK
-SCSI_Out__2__BYP EQU CYREG_PRT0_BYP
-SCSI_Out__2__CTL EQU CYREG_PRT0_CTL
-SCSI_Out__2__DM0 EQU CYREG_PRT0_DM0
-SCSI_Out__2__DM1 EQU CYREG_PRT0_DM1
-SCSI_Out__2__DM2 EQU CYREG_PRT0_DM2
-SCSI_Out__2__DR EQU CYREG_PRT0_DR
-SCSI_Out__2__INP_DIS EQU CYREG_PRT0_INP_DIS
-SCSI_Out__2__INTTYPE EQU CYREG_PICU0_INTTYPE7
-SCSI_Out__2__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
-SCSI_Out__2__LCD_EN EQU CYREG_PRT0_LCD_EN
-SCSI_Out__2__MASK EQU 0x80
-SCSI_Out__2__PC EQU CYREG_PRT0_PC7
-SCSI_Out__2__PORT EQU 0
-SCSI_Out__2__PRT EQU CYREG_PRT0_PRT
-SCSI_Out__2__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
-SCSI_Out__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
-SCSI_Out__2__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
-SCSI_Out__2__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
-SCSI_Out__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
-SCSI_Out__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
-SCSI_Out__2__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
-SCSI_Out__2__PS EQU CYREG_PRT0_PS
-SCSI_Out__2__SHIFT EQU 7
-SCSI_Out__2__SLW EQU CYREG_PRT0_SLW
-SCSI_Out__3__AG EQU CYREG_PRT0_AG
-SCSI_Out__3__AMUX EQU CYREG_PRT0_AMUX
-SCSI_Out__3__BIE EQU CYREG_PRT0_BIE
-SCSI_Out__3__BIT_MASK EQU CYREG_PRT0_BIT_MASK
-SCSI_Out__3__BYP EQU CYREG_PRT0_BYP
-SCSI_Out__3__CTL EQU CYREG_PRT0_CTL
-SCSI_Out__3__DM0 EQU CYREG_PRT0_DM0
-SCSI_Out__3__DM1 EQU CYREG_PRT0_DM1
-SCSI_Out__3__DM2 EQU CYREG_PRT0_DM2
-SCSI_Out__3__DR EQU CYREG_PRT0_DR
-SCSI_Out__3__INP_DIS EQU CYREG_PRT0_INP_DIS
-SCSI_Out__3__INTTYPE EQU CYREG_PICU0_INTTYPE5
-SCSI_Out__3__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
-SCSI_Out__3__LCD_EN EQU CYREG_PRT0_LCD_EN
-SCSI_Out__3__MASK EQU 0x20
-SCSI_Out__3__PC EQU CYREG_PRT0_PC5
-SCSI_Out__3__PORT EQU 0
-SCSI_Out__3__PRT EQU CYREG_PRT0_PRT
-SCSI_Out__3__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
-SCSI_Out__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
-SCSI_Out__3__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
-SCSI_Out__3__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
-SCSI_Out__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
-SCSI_Out__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
-SCSI_Out__3__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
-SCSI_Out__3__PS EQU CYREG_PRT0_PS
-SCSI_Out__3__SHIFT EQU 5
-SCSI_Out__3__SLW EQU CYREG_PRT0_SLW
-SCSI_Out__4__AG EQU CYREG_PRT0_AG
-SCSI_Out__4__AMUX EQU CYREG_PRT0_AMUX
-SCSI_Out__4__BIE EQU CYREG_PRT0_BIE
-SCSI_Out__4__BIT_MASK EQU CYREG_PRT0_BIT_MASK
-SCSI_Out__4__BYP EQU CYREG_PRT0_BYP
-SCSI_Out__4__CTL EQU CYREG_PRT0_CTL
-SCSI_Out__4__DM0 EQU CYREG_PRT0_DM0
-SCSI_Out__4__DM1 EQU CYREG_PRT0_DM1
-SCSI_Out__4__DM2 EQU CYREG_PRT0_DM2
-SCSI_Out__4__DR EQU CYREG_PRT0_DR
-SCSI_Out__4__INP_DIS EQU CYREG_PRT0_INP_DIS
-SCSI_Out__4__INTTYPE EQU CYREG_PICU0_INTTYPE3
-SCSI_Out__4__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
-SCSI_Out__4__LCD_EN EQU CYREG_PRT0_LCD_EN
-SCSI_Out__4__MASK EQU 0x08
-SCSI_Out__4__PC EQU CYREG_PRT0_PC3
-SCSI_Out__4__PORT EQU 0
-SCSI_Out__4__PRT EQU CYREG_PRT0_PRT
-SCSI_Out__4__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
-SCSI_Out__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
-SCSI_Out__4__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
-SCSI_Out__4__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
-SCSI_Out__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
-SCSI_Out__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
-SCSI_Out__4__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
-SCSI_Out__4__PS EQU CYREG_PRT0_PS
-SCSI_Out__4__SHIFT EQU 3
-SCSI_Out__4__SLW EQU CYREG_PRT0_SLW
-SCSI_Out__5__AG EQU CYREG_PRT0_AG
-SCSI_Out__5__AMUX EQU CYREG_PRT0_AMUX
-SCSI_Out__5__BIE EQU CYREG_PRT0_BIE
-SCSI_Out__5__BIT_MASK EQU CYREG_PRT0_BIT_MASK
-SCSI_Out__5__BYP EQU CYREG_PRT0_BYP
-SCSI_Out__5__CTL EQU CYREG_PRT0_CTL
-SCSI_Out__5__DM0 EQU CYREG_PRT0_DM0
-SCSI_Out__5__DM1 EQU CYREG_PRT0_DM1
-SCSI_Out__5__DM2 EQU CYREG_PRT0_DM2
-SCSI_Out__5__DR EQU CYREG_PRT0_DR
-SCSI_Out__5__INP_DIS EQU CYREG_PRT0_INP_DIS
-SCSI_Out__5__INTTYPE EQU CYREG_PICU0_INTTYPE1
-SCSI_Out__5__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
-SCSI_Out__5__LCD_EN EQU CYREG_PRT0_LCD_EN
-SCSI_Out__5__MASK EQU 0x02
-SCSI_Out__5__PC EQU CYREG_PRT0_PC1
-SCSI_Out__5__PORT EQU 0
-SCSI_Out__5__PRT EQU CYREG_PRT0_PRT
-SCSI_Out__5__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
-SCSI_Out__5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
-SCSI_Out__5__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
-SCSI_Out__5__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
-SCSI_Out__5__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
-SCSI_Out__5__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
-SCSI_Out__5__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
-SCSI_Out__5__PS EQU CYREG_PRT0_PS
-SCSI_Out__5__SHIFT EQU 1
-SCSI_Out__5__SLW EQU CYREG_PRT0_SLW
-SCSI_Out__6__AG EQU CYREG_PRT4_AG
-SCSI_Out__6__AMUX EQU CYREG_PRT4_AMUX
-SCSI_Out__6__BIE EQU CYREG_PRT4_BIE
-SCSI_Out__6__BIT_MASK EQU CYREG_PRT4_BIT_MASK
-SCSI_Out__6__BYP EQU CYREG_PRT4_BYP
-SCSI_Out__6__CTL EQU CYREG_PRT4_CTL
-SCSI_Out__6__DM0 EQU CYREG_PRT4_DM0
-SCSI_Out__6__DM1 EQU CYREG_PRT4_DM1
-SCSI_Out__6__DM2 EQU CYREG_PRT4_DM2
-SCSI_Out__6__DR EQU CYREG_PRT4_DR
-SCSI_Out__6__INP_DIS EQU CYREG_PRT4_INP_DIS
-SCSI_Out__6__INTTYPE EQU CYREG_PICU4_INTTYPE1
-SCSI_Out__6__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
-SCSI_Out__6__LCD_EN EQU CYREG_PRT4_LCD_EN
-SCSI_Out__6__MASK EQU 0x02
-SCSI_Out__6__PC EQU CYREG_PRT4_PC1
-SCSI_Out__6__PORT EQU 4
-SCSI_Out__6__PRT EQU CYREG_PRT4_PRT
-SCSI_Out__6__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
-SCSI_Out__6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
-SCSI_Out__6__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
-SCSI_Out__6__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
-SCSI_Out__6__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
-SCSI_Out__6__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
-SCSI_Out__6__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
-SCSI_Out__6__PS EQU CYREG_PRT4_PS
-SCSI_Out__6__SHIFT EQU 1
-SCSI_Out__6__SLW EQU CYREG_PRT4_SLW
-SCSI_Out__7__AG EQU CYREG_PRT12_AG
-SCSI_Out__7__BIE EQU CYREG_PRT12_BIE
-SCSI_Out__7__BIT_MASK EQU CYREG_PRT12_BIT_MASK
-SCSI_Out__7__BYP EQU CYREG_PRT12_BYP
-SCSI_Out__7__DM0 EQU CYREG_PRT12_DM0
-SCSI_Out__7__DM1 EQU CYREG_PRT12_DM1
-SCSI_Out__7__DM2 EQU CYREG_PRT12_DM2
-SCSI_Out__7__DR EQU CYREG_PRT12_DR
-SCSI_Out__7__INP_DIS EQU CYREG_PRT12_INP_DIS
-SCSI_Out__7__INTTYPE EQU CYREG_PICU12_INTTYPE3
-SCSI_Out__7__MASK EQU 0x08
-SCSI_Out__7__PC EQU CYREG_PRT12_PC3
-SCSI_Out__7__PORT EQU 12
-SCSI_Out__7__PRT EQU CYREG_PRT12_PRT
-SCSI_Out__7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN
-SCSI_Out__7__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0
-SCSI_Out__7__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1
-SCSI_Out__7__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0
-SCSI_Out__7__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1
-SCSI_Out__7__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT
-SCSI_Out__7__PS EQU CYREG_PRT12_PS
-SCSI_Out__7__SHIFT EQU 3
-SCSI_Out__7__SIO_CFG EQU CYREG_PRT12_SIO_CFG
-SCSI_Out__7__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF
-SCSI_Out__7__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN
-SCSI_Out__7__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ
-SCSI_Out__7__SLW EQU CYREG_PRT12_SLW
-SCSI_Out__BSY__AG EQU CYREG_PRT4_AG
-SCSI_Out__BSY__AMUX EQU CYREG_PRT4_AMUX
-SCSI_Out__BSY__BIE EQU CYREG_PRT4_BIE
-SCSI_Out__BSY__BIT_MASK EQU CYREG_PRT4_BIT_MASK
-SCSI_Out__BSY__BYP EQU CYREG_PRT4_BYP
-SCSI_Out__BSY__CTL EQU CYREG_PRT4_CTL
-SCSI_Out__BSY__DM0 EQU CYREG_PRT4_DM0
-SCSI_Out__BSY__DM1 EQU CYREG_PRT4_DM1
-SCSI_Out__BSY__DM2 EQU CYREG_PRT4_DM2
-SCSI_Out__BSY__DR EQU CYREG_PRT4_DR
-SCSI_Out__BSY__INP_DIS EQU CYREG_PRT4_INP_DIS
-SCSI_Out__BSY__INTTYPE EQU CYREG_PICU4_INTTYPE6
-SCSI_Out__BSY__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
-SCSI_Out__BSY__LCD_EN EQU CYREG_PRT4_LCD_EN
-SCSI_Out__BSY__MASK EQU 0x40
-SCSI_Out__BSY__PC EQU CYREG_PRT4_PC6
-SCSI_Out__BSY__PORT EQU 4
-SCSI_Out__BSY__PRT EQU CYREG_PRT4_PRT
-SCSI_Out__BSY__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
-SCSI_Out__BSY__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
-SCSI_Out__BSY__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
-SCSI_Out__BSY__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
-SCSI_Out__BSY__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
-SCSI_Out__BSY__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
-SCSI_Out__BSY__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
-SCSI_Out__BSY__PS EQU CYREG_PRT4_PS
-SCSI_Out__BSY__SHIFT EQU 6
-SCSI_Out__BSY__SLW EQU CYREG_PRT4_SLW
-SCSI_Out__CD_raw__AG EQU CYREG_PRT0_AG
-SCSI_Out__CD_raw__AMUX EQU CYREG_PRT0_AMUX
-SCSI_Out__CD_raw__BIE EQU CYREG_PRT0_BIE
-SCSI_Out__CD_raw__BIT_MASK EQU CYREG_PRT0_BIT_MASK
-SCSI_Out__CD_raw__BYP EQU CYREG_PRT0_BYP
-SCSI_Out__CD_raw__CTL EQU CYREG_PRT0_CTL
-SCSI_Out__CD_raw__DM0 EQU CYREG_PRT0_DM0
-SCSI_Out__CD_raw__DM1 EQU CYREG_PRT0_DM1
-SCSI_Out__CD_raw__DM2 EQU CYREG_PRT0_DM2
-SCSI_Out__CD_raw__DR EQU CYREG_PRT0_DR
-SCSI_Out__CD_raw__INP_DIS EQU CYREG_PRT0_INP_DIS
-SCSI_Out__CD_raw__INTTYPE EQU CYREG_PICU0_INTTYPE1
-SCSI_Out__CD_raw__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
-SCSI_Out__CD_raw__LCD_EN EQU CYREG_PRT0_LCD_EN
-SCSI_Out__CD_raw__MASK EQU 0x02
-SCSI_Out__CD_raw__PC EQU CYREG_PRT0_PC1
-SCSI_Out__CD_raw__PORT EQU 0
-SCSI_Out__CD_raw__PRT EQU CYREG_PRT0_PRT
-SCSI_Out__CD_raw__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
-SCSI_Out__CD_raw__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
-SCSI_Out__CD_raw__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
-SCSI_Out__CD_raw__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
-SCSI_Out__CD_raw__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
-SCSI_Out__CD_raw__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
-SCSI_Out__CD_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
-SCSI_Out__CD_raw__PS EQU CYREG_PRT0_PS
-SCSI_Out__CD_raw__SHIFT EQU 1
-SCSI_Out__CD_raw__SLW EQU CYREG_PRT0_SLW
-SCSI_Out__DBP_raw__AG EQU CYREG_PRT6_AG
-SCSI_Out__DBP_raw__AMUX EQU CYREG_PRT6_AMUX
-SCSI_Out__DBP_raw__BIE EQU CYREG_PRT6_BIE
-SCSI_Out__DBP_raw__BIT_MASK EQU CYREG_PRT6_BIT_MASK
-SCSI_Out__DBP_raw__BYP EQU CYREG_PRT6_BYP
-SCSI_Out__DBP_raw__CTL EQU CYREG_PRT6_CTL
-SCSI_Out__DBP_raw__DM0 EQU CYREG_PRT6_DM0
-SCSI_Out__DBP_raw__DM1 EQU CYREG_PRT6_DM1
-SCSI_Out__DBP_raw__DM2 EQU CYREG_PRT6_DM2
-SCSI_Out__DBP_raw__DR EQU CYREG_PRT6_DR
-SCSI_Out__DBP_raw__INP_DIS EQU CYREG_PRT6_INP_DIS
-SCSI_Out__DBP_raw__INTTYPE EQU CYREG_PICU6_INTTYPE2
-SCSI_Out__DBP_raw__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
-SCSI_Out__DBP_raw__LCD_EN EQU CYREG_PRT6_LCD_EN
-SCSI_Out__DBP_raw__MASK EQU 0x04
-SCSI_Out__DBP_raw__PC EQU CYREG_PRT6_PC2
-SCSI_Out__DBP_raw__PORT EQU 6
-SCSI_Out__DBP_raw__PRT EQU CYREG_PRT6_PRT
-SCSI_Out__DBP_raw__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
-SCSI_Out__DBP_raw__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
-SCSI_Out__DBP_raw__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
-SCSI_Out__DBP_raw__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
-SCSI_Out__DBP_raw__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
-SCSI_Out__DBP_raw__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
-SCSI_Out__DBP_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
-SCSI_Out__DBP_raw__PS EQU CYREG_PRT6_PS
-SCSI_Out__DBP_raw__SHIFT EQU 2
-SCSI_Out__DBP_raw__SLW EQU CYREG_PRT6_SLW
-SCSI_Out__IO_raw__AG EQU CYREG_PRT12_AG
-SCSI_Out__IO_raw__BIE EQU CYREG_PRT12_BIE
-SCSI_Out__IO_raw__BIT_MASK EQU CYREG_PRT12_BIT_MASK
-SCSI_Out__IO_raw__BYP EQU CYREG_PRT12_BYP
-SCSI_Out__IO_raw__DM0 EQU CYREG_PRT12_DM0
-SCSI_Out__IO_raw__DM1 EQU CYREG_PRT12_DM1
-SCSI_Out__IO_raw__DM2 EQU CYREG_PRT12_DM2
-SCSI_Out__IO_raw__DR EQU CYREG_PRT12_DR
-SCSI_Out__IO_raw__INP_DIS EQU CYREG_PRT12_INP_DIS
-SCSI_Out__IO_raw__INTTYPE EQU CYREG_PICU12_INTTYPE3
-SCSI_Out__IO_raw__MASK EQU 0x08
-SCSI_Out__IO_raw__PC EQU CYREG_PRT12_PC3
-SCSI_Out__IO_raw__PORT EQU 12
-SCSI_Out__IO_raw__PRT EQU CYREG_PRT12_PRT
-SCSI_Out__IO_raw__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN
-SCSI_Out__IO_raw__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0
-SCSI_Out__IO_raw__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1
-SCSI_Out__IO_raw__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0
-SCSI_Out__IO_raw__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1
-SCSI_Out__IO_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT
-SCSI_Out__IO_raw__PS EQU CYREG_PRT12_PS
-SCSI_Out__IO_raw__SHIFT EQU 3
-SCSI_Out__IO_raw__SIO_CFG EQU CYREG_PRT12_SIO_CFG
-SCSI_Out__IO_raw__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF
-SCSI_Out__IO_raw__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN
-SCSI_Out__IO_raw__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ
-SCSI_Out__IO_raw__SLW EQU CYREG_PRT12_SLW
-SCSI_Out__MSG_raw__AG EQU CYREG_PRT0_AG
-SCSI_Out__MSG_raw__AMUX EQU CYREG_PRT0_AMUX
-SCSI_Out__MSG_raw__BIE EQU CYREG_PRT0_BIE
-SCSI_Out__MSG_raw__BIT_MASK EQU CYREG_PRT0_BIT_MASK
-SCSI_Out__MSG_raw__BYP EQU CYREG_PRT0_BYP
-SCSI_Out__MSG_raw__CTL EQU CYREG_PRT0_CTL
-SCSI_Out__MSG_raw__DM0 EQU CYREG_PRT0_DM0
-SCSI_Out__MSG_raw__DM1 EQU CYREG_PRT0_DM1
-SCSI_Out__MSG_raw__DM2 EQU CYREG_PRT0_DM2
-SCSI_Out__MSG_raw__DR EQU CYREG_PRT0_DR
-SCSI_Out__MSG_raw__INP_DIS EQU CYREG_PRT0_INP_DIS
-SCSI_Out__MSG_raw__INTTYPE EQU CYREG_PICU0_INTTYPE5
-SCSI_Out__MSG_raw__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
-SCSI_Out__MSG_raw__LCD_EN EQU CYREG_PRT0_LCD_EN
-SCSI_Out__MSG_raw__MASK EQU 0x20
-SCSI_Out__MSG_raw__PC EQU CYREG_PRT0_PC5
-SCSI_Out__MSG_raw__PORT EQU 0
-SCSI_Out__MSG_raw__PRT EQU CYREG_PRT0_PRT
-SCSI_Out__MSG_raw__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
-SCSI_Out__MSG_raw__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
-SCSI_Out__MSG_raw__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
-SCSI_Out__MSG_raw__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
-SCSI_Out__MSG_raw__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
-SCSI_Out__MSG_raw__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
-SCSI_Out__MSG_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
-SCSI_Out__MSG_raw__PS EQU CYREG_PRT0_PS
-SCSI_Out__MSG_raw__SHIFT EQU 5
-SCSI_Out__MSG_raw__SLW EQU CYREG_PRT0_SLW
-SCSI_Out__REQ__AG EQU CYREG_PRT4_AG
-SCSI_Out__REQ__AMUX EQU CYREG_PRT4_AMUX
-SCSI_Out__REQ__BIE EQU CYREG_PRT4_BIE
-SCSI_Out__REQ__BIT_MASK EQU CYREG_PRT4_BIT_MASK
-SCSI_Out__REQ__BYP EQU CYREG_PRT4_BYP
-SCSI_Out__REQ__CTL EQU CYREG_PRT4_CTL
-SCSI_Out__REQ__DM0 EQU CYREG_PRT4_DM0
-SCSI_Out__REQ__DM1 EQU CYREG_PRT4_DM1
-SCSI_Out__REQ__DM2 EQU CYREG_PRT4_DM2
-SCSI_Out__REQ__DR EQU CYREG_PRT4_DR
-SCSI_Out__REQ__INP_DIS EQU CYREG_PRT4_INP_DIS
-SCSI_Out__REQ__INTTYPE EQU CYREG_PICU4_INTTYPE1
-SCSI_Out__REQ__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
-SCSI_Out__REQ__LCD_EN EQU CYREG_PRT4_LCD_EN
-SCSI_Out__REQ__MASK EQU 0x02
-SCSI_Out__REQ__PC EQU CYREG_PRT4_PC1
-SCSI_Out__REQ__PORT EQU 4
-SCSI_Out__REQ__PRT EQU CYREG_PRT4_PRT
-SCSI_Out__REQ__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
-SCSI_Out__REQ__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
-SCSI_Out__REQ__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
-SCSI_Out__REQ__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
-SCSI_Out__REQ__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
-SCSI_Out__REQ__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
-SCSI_Out__REQ__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
-SCSI_Out__REQ__PS EQU CYREG_PRT4_PS
-SCSI_Out__REQ__SHIFT EQU 1
-SCSI_Out__REQ__SLW EQU CYREG_PRT4_SLW
-SCSI_Out__RST__AG EQU CYREG_PRT0_AG
-SCSI_Out__RST__AMUX EQU CYREG_PRT0_AMUX
-SCSI_Out__RST__BIE EQU CYREG_PRT0_BIE
-SCSI_Out__RST__BIT_MASK EQU CYREG_PRT0_BIT_MASK
-SCSI_Out__RST__BYP EQU CYREG_PRT0_BYP
-SCSI_Out__RST__CTL EQU CYREG_PRT0_CTL
-SCSI_Out__RST__DM0 EQU CYREG_PRT0_DM0
-SCSI_Out__RST__DM1 EQU CYREG_PRT0_DM1
-SCSI_Out__RST__DM2 EQU CYREG_PRT0_DM2
-SCSI_Out__RST__DR EQU CYREG_PRT0_DR
-SCSI_Out__RST__INP_DIS EQU CYREG_PRT0_INP_DIS
-SCSI_Out__RST__INTTYPE EQU CYREG_PICU0_INTTYPE7
-SCSI_Out__RST__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
-SCSI_Out__RST__LCD_EN EQU CYREG_PRT0_LCD_EN
-SCSI_Out__RST__MASK EQU 0x80
-SCSI_Out__RST__PC EQU CYREG_PRT0_PC7
-SCSI_Out__RST__PORT EQU 0
-SCSI_Out__RST__PRT EQU CYREG_PRT0_PRT
-SCSI_Out__RST__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
-SCSI_Out__RST__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
-SCSI_Out__RST__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
-SCSI_Out__RST__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
-SCSI_Out__RST__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
-SCSI_Out__RST__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
-SCSI_Out__RST__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
-SCSI_Out__RST__PS EQU CYREG_PRT0_PS
-SCSI_Out__RST__SHIFT EQU 7
-SCSI_Out__RST__SLW EQU CYREG_PRT0_SLW
-SCSI_Out__SEL__AG EQU CYREG_PRT0_AG
-SCSI_Out__SEL__AMUX EQU CYREG_PRT0_AMUX
-SCSI_Out__SEL__BIE EQU CYREG_PRT0_BIE
-SCSI_Out__SEL__BIT_MASK EQU CYREG_PRT0_BIT_MASK
-SCSI_Out__SEL__BYP EQU CYREG_PRT0_BYP
-SCSI_Out__SEL__CTL EQU CYREG_PRT0_CTL
-SCSI_Out__SEL__DM0 EQU CYREG_PRT0_DM0
-SCSI_Out__SEL__DM1 EQU CYREG_PRT0_DM1
-SCSI_Out__SEL__DM2 EQU CYREG_PRT0_DM2
-SCSI_Out__SEL__DR EQU CYREG_PRT0_DR
-SCSI_Out__SEL__INP_DIS EQU CYREG_PRT0_INP_DIS
-SCSI_Out__SEL__INTTYPE EQU CYREG_PICU0_INTTYPE3
-SCSI_Out__SEL__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
-SCSI_Out__SEL__LCD_EN EQU CYREG_PRT0_LCD_EN
-SCSI_Out__SEL__MASK EQU 0x08
-SCSI_Out__SEL__PC EQU CYREG_PRT0_PC3
-SCSI_Out__SEL__PORT EQU 0
-SCSI_Out__SEL__PRT EQU CYREG_PRT0_PRT
-SCSI_Out__SEL__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
-SCSI_Out__SEL__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
-SCSI_Out__SEL__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
-SCSI_Out__SEL__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
-SCSI_Out__SEL__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
-SCSI_Out__SEL__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
-SCSI_Out__SEL__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
-SCSI_Out__SEL__PS EQU CYREG_PRT0_PS
-SCSI_Out__SEL__SHIFT EQU 3
-SCSI_Out__SEL__SLW EQU CYREG_PRT0_SLW
-
-/* SCSI_Out_Bits */
-SCSI_Out_Bits_Sync_ctrl_reg__0__MASK EQU 0x01
-SCSI_Out_Bits_Sync_ctrl_reg__0__POS EQU 0
-SCSI_Out_Bits_Sync_ctrl_reg__1__MASK EQU 0x02
-SCSI_Out_Bits_Sync_ctrl_reg__1__POS EQU 1
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB07_08_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB07_08_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB07_08_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB07_08_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB07_08_MSK
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB07_08_MSK
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB07_08_MSK
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB07_08_MSK
-SCSI_Out_Bits_Sync_ctrl_reg__2__MASK EQU 0x04
-SCSI_Out_Bits_Sync_ctrl_reg__2__POS EQU 2
-SCSI_Out_Bits_Sync_ctrl_reg__3__MASK EQU 0x08
-SCSI_Out_Bits_Sync_ctrl_reg__3__POS EQU 3
-SCSI_Out_Bits_Sync_ctrl_reg__4__MASK EQU 0x10
-SCSI_Out_Bits_Sync_ctrl_reg__4__POS EQU 4
-SCSI_Out_Bits_Sync_ctrl_reg__5__MASK EQU 0x20
-SCSI_Out_Bits_Sync_ctrl_reg__5__POS EQU 5
-SCSI_Out_Bits_Sync_ctrl_reg__6__MASK EQU 0x40
-SCSI_Out_Bits_Sync_ctrl_reg__6__POS EQU 6
-SCSI_Out_Bits_Sync_ctrl_reg__7__MASK EQU 0x80
-SCSI_Out_Bits_Sync_ctrl_reg__7__POS EQU 7
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB07_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB07_ST_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB07_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB07_ST_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__MASK EQU 0xFF
-SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL
-SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL
-SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB07_MSK
-
-/* SCSI_Out_Ctl */
-SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01
-SCSI_Out_Ctl_Sync_ctrl_reg__0__POS EQU 0
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB11_12_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB11_12_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB11_12_MSK
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB11_12_MSK
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB11_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB11_ST_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB11_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB11_ST_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__MASK EQU 0x01
-SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
-SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
-SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB11_MSK
-
-/* SCSI_Out_DBx */
-SCSI_Out_DBx__0__AG EQU CYREG_PRT6_AG
-SCSI_Out_DBx__0__AMUX EQU CYREG_PRT6_AMUX
-SCSI_Out_DBx__0__BIE EQU CYREG_PRT6_BIE
-SCSI_Out_DBx__0__BIT_MASK EQU CYREG_PRT6_BIT_MASK
-SCSI_Out_DBx__0__BYP EQU CYREG_PRT6_BYP
-SCSI_Out_DBx__0__CTL EQU CYREG_PRT6_CTL
-SCSI_Out_DBx__0__DM0 EQU CYREG_PRT6_DM0
-SCSI_Out_DBx__0__DM1 EQU CYREG_PRT6_DM1
-SCSI_Out_DBx__0__DM2 EQU CYREG_PRT6_DM2
-SCSI_Out_DBx__0__DR EQU CYREG_PRT6_DR
-SCSI_Out_DBx__0__INP_DIS EQU CYREG_PRT6_INP_DIS
-SCSI_Out_DBx__0__INTTYPE EQU CYREG_PICU6_INTTYPE7
-SCSI_Out_DBx__0__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
-SCSI_Out_DBx__0__LCD_EN EQU CYREG_PRT6_LCD_EN
-SCSI_Out_DBx__0__MASK EQU 0x80
-SCSI_Out_DBx__0__PC EQU CYREG_PRT6_PC7
-SCSI_Out_DBx__0__PORT EQU 6
-SCSI_Out_DBx__0__PRT EQU CYREG_PRT6_PRT
-SCSI_Out_DBx__0__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
-SCSI_Out_DBx__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
-SCSI_Out_DBx__0__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
-SCSI_Out_DBx__0__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
-SCSI_Out_DBx__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
-SCSI_Out_DBx__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
-SCSI_Out_DBx__0__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
-SCSI_Out_DBx__0__PS EQU CYREG_PRT6_PS
-SCSI_Out_DBx__0__SHIFT EQU 7
-SCSI_Out_DBx__0__SLW EQU CYREG_PRT6_SLW
-SCSI_Out_DBx__1__AG EQU CYREG_PRT6_AG
-SCSI_Out_DBx__1__AMUX EQU CYREG_PRT6_AMUX
-SCSI_Out_DBx__1__BIE EQU CYREG_PRT6_BIE
-SCSI_Out_DBx__1__BIT_MASK EQU CYREG_PRT6_BIT_MASK
-SCSI_Out_DBx__1__BYP EQU CYREG_PRT6_BYP
-SCSI_Out_DBx__1__CTL EQU CYREG_PRT6_CTL
-SCSI_Out_DBx__1__DM0 EQU CYREG_PRT6_DM0
-SCSI_Out_DBx__1__DM1 EQU CYREG_PRT6_DM1
-SCSI_Out_DBx__1__DM2 EQU CYREG_PRT6_DM2
-SCSI_Out_DBx__1__DR EQU CYREG_PRT6_DR
-SCSI_Out_DBx__1__INP_DIS EQU CYREG_PRT6_INP_DIS
-SCSI_Out_DBx__1__INTTYPE EQU CYREG_PICU6_INTTYPE5
-SCSI_Out_DBx__1__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
-SCSI_Out_DBx__1__LCD_EN EQU CYREG_PRT6_LCD_EN
-SCSI_Out_DBx__1__MASK EQU 0x20
-SCSI_Out_DBx__1__PC EQU CYREG_PRT6_PC5
-SCSI_Out_DBx__1__PORT EQU 6
-SCSI_Out_DBx__1__PRT EQU CYREG_PRT6_PRT
-SCSI_Out_DBx__1__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
-SCSI_Out_DBx__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
-SCSI_Out_DBx__1__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
-SCSI_Out_DBx__1__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
-SCSI_Out_DBx__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
-SCSI_Out_DBx__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
-SCSI_Out_DBx__1__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
-SCSI_Out_DBx__1__PS EQU CYREG_PRT6_PS
-SCSI_Out_DBx__1__SHIFT EQU 5
-SCSI_Out_DBx__1__SLW EQU CYREG_PRT6_SLW
-SCSI_Out_DBx__2__AG EQU CYREG_PRT12_AG
-SCSI_Out_DBx__2__BIE EQU CYREG_PRT12_BIE
-SCSI_Out_DBx__2__BIT_MASK EQU CYREG_PRT12_BIT_MASK
-SCSI_Out_DBx__2__BYP EQU CYREG_PRT12_BYP
-SCSI_Out_DBx__2__DM0 EQU CYREG_PRT12_DM0
-SCSI_Out_DBx__2__DM1 EQU CYREG_PRT12_DM1
-SCSI_Out_DBx__2__DM2 EQU CYREG_PRT12_DM2
-SCSI_Out_DBx__2__DR EQU CYREG_PRT12_DR
-SCSI_Out_DBx__2__INP_DIS EQU CYREG_PRT12_INP_DIS
-SCSI_Out_DBx__2__INTTYPE EQU CYREG_PICU12_INTTYPE5
-SCSI_Out_DBx__2__MASK EQU 0x20
-SCSI_Out_DBx__2__PC EQU CYREG_PRT12_PC5
-SCSI_Out_DBx__2__PORT EQU 12
-SCSI_Out_DBx__2__PRT EQU CYREG_PRT12_PRT
-SCSI_Out_DBx__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN
-SCSI_Out_DBx__2__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0
-SCSI_Out_DBx__2__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1
-SCSI_Out_DBx__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0
-SCSI_Out_DBx__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1
-SCSI_Out_DBx__2__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT
-SCSI_Out_DBx__2__PS EQU CYREG_PRT12_PS
-SCSI_Out_DBx__2__SHIFT EQU 5
-SCSI_Out_DBx__2__SIO_CFG EQU CYREG_PRT12_SIO_CFG
-SCSI_Out_DBx__2__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF
-SCSI_Out_DBx__2__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN
-SCSI_Out_DBx__2__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ
-SCSI_Out_DBx__2__SLW EQU CYREG_PRT12_SLW
-SCSI_Out_DBx__3__AG EQU CYREG_PRT2_AG
-SCSI_Out_DBx__3__AMUX EQU CYREG_PRT2_AMUX
-SCSI_Out_DBx__3__BIE EQU CYREG_PRT2_BIE
-SCSI_Out_DBx__3__BIT_MASK EQU CYREG_PRT2_BIT_MASK
-SCSI_Out_DBx__3__BYP EQU CYREG_PRT2_BYP
-SCSI_Out_DBx__3__CTL EQU CYREG_PRT2_CTL
-SCSI_Out_DBx__3__DM0 EQU CYREG_PRT2_DM0
-SCSI_Out_DBx__3__DM1 EQU CYREG_PRT2_DM1
-SCSI_Out_DBx__3__DM2 EQU CYREG_PRT2_DM2
-SCSI_Out_DBx__3__DR EQU CYREG_PRT2_DR
-SCSI_Out_DBx__3__INP_DIS EQU CYREG_PRT2_INP_DIS
-SCSI_Out_DBx__3__INTTYPE EQU CYREG_PICU2_INTTYPE7
-SCSI_Out_DBx__3__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
-SCSI_Out_DBx__3__LCD_EN EQU CYREG_PRT2_LCD_EN
-SCSI_Out_DBx__3__MASK EQU 0x80
-SCSI_Out_DBx__3__PC EQU CYREG_PRT2_PC7
-SCSI_Out_DBx__3__PORT EQU 2
-SCSI_Out_DBx__3__PRT EQU CYREG_PRT2_PRT
-SCSI_Out_DBx__3__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
-SCSI_Out_DBx__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
-SCSI_Out_DBx__3__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
-SCSI_Out_DBx__3__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
-SCSI_Out_DBx__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
-SCSI_Out_DBx__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
-SCSI_Out_DBx__3__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
-SCSI_Out_DBx__3__PS EQU CYREG_PRT2_PS
-SCSI_Out_DBx__3__SHIFT EQU 7
-SCSI_Out_DBx__3__SLW EQU CYREG_PRT2_SLW
-SCSI_Out_DBx__4__AG EQU CYREG_PRT2_AG
-SCSI_Out_DBx__4__AMUX EQU CYREG_PRT2_AMUX
-SCSI_Out_DBx__4__BIE EQU CYREG_PRT2_BIE
-SCSI_Out_DBx__4__BIT_MASK EQU CYREG_PRT2_BIT_MASK
-SCSI_Out_DBx__4__BYP EQU CYREG_PRT2_BYP
-SCSI_Out_DBx__4__CTL EQU CYREG_PRT2_CTL
-SCSI_Out_DBx__4__DM0 EQU CYREG_PRT2_DM0
-SCSI_Out_DBx__4__DM1 EQU CYREG_PRT2_DM1
-SCSI_Out_DBx__4__DM2 EQU CYREG_PRT2_DM2
-SCSI_Out_DBx__4__DR EQU CYREG_PRT2_DR
-SCSI_Out_DBx__4__INP_DIS EQU CYREG_PRT2_INP_DIS
-SCSI_Out_DBx__4__INTTYPE EQU CYREG_PICU2_INTTYPE5
-SCSI_Out_DBx__4__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
-SCSI_Out_DBx__4__LCD_EN EQU CYREG_PRT2_LCD_EN
-SCSI_Out_DBx__4__MASK EQU 0x20
-SCSI_Out_DBx__4__PC EQU CYREG_PRT2_PC5
-SCSI_Out_DBx__4__PORT EQU 2
-SCSI_Out_DBx__4__PRT EQU CYREG_PRT2_PRT
-SCSI_Out_DBx__4__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
-SCSI_Out_DBx__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
-SCSI_Out_DBx__4__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
-SCSI_Out_DBx__4__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
-SCSI_Out_DBx__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
-SCSI_Out_DBx__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
-SCSI_Out_DBx__4__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
-SCSI_Out_DBx__4__PS EQU CYREG_PRT2_PS
-SCSI_Out_DBx__4__SHIFT EQU 5
-SCSI_Out_DBx__4__SLW EQU CYREG_PRT2_SLW
-SCSI_Out_DBx__5__AG EQU CYREG_PRT2_AG
-SCSI_Out_DBx__5__AMUX EQU CYREG_PRT2_AMUX
-SCSI_Out_DBx__5__BIE EQU CYREG_PRT2_BIE
-SCSI_Out_DBx__5__BIT_MASK EQU CYREG_PRT2_BIT_MASK
-SCSI_Out_DBx__5__BYP EQU CYREG_PRT2_BYP
-SCSI_Out_DBx__5__CTL EQU CYREG_PRT2_CTL
-SCSI_Out_DBx__5__DM0 EQU CYREG_PRT2_DM0
-SCSI_Out_DBx__5__DM1 EQU CYREG_PRT2_DM1
-SCSI_Out_DBx__5__DM2 EQU CYREG_PRT2_DM2
-SCSI_Out_DBx__5__DR EQU CYREG_PRT2_DR
-SCSI_Out_DBx__5__INP_DIS EQU CYREG_PRT2_INP_DIS
-SCSI_Out_DBx__5__INTTYPE EQU CYREG_PICU2_INTTYPE3
-SCSI_Out_DBx__5__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
-SCSI_Out_DBx__5__LCD_EN EQU CYREG_PRT2_LCD_EN
-SCSI_Out_DBx__5__MASK EQU 0x08
-SCSI_Out_DBx__5__PC EQU CYREG_PRT2_PC3
-SCSI_Out_DBx__5__PORT EQU 2
-SCSI_Out_DBx__5__PRT EQU CYREG_PRT2_PRT
-SCSI_Out_DBx__5__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
-SCSI_Out_DBx__5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
-SCSI_Out_DBx__5__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
-SCSI_Out_DBx__5__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
-SCSI_Out_DBx__5__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
-SCSI_Out_DBx__5__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
-SCSI_Out_DBx__5__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
-SCSI_Out_DBx__5__PS EQU CYREG_PRT2_PS
-SCSI_Out_DBx__5__SHIFT EQU 3
-SCSI_Out_DBx__5__SLW EQU CYREG_PRT2_SLW
-SCSI_Out_DBx__6__AG EQU CYREG_PRT2_AG
-SCSI_Out_DBx__6__AMUX EQU CYREG_PRT2_AMUX
-SCSI_Out_DBx__6__BIE EQU CYREG_PRT2_BIE
-SCSI_Out_DBx__6__BIT_MASK EQU CYREG_PRT2_BIT_MASK
-SCSI_Out_DBx__6__BYP EQU CYREG_PRT2_BYP
-SCSI_Out_DBx__6__CTL EQU CYREG_PRT2_CTL
-SCSI_Out_DBx__6__DM0 EQU CYREG_PRT2_DM0
-SCSI_Out_DBx__6__DM1 EQU CYREG_PRT2_DM1
-SCSI_Out_DBx__6__DM2 EQU CYREG_PRT2_DM2
-SCSI_Out_DBx__6__DR EQU CYREG_PRT2_DR
-SCSI_Out_DBx__6__INP_DIS EQU CYREG_PRT2_INP_DIS
-SCSI_Out_DBx__6__INTTYPE EQU CYREG_PICU2_INTTYPE1
-SCSI_Out_DBx__6__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
-SCSI_Out_DBx__6__LCD_EN EQU CYREG_PRT2_LCD_EN
-SCSI_Out_DBx__6__MASK EQU 0x02
-SCSI_Out_DBx__6__PC EQU CYREG_PRT2_PC1
-SCSI_Out_DBx__6__PORT EQU 2
-SCSI_Out_DBx__6__PRT EQU CYREG_PRT2_PRT
-SCSI_Out_DBx__6__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
-SCSI_Out_DBx__6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
-SCSI_Out_DBx__6__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
-SCSI_Out_DBx__6__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
-SCSI_Out_DBx__6__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
-SCSI_Out_DBx__6__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
-SCSI_Out_DBx__6__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
-SCSI_Out_DBx__6__PS EQU CYREG_PRT2_PS
-SCSI_Out_DBx__6__SHIFT EQU 1
-SCSI_Out_DBx__6__SLW EQU CYREG_PRT2_SLW
-SCSI_Out_DBx__7__AG EQU CYREG_PRT15_AG
-SCSI_Out_DBx__7__AMUX EQU CYREG_PRT15_AMUX
-SCSI_Out_DBx__7__BIE EQU CYREG_PRT15_BIE
-SCSI_Out_DBx__7__BIT_MASK EQU CYREG_PRT15_BIT_MASK
-SCSI_Out_DBx__7__BYP EQU CYREG_PRT15_BYP
-SCSI_Out_DBx__7__CTL EQU CYREG_PRT15_CTL
-SCSI_Out_DBx__7__DM0 EQU CYREG_PRT15_DM0
-SCSI_Out_DBx__7__DM1 EQU CYREG_PRT15_DM1
-SCSI_Out_DBx__7__DM2 EQU CYREG_PRT15_DM2
-SCSI_Out_DBx__7__DR EQU CYREG_PRT15_DR
-SCSI_Out_DBx__7__INP_DIS EQU CYREG_PRT15_INP_DIS
-SCSI_Out_DBx__7__INTTYPE EQU CYREG_PICU15_INTTYPE5
-SCSI_Out_DBx__7__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG
-SCSI_Out_DBx__7__LCD_EN EQU CYREG_PRT15_LCD_EN
-SCSI_Out_DBx__7__MASK EQU 0x20
-SCSI_Out_DBx__7__PC EQU CYREG_IO_PC_PRT15_PC5
-SCSI_Out_DBx__7__PORT EQU 15
-SCSI_Out_DBx__7__PRT EQU CYREG_PRT15_PRT
-SCSI_Out_DBx__7__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL
-SCSI_Out_DBx__7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN
-SCSI_Out_DBx__7__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0
-SCSI_Out_DBx__7__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1
-SCSI_Out_DBx__7__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0
-SCSI_Out_DBx__7__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1
-SCSI_Out_DBx__7__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT
-SCSI_Out_DBx__7__PS EQU CYREG_PRT15_PS
-SCSI_Out_DBx__7__SHIFT EQU 5
-SCSI_Out_DBx__7__SLW EQU CYREG_PRT15_SLW
-SCSI_Out_DBx__DB0__AG EQU CYREG_PRT6_AG
-SCSI_Out_DBx__DB0__AMUX EQU CYREG_PRT6_AMUX
-SCSI_Out_DBx__DB0__BIE EQU CYREG_PRT6_BIE
-SCSI_Out_DBx__DB0__BIT_MASK EQU CYREG_PRT6_BIT_MASK
-SCSI_Out_DBx__DB0__BYP EQU CYREG_PRT6_BYP
-SCSI_Out_DBx__DB0__CTL EQU CYREG_PRT6_CTL
-SCSI_Out_DBx__DB0__DM0 EQU CYREG_PRT6_DM0
-SCSI_Out_DBx__DB0__DM1 EQU CYREG_PRT6_DM1
-SCSI_Out_DBx__DB0__DM2 EQU CYREG_PRT6_DM2
-SCSI_Out_DBx__DB0__DR EQU CYREG_PRT6_DR
-SCSI_Out_DBx__DB0__INP_DIS EQU CYREG_PRT6_INP_DIS
-SCSI_Out_DBx__DB0__INTTYPE EQU CYREG_PICU6_INTTYPE7
-SCSI_Out_DBx__DB0__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
-SCSI_Out_DBx__DB0__LCD_EN EQU CYREG_PRT6_LCD_EN
-SCSI_Out_DBx__DB0__MASK EQU 0x80
-SCSI_Out_DBx__DB0__PC EQU CYREG_PRT6_PC7
-SCSI_Out_DBx__DB0__PORT EQU 6
-SCSI_Out_DBx__DB0__PRT EQU CYREG_PRT6_PRT
-SCSI_Out_DBx__DB0__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
-SCSI_Out_DBx__DB0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
-SCSI_Out_DBx__DB0__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
-SCSI_Out_DBx__DB0__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
-SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
-SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
-SCSI_Out_DBx__DB0__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
-SCSI_Out_DBx__DB0__PS EQU CYREG_PRT6_PS
-SCSI_Out_DBx__DB0__SHIFT EQU 7
-SCSI_Out_DBx__DB0__SLW EQU CYREG_PRT6_SLW
-SCSI_Out_DBx__DB1__AG EQU CYREG_PRT6_AG
-SCSI_Out_DBx__DB1__AMUX EQU CYREG_PRT6_AMUX
-SCSI_Out_DBx__DB1__BIE EQU CYREG_PRT6_BIE
-SCSI_Out_DBx__DB1__BIT_MASK EQU CYREG_PRT6_BIT_MASK
-SCSI_Out_DBx__DB1__BYP EQU CYREG_PRT6_BYP
-SCSI_Out_DBx__DB1__CTL EQU CYREG_PRT6_CTL
-SCSI_Out_DBx__DB1__DM0 EQU CYREG_PRT6_DM0
-SCSI_Out_DBx__DB1__DM1 EQU CYREG_PRT6_DM1
-SCSI_Out_DBx__DB1__DM2 EQU CYREG_PRT6_DM2
-SCSI_Out_DBx__DB1__DR EQU CYREG_PRT6_DR
-SCSI_Out_DBx__DB1__INP_DIS EQU CYREG_PRT6_INP_DIS
-SCSI_Out_DBx__DB1__INTTYPE EQU CYREG_PICU6_INTTYPE5
-SCSI_Out_DBx__DB1__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
-SCSI_Out_DBx__DB1__LCD_EN EQU CYREG_PRT6_LCD_EN
-SCSI_Out_DBx__DB1__MASK EQU 0x20
-SCSI_Out_DBx__DB1__PC EQU CYREG_PRT6_PC5
-SCSI_Out_DBx__DB1__PORT EQU 6
-SCSI_Out_DBx__DB1__PRT EQU CYREG_PRT6_PRT
-SCSI_Out_DBx__DB1__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
-SCSI_Out_DBx__DB1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
-SCSI_Out_DBx__DB1__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
-SCSI_Out_DBx__DB1__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
-SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
-SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
-SCSI_Out_DBx__DB1__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
-SCSI_Out_DBx__DB1__PS EQU CYREG_PRT6_PS
-SCSI_Out_DBx__DB1__SHIFT EQU 5
-SCSI_Out_DBx__DB1__SLW EQU CYREG_PRT6_SLW
-SCSI_Out_DBx__DB2__AG EQU CYREG_PRT12_AG
-SCSI_Out_DBx__DB2__BIE EQU CYREG_PRT12_BIE
-SCSI_Out_DBx__DB2__BIT_MASK EQU CYREG_PRT12_BIT_MASK
-SCSI_Out_DBx__DB2__BYP EQU CYREG_PRT12_BYP
-SCSI_Out_DBx__DB2__DM0 EQU CYREG_PRT12_DM0
-SCSI_Out_DBx__DB2__DM1 EQU CYREG_PRT12_DM1
-SCSI_Out_DBx__DB2__DM2 EQU CYREG_PRT12_DM2
-SCSI_Out_DBx__DB2__DR EQU CYREG_PRT12_DR
-SCSI_Out_DBx__DB2__INP_DIS EQU CYREG_PRT12_INP_DIS
-SCSI_Out_DBx__DB2__INTTYPE EQU CYREG_PICU12_INTTYPE5
-SCSI_Out_DBx__DB2__MASK EQU 0x20
-SCSI_Out_DBx__DB2__PC EQU CYREG_PRT12_PC5
-SCSI_Out_DBx__DB2__PORT EQU 12
-SCSI_Out_DBx__DB2__PRT EQU CYREG_PRT12_PRT
-SCSI_Out_DBx__DB2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN
-SCSI_Out_DBx__DB2__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0
-SCSI_Out_DBx__DB2__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1
-SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0
-SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1
-SCSI_Out_DBx__DB2__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT
-SCSI_Out_DBx__DB2__PS EQU CYREG_PRT12_PS
-SCSI_Out_DBx__DB2__SHIFT EQU 5
-SCSI_Out_DBx__DB2__SIO_CFG EQU CYREG_PRT12_SIO_CFG
-SCSI_Out_DBx__DB2__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF
-SCSI_Out_DBx__DB2__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN
-SCSI_Out_DBx__DB2__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ
-SCSI_Out_DBx__DB2__SLW EQU CYREG_PRT12_SLW
-SCSI_Out_DBx__DB3__AG EQU CYREG_PRT2_AG
-SCSI_Out_DBx__DB3__AMUX EQU CYREG_PRT2_AMUX
-SCSI_Out_DBx__DB3__BIE EQU CYREG_PRT2_BIE
-SCSI_Out_DBx__DB3__BIT_MASK EQU CYREG_PRT2_BIT_MASK
-SCSI_Out_DBx__DB3__BYP EQU CYREG_PRT2_BYP
-SCSI_Out_DBx__DB3__CTL EQU CYREG_PRT2_CTL
-SCSI_Out_DBx__DB3__DM0 EQU CYREG_PRT2_DM0
-SCSI_Out_DBx__DB3__DM1 EQU CYREG_PRT2_DM1
-SCSI_Out_DBx__DB3__DM2 EQU CYREG_PRT2_DM2
-SCSI_Out_DBx__DB3__DR EQU CYREG_PRT2_DR
-SCSI_Out_DBx__DB3__INP_DIS EQU CYREG_PRT2_INP_DIS
-SCSI_Out_DBx__DB3__INTTYPE EQU CYREG_PICU2_INTTYPE7
-SCSI_Out_DBx__DB3__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
-SCSI_Out_DBx__DB3__LCD_EN EQU CYREG_PRT2_LCD_EN
-SCSI_Out_DBx__DB3__MASK EQU 0x80
-SCSI_Out_DBx__DB3__PC EQU CYREG_PRT2_PC7
-SCSI_Out_DBx__DB3__PORT EQU 2
-SCSI_Out_DBx__DB3__PRT EQU CYREG_PRT2_PRT
-SCSI_Out_DBx__DB3__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
-SCSI_Out_DBx__DB3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
-SCSI_Out_DBx__DB3__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
-SCSI_Out_DBx__DB3__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
-SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
-SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
-SCSI_Out_DBx__DB3__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
-SCSI_Out_DBx__DB3__PS EQU CYREG_PRT2_PS
-SCSI_Out_DBx__DB3__SHIFT EQU 7
-SCSI_Out_DBx__DB3__SLW EQU CYREG_PRT2_SLW
-SCSI_Out_DBx__DB4__AG EQU CYREG_PRT2_AG
-SCSI_Out_DBx__DB4__AMUX EQU CYREG_PRT2_AMUX
-SCSI_Out_DBx__DB4__BIE EQU CYREG_PRT2_BIE
-SCSI_Out_DBx__DB4__BIT_MASK EQU CYREG_PRT2_BIT_MASK
-SCSI_Out_DBx__DB4__BYP EQU CYREG_PRT2_BYP
-SCSI_Out_DBx__DB4__CTL EQU CYREG_PRT2_CTL
-SCSI_Out_DBx__DB4__DM0 EQU CYREG_PRT2_DM0
-SCSI_Out_DBx__DB4__DM1 EQU CYREG_PRT2_DM1
-SCSI_Out_DBx__DB4__DM2 EQU CYREG_PRT2_DM2
-SCSI_Out_DBx__DB4__DR EQU CYREG_PRT2_DR
-SCSI_Out_DBx__DB4__INP_DIS EQU CYREG_PRT2_INP_DIS
-SCSI_Out_DBx__DB4__INTTYPE EQU CYREG_PICU2_INTTYPE5
-SCSI_Out_DBx__DB4__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
-SCSI_Out_DBx__DB4__LCD_EN EQU CYREG_PRT2_LCD_EN
-SCSI_Out_DBx__DB4__MASK EQU 0x20
-SCSI_Out_DBx__DB4__PC EQU CYREG_PRT2_PC5
-SCSI_Out_DBx__DB4__PORT EQU 2
-SCSI_Out_DBx__DB4__PRT EQU CYREG_PRT2_PRT
-SCSI_Out_DBx__DB4__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
-SCSI_Out_DBx__DB4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
-SCSI_Out_DBx__DB4__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
-SCSI_Out_DBx__DB4__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
-SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
-SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
-SCSI_Out_DBx__DB4__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
-SCSI_Out_DBx__DB4__PS EQU CYREG_PRT2_PS
-SCSI_Out_DBx__DB4__SHIFT EQU 5
-SCSI_Out_DBx__DB4__SLW EQU CYREG_PRT2_SLW
-SCSI_Out_DBx__DB5__AG EQU CYREG_PRT2_AG
-SCSI_Out_DBx__DB5__AMUX EQU CYREG_PRT2_AMUX
-SCSI_Out_DBx__DB5__BIE EQU CYREG_PRT2_BIE
-SCSI_Out_DBx__DB5__BIT_MASK EQU CYREG_PRT2_BIT_MASK
-SCSI_Out_DBx__DB5__BYP EQU CYREG_PRT2_BYP
-SCSI_Out_DBx__DB5__CTL EQU CYREG_PRT2_CTL
-SCSI_Out_DBx__DB5__DM0 EQU CYREG_PRT2_DM0
-SCSI_Out_DBx__DB5__DM1 EQU CYREG_PRT2_DM1
-SCSI_Out_DBx__DB5__DM2 EQU CYREG_PRT2_DM2
-SCSI_Out_DBx__DB5__DR EQU CYREG_PRT2_DR
-SCSI_Out_DBx__DB5__INP_DIS EQU CYREG_PRT2_INP_DIS
-SCSI_Out_DBx__DB5__INTTYPE EQU CYREG_PICU2_INTTYPE3
-SCSI_Out_DBx__DB5__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
-SCSI_Out_DBx__DB5__LCD_EN EQU CYREG_PRT2_LCD_EN
-SCSI_Out_DBx__DB5__MASK EQU 0x08
-SCSI_Out_DBx__DB5__PC EQU CYREG_PRT2_PC3
-SCSI_Out_DBx__DB5__PORT EQU 2
-SCSI_Out_DBx__DB5__PRT EQU CYREG_PRT2_PRT
-SCSI_Out_DBx__DB5__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
-SCSI_Out_DBx__DB5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
-SCSI_Out_DBx__DB5__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
-SCSI_Out_DBx__DB5__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
-SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
-SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
-SCSI_Out_DBx__DB5__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
-SCSI_Out_DBx__DB5__PS EQU CYREG_PRT2_PS
-SCSI_Out_DBx__DB5__SHIFT EQU 3
-SCSI_Out_DBx__DB5__SLW EQU CYREG_PRT2_SLW
-SCSI_Out_DBx__DB6__AG EQU CYREG_PRT2_AG
-SCSI_Out_DBx__DB6__AMUX EQU CYREG_PRT2_AMUX
-SCSI_Out_DBx__DB6__BIE EQU CYREG_PRT2_BIE
-SCSI_Out_DBx__DB6__BIT_MASK EQU CYREG_PRT2_BIT_MASK
-SCSI_Out_DBx__DB6__BYP EQU CYREG_PRT2_BYP
-SCSI_Out_DBx__DB6__CTL EQU CYREG_PRT2_CTL
-SCSI_Out_DBx__DB6__DM0 EQU CYREG_PRT2_DM0
-SCSI_Out_DBx__DB6__DM1 EQU CYREG_PRT2_DM1
-SCSI_Out_DBx__DB6__DM2 EQU CYREG_PRT2_DM2
-SCSI_Out_DBx__DB6__DR EQU CYREG_PRT2_DR
-SCSI_Out_DBx__DB6__INP_DIS EQU CYREG_PRT2_INP_DIS
-SCSI_Out_DBx__DB6__INTTYPE EQU CYREG_PICU2_INTTYPE1
-SCSI_Out_DBx__DB6__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
-SCSI_Out_DBx__DB6__LCD_EN EQU CYREG_PRT2_LCD_EN
-SCSI_Out_DBx__DB6__MASK EQU 0x02
-SCSI_Out_DBx__DB6__PC EQU CYREG_PRT2_PC1
-SCSI_Out_DBx__DB6__PORT EQU 2
-SCSI_Out_DBx__DB6__PRT EQU CYREG_PRT2_PRT
-SCSI_Out_DBx__DB6__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
-SCSI_Out_DBx__DB6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
-SCSI_Out_DBx__DB6__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
-SCSI_Out_DBx__DB6__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
-SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
-SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
-SCSI_Out_DBx__DB6__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
-SCSI_Out_DBx__DB6__PS EQU CYREG_PRT2_PS
-SCSI_Out_DBx__DB6__SHIFT EQU 1
-SCSI_Out_DBx__DB6__SLW EQU CYREG_PRT2_SLW
-SCSI_Out_DBx__DB7__AG EQU CYREG_PRT15_AG
-SCSI_Out_DBx__DB7__AMUX EQU CYREG_PRT15_AMUX
-SCSI_Out_DBx__DB7__BIE EQU CYREG_PRT15_BIE
-SCSI_Out_DBx__DB7__BIT_MASK EQU CYREG_PRT15_BIT_MASK
-SCSI_Out_DBx__DB7__BYP EQU CYREG_PRT15_BYP
-SCSI_Out_DBx__DB7__CTL EQU CYREG_PRT15_CTL
-SCSI_Out_DBx__DB7__DM0 EQU CYREG_PRT15_DM0
-SCSI_Out_DBx__DB7__DM1 EQU CYREG_PRT15_DM1
-SCSI_Out_DBx__DB7__DM2 EQU CYREG_PRT15_DM2
-SCSI_Out_DBx__DB7__DR EQU CYREG_PRT15_DR
-SCSI_Out_DBx__DB7__INP_DIS EQU CYREG_PRT15_INP_DIS
-SCSI_Out_DBx__DB7__INTTYPE EQU CYREG_PICU15_INTTYPE5
-SCSI_Out_DBx__DB7__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG
-SCSI_Out_DBx__DB7__LCD_EN EQU CYREG_PRT15_LCD_EN
-SCSI_Out_DBx__DB7__MASK EQU 0x20
-SCSI_Out_DBx__DB7__PC EQU CYREG_IO_PC_PRT15_PC5
-SCSI_Out_DBx__DB7__PORT EQU 15
-SCSI_Out_DBx__DB7__PRT EQU CYREG_PRT15_PRT
-SCSI_Out_DBx__DB7__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL
-SCSI_Out_DBx__DB7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN
-SCSI_Out_DBx__DB7__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0
-SCSI_Out_DBx__DB7__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1
-SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0
-SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1
-SCSI_Out_DBx__DB7__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT
-SCSI_Out_DBx__DB7__PS EQU CYREG_PRT15_PS
-SCSI_Out_DBx__DB7__SHIFT EQU 5
-SCSI_Out_DBx__DB7__SLW EQU CYREG_PRT15_SLW
-
-/* SD_RX_DMA */
-SD_RX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0
-SD_RX_DMA__DRQ_NUMBER EQU 2
-SD_RX_DMA__NUMBEROF_TDS EQU 0
-SD_RX_DMA__PRIORITY EQU 0
-SD_RX_DMA__TERMIN_EN EQU 0
-SD_RX_DMA__TERMIN_SEL EQU 0
-SD_RX_DMA__TERMOUT0_EN EQU 1
-SD_RX_DMA__TERMOUT0_SEL EQU 2
-SD_RX_DMA__TERMOUT1_EN EQU 0
-SD_RX_DMA__TERMOUT1_SEL EQU 0
-
-/* SD_RX_DMA_COMPLETE */
-SD_RX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
-SD_RX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-SD_RX_DMA_COMPLETE__INTC_MASK EQU 0x20
-SD_RX_DMA_COMPLETE__INTC_NUMBER EQU 5
-SD_RX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7
-SD_RX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_5
-SD_RX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
-SD_RX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
-
-/* SD_TX_DMA */
-SD_TX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0
-SD_TX_DMA__DRQ_NUMBER EQU 3
-SD_TX_DMA__NUMBEROF_TDS EQU 0
-SD_TX_DMA__PRIORITY EQU 1
-SD_TX_DMA__TERMIN_EN EQU 0
-SD_TX_DMA__TERMIN_SEL EQU 0
-SD_TX_DMA__TERMOUT0_EN EQU 1
-SD_TX_DMA__TERMOUT0_SEL EQU 3
-SD_TX_DMA__TERMOUT1_EN EQU 0
-SD_TX_DMA__TERMOUT1_SEL EQU 0
-
-/* SD_TX_DMA_COMPLETE */
-SD_TX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
-SD_TX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-SD_TX_DMA_COMPLETE__INTC_MASK EQU 0x40
-SD_TX_DMA_COMPLETE__INTC_NUMBER EQU 6
-SD_TX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7
-SD_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_6
-SD_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
-SD_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
+/* SCSI_In */
+SCSI_In__0__INTTYPE EQU CYREG_PICU6_INTTYPE1
+SCSI_In__0__MASK EQU 0x02
+SCSI_In__0__PC EQU CYREG_PRT6_PC1
+SCSI_In__0__PORT EQU 6
+SCSI_In__0__SHIFT EQU 1
+SCSI_In__AG EQU CYREG_PRT6_AG
+SCSI_In__AMUX EQU CYREG_PRT6_AMUX
+SCSI_In__BIE EQU CYREG_PRT6_BIE
+SCSI_In__BIT_MASK EQU CYREG_PRT6_BIT_MASK
+SCSI_In__BYP EQU CYREG_PRT6_BYP
+SCSI_In__CTL EQU CYREG_PRT6_CTL
+SCSI_In__DBP__INTTYPE EQU CYREG_PICU6_INTTYPE1
+SCSI_In__DBP__MASK EQU 0x02
+SCSI_In__DBP__PC EQU CYREG_PRT6_PC1
+SCSI_In__DBP__PORT EQU 6
+SCSI_In__DBP__SHIFT EQU 1
+SCSI_In__DM0 EQU CYREG_PRT6_DM0
+SCSI_In__DM1 EQU CYREG_PRT6_DM1
+SCSI_In__DM2 EQU CYREG_PRT6_DM2
+SCSI_In__DR EQU CYREG_PRT6_DR
+SCSI_In__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_In__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU6_BASE
+SCSI_In__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
+SCSI_In__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_In__MASK EQU 0x02
+SCSI_In__PORT EQU 6
+SCSI_In__PRT EQU CYREG_PRT6_PRT
+SCSI_In__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
+SCSI_In__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
+SCSI_In__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
+SCSI_In__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
+SCSI_In__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
+SCSI_In__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
+SCSI_In__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
+SCSI_In__PS EQU CYREG_PRT6_PS
+SCSI_In__SHIFT EQU 1
+SCSI_In__SLW EQU CYREG_PRT6_SLW
+SCSI_In_DBx__0__AG EQU CYREG_PRT6_AG
+SCSI_In_DBx__0__AMUX EQU CYREG_PRT6_AMUX
+SCSI_In_DBx__0__BIE EQU CYREG_PRT6_BIE
+SCSI_In_DBx__0__BIT_MASK EQU CYREG_PRT6_BIT_MASK
+SCSI_In_DBx__0__BYP EQU CYREG_PRT6_BYP
+SCSI_In_DBx__0__CTL EQU CYREG_PRT6_CTL
+SCSI_In_DBx__0__DM0 EQU CYREG_PRT6_DM0
+SCSI_In_DBx__0__DM1 EQU CYREG_PRT6_DM1
+SCSI_In_DBx__0__DM2 EQU CYREG_PRT6_DM2
+SCSI_In_DBx__0__DR EQU CYREG_PRT6_DR
+SCSI_In_DBx__0__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_In_DBx__0__INTTYPE EQU CYREG_PICU6_INTTYPE6
+SCSI_In_DBx__0__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
+SCSI_In_DBx__0__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_In_DBx__0__MASK EQU 0x40
+SCSI_In_DBx__0__PC EQU CYREG_PRT6_PC6
+SCSI_In_DBx__0__PORT EQU 6
+SCSI_In_DBx__0__PRT EQU CYREG_PRT6_PRT
+SCSI_In_DBx__0__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
+SCSI_In_DBx__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
+SCSI_In_DBx__0__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
+SCSI_In_DBx__0__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
+SCSI_In_DBx__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
+SCSI_In_DBx__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
+SCSI_In_DBx__0__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
+SCSI_In_DBx__0__PS EQU CYREG_PRT6_PS
+SCSI_In_DBx__0__SHIFT EQU 6
+SCSI_In_DBx__0__SLW EQU CYREG_PRT6_SLW
+SCSI_In_DBx__1__AG EQU CYREG_PRT6_AG
+SCSI_In_DBx__1__AMUX EQU CYREG_PRT6_AMUX
+SCSI_In_DBx__1__BIE EQU CYREG_PRT6_BIE
+SCSI_In_DBx__1__BIT_MASK EQU CYREG_PRT6_BIT_MASK
+SCSI_In_DBx__1__BYP EQU CYREG_PRT6_BYP
+SCSI_In_DBx__1__CTL EQU CYREG_PRT6_CTL
+SCSI_In_DBx__1__DM0 EQU CYREG_PRT6_DM0
+SCSI_In_DBx__1__DM1 EQU CYREG_PRT6_DM1
+SCSI_In_DBx__1__DM2 EQU CYREG_PRT6_DM2
+SCSI_In_DBx__1__DR EQU CYREG_PRT6_DR
+SCSI_In_DBx__1__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_In_DBx__1__INTTYPE EQU CYREG_PICU6_INTTYPE4
+SCSI_In_DBx__1__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
+SCSI_In_DBx__1__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_In_DBx__1__MASK EQU 0x10
+SCSI_In_DBx__1__PC EQU CYREG_PRT6_PC4
+SCSI_In_DBx__1__PORT EQU 6
+SCSI_In_DBx__1__PRT EQU CYREG_PRT6_PRT
+SCSI_In_DBx__1__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
+SCSI_In_DBx__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
+SCSI_In_DBx__1__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
+SCSI_In_DBx__1__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
+SCSI_In_DBx__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
+SCSI_In_DBx__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
+SCSI_In_DBx__1__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
+SCSI_In_DBx__1__PS EQU CYREG_PRT6_PS
+SCSI_In_DBx__1__SHIFT EQU 4
+SCSI_In_DBx__1__SLW EQU CYREG_PRT6_SLW
+SCSI_In_DBx__2__AG EQU CYREG_PRT12_AG
+SCSI_In_DBx__2__BIE EQU CYREG_PRT12_BIE
+SCSI_In_DBx__2__BIT_MASK EQU CYREG_PRT12_BIT_MASK
+SCSI_In_DBx__2__BYP EQU CYREG_PRT12_BYP
+SCSI_In_DBx__2__DM0 EQU CYREG_PRT12_DM0
+SCSI_In_DBx__2__DM1 EQU CYREG_PRT12_DM1
+SCSI_In_DBx__2__DM2 EQU CYREG_PRT12_DM2
+SCSI_In_DBx__2__DR EQU CYREG_PRT12_DR
+SCSI_In_DBx__2__INP_DIS EQU CYREG_PRT12_INP_DIS
+SCSI_In_DBx__2__INTTYPE EQU CYREG_PICU12_INTTYPE4
+SCSI_In_DBx__2__MASK EQU 0x10
+SCSI_In_DBx__2__PC EQU CYREG_PRT12_PC4
+SCSI_In_DBx__2__PORT EQU 12
+SCSI_In_DBx__2__PRT EQU CYREG_PRT12_PRT
+SCSI_In_DBx__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN
+SCSI_In_DBx__2__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0
+SCSI_In_DBx__2__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1
+SCSI_In_DBx__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0
+SCSI_In_DBx__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1
+SCSI_In_DBx__2__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT
+SCSI_In_DBx__2__PS EQU CYREG_PRT12_PS
+SCSI_In_DBx__2__SHIFT EQU 4
+SCSI_In_DBx__2__SIO_CFG EQU CYREG_PRT12_SIO_CFG
+SCSI_In_DBx__2__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF
+SCSI_In_DBx__2__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN
+SCSI_In_DBx__2__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ
+SCSI_In_DBx__2__SLW EQU CYREG_PRT12_SLW
+SCSI_In_DBx__3__AG EQU CYREG_PRT2_AG
+SCSI_In_DBx__3__AMUX EQU CYREG_PRT2_AMUX
+SCSI_In_DBx__3__BIE EQU CYREG_PRT2_BIE
+SCSI_In_DBx__3__BIT_MASK EQU CYREG_PRT2_BIT_MASK
+SCSI_In_DBx__3__BYP EQU CYREG_PRT2_BYP
+SCSI_In_DBx__3__CTL EQU CYREG_PRT2_CTL
+SCSI_In_DBx__3__DM0 EQU CYREG_PRT2_DM0
+SCSI_In_DBx__3__DM1 EQU CYREG_PRT2_DM1
+SCSI_In_DBx__3__DM2 EQU CYREG_PRT2_DM2
+SCSI_In_DBx__3__DR EQU CYREG_PRT2_DR
+SCSI_In_DBx__3__INP_DIS EQU CYREG_PRT2_INP_DIS
+SCSI_In_DBx__3__INTTYPE EQU CYREG_PICU2_INTTYPE6
+SCSI_In_DBx__3__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
+SCSI_In_DBx__3__LCD_EN EQU CYREG_PRT2_LCD_EN
+SCSI_In_DBx__3__MASK EQU 0x40
+SCSI_In_DBx__3__PC EQU CYREG_PRT2_PC6
+SCSI_In_DBx__3__PORT EQU 2
+SCSI_In_DBx__3__PRT EQU CYREG_PRT2_PRT
+SCSI_In_DBx__3__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
+SCSI_In_DBx__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
+SCSI_In_DBx__3__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
+SCSI_In_DBx__3__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
+SCSI_In_DBx__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
+SCSI_In_DBx__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
+SCSI_In_DBx__3__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
+SCSI_In_DBx__3__PS EQU CYREG_PRT2_PS
+SCSI_In_DBx__3__SHIFT EQU 6
+SCSI_In_DBx__3__SLW EQU CYREG_PRT2_SLW
+SCSI_In_DBx__4__AG EQU CYREG_PRT2_AG
+SCSI_In_DBx__4__AMUX EQU CYREG_PRT2_AMUX
+SCSI_In_DBx__4__BIE EQU CYREG_PRT2_BIE
+SCSI_In_DBx__4__BIT_MASK EQU CYREG_PRT2_BIT_MASK
+SCSI_In_DBx__4__BYP EQU CYREG_PRT2_BYP
+SCSI_In_DBx__4__CTL EQU CYREG_PRT2_CTL
+SCSI_In_DBx__4__DM0 EQU CYREG_PRT2_DM0
+SCSI_In_DBx__4__DM1 EQU CYREG_PRT2_DM1
+SCSI_In_DBx__4__DM2 EQU CYREG_PRT2_DM2
+SCSI_In_DBx__4__DR EQU CYREG_PRT2_DR
+SCSI_In_DBx__4__INP_DIS EQU CYREG_PRT2_INP_DIS
+SCSI_In_DBx__4__INTTYPE EQU CYREG_PICU2_INTTYPE4
+SCSI_In_DBx__4__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
+SCSI_In_DBx__4__LCD_EN EQU CYREG_PRT2_LCD_EN
+SCSI_In_DBx__4__MASK EQU 0x10
+SCSI_In_DBx__4__PC EQU CYREG_PRT2_PC4
+SCSI_In_DBx__4__PORT EQU 2
+SCSI_In_DBx__4__PRT EQU CYREG_PRT2_PRT
+SCSI_In_DBx__4__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
+SCSI_In_DBx__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
+SCSI_In_DBx__4__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
+SCSI_In_DBx__4__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
+SCSI_In_DBx__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
+SCSI_In_DBx__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
+SCSI_In_DBx__4__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
+SCSI_In_DBx__4__PS EQU CYREG_PRT2_PS
+SCSI_In_DBx__4__SHIFT EQU 4
+SCSI_In_DBx__4__SLW EQU CYREG_PRT2_SLW
+SCSI_In_DBx__5__AG EQU CYREG_PRT2_AG
+SCSI_In_DBx__5__AMUX EQU CYREG_PRT2_AMUX
+SCSI_In_DBx__5__BIE EQU CYREG_PRT2_BIE
+SCSI_In_DBx__5__BIT_MASK EQU CYREG_PRT2_BIT_MASK
+SCSI_In_DBx__5__BYP EQU CYREG_PRT2_BYP
+SCSI_In_DBx__5__CTL EQU CYREG_PRT2_CTL
+SCSI_In_DBx__5__DM0 EQU CYREG_PRT2_DM0
+SCSI_In_DBx__5__DM1 EQU CYREG_PRT2_DM1
+SCSI_In_DBx__5__DM2 EQU CYREG_PRT2_DM2
+SCSI_In_DBx__5__DR EQU CYREG_PRT2_DR
+SCSI_In_DBx__5__INP_DIS EQU CYREG_PRT2_INP_DIS
+SCSI_In_DBx__5__INTTYPE EQU CYREG_PICU2_INTTYPE2
+SCSI_In_DBx__5__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
+SCSI_In_DBx__5__LCD_EN EQU CYREG_PRT2_LCD_EN
+SCSI_In_DBx__5__MASK EQU 0x04
+SCSI_In_DBx__5__PC EQU CYREG_PRT2_PC2
+SCSI_In_DBx__5__PORT EQU 2
+SCSI_In_DBx__5__PRT EQU CYREG_PRT2_PRT
+SCSI_In_DBx__5__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
+SCSI_In_DBx__5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
+SCSI_In_DBx__5__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
+SCSI_In_DBx__5__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
+SCSI_In_DBx__5__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
+SCSI_In_DBx__5__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
+SCSI_In_DBx__5__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
+SCSI_In_DBx__5__PS EQU CYREG_PRT2_PS
+SCSI_In_DBx__5__SHIFT EQU 2
+SCSI_In_DBx__5__SLW EQU CYREG_PRT2_SLW
+SCSI_In_DBx__6__AG EQU CYREG_PRT2_AG
+SCSI_In_DBx__6__AMUX EQU CYREG_PRT2_AMUX
+SCSI_In_DBx__6__BIE EQU CYREG_PRT2_BIE
+SCSI_In_DBx__6__BIT_MASK EQU CYREG_PRT2_BIT_MASK
+SCSI_In_DBx__6__BYP EQU CYREG_PRT2_BYP
+SCSI_In_DBx__6__CTL EQU CYREG_PRT2_CTL
+SCSI_In_DBx__6__DM0 EQU CYREG_PRT2_DM0
+SCSI_In_DBx__6__DM1 EQU CYREG_PRT2_DM1
+SCSI_In_DBx__6__DM2 EQU CYREG_PRT2_DM2
+SCSI_In_DBx__6__DR EQU CYREG_PRT2_DR
+SCSI_In_DBx__6__INP_DIS EQU CYREG_PRT2_INP_DIS
+SCSI_In_DBx__6__INTTYPE EQU CYREG_PICU2_INTTYPE0
+SCSI_In_DBx__6__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
+SCSI_In_DBx__6__LCD_EN EQU CYREG_PRT2_LCD_EN
+SCSI_In_DBx__6__MASK EQU 0x01
+SCSI_In_DBx__6__PC EQU CYREG_PRT2_PC0
+SCSI_In_DBx__6__PORT EQU 2
+SCSI_In_DBx__6__PRT EQU CYREG_PRT2_PRT
+SCSI_In_DBx__6__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
+SCSI_In_DBx__6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
+SCSI_In_DBx__6__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
+SCSI_In_DBx__6__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
+SCSI_In_DBx__6__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
+SCSI_In_DBx__6__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
+SCSI_In_DBx__6__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
+SCSI_In_DBx__6__PS EQU CYREG_PRT2_PS
+SCSI_In_DBx__6__SHIFT EQU 0
+SCSI_In_DBx__6__SLW EQU CYREG_PRT2_SLW
+SCSI_In_DBx__7__AG EQU CYREG_PRT6_AG
+SCSI_In_DBx__7__AMUX EQU CYREG_PRT6_AMUX
+SCSI_In_DBx__7__BIE EQU CYREG_PRT6_BIE
+SCSI_In_DBx__7__BIT_MASK EQU CYREG_PRT6_BIT_MASK
+SCSI_In_DBx__7__BYP EQU CYREG_PRT6_BYP
+SCSI_In_DBx__7__CTL EQU CYREG_PRT6_CTL
+SCSI_In_DBx__7__DM0 EQU CYREG_PRT6_DM0
+SCSI_In_DBx__7__DM1 EQU CYREG_PRT6_DM1
+SCSI_In_DBx__7__DM2 EQU CYREG_PRT6_DM2
+SCSI_In_DBx__7__DR EQU CYREG_PRT6_DR
+SCSI_In_DBx__7__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_In_DBx__7__INTTYPE EQU CYREG_PICU6_INTTYPE3
+SCSI_In_DBx__7__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
+SCSI_In_DBx__7__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_In_DBx__7__MASK EQU 0x08
+SCSI_In_DBx__7__PC EQU CYREG_PRT6_PC3
+SCSI_In_DBx__7__PORT EQU 6
+SCSI_In_DBx__7__PRT EQU CYREG_PRT6_PRT
+SCSI_In_DBx__7__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
+SCSI_In_DBx__7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
+SCSI_In_DBx__7__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
+SCSI_In_DBx__7__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
+SCSI_In_DBx__7__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
+SCSI_In_DBx__7__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
+SCSI_In_DBx__7__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
+SCSI_In_DBx__7__PS EQU CYREG_PRT6_PS
+SCSI_In_DBx__7__SHIFT EQU 3
+SCSI_In_DBx__7__SLW EQU CYREG_PRT6_SLW
+SCSI_In_DBx__DB0__AG EQU CYREG_PRT6_AG
+SCSI_In_DBx__DB0__AMUX EQU CYREG_PRT6_AMUX
+SCSI_In_DBx__DB0__BIE EQU CYREG_PRT6_BIE
+SCSI_In_DBx__DB0__BIT_MASK EQU CYREG_PRT6_BIT_MASK
+SCSI_In_DBx__DB0__BYP EQU CYREG_PRT6_BYP
+SCSI_In_DBx__DB0__CTL EQU CYREG_PRT6_CTL
+SCSI_In_DBx__DB0__DM0 EQU CYREG_PRT6_DM0
+SCSI_In_DBx__DB0__DM1 EQU CYREG_PRT6_DM1
+SCSI_In_DBx__DB0__DM2 EQU CYREG_PRT6_DM2
+SCSI_In_DBx__DB0__DR EQU CYREG_PRT6_DR
+SCSI_In_DBx__DB0__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_In_DBx__DB0__INTTYPE EQU CYREG_PICU6_INTTYPE6
+SCSI_In_DBx__DB0__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
+SCSI_In_DBx__DB0__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_In_DBx__DB0__MASK EQU 0x40
+SCSI_In_DBx__DB0__PC EQU CYREG_PRT6_PC6
+SCSI_In_DBx__DB0__PORT EQU 6
+SCSI_In_DBx__DB0__PRT EQU CYREG_PRT6_PRT
+SCSI_In_DBx__DB0__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
+SCSI_In_DBx__DB0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
+SCSI_In_DBx__DB0__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
+SCSI_In_DBx__DB0__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
+SCSI_In_DBx__DB0__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
+SCSI_In_DBx__DB0__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
+SCSI_In_DBx__DB0__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
+SCSI_In_DBx__DB0__PS EQU CYREG_PRT6_PS
+SCSI_In_DBx__DB0__SHIFT EQU 6
+SCSI_In_DBx__DB0__SLW EQU CYREG_PRT6_SLW
+SCSI_In_DBx__DB1__AG EQU CYREG_PRT6_AG
+SCSI_In_DBx__DB1__AMUX EQU CYREG_PRT6_AMUX
+SCSI_In_DBx__DB1__BIE EQU CYREG_PRT6_BIE
+SCSI_In_DBx__DB1__BIT_MASK EQU CYREG_PRT6_BIT_MASK
+SCSI_In_DBx__DB1__BYP EQU CYREG_PRT6_BYP
+SCSI_In_DBx__DB1__CTL EQU CYREG_PRT6_CTL
+SCSI_In_DBx__DB1__DM0 EQU CYREG_PRT6_DM0
+SCSI_In_DBx__DB1__DM1 EQU CYREG_PRT6_DM1
+SCSI_In_DBx__DB1__DM2 EQU CYREG_PRT6_DM2
+SCSI_In_DBx__DB1__DR EQU CYREG_PRT6_DR
+SCSI_In_DBx__DB1__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_In_DBx__DB1__INTTYPE EQU CYREG_PICU6_INTTYPE4
+SCSI_In_DBx__DB1__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
+SCSI_In_DBx__DB1__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_In_DBx__DB1__MASK EQU 0x10
+SCSI_In_DBx__DB1__PC EQU CYREG_PRT6_PC4
+SCSI_In_DBx__DB1__PORT EQU 6
+SCSI_In_DBx__DB1__PRT EQU CYREG_PRT6_PRT
+SCSI_In_DBx__DB1__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
+SCSI_In_DBx__DB1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
+SCSI_In_DBx__DB1__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
+SCSI_In_DBx__DB1__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
+SCSI_In_DBx__DB1__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
+SCSI_In_DBx__DB1__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
+SCSI_In_DBx__DB1__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
+SCSI_In_DBx__DB1__PS EQU CYREG_PRT6_PS
+SCSI_In_DBx__DB1__SHIFT EQU 4
+SCSI_In_DBx__DB1__SLW EQU CYREG_PRT6_SLW
+SCSI_In_DBx__DB2__AG EQU CYREG_PRT12_AG
+SCSI_In_DBx__DB2__BIE EQU CYREG_PRT12_BIE
+SCSI_In_DBx__DB2__BIT_MASK EQU CYREG_PRT12_BIT_MASK
+SCSI_In_DBx__DB2__BYP EQU CYREG_PRT12_BYP
+SCSI_In_DBx__DB2__DM0 EQU CYREG_PRT12_DM0
+SCSI_In_DBx__DB2__DM1 EQU CYREG_PRT12_DM1
+SCSI_In_DBx__DB2__DM2 EQU CYREG_PRT12_DM2
+SCSI_In_DBx__DB2__DR EQU CYREG_PRT12_DR
+SCSI_In_DBx__DB2__INP_DIS EQU CYREG_PRT12_INP_DIS
+SCSI_In_DBx__DB2__INTTYPE EQU CYREG_PICU12_INTTYPE4
+SCSI_In_DBx__DB2__MASK EQU 0x10
+SCSI_In_DBx__DB2__PC EQU CYREG_PRT12_PC4
+SCSI_In_DBx__DB2__PORT EQU 12
+SCSI_In_DBx__DB2__PRT EQU CYREG_PRT12_PRT
+SCSI_In_DBx__DB2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN
+SCSI_In_DBx__DB2__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0
+SCSI_In_DBx__DB2__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1
+SCSI_In_DBx__DB2__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0
+SCSI_In_DBx__DB2__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1
+SCSI_In_DBx__DB2__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT
+SCSI_In_DBx__DB2__PS EQU CYREG_PRT12_PS
+SCSI_In_DBx__DB2__SHIFT EQU 4
+SCSI_In_DBx__DB2__SIO_CFG EQU CYREG_PRT12_SIO_CFG
+SCSI_In_DBx__DB2__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF
+SCSI_In_DBx__DB2__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN
+SCSI_In_DBx__DB2__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ
+SCSI_In_DBx__DB2__SLW EQU CYREG_PRT12_SLW
+SCSI_In_DBx__DB3__AG EQU CYREG_PRT2_AG
+SCSI_In_DBx__DB3__AMUX EQU CYREG_PRT2_AMUX
+SCSI_In_DBx__DB3__BIE EQU CYREG_PRT2_BIE
+SCSI_In_DBx__DB3__BIT_MASK EQU CYREG_PRT2_BIT_MASK
+SCSI_In_DBx__DB3__BYP EQU CYREG_PRT2_BYP
+SCSI_In_DBx__DB3__CTL EQU CYREG_PRT2_CTL
+SCSI_In_DBx__DB3__DM0 EQU CYREG_PRT2_DM0
+SCSI_In_DBx__DB3__DM1 EQU CYREG_PRT2_DM1
+SCSI_In_DBx__DB3__DM2 EQU CYREG_PRT2_DM2
+SCSI_In_DBx__DB3__DR EQU CYREG_PRT2_DR
+SCSI_In_DBx__DB3__INP_DIS EQU CYREG_PRT2_INP_DIS
+SCSI_In_DBx__DB3__INTTYPE EQU CYREG_PICU2_INTTYPE6
+SCSI_In_DBx__DB3__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
+SCSI_In_DBx__DB3__LCD_EN EQU CYREG_PRT2_LCD_EN
+SCSI_In_DBx__DB3__MASK EQU 0x40
+SCSI_In_DBx__DB3__PC EQU CYREG_PRT2_PC6
+SCSI_In_DBx__DB3__PORT EQU 2
+SCSI_In_DBx__DB3__PRT EQU CYREG_PRT2_PRT
+SCSI_In_DBx__DB3__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
+SCSI_In_DBx__DB3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
+SCSI_In_DBx__DB3__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
+SCSI_In_DBx__DB3__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
+SCSI_In_DBx__DB3__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
+SCSI_In_DBx__DB3__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
+SCSI_In_DBx__DB3__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
+SCSI_In_DBx__DB3__PS EQU CYREG_PRT2_PS
+SCSI_In_DBx__DB3__SHIFT EQU 6
+SCSI_In_DBx__DB3__SLW EQU CYREG_PRT2_SLW
+SCSI_In_DBx__DB4__AG EQU CYREG_PRT2_AG
+SCSI_In_DBx__DB4__AMUX EQU CYREG_PRT2_AMUX
+SCSI_In_DBx__DB4__BIE EQU CYREG_PRT2_BIE
+SCSI_In_DBx__DB4__BIT_MASK EQU CYREG_PRT2_BIT_MASK
+SCSI_In_DBx__DB4__BYP EQU CYREG_PRT2_BYP
+SCSI_In_DBx__DB4__CTL EQU CYREG_PRT2_CTL
+SCSI_In_DBx__DB4__DM0 EQU CYREG_PRT2_DM0
+SCSI_In_DBx__DB4__DM1 EQU CYREG_PRT2_DM1
+SCSI_In_DBx__DB4__DM2 EQU CYREG_PRT2_DM2
+SCSI_In_DBx__DB4__DR EQU CYREG_PRT2_DR
+SCSI_In_DBx__DB4__INP_DIS EQU CYREG_PRT2_INP_DIS
+SCSI_In_DBx__DB4__INTTYPE EQU CYREG_PICU2_INTTYPE4
+SCSI_In_DBx__DB4__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
+SCSI_In_DBx__DB4__LCD_EN EQU CYREG_PRT2_LCD_EN
+SCSI_In_DBx__DB4__MASK EQU 0x10
+SCSI_In_DBx__DB4__PC EQU CYREG_PRT2_PC4
+SCSI_In_DBx__DB4__PORT EQU 2
+SCSI_In_DBx__DB4__PRT EQU CYREG_PRT2_PRT
+SCSI_In_DBx__DB4__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
+SCSI_In_DBx__DB4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
+SCSI_In_DBx__DB4__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
+SCSI_In_DBx__DB4__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
+SCSI_In_DBx__DB4__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
+SCSI_In_DBx__DB4__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
+SCSI_In_DBx__DB4__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
+SCSI_In_DBx__DB4__PS EQU CYREG_PRT2_PS
+SCSI_In_DBx__DB4__SHIFT EQU 4
+SCSI_In_DBx__DB4__SLW EQU CYREG_PRT2_SLW
+SCSI_In_DBx__DB5__AG EQU CYREG_PRT2_AG
+SCSI_In_DBx__DB5__AMUX EQU CYREG_PRT2_AMUX
+SCSI_In_DBx__DB5__BIE EQU CYREG_PRT2_BIE
+SCSI_In_DBx__DB5__BIT_MASK EQU CYREG_PRT2_BIT_MASK
+SCSI_In_DBx__DB5__BYP EQU CYREG_PRT2_BYP
+SCSI_In_DBx__DB5__CTL EQU CYREG_PRT2_CTL
+SCSI_In_DBx__DB5__DM0 EQU CYREG_PRT2_DM0
+SCSI_In_DBx__DB5__DM1 EQU CYREG_PRT2_DM1
+SCSI_In_DBx__DB5__DM2 EQU CYREG_PRT2_DM2
+SCSI_In_DBx__DB5__DR EQU CYREG_PRT2_DR
+SCSI_In_DBx__DB5__INP_DIS EQU CYREG_PRT2_INP_DIS
+SCSI_In_DBx__DB5__INTTYPE EQU CYREG_PICU2_INTTYPE2
+SCSI_In_DBx__DB5__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
+SCSI_In_DBx__DB5__LCD_EN EQU CYREG_PRT2_LCD_EN
+SCSI_In_DBx__DB5__MASK EQU 0x04
+SCSI_In_DBx__DB5__PC EQU CYREG_PRT2_PC2
+SCSI_In_DBx__DB5__PORT EQU 2
+SCSI_In_DBx__DB5__PRT EQU CYREG_PRT2_PRT
+SCSI_In_DBx__DB5__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
+SCSI_In_DBx__DB5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
+SCSI_In_DBx__DB5__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
+SCSI_In_DBx__DB5__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
+SCSI_In_DBx__DB5__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
+SCSI_In_DBx__DB5__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
+SCSI_In_DBx__DB5__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
+SCSI_In_DBx__DB5__PS EQU CYREG_PRT2_PS
+SCSI_In_DBx__DB5__SHIFT EQU 2
+SCSI_In_DBx__DB5__SLW EQU CYREG_PRT2_SLW
+SCSI_In_DBx__DB6__AG EQU CYREG_PRT2_AG
+SCSI_In_DBx__DB6__AMUX EQU CYREG_PRT2_AMUX
+SCSI_In_DBx__DB6__BIE EQU CYREG_PRT2_BIE
+SCSI_In_DBx__DB6__BIT_MASK EQU CYREG_PRT2_BIT_MASK
+SCSI_In_DBx__DB6__BYP EQU CYREG_PRT2_BYP
+SCSI_In_DBx__DB6__CTL EQU CYREG_PRT2_CTL
+SCSI_In_DBx__DB6__DM0 EQU CYREG_PRT2_DM0
+SCSI_In_DBx__DB6__DM1 EQU CYREG_PRT2_DM1
+SCSI_In_DBx__DB6__DM2 EQU CYREG_PRT2_DM2
+SCSI_In_DBx__DB6__DR EQU CYREG_PRT2_DR
+SCSI_In_DBx__DB6__INP_DIS EQU CYREG_PRT2_INP_DIS
+SCSI_In_DBx__DB6__INTTYPE EQU CYREG_PICU2_INTTYPE0
+SCSI_In_DBx__DB6__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
+SCSI_In_DBx__DB6__LCD_EN EQU CYREG_PRT2_LCD_EN
+SCSI_In_DBx__DB6__MASK EQU 0x01
+SCSI_In_DBx__DB6__PC EQU CYREG_PRT2_PC0
+SCSI_In_DBx__DB6__PORT EQU 2
+SCSI_In_DBx__DB6__PRT EQU CYREG_PRT2_PRT
+SCSI_In_DBx__DB6__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
+SCSI_In_DBx__DB6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
+SCSI_In_DBx__DB6__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
+SCSI_In_DBx__DB6__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
+SCSI_In_DBx__DB6__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
+SCSI_In_DBx__DB6__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
+SCSI_In_DBx__DB6__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
+SCSI_In_DBx__DB6__PS EQU CYREG_PRT2_PS
+SCSI_In_DBx__DB6__SHIFT EQU 0
+SCSI_In_DBx__DB6__SLW EQU CYREG_PRT2_SLW
+SCSI_In_DBx__DB7__AG EQU CYREG_PRT6_AG
+SCSI_In_DBx__DB7__AMUX EQU CYREG_PRT6_AMUX
+SCSI_In_DBx__DB7__BIE EQU CYREG_PRT6_BIE
+SCSI_In_DBx__DB7__BIT_MASK EQU CYREG_PRT6_BIT_MASK
+SCSI_In_DBx__DB7__BYP EQU CYREG_PRT6_BYP
+SCSI_In_DBx__DB7__CTL EQU CYREG_PRT6_CTL
+SCSI_In_DBx__DB7__DM0 EQU CYREG_PRT6_DM0
+SCSI_In_DBx__DB7__DM1 EQU CYREG_PRT6_DM1
+SCSI_In_DBx__DB7__DM2 EQU CYREG_PRT6_DM2
+SCSI_In_DBx__DB7__DR EQU CYREG_PRT6_DR
+SCSI_In_DBx__DB7__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_In_DBx__DB7__INTTYPE EQU CYREG_PICU6_INTTYPE3
+SCSI_In_DBx__DB7__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
+SCSI_In_DBx__DB7__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_In_DBx__DB7__MASK EQU 0x08
+SCSI_In_DBx__DB7__PC EQU CYREG_PRT6_PC3
+SCSI_In_DBx__DB7__PORT EQU 6
+SCSI_In_DBx__DB7__PRT EQU CYREG_PRT6_PRT
+SCSI_In_DBx__DB7__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
+SCSI_In_DBx__DB7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
+SCSI_In_DBx__DB7__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
+SCSI_In_DBx__DB7__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
+SCSI_In_DBx__DB7__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
+SCSI_In_DBx__DB7__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
+SCSI_In_DBx__DB7__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
+SCSI_In_DBx__DB7__PS EQU CYREG_PRT6_PS
+SCSI_In_DBx__DB7__SHIFT EQU 3
+SCSI_In_DBx__DB7__SLW EQU CYREG_PRT6_SLW
 
 /* SCSI_Noise */
 SCSI_Noise__0__AG EQU CYREG_PRT4_AG
@@ -2354,6 +932,1592 @@ SCSI_Noise__SEL__PS EQU CYREG_PRT0_PS
 SCSI_Noise__SEL__SHIFT EQU 2
 SCSI_Noise__SEL__SLW EQU CYREG_PRT0_SLW
 
+/* SCSI_Out */
+SCSI_Out__0__AG EQU CYREG_PRT6_AG
+SCSI_Out__0__AMUX EQU CYREG_PRT6_AMUX
+SCSI_Out__0__BIE EQU CYREG_PRT6_BIE
+SCSI_Out__0__BIT_MASK EQU CYREG_PRT6_BIT_MASK
+SCSI_Out__0__BYP EQU CYREG_PRT6_BYP
+SCSI_Out__0__CTL EQU CYREG_PRT6_CTL
+SCSI_Out__0__DM0 EQU CYREG_PRT6_DM0
+SCSI_Out__0__DM1 EQU CYREG_PRT6_DM1
+SCSI_Out__0__DM2 EQU CYREG_PRT6_DM2
+SCSI_Out__0__DR EQU CYREG_PRT6_DR
+SCSI_Out__0__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_Out__0__INTTYPE EQU CYREG_PICU6_INTTYPE2
+SCSI_Out__0__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
+SCSI_Out__0__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_Out__0__MASK EQU 0x04
+SCSI_Out__0__PC EQU CYREG_PRT6_PC2
+SCSI_Out__0__PORT EQU 6
+SCSI_Out__0__PRT EQU CYREG_PRT6_PRT
+SCSI_Out__0__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
+SCSI_Out__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
+SCSI_Out__0__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
+SCSI_Out__0__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
+SCSI_Out__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
+SCSI_Out__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
+SCSI_Out__0__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
+SCSI_Out__0__PS EQU CYREG_PRT6_PS
+SCSI_Out__0__SHIFT EQU 2
+SCSI_Out__0__SLW EQU CYREG_PRT6_SLW
+SCSI_Out__1__AG EQU CYREG_PRT4_AG
+SCSI_Out__1__AMUX EQU CYREG_PRT4_AMUX
+SCSI_Out__1__BIE EQU CYREG_PRT4_BIE
+SCSI_Out__1__BIT_MASK EQU CYREG_PRT4_BIT_MASK
+SCSI_Out__1__BYP EQU CYREG_PRT4_BYP
+SCSI_Out__1__CTL EQU CYREG_PRT4_CTL
+SCSI_Out__1__DM0 EQU CYREG_PRT4_DM0
+SCSI_Out__1__DM1 EQU CYREG_PRT4_DM1
+SCSI_Out__1__DM2 EQU CYREG_PRT4_DM2
+SCSI_Out__1__DR EQU CYREG_PRT4_DR
+SCSI_Out__1__INP_DIS EQU CYREG_PRT4_INP_DIS
+SCSI_Out__1__INTTYPE EQU CYREG_PICU4_INTTYPE6
+SCSI_Out__1__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
+SCSI_Out__1__LCD_EN EQU CYREG_PRT4_LCD_EN
+SCSI_Out__1__MASK EQU 0x40
+SCSI_Out__1__PC EQU CYREG_PRT4_PC6
+SCSI_Out__1__PORT EQU 4
+SCSI_Out__1__PRT EQU CYREG_PRT4_PRT
+SCSI_Out__1__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
+SCSI_Out__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
+SCSI_Out__1__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
+SCSI_Out__1__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
+SCSI_Out__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
+SCSI_Out__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
+SCSI_Out__1__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
+SCSI_Out__1__PS EQU CYREG_PRT4_PS
+SCSI_Out__1__SHIFT EQU 6
+SCSI_Out__1__SLW EQU CYREG_PRT4_SLW
+SCSI_Out__2__AG EQU CYREG_PRT0_AG
+SCSI_Out__2__AMUX EQU CYREG_PRT0_AMUX
+SCSI_Out__2__BIE EQU CYREG_PRT0_BIE
+SCSI_Out__2__BIT_MASK EQU CYREG_PRT0_BIT_MASK
+SCSI_Out__2__BYP EQU CYREG_PRT0_BYP
+SCSI_Out__2__CTL EQU CYREG_PRT0_CTL
+SCSI_Out__2__DM0 EQU CYREG_PRT0_DM0
+SCSI_Out__2__DM1 EQU CYREG_PRT0_DM1
+SCSI_Out__2__DM2 EQU CYREG_PRT0_DM2
+SCSI_Out__2__DR EQU CYREG_PRT0_DR
+SCSI_Out__2__INP_DIS EQU CYREG_PRT0_INP_DIS
+SCSI_Out__2__INTTYPE EQU CYREG_PICU0_INTTYPE7
+SCSI_Out__2__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
+SCSI_Out__2__LCD_EN EQU CYREG_PRT0_LCD_EN
+SCSI_Out__2__MASK EQU 0x80
+SCSI_Out__2__PC EQU CYREG_PRT0_PC7
+SCSI_Out__2__PORT EQU 0
+SCSI_Out__2__PRT EQU CYREG_PRT0_PRT
+SCSI_Out__2__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
+SCSI_Out__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
+SCSI_Out__2__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
+SCSI_Out__2__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
+SCSI_Out__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
+SCSI_Out__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
+SCSI_Out__2__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
+SCSI_Out__2__PS EQU CYREG_PRT0_PS
+SCSI_Out__2__SHIFT EQU 7
+SCSI_Out__2__SLW EQU CYREG_PRT0_SLW
+SCSI_Out__3__AG EQU CYREG_PRT0_AG
+SCSI_Out__3__AMUX EQU CYREG_PRT0_AMUX
+SCSI_Out__3__BIE EQU CYREG_PRT0_BIE
+SCSI_Out__3__BIT_MASK EQU CYREG_PRT0_BIT_MASK
+SCSI_Out__3__BYP EQU CYREG_PRT0_BYP
+SCSI_Out__3__CTL EQU CYREG_PRT0_CTL
+SCSI_Out__3__DM0 EQU CYREG_PRT0_DM0
+SCSI_Out__3__DM1 EQU CYREG_PRT0_DM1
+SCSI_Out__3__DM2 EQU CYREG_PRT0_DM2
+SCSI_Out__3__DR EQU CYREG_PRT0_DR
+SCSI_Out__3__INP_DIS EQU CYREG_PRT0_INP_DIS
+SCSI_Out__3__INTTYPE EQU CYREG_PICU0_INTTYPE5
+SCSI_Out__3__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
+SCSI_Out__3__LCD_EN EQU CYREG_PRT0_LCD_EN
+SCSI_Out__3__MASK EQU 0x20
+SCSI_Out__3__PC EQU CYREG_PRT0_PC5
+SCSI_Out__3__PORT EQU 0
+SCSI_Out__3__PRT EQU CYREG_PRT0_PRT
+SCSI_Out__3__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
+SCSI_Out__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
+SCSI_Out__3__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
+SCSI_Out__3__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
+SCSI_Out__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
+SCSI_Out__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
+SCSI_Out__3__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
+SCSI_Out__3__PS EQU CYREG_PRT0_PS
+SCSI_Out__3__SHIFT EQU 5
+SCSI_Out__3__SLW EQU CYREG_PRT0_SLW
+SCSI_Out__4__AG EQU CYREG_PRT0_AG
+SCSI_Out__4__AMUX EQU CYREG_PRT0_AMUX
+SCSI_Out__4__BIE EQU CYREG_PRT0_BIE
+SCSI_Out__4__BIT_MASK EQU CYREG_PRT0_BIT_MASK
+SCSI_Out__4__BYP EQU CYREG_PRT0_BYP
+SCSI_Out__4__CTL EQU CYREG_PRT0_CTL
+SCSI_Out__4__DM0 EQU CYREG_PRT0_DM0
+SCSI_Out__4__DM1 EQU CYREG_PRT0_DM1
+SCSI_Out__4__DM2 EQU CYREG_PRT0_DM2
+SCSI_Out__4__DR EQU CYREG_PRT0_DR
+SCSI_Out__4__INP_DIS EQU CYREG_PRT0_INP_DIS
+SCSI_Out__4__INTTYPE EQU CYREG_PICU0_INTTYPE3
+SCSI_Out__4__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
+SCSI_Out__4__LCD_EN EQU CYREG_PRT0_LCD_EN
+SCSI_Out__4__MASK EQU 0x08
+SCSI_Out__4__PC EQU CYREG_PRT0_PC3
+SCSI_Out__4__PORT EQU 0
+SCSI_Out__4__PRT EQU CYREG_PRT0_PRT
+SCSI_Out__4__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
+SCSI_Out__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
+SCSI_Out__4__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
+SCSI_Out__4__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
+SCSI_Out__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
+SCSI_Out__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
+SCSI_Out__4__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
+SCSI_Out__4__PS EQU CYREG_PRT0_PS
+SCSI_Out__4__SHIFT EQU 3
+SCSI_Out__4__SLW EQU CYREG_PRT0_SLW
+SCSI_Out__5__AG EQU CYREG_PRT0_AG
+SCSI_Out__5__AMUX EQU CYREG_PRT0_AMUX
+SCSI_Out__5__BIE EQU CYREG_PRT0_BIE
+SCSI_Out__5__BIT_MASK EQU CYREG_PRT0_BIT_MASK
+SCSI_Out__5__BYP EQU CYREG_PRT0_BYP
+SCSI_Out__5__CTL EQU CYREG_PRT0_CTL
+SCSI_Out__5__DM0 EQU CYREG_PRT0_DM0
+SCSI_Out__5__DM1 EQU CYREG_PRT0_DM1
+SCSI_Out__5__DM2 EQU CYREG_PRT0_DM2
+SCSI_Out__5__DR EQU CYREG_PRT0_DR
+SCSI_Out__5__INP_DIS EQU CYREG_PRT0_INP_DIS
+SCSI_Out__5__INTTYPE EQU CYREG_PICU0_INTTYPE1
+SCSI_Out__5__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
+SCSI_Out__5__LCD_EN EQU CYREG_PRT0_LCD_EN
+SCSI_Out__5__MASK EQU 0x02
+SCSI_Out__5__PC EQU CYREG_PRT0_PC1
+SCSI_Out__5__PORT EQU 0
+SCSI_Out__5__PRT EQU CYREG_PRT0_PRT
+SCSI_Out__5__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
+SCSI_Out__5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
+SCSI_Out__5__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
+SCSI_Out__5__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
+SCSI_Out__5__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
+SCSI_Out__5__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
+SCSI_Out__5__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
+SCSI_Out__5__PS EQU CYREG_PRT0_PS
+SCSI_Out__5__SHIFT EQU 1
+SCSI_Out__5__SLW EQU CYREG_PRT0_SLW
+SCSI_Out__6__AG EQU CYREG_PRT4_AG
+SCSI_Out__6__AMUX EQU CYREG_PRT4_AMUX
+SCSI_Out__6__BIE EQU CYREG_PRT4_BIE
+SCSI_Out__6__BIT_MASK EQU CYREG_PRT4_BIT_MASK
+SCSI_Out__6__BYP EQU CYREG_PRT4_BYP
+SCSI_Out__6__CTL EQU CYREG_PRT4_CTL
+SCSI_Out__6__DM0 EQU CYREG_PRT4_DM0
+SCSI_Out__6__DM1 EQU CYREG_PRT4_DM1
+SCSI_Out__6__DM2 EQU CYREG_PRT4_DM2
+SCSI_Out__6__DR EQU CYREG_PRT4_DR
+SCSI_Out__6__INP_DIS EQU CYREG_PRT4_INP_DIS
+SCSI_Out__6__INTTYPE EQU CYREG_PICU4_INTTYPE1
+SCSI_Out__6__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
+SCSI_Out__6__LCD_EN EQU CYREG_PRT4_LCD_EN
+SCSI_Out__6__MASK EQU 0x02
+SCSI_Out__6__PC EQU CYREG_PRT4_PC1
+SCSI_Out__6__PORT EQU 4
+SCSI_Out__6__PRT EQU CYREG_PRT4_PRT
+SCSI_Out__6__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
+SCSI_Out__6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
+SCSI_Out__6__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
+SCSI_Out__6__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
+SCSI_Out__6__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
+SCSI_Out__6__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
+SCSI_Out__6__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
+SCSI_Out__6__PS EQU CYREG_PRT4_PS
+SCSI_Out__6__SHIFT EQU 1
+SCSI_Out__6__SLW EQU CYREG_PRT4_SLW
+SCSI_Out__7__AG EQU CYREG_PRT12_AG
+SCSI_Out__7__BIE EQU CYREG_PRT12_BIE
+SCSI_Out__7__BIT_MASK EQU CYREG_PRT12_BIT_MASK
+SCSI_Out__7__BYP EQU CYREG_PRT12_BYP
+SCSI_Out__7__DM0 EQU CYREG_PRT12_DM0
+SCSI_Out__7__DM1 EQU CYREG_PRT12_DM1
+SCSI_Out__7__DM2 EQU CYREG_PRT12_DM2
+SCSI_Out__7__DR EQU CYREG_PRT12_DR
+SCSI_Out__7__INP_DIS EQU CYREG_PRT12_INP_DIS
+SCSI_Out__7__INTTYPE EQU CYREG_PICU12_INTTYPE3
+SCSI_Out__7__MASK EQU 0x08
+SCSI_Out__7__PC EQU CYREG_PRT12_PC3
+SCSI_Out__7__PORT EQU 12
+SCSI_Out__7__PRT EQU CYREG_PRT12_PRT
+SCSI_Out__7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN
+SCSI_Out__7__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0
+SCSI_Out__7__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1
+SCSI_Out__7__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0
+SCSI_Out__7__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1
+SCSI_Out__7__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT
+SCSI_Out__7__PS EQU CYREG_PRT12_PS
+SCSI_Out__7__SHIFT EQU 3
+SCSI_Out__7__SIO_CFG EQU CYREG_PRT12_SIO_CFG
+SCSI_Out__7__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF
+SCSI_Out__7__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN
+SCSI_Out__7__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ
+SCSI_Out__7__SLW EQU CYREG_PRT12_SLW
+SCSI_Out__BSY__AG EQU CYREG_PRT4_AG
+SCSI_Out__BSY__AMUX EQU CYREG_PRT4_AMUX
+SCSI_Out__BSY__BIE EQU CYREG_PRT4_BIE
+SCSI_Out__BSY__BIT_MASK EQU CYREG_PRT4_BIT_MASK
+SCSI_Out__BSY__BYP EQU CYREG_PRT4_BYP
+SCSI_Out__BSY__CTL EQU CYREG_PRT4_CTL
+SCSI_Out__BSY__DM0 EQU CYREG_PRT4_DM0
+SCSI_Out__BSY__DM1 EQU CYREG_PRT4_DM1
+SCSI_Out__BSY__DM2 EQU CYREG_PRT4_DM2
+SCSI_Out__BSY__DR EQU CYREG_PRT4_DR
+SCSI_Out__BSY__INP_DIS EQU CYREG_PRT4_INP_DIS
+SCSI_Out__BSY__INTTYPE EQU CYREG_PICU4_INTTYPE6
+SCSI_Out__BSY__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
+SCSI_Out__BSY__LCD_EN EQU CYREG_PRT4_LCD_EN
+SCSI_Out__BSY__MASK EQU 0x40
+SCSI_Out__BSY__PC EQU CYREG_PRT4_PC6
+SCSI_Out__BSY__PORT EQU 4
+SCSI_Out__BSY__PRT EQU CYREG_PRT4_PRT
+SCSI_Out__BSY__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
+SCSI_Out__BSY__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
+SCSI_Out__BSY__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
+SCSI_Out__BSY__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
+SCSI_Out__BSY__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
+SCSI_Out__BSY__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
+SCSI_Out__BSY__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
+SCSI_Out__BSY__PS EQU CYREG_PRT4_PS
+SCSI_Out__BSY__SHIFT EQU 6
+SCSI_Out__BSY__SLW EQU CYREG_PRT4_SLW
+SCSI_Out__CD_raw__AG EQU CYREG_PRT0_AG
+SCSI_Out__CD_raw__AMUX EQU CYREG_PRT0_AMUX
+SCSI_Out__CD_raw__BIE EQU CYREG_PRT0_BIE
+SCSI_Out__CD_raw__BIT_MASK EQU CYREG_PRT0_BIT_MASK
+SCSI_Out__CD_raw__BYP EQU CYREG_PRT0_BYP
+SCSI_Out__CD_raw__CTL EQU CYREG_PRT0_CTL
+SCSI_Out__CD_raw__DM0 EQU CYREG_PRT0_DM0
+SCSI_Out__CD_raw__DM1 EQU CYREG_PRT0_DM1
+SCSI_Out__CD_raw__DM2 EQU CYREG_PRT0_DM2
+SCSI_Out__CD_raw__DR EQU CYREG_PRT0_DR
+SCSI_Out__CD_raw__INP_DIS EQU CYREG_PRT0_INP_DIS
+SCSI_Out__CD_raw__INTTYPE EQU CYREG_PICU0_INTTYPE1
+SCSI_Out__CD_raw__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
+SCSI_Out__CD_raw__LCD_EN EQU CYREG_PRT0_LCD_EN
+SCSI_Out__CD_raw__MASK EQU 0x02
+SCSI_Out__CD_raw__PC EQU CYREG_PRT0_PC1
+SCSI_Out__CD_raw__PORT EQU 0
+SCSI_Out__CD_raw__PRT EQU CYREG_PRT0_PRT
+SCSI_Out__CD_raw__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
+SCSI_Out__CD_raw__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
+SCSI_Out__CD_raw__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
+SCSI_Out__CD_raw__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
+SCSI_Out__CD_raw__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
+SCSI_Out__CD_raw__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
+SCSI_Out__CD_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
+SCSI_Out__CD_raw__PS EQU CYREG_PRT0_PS
+SCSI_Out__CD_raw__SHIFT EQU 1
+SCSI_Out__CD_raw__SLW EQU CYREG_PRT0_SLW
+SCSI_Out__DBP_raw__AG EQU CYREG_PRT6_AG
+SCSI_Out__DBP_raw__AMUX EQU CYREG_PRT6_AMUX
+SCSI_Out__DBP_raw__BIE EQU CYREG_PRT6_BIE
+SCSI_Out__DBP_raw__BIT_MASK EQU CYREG_PRT6_BIT_MASK
+SCSI_Out__DBP_raw__BYP EQU CYREG_PRT6_BYP
+SCSI_Out__DBP_raw__CTL EQU CYREG_PRT6_CTL
+SCSI_Out__DBP_raw__DM0 EQU CYREG_PRT6_DM0
+SCSI_Out__DBP_raw__DM1 EQU CYREG_PRT6_DM1
+SCSI_Out__DBP_raw__DM2 EQU CYREG_PRT6_DM2
+SCSI_Out__DBP_raw__DR EQU CYREG_PRT6_DR
+SCSI_Out__DBP_raw__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_Out__DBP_raw__INTTYPE EQU CYREG_PICU6_INTTYPE2
+SCSI_Out__DBP_raw__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
+SCSI_Out__DBP_raw__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_Out__DBP_raw__MASK EQU 0x04
+SCSI_Out__DBP_raw__PC EQU CYREG_PRT6_PC2
+SCSI_Out__DBP_raw__PORT EQU 6
+SCSI_Out__DBP_raw__PRT EQU CYREG_PRT6_PRT
+SCSI_Out__DBP_raw__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
+SCSI_Out__DBP_raw__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
+SCSI_Out__DBP_raw__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
+SCSI_Out__DBP_raw__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
+SCSI_Out__DBP_raw__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
+SCSI_Out__DBP_raw__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
+SCSI_Out__DBP_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
+SCSI_Out__DBP_raw__PS EQU CYREG_PRT6_PS
+SCSI_Out__DBP_raw__SHIFT EQU 2
+SCSI_Out__DBP_raw__SLW EQU CYREG_PRT6_SLW
+SCSI_Out__IO_raw__AG EQU CYREG_PRT12_AG
+SCSI_Out__IO_raw__BIE EQU CYREG_PRT12_BIE
+SCSI_Out__IO_raw__BIT_MASK EQU CYREG_PRT12_BIT_MASK
+SCSI_Out__IO_raw__BYP EQU CYREG_PRT12_BYP
+SCSI_Out__IO_raw__DM0 EQU CYREG_PRT12_DM0
+SCSI_Out__IO_raw__DM1 EQU CYREG_PRT12_DM1
+SCSI_Out__IO_raw__DM2 EQU CYREG_PRT12_DM2
+SCSI_Out__IO_raw__DR EQU CYREG_PRT12_DR
+SCSI_Out__IO_raw__INP_DIS EQU CYREG_PRT12_INP_DIS
+SCSI_Out__IO_raw__INTTYPE EQU CYREG_PICU12_INTTYPE3
+SCSI_Out__IO_raw__MASK EQU 0x08
+SCSI_Out__IO_raw__PC EQU CYREG_PRT12_PC3
+SCSI_Out__IO_raw__PORT EQU 12
+SCSI_Out__IO_raw__PRT EQU CYREG_PRT12_PRT
+SCSI_Out__IO_raw__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN
+SCSI_Out__IO_raw__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0
+SCSI_Out__IO_raw__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1
+SCSI_Out__IO_raw__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0
+SCSI_Out__IO_raw__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1
+SCSI_Out__IO_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT
+SCSI_Out__IO_raw__PS EQU CYREG_PRT12_PS
+SCSI_Out__IO_raw__SHIFT EQU 3
+SCSI_Out__IO_raw__SIO_CFG EQU CYREG_PRT12_SIO_CFG
+SCSI_Out__IO_raw__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF
+SCSI_Out__IO_raw__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN
+SCSI_Out__IO_raw__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ
+SCSI_Out__IO_raw__SLW EQU CYREG_PRT12_SLW
+SCSI_Out__MSG_raw__AG EQU CYREG_PRT0_AG
+SCSI_Out__MSG_raw__AMUX EQU CYREG_PRT0_AMUX
+SCSI_Out__MSG_raw__BIE EQU CYREG_PRT0_BIE
+SCSI_Out__MSG_raw__BIT_MASK EQU CYREG_PRT0_BIT_MASK
+SCSI_Out__MSG_raw__BYP EQU CYREG_PRT0_BYP
+SCSI_Out__MSG_raw__CTL EQU CYREG_PRT0_CTL
+SCSI_Out__MSG_raw__DM0 EQU CYREG_PRT0_DM0
+SCSI_Out__MSG_raw__DM1 EQU CYREG_PRT0_DM1
+SCSI_Out__MSG_raw__DM2 EQU CYREG_PRT0_DM2
+SCSI_Out__MSG_raw__DR EQU CYREG_PRT0_DR
+SCSI_Out__MSG_raw__INP_DIS EQU CYREG_PRT0_INP_DIS
+SCSI_Out__MSG_raw__INTTYPE EQU CYREG_PICU0_INTTYPE5
+SCSI_Out__MSG_raw__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
+SCSI_Out__MSG_raw__LCD_EN EQU CYREG_PRT0_LCD_EN
+SCSI_Out__MSG_raw__MASK EQU 0x20
+SCSI_Out__MSG_raw__PC EQU CYREG_PRT0_PC5
+SCSI_Out__MSG_raw__PORT EQU 0
+SCSI_Out__MSG_raw__PRT EQU CYREG_PRT0_PRT
+SCSI_Out__MSG_raw__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
+SCSI_Out__MSG_raw__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
+SCSI_Out__MSG_raw__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
+SCSI_Out__MSG_raw__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
+SCSI_Out__MSG_raw__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
+SCSI_Out__MSG_raw__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
+SCSI_Out__MSG_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
+SCSI_Out__MSG_raw__PS EQU CYREG_PRT0_PS
+SCSI_Out__MSG_raw__SHIFT EQU 5
+SCSI_Out__MSG_raw__SLW EQU CYREG_PRT0_SLW
+SCSI_Out__REQ__AG EQU CYREG_PRT4_AG
+SCSI_Out__REQ__AMUX EQU CYREG_PRT4_AMUX
+SCSI_Out__REQ__BIE EQU CYREG_PRT4_BIE
+SCSI_Out__REQ__BIT_MASK EQU CYREG_PRT4_BIT_MASK
+SCSI_Out__REQ__BYP EQU CYREG_PRT4_BYP
+SCSI_Out__REQ__CTL EQU CYREG_PRT4_CTL
+SCSI_Out__REQ__DM0 EQU CYREG_PRT4_DM0
+SCSI_Out__REQ__DM1 EQU CYREG_PRT4_DM1
+SCSI_Out__REQ__DM2 EQU CYREG_PRT4_DM2
+SCSI_Out__REQ__DR EQU CYREG_PRT4_DR
+SCSI_Out__REQ__INP_DIS EQU CYREG_PRT4_INP_DIS
+SCSI_Out__REQ__INTTYPE EQU CYREG_PICU4_INTTYPE1
+SCSI_Out__REQ__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
+SCSI_Out__REQ__LCD_EN EQU CYREG_PRT4_LCD_EN
+SCSI_Out__REQ__MASK EQU 0x02
+SCSI_Out__REQ__PC EQU CYREG_PRT4_PC1
+SCSI_Out__REQ__PORT EQU 4
+SCSI_Out__REQ__PRT EQU CYREG_PRT4_PRT
+SCSI_Out__REQ__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
+SCSI_Out__REQ__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
+SCSI_Out__REQ__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
+SCSI_Out__REQ__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
+SCSI_Out__REQ__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
+SCSI_Out__REQ__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
+SCSI_Out__REQ__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
+SCSI_Out__REQ__PS EQU CYREG_PRT4_PS
+SCSI_Out__REQ__SHIFT EQU 1
+SCSI_Out__REQ__SLW EQU CYREG_PRT4_SLW
+SCSI_Out__RST__AG EQU CYREG_PRT0_AG
+SCSI_Out__RST__AMUX EQU CYREG_PRT0_AMUX
+SCSI_Out__RST__BIE EQU CYREG_PRT0_BIE
+SCSI_Out__RST__BIT_MASK EQU CYREG_PRT0_BIT_MASK
+SCSI_Out__RST__BYP EQU CYREG_PRT0_BYP
+SCSI_Out__RST__CTL EQU CYREG_PRT0_CTL
+SCSI_Out__RST__DM0 EQU CYREG_PRT0_DM0
+SCSI_Out__RST__DM1 EQU CYREG_PRT0_DM1
+SCSI_Out__RST__DM2 EQU CYREG_PRT0_DM2
+SCSI_Out__RST__DR EQU CYREG_PRT0_DR
+SCSI_Out__RST__INP_DIS EQU CYREG_PRT0_INP_DIS
+SCSI_Out__RST__INTTYPE EQU CYREG_PICU0_INTTYPE7
+SCSI_Out__RST__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
+SCSI_Out__RST__LCD_EN EQU CYREG_PRT0_LCD_EN
+SCSI_Out__RST__MASK EQU 0x80
+SCSI_Out__RST__PC EQU CYREG_PRT0_PC7
+SCSI_Out__RST__PORT EQU 0
+SCSI_Out__RST__PRT EQU CYREG_PRT0_PRT
+SCSI_Out__RST__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
+SCSI_Out__RST__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
+SCSI_Out__RST__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
+SCSI_Out__RST__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
+SCSI_Out__RST__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
+SCSI_Out__RST__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
+SCSI_Out__RST__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
+SCSI_Out__RST__PS EQU CYREG_PRT0_PS
+SCSI_Out__RST__SHIFT EQU 7
+SCSI_Out__RST__SLW EQU CYREG_PRT0_SLW
+SCSI_Out__SEL__AG EQU CYREG_PRT0_AG
+SCSI_Out__SEL__AMUX EQU CYREG_PRT0_AMUX
+SCSI_Out__SEL__BIE EQU CYREG_PRT0_BIE
+SCSI_Out__SEL__BIT_MASK EQU CYREG_PRT0_BIT_MASK
+SCSI_Out__SEL__BYP EQU CYREG_PRT0_BYP
+SCSI_Out__SEL__CTL EQU CYREG_PRT0_CTL
+SCSI_Out__SEL__DM0 EQU CYREG_PRT0_DM0
+SCSI_Out__SEL__DM1 EQU CYREG_PRT0_DM1
+SCSI_Out__SEL__DM2 EQU CYREG_PRT0_DM2
+SCSI_Out__SEL__DR EQU CYREG_PRT0_DR
+SCSI_Out__SEL__INP_DIS EQU CYREG_PRT0_INP_DIS
+SCSI_Out__SEL__INTTYPE EQU CYREG_PICU0_INTTYPE3
+SCSI_Out__SEL__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
+SCSI_Out__SEL__LCD_EN EQU CYREG_PRT0_LCD_EN
+SCSI_Out__SEL__MASK EQU 0x08
+SCSI_Out__SEL__PC EQU CYREG_PRT0_PC3
+SCSI_Out__SEL__PORT EQU 0
+SCSI_Out__SEL__PRT EQU CYREG_PRT0_PRT
+SCSI_Out__SEL__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
+SCSI_Out__SEL__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
+SCSI_Out__SEL__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
+SCSI_Out__SEL__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
+SCSI_Out__SEL__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
+SCSI_Out__SEL__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
+SCSI_Out__SEL__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
+SCSI_Out__SEL__PS EQU CYREG_PRT0_PS
+SCSI_Out__SEL__SHIFT EQU 3
+SCSI_Out__SEL__SLW EQU CYREG_PRT0_SLW
+SCSI_Out_Bits_Sync_ctrl_reg__0__MASK EQU 0x01
+SCSI_Out_Bits_Sync_ctrl_reg__0__POS EQU 0
+SCSI_Out_Bits_Sync_ctrl_reg__1__MASK EQU 0x02
+SCSI_Out_Bits_Sync_ctrl_reg__1__POS EQU 1
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB07_08_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB07_08_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB07_08_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB07_08_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB07_08_MSK
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB07_08_MSK
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB07_08_MSK
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB07_08_MSK
+SCSI_Out_Bits_Sync_ctrl_reg__2__MASK EQU 0x04
+SCSI_Out_Bits_Sync_ctrl_reg__2__POS EQU 2
+SCSI_Out_Bits_Sync_ctrl_reg__3__MASK EQU 0x08
+SCSI_Out_Bits_Sync_ctrl_reg__3__POS EQU 3
+SCSI_Out_Bits_Sync_ctrl_reg__4__MASK EQU 0x10
+SCSI_Out_Bits_Sync_ctrl_reg__4__POS EQU 4
+SCSI_Out_Bits_Sync_ctrl_reg__5__MASK EQU 0x20
+SCSI_Out_Bits_Sync_ctrl_reg__5__POS EQU 5
+SCSI_Out_Bits_Sync_ctrl_reg__6__MASK EQU 0x40
+SCSI_Out_Bits_Sync_ctrl_reg__6__POS EQU 6
+SCSI_Out_Bits_Sync_ctrl_reg__7__MASK EQU 0x80
+SCSI_Out_Bits_Sync_ctrl_reg__7__POS EQU 7
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB07_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB07_ST_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB07_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB07_ST_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__MASK EQU 0xFF
+SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL
+SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL
+SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB07_MSK
+SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01
+SCSI_Out_Ctl_Sync_ctrl_reg__0__POS EQU 0
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB11_12_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB11_12_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB11_12_MSK
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB11_12_MSK
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB11_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB11_ST_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB11_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB11_ST_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__MASK EQU 0x01
+SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
+SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
+SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB11_MSK
+SCSI_Out_DBx__0__AG EQU CYREG_PRT6_AG
+SCSI_Out_DBx__0__AMUX EQU CYREG_PRT6_AMUX
+SCSI_Out_DBx__0__BIE EQU CYREG_PRT6_BIE
+SCSI_Out_DBx__0__BIT_MASK EQU CYREG_PRT6_BIT_MASK
+SCSI_Out_DBx__0__BYP EQU CYREG_PRT6_BYP
+SCSI_Out_DBx__0__CTL EQU CYREG_PRT6_CTL
+SCSI_Out_DBx__0__DM0 EQU CYREG_PRT6_DM0
+SCSI_Out_DBx__0__DM1 EQU CYREG_PRT6_DM1
+SCSI_Out_DBx__0__DM2 EQU CYREG_PRT6_DM2
+SCSI_Out_DBx__0__DR EQU CYREG_PRT6_DR
+SCSI_Out_DBx__0__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_Out_DBx__0__INTTYPE EQU CYREG_PICU6_INTTYPE7
+SCSI_Out_DBx__0__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
+SCSI_Out_DBx__0__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_Out_DBx__0__MASK EQU 0x80
+SCSI_Out_DBx__0__PC EQU CYREG_PRT6_PC7
+SCSI_Out_DBx__0__PORT EQU 6
+SCSI_Out_DBx__0__PRT EQU CYREG_PRT6_PRT
+SCSI_Out_DBx__0__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
+SCSI_Out_DBx__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
+SCSI_Out_DBx__0__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
+SCSI_Out_DBx__0__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
+SCSI_Out_DBx__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
+SCSI_Out_DBx__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
+SCSI_Out_DBx__0__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
+SCSI_Out_DBx__0__PS EQU CYREG_PRT6_PS
+SCSI_Out_DBx__0__SHIFT EQU 7
+SCSI_Out_DBx__0__SLW EQU CYREG_PRT6_SLW
+SCSI_Out_DBx__1__AG EQU CYREG_PRT6_AG
+SCSI_Out_DBx__1__AMUX EQU CYREG_PRT6_AMUX
+SCSI_Out_DBx__1__BIE EQU CYREG_PRT6_BIE
+SCSI_Out_DBx__1__BIT_MASK EQU CYREG_PRT6_BIT_MASK
+SCSI_Out_DBx__1__BYP EQU CYREG_PRT6_BYP
+SCSI_Out_DBx__1__CTL EQU CYREG_PRT6_CTL
+SCSI_Out_DBx__1__DM0 EQU CYREG_PRT6_DM0
+SCSI_Out_DBx__1__DM1 EQU CYREG_PRT6_DM1
+SCSI_Out_DBx__1__DM2 EQU CYREG_PRT6_DM2
+SCSI_Out_DBx__1__DR EQU CYREG_PRT6_DR
+SCSI_Out_DBx__1__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_Out_DBx__1__INTTYPE EQU CYREG_PICU6_INTTYPE5
+SCSI_Out_DBx__1__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
+SCSI_Out_DBx__1__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_Out_DBx__1__MASK EQU 0x20
+SCSI_Out_DBx__1__PC EQU CYREG_PRT6_PC5
+SCSI_Out_DBx__1__PORT EQU 6
+SCSI_Out_DBx__1__PRT EQU CYREG_PRT6_PRT
+SCSI_Out_DBx__1__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
+SCSI_Out_DBx__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
+SCSI_Out_DBx__1__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
+SCSI_Out_DBx__1__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
+SCSI_Out_DBx__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
+SCSI_Out_DBx__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
+SCSI_Out_DBx__1__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
+SCSI_Out_DBx__1__PS EQU CYREG_PRT6_PS
+SCSI_Out_DBx__1__SHIFT EQU 5
+SCSI_Out_DBx__1__SLW EQU CYREG_PRT6_SLW
+SCSI_Out_DBx__2__AG EQU CYREG_PRT12_AG
+SCSI_Out_DBx__2__BIE EQU CYREG_PRT12_BIE
+SCSI_Out_DBx__2__BIT_MASK EQU CYREG_PRT12_BIT_MASK
+SCSI_Out_DBx__2__BYP EQU CYREG_PRT12_BYP
+SCSI_Out_DBx__2__DM0 EQU CYREG_PRT12_DM0
+SCSI_Out_DBx__2__DM1 EQU CYREG_PRT12_DM1
+SCSI_Out_DBx__2__DM2 EQU CYREG_PRT12_DM2
+SCSI_Out_DBx__2__DR EQU CYREG_PRT12_DR
+SCSI_Out_DBx__2__INP_DIS EQU CYREG_PRT12_INP_DIS
+SCSI_Out_DBx__2__INTTYPE EQU CYREG_PICU12_INTTYPE5
+SCSI_Out_DBx__2__MASK EQU 0x20
+SCSI_Out_DBx__2__PC EQU CYREG_PRT12_PC5
+SCSI_Out_DBx__2__PORT EQU 12
+SCSI_Out_DBx__2__PRT EQU CYREG_PRT12_PRT
+SCSI_Out_DBx__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN
+SCSI_Out_DBx__2__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0
+SCSI_Out_DBx__2__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1
+SCSI_Out_DBx__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0
+SCSI_Out_DBx__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1
+SCSI_Out_DBx__2__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT
+SCSI_Out_DBx__2__PS EQU CYREG_PRT12_PS
+SCSI_Out_DBx__2__SHIFT EQU 5
+SCSI_Out_DBx__2__SIO_CFG EQU CYREG_PRT12_SIO_CFG
+SCSI_Out_DBx__2__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF
+SCSI_Out_DBx__2__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN
+SCSI_Out_DBx__2__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ
+SCSI_Out_DBx__2__SLW EQU CYREG_PRT12_SLW
+SCSI_Out_DBx__3__AG EQU CYREG_PRT2_AG
+SCSI_Out_DBx__3__AMUX EQU CYREG_PRT2_AMUX
+SCSI_Out_DBx__3__BIE EQU CYREG_PRT2_BIE
+SCSI_Out_DBx__3__BIT_MASK EQU CYREG_PRT2_BIT_MASK
+SCSI_Out_DBx__3__BYP EQU CYREG_PRT2_BYP
+SCSI_Out_DBx__3__CTL EQU CYREG_PRT2_CTL
+SCSI_Out_DBx__3__DM0 EQU CYREG_PRT2_DM0
+SCSI_Out_DBx__3__DM1 EQU CYREG_PRT2_DM1
+SCSI_Out_DBx__3__DM2 EQU CYREG_PRT2_DM2
+SCSI_Out_DBx__3__DR EQU CYREG_PRT2_DR
+SCSI_Out_DBx__3__INP_DIS EQU CYREG_PRT2_INP_DIS
+SCSI_Out_DBx__3__INTTYPE EQU CYREG_PICU2_INTTYPE7
+SCSI_Out_DBx__3__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
+SCSI_Out_DBx__3__LCD_EN EQU CYREG_PRT2_LCD_EN
+SCSI_Out_DBx__3__MASK EQU 0x80
+SCSI_Out_DBx__3__PC EQU CYREG_PRT2_PC7
+SCSI_Out_DBx__3__PORT EQU 2
+SCSI_Out_DBx__3__PRT EQU CYREG_PRT2_PRT
+SCSI_Out_DBx__3__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
+SCSI_Out_DBx__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
+SCSI_Out_DBx__3__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
+SCSI_Out_DBx__3__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
+SCSI_Out_DBx__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
+SCSI_Out_DBx__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
+SCSI_Out_DBx__3__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
+SCSI_Out_DBx__3__PS EQU CYREG_PRT2_PS
+SCSI_Out_DBx__3__SHIFT EQU 7
+SCSI_Out_DBx__3__SLW EQU CYREG_PRT2_SLW
+SCSI_Out_DBx__4__AG EQU CYREG_PRT2_AG
+SCSI_Out_DBx__4__AMUX EQU CYREG_PRT2_AMUX
+SCSI_Out_DBx__4__BIE EQU CYREG_PRT2_BIE
+SCSI_Out_DBx__4__BIT_MASK EQU CYREG_PRT2_BIT_MASK
+SCSI_Out_DBx__4__BYP EQU CYREG_PRT2_BYP
+SCSI_Out_DBx__4__CTL EQU CYREG_PRT2_CTL
+SCSI_Out_DBx__4__DM0 EQU CYREG_PRT2_DM0
+SCSI_Out_DBx__4__DM1 EQU CYREG_PRT2_DM1
+SCSI_Out_DBx__4__DM2 EQU CYREG_PRT2_DM2
+SCSI_Out_DBx__4__DR EQU CYREG_PRT2_DR
+SCSI_Out_DBx__4__INP_DIS EQU CYREG_PRT2_INP_DIS
+SCSI_Out_DBx__4__INTTYPE EQU CYREG_PICU2_INTTYPE5
+SCSI_Out_DBx__4__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
+SCSI_Out_DBx__4__LCD_EN EQU CYREG_PRT2_LCD_EN
+SCSI_Out_DBx__4__MASK EQU 0x20
+SCSI_Out_DBx__4__PC EQU CYREG_PRT2_PC5
+SCSI_Out_DBx__4__PORT EQU 2
+SCSI_Out_DBx__4__PRT EQU CYREG_PRT2_PRT
+SCSI_Out_DBx__4__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
+SCSI_Out_DBx__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
+SCSI_Out_DBx__4__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
+SCSI_Out_DBx__4__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
+SCSI_Out_DBx__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
+SCSI_Out_DBx__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
+SCSI_Out_DBx__4__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
+SCSI_Out_DBx__4__PS EQU CYREG_PRT2_PS
+SCSI_Out_DBx__4__SHIFT EQU 5
+SCSI_Out_DBx__4__SLW EQU CYREG_PRT2_SLW
+SCSI_Out_DBx__5__AG EQU CYREG_PRT2_AG
+SCSI_Out_DBx__5__AMUX EQU CYREG_PRT2_AMUX
+SCSI_Out_DBx__5__BIE EQU CYREG_PRT2_BIE
+SCSI_Out_DBx__5__BIT_MASK EQU CYREG_PRT2_BIT_MASK
+SCSI_Out_DBx__5__BYP EQU CYREG_PRT2_BYP
+SCSI_Out_DBx__5__CTL EQU CYREG_PRT2_CTL
+SCSI_Out_DBx__5__DM0 EQU CYREG_PRT2_DM0
+SCSI_Out_DBx__5__DM1 EQU CYREG_PRT2_DM1
+SCSI_Out_DBx__5__DM2 EQU CYREG_PRT2_DM2
+SCSI_Out_DBx__5__DR EQU CYREG_PRT2_DR
+SCSI_Out_DBx__5__INP_DIS EQU CYREG_PRT2_INP_DIS
+SCSI_Out_DBx__5__INTTYPE EQU CYREG_PICU2_INTTYPE3
+SCSI_Out_DBx__5__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
+SCSI_Out_DBx__5__LCD_EN EQU CYREG_PRT2_LCD_EN
+SCSI_Out_DBx__5__MASK EQU 0x08
+SCSI_Out_DBx__5__PC EQU CYREG_PRT2_PC3
+SCSI_Out_DBx__5__PORT EQU 2
+SCSI_Out_DBx__5__PRT EQU CYREG_PRT2_PRT
+SCSI_Out_DBx__5__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
+SCSI_Out_DBx__5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
+SCSI_Out_DBx__5__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
+SCSI_Out_DBx__5__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
+SCSI_Out_DBx__5__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
+SCSI_Out_DBx__5__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
+SCSI_Out_DBx__5__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
+SCSI_Out_DBx__5__PS EQU CYREG_PRT2_PS
+SCSI_Out_DBx__5__SHIFT EQU 3
+SCSI_Out_DBx__5__SLW EQU CYREG_PRT2_SLW
+SCSI_Out_DBx__6__AG EQU CYREG_PRT2_AG
+SCSI_Out_DBx__6__AMUX EQU CYREG_PRT2_AMUX
+SCSI_Out_DBx__6__BIE EQU CYREG_PRT2_BIE
+SCSI_Out_DBx__6__BIT_MASK EQU CYREG_PRT2_BIT_MASK
+SCSI_Out_DBx__6__BYP EQU CYREG_PRT2_BYP
+SCSI_Out_DBx__6__CTL EQU CYREG_PRT2_CTL
+SCSI_Out_DBx__6__DM0 EQU CYREG_PRT2_DM0
+SCSI_Out_DBx__6__DM1 EQU CYREG_PRT2_DM1
+SCSI_Out_DBx__6__DM2 EQU CYREG_PRT2_DM2
+SCSI_Out_DBx__6__DR EQU CYREG_PRT2_DR
+SCSI_Out_DBx__6__INP_DIS EQU CYREG_PRT2_INP_DIS
+SCSI_Out_DBx__6__INTTYPE EQU CYREG_PICU2_INTTYPE1
+SCSI_Out_DBx__6__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
+SCSI_Out_DBx__6__LCD_EN EQU CYREG_PRT2_LCD_EN
+SCSI_Out_DBx__6__MASK EQU 0x02
+SCSI_Out_DBx__6__PC EQU CYREG_PRT2_PC1
+SCSI_Out_DBx__6__PORT EQU 2
+SCSI_Out_DBx__6__PRT EQU CYREG_PRT2_PRT
+SCSI_Out_DBx__6__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
+SCSI_Out_DBx__6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
+SCSI_Out_DBx__6__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
+SCSI_Out_DBx__6__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
+SCSI_Out_DBx__6__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
+SCSI_Out_DBx__6__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
+SCSI_Out_DBx__6__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
+SCSI_Out_DBx__6__PS EQU CYREG_PRT2_PS
+SCSI_Out_DBx__6__SHIFT EQU 1
+SCSI_Out_DBx__6__SLW EQU CYREG_PRT2_SLW
+SCSI_Out_DBx__7__AG EQU CYREG_PRT15_AG
+SCSI_Out_DBx__7__AMUX EQU CYREG_PRT15_AMUX
+SCSI_Out_DBx__7__BIE EQU CYREG_PRT15_BIE
+SCSI_Out_DBx__7__BIT_MASK EQU CYREG_PRT15_BIT_MASK
+SCSI_Out_DBx__7__BYP EQU CYREG_PRT15_BYP
+SCSI_Out_DBx__7__CTL EQU CYREG_PRT15_CTL
+SCSI_Out_DBx__7__DM0 EQU CYREG_PRT15_DM0
+SCSI_Out_DBx__7__DM1 EQU CYREG_PRT15_DM1
+SCSI_Out_DBx__7__DM2 EQU CYREG_PRT15_DM2
+SCSI_Out_DBx__7__DR EQU CYREG_PRT15_DR
+SCSI_Out_DBx__7__INP_DIS EQU CYREG_PRT15_INP_DIS
+SCSI_Out_DBx__7__INTTYPE EQU CYREG_PICU15_INTTYPE5
+SCSI_Out_DBx__7__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG
+SCSI_Out_DBx__7__LCD_EN EQU CYREG_PRT15_LCD_EN
+SCSI_Out_DBx__7__MASK EQU 0x20
+SCSI_Out_DBx__7__PC EQU CYREG_IO_PC_PRT15_PC5
+SCSI_Out_DBx__7__PORT EQU 15
+SCSI_Out_DBx__7__PRT EQU CYREG_PRT15_PRT
+SCSI_Out_DBx__7__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL
+SCSI_Out_DBx__7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN
+SCSI_Out_DBx__7__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0
+SCSI_Out_DBx__7__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1
+SCSI_Out_DBx__7__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0
+SCSI_Out_DBx__7__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1
+SCSI_Out_DBx__7__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT
+SCSI_Out_DBx__7__PS EQU CYREG_PRT15_PS
+SCSI_Out_DBx__7__SHIFT EQU 5
+SCSI_Out_DBx__7__SLW EQU CYREG_PRT15_SLW
+SCSI_Out_DBx__DB0__AG EQU CYREG_PRT6_AG
+SCSI_Out_DBx__DB0__AMUX EQU CYREG_PRT6_AMUX
+SCSI_Out_DBx__DB0__BIE EQU CYREG_PRT6_BIE
+SCSI_Out_DBx__DB0__BIT_MASK EQU CYREG_PRT6_BIT_MASK
+SCSI_Out_DBx__DB0__BYP EQU CYREG_PRT6_BYP
+SCSI_Out_DBx__DB0__CTL EQU CYREG_PRT6_CTL
+SCSI_Out_DBx__DB0__DM0 EQU CYREG_PRT6_DM0
+SCSI_Out_DBx__DB0__DM1 EQU CYREG_PRT6_DM1
+SCSI_Out_DBx__DB0__DM2 EQU CYREG_PRT6_DM2
+SCSI_Out_DBx__DB0__DR EQU CYREG_PRT6_DR
+SCSI_Out_DBx__DB0__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_Out_DBx__DB0__INTTYPE EQU CYREG_PICU6_INTTYPE7
+SCSI_Out_DBx__DB0__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
+SCSI_Out_DBx__DB0__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_Out_DBx__DB0__MASK EQU 0x80
+SCSI_Out_DBx__DB0__PC EQU CYREG_PRT6_PC7
+SCSI_Out_DBx__DB0__PORT EQU 6
+SCSI_Out_DBx__DB0__PRT EQU CYREG_PRT6_PRT
+SCSI_Out_DBx__DB0__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
+SCSI_Out_DBx__DB0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
+SCSI_Out_DBx__DB0__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
+SCSI_Out_DBx__DB0__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
+SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
+SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
+SCSI_Out_DBx__DB0__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
+SCSI_Out_DBx__DB0__PS EQU CYREG_PRT6_PS
+SCSI_Out_DBx__DB0__SHIFT EQU 7
+SCSI_Out_DBx__DB0__SLW EQU CYREG_PRT6_SLW
+SCSI_Out_DBx__DB1__AG EQU CYREG_PRT6_AG
+SCSI_Out_DBx__DB1__AMUX EQU CYREG_PRT6_AMUX
+SCSI_Out_DBx__DB1__BIE EQU CYREG_PRT6_BIE
+SCSI_Out_DBx__DB1__BIT_MASK EQU CYREG_PRT6_BIT_MASK
+SCSI_Out_DBx__DB1__BYP EQU CYREG_PRT6_BYP
+SCSI_Out_DBx__DB1__CTL EQU CYREG_PRT6_CTL
+SCSI_Out_DBx__DB1__DM0 EQU CYREG_PRT6_DM0
+SCSI_Out_DBx__DB1__DM1 EQU CYREG_PRT6_DM1
+SCSI_Out_DBx__DB1__DM2 EQU CYREG_PRT6_DM2
+SCSI_Out_DBx__DB1__DR EQU CYREG_PRT6_DR
+SCSI_Out_DBx__DB1__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_Out_DBx__DB1__INTTYPE EQU CYREG_PICU6_INTTYPE5
+SCSI_Out_DBx__DB1__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
+SCSI_Out_DBx__DB1__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_Out_DBx__DB1__MASK EQU 0x20
+SCSI_Out_DBx__DB1__PC EQU CYREG_PRT6_PC5
+SCSI_Out_DBx__DB1__PORT EQU 6
+SCSI_Out_DBx__DB1__PRT EQU CYREG_PRT6_PRT
+SCSI_Out_DBx__DB1__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
+SCSI_Out_DBx__DB1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
+SCSI_Out_DBx__DB1__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
+SCSI_Out_DBx__DB1__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
+SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
+SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
+SCSI_Out_DBx__DB1__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
+SCSI_Out_DBx__DB1__PS EQU CYREG_PRT6_PS
+SCSI_Out_DBx__DB1__SHIFT EQU 5
+SCSI_Out_DBx__DB1__SLW EQU CYREG_PRT6_SLW
+SCSI_Out_DBx__DB2__AG EQU CYREG_PRT12_AG
+SCSI_Out_DBx__DB2__BIE EQU CYREG_PRT12_BIE
+SCSI_Out_DBx__DB2__BIT_MASK EQU CYREG_PRT12_BIT_MASK
+SCSI_Out_DBx__DB2__BYP EQU CYREG_PRT12_BYP
+SCSI_Out_DBx__DB2__DM0 EQU CYREG_PRT12_DM0
+SCSI_Out_DBx__DB2__DM1 EQU CYREG_PRT12_DM1
+SCSI_Out_DBx__DB2__DM2 EQU CYREG_PRT12_DM2
+SCSI_Out_DBx__DB2__DR EQU CYREG_PRT12_DR
+SCSI_Out_DBx__DB2__INP_DIS EQU CYREG_PRT12_INP_DIS
+SCSI_Out_DBx__DB2__INTTYPE EQU CYREG_PICU12_INTTYPE5
+SCSI_Out_DBx__DB2__MASK EQU 0x20
+SCSI_Out_DBx__DB2__PC EQU CYREG_PRT12_PC5
+SCSI_Out_DBx__DB2__PORT EQU 12
+SCSI_Out_DBx__DB2__PRT EQU CYREG_PRT12_PRT
+SCSI_Out_DBx__DB2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN
+SCSI_Out_DBx__DB2__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0
+SCSI_Out_DBx__DB2__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1
+SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0
+SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1
+SCSI_Out_DBx__DB2__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT
+SCSI_Out_DBx__DB2__PS EQU CYREG_PRT12_PS
+SCSI_Out_DBx__DB2__SHIFT EQU 5
+SCSI_Out_DBx__DB2__SIO_CFG EQU CYREG_PRT12_SIO_CFG
+SCSI_Out_DBx__DB2__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF
+SCSI_Out_DBx__DB2__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN
+SCSI_Out_DBx__DB2__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ
+SCSI_Out_DBx__DB2__SLW EQU CYREG_PRT12_SLW
+SCSI_Out_DBx__DB3__AG EQU CYREG_PRT2_AG
+SCSI_Out_DBx__DB3__AMUX EQU CYREG_PRT2_AMUX
+SCSI_Out_DBx__DB3__BIE EQU CYREG_PRT2_BIE
+SCSI_Out_DBx__DB3__BIT_MASK EQU CYREG_PRT2_BIT_MASK
+SCSI_Out_DBx__DB3__BYP EQU CYREG_PRT2_BYP
+SCSI_Out_DBx__DB3__CTL EQU CYREG_PRT2_CTL
+SCSI_Out_DBx__DB3__DM0 EQU CYREG_PRT2_DM0
+SCSI_Out_DBx__DB3__DM1 EQU CYREG_PRT2_DM1
+SCSI_Out_DBx__DB3__DM2 EQU CYREG_PRT2_DM2
+SCSI_Out_DBx__DB3__DR EQU CYREG_PRT2_DR
+SCSI_Out_DBx__DB3__INP_DIS EQU CYREG_PRT2_INP_DIS
+SCSI_Out_DBx__DB3__INTTYPE EQU CYREG_PICU2_INTTYPE7
+SCSI_Out_DBx__DB3__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
+SCSI_Out_DBx__DB3__LCD_EN EQU CYREG_PRT2_LCD_EN
+SCSI_Out_DBx__DB3__MASK EQU 0x80
+SCSI_Out_DBx__DB3__PC EQU CYREG_PRT2_PC7
+SCSI_Out_DBx__DB3__PORT EQU 2
+SCSI_Out_DBx__DB3__PRT EQU CYREG_PRT2_PRT
+SCSI_Out_DBx__DB3__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
+SCSI_Out_DBx__DB3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
+SCSI_Out_DBx__DB3__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
+SCSI_Out_DBx__DB3__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
+SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
+SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
+SCSI_Out_DBx__DB3__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
+SCSI_Out_DBx__DB3__PS EQU CYREG_PRT2_PS
+SCSI_Out_DBx__DB3__SHIFT EQU 7
+SCSI_Out_DBx__DB3__SLW EQU CYREG_PRT2_SLW
+SCSI_Out_DBx__DB4__AG EQU CYREG_PRT2_AG
+SCSI_Out_DBx__DB4__AMUX EQU CYREG_PRT2_AMUX
+SCSI_Out_DBx__DB4__BIE EQU CYREG_PRT2_BIE
+SCSI_Out_DBx__DB4__BIT_MASK EQU CYREG_PRT2_BIT_MASK
+SCSI_Out_DBx__DB4__BYP EQU CYREG_PRT2_BYP
+SCSI_Out_DBx__DB4__CTL EQU CYREG_PRT2_CTL
+SCSI_Out_DBx__DB4__DM0 EQU CYREG_PRT2_DM0
+SCSI_Out_DBx__DB4__DM1 EQU CYREG_PRT2_DM1
+SCSI_Out_DBx__DB4__DM2 EQU CYREG_PRT2_DM2
+SCSI_Out_DBx__DB4__DR EQU CYREG_PRT2_DR
+SCSI_Out_DBx__DB4__INP_DIS EQU CYREG_PRT2_INP_DIS
+SCSI_Out_DBx__DB4__INTTYPE EQU CYREG_PICU2_INTTYPE5
+SCSI_Out_DBx__DB4__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
+SCSI_Out_DBx__DB4__LCD_EN EQU CYREG_PRT2_LCD_EN
+SCSI_Out_DBx__DB4__MASK EQU 0x20
+SCSI_Out_DBx__DB4__PC EQU CYREG_PRT2_PC5
+SCSI_Out_DBx__DB4__PORT EQU 2
+SCSI_Out_DBx__DB4__PRT EQU CYREG_PRT2_PRT
+SCSI_Out_DBx__DB4__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
+SCSI_Out_DBx__DB4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
+SCSI_Out_DBx__DB4__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
+SCSI_Out_DBx__DB4__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
+SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
+SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
+SCSI_Out_DBx__DB4__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
+SCSI_Out_DBx__DB4__PS EQU CYREG_PRT2_PS
+SCSI_Out_DBx__DB4__SHIFT EQU 5
+SCSI_Out_DBx__DB4__SLW EQU CYREG_PRT2_SLW
+SCSI_Out_DBx__DB5__AG EQU CYREG_PRT2_AG
+SCSI_Out_DBx__DB5__AMUX EQU CYREG_PRT2_AMUX
+SCSI_Out_DBx__DB5__BIE EQU CYREG_PRT2_BIE
+SCSI_Out_DBx__DB5__BIT_MASK EQU CYREG_PRT2_BIT_MASK
+SCSI_Out_DBx__DB5__BYP EQU CYREG_PRT2_BYP
+SCSI_Out_DBx__DB5__CTL EQU CYREG_PRT2_CTL
+SCSI_Out_DBx__DB5__DM0 EQU CYREG_PRT2_DM0
+SCSI_Out_DBx__DB5__DM1 EQU CYREG_PRT2_DM1
+SCSI_Out_DBx__DB5__DM2 EQU CYREG_PRT2_DM2
+SCSI_Out_DBx__DB5__DR EQU CYREG_PRT2_DR
+SCSI_Out_DBx__DB5__INP_DIS EQU CYREG_PRT2_INP_DIS
+SCSI_Out_DBx__DB5__INTTYPE EQU CYREG_PICU2_INTTYPE3
+SCSI_Out_DBx__DB5__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
+SCSI_Out_DBx__DB5__LCD_EN EQU CYREG_PRT2_LCD_EN
+SCSI_Out_DBx__DB5__MASK EQU 0x08
+SCSI_Out_DBx__DB5__PC EQU CYREG_PRT2_PC3
+SCSI_Out_DBx__DB5__PORT EQU 2
+SCSI_Out_DBx__DB5__PRT EQU CYREG_PRT2_PRT
+SCSI_Out_DBx__DB5__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
+SCSI_Out_DBx__DB5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
+SCSI_Out_DBx__DB5__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
+SCSI_Out_DBx__DB5__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
+SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
+SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
+SCSI_Out_DBx__DB5__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
+SCSI_Out_DBx__DB5__PS EQU CYREG_PRT2_PS
+SCSI_Out_DBx__DB5__SHIFT EQU 3
+SCSI_Out_DBx__DB5__SLW EQU CYREG_PRT2_SLW
+SCSI_Out_DBx__DB6__AG EQU CYREG_PRT2_AG
+SCSI_Out_DBx__DB6__AMUX EQU CYREG_PRT2_AMUX
+SCSI_Out_DBx__DB6__BIE EQU CYREG_PRT2_BIE
+SCSI_Out_DBx__DB6__BIT_MASK EQU CYREG_PRT2_BIT_MASK
+SCSI_Out_DBx__DB6__BYP EQU CYREG_PRT2_BYP
+SCSI_Out_DBx__DB6__CTL EQU CYREG_PRT2_CTL
+SCSI_Out_DBx__DB6__DM0 EQU CYREG_PRT2_DM0
+SCSI_Out_DBx__DB6__DM1 EQU CYREG_PRT2_DM1
+SCSI_Out_DBx__DB6__DM2 EQU CYREG_PRT2_DM2
+SCSI_Out_DBx__DB6__DR EQU CYREG_PRT2_DR
+SCSI_Out_DBx__DB6__INP_DIS EQU CYREG_PRT2_INP_DIS
+SCSI_Out_DBx__DB6__INTTYPE EQU CYREG_PICU2_INTTYPE1
+SCSI_Out_DBx__DB6__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
+SCSI_Out_DBx__DB6__LCD_EN EQU CYREG_PRT2_LCD_EN
+SCSI_Out_DBx__DB6__MASK EQU 0x02
+SCSI_Out_DBx__DB6__PC EQU CYREG_PRT2_PC1
+SCSI_Out_DBx__DB6__PORT EQU 2
+SCSI_Out_DBx__DB6__PRT EQU CYREG_PRT2_PRT
+SCSI_Out_DBx__DB6__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
+SCSI_Out_DBx__DB6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
+SCSI_Out_DBx__DB6__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
+SCSI_Out_DBx__DB6__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
+SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
+SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
+SCSI_Out_DBx__DB6__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
+SCSI_Out_DBx__DB6__PS EQU CYREG_PRT2_PS
+SCSI_Out_DBx__DB6__SHIFT EQU 1
+SCSI_Out_DBx__DB6__SLW EQU CYREG_PRT2_SLW
+SCSI_Out_DBx__DB7__AG EQU CYREG_PRT15_AG
+SCSI_Out_DBx__DB7__AMUX EQU CYREG_PRT15_AMUX
+SCSI_Out_DBx__DB7__BIE EQU CYREG_PRT15_BIE
+SCSI_Out_DBx__DB7__BIT_MASK EQU CYREG_PRT15_BIT_MASK
+SCSI_Out_DBx__DB7__BYP EQU CYREG_PRT15_BYP
+SCSI_Out_DBx__DB7__CTL EQU CYREG_PRT15_CTL
+SCSI_Out_DBx__DB7__DM0 EQU CYREG_PRT15_DM0
+SCSI_Out_DBx__DB7__DM1 EQU CYREG_PRT15_DM1
+SCSI_Out_DBx__DB7__DM2 EQU CYREG_PRT15_DM2
+SCSI_Out_DBx__DB7__DR EQU CYREG_PRT15_DR
+SCSI_Out_DBx__DB7__INP_DIS EQU CYREG_PRT15_INP_DIS
+SCSI_Out_DBx__DB7__INTTYPE EQU CYREG_PICU15_INTTYPE5
+SCSI_Out_DBx__DB7__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG
+SCSI_Out_DBx__DB7__LCD_EN EQU CYREG_PRT15_LCD_EN
+SCSI_Out_DBx__DB7__MASK EQU 0x20
+SCSI_Out_DBx__DB7__PC EQU CYREG_IO_PC_PRT15_PC5
+SCSI_Out_DBx__DB7__PORT EQU 15
+SCSI_Out_DBx__DB7__PRT EQU CYREG_PRT15_PRT
+SCSI_Out_DBx__DB7__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL
+SCSI_Out_DBx__DB7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN
+SCSI_Out_DBx__DB7__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0
+SCSI_Out_DBx__DB7__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1
+SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0
+SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1
+SCSI_Out_DBx__DB7__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT
+SCSI_Out_DBx__DB7__PS EQU CYREG_PRT15_PS
+SCSI_Out_DBx__DB7__SHIFT EQU 5
+SCSI_Out_DBx__DB7__SLW EQU CYREG_PRT15_SLW
+
+/* SCSI_Parity_Error */
+SCSI_Parity_Error_sts_sts_reg__0__MASK EQU 0x01
+SCSI_Parity_Error_sts_sts_reg__0__POS EQU 0
+SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL
+SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB02_03_ST
+SCSI_Parity_Error_sts_sts_reg__MASK EQU 0x01
+SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB02_MSK
+SCSI_Parity_Error_sts_sts_reg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL
+SCSI_Parity_Error_sts_sts_reg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL
+SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL
+SCSI_Parity_Error_sts_sts_reg__STATUS_CNT_REG EQU CYREG_B0_UDB02_ST_CTL
+SCSI_Parity_Error_sts_sts_reg__STATUS_CONTROL_REG EQU CYREG_B0_UDB02_ST_CTL
+SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB02_ST
+
+/* SCSI_RST_ISR */
+SCSI_RST_ISR__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
+SCSI_RST_ISR__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
+SCSI_RST_ISR__INTC_MASK EQU 0x02
+SCSI_RST_ISR__INTC_NUMBER EQU 1
+SCSI_RST_ISR__INTC_PRIOR_NUM EQU 7
+SCSI_RST_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_1
+SCSI_RST_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
+SCSI_RST_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
+
+/* SCSI_RX_DMA */
+SCSI_RX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0
+SCSI_RX_DMA__DRQ_NUMBER EQU 0
+SCSI_RX_DMA__NUMBEROF_TDS EQU 0
+SCSI_RX_DMA__PRIORITY EQU 2
+SCSI_RX_DMA__TERMIN_EN EQU 0
+SCSI_RX_DMA__TERMIN_SEL EQU 0
+SCSI_RX_DMA__TERMOUT0_EN EQU 1
+SCSI_RX_DMA__TERMOUT0_SEL EQU 0
+SCSI_RX_DMA__TERMOUT1_EN EQU 0
+SCSI_RX_DMA__TERMOUT1_SEL EQU 0
+SCSI_RX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
+SCSI_RX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
+SCSI_RX_DMA_COMPLETE__INTC_MASK EQU 0x04
+SCSI_RX_DMA_COMPLETE__INTC_NUMBER EQU 2
+SCSI_RX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7
+SCSI_RX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_2
+SCSI_RX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
+SCSI_RX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
+
+/* SCSI_SEL_ISR */
+SCSI_SEL_ISR__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
+SCSI_SEL_ISR__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
+SCSI_SEL_ISR__INTC_MASK EQU 0x08
+SCSI_SEL_ISR__INTC_NUMBER EQU 3
+SCSI_SEL_ISR__INTC_PRIOR_NUM EQU 7
+SCSI_SEL_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_3
+SCSI_SEL_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
+SCSI_SEL_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
+
+/* SCSI_TX_DMA */
+SCSI_TX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0
+SCSI_TX_DMA__DRQ_NUMBER EQU 1
+SCSI_TX_DMA__NUMBEROF_TDS EQU 0
+SCSI_TX_DMA__PRIORITY EQU 2
+SCSI_TX_DMA__TERMIN_EN EQU 0
+SCSI_TX_DMA__TERMIN_SEL EQU 0
+SCSI_TX_DMA__TERMOUT0_EN EQU 1
+SCSI_TX_DMA__TERMOUT0_SEL EQU 1
+SCSI_TX_DMA__TERMOUT1_EN EQU 0
+SCSI_TX_DMA__TERMOUT1_SEL EQU 0
+SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
+SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
+SCSI_TX_DMA_COMPLETE__INTC_MASK EQU 0x10
+SCSI_TX_DMA_COMPLETE__INTC_NUMBER EQU 4
+SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7
+SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_4
+SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
+SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
+
+/* SDCard_BSPIM */
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB04_05_CTL
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB04_05_CTL
+SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB04_05_CTL
+SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB04_05_CTL
+SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB04_05_MSK
+SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB04_05_MSK
+SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB04_05_MSK
+SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB04_05_MSK
+SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL
+SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB04_CTL
+SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB04_ST_CTL
+SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB04_CTL
+SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB04_ST_CTL
+SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL
+SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL
+SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB04_MSK
+SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL
+SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB04_05_ST
+SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB04_MSK
+SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL
+SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL
+SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL
+SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB04_ST_CTL
+SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB04_ST_CTL
+SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB04_ST
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB07_08_ST
+SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10
+SDCard_BSPIM_RxStsReg__4__POS EQU 4
+SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20
+SDCard_BSPIM_RxStsReg__5__POS EQU 5
+SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40
+SDCard_BSPIM_RxStsReg__6__POS EQU 6
+SDCard_BSPIM_RxStsReg__MASK EQU 0x70
+SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B0_UDB07_MSK
+SDCard_BSPIM_RxStsReg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL
+SDCard_BSPIM_RxStsReg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL
+SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL
+SDCard_BSPIM_RxStsReg__STATUS_CNT_REG EQU CYREG_B0_UDB07_ST_CTL
+SDCard_BSPIM_RxStsReg__STATUS_CONTROL_REG EQU CYREG_B0_UDB07_ST_CTL
+SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B0_UDB07_ST
+SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB04_05_A0
+SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB04_05_A1
+SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B1_UDB04_05_D0
+SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B1_UDB04_05_D1
+SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL
+SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B1_UDB04_05_F0
+SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B1_UDB04_05_F1
+SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B1_UDB04_A0_A1
+SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B1_UDB04_A0
+SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B1_UDB04_A1
+SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B1_UDB04_D0_D1
+SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B1_UDB04_D0
+SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B1_UDB04_D1
+SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL
+SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B1_UDB04_F0_F1
+SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B1_UDB04_F0
+SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B1_UDB04_F1
+SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL
+SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL
+SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01
+SDCard_BSPIM_TxStsReg__0__POS EQU 0
+SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02
+SDCard_BSPIM_TxStsReg__1__POS EQU 1
+SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL
+SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST
+SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04
+SDCard_BSPIM_TxStsReg__2__POS EQU 2
+SDCard_BSPIM_TxStsReg__3__MASK EQU 0x08
+SDCard_BSPIM_TxStsReg__3__POS EQU 3
+SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10
+SDCard_BSPIM_TxStsReg__4__POS EQU 4
+SDCard_BSPIM_TxStsReg__MASK EQU 0x1F
+SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB07_MSK
+SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL
+SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB07_ST
+
+/* SD_CS */
+SD_CS__0__INTTYPE EQU CYREG_PICU3_INTTYPE5
+SD_CS__0__MASK EQU 0x20
+SD_CS__0__PC EQU CYREG_PRT3_PC5
+SD_CS__0__PORT EQU 3
+SD_CS__0__SHIFT EQU 5
+SD_CS__AG EQU CYREG_PRT3_AG
+SD_CS__AMUX EQU CYREG_PRT3_AMUX
+SD_CS__BIE EQU CYREG_PRT3_BIE
+SD_CS__BIT_MASK EQU CYREG_PRT3_BIT_MASK
+SD_CS__BYP EQU CYREG_PRT3_BYP
+SD_CS__CTL EQU CYREG_PRT3_CTL
+SD_CS__DM0 EQU CYREG_PRT3_DM0
+SD_CS__DM1 EQU CYREG_PRT3_DM1
+SD_CS__DM2 EQU CYREG_PRT3_DM2
+SD_CS__DR EQU CYREG_PRT3_DR
+SD_CS__INP_DIS EQU CYREG_PRT3_INP_DIS
+SD_CS__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE
+SD_CS__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG
+SD_CS__LCD_EN EQU CYREG_PRT3_LCD_EN
+SD_CS__MASK EQU 0x20
+SD_CS__PORT EQU 3
+SD_CS__PRT EQU CYREG_PRT3_PRT
+SD_CS__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL
+SD_CS__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN
+SD_CS__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0
+SD_CS__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1
+SD_CS__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0
+SD_CS__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1
+SD_CS__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT
+SD_CS__PS EQU CYREG_PRT3_PS
+SD_CS__SHIFT EQU 5
+SD_CS__SLW EQU CYREG_PRT3_SLW
+
+/* SD_Data_Clk */
+SD_Data_Clk__CFG0 EQU CYREG_CLKDIST_DCFG0_CFG0
+SD_Data_Clk__CFG1 EQU CYREG_CLKDIST_DCFG0_CFG1
+SD_Data_Clk__CFG2 EQU CYREG_CLKDIST_DCFG0_CFG2
+SD_Data_Clk__CFG2_SRC_SEL_MASK EQU 0x07
+SD_Data_Clk__INDEX EQU 0x00
+SD_Data_Clk__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2
+SD_Data_Clk__PM_ACT_MSK EQU 0x01
+SD_Data_Clk__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2
+SD_Data_Clk__PM_STBY_MSK EQU 0x01
+
+/* SD_MISO */
+SD_MISO__0__INTTYPE EQU CYREG_PICU3_INTTYPE2
+SD_MISO__0__MASK EQU 0x04
+SD_MISO__0__PC EQU CYREG_PRT3_PC2
+SD_MISO__0__PORT EQU 3
+SD_MISO__0__SHIFT EQU 2
+SD_MISO__AG EQU CYREG_PRT3_AG
+SD_MISO__AMUX EQU CYREG_PRT3_AMUX
+SD_MISO__BIE EQU CYREG_PRT3_BIE
+SD_MISO__BIT_MASK EQU CYREG_PRT3_BIT_MASK
+SD_MISO__BYP EQU CYREG_PRT3_BYP
+SD_MISO__CTL EQU CYREG_PRT3_CTL
+SD_MISO__DM0 EQU CYREG_PRT3_DM0
+SD_MISO__DM1 EQU CYREG_PRT3_DM1
+SD_MISO__DM2 EQU CYREG_PRT3_DM2
+SD_MISO__DR EQU CYREG_PRT3_DR
+SD_MISO__INP_DIS EQU CYREG_PRT3_INP_DIS
+SD_MISO__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE
+SD_MISO__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG
+SD_MISO__LCD_EN EQU CYREG_PRT3_LCD_EN
+SD_MISO__MASK EQU 0x04
+SD_MISO__PORT EQU 3
+SD_MISO__PRT EQU CYREG_PRT3_PRT
+SD_MISO__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL
+SD_MISO__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN
+SD_MISO__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0
+SD_MISO__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1
+SD_MISO__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0
+SD_MISO__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1
+SD_MISO__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT
+SD_MISO__PS EQU CYREG_PRT3_PS
+SD_MISO__SHIFT EQU 2
+SD_MISO__SLW EQU CYREG_PRT3_SLW
+
+/* SD_MOSI */
+SD_MOSI__0__INTTYPE EQU CYREG_PICU3_INTTYPE4
+SD_MOSI__0__MASK EQU 0x10
+SD_MOSI__0__PC EQU CYREG_PRT3_PC4
+SD_MOSI__0__PORT EQU 3
+SD_MOSI__0__SHIFT EQU 4
+SD_MOSI__AG EQU CYREG_PRT3_AG
+SD_MOSI__AMUX EQU CYREG_PRT3_AMUX
+SD_MOSI__BIE EQU CYREG_PRT3_BIE
+SD_MOSI__BIT_MASK EQU CYREG_PRT3_BIT_MASK
+SD_MOSI__BYP EQU CYREG_PRT3_BYP
+SD_MOSI__CTL EQU CYREG_PRT3_CTL
+SD_MOSI__DM0 EQU CYREG_PRT3_DM0
+SD_MOSI__DM1 EQU CYREG_PRT3_DM1
+SD_MOSI__DM2 EQU CYREG_PRT3_DM2
+SD_MOSI__DR EQU CYREG_PRT3_DR
+SD_MOSI__INP_DIS EQU CYREG_PRT3_INP_DIS
+SD_MOSI__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE
+SD_MOSI__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG
+SD_MOSI__LCD_EN EQU CYREG_PRT3_LCD_EN
+SD_MOSI__MASK EQU 0x10
+SD_MOSI__PORT EQU 3
+SD_MOSI__PRT EQU CYREG_PRT3_PRT
+SD_MOSI__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL
+SD_MOSI__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN
+SD_MOSI__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0
+SD_MOSI__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1
+SD_MOSI__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0
+SD_MOSI__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1
+SD_MOSI__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT
+SD_MOSI__PS EQU CYREG_PRT3_PS
+SD_MOSI__SHIFT EQU 4
+SD_MOSI__SLW EQU CYREG_PRT3_SLW
+
+/* SD_RX_DMA */
+SD_RX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0
+SD_RX_DMA__DRQ_NUMBER EQU 2
+SD_RX_DMA__NUMBEROF_TDS EQU 0
+SD_RX_DMA__PRIORITY EQU 0
+SD_RX_DMA__TERMIN_EN EQU 0
+SD_RX_DMA__TERMIN_SEL EQU 0
+SD_RX_DMA__TERMOUT0_EN EQU 1
+SD_RX_DMA__TERMOUT0_SEL EQU 2
+SD_RX_DMA__TERMOUT1_EN EQU 0
+SD_RX_DMA__TERMOUT1_SEL EQU 0
+SD_RX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
+SD_RX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
+SD_RX_DMA_COMPLETE__INTC_MASK EQU 0x20
+SD_RX_DMA_COMPLETE__INTC_NUMBER EQU 5
+SD_RX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7
+SD_RX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_5
+SD_RX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
+SD_RX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
+
+/* SD_SCK */
+SD_SCK__0__INTTYPE EQU CYREG_PICU3_INTTYPE3
+SD_SCK__0__MASK EQU 0x08
+SD_SCK__0__PC EQU CYREG_PRT3_PC3
+SD_SCK__0__PORT EQU 3
+SD_SCK__0__SHIFT EQU 3
+SD_SCK__AG EQU CYREG_PRT3_AG
+SD_SCK__AMUX EQU CYREG_PRT3_AMUX
+SD_SCK__BIE EQU CYREG_PRT3_BIE
+SD_SCK__BIT_MASK EQU CYREG_PRT3_BIT_MASK
+SD_SCK__BYP EQU CYREG_PRT3_BYP
+SD_SCK__CTL EQU CYREG_PRT3_CTL
+SD_SCK__DM0 EQU CYREG_PRT3_DM0
+SD_SCK__DM1 EQU CYREG_PRT3_DM1
+SD_SCK__DM2 EQU CYREG_PRT3_DM2
+SD_SCK__DR EQU CYREG_PRT3_DR
+SD_SCK__INP_DIS EQU CYREG_PRT3_INP_DIS
+SD_SCK__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE
+SD_SCK__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG
+SD_SCK__LCD_EN EQU CYREG_PRT3_LCD_EN
+SD_SCK__MASK EQU 0x08
+SD_SCK__PORT EQU 3
+SD_SCK__PRT EQU CYREG_PRT3_PRT
+SD_SCK__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL
+SD_SCK__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN
+SD_SCK__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0
+SD_SCK__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1
+SD_SCK__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0
+SD_SCK__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1
+SD_SCK__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT
+SD_SCK__PS EQU CYREG_PRT3_PS
+SD_SCK__SHIFT EQU 3
+SD_SCK__SLW EQU CYREG_PRT3_SLW
+
+/* SD_TX_DMA */
+SD_TX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0
+SD_TX_DMA__DRQ_NUMBER EQU 3
+SD_TX_DMA__NUMBEROF_TDS EQU 0
+SD_TX_DMA__PRIORITY EQU 1
+SD_TX_DMA__TERMIN_EN EQU 0
+SD_TX_DMA__TERMIN_SEL EQU 0
+SD_TX_DMA__TERMOUT0_EN EQU 1
+SD_TX_DMA__TERMOUT0_SEL EQU 3
+SD_TX_DMA__TERMOUT1_EN EQU 0
+SD_TX_DMA__TERMOUT1_SEL EQU 0
+SD_TX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
+SD_TX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
+SD_TX_DMA_COMPLETE__INTC_MASK EQU 0x40
+SD_TX_DMA_COMPLETE__INTC_NUMBER EQU 6
+SD_TX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7
+SD_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_6
+SD_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
+SD_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
+
+/* TERM_EN */
+TERM_EN__0__INTTYPE EQU CYREG_PICU15_INTTYPE3
+TERM_EN__0__MASK EQU 0x08
+TERM_EN__0__PC EQU CYREG_IO_PC_PRT15_PC3
+TERM_EN__0__PORT EQU 15
+TERM_EN__0__SHIFT EQU 3
+TERM_EN__AG EQU CYREG_PRT15_AG
+TERM_EN__AMUX EQU CYREG_PRT15_AMUX
+TERM_EN__BIE EQU CYREG_PRT15_BIE
+TERM_EN__BIT_MASK EQU CYREG_PRT15_BIT_MASK
+TERM_EN__BYP EQU CYREG_PRT15_BYP
+TERM_EN__CTL EQU CYREG_PRT15_CTL
+TERM_EN__DM0 EQU CYREG_PRT15_DM0
+TERM_EN__DM1 EQU CYREG_PRT15_DM1
+TERM_EN__DM2 EQU CYREG_PRT15_DM2
+TERM_EN__DR EQU CYREG_PRT15_DR
+TERM_EN__INP_DIS EQU CYREG_PRT15_INP_DIS
+TERM_EN__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU15_BASE
+TERM_EN__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG
+TERM_EN__LCD_EN EQU CYREG_PRT15_LCD_EN
+TERM_EN__MASK EQU 0x08
+TERM_EN__PORT EQU 15
+TERM_EN__PRT EQU CYREG_PRT15_PRT
+TERM_EN__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL
+TERM_EN__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN
+TERM_EN__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0
+TERM_EN__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1
+TERM_EN__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0
+TERM_EN__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1
+TERM_EN__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT
+TERM_EN__PS EQU CYREG_PRT15_PS
+TERM_EN__SHIFT EQU 3
+TERM_EN__SLW EQU CYREG_PRT15_SLW
+
+/* USBFS */
+USBFS_arb_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
+USBFS_arb_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
+USBFS_arb_int__INTC_MASK EQU 0x400000
+USBFS_arb_int__INTC_NUMBER EQU 22
+USBFS_arb_int__INTC_PRIOR_NUM EQU 6
+USBFS_arb_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_22
+USBFS_arb_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
+USBFS_arb_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
+USBFS_bus_reset__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
+USBFS_bus_reset__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
+USBFS_bus_reset__INTC_MASK EQU 0x800000
+USBFS_bus_reset__INTC_NUMBER EQU 23
+USBFS_bus_reset__INTC_PRIOR_NUM EQU 7
+USBFS_bus_reset__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_23
+USBFS_bus_reset__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
+USBFS_bus_reset__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
+USBFS_Dm__0__INTTYPE EQU CYREG_PICU15_INTTYPE7
+USBFS_Dm__0__MASK EQU 0x80
+USBFS_Dm__0__PC EQU CYREG_IO_PC_PRT15_7_6_PC1
+USBFS_Dm__0__PORT EQU 15
+USBFS_Dm__0__SHIFT EQU 7
+USBFS_Dm__AG EQU CYREG_PRT15_AG
+USBFS_Dm__AMUX EQU CYREG_PRT15_AMUX
+USBFS_Dm__BIE EQU CYREG_PRT15_BIE
+USBFS_Dm__BIT_MASK EQU CYREG_PRT15_BIT_MASK
+USBFS_Dm__BYP EQU CYREG_PRT15_BYP
+USBFS_Dm__CTL EQU CYREG_PRT15_CTL
+USBFS_Dm__DM0 EQU CYREG_PRT15_DM0
+USBFS_Dm__DM1 EQU CYREG_PRT15_DM1
+USBFS_Dm__DM2 EQU CYREG_PRT15_DM2
+USBFS_Dm__DR EQU CYREG_PRT15_DR
+USBFS_Dm__INP_DIS EQU CYREG_PRT15_INP_DIS
+USBFS_Dm__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU15_BASE
+USBFS_Dm__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG
+USBFS_Dm__LCD_EN EQU CYREG_PRT15_LCD_EN
+USBFS_Dm__MASK EQU 0x80
+USBFS_Dm__PORT EQU 15
+USBFS_Dm__PRT EQU CYREG_PRT15_PRT
+USBFS_Dm__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL
+USBFS_Dm__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN
+USBFS_Dm__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0
+USBFS_Dm__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1
+USBFS_Dm__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0
+USBFS_Dm__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1
+USBFS_Dm__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT
+USBFS_Dm__PS EQU CYREG_PRT15_PS
+USBFS_Dm__SHIFT EQU 7
+USBFS_Dm__SLW EQU CYREG_PRT15_SLW
+USBFS_Dp__0__INTTYPE EQU CYREG_PICU15_INTTYPE6
+USBFS_Dp__0__MASK EQU 0x40
+USBFS_Dp__0__PC EQU CYREG_IO_PC_PRT15_7_6_PC0
+USBFS_Dp__0__PORT EQU 15
+USBFS_Dp__0__SHIFT EQU 6
+USBFS_Dp__AG EQU CYREG_PRT15_AG
+USBFS_Dp__AMUX EQU CYREG_PRT15_AMUX
+USBFS_Dp__BIE EQU CYREG_PRT15_BIE
+USBFS_Dp__BIT_MASK EQU CYREG_PRT15_BIT_MASK
+USBFS_Dp__BYP EQU CYREG_PRT15_BYP
+USBFS_Dp__CTL EQU CYREG_PRT15_CTL
+USBFS_Dp__DM0 EQU CYREG_PRT15_DM0
+USBFS_Dp__DM1 EQU CYREG_PRT15_DM1
+USBFS_Dp__DM2 EQU CYREG_PRT15_DM2
+USBFS_Dp__DR EQU CYREG_PRT15_DR
+USBFS_Dp__INP_DIS EQU CYREG_PRT15_INP_DIS
+USBFS_Dp__INTSTAT EQU CYREG_PICU15_INTSTAT
+USBFS_Dp__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU15_BASE
+USBFS_Dp__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG
+USBFS_Dp__LCD_EN EQU CYREG_PRT15_LCD_EN
+USBFS_Dp__MASK EQU 0x40
+USBFS_Dp__PORT EQU 15
+USBFS_Dp__PRT EQU CYREG_PRT15_PRT
+USBFS_Dp__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL
+USBFS_Dp__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN
+USBFS_Dp__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0
+USBFS_Dp__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1
+USBFS_Dp__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0
+USBFS_Dp__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1
+USBFS_Dp__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT
+USBFS_Dp__PS EQU CYREG_PRT15_PS
+USBFS_Dp__SHIFT EQU 6
+USBFS_Dp__SLW EQU CYREG_PRT15_SLW
+USBFS_Dp__SNAP EQU CYREG_PICU_15_SNAP_15
+USBFS_dp_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
+USBFS_dp_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
+USBFS_dp_int__INTC_MASK EQU 0x1000
+USBFS_dp_int__INTC_NUMBER EQU 12
+USBFS_dp_int__INTC_PRIOR_NUM EQU 7
+USBFS_dp_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_12
+USBFS_dp_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
+USBFS_dp_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
+USBFS_ep_0__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
+USBFS_ep_0__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
+USBFS_ep_0__INTC_MASK EQU 0x1000000
+USBFS_ep_0__INTC_NUMBER EQU 24
+USBFS_ep_0__INTC_PRIOR_NUM EQU 7
+USBFS_ep_0__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_24
+USBFS_ep_0__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
+USBFS_ep_0__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
+USBFS_ep_1__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
+USBFS_ep_1__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
+USBFS_ep_1__INTC_MASK EQU 0x80
+USBFS_ep_1__INTC_NUMBER EQU 7
+USBFS_ep_1__INTC_PRIOR_NUM EQU 7
+USBFS_ep_1__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_7
+USBFS_ep_1__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
+USBFS_ep_1__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
+USBFS_ep_2__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
+USBFS_ep_2__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
+USBFS_ep_2__INTC_MASK EQU 0x100
+USBFS_ep_2__INTC_NUMBER EQU 8
+USBFS_ep_2__INTC_PRIOR_NUM EQU 7
+USBFS_ep_2__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_8
+USBFS_ep_2__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
+USBFS_ep_2__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
+USBFS_ep_3__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
+USBFS_ep_3__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
+USBFS_ep_3__INTC_MASK EQU 0x200
+USBFS_ep_3__INTC_NUMBER EQU 9
+USBFS_ep_3__INTC_PRIOR_NUM EQU 7
+USBFS_ep_3__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_9
+USBFS_ep_3__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
+USBFS_ep_3__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
+USBFS_ep_4__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
+USBFS_ep_4__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
+USBFS_ep_4__INTC_MASK EQU 0x400
+USBFS_ep_4__INTC_NUMBER EQU 10
+USBFS_ep_4__INTC_PRIOR_NUM EQU 7
+USBFS_ep_4__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_10
+USBFS_ep_4__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
+USBFS_ep_4__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
+USBFS_sof_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
+USBFS_sof_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
+USBFS_sof_int__INTC_MASK EQU 0x200000
+USBFS_sof_int__INTC_NUMBER EQU 21
+USBFS_sof_int__INTC_PRIOR_NUM EQU 7
+USBFS_sof_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_21
+USBFS_sof_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
+USBFS_sof_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
+USBFS_USB__ARB_CFG EQU CYREG_USB_ARB_CFG
+USBFS_USB__ARB_EP1_CFG EQU CYREG_USB_ARB_EP1_CFG
+USBFS_USB__ARB_EP1_INT_EN EQU CYREG_USB_ARB_EP1_INT_EN
+USBFS_USB__ARB_EP1_SR EQU CYREG_USB_ARB_EP1_SR
+USBFS_USB__ARB_EP2_CFG EQU CYREG_USB_ARB_EP2_CFG
+USBFS_USB__ARB_EP2_INT_EN EQU CYREG_USB_ARB_EP2_INT_EN
+USBFS_USB__ARB_EP2_SR EQU CYREG_USB_ARB_EP2_SR
+USBFS_USB__ARB_EP3_CFG EQU CYREG_USB_ARB_EP3_CFG
+USBFS_USB__ARB_EP3_INT_EN EQU CYREG_USB_ARB_EP3_INT_EN
+USBFS_USB__ARB_EP3_SR EQU CYREG_USB_ARB_EP3_SR
+USBFS_USB__ARB_EP4_CFG EQU CYREG_USB_ARB_EP4_CFG
+USBFS_USB__ARB_EP4_INT_EN EQU CYREG_USB_ARB_EP4_INT_EN
+USBFS_USB__ARB_EP4_SR EQU CYREG_USB_ARB_EP4_SR
+USBFS_USB__ARB_EP5_CFG EQU CYREG_USB_ARB_EP5_CFG
+USBFS_USB__ARB_EP5_INT_EN EQU CYREG_USB_ARB_EP5_INT_EN
+USBFS_USB__ARB_EP5_SR EQU CYREG_USB_ARB_EP5_SR
+USBFS_USB__ARB_EP6_CFG EQU CYREG_USB_ARB_EP6_CFG
+USBFS_USB__ARB_EP6_INT_EN EQU CYREG_USB_ARB_EP6_INT_EN
+USBFS_USB__ARB_EP6_SR EQU CYREG_USB_ARB_EP6_SR
+USBFS_USB__ARB_EP7_CFG EQU CYREG_USB_ARB_EP7_CFG
+USBFS_USB__ARB_EP7_INT_EN EQU CYREG_USB_ARB_EP7_INT_EN
+USBFS_USB__ARB_EP7_SR EQU CYREG_USB_ARB_EP7_SR
+USBFS_USB__ARB_EP8_CFG EQU CYREG_USB_ARB_EP8_CFG
+USBFS_USB__ARB_EP8_INT_EN EQU CYREG_USB_ARB_EP8_INT_EN
+USBFS_USB__ARB_EP8_SR EQU CYREG_USB_ARB_EP8_SR
+USBFS_USB__ARB_INT_EN EQU CYREG_USB_ARB_INT_EN
+USBFS_USB__ARB_INT_SR EQU CYREG_USB_ARB_INT_SR
+USBFS_USB__ARB_RW1_DR EQU CYREG_USB_ARB_RW1_DR
+USBFS_USB__ARB_RW1_RA EQU CYREG_USB_ARB_RW1_RA
+USBFS_USB__ARB_RW1_RA_MSB EQU CYREG_USB_ARB_RW1_RA_MSB
+USBFS_USB__ARB_RW1_WA EQU CYREG_USB_ARB_RW1_WA
+USBFS_USB__ARB_RW1_WA_MSB EQU CYREG_USB_ARB_RW1_WA_MSB
+USBFS_USB__ARB_RW2_DR EQU CYREG_USB_ARB_RW2_DR
+USBFS_USB__ARB_RW2_RA EQU CYREG_USB_ARB_RW2_RA
+USBFS_USB__ARB_RW2_RA_MSB EQU CYREG_USB_ARB_RW2_RA_MSB
+USBFS_USB__ARB_RW2_WA EQU CYREG_USB_ARB_RW2_WA
+USBFS_USB__ARB_RW2_WA_MSB EQU CYREG_USB_ARB_RW2_WA_MSB
+USBFS_USB__ARB_RW3_DR EQU CYREG_USB_ARB_RW3_DR
+USBFS_USB__ARB_RW3_RA EQU CYREG_USB_ARB_RW3_RA
+USBFS_USB__ARB_RW3_RA_MSB EQU CYREG_USB_ARB_RW3_RA_MSB
+USBFS_USB__ARB_RW3_WA EQU CYREG_USB_ARB_RW3_WA
+USBFS_USB__ARB_RW3_WA_MSB EQU CYREG_USB_ARB_RW3_WA_MSB
+USBFS_USB__ARB_RW4_DR EQU CYREG_USB_ARB_RW4_DR
+USBFS_USB__ARB_RW4_RA EQU CYREG_USB_ARB_RW4_RA
+USBFS_USB__ARB_RW4_RA_MSB EQU CYREG_USB_ARB_RW4_RA_MSB
+USBFS_USB__ARB_RW4_WA EQU CYREG_USB_ARB_RW4_WA
+USBFS_USB__ARB_RW4_WA_MSB EQU CYREG_USB_ARB_RW4_WA_MSB
+USBFS_USB__ARB_RW5_DR EQU CYREG_USB_ARB_RW5_DR
+USBFS_USB__ARB_RW5_RA EQU CYREG_USB_ARB_RW5_RA
+USBFS_USB__ARB_RW5_RA_MSB EQU CYREG_USB_ARB_RW5_RA_MSB
+USBFS_USB__ARB_RW5_WA EQU CYREG_USB_ARB_RW5_WA
+USBFS_USB__ARB_RW5_WA_MSB EQU CYREG_USB_ARB_RW5_WA_MSB
+USBFS_USB__ARB_RW6_DR EQU CYREG_USB_ARB_RW6_DR
+USBFS_USB__ARB_RW6_RA EQU CYREG_USB_ARB_RW6_RA
+USBFS_USB__ARB_RW6_RA_MSB EQU CYREG_USB_ARB_RW6_RA_MSB
+USBFS_USB__ARB_RW6_WA EQU CYREG_USB_ARB_RW6_WA
+USBFS_USB__ARB_RW6_WA_MSB EQU CYREG_USB_ARB_RW6_WA_MSB
+USBFS_USB__ARB_RW7_DR EQU CYREG_USB_ARB_RW7_DR
+USBFS_USB__ARB_RW7_RA EQU CYREG_USB_ARB_RW7_RA
+USBFS_USB__ARB_RW7_RA_MSB EQU CYREG_USB_ARB_RW7_RA_MSB
+USBFS_USB__ARB_RW7_WA EQU CYREG_USB_ARB_RW7_WA
+USBFS_USB__ARB_RW7_WA_MSB EQU CYREG_USB_ARB_RW7_WA_MSB
+USBFS_USB__ARB_RW8_DR EQU CYREG_USB_ARB_RW8_DR
+USBFS_USB__ARB_RW8_RA EQU CYREG_USB_ARB_RW8_RA
+USBFS_USB__ARB_RW8_RA_MSB EQU CYREG_USB_ARB_RW8_RA_MSB
+USBFS_USB__ARB_RW8_WA EQU CYREG_USB_ARB_RW8_WA
+USBFS_USB__ARB_RW8_WA_MSB EQU CYREG_USB_ARB_RW8_WA_MSB
+USBFS_USB__BUF_SIZE EQU CYREG_USB_BUF_SIZE
+USBFS_USB__BUS_RST_CNT EQU CYREG_USB_BUS_RST_CNT
+USBFS_USB__CR0 EQU CYREG_USB_CR0
+USBFS_USB__CR1 EQU CYREG_USB_CR1
+USBFS_USB__CWA EQU CYREG_USB_CWA
+USBFS_USB__CWA_MSB EQU CYREG_USB_CWA_MSB
+USBFS_USB__DMA_THRES EQU CYREG_USB_DMA_THRES
+USBFS_USB__DMA_THRES_MSB EQU CYREG_USB_DMA_THRES_MSB
+USBFS_USB__DYN_RECONFIG EQU CYREG_USB_DYN_RECONFIG
+USBFS_USB__EP_ACTIVE EQU CYREG_USB_EP_ACTIVE
+USBFS_USB__EP_TYPE EQU CYREG_USB_EP_TYPE
+USBFS_USB__EP0_CNT EQU CYREG_USB_EP0_CNT
+USBFS_USB__EP0_CR EQU CYREG_USB_EP0_CR
+USBFS_USB__EP0_DR0 EQU CYREG_USB_EP0_DR0
+USBFS_USB__EP0_DR1 EQU CYREG_USB_EP0_DR1
+USBFS_USB__EP0_DR2 EQU CYREG_USB_EP0_DR2
+USBFS_USB__EP0_DR3 EQU CYREG_USB_EP0_DR3
+USBFS_USB__EP0_DR4 EQU CYREG_USB_EP0_DR4
+USBFS_USB__EP0_DR5 EQU CYREG_USB_EP0_DR5
+USBFS_USB__EP0_DR6 EQU CYREG_USB_EP0_DR6
+USBFS_USB__EP0_DR7 EQU CYREG_USB_EP0_DR7
+USBFS_USB__MEM_DATA EQU CYREG_USB_MEM_DATA_MBASE
+USBFS_USB__PM_ACT_CFG EQU CYREG_PM_ACT_CFG5
+USBFS_USB__PM_ACT_MSK EQU 0x01
+USBFS_USB__PM_STBY_CFG EQU CYREG_PM_STBY_CFG5
+USBFS_USB__PM_STBY_MSK EQU 0x01
+USBFS_USB__SIE_EP_INT_EN EQU CYREG_USB_SIE_EP_INT_EN
+USBFS_USB__SIE_EP_INT_SR EQU CYREG_USB_SIE_EP_INT_SR
+USBFS_USB__SIE_EP1_CNT0 EQU CYREG_USB_SIE_EP1_CNT0
+USBFS_USB__SIE_EP1_CNT1 EQU CYREG_USB_SIE_EP1_CNT1
+USBFS_USB__SIE_EP1_CR0 EQU CYREG_USB_SIE_EP1_CR0
+USBFS_USB__SIE_EP2_CNT0 EQU CYREG_USB_SIE_EP2_CNT0
+USBFS_USB__SIE_EP2_CNT1 EQU CYREG_USB_SIE_EP2_CNT1
+USBFS_USB__SIE_EP2_CR0 EQU CYREG_USB_SIE_EP2_CR0
+USBFS_USB__SIE_EP3_CNT0 EQU CYREG_USB_SIE_EP3_CNT0
+USBFS_USB__SIE_EP3_CNT1 EQU CYREG_USB_SIE_EP3_CNT1
+USBFS_USB__SIE_EP3_CR0 EQU CYREG_USB_SIE_EP3_CR0
+USBFS_USB__SIE_EP4_CNT0 EQU CYREG_USB_SIE_EP4_CNT0
+USBFS_USB__SIE_EP4_CNT1 EQU CYREG_USB_SIE_EP4_CNT1
+USBFS_USB__SIE_EP4_CR0 EQU CYREG_USB_SIE_EP4_CR0
+USBFS_USB__SIE_EP5_CNT0 EQU CYREG_USB_SIE_EP5_CNT0
+USBFS_USB__SIE_EP5_CNT1 EQU CYREG_USB_SIE_EP5_CNT1
+USBFS_USB__SIE_EP5_CR0 EQU CYREG_USB_SIE_EP5_CR0
+USBFS_USB__SIE_EP6_CNT0 EQU CYREG_USB_SIE_EP6_CNT0
+USBFS_USB__SIE_EP6_CNT1 EQU CYREG_USB_SIE_EP6_CNT1
+USBFS_USB__SIE_EP6_CR0 EQU CYREG_USB_SIE_EP6_CR0
+USBFS_USB__SIE_EP7_CNT0 EQU CYREG_USB_SIE_EP7_CNT0
+USBFS_USB__SIE_EP7_CNT1 EQU CYREG_USB_SIE_EP7_CNT1
+USBFS_USB__SIE_EP7_CR0 EQU CYREG_USB_SIE_EP7_CR0
+USBFS_USB__SIE_EP8_CNT0 EQU CYREG_USB_SIE_EP8_CNT0
+USBFS_USB__SIE_EP8_CNT1 EQU CYREG_USB_SIE_EP8_CNT1
+USBFS_USB__SIE_EP8_CR0 EQU CYREG_USB_SIE_EP8_CR0
+USBFS_USB__SOF0 EQU CYREG_USB_SOF0
+USBFS_USB__SOF1 EQU CYREG_USB_SOF1
+USBFS_USB__USB_CLK_EN EQU CYREG_USB_USB_CLK_EN
+USBFS_USB__USBIO_CR0 EQU CYREG_USB_USBIO_CR0
+USBFS_USB__USBIO_CR1 EQU CYREG_USB_USBIO_CR1
+
 /* scsiTarget */
 scsiTarget_datapath__16BIT_A0_REG EQU CYREG_B0_UDB00_01_A0
 scsiTarget_datapath__16BIT_A1_REG EQU CYREG_B0_UDB00_01_A1
@@ -2415,89 +2579,6 @@ scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB15_MSK
 scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB15_ACTL
 scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB15_ST
 
-/* Debug_Timer_Interrupt */
-Debug_Timer_Interrupt__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
-Debug_Timer_Interrupt__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-Debug_Timer_Interrupt__INTC_MASK EQU 0x02
-Debug_Timer_Interrupt__INTC_NUMBER EQU 1
-Debug_Timer_Interrupt__INTC_PRIOR_NUM EQU 7
-Debug_Timer_Interrupt__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_1
-Debug_Timer_Interrupt__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
-Debug_Timer_Interrupt__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
-
-/* Debug_Timer_TimerHW */
-Debug_Timer_TimerHW__CAP0 EQU CYREG_TMR0_CAP0
-Debug_Timer_TimerHW__CAP1 EQU CYREG_TMR0_CAP1
-Debug_Timer_TimerHW__CFG0 EQU CYREG_TMR0_CFG0
-Debug_Timer_TimerHW__CFG1 EQU CYREG_TMR0_CFG1
-Debug_Timer_TimerHW__CFG2 EQU CYREG_TMR0_CFG2
-Debug_Timer_TimerHW__CNT_CMP0 EQU CYREG_TMR0_CNT_CMP0
-Debug_Timer_TimerHW__CNT_CMP1 EQU CYREG_TMR0_CNT_CMP1
-Debug_Timer_TimerHW__PER0 EQU CYREG_TMR0_PER0
-Debug_Timer_TimerHW__PER1 EQU CYREG_TMR0_PER1
-Debug_Timer_TimerHW__PM_ACT_CFG EQU CYREG_PM_ACT_CFG3
-Debug_Timer_TimerHW__PM_ACT_MSK EQU 0x01
-Debug_Timer_TimerHW__PM_STBY_CFG EQU CYREG_PM_STBY_CFG3
-Debug_Timer_TimerHW__PM_STBY_MSK EQU 0x01
-Debug_Timer_TimerHW__RT0 EQU CYREG_TMR0_RT0
-Debug_Timer_TimerHW__RT1 EQU CYREG_TMR0_RT1
-Debug_Timer_TimerHW__SR0 EQU CYREG_TMR0_SR0
-
-/* SCSI_RX_DMA */
-SCSI_RX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0
-SCSI_RX_DMA__DRQ_NUMBER EQU 0
-SCSI_RX_DMA__NUMBEROF_TDS EQU 0
-SCSI_RX_DMA__PRIORITY EQU 2
-SCSI_RX_DMA__TERMIN_EN EQU 0
-SCSI_RX_DMA__TERMIN_SEL EQU 0
-SCSI_RX_DMA__TERMOUT0_EN EQU 1
-SCSI_RX_DMA__TERMOUT0_SEL EQU 0
-SCSI_RX_DMA__TERMOUT1_EN EQU 0
-SCSI_RX_DMA__TERMOUT1_SEL EQU 0
-
-/* SCSI_RX_DMA_COMPLETE */
-SCSI_RX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
-SCSI_RX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-SCSI_RX_DMA_COMPLETE__INTC_MASK EQU 0x01
-SCSI_RX_DMA_COMPLETE__INTC_NUMBER EQU 0
-SCSI_RX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7
-SCSI_RX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_0
-SCSI_RX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
-SCSI_RX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
-
-/* SCSI_TX_DMA */
-SCSI_TX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0
-SCSI_TX_DMA__DRQ_NUMBER EQU 1
-SCSI_TX_DMA__NUMBEROF_TDS EQU 0
-SCSI_TX_DMA__PRIORITY EQU 2
-SCSI_TX_DMA__TERMIN_EN EQU 0
-SCSI_TX_DMA__TERMIN_SEL EQU 0
-SCSI_TX_DMA__TERMOUT0_EN EQU 1
-SCSI_TX_DMA__TERMOUT0_SEL EQU 1
-SCSI_TX_DMA__TERMOUT1_EN EQU 0
-SCSI_TX_DMA__TERMOUT1_SEL EQU 0
-
-/* SCSI_TX_DMA_COMPLETE */
-SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
-SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-SCSI_TX_DMA_COMPLETE__INTC_MASK EQU 0x10
-SCSI_TX_DMA_COMPLETE__INTC_NUMBER EQU 4
-SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7
-SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_4
-SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
-SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
-
-/* SD_Data_Clk */
-SD_Data_Clk__CFG0 EQU CYREG_CLKDIST_DCFG0_CFG0
-SD_Data_Clk__CFG1 EQU CYREG_CLKDIST_DCFG0_CFG1
-SD_Data_Clk__CFG2 EQU CYREG_CLKDIST_DCFG0_CFG2
-SD_Data_Clk__CFG2_SRC_SEL_MASK EQU 0x07
-SD_Data_Clk__INDEX EQU 0x00
-SD_Data_Clk__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2
-SD_Data_Clk__PM_ACT_MSK EQU 0x01
-SD_Data_Clk__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2
-SD_Data_Clk__PM_STBY_MSK EQU 0x01
-
 /* timer_clock */
 timer_clock__CFG0 EQU CYREG_CLKDIST_DCFG2_CFG0
 timer_clock__CFG1 EQU CYREG_CLKDIST_DCFG2_CFG1
@@ -2509,154 +2590,53 @@ timer_clock__PM_ACT_MSK EQU 0x04
 timer_clock__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2
 timer_clock__PM_STBY_MSK EQU 0x04
 
-/* SCSI_RST_ISR */
-SCSI_RST_ISR__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
-SCSI_RST_ISR__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-SCSI_RST_ISR__INTC_MASK EQU 0x04
-SCSI_RST_ISR__INTC_NUMBER EQU 2
-SCSI_RST_ISR__INTC_PRIOR_NUM EQU 7
-SCSI_RST_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_2
-SCSI_RST_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
-SCSI_RST_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
-
-/* SCSI_SEL_ISR */
-SCSI_SEL_ISR__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
-SCSI_SEL_ISR__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-SCSI_SEL_ISR__INTC_MASK EQU 0x08
-SCSI_SEL_ISR__INTC_NUMBER EQU 3
-SCSI_SEL_ISR__INTC_PRIOR_NUM EQU 7
-SCSI_SEL_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_3
-SCSI_SEL_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
-SCSI_SEL_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
-
-/* SCSI_Filtered */
-SCSI_Filtered_sts_sts_reg__0__MASK EQU 0x01
-SCSI_Filtered_sts_sts_reg__0__POS EQU 0
-SCSI_Filtered_sts_sts_reg__1__MASK EQU 0x02
-SCSI_Filtered_sts_sts_reg__1__POS EQU 1
-SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL
-SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB11_12_ST
-SCSI_Filtered_sts_sts_reg__2__MASK EQU 0x04
-SCSI_Filtered_sts_sts_reg__2__POS EQU 2
-SCSI_Filtered_sts_sts_reg__3__MASK EQU 0x08
-SCSI_Filtered_sts_sts_reg__3__POS EQU 3
-SCSI_Filtered_sts_sts_reg__4__MASK EQU 0x10
-SCSI_Filtered_sts_sts_reg__4__POS EQU 4
-SCSI_Filtered_sts_sts_reg__MASK EQU 0x1F
-SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB11_MSK
-SCSI_Filtered_sts_sts_reg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
-SCSI_Filtered_sts_sts_reg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
-SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL
-SCSI_Filtered_sts_sts_reg__STATUS_CNT_REG EQU CYREG_B0_UDB11_ST_CTL
-SCSI_Filtered_sts_sts_reg__STATUS_CONTROL_REG EQU CYREG_B0_UDB11_ST_CTL
-SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB11_ST
-
-/* SCSI_CTL_PHASE */
-SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01
-SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS EQU 0
-SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK EQU 0x02
-SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS EQU 1
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB02_03_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB02_03_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB02_03_MSK
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB02_03_MSK
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK
-SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK EQU 0x04
-SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS EQU 2
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB02_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB02_ST_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB02_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB02_ST_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__MASK EQU 0x07
-SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB02_MSK
-
-/* SCSI_Glitch_Ctl */
-SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01
-SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS EQU 0
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB05_06_CTL
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB05_06_CTL
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB05_06_MSK
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB05_06_MSK
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK
-SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL
-SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB05_CTL
-SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB05_ST_CTL
-SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB05_CTL
-SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB05_ST_CTL
-SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK EQU 0x01
-SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL
-SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL
-SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB05_MSK
-
-/* SCSI_Parity_Error */
-SCSI_Parity_Error_sts_sts_reg__0__MASK EQU 0x01
-SCSI_Parity_Error_sts_sts_reg__0__POS EQU 0
-SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL
-SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB02_03_ST
-SCSI_Parity_Error_sts_sts_reg__MASK EQU 0x01
-SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB02_MSK
-SCSI_Parity_Error_sts_sts_reg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL
-SCSI_Parity_Error_sts_sts_reg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL
-SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL
-SCSI_Parity_Error_sts_sts_reg__STATUS_CNT_REG EQU CYREG_B0_UDB02_ST_CTL
-SCSI_Parity_Error_sts_sts_reg__STATUS_CONTROL_REG EQU CYREG_B0_UDB02_ST_CTL
-SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB02_ST
-
 /* Miscellaneous */
 BCLK__BUS_CLK__HZ EQU 50000000
 BCLK__BUS_CLK__KHZ EQU 50000
 BCLK__BUS_CLK__MHZ EQU 50
 CYDEV_CHIP_DIE_LEOPARD EQU 1
-CYDEV_CHIP_DIE_PSOC4A EQU 12
-CYDEV_CHIP_DIE_PSOC5LP EQU 19
-CYDEV_CHIP_DIE_PSOC5TM EQU 20
-CYDEV_CHIP_DIE_TMA4 EQU 2
+CYDEV_CHIP_DIE_PSOC4A EQU 16
+CYDEV_CHIP_DIE_PSOC5LP EQU 2
+CYDEV_CHIP_DIE_PSOC5TM EQU 3
+CYDEV_CHIP_DIE_TMA4 EQU 4
 CYDEV_CHIP_DIE_UNKNOWN EQU 0
-CYDEV_CHIP_FAMILY_FM0P EQU 4
-CYDEV_CHIP_FAMILY_FM3 EQU 5
-CYDEV_CHIP_FAMILY_FM4 EQU 6
+CYDEV_CHIP_FAMILY_FM0P EQU 5
+CYDEV_CHIP_FAMILY_FM3 EQU 6
+CYDEV_CHIP_FAMILY_FM4 EQU 7
 CYDEV_CHIP_FAMILY_PSOC3 EQU 1
 CYDEV_CHIP_FAMILY_PSOC4 EQU 2
 CYDEV_CHIP_FAMILY_PSOC5 EQU 3
+CYDEV_CHIP_FAMILY_PSOC6 EQU 4
 CYDEV_CHIP_FAMILY_UNKNOWN EQU 0
 CYDEV_CHIP_FAMILY_USED EQU CYDEV_CHIP_FAMILY_PSOC5
 CYDEV_CHIP_JTAG_ID EQU 0x2E133069
 CYDEV_CHIP_MEMBER_3A EQU 1
-CYDEV_CHIP_MEMBER_4A EQU 12
-CYDEV_CHIP_MEMBER_4C EQU 18
-CYDEV_CHIP_MEMBER_4D EQU 8
-CYDEV_CHIP_MEMBER_4E EQU 4
-CYDEV_CHIP_MEMBER_4F EQU 13
-CYDEV_CHIP_MEMBER_4G EQU 2
-CYDEV_CHIP_MEMBER_4H EQU 11
-CYDEV_CHIP_MEMBER_4I EQU 17
-CYDEV_CHIP_MEMBER_4J EQU 9
-CYDEV_CHIP_MEMBER_4K EQU 10
-CYDEV_CHIP_MEMBER_4L EQU 16
-CYDEV_CHIP_MEMBER_4M EQU 15
-CYDEV_CHIP_MEMBER_4N EQU 6
-CYDEV_CHIP_MEMBER_4O EQU 5
-CYDEV_CHIP_MEMBER_4P EQU 14
-CYDEV_CHIP_MEMBER_4Q EQU 7
-CYDEV_CHIP_MEMBER_4U EQU 3
-CYDEV_CHIP_MEMBER_5A EQU 20
-CYDEV_CHIP_MEMBER_5B EQU 19
-CYDEV_CHIP_MEMBER_FM3 EQU 24
-CYDEV_CHIP_MEMBER_FM4 EQU 25
-CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE1 EQU 21
-CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE2 EQU 22
-CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE3 EQU 23
+CYDEV_CHIP_MEMBER_4A EQU 16
+CYDEV_CHIP_MEMBER_4D EQU 12
+CYDEV_CHIP_MEMBER_4E EQU 6
+CYDEV_CHIP_MEMBER_4F EQU 17
+CYDEV_CHIP_MEMBER_4G EQU 4
+CYDEV_CHIP_MEMBER_4H EQU 15
+CYDEV_CHIP_MEMBER_4I EQU 21
+CYDEV_CHIP_MEMBER_4J EQU 13
+CYDEV_CHIP_MEMBER_4K EQU 14
+CYDEV_CHIP_MEMBER_4L EQU 20
+CYDEV_CHIP_MEMBER_4M EQU 19
+CYDEV_CHIP_MEMBER_4N EQU 9
+CYDEV_CHIP_MEMBER_4O EQU 7
+CYDEV_CHIP_MEMBER_4P EQU 18
+CYDEV_CHIP_MEMBER_4Q EQU 11
+CYDEV_CHIP_MEMBER_4R EQU 8
+CYDEV_CHIP_MEMBER_4S EQU 10
+CYDEV_CHIP_MEMBER_4U EQU 5
+CYDEV_CHIP_MEMBER_5A EQU 3
+CYDEV_CHIP_MEMBER_5B EQU 2
+CYDEV_CHIP_MEMBER_6A EQU 22
+CYDEV_CHIP_MEMBER_FM3 EQU 26
+CYDEV_CHIP_MEMBER_FM4 EQU 27
+CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE1 EQU 23
+CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE2 EQU 24
+CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE3 EQU 25
 CYDEV_CHIP_MEMBER_UNKNOWN EQU 0
 CYDEV_CHIP_MEMBER_USED EQU CYDEV_CHIP_MEMBER_5B
 CYDEV_CHIP_DIE_EXPECT EQU CYDEV_CHIP_MEMBER_USED
@@ -2681,7 +2661,6 @@ CYDEV_CHIP_REVISION_3A_ES3 EQU 3
 CYDEV_CHIP_REVISION_3A_PRODUCTION EQU 3
 CYDEV_CHIP_REVISION_4A_ES0 EQU 17
 CYDEV_CHIP_REVISION_4A_PRODUCTION EQU 17
-CYDEV_CHIP_REVISION_4C_PRODUCTION EQU 0
 CYDEV_CHIP_REVISION_4D_PRODUCTION EQU 0
 CYDEV_CHIP_REVISION_4E_PRODUCTION EQU 0
 CYDEV_CHIP_REVISION_4F_PRODUCTION EQU 0
@@ -2700,12 +2679,16 @@ CYDEV_CHIP_REVISION_4N_PRODUCTION EQU 0
 CYDEV_CHIP_REVISION_4O_PRODUCTION EQU 0
 CYDEV_CHIP_REVISION_4P_PRODUCTION EQU 0
 CYDEV_CHIP_REVISION_4Q_PRODUCTION EQU 0
+CYDEV_CHIP_REVISION_4R_PRODUCTION EQU 0
+CYDEV_CHIP_REVISION_4S_PRODUCTION EQU 0
 CYDEV_CHIP_REVISION_4U_PRODUCTION EQU 0
 CYDEV_CHIP_REVISION_5A_ES0 EQU 0
 CYDEV_CHIP_REVISION_5A_ES1 EQU 1
 CYDEV_CHIP_REVISION_5A_PRODUCTION EQU 1
 CYDEV_CHIP_REVISION_5B_ES0 EQU 0
 CYDEV_CHIP_REVISION_5B_PRODUCTION EQU 0
+CYDEV_CHIP_REVISION_6A_NO_UDB EQU 0
+CYDEV_CHIP_REVISION_6A_PRODUCTION EQU 0
 CYDEV_CHIP_REVISION_FM3_PRODUCTION EQU 0
 CYDEV_CHIP_REVISION_FM4_PRODUCTION EQU 0
 CYDEV_CHIP_REVISION_PDL_FM0P_TYPE1_PRODUCTION EQU 0
@@ -2737,7 +2720,7 @@ CYDEV_DMA_CHANNELS_AVAILABLE EQU 24
 CYDEV_ECC_ENABLE EQU 0
 CYDEV_HEAP_SIZE EQU 0x0400
 CYDEV_INSTRUCT_CACHE_ENABLED EQU 1
-CYDEV_INTR_RISING EQU 0x0000007E
+CYDEV_INTR_RISING EQU 0x0000007F
 CYDEV_IS_EXPORTING_CODE EQU 0
 CYDEV_IS_IMPORTING_CODE EQU 0
 CYDEV_PROJ_TYPE EQU 2

diff --git a/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitterrv.inc b/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitterrv.inc
index a01896829e3733c20347807d7db2ff92575b499f..f8955d94ecc1bd8ee6e070fab38eb779c39b65cb 100755 (executable)
--- a/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitterrv.inc
+++ b/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitterrv.inc
@@ -1,8 +1,51 @@
+;
+; File Name: cyfitterrv.inc
+; 
+; PSoC Creator  4.1
+;
+; Description:
+; 
+;
+;-------------------------------------------------------------------------------
+; Copyright (c) 2007-2017 Cypress Semiconductor.  All rights reserved.
+; You may use this file only in accordance with the license, terms, conditions, 
+; disclaimers, and limitations in the end user license agreement accompanying 
+; the software package with which this file was provided.
+;-------------------------------------------------------------------------------
+
     IF :LNOT::DEF:INCLUDED_CYFITTERRV_INC
 INCLUDED_CYFITTERRV_INC EQU 1
     GET cydevicerv.inc
     GET cydevicerv_trm.inc
 
+; Debug_Timer_Interrupt
+Debug_Timer_Interrupt__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
+Debug_Timer_Interrupt__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
+Debug_Timer_Interrupt__INTC_MASK EQU 0x01
+Debug_Timer_Interrupt__INTC_NUMBER EQU 0
+Debug_Timer_Interrupt__INTC_PRIOR_NUM EQU 7
+Debug_Timer_Interrupt__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_0
+Debug_Timer_Interrupt__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
+Debug_Timer_Interrupt__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
+
+; Debug_Timer_TimerHW
+Debug_Timer_TimerHW__CAP0 EQU CYREG_TMR0_CAP0
+Debug_Timer_TimerHW__CAP1 EQU CYREG_TMR0_CAP1
+Debug_Timer_TimerHW__CFG0 EQU CYREG_TMR0_CFG0
+Debug_Timer_TimerHW__CFG1 EQU CYREG_TMR0_CFG1
+Debug_Timer_TimerHW__CFG2 EQU CYREG_TMR0_CFG2
+Debug_Timer_TimerHW__CNT_CMP0 EQU CYREG_TMR0_CNT_CMP0
+Debug_Timer_TimerHW__CNT_CMP1 EQU CYREG_TMR0_CNT_CMP1
+Debug_Timer_TimerHW__PER0 EQU CYREG_TMR0_PER0
+Debug_Timer_TimerHW__PER1 EQU CYREG_TMR0_PER1
+Debug_Timer_TimerHW__PM_ACT_CFG EQU CYREG_PM_ACT_CFG3
+Debug_Timer_TimerHW__PM_ACT_MSK EQU 0x01
+Debug_Timer_TimerHW__PM_STBY_CFG EQU CYREG_PM_STBY_CFG3
+Debug_Timer_TimerHW__PM_STBY_MSK EQU 0x01
+Debug_Timer_TimerHW__RT0 EQU CYREG_TMR0_RT0
+Debug_Timer_TimerHW__RT1 EQU CYREG_TMR0_RT1
+Debug_Timer_TimerHW__SR0 EQU CYREG_TMR0_SR0
+
 ; LED1
 LED1__0__INTTYPE EQU CYREG_PICU12_INTTYPE0
 LED1__0__MASK EQU 0x01
@@ -41,2036 +84,571 @@ LED1__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN
 LED1__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ
 LED1__SLW EQU CYREG_PRT12_SLW
 
-; SD_CS
-SD_CS__0__INTTYPE EQU CYREG_PICU3_INTTYPE5
-SD_CS__0__MASK EQU 0x20
-SD_CS__0__PC EQU CYREG_PRT3_PC5
-SD_CS__0__PORT EQU 3
-SD_CS__0__SHIFT EQU 5
-SD_CS__AG EQU CYREG_PRT3_AG
-SD_CS__AMUX EQU CYREG_PRT3_AMUX
-SD_CS__BIE EQU CYREG_PRT3_BIE
-SD_CS__BIT_MASK EQU CYREG_PRT3_BIT_MASK
-SD_CS__BYP EQU CYREG_PRT3_BYP
-SD_CS__CTL EQU CYREG_PRT3_CTL
-SD_CS__DM0 EQU CYREG_PRT3_DM0
-SD_CS__DM1 EQU CYREG_PRT3_DM1
-SD_CS__DM2 EQU CYREG_PRT3_DM2
-SD_CS__DR EQU CYREG_PRT3_DR
-SD_CS__INP_DIS EQU CYREG_PRT3_INP_DIS
-SD_CS__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE
-SD_CS__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG
-SD_CS__LCD_EN EQU CYREG_PRT3_LCD_EN
-SD_CS__MASK EQU 0x20
-SD_CS__PORT EQU 3
-SD_CS__PRT EQU CYREG_PRT3_PRT
-SD_CS__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL
-SD_CS__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN
-SD_CS__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0
-SD_CS__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1
-SD_CS__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0
-SD_CS__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1
-SD_CS__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT
-SD_CS__PS EQU CYREG_PRT3_PS
-SD_CS__SHIFT EQU 5
-SD_CS__SLW EQU CYREG_PRT3_SLW
-
-; USBFS_arb_int
-USBFS_arb_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
-USBFS_arb_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-USBFS_arb_int__INTC_MASK EQU 0x400000
-USBFS_arb_int__INTC_NUMBER EQU 22
-USBFS_arb_int__INTC_PRIOR_NUM EQU 6
-USBFS_arb_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_22
-USBFS_arb_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
-USBFS_arb_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
-
-; USBFS_bus_reset
-USBFS_bus_reset__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
-USBFS_bus_reset__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-USBFS_bus_reset__INTC_MASK EQU 0x800000
-USBFS_bus_reset__INTC_NUMBER EQU 23
-USBFS_bus_reset__INTC_PRIOR_NUM EQU 7
-USBFS_bus_reset__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_23
-USBFS_bus_reset__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
-USBFS_bus_reset__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
-
-; USBFS_Dm
-USBFS_Dm__0__INTTYPE EQU CYREG_PICU15_INTTYPE7
-USBFS_Dm__0__MASK EQU 0x80
-USBFS_Dm__0__PC EQU CYREG_IO_PC_PRT15_7_6_PC1
-USBFS_Dm__0__PORT EQU 15
-USBFS_Dm__0__SHIFT EQU 7
-USBFS_Dm__AG EQU CYREG_PRT15_AG
-USBFS_Dm__AMUX EQU CYREG_PRT15_AMUX
-USBFS_Dm__BIE EQU CYREG_PRT15_BIE
-USBFS_Dm__BIT_MASK EQU CYREG_PRT15_BIT_MASK
-USBFS_Dm__BYP EQU CYREG_PRT15_BYP
-USBFS_Dm__CTL EQU CYREG_PRT15_CTL
-USBFS_Dm__DM0 EQU CYREG_PRT15_DM0
-USBFS_Dm__DM1 EQU CYREG_PRT15_DM1
-USBFS_Dm__DM2 EQU CYREG_PRT15_DM2
-USBFS_Dm__DR EQU CYREG_PRT15_DR
-USBFS_Dm__INP_DIS EQU CYREG_PRT15_INP_DIS
-USBFS_Dm__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU15_BASE
-USBFS_Dm__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG
-USBFS_Dm__LCD_EN EQU CYREG_PRT15_LCD_EN
-USBFS_Dm__MASK EQU 0x80
-USBFS_Dm__PORT EQU 15
-USBFS_Dm__PRT EQU CYREG_PRT15_PRT
-USBFS_Dm__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL
-USBFS_Dm__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN
-USBFS_Dm__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0
-USBFS_Dm__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1
-USBFS_Dm__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0
-USBFS_Dm__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1
-USBFS_Dm__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT
-USBFS_Dm__PS EQU CYREG_PRT15_PS
-USBFS_Dm__SHIFT EQU 7
-USBFS_Dm__SLW EQU CYREG_PRT15_SLW
-
-; USBFS_Dp
-USBFS_Dp__0__INTTYPE EQU CYREG_PICU15_INTTYPE6
-USBFS_Dp__0__MASK EQU 0x40
-USBFS_Dp__0__PC EQU CYREG_IO_PC_PRT15_7_6_PC0
-USBFS_Dp__0__PORT EQU 15
-USBFS_Dp__0__SHIFT EQU 6
-USBFS_Dp__AG EQU CYREG_PRT15_AG
-USBFS_Dp__AMUX EQU CYREG_PRT15_AMUX
-USBFS_Dp__BIE EQU CYREG_PRT15_BIE
-USBFS_Dp__BIT_MASK EQU CYREG_PRT15_BIT_MASK
-USBFS_Dp__BYP EQU CYREG_PRT15_BYP
-USBFS_Dp__CTL EQU CYREG_PRT15_CTL
-USBFS_Dp__DM0 EQU CYREG_PRT15_DM0
-USBFS_Dp__DM1 EQU CYREG_PRT15_DM1
-USBFS_Dp__DM2 EQU CYREG_PRT15_DM2
-USBFS_Dp__DR EQU CYREG_PRT15_DR
-USBFS_Dp__INP_DIS EQU CYREG_PRT15_INP_DIS
-USBFS_Dp__INTSTAT EQU CYREG_PICU15_INTSTAT
-USBFS_Dp__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU15_BASE
-USBFS_Dp__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG
-USBFS_Dp__LCD_EN EQU CYREG_PRT15_LCD_EN
-USBFS_Dp__MASK EQU 0x40
-USBFS_Dp__PORT EQU 15
-USBFS_Dp__PRT EQU CYREG_PRT15_PRT
-USBFS_Dp__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL
-USBFS_Dp__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN
-USBFS_Dp__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0
-USBFS_Dp__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1
-USBFS_Dp__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0
-USBFS_Dp__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1
-USBFS_Dp__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT
-USBFS_Dp__PS EQU CYREG_PRT15_PS
-USBFS_Dp__SHIFT EQU 6
-USBFS_Dp__SLW EQU CYREG_PRT15_SLW
-USBFS_Dp__SNAP EQU CYREG_PICU_15_SNAP_15
-
-; USBFS_dp_int
-USBFS_dp_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
-USBFS_dp_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-USBFS_dp_int__INTC_MASK EQU 0x1000
-USBFS_dp_int__INTC_NUMBER EQU 12
-USBFS_dp_int__INTC_PRIOR_NUM EQU 7
-USBFS_dp_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_12
-USBFS_dp_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
-USBFS_dp_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
+; SCSI_CLK
+SCSI_CLK__CFG0 EQU CYREG_CLKDIST_DCFG1_CFG0
+SCSI_CLK__CFG1 EQU CYREG_CLKDIST_DCFG1_CFG1
+SCSI_CLK__CFG2 EQU CYREG_CLKDIST_DCFG1_CFG2
+SCSI_CLK__CFG2_SRC_SEL_MASK EQU 0x07
+SCSI_CLK__INDEX EQU 0x01
+SCSI_CLK__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2
+SCSI_CLK__PM_ACT_MSK EQU 0x02
+SCSI_CLK__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2
+SCSI_CLK__PM_STBY_MSK EQU 0x02
 
-; USBFS_ep_0
-USBFS_ep_0__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
-USBFS_ep_0__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-USBFS_ep_0__INTC_MASK EQU 0x1000000
-USBFS_ep_0__INTC_NUMBER EQU 24
-USBFS_ep_0__INTC_PRIOR_NUM EQU 7
-USBFS_ep_0__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_24
-USBFS_ep_0__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
-USBFS_ep_0__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
+; SCSI_CTL_PHASE
+SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01
+SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS EQU 0
+SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK EQU 0x02
+SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS EQU 1
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB02_03_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB02_03_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB02_03_MSK
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB02_03_MSK
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK
+SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK EQU 0x04
+SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS EQU 2
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB02_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB02_ST_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB02_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB02_ST_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__MASK EQU 0x07
+SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB02_MSK
 
-; USBFS_ep_1
-USBFS_ep_1__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
-USBFS_ep_1__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-USBFS_ep_1__INTC_MASK EQU 0x80
-USBFS_ep_1__INTC_NUMBER EQU 7
-USBFS_ep_1__INTC_PRIOR_NUM EQU 7
-USBFS_ep_1__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_7
-USBFS_ep_1__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
-USBFS_ep_1__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
+; SCSI_Filtered
+SCSI_Filtered_sts_sts_reg__0__MASK EQU 0x01
+SCSI_Filtered_sts_sts_reg__0__POS EQU 0
+SCSI_Filtered_sts_sts_reg__1__MASK EQU 0x02
+SCSI_Filtered_sts_sts_reg__1__POS EQU 1
+SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL
+SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB11_12_ST
+SCSI_Filtered_sts_sts_reg__2__MASK EQU 0x04
+SCSI_Filtered_sts_sts_reg__2__POS EQU 2
+SCSI_Filtered_sts_sts_reg__3__MASK EQU 0x08
+SCSI_Filtered_sts_sts_reg__3__POS EQU 3
+SCSI_Filtered_sts_sts_reg__4__MASK EQU 0x10
+SCSI_Filtered_sts_sts_reg__4__POS EQU 4
+SCSI_Filtered_sts_sts_reg__MASK EQU 0x1F
+SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB11_MSK
+SCSI_Filtered_sts_sts_reg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
+SCSI_Filtered_sts_sts_reg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
+SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL
+SCSI_Filtered_sts_sts_reg__STATUS_CNT_REG EQU CYREG_B0_UDB11_ST_CTL
+SCSI_Filtered_sts_sts_reg__STATUS_CONTROL_REG EQU CYREG_B0_UDB11_ST_CTL
+SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB11_ST
 
-; USBFS_ep_2
-USBFS_ep_2__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
-USBFS_ep_2__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-USBFS_ep_2__INTC_MASK EQU 0x100
-USBFS_ep_2__INTC_NUMBER EQU 8
-USBFS_ep_2__INTC_PRIOR_NUM EQU 7
-USBFS_ep_2__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_8
-USBFS_ep_2__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
-USBFS_ep_2__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
+; SCSI_Glitch_Ctl
+SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01
+SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS EQU 0
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB05_06_CTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB05_06_CTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB05_06_MSK
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB05_06_MSK
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK
+SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB05_CTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB05_ST_CTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB05_CTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB05_ST_CTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK EQU 0x01
+SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB05_MSK
 
-; USBFS_ep_3
-USBFS_ep_3__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
-USBFS_ep_3__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-USBFS_ep_3__INTC_MASK EQU 0x200
-USBFS_ep_3__INTC_NUMBER EQU 9
-USBFS_ep_3__INTC_PRIOR_NUM EQU 7
-USBFS_ep_3__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_9
-USBFS_ep_3__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
-USBFS_ep_3__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
-
-; USBFS_ep_4
-USBFS_ep_4__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
-USBFS_ep_4__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-USBFS_ep_4__INTC_MASK EQU 0x400
-USBFS_ep_4__INTC_NUMBER EQU 10
-USBFS_ep_4__INTC_PRIOR_NUM EQU 7
-USBFS_ep_4__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_10
-USBFS_ep_4__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
-USBFS_ep_4__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
-
-; USBFS_sof_int
-USBFS_sof_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
-USBFS_sof_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-USBFS_sof_int__INTC_MASK EQU 0x200000
-USBFS_sof_int__INTC_NUMBER EQU 21
-USBFS_sof_int__INTC_PRIOR_NUM EQU 7
-USBFS_sof_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_21
-USBFS_sof_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
-USBFS_sof_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
-
-; USBFS_USB
-USBFS_USB__ARB_CFG EQU CYREG_USB_ARB_CFG
-USBFS_USB__ARB_EP1_CFG EQU CYREG_USB_ARB_EP1_CFG
-USBFS_USB__ARB_EP1_INT_EN EQU CYREG_USB_ARB_EP1_INT_EN
-USBFS_USB__ARB_EP1_SR EQU CYREG_USB_ARB_EP1_SR
-USBFS_USB__ARB_EP2_CFG EQU CYREG_USB_ARB_EP2_CFG
-USBFS_USB__ARB_EP2_INT_EN EQU CYREG_USB_ARB_EP2_INT_EN
-USBFS_USB__ARB_EP2_SR EQU CYREG_USB_ARB_EP2_SR
-USBFS_USB__ARB_EP3_CFG EQU CYREG_USB_ARB_EP3_CFG
-USBFS_USB__ARB_EP3_INT_EN EQU CYREG_USB_ARB_EP3_INT_EN
-USBFS_USB__ARB_EP3_SR EQU CYREG_USB_ARB_EP3_SR
-USBFS_USB__ARB_EP4_CFG EQU CYREG_USB_ARB_EP4_CFG
-USBFS_USB__ARB_EP4_INT_EN EQU CYREG_USB_ARB_EP4_INT_EN
-USBFS_USB__ARB_EP4_SR EQU CYREG_USB_ARB_EP4_SR
-USBFS_USB__ARB_EP5_CFG EQU CYREG_USB_ARB_EP5_CFG
-USBFS_USB__ARB_EP5_INT_EN EQU CYREG_USB_ARB_EP5_INT_EN
-USBFS_USB__ARB_EP5_SR EQU CYREG_USB_ARB_EP5_SR
-USBFS_USB__ARB_EP6_CFG EQU CYREG_USB_ARB_EP6_CFG
-USBFS_USB__ARB_EP6_INT_EN EQU CYREG_USB_ARB_EP6_INT_EN
-USBFS_USB__ARB_EP6_SR EQU CYREG_USB_ARB_EP6_SR
-USBFS_USB__ARB_EP7_CFG EQU CYREG_USB_ARB_EP7_CFG
-USBFS_USB__ARB_EP7_INT_EN EQU CYREG_USB_ARB_EP7_INT_EN
-USBFS_USB__ARB_EP7_SR EQU CYREG_USB_ARB_EP7_SR
-USBFS_USB__ARB_EP8_CFG EQU CYREG_USB_ARB_EP8_CFG
-USBFS_USB__ARB_EP8_INT_EN EQU CYREG_USB_ARB_EP8_INT_EN
-USBFS_USB__ARB_EP8_SR EQU CYREG_USB_ARB_EP8_SR
-USBFS_USB__ARB_INT_EN EQU CYREG_USB_ARB_INT_EN
-USBFS_USB__ARB_INT_SR EQU CYREG_USB_ARB_INT_SR
-USBFS_USB__ARB_RW1_DR EQU CYREG_USB_ARB_RW1_DR
-USBFS_USB__ARB_RW1_RA EQU CYREG_USB_ARB_RW1_RA
-USBFS_USB__ARB_RW1_RA_MSB EQU CYREG_USB_ARB_RW1_RA_MSB
-USBFS_USB__ARB_RW1_WA EQU CYREG_USB_ARB_RW1_WA
-USBFS_USB__ARB_RW1_WA_MSB EQU CYREG_USB_ARB_RW1_WA_MSB
-USBFS_USB__ARB_RW2_DR EQU CYREG_USB_ARB_RW2_DR
-USBFS_USB__ARB_RW2_RA EQU CYREG_USB_ARB_RW2_RA
-USBFS_USB__ARB_RW2_RA_MSB EQU CYREG_USB_ARB_RW2_RA_MSB
-USBFS_USB__ARB_RW2_WA EQU CYREG_USB_ARB_RW2_WA
-USBFS_USB__ARB_RW2_WA_MSB EQU CYREG_USB_ARB_RW2_WA_MSB
-USBFS_USB__ARB_RW3_DR EQU CYREG_USB_ARB_RW3_DR
-USBFS_USB__ARB_RW3_RA EQU CYREG_USB_ARB_RW3_RA
-USBFS_USB__ARB_RW3_RA_MSB EQU CYREG_USB_ARB_RW3_RA_MSB
-USBFS_USB__ARB_RW3_WA EQU CYREG_USB_ARB_RW3_WA
-USBFS_USB__ARB_RW3_WA_MSB EQU CYREG_USB_ARB_RW3_WA_MSB
-USBFS_USB__ARB_RW4_DR EQU CYREG_USB_ARB_RW4_DR
-USBFS_USB__ARB_RW4_RA EQU CYREG_USB_ARB_RW4_RA
-USBFS_USB__ARB_RW4_RA_MSB EQU CYREG_USB_ARB_RW4_RA_MSB
-USBFS_USB__ARB_RW4_WA EQU CYREG_USB_ARB_RW4_WA
-USBFS_USB__ARB_RW4_WA_MSB EQU CYREG_USB_ARB_RW4_WA_MSB
-USBFS_USB__ARB_RW5_DR EQU CYREG_USB_ARB_RW5_DR
-USBFS_USB__ARB_RW5_RA EQU CYREG_USB_ARB_RW5_RA
-USBFS_USB__ARB_RW5_RA_MSB EQU CYREG_USB_ARB_RW5_RA_MSB
-USBFS_USB__ARB_RW5_WA EQU CYREG_USB_ARB_RW5_WA
-USBFS_USB__ARB_RW5_WA_MSB EQU CYREG_USB_ARB_RW5_WA_MSB
-USBFS_USB__ARB_RW6_DR EQU CYREG_USB_ARB_RW6_DR
-USBFS_USB__ARB_RW6_RA EQU CYREG_USB_ARB_RW6_RA
-USBFS_USB__ARB_RW6_RA_MSB EQU CYREG_USB_ARB_RW6_RA_MSB
-USBFS_USB__ARB_RW6_WA EQU CYREG_USB_ARB_RW6_WA
-USBFS_USB__ARB_RW6_WA_MSB EQU CYREG_USB_ARB_RW6_WA_MSB
-USBFS_USB__ARB_RW7_DR EQU CYREG_USB_ARB_RW7_DR
-USBFS_USB__ARB_RW7_RA EQU CYREG_USB_ARB_RW7_RA
-USBFS_USB__ARB_RW7_RA_MSB EQU CYREG_USB_ARB_RW7_RA_MSB
-USBFS_USB__ARB_RW7_WA EQU CYREG_USB_ARB_RW7_WA
-USBFS_USB__ARB_RW7_WA_MSB EQU CYREG_USB_ARB_RW7_WA_MSB
-USBFS_USB__ARB_RW8_DR EQU CYREG_USB_ARB_RW8_DR
-USBFS_USB__ARB_RW8_RA EQU CYREG_USB_ARB_RW8_RA
-USBFS_USB__ARB_RW8_RA_MSB EQU CYREG_USB_ARB_RW8_RA_MSB
-USBFS_USB__ARB_RW8_WA EQU CYREG_USB_ARB_RW8_WA
-USBFS_USB__ARB_RW8_WA_MSB EQU CYREG_USB_ARB_RW8_WA_MSB
-USBFS_USB__BUF_SIZE EQU CYREG_USB_BUF_SIZE
-USBFS_USB__BUS_RST_CNT EQU CYREG_USB_BUS_RST_CNT
-USBFS_USB__CR0 EQU CYREG_USB_CR0
-USBFS_USB__CR1 EQU CYREG_USB_CR1
-USBFS_USB__CWA EQU CYREG_USB_CWA
-USBFS_USB__CWA_MSB EQU CYREG_USB_CWA_MSB
-USBFS_USB__DMA_THRES EQU CYREG_USB_DMA_THRES
-USBFS_USB__DMA_THRES_MSB EQU CYREG_USB_DMA_THRES_MSB
-USBFS_USB__DYN_RECONFIG EQU CYREG_USB_DYN_RECONFIG
-USBFS_USB__EP_ACTIVE EQU CYREG_USB_EP_ACTIVE
-USBFS_USB__EP_TYPE EQU CYREG_USB_EP_TYPE
-USBFS_USB__EP0_CNT EQU CYREG_USB_EP0_CNT
-USBFS_USB__EP0_CR EQU CYREG_USB_EP0_CR
-USBFS_USB__EP0_DR0 EQU CYREG_USB_EP0_DR0
-USBFS_USB__EP0_DR1 EQU CYREG_USB_EP0_DR1
-USBFS_USB__EP0_DR2 EQU CYREG_USB_EP0_DR2
-USBFS_USB__EP0_DR3 EQU CYREG_USB_EP0_DR3
-USBFS_USB__EP0_DR4 EQU CYREG_USB_EP0_DR4
-USBFS_USB__EP0_DR5 EQU CYREG_USB_EP0_DR5
-USBFS_USB__EP0_DR6 EQU CYREG_USB_EP0_DR6
-USBFS_USB__EP0_DR7 EQU CYREG_USB_EP0_DR7
-USBFS_USB__MEM_DATA EQU CYREG_USB_MEM_DATA_MBASE
-USBFS_USB__PM_ACT_CFG EQU CYREG_PM_ACT_CFG5
-USBFS_USB__PM_ACT_MSK EQU 0x01
-USBFS_USB__PM_STBY_CFG EQU CYREG_PM_STBY_CFG5
-USBFS_USB__PM_STBY_MSK EQU 0x01
-USBFS_USB__SIE_EP_INT_EN EQU CYREG_USB_SIE_EP_INT_EN
-USBFS_USB__SIE_EP_INT_SR EQU CYREG_USB_SIE_EP_INT_SR
-USBFS_USB__SIE_EP1_CNT0 EQU CYREG_USB_SIE_EP1_CNT0
-USBFS_USB__SIE_EP1_CNT1 EQU CYREG_USB_SIE_EP1_CNT1
-USBFS_USB__SIE_EP1_CR0 EQU CYREG_USB_SIE_EP1_CR0
-USBFS_USB__SIE_EP2_CNT0 EQU CYREG_USB_SIE_EP2_CNT0
-USBFS_USB__SIE_EP2_CNT1 EQU CYREG_USB_SIE_EP2_CNT1
-USBFS_USB__SIE_EP2_CR0 EQU CYREG_USB_SIE_EP2_CR0
-USBFS_USB__SIE_EP3_CNT0 EQU CYREG_USB_SIE_EP3_CNT0
-USBFS_USB__SIE_EP3_CNT1 EQU CYREG_USB_SIE_EP3_CNT1
-USBFS_USB__SIE_EP3_CR0 EQU CYREG_USB_SIE_EP3_CR0
-USBFS_USB__SIE_EP4_CNT0 EQU CYREG_USB_SIE_EP4_CNT0
-USBFS_USB__SIE_EP4_CNT1 EQU CYREG_USB_SIE_EP4_CNT1
-USBFS_USB__SIE_EP4_CR0 EQU CYREG_USB_SIE_EP4_CR0
-USBFS_USB__SIE_EP5_CNT0 EQU CYREG_USB_SIE_EP5_CNT0
-USBFS_USB__SIE_EP5_CNT1 EQU CYREG_USB_SIE_EP5_CNT1
-USBFS_USB__SIE_EP5_CR0 EQU CYREG_USB_SIE_EP5_CR0
-USBFS_USB__SIE_EP6_CNT0 EQU CYREG_USB_SIE_EP6_CNT0
-USBFS_USB__SIE_EP6_CNT1 EQU CYREG_USB_SIE_EP6_CNT1
-USBFS_USB__SIE_EP6_CR0 EQU CYREG_USB_SIE_EP6_CR0
-USBFS_USB__SIE_EP7_CNT0 EQU CYREG_USB_SIE_EP7_CNT0
-USBFS_USB__SIE_EP7_CNT1 EQU CYREG_USB_SIE_EP7_CNT1
-USBFS_USB__SIE_EP7_CR0 EQU CYREG_USB_SIE_EP7_CR0
-USBFS_USB__SIE_EP8_CNT0 EQU CYREG_USB_SIE_EP8_CNT0
-USBFS_USB__SIE_EP8_CNT1 EQU CYREG_USB_SIE_EP8_CNT1
-USBFS_USB__SIE_EP8_CR0 EQU CYREG_USB_SIE_EP8_CR0
-USBFS_USB__SOF0 EQU CYREG_USB_SOF0
-USBFS_USB__SOF1 EQU CYREG_USB_SOF1
-USBFS_USB__USB_CLK_EN EQU CYREG_USB_USB_CLK_EN
-USBFS_USB__USBIO_CR0 EQU CYREG_USB_USBIO_CR0
-USBFS_USB__USBIO_CR1 EQU CYREG_USB_USBIO_CR1
-
-; SDCard_BSPIM
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB04_05_CTL
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB04_05_CTL
-SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB04_05_CTL
-SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB04_05_CTL
-SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB04_05_MSK
-SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB04_05_MSK
-SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB04_05_MSK
-SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB04_05_MSK
-SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL
-SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB04_CTL
-SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB04_ST_CTL
-SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB04_CTL
-SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB04_ST_CTL
-SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL
-SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL
-SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB04_MSK
-SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL
-SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB04_05_ST
-SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB04_MSK
-SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL
-SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL
-SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL
-SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB04_ST_CTL
-SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB04_ST_CTL
-SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB04_ST
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB07_08_ST
-SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10
-SDCard_BSPIM_RxStsReg__4__POS EQU 4
-SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20
-SDCard_BSPIM_RxStsReg__5__POS EQU 5
-SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40
-SDCard_BSPIM_RxStsReg__6__POS EQU 6
-SDCard_BSPIM_RxStsReg__MASK EQU 0x70
-SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B0_UDB07_MSK
-SDCard_BSPIM_RxStsReg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL
-SDCard_BSPIM_RxStsReg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL
-SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL
-SDCard_BSPIM_RxStsReg__STATUS_CNT_REG EQU CYREG_B0_UDB07_ST_CTL
-SDCard_BSPIM_RxStsReg__STATUS_CONTROL_REG EQU CYREG_B0_UDB07_ST_CTL
-SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B0_UDB07_ST
-SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB04_05_A0
-SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB04_05_A1
-SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B1_UDB04_05_D0
-SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B1_UDB04_05_D1
-SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL
-SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B1_UDB04_05_F0
-SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B1_UDB04_05_F1
-SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B1_UDB04_A0_A1
-SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B1_UDB04_A0
-SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B1_UDB04_A1
-SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B1_UDB04_D0_D1
-SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B1_UDB04_D0
-SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B1_UDB04_D1
-SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL
-SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B1_UDB04_F0_F1
-SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B1_UDB04_F0
-SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B1_UDB04_F1
-SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL
-SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL
-SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01
-SDCard_BSPIM_TxStsReg__0__POS EQU 0
-SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02
-SDCard_BSPIM_TxStsReg__1__POS EQU 1
-SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL
-SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST
-SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04
-SDCard_BSPIM_TxStsReg__2__POS EQU 2
-SDCard_BSPIM_TxStsReg__3__MASK EQU 0x08
-SDCard_BSPIM_TxStsReg__3__POS EQU 3
-SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10
-SDCard_BSPIM_TxStsReg__4__POS EQU 4
-SDCard_BSPIM_TxStsReg__MASK EQU 0x1F
-SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB07_MSK
-SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL
-SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB07_ST
-
-; SD_SCK
-SD_SCK__0__INTTYPE EQU CYREG_PICU3_INTTYPE3
-SD_SCK__0__MASK EQU 0x08
-SD_SCK__0__PC EQU CYREG_PRT3_PC3
-SD_SCK__0__PORT EQU 3
-SD_SCK__0__SHIFT EQU 3
-SD_SCK__AG EQU CYREG_PRT3_AG
-SD_SCK__AMUX EQU CYREG_PRT3_AMUX
-SD_SCK__BIE EQU CYREG_PRT3_BIE
-SD_SCK__BIT_MASK EQU CYREG_PRT3_BIT_MASK
-SD_SCK__BYP EQU CYREG_PRT3_BYP
-SD_SCK__CTL EQU CYREG_PRT3_CTL
-SD_SCK__DM0 EQU CYREG_PRT3_DM0
-SD_SCK__DM1 EQU CYREG_PRT3_DM1
-SD_SCK__DM2 EQU CYREG_PRT3_DM2
-SD_SCK__DR EQU CYREG_PRT3_DR
-SD_SCK__INP_DIS EQU CYREG_PRT3_INP_DIS
-SD_SCK__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE
-SD_SCK__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG
-SD_SCK__LCD_EN EQU CYREG_PRT3_LCD_EN
-SD_SCK__MASK EQU 0x08
-SD_SCK__PORT EQU 3
-SD_SCK__PRT EQU CYREG_PRT3_PRT
-SD_SCK__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL
-SD_SCK__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN
-SD_SCK__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0
-SD_SCK__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1
-SD_SCK__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0
-SD_SCK__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1
-SD_SCK__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT
-SD_SCK__PS EQU CYREG_PRT3_PS
-SD_SCK__SHIFT EQU 3
-SD_SCK__SLW EQU CYREG_PRT3_SLW
-
-; SCSI_In
-SCSI_In__0__INTTYPE EQU CYREG_PICU6_INTTYPE1
-SCSI_In__0__MASK EQU 0x02
-SCSI_In__0__PC EQU CYREG_PRT6_PC1
-SCSI_In__0__PORT EQU 6
-SCSI_In__0__SHIFT EQU 1
-SCSI_In__AG EQU CYREG_PRT6_AG
-SCSI_In__AMUX EQU CYREG_PRT6_AMUX
-SCSI_In__BIE EQU CYREG_PRT6_BIE
-SCSI_In__BIT_MASK EQU CYREG_PRT6_BIT_MASK
-SCSI_In__BYP EQU CYREG_PRT6_BYP
-SCSI_In__CTL EQU CYREG_PRT6_CTL
-SCSI_In__DBP__INTTYPE EQU CYREG_PICU6_INTTYPE1
-SCSI_In__DBP__MASK EQU 0x02
-SCSI_In__DBP__PC EQU CYREG_PRT6_PC1
-SCSI_In__DBP__PORT EQU 6
-SCSI_In__DBP__SHIFT EQU 1
-SCSI_In__DM0 EQU CYREG_PRT6_DM0
-SCSI_In__DM1 EQU CYREG_PRT6_DM1
-SCSI_In__DM2 EQU CYREG_PRT6_DM2
-SCSI_In__DR EQU CYREG_PRT6_DR
-SCSI_In__INP_DIS EQU CYREG_PRT6_INP_DIS
-SCSI_In__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU6_BASE
-SCSI_In__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
-SCSI_In__LCD_EN EQU CYREG_PRT6_LCD_EN
-SCSI_In__MASK EQU 0x02
-SCSI_In__PORT EQU 6
-SCSI_In__PRT EQU CYREG_PRT6_PRT
-SCSI_In__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
-SCSI_In__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
-SCSI_In__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
-SCSI_In__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
-SCSI_In__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
-SCSI_In__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
-SCSI_In__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
-SCSI_In__PS EQU CYREG_PRT6_PS
-SCSI_In__SHIFT EQU 1
-SCSI_In__SLW EQU CYREG_PRT6_SLW
-
-; SCSI_In_DBx
-SCSI_In_DBx__0__AG EQU CYREG_PRT6_AG
-SCSI_In_DBx__0__AMUX EQU CYREG_PRT6_AMUX
-SCSI_In_DBx__0__BIE EQU CYREG_PRT6_BIE
-SCSI_In_DBx__0__BIT_MASK EQU CYREG_PRT6_BIT_MASK
-SCSI_In_DBx__0__BYP EQU CYREG_PRT6_BYP
-SCSI_In_DBx__0__CTL EQU CYREG_PRT6_CTL
-SCSI_In_DBx__0__DM0 EQU CYREG_PRT6_DM0
-SCSI_In_DBx__0__DM1 EQU CYREG_PRT6_DM1
-SCSI_In_DBx__0__DM2 EQU CYREG_PRT6_DM2
-SCSI_In_DBx__0__DR EQU CYREG_PRT6_DR
-SCSI_In_DBx__0__INP_DIS EQU CYREG_PRT6_INP_DIS
-SCSI_In_DBx__0__INTTYPE EQU CYREG_PICU6_INTTYPE6
-SCSI_In_DBx__0__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
-SCSI_In_DBx__0__LCD_EN EQU CYREG_PRT6_LCD_EN
-SCSI_In_DBx__0__MASK EQU 0x40
-SCSI_In_DBx__0__PC EQU CYREG_PRT6_PC6
-SCSI_In_DBx__0__PORT EQU 6
-SCSI_In_DBx__0__PRT EQU CYREG_PRT6_PRT
-SCSI_In_DBx__0__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
-SCSI_In_DBx__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
-SCSI_In_DBx__0__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
-SCSI_In_DBx__0__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
-SCSI_In_DBx__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
-SCSI_In_DBx__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
-SCSI_In_DBx__0__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
-SCSI_In_DBx__0__PS EQU CYREG_PRT6_PS
-SCSI_In_DBx__0__SHIFT EQU 6
-SCSI_In_DBx__0__SLW EQU CYREG_PRT6_SLW
-SCSI_In_DBx__1__AG EQU CYREG_PRT6_AG
-SCSI_In_DBx__1__AMUX EQU CYREG_PRT6_AMUX
-SCSI_In_DBx__1__BIE EQU CYREG_PRT6_BIE
-SCSI_In_DBx__1__BIT_MASK EQU CYREG_PRT6_BIT_MASK
-SCSI_In_DBx__1__BYP EQU CYREG_PRT6_BYP
-SCSI_In_DBx__1__CTL EQU CYREG_PRT6_CTL
-SCSI_In_DBx__1__DM0 EQU CYREG_PRT6_DM0
-SCSI_In_DBx__1__DM1 EQU CYREG_PRT6_DM1
-SCSI_In_DBx__1__DM2 EQU CYREG_PRT6_DM2
-SCSI_In_DBx__1__DR EQU CYREG_PRT6_DR
-SCSI_In_DBx__1__INP_DIS EQU CYREG_PRT6_INP_DIS
-SCSI_In_DBx__1__INTTYPE EQU CYREG_PICU6_INTTYPE4
-SCSI_In_DBx__1__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
-SCSI_In_DBx__1__LCD_EN EQU CYREG_PRT6_LCD_EN
-SCSI_In_DBx__1__MASK EQU 0x10
-SCSI_In_DBx__1__PC EQU CYREG_PRT6_PC4
-SCSI_In_DBx__1__PORT EQU 6
-SCSI_In_DBx__1__PRT EQU CYREG_PRT6_PRT
-SCSI_In_DBx__1__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
-SCSI_In_DBx__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
-SCSI_In_DBx__1__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
-SCSI_In_DBx__1__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
-SCSI_In_DBx__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
-SCSI_In_DBx__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
-SCSI_In_DBx__1__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
-SCSI_In_DBx__1__PS EQU CYREG_PRT6_PS
-SCSI_In_DBx__1__SHIFT EQU 4
-SCSI_In_DBx__1__SLW EQU CYREG_PRT6_SLW
-SCSI_In_DBx__2__AG EQU CYREG_PRT12_AG
-SCSI_In_DBx__2__BIE EQU CYREG_PRT12_BIE
-SCSI_In_DBx__2__BIT_MASK EQU CYREG_PRT12_BIT_MASK
-SCSI_In_DBx__2__BYP EQU CYREG_PRT12_BYP
-SCSI_In_DBx__2__DM0 EQU CYREG_PRT12_DM0
-SCSI_In_DBx__2__DM1 EQU CYREG_PRT12_DM1
-SCSI_In_DBx__2__DM2 EQU CYREG_PRT12_DM2
-SCSI_In_DBx__2__DR EQU CYREG_PRT12_DR
-SCSI_In_DBx__2__INP_DIS EQU CYREG_PRT12_INP_DIS
-SCSI_In_DBx__2__INTTYPE EQU CYREG_PICU12_INTTYPE4
-SCSI_In_DBx__2__MASK EQU 0x10
-SCSI_In_DBx__2__PC EQU CYREG_PRT12_PC4
-SCSI_In_DBx__2__PORT EQU 12
-SCSI_In_DBx__2__PRT EQU CYREG_PRT12_PRT
-SCSI_In_DBx__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN
-SCSI_In_DBx__2__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0
-SCSI_In_DBx__2__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1
-SCSI_In_DBx__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0
-SCSI_In_DBx__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1
-SCSI_In_DBx__2__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT
-SCSI_In_DBx__2__PS EQU CYREG_PRT12_PS
-SCSI_In_DBx__2__SHIFT EQU 4
-SCSI_In_DBx__2__SIO_CFG EQU CYREG_PRT12_SIO_CFG
-SCSI_In_DBx__2__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF
-SCSI_In_DBx__2__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN
-SCSI_In_DBx__2__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ
-SCSI_In_DBx__2__SLW EQU CYREG_PRT12_SLW
-SCSI_In_DBx__3__AG EQU CYREG_PRT2_AG
-SCSI_In_DBx__3__AMUX EQU CYREG_PRT2_AMUX
-SCSI_In_DBx__3__BIE EQU CYREG_PRT2_BIE
-SCSI_In_DBx__3__BIT_MASK EQU CYREG_PRT2_BIT_MASK
-SCSI_In_DBx__3__BYP EQU CYREG_PRT2_BYP
-SCSI_In_DBx__3__CTL EQU CYREG_PRT2_CTL
-SCSI_In_DBx__3__DM0 EQU CYREG_PRT2_DM0
-SCSI_In_DBx__3__DM1 EQU CYREG_PRT2_DM1
-SCSI_In_DBx__3__DM2 EQU CYREG_PRT2_DM2
-SCSI_In_DBx__3__DR EQU CYREG_PRT2_DR
-SCSI_In_DBx__3__INP_DIS EQU CYREG_PRT2_INP_DIS
-SCSI_In_DBx__3__INTTYPE EQU CYREG_PICU2_INTTYPE6
-SCSI_In_DBx__3__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
-SCSI_In_DBx__3__LCD_EN EQU CYREG_PRT2_LCD_EN
-SCSI_In_DBx__3__MASK EQU 0x40
-SCSI_In_DBx__3__PC EQU CYREG_PRT2_PC6
-SCSI_In_DBx__3__PORT EQU 2
-SCSI_In_DBx__3__PRT EQU CYREG_PRT2_PRT
-SCSI_In_DBx__3__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
-SCSI_In_DBx__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
-SCSI_In_DBx__3__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
-SCSI_In_DBx__3__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
-SCSI_In_DBx__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
-SCSI_In_DBx__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
-SCSI_In_DBx__3__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
-SCSI_In_DBx__3__PS EQU CYREG_PRT2_PS
-SCSI_In_DBx__3__SHIFT EQU 6
-SCSI_In_DBx__3__SLW EQU CYREG_PRT2_SLW
-SCSI_In_DBx__4__AG EQU CYREG_PRT2_AG
-SCSI_In_DBx__4__AMUX EQU CYREG_PRT2_AMUX
-SCSI_In_DBx__4__BIE EQU CYREG_PRT2_BIE
-SCSI_In_DBx__4__BIT_MASK EQU CYREG_PRT2_BIT_MASK
-SCSI_In_DBx__4__BYP EQU CYREG_PRT2_BYP
-SCSI_In_DBx__4__CTL EQU CYREG_PRT2_CTL
-SCSI_In_DBx__4__DM0 EQU CYREG_PRT2_DM0
-SCSI_In_DBx__4__DM1 EQU CYREG_PRT2_DM1
-SCSI_In_DBx__4__DM2 EQU CYREG_PRT2_DM2
-SCSI_In_DBx__4__DR EQU CYREG_PRT2_DR
-SCSI_In_DBx__4__INP_DIS EQU CYREG_PRT2_INP_DIS
-SCSI_In_DBx__4__INTTYPE EQU CYREG_PICU2_INTTYPE4
-SCSI_In_DBx__4__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
-SCSI_In_DBx__4__LCD_EN EQU CYREG_PRT2_LCD_EN
-SCSI_In_DBx__4__MASK EQU 0x10
-SCSI_In_DBx__4__PC EQU CYREG_PRT2_PC4
-SCSI_In_DBx__4__PORT EQU 2
-SCSI_In_DBx__4__PRT EQU CYREG_PRT2_PRT
-SCSI_In_DBx__4__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
-SCSI_In_DBx__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
-SCSI_In_DBx__4__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
-SCSI_In_DBx__4__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
-SCSI_In_DBx__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
-SCSI_In_DBx__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
-SCSI_In_DBx__4__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
-SCSI_In_DBx__4__PS EQU CYREG_PRT2_PS
-SCSI_In_DBx__4__SHIFT EQU 4
-SCSI_In_DBx__4__SLW EQU CYREG_PRT2_SLW
-SCSI_In_DBx__5__AG EQU CYREG_PRT2_AG
-SCSI_In_DBx__5__AMUX EQU CYREG_PRT2_AMUX
-SCSI_In_DBx__5__BIE EQU CYREG_PRT2_BIE
-SCSI_In_DBx__5__BIT_MASK EQU CYREG_PRT2_BIT_MASK
-SCSI_In_DBx__5__BYP EQU CYREG_PRT2_BYP
-SCSI_In_DBx__5__CTL EQU CYREG_PRT2_CTL
-SCSI_In_DBx__5__DM0 EQU CYREG_PRT2_DM0
-SCSI_In_DBx__5__DM1 EQU CYREG_PRT2_DM1
-SCSI_In_DBx__5__DM2 EQU CYREG_PRT2_DM2
-SCSI_In_DBx__5__DR EQU CYREG_PRT2_DR
-SCSI_In_DBx__5__INP_DIS EQU CYREG_PRT2_INP_DIS
-SCSI_In_DBx__5__INTTYPE EQU CYREG_PICU2_INTTYPE2
-SCSI_In_DBx__5__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
-SCSI_In_DBx__5__LCD_EN EQU CYREG_PRT2_LCD_EN
-SCSI_In_DBx__5__MASK EQU 0x04
-SCSI_In_DBx__5__PC EQU CYREG_PRT2_PC2
-SCSI_In_DBx__5__PORT EQU 2
-SCSI_In_DBx__5__PRT EQU CYREG_PRT2_PRT
-SCSI_In_DBx__5__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
-SCSI_In_DBx__5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
-SCSI_In_DBx__5__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
-SCSI_In_DBx__5__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
-SCSI_In_DBx__5__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
-SCSI_In_DBx__5__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
-SCSI_In_DBx__5__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
-SCSI_In_DBx__5__PS EQU CYREG_PRT2_PS
-SCSI_In_DBx__5__SHIFT EQU 2
-SCSI_In_DBx__5__SLW EQU CYREG_PRT2_SLW
-SCSI_In_DBx__6__AG EQU CYREG_PRT2_AG
-SCSI_In_DBx__6__AMUX EQU CYREG_PRT2_AMUX
-SCSI_In_DBx__6__BIE EQU CYREG_PRT2_BIE
-SCSI_In_DBx__6__BIT_MASK EQU CYREG_PRT2_BIT_MASK
-SCSI_In_DBx__6__BYP EQU CYREG_PRT2_BYP
-SCSI_In_DBx__6__CTL EQU CYREG_PRT2_CTL
-SCSI_In_DBx__6__DM0 EQU CYREG_PRT2_DM0
-SCSI_In_DBx__6__DM1 EQU CYREG_PRT2_DM1
-SCSI_In_DBx__6__DM2 EQU CYREG_PRT2_DM2
-SCSI_In_DBx__6__DR EQU CYREG_PRT2_DR
-SCSI_In_DBx__6__INP_DIS EQU CYREG_PRT2_INP_DIS
-SCSI_In_DBx__6__INTTYPE EQU CYREG_PICU2_INTTYPE0
-SCSI_In_DBx__6__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
-SCSI_In_DBx__6__LCD_EN EQU CYREG_PRT2_LCD_EN
-SCSI_In_DBx__6__MASK EQU 0x01
-SCSI_In_DBx__6__PC EQU CYREG_PRT2_PC0
-SCSI_In_DBx__6__PORT EQU 2
-SCSI_In_DBx__6__PRT EQU CYREG_PRT2_PRT
-SCSI_In_DBx__6__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
-SCSI_In_DBx__6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
-SCSI_In_DBx__6__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
-SCSI_In_DBx__6__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
-SCSI_In_DBx__6__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
-SCSI_In_DBx__6__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
-SCSI_In_DBx__6__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
-SCSI_In_DBx__6__PS EQU CYREG_PRT2_PS
-SCSI_In_DBx__6__SHIFT EQU 0
-SCSI_In_DBx__6__SLW EQU CYREG_PRT2_SLW
-SCSI_In_DBx__7__AG EQU CYREG_PRT6_AG
-SCSI_In_DBx__7__AMUX EQU CYREG_PRT6_AMUX
-SCSI_In_DBx__7__BIE EQU CYREG_PRT6_BIE
-SCSI_In_DBx__7__BIT_MASK EQU CYREG_PRT6_BIT_MASK
-SCSI_In_DBx__7__BYP EQU CYREG_PRT6_BYP
-SCSI_In_DBx__7__CTL EQU CYREG_PRT6_CTL
-SCSI_In_DBx__7__DM0 EQU CYREG_PRT6_DM0
-SCSI_In_DBx__7__DM1 EQU CYREG_PRT6_DM1
-SCSI_In_DBx__7__DM2 EQU CYREG_PRT6_DM2
-SCSI_In_DBx__7__DR EQU CYREG_PRT6_DR
-SCSI_In_DBx__7__INP_DIS EQU CYREG_PRT6_INP_DIS
-SCSI_In_DBx__7__INTTYPE EQU CYREG_PICU6_INTTYPE3
-SCSI_In_DBx__7__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
-SCSI_In_DBx__7__LCD_EN EQU CYREG_PRT6_LCD_EN
-SCSI_In_DBx__7__MASK EQU 0x08
-SCSI_In_DBx__7__PC EQU CYREG_PRT6_PC3
-SCSI_In_DBx__7__PORT EQU 6
-SCSI_In_DBx__7__PRT EQU CYREG_PRT6_PRT
-SCSI_In_DBx__7__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
-SCSI_In_DBx__7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
-SCSI_In_DBx__7__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
-SCSI_In_DBx__7__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
-SCSI_In_DBx__7__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
-SCSI_In_DBx__7__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
-SCSI_In_DBx__7__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
-SCSI_In_DBx__7__PS EQU CYREG_PRT6_PS
-SCSI_In_DBx__7__SHIFT EQU 3
-SCSI_In_DBx__7__SLW EQU CYREG_PRT6_SLW
-SCSI_In_DBx__DB0__AG EQU CYREG_PRT6_AG
-SCSI_In_DBx__DB0__AMUX EQU CYREG_PRT6_AMUX
-SCSI_In_DBx__DB0__BIE EQU CYREG_PRT6_BIE
-SCSI_In_DBx__DB0__BIT_MASK EQU CYREG_PRT6_BIT_MASK
-SCSI_In_DBx__DB0__BYP EQU CYREG_PRT6_BYP
-SCSI_In_DBx__DB0__CTL EQU CYREG_PRT6_CTL
-SCSI_In_DBx__DB0__DM0 EQU CYREG_PRT6_DM0
-SCSI_In_DBx__DB0__DM1 EQU CYREG_PRT6_DM1
-SCSI_In_DBx__DB0__DM2 EQU CYREG_PRT6_DM2
-SCSI_In_DBx__DB0__DR EQU CYREG_PRT6_DR
-SCSI_In_DBx__DB0__INP_DIS EQU CYREG_PRT6_INP_DIS
-SCSI_In_DBx__DB0__INTTYPE EQU CYREG_PICU6_INTTYPE6
-SCSI_In_DBx__DB0__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
-SCSI_In_DBx__DB0__LCD_EN EQU CYREG_PRT6_LCD_EN
-SCSI_In_DBx__DB0__MASK EQU 0x40
-SCSI_In_DBx__DB0__PC EQU CYREG_PRT6_PC6
-SCSI_In_DBx__DB0__PORT EQU 6
-SCSI_In_DBx__DB0__PRT EQU CYREG_PRT6_PRT
-SCSI_In_DBx__DB0__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
-SCSI_In_DBx__DB0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
-SCSI_In_DBx__DB0__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
-SCSI_In_DBx__DB0__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
-SCSI_In_DBx__DB0__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
-SCSI_In_DBx__DB0__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
-SCSI_In_DBx__DB0__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
-SCSI_In_DBx__DB0__PS EQU CYREG_PRT6_PS
-SCSI_In_DBx__DB0__SHIFT EQU 6
-SCSI_In_DBx__DB0__SLW EQU CYREG_PRT6_SLW
-SCSI_In_DBx__DB1__AG EQU CYREG_PRT6_AG
-SCSI_In_DBx__DB1__AMUX EQU CYREG_PRT6_AMUX
-SCSI_In_DBx__DB1__BIE EQU CYREG_PRT6_BIE
-SCSI_In_DBx__DB1__BIT_MASK EQU CYREG_PRT6_BIT_MASK
-SCSI_In_DBx__DB1__BYP EQU CYREG_PRT6_BYP
-SCSI_In_DBx__DB1__CTL EQU CYREG_PRT6_CTL
-SCSI_In_DBx__DB1__DM0 EQU CYREG_PRT6_DM0
-SCSI_In_DBx__DB1__DM1 EQU CYREG_PRT6_DM1
-SCSI_In_DBx__DB1__DM2 EQU CYREG_PRT6_DM2
-SCSI_In_DBx__DB1__DR EQU CYREG_PRT6_DR
-SCSI_In_DBx__DB1__INP_DIS EQU CYREG_PRT6_INP_DIS
-SCSI_In_DBx__DB1__INTTYPE EQU CYREG_PICU6_INTTYPE4
-SCSI_In_DBx__DB1__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
-SCSI_In_DBx__DB1__LCD_EN EQU CYREG_PRT6_LCD_EN
-SCSI_In_DBx__DB1__MASK EQU 0x10
-SCSI_In_DBx__DB1__PC EQU CYREG_PRT6_PC4
-SCSI_In_DBx__DB1__PORT EQU 6
-SCSI_In_DBx__DB1__PRT EQU CYREG_PRT6_PRT
-SCSI_In_DBx__DB1__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
-SCSI_In_DBx__DB1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
-SCSI_In_DBx__DB1__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
-SCSI_In_DBx__DB1__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
-SCSI_In_DBx__DB1__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
-SCSI_In_DBx__DB1__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
-SCSI_In_DBx__DB1__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
-SCSI_In_DBx__DB1__PS EQU CYREG_PRT6_PS
-SCSI_In_DBx__DB1__SHIFT EQU 4
-SCSI_In_DBx__DB1__SLW EQU CYREG_PRT6_SLW
-SCSI_In_DBx__DB2__AG EQU CYREG_PRT12_AG
-SCSI_In_DBx__DB2__BIE EQU CYREG_PRT12_BIE
-SCSI_In_DBx__DB2__BIT_MASK EQU CYREG_PRT12_BIT_MASK
-SCSI_In_DBx__DB2__BYP EQU CYREG_PRT12_BYP
-SCSI_In_DBx__DB2__DM0 EQU CYREG_PRT12_DM0
-SCSI_In_DBx__DB2__DM1 EQU CYREG_PRT12_DM1
-SCSI_In_DBx__DB2__DM2 EQU CYREG_PRT12_DM2
-SCSI_In_DBx__DB2__DR EQU CYREG_PRT12_DR
-SCSI_In_DBx__DB2__INP_DIS EQU CYREG_PRT12_INP_DIS
-SCSI_In_DBx__DB2__INTTYPE EQU CYREG_PICU12_INTTYPE4
-SCSI_In_DBx__DB2__MASK EQU 0x10
-SCSI_In_DBx__DB2__PC EQU CYREG_PRT12_PC4
-SCSI_In_DBx__DB2__PORT EQU 12
-SCSI_In_DBx__DB2__PRT EQU CYREG_PRT12_PRT
-SCSI_In_DBx__DB2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN
-SCSI_In_DBx__DB2__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0
-SCSI_In_DBx__DB2__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1
-SCSI_In_DBx__DB2__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0
-SCSI_In_DBx__DB2__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1
-SCSI_In_DBx__DB2__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT
-SCSI_In_DBx__DB2__PS EQU CYREG_PRT12_PS
-SCSI_In_DBx__DB2__SHIFT EQU 4
-SCSI_In_DBx__DB2__SIO_CFG EQU CYREG_PRT12_SIO_CFG
-SCSI_In_DBx__DB2__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF
-SCSI_In_DBx__DB2__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN
-SCSI_In_DBx__DB2__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ
-SCSI_In_DBx__DB2__SLW EQU CYREG_PRT12_SLW
-SCSI_In_DBx__DB3__AG EQU CYREG_PRT2_AG
-SCSI_In_DBx__DB3__AMUX EQU CYREG_PRT2_AMUX
-SCSI_In_DBx__DB3__BIE EQU CYREG_PRT2_BIE
-SCSI_In_DBx__DB3__BIT_MASK EQU CYREG_PRT2_BIT_MASK
-SCSI_In_DBx__DB3__BYP EQU CYREG_PRT2_BYP
-SCSI_In_DBx__DB3__CTL EQU CYREG_PRT2_CTL
-SCSI_In_DBx__DB3__DM0 EQU CYREG_PRT2_DM0
-SCSI_In_DBx__DB3__DM1 EQU CYREG_PRT2_DM1
-SCSI_In_DBx__DB3__DM2 EQU CYREG_PRT2_DM2
-SCSI_In_DBx__DB3__DR EQU CYREG_PRT2_DR
-SCSI_In_DBx__DB3__INP_DIS EQU CYREG_PRT2_INP_DIS
-SCSI_In_DBx__DB3__INTTYPE EQU CYREG_PICU2_INTTYPE6
-SCSI_In_DBx__DB3__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
-SCSI_In_DBx__DB3__LCD_EN EQU CYREG_PRT2_LCD_EN
-SCSI_In_DBx__DB3__MASK EQU 0x40
-SCSI_In_DBx__DB3__PC EQU CYREG_PRT2_PC6
-SCSI_In_DBx__DB3__PORT EQU 2
-SCSI_In_DBx__DB3__PRT EQU CYREG_PRT2_PRT
-SCSI_In_DBx__DB3__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
-SCSI_In_DBx__DB3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
-SCSI_In_DBx__DB3__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
-SCSI_In_DBx__DB3__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
-SCSI_In_DBx__DB3__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
-SCSI_In_DBx__DB3__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
-SCSI_In_DBx__DB3__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
-SCSI_In_DBx__DB3__PS EQU CYREG_PRT2_PS
-SCSI_In_DBx__DB3__SHIFT EQU 6
-SCSI_In_DBx__DB3__SLW EQU CYREG_PRT2_SLW
-SCSI_In_DBx__DB4__AG EQU CYREG_PRT2_AG
-SCSI_In_DBx__DB4__AMUX EQU CYREG_PRT2_AMUX
-SCSI_In_DBx__DB4__BIE EQU CYREG_PRT2_BIE
-SCSI_In_DBx__DB4__BIT_MASK EQU CYREG_PRT2_BIT_MASK
-SCSI_In_DBx__DB4__BYP EQU CYREG_PRT2_BYP
-SCSI_In_DBx__DB4__CTL EQU CYREG_PRT2_CTL
-SCSI_In_DBx__DB4__DM0 EQU CYREG_PRT2_DM0
-SCSI_In_DBx__DB4__DM1 EQU CYREG_PRT2_DM1
-SCSI_In_DBx__DB4__DM2 EQU CYREG_PRT2_DM2
-SCSI_In_DBx__DB4__DR EQU CYREG_PRT2_DR
-SCSI_In_DBx__DB4__INP_DIS EQU CYREG_PRT2_INP_DIS
-SCSI_In_DBx__DB4__INTTYPE EQU CYREG_PICU2_INTTYPE4
-SCSI_In_DBx__DB4__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
-SCSI_In_DBx__DB4__LCD_EN EQU CYREG_PRT2_LCD_EN
-SCSI_In_DBx__DB4__MASK EQU 0x10
-SCSI_In_DBx__DB4__PC EQU CYREG_PRT2_PC4
-SCSI_In_DBx__DB4__PORT EQU 2
-SCSI_In_DBx__DB4__PRT EQU CYREG_PRT2_PRT
-SCSI_In_DBx__DB4__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
-SCSI_In_DBx__DB4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
-SCSI_In_DBx__DB4__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
-SCSI_In_DBx__DB4__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
-SCSI_In_DBx__DB4__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
-SCSI_In_DBx__DB4__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
-SCSI_In_DBx__DB4__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
-SCSI_In_DBx__DB4__PS EQU CYREG_PRT2_PS
-SCSI_In_DBx__DB4__SHIFT EQU 4
-SCSI_In_DBx__DB4__SLW EQU CYREG_PRT2_SLW
-SCSI_In_DBx__DB5__AG EQU CYREG_PRT2_AG
-SCSI_In_DBx__DB5__AMUX EQU CYREG_PRT2_AMUX
-SCSI_In_DBx__DB5__BIE EQU CYREG_PRT2_BIE
-SCSI_In_DBx__DB5__BIT_MASK EQU CYREG_PRT2_BIT_MASK
-SCSI_In_DBx__DB5__BYP EQU CYREG_PRT2_BYP
-SCSI_In_DBx__DB5__CTL EQU CYREG_PRT2_CTL
-SCSI_In_DBx__DB5__DM0 EQU CYREG_PRT2_DM0
-SCSI_In_DBx__DB5__DM1 EQU CYREG_PRT2_DM1
-SCSI_In_DBx__DB5__DM2 EQU CYREG_PRT2_DM2
-SCSI_In_DBx__DB5__DR EQU CYREG_PRT2_DR
-SCSI_In_DBx__DB5__INP_DIS EQU CYREG_PRT2_INP_DIS
-SCSI_In_DBx__DB5__INTTYPE EQU CYREG_PICU2_INTTYPE2
-SCSI_In_DBx__DB5__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
-SCSI_In_DBx__DB5__LCD_EN EQU CYREG_PRT2_LCD_EN
-SCSI_In_DBx__DB5__MASK EQU 0x04
-SCSI_In_DBx__DB5__PC EQU CYREG_PRT2_PC2
-SCSI_In_DBx__DB5__PORT EQU 2
-SCSI_In_DBx__DB5__PRT EQU CYREG_PRT2_PRT
-SCSI_In_DBx__DB5__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
-SCSI_In_DBx__DB5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
-SCSI_In_DBx__DB5__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
-SCSI_In_DBx__DB5__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
-SCSI_In_DBx__DB5__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
-SCSI_In_DBx__DB5__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
-SCSI_In_DBx__DB5__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
-SCSI_In_DBx__DB5__PS EQU CYREG_PRT2_PS
-SCSI_In_DBx__DB5__SHIFT EQU 2
-SCSI_In_DBx__DB5__SLW EQU CYREG_PRT2_SLW
-SCSI_In_DBx__DB6__AG EQU CYREG_PRT2_AG
-SCSI_In_DBx__DB6__AMUX EQU CYREG_PRT2_AMUX
-SCSI_In_DBx__DB6__BIE EQU CYREG_PRT2_BIE
-SCSI_In_DBx__DB6__BIT_MASK EQU CYREG_PRT2_BIT_MASK
-SCSI_In_DBx__DB6__BYP EQU CYREG_PRT2_BYP
-SCSI_In_DBx__DB6__CTL EQU CYREG_PRT2_CTL
-SCSI_In_DBx__DB6__DM0 EQU CYREG_PRT2_DM0
-SCSI_In_DBx__DB6__DM1 EQU CYREG_PRT2_DM1
-SCSI_In_DBx__DB6__DM2 EQU CYREG_PRT2_DM2
-SCSI_In_DBx__DB6__DR EQU CYREG_PRT2_DR
-SCSI_In_DBx__DB6__INP_DIS EQU CYREG_PRT2_INP_DIS
-SCSI_In_DBx__DB6__INTTYPE EQU CYREG_PICU2_INTTYPE0
-SCSI_In_DBx__DB6__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
-SCSI_In_DBx__DB6__LCD_EN EQU CYREG_PRT2_LCD_EN
-SCSI_In_DBx__DB6__MASK EQU 0x01
-SCSI_In_DBx__DB6__PC EQU CYREG_PRT2_PC0
-SCSI_In_DBx__DB6__PORT EQU 2
-SCSI_In_DBx__DB6__PRT EQU CYREG_PRT2_PRT
-SCSI_In_DBx__DB6__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
-SCSI_In_DBx__DB6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
-SCSI_In_DBx__DB6__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
-SCSI_In_DBx__DB6__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
-SCSI_In_DBx__DB6__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
-SCSI_In_DBx__DB6__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
-SCSI_In_DBx__DB6__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
-SCSI_In_DBx__DB6__PS EQU CYREG_PRT2_PS
-SCSI_In_DBx__DB6__SHIFT EQU 0
-SCSI_In_DBx__DB6__SLW EQU CYREG_PRT2_SLW
-SCSI_In_DBx__DB7__AG EQU CYREG_PRT6_AG
-SCSI_In_DBx__DB7__AMUX EQU CYREG_PRT6_AMUX
-SCSI_In_DBx__DB7__BIE EQU CYREG_PRT6_BIE
-SCSI_In_DBx__DB7__BIT_MASK EQU CYREG_PRT6_BIT_MASK
-SCSI_In_DBx__DB7__BYP EQU CYREG_PRT6_BYP
-SCSI_In_DBx__DB7__CTL EQU CYREG_PRT6_CTL
-SCSI_In_DBx__DB7__DM0 EQU CYREG_PRT6_DM0
-SCSI_In_DBx__DB7__DM1 EQU CYREG_PRT6_DM1
-SCSI_In_DBx__DB7__DM2 EQU CYREG_PRT6_DM2
-SCSI_In_DBx__DB7__DR EQU CYREG_PRT6_DR
-SCSI_In_DBx__DB7__INP_DIS EQU CYREG_PRT6_INP_DIS
-SCSI_In_DBx__DB7__INTTYPE EQU CYREG_PICU6_INTTYPE3
-SCSI_In_DBx__DB7__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
-SCSI_In_DBx__DB7__LCD_EN EQU CYREG_PRT6_LCD_EN
-SCSI_In_DBx__DB7__MASK EQU 0x08
-SCSI_In_DBx__DB7__PC EQU CYREG_PRT6_PC3
-SCSI_In_DBx__DB7__PORT EQU 6
-SCSI_In_DBx__DB7__PRT EQU CYREG_PRT6_PRT
-SCSI_In_DBx__DB7__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
-SCSI_In_DBx__DB7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
-SCSI_In_DBx__DB7__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
-SCSI_In_DBx__DB7__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
-SCSI_In_DBx__DB7__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
-SCSI_In_DBx__DB7__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
-SCSI_In_DBx__DB7__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
-SCSI_In_DBx__DB7__PS EQU CYREG_PRT6_PS
-SCSI_In_DBx__DB7__SHIFT EQU 3
-SCSI_In_DBx__DB7__SLW EQU CYREG_PRT6_SLW
-
-; SD_MISO
-SD_MISO__0__INTTYPE EQU CYREG_PICU3_INTTYPE2
-SD_MISO__0__MASK EQU 0x04
-SD_MISO__0__PC EQU CYREG_PRT3_PC2
-SD_MISO__0__PORT EQU 3
-SD_MISO__0__SHIFT EQU 2
-SD_MISO__AG EQU CYREG_PRT3_AG
-SD_MISO__AMUX EQU CYREG_PRT3_AMUX
-SD_MISO__BIE EQU CYREG_PRT3_BIE
-SD_MISO__BIT_MASK EQU CYREG_PRT3_BIT_MASK
-SD_MISO__BYP EQU CYREG_PRT3_BYP
-SD_MISO__CTL EQU CYREG_PRT3_CTL
-SD_MISO__DM0 EQU CYREG_PRT3_DM0
-SD_MISO__DM1 EQU CYREG_PRT3_DM1
-SD_MISO__DM2 EQU CYREG_PRT3_DM2
-SD_MISO__DR EQU CYREG_PRT3_DR
-SD_MISO__INP_DIS EQU CYREG_PRT3_INP_DIS
-SD_MISO__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE
-SD_MISO__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG
-SD_MISO__LCD_EN EQU CYREG_PRT3_LCD_EN
-SD_MISO__MASK EQU 0x04
-SD_MISO__PORT EQU 3
-SD_MISO__PRT EQU CYREG_PRT3_PRT
-SD_MISO__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL
-SD_MISO__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN
-SD_MISO__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0
-SD_MISO__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1
-SD_MISO__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0
-SD_MISO__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1
-SD_MISO__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT
-SD_MISO__PS EQU CYREG_PRT3_PS
-SD_MISO__SHIFT EQU 2
-SD_MISO__SLW EQU CYREG_PRT3_SLW
-
-; SD_MOSI
-SD_MOSI__0__INTTYPE EQU CYREG_PICU3_INTTYPE4
-SD_MOSI__0__MASK EQU 0x10
-SD_MOSI__0__PC EQU CYREG_PRT3_PC4
-SD_MOSI__0__PORT EQU 3
-SD_MOSI__0__SHIFT EQU 4
-SD_MOSI__AG EQU CYREG_PRT3_AG
-SD_MOSI__AMUX EQU CYREG_PRT3_AMUX
-SD_MOSI__BIE EQU CYREG_PRT3_BIE
-SD_MOSI__BIT_MASK EQU CYREG_PRT3_BIT_MASK
-SD_MOSI__BYP EQU CYREG_PRT3_BYP
-SD_MOSI__CTL EQU CYREG_PRT3_CTL
-SD_MOSI__DM0 EQU CYREG_PRT3_DM0
-SD_MOSI__DM1 EQU CYREG_PRT3_DM1
-SD_MOSI__DM2 EQU CYREG_PRT3_DM2
-SD_MOSI__DR EQU CYREG_PRT3_DR
-SD_MOSI__INP_DIS EQU CYREG_PRT3_INP_DIS
-SD_MOSI__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE
-SD_MOSI__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG
-SD_MOSI__LCD_EN EQU CYREG_PRT3_LCD_EN
-SD_MOSI__MASK EQU 0x10
-SD_MOSI__PORT EQU 3
-SD_MOSI__PRT EQU CYREG_PRT3_PRT
-SD_MOSI__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL
-SD_MOSI__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN
-SD_MOSI__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0
-SD_MOSI__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1
-SD_MOSI__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0
-SD_MOSI__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1
-SD_MOSI__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT
-SD_MOSI__PS EQU CYREG_PRT3_PS
-SD_MOSI__SHIFT EQU 4
-SD_MOSI__SLW EQU CYREG_PRT3_SLW
-
-; TERM_EN
-TERM_EN__0__INTTYPE EQU CYREG_PICU15_INTTYPE3
-TERM_EN__0__MASK EQU 0x08
-TERM_EN__0__PC EQU CYREG_IO_PC_PRT15_PC3
-TERM_EN__0__PORT EQU 15
-TERM_EN__0__SHIFT EQU 3
-TERM_EN__AG EQU CYREG_PRT15_AG
-TERM_EN__AMUX EQU CYREG_PRT15_AMUX
-TERM_EN__BIE EQU CYREG_PRT15_BIE
-TERM_EN__BIT_MASK EQU CYREG_PRT15_BIT_MASK
-TERM_EN__BYP EQU CYREG_PRT15_BYP
-TERM_EN__CTL EQU CYREG_PRT15_CTL
-TERM_EN__DM0 EQU CYREG_PRT15_DM0
-TERM_EN__DM1 EQU CYREG_PRT15_DM1
-TERM_EN__DM2 EQU CYREG_PRT15_DM2
-TERM_EN__DR EQU CYREG_PRT15_DR
-TERM_EN__INP_DIS EQU CYREG_PRT15_INP_DIS
-TERM_EN__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU15_BASE
-TERM_EN__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG
-TERM_EN__LCD_EN EQU CYREG_PRT15_LCD_EN
-TERM_EN__MASK EQU 0x08
-TERM_EN__PORT EQU 15
-TERM_EN__PRT EQU CYREG_PRT15_PRT
-TERM_EN__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL
-TERM_EN__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN
-TERM_EN__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0
-TERM_EN__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1
-TERM_EN__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0
-TERM_EN__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1
-TERM_EN__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT
-TERM_EN__PS EQU CYREG_PRT15_PS
-TERM_EN__SHIFT EQU 3
-TERM_EN__SLW EQU CYREG_PRT15_SLW
-
-; SCSI_CLK
-SCSI_CLK__CFG0 EQU CYREG_CLKDIST_DCFG1_CFG0
-SCSI_CLK__CFG1 EQU CYREG_CLKDIST_DCFG1_CFG1
-SCSI_CLK__CFG2 EQU CYREG_CLKDIST_DCFG1_CFG2
-SCSI_CLK__CFG2_SRC_SEL_MASK EQU 0x07
-SCSI_CLK__INDEX EQU 0x01
-SCSI_CLK__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2
-SCSI_CLK__PM_ACT_MSK EQU 0x02
-SCSI_CLK__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2
-SCSI_CLK__PM_STBY_MSK EQU 0x02
-
-; SCSI_Out
-SCSI_Out__0__AG EQU CYREG_PRT6_AG
-SCSI_Out__0__AMUX EQU CYREG_PRT6_AMUX
-SCSI_Out__0__BIE EQU CYREG_PRT6_BIE
-SCSI_Out__0__BIT_MASK EQU CYREG_PRT6_BIT_MASK
-SCSI_Out__0__BYP EQU CYREG_PRT6_BYP
-SCSI_Out__0__CTL EQU CYREG_PRT6_CTL
-SCSI_Out__0__DM0 EQU CYREG_PRT6_DM0
-SCSI_Out__0__DM1 EQU CYREG_PRT6_DM1
-SCSI_Out__0__DM2 EQU CYREG_PRT6_DM2
-SCSI_Out__0__DR EQU CYREG_PRT6_DR
-SCSI_Out__0__INP_DIS EQU CYREG_PRT6_INP_DIS
-SCSI_Out__0__INTTYPE EQU CYREG_PICU6_INTTYPE2
-SCSI_Out__0__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
-SCSI_Out__0__LCD_EN EQU CYREG_PRT6_LCD_EN
-SCSI_Out__0__MASK EQU 0x04
-SCSI_Out__0__PC EQU CYREG_PRT6_PC2
-SCSI_Out__0__PORT EQU 6
-SCSI_Out__0__PRT EQU CYREG_PRT6_PRT
-SCSI_Out__0__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
-SCSI_Out__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
-SCSI_Out__0__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
-SCSI_Out__0__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
-SCSI_Out__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
-SCSI_Out__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
-SCSI_Out__0__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
-SCSI_Out__0__PS EQU CYREG_PRT6_PS
-SCSI_Out__0__SHIFT EQU 2
-SCSI_Out__0__SLW EQU CYREG_PRT6_SLW
-SCSI_Out__1__AG EQU CYREG_PRT4_AG
-SCSI_Out__1__AMUX EQU CYREG_PRT4_AMUX
-SCSI_Out__1__BIE EQU CYREG_PRT4_BIE
-SCSI_Out__1__BIT_MASK EQU CYREG_PRT4_BIT_MASK
-SCSI_Out__1__BYP EQU CYREG_PRT4_BYP
-SCSI_Out__1__CTL EQU CYREG_PRT4_CTL
-SCSI_Out__1__DM0 EQU CYREG_PRT4_DM0
-SCSI_Out__1__DM1 EQU CYREG_PRT4_DM1
-SCSI_Out__1__DM2 EQU CYREG_PRT4_DM2
-SCSI_Out__1__DR EQU CYREG_PRT4_DR
-SCSI_Out__1__INP_DIS EQU CYREG_PRT4_INP_DIS
-SCSI_Out__1__INTTYPE EQU CYREG_PICU4_INTTYPE6
-SCSI_Out__1__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
-SCSI_Out__1__LCD_EN EQU CYREG_PRT4_LCD_EN
-SCSI_Out__1__MASK EQU 0x40
-SCSI_Out__1__PC EQU CYREG_PRT4_PC6
-SCSI_Out__1__PORT EQU 4
-SCSI_Out__1__PRT EQU CYREG_PRT4_PRT
-SCSI_Out__1__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
-SCSI_Out__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
-SCSI_Out__1__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
-SCSI_Out__1__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
-SCSI_Out__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
-SCSI_Out__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
-SCSI_Out__1__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
-SCSI_Out__1__PS EQU CYREG_PRT4_PS
-SCSI_Out__1__SHIFT EQU 6
-SCSI_Out__1__SLW EQU CYREG_PRT4_SLW
-SCSI_Out__2__AG EQU CYREG_PRT0_AG
-SCSI_Out__2__AMUX EQU CYREG_PRT0_AMUX
-SCSI_Out__2__BIE EQU CYREG_PRT0_BIE
-SCSI_Out__2__BIT_MASK EQU CYREG_PRT0_BIT_MASK
-SCSI_Out__2__BYP EQU CYREG_PRT0_BYP
-SCSI_Out__2__CTL EQU CYREG_PRT0_CTL
-SCSI_Out__2__DM0 EQU CYREG_PRT0_DM0
-SCSI_Out__2__DM1 EQU CYREG_PRT0_DM1
-SCSI_Out__2__DM2 EQU CYREG_PRT0_DM2
-SCSI_Out__2__DR EQU CYREG_PRT0_DR
-SCSI_Out__2__INP_DIS EQU CYREG_PRT0_INP_DIS
-SCSI_Out__2__INTTYPE EQU CYREG_PICU0_INTTYPE7
-SCSI_Out__2__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
-SCSI_Out__2__LCD_EN EQU CYREG_PRT0_LCD_EN
-SCSI_Out__2__MASK EQU 0x80
-SCSI_Out__2__PC EQU CYREG_PRT0_PC7
-SCSI_Out__2__PORT EQU 0
-SCSI_Out__2__PRT EQU CYREG_PRT0_PRT
-SCSI_Out__2__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
-SCSI_Out__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
-SCSI_Out__2__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
-SCSI_Out__2__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
-SCSI_Out__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
-SCSI_Out__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
-SCSI_Out__2__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
-SCSI_Out__2__PS EQU CYREG_PRT0_PS
-SCSI_Out__2__SHIFT EQU 7
-SCSI_Out__2__SLW EQU CYREG_PRT0_SLW
-SCSI_Out__3__AG EQU CYREG_PRT0_AG
-SCSI_Out__3__AMUX EQU CYREG_PRT0_AMUX
-SCSI_Out__3__BIE EQU CYREG_PRT0_BIE
-SCSI_Out__3__BIT_MASK EQU CYREG_PRT0_BIT_MASK
-SCSI_Out__3__BYP EQU CYREG_PRT0_BYP
-SCSI_Out__3__CTL EQU CYREG_PRT0_CTL
-SCSI_Out__3__DM0 EQU CYREG_PRT0_DM0
-SCSI_Out__3__DM1 EQU CYREG_PRT0_DM1
-SCSI_Out__3__DM2 EQU CYREG_PRT0_DM2
-SCSI_Out__3__DR EQU CYREG_PRT0_DR
-SCSI_Out__3__INP_DIS EQU CYREG_PRT0_INP_DIS
-SCSI_Out__3__INTTYPE EQU CYREG_PICU0_INTTYPE5
-SCSI_Out__3__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
-SCSI_Out__3__LCD_EN EQU CYREG_PRT0_LCD_EN
-SCSI_Out__3__MASK EQU 0x20
-SCSI_Out__3__PC EQU CYREG_PRT0_PC5
-SCSI_Out__3__PORT EQU 0
-SCSI_Out__3__PRT EQU CYREG_PRT0_PRT
-SCSI_Out__3__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
-SCSI_Out__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
-SCSI_Out__3__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
-SCSI_Out__3__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
-SCSI_Out__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
-SCSI_Out__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
-SCSI_Out__3__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
-SCSI_Out__3__PS EQU CYREG_PRT0_PS
-SCSI_Out__3__SHIFT EQU 5
-SCSI_Out__3__SLW EQU CYREG_PRT0_SLW
-SCSI_Out__4__AG EQU CYREG_PRT0_AG
-SCSI_Out__4__AMUX EQU CYREG_PRT0_AMUX
-SCSI_Out__4__BIE EQU CYREG_PRT0_BIE
-SCSI_Out__4__BIT_MASK EQU CYREG_PRT0_BIT_MASK
-SCSI_Out__4__BYP EQU CYREG_PRT0_BYP
-SCSI_Out__4__CTL EQU CYREG_PRT0_CTL
-SCSI_Out__4__DM0 EQU CYREG_PRT0_DM0
-SCSI_Out__4__DM1 EQU CYREG_PRT0_DM1
-SCSI_Out__4__DM2 EQU CYREG_PRT0_DM2
-SCSI_Out__4__DR EQU CYREG_PRT0_DR
-SCSI_Out__4__INP_DIS EQU CYREG_PRT0_INP_DIS
-SCSI_Out__4__INTTYPE EQU CYREG_PICU0_INTTYPE3
-SCSI_Out__4__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
-SCSI_Out__4__LCD_EN EQU CYREG_PRT0_LCD_EN
-SCSI_Out__4__MASK EQU 0x08
-SCSI_Out__4__PC EQU CYREG_PRT0_PC3
-SCSI_Out__4__PORT EQU 0
-SCSI_Out__4__PRT EQU CYREG_PRT0_PRT
-SCSI_Out__4__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
-SCSI_Out__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
-SCSI_Out__4__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
-SCSI_Out__4__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
-SCSI_Out__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
-SCSI_Out__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
-SCSI_Out__4__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
-SCSI_Out__4__PS EQU CYREG_PRT0_PS
-SCSI_Out__4__SHIFT EQU 3
-SCSI_Out__4__SLW EQU CYREG_PRT0_SLW
-SCSI_Out__5__AG EQU CYREG_PRT0_AG
-SCSI_Out__5__AMUX EQU CYREG_PRT0_AMUX
-SCSI_Out__5__BIE EQU CYREG_PRT0_BIE
-SCSI_Out__5__BIT_MASK EQU CYREG_PRT0_BIT_MASK
-SCSI_Out__5__BYP EQU CYREG_PRT0_BYP
-SCSI_Out__5__CTL EQU CYREG_PRT0_CTL
-SCSI_Out__5__DM0 EQU CYREG_PRT0_DM0
-SCSI_Out__5__DM1 EQU CYREG_PRT0_DM1
-SCSI_Out__5__DM2 EQU CYREG_PRT0_DM2
-SCSI_Out__5__DR EQU CYREG_PRT0_DR
-SCSI_Out__5__INP_DIS EQU CYREG_PRT0_INP_DIS
-SCSI_Out__5__INTTYPE EQU CYREG_PICU0_INTTYPE1
-SCSI_Out__5__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
-SCSI_Out__5__LCD_EN EQU CYREG_PRT0_LCD_EN
-SCSI_Out__5__MASK EQU 0x02
-SCSI_Out__5__PC EQU CYREG_PRT0_PC1
-SCSI_Out__5__PORT EQU 0
-SCSI_Out__5__PRT EQU CYREG_PRT0_PRT
-SCSI_Out__5__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
-SCSI_Out__5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
-SCSI_Out__5__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
-SCSI_Out__5__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
-SCSI_Out__5__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
-SCSI_Out__5__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
-SCSI_Out__5__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
-SCSI_Out__5__PS EQU CYREG_PRT0_PS
-SCSI_Out__5__SHIFT EQU 1
-SCSI_Out__5__SLW EQU CYREG_PRT0_SLW
-SCSI_Out__6__AG EQU CYREG_PRT4_AG
-SCSI_Out__6__AMUX EQU CYREG_PRT4_AMUX
-SCSI_Out__6__BIE EQU CYREG_PRT4_BIE
-SCSI_Out__6__BIT_MASK EQU CYREG_PRT4_BIT_MASK
-SCSI_Out__6__BYP EQU CYREG_PRT4_BYP
-SCSI_Out__6__CTL EQU CYREG_PRT4_CTL
-SCSI_Out__6__DM0 EQU CYREG_PRT4_DM0
-SCSI_Out__6__DM1 EQU CYREG_PRT4_DM1
-SCSI_Out__6__DM2 EQU CYREG_PRT4_DM2
-SCSI_Out__6__DR EQU CYREG_PRT4_DR
-SCSI_Out__6__INP_DIS EQU CYREG_PRT4_INP_DIS
-SCSI_Out__6__INTTYPE EQU CYREG_PICU4_INTTYPE1
-SCSI_Out__6__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
-SCSI_Out__6__LCD_EN EQU CYREG_PRT4_LCD_EN
-SCSI_Out__6__MASK EQU 0x02
-SCSI_Out__6__PC EQU CYREG_PRT4_PC1
-SCSI_Out__6__PORT EQU 4
-SCSI_Out__6__PRT EQU CYREG_PRT4_PRT
-SCSI_Out__6__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
-SCSI_Out__6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
-SCSI_Out__6__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
-SCSI_Out__6__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
-SCSI_Out__6__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
-SCSI_Out__6__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
-SCSI_Out__6__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
-SCSI_Out__6__PS EQU CYREG_PRT4_PS
-SCSI_Out__6__SHIFT EQU 1
-SCSI_Out__6__SLW EQU CYREG_PRT4_SLW
-SCSI_Out__7__AG EQU CYREG_PRT12_AG
-SCSI_Out__7__BIE EQU CYREG_PRT12_BIE
-SCSI_Out__7__BIT_MASK EQU CYREG_PRT12_BIT_MASK
-SCSI_Out__7__BYP EQU CYREG_PRT12_BYP
-SCSI_Out__7__DM0 EQU CYREG_PRT12_DM0
-SCSI_Out__7__DM1 EQU CYREG_PRT12_DM1
-SCSI_Out__7__DM2 EQU CYREG_PRT12_DM2
-SCSI_Out__7__DR EQU CYREG_PRT12_DR
-SCSI_Out__7__INP_DIS EQU CYREG_PRT12_INP_DIS
-SCSI_Out__7__INTTYPE EQU CYREG_PICU12_INTTYPE3
-SCSI_Out__7__MASK EQU 0x08
-SCSI_Out__7__PC EQU CYREG_PRT12_PC3
-SCSI_Out__7__PORT EQU 12
-SCSI_Out__7__PRT EQU CYREG_PRT12_PRT
-SCSI_Out__7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN
-SCSI_Out__7__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0
-SCSI_Out__7__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1
-SCSI_Out__7__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0
-SCSI_Out__7__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1
-SCSI_Out__7__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT
-SCSI_Out__7__PS EQU CYREG_PRT12_PS
-SCSI_Out__7__SHIFT EQU 3
-SCSI_Out__7__SIO_CFG EQU CYREG_PRT12_SIO_CFG
-SCSI_Out__7__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF
-SCSI_Out__7__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN
-SCSI_Out__7__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ
-SCSI_Out__7__SLW EQU CYREG_PRT12_SLW
-SCSI_Out__BSY__AG EQU CYREG_PRT4_AG
-SCSI_Out__BSY__AMUX EQU CYREG_PRT4_AMUX
-SCSI_Out__BSY__BIE EQU CYREG_PRT4_BIE
-SCSI_Out__BSY__BIT_MASK EQU CYREG_PRT4_BIT_MASK
-SCSI_Out__BSY__BYP EQU CYREG_PRT4_BYP
-SCSI_Out__BSY__CTL EQU CYREG_PRT4_CTL
-SCSI_Out__BSY__DM0 EQU CYREG_PRT4_DM0
-SCSI_Out__BSY__DM1 EQU CYREG_PRT4_DM1
-SCSI_Out__BSY__DM2 EQU CYREG_PRT4_DM2
-SCSI_Out__BSY__DR EQU CYREG_PRT4_DR
-SCSI_Out__BSY__INP_DIS EQU CYREG_PRT4_INP_DIS
-SCSI_Out__BSY__INTTYPE EQU CYREG_PICU4_INTTYPE6
-SCSI_Out__BSY__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
-SCSI_Out__BSY__LCD_EN EQU CYREG_PRT4_LCD_EN
-SCSI_Out__BSY__MASK EQU 0x40
-SCSI_Out__BSY__PC EQU CYREG_PRT4_PC6
-SCSI_Out__BSY__PORT EQU 4
-SCSI_Out__BSY__PRT EQU CYREG_PRT4_PRT
-SCSI_Out__BSY__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
-SCSI_Out__BSY__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
-SCSI_Out__BSY__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
-SCSI_Out__BSY__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
-SCSI_Out__BSY__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
-SCSI_Out__BSY__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
-SCSI_Out__BSY__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
-SCSI_Out__BSY__PS EQU CYREG_PRT4_PS
-SCSI_Out__BSY__SHIFT EQU 6
-SCSI_Out__BSY__SLW EQU CYREG_PRT4_SLW
-SCSI_Out__CD_raw__AG EQU CYREG_PRT0_AG
-SCSI_Out__CD_raw__AMUX EQU CYREG_PRT0_AMUX
-SCSI_Out__CD_raw__BIE EQU CYREG_PRT0_BIE
-SCSI_Out__CD_raw__BIT_MASK EQU CYREG_PRT0_BIT_MASK
-SCSI_Out__CD_raw__BYP EQU CYREG_PRT0_BYP
-SCSI_Out__CD_raw__CTL EQU CYREG_PRT0_CTL
-SCSI_Out__CD_raw__DM0 EQU CYREG_PRT0_DM0
-SCSI_Out__CD_raw__DM1 EQU CYREG_PRT0_DM1
-SCSI_Out__CD_raw__DM2 EQU CYREG_PRT0_DM2
-SCSI_Out__CD_raw__DR EQU CYREG_PRT0_DR
-SCSI_Out__CD_raw__INP_DIS EQU CYREG_PRT0_INP_DIS
-SCSI_Out__CD_raw__INTTYPE EQU CYREG_PICU0_INTTYPE1
-SCSI_Out__CD_raw__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
-SCSI_Out__CD_raw__LCD_EN EQU CYREG_PRT0_LCD_EN
-SCSI_Out__CD_raw__MASK EQU 0x02
-SCSI_Out__CD_raw__PC EQU CYREG_PRT0_PC1
-SCSI_Out__CD_raw__PORT EQU 0
-SCSI_Out__CD_raw__PRT EQU CYREG_PRT0_PRT
-SCSI_Out__CD_raw__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
-SCSI_Out__CD_raw__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
-SCSI_Out__CD_raw__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
-SCSI_Out__CD_raw__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
-SCSI_Out__CD_raw__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
-SCSI_Out__CD_raw__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
-SCSI_Out__CD_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
-SCSI_Out__CD_raw__PS EQU CYREG_PRT0_PS
-SCSI_Out__CD_raw__SHIFT EQU 1
-SCSI_Out__CD_raw__SLW EQU CYREG_PRT0_SLW
-SCSI_Out__DBP_raw__AG EQU CYREG_PRT6_AG
-SCSI_Out__DBP_raw__AMUX EQU CYREG_PRT6_AMUX
-SCSI_Out__DBP_raw__BIE EQU CYREG_PRT6_BIE
-SCSI_Out__DBP_raw__BIT_MASK EQU CYREG_PRT6_BIT_MASK
-SCSI_Out__DBP_raw__BYP EQU CYREG_PRT6_BYP
-SCSI_Out__DBP_raw__CTL EQU CYREG_PRT6_CTL
-SCSI_Out__DBP_raw__DM0 EQU CYREG_PRT6_DM0
-SCSI_Out__DBP_raw__DM1 EQU CYREG_PRT6_DM1
-SCSI_Out__DBP_raw__DM2 EQU CYREG_PRT6_DM2
-SCSI_Out__DBP_raw__DR EQU CYREG_PRT6_DR
-SCSI_Out__DBP_raw__INP_DIS EQU CYREG_PRT6_INP_DIS
-SCSI_Out__DBP_raw__INTTYPE EQU CYREG_PICU6_INTTYPE2
-SCSI_Out__DBP_raw__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
-SCSI_Out__DBP_raw__LCD_EN EQU CYREG_PRT6_LCD_EN
-SCSI_Out__DBP_raw__MASK EQU 0x04
-SCSI_Out__DBP_raw__PC EQU CYREG_PRT6_PC2
-SCSI_Out__DBP_raw__PORT EQU 6
-SCSI_Out__DBP_raw__PRT EQU CYREG_PRT6_PRT
-SCSI_Out__DBP_raw__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
-SCSI_Out__DBP_raw__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
-SCSI_Out__DBP_raw__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
-SCSI_Out__DBP_raw__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
-SCSI_Out__DBP_raw__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
-SCSI_Out__DBP_raw__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
-SCSI_Out__DBP_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
-SCSI_Out__DBP_raw__PS EQU CYREG_PRT6_PS
-SCSI_Out__DBP_raw__SHIFT EQU 2
-SCSI_Out__DBP_raw__SLW EQU CYREG_PRT6_SLW
-SCSI_Out__IO_raw__AG EQU CYREG_PRT12_AG
-SCSI_Out__IO_raw__BIE EQU CYREG_PRT12_BIE
-SCSI_Out__IO_raw__BIT_MASK EQU CYREG_PRT12_BIT_MASK
-SCSI_Out__IO_raw__BYP EQU CYREG_PRT12_BYP
-SCSI_Out__IO_raw__DM0 EQU CYREG_PRT12_DM0
-SCSI_Out__IO_raw__DM1 EQU CYREG_PRT12_DM1
-SCSI_Out__IO_raw__DM2 EQU CYREG_PRT12_DM2
-SCSI_Out__IO_raw__DR EQU CYREG_PRT12_DR
-SCSI_Out__IO_raw__INP_DIS EQU CYREG_PRT12_INP_DIS
-SCSI_Out__IO_raw__INTTYPE EQU CYREG_PICU12_INTTYPE3
-SCSI_Out__IO_raw__MASK EQU 0x08
-SCSI_Out__IO_raw__PC EQU CYREG_PRT12_PC3
-SCSI_Out__IO_raw__PORT EQU 12
-SCSI_Out__IO_raw__PRT EQU CYREG_PRT12_PRT
-SCSI_Out__IO_raw__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN
-SCSI_Out__IO_raw__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0
-SCSI_Out__IO_raw__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1
-SCSI_Out__IO_raw__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0
-SCSI_Out__IO_raw__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1
-SCSI_Out__IO_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT
-SCSI_Out__IO_raw__PS EQU CYREG_PRT12_PS
-SCSI_Out__IO_raw__SHIFT EQU 3
-SCSI_Out__IO_raw__SIO_CFG EQU CYREG_PRT12_SIO_CFG
-SCSI_Out__IO_raw__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF
-SCSI_Out__IO_raw__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN
-SCSI_Out__IO_raw__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ
-SCSI_Out__IO_raw__SLW EQU CYREG_PRT12_SLW
-SCSI_Out__MSG_raw__AG EQU CYREG_PRT0_AG
-SCSI_Out__MSG_raw__AMUX EQU CYREG_PRT0_AMUX
-SCSI_Out__MSG_raw__BIE EQU CYREG_PRT0_BIE
-SCSI_Out__MSG_raw__BIT_MASK EQU CYREG_PRT0_BIT_MASK
-SCSI_Out__MSG_raw__BYP EQU CYREG_PRT0_BYP
-SCSI_Out__MSG_raw__CTL EQU CYREG_PRT0_CTL
-SCSI_Out__MSG_raw__DM0 EQU CYREG_PRT0_DM0
-SCSI_Out__MSG_raw__DM1 EQU CYREG_PRT0_DM1
-SCSI_Out__MSG_raw__DM2 EQU CYREG_PRT0_DM2
-SCSI_Out__MSG_raw__DR EQU CYREG_PRT0_DR
-SCSI_Out__MSG_raw__INP_DIS EQU CYREG_PRT0_INP_DIS
-SCSI_Out__MSG_raw__INTTYPE EQU CYREG_PICU0_INTTYPE5
-SCSI_Out__MSG_raw__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
-SCSI_Out__MSG_raw__LCD_EN EQU CYREG_PRT0_LCD_EN
-SCSI_Out__MSG_raw__MASK EQU 0x20
-SCSI_Out__MSG_raw__PC EQU CYREG_PRT0_PC5
-SCSI_Out__MSG_raw__PORT EQU 0
-SCSI_Out__MSG_raw__PRT EQU CYREG_PRT0_PRT
-SCSI_Out__MSG_raw__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
-SCSI_Out__MSG_raw__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
-SCSI_Out__MSG_raw__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
-SCSI_Out__MSG_raw__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
-SCSI_Out__MSG_raw__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
-SCSI_Out__MSG_raw__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
-SCSI_Out__MSG_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
-SCSI_Out__MSG_raw__PS EQU CYREG_PRT0_PS
-SCSI_Out__MSG_raw__SHIFT EQU 5
-SCSI_Out__MSG_raw__SLW EQU CYREG_PRT0_SLW
-SCSI_Out__REQ__AG EQU CYREG_PRT4_AG
-SCSI_Out__REQ__AMUX EQU CYREG_PRT4_AMUX
-SCSI_Out__REQ__BIE EQU CYREG_PRT4_BIE
-SCSI_Out__REQ__BIT_MASK EQU CYREG_PRT4_BIT_MASK
-SCSI_Out__REQ__BYP EQU CYREG_PRT4_BYP
-SCSI_Out__REQ__CTL EQU CYREG_PRT4_CTL
-SCSI_Out__REQ__DM0 EQU CYREG_PRT4_DM0
-SCSI_Out__REQ__DM1 EQU CYREG_PRT4_DM1
-SCSI_Out__REQ__DM2 EQU CYREG_PRT4_DM2
-SCSI_Out__REQ__DR EQU CYREG_PRT4_DR
-SCSI_Out__REQ__INP_DIS EQU CYREG_PRT4_INP_DIS
-SCSI_Out__REQ__INTTYPE EQU CYREG_PICU4_INTTYPE1
-SCSI_Out__REQ__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
-SCSI_Out__REQ__LCD_EN EQU CYREG_PRT4_LCD_EN
-SCSI_Out__REQ__MASK EQU 0x02
-SCSI_Out__REQ__PC EQU CYREG_PRT4_PC1
-SCSI_Out__REQ__PORT EQU 4
-SCSI_Out__REQ__PRT EQU CYREG_PRT4_PRT
-SCSI_Out__REQ__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
-SCSI_Out__REQ__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
-SCSI_Out__REQ__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
-SCSI_Out__REQ__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
-SCSI_Out__REQ__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
-SCSI_Out__REQ__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
-SCSI_Out__REQ__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
-SCSI_Out__REQ__PS EQU CYREG_PRT4_PS
-SCSI_Out__REQ__SHIFT EQU 1
-SCSI_Out__REQ__SLW EQU CYREG_PRT4_SLW
-SCSI_Out__RST__AG EQU CYREG_PRT0_AG
-SCSI_Out__RST__AMUX EQU CYREG_PRT0_AMUX
-SCSI_Out__RST__BIE EQU CYREG_PRT0_BIE
-SCSI_Out__RST__BIT_MASK EQU CYREG_PRT0_BIT_MASK
-SCSI_Out__RST__BYP EQU CYREG_PRT0_BYP
-SCSI_Out__RST__CTL EQU CYREG_PRT0_CTL
-SCSI_Out__RST__DM0 EQU CYREG_PRT0_DM0
-SCSI_Out__RST__DM1 EQU CYREG_PRT0_DM1
-SCSI_Out__RST__DM2 EQU CYREG_PRT0_DM2
-SCSI_Out__RST__DR EQU CYREG_PRT0_DR
-SCSI_Out__RST__INP_DIS EQU CYREG_PRT0_INP_DIS
-SCSI_Out__RST__INTTYPE EQU CYREG_PICU0_INTTYPE7
-SCSI_Out__RST__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
-SCSI_Out__RST__LCD_EN EQU CYREG_PRT0_LCD_EN
-SCSI_Out__RST__MASK EQU 0x80
-SCSI_Out__RST__PC EQU CYREG_PRT0_PC7
-SCSI_Out__RST__PORT EQU 0
-SCSI_Out__RST__PRT EQU CYREG_PRT0_PRT
-SCSI_Out__RST__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
-SCSI_Out__RST__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
-SCSI_Out__RST__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
-SCSI_Out__RST__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
-SCSI_Out__RST__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
-SCSI_Out__RST__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
-SCSI_Out__RST__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
-SCSI_Out__RST__PS EQU CYREG_PRT0_PS
-SCSI_Out__RST__SHIFT EQU 7
-SCSI_Out__RST__SLW EQU CYREG_PRT0_SLW
-SCSI_Out__SEL__AG EQU CYREG_PRT0_AG
-SCSI_Out__SEL__AMUX EQU CYREG_PRT0_AMUX
-SCSI_Out__SEL__BIE EQU CYREG_PRT0_BIE
-SCSI_Out__SEL__BIT_MASK EQU CYREG_PRT0_BIT_MASK
-SCSI_Out__SEL__BYP EQU CYREG_PRT0_BYP
-SCSI_Out__SEL__CTL EQU CYREG_PRT0_CTL
-SCSI_Out__SEL__DM0 EQU CYREG_PRT0_DM0
-SCSI_Out__SEL__DM1 EQU CYREG_PRT0_DM1
-SCSI_Out__SEL__DM2 EQU CYREG_PRT0_DM2
-SCSI_Out__SEL__DR EQU CYREG_PRT0_DR
-SCSI_Out__SEL__INP_DIS EQU CYREG_PRT0_INP_DIS
-SCSI_Out__SEL__INTTYPE EQU CYREG_PICU0_INTTYPE3
-SCSI_Out__SEL__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
-SCSI_Out__SEL__LCD_EN EQU CYREG_PRT0_LCD_EN
-SCSI_Out__SEL__MASK EQU 0x08
-SCSI_Out__SEL__PC EQU CYREG_PRT0_PC3
-SCSI_Out__SEL__PORT EQU 0
-SCSI_Out__SEL__PRT EQU CYREG_PRT0_PRT
-SCSI_Out__SEL__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
-SCSI_Out__SEL__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
-SCSI_Out__SEL__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
-SCSI_Out__SEL__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
-SCSI_Out__SEL__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
-SCSI_Out__SEL__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
-SCSI_Out__SEL__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
-SCSI_Out__SEL__PS EQU CYREG_PRT0_PS
-SCSI_Out__SEL__SHIFT EQU 3
-SCSI_Out__SEL__SLW EQU CYREG_PRT0_SLW
-
-; SCSI_Out_Bits
-SCSI_Out_Bits_Sync_ctrl_reg__0__MASK EQU 0x01
-SCSI_Out_Bits_Sync_ctrl_reg__0__POS EQU 0
-SCSI_Out_Bits_Sync_ctrl_reg__1__MASK EQU 0x02
-SCSI_Out_Bits_Sync_ctrl_reg__1__POS EQU 1
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB07_08_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB07_08_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB07_08_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB07_08_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB07_08_MSK
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB07_08_MSK
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB07_08_MSK
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB07_08_MSK
-SCSI_Out_Bits_Sync_ctrl_reg__2__MASK EQU 0x04
-SCSI_Out_Bits_Sync_ctrl_reg__2__POS EQU 2
-SCSI_Out_Bits_Sync_ctrl_reg__3__MASK EQU 0x08
-SCSI_Out_Bits_Sync_ctrl_reg__3__POS EQU 3
-SCSI_Out_Bits_Sync_ctrl_reg__4__MASK EQU 0x10
-SCSI_Out_Bits_Sync_ctrl_reg__4__POS EQU 4
-SCSI_Out_Bits_Sync_ctrl_reg__5__MASK EQU 0x20
-SCSI_Out_Bits_Sync_ctrl_reg__5__POS EQU 5
-SCSI_Out_Bits_Sync_ctrl_reg__6__MASK EQU 0x40
-SCSI_Out_Bits_Sync_ctrl_reg__6__POS EQU 6
-SCSI_Out_Bits_Sync_ctrl_reg__7__MASK EQU 0x80
-SCSI_Out_Bits_Sync_ctrl_reg__7__POS EQU 7
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB07_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB07_ST_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB07_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB07_ST_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__MASK EQU 0xFF
-SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL
-SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL
-SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB07_MSK
-
-; SCSI_Out_Ctl
-SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01
-SCSI_Out_Ctl_Sync_ctrl_reg__0__POS EQU 0
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB11_12_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB11_12_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB11_12_MSK
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB11_12_MSK
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB11_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB11_ST_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB11_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB11_ST_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__MASK EQU 0x01
-SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
-SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
-SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB11_MSK
-
-; SCSI_Out_DBx
-SCSI_Out_DBx__0__AG EQU CYREG_PRT6_AG
-SCSI_Out_DBx__0__AMUX EQU CYREG_PRT6_AMUX
-SCSI_Out_DBx__0__BIE EQU CYREG_PRT6_BIE
-SCSI_Out_DBx__0__BIT_MASK EQU CYREG_PRT6_BIT_MASK
-SCSI_Out_DBx__0__BYP EQU CYREG_PRT6_BYP
-SCSI_Out_DBx__0__CTL EQU CYREG_PRT6_CTL
-SCSI_Out_DBx__0__DM0 EQU CYREG_PRT6_DM0
-SCSI_Out_DBx__0__DM1 EQU CYREG_PRT6_DM1
-SCSI_Out_DBx__0__DM2 EQU CYREG_PRT6_DM2
-SCSI_Out_DBx__0__DR EQU CYREG_PRT6_DR
-SCSI_Out_DBx__0__INP_DIS EQU CYREG_PRT6_INP_DIS
-SCSI_Out_DBx__0__INTTYPE EQU CYREG_PICU6_INTTYPE7
-SCSI_Out_DBx__0__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
-SCSI_Out_DBx__0__LCD_EN EQU CYREG_PRT6_LCD_EN
-SCSI_Out_DBx__0__MASK EQU 0x80
-SCSI_Out_DBx__0__PC EQU CYREG_PRT6_PC7
-SCSI_Out_DBx__0__PORT EQU 6
-SCSI_Out_DBx__0__PRT EQU CYREG_PRT6_PRT
-SCSI_Out_DBx__0__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
-SCSI_Out_DBx__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
-SCSI_Out_DBx__0__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
-SCSI_Out_DBx__0__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
-SCSI_Out_DBx__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
-SCSI_Out_DBx__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
-SCSI_Out_DBx__0__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
-SCSI_Out_DBx__0__PS EQU CYREG_PRT6_PS
-SCSI_Out_DBx__0__SHIFT EQU 7
-SCSI_Out_DBx__0__SLW EQU CYREG_PRT6_SLW
-SCSI_Out_DBx__1__AG EQU CYREG_PRT6_AG
-SCSI_Out_DBx__1__AMUX EQU CYREG_PRT6_AMUX
-SCSI_Out_DBx__1__BIE EQU CYREG_PRT6_BIE
-SCSI_Out_DBx__1__BIT_MASK EQU CYREG_PRT6_BIT_MASK
-SCSI_Out_DBx__1__BYP EQU CYREG_PRT6_BYP
-SCSI_Out_DBx__1__CTL EQU CYREG_PRT6_CTL
-SCSI_Out_DBx__1__DM0 EQU CYREG_PRT6_DM0
-SCSI_Out_DBx__1__DM1 EQU CYREG_PRT6_DM1
-SCSI_Out_DBx__1__DM2 EQU CYREG_PRT6_DM2
-SCSI_Out_DBx__1__DR EQU CYREG_PRT6_DR
-SCSI_Out_DBx__1__INP_DIS EQU CYREG_PRT6_INP_DIS
-SCSI_Out_DBx__1__INTTYPE EQU CYREG_PICU6_INTTYPE5
-SCSI_Out_DBx__1__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
-SCSI_Out_DBx__1__LCD_EN EQU CYREG_PRT6_LCD_EN
-SCSI_Out_DBx__1__MASK EQU 0x20
-SCSI_Out_DBx__1__PC EQU CYREG_PRT6_PC5
-SCSI_Out_DBx__1__PORT EQU 6
-SCSI_Out_DBx__1__PRT EQU CYREG_PRT6_PRT
-SCSI_Out_DBx__1__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
-SCSI_Out_DBx__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
-SCSI_Out_DBx__1__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
-SCSI_Out_DBx__1__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
-SCSI_Out_DBx__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
-SCSI_Out_DBx__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
-SCSI_Out_DBx__1__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
-SCSI_Out_DBx__1__PS EQU CYREG_PRT6_PS
-SCSI_Out_DBx__1__SHIFT EQU 5
-SCSI_Out_DBx__1__SLW EQU CYREG_PRT6_SLW
-SCSI_Out_DBx__2__AG EQU CYREG_PRT12_AG
-SCSI_Out_DBx__2__BIE EQU CYREG_PRT12_BIE
-SCSI_Out_DBx__2__BIT_MASK EQU CYREG_PRT12_BIT_MASK
-SCSI_Out_DBx__2__BYP EQU CYREG_PRT12_BYP
-SCSI_Out_DBx__2__DM0 EQU CYREG_PRT12_DM0
-SCSI_Out_DBx__2__DM1 EQU CYREG_PRT12_DM1
-SCSI_Out_DBx__2__DM2 EQU CYREG_PRT12_DM2
-SCSI_Out_DBx__2__DR EQU CYREG_PRT12_DR
-SCSI_Out_DBx__2__INP_DIS EQU CYREG_PRT12_INP_DIS
-SCSI_Out_DBx__2__INTTYPE EQU CYREG_PICU12_INTTYPE5
-SCSI_Out_DBx__2__MASK EQU 0x20
-SCSI_Out_DBx__2__PC EQU CYREG_PRT12_PC5
-SCSI_Out_DBx__2__PORT EQU 12
-SCSI_Out_DBx__2__PRT EQU CYREG_PRT12_PRT
-SCSI_Out_DBx__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN
-SCSI_Out_DBx__2__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0
-SCSI_Out_DBx__2__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1
-SCSI_Out_DBx__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0
-SCSI_Out_DBx__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1
-SCSI_Out_DBx__2__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT
-SCSI_Out_DBx__2__PS EQU CYREG_PRT12_PS
-SCSI_Out_DBx__2__SHIFT EQU 5
-SCSI_Out_DBx__2__SIO_CFG EQU CYREG_PRT12_SIO_CFG
-SCSI_Out_DBx__2__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF
-SCSI_Out_DBx__2__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN
-SCSI_Out_DBx__2__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ
-SCSI_Out_DBx__2__SLW EQU CYREG_PRT12_SLW
-SCSI_Out_DBx__3__AG EQU CYREG_PRT2_AG
-SCSI_Out_DBx__3__AMUX EQU CYREG_PRT2_AMUX
-SCSI_Out_DBx__3__BIE EQU CYREG_PRT2_BIE
-SCSI_Out_DBx__3__BIT_MASK EQU CYREG_PRT2_BIT_MASK
-SCSI_Out_DBx__3__BYP EQU CYREG_PRT2_BYP
-SCSI_Out_DBx__3__CTL EQU CYREG_PRT2_CTL
-SCSI_Out_DBx__3__DM0 EQU CYREG_PRT2_DM0
-SCSI_Out_DBx__3__DM1 EQU CYREG_PRT2_DM1
-SCSI_Out_DBx__3__DM2 EQU CYREG_PRT2_DM2
-SCSI_Out_DBx__3__DR EQU CYREG_PRT2_DR
-SCSI_Out_DBx__3__INP_DIS EQU CYREG_PRT2_INP_DIS
-SCSI_Out_DBx__3__INTTYPE EQU CYREG_PICU2_INTTYPE7
-SCSI_Out_DBx__3__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
-SCSI_Out_DBx__3__LCD_EN EQU CYREG_PRT2_LCD_EN
-SCSI_Out_DBx__3__MASK EQU 0x80
-SCSI_Out_DBx__3__PC EQU CYREG_PRT2_PC7
-SCSI_Out_DBx__3__PORT EQU 2
-SCSI_Out_DBx__3__PRT EQU CYREG_PRT2_PRT
-SCSI_Out_DBx__3__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
-SCSI_Out_DBx__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
-SCSI_Out_DBx__3__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
-SCSI_Out_DBx__3__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
-SCSI_Out_DBx__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
-SCSI_Out_DBx__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
-SCSI_Out_DBx__3__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
-SCSI_Out_DBx__3__PS EQU CYREG_PRT2_PS
-SCSI_Out_DBx__3__SHIFT EQU 7
-SCSI_Out_DBx__3__SLW EQU CYREG_PRT2_SLW
-SCSI_Out_DBx__4__AG EQU CYREG_PRT2_AG
-SCSI_Out_DBx__4__AMUX EQU CYREG_PRT2_AMUX
-SCSI_Out_DBx__4__BIE EQU CYREG_PRT2_BIE
-SCSI_Out_DBx__4__BIT_MASK EQU CYREG_PRT2_BIT_MASK
-SCSI_Out_DBx__4__BYP EQU CYREG_PRT2_BYP
-SCSI_Out_DBx__4__CTL EQU CYREG_PRT2_CTL
-SCSI_Out_DBx__4__DM0 EQU CYREG_PRT2_DM0
-SCSI_Out_DBx__4__DM1 EQU CYREG_PRT2_DM1
-SCSI_Out_DBx__4__DM2 EQU CYREG_PRT2_DM2
-SCSI_Out_DBx__4__DR EQU CYREG_PRT2_DR
-SCSI_Out_DBx__4__INP_DIS EQU CYREG_PRT2_INP_DIS
-SCSI_Out_DBx__4__INTTYPE EQU CYREG_PICU2_INTTYPE5
-SCSI_Out_DBx__4__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
-SCSI_Out_DBx__4__LCD_EN EQU CYREG_PRT2_LCD_EN
-SCSI_Out_DBx__4__MASK EQU 0x20
-SCSI_Out_DBx__4__PC EQU CYREG_PRT2_PC5
-SCSI_Out_DBx__4__PORT EQU 2
-SCSI_Out_DBx__4__PRT EQU CYREG_PRT2_PRT
-SCSI_Out_DBx__4__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
-SCSI_Out_DBx__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
-SCSI_Out_DBx__4__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
-SCSI_Out_DBx__4__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
-SCSI_Out_DBx__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
-SCSI_Out_DBx__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
-SCSI_Out_DBx__4__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
-SCSI_Out_DBx__4__PS EQU CYREG_PRT2_PS
-SCSI_Out_DBx__4__SHIFT EQU 5
-SCSI_Out_DBx__4__SLW EQU CYREG_PRT2_SLW
-SCSI_Out_DBx__5__AG EQU CYREG_PRT2_AG
-SCSI_Out_DBx__5__AMUX EQU CYREG_PRT2_AMUX
-SCSI_Out_DBx__5__BIE EQU CYREG_PRT2_BIE
-SCSI_Out_DBx__5__BIT_MASK EQU CYREG_PRT2_BIT_MASK
-SCSI_Out_DBx__5__BYP EQU CYREG_PRT2_BYP
-SCSI_Out_DBx__5__CTL EQU CYREG_PRT2_CTL
-SCSI_Out_DBx__5__DM0 EQU CYREG_PRT2_DM0
-SCSI_Out_DBx__5__DM1 EQU CYREG_PRT2_DM1
-SCSI_Out_DBx__5__DM2 EQU CYREG_PRT2_DM2
-SCSI_Out_DBx__5__DR EQU CYREG_PRT2_DR
-SCSI_Out_DBx__5__INP_DIS EQU CYREG_PRT2_INP_DIS
-SCSI_Out_DBx__5__INTTYPE EQU CYREG_PICU2_INTTYPE3
-SCSI_Out_DBx__5__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
-SCSI_Out_DBx__5__LCD_EN EQU CYREG_PRT2_LCD_EN
-SCSI_Out_DBx__5__MASK EQU 0x08
-SCSI_Out_DBx__5__PC EQU CYREG_PRT2_PC3
-SCSI_Out_DBx__5__PORT EQU 2
-SCSI_Out_DBx__5__PRT EQU CYREG_PRT2_PRT
-SCSI_Out_DBx__5__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
-SCSI_Out_DBx__5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
-SCSI_Out_DBx__5__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
-SCSI_Out_DBx__5__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
-SCSI_Out_DBx__5__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
-SCSI_Out_DBx__5__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
-SCSI_Out_DBx__5__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
-SCSI_Out_DBx__5__PS EQU CYREG_PRT2_PS
-SCSI_Out_DBx__5__SHIFT EQU 3
-SCSI_Out_DBx__5__SLW EQU CYREG_PRT2_SLW
-SCSI_Out_DBx__6__AG EQU CYREG_PRT2_AG
-SCSI_Out_DBx__6__AMUX EQU CYREG_PRT2_AMUX
-SCSI_Out_DBx__6__BIE EQU CYREG_PRT2_BIE
-SCSI_Out_DBx__6__BIT_MASK EQU CYREG_PRT2_BIT_MASK
-SCSI_Out_DBx__6__BYP EQU CYREG_PRT2_BYP
-SCSI_Out_DBx__6__CTL EQU CYREG_PRT2_CTL
-SCSI_Out_DBx__6__DM0 EQU CYREG_PRT2_DM0
-SCSI_Out_DBx__6__DM1 EQU CYREG_PRT2_DM1
-SCSI_Out_DBx__6__DM2 EQU CYREG_PRT2_DM2
-SCSI_Out_DBx__6__DR EQU CYREG_PRT2_DR
-SCSI_Out_DBx__6__INP_DIS EQU CYREG_PRT2_INP_DIS
-SCSI_Out_DBx__6__INTTYPE EQU CYREG_PICU2_INTTYPE1
-SCSI_Out_DBx__6__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
-SCSI_Out_DBx__6__LCD_EN EQU CYREG_PRT2_LCD_EN
-SCSI_Out_DBx__6__MASK EQU 0x02
-SCSI_Out_DBx__6__PC EQU CYREG_PRT2_PC1
-SCSI_Out_DBx__6__PORT EQU 2
-SCSI_Out_DBx__6__PRT EQU CYREG_PRT2_PRT
-SCSI_Out_DBx__6__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
-SCSI_Out_DBx__6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
-SCSI_Out_DBx__6__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
-SCSI_Out_DBx__6__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
-SCSI_Out_DBx__6__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
-SCSI_Out_DBx__6__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
-SCSI_Out_DBx__6__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
-SCSI_Out_DBx__6__PS EQU CYREG_PRT2_PS
-SCSI_Out_DBx__6__SHIFT EQU 1
-SCSI_Out_DBx__6__SLW EQU CYREG_PRT2_SLW
-SCSI_Out_DBx__7__AG EQU CYREG_PRT15_AG
-SCSI_Out_DBx__7__AMUX EQU CYREG_PRT15_AMUX
-SCSI_Out_DBx__7__BIE EQU CYREG_PRT15_BIE
-SCSI_Out_DBx__7__BIT_MASK EQU CYREG_PRT15_BIT_MASK
-SCSI_Out_DBx__7__BYP EQU CYREG_PRT15_BYP
-SCSI_Out_DBx__7__CTL EQU CYREG_PRT15_CTL
-SCSI_Out_DBx__7__DM0 EQU CYREG_PRT15_DM0
-SCSI_Out_DBx__7__DM1 EQU CYREG_PRT15_DM1
-SCSI_Out_DBx__7__DM2 EQU CYREG_PRT15_DM2
-SCSI_Out_DBx__7__DR EQU CYREG_PRT15_DR
-SCSI_Out_DBx__7__INP_DIS EQU CYREG_PRT15_INP_DIS
-SCSI_Out_DBx__7__INTTYPE EQU CYREG_PICU15_INTTYPE5
-SCSI_Out_DBx__7__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG
-SCSI_Out_DBx__7__LCD_EN EQU CYREG_PRT15_LCD_EN
-SCSI_Out_DBx__7__MASK EQU 0x20
-SCSI_Out_DBx__7__PC EQU CYREG_IO_PC_PRT15_PC5
-SCSI_Out_DBx__7__PORT EQU 15
-SCSI_Out_DBx__7__PRT EQU CYREG_PRT15_PRT
-SCSI_Out_DBx__7__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL
-SCSI_Out_DBx__7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN
-SCSI_Out_DBx__7__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0
-SCSI_Out_DBx__7__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1
-SCSI_Out_DBx__7__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0
-SCSI_Out_DBx__7__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1
-SCSI_Out_DBx__7__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT
-SCSI_Out_DBx__7__PS EQU CYREG_PRT15_PS
-SCSI_Out_DBx__7__SHIFT EQU 5
-SCSI_Out_DBx__7__SLW EQU CYREG_PRT15_SLW
-SCSI_Out_DBx__DB0__AG EQU CYREG_PRT6_AG
-SCSI_Out_DBx__DB0__AMUX EQU CYREG_PRT6_AMUX
-SCSI_Out_DBx__DB0__BIE EQU CYREG_PRT6_BIE
-SCSI_Out_DBx__DB0__BIT_MASK EQU CYREG_PRT6_BIT_MASK
-SCSI_Out_DBx__DB0__BYP EQU CYREG_PRT6_BYP
-SCSI_Out_DBx__DB0__CTL EQU CYREG_PRT6_CTL
-SCSI_Out_DBx__DB0__DM0 EQU CYREG_PRT6_DM0
-SCSI_Out_DBx__DB0__DM1 EQU CYREG_PRT6_DM1
-SCSI_Out_DBx__DB0__DM2 EQU CYREG_PRT6_DM2
-SCSI_Out_DBx__DB0__DR EQU CYREG_PRT6_DR
-SCSI_Out_DBx__DB0__INP_DIS EQU CYREG_PRT6_INP_DIS
-SCSI_Out_DBx__DB0__INTTYPE EQU CYREG_PICU6_INTTYPE7
-SCSI_Out_DBx__DB0__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
-SCSI_Out_DBx__DB0__LCD_EN EQU CYREG_PRT6_LCD_EN
-SCSI_Out_DBx__DB0__MASK EQU 0x80
-SCSI_Out_DBx__DB0__PC EQU CYREG_PRT6_PC7
-SCSI_Out_DBx__DB0__PORT EQU 6
-SCSI_Out_DBx__DB0__PRT EQU CYREG_PRT6_PRT
-SCSI_Out_DBx__DB0__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
-SCSI_Out_DBx__DB0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
-SCSI_Out_DBx__DB0__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
-SCSI_Out_DBx__DB0__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
-SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
-SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
-SCSI_Out_DBx__DB0__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
-SCSI_Out_DBx__DB0__PS EQU CYREG_PRT6_PS
-SCSI_Out_DBx__DB0__SHIFT EQU 7
-SCSI_Out_DBx__DB0__SLW EQU CYREG_PRT6_SLW
-SCSI_Out_DBx__DB1__AG EQU CYREG_PRT6_AG
-SCSI_Out_DBx__DB1__AMUX EQU CYREG_PRT6_AMUX
-SCSI_Out_DBx__DB1__BIE EQU CYREG_PRT6_BIE
-SCSI_Out_DBx__DB1__BIT_MASK EQU CYREG_PRT6_BIT_MASK
-SCSI_Out_DBx__DB1__BYP EQU CYREG_PRT6_BYP
-SCSI_Out_DBx__DB1__CTL EQU CYREG_PRT6_CTL
-SCSI_Out_DBx__DB1__DM0 EQU CYREG_PRT6_DM0
-SCSI_Out_DBx__DB1__DM1 EQU CYREG_PRT6_DM1
-SCSI_Out_DBx__DB1__DM2 EQU CYREG_PRT6_DM2
-SCSI_Out_DBx__DB1__DR EQU CYREG_PRT6_DR
-SCSI_Out_DBx__DB1__INP_DIS EQU CYREG_PRT6_INP_DIS
-SCSI_Out_DBx__DB1__INTTYPE EQU CYREG_PICU6_INTTYPE5
-SCSI_Out_DBx__DB1__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
-SCSI_Out_DBx__DB1__LCD_EN EQU CYREG_PRT6_LCD_EN
-SCSI_Out_DBx__DB1__MASK EQU 0x20
-SCSI_Out_DBx__DB1__PC EQU CYREG_PRT6_PC5
-SCSI_Out_DBx__DB1__PORT EQU 6
-SCSI_Out_DBx__DB1__PRT EQU CYREG_PRT6_PRT
-SCSI_Out_DBx__DB1__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
-SCSI_Out_DBx__DB1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
-SCSI_Out_DBx__DB1__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
-SCSI_Out_DBx__DB1__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
-SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
-SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
-SCSI_Out_DBx__DB1__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
-SCSI_Out_DBx__DB1__PS EQU CYREG_PRT6_PS
-SCSI_Out_DBx__DB1__SHIFT EQU 5
-SCSI_Out_DBx__DB1__SLW EQU CYREG_PRT6_SLW
-SCSI_Out_DBx__DB2__AG EQU CYREG_PRT12_AG
-SCSI_Out_DBx__DB2__BIE EQU CYREG_PRT12_BIE
-SCSI_Out_DBx__DB2__BIT_MASK EQU CYREG_PRT12_BIT_MASK
-SCSI_Out_DBx__DB2__BYP EQU CYREG_PRT12_BYP
-SCSI_Out_DBx__DB2__DM0 EQU CYREG_PRT12_DM0
-SCSI_Out_DBx__DB2__DM1 EQU CYREG_PRT12_DM1
-SCSI_Out_DBx__DB2__DM2 EQU CYREG_PRT12_DM2
-SCSI_Out_DBx__DB2__DR EQU CYREG_PRT12_DR
-SCSI_Out_DBx__DB2__INP_DIS EQU CYREG_PRT12_INP_DIS
-SCSI_Out_DBx__DB2__INTTYPE EQU CYREG_PICU12_INTTYPE5
-SCSI_Out_DBx__DB2__MASK EQU 0x20
-SCSI_Out_DBx__DB2__PC EQU CYREG_PRT12_PC5
-SCSI_Out_DBx__DB2__PORT EQU 12
-SCSI_Out_DBx__DB2__PRT EQU CYREG_PRT12_PRT
-SCSI_Out_DBx__DB2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN
-SCSI_Out_DBx__DB2__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0
-SCSI_Out_DBx__DB2__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1
-SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0
-SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1
-SCSI_Out_DBx__DB2__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT
-SCSI_Out_DBx__DB2__PS EQU CYREG_PRT12_PS
-SCSI_Out_DBx__DB2__SHIFT EQU 5
-SCSI_Out_DBx__DB2__SIO_CFG EQU CYREG_PRT12_SIO_CFG
-SCSI_Out_DBx__DB2__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF
-SCSI_Out_DBx__DB2__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN
-SCSI_Out_DBx__DB2__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ
-SCSI_Out_DBx__DB2__SLW EQU CYREG_PRT12_SLW
-SCSI_Out_DBx__DB3__AG EQU CYREG_PRT2_AG
-SCSI_Out_DBx__DB3__AMUX EQU CYREG_PRT2_AMUX
-SCSI_Out_DBx__DB3__BIE EQU CYREG_PRT2_BIE
-SCSI_Out_DBx__DB3__BIT_MASK EQU CYREG_PRT2_BIT_MASK
-SCSI_Out_DBx__DB3__BYP EQU CYREG_PRT2_BYP
-SCSI_Out_DBx__DB3__CTL EQU CYREG_PRT2_CTL
-SCSI_Out_DBx__DB3__DM0 EQU CYREG_PRT2_DM0
-SCSI_Out_DBx__DB3__DM1 EQU CYREG_PRT2_DM1
-SCSI_Out_DBx__DB3__DM2 EQU CYREG_PRT2_DM2
-SCSI_Out_DBx__DB3__DR EQU CYREG_PRT2_DR
-SCSI_Out_DBx__DB3__INP_DIS EQU CYREG_PRT2_INP_DIS
-SCSI_Out_DBx__DB3__INTTYPE EQU CYREG_PICU2_INTTYPE7
-SCSI_Out_DBx__DB3__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
-SCSI_Out_DBx__DB3__LCD_EN EQU CYREG_PRT2_LCD_EN
-SCSI_Out_DBx__DB3__MASK EQU 0x80
-SCSI_Out_DBx__DB3__PC EQU CYREG_PRT2_PC7
-SCSI_Out_DBx__DB3__PORT EQU 2
-SCSI_Out_DBx__DB3__PRT EQU CYREG_PRT2_PRT
-SCSI_Out_DBx__DB3__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
-SCSI_Out_DBx__DB3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
-SCSI_Out_DBx__DB3__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
-SCSI_Out_DBx__DB3__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
-SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
-SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
-SCSI_Out_DBx__DB3__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
-SCSI_Out_DBx__DB3__PS EQU CYREG_PRT2_PS
-SCSI_Out_DBx__DB3__SHIFT EQU 7
-SCSI_Out_DBx__DB3__SLW EQU CYREG_PRT2_SLW
-SCSI_Out_DBx__DB4__AG EQU CYREG_PRT2_AG
-SCSI_Out_DBx__DB4__AMUX EQU CYREG_PRT2_AMUX
-SCSI_Out_DBx__DB4__BIE EQU CYREG_PRT2_BIE
-SCSI_Out_DBx__DB4__BIT_MASK EQU CYREG_PRT2_BIT_MASK
-SCSI_Out_DBx__DB4__BYP EQU CYREG_PRT2_BYP
-SCSI_Out_DBx__DB4__CTL EQU CYREG_PRT2_CTL
-SCSI_Out_DBx__DB4__DM0 EQU CYREG_PRT2_DM0
-SCSI_Out_DBx__DB4__DM1 EQU CYREG_PRT2_DM1
-SCSI_Out_DBx__DB4__DM2 EQU CYREG_PRT2_DM2
-SCSI_Out_DBx__DB4__DR EQU CYREG_PRT2_DR
-SCSI_Out_DBx__DB4__INP_DIS EQU CYREG_PRT2_INP_DIS
-SCSI_Out_DBx__DB4__INTTYPE EQU CYREG_PICU2_INTTYPE5
-SCSI_Out_DBx__DB4__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
-SCSI_Out_DBx__DB4__LCD_EN EQU CYREG_PRT2_LCD_EN
-SCSI_Out_DBx__DB4__MASK EQU 0x20
-SCSI_Out_DBx__DB4__PC EQU CYREG_PRT2_PC5
-SCSI_Out_DBx__DB4__PORT EQU 2
-SCSI_Out_DBx__DB4__PRT EQU CYREG_PRT2_PRT
-SCSI_Out_DBx__DB4__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
-SCSI_Out_DBx__DB4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
-SCSI_Out_DBx__DB4__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
-SCSI_Out_DBx__DB4__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
-SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
-SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
-SCSI_Out_DBx__DB4__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
-SCSI_Out_DBx__DB4__PS EQU CYREG_PRT2_PS
-SCSI_Out_DBx__DB4__SHIFT EQU 5
-SCSI_Out_DBx__DB4__SLW EQU CYREG_PRT2_SLW
-SCSI_Out_DBx__DB5__AG EQU CYREG_PRT2_AG
-SCSI_Out_DBx__DB5__AMUX EQU CYREG_PRT2_AMUX
-SCSI_Out_DBx__DB5__BIE EQU CYREG_PRT2_BIE
-SCSI_Out_DBx__DB5__BIT_MASK EQU CYREG_PRT2_BIT_MASK
-SCSI_Out_DBx__DB5__BYP EQU CYREG_PRT2_BYP
-SCSI_Out_DBx__DB5__CTL EQU CYREG_PRT2_CTL
-SCSI_Out_DBx__DB5__DM0 EQU CYREG_PRT2_DM0
-SCSI_Out_DBx__DB5__DM1 EQU CYREG_PRT2_DM1
-SCSI_Out_DBx__DB5__DM2 EQU CYREG_PRT2_DM2
-SCSI_Out_DBx__DB5__DR EQU CYREG_PRT2_DR
-SCSI_Out_DBx__DB5__INP_DIS EQU CYREG_PRT2_INP_DIS
-SCSI_Out_DBx__DB5__INTTYPE EQU CYREG_PICU2_INTTYPE3
-SCSI_Out_DBx__DB5__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
-SCSI_Out_DBx__DB5__LCD_EN EQU CYREG_PRT2_LCD_EN
-SCSI_Out_DBx__DB5__MASK EQU 0x08
-SCSI_Out_DBx__DB5__PC EQU CYREG_PRT2_PC3
-SCSI_Out_DBx__DB5__PORT EQU 2
-SCSI_Out_DBx__DB5__PRT EQU CYREG_PRT2_PRT
-SCSI_Out_DBx__DB5__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
-SCSI_Out_DBx__DB5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
-SCSI_Out_DBx__DB5__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
-SCSI_Out_DBx__DB5__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
-SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
-SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
-SCSI_Out_DBx__DB5__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
-SCSI_Out_DBx__DB5__PS EQU CYREG_PRT2_PS
-SCSI_Out_DBx__DB5__SHIFT EQU 3
-SCSI_Out_DBx__DB5__SLW EQU CYREG_PRT2_SLW
-SCSI_Out_DBx__DB6__AG EQU CYREG_PRT2_AG
-SCSI_Out_DBx__DB6__AMUX EQU CYREG_PRT2_AMUX
-SCSI_Out_DBx__DB6__BIE EQU CYREG_PRT2_BIE
-SCSI_Out_DBx__DB6__BIT_MASK EQU CYREG_PRT2_BIT_MASK
-SCSI_Out_DBx__DB6__BYP EQU CYREG_PRT2_BYP
-SCSI_Out_DBx__DB6__CTL EQU CYREG_PRT2_CTL
-SCSI_Out_DBx__DB6__DM0 EQU CYREG_PRT2_DM0
-SCSI_Out_DBx__DB6__DM1 EQU CYREG_PRT2_DM1
-SCSI_Out_DBx__DB6__DM2 EQU CYREG_PRT2_DM2
-SCSI_Out_DBx__DB6__DR EQU CYREG_PRT2_DR
-SCSI_Out_DBx__DB6__INP_DIS EQU CYREG_PRT2_INP_DIS
-SCSI_Out_DBx__DB6__INTTYPE EQU CYREG_PICU2_INTTYPE1
-SCSI_Out_DBx__DB6__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
-SCSI_Out_DBx__DB6__LCD_EN EQU CYREG_PRT2_LCD_EN
-SCSI_Out_DBx__DB6__MASK EQU 0x02
-SCSI_Out_DBx__DB6__PC EQU CYREG_PRT2_PC1
-SCSI_Out_DBx__DB6__PORT EQU 2
-SCSI_Out_DBx__DB6__PRT EQU CYREG_PRT2_PRT
-SCSI_Out_DBx__DB6__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
-SCSI_Out_DBx__DB6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
-SCSI_Out_DBx__DB6__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
-SCSI_Out_DBx__DB6__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
-SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
-SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
-SCSI_Out_DBx__DB6__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
-SCSI_Out_DBx__DB6__PS EQU CYREG_PRT2_PS
-SCSI_Out_DBx__DB6__SHIFT EQU 1
-SCSI_Out_DBx__DB6__SLW EQU CYREG_PRT2_SLW
-SCSI_Out_DBx__DB7__AG EQU CYREG_PRT15_AG
-SCSI_Out_DBx__DB7__AMUX EQU CYREG_PRT15_AMUX
-SCSI_Out_DBx__DB7__BIE EQU CYREG_PRT15_BIE
-SCSI_Out_DBx__DB7__BIT_MASK EQU CYREG_PRT15_BIT_MASK
-SCSI_Out_DBx__DB7__BYP EQU CYREG_PRT15_BYP
-SCSI_Out_DBx__DB7__CTL EQU CYREG_PRT15_CTL
-SCSI_Out_DBx__DB7__DM0 EQU CYREG_PRT15_DM0
-SCSI_Out_DBx__DB7__DM1 EQU CYREG_PRT15_DM1
-SCSI_Out_DBx__DB7__DM2 EQU CYREG_PRT15_DM2
-SCSI_Out_DBx__DB7__DR EQU CYREG_PRT15_DR
-SCSI_Out_DBx__DB7__INP_DIS EQU CYREG_PRT15_INP_DIS
-SCSI_Out_DBx__DB7__INTTYPE EQU CYREG_PICU15_INTTYPE5
-SCSI_Out_DBx__DB7__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG
-SCSI_Out_DBx__DB7__LCD_EN EQU CYREG_PRT15_LCD_EN
-SCSI_Out_DBx__DB7__MASK EQU 0x20
-SCSI_Out_DBx__DB7__PC EQU CYREG_IO_PC_PRT15_PC5
-SCSI_Out_DBx__DB7__PORT EQU 15
-SCSI_Out_DBx__DB7__PRT EQU CYREG_PRT15_PRT
-SCSI_Out_DBx__DB7__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL
-SCSI_Out_DBx__DB7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN
-SCSI_Out_DBx__DB7__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0
-SCSI_Out_DBx__DB7__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1
-SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0
-SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1
-SCSI_Out_DBx__DB7__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT
-SCSI_Out_DBx__DB7__PS EQU CYREG_PRT15_PS
-SCSI_Out_DBx__DB7__SHIFT EQU 5
-SCSI_Out_DBx__DB7__SLW EQU CYREG_PRT15_SLW
-
-; SD_RX_DMA
-SD_RX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0
-SD_RX_DMA__DRQ_NUMBER EQU 2
-SD_RX_DMA__NUMBEROF_TDS EQU 0
-SD_RX_DMA__PRIORITY EQU 0
-SD_RX_DMA__TERMIN_EN EQU 0
-SD_RX_DMA__TERMIN_SEL EQU 0
-SD_RX_DMA__TERMOUT0_EN EQU 1
-SD_RX_DMA__TERMOUT0_SEL EQU 2
-SD_RX_DMA__TERMOUT1_EN EQU 0
-SD_RX_DMA__TERMOUT1_SEL EQU 0
-
-; SD_RX_DMA_COMPLETE
-SD_RX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
-SD_RX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-SD_RX_DMA_COMPLETE__INTC_MASK EQU 0x20
-SD_RX_DMA_COMPLETE__INTC_NUMBER EQU 5
-SD_RX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7
-SD_RX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_5
-SD_RX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
-SD_RX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
-
-; SD_TX_DMA
-SD_TX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0
-SD_TX_DMA__DRQ_NUMBER EQU 3
-SD_TX_DMA__NUMBEROF_TDS EQU 0
-SD_TX_DMA__PRIORITY EQU 1
-SD_TX_DMA__TERMIN_EN EQU 0
-SD_TX_DMA__TERMIN_SEL EQU 0
-SD_TX_DMA__TERMOUT0_EN EQU 1
-SD_TX_DMA__TERMOUT0_SEL EQU 3
-SD_TX_DMA__TERMOUT1_EN EQU 0
-SD_TX_DMA__TERMOUT1_SEL EQU 0
-
-; SD_TX_DMA_COMPLETE
-SD_TX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
-SD_TX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-SD_TX_DMA_COMPLETE__INTC_MASK EQU 0x40
-SD_TX_DMA_COMPLETE__INTC_NUMBER EQU 6
-SD_TX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7
-SD_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_6
-SD_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
-SD_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
+; SCSI_In
+SCSI_In__0__INTTYPE EQU CYREG_PICU6_INTTYPE1
+SCSI_In__0__MASK EQU 0x02
+SCSI_In__0__PC EQU CYREG_PRT6_PC1
+SCSI_In__0__PORT EQU 6
+SCSI_In__0__SHIFT EQU 1
+SCSI_In__AG EQU CYREG_PRT6_AG
+SCSI_In__AMUX EQU CYREG_PRT6_AMUX
+SCSI_In__BIE EQU CYREG_PRT6_BIE
+SCSI_In__BIT_MASK EQU CYREG_PRT6_BIT_MASK
+SCSI_In__BYP EQU CYREG_PRT6_BYP
+SCSI_In__CTL EQU CYREG_PRT6_CTL
+SCSI_In__DBP__INTTYPE EQU CYREG_PICU6_INTTYPE1
+SCSI_In__DBP__MASK EQU 0x02
+SCSI_In__DBP__PC EQU CYREG_PRT6_PC1
+SCSI_In__DBP__PORT EQU 6
+SCSI_In__DBP__SHIFT EQU 1
+SCSI_In__DM0 EQU CYREG_PRT6_DM0
+SCSI_In__DM1 EQU CYREG_PRT6_DM1
+SCSI_In__DM2 EQU CYREG_PRT6_DM2
+SCSI_In__DR EQU CYREG_PRT6_DR
+SCSI_In__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_In__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU6_BASE
+SCSI_In__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
+SCSI_In__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_In__MASK EQU 0x02
+SCSI_In__PORT EQU 6
+SCSI_In__PRT EQU CYREG_PRT6_PRT
+SCSI_In__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
+SCSI_In__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
+SCSI_In__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
+SCSI_In__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
+SCSI_In__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
+SCSI_In__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
+SCSI_In__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
+SCSI_In__PS EQU CYREG_PRT6_PS
+SCSI_In__SHIFT EQU 1
+SCSI_In__SLW EQU CYREG_PRT6_SLW
+SCSI_In_DBx__0__AG EQU CYREG_PRT6_AG
+SCSI_In_DBx__0__AMUX EQU CYREG_PRT6_AMUX
+SCSI_In_DBx__0__BIE EQU CYREG_PRT6_BIE
+SCSI_In_DBx__0__BIT_MASK EQU CYREG_PRT6_BIT_MASK
+SCSI_In_DBx__0__BYP EQU CYREG_PRT6_BYP
+SCSI_In_DBx__0__CTL EQU CYREG_PRT6_CTL
+SCSI_In_DBx__0__DM0 EQU CYREG_PRT6_DM0
+SCSI_In_DBx__0__DM1 EQU CYREG_PRT6_DM1
+SCSI_In_DBx__0__DM2 EQU CYREG_PRT6_DM2
+SCSI_In_DBx__0__DR EQU CYREG_PRT6_DR
+SCSI_In_DBx__0__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_In_DBx__0__INTTYPE EQU CYREG_PICU6_INTTYPE6
+SCSI_In_DBx__0__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
+SCSI_In_DBx__0__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_In_DBx__0__MASK EQU 0x40
+SCSI_In_DBx__0__PC EQU CYREG_PRT6_PC6
+SCSI_In_DBx__0__PORT EQU 6
+SCSI_In_DBx__0__PRT EQU CYREG_PRT6_PRT
+SCSI_In_DBx__0__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
+SCSI_In_DBx__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
+SCSI_In_DBx__0__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
+SCSI_In_DBx__0__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
+SCSI_In_DBx__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
+SCSI_In_DBx__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
+SCSI_In_DBx__0__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
+SCSI_In_DBx__0__PS EQU CYREG_PRT6_PS
+SCSI_In_DBx__0__SHIFT EQU 6
+SCSI_In_DBx__0__SLW EQU CYREG_PRT6_SLW
+SCSI_In_DBx__1__AG EQU CYREG_PRT6_AG
+SCSI_In_DBx__1__AMUX EQU CYREG_PRT6_AMUX
+SCSI_In_DBx__1__BIE EQU CYREG_PRT6_BIE
+SCSI_In_DBx__1__BIT_MASK EQU CYREG_PRT6_BIT_MASK
+SCSI_In_DBx__1__BYP EQU CYREG_PRT6_BYP
+SCSI_In_DBx__1__CTL EQU CYREG_PRT6_CTL
+SCSI_In_DBx__1__DM0 EQU CYREG_PRT6_DM0
+SCSI_In_DBx__1__DM1 EQU CYREG_PRT6_DM1
+SCSI_In_DBx__1__DM2 EQU CYREG_PRT6_DM2
+SCSI_In_DBx__1__DR EQU CYREG_PRT6_DR
+SCSI_In_DBx__1__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_In_DBx__1__INTTYPE EQU CYREG_PICU6_INTTYPE4
+SCSI_In_DBx__1__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
+SCSI_In_DBx__1__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_In_DBx__1__MASK EQU 0x10
+SCSI_In_DBx__1__PC EQU CYREG_PRT6_PC4
+SCSI_In_DBx__1__PORT EQU 6
+SCSI_In_DBx__1__PRT EQU CYREG_PRT6_PRT
+SCSI_In_DBx__1__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
+SCSI_In_DBx__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
+SCSI_In_DBx__1__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
+SCSI_In_DBx__1__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
+SCSI_In_DBx__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
+SCSI_In_DBx__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
+SCSI_In_DBx__1__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
+SCSI_In_DBx__1__PS EQU CYREG_PRT6_PS
+SCSI_In_DBx__1__SHIFT EQU 4
+SCSI_In_DBx__1__SLW EQU CYREG_PRT6_SLW
+SCSI_In_DBx__2__AG EQU CYREG_PRT12_AG
+SCSI_In_DBx__2__BIE EQU CYREG_PRT12_BIE
+SCSI_In_DBx__2__BIT_MASK EQU CYREG_PRT12_BIT_MASK
+SCSI_In_DBx__2__BYP EQU CYREG_PRT12_BYP
+SCSI_In_DBx__2__DM0 EQU CYREG_PRT12_DM0
+SCSI_In_DBx__2__DM1 EQU CYREG_PRT12_DM1
+SCSI_In_DBx__2__DM2 EQU CYREG_PRT12_DM2
+SCSI_In_DBx__2__DR EQU CYREG_PRT12_DR
+SCSI_In_DBx__2__INP_DIS EQU CYREG_PRT12_INP_DIS
+SCSI_In_DBx__2__INTTYPE EQU CYREG_PICU12_INTTYPE4
+SCSI_In_DBx__2__MASK EQU 0x10
+SCSI_In_DBx__2__PC EQU CYREG_PRT12_PC4
+SCSI_In_DBx__2__PORT EQU 12
+SCSI_In_DBx__2__PRT EQU CYREG_PRT12_PRT
+SCSI_In_DBx__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN
+SCSI_In_DBx__2__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0
+SCSI_In_DBx__2__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1
+SCSI_In_DBx__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0
+SCSI_In_DBx__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1
+SCSI_In_DBx__2__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT
+SCSI_In_DBx__2__PS EQU CYREG_PRT12_PS
+SCSI_In_DBx__2__SHIFT EQU 4
+SCSI_In_DBx__2__SIO_CFG EQU CYREG_PRT12_SIO_CFG
+SCSI_In_DBx__2__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF
+SCSI_In_DBx__2__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN
+SCSI_In_DBx__2__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ
+SCSI_In_DBx__2__SLW EQU CYREG_PRT12_SLW
+SCSI_In_DBx__3__AG EQU CYREG_PRT2_AG
+SCSI_In_DBx__3__AMUX EQU CYREG_PRT2_AMUX
+SCSI_In_DBx__3__BIE EQU CYREG_PRT2_BIE
+SCSI_In_DBx__3__BIT_MASK EQU CYREG_PRT2_BIT_MASK
+SCSI_In_DBx__3__BYP EQU CYREG_PRT2_BYP
+SCSI_In_DBx__3__CTL EQU CYREG_PRT2_CTL
+SCSI_In_DBx__3__DM0 EQU CYREG_PRT2_DM0
+SCSI_In_DBx__3__DM1 EQU CYREG_PRT2_DM1
+SCSI_In_DBx__3__DM2 EQU CYREG_PRT2_DM2
+SCSI_In_DBx__3__DR EQU CYREG_PRT2_DR
+SCSI_In_DBx__3__INP_DIS EQU CYREG_PRT2_INP_DIS
+SCSI_In_DBx__3__INTTYPE EQU CYREG_PICU2_INTTYPE6
+SCSI_In_DBx__3__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
+SCSI_In_DBx__3__LCD_EN EQU CYREG_PRT2_LCD_EN
+SCSI_In_DBx__3__MASK EQU 0x40
+SCSI_In_DBx__3__PC EQU CYREG_PRT2_PC6
+SCSI_In_DBx__3__PORT EQU 2
+SCSI_In_DBx__3__PRT EQU CYREG_PRT2_PRT
+SCSI_In_DBx__3__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
+SCSI_In_DBx__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
+SCSI_In_DBx__3__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
+SCSI_In_DBx__3__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
+SCSI_In_DBx__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
+SCSI_In_DBx__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
+SCSI_In_DBx__3__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
+SCSI_In_DBx__3__PS EQU CYREG_PRT2_PS
+SCSI_In_DBx__3__SHIFT EQU 6
+SCSI_In_DBx__3__SLW EQU CYREG_PRT2_SLW
+SCSI_In_DBx__4__AG EQU CYREG_PRT2_AG
+SCSI_In_DBx__4__AMUX EQU CYREG_PRT2_AMUX
+SCSI_In_DBx__4__BIE EQU CYREG_PRT2_BIE
+SCSI_In_DBx__4__BIT_MASK EQU CYREG_PRT2_BIT_MASK
+SCSI_In_DBx__4__BYP EQU CYREG_PRT2_BYP
+SCSI_In_DBx__4__CTL EQU CYREG_PRT2_CTL
+SCSI_In_DBx__4__DM0 EQU CYREG_PRT2_DM0
+SCSI_In_DBx__4__DM1 EQU CYREG_PRT2_DM1
+SCSI_In_DBx__4__DM2 EQU CYREG_PRT2_DM2
+SCSI_In_DBx__4__DR EQU CYREG_PRT2_DR
+SCSI_In_DBx__4__INP_DIS EQU CYREG_PRT2_INP_DIS
+SCSI_In_DBx__4__INTTYPE EQU CYREG_PICU2_INTTYPE4
+SCSI_In_DBx__4__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
+SCSI_In_DBx__4__LCD_EN EQU CYREG_PRT2_LCD_EN
+SCSI_In_DBx__4__MASK EQU 0x10
+SCSI_In_DBx__4__PC EQU CYREG_PRT2_PC4
+SCSI_In_DBx__4__PORT EQU 2
+SCSI_In_DBx__4__PRT EQU CYREG_PRT2_PRT
+SCSI_In_DBx__4__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
+SCSI_In_DBx__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
+SCSI_In_DBx__4__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
+SCSI_In_DBx__4__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
+SCSI_In_DBx__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
+SCSI_In_DBx__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
+SCSI_In_DBx__4__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
+SCSI_In_DBx__4__PS EQU CYREG_PRT2_PS
+SCSI_In_DBx__4__SHIFT EQU 4
+SCSI_In_DBx__4__SLW EQU CYREG_PRT2_SLW
+SCSI_In_DBx__5__AG EQU CYREG_PRT2_AG
+SCSI_In_DBx__5__AMUX EQU CYREG_PRT2_AMUX
+SCSI_In_DBx__5__BIE EQU CYREG_PRT2_BIE
+SCSI_In_DBx__5__BIT_MASK EQU CYREG_PRT2_BIT_MASK
+SCSI_In_DBx__5__BYP EQU CYREG_PRT2_BYP
+SCSI_In_DBx__5__CTL EQU CYREG_PRT2_CTL
+SCSI_In_DBx__5__DM0 EQU CYREG_PRT2_DM0
+SCSI_In_DBx__5__DM1 EQU CYREG_PRT2_DM1
+SCSI_In_DBx__5__DM2 EQU CYREG_PRT2_DM2
+SCSI_In_DBx__5__DR EQU CYREG_PRT2_DR
+SCSI_In_DBx__5__INP_DIS EQU CYREG_PRT2_INP_DIS
+SCSI_In_DBx__5__INTTYPE EQU CYREG_PICU2_INTTYPE2
+SCSI_In_DBx__5__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
+SCSI_In_DBx__5__LCD_EN EQU CYREG_PRT2_LCD_EN
+SCSI_In_DBx__5__MASK EQU 0x04
+SCSI_In_DBx__5__PC EQU CYREG_PRT2_PC2
+SCSI_In_DBx__5__PORT EQU 2
+SCSI_In_DBx__5__PRT EQU CYREG_PRT2_PRT
+SCSI_In_DBx__5__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
+SCSI_In_DBx__5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
+SCSI_In_DBx__5__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
+SCSI_In_DBx__5__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
+SCSI_In_DBx__5__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
+SCSI_In_DBx__5__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
+SCSI_In_DBx__5__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
+SCSI_In_DBx__5__PS EQU CYREG_PRT2_PS
+SCSI_In_DBx__5__SHIFT EQU 2
+SCSI_In_DBx__5__SLW EQU CYREG_PRT2_SLW
+SCSI_In_DBx__6__AG EQU CYREG_PRT2_AG
+SCSI_In_DBx__6__AMUX EQU CYREG_PRT2_AMUX
+SCSI_In_DBx__6__BIE EQU CYREG_PRT2_BIE
+SCSI_In_DBx__6__BIT_MASK EQU CYREG_PRT2_BIT_MASK
+SCSI_In_DBx__6__BYP EQU CYREG_PRT2_BYP
+SCSI_In_DBx__6__CTL EQU CYREG_PRT2_CTL
+SCSI_In_DBx__6__DM0 EQU CYREG_PRT2_DM0
+SCSI_In_DBx__6__DM1 EQU CYREG_PRT2_DM1
+SCSI_In_DBx__6__DM2 EQU CYREG_PRT2_DM2
+SCSI_In_DBx__6__DR EQU CYREG_PRT2_DR
+SCSI_In_DBx__6__INP_DIS EQU CYREG_PRT2_INP_DIS
+SCSI_In_DBx__6__INTTYPE EQU CYREG_PICU2_INTTYPE0
+SCSI_In_DBx__6__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
+SCSI_In_DBx__6__LCD_EN EQU CYREG_PRT2_LCD_EN
+SCSI_In_DBx__6__MASK EQU 0x01
+SCSI_In_DBx__6__PC EQU CYREG_PRT2_PC0
+SCSI_In_DBx__6__PORT EQU 2
+SCSI_In_DBx__6__PRT EQU CYREG_PRT2_PRT
+SCSI_In_DBx__6__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
+SCSI_In_DBx__6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
+SCSI_In_DBx__6__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
+SCSI_In_DBx__6__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
+SCSI_In_DBx__6__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
+SCSI_In_DBx__6__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
+SCSI_In_DBx__6__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
+SCSI_In_DBx__6__PS EQU CYREG_PRT2_PS
+SCSI_In_DBx__6__SHIFT EQU 0
+SCSI_In_DBx__6__SLW EQU CYREG_PRT2_SLW
+SCSI_In_DBx__7__AG EQU CYREG_PRT6_AG
+SCSI_In_DBx__7__AMUX EQU CYREG_PRT6_AMUX
+SCSI_In_DBx__7__BIE EQU CYREG_PRT6_BIE
+SCSI_In_DBx__7__BIT_MASK EQU CYREG_PRT6_BIT_MASK
+SCSI_In_DBx__7__BYP EQU CYREG_PRT6_BYP
+SCSI_In_DBx__7__CTL EQU CYREG_PRT6_CTL
+SCSI_In_DBx__7__DM0 EQU CYREG_PRT6_DM0
+SCSI_In_DBx__7__DM1 EQU CYREG_PRT6_DM1
+SCSI_In_DBx__7__DM2 EQU CYREG_PRT6_DM2
+SCSI_In_DBx__7__DR EQU CYREG_PRT6_DR
+SCSI_In_DBx__7__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_In_DBx__7__INTTYPE EQU CYREG_PICU6_INTTYPE3
+SCSI_In_DBx__7__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
+SCSI_In_DBx__7__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_In_DBx__7__MASK EQU 0x08
+SCSI_In_DBx__7__PC EQU CYREG_PRT6_PC3
+SCSI_In_DBx__7__PORT EQU 6
+SCSI_In_DBx__7__PRT EQU CYREG_PRT6_PRT
+SCSI_In_DBx__7__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
+SCSI_In_DBx__7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
+SCSI_In_DBx__7__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
+SCSI_In_DBx__7__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
+SCSI_In_DBx__7__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
+SCSI_In_DBx__7__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
+SCSI_In_DBx__7__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
+SCSI_In_DBx__7__PS EQU CYREG_PRT6_PS
+SCSI_In_DBx__7__SHIFT EQU 3
+SCSI_In_DBx__7__SLW EQU CYREG_PRT6_SLW
+SCSI_In_DBx__DB0__AG EQU CYREG_PRT6_AG
+SCSI_In_DBx__DB0__AMUX EQU CYREG_PRT6_AMUX
+SCSI_In_DBx__DB0__BIE EQU CYREG_PRT6_BIE
+SCSI_In_DBx__DB0__BIT_MASK EQU CYREG_PRT6_BIT_MASK
+SCSI_In_DBx__DB0__BYP EQU CYREG_PRT6_BYP
+SCSI_In_DBx__DB0__CTL EQU CYREG_PRT6_CTL
+SCSI_In_DBx__DB0__DM0 EQU CYREG_PRT6_DM0
+SCSI_In_DBx__DB0__DM1 EQU CYREG_PRT6_DM1
+SCSI_In_DBx__DB0__DM2 EQU CYREG_PRT6_DM2
+SCSI_In_DBx__DB0__DR EQU CYREG_PRT6_DR
+SCSI_In_DBx__DB0__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_In_DBx__DB0__INTTYPE EQU CYREG_PICU6_INTTYPE6
+SCSI_In_DBx__DB0__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
+SCSI_In_DBx__DB0__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_In_DBx__DB0__MASK EQU 0x40
+SCSI_In_DBx__DB0__PC EQU CYREG_PRT6_PC6
+SCSI_In_DBx__DB0__PORT EQU 6
+SCSI_In_DBx__DB0__PRT EQU CYREG_PRT6_PRT
+SCSI_In_DBx__DB0__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
+SCSI_In_DBx__DB0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
+SCSI_In_DBx__DB0__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
+SCSI_In_DBx__DB0__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
+SCSI_In_DBx__DB0__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
+SCSI_In_DBx__DB0__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
+SCSI_In_DBx__DB0__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
+SCSI_In_DBx__DB0__PS EQU CYREG_PRT6_PS
+SCSI_In_DBx__DB0__SHIFT EQU 6
+SCSI_In_DBx__DB0__SLW EQU CYREG_PRT6_SLW
+SCSI_In_DBx__DB1__AG EQU CYREG_PRT6_AG
+SCSI_In_DBx__DB1__AMUX EQU CYREG_PRT6_AMUX
+SCSI_In_DBx__DB1__BIE EQU CYREG_PRT6_BIE
+SCSI_In_DBx__DB1__BIT_MASK EQU CYREG_PRT6_BIT_MASK
+SCSI_In_DBx__DB1__BYP EQU CYREG_PRT6_BYP
+SCSI_In_DBx__DB1__CTL EQU CYREG_PRT6_CTL
+SCSI_In_DBx__DB1__DM0 EQU CYREG_PRT6_DM0
+SCSI_In_DBx__DB1__DM1 EQU CYREG_PRT6_DM1
+SCSI_In_DBx__DB1__DM2 EQU CYREG_PRT6_DM2
+SCSI_In_DBx__DB1__DR EQU CYREG_PRT6_DR
+SCSI_In_DBx__DB1__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_In_DBx__DB1__INTTYPE EQU CYREG_PICU6_INTTYPE4
+SCSI_In_DBx__DB1__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
+SCSI_In_DBx__DB1__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_In_DBx__DB1__MASK EQU 0x10
+SCSI_In_DBx__DB1__PC EQU CYREG_PRT6_PC4
+SCSI_In_DBx__DB1__PORT EQU 6
+SCSI_In_DBx__DB1__PRT EQU CYREG_PRT6_PRT
+SCSI_In_DBx__DB1__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
+SCSI_In_DBx__DB1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
+SCSI_In_DBx__DB1__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
+SCSI_In_DBx__DB1__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
+SCSI_In_DBx__DB1__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
+SCSI_In_DBx__DB1__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
+SCSI_In_DBx__DB1__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
+SCSI_In_DBx__DB1__PS EQU CYREG_PRT6_PS
+SCSI_In_DBx__DB1__SHIFT EQU 4
+SCSI_In_DBx__DB1__SLW EQU CYREG_PRT6_SLW
+SCSI_In_DBx__DB2__AG EQU CYREG_PRT12_AG
+SCSI_In_DBx__DB2__BIE EQU CYREG_PRT12_BIE
+SCSI_In_DBx__DB2__BIT_MASK EQU CYREG_PRT12_BIT_MASK
+SCSI_In_DBx__DB2__BYP EQU CYREG_PRT12_BYP
+SCSI_In_DBx__DB2__DM0 EQU CYREG_PRT12_DM0
+SCSI_In_DBx__DB2__DM1 EQU CYREG_PRT12_DM1
+SCSI_In_DBx__DB2__DM2 EQU CYREG_PRT12_DM2
+SCSI_In_DBx__DB2__DR EQU CYREG_PRT12_DR
+SCSI_In_DBx__DB2__INP_DIS EQU CYREG_PRT12_INP_DIS
+SCSI_In_DBx__DB2__INTTYPE EQU CYREG_PICU12_INTTYPE4
+SCSI_In_DBx__DB2__MASK EQU 0x10
+SCSI_In_DBx__DB2__PC EQU CYREG_PRT12_PC4
+SCSI_In_DBx__DB2__PORT EQU 12
+SCSI_In_DBx__DB2__PRT EQU CYREG_PRT12_PRT
+SCSI_In_DBx__DB2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN
+SCSI_In_DBx__DB2__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0
+SCSI_In_DBx__DB2__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1
+SCSI_In_DBx__DB2__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0
+SCSI_In_DBx__DB2__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1
+SCSI_In_DBx__DB2__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT
+SCSI_In_DBx__DB2__PS EQU CYREG_PRT12_PS
+SCSI_In_DBx__DB2__SHIFT EQU 4
+SCSI_In_DBx__DB2__SIO_CFG EQU CYREG_PRT12_SIO_CFG
+SCSI_In_DBx__DB2__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF
+SCSI_In_DBx__DB2__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN
+SCSI_In_DBx__DB2__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ
+SCSI_In_DBx__DB2__SLW EQU CYREG_PRT12_SLW
+SCSI_In_DBx__DB3__AG EQU CYREG_PRT2_AG
+SCSI_In_DBx__DB3__AMUX EQU CYREG_PRT2_AMUX
+SCSI_In_DBx__DB3__BIE EQU CYREG_PRT2_BIE
+SCSI_In_DBx__DB3__BIT_MASK EQU CYREG_PRT2_BIT_MASK
+SCSI_In_DBx__DB3__BYP EQU CYREG_PRT2_BYP
+SCSI_In_DBx__DB3__CTL EQU CYREG_PRT2_CTL
+SCSI_In_DBx__DB3__DM0 EQU CYREG_PRT2_DM0
+SCSI_In_DBx__DB3__DM1 EQU CYREG_PRT2_DM1
+SCSI_In_DBx__DB3__DM2 EQU CYREG_PRT2_DM2
+SCSI_In_DBx__DB3__DR EQU CYREG_PRT2_DR
+SCSI_In_DBx__DB3__INP_DIS EQU CYREG_PRT2_INP_DIS
+SCSI_In_DBx__DB3__INTTYPE EQU CYREG_PICU2_INTTYPE6
+SCSI_In_DBx__DB3__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
+SCSI_In_DBx__DB3__LCD_EN EQU CYREG_PRT2_LCD_EN
+SCSI_In_DBx__DB3__MASK EQU 0x40
+SCSI_In_DBx__DB3__PC EQU CYREG_PRT2_PC6
+SCSI_In_DBx__DB3__PORT EQU 2
+SCSI_In_DBx__DB3__PRT EQU CYREG_PRT2_PRT
+SCSI_In_DBx__DB3__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
+SCSI_In_DBx__DB3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
+SCSI_In_DBx__DB3__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
+SCSI_In_DBx__DB3__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
+SCSI_In_DBx__DB3__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
+SCSI_In_DBx__DB3__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
+SCSI_In_DBx__DB3__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
+SCSI_In_DBx__DB3__PS EQU CYREG_PRT2_PS
+SCSI_In_DBx__DB3__SHIFT EQU 6
+SCSI_In_DBx__DB3__SLW EQU CYREG_PRT2_SLW
+SCSI_In_DBx__DB4__AG EQU CYREG_PRT2_AG
+SCSI_In_DBx__DB4__AMUX EQU CYREG_PRT2_AMUX
+SCSI_In_DBx__DB4__BIE EQU CYREG_PRT2_BIE
+SCSI_In_DBx__DB4__BIT_MASK EQU CYREG_PRT2_BIT_MASK
+SCSI_In_DBx__DB4__BYP EQU CYREG_PRT2_BYP
+SCSI_In_DBx__DB4__CTL EQU CYREG_PRT2_CTL
+SCSI_In_DBx__DB4__DM0 EQU CYREG_PRT2_DM0
+SCSI_In_DBx__DB4__DM1 EQU CYREG_PRT2_DM1
+SCSI_In_DBx__DB4__DM2 EQU CYREG_PRT2_DM2
+SCSI_In_DBx__DB4__DR EQU CYREG_PRT2_DR
+SCSI_In_DBx__DB4__INP_DIS EQU CYREG_PRT2_INP_DIS
+SCSI_In_DBx__DB4__INTTYPE EQU CYREG_PICU2_INTTYPE4
+SCSI_In_DBx__DB4__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
+SCSI_In_DBx__DB4__LCD_EN EQU CYREG_PRT2_LCD_EN
+SCSI_In_DBx__DB4__MASK EQU 0x10
+SCSI_In_DBx__DB4__PC EQU CYREG_PRT2_PC4
+SCSI_In_DBx__DB4__PORT EQU 2
+SCSI_In_DBx__DB4__PRT EQU CYREG_PRT2_PRT
+SCSI_In_DBx__DB4__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
+SCSI_In_DBx__DB4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
+SCSI_In_DBx__DB4__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
+SCSI_In_DBx__DB4__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
+SCSI_In_DBx__DB4__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
+SCSI_In_DBx__DB4__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
+SCSI_In_DBx__DB4__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
+SCSI_In_DBx__DB4__PS EQU CYREG_PRT2_PS
+SCSI_In_DBx__DB4__SHIFT EQU 4
+SCSI_In_DBx__DB4__SLW EQU CYREG_PRT2_SLW
+SCSI_In_DBx__DB5__AG EQU CYREG_PRT2_AG
+SCSI_In_DBx__DB5__AMUX EQU CYREG_PRT2_AMUX
+SCSI_In_DBx__DB5__BIE EQU CYREG_PRT2_BIE
+SCSI_In_DBx__DB5__BIT_MASK EQU CYREG_PRT2_BIT_MASK
+SCSI_In_DBx__DB5__BYP EQU CYREG_PRT2_BYP
+SCSI_In_DBx__DB5__CTL EQU CYREG_PRT2_CTL
+SCSI_In_DBx__DB5__DM0 EQU CYREG_PRT2_DM0
+SCSI_In_DBx__DB5__DM1 EQU CYREG_PRT2_DM1
+SCSI_In_DBx__DB5__DM2 EQU CYREG_PRT2_DM2
+SCSI_In_DBx__DB5__DR EQU CYREG_PRT2_DR
+SCSI_In_DBx__DB5__INP_DIS EQU CYREG_PRT2_INP_DIS
+SCSI_In_DBx__DB5__INTTYPE EQU CYREG_PICU2_INTTYPE2
+SCSI_In_DBx__DB5__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
+SCSI_In_DBx__DB5__LCD_EN EQU CYREG_PRT2_LCD_EN
+SCSI_In_DBx__DB5__MASK EQU 0x04
+SCSI_In_DBx__DB5__PC EQU CYREG_PRT2_PC2
+SCSI_In_DBx__DB5__PORT EQU 2
+SCSI_In_DBx__DB5__PRT EQU CYREG_PRT2_PRT
+SCSI_In_DBx__DB5__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
+SCSI_In_DBx__DB5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
+SCSI_In_DBx__DB5__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
+SCSI_In_DBx__DB5__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
+SCSI_In_DBx__DB5__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
+SCSI_In_DBx__DB5__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
+SCSI_In_DBx__DB5__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
+SCSI_In_DBx__DB5__PS EQU CYREG_PRT2_PS
+SCSI_In_DBx__DB5__SHIFT EQU 2
+SCSI_In_DBx__DB5__SLW EQU CYREG_PRT2_SLW
+SCSI_In_DBx__DB6__AG EQU CYREG_PRT2_AG
+SCSI_In_DBx__DB6__AMUX EQU CYREG_PRT2_AMUX
+SCSI_In_DBx__DB6__BIE EQU CYREG_PRT2_BIE
+SCSI_In_DBx__DB6__BIT_MASK EQU CYREG_PRT2_BIT_MASK
+SCSI_In_DBx__DB6__BYP EQU CYREG_PRT2_BYP
+SCSI_In_DBx__DB6__CTL EQU CYREG_PRT2_CTL
+SCSI_In_DBx__DB6__DM0 EQU CYREG_PRT2_DM0
+SCSI_In_DBx__DB6__DM1 EQU CYREG_PRT2_DM1
+SCSI_In_DBx__DB6__DM2 EQU CYREG_PRT2_DM2
+SCSI_In_DBx__DB6__DR EQU CYREG_PRT2_DR
+SCSI_In_DBx__DB6__INP_DIS EQU CYREG_PRT2_INP_DIS
+SCSI_In_DBx__DB6__INTTYPE EQU CYREG_PICU2_INTTYPE0
+SCSI_In_DBx__DB6__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
+SCSI_In_DBx__DB6__LCD_EN EQU CYREG_PRT2_LCD_EN
+SCSI_In_DBx__DB6__MASK EQU 0x01
+SCSI_In_DBx__DB6__PC EQU CYREG_PRT2_PC0
+SCSI_In_DBx__DB6__PORT EQU 2
+SCSI_In_DBx__DB6__PRT EQU CYREG_PRT2_PRT
+SCSI_In_DBx__DB6__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
+SCSI_In_DBx__DB6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
+SCSI_In_DBx__DB6__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
+SCSI_In_DBx__DB6__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
+SCSI_In_DBx__DB6__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
+SCSI_In_DBx__DB6__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
+SCSI_In_DBx__DB6__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
+SCSI_In_DBx__DB6__PS EQU CYREG_PRT2_PS
+SCSI_In_DBx__DB6__SHIFT EQU 0
+SCSI_In_DBx__DB6__SLW EQU CYREG_PRT2_SLW
+SCSI_In_DBx__DB7__AG EQU CYREG_PRT6_AG
+SCSI_In_DBx__DB7__AMUX EQU CYREG_PRT6_AMUX
+SCSI_In_DBx__DB7__BIE EQU CYREG_PRT6_BIE
+SCSI_In_DBx__DB7__BIT_MASK EQU CYREG_PRT6_BIT_MASK
+SCSI_In_DBx__DB7__BYP EQU CYREG_PRT6_BYP
+SCSI_In_DBx__DB7__CTL EQU CYREG_PRT6_CTL
+SCSI_In_DBx__DB7__DM0 EQU CYREG_PRT6_DM0
+SCSI_In_DBx__DB7__DM1 EQU CYREG_PRT6_DM1
+SCSI_In_DBx__DB7__DM2 EQU CYREG_PRT6_DM2
+SCSI_In_DBx__DB7__DR EQU CYREG_PRT6_DR
+SCSI_In_DBx__DB7__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_In_DBx__DB7__INTTYPE EQU CYREG_PICU6_INTTYPE3
+SCSI_In_DBx__DB7__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
+SCSI_In_DBx__DB7__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_In_DBx__DB7__MASK EQU 0x08
+SCSI_In_DBx__DB7__PC EQU CYREG_PRT6_PC3
+SCSI_In_DBx__DB7__PORT EQU 6
+SCSI_In_DBx__DB7__PRT EQU CYREG_PRT6_PRT
+SCSI_In_DBx__DB7__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
+SCSI_In_DBx__DB7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
+SCSI_In_DBx__DB7__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
+SCSI_In_DBx__DB7__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
+SCSI_In_DBx__DB7__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
+SCSI_In_DBx__DB7__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
+SCSI_In_DBx__DB7__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
+SCSI_In_DBx__DB7__PS EQU CYREG_PRT6_PS
+SCSI_In_DBx__DB7__SHIFT EQU 3
+SCSI_In_DBx__DB7__SLW EQU CYREG_PRT6_SLW
 
 ; SCSI_Noise
 SCSI_Noise__0__AG EQU CYREG_PRT4_AG
@@ -2354,6 +932,1592 @@ SCSI_Noise__SEL__PS EQU CYREG_PRT0_PS
 SCSI_Noise__SEL__SHIFT EQU 2
 SCSI_Noise__SEL__SLW EQU CYREG_PRT0_SLW
 
+; SCSI_Out
+SCSI_Out__0__AG EQU CYREG_PRT6_AG
+SCSI_Out__0__AMUX EQU CYREG_PRT6_AMUX
+SCSI_Out__0__BIE EQU CYREG_PRT6_BIE
+SCSI_Out__0__BIT_MASK EQU CYREG_PRT6_BIT_MASK
+SCSI_Out__0__BYP EQU CYREG_PRT6_BYP
+SCSI_Out__0__CTL EQU CYREG_PRT6_CTL
+SCSI_Out__0__DM0 EQU CYREG_PRT6_DM0
+SCSI_Out__0__DM1 EQU CYREG_PRT6_DM1
+SCSI_Out__0__DM2 EQU CYREG_PRT6_DM2
+SCSI_Out__0__DR EQU CYREG_PRT6_DR
+SCSI_Out__0__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_Out__0__INTTYPE EQU CYREG_PICU6_INTTYPE2
+SCSI_Out__0__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
+SCSI_Out__0__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_Out__0__MASK EQU 0x04
+SCSI_Out__0__PC EQU CYREG_PRT6_PC2
+SCSI_Out__0__PORT EQU 6
+SCSI_Out__0__PRT EQU CYREG_PRT6_PRT
+SCSI_Out__0__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
+SCSI_Out__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
+SCSI_Out__0__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
+SCSI_Out__0__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
+SCSI_Out__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
+SCSI_Out__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
+SCSI_Out__0__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
+SCSI_Out__0__PS EQU CYREG_PRT6_PS
+SCSI_Out__0__SHIFT EQU 2
+SCSI_Out__0__SLW EQU CYREG_PRT6_SLW
+SCSI_Out__1__AG EQU CYREG_PRT4_AG
+SCSI_Out__1__AMUX EQU CYREG_PRT4_AMUX
+SCSI_Out__1__BIE EQU CYREG_PRT4_BIE
+SCSI_Out__1__BIT_MASK EQU CYREG_PRT4_BIT_MASK
+SCSI_Out__1__BYP EQU CYREG_PRT4_BYP
+SCSI_Out__1__CTL EQU CYREG_PRT4_CTL
+SCSI_Out__1__DM0 EQU CYREG_PRT4_DM0
+SCSI_Out__1__DM1 EQU CYREG_PRT4_DM1
+SCSI_Out__1__DM2 EQU CYREG_PRT4_DM2
+SCSI_Out__1__DR EQU CYREG_PRT4_DR
+SCSI_Out__1__INP_DIS EQU CYREG_PRT4_INP_DIS
+SCSI_Out__1__INTTYPE EQU CYREG_PICU4_INTTYPE6
+SCSI_Out__1__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
+SCSI_Out__1__LCD_EN EQU CYREG_PRT4_LCD_EN
+SCSI_Out__1__MASK EQU 0x40
+SCSI_Out__1__PC EQU CYREG_PRT4_PC6
+SCSI_Out__1__PORT EQU 4
+SCSI_Out__1__PRT EQU CYREG_PRT4_PRT
+SCSI_Out__1__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
+SCSI_Out__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
+SCSI_Out__1__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
+SCSI_Out__1__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
+SCSI_Out__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
+SCSI_Out__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
+SCSI_Out__1__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
+SCSI_Out__1__PS EQU CYREG_PRT4_PS
+SCSI_Out__1__SHIFT EQU 6
+SCSI_Out__1__SLW EQU CYREG_PRT4_SLW
+SCSI_Out__2__AG EQU CYREG_PRT0_AG
+SCSI_Out__2__AMUX EQU CYREG_PRT0_AMUX
+SCSI_Out__2__BIE EQU CYREG_PRT0_BIE
+SCSI_Out__2__BIT_MASK EQU CYREG_PRT0_BIT_MASK
+SCSI_Out__2__BYP EQU CYREG_PRT0_BYP
+SCSI_Out__2__CTL EQU CYREG_PRT0_CTL
+SCSI_Out__2__DM0 EQU CYREG_PRT0_DM0
+SCSI_Out__2__DM1 EQU CYREG_PRT0_DM1
+SCSI_Out__2__DM2 EQU CYREG_PRT0_DM2
+SCSI_Out__2__DR EQU CYREG_PRT0_DR
+SCSI_Out__2__INP_DIS EQU CYREG_PRT0_INP_DIS
+SCSI_Out__2__INTTYPE EQU CYREG_PICU0_INTTYPE7
+SCSI_Out__2__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
+SCSI_Out__2__LCD_EN EQU CYREG_PRT0_LCD_EN
+SCSI_Out__2__MASK EQU 0x80
+SCSI_Out__2__PC EQU CYREG_PRT0_PC7
+SCSI_Out__2__PORT EQU 0
+SCSI_Out__2__PRT EQU CYREG_PRT0_PRT
+SCSI_Out__2__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
+SCSI_Out__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
+SCSI_Out__2__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
+SCSI_Out__2__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
+SCSI_Out__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
+SCSI_Out__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
+SCSI_Out__2__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
+SCSI_Out__2__PS EQU CYREG_PRT0_PS
+SCSI_Out__2__SHIFT EQU 7
+SCSI_Out__2__SLW EQU CYREG_PRT0_SLW
+SCSI_Out__3__AG EQU CYREG_PRT0_AG
+SCSI_Out__3__AMUX EQU CYREG_PRT0_AMUX
+SCSI_Out__3__BIE EQU CYREG_PRT0_BIE
+SCSI_Out__3__BIT_MASK EQU CYREG_PRT0_BIT_MASK
+SCSI_Out__3__BYP EQU CYREG_PRT0_BYP
+SCSI_Out__3__CTL EQU CYREG_PRT0_CTL
+SCSI_Out__3__DM0 EQU CYREG_PRT0_DM0
+SCSI_Out__3__DM1 EQU CYREG_PRT0_DM1
+SCSI_Out__3__DM2 EQU CYREG_PRT0_DM2
+SCSI_Out__3__DR EQU CYREG_PRT0_DR
+SCSI_Out__3__INP_DIS EQU CYREG_PRT0_INP_DIS
+SCSI_Out__3__INTTYPE EQU CYREG_PICU0_INTTYPE5
+SCSI_Out__3__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
+SCSI_Out__3__LCD_EN EQU CYREG_PRT0_LCD_EN
+SCSI_Out__3__MASK EQU 0x20
+SCSI_Out__3__PC EQU CYREG_PRT0_PC5
+SCSI_Out__3__PORT EQU 0
+SCSI_Out__3__PRT EQU CYREG_PRT0_PRT
+SCSI_Out__3__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
+SCSI_Out__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
+SCSI_Out__3__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
+SCSI_Out__3__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
+SCSI_Out__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
+SCSI_Out__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
+SCSI_Out__3__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
+SCSI_Out__3__PS EQU CYREG_PRT0_PS
+SCSI_Out__3__SHIFT EQU 5
+SCSI_Out__3__SLW EQU CYREG_PRT0_SLW
+SCSI_Out__4__AG EQU CYREG_PRT0_AG
+SCSI_Out__4__AMUX EQU CYREG_PRT0_AMUX
+SCSI_Out__4__BIE EQU CYREG_PRT0_BIE
+SCSI_Out__4__BIT_MASK EQU CYREG_PRT0_BIT_MASK
+SCSI_Out__4__BYP EQU CYREG_PRT0_BYP
+SCSI_Out__4__CTL EQU CYREG_PRT0_CTL
+SCSI_Out__4__DM0 EQU CYREG_PRT0_DM0
+SCSI_Out__4__DM1 EQU CYREG_PRT0_DM1
+SCSI_Out__4__DM2 EQU CYREG_PRT0_DM2
+SCSI_Out__4__DR EQU CYREG_PRT0_DR
+SCSI_Out__4__INP_DIS EQU CYREG_PRT0_INP_DIS
+SCSI_Out__4__INTTYPE EQU CYREG_PICU0_INTTYPE3
+SCSI_Out__4__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
+SCSI_Out__4__LCD_EN EQU CYREG_PRT0_LCD_EN
+SCSI_Out__4__MASK EQU 0x08
+SCSI_Out__4__PC EQU CYREG_PRT0_PC3
+SCSI_Out__4__PORT EQU 0
+SCSI_Out__4__PRT EQU CYREG_PRT0_PRT
+SCSI_Out__4__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
+SCSI_Out__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
+SCSI_Out__4__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
+SCSI_Out__4__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
+SCSI_Out__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
+SCSI_Out__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
+SCSI_Out__4__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
+SCSI_Out__4__PS EQU CYREG_PRT0_PS
+SCSI_Out__4__SHIFT EQU 3
+SCSI_Out__4__SLW EQU CYREG_PRT0_SLW
+SCSI_Out__5__AG EQU CYREG_PRT0_AG
+SCSI_Out__5__AMUX EQU CYREG_PRT0_AMUX
+SCSI_Out__5__BIE EQU CYREG_PRT0_BIE
+SCSI_Out__5__BIT_MASK EQU CYREG_PRT0_BIT_MASK
+SCSI_Out__5__BYP EQU CYREG_PRT0_BYP
+SCSI_Out__5__CTL EQU CYREG_PRT0_CTL
+SCSI_Out__5__DM0 EQU CYREG_PRT0_DM0
+SCSI_Out__5__DM1 EQU CYREG_PRT0_DM1
+SCSI_Out__5__DM2 EQU CYREG_PRT0_DM2
+SCSI_Out__5__DR EQU CYREG_PRT0_DR
+SCSI_Out__5__INP_DIS EQU CYREG_PRT0_INP_DIS
+SCSI_Out__5__INTTYPE EQU CYREG_PICU0_INTTYPE1
+SCSI_Out__5__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
+SCSI_Out__5__LCD_EN EQU CYREG_PRT0_LCD_EN
+SCSI_Out__5__MASK EQU 0x02
+SCSI_Out__5__PC EQU CYREG_PRT0_PC1
+SCSI_Out__5__PORT EQU 0
+SCSI_Out__5__PRT EQU CYREG_PRT0_PRT
+SCSI_Out__5__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
+SCSI_Out__5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
+SCSI_Out__5__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
+SCSI_Out__5__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
+SCSI_Out__5__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
+SCSI_Out__5__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
+SCSI_Out__5__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
+SCSI_Out__5__PS EQU CYREG_PRT0_PS
+SCSI_Out__5__SHIFT EQU 1
+SCSI_Out__5__SLW EQU CYREG_PRT0_SLW
+SCSI_Out__6__AG EQU CYREG_PRT4_AG
+SCSI_Out__6__AMUX EQU CYREG_PRT4_AMUX
+SCSI_Out__6__BIE EQU CYREG_PRT4_BIE
+SCSI_Out__6__BIT_MASK EQU CYREG_PRT4_BIT_MASK
+SCSI_Out__6__BYP EQU CYREG_PRT4_BYP
+SCSI_Out__6__CTL EQU CYREG_PRT4_CTL
+SCSI_Out__6__DM0 EQU CYREG_PRT4_DM0
+SCSI_Out__6__DM1 EQU CYREG_PRT4_DM1
+SCSI_Out__6__DM2 EQU CYREG_PRT4_DM2
+SCSI_Out__6__DR EQU CYREG_PRT4_DR
+SCSI_Out__6__INP_DIS EQU CYREG_PRT4_INP_DIS
+SCSI_Out__6__INTTYPE EQU CYREG_PICU4_INTTYPE1
+SCSI_Out__6__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
+SCSI_Out__6__LCD_EN EQU CYREG_PRT4_LCD_EN
+SCSI_Out__6__MASK EQU 0x02
+SCSI_Out__6__PC EQU CYREG_PRT4_PC1
+SCSI_Out__6__PORT EQU 4
+SCSI_Out__6__PRT EQU CYREG_PRT4_PRT
+SCSI_Out__6__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
+SCSI_Out__6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
+SCSI_Out__6__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
+SCSI_Out__6__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
+SCSI_Out__6__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
+SCSI_Out__6__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
+SCSI_Out__6__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
+SCSI_Out__6__PS EQU CYREG_PRT4_PS
+SCSI_Out__6__SHIFT EQU 1
+SCSI_Out__6__SLW EQU CYREG_PRT4_SLW
+SCSI_Out__7__AG EQU CYREG_PRT12_AG
+SCSI_Out__7__BIE EQU CYREG_PRT12_BIE
+SCSI_Out__7__BIT_MASK EQU CYREG_PRT12_BIT_MASK
+SCSI_Out__7__BYP EQU CYREG_PRT12_BYP
+SCSI_Out__7__DM0 EQU CYREG_PRT12_DM0
+SCSI_Out__7__DM1 EQU CYREG_PRT12_DM1
+SCSI_Out__7__DM2 EQU CYREG_PRT12_DM2
+SCSI_Out__7__DR EQU CYREG_PRT12_DR
+SCSI_Out__7__INP_DIS EQU CYREG_PRT12_INP_DIS
+SCSI_Out__7__INTTYPE EQU CYREG_PICU12_INTTYPE3
+SCSI_Out__7__MASK EQU 0x08
+SCSI_Out__7__PC EQU CYREG_PRT12_PC3
+SCSI_Out__7__PORT EQU 12
+SCSI_Out__7__PRT EQU CYREG_PRT12_PRT
+SCSI_Out__7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN
+SCSI_Out__7__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0
+SCSI_Out__7__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1
+SCSI_Out__7__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0
+SCSI_Out__7__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1
+SCSI_Out__7__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT
+SCSI_Out__7__PS EQU CYREG_PRT12_PS
+SCSI_Out__7__SHIFT EQU 3
+SCSI_Out__7__SIO_CFG EQU CYREG_PRT12_SIO_CFG
+SCSI_Out__7__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF
+SCSI_Out__7__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN
+SCSI_Out__7__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ
+SCSI_Out__7__SLW EQU CYREG_PRT12_SLW
+SCSI_Out__BSY__AG EQU CYREG_PRT4_AG
+SCSI_Out__BSY__AMUX EQU CYREG_PRT4_AMUX
+SCSI_Out__BSY__BIE EQU CYREG_PRT4_BIE
+SCSI_Out__BSY__BIT_MASK EQU CYREG_PRT4_BIT_MASK
+SCSI_Out__BSY__BYP EQU CYREG_PRT4_BYP
+SCSI_Out__BSY__CTL EQU CYREG_PRT4_CTL
+SCSI_Out__BSY__DM0 EQU CYREG_PRT4_DM0
+SCSI_Out__BSY__DM1 EQU CYREG_PRT4_DM1
+SCSI_Out__BSY__DM2 EQU CYREG_PRT4_DM2
+SCSI_Out__BSY__DR EQU CYREG_PRT4_DR
+SCSI_Out__BSY__INP_DIS EQU CYREG_PRT4_INP_DIS
+SCSI_Out__BSY__INTTYPE EQU CYREG_PICU4_INTTYPE6
+SCSI_Out__BSY__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
+SCSI_Out__BSY__LCD_EN EQU CYREG_PRT4_LCD_EN
+SCSI_Out__BSY__MASK EQU 0x40
+SCSI_Out__BSY__PC EQU CYREG_PRT4_PC6
+SCSI_Out__BSY__PORT EQU 4
+SCSI_Out__BSY__PRT EQU CYREG_PRT4_PRT
+SCSI_Out__BSY__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
+SCSI_Out__BSY__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
+SCSI_Out__BSY__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
+SCSI_Out__BSY__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
+SCSI_Out__BSY__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
+SCSI_Out__BSY__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
+SCSI_Out__BSY__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
+SCSI_Out__BSY__PS EQU CYREG_PRT4_PS
+SCSI_Out__BSY__SHIFT EQU 6
+SCSI_Out__BSY__SLW EQU CYREG_PRT4_SLW
+SCSI_Out__CD_raw__AG EQU CYREG_PRT0_AG
+SCSI_Out__CD_raw__AMUX EQU CYREG_PRT0_AMUX
+SCSI_Out__CD_raw__BIE EQU CYREG_PRT0_BIE
+SCSI_Out__CD_raw__BIT_MASK EQU CYREG_PRT0_BIT_MASK
+SCSI_Out__CD_raw__BYP EQU CYREG_PRT0_BYP
+SCSI_Out__CD_raw__CTL EQU CYREG_PRT0_CTL
+SCSI_Out__CD_raw__DM0 EQU CYREG_PRT0_DM0
+SCSI_Out__CD_raw__DM1 EQU CYREG_PRT0_DM1
+SCSI_Out__CD_raw__DM2 EQU CYREG_PRT0_DM2
+SCSI_Out__CD_raw__DR EQU CYREG_PRT0_DR
+SCSI_Out__CD_raw__INP_DIS EQU CYREG_PRT0_INP_DIS
+SCSI_Out__CD_raw__INTTYPE EQU CYREG_PICU0_INTTYPE1
+SCSI_Out__CD_raw__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
+SCSI_Out__CD_raw__LCD_EN EQU CYREG_PRT0_LCD_EN
+SCSI_Out__CD_raw__MASK EQU 0x02
+SCSI_Out__CD_raw__PC EQU CYREG_PRT0_PC1
+SCSI_Out__CD_raw__PORT EQU 0
+SCSI_Out__CD_raw__PRT EQU CYREG_PRT0_PRT
+SCSI_Out__CD_raw__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
+SCSI_Out__CD_raw__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
+SCSI_Out__CD_raw__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
+SCSI_Out__CD_raw__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
+SCSI_Out__CD_raw__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
+SCSI_Out__CD_raw__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
+SCSI_Out__CD_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
+SCSI_Out__CD_raw__PS EQU CYREG_PRT0_PS
+SCSI_Out__CD_raw__SHIFT EQU 1
+SCSI_Out__CD_raw__SLW EQU CYREG_PRT0_SLW
+SCSI_Out__DBP_raw__AG EQU CYREG_PRT6_AG
+SCSI_Out__DBP_raw__AMUX EQU CYREG_PRT6_AMUX
+SCSI_Out__DBP_raw__BIE EQU CYREG_PRT6_BIE
+SCSI_Out__DBP_raw__BIT_MASK EQU CYREG_PRT6_BIT_MASK
+SCSI_Out__DBP_raw__BYP EQU CYREG_PRT6_BYP
+SCSI_Out__DBP_raw__CTL EQU CYREG_PRT6_CTL
+SCSI_Out__DBP_raw__DM0 EQU CYREG_PRT6_DM0
+SCSI_Out__DBP_raw__DM1 EQU CYREG_PRT6_DM1
+SCSI_Out__DBP_raw__DM2 EQU CYREG_PRT6_DM2
+SCSI_Out__DBP_raw__DR EQU CYREG_PRT6_DR
+SCSI_Out__DBP_raw__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_Out__DBP_raw__INTTYPE EQU CYREG_PICU6_INTTYPE2
+SCSI_Out__DBP_raw__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
+SCSI_Out__DBP_raw__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_Out__DBP_raw__MASK EQU 0x04
+SCSI_Out__DBP_raw__PC EQU CYREG_PRT6_PC2
+SCSI_Out__DBP_raw__PORT EQU 6
+SCSI_Out__DBP_raw__PRT EQU CYREG_PRT6_PRT
+SCSI_Out__DBP_raw__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
+SCSI_Out__DBP_raw__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
+SCSI_Out__DBP_raw__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
+SCSI_Out__DBP_raw__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
+SCSI_Out__DBP_raw__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
+SCSI_Out__DBP_raw__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
+SCSI_Out__DBP_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
+SCSI_Out__DBP_raw__PS EQU CYREG_PRT6_PS
+SCSI_Out__DBP_raw__SHIFT EQU 2
+SCSI_Out__DBP_raw__SLW EQU CYREG_PRT6_SLW
+SCSI_Out__IO_raw__AG EQU CYREG_PRT12_AG
+SCSI_Out__IO_raw__BIE EQU CYREG_PRT12_BIE
+SCSI_Out__IO_raw__BIT_MASK EQU CYREG_PRT12_BIT_MASK
+SCSI_Out__IO_raw__BYP EQU CYREG_PRT12_BYP
+SCSI_Out__IO_raw__DM0 EQU CYREG_PRT12_DM0
+SCSI_Out__IO_raw__DM1 EQU CYREG_PRT12_DM1
+SCSI_Out__IO_raw__DM2 EQU CYREG_PRT12_DM2
+SCSI_Out__IO_raw__DR EQU CYREG_PRT12_DR
+SCSI_Out__IO_raw__INP_DIS EQU CYREG_PRT12_INP_DIS
+SCSI_Out__IO_raw__INTTYPE EQU CYREG_PICU12_INTTYPE3
+SCSI_Out__IO_raw__MASK EQU 0x08
+SCSI_Out__IO_raw__PC EQU CYREG_PRT12_PC3
+SCSI_Out__IO_raw__PORT EQU 12
+SCSI_Out__IO_raw__PRT EQU CYREG_PRT12_PRT
+SCSI_Out__IO_raw__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN
+SCSI_Out__IO_raw__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0
+SCSI_Out__IO_raw__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1
+SCSI_Out__IO_raw__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0
+SCSI_Out__IO_raw__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1
+SCSI_Out__IO_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT
+SCSI_Out__IO_raw__PS EQU CYREG_PRT12_PS
+SCSI_Out__IO_raw__SHIFT EQU 3
+SCSI_Out__IO_raw__SIO_CFG EQU CYREG_PRT12_SIO_CFG
+SCSI_Out__IO_raw__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF
+SCSI_Out__IO_raw__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN
+SCSI_Out__IO_raw__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ
+SCSI_Out__IO_raw__SLW EQU CYREG_PRT12_SLW
+SCSI_Out__MSG_raw__AG EQU CYREG_PRT0_AG
+SCSI_Out__MSG_raw__AMUX EQU CYREG_PRT0_AMUX
+SCSI_Out__MSG_raw__BIE EQU CYREG_PRT0_BIE
+SCSI_Out__MSG_raw__BIT_MASK EQU CYREG_PRT0_BIT_MASK
+SCSI_Out__MSG_raw__BYP EQU CYREG_PRT0_BYP
+SCSI_Out__MSG_raw__CTL EQU CYREG_PRT0_CTL
+SCSI_Out__MSG_raw__DM0 EQU CYREG_PRT0_DM0
+SCSI_Out__MSG_raw__DM1 EQU CYREG_PRT0_DM1
+SCSI_Out__MSG_raw__DM2 EQU CYREG_PRT0_DM2
+SCSI_Out__MSG_raw__DR EQU CYREG_PRT0_DR
+SCSI_Out__MSG_raw__INP_DIS EQU CYREG_PRT0_INP_DIS
+SCSI_Out__MSG_raw__INTTYPE EQU CYREG_PICU0_INTTYPE5
+SCSI_Out__MSG_raw__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
+SCSI_Out__MSG_raw__LCD_EN EQU CYREG_PRT0_LCD_EN
+SCSI_Out__MSG_raw__MASK EQU 0x20
+SCSI_Out__MSG_raw__PC EQU CYREG_PRT0_PC5
+SCSI_Out__MSG_raw__PORT EQU 0
+SCSI_Out__MSG_raw__PRT EQU CYREG_PRT0_PRT
+SCSI_Out__MSG_raw__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
+SCSI_Out__MSG_raw__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
+SCSI_Out__MSG_raw__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
+SCSI_Out__MSG_raw__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
+SCSI_Out__MSG_raw__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
+SCSI_Out__MSG_raw__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
+SCSI_Out__MSG_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
+SCSI_Out__MSG_raw__PS EQU CYREG_PRT0_PS
+SCSI_Out__MSG_raw__SHIFT EQU 5
+SCSI_Out__MSG_raw__SLW EQU CYREG_PRT0_SLW
+SCSI_Out__REQ__AG EQU CYREG_PRT4_AG
+SCSI_Out__REQ__AMUX EQU CYREG_PRT4_AMUX
+SCSI_Out__REQ__BIE EQU CYREG_PRT4_BIE
+SCSI_Out__REQ__BIT_MASK EQU CYREG_PRT4_BIT_MASK
+SCSI_Out__REQ__BYP EQU CYREG_PRT4_BYP
+SCSI_Out__REQ__CTL EQU CYREG_PRT4_CTL
+SCSI_Out__REQ__DM0 EQU CYREG_PRT4_DM0
+SCSI_Out__REQ__DM1 EQU CYREG_PRT4_DM1
+SCSI_Out__REQ__DM2 EQU CYREG_PRT4_DM2
+SCSI_Out__REQ__DR EQU CYREG_PRT4_DR
+SCSI_Out__REQ__INP_DIS EQU CYREG_PRT4_INP_DIS
+SCSI_Out__REQ__INTTYPE EQU CYREG_PICU4_INTTYPE1
+SCSI_Out__REQ__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
+SCSI_Out__REQ__LCD_EN EQU CYREG_PRT4_LCD_EN
+SCSI_Out__REQ__MASK EQU 0x02
+SCSI_Out__REQ__PC EQU CYREG_PRT4_PC1
+SCSI_Out__REQ__PORT EQU 4
+SCSI_Out__REQ__PRT EQU CYREG_PRT4_PRT
+SCSI_Out__REQ__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
+SCSI_Out__REQ__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
+SCSI_Out__REQ__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
+SCSI_Out__REQ__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
+SCSI_Out__REQ__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
+SCSI_Out__REQ__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
+SCSI_Out__REQ__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
+SCSI_Out__REQ__PS EQU CYREG_PRT4_PS
+SCSI_Out__REQ__SHIFT EQU 1
+SCSI_Out__REQ__SLW EQU CYREG_PRT4_SLW
+SCSI_Out__RST__AG EQU CYREG_PRT0_AG
+SCSI_Out__RST__AMUX EQU CYREG_PRT0_AMUX
+SCSI_Out__RST__BIE EQU CYREG_PRT0_BIE
+SCSI_Out__RST__BIT_MASK EQU CYREG_PRT0_BIT_MASK
+SCSI_Out__RST__BYP EQU CYREG_PRT0_BYP
+SCSI_Out__RST__CTL EQU CYREG_PRT0_CTL
+SCSI_Out__RST__DM0 EQU CYREG_PRT0_DM0
+SCSI_Out__RST__DM1 EQU CYREG_PRT0_DM1
+SCSI_Out__RST__DM2 EQU CYREG_PRT0_DM2
+SCSI_Out__RST__DR EQU CYREG_PRT0_DR
+SCSI_Out__RST__INP_DIS EQU CYREG_PRT0_INP_DIS
+SCSI_Out__RST__INTTYPE EQU CYREG_PICU0_INTTYPE7
+SCSI_Out__RST__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
+SCSI_Out__RST__LCD_EN EQU CYREG_PRT0_LCD_EN
+SCSI_Out__RST__MASK EQU 0x80
+SCSI_Out__RST__PC EQU CYREG_PRT0_PC7
+SCSI_Out__RST__PORT EQU 0
+SCSI_Out__RST__PRT EQU CYREG_PRT0_PRT
+SCSI_Out__RST__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
+SCSI_Out__RST__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
+SCSI_Out__RST__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
+SCSI_Out__RST__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
+SCSI_Out__RST__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
+SCSI_Out__RST__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
+SCSI_Out__RST__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
+SCSI_Out__RST__PS EQU CYREG_PRT0_PS
+SCSI_Out__RST__SHIFT EQU 7
+SCSI_Out__RST__SLW EQU CYREG_PRT0_SLW
+SCSI_Out__SEL__AG EQU CYREG_PRT0_AG
+SCSI_Out__SEL__AMUX EQU CYREG_PRT0_AMUX
+SCSI_Out__SEL__BIE EQU CYREG_PRT0_BIE
+SCSI_Out__SEL__BIT_MASK EQU CYREG_PRT0_BIT_MASK
+SCSI_Out__SEL__BYP EQU CYREG_PRT0_BYP
+SCSI_Out__SEL__CTL EQU CYREG_PRT0_CTL
+SCSI_Out__SEL__DM0 EQU CYREG_PRT0_DM0
+SCSI_Out__SEL__DM1 EQU CYREG_PRT0_DM1
+SCSI_Out__SEL__DM2 EQU CYREG_PRT0_DM2
+SCSI_Out__SEL__DR EQU CYREG_PRT0_DR
+SCSI_Out__SEL__INP_DIS EQU CYREG_PRT0_INP_DIS
+SCSI_Out__SEL__INTTYPE EQU CYREG_PICU0_INTTYPE3
+SCSI_Out__SEL__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
+SCSI_Out__SEL__LCD_EN EQU CYREG_PRT0_LCD_EN
+SCSI_Out__SEL__MASK EQU 0x08
+SCSI_Out__SEL__PC EQU CYREG_PRT0_PC3
+SCSI_Out__SEL__PORT EQU 0
+SCSI_Out__SEL__PRT EQU CYREG_PRT0_PRT
+SCSI_Out__SEL__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
+SCSI_Out__SEL__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
+SCSI_Out__SEL__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
+SCSI_Out__SEL__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
+SCSI_Out__SEL__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
+SCSI_Out__SEL__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
+SCSI_Out__SEL__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
+SCSI_Out__SEL__PS EQU CYREG_PRT0_PS
+SCSI_Out__SEL__SHIFT EQU 3
+SCSI_Out__SEL__SLW EQU CYREG_PRT0_SLW
+SCSI_Out_Bits_Sync_ctrl_reg__0__MASK EQU 0x01
+SCSI_Out_Bits_Sync_ctrl_reg__0__POS EQU 0
+SCSI_Out_Bits_Sync_ctrl_reg__1__MASK EQU 0x02
+SCSI_Out_Bits_Sync_ctrl_reg__1__POS EQU 1
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB07_08_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB07_08_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB07_08_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB07_08_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB07_08_MSK
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB07_08_MSK
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB07_08_MSK
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB07_08_MSK
+SCSI_Out_Bits_Sync_ctrl_reg__2__MASK EQU 0x04
+SCSI_Out_Bits_Sync_ctrl_reg__2__POS EQU 2
+SCSI_Out_Bits_Sync_ctrl_reg__3__MASK EQU 0x08
+SCSI_Out_Bits_Sync_ctrl_reg__3__POS EQU 3
+SCSI_Out_Bits_Sync_ctrl_reg__4__MASK EQU 0x10
+SCSI_Out_Bits_Sync_ctrl_reg__4__POS EQU 4
+SCSI_Out_Bits_Sync_ctrl_reg__5__MASK EQU 0x20
+SCSI_Out_Bits_Sync_ctrl_reg__5__POS EQU 5
+SCSI_Out_Bits_Sync_ctrl_reg__6__MASK EQU 0x40
+SCSI_Out_Bits_Sync_ctrl_reg__6__POS EQU 6
+SCSI_Out_Bits_Sync_ctrl_reg__7__MASK EQU 0x80
+SCSI_Out_Bits_Sync_ctrl_reg__7__POS EQU 7
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB07_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB07_ST_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB07_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB07_ST_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__MASK EQU 0xFF
+SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL
+SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL
+SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB07_MSK
+SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01
+SCSI_Out_Ctl_Sync_ctrl_reg__0__POS EQU 0
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB11_12_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB11_12_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB11_12_MSK
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB11_12_MSK
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB11_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB11_ST_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB11_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB11_ST_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__MASK EQU 0x01
+SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
+SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
+SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB11_MSK
+SCSI_Out_DBx__0__AG EQU CYREG_PRT6_AG
+SCSI_Out_DBx__0__AMUX EQU CYREG_PRT6_AMUX
+SCSI_Out_DBx__0__BIE EQU CYREG_PRT6_BIE
+SCSI_Out_DBx__0__BIT_MASK EQU CYREG_PRT6_BIT_MASK
+SCSI_Out_DBx__0__BYP EQU CYREG_PRT6_BYP
+SCSI_Out_DBx__0__CTL EQU CYREG_PRT6_CTL
+SCSI_Out_DBx__0__DM0 EQU CYREG_PRT6_DM0
+SCSI_Out_DBx__0__DM1 EQU CYREG_PRT6_DM1
+SCSI_Out_DBx__0__DM2 EQU CYREG_PRT6_DM2
+SCSI_Out_DBx__0__DR EQU CYREG_PRT6_DR
+SCSI_Out_DBx__0__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_Out_DBx__0__INTTYPE EQU CYREG_PICU6_INTTYPE7
+SCSI_Out_DBx__0__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
+SCSI_Out_DBx__0__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_Out_DBx__0__MASK EQU 0x80
+SCSI_Out_DBx__0__PC EQU CYREG_PRT6_PC7
+SCSI_Out_DBx__0__PORT EQU 6
+SCSI_Out_DBx__0__PRT EQU CYREG_PRT6_PRT
+SCSI_Out_DBx__0__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
+SCSI_Out_DBx__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
+SCSI_Out_DBx__0__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
+SCSI_Out_DBx__0__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
+SCSI_Out_DBx__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
+SCSI_Out_DBx__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
+SCSI_Out_DBx__0__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
+SCSI_Out_DBx__0__PS EQU CYREG_PRT6_PS
+SCSI_Out_DBx__0__SHIFT EQU 7
+SCSI_Out_DBx__0__SLW EQU CYREG_PRT6_SLW
+SCSI_Out_DBx__1__AG EQU CYREG_PRT6_AG
+SCSI_Out_DBx__1__AMUX EQU CYREG_PRT6_AMUX
+SCSI_Out_DBx__1__BIE EQU CYREG_PRT6_BIE
+SCSI_Out_DBx__1__BIT_MASK EQU CYREG_PRT6_BIT_MASK
+SCSI_Out_DBx__1__BYP EQU CYREG_PRT6_BYP
+SCSI_Out_DBx__1__CTL EQU CYREG_PRT6_CTL
+SCSI_Out_DBx__1__DM0 EQU CYREG_PRT6_DM0
+SCSI_Out_DBx__1__DM1 EQU CYREG_PRT6_DM1
+SCSI_Out_DBx__1__DM2 EQU CYREG_PRT6_DM2
+SCSI_Out_DBx__1__DR EQU CYREG_PRT6_DR
+SCSI_Out_DBx__1__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_Out_DBx__1__INTTYPE EQU CYREG_PICU6_INTTYPE5
+SCSI_Out_DBx__1__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
+SCSI_Out_DBx__1__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_Out_DBx__1__MASK EQU 0x20
+SCSI_Out_DBx__1__PC EQU CYREG_PRT6_PC5
+SCSI_Out_DBx__1__PORT EQU 6
+SCSI_Out_DBx__1__PRT EQU CYREG_PRT6_PRT
+SCSI_Out_DBx__1__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
+SCSI_Out_DBx__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
+SCSI_Out_DBx__1__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
+SCSI_Out_DBx__1__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
+SCSI_Out_DBx__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
+SCSI_Out_DBx__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
+SCSI_Out_DBx__1__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
+SCSI_Out_DBx__1__PS EQU CYREG_PRT6_PS
+SCSI_Out_DBx__1__SHIFT EQU 5
+SCSI_Out_DBx__1__SLW EQU CYREG_PRT6_SLW
+SCSI_Out_DBx__2__AG EQU CYREG_PRT12_AG
+SCSI_Out_DBx__2__BIE EQU CYREG_PRT12_BIE
+SCSI_Out_DBx__2__BIT_MASK EQU CYREG_PRT12_BIT_MASK
+SCSI_Out_DBx__2__BYP EQU CYREG_PRT12_BYP
+SCSI_Out_DBx__2__DM0 EQU CYREG_PRT12_DM0
+SCSI_Out_DBx__2__DM1 EQU CYREG_PRT12_DM1
+SCSI_Out_DBx__2__DM2 EQU CYREG_PRT12_DM2
+SCSI_Out_DBx__2__DR EQU CYREG_PRT12_DR
+SCSI_Out_DBx__2__INP_DIS EQU CYREG_PRT12_INP_DIS
+SCSI_Out_DBx__2__INTTYPE EQU CYREG_PICU12_INTTYPE5
+SCSI_Out_DBx__2__MASK EQU 0x20
+SCSI_Out_DBx__2__PC EQU CYREG_PRT12_PC5
+SCSI_Out_DBx__2__PORT EQU 12
+SCSI_Out_DBx__2__PRT EQU CYREG_PRT12_PRT
+SCSI_Out_DBx__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN
+SCSI_Out_DBx__2__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0
+SCSI_Out_DBx__2__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1
+SCSI_Out_DBx__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0
+SCSI_Out_DBx__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1
+SCSI_Out_DBx__2__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT
+SCSI_Out_DBx__2__PS EQU CYREG_PRT12_PS
+SCSI_Out_DBx__2__SHIFT EQU 5
+SCSI_Out_DBx__2__SIO_CFG EQU CYREG_PRT12_SIO_CFG
+SCSI_Out_DBx__2__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF
+SCSI_Out_DBx__2__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN
+SCSI_Out_DBx__2__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ
+SCSI_Out_DBx__2__SLW EQU CYREG_PRT12_SLW
+SCSI_Out_DBx__3__AG EQU CYREG_PRT2_AG
+SCSI_Out_DBx__3__AMUX EQU CYREG_PRT2_AMUX
+SCSI_Out_DBx__3__BIE EQU CYREG_PRT2_BIE
+SCSI_Out_DBx__3__BIT_MASK EQU CYREG_PRT2_BIT_MASK
+SCSI_Out_DBx__3__BYP EQU CYREG_PRT2_BYP
+SCSI_Out_DBx__3__CTL EQU CYREG_PRT2_CTL
+SCSI_Out_DBx__3__DM0 EQU CYREG_PRT2_DM0
+SCSI_Out_DBx__3__DM1 EQU CYREG_PRT2_DM1
+SCSI_Out_DBx__3__DM2 EQU CYREG_PRT2_DM2
+SCSI_Out_DBx__3__DR EQU CYREG_PRT2_DR
+SCSI_Out_DBx__3__INP_DIS EQU CYREG_PRT2_INP_DIS
+SCSI_Out_DBx__3__INTTYPE EQU CYREG_PICU2_INTTYPE7
+SCSI_Out_DBx__3__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
+SCSI_Out_DBx__3__LCD_EN EQU CYREG_PRT2_LCD_EN
+SCSI_Out_DBx__3__MASK EQU 0x80
+SCSI_Out_DBx__3__PC EQU CYREG_PRT2_PC7
+SCSI_Out_DBx__3__PORT EQU 2
+SCSI_Out_DBx__3__PRT EQU CYREG_PRT2_PRT
+SCSI_Out_DBx__3__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
+SCSI_Out_DBx__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
+SCSI_Out_DBx__3__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
+SCSI_Out_DBx__3__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
+SCSI_Out_DBx__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
+SCSI_Out_DBx__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
+SCSI_Out_DBx__3__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
+SCSI_Out_DBx__3__PS EQU CYREG_PRT2_PS
+SCSI_Out_DBx__3__SHIFT EQU 7
+SCSI_Out_DBx__3__SLW EQU CYREG_PRT2_SLW
+SCSI_Out_DBx__4__AG EQU CYREG_PRT2_AG
+SCSI_Out_DBx__4__AMUX EQU CYREG_PRT2_AMUX
+SCSI_Out_DBx__4__BIE EQU CYREG_PRT2_BIE
+SCSI_Out_DBx__4__BIT_MASK EQU CYREG_PRT2_BIT_MASK
+SCSI_Out_DBx__4__BYP EQU CYREG_PRT2_BYP
+SCSI_Out_DBx__4__CTL EQU CYREG_PRT2_CTL
+SCSI_Out_DBx__4__DM0 EQU CYREG_PRT2_DM0
+SCSI_Out_DBx__4__DM1 EQU CYREG_PRT2_DM1
+SCSI_Out_DBx__4__DM2 EQU CYREG_PRT2_DM2
+SCSI_Out_DBx__4__DR EQU CYREG_PRT2_DR
+SCSI_Out_DBx__4__INP_DIS EQU CYREG_PRT2_INP_DIS
+SCSI_Out_DBx__4__INTTYPE EQU CYREG_PICU2_INTTYPE5
+SCSI_Out_DBx__4__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
+SCSI_Out_DBx__4__LCD_EN EQU CYREG_PRT2_LCD_EN
+SCSI_Out_DBx__4__MASK EQU 0x20
+SCSI_Out_DBx__4__PC EQU CYREG_PRT2_PC5
+SCSI_Out_DBx__4__PORT EQU 2
+SCSI_Out_DBx__4__PRT EQU CYREG_PRT2_PRT
+SCSI_Out_DBx__4__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
+SCSI_Out_DBx__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
+SCSI_Out_DBx__4__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
+SCSI_Out_DBx__4__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
+SCSI_Out_DBx__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
+SCSI_Out_DBx__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
+SCSI_Out_DBx__4__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
+SCSI_Out_DBx__4__PS EQU CYREG_PRT2_PS
+SCSI_Out_DBx__4__SHIFT EQU 5
+SCSI_Out_DBx__4__SLW EQU CYREG_PRT2_SLW
+SCSI_Out_DBx__5__AG EQU CYREG_PRT2_AG
+SCSI_Out_DBx__5__AMUX EQU CYREG_PRT2_AMUX
+SCSI_Out_DBx__5__BIE EQU CYREG_PRT2_BIE
+SCSI_Out_DBx__5__BIT_MASK EQU CYREG_PRT2_BIT_MASK
+SCSI_Out_DBx__5__BYP EQU CYREG_PRT2_BYP
+SCSI_Out_DBx__5__CTL EQU CYREG_PRT2_CTL
+SCSI_Out_DBx__5__DM0 EQU CYREG_PRT2_DM0
+SCSI_Out_DBx__5__DM1 EQU CYREG_PRT2_DM1
+SCSI_Out_DBx__5__DM2 EQU CYREG_PRT2_DM2
+SCSI_Out_DBx__5__DR EQU CYREG_PRT2_DR
+SCSI_Out_DBx__5__INP_DIS EQU CYREG_PRT2_INP_DIS
+SCSI_Out_DBx__5__INTTYPE EQU CYREG_PICU2_INTTYPE3
+SCSI_Out_DBx__5__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
+SCSI_Out_DBx__5__LCD_EN EQU CYREG_PRT2_LCD_EN
+SCSI_Out_DBx__5__MASK EQU 0x08
+SCSI_Out_DBx__5__PC EQU CYREG_PRT2_PC3
+SCSI_Out_DBx__5__PORT EQU 2
+SCSI_Out_DBx__5__PRT EQU CYREG_PRT2_PRT
+SCSI_Out_DBx__5__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
+SCSI_Out_DBx__5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
+SCSI_Out_DBx__5__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
+SCSI_Out_DBx__5__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
+SCSI_Out_DBx__5__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
+SCSI_Out_DBx__5__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
+SCSI_Out_DBx__5__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
+SCSI_Out_DBx__5__PS EQU CYREG_PRT2_PS
+SCSI_Out_DBx__5__SHIFT EQU 3
+SCSI_Out_DBx__5__SLW EQU CYREG_PRT2_SLW
+SCSI_Out_DBx__6__AG EQU CYREG_PRT2_AG
+SCSI_Out_DBx__6__AMUX EQU CYREG_PRT2_AMUX
+SCSI_Out_DBx__6__BIE EQU CYREG_PRT2_BIE
+SCSI_Out_DBx__6__BIT_MASK EQU CYREG_PRT2_BIT_MASK
+SCSI_Out_DBx__6__BYP EQU CYREG_PRT2_BYP
+SCSI_Out_DBx__6__CTL EQU CYREG_PRT2_CTL
+SCSI_Out_DBx__6__DM0 EQU CYREG_PRT2_DM0
+SCSI_Out_DBx__6__DM1 EQU CYREG_PRT2_DM1
+SCSI_Out_DBx__6__DM2 EQU CYREG_PRT2_DM2
+SCSI_Out_DBx__6__DR EQU CYREG_PRT2_DR
+SCSI_Out_DBx__6__INP_DIS EQU CYREG_PRT2_INP_DIS
+SCSI_Out_DBx__6__INTTYPE EQU CYREG_PICU2_INTTYPE1
+SCSI_Out_DBx__6__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
+SCSI_Out_DBx__6__LCD_EN EQU CYREG_PRT2_LCD_EN
+SCSI_Out_DBx__6__MASK EQU 0x02
+SCSI_Out_DBx__6__PC EQU CYREG_PRT2_PC1
+SCSI_Out_DBx__6__PORT EQU 2
+SCSI_Out_DBx__6__PRT EQU CYREG_PRT2_PRT
+SCSI_Out_DBx__6__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
+SCSI_Out_DBx__6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
+SCSI_Out_DBx__6__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
+SCSI_Out_DBx__6__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
+SCSI_Out_DBx__6__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
+SCSI_Out_DBx__6__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
+SCSI_Out_DBx__6__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
+SCSI_Out_DBx__6__PS EQU CYREG_PRT2_PS
+SCSI_Out_DBx__6__SHIFT EQU 1
+SCSI_Out_DBx__6__SLW EQU CYREG_PRT2_SLW
+SCSI_Out_DBx__7__AG EQU CYREG_PRT15_AG
+SCSI_Out_DBx__7__AMUX EQU CYREG_PRT15_AMUX
+SCSI_Out_DBx__7__BIE EQU CYREG_PRT15_BIE
+SCSI_Out_DBx__7__BIT_MASK EQU CYREG_PRT15_BIT_MASK
+SCSI_Out_DBx__7__BYP EQU CYREG_PRT15_BYP
+SCSI_Out_DBx__7__CTL EQU CYREG_PRT15_CTL
+SCSI_Out_DBx__7__DM0 EQU CYREG_PRT15_DM0
+SCSI_Out_DBx__7__DM1 EQU CYREG_PRT15_DM1
+SCSI_Out_DBx__7__DM2 EQU CYREG_PRT15_DM2
+SCSI_Out_DBx__7__DR EQU CYREG_PRT15_DR
+SCSI_Out_DBx__7__INP_DIS EQU CYREG_PRT15_INP_DIS
+SCSI_Out_DBx__7__INTTYPE EQU CYREG_PICU15_INTTYPE5
+SCSI_Out_DBx__7__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG
+SCSI_Out_DBx__7__LCD_EN EQU CYREG_PRT15_LCD_EN
+SCSI_Out_DBx__7__MASK EQU 0x20
+SCSI_Out_DBx__7__PC EQU CYREG_IO_PC_PRT15_PC5
+SCSI_Out_DBx__7__PORT EQU 15
+SCSI_Out_DBx__7__PRT EQU CYREG_PRT15_PRT
+SCSI_Out_DBx__7__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL
+SCSI_Out_DBx__7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN
+SCSI_Out_DBx__7__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0
+SCSI_Out_DBx__7__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1
+SCSI_Out_DBx__7__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0
+SCSI_Out_DBx__7__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1
+SCSI_Out_DBx__7__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT
+SCSI_Out_DBx__7__PS EQU CYREG_PRT15_PS
+SCSI_Out_DBx__7__SHIFT EQU 5
+SCSI_Out_DBx__7__SLW EQU CYREG_PRT15_SLW
+SCSI_Out_DBx__DB0__AG EQU CYREG_PRT6_AG
+SCSI_Out_DBx__DB0__AMUX EQU CYREG_PRT6_AMUX
+SCSI_Out_DBx__DB0__BIE EQU CYREG_PRT6_BIE
+SCSI_Out_DBx__DB0__BIT_MASK EQU CYREG_PRT6_BIT_MASK
+SCSI_Out_DBx__DB0__BYP EQU CYREG_PRT6_BYP
+SCSI_Out_DBx__DB0__CTL EQU CYREG_PRT6_CTL
+SCSI_Out_DBx__DB0__DM0 EQU CYREG_PRT6_DM0
+SCSI_Out_DBx__DB0__DM1 EQU CYREG_PRT6_DM1
+SCSI_Out_DBx__DB0__DM2 EQU CYREG_PRT6_DM2
+SCSI_Out_DBx__DB0__DR EQU CYREG_PRT6_DR
+SCSI_Out_DBx__DB0__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_Out_DBx__DB0__INTTYPE EQU CYREG_PICU6_INTTYPE7
+SCSI_Out_DBx__DB0__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
+SCSI_Out_DBx__DB0__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_Out_DBx__DB0__MASK EQU 0x80
+SCSI_Out_DBx__DB0__PC EQU CYREG_PRT6_PC7
+SCSI_Out_DBx__DB0__PORT EQU 6
+SCSI_Out_DBx__DB0__PRT EQU CYREG_PRT6_PRT
+SCSI_Out_DBx__DB0__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
+SCSI_Out_DBx__DB0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
+SCSI_Out_DBx__DB0__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
+SCSI_Out_DBx__DB0__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
+SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
+SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
+SCSI_Out_DBx__DB0__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
+SCSI_Out_DBx__DB0__PS EQU CYREG_PRT6_PS
+SCSI_Out_DBx__DB0__SHIFT EQU 7
+SCSI_Out_DBx__DB0__SLW EQU CYREG_PRT6_SLW
+SCSI_Out_DBx__DB1__AG EQU CYREG_PRT6_AG
+SCSI_Out_DBx__DB1__AMUX EQU CYREG_PRT6_AMUX
+SCSI_Out_DBx__DB1__BIE EQU CYREG_PRT6_BIE
+SCSI_Out_DBx__DB1__BIT_MASK EQU CYREG_PRT6_BIT_MASK
+SCSI_Out_DBx__DB1__BYP EQU CYREG_PRT6_BYP
+SCSI_Out_DBx__DB1__CTL EQU CYREG_PRT6_CTL
+SCSI_Out_DBx__DB1__DM0 EQU CYREG_PRT6_DM0
+SCSI_Out_DBx__DB1__DM1 EQU CYREG_PRT6_DM1
+SCSI_Out_DBx__DB1__DM2 EQU CYREG_PRT6_DM2
+SCSI_Out_DBx__DB1__DR EQU CYREG_PRT6_DR
+SCSI_Out_DBx__DB1__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_Out_DBx__DB1__INTTYPE EQU CYREG_PICU6_INTTYPE5
+SCSI_Out_DBx__DB1__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
+SCSI_Out_DBx__DB1__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_Out_DBx__DB1__MASK EQU 0x20
+SCSI_Out_DBx__DB1__PC EQU CYREG_PRT6_PC5
+SCSI_Out_DBx__DB1__PORT EQU 6
+SCSI_Out_DBx__DB1__PRT EQU CYREG_PRT6_PRT
+SCSI_Out_DBx__DB1__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
+SCSI_Out_DBx__DB1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
+SCSI_Out_DBx__DB1__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
+SCSI_Out_DBx__DB1__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
+SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
+SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
+SCSI_Out_DBx__DB1__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
+SCSI_Out_DBx__DB1__PS EQU CYREG_PRT6_PS
+SCSI_Out_DBx__DB1__SHIFT EQU 5
+SCSI_Out_DBx__DB1__SLW EQU CYREG_PRT6_SLW
+SCSI_Out_DBx__DB2__AG EQU CYREG_PRT12_AG
+SCSI_Out_DBx__DB2__BIE EQU CYREG_PRT12_BIE
+SCSI_Out_DBx__DB2__BIT_MASK EQU CYREG_PRT12_BIT_MASK
+SCSI_Out_DBx__DB2__BYP EQU CYREG_PRT12_BYP
+SCSI_Out_DBx__DB2__DM0 EQU CYREG_PRT12_DM0
+SCSI_Out_DBx__DB2__DM1 EQU CYREG_PRT12_DM1
+SCSI_Out_DBx__DB2__DM2 EQU CYREG_PRT12_DM2
+SCSI_Out_DBx__DB2__DR EQU CYREG_PRT12_DR
+SCSI_Out_DBx__DB2__INP_DIS EQU CYREG_PRT12_INP_DIS
+SCSI_Out_DBx__DB2__INTTYPE EQU CYREG_PICU12_INTTYPE5
+SCSI_Out_DBx__DB2__MASK EQU 0x20
+SCSI_Out_DBx__DB2__PC EQU CYREG_PRT12_PC5
+SCSI_Out_DBx__DB2__PORT EQU 12
+SCSI_Out_DBx__DB2__PRT EQU CYREG_PRT12_PRT
+SCSI_Out_DBx__DB2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN
+SCSI_Out_DBx__DB2__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0
+SCSI_Out_DBx__DB2__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1
+SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0
+SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1
+SCSI_Out_DBx__DB2__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT
+SCSI_Out_DBx__DB2__PS EQU CYREG_PRT12_PS
+SCSI_Out_DBx__DB2__SHIFT EQU 5
+SCSI_Out_DBx__DB2__SIO_CFG EQU CYREG_PRT12_SIO_CFG
+SCSI_Out_DBx__DB2__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF
+SCSI_Out_DBx__DB2__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN
+SCSI_Out_DBx__DB2__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ
+SCSI_Out_DBx__DB2__SLW EQU CYREG_PRT12_SLW
+SCSI_Out_DBx__DB3__AG EQU CYREG_PRT2_AG
+SCSI_Out_DBx__DB3__AMUX EQU CYREG_PRT2_AMUX
+SCSI_Out_DBx__DB3__BIE EQU CYREG_PRT2_BIE
+SCSI_Out_DBx__DB3__BIT_MASK EQU CYREG_PRT2_BIT_MASK
+SCSI_Out_DBx__DB3__BYP EQU CYREG_PRT2_BYP
+SCSI_Out_DBx__DB3__CTL EQU CYREG_PRT2_CTL
+SCSI_Out_DBx__DB3__DM0 EQU CYREG_PRT2_DM0
+SCSI_Out_DBx__DB3__DM1 EQU CYREG_PRT2_DM1
+SCSI_Out_DBx__DB3__DM2 EQU CYREG_PRT2_DM2
+SCSI_Out_DBx__DB3__DR EQU CYREG_PRT2_DR
+SCSI_Out_DBx__DB3__INP_DIS EQU CYREG_PRT2_INP_DIS
+SCSI_Out_DBx__DB3__INTTYPE EQU CYREG_PICU2_INTTYPE7
+SCSI_Out_DBx__DB3__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
+SCSI_Out_DBx__DB3__LCD_EN EQU CYREG_PRT2_LCD_EN
+SCSI_Out_DBx__DB3__MASK EQU 0x80
+SCSI_Out_DBx__DB3__PC EQU CYREG_PRT2_PC7
+SCSI_Out_DBx__DB3__PORT EQU 2
+SCSI_Out_DBx__DB3__PRT EQU CYREG_PRT2_PRT
+SCSI_Out_DBx__DB3__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
+SCSI_Out_DBx__DB3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
+SCSI_Out_DBx__DB3__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
+SCSI_Out_DBx__DB3__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
+SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
+SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
+SCSI_Out_DBx__DB3__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
+SCSI_Out_DBx__DB3__PS EQU CYREG_PRT2_PS
+SCSI_Out_DBx__DB3__SHIFT EQU 7
+SCSI_Out_DBx__DB3__SLW EQU CYREG_PRT2_SLW
+SCSI_Out_DBx__DB4__AG EQU CYREG_PRT2_AG
+SCSI_Out_DBx__DB4__AMUX EQU CYREG_PRT2_AMUX
+SCSI_Out_DBx__DB4__BIE EQU CYREG_PRT2_BIE
+SCSI_Out_DBx__DB4__BIT_MASK EQU CYREG_PRT2_BIT_MASK
+SCSI_Out_DBx__DB4__BYP EQU CYREG_PRT2_BYP
+SCSI_Out_DBx__DB4__CTL EQU CYREG_PRT2_CTL
+SCSI_Out_DBx__DB4__DM0 EQU CYREG_PRT2_DM0
+SCSI_Out_DBx__DB4__DM1 EQU CYREG_PRT2_DM1
+SCSI_Out_DBx__DB4__DM2 EQU CYREG_PRT2_DM2
+SCSI_Out_DBx__DB4__DR EQU CYREG_PRT2_DR
+SCSI_Out_DBx__DB4__INP_DIS EQU CYREG_PRT2_INP_DIS
+SCSI_Out_DBx__DB4__INTTYPE EQU CYREG_PICU2_INTTYPE5
+SCSI_Out_DBx__DB4__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
+SCSI_Out_DBx__DB4__LCD_EN EQU CYREG_PRT2_LCD_EN
+SCSI_Out_DBx__DB4__MASK EQU 0x20
+SCSI_Out_DBx__DB4__PC EQU CYREG_PRT2_PC5
+SCSI_Out_DBx__DB4__PORT EQU 2
+SCSI_Out_DBx__DB4__PRT EQU CYREG_PRT2_PRT
+SCSI_Out_DBx__DB4__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
+SCSI_Out_DBx__DB4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
+SCSI_Out_DBx__DB4__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
+SCSI_Out_DBx__DB4__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
+SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
+SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
+SCSI_Out_DBx__DB4__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
+SCSI_Out_DBx__DB4__PS EQU CYREG_PRT2_PS
+SCSI_Out_DBx__DB4__SHIFT EQU 5
+SCSI_Out_DBx__DB4__SLW EQU CYREG_PRT2_SLW
+SCSI_Out_DBx__DB5__AG EQU CYREG_PRT2_AG
+SCSI_Out_DBx__DB5__AMUX EQU CYREG_PRT2_AMUX
+SCSI_Out_DBx__DB5__BIE EQU CYREG_PRT2_BIE
+SCSI_Out_DBx__DB5__BIT_MASK EQU CYREG_PRT2_BIT_MASK
+SCSI_Out_DBx__DB5__BYP EQU CYREG_PRT2_BYP
+SCSI_Out_DBx__DB5__CTL EQU CYREG_PRT2_CTL
+SCSI_Out_DBx__DB5__DM0 EQU CYREG_PRT2_DM0
+SCSI_Out_DBx__DB5__DM1 EQU CYREG_PRT2_DM1
+SCSI_Out_DBx__DB5__DM2 EQU CYREG_PRT2_DM2
+SCSI_Out_DBx__DB5__DR EQU CYREG_PRT2_DR
+SCSI_Out_DBx__DB5__INP_DIS EQU CYREG_PRT2_INP_DIS
+SCSI_Out_DBx__DB5__INTTYPE EQU CYREG_PICU2_INTTYPE3
+SCSI_Out_DBx__DB5__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
+SCSI_Out_DBx__DB5__LCD_EN EQU CYREG_PRT2_LCD_EN
+SCSI_Out_DBx__DB5__MASK EQU 0x08
+SCSI_Out_DBx__DB5__PC EQU CYREG_PRT2_PC3
+SCSI_Out_DBx__DB5__PORT EQU 2
+SCSI_Out_DBx__DB5__PRT EQU CYREG_PRT2_PRT
+SCSI_Out_DBx__DB5__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
+SCSI_Out_DBx__DB5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
+SCSI_Out_DBx__DB5__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
+SCSI_Out_DBx__DB5__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
+SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
+SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
+SCSI_Out_DBx__DB5__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
+SCSI_Out_DBx__DB5__PS EQU CYREG_PRT2_PS
+SCSI_Out_DBx__DB5__SHIFT EQU 3
+SCSI_Out_DBx__DB5__SLW EQU CYREG_PRT2_SLW
+SCSI_Out_DBx__DB6__AG EQU CYREG_PRT2_AG
+SCSI_Out_DBx__DB6__AMUX EQU CYREG_PRT2_AMUX
+SCSI_Out_DBx__DB6__BIE EQU CYREG_PRT2_BIE
+SCSI_Out_DBx__DB6__BIT_MASK EQU CYREG_PRT2_BIT_MASK
+SCSI_Out_DBx__DB6__BYP EQU CYREG_PRT2_BYP
+SCSI_Out_DBx__DB6__CTL EQU CYREG_PRT2_CTL
+SCSI_Out_DBx__DB6__DM0 EQU CYREG_PRT2_DM0
+SCSI_Out_DBx__DB6__DM1 EQU CYREG_PRT2_DM1
+SCSI_Out_DBx__DB6__DM2 EQU CYREG_PRT2_DM2
+SCSI_Out_DBx__DB6__DR EQU CYREG_PRT2_DR
+SCSI_Out_DBx__DB6__INP_DIS EQU CYREG_PRT2_INP_DIS
+SCSI_Out_DBx__DB6__INTTYPE EQU CYREG_PICU2_INTTYPE1
+SCSI_Out_DBx__DB6__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
+SCSI_Out_DBx__DB6__LCD_EN EQU CYREG_PRT2_LCD_EN
+SCSI_Out_DBx__DB6__MASK EQU 0x02
+SCSI_Out_DBx__DB6__PC EQU CYREG_PRT2_PC1
+SCSI_Out_DBx__DB6__PORT EQU 2
+SCSI_Out_DBx__DB6__PRT EQU CYREG_PRT2_PRT
+SCSI_Out_DBx__DB6__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
+SCSI_Out_DBx__DB6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
+SCSI_Out_DBx__DB6__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
+SCSI_Out_DBx__DB6__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
+SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
+SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
+SCSI_Out_DBx__DB6__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
+SCSI_Out_DBx__DB6__PS EQU CYREG_PRT2_PS
+SCSI_Out_DBx__DB6__SHIFT EQU 1
+SCSI_Out_DBx__DB6__SLW EQU CYREG_PRT2_SLW
+SCSI_Out_DBx__DB7__AG EQU CYREG_PRT15_AG
+SCSI_Out_DBx__DB7__AMUX EQU CYREG_PRT15_AMUX
+SCSI_Out_DBx__DB7__BIE EQU CYREG_PRT15_BIE
+SCSI_Out_DBx__DB7__BIT_MASK EQU CYREG_PRT15_BIT_MASK
+SCSI_Out_DBx__DB7__BYP EQU CYREG_PRT15_BYP
+SCSI_Out_DBx__DB7__CTL EQU CYREG_PRT15_CTL
+SCSI_Out_DBx__DB7__DM0 EQU CYREG_PRT15_DM0
+SCSI_Out_DBx__DB7__DM1 EQU CYREG_PRT15_DM1
+SCSI_Out_DBx__DB7__DM2 EQU CYREG_PRT15_DM2
+SCSI_Out_DBx__DB7__DR EQU CYREG_PRT15_DR
+SCSI_Out_DBx__DB7__INP_DIS EQU CYREG_PRT15_INP_DIS
+SCSI_Out_DBx__DB7__INTTYPE EQU CYREG_PICU15_INTTYPE5
+SCSI_Out_DBx__DB7__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG
+SCSI_Out_DBx__DB7__LCD_EN EQU CYREG_PRT15_LCD_EN
+SCSI_Out_DBx__DB7__MASK EQU 0x20
+SCSI_Out_DBx__DB7__PC EQU CYREG_IO_PC_PRT15_PC5
+SCSI_Out_DBx__DB7__PORT EQU 15
+SCSI_Out_DBx__DB7__PRT EQU CYREG_PRT15_PRT
+SCSI_Out_DBx__DB7__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL
+SCSI_Out_DBx__DB7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN
+SCSI_Out_DBx__DB7__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0
+SCSI_Out_DBx__DB7__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1
+SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0
+SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1
+SCSI_Out_DBx__DB7__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT
+SCSI_Out_DBx__DB7__PS EQU CYREG_PRT15_PS
+SCSI_Out_DBx__DB7__SHIFT EQU 5
+SCSI_Out_DBx__DB7__SLW EQU CYREG_PRT15_SLW
+
+; SCSI_Parity_Error
+SCSI_Parity_Error_sts_sts_reg__0__MASK EQU 0x01
+SCSI_Parity_Error_sts_sts_reg__0__POS EQU 0
+SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL
+SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB02_03_ST
+SCSI_Parity_Error_sts_sts_reg__MASK EQU 0x01
+SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB02_MSK
+SCSI_Parity_Error_sts_sts_reg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL
+SCSI_Parity_Error_sts_sts_reg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL
+SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL
+SCSI_Parity_Error_sts_sts_reg__STATUS_CNT_REG EQU CYREG_B0_UDB02_ST_CTL
+SCSI_Parity_Error_sts_sts_reg__STATUS_CONTROL_REG EQU CYREG_B0_UDB02_ST_CTL
+SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB02_ST
+
+; SCSI_RST_ISR
+SCSI_RST_ISR__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
+SCSI_RST_ISR__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
+SCSI_RST_ISR__INTC_MASK EQU 0x02
+SCSI_RST_ISR__INTC_NUMBER EQU 1
+SCSI_RST_ISR__INTC_PRIOR_NUM EQU 7
+SCSI_RST_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_1
+SCSI_RST_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
+SCSI_RST_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
+
+; SCSI_RX_DMA
+SCSI_RX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0
+SCSI_RX_DMA__DRQ_NUMBER EQU 0
+SCSI_RX_DMA__NUMBEROF_TDS EQU 0
+SCSI_RX_DMA__PRIORITY EQU 2
+SCSI_RX_DMA__TERMIN_EN EQU 0
+SCSI_RX_DMA__TERMIN_SEL EQU 0
+SCSI_RX_DMA__TERMOUT0_EN EQU 1
+SCSI_RX_DMA__TERMOUT0_SEL EQU 0
+SCSI_RX_DMA__TERMOUT1_EN EQU 0
+SCSI_RX_DMA__TERMOUT1_SEL EQU 0
+SCSI_RX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
+SCSI_RX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
+SCSI_RX_DMA_COMPLETE__INTC_MASK EQU 0x04
+SCSI_RX_DMA_COMPLETE__INTC_NUMBER EQU 2
+SCSI_RX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7
+SCSI_RX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_2
+SCSI_RX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
+SCSI_RX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
+
+; SCSI_SEL_ISR
+SCSI_SEL_ISR__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
+SCSI_SEL_ISR__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
+SCSI_SEL_ISR__INTC_MASK EQU 0x08
+SCSI_SEL_ISR__INTC_NUMBER EQU 3
+SCSI_SEL_ISR__INTC_PRIOR_NUM EQU 7
+SCSI_SEL_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_3
+SCSI_SEL_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
+SCSI_SEL_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
+
+; SCSI_TX_DMA
+SCSI_TX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0
+SCSI_TX_DMA__DRQ_NUMBER EQU 1
+SCSI_TX_DMA__NUMBEROF_TDS EQU 0
+SCSI_TX_DMA__PRIORITY EQU 2
+SCSI_TX_DMA__TERMIN_EN EQU 0
+SCSI_TX_DMA__TERMIN_SEL EQU 0
+SCSI_TX_DMA__TERMOUT0_EN EQU 1
+SCSI_TX_DMA__TERMOUT0_SEL EQU 1
+SCSI_TX_DMA__TERMOUT1_EN EQU 0
+SCSI_TX_DMA__TERMOUT1_SEL EQU 0
+SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
+SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
+SCSI_TX_DMA_COMPLETE__INTC_MASK EQU 0x10
+SCSI_TX_DMA_COMPLETE__INTC_NUMBER EQU 4
+SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7
+SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_4
+SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
+SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
+
+; SDCard_BSPIM
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB04_05_CTL
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB04_05_CTL
+SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB04_05_CTL
+SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB04_05_CTL
+SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB04_05_MSK
+SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB04_05_MSK
+SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB04_05_MSK
+SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB04_05_MSK
+SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL
+SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB04_CTL
+SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB04_ST_CTL
+SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB04_CTL
+SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB04_ST_CTL
+SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL
+SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL
+SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB04_MSK
+SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL
+SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB04_05_ST
+SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB04_MSK
+SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL
+SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL
+SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL
+SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB04_ST_CTL
+SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB04_ST_CTL
+SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB04_ST
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB07_08_ST
+SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10
+SDCard_BSPIM_RxStsReg__4__POS EQU 4
+SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20
+SDCard_BSPIM_RxStsReg__5__POS EQU 5
+SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40
+SDCard_BSPIM_RxStsReg__6__POS EQU 6
+SDCard_BSPIM_RxStsReg__MASK EQU 0x70
+SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B0_UDB07_MSK
+SDCard_BSPIM_RxStsReg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL
+SDCard_BSPIM_RxStsReg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL
+SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL
+SDCard_BSPIM_RxStsReg__STATUS_CNT_REG EQU CYREG_B0_UDB07_ST_CTL
+SDCard_BSPIM_RxStsReg__STATUS_CONTROL_REG EQU CYREG_B0_UDB07_ST_CTL
+SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B0_UDB07_ST
+SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB04_05_A0
+SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB04_05_A1
+SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B1_UDB04_05_D0
+SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B1_UDB04_05_D1
+SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL
+SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B1_UDB04_05_F0
+SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B1_UDB04_05_F1
+SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B1_UDB04_A0_A1
+SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B1_UDB04_A0
+SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B1_UDB04_A1
+SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B1_UDB04_D0_D1
+SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B1_UDB04_D0
+SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B1_UDB04_D1
+SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL
+SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B1_UDB04_F0_F1
+SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B1_UDB04_F0
+SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B1_UDB04_F1
+SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL
+SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL
+SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01
+SDCard_BSPIM_TxStsReg__0__POS EQU 0
+SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02
+SDCard_BSPIM_TxStsReg__1__POS EQU 1
+SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL
+SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST
+SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04
+SDCard_BSPIM_TxStsReg__2__POS EQU 2
+SDCard_BSPIM_TxStsReg__3__MASK EQU 0x08
+SDCard_BSPIM_TxStsReg__3__POS EQU 3
+SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10
+SDCard_BSPIM_TxStsReg__4__POS EQU 4
+SDCard_BSPIM_TxStsReg__MASK EQU 0x1F
+SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB07_MSK
+SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL
+SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB07_ST
+
+; SD_CS
+SD_CS__0__INTTYPE EQU CYREG_PICU3_INTTYPE5
+SD_CS__0__MASK EQU 0x20
+SD_CS__0__PC EQU CYREG_PRT3_PC5
+SD_CS__0__PORT EQU 3
+SD_CS__0__SHIFT EQU 5
+SD_CS__AG EQU CYREG_PRT3_AG
+SD_CS__AMUX EQU CYREG_PRT3_AMUX
+SD_CS__BIE EQU CYREG_PRT3_BIE
+SD_CS__BIT_MASK EQU CYREG_PRT3_BIT_MASK
+SD_CS__BYP EQU CYREG_PRT3_BYP
+SD_CS__CTL EQU CYREG_PRT3_CTL
+SD_CS__DM0 EQU CYREG_PRT3_DM0
+SD_CS__DM1 EQU CYREG_PRT3_DM1
+SD_CS__DM2 EQU CYREG_PRT3_DM2
+SD_CS__DR EQU CYREG_PRT3_DR
+SD_CS__INP_DIS EQU CYREG_PRT3_INP_DIS
+SD_CS__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE
+SD_CS__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG
+SD_CS__LCD_EN EQU CYREG_PRT3_LCD_EN
+SD_CS__MASK EQU 0x20
+SD_CS__PORT EQU 3
+SD_CS__PRT EQU CYREG_PRT3_PRT
+SD_CS__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL
+SD_CS__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN
+SD_CS__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0
+SD_CS__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1
+SD_CS__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0
+SD_CS__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1
+SD_CS__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT
+SD_CS__PS EQU CYREG_PRT3_PS
+SD_CS__SHIFT EQU 5
+SD_CS__SLW EQU CYREG_PRT3_SLW
+
+; SD_Data_Clk
+SD_Data_Clk__CFG0 EQU CYREG_CLKDIST_DCFG0_CFG0
+SD_Data_Clk__CFG1 EQU CYREG_CLKDIST_DCFG0_CFG1
+SD_Data_Clk__CFG2 EQU CYREG_CLKDIST_DCFG0_CFG2
+SD_Data_Clk__CFG2_SRC_SEL_MASK EQU 0x07
+SD_Data_Clk__INDEX EQU 0x00
+SD_Data_Clk__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2
+SD_Data_Clk__PM_ACT_MSK EQU 0x01
+SD_Data_Clk__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2
+SD_Data_Clk__PM_STBY_MSK EQU 0x01
+
+; SD_MISO
+SD_MISO__0__INTTYPE EQU CYREG_PICU3_INTTYPE2
+SD_MISO__0__MASK EQU 0x04
+SD_MISO__0__PC EQU CYREG_PRT3_PC2
+SD_MISO__0__PORT EQU 3
+SD_MISO__0__SHIFT EQU 2
+SD_MISO__AG EQU CYREG_PRT3_AG
+SD_MISO__AMUX EQU CYREG_PRT3_AMUX
+SD_MISO__BIE EQU CYREG_PRT3_BIE
+SD_MISO__BIT_MASK EQU CYREG_PRT3_BIT_MASK
+SD_MISO__BYP EQU CYREG_PRT3_BYP
+SD_MISO__CTL EQU CYREG_PRT3_CTL
+SD_MISO__DM0 EQU CYREG_PRT3_DM0
+SD_MISO__DM1 EQU CYREG_PRT3_DM1
+SD_MISO__DM2 EQU CYREG_PRT3_DM2
+SD_MISO__DR EQU CYREG_PRT3_DR
+SD_MISO__INP_DIS EQU CYREG_PRT3_INP_DIS
+SD_MISO__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE
+SD_MISO__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG
+SD_MISO__LCD_EN EQU CYREG_PRT3_LCD_EN
+SD_MISO__MASK EQU 0x04
+SD_MISO__PORT EQU 3
+SD_MISO__PRT EQU CYREG_PRT3_PRT
+SD_MISO__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL
+SD_MISO__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN
+SD_MISO__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0
+SD_MISO__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1
+SD_MISO__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0
+SD_MISO__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1
+SD_MISO__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT
+SD_MISO__PS EQU CYREG_PRT3_PS
+SD_MISO__SHIFT EQU 2
+SD_MISO__SLW EQU CYREG_PRT3_SLW
+
+; SD_MOSI
+SD_MOSI__0__INTTYPE EQU CYREG_PICU3_INTTYPE4
+SD_MOSI__0__MASK EQU 0x10
+SD_MOSI__0__PC EQU CYREG_PRT3_PC4
+SD_MOSI__0__PORT EQU 3
+SD_MOSI__0__SHIFT EQU 4
+SD_MOSI__AG EQU CYREG_PRT3_AG
+SD_MOSI__AMUX EQU CYREG_PRT3_AMUX
+SD_MOSI__BIE EQU CYREG_PRT3_BIE
+SD_MOSI__BIT_MASK EQU CYREG_PRT3_BIT_MASK
+SD_MOSI__BYP EQU CYREG_PRT3_BYP
+SD_MOSI__CTL EQU CYREG_PRT3_CTL
+SD_MOSI__DM0 EQU CYREG_PRT3_DM0
+SD_MOSI__DM1 EQU CYREG_PRT3_DM1
+SD_MOSI__DM2 EQU CYREG_PRT3_DM2
+SD_MOSI__DR EQU CYREG_PRT3_DR
+SD_MOSI__INP_DIS EQU CYREG_PRT3_INP_DIS
+SD_MOSI__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE
+SD_MOSI__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG
+SD_MOSI__LCD_EN EQU CYREG_PRT3_LCD_EN
+SD_MOSI__MASK EQU 0x10
+SD_MOSI__PORT EQU 3
+SD_MOSI__PRT EQU CYREG_PRT3_PRT
+SD_MOSI__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL
+SD_MOSI__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN
+SD_MOSI__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0
+SD_MOSI__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1
+SD_MOSI__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0
+SD_MOSI__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1
+SD_MOSI__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT
+SD_MOSI__PS EQU CYREG_PRT3_PS
+SD_MOSI__SHIFT EQU 4
+SD_MOSI__SLW EQU CYREG_PRT3_SLW
+
+; SD_RX_DMA
+SD_RX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0
+SD_RX_DMA__DRQ_NUMBER EQU 2
+SD_RX_DMA__NUMBEROF_TDS EQU 0
+SD_RX_DMA__PRIORITY EQU 0
+SD_RX_DMA__TERMIN_EN EQU 0
+SD_RX_DMA__TERMIN_SEL EQU 0
+SD_RX_DMA__TERMOUT0_EN EQU 1
+SD_RX_DMA__TERMOUT0_SEL EQU 2
+SD_RX_DMA__TERMOUT1_EN EQU 0
+SD_RX_DMA__TERMOUT1_SEL EQU 0
+SD_RX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
+SD_RX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
+SD_RX_DMA_COMPLETE__INTC_MASK EQU 0x20
+SD_RX_DMA_COMPLETE__INTC_NUMBER EQU 5
+SD_RX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7
+SD_RX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_5
+SD_RX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
+SD_RX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
+
+; SD_SCK
+SD_SCK__0__INTTYPE EQU CYREG_PICU3_INTTYPE3
+SD_SCK__0__MASK EQU 0x08
+SD_SCK__0__PC EQU CYREG_PRT3_PC3
+SD_SCK__0__PORT EQU 3
+SD_SCK__0__SHIFT EQU 3
+SD_SCK__AG EQU CYREG_PRT3_AG
+SD_SCK__AMUX EQU CYREG_PRT3_AMUX
+SD_SCK__BIE EQU CYREG_PRT3_BIE
+SD_SCK__BIT_MASK EQU CYREG_PRT3_BIT_MASK
+SD_SCK__BYP EQU CYREG_PRT3_BYP
+SD_SCK__CTL EQU CYREG_PRT3_CTL
+SD_SCK__DM0 EQU CYREG_PRT3_DM0
+SD_SCK__DM1 EQU CYREG_PRT3_DM1
+SD_SCK__DM2 EQU CYREG_PRT3_DM2
+SD_SCK__DR EQU CYREG_PRT3_DR
+SD_SCK__INP_DIS EQU CYREG_PRT3_INP_DIS
+SD_SCK__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE
+SD_SCK__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG
+SD_SCK__LCD_EN EQU CYREG_PRT3_LCD_EN
+SD_SCK__MASK EQU 0x08
+SD_SCK__PORT EQU 3
+SD_SCK__PRT EQU CYREG_PRT3_PRT
+SD_SCK__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL
+SD_SCK__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN
+SD_SCK__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0
+SD_SCK__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1
+SD_SCK__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0
+SD_SCK__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1
+SD_SCK__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT
+SD_SCK__PS EQU CYREG_PRT3_PS
+SD_SCK__SHIFT EQU 3
+SD_SCK__SLW EQU CYREG_PRT3_SLW
+
+; SD_TX_DMA
+SD_TX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0
+SD_TX_DMA__DRQ_NUMBER EQU 3
+SD_TX_DMA__NUMBEROF_TDS EQU 0
+SD_TX_DMA__PRIORITY EQU 1
+SD_TX_DMA__TERMIN_EN EQU 0
+SD_TX_DMA__TERMIN_SEL EQU 0
+SD_TX_DMA__TERMOUT0_EN EQU 1
+SD_TX_DMA__TERMOUT0_SEL EQU 3
+SD_TX_DMA__TERMOUT1_EN EQU 0
+SD_TX_DMA__TERMOUT1_SEL EQU 0
+SD_TX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
+SD_TX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
+SD_TX_DMA_COMPLETE__INTC_MASK EQU 0x40
+SD_TX_DMA_COMPLETE__INTC_NUMBER EQU 6
+SD_TX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7
+SD_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_6
+SD_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
+SD_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
+
+; TERM_EN
+TERM_EN__0__INTTYPE EQU CYREG_PICU15_INTTYPE3
+TERM_EN__0__MASK EQU 0x08
+TERM_EN__0__PC EQU CYREG_IO_PC_PRT15_PC3
+TERM_EN__0__PORT EQU 15
+TERM_EN__0__SHIFT EQU 3
+TERM_EN__AG EQU CYREG_PRT15_AG
+TERM_EN__AMUX EQU CYREG_PRT15_AMUX
+TERM_EN__BIE EQU CYREG_PRT15_BIE
+TERM_EN__BIT_MASK EQU CYREG_PRT15_BIT_MASK
+TERM_EN__BYP EQU CYREG_PRT15_BYP
+TERM_EN__CTL EQU CYREG_PRT15_CTL
+TERM_EN__DM0 EQU CYREG_PRT15_DM0
+TERM_EN__DM1 EQU CYREG_PRT15_DM1
+TERM_EN__DM2 EQU CYREG_PRT15_DM2
+TERM_EN__DR EQU CYREG_PRT15_DR
+TERM_EN__INP_DIS EQU CYREG_PRT15_INP_DIS
+TERM_EN__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU15_BASE
+TERM_EN__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG
+TERM_EN__LCD_EN EQU CYREG_PRT15_LCD_EN
+TERM_EN__MASK EQU 0x08
+TERM_EN__PORT EQU 15
+TERM_EN__PRT EQU CYREG_PRT15_PRT
+TERM_EN__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL
+TERM_EN__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN
+TERM_EN__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0
+TERM_EN__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1
+TERM_EN__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0
+TERM_EN__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1
+TERM_EN__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT
+TERM_EN__PS EQU CYREG_PRT15_PS
+TERM_EN__SHIFT EQU 3
+TERM_EN__SLW EQU CYREG_PRT15_SLW
+
+; USBFS
+USBFS_arb_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
+USBFS_arb_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
+USBFS_arb_int__INTC_MASK EQU 0x400000
+USBFS_arb_int__INTC_NUMBER EQU 22
+USBFS_arb_int__INTC_PRIOR_NUM EQU 6
+USBFS_arb_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_22
+USBFS_arb_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
+USBFS_arb_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
+USBFS_bus_reset__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
+USBFS_bus_reset__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
+USBFS_bus_reset__INTC_MASK EQU 0x800000
+USBFS_bus_reset__INTC_NUMBER EQU 23
+USBFS_bus_reset__INTC_PRIOR_NUM EQU 7
+USBFS_bus_reset__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_23
+USBFS_bus_reset__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
+USBFS_bus_reset__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
+USBFS_Dm__0__INTTYPE EQU CYREG_PICU15_INTTYPE7
+USBFS_Dm__0__MASK EQU 0x80
+USBFS_Dm__0__PC EQU CYREG_IO_PC_PRT15_7_6_PC1
+USBFS_Dm__0__PORT EQU 15
+USBFS_Dm__0__SHIFT EQU 7
+USBFS_Dm__AG EQU CYREG_PRT15_AG
+USBFS_Dm__AMUX EQU CYREG_PRT15_AMUX
+USBFS_Dm__BIE EQU CYREG_PRT15_BIE
+USBFS_Dm__BIT_MASK EQU CYREG_PRT15_BIT_MASK
+USBFS_Dm__BYP EQU CYREG_PRT15_BYP
+USBFS_Dm__CTL EQU CYREG_PRT15_CTL
+USBFS_Dm__DM0 EQU CYREG_PRT15_DM0
+USBFS_Dm__DM1 EQU CYREG_PRT15_DM1
+USBFS_Dm__DM2 EQU CYREG_PRT15_DM2
+USBFS_Dm__DR EQU CYREG_PRT15_DR
+USBFS_Dm__INP_DIS EQU CYREG_PRT15_INP_DIS
+USBFS_Dm__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU15_BASE
+USBFS_Dm__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG
+USBFS_Dm__LCD_EN EQU CYREG_PRT15_LCD_EN
+USBFS_Dm__MASK EQU 0x80
+USBFS_Dm__PORT EQU 15
+USBFS_Dm__PRT EQU CYREG_PRT15_PRT
+USBFS_Dm__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL
+USBFS_Dm__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN
+USBFS_Dm__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0
+USBFS_Dm__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1
+USBFS_Dm__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0
+USBFS_Dm__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1
+USBFS_Dm__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT
+USBFS_Dm__PS EQU CYREG_PRT15_PS
+USBFS_Dm__SHIFT EQU 7
+USBFS_Dm__SLW EQU CYREG_PRT15_SLW
+USBFS_Dp__0__INTTYPE EQU CYREG_PICU15_INTTYPE6
+USBFS_Dp__0__MASK EQU 0x40
+USBFS_Dp__0__PC EQU CYREG_IO_PC_PRT15_7_6_PC0
+USBFS_Dp__0__PORT EQU 15
+USBFS_Dp__0__SHIFT EQU 6
+USBFS_Dp__AG EQU CYREG_PRT15_AG
+USBFS_Dp__AMUX EQU CYREG_PRT15_AMUX
+USBFS_Dp__BIE EQU CYREG_PRT15_BIE
+USBFS_Dp__BIT_MASK EQU CYREG_PRT15_BIT_MASK
+USBFS_Dp__BYP EQU CYREG_PRT15_BYP
+USBFS_Dp__CTL EQU CYREG_PRT15_CTL
+USBFS_Dp__DM0 EQU CYREG_PRT15_DM0
+USBFS_Dp__DM1 EQU CYREG_PRT15_DM1
+USBFS_Dp__DM2 EQU CYREG_PRT15_DM2
+USBFS_Dp__DR EQU CYREG_PRT15_DR
+USBFS_Dp__INP_DIS EQU CYREG_PRT15_INP_DIS
+USBFS_Dp__INTSTAT EQU CYREG_PICU15_INTSTAT
+USBFS_Dp__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU15_BASE
+USBFS_Dp__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG
+USBFS_Dp__LCD_EN EQU CYREG_PRT15_LCD_EN
+USBFS_Dp__MASK EQU 0x40
+USBFS_Dp__PORT EQU 15
+USBFS_Dp__PRT EQU CYREG_PRT15_PRT
+USBFS_Dp__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL
+USBFS_Dp__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN
+USBFS_Dp__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0
+USBFS_Dp__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1
+USBFS_Dp__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0
+USBFS_Dp__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1
+USBFS_Dp__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT
+USBFS_Dp__PS EQU CYREG_PRT15_PS
+USBFS_Dp__SHIFT EQU 6
+USBFS_Dp__SLW EQU CYREG_PRT15_SLW
+USBFS_Dp__SNAP EQU CYREG_PICU_15_SNAP_15
+USBFS_dp_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
+USBFS_dp_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
+USBFS_dp_int__INTC_MASK EQU 0x1000
+USBFS_dp_int__INTC_NUMBER EQU 12
+USBFS_dp_int__INTC_PRIOR_NUM EQU 7
+USBFS_dp_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_12
+USBFS_dp_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
+USBFS_dp_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
+USBFS_ep_0__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
+USBFS_ep_0__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
+USBFS_ep_0__INTC_MASK EQU 0x1000000
+USBFS_ep_0__INTC_NUMBER EQU 24
+USBFS_ep_0__INTC_PRIOR_NUM EQU 7
+USBFS_ep_0__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_24
+USBFS_ep_0__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
+USBFS_ep_0__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
+USBFS_ep_1__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
+USBFS_ep_1__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
+USBFS_ep_1__INTC_MASK EQU 0x80
+USBFS_ep_1__INTC_NUMBER EQU 7
+USBFS_ep_1__INTC_PRIOR_NUM EQU 7
+USBFS_ep_1__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_7
+USBFS_ep_1__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
+USBFS_ep_1__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
+USBFS_ep_2__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
+USBFS_ep_2__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
+USBFS_ep_2__INTC_MASK EQU 0x100
+USBFS_ep_2__INTC_NUMBER EQU 8
+USBFS_ep_2__INTC_PRIOR_NUM EQU 7
+USBFS_ep_2__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_8
+USBFS_ep_2__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
+USBFS_ep_2__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
+USBFS_ep_3__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
+USBFS_ep_3__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
+USBFS_ep_3__INTC_MASK EQU 0x200
+USBFS_ep_3__INTC_NUMBER EQU 9
+USBFS_ep_3__INTC_PRIOR_NUM EQU 7
+USBFS_ep_3__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_9
+USBFS_ep_3__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
+USBFS_ep_3__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
+USBFS_ep_4__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
+USBFS_ep_4__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
+USBFS_ep_4__INTC_MASK EQU 0x400
+USBFS_ep_4__INTC_NUMBER EQU 10
+USBFS_ep_4__INTC_PRIOR_NUM EQU 7
+USBFS_ep_4__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_10
+USBFS_ep_4__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
+USBFS_ep_4__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
+USBFS_sof_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
+USBFS_sof_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
+USBFS_sof_int__INTC_MASK EQU 0x200000
+USBFS_sof_int__INTC_NUMBER EQU 21
+USBFS_sof_int__INTC_PRIOR_NUM EQU 7
+USBFS_sof_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_21
+USBFS_sof_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
+USBFS_sof_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
+USBFS_USB__ARB_CFG EQU CYREG_USB_ARB_CFG
+USBFS_USB__ARB_EP1_CFG EQU CYREG_USB_ARB_EP1_CFG
+USBFS_USB__ARB_EP1_INT_EN EQU CYREG_USB_ARB_EP1_INT_EN
+USBFS_USB__ARB_EP1_SR EQU CYREG_USB_ARB_EP1_SR
+USBFS_USB__ARB_EP2_CFG EQU CYREG_USB_ARB_EP2_CFG
+USBFS_USB__ARB_EP2_INT_EN EQU CYREG_USB_ARB_EP2_INT_EN
+USBFS_USB__ARB_EP2_SR EQU CYREG_USB_ARB_EP2_SR
+USBFS_USB__ARB_EP3_CFG EQU CYREG_USB_ARB_EP3_CFG
+USBFS_USB__ARB_EP3_INT_EN EQU CYREG_USB_ARB_EP3_INT_EN
+USBFS_USB__ARB_EP3_SR EQU CYREG_USB_ARB_EP3_SR
+USBFS_USB__ARB_EP4_CFG EQU CYREG_USB_ARB_EP4_CFG
+USBFS_USB__ARB_EP4_INT_EN EQU CYREG_USB_ARB_EP4_INT_EN
+USBFS_USB__ARB_EP4_SR EQU CYREG_USB_ARB_EP4_SR
+USBFS_USB__ARB_EP5_CFG EQU CYREG_USB_ARB_EP5_CFG
+USBFS_USB__ARB_EP5_INT_EN EQU CYREG_USB_ARB_EP5_INT_EN
+USBFS_USB__ARB_EP5_SR EQU CYREG_USB_ARB_EP5_SR
+USBFS_USB__ARB_EP6_CFG EQU CYREG_USB_ARB_EP6_CFG
+USBFS_USB__ARB_EP6_INT_EN EQU CYREG_USB_ARB_EP6_INT_EN
+USBFS_USB__ARB_EP6_SR EQU CYREG_USB_ARB_EP6_SR
+USBFS_USB__ARB_EP7_CFG EQU CYREG_USB_ARB_EP7_CFG
+USBFS_USB__ARB_EP7_INT_EN EQU CYREG_USB_ARB_EP7_INT_EN
+USBFS_USB__ARB_EP7_SR EQU CYREG_USB_ARB_EP7_SR
+USBFS_USB__ARB_EP8_CFG EQU CYREG_USB_ARB_EP8_CFG
+USBFS_USB__ARB_EP8_INT_EN EQU CYREG_USB_ARB_EP8_INT_EN
+USBFS_USB__ARB_EP8_SR EQU CYREG_USB_ARB_EP8_SR
+USBFS_USB__ARB_INT_EN EQU CYREG_USB_ARB_INT_EN
+USBFS_USB__ARB_INT_SR EQU CYREG_USB_ARB_INT_SR
+USBFS_USB__ARB_RW1_DR EQU CYREG_USB_ARB_RW1_DR
+USBFS_USB__ARB_RW1_RA EQU CYREG_USB_ARB_RW1_RA
+USBFS_USB__ARB_RW1_RA_MSB EQU CYREG_USB_ARB_RW1_RA_MSB
+USBFS_USB__ARB_RW1_WA EQU CYREG_USB_ARB_RW1_WA
+USBFS_USB__ARB_RW1_WA_MSB EQU CYREG_USB_ARB_RW1_WA_MSB
+USBFS_USB__ARB_RW2_DR EQU CYREG_USB_ARB_RW2_DR
+USBFS_USB__ARB_RW2_RA EQU CYREG_USB_ARB_RW2_RA
+USBFS_USB__ARB_RW2_RA_MSB EQU CYREG_USB_ARB_RW2_RA_MSB
+USBFS_USB__ARB_RW2_WA EQU CYREG_USB_ARB_RW2_WA
+USBFS_USB__ARB_RW2_WA_MSB EQU CYREG_USB_ARB_RW2_WA_MSB
+USBFS_USB__ARB_RW3_DR EQU CYREG_USB_ARB_RW3_DR
+USBFS_USB__ARB_RW3_RA EQU CYREG_USB_ARB_RW3_RA
+USBFS_USB__ARB_RW3_RA_MSB EQU CYREG_USB_ARB_RW3_RA_MSB
+USBFS_USB__ARB_RW3_WA EQU CYREG_USB_ARB_RW3_WA
+USBFS_USB__ARB_RW3_WA_MSB EQU CYREG_USB_ARB_RW3_WA_MSB
+USBFS_USB__ARB_RW4_DR EQU CYREG_USB_ARB_RW4_DR
+USBFS_USB__ARB_RW4_RA EQU CYREG_USB_ARB_RW4_RA
+USBFS_USB__ARB_RW4_RA_MSB EQU CYREG_USB_ARB_RW4_RA_MSB
+USBFS_USB__ARB_RW4_WA EQU CYREG_USB_ARB_RW4_WA
+USBFS_USB__ARB_RW4_WA_MSB EQU CYREG_USB_ARB_RW4_WA_MSB
+USBFS_USB__ARB_RW5_DR EQU CYREG_USB_ARB_RW5_DR
+USBFS_USB__ARB_RW5_RA EQU CYREG_USB_ARB_RW5_RA
+USBFS_USB__ARB_RW5_RA_MSB EQU CYREG_USB_ARB_RW5_RA_MSB
+USBFS_USB__ARB_RW5_WA EQU CYREG_USB_ARB_RW5_WA
+USBFS_USB__ARB_RW5_WA_MSB EQU CYREG_USB_ARB_RW5_WA_MSB
+USBFS_USB__ARB_RW6_DR EQU CYREG_USB_ARB_RW6_DR
+USBFS_USB__ARB_RW6_RA EQU CYREG_USB_ARB_RW6_RA
+USBFS_USB__ARB_RW6_RA_MSB EQU CYREG_USB_ARB_RW6_RA_MSB
+USBFS_USB__ARB_RW6_WA EQU CYREG_USB_ARB_RW6_WA
+USBFS_USB__ARB_RW6_WA_MSB EQU CYREG_USB_ARB_RW6_WA_MSB
+USBFS_USB__ARB_RW7_DR EQU CYREG_USB_ARB_RW7_DR
+USBFS_USB__ARB_RW7_RA EQU CYREG_USB_ARB_RW7_RA
+USBFS_USB__ARB_RW7_RA_MSB EQU CYREG_USB_ARB_RW7_RA_MSB
+USBFS_USB__ARB_RW7_WA EQU CYREG_USB_ARB_RW7_WA
+USBFS_USB__ARB_RW7_WA_MSB EQU CYREG_USB_ARB_RW7_WA_MSB
+USBFS_USB__ARB_RW8_DR EQU CYREG_USB_ARB_RW8_DR
+USBFS_USB__ARB_RW8_RA EQU CYREG_USB_ARB_RW8_RA
+USBFS_USB__ARB_RW8_RA_MSB EQU CYREG_USB_ARB_RW8_RA_MSB
+USBFS_USB__ARB_RW8_WA EQU CYREG_USB_ARB_RW8_WA
+USBFS_USB__ARB_RW8_WA_MSB EQU CYREG_USB_ARB_RW8_WA_MSB
+USBFS_USB__BUF_SIZE EQU CYREG_USB_BUF_SIZE
+USBFS_USB__BUS_RST_CNT EQU CYREG_USB_BUS_RST_CNT
+USBFS_USB__CR0 EQU CYREG_USB_CR0
+USBFS_USB__CR1 EQU CYREG_USB_CR1
+USBFS_USB__CWA EQU CYREG_USB_CWA
+USBFS_USB__CWA_MSB EQU CYREG_USB_CWA_MSB
+USBFS_USB__DMA_THRES EQU CYREG_USB_DMA_THRES
+USBFS_USB__DMA_THRES_MSB EQU CYREG_USB_DMA_THRES_MSB
+USBFS_USB__DYN_RECONFIG EQU CYREG_USB_DYN_RECONFIG
+USBFS_USB__EP_ACTIVE EQU CYREG_USB_EP_ACTIVE
+USBFS_USB__EP_TYPE EQU CYREG_USB_EP_TYPE
+USBFS_USB__EP0_CNT EQU CYREG_USB_EP0_CNT
+USBFS_USB__EP0_CR EQU CYREG_USB_EP0_CR
+USBFS_USB__EP0_DR0 EQU CYREG_USB_EP0_DR0
+USBFS_USB__EP0_DR1 EQU CYREG_USB_EP0_DR1
+USBFS_USB__EP0_DR2 EQU CYREG_USB_EP0_DR2
+USBFS_USB__EP0_DR3 EQU CYREG_USB_EP0_DR3
+USBFS_USB__EP0_DR4 EQU CYREG_USB_EP0_DR4
+USBFS_USB__EP0_DR5 EQU CYREG_USB_EP0_DR5
+USBFS_USB__EP0_DR6 EQU CYREG_USB_EP0_DR6
+USBFS_USB__EP0_DR7 EQU CYREG_USB_EP0_DR7
+USBFS_USB__MEM_DATA EQU CYREG_USB_MEM_DATA_MBASE
+USBFS_USB__PM_ACT_CFG EQU CYREG_PM_ACT_CFG5
+USBFS_USB__PM_ACT_MSK EQU 0x01
+USBFS_USB__PM_STBY_CFG EQU CYREG_PM_STBY_CFG5
+USBFS_USB__PM_STBY_MSK EQU 0x01
+USBFS_USB__SIE_EP_INT_EN EQU CYREG_USB_SIE_EP_INT_EN
+USBFS_USB__SIE_EP_INT_SR EQU CYREG_USB_SIE_EP_INT_SR
+USBFS_USB__SIE_EP1_CNT0 EQU CYREG_USB_SIE_EP1_CNT0
+USBFS_USB__SIE_EP1_CNT1 EQU CYREG_USB_SIE_EP1_CNT1
+USBFS_USB__SIE_EP1_CR0 EQU CYREG_USB_SIE_EP1_CR0
+USBFS_USB__SIE_EP2_CNT0 EQU CYREG_USB_SIE_EP2_CNT0
+USBFS_USB__SIE_EP2_CNT1 EQU CYREG_USB_SIE_EP2_CNT1
+USBFS_USB__SIE_EP2_CR0 EQU CYREG_USB_SIE_EP2_CR0
+USBFS_USB__SIE_EP3_CNT0 EQU CYREG_USB_SIE_EP3_CNT0
+USBFS_USB__SIE_EP3_CNT1 EQU CYREG_USB_SIE_EP3_CNT1
+USBFS_USB__SIE_EP3_CR0 EQU CYREG_USB_SIE_EP3_CR0
+USBFS_USB__SIE_EP4_CNT0 EQU CYREG_USB_SIE_EP4_CNT0
+USBFS_USB__SIE_EP4_CNT1 EQU CYREG_USB_SIE_EP4_CNT1
+USBFS_USB__SIE_EP4_CR0 EQU CYREG_USB_SIE_EP4_CR0
+USBFS_USB__SIE_EP5_CNT0 EQU CYREG_USB_SIE_EP5_CNT0
+USBFS_USB__SIE_EP5_CNT1 EQU CYREG_USB_SIE_EP5_CNT1
+USBFS_USB__SIE_EP5_CR0 EQU CYREG_USB_SIE_EP5_CR0
+USBFS_USB__SIE_EP6_CNT0 EQU CYREG_USB_SIE_EP6_CNT0
+USBFS_USB__SIE_EP6_CNT1 EQU CYREG_USB_SIE_EP6_CNT1
+USBFS_USB__SIE_EP6_CR0 EQU CYREG_USB_SIE_EP6_CR0
+USBFS_USB__SIE_EP7_CNT0 EQU CYREG_USB_SIE_EP7_CNT0
+USBFS_USB__SIE_EP7_CNT1 EQU CYREG_USB_SIE_EP7_CNT1
+USBFS_USB__SIE_EP7_CR0 EQU CYREG_USB_SIE_EP7_CR0
+USBFS_USB__SIE_EP8_CNT0 EQU CYREG_USB_SIE_EP8_CNT0
+USBFS_USB__SIE_EP8_CNT1 EQU CYREG_USB_SIE_EP8_CNT1
+USBFS_USB__SIE_EP8_CR0 EQU CYREG_USB_SIE_EP8_CR0
+USBFS_USB__SOF0 EQU CYREG_USB_SOF0
+USBFS_USB__SOF1 EQU CYREG_USB_SOF1
+USBFS_USB__USB_CLK_EN EQU CYREG_USB_USB_CLK_EN
+USBFS_USB__USBIO_CR0 EQU CYREG_USB_USBIO_CR0
+USBFS_USB__USBIO_CR1 EQU CYREG_USB_USBIO_CR1
+
 ; scsiTarget
 scsiTarget_datapath__16BIT_A0_REG EQU CYREG_B0_UDB00_01_A0
 scsiTarget_datapath__16BIT_A1_REG EQU CYREG_B0_UDB00_01_A1
@@ -2415,89 +2579,6 @@ scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB15_MSK
 scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB15_ACTL
 scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB15_ST
 
-; Debug_Timer_Interrupt
-Debug_Timer_Interrupt__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
-Debug_Timer_Interrupt__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-Debug_Timer_Interrupt__INTC_MASK EQU 0x02
-Debug_Timer_Interrupt__INTC_NUMBER EQU 1
-Debug_Timer_Interrupt__INTC_PRIOR_NUM EQU 7
-Debug_Timer_Interrupt__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_1
-Debug_Timer_Interrupt__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
-Debug_Timer_Interrupt__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
-
-; Debug_Timer_TimerHW
-Debug_Timer_TimerHW__CAP0 EQU CYREG_TMR0_CAP0
-Debug_Timer_TimerHW__CAP1 EQU CYREG_TMR0_CAP1
-Debug_Timer_TimerHW__CFG0 EQU CYREG_TMR0_CFG0
-Debug_Timer_TimerHW__CFG1 EQU CYREG_TMR0_CFG1
-Debug_Timer_TimerHW__CFG2 EQU CYREG_TMR0_CFG2
-Debug_Timer_TimerHW__CNT_CMP0 EQU CYREG_TMR0_CNT_CMP0
-Debug_Timer_TimerHW__CNT_CMP1 EQU CYREG_TMR0_CNT_CMP1
-Debug_Timer_TimerHW__PER0 EQU CYREG_TMR0_PER0
-Debug_Timer_TimerHW__PER1 EQU CYREG_TMR0_PER1
-Debug_Timer_TimerHW__PM_ACT_CFG EQU CYREG_PM_ACT_CFG3
-Debug_Timer_TimerHW__PM_ACT_MSK EQU 0x01
-Debug_Timer_TimerHW__PM_STBY_CFG EQU CYREG_PM_STBY_CFG3
-Debug_Timer_TimerHW__PM_STBY_MSK EQU 0x01
-Debug_Timer_TimerHW__RT0 EQU CYREG_TMR0_RT0
-Debug_Timer_TimerHW__RT1 EQU CYREG_TMR0_RT1
-Debug_Timer_TimerHW__SR0 EQU CYREG_TMR0_SR0
-
-; SCSI_RX_DMA
-SCSI_RX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0
-SCSI_RX_DMA__DRQ_NUMBER EQU 0
-SCSI_RX_DMA__NUMBEROF_TDS EQU 0
-SCSI_RX_DMA__PRIORITY EQU 2
-SCSI_RX_DMA__TERMIN_EN EQU 0
-SCSI_RX_DMA__TERMIN_SEL EQU 0
-SCSI_RX_DMA__TERMOUT0_EN EQU 1
-SCSI_RX_DMA__TERMOUT0_SEL EQU 0
-SCSI_RX_DMA__TERMOUT1_EN EQU 0
-SCSI_RX_DMA__TERMOUT1_SEL EQU 0
-
-; SCSI_RX_DMA_COMPLETE
-SCSI_RX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
-SCSI_RX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-SCSI_RX_DMA_COMPLETE__INTC_MASK EQU 0x01
-SCSI_RX_DMA_COMPLETE__INTC_NUMBER EQU 0
-SCSI_RX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7
-SCSI_RX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_0
-SCSI_RX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
-SCSI_RX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
-
-; SCSI_TX_DMA
-SCSI_TX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0
-SCSI_TX_DMA__DRQ_NUMBER EQU 1
-SCSI_TX_DMA__NUMBEROF_TDS EQU 0
-SCSI_TX_DMA__PRIORITY EQU 2
-SCSI_TX_DMA__TERMIN_EN EQU 0
-SCSI_TX_DMA__TERMIN_SEL EQU 0
-SCSI_TX_DMA__TERMOUT0_EN EQU 1
-SCSI_TX_DMA__TERMOUT0_SEL EQU 1
-SCSI_TX_DMA__TERMOUT1_EN EQU 0
-SCSI_TX_DMA__TERMOUT1_SEL EQU 0
-
-; SCSI_TX_DMA_COMPLETE
-SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
-SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-SCSI_TX_DMA_COMPLETE__INTC_MASK EQU 0x10
-SCSI_TX_DMA_COMPLETE__INTC_NUMBER EQU 4
-SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7
-SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_4
-SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
-SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
-
-; SD_Data_Clk
-SD_Data_Clk__CFG0 EQU CYREG_CLKDIST_DCFG0_CFG0
-SD_Data_Clk__CFG1 EQU CYREG_CLKDIST_DCFG0_CFG1
-SD_Data_Clk__CFG2 EQU CYREG_CLKDIST_DCFG0_CFG2
-SD_Data_Clk__CFG2_SRC_SEL_MASK EQU 0x07
-SD_Data_Clk__INDEX EQU 0x00
-SD_Data_Clk__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2
-SD_Data_Clk__PM_ACT_MSK EQU 0x01
-SD_Data_Clk__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2
-SD_Data_Clk__PM_STBY_MSK EQU 0x01
-
 ; timer_clock
 timer_clock__CFG0 EQU CYREG_CLKDIST_DCFG2_CFG0
 timer_clock__CFG1 EQU CYREG_CLKDIST_DCFG2_CFG1
@@ -2509,154 +2590,53 @@ timer_clock__PM_ACT_MSK EQU 0x04
 timer_clock__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2
 timer_clock__PM_STBY_MSK EQU 0x04
 
-; SCSI_RST_ISR
-SCSI_RST_ISR__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
-SCSI_RST_ISR__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-SCSI_RST_ISR__INTC_MASK EQU 0x04
-SCSI_RST_ISR__INTC_NUMBER EQU 2
-SCSI_RST_ISR__INTC_PRIOR_NUM EQU 7
-SCSI_RST_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_2
-SCSI_RST_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
-SCSI_RST_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
-
-; SCSI_SEL_ISR
-SCSI_SEL_ISR__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
-SCSI_SEL_ISR__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-SCSI_SEL_ISR__INTC_MASK EQU 0x08
-SCSI_SEL_ISR__INTC_NUMBER EQU 3
-SCSI_SEL_ISR__INTC_PRIOR_NUM EQU 7
-SCSI_SEL_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_3
-SCSI_SEL_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
-SCSI_SEL_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
-
-; SCSI_Filtered
-SCSI_Filtered_sts_sts_reg__0__MASK EQU 0x01
-SCSI_Filtered_sts_sts_reg__0__POS EQU 0
-SCSI_Filtered_sts_sts_reg__1__MASK EQU 0x02
-SCSI_Filtered_sts_sts_reg__1__POS EQU 1
-SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL
-SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB11_12_ST
-SCSI_Filtered_sts_sts_reg__2__MASK EQU 0x04
-SCSI_Filtered_sts_sts_reg__2__POS EQU 2
-SCSI_Filtered_sts_sts_reg__3__MASK EQU 0x08
-SCSI_Filtered_sts_sts_reg__3__POS EQU 3
-SCSI_Filtered_sts_sts_reg__4__MASK EQU 0x10
-SCSI_Filtered_sts_sts_reg__4__POS EQU 4
-SCSI_Filtered_sts_sts_reg__MASK EQU 0x1F
-SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB11_MSK
-SCSI_Filtered_sts_sts_reg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
-SCSI_Filtered_sts_sts_reg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
-SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL
-SCSI_Filtered_sts_sts_reg__STATUS_CNT_REG EQU CYREG_B0_UDB11_ST_CTL
-SCSI_Filtered_sts_sts_reg__STATUS_CONTROL_REG EQU CYREG_B0_UDB11_ST_CTL
-SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB11_ST
-
-; SCSI_CTL_PHASE
-SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01
-SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS EQU 0
-SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK EQU 0x02
-SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS EQU 1
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB02_03_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB02_03_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB02_03_MSK
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB02_03_MSK
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK
-SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK EQU 0x04
-SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS EQU 2
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB02_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB02_ST_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB02_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB02_ST_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__MASK EQU 0x07
-SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB02_MSK
-
-; SCSI_Glitch_Ctl
-SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01
-SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS EQU 0
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB05_06_CTL
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB05_06_CTL
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB05_06_MSK
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB05_06_MSK
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK
-SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL
-SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB05_CTL
-SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB05_ST_CTL
-SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB05_CTL
-SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB05_ST_CTL
-SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK EQU 0x01
-SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL
-SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL
-SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB05_MSK
-
-; SCSI_Parity_Error
-SCSI_Parity_Error_sts_sts_reg__0__MASK EQU 0x01
-SCSI_Parity_Error_sts_sts_reg__0__POS EQU 0
-SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL
-SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB02_03_ST
-SCSI_Parity_Error_sts_sts_reg__MASK EQU 0x01
-SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB02_MSK
-SCSI_Parity_Error_sts_sts_reg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL
-SCSI_Parity_Error_sts_sts_reg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL
-SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL
-SCSI_Parity_Error_sts_sts_reg__STATUS_CNT_REG EQU CYREG_B0_UDB02_ST_CTL
-SCSI_Parity_Error_sts_sts_reg__STATUS_CONTROL_REG EQU CYREG_B0_UDB02_ST_CTL
-SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB02_ST
-
 ; Miscellaneous
 BCLK__BUS_CLK__HZ EQU 50000000
 BCLK__BUS_CLK__KHZ EQU 50000
 BCLK__BUS_CLK__MHZ EQU 50
 CYDEV_CHIP_DIE_LEOPARD EQU 1
-CYDEV_CHIP_DIE_PSOC4A EQU 12
-CYDEV_CHIP_DIE_PSOC5LP EQU 19
-CYDEV_CHIP_DIE_PSOC5TM EQU 20
-CYDEV_CHIP_DIE_TMA4 EQU 2
+CYDEV_CHIP_DIE_PSOC4A EQU 16
+CYDEV_CHIP_DIE_PSOC5LP EQU 2
+CYDEV_CHIP_DIE_PSOC5TM EQU 3
+CYDEV_CHIP_DIE_TMA4 EQU 4
 CYDEV_CHIP_DIE_UNKNOWN EQU 0
-CYDEV_CHIP_FAMILY_FM0P EQU 4
-CYDEV_CHIP_FAMILY_FM3 EQU 5
-CYDEV_CHIP_FAMILY_FM4 EQU 6
+CYDEV_CHIP_FAMILY_FM0P EQU 5
+CYDEV_CHIP_FAMILY_FM3 EQU 6
+CYDEV_CHIP_FAMILY_FM4 EQU 7
 CYDEV_CHIP_FAMILY_PSOC3 EQU 1
 CYDEV_CHIP_FAMILY_PSOC4 EQU 2
 CYDEV_CHIP_FAMILY_PSOC5 EQU 3
+CYDEV_CHIP_FAMILY_PSOC6 EQU 4
 CYDEV_CHIP_FAMILY_UNKNOWN EQU 0
 CYDEV_CHIP_FAMILY_USED EQU CYDEV_CHIP_FAMILY_PSOC5
 CYDEV_CHIP_JTAG_ID EQU 0x2E133069
 CYDEV_CHIP_MEMBER_3A EQU 1
-CYDEV_CHIP_MEMBER_4A EQU 12
-CYDEV_CHIP_MEMBER_4C EQU 18
-CYDEV_CHIP_MEMBER_4D EQU 8
-CYDEV_CHIP_MEMBER_4E EQU 4
-CYDEV_CHIP_MEMBER_4F EQU 13
-CYDEV_CHIP_MEMBER_4G EQU 2
-CYDEV_CHIP_MEMBER_4H EQU 11
-CYDEV_CHIP_MEMBER_4I EQU 17
-CYDEV_CHIP_MEMBER_4J EQU 9
-CYDEV_CHIP_MEMBER_4K EQU 10
-CYDEV_CHIP_MEMBER_4L EQU 16
-CYDEV_CHIP_MEMBER_4M EQU 15
-CYDEV_CHIP_MEMBER_4N EQU 6
-CYDEV_CHIP_MEMBER_4O EQU 5
-CYDEV_CHIP_MEMBER_4P EQU 14
-CYDEV_CHIP_MEMBER_4Q EQU 7
-CYDEV_CHIP_MEMBER_4U EQU 3
-CYDEV_CHIP_MEMBER_5A EQU 20
-CYDEV_CHIP_MEMBER_5B EQU 19
-CYDEV_CHIP_MEMBER_FM3 EQU 24
-CYDEV_CHIP_MEMBER_FM4 EQU 25
-CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE1 EQU 21
-CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE2 EQU 22
-CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE3 EQU 23
+CYDEV_CHIP_MEMBER_4A EQU 16
+CYDEV_CHIP_MEMBER_4D EQU 12
+CYDEV_CHIP_MEMBER_4E EQU 6
+CYDEV_CHIP_MEMBER_4F EQU 17
+CYDEV_CHIP_MEMBER_4G EQU 4
+CYDEV_CHIP_MEMBER_4H EQU 15
+CYDEV_CHIP_MEMBER_4I EQU 21
+CYDEV_CHIP_MEMBER_4J EQU 13
+CYDEV_CHIP_MEMBER_4K EQU 14
+CYDEV_CHIP_MEMBER_4L EQU 20
+CYDEV_CHIP_MEMBER_4M EQU 19
+CYDEV_CHIP_MEMBER_4N EQU 9
+CYDEV_CHIP_MEMBER_4O EQU 7
+CYDEV_CHIP_MEMBER_4P EQU 18
+CYDEV_CHIP_MEMBER_4Q EQU 11
+CYDEV_CHIP_MEMBER_4R EQU 8
+CYDEV_CHIP_MEMBER_4S EQU 10
+CYDEV_CHIP_MEMBER_4U EQU 5
+CYDEV_CHIP_MEMBER_5A EQU 3
+CYDEV_CHIP_MEMBER_5B EQU 2
+CYDEV_CHIP_MEMBER_6A EQU 22
+CYDEV_CHIP_MEMBER_FM3 EQU 26
+CYDEV_CHIP_MEMBER_FM4 EQU 27
+CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE1 EQU 23
+CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE2 EQU 24
+CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE3 EQU 25
 CYDEV_CHIP_MEMBER_UNKNOWN EQU 0
 CYDEV_CHIP_MEMBER_USED EQU CYDEV_CHIP_MEMBER_5B
 CYDEV_CHIP_DIE_EXPECT EQU CYDEV_CHIP_MEMBER_USED
@@ -2681,7 +2661,6 @@ CYDEV_CHIP_REVISION_3A_ES3 EQU 3
 CYDEV_CHIP_REVISION_3A_PRODUCTION EQU 3
 CYDEV_CHIP_REVISION_4A_ES0 EQU 17
 CYDEV_CHIP_REVISION_4A_PRODUCTION EQU 17
-CYDEV_CHIP_REVISION_4C_PRODUCTION EQU 0
 CYDEV_CHIP_REVISION_4D_PRODUCTION EQU 0
 CYDEV_CHIP_REVISION_4E_PRODUCTION EQU 0
 CYDEV_CHIP_REVISION_4F_PRODUCTION EQU 0
@@ -2700,12 +2679,16 @@ CYDEV_CHIP_REVISION_4N_PRODUCTION EQU 0
 CYDEV_CHIP_REVISION_4O_PRODUCTION EQU 0
 CYDEV_CHIP_REVISION_4P_PRODUCTION EQU 0
 CYDEV_CHIP_REVISION_4Q_PRODUCTION EQU 0
+CYDEV_CHIP_REVISION_4R_PRODUCTION EQU 0
+CYDEV_CHIP_REVISION_4S_PRODUCTION EQU 0
 CYDEV_CHIP_REVISION_4U_PRODUCTION EQU 0
 CYDEV_CHIP_REVISION_5A_ES0 EQU 0
 CYDEV_CHIP_REVISION_5A_ES1 EQU 1
 CYDEV_CHIP_REVISION_5A_PRODUCTION EQU 1
 CYDEV_CHIP_REVISION_5B_ES0 EQU 0
 CYDEV_CHIP_REVISION_5B_PRODUCTION EQU 0
+CYDEV_CHIP_REVISION_6A_NO_UDB EQU 0
+CYDEV_CHIP_REVISION_6A_PRODUCTION EQU 0
 CYDEV_CHIP_REVISION_FM3_PRODUCTION EQU 0
 CYDEV_CHIP_REVISION_FM4_PRODUCTION EQU 0
 CYDEV_CHIP_REVISION_PDL_FM0P_TYPE1_PRODUCTION EQU 0
@@ -2737,7 +2720,7 @@ CYDEV_DMA_CHANNELS_AVAILABLE EQU 24
 CYDEV_ECC_ENABLE EQU 0
 CYDEV_HEAP_SIZE EQU 0x0400
 CYDEV_INSTRUCT_CACHE_ENABLED EQU 1
-CYDEV_INTR_RISING EQU 0x0000007E
+CYDEV_INTR_RISING EQU 0x0000007F
 CYDEV_IS_EXPORTING_CODE EQU 0
 CYDEV_IS_IMPORTING_CODE EQU 0
 CYDEV_PROJ_TYPE EQU 2

diff --git a/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/cymetadata.c b/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/cymetadata.c
index 25c6a2d0e7dd875e9d60a91b40f3704969e16730..335a95068764a8d4b29da7d5f21d6791ee25f916 100755 (executable)
--- a/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/cymetadata.c
+++ b/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/cymetadata.c
@@ -1,21 +1,21 @@
 /*******************************************************************************
 * File Name: cymetadata.c
 * 
-* PSoC Creator  4.0 Update 1
+* PSoC Creator  4.1
 *
 * Description:
 * This file defines all extra memory spaces that need to be included.
 * This file is automatically generated by PSoC Creator.
 *
 ********************************************************************************
-* Copyright (c) 2007-2016 Cypress Semiconductor.  All rights reserved.
+* Copyright (c) 2007-2017 Cypress Semiconductor.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions, 
 * disclaimers, and limitations in the end user license agreement accompanying 
 * the software package with which this file was provided.
 ********************************************************************************/
 
 
-#include "cytypes.h"
+#include "stdint.h"
 
 
 #if defined(__GNUC__) || defined(__ARMCC_VERSION)
@@ -28,7 +28,7 @@ CY_LOADABLE_META_SECTION
 #else
 #error "Unsupported toolchain"
 #endif
-const uint8 cy_meta_loadable[] = {
+const uint8_t cy_meta_loadable[] = {
     0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
     0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
     0x00u, 0x00u, 0x00u, 0x00u, 0x5Cu, 0xD1u, 0x10u, 0x05u,
@@ -49,6 +49,6 @@ CY_CONFIG_ECC_SECTION
 #else
 #error "Unsupported toolchain"
 #endif
-const uint8 cy_meta_configecc[] = {
+const uint8_t cy_meta_configecc[] = {
     0x00u
 };

diff --git a/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/project.h b/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/project.h
index a26a4fb0ef195bbcde72e7323783cc95ac4f56ca..66447c7bb171df8405b1e69f2cf73acda0c1015e 100755 (executable)
--- a/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/project.h
+++ b/software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/project.h
@@ -1,14 +1,14 @@
 /*******************************************************************************
 * File Name: project.h
 * 
-* PSoC Creator  4.0 Update 1
+* PSoC Creator  4.1
 *
 * Description:
 * It contains references to all generated header files and should not be modified.
 * This file is automatically generated by PSoC Creator.
 *
 ********************************************************************************
-* Copyright (c) 2007-2016 Cypress Semiconductor.  All rights reserved.
+* Copyright (c) 2007-2017 Cypress Semiconductor.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions, 
 * disclaimers, and limitations in the end user license agreement accompanying 
 * the software package with which this file was provided.

diff --git a/software/SCSI2SD/v5.1/SCSI2SD.cydsn/SCSI2SD.cyfit b/software/SCSI2SD/v5.1/SCSI2SD.cydsn/SCSI2SD.cyfit
index 47d2aca571bf619d983062342d9f208a2a317ff7..ff02c0cdc5c0d568d992b82ba774e6973ce6e693 100644 (file)
Binary files a/software/SCSI2SD/v5.1/SCSI2SD.cydsn/SCSI2SD.cyfit and b/software/SCSI2SD/v5.1/SCSI2SD.cydsn/SCSI2SD.cyfit differ

diff --git a/software/SCSI2SD/v5.1/SCSI2SD.cydsn/SCSI2SD.cyprj b/software/SCSI2SD/v5.1/SCSI2SD.cydsn/SCSI2SD.cyprj
index d14bc6aaa3495304e8513c136658cb3a07a2147c..ed402967204f206df6a829ef5c12038272415121 100755 (executable)
--- a/software/SCSI2SD/v5.1/SCSI2SD.cydsn/SCSI2SD.cyprj
+++ b/software/SCSI2SD/v5.1/SCSI2SD.cydsn/SCSI2SD.cyprj
@@ -4,14 +4,14 @@
 <!--Due to this, there is no schema for this file.-->
 <CyGuid_fec8f9e8-2365-4bdb-96d3-a4380222e01b type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtProjectPSoCExeSerialize" version="4">
 <CyGuid_60697ce6-dce2-4816-8680-4de0635742eb type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtProjectExeSerialize" version="3">
-<CyGuid_49cfd574-032a-4a64-b7be-d4eeeaf25e43 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtProjectSerialize" version="7" xml_contents_version="1">
+<CyGuid_49cfd574-032a-4a64-b7be-d4eeeaf25e43 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtProjectSerialize" version="8" xml_contents_version="1">
 <CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtBaseContainerSerialize" version="1">
 <CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItemSerialize" version="2" name="SCSI2SD" persistent="SCSI2SD.cyprj">
 <Hidden v="False" />
 </CyGuid_31768f72-0253-412b-af77-e7dba74d1330>
 <CyGuid_0820c2e7-528d-4137-9a08-97257b946089 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItemListSerialize" version="2">
 <dependencies>
-<CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFolderSerialize" version="2">
+<CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFolderSerialize" version="3">
 <CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtBaseContainerSerialize" version="1">
 <CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItemSerialize" version="2" name="Source Files" persistent="">
 <Hidden v="False" />
@@ -161,7 +161,7 @@
 <filter v="a51" />
 </filters>
 </CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0>
-<CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFolderSerialize" version="2">
+<CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFolderSerialize" version="3">
 <CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtBaseContainerSerialize" version="1">
 <CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItemSerialize" version="2" name="Header Files" persistent="">
 <Hidden v="False" />
@@ -331,7 +331,7 @@
 </CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0>
 <CyGuid_4429d4ed-fe84-42d0-9e9f-19aee0ff4e7e type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtComponentSerialize" version="1">
 <CyGuid_813b8d13-518a-4dc8-91ba-cda6042dfb52 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtPhysicalFolderSerialize" version="1">
-<CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFolderSerialize" version="2">
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@@ -2090,7 +2090,7 @@
 </CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8>
 <filters />
 </CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0>
-<CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFolderSerialize" version="2">
+<CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFolderSerialize" version="3">
 <CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtBaseContainerSerialize" version="1">
 <CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItemSerialize" version="2" name="SCSI_Glitch_Ctrl" persistent="">
 <Hidden v="True" />
@@ -2116,7 +2116,7 @@
 </CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8>
 <filters />
 </CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0>
-<CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFolderSerialize" version="2">
+<CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFolderSerialize" version="3">
 <CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtBaseContainerSerialize" version="1">
 <CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItemSerialize" version="2" name="SCSI_Glitch_Ctl" persistent="">
 <Hidden v="False" />
@@ -2170,7 +2170,7 @@
 <build_action v="OTHER;;;;" />
 <PropertyDeltas />
 </CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b>
-<CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFolderSerialize" version="2">
+<CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFolderSerialize" version="3">
 <CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtBaseContainerSerialize" version="1">
 <CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItemSerialize" version="2" name="TERM_EN" persistent="">
 <Hidden v="False" />
@@ -2219,7 +2219,7 @@
 </CyGuid_d8451a8e-a4ea-4e21-aba8-966eaa7ea07d>
 <CyGuid_4429d4ed-fe84-42d0-9e9f-19aee0ff4e7e type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtComponentSerialize" version="1">
 <CyGuid_813b8d13-518a-4dc8-91ba-cda6042dfb52 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtPhysicalFolderSerialize" version="1">
-<CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFolderSerialize" version="2">
+<CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFolderSerialize" version="3">
 <CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtBaseContainerSerialize" version="1">
 <CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItemSerialize" version="2" name="OddParityGen" persistent="OddParityGen">
 <Hidden v="False" />
@@ -2249,7 +2249,7 @@
 </CyGuid_4429d4ed-fe84-42d0-9e9f-19aee0ff4e7e>
 <CyGuid_4429d4ed-fe84-42d0-9e9f-19aee0ff4e7e type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtComponentSerialize" version="1">
 <CyGuid_813b8d13-518a-4dc8-91ba-cda6042dfb52 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtPhysicalFolderSerialize" version="1">
-<CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFolderSerialize" version="2">
+<CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFolderSerialize" version="3">
 <CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtBaseContainerSerialize" version="1">
 <CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItemSerialize" version="2" name="scsiTarget" persistent="scsiTarget">
 <Hidden v="False" />
@@ -2328,10 +2328,10 @@
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@C/C++@General@Struct Return Method" v="System Default" />
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@C/C++@General@Verbose Asm" v="False" />
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@C/C++@Optimization@Remove Unused Functions" v="True" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@C/C++@Optimization@Fat LTO objects" v="True" />
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@C/C++@Optimization@Inline Functions" v="False" />
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@C/C++@Optimization@Optimization Level" v="None" />
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@C/C++@Optimization@Link Time Optimization" v="False" />
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@C/C++@Optimization@Fat LTO objects" v="True" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@C/C++@Optimization@Optimization Level" v="None" />
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@C/C++@Command Line@Command Line" v="" />
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Library Generation@Command Line@Command Line" v="" />
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Linker@General@Additional Libraries" v="" />
@@ -2344,6 +2344,15 @@
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Linker@General@Enable Float printf" v="False" />
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Linker@Optimization@Remove Unused Functions" v="True" />
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Linker@Command Line@Command Line" v="" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Linker@Optimization@SHARED Generate Debugging Information" v="" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Linker@Optimization@SHARED Struct Return Method" v="" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Linker@Optimization@SHARED Remove Unused Functions" v="" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Linker@Optimization@SHARED Inline Functions" v="" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Linker@Optimization@SHARED Optimization Level" v="" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Linker@Optimization@SHARED Link Time Optimization" v="" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Linker@Optimization@SHARED Fat LTO objects" v="" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@User Commands@General@Pre Build Commands" v="" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@User Commands@General@Post Build Commands" v="" />
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@General@Output Directory" v="${ProjectDir}\${ProcessorType}\${Platform}\${Config}" />
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@Assembly@General@Additional Include Directories" v="" />
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@Assembly@General@Create Listing File" v="True" />
@@ -2362,10 +2371,10 @@
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@C/C++@General@Struct Return Method" v="System Default" />
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@C/C++@General@Verbose Asm" v="False" />
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@C/C++@Optimization@Remove Unused Functions" v="True" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@C/C++@Optimization@Fat LTO objects" v="True" />
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@C/C++@Optimization@Inline Functions" v="False" />
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@C/C++@Optimization@Optimization Level" v="Size" />
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@C/C++@Optimization@Link Time Optimization" v="False" />
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@C/C++@Optimization@Fat LTO objects" v="True" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@C/C++@Optimization@Optimization Level" v="Size" />
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@C/C++@Command Line@Command Line" v="" />
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@Library Generation@Command Line@Command Line" v="" />
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@Linker@General@Additional Libraries" v="" />
@@ -2378,6 +2387,15 @@
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@Linker@General@Enable Float printf" v="False" />
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@Linker@Optimization@Remove Unused Functions" v="True" />
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@Linker@Command Line@Command Line" v="" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@Linker@Optimization@SHARED Generate Debugging Information" v="" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@Linker@Optimization@SHARED Struct Return Method" v="" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@Linker@Optimization@SHARED Remove Unused Functions" v="" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@Linker@Optimization@SHARED Inline Functions" v="" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@Linker@Optimization@SHARED Optimization Level" v="" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@Linker@Optimization@SHARED Link Time Optimization" v="" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@Linker@Optimization@SHARED Fat LTO objects" v="" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@User Commands@General@Pre Build Commands" v="" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@User Commands@General@Post Build Commands" v="" />
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@General@Output Directory" v="${ProjectDir}\${ProcessorType}\${Platform}\${Config}" />
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@Assembly@General@Additional Include Directories" v="" />
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@Assembly@General@Create Listing File" v="True" />
@@ -2396,10 +2414,10 @@
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 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@C/C++@General@Verbose Asm" v="False" />
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@C/C++@Optimization@Remove Unused Functions" v="True" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@C/C++@Optimization@Fat LTO objects" v="True" />
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@C/C++@Optimization@Inline Functions" v="False" />
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@C/C++@Optimization@Optimization Level" v="None" />
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@C/C++@Optimization@Link Time Optimization" v="False" />
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@C/C++@Optimization@Fat LTO objects" v="True" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@C/C++@Optimization@Optimization Level" v="None" />
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@C/C++@Command Line@Command Line" v="" />
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@Library Generation@Command Line@Command Line" v="" />
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@Linker@General@Additional Libraries" v="" />
@@ -2412,6 +2430,15 @@
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 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@Linker@Optimization@Remove Unused Functions" v="True" />
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@Linker@Command Line@Command Line" v="" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@Linker@Optimization@SHARED Generate Debugging Information" v="" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@Linker@Optimization@SHARED Struct Return Method" v="" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@Linker@Optimization@SHARED Remove Unused Functions" v="" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@Linker@Optimization@SHARED Inline Functions" v="" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@Linker@Optimization@SHARED Optimization Level" v="" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@Linker@Optimization@SHARED Link Time Optimization" v="" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@Linker@Optimization@SHARED Fat LTO objects" v="" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@User Commands@General@Pre Build Commands" v="" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@User Commands@General@Post Build Commands" v="" />
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@General@Output Directory" v="${ProjectDir}\${ProcessorType}\${Platform}\${Config}" />
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@Assembly@General@Additional Include Directories" v="" />
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@Assembly@General@Create Listing File" v="True" />
@@ -2430,10 +2457,10 @@
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 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@C/C++@General@Verbose Asm" v="False" />
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@C/C++@Optimization@Remove Unused Functions" v="True" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@C/C++@Optimization@Fat LTO objects" v="True" />
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@C/C++@Optimization@Inline Functions" v="True" />
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@C/C++@Optimization@Optimization Level" v="Size" />
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@C/C++@Optimization@Link Time Optimization" v="False" />
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@C/C++@Optimization@Fat LTO objects" v="True" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@C/C++@Optimization@Optimization Level" v="Size" />
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@C/C++@Command Line@Command Line" v="" />
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@Library Generation@Command Line@Command Line" v="" />
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@Linker@General@Additional Libraries" v="" />
@@ -2446,6 +2473,15 @@
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 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@Linker@Optimization@Remove Unused Functions" v="True" />
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@Linker@Command Line@Command Line" v="" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@Linker@Optimization@SHARED Generate Debugging Information" v="" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@Linker@Optimization@SHARED Struct Return Method" v="" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@Linker@Optimization@SHARED Remove Unused Functions" v="" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@Linker@Optimization@SHARED Inline Functions" v="" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@Linker@Optimization@SHARED Optimization Level" v="" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@Linker@Optimization@SHARED Link Time Optimization" v="" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@Linker@Optimization@SHARED Fat LTO objects" v="" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@User Commands@General@Pre Build Commands" v="" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@User Commands@General@Post Build Commands" v="" />
 </name>
 </platform>
 <platform>
@@ -2468,10 +2504,10 @@
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM0@C/C++@General@Struct Return Method" v="System Default" />
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM0@C/C++@General@Verbose Asm" v="False" />
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM0@C/C++@Optimization@Remove Unused Functions" v="True" />
+<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM0@C/C++@Optimization@Fat LTO objects" v="True" />
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM0@C/C++@Optimization@Inline Functions" v="False" />
-<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM0@C/C++@Optimization@Optimization Level" v="None" />
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM0@C/C++@Optimization@Link Time Optimization" v="False" />
-<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM0@C/C++@Optimization@Fat LTO objects" v="True" />
+<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM0@C/C++@Optimization@Optimization Level" v="None" />
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM0@C/C++@Command Line@Command Line" v="" />
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM0@Library Generation@Command Line@Command Line" v="" />
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM0@Linker@General@Additional Libraries" v="" />
@@ -2484,6 +2520,15 @@
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM0@Linker@General@Enable Float printf" v="False" />
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM0@Linker@Optimization@Remove Unused Functions" v="True" />
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM0@Linker@Command Line@Command Line" v="" />
+<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM0@Linker@Optimization@SHARED Generate Debugging Information" v="" />
+<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM0@Linker@Optimization@SHARED Struct Return Method" v="" />
+<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM0@Linker@Optimization@SHARED Remove Unused Functions" v="" />
+<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM0@Linker@Optimization@SHARED Inline Functions" v="" />
+<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM0@Linker@Optimization@SHARED Optimization Level" v="" />
+<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM0@Linker@Optimization@SHARED Link Time Optimization" v="" />
+<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM0@Linker@Optimization@SHARED Fat LTO objects" v="" />
+<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM0@User Commands@General@Pre Build Commands" v="" />
+<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM0@User Commands@General@Post Build Commands" v="" />
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM0@General@Output Directory" v="${ProjectDir}\${ProcessorType}\${Platform}\${Config}" />
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM0@Assembly@General@Additional Include Directories" v="" />
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM0@Assembly@General@Create Listing File" v="True" />
@@ -2502,10 +2547,10 @@
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM0@C/C++@General@Struct Return Method" v="System Default" />
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM0@C/C++@General@Verbose Asm" v="False" />
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM0@C/C++@Optimization@Remove Unused Functions" v="True" />
+<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM0@C/C++@Optimization@Fat LTO objects" v="True" />
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM0@C/C++@Optimization@Inline Functions" v="False" />
-<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM0@C/C++@Optimization@Optimization Level" v="Size" />
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM0@C/C++@Optimization@Link Time Optimization" v="False" />
-<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM0@C/C++@Optimization@Fat LTO objects" v="True" />
+<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM0@C/C++@Optimization@Optimization Level" v="Size" />
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM0@C/C++@Command Line@Command Line" v="" />
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM0@Library Generation@Command Line@Command Line" v="" />
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM0@Linker@General@Additional Libraries" v="" />
@@ -2518,6 +2563,15 @@
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM0@Linker@General@Enable Float printf" v="False" />
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM0@Linker@Optimization@Remove Unused Functions" v="True" />
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM0@Linker@Command Line@Command Line" v="" />
+<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM0@Linker@Optimization@SHARED Generate Debugging Information" v="" />
+<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM0@Linker@Optimization@SHARED Struct Return Method" v="" />
+<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM0@Linker@Optimization@SHARED Remove Unused Functions" v="" />
+<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM0@Linker@Optimization@SHARED Inline Functions" v="" />
+<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM0@Linker@Optimization@SHARED Optimization Level" v="" />
+<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM0@Linker@Optimization@SHARED Link Time Optimization" v="" />
+<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM0@Linker@Optimization@SHARED Fat LTO objects" v="" />
+<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM0@User Commands@General@Pre Build Commands" v="" />
+<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM0@User Commands@General@Post Build Commands" v="" />
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM3@General@Output Directory" v="${ProjectDir}\${ProcessorType}\${Platform}\${Config}" />
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM3@Assembly@General@Additional Include Directories" v="" />
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM3@Assembly@General@Create Listing File" v="True" />
@@ -2536,10 +2590,10 @@
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM3@C/C++@General@Struct Return Method" v="System Default" />
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM3@C/C++@General@Verbose Asm" v="False" />
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM3@C/C++@Optimization@Remove Unused Functions" v="True" />
+<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM3@C/C++@Optimization@Fat LTO objects" v="True" />
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM3@C/C++@Optimization@Inline Functions" v="False" />
-<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM3@C/C++@Optimization@Optimization Level" v="None" />
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM3@C/C++@Optimization@Link Time Optimization" v="False" />
-<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM3@C/C++@Optimization@Fat LTO objects" v="True" />
+<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM3@C/C++@Optimization@Optimization Level" v="None" />
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM3@C/C++@Command Line@Command Line" v="" />
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM3@Library Generation@Command Line@Command Line" v="" />
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM3@Linker@General@Additional Libraries" v="" />
@@ -2552,6 +2606,15 @@
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM3@Linker@General@Enable Float printf" v="False" />
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM3@Linker@Optimization@Remove Unused Functions" v="True" />
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM3@Linker@Command Line@Command Line" v="" />
+<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM3@Linker@Optimization@SHARED Generate Debugging Information" v="" />
+<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM3@Linker@Optimization@SHARED Struct Return Method" v="" />
+<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM3@Linker@Optimization@SHARED Remove Unused Functions" v="" />
+<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM3@Linker@Optimization@SHARED Inline Functions" v="" />
+<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM3@Linker@Optimization@SHARED Optimization Level" v="" />
+<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM3@Linker@Optimization@SHARED Link Time Optimization" v="" />
+<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM3@Linker@Optimization@SHARED Fat LTO objects" v="" />
+<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM3@User Commands@General@Pre Build Commands" v="" />
+<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM3@User Commands@General@Post Build Commands" v="" />
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM3@General@Output Directory" v="${ProjectDir}\${ProcessorType}\${Platform}\${Config}" />
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM3@Assembly@General@Additional Include Directories" v="" />
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM3@Assembly@General@Create Listing File" v="True" />
@@ -2570,10 +2633,10 @@
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM3@C/C++@General@Struct Return Method" v="System Default" />
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM3@C/C++@General@Verbose Asm" v="False" />
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM3@C/C++@Optimization@Remove Unused Functions" v="True" />
+<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM3@C/C++@Optimization@Fat LTO objects" v="True" />
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM3@C/C++@Optimization@Inline Functions" v="False" />
-<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM3@C/C++@Optimization@Optimization Level" v="Size" />
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM3@C/C++@Optimization@Link Time Optimization" v="False" />
-<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM3@C/C++@Optimization@Fat LTO objects" v="True" />
+<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM3@C/C++@Optimization@Optimization Level" v="Size" />
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM3@C/C++@Command Line@Command Line" v="" />
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM3@Library Generation@Command Line@Command Line" v="" />
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM3@Linker@General@Additional Libraries" v="" />
@@ -2586,14 +2649,31 @@
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM3@Linker@General@Enable Float printf" v="False" />
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM3@Linker@Optimization@Remove Unused Functions" v="True" />
 <name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM3@Linker@Command Line@Command Line" v="" />
+<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM3@Linker@Optimization@SHARED Generate Debugging Information" v="" />
+<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM3@Linker@Optimization@SHARED Struct Return Method" v="" />
+<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM3@Linker@Optimization@SHARED Remove Unused Functions" v="" />
+<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM3@Linker@Optimization@SHARED Inline Functions" v="" />
+<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM3@Linker@Optimization@SHARED Optimization Level" v="" />
+<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM3@Linker@Optimization@SHARED Link Time Optimization" v="" />
+<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM3@Linker@Optimization@SHARED Fat LTO objects" v="" />
+<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM3@User Commands@General@Pre Build Commands" v="" />
+<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM3@User Commands@General@Post Build Commands" v="" />
 </name>
 </platform>
 <platform>
 <name v="5bca58cd-5542-421c-b08d-9513dbb687fd">
 <name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Debug@CortexM0@General@Output Directory" v="${ProjectDir}\${ProcessorType}\${Platform}\${Config}" />
+<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Debug@CortexM0@User Commands@General@Pre Build Commands" v="" />
+<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Debug@CortexM0@User Commands@General@Post Build Commands" v="" />
 <name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Release@CortexM0@General@Output Directory" v="${ProjectDir}\${ProcessorType}\${Platform}\${Config}" />
+<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Release@CortexM0@User Commands@General@Pre Build Commands" v="" />
+<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Release@CortexM0@User Commands@General@Post Build Commands" v="" />
 <name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Debug@CortexM3@General@Output Directory" v="${ProjectDir}\${ProcessorType}\${Platform}\${Config}" />
+<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Debug@CortexM3@User Commands@General@Pre Build Commands" v="" />
+<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Debug@CortexM3@User Commands@General@Post Build Commands" v="" />
 <name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Release@CortexM3@General@Output Directory" v="${ProjectDir}\${ProcessorType}\${Platform}\${Config}" />
+<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Release@CortexM3@User Commands@General@Pre Build Commands" v="" />
+<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Release@CortexM3@User Commands@General@Post Build Commands" v="" />
 </name>
 </platform>
 <platform>
@@ -2604,6 +2684,7 @@
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM0@Assembly@General@Suppress Warnings" v="False" />
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM0@Assembly@General@Generate List Files" v="True" />
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM0@Assembly@Command Line@Command Line" v="" />
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM0@Assembly@General@SHARED Use MicroLib" v="" />
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM0@C/C++@General@Additional Include Directories" v="" />
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM0@C/C++@General@Generate List Files" v="True" />
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM0@C/C++@General@Default Char Unsigned" v="False" />
@@ -2614,6 +2695,7 @@
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM0@C/C++@Optimization@Optimization Level" v="None" />
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM0@C/C++@Optimization@Split Sections" v="True" />
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM0@C/C++@Command Line@Command Line" v="" />
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM0@C/C++@General@SHARED Use MicroLib" v="" />
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM0@Library Generation@Command Line@Command Line" v="" />
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM0@Linker@General@Additional Libraries" v="" />
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM0@Linker@General@Additional Library Directories" v="" />
@@ -2623,12 +2705,15 @@
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM0@Linker@General@Generate Debugging Information" v="True" />
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 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM0@Linker@Command Line@Command Line" v="" />
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM0@User Commands@General@Pre Build Commands" v="" />
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM0@User Commands@General@Post Build Commands" v="" />
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM0@General@Output Directory" v="${ProjectDir}\${ProcessorType}\${Platform}\${Config}" />
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 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM0@Assembly@Command Line@Command Line" v="" />
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM0@Assembly@General@SHARED Use MicroLib" v="" />
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM0@C/C++@General@Additional Include Directories" v="" />
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@@ -2639,6 +2724,7 @@
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 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM0@C/C++@Command Line@Command Line" v="" />
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM0@C/C++@General@SHARED Use MicroLib" v="" />
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 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM0@Linker@General@Additional Library Directories" v="" />
@@ -2648,12 +2734,15 @@
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+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM0@User Commands@General@Pre Build Commands" v="" />
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM0@User Commands@General@Post Build Commands" v="" />
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM3@General@Output Directory" v="${ProjectDir}\${ProcessorType}\${Platform}\${Config}" />
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 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM3@Assembly@General@Generate Debugging Information" v="True" />
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 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM3@Assembly@Command Line@Command Line" v="" />
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM3@Assembly@General@SHARED Use MicroLib" v="" />
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@@ -2664,6 +2753,7 @@
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 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM3@C/C++@Command Line@Command Line" v="" />
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM3@C/C++@General@SHARED Use MicroLib" v="" />
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@@ -2673,12 +2763,15 @@
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 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM3@Linker@Command Line@Command Line" v="" />
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM3@User Commands@General@Pre Build Commands" v="" />
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM3@User Commands@General@Post Build Commands" v="" />
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 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@Assembly@Command Line@Command Line" v="" />
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@Assembly@General@SHARED Use MicroLib" v="" />
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@C/C++@General@Additional Include Directories" v="" />
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@@ -2689,6 +2782,7 @@
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 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@C/C++@Optimization@Split Sections" v="True" />
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@C/C++@Command Line@Command Line" v="" />
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@C/C++@General@SHARED Use MicroLib" v="" />
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 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@Linker@General@Additional Library Directories" v="" />
@@ -2698,31 +2792,33 @@
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+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@User Commands@General@Pre Build Commands" v="" />
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@User Commands@General@Post Build Commands" v="" />
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