-2019XXXX 4.9.X
+20190610 4.8.3
- Improve XEBEC controller support
- Add Flexible Disk Drive Geometry SCSI MODE page
+ - Fix SD card hotswap bug
+ - Add scsi mode page 0 support
+ - Fix regression for EMU EMAX
20180926 4.8.1
- Fix bug when writing with multiple SCSI devices on the chain
\r
#include <string.h>\r
\r
-static const uint16_t FIRMWARE_VERSION = 0x0482;\r
+static const uint16_t FIRMWARE_VERSION = 0x0483;\r
\r
// 1 flash row\r
static const uint8_t DEFAULT_CONFIG[256] =\r
--- /dev/null
+/***************************************************************************//**
+* \file cy_em_eeprom.c
+* \version 2.0
+*
+* \brief
+* This file provides source code of the API for the Emulated EEPROM library.
+* The Emulated EEPROM API allows creating of an emulated EEPROM in flash that
+* has the ability to do wear leveling and restore corrupted data from a
+* redundant copy.
+*
+********************************************************************************
+* \copyright
+* Copyright 2017, Cypress Semiconductor Corporation. All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions,
+* disclaimers, and limitations in the end user license agreement accompanying
+* the software package with which this file was provided.
+*******************************************************************************/
+
+
+#include "cytypes.h"
+#include <string.h>
+
+#if (CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC6)
+ #include "em_eeprom/cy_em_eeprom.h"
+#else
+ #include "cy_em_eeprom.h"
+#endif /* (CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC6) */
+
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+
+/***************************************
+* Private Function Prototypes
+***************************************/
+static void FindLastWrittenRow(uint32 * lastWrRowPtr, cy_stc_eeprom_context_t * context);
+static uint32 GetRowAddrBySeqNum(uint32 seqNum, cy_stc_eeprom_context_t * context);
+static uint8 CalcChecksum(uint8 rowData[], uint32 len);
+static void GetNextRowToWrite(uint32 seqNum,
+ uint32 * rowToWrPtr,
+ uint32 * rowToRdPtr,
+ cy_stc_eeprom_context_t * context);
+static cy_en_em_eeprom_status_t CheckRanges(cy_stc_eeprom_config_t* config);
+static cy_en_em_eeprom_status_t WriteRow(uint32 rowAddr, uint32 *rowData, cy_stc_eeprom_context_t * context);
+static cy_en_em_eeprom_status_t EraseRow(uint32 rowAddr, uint32 ramBuffAddr, cy_stc_eeprom_context_t * context);
+static cy_en_em_eeprom_status_t CheckCrcAndCopy(uint32 startAddr,
+ uint32 dstAddr,
+ uint32 rowOffset,
+ uint32 numBytes,
+ cy_stc_eeprom_context_t * context);
+static uint32 GetAddresses(uint32 *startAddr, uint32 *endAddr, uint32 *offset, uint32 rowNum, uint32 addr, uint32 len);
+static cy_en_em_eeprom_status_t FillChecksum(cy_stc_eeprom_context_t * context);
+
+/**
+* \addtogroup group_em_eeprom_functions
+* \{
+*/
+
+/*******************************************************************************
+* Function Name: Cy_Em_EEPROM_Init
+****************************************************************************//**
+*
+* Initializes the Emulated EEPROM library by filling the context structure.
+*
+* \param config
+* The pointer to a configuration structure. See \ref cy_stc_eeprom_config_t.
+*
+* \param context
+* The pointer to the EEPROM context structure to be filled by the function.
+* \ref cy_stc_eeprom_context_t.
+*
+* \return
+* error / status code. See \ref cy_en_em_eeprom_status_t.
+*
+* \note
+* The context structure should not be modified by the user after it is filled
+* with this function. Modification of context structure may cause the
+* unexpected behavior of the Cy_Em_EEPROM API functions which rely on it.
+*
+* \note
+* This function uses a buffer of the flash row size to perform read
+* operation. For the size of the row refer to the specific PSoC device
+* datasheet.
+*
+* \sideeffect
+* If the "Redundant Copy" option is used, the function performs a number of
+* write operations to the EEPROM to initialize flash rows checksums. Therefore,
+* Cy_Em_EEPROM_NumWrites(), when it is called right after Cy_Em_EEPROM_Init(),
+* will return a non-zero value that identifies the number of writes performed
+* by Cy_Em_EEPROM_Init().
+*
+*******************************************************************************/
+cy_en_em_eeprom_status_t Cy_Em_EEPROM_Init(cy_stc_eeprom_config_t* config, cy_stc_eeprom_context_t * context)
+{
+ cy_en_em_eeprom_status_t ret = CY_EM_EEPROM_BAD_PARAM;
+
+ if((NULL != context) && (NULL != config) && (NULL != ((uint32 *)config->userFlashStartAddr)) &&
+ (config->wearLevelingFactor <= CY_EM_EEPROM_MAX_WEAR_LEVELING_FACTOR) && (config->eepromSize != 0u))
+ {
+ ret = CheckRanges(config);
+
+ if(CY_EM_EEPROM_SUCCESS == ret)
+ {
+ /* Copy the user config structure fields into context */
+ context->eepromSize = config->eepromSize;
+ context->wearLevelingFactor = config->wearLevelingFactor;
+ context->redundantCopy = config->redundantCopy;
+ context->blockingWrite = config->blockingWrite;
+ context->userFlashStartAddr = config->userFlashStartAddr;
+ /* Store frequently used data for internal use */
+ context->numberOfRows = CY_EM_EEPROM_GET_NUM_ROWS_IN_EEPROM(config->eepromSize);
+ context->wlEndAddr = ((CY_EM_EEPROM_GET_EEPROM_SIZE(context->numberOfRows) * config->wearLevelingFactor) +
+ config->userFlashStartAddr);
+ /* Find last written EEPROM row and store it for quick access */
+ FindLastWrittenRow(&context->lastWrRowAddr, context);
+
+ if((0u == CY_EM_EEPROM_GET_SEQ_NUM(context->lastWrRowAddr)) && (0u != context->redundantCopy))
+ {
+ /* Call the function only after device reprogramming in case
+ * if redundant copy is enabled.
+ */
+ ret = FillChecksum(context);
+
+ /* Update the last written EEPROM row for Cy_Em_EEPROM_NumWrites() */
+ FindLastWrittenRow(&context->lastWrRowAddr, context);
+ }
+ }
+ }
+
+ return(ret);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_Em_EEPROM_Read
+****************************************************************************//**
+*
+* This function takes the logical EEPROM address, converts it to the actual
+* physical address where the data is stored and returns the data to the user.
+*
+* \param addr
+* The logical start address in EEPROM to start reading data from.
+*
+* \param eepromData
+* The pointer to a user array to write data to.
+*
+* \param size
+* The amount of data to read.
+*
+* \param context
+* The pointer to the EEPROM context structure \ref cy_stc_eeprom_context_t.
+*
+* \return
+* This function returns \ref cy_en_em_eeprom_status_t.
+*
+* \note
+* This function uses a buffer of the flash row size to perform read
+* operation. For the size of the row refer to the specific PSoC device
+* datasheet.
+*
+* \note
+* In case if redundant copy option is enabled the function may perform writes
+* to EEPROM. This is done in case if the data in the EEPPROM is corrupted and
+* the data in redundant copy is valid based on CRC-8 data integrity check.
+*
+*******************************************************************************/
+cy_en_em_eeprom_status_t Cy_Em_EEPROM_Read(uint32 addr,
+ void * eepromData,
+ uint32 size,
+ cy_stc_eeprom_context_t * context)
+{
+ cy_en_em_eeprom_status_t ret = CY_EM_EEPROM_BAD_PARAM;
+ uint32 i;
+ uint32 numBytesToRead;
+ uint32 curEepromBaseAddr;
+ uint32 curRowOffset;
+ uint32 startRowAddr;
+ uint32 actEepromRowNum;
+ uint32 curRdEepromRowNum = 0u;
+ uint32 dataStartEepromRowNum = 0u;
+ uint32 eeData = (uint32) eepromData; /* To avoid the pointer arithmetic with void */
+
+ /* Validate input parameters */
+ if((0u != size) && ((addr + size) <= (context->eepromSize)) && (NULL != eepromData))
+ {
+ uint32 rdAddr = addr;
+ uint32 rdSize = size;
+ /* Get the sequence number of the last written row */
+ uint32 seqNum = CY_EM_EEPROM_GET_SEQ_NUM(context->lastWrRowAddr);
+ uint32 updateAddrFlag = 0u;
+
+ /* Calculate the number of the row read operations. Currently this only concerns
+ * the reads from the EEPROM data locations.
+ */
+ uint32 numRowReads = ((((rdAddr + rdSize) - 1u) / CY_EM_EEPROM_EEPROM_DATA_LEN) -
+ (rdAddr / CY_EM_EEPROM_EEPROM_DATA_LEN)) + 1u;
+
+ /* Get the address of the first row of the currently active EEPROM sector. If
+ * no wear leveling is used - the EEPROM has only one sector, so use the base
+ * addr stored in "context->userFlashStartAddr".
+ */
+ curEepromBaseAddr = (((context->lastWrRowAddr - context->userFlashStartAddr) /
+ (CY_EM_EEPROM_FLASH_SIZEOF_ROW * context->numberOfRows)) *
+ (CY_EM_EEPROM_FLASH_SIZEOF_ROW * context->numberOfRows)) +
+ context->userFlashStartAddr;
+
+ /* Find the number of the row that contains the start address of the data */
+ for(i = 0u; i < context->numberOfRows; i++)
+ {
+ if(0u != CY_EM_EEPROM_IS_ADDR_IN_ROW_RANGE(rdAddr, i))
+ {
+ dataStartEepromRowNum = i;
+ curRdEepromRowNum = dataStartEepromRowNum;
+ break;
+ }
+ }
+
+ /* Find the row number of the last written row */
+ actEepromRowNum = (context->lastWrRowAddr - curEepromBaseAddr) / CY_EM_EEPROM_FLASH_SIZEOF_ROW;
+
+ /* Check if wear leveling is used */
+ if(context->wearLevelingFactor > 1u)
+ {
+ uint32 dataEndEepromRowNum = dataStartEepromRowNum + (numRowReads - 1u);
+
+ /* Check if the future validation of the read address is required. */
+ updateAddrFlag = (dataStartEepromRowNum > actEepromRowNum) ? 1u :
+ ((dataEndEepromRowNum > actEepromRowNum) ? 1u : 0u);
+ }
+
+ /* Copy data from the EEPROM data locations to the user buffer */
+ for(i = 0u; i < numRowReads; i++)
+ {
+ startRowAddr = curEepromBaseAddr + (curRdEepromRowNum * CY_EM_EEPROM_FLASH_SIZEOF_ROW);
+ curRowOffset = CY_EM_EEPROM_EEPROM_DATA_LEN + (rdAddr % CY_EM_EEPROM_EEPROM_DATA_LEN);
+
+ /* Check if there are more reads pending and update the number of the
+ * remaining bytes to read respectively.
+ */
+ if((i + 1u) < numRowReads)
+ {
+ numBytesToRead = CY_EM_EEPROM_EEPROM_DATA_LEN - (rdAddr % CY_EM_EEPROM_EEPROM_DATA_LEN);
+ }
+ else
+ {
+ numBytesToRead = rdSize;
+ }
+
+ /* Check if the read address needs to be updated to point to the correct
+ * EEPROM sector.
+ */
+ if((0u != updateAddrFlag) && (curRdEepromRowNum > actEepromRowNum))
+ {
+ startRowAddr -= context->numberOfRows * CY_EM_EEPROM_FLASH_SIZEOF_ROW;
+
+ if(startRowAddr < context->userFlashStartAddr)
+ {
+ startRowAddr = context->wlEndAddr -
+ ((context->numberOfRows - curRdEepromRowNum) * CY_EM_EEPROM_FLASH_SIZEOF_ROW);
+ }
+ }
+
+ if(0u != context->redundantCopy)
+ {
+ /* Check a checksum of the EEPROM row and if it is bad, check a checksum in
+ * the corresponding row in redundant copy, otherwise return failure.
+ */
+ ret = CheckCrcAndCopy(startRowAddr, eeData, curRowOffset, numBytesToRead, context);
+
+ if(CY_EM_EEPROM_SUCCESS != ret)
+ {
+ break;
+ }
+ }
+ else
+ {
+ /* Copy the data to the user buffer */
+ (void)memcpy((void *)(eeData),
+ (void *)(startRowAddr + curRowOffset),
+ numBytesToRead);
+
+ /* Indicate success to be able to execute next code block */
+ ret = CY_EM_EEPROM_SUCCESS;
+ }
+
+ /* Update variables anticipated in the read operation */
+ rdAddr += numBytesToRead;
+ rdSize -= numBytesToRead;
+ eeData += numBytesToRead;
+ curRdEepromRowNum++;
+ }
+
+ /* This code block will copy the latest data from the EEPROM headers into the
+ * user buffer. The data previously copied into the user buffer may be updated
+ * as the EEPROM headers contain more recent data.
+ * The code block is executed when two following conditions are true:
+ * 1) The reads from "historic" data locations were successful;
+ * 2) The user performed at least one write operation to Em_EEPROM (0u !=
+ * seqNum).
+ */
+ if((CY_EM_EEPROM_SUCCESS == ret) && (0u != seqNum))
+ {
+ numRowReads = (context->numberOfRows <= seqNum) ? (context->numberOfRows) : (seqNum);
+ numRowReads--;
+
+ for(i = (seqNum - numRowReads); i <= seqNum; i++)
+ {
+ startRowAddr = GetRowAddrBySeqNum(i, context);
+
+ if (0u != startRowAddr)
+ {
+ /* The following variables are introduced to increase code readability. */
+ uint32 startAddr = *(uint32 *)(startRowAddr + CY_EM_EEPROM_HEADER_ADDR_OFFSET);
+ uint32 endAddr = startAddr + (*(uint32 *)(startRowAddr + CY_EM_EEPROM_HEADER_LEN_OFFSET));
+
+ /* Check if the current row EEPROM header contains the data requested for read */
+ if(0u != CY_EM_EEPROM_IS_ADDRESES_CROSSING(startAddr, endAddr, addr, addr + size))
+ {
+ uint32 srcOffset = (startAddr > addr) ? (0u) : (addr - startAddr);
+ uint32 dstOffset = (startAddr > addr) ? (startAddr - addr): (0u);
+ rdAddr = (startAddr > addr) ? (startAddr) : (addr);
+
+ srcOffset += CY_EM_EEPROM_HEADER_DATA_OFFSET;
+
+ /* Calculate the number of bytes to be read from the current row's EEPROM header */
+ numBytesToRead = ((endAddr < (addr + size)) ? endAddr : (addr + size)) - rdAddr;
+
+ /* Calculate the offset in the user buffer from which the data will be updated. */
+ eeData = ((uint32)eepromData) + dstOffset;
+
+ /* Check a checksum of the EEPROM row and if it is bad, check a checksum in the
+ * corresponding row in redundant copy, otherwise return failure. Copy the data
+ * from the recent EEPROM headers to the user buffer. This will overwrite the
+ * data copied form EEPROM data locations as the data in EEPROM headers is newer.
+ */
+ if(0u != context->redundantCopy)
+ {
+ ret = CheckCrcAndCopy(startRowAddr, eeData, srcOffset, numBytesToRead, context);
+
+ if(CY_EM_EEPROM_SUCCESS != ret)
+ {
+ break;
+ }
+ }
+ else
+ {
+ (void)memcpy((void *)(eeData), (void *)(startRowAddr + srcOffset), numBytesToRead);
+ }
+ }
+ }
+ }
+ }
+ }
+
+ return(ret);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_Em_EEPROM_Write
+****************************************************************************//**
+*
+* This function takes the logical EEPROM address and converts it to the actual
+* physical address and writes data there. If wear leveling is implemented, the
+* writing process will use the wear leveling techniques. This is a blocking
+* function and it does not return until the write operation is completed. The
+* user firmware should not enter Hibernate mode until write is completed. The
+* write operation is allowed in Sleep and Deep-Sleep modes. During the flash
+* operation, the device should not be reset, including the XRES pin, a software
+* reset, and watchdog reset sources. Also, low-voltage detect circuits should
+* be configured to generate an interrupt instead of a reset. Otherwise, portions
+* of flash may undergo unexpected changes.
+*
+* \param addr
+* The logical start address in EEPROM to start writing data from.
+*
+* \param eepromData
+* Data to write to EEPROM.
+*
+* \param size
+* The amount of data to write to EEPROM.
+*
+* \param context
+* The pointer to the EEPROM context structure \ref cy_stc_eeprom_context_t.
+*
+* \return
+* This function returns \ref cy_en_em_eeprom_status_t.
+*
+* \note
+* This function uses a buffer of the flash row size to perform write
+* operation. For the size of the row refer to the specific PSoC device
+* datasheet.
+*
+* \sideeffect
+* In case when blocking write option is used, if this function is called by
+* the CM4 the user code on CM0P and the user code on CM4 are blocked until erase
+* flash row operation is finished. If this function is called by the CM0P the
+* user code on CM4 is not blocked and the user code on CM0P is blocked until
+* erase flash row operation is finished. Plan your task allocation accordingly.
+*
+* \sideeffect
+* In case if non-blocking write option is used and when user flash is used as
+* an EEPROM storage care should be taken to prevent the read while write (RWW)
+* exception. To prevent the RWW exception the user flash macro that includes
+* the EEPROM storage should not be read while the EEPROM write is not completed.
+* The read also means the user code execution from the respective flash macro.
+*
+*******************************************************************************/
+cy_en_em_eeprom_status_t Cy_Em_EEPROM_Write(uint32 addr,
+ void * eepromData,
+ uint32 size,
+ cy_stc_eeprom_context_t * context)
+{
+ cy_en_em_eeprom_status_t ret = CY_EM_EEPROM_BAD_PARAM;
+ uint32 i;
+ uint32 wrCnt;
+ uint32 actEmEepromRowNum;
+ uint32 writeRamBuffer[CY_EM_EEPROM_FLASH_SIZEOF_ROW / CY_EM_EEPROM_U32_DIV];
+ uint32 startAddr = 0u;
+ uint32 endAddr = 0u;
+ uint32 tmpRowAddr;
+ uint32 emEepromRowAddr = context->lastWrRowAddr;
+ uint32 emEepromRowRdAddr;
+ void * tmpData;
+ uint32 eeData = (uint32) eepromData; /* To avoid the pointer arithmetic with void */
+
+ /* Check if the EEPROM data does not exceed the EEPROM capacity */
+ if((0u != size) && ((addr + size) <= (context->eepromSize)) && (NULL != eepromData))
+ {
+ uint32 numWrites = ((size - 1u) / CY_EM_EEPROM_HEADER_DATA_LEN) + 1u;
+ uint32 eeHeaderDataOffset = 0u;
+
+ for(wrCnt = 0u; wrCnt < numWrites; wrCnt++)
+ {
+ uint32 skipOperation = 0u;
+ /* Get the sequence number of the last written row */
+ uint32 seqNum = CY_EM_EEPROM_GET_SEQ_NUM(emEepromRowAddr);
+
+ /* Get the address of the row to be written. The "emEepromRowAddr" may be
+ * updated with the proper address (if wear leveling is used). The
+ * "emEepromRowRdAddr" will point to the row address from which the historic
+ * data will be read into the RAM buffer.
+ */
+ GetNextRowToWrite(seqNum, &emEepromRowAddr, &emEepromRowRdAddr, context);
+
+ /* Clear the RAM buffer so to not put junk into flash */
+ (void)memset(writeRamBuffer, 0, CY_EM_EEPROM_FLASH_SIZEOF_ROW);
+
+ /* Fill the EM_EEPROM header info for the row in the RAM buffer */
+ seqNum++;
+ writeRamBuffer[CY_EM_EEPROM_HEADER_SEQ_NUM_OFFSET_U32] = seqNum;
+ writeRamBuffer[CY_EM_EEPROM_HEADER_ADDR_OFFSET_U32] = addr;
+ tmpData = (void *) eeData;
+
+ /* Check if this is the last row to write */
+ if(wrCnt == (numWrites - 1u))
+ {
+ /* Fill in the remaining size value to the EEPROM header. */
+ writeRamBuffer[CY_EM_EEPROM_HEADER_LEN_OFFSET_U32] = size;
+ }
+ else
+ {
+ /* This is not the last row to write in the current EEPROM write operation.
+ * Write the maximum possible data size to the EEPROM header. Update the
+ * size, eeData and addr respectively.
+ */
+ writeRamBuffer[CY_EM_EEPROM_HEADER_LEN_OFFSET_U32] = CY_EM_EEPROM_HEADER_DATA_LEN;
+ size -= CY_EM_EEPROM_HEADER_DATA_LEN;
+ addr += CY_EM_EEPROM_HEADER_DATA_LEN;
+ eeData += CY_EM_EEPROM_HEADER_DATA_LEN;
+ }
+
+ /* Write the data to the EEPROM header */
+ (void)memcpy((void *)&writeRamBuffer[CY_EM_EEPROM_HEADER_DATA_OFFSET_U32],
+ tmpData,
+ writeRamBuffer[CY_EM_EEPROM_HEADER_LEN_OFFSET_U32]);
+
+ if(emEepromRowRdAddr != 0UL)
+ {
+ /* Copy the EEPROM historic data for this row from flash to RAM */
+ (void)memcpy((void *)&writeRamBuffer[CY_EM_EEPROM_EEPROM_DATA_OFFSET_U32],
+ (void *)(emEepromRowRdAddr + CY_EM_EEPROM_EEPROM_DATA_LEN),
+ CY_EM_EEPROM_EEPROM_DATA_LEN);
+ }
+
+ /* Check if there is data for this location in other EEPROM headers:
+ * find out the row with the lowest possible sequence number which
+ * may contain the data for the current row.
+ */
+ i = (seqNum > context->numberOfRows) ? ((seqNum - (context->numberOfRows)) + 1u) : 1u;
+
+ for(; i <= seqNum; i++)
+ {
+ if(i == seqNum)
+ {
+ /* The code reached the row that is about to be written. Analyze the recently
+ * created EEPROM header (stored in the RAM buffer currently): if it contains
+ * the data for EEPROM data locations in the row that is about to be written.
+ */
+ tmpRowAddr = (uint32) writeRamBuffer;
+ }
+ else
+ {
+ /* Retrieve the address of the previously written row by its sequence number.
+ * The pointer will be used to get data from the respective EEPROM header.
+ */
+ tmpRowAddr = GetRowAddrBySeqNum(i, context);
+ }
+
+ actEmEepromRowNum = CY_EM_EEPROM_GET_ACT_ROW_NUM_FROM_ADDR(emEepromRowAddr,
+ context->numberOfRows,
+ context->userFlashStartAddr);
+ if(0UL != tmpRowAddr)
+ {
+ /* Calculate the required addressed for the later EEPROM historic data update */
+ skipOperation = GetAddresses(
+ &startAddr,
+ &endAddr,
+ &eeHeaderDataOffset,
+ actEmEepromRowNum,
+ *(uint32 *)(tmpRowAddr + CY_EM_EEPROM_HEADER_ADDR_OFFSET),
+ *(uint32 *)(tmpRowAddr + CY_EM_EEPROM_HEADER_LEN_OFFSET));
+ }
+ else
+ {
+ /* Skip writes to the RAM buffer */
+ skipOperation++;
+ }
+
+ /* Write data to the RAM buffer */
+ if(0u == skipOperation)
+ {
+ uint32 dataAddr = ((uint32)((uint8 *)&writeRamBuffer)) + startAddr;
+
+ /* Update the address to point to the EEPROM header data and not to
+ * the start of the row.
+ */
+ tmpRowAddr = tmpRowAddr + CY_EM_EEPROM_HEADER_DATA_OFFSET + eeHeaderDataOffset;
+ (void)memcpy((void *)(dataAddr), (void *)(tmpRowAddr), endAddr - startAddr);
+ }
+
+ /* Calculate the checksum if redundant copy is enabled */
+ if(0u != context->redundantCopy)
+ {
+ writeRamBuffer[CY_EM_EEPROM_HEADER_CHECKSUM_OFFSET_U32] = (uint32)
+ CalcChecksum((uint8 *) &writeRamBuffer[CY_EM_EEPROM_EEPROM_DATA_OFFSET_U32],
+ CY_EM_EEPROM_EEPROM_DATA_LEN);
+ }
+ }
+
+ /* Write the data to the specified flash row */
+ ret = WriteRow(emEepromRowAddr, writeRamBuffer, context);
+ tmpRowAddr = emEepromRowAddr;
+
+ /* Check if redundant copy is used */
+ if((0u != context->redundantCopy) && (CY_EM_EEPROM_SUCCESS == ret))
+ {
+ /* Update the row address to point to the row in the redundant EEPROM's copy */
+ tmpRowAddr = (emEepromRowAddr - context->userFlashStartAddr) + context->wlEndAddr;
+
+ /* Write the data to the specified flash row */
+ ret = WriteRow(tmpRowAddr, writeRamBuffer, context);
+ }
+
+ if(CY_EM_EEPROM_SUCCESS == ret)
+ {
+ /* Store last written row address only when EEPROM and redundant
+ * copy writes were successful.
+ */
+ context->lastWrRowAddr = emEepromRowAddr;
+ }
+ else
+ {
+ break;
+ }
+ }
+ }
+ return(ret);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_Em_EEPROM_Erase
+****************************************************************************//**
+*
+* This function erases the entire contents of the EEPROM. Erased values are all
+* zeros. This is a blocking function and it does not return until the write
+* operation is completed. The user firmware should not enter Hibernate mode until
+* erase is completed. The erase operation is allowed in Sleep and Deep-Sleep modes.
+* During the flash operation, the device should not be reset, including the
+* XRES pin, a software reset, and watchdog reset sources. Also, low-voltage
+* detect circuits should be configured to generate an interrupt instead of a
+* reset. Otherwise, portions of flash may undergo unexpected changes.
+*
+* \param context
+* The pointer to the EEPROM context structure \ref cy_stc_eeprom_context_t.
+*
+* \return
+* This function returns \ref cy_en_em_eeprom_status_t.
+*
+* \note
+* For all non PSoC 6 devices the erase operation is performed by clearing
+* the EEPROM data using flash write. This affects the flash durability.
+* So it is recommended to use this function in utmost case to prolongate
+* flash life.
+*
+* \note
+* This function uses a buffer of the flash row size to perform erase
+* operation. For the size of the row refer to the specific PSoC device
+* datasheet.
+*
+* \sideeffect
+* In case when blocking write option is used, if this function is called by
+* the CM4 the user code on CM0P and the user code on CM4 are blocked until erase
+* flash row operation is finished. If this function is called by the CM0P the
+* user code on CM4 is not blocked and the user code on CM0P is blocked until
+* erase flash row operation is finished. Plan your task allocation accordingly.
+*
+* \sideeffect
+* In case if non-blocking write option is used and when user flash is used as
+* an EEPROM storage care should be taken to prevent the read while write (RWW)
+* exception. To prevent the RWW exception the user flash macro that includes
+* the EEPROM storage should not be read while the EEPROM erase is not completed.
+* The read also means the user code execution from the respective flash macro.
+*
+*******************************************************************************/
+cy_en_em_eeprom_status_t Cy_Em_EEPROM_Erase(cy_stc_eeprom_context_t * context)
+{
+ uint32 i;
+ uint32 seqNum;
+ uint32 emEepromRowAddr = context->lastWrRowAddr;
+ uint32 emEepromRowRdAddr;
+ cy_en_em_eeprom_status_t ret = CY_EM_EEPROM_WRITE_FAIL;
+ uint32 writeRamBuffer[CY_EM_EEPROM_FLASH_SIZEOF_ROW / CY_EM_EEPROM_U32_DIV] = {0u};
+#if (CY_PSOC6)
+ uint32 emEepromStoredRowAddr = context->lastWrRowAddr;
+ uint32 storedSeqNum;
+#endif /* (!CY_PSOC6) */
+
+ /* Get the sequence number of the last written row */
+ seqNum = CY_EM_EEPROM_GET_SEQ_NUM(emEepromRowAddr);
+
+ /* If there were no writes to EEPROM - nothing to erase */
+ if(0u != seqNum)
+ {
+ /* Calculate the number of row erase operations required */
+ uint32 numWrites = context->numberOfRows * context->wearLevelingFactor;
+
+ #if (CY_PSOC6)
+ GetNextRowToWrite(seqNum, &emEepromStoredRowAddr, &emEepromRowRdAddr, context);
+ storedSeqNum = seqNum + 1u;
+ #endif /* (CY_PSOC6) */
+
+ if(0u != context->redundantCopy)
+ {
+ writeRamBuffer[CY_EM_EEPROM_HEADER_CHECKSUM_OFFSET_U32] = (uint32)
+ CalcChecksum((uint8 *) &writeRamBuffer[CY_EM_EEPROM_EEPROM_DATA_OFFSET_U32],
+ CY_EM_EEPROM_EEPROM_DATA_LEN);
+ }
+
+ for(i = 0u; i < numWrites; i++)
+ {
+ #if (CY_PSOC6)
+ /* For PSoC 6 the erase operation moves backwards. From last written row
+ * identified by "seqNum" down to "seqNum" - "numWrites". If "emEepromRowAddr"
+ * is zero this means that the row identified by "seqNum" was previously
+ * erased.
+ */
+ if(0u != emEepromRowAddr)
+ {
+ ret = EraseRow(emEepromRowAddr, (uint32)writeRamBuffer, context);
+ }
+
+ seqNum--;
+
+ if(0u == seqNum)
+ {
+ /* Exit the loop as there is no more row is EEPROM to be erased */
+ break;
+ }
+ emEepromRowAddr = GetRowAddrBySeqNum(seqNum, context);
+ #else
+ seqNum = CY_EM_EEPROM_GET_SEQ_NUM(emEepromRowAddr);
+ /* Get the address of the row to be erased. "emEepromRowAddr" may be updated
+ * with the proper address (if wear leveling is used).
+ */
+ GetNextRowToWrite(seqNum, &emEepromRowAddr, &emEepromRowRdAddr, context);
+ seqNum++;
+ writeRamBuffer[0u] = seqNum;
+ ret = EraseRow(emEepromRowAddr, (uint32)writeRamBuffer, context);
+ #endif /* (CY_PSOC6) */
+ }
+
+ #if (CY_PSOC6)
+ if(CY_EM_EEPROM_SUCCESS == ret)
+ {
+ writeRamBuffer[0u] = storedSeqNum;
+
+ /* Write the previously stored sequence number to the flash row which would be
+ * written next if the erase wouldn't happen. In this case the write to
+ * redundant copy can be skipped as it does not add any value.
+ */
+ ret = WriteRow(emEepromStoredRowAddr, writeRamBuffer, context);
+
+ if(CY_EM_EEPROM_SUCCESS == ret)
+ {
+ context->lastWrRowAddr = emEepromStoredRowAddr;
+ }
+ }
+ #endif /* (CY_PSOC6) */
+
+ }
+ return(ret);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_Em_EEPROM_NumWrites
+****************************************************************************//**
+*
+* Returns the number of the EEPROM writes completed so far.
+*
+* \param context
+* The pointer to the EEPROM context structure \ref cy_stc_eeprom_context_t.
+*
+* \return
+* The number of writes performed to the EEPROM.
+*
+*******************************************************************************/
+uint32 Cy_Em_EEPROM_NumWrites(cy_stc_eeprom_context_t * context)
+{
+ return(CY_EM_EEPROM_GET_SEQ_NUM(context->lastWrRowAddr));
+}
+
+/** \} */
+
+/** \cond INTERNAL */
+
+
+/*******************************************************************************
+* Function Name: FindLastWrittenRow
+****************************************************************************//**
+*
+* Performs a search of the last written row address of the EEPROM associated
+* with the context structure. If there were no writes to the EEPROM the
+* function returns the start address of the EEPROM. The row address is returned
+* in the input parameter.
+*
+* \param lastWrRowPtr
+* The pointer to a memory where the last written row will be returned.
+*
+* \param context
+* The pointer to the EEPROM context structure \ref cy_stc_eeprom_context_t.
+*
+*******************************************************************************/
+static void FindLastWrittenRow(uint32 * lastWrRowPtr, cy_stc_eeprom_context_t * context)
+{
+ uint32 seqNum = 0u;
+ uint32 prevSeqNum = 0u;
+ uint32 numRows;
+ uint32 emEepromAddr = context->userFlashStartAddr;
+
+ *lastWrRowPtr = emEepromAddr;
+
+ for(numRows = 0u; numRows < (context->numberOfRows * context->wearLevelingFactor); numRows++)
+ {
+ seqNum = CY_EM_EEPROM_GET_SEQ_NUM(emEepromAddr);
+ if((0u != seqNum) && (seqNum > prevSeqNum))
+ {
+ /* Some record in EEPROM was found. Store found sequence
+ * number and row address.
+ */
+ prevSeqNum = seqNum;
+ *lastWrRowPtr = emEepromAddr;
+ }
+
+ /* Switch to the next row */
+ emEepromAddr = emEepromAddr + CY_EM_EEPROM_FLASH_SIZEOF_ROW;
+ }
+}
+
+
+/*******************************************************************************
+* Function Name: GetRowAddrBySeqNum
+****************************************************************************//**
+*
+* Returns the address of the row in EEPROM using its sequence number.
+*
+* \param seqNum
+* The sequence number of the row.
+*
+* \param context
+* The pointer to the EEPROM context structure.
+*
+* \return
+* The address of the row or zero if the row with the sequence number was not
+* found.
+*
+*******************************************************************************/
+static uint32 GetRowAddrBySeqNum(uint32 seqNum, cy_stc_eeprom_context_t * context)
+{
+ uint32 emEepromAddr = context->userFlashStartAddr;
+
+ while(CY_EM_EEPROM_GET_SEQ_NUM(emEepromAddr) != seqNum)
+ {
+ /* Switch to the next row */
+ emEepromAddr = emEepromAddr + CY_EM_EEPROM_FLASH_SIZEOF_ROW;
+
+ if (CY_EM_EEPROM_ADDR_IN_RANGE !=
+ CY_EM_EEPROM_IS_ADDR_EXCEED_RANGE(emEepromAddr, context->wlEndAddr))
+ {
+ emEepromAddr = 0u;
+ /* Exit the loop as we reached the end of EEPROM */
+ break;
+ }
+ }
+
+ return (emEepromAddr);
+}
+
+
+/*******************************************************************************
+* Function Name: GetNextRowToWrite
+****************************************************************************//**
+*
+* Performs a range check of the row that should be written and updates the
+* address to the row respectively. The similar actions are done for the read
+* address.
+*
+* \param seqNum
+* The sequence number of the last written row.
+*
+* \param rowToWrPtr
+* The address of the last written row (input). The address of the row to be
+* written (output).
+*
+* \param rowToRdPtr
+* The address of the row from which the data should be read into the RAM buffer
+* in a later write operation. Out parameter.
+*
+* \param context
+* The pointer to the EEPROM context structure \ref cy_stc_eeprom_context_t.
+*
+*******************************************************************************/
+static void GetNextRowToWrite(uint32 seqNum,
+ uint32 * rowToWrPtr,
+ uint32 * rowToRdPtr,
+ cy_stc_eeprom_context_t * context)
+{
+ /* Switch to the next row to be written if the current sequence number is
+ * not zero.
+ */
+ if(0u != seqNum)
+ {
+ *rowToWrPtr = (*rowToWrPtr + CY_EM_EEPROM_FLASH_SIZEOF_ROW);
+ }
+
+ /* If the resulting row address is out of EEPROM, then switch to the base
+ * EEPROM address (Row#0).
+ */
+ if(CY_EM_EEPROM_ADDR_IN_RANGE !=
+ CY_EM_EEPROM_IS_ADDR_EXCEED_RANGE(*rowToWrPtr, context->wlEndAddr))
+ {
+ *rowToWrPtr = context->userFlashStartAddr;
+ }
+
+ *rowToRdPtr = 0u;
+
+ /* Check if the sequence number is larger than the number of rows in the EEPROM.
+ * If not, do not update the row read address because there is no historic
+ * data to be read.
+ */
+ if(context->numberOfRows <= seqNum)
+ {
+ /* Check if wear leveling is used in EEPROM */
+ if(context->wearLevelingFactor > 1u)
+ {
+ /* The read row address should be taken from an EEPROM copy that became
+ * inactive recently. This condition check handles that.
+ */
+ if((*rowToWrPtr - (context->numberOfRows * CY_EM_EEPROM_FLASH_SIZEOF_ROW)) <
+ context->userFlashStartAddr)
+ {
+ *rowToRdPtr = context->userFlashStartAddr +
+ (context->numberOfRows * (context->wearLevelingFactor - 1u) *
+ CY_EM_EEPROM_FLASH_SIZEOF_ROW) + (*rowToWrPtr - context->userFlashStartAddr);
+ }
+ else
+ {
+ *rowToRdPtr = *rowToWrPtr - (context->numberOfRows * CY_EM_EEPROM_FLASH_SIZEOF_ROW);
+ }
+ }
+ else
+ {
+ /* If no wear leveling, always read from the same flash row that
+ * should be written.
+ */
+ *rowToRdPtr = *rowToWrPtr;
+ }
+ }
+}
+
+
+/*******************************************************************************
+* Function Name: CalcChecksum
+****************************************************************************//**
+*
+* Implements CRC-8 that is used in checksum calculation for the redundant copy
+* algorithm.
+*
+* \param rowData
+* The row data to be used to calculate the checksum.
+*
+* \param len
+* The length of rowData.
+*
+* \return
+* The calculated value of CRC-8.
+*
+*******************************************************************************/
+static uint8 CalcChecksum(uint8 rowData[], uint32 len)
+{
+ uint8 crc = CY_EM_EEPROM_CRC8_SEED;
+ uint8 i;
+ uint16 cnt = 0u;
+
+ while(cnt != len)
+ {
+ crc ^= rowData[cnt];
+ for (i = 0u; i < CY_EM_EEPROM_CRC8_POLYNOM_LEN; i++)
+ {
+ crc = CY_EM_EEPROM_CALCULATE_CRC8(crc);
+ }
+ cnt++;
+ }
+
+ return (crc);
+}
+
+
+/*******************************************************************************
+* Function Name: CheckRanges
+****************************************************************************//**
+*
+* Checks if the EEPROM of the requested size can be placed in flash.
+*
+* \param config
+* The pointer to a configuration structure. See \ref cy_stc_eeprom_config_t.
+*
+* \return
+* error / status code. See \ref cy_en_em_eeprom_status_t.
+*
+*******************************************************************************/
+static cy_en_em_eeprom_status_t CheckRanges(cy_stc_eeprom_config_t* config)
+{
+ cy_en_em_eeprom_status_t ret = CY_EM_EEPROM_BAD_DATA;
+ uint32 startAddr = config->userFlashStartAddr;
+ uint32 endAddr = startAddr + CY_EM_EEPROM_GET_PHYSICAL_SIZE(config->eepromSize,
+ config->wearLevelingFactor, config->redundantCopy);
+
+ /* Range check if there is enough flash for EEPROM */
+ if (CY_EM_EEPROM_IS_IN_FLASH_RANGE(startAddr, endAddr))
+ {
+ ret = CY_EM_EEPROM_SUCCESS;
+ }
+ return (ret);
+}
+
+
+/*******************************************************************************
+* Function Name: WriteRow
+****************************************************************************//**
+*
+* Writes one flash row starting from the specified row address.
+*
+* \param rowAdd
+* The address of the flash row.
+*
+* \param rowData
+* The pointer to the data to be written to the row.
+*
+* \param context
+* The pointer to the EEPROM context structure \ref cy_stc_eeprom_context_t.
+*
+* \return
+* error / status code. See \ref cy_en_em_eeprom_status_t.
+*
+*******************************************************************************/
+static cy_en_em_eeprom_status_t WriteRow(uint32 rowAddr,
+ uint32 *rowData,
+ cy_stc_eeprom_context_t * context)
+{
+ cy_en_em_eeprom_status_t ret = CY_EM_EEPROM_WRITE_FAIL;
+#if (!CY_PSOC6)
+ cystatus rc;
+ uint32 rowId;
+ #if ((CY_PSOC3) || (CY_PSOC5))
+ uint32 arrayId;
+ #endif /* (CY_PSOC3) */
+
+ #if (CY_PSOC3)
+ rowAddr &= CY_EM_EEPROM_CODE_ADDR_MASK;
+ context = context; /* To avoid compiler warning generation */
+ #else
+ (void)context; /* To avoid compiler warning generation */
+ #endif /* ((CY_PSOC3) */
+
+ /* For non-PSoC 6 devices, the Array ID and Row ID needed to write the row */
+ rowId = (rowAddr / CY_EM_EEPROM_FLASH_SIZEOF_ROW) % CY_EM_EEPROM_ROWS_IN_ARRAY;
+
+ /* Write the flash row */
+ #if (CY_PSOC4)
+ rc = CySysFlashWriteRow(rowId, (uint8 *)rowData);
+ #else
+
+ #ifndef CY_EM_EEPROM_SKIP_TEMP_MEASUREMENT
+ (void)CySetTemp();
+ #endif /* (CY_EM_EEPROM_SKIP_TEMP_MEASUREMENT) */
+
+ arrayId = rowAddr / CY_FLASH_SIZEOF_ARRAY;
+ rc = CyWriteRowData((uint8)arrayId, (uint16)rowId, (uint8 *)rowData);
+
+ #if (CY_PSOC5)
+ CyFlushCache();
+ #endif /* (CY_PSOC5) */
+ #endif /* (CY_PSOC4) */
+
+ if(CYRET_SUCCESS == rc)
+ {
+ ret = CY_EM_EEPROM_SUCCESS;
+ }
+#else /* PSoC 6 */
+ if(0u != context->blockingWrite)
+ {
+ /* Do blocking write */
+ if(CY_FLASH_DRV_SUCCESS == Cy_Flash_WriteRow(rowAddr, (const uint32 *)rowData))
+ {
+ ret = CY_EM_EEPROM_SUCCESS;
+ }
+ }
+ else
+ {
+ /* Initiate write */
+ if(CY_FLASH_DRV_OPERATION_STARTED == Cy_Flash_StartWrite(rowAddr, (const uint32 *)rowData))
+ {
+ uint32 countMs = CY_EM_EEPROM_MAX_WRITE_DURATION_MS;
+ cy_en_flashdrv_status_t rc;
+
+ do
+ {
+ CyDelay(1u); /* Wait 1ms */
+ rc = Cy_Flash_IsWriteComplete(); /* Check if write completed */
+ countMs--;
+ }
+ while ((rc == CY_FLASH_DRV_OPCODE_BUSY) && (0u != countMs));
+
+ if(CY_FLASH_DRV_SUCCESS == rc)
+ {
+ ret = CY_EM_EEPROM_SUCCESS;
+ }
+ }
+ }
+#endif /* (CY_PSOC6) */
+
+ return (ret);
+}
+
+
+/*******************************************************************************
+* Function Name: EraseRow
+****************************************************************************//**
+*
+* Erases one flash row starting from the specified row address. If the redundant
+* copy option is enabled the corresponding row in the redundant copy will also
+* be erased.
+*
+* \param rowAdd
+* The address of the flash row.
+*
+* \param ramBuffAddr
+* The address of the RAM buffer that contains zeroed data (used only for
+* non-PSoC 6 devices).
+*
+* \param context
+* The pointer to the EEPROM context structure \ref cy_stc_eeprom_context_t.
+*
+* \return
+* error / status code. See \ref cy_en_em_eeprom_status_t.
+*
+*******************************************************************************/
+static cy_en_em_eeprom_status_t EraseRow(uint32 rowAddr,
+ uint32 ramBuffAddr,
+ cy_stc_eeprom_context_t * context)
+{
+ uint32 emEepromRowAddr = rowAddr;
+ cy_en_em_eeprom_status_t ret = CY_EM_EEPROM_WRITE_FAIL;
+#if (CY_PSOC6)
+ uint32 i = 1u;
+
+ (void)ramBuffAddr; /* To avoid compiler warning */
+
+ if(0u != context->redundantCopy)
+ {
+ i++;
+ }
+
+ do
+ {
+ if(0u != context->blockingWrite)
+ {
+ /* Erase the flash row */
+ if(CY_FLASH_DRV_SUCCESS == Cy_Flash_EraseRow(emEepromRowAddr))
+ {
+ ret = CY_EM_EEPROM_SUCCESS;
+ }
+ }
+ else
+ {
+ /* Initiate erase */
+ if(CY_FLASH_DRV_OPERATION_STARTED == Cy_Flash_StartErase(emEepromRowAddr))
+ {
+ uint32 countMs = CY_EM_EEPROM_MAX_WRITE_DURATION_MS;
+ cy_en_flashdrv_status_t rc;
+
+ do
+ {
+ CyDelay(1u); /* Wait 1ms */
+ rc = Cy_Flash_IsWriteComplete(); /* Check if erase completed */
+ countMs--;
+ }
+ while ((rc == CY_FLASH_DRV_OPCODE_BUSY) && (0u != countMs));
+
+ if(CY_FLASH_DRV_SUCCESS == rc)
+ {
+ ret = CY_EM_EEPROM_SUCCESS;
+ }
+ }
+ }
+
+ if(CY_EM_EEPROM_SUCCESS == ret)
+ {
+ /* Update the address to point to the redundant copy row */
+ emEepromRowAddr = (emEepromRowAddr - context->userFlashStartAddr) + context->wlEndAddr;
+ }
+ else
+ {
+ break;
+ }
+ i--;
+ } while (0u != i);
+#else
+ /* Write the data to the specified flash row */
+ ret = WriteRow(emEepromRowAddr, (uint32 *)ramBuffAddr, context);
+
+ if((CY_EM_EEPROM_SUCCESS == ret) && (0u != context->redundantCopy))
+ {
+ /* Update the address to point to the redundant copy row */
+ emEepromRowAddr = (emEepromRowAddr - context->userFlashStartAddr) + context->wlEndAddr;
+ ret = WriteRow(emEepromRowAddr, (uint32 *)ramBuffAddr, context);
+ }
+
+ if(CY_EM_EEPROM_SUCCESS == ret)
+ {
+ context->lastWrRowAddr = rowAddr;
+ }
+#endif /* (CY_PSOC6) */
+
+ return(ret);
+}
+
+
+/*******************************************************************************
+* Function Name: CheckCrcAndCopy
+****************************************************************************//**
+*
+* Checks the checksum of the specific row in EEPROM. If the CRC matches - copies
+* the data to the "datAddr" from EEPROM. f the CRC does not match checks the
+* CRC of the corresponding row in the EEPROM's redundant copy. If the CRC
+* matches - copies the data to the "datAddr" from EEPROM redundant copy. If the
+* CRC of the redundant copy does not match - returns bad checksum.
+*
+* \param startAddr
+* The address that points to the start of the specified row.
+*
+* \param datAddr
+* The start address of where the row data will be copied if the CRC check
+* will succeed.
+*
+* \param rowOffset
+* The offset in the row from which the data should be copied.
+*
+* \param numBytes
+* The number of bytes to be copied.
+*
+* \param context
+* The pointer to the EEPROM context structure \ref cy_stc_eeprom_context_t.
+*
+* \return
+* error / status code. See \ref cy_en_em_eeprom_status_t.
+*
+* \note
+* This function uses a buffer of the flash row size to perform read
+* operation. For the size of the row refer to the specific PSoC device
+* datasheet.
+*
+*******************************************************************************/
+static cy_en_em_eeprom_status_t CheckCrcAndCopy(uint32 startAddr,
+ uint32 dstAddr,
+ uint32 rowOffset,
+ uint32 numBytes,
+ cy_stc_eeprom_context_t * context)
+{
+ cy_en_em_eeprom_status_t ret;
+ uint32 writeRamBuffer[CY_EM_EEPROM_FLASH_SIZEOF_ROW / CY_EM_EEPROM_U32_DIV];
+
+ /* Calculate the row address in the EEPROM's redundant copy */
+ uint32 rcStartRowAddr = (startAddr - context->userFlashStartAddr) + context->wlEndAddr;
+
+ /* Check the row data CRC in the EEPROM */
+ if((*(uint32 *)(startAddr + CY_EM_EEPROM_HEADER_CHECKSUM_OFFSET)) ==
+ ((uint32) CalcChecksum((uint8 *)(startAddr + CY_EM_EEPROM_EEPROM_DATA_OFFSET),
+ CY_EM_EEPROM_EEPROM_DATA_LEN)))
+ {
+ (void)memcpy((void *)(dstAddr), (void *)(startAddr + rowOffset), numBytes);
+
+ ret = CY_EM_EEPROM_SUCCESS;
+ }
+ /* Check the row data CRC in the EEPROM's redundant copy */
+ else if((*(uint32 *)(rcStartRowAddr + CY_EM_EEPROM_HEADER_CHECKSUM_OFFSET)) ==
+ ((uint32) CalcChecksum((uint8 *)(rcStartRowAddr + CY_EM_EEPROM_EEPROM_DATA_OFFSET),
+ CY_EM_EEPROM_EEPROM_DATA_LEN)))
+ {
+ /* Copy the redundant copy row to RAM buffer to avoid read while write (RWW)
+ * flash exception. The RWW occurs while trying to write and read the data from
+ * same flash macro.
+ */
+ (void)memcpy((void *)(writeRamBuffer), (void *)(rcStartRowAddr), CY_EM_EEPROM_FLASH_SIZEOF_ROW);
+
+ /* Restore bad row data from the RAM buffer */
+ ret = WriteRow(startAddr, (uint32 *)writeRamBuffer, context);
+
+ if(CY_EM_EEPROM_SUCCESS == ret)
+ {
+ (void)memcpy((void *)(dstAddr), (void *)(writeRamBuffer + rowOffset), numBytes);
+ }
+ }
+ else
+ {
+ ret = CY_EM_EEPROM_BAD_CHECKSUM;
+ }
+
+ return(ret);
+}
+
+
+/*******************************************************************************
+* Function Name: GetAddresses
+****************************************************************************//**
+*
+* Calculates the start and end address of the row's EEPROM data to be updated.
+* The start and end are not absolute addresses but a relative addresses in a
+* flash row.
+*
+* \param startAddr
+* The pointer the address where the EEPROM data start address will be returned.
+*
+* \param endAddr
+* The pointer the address where the EEPROM data end address will be returned.
+*
+* \param offset
+* The pointer the address where the calculated offset of the EEPROM header data
+* will be returned.
+*
+* \param rowNum
+* The row number that is about to be written.
+*
+* \param addr
+* The address of the EEPROM header data in the currently analyzed row that may
+* concern to the row about to be written.
+*
+* \param len
+* The length of the EEPROM header data in the currently analyzed row that may
+* concern to the row about to be written.
+*
+* \return
+* Zero indicates that the currently analyzed row has the data to be written to
+* the active EEPROM row data locations. Non zero value indicates that there is
+* no data to be written
+*
+*******************************************************************************/
+static uint32 GetAddresses(uint32 *startAddr,
+ uint32 *endAddr,
+ uint32 *offset,
+ uint32 rowNum,
+ uint32 addr,
+ uint32 len)
+{
+ uint32 skip = 0u;
+
+ *offset =0u;
+
+ if(0u != CY_EM_EEPROM_IS_ADDR_IN_ROW_RANGE(addr, rowNum))
+ {
+ *startAddr = CY_EM_EEPROM_EEPROM_DATA_LEN + (addr % CY_EM_EEPROM_EEPROM_DATA_LEN);
+
+ if(0u != CY_EM_EEPROM_IS_ADDR_IN_ROW_RANGE(addr + len, rowNum))
+ {
+ *endAddr = *startAddr + len;
+ }
+ else
+ {
+ *endAddr = CY_EM_EEPROM_FLASH_SIZEOF_ROW;
+ }
+ }
+ else
+ {
+
+ if(0u != CY_EM_EEPROM_IS_ADDR_IN_ROW_RANGE(addr + len, rowNum))
+ {
+ *startAddr = CY_EM_EEPROM_EEPROM_DATA_LEN;
+ *endAddr = (*startAddr + len) - (*startAddr - (addr % CY_EM_EEPROM_EEPROM_DATA_LEN));
+ *offset = len - (*endAddr - *startAddr);
+ }
+ else
+ {
+ skip++;
+ }
+ }
+
+ return (skip);
+}
+
+
+/*******************************************************************************
+* Function Name: FillChecksum
+****************************************************************************//**
+*
+* Performs calculation of the checksum on each row in the Em_EEPROM and fills
+* the Em_EEPROM headers checksum field with the calculated checksums.
+*
+* \param context
+* The pointer to the EEPROM context structure.
+*
+* \return
+* error / status code. See \ref cy_en_em_eeprom_status_t.
+*
+* \theory
+* In case if redundant copy option is used the Em_EEPROM would return bad
+* checksum while trying to read the EEPROM rows which were not yet written by
+* the user. E.g. any read after device reprogramming without previous Write()
+* operation to the EEPROM would fail. This would happen because the Em_EEPROM
+* headers checksum field values (which is zero at the moment) would not be
+* equal to the actual data checksum. This function allows to avoid read failure
+* after device reprogramming.
+*
+* \note
+* This function uses a buffer of the flash row size to perform read
+* operation. For the size of the row refer to the specific PSoC device
+* datasheet.
+*
+*******************************************************************************/
+static cy_en_em_eeprom_status_t FillChecksum(cy_stc_eeprom_context_t * context)
+{
+ uint32 i;
+ uint32 rdAddr;
+ uint32 writeRamBuffer[CY_EM_EEPROM_FLASH_SIZEOF_ROW / CY_EM_EEPROM_U32_DIV];
+ uint32 wrAddr = context->lastWrRowAddr;
+ uint32 tmpRowAddr;
+ /* Get the sequence number (number of writes) */
+ uint32 seqNum = CY_EM_EEPROM_GET_SEQ_NUM(wrAddr);
+ cy_en_em_eeprom_status_t ret = CY_EM_EEPROM_BAD_PARAM;
+
+ for(i = 0u; i < (context->numberOfRows * context->wearLevelingFactor); i++)
+ {
+ /* Copy the EEPROM row from Flash to RAM */
+ (void)memcpy((void *)&writeRamBuffer[0u], (void *)(wrAddr), CY_EM_EEPROM_FLASH_SIZEOF_ROW);
+
+ /* Increment the sequence number */
+ seqNum++;
+ writeRamBuffer[CY_EM_EEPROM_HEADER_SEQ_NUM_OFFSET_U32] = seqNum;
+
+ /* Calculate and fill the checksum to the Em_EEPROM header */
+ writeRamBuffer[CY_EM_EEPROM_HEADER_CHECKSUM_OFFSET_U32] = (uint32)
+ CalcChecksum((uint8 *) &writeRamBuffer[CY_EM_EEPROM_EEPROM_DATA_OFFSET_U32],
+ CY_EM_EEPROM_EEPROM_DATA_LEN);
+
+ /* Write the data to the specified flash row */
+ ret = WriteRow(wrAddr, writeRamBuffer, context);
+
+ /* Update the row address to point to the relevant row in the redundant
+ * EEPROM's copy.
+ */
+ tmpRowAddr = (wrAddr - context->userFlashStartAddr) + context->wlEndAddr;
+
+ /* Write the data to the specified flash row */
+ ret = WriteRow(tmpRowAddr, writeRamBuffer, context);
+
+ /* Get the address of the next row to be written.
+ * "rdAddr" is not used in this function but provided to prevent NULL
+ * pointer exception in GetNextRowToWrite().
+ */
+ GetNextRowToWrite(seqNum, &wrAddr, &rdAddr, context);
+ }
+
+ return(ret);
+}
+
+/** \endcond */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/* [] END OF FILE */
--- /dev/null
+/*******************************************************************************
+* \file cy_em_eeprom.h
+* \version 2.0
+*
+* \brief
+* This file provides the function prototypes and constants for the Emulated
+* EEPROM middleware library.
+*
+********************************************************************************
+* Copyright 2017, Cypress Semiconductor Corporation. All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions,
+* disclaimers, and limitations in the end user license agreement accompanying
+* the software package with which this file was provided.
+*******************************************************************************/
+
+/**
+ * \mainpage Cypress Em_EEPROM Middleware Library
+ *
+ * The Emulated EEPROM provides an API that allows creating an emulated
+ * EEPROM in flash that has the ability to do wear leveling and restore
+ * corrupted data from a redundant copy. The Emulated EEPROM library is designed
+ * to be used with the Em_EEPROM component.
+ *
+ * The Cy_Em_EEPROM API is described in the following sections:
+ * - \ref group_em_eeprom_macros
+ * - \ref group_em_eeprom_data_structures
+ * - \ref group_em_eeprom_enums
+ * - \ref group_em_eeprom_functions
+ *
+ * <b>Features:</b>
+ * * EEPROM-Like Non-Volatile Storage
+ * * Easy to use Read and Write API
+ * * Optional Wear Leveling
+ * * Optional Redundant Data storage
+ *
+ * \section group_em_eeprom_configuration Configuration Considerations
+ *
+ * The Em_EEPROM operates on the top of the flash driver. The flash driver has
+ * some prerequisites for proper operation. Refer to the "Flash System
+ * Routine (Flash)" section of the PDL API Reference Manual.
+ *
+ * <b>Initializing Emulated EEPROM in User flash</b>
+ *
+ * To initialize an Emulated EEPROM in the User flash, the EEPROM storage should
+ * be declared by the user. For the proper operation, the EEPROM storage should
+ * be aligned to the size of the flash row. An example of the EEPROM storage
+ * declaration is below (applicable for GCC and MDK compilers):
+ *
+ * CY_ALIGN(CY_EM_EEPROM_FLASH_SIZEOF_ROW)
+ * const uint8 emEeprom[Em_EEPROM_PHYSICAL_SIZE] = {0u};
+ *
+ * The same declaration for the IAR compiler:
+ *
+ * #pragma data_alignment = CY_EM_EEPROM_FLASH_SIZEOF_ROW
+ * const uint8 emEeprom[Em_EEPROM_PHYSICAL_SIZE] = {0u};
+ *
+ * Note that the name "emEeprom" is shown for reference. Any other name can be
+ * used instead. Also, note that the Em_EEPROM_PHYSICAL_SIZE constant is
+ * generated by the PSoC Creator Em_EEPROM component and so it is instance name
+ * dependent and its prefix should be changed when the name of the component
+ * changes. If the The Cy_Em_EEPROM middleware library is used without the
+ * Em_EEPROM component, the user has to provide a proper size for the EEPROM
+ * storage instead of Em_EEPROM_PHYSICAL_SIZE. The size of the EEPROM storage
+ * can be calculated using the following equation:
+ *
+ * Physical size = EEPROM data size * 2 * wear leveling * (1 + redundant copy)
+ *
+ * where,
+ * "EEPROM data size" - the size of data the user wants to store in the
+ * EEPROM. The data size must divide evenly to the half of the flash row size.
+ * "wear leveling" - the wear leveling factor (1-10).
+ * "redundant copy" - "zero" if a redundant copy is not used, and "one"
+ * otherwise.
+ *
+ * The start address of the storage should be filled to the Emulated EEPROM
+ * configuration structure and then passed to the Cy_Em_EEPROM_Init().
+ * If the Em_EEPROM component is used, the config (Em_EEPROM_config) and
+ * context structures (Em_EEPROM_context) are defined by the component, so the
+ * user may just use that structures otherwise both of the structures need to
+ * be provided by the user. Note that if the "Config Data in Flash"
+ * option is selected in the component, then the configuration structure should
+ * be copied to RAM to allow EEPROM storage start address update. The following
+ * code demonstrates utilization of "Em_EEPROM_config" and "Em_EEPROM_context"
+ * Em_EEPROM component structures for Cy_Em_EEPROM middleware library
+ * initialization:
+ *
+ * cy_en_em_eeprom_status_t retValue;
+ * cy_stc_eeprom_config_t config;
+ *
+ * memcpy((void *)&config,
+ (void *)&Em_EEPROM_config,
+ sizeof(cy_stc_eeprom_config_t));
+ * config.userFlashStartAddr = (uint32)emEeprom;
+ * retValue = Cy_Em_EEPROM_Init(&config, &Em_EEPROM_context);
+ *
+ * <b>Initializing EEPROM in Emulated EEPROM flash area</b>
+ *
+ * Initializing of the EEPROM storage in the Emulated EEPROM flash area is
+ * identical to initializing of the EEPROM storage in the User flash with one
+ * difference. The location of the Emulated EEPROM storage should be specified
+ * somewhere in the EmulatedEEPROM flash area. If the Em_EEPROM component is
+ * utilized in the project, then the respective storage
+ * (Em_EEPROM_em_EepromStorage[]) is automatically declared by the component
+ * if the "Use Emulated EEPROM" option is set to "Yes". The user just needs to
+ * fill the start address of the storage to the config structure. If the
+ * Em_EEPROM component is not used, the user needs to declare the storage
+ * in the Emulated EEPROM flash area. An example of such declaration is
+ * following (applicable for GCC and MDK compilers):
+ *
+ * CY_SECTION(".cy_em_eeprom") CY_ALIGN(CY_EM_EEPROM_FLASH_SIZEOF_ROW)
+ * const uint8_t emEeprom[Em_EEPROM_PHYSICAL_SIZE] = {0u};
+ *
+ * The same declaration for the IAR compiler:
+ *
+ * #pragma location = ".cy_em_eeprom"
+ * #pragma data_alignment = CY_EM_EEPROM_FLASH_SIZEOF_ROW
+ * const uint8 emEeprom[Em_EEPROM_PHYSICAL_SIZE] = {0u};
+ *
+ * where,
+ * Em_EEPROM_PHYSICAL_SIZE - is a constant that is generated by the Em_EEPROM
+ * component when the component is utilized in the project or it should be
+ * provided by the user. The equation for the calculation of the constant is
+ * shown above.
+ *
+ * Note that the size of the Emulated EEPROM flash area is limited. Refer to the
+ * specific device datasheet for the value of the available EEPROM Emulation
+ * area.
+ *
+ * \section group_em_eeprom_more_information More Information
+ * See the Em_EEPROM Component datasheet.
+ *
+ *
+ * \section group_em_eeprom_MISRA MISRA-C Compliance
+ *
+ * The Cy_Em_EEPROM library has the following specific deviations:
+ *
+ * <table class="doxtable">
+ * <tr>
+ * <th>MISRA Rule</th>
+ * <th>Rule Class (Required/Advisory)</th>
+ * <th>Rule Description</th>
+ * <th>Description of Deviation(s)</th>
+ * </tr>
+ * <tr>
+ * <td>11.4</td>
+ * <td>A</td>
+ * <td>The cast should not be performed between a pointer to the object type
+ * and a different pointer to the object type.</td>
+ * <td>The cast from the object type and a different pointer to the object
+ * was used intentionally because of the performance reasons.</td>
+ * </tr>
+ * <tr>
+ * <td>14.2</td>
+ * <td>R</td>
+ * <td>All non-null statements shall either have at least one side-effect,
+ * however executed, or cause control flow to change.</td>
+ * <td>To maintain common codebase, some variables, unused for a specific
+ * device, are casted to void to prevent generation of an unused variable
+ * compiler warning.</td>
+ * </tr>
+ * <tr>
+ * <td>16.7</td>
+ * <td>A</td>
+ * <td>The object addressed by the pointer parameter is not modified and so
+ * the pointer could be of type 'pointer to const'.</td>
+ * <td>The warning is generated because of the pointer dereferencing to
+ * address which makes the MISRA checker think the data is not
+ * modified.</td>
+ * </tr>
+ * <tr>
+ * <td>17.4</td>
+ * <td>R</td>
+ * <td>The array indexing shall be the only allowed form of pointer
+ * arithmetic.</td>
+ * <td>The pointer arithmetic used in several places on the Cy_Em_EEPROM
+ * implementation is safe and preferred because it increases the code
+ * flexibility.</td>
+ * </tr>
+ * <tr>
+ * <td>19.7</td>
+ * <td>A</td>
+ * <td>A function shall be used in preference to a function-like macro.</td>
+ * <td>Macro is used because of performance reasons.</td>
+ * </tr>
+ * </table>
+ *
+ * \section group_em_eeprom_changelog Changelog
+ * <table class="doxtable">
+ * <tr><th>Version</th><th>Changes</th><th>Reason for Change</th></tr>
+ * <tr>
+ * <td>1.0</td>
+ * <td>Initial Version</td>
+ * <td></td>
+ * </tr>
+ * </table>
+ *
+ * \defgroup group_em_eeprom_macros Macros
+ * \brief
+ * This section describes the Emulated EEPROM Macros.
+ *
+ * \defgroup group_em_eeprom_functions Functions
+ * \brief
+ * This section describes the Emulated EEPROM Function Prototypes.
+ *
+ * \defgroup group_em_eeprom_data_structures Data Structures
+ * \brief
+ * Describes the data structures defined by the Emulated EEPROM.
+ *
+ * \defgroup group_em_eeprom_enums Enumerated types
+ * \brief
+ * Describes the enumeration types defined by the Emulated EEPROM.
+ *
+ */
+
+
+#if !defined(CY_EM_EEPROM_H)
+#define CY_EM_EEPROM_H
+
+#include "cytypes.h"
+#include <stddef.h>
+#if (CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC6)
+ #include <cy_device_headers.h>
+ #include "syslib/cy_syslib.h"
+ #include "flash/cy_flash.h"
+#else
+ #include "CyFlash.h"
+ #include <cyfitter.h>
+#endif /* (CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC6) */
+
+/* The C binding of definitions if building with the C++ compiler */
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+
+/***************************************
+* Conditional Compilation Parameters
+***************************************/
+#define CY_PSOC6 (CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC6)
+
+
+/***************************************
+* Data Structure definitions
+***************************************/
+/**
+* \addtogroup group_em_eeprom_data_structures
+* \{
+*/
+
+/** EEPROM configuration structure */
+typedef struct
+{
+ /** The number of bytes to store in EEPROM */
+ uint32 eepromSize;
+
+ /** The amount of wear leveling from 1 to 10. 1 means no wear leveling
+ * is used.
+ */
+ uint32 wearLevelingFactor;
+
+ /** If not zero, a redundant copy of the Em_EEPROM is included. */
+ uint8 redundantCopy;
+
+ /** If not zero, a blocking write to flash is used. Otherwise non-blocking
+ * write is used. This parameter is used only for PSoC 6.
+ */
+ uint8 blockingWrite;
+
+ /** The start address for the EEPROM memory in the user's flash. */
+ uint32 userFlashStartAddr;
+} cy_stc_eeprom_config_t;
+
+/** \} group_em_eeprom_data_structures */
+
+/** The EEPROM context data structure. It is used to store the specific
+* EEPROM context data.
+*/
+typedef struct
+{
+ /** The pointer to the end address of EEPROM including wear leveling overhead
+ * and excluding redundant copy overhead.
+ */
+ uint32 wlEndAddr;
+
+ /** The number of flash rows allocated for the EEPROM excluding the number of
+ * rows allocated for wear leveling and redundant copy overhead.
+ */
+ uint32 numberOfRows;
+
+ /** The address of the last written EEPROM row */
+ uint32 lastWrRowAddr;
+
+ /** The number of bytes to store in EEPROM */
+ uint32 eepromSize;
+
+ /** The amount of wear leveling from 1 to 10. 1 means no wear leveling
+ * is used.
+ */
+ uint32 wearLevelingFactor;
+
+ /** If not zero, a redundant copy of the Em_EEPROM is included. */
+ uint8 redundantCopy;
+
+ /** If not zero, a blocking write to flash is used. Otherwise non-blocking
+ * write is used. This parameter is used only for PSoC 6.
+ */
+ uint8 blockingWrite;
+
+ /** The start address for the EEPROM memory in the user's flash. */
+ uint32 userFlashStartAddr;
+} cy_stc_eeprom_context_t;
+
+#if (CY_PSOC6)
+
+ #define CY_EM_EEPROM_ID (CY_PDL_DRV_ID(0x1BuL)) /**< Em_EEPROM PDL ID */
+ /**
+ * \addtogroup group_em_eeprom_enums
+ * \{
+ * Specifies return values meaning.
+ */
+ /** A prefix for EEPROM function error return-values */
+ #define CY_EM_EEPROM_ID_ERROR (uint32_t)(CY_EM_EEPROM_ID | CY_PDL_STATUS_ERROR)
+
+#else
+
+ /** A prefix for EEPROM function status codes. For non-PSoC6 devices,
+ * prefix is zero.
+ */
+ #define CY_EM_EEPROM_ID_ERROR (0uL)
+
+#endif /* (CY_PSOC6) */
+
+
+/***************************************
+* Enumerated Types and Parameters
+***************************************/
+
+/** EEPROM return enumeration type */
+typedef enum
+{
+ CY_EM_EEPROM_SUCCESS = 0x00uL, /**< The function executed successfully */
+ CY_EM_EEPROM_BAD_PARAM = (CY_EM_EEPROM_ID_ERROR + 1uL), /**< The input parameter is invalid */
+ CY_EM_EEPROM_BAD_CHECKSUM = (CY_EM_EEPROM_ID_ERROR + 2uL), /**< The data in EEPROM is corrupted */
+ CY_EM_EEPROM_BAD_DATA = (CY_EM_EEPROM_ID_ERROR + 3uL), /**< Failed to place the EEPROM in flash */
+ CY_EM_EEPROM_WRITE_FAIL = (CY_EM_EEPROM_ID_ERROR + 4uL) /**< Write to EEPROM failed */
+} cy_en_em_eeprom_status_t;
+
+/** \} group_em_eeprom_enums */
+
+
+/***************************************
+* Function Prototypes
+***************************************/
+
+/**
+* \addtogroup group_em_eeprom_functions
+* \{
+*/
+cy_en_em_eeprom_status_t Cy_Em_EEPROM_Init(cy_stc_eeprom_config_t* config, cy_stc_eeprom_context_t * context);
+cy_en_em_eeprom_status_t Cy_Em_EEPROM_Read(uint32 addr,
+ void * eepromData,
+ uint32 size,
+ cy_stc_eeprom_context_t * context);
+cy_en_em_eeprom_status_t Cy_Em_EEPROM_Write(uint32 addr,
+ void * eepromData,
+ uint32 size,
+ cy_stc_eeprom_context_t * context);
+cy_en_em_eeprom_status_t Cy_Em_EEPROM_Erase(cy_stc_eeprom_context_t * context);
+uint32 Cy_Em_EEPROM_NumWrites(cy_stc_eeprom_context_t * context);
+/** \} group_em_eeprom_functions */
+
+
+/***************************************
+* API Constants
+***************************************/
+/**
+* \addtogroup group_em_eeprom_macros
+* \{
+*/
+/** Library major version */
+#define CY_EM_EEPROM_VERSION_MAJOR (2)
+
+/** Library minor version */
+#define CY_EM_EEPROM_VERSION_MINOR (0)
+
+/** Defines the maximum data length that can be stored in one flash row */
+#define CY_EM_EEPROM_EEPROM_DATA_LEN (CY_EM_EEPROM_FLASH_SIZEOF_ROW / 2u)
+
+/** \} group_em_eeprom_macros */
+
+
+/***************************************
+* Macro definitions
+***************************************/
+/** \cond INTERNAL */
+
+/* Defines the size of flash row */
+#define CY_EM_EEPROM_FLASH_SIZEOF_ROW (CY_FLASH_SIZEOF_ROW)
+
+/* Device specific flash constants */
+#if (!CY_PSOC6)
+ #define CY_EM_EEPROM_FLASH_BASE_ADDR (CYDEV_FLASH_BASE)
+ #define CY_EM_EEPROM_FLASH_SIZE (CYDEV_FLASH_SIZE)
+ #define CY_EM_EEPROM_ROWS_IN_ARRAY (CY_FLASH_SIZEOF_ARRAY / CY_EM_EEPROM_FLASH_SIZEOF_ROW)
+ #if (CY_PSOC3)
+ #define CY_EM_EEPROM_CODE_MEM_CLASS_PREFIX (0xff0000uL)
+ #define CY_EM_EEPROM_CODE_ADDR_END \
+ (CY_EM_EEPROM_CODE_MEM_CLASS_PREFIX + (CY_EM_EEPROM_FLASH_SIZE - 1u))
+ #define CY_EM_EEPROM_CODE_ADDR_MASK (0xffffu)
+ /* Checks if the EEPROM is in flash range */
+ #define CY_EM_EEPROM_IS_IN_FLASH_RANGE(startAddr, endAddr) \
+ (((startAddr) > CY_EM_EEPROM_CODE_MEM_CLASS_PREFIX) && \
+ ((endAddr) <= CY_EM_EEPROM_CODE_ADDR_END))
+ #else
+ /* Checks is the EEPROM is in flash range */
+ #define CY_EM_EEPROM_IS_IN_FLASH_RANGE(startAddr, endAddr) \
+ (((startAddr) > CY_EM_EEPROM_FLASH_BASE_ADDR) && ((endAddr) <= CY_EM_EEPROM_FLASH_END_ADDR))
+ #endif /* (CY_PSOC3) */
+#else
+ #define CY_EM_EEPROM_FLASH_BASE_ADDR (CY_FLASH_BASE)
+ #define CY_EM_EEPROM_FLASH_SIZE (CY_FLASH_SIZE)
+ #define CY_EM_EEPROM_EM_EEPROM_BASE_ADDR (CY_EM_EEPROM_BASE)
+ #define CY_EM_EEPROM_EM_EEPROM_SIZE (CY_EM_EEPROM_SIZE)
+ #define CY_EM_EEPROM_EM_EEPROM_END_ADDR (CY_EM_EEPROM_EM_EEPROM_BASE_ADDR + CY_EM_EEPROM_EM_EEPROM_SIZE)
+ /* Checks is the EEPROM is in flash range */
+ #define CY_EM_EEPROM_IS_IN_FLASH_RANGE(startAddr, endAddr) \
+ (((((startAddr) > CY_EM_EEPROM_FLASH_BASE_ADDR) && ((endAddr) <= CY_EM_EEPROM_FLASH_END_ADDR)) || \
+ (((startAddr) >= CY_EM_EEPROM_EM_EEPROM_BASE_ADDR) && \
+ ((endAddr) <= CY_EM_EEPROM_EM_EEPROM_END_ADDR))))
+#endif /* (!CY_PSOC6) */
+
+#define CY_EM_EEPROM_FLASH_END_ADDR (CY_EM_EEPROM_FLASH_BASE_ADDR + CY_EM_EEPROM_FLASH_SIZE)
+
+/* Defines the length of EEPROM data that can be stored in Em_EEPROM header */
+#define CY_EM_EEPROM_HEADER_DATA_LEN ((CY_EM_EEPROM_FLASH_SIZEOF_ROW / 2u) - 16u)
+
+#define CY_EM_EEPROM_ADDR_IN_RANGE (1u)
+
+/* Return CY_EM_EEPROM_ADDR_IN_RANGE if addr exceeded the upper range of
+* EEPROM. The wear leveling overhead is included in the range but redundant copy
+* is excluded.
+*/
+#define CY_EM_EEPROM_IS_ADDR_EXCEED_RANGE(addr, endEepromAddr) \
+ (((addr) >= (endEepromAddr)) ? (0u) : (CY_EM_EEPROM_ADDR_IN_RANGE))
+
+/* Check to see if the specified address is present in the EEPROM */
+#define CY_EM_EEPROM_IS_ADDR_IN_RANGE(addr, startEepromAddr, endEepromAddr) \
+ (((addr) > (startEepromAddr)) ? \
+ (((addr) < (endEepromAddr)) ? (CY_EM_EEPROM_ADDR_IN_RANGE) : (0u)) : (0u))
+
+/* Check if the EEPROM address locations from startAddr1 to endAddr1
+* are crossed with EEPROM address locations from startAddr2 to endAddr2.
+*/
+#define CY_EM_EEPROM_IS_ADDRESES_CROSSING(startAddr1, endAddr1 , startAddr2, endAddr2) \
+ (((startAddr1) > (startAddr2)) ? (((startAddr1) >= (endAddr2)) ? (0u) : (1u) ) : \
+ (((startAddr2) >= (endAddr1)) ? (0u) : (1u)))
+
+/* Return the pointer to the start of the redundant copy of the EEPROM */
+#define CY_EM_EEPROM_GET_REDNT_COPY_ADDR_BASE(numRows, wearLeveling, eepromStartAddr) \
+ ((((numRows) * CY_EM_EEPROM_FLASH_SIZEOF_ROW) * (wearLeveling)) + (eepromStartAddr))
+
+/* Return the number of the row in EM_EEPROM which contains an address defined by
+* rowAddr.
+ */
+#define CY_EM_EEPROM_GET_ACT_ROW_NUM_FROM_ADDR(rowAddr, maxRows, eepromStartAddr) \
+ ((((rowAddr) - (eepromStartAddr)) / CY_EM_EEPROM_FLASH_SIZEOF_ROW) % (maxRows))
+
+
+/** Returns the size allocated for the EEPROM excluding wear leveling and
+* redundant copy overhead.
+*/
+#define CY_EM_EEPROM_GET_EEPROM_SIZE(numRows) ((numRows) * CY_EM_EEPROM_FLASH_SIZEOF_ROW)
+
+/* Check if the given address belongs to the EEPROM address of the row
+* specified by rowNum.
+*/
+#define CY_EM_EEPROM_IS_ADDR_IN_ROW_RANGE(addr, rowNum) \
+ (((addr) < ((rowNum) * (CY_EM_EEPROM_FLASH_SIZEOF_ROW / 2u))) ? (0u) : \
+ (((addr) > ((((rowNum) + 1u) * (CY_EM_EEPROM_FLASH_SIZEOF_ROW / 2u)) - 1u)) ? \
+ (0u) : (1u)))
+
+/* CRC-8 constants */
+#define CY_EM_EEPROM_CRC8_POLYNOM ((uint8)(0x31u))
+#define CY_EM_EEPROM_CRC8_POLYNOM_LEN (8u)
+#define CY_EM_EEPROM_CRC8_SEED (0xFFu)
+#define CY_EM_EEPROM_CRC8_XOR_VAL ((uint8) (0x80u))
+
+#define CY_EM_EEPROM_CALCULATE_CRC8(crc) \
+ ((CY_EM_EEPROM_CRC8_XOR_VAL == ((crc) & CY_EM_EEPROM_CRC8_XOR_VAL)) ? \
+ ((uint8)(((uint8)((uint8)((crc) << 1u))) ^ CY_EM_EEPROM_CRC8_POLYNOM)) : ((uint8)((crc) << 1u)))
+
+#define CY_EM_EEPROM_GET_SEQ_NUM(addr) (*(uint32*)(addr))
+
+/** \endcond */
+
+/**
+* \addtogroup group_em_eeprom_macros
+* \{
+*/
+
+/** Calculate the number of flash rows required to create an Em_EEPROM of
+* dataSize.
+*/
+#define CY_EM_EEPROM_GET_NUM_ROWS_IN_EEPROM(dataSize) \
+ (((dataSize) / (CY_EM_EEPROM_EEPROM_DATA_LEN)) + \
+ ((((dataSize) % (CY_EM_EEPROM_EEPROM_DATA_LEN)) != 0u) ? 1U : 0U))
+
+/** Returns the size of flash allocated for EEPROM including wear leveling and
+* redundant copy overhead.
+*/
+#define CY_EM_EEPROM_GET_PHYSICAL_SIZE(dataSize, wearLeveling, redundantCopy) \
+ (((CY_EM_EEPROM_GET_NUM_ROWS_IN_EEPROM(dataSize) * \
+ CY_EM_EEPROM_FLASH_SIZEOF_ROW) * \
+ (wearLeveling)) * (1uL + (redundantCopy)))
+
+/** \} group_em_eeprom_macros */
+
+
+/******************************************************************************
+* Local definitions
+*******************************************************************************/
+/** \cond INTERNAL */
+
+/* Offsets for 32-bit RAM buffer addressing */
+#define CY_EM_EEPROM_EEPROM_DATA_OFFSET_U32 ((CY_EM_EEPROM_FLASH_SIZEOF_ROW / 2u) / 4u)
+#define CY_EM_EEPROM_HEADER_SEQ_NUM_OFFSET_U32 (0u)
+#define CY_EM_EEPROM_HEADER_ADDR_OFFSET_U32 (1u)
+#define CY_EM_EEPROM_HEADER_LEN_OFFSET_U32 (2u)
+#define CY_EM_EEPROM_HEADER_DATA_OFFSET_U32 (3u)
+#define CY_EM_EEPROM_HEADER_CHECKSUM_OFFSET_U32 (CY_EM_EEPROM_EEPROM_DATA_OFFSET_U32 - 1u)
+
+/* The same offsets as above used for direct memory addressing */
+#define CY_EM_EEPROM_EEPROM_DATA_OFFSET (CY_EM_EEPROM_FLASH_SIZEOF_ROW / 2u)
+#define CY_EM_EEPROM_HEADER_ADDR_OFFSET (4u)
+#define CY_EM_EEPROM_HEADER_LEN_OFFSET (8u)
+#define CY_EM_EEPROM_HEADER_DATA_OFFSET (12u)
+#define CY_EM_EEPROM_HEADER_CHECKSUM_OFFSET (CY_EM_EEPROM_EEPROM_DATA_OFFSET - 4u)
+
+#define CY_EM_EEPROM_U32_DIV (4u)
+
+/* Maximum wear leveling value */
+#define CY_EM_EEPROM_MAX_WEAR_LEVELING_FACTOR (10u)
+
+/* Maximum allowed flash row write/erase operation duration */
+#define CY_EM_EEPROM_MAX_WRITE_DURATION_MS (50u)
+
+/** \endcond */
+
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* CY_EM_EEPROM_H */
+
+
+/* [] END OF FILE */
/*******************************************************************************\r
* File Name: cydevice.h\r
* OBSOLETE: Do not use this file. Use the _trm version instead.\r
-* PSoC Creator 4.1\r
+* PSoC Creator 4.2\r
*\r
* Description:\r
* This file provides all of the address values for the entire PSoC device.\r
* This file is automatically generated by PSoC Creator.\r
*\r
********************************************************************************\r
-* Copyright (c) 2007-2017 Cypress Semiconductor. All rights reserved.\r
+* Copyright (c) 2007-2018 Cypress Semiconductor. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions, \r
* disclaimers, and limitations in the end user license agreement accompanying \r
* the software package with which this file was provided.\r
/*******************************************************************************\r
* File Name: cydevice_trm.h\r
* \r
-* PSoC Creator 4.1\r
+* PSoC Creator 4.2\r
*\r
* Description:\r
* This file provides all of the address values for the entire PSoC device.\r
* This file is automatically generated by PSoC Creator.\r
*\r
********************************************************************************\r
-* Copyright (c) 2007-2017 Cypress Semiconductor. All rights reserved.\r
+* Copyright (c) 2007-2018 Cypress Semiconductor. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions, \r
* disclaimers, and limitations in the end user license agreement accompanying \r
* the software package with which this file was provided.\r
/*******************************************************************************\r
* File Name: cydevicegnu.inc\r
* OBSOLETE: Do not use this file. Use the _trm version instead.\r
-* PSoC Creator 4.1\r
+* PSoC Creator 4.2\r
*\r
* Description:\r
* This file provides all of the address values for the entire PSoC device.\r
* This file is automatically generated by PSoC Creator.\r
*\r
********************************************************************************\r
-* Copyright (c) 2007-2017 Cypress Semiconductor. All rights reserved.\r
+* Copyright (c) 2007-2018 Cypress Semiconductor. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions, \r
* disclaimers, and limitations in the end user license agreement accompanying \r
* the software package with which this file was provided.\r
/*******************************************************************************\r
* File Name: cydevicegnu_trm.inc\r
* \r
-* PSoC Creator 4.1\r
+* PSoC Creator 4.2\r
*\r
* Description:\r
* This file provides all of the address values for the entire PSoC device.\r
* This file is automatically generated by PSoC Creator.\r
*\r
********************************************************************************\r
-* Copyright (c) 2007-2017 Cypress Semiconductor. All rights reserved.\r
+* Copyright (c) 2007-2018 Cypress Semiconductor. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions, \r
* disclaimers, and limitations in the end user license agreement accompanying \r
* the software package with which this file was provided.\r
;\r
; File Name: cydeviceiar.inc\r
; OBSOLETE: Do not use this file. Use the _trm version instead.\r
-; PSoC Creator 4.1\r
+; PSoC Creator 4.2\r
;\r
; Description:\r
; This file provides all of the address values for the entire PSoC device.\r
;\r
;-------------------------------------------------------------------------------\r
-; Copyright (c) 2007-2017 Cypress Semiconductor. All rights reserved.\r
+; Copyright (c) 2007-2018 Cypress Semiconductor. All rights reserved.\r
; You may use this file only in accordance with the license, terms, conditions, \r
; disclaimers, and limitations in the end user license agreement accompanying \r
; the software package with which this file was provided.\r
;\r
; File Name: cydeviceiar_trm.inc\r
; \r
-; PSoC Creator 4.1\r
+; PSoC Creator 4.2\r
;\r
; Description:\r
; This file provides all of the address values for the entire PSoC device.\r
;\r
;-------------------------------------------------------------------------------\r
-; Copyright (c) 2007-2017 Cypress Semiconductor. All rights reserved.\r
+; Copyright (c) 2007-2018 Cypress Semiconductor. All rights reserved.\r
; You may use this file only in accordance with the license, terms, conditions, \r
; disclaimers, and limitations in the end user license agreement accompanying \r
; the software package with which this file was provided.\r
;\r
; File Name: cydevicerv.inc\r
; OBSOLETE: Do not use this file. Use the _trm version instead.\r
-; PSoC Creator 4.1\r
+; PSoC Creator 4.2\r
;\r
; Description:\r
; This file provides all of the address values for the entire PSoC device.\r
;\r
;-------------------------------------------------------------------------------\r
-; Copyright (c) 2007-2017 Cypress Semiconductor. All rights reserved.\r
+; Copyright (c) 2007-2018 Cypress Semiconductor. All rights reserved.\r
; You may use this file only in accordance with the license, terms, conditions, \r
; disclaimers, and limitations in the end user license agreement accompanying \r
; the software package with which this file was provided.\r
;\r
; File Name: cydevicerv_trm.inc\r
; \r
-; PSoC Creator 4.1\r
+; PSoC Creator 4.2\r
;\r
; Description:\r
; This file provides all of the address values for the entire PSoC device.\r
;\r
;-------------------------------------------------------------------------------\r
-; Copyright (c) 2007-2017 Cypress Semiconductor. All rights reserved.\r
+; Copyright (c) 2007-2018 Cypress Semiconductor. All rights reserved.\r
; You may use this file only in accordance with the license, terms, conditions, \r
; disclaimers, and limitations in the end user license agreement accompanying \r
; the software package with which this file was provided.\r
/*******************************************************************************\r
* File Name: cyfitter.h\r
* \r
-* PSoC Creator 4.1\r
+* PSoC Creator 4.2\r
*\r
* Description:\r
* \r
* This file is automatically generated by PSoC Creator.\r
*\r
********************************************************************************\r
-* Copyright (c) 2007-2017 Cypress Semiconductor. All rights reserved.\r
+* Copyright (c) 2007-2018 Cypress Semiconductor. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions, \r
* disclaimers, and limitations in the end user license agreement accompanying \r
* the software package with which this file was provided.\r
#include "cydevice.h"\r
#include "cydevice_trm.h"\r
\r
-/* Debug_Timer_Interrupt */\r
-#define Debug_Timer_Interrupt__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
-#define Debug_Timer_Interrupt__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
-#define Debug_Timer_Interrupt__INTC_MASK 0x01u\r
-#define Debug_Timer_Interrupt__INTC_NUMBER 0u\r
-#define Debug_Timer_Interrupt__INTC_PRIOR_NUM 7u\r
-#define Debug_Timer_Interrupt__INTC_PRIOR_REG CYREG_NVIC_PRI_0\r
-#define Debug_Timer_Interrupt__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
-#define Debug_Timer_Interrupt__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
-\r
-/* Debug_Timer_TimerHW */\r
-#define Debug_Timer_TimerHW__CAP0 CYREG_TMR0_CAP0\r
-#define Debug_Timer_TimerHW__CAP1 CYREG_TMR0_CAP1\r
-#define Debug_Timer_TimerHW__CFG0 CYREG_TMR0_CFG0\r
-#define Debug_Timer_TimerHW__CFG1 CYREG_TMR0_CFG1\r
-#define Debug_Timer_TimerHW__CFG2 CYREG_TMR0_CFG2\r
-#define Debug_Timer_TimerHW__CNT_CMP0 CYREG_TMR0_CNT_CMP0\r
-#define Debug_Timer_TimerHW__CNT_CMP1 CYREG_TMR0_CNT_CMP1\r
-#define Debug_Timer_TimerHW__PER0 CYREG_TMR0_PER0\r
-#define Debug_Timer_TimerHW__PER1 CYREG_TMR0_PER1\r
-#define Debug_Timer_TimerHW__PM_ACT_CFG CYREG_PM_ACT_CFG3\r
-#define Debug_Timer_TimerHW__PM_ACT_MSK 0x01u\r
-#define Debug_Timer_TimerHW__PM_STBY_CFG CYREG_PM_STBY_CFG3\r
-#define Debug_Timer_TimerHW__PM_STBY_MSK 0x01u\r
-#define Debug_Timer_TimerHW__RT0 CYREG_TMR0_RT0\r
-#define Debug_Timer_TimerHW__RT1 CYREG_TMR0_RT1\r
-#define Debug_Timer_TimerHW__SR0 CYREG_TMR0_SR0\r
-\r
/* LED1 */\r
#define LED1__0__INTTYPE CYREG_PICU12_INTTYPE3\r
#define LED1__0__MASK 0x08u\r
#define LED1__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ\r
#define LED1__SLW CYREG_PRT12_SLW\r
\r
-/* SCSI_CLK */\r
-#define SCSI_CLK__CFG0 CYREG_CLKDIST_DCFG1_CFG0\r
-#define SCSI_CLK__CFG1 CYREG_CLKDIST_DCFG1_CFG1\r
-#define SCSI_CLK__CFG2 CYREG_CLKDIST_DCFG1_CFG2\r
-#define SCSI_CLK__CFG2_SRC_SEL_MASK 0x07u\r
-#define SCSI_CLK__INDEX 0x01u\r
-#define SCSI_CLK__PM_ACT_CFG CYREG_PM_ACT_CFG2\r
-#define SCSI_CLK__PM_ACT_MSK 0x02u\r
-#define SCSI_CLK__PM_STBY_CFG CYREG_PM_STBY_CFG2\r
-#define SCSI_CLK__PM_STBY_MSK 0x02u\r
-\r
-/* SCSI_CTL_PHASE */\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK 0x01u\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS 0\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK 0x02u\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS 1\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB05_06_ACTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB05_06_CTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB05_06_CTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB05_06_CTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB05_06_CTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB05_06_MSK\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB05_06_MSK\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB05_06_MSK\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB05_06_MSK\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK 0x04u\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS 2\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB05_ACTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB05_CTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB05_ST_CTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB05_CTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB05_ST_CTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK 0x07u\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB05_MSK\r
-\r
-/* SCSI_Filtered */\r
-#define SCSI_Filtered_sts_sts_reg__0__MASK 0x01u\r
-#define SCSI_Filtered_sts_sts_reg__0__POS 0\r
-#define SCSI_Filtered_sts_sts_reg__1__MASK 0x02u\r
-#define SCSI_Filtered_sts_sts_reg__1__POS 1\r
-#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB02_03_ACTL\r
-#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB02_03_ST\r
-#define SCSI_Filtered_sts_sts_reg__2__MASK 0x04u\r
-#define SCSI_Filtered_sts_sts_reg__2__POS 2\r
-#define SCSI_Filtered_sts_sts_reg__3__MASK 0x08u\r
-#define SCSI_Filtered_sts_sts_reg__3__POS 3\r
-#define SCSI_Filtered_sts_sts_reg__4__MASK 0x10u\r
-#define SCSI_Filtered_sts_sts_reg__4__POS 4\r
-#define SCSI_Filtered_sts_sts_reg__MASK 0x1Fu\r
-#define SCSI_Filtered_sts_sts_reg__MASK_REG CYREG_B0_UDB02_MSK\r
-#define SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB02_ACTL\r
-#define SCSI_Filtered_sts_sts_reg__STATUS_REG CYREG_B0_UDB02_ST\r
+/* SD_CD */\r
+#define SD_CD__0__INTTYPE CYREG_PICU3_INTTYPE6\r
+#define SD_CD__0__MASK 0x40u\r
+#define SD_CD__0__PC CYREG_PRT3_PC6\r
+#define SD_CD__0__PORT 3u\r
+#define SD_CD__0__SHIFT 6u\r
+#define SD_CD__AG CYREG_PRT3_AG\r
+#define SD_CD__AMUX CYREG_PRT3_AMUX\r
+#define SD_CD__BIE CYREG_PRT3_BIE\r
+#define SD_CD__BIT_MASK CYREG_PRT3_BIT_MASK\r
+#define SD_CD__BYP CYREG_PRT3_BYP\r
+#define SD_CD__CTL CYREG_PRT3_CTL\r
+#define SD_CD__DM0 CYREG_PRT3_DM0\r
+#define SD_CD__DM1 CYREG_PRT3_DM1\r
+#define SD_CD__DM2 CYREG_PRT3_DM2\r
+#define SD_CD__DR CYREG_PRT3_DR\r
+#define SD_CD__INP_DIS CYREG_PRT3_INP_DIS\r
+#define SD_CD__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU3_BASE\r
+#define SD_CD__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG\r
+#define SD_CD__LCD_EN CYREG_PRT3_LCD_EN\r
+#define SD_CD__MASK 0x40u\r
+#define SD_CD__PORT 3u\r
+#define SD_CD__PRT CYREG_PRT3_PRT\r
+#define SD_CD__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL\r
+#define SD_CD__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN\r
+#define SD_CD__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0\r
+#define SD_CD__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1\r
+#define SD_CD__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0\r
+#define SD_CD__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1\r
+#define SD_CD__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT\r
+#define SD_CD__PS CYREG_PRT3_PS\r
+#define SD_CD__SHIFT 6u\r
+#define SD_CD__SLW CYREG_PRT3_SLW\r
\r
-/* SCSI_Glitch_Ctl */\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK 0x01u\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS 0\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB07_08_ACTL\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB07_08_CTL\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB07_08_CTL\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB07_08_CTL\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB07_08_CTL\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB07_08_MSK\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB07_08_MSK\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB07_08_MSK\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB07_08_MSK\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB07_ACTL\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB07_CTL\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB07_ST_CTL\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB07_CTL\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB07_ST_CTL\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK 0x01u\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB07_MSK_ACTL\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB07_MSK_ACTL\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB07_MSK\r
-\r
-/* SCSI_In */\r
-#define SCSI_In__0__AG CYREG_PRT2_AG\r
-#define SCSI_In__0__AMUX CYREG_PRT2_AMUX\r
-#define SCSI_In__0__BIE CYREG_PRT2_BIE\r
-#define SCSI_In__0__BIT_MASK CYREG_PRT2_BIT_MASK\r
-#define SCSI_In__0__BYP CYREG_PRT2_BYP\r
-#define SCSI_In__0__CTL CYREG_PRT2_CTL\r
-#define SCSI_In__0__DM0 CYREG_PRT2_DM0\r
-#define SCSI_In__0__DM1 CYREG_PRT2_DM1\r
-#define SCSI_In__0__DM2 CYREG_PRT2_DM2\r
-#define SCSI_In__0__DR CYREG_PRT2_DR\r
-#define SCSI_In__0__INP_DIS CYREG_PRT2_INP_DIS\r
-#define SCSI_In__0__INTTYPE CYREG_PICU2_INTTYPE0\r
-#define SCSI_In__0__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG\r
-#define SCSI_In__0__LCD_EN CYREG_PRT2_LCD_EN\r
-#define SCSI_In__0__MASK 0x01u\r
-#define SCSI_In__0__PC CYREG_PRT2_PC0\r
-#define SCSI_In__0__PORT 2u\r
-#define SCSI_In__0__PRT CYREG_PRT2_PRT\r
-#define SCSI_In__0__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL\r
-#define SCSI_In__0__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN\r
-#define SCSI_In__0__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0\r
-#define SCSI_In__0__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1\r
-#define SCSI_In__0__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0\r
-#define SCSI_In__0__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1\r
-#define SCSI_In__0__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT\r
-#define SCSI_In__0__PS CYREG_PRT2_PS\r
-#define SCSI_In__0__SHIFT 0u\r
-#define SCSI_In__0__SLW CYREG_PRT2_SLW\r
-#define SCSI_In__1__AG CYREG_PRT6_AG\r
-#define SCSI_In__1__AMUX CYREG_PRT6_AMUX\r
-#define SCSI_In__1__BIE CYREG_PRT6_BIE\r
-#define SCSI_In__1__BIT_MASK CYREG_PRT6_BIT_MASK\r
-#define SCSI_In__1__BYP CYREG_PRT6_BYP\r
-#define SCSI_In__1__CTL CYREG_PRT6_CTL\r
-#define SCSI_In__1__DM0 CYREG_PRT6_DM0\r
-#define SCSI_In__1__DM1 CYREG_PRT6_DM1\r
-#define SCSI_In__1__DM2 CYREG_PRT6_DM2\r
-#define SCSI_In__1__DR CYREG_PRT6_DR\r
-#define SCSI_In__1__INP_DIS CYREG_PRT6_INP_DIS\r
-#define SCSI_In__1__INTTYPE CYREG_PICU6_INTTYPE7\r
-#define SCSI_In__1__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
-#define SCSI_In__1__LCD_EN CYREG_PRT6_LCD_EN\r
-#define SCSI_In__1__MASK 0x80u\r
-#define SCSI_In__1__PC CYREG_PRT6_PC7\r
-#define SCSI_In__1__PORT 6u\r
-#define SCSI_In__1__PRT CYREG_PRT6_PRT\r
-#define SCSI_In__1__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
-#define SCSI_In__1__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
-#define SCSI_In__1__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
-#define SCSI_In__1__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
-#define SCSI_In__1__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
-#define SCSI_In__1__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
-#define SCSI_In__1__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
-#define SCSI_In__1__PS CYREG_PRT6_PS\r
-#define SCSI_In__1__SHIFT 7u\r
-#define SCSI_In__1__SLW CYREG_PRT6_SLW\r
-#define SCSI_In__2__AG CYREG_PRT5_AG\r
-#define SCSI_In__2__AMUX CYREG_PRT5_AMUX\r
-#define SCSI_In__2__BIE CYREG_PRT5_BIE\r
-#define SCSI_In__2__BIT_MASK CYREG_PRT5_BIT_MASK\r
-#define SCSI_In__2__BYP CYREG_PRT5_BYP\r
-#define SCSI_In__2__CTL CYREG_PRT5_CTL\r
-#define SCSI_In__2__DM0 CYREG_PRT5_DM0\r
-#define SCSI_In__2__DM1 CYREG_PRT5_DM1\r
-#define SCSI_In__2__DM2 CYREG_PRT5_DM2\r
-#define SCSI_In__2__DR CYREG_PRT5_DR\r
-#define SCSI_In__2__INP_DIS CYREG_PRT5_INP_DIS\r
-#define SCSI_In__2__INTTYPE CYREG_PICU5_INTTYPE1\r
-#define SCSI_In__2__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG\r
-#define SCSI_In__2__LCD_EN CYREG_PRT5_LCD_EN\r
-#define SCSI_In__2__MASK 0x02u\r
-#define SCSI_In__2__PC CYREG_PRT5_PC1\r
-#define SCSI_In__2__PORT 5u\r
-#define SCSI_In__2__PRT CYREG_PRT5_PRT\r
-#define SCSI_In__2__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL\r
-#define SCSI_In__2__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN\r
-#define SCSI_In__2__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0\r
-#define SCSI_In__2__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1\r
-#define SCSI_In__2__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0\r
-#define SCSI_In__2__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1\r
-#define SCSI_In__2__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT\r
-#define SCSI_In__2__PS CYREG_PRT5_PS\r
-#define SCSI_In__2__SHIFT 1u\r
-#define SCSI_In__2__SLW CYREG_PRT5_SLW\r
-#define SCSI_In__3__AG CYREG_PRT5_AG\r
-#define SCSI_In__3__AMUX CYREG_PRT5_AMUX\r
-#define SCSI_In__3__BIE CYREG_PRT5_BIE\r
-#define SCSI_In__3__BIT_MASK CYREG_PRT5_BIT_MASK\r
-#define SCSI_In__3__BYP CYREG_PRT5_BYP\r
-#define SCSI_In__3__CTL CYREG_PRT5_CTL\r
-#define SCSI_In__3__DM0 CYREG_PRT5_DM0\r
-#define SCSI_In__3__DM1 CYREG_PRT5_DM1\r
-#define SCSI_In__3__DM2 CYREG_PRT5_DM2\r
-#define SCSI_In__3__DR CYREG_PRT5_DR\r
-#define SCSI_In__3__INP_DIS CYREG_PRT5_INP_DIS\r
-#define SCSI_In__3__INTTYPE CYREG_PICU5_INTTYPE2\r
-#define SCSI_In__3__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG\r
-#define SCSI_In__3__LCD_EN CYREG_PRT5_LCD_EN\r
-#define SCSI_In__3__MASK 0x04u\r
-#define SCSI_In__3__PC CYREG_PRT5_PC2\r
-#define SCSI_In__3__PORT 5u\r
-#define SCSI_In__3__PRT CYREG_PRT5_PRT\r
-#define SCSI_In__3__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL\r
-#define SCSI_In__3__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN\r
-#define SCSI_In__3__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0\r
-#define SCSI_In__3__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1\r
-#define SCSI_In__3__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0\r
-#define SCSI_In__3__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1\r
-#define SCSI_In__3__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT\r
-#define SCSI_In__3__PS CYREG_PRT5_PS\r
-#define SCSI_In__3__SHIFT 2u\r
-#define SCSI_In__3__SLW CYREG_PRT5_SLW\r
-#define SCSI_In__4__AG CYREG_PRT5_AG\r
-#define SCSI_In__4__AMUX CYREG_PRT5_AMUX\r
-#define SCSI_In__4__BIE CYREG_PRT5_BIE\r
-#define SCSI_In__4__BIT_MASK CYREG_PRT5_BIT_MASK\r
-#define SCSI_In__4__BYP CYREG_PRT5_BYP\r
-#define SCSI_In__4__CTL CYREG_PRT5_CTL\r
-#define SCSI_In__4__DM0 CYREG_PRT5_DM0\r
-#define SCSI_In__4__DM1 CYREG_PRT5_DM1\r
-#define SCSI_In__4__DM2 CYREG_PRT5_DM2\r
-#define SCSI_In__4__DR CYREG_PRT5_DR\r
-#define SCSI_In__4__INP_DIS CYREG_PRT5_INP_DIS\r
-#define SCSI_In__4__INTTYPE CYREG_PICU5_INTTYPE3\r
-#define SCSI_In__4__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG\r
-#define SCSI_In__4__LCD_EN CYREG_PRT5_LCD_EN\r
-#define SCSI_In__4__MASK 0x08u\r
-#define SCSI_In__4__PC CYREG_PRT5_PC3\r
-#define SCSI_In__4__PORT 5u\r
-#define SCSI_In__4__PRT CYREG_PRT5_PRT\r
-#define SCSI_In__4__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL\r
-#define SCSI_In__4__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN\r
-#define SCSI_In__4__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0\r
-#define SCSI_In__4__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1\r
-#define SCSI_In__4__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0\r
-#define SCSI_In__4__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1\r
-#define SCSI_In__4__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT\r
-#define SCSI_In__4__PS CYREG_PRT5_PS\r
-#define SCSI_In__4__SHIFT 3u\r
-#define SCSI_In__4__SLW CYREG_PRT5_SLW\r
-#define SCSI_In__CD__AG CYREG_PRT5_AG\r
-#define SCSI_In__CD__AMUX CYREG_PRT5_AMUX\r
-#define SCSI_In__CD__BIE CYREG_PRT5_BIE\r
-#define SCSI_In__CD__BIT_MASK CYREG_PRT5_BIT_MASK\r
-#define SCSI_In__CD__BYP CYREG_PRT5_BYP\r
-#define SCSI_In__CD__CTL CYREG_PRT5_CTL\r
-#define SCSI_In__CD__DM0 CYREG_PRT5_DM0\r
-#define SCSI_In__CD__DM1 CYREG_PRT5_DM1\r
-#define SCSI_In__CD__DM2 CYREG_PRT5_DM2\r
-#define SCSI_In__CD__DR CYREG_PRT5_DR\r
-#define SCSI_In__CD__INP_DIS CYREG_PRT5_INP_DIS\r
-#define SCSI_In__CD__INTTYPE CYREG_PICU5_INTTYPE1\r
-#define SCSI_In__CD__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG\r
-#define SCSI_In__CD__LCD_EN CYREG_PRT5_LCD_EN\r
-#define SCSI_In__CD__MASK 0x02u\r
-#define SCSI_In__CD__PC CYREG_PRT5_PC1\r
-#define SCSI_In__CD__PORT 5u\r
-#define SCSI_In__CD__PRT CYREG_PRT5_PRT\r
-#define SCSI_In__CD__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL\r
-#define SCSI_In__CD__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN\r
-#define SCSI_In__CD__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0\r
-#define SCSI_In__CD__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1\r
-#define SCSI_In__CD__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0\r
-#define SCSI_In__CD__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1\r
-#define SCSI_In__CD__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT\r
-#define SCSI_In__CD__PS CYREG_PRT5_PS\r
-#define SCSI_In__CD__SHIFT 1u\r
-#define SCSI_In__CD__SLW CYREG_PRT5_SLW\r
-#define SCSI_In__DBP__AG CYREG_PRT2_AG\r
-#define SCSI_In__DBP__AMUX CYREG_PRT2_AMUX\r
-#define SCSI_In__DBP__BIE CYREG_PRT2_BIE\r
-#define SCSI_In__DBP__BIT_MASK CYREG_PRT2_BIT_MASK\r
-#define SCSI_In__DBP__BYP CYREG_PRT2_BYP\r
-#define SCSI_In__DBP__CTL CYREG_PRT2_CTL\r
-#define SCSI_In__DBP__DM0 CYREG_PRT2_DM0\r
-#define SCSI_In__DBP__DM1 CYREG_PRT2_DM1\r
-#define SCSI_In__DBP__DM2 CYREG_PRT2_DM2\r
-#define SCSI_In__DBP__DR CYREG_PRT2_DR\r
-#define SCSI_In__DBP__INP_DIS CYREG_PRT2_INP_DIS\r
-#define SCSI_In__DBP__INTTYPE CYREG_PICU2_INTTYPE0\r
-#define SCSI_In__DBP__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG\r
-#define SCSI_In__DBP__LCD_EN CYREG_PRT2_LCD_EN\r
-#define SCSI_In__DBP__MASK 0x01u\r
-#define SCSI_In__DBP__PC CYREG_PRT2_PC0\r
-#define SCSI_In__DBP__PORT 2u\r
-#define SCSI_In__DBP__PRT CYREG_PRT2_PRT\r
-#define SCSI_In__DBP__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL\r
-#define SCSI_In__DBP__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN\r
-#define SCSI_In__DBP__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0\r
-#define SCSI_In__DBP__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1\r
-#define SCSI_In__DBP__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0\r
-#define SCSI_In__DBP__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1\r
-#define SCSI_In__DBP__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT\r
-#define SCSI_In__DBP__PS CYREG_PRT2_PS\r
-#define SCSI_In__DBP__SHIFT 0u\r
-#define SCSI_In__DBP__SLW CYREG_PRT2_SLW\r
-#define SCSI_In__IO__AG CYREG_PRT5_AG\r
-#define SCSI_In__IO__AMUX CYREG_PRT5_AMUX\r
-#define SCSI_In__IO__BIE CYREG_PRT5_BIE\r
-#define SCSI_In__IO__BIT_MASK CYREG_PRT5_BIT_MASK\r
-#define SCSI_In__IO__BYP CYREG_PRT5_BYP\r
-#define SCSI_In__IO__CTL CYREG_PRT5_CTL\r
-#define SCSI_In__IO__DM0 CYREG_PRT5_DM0\r
-#define SCSI_In__IO__DM1 CYREG_PRT5_DM1\r
-#define SCSI_In__IO__DM2 CYREG_PRT5_DM2\r
-#define SCSI_In__IO__DR CYREG_PRT5_DR\r
-#define SCSI_In__IO__INP_DIS CYREG_PRT5_INP_DIS\r
-#define SCSI_In__IO__INTTYPE CYREG_PICU5_INTTYPE3\r
-#define SCSI_In__IO__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG\r
-#define SCSI_In__IO__LCD_EN CYREG_PRT5_LCD_EN\r
-#define SCSI_In__IO__MASK 0x08u\r
-#define SCSI_In__IO__PC CYREG_PRT5_PC3\r
-#define SCSI_In__IO__PORT 5u\r
-#define SCSI_In__IO__PRT CYREG_PRT5_PRT\r
-#define SCSI_In__IO__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL\r
-#define SCSI_In__IO__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN\r
-#define SCSI_In__IO__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0\r
-#define SCSI_In__IO__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1\r
-#define SCSI_In__IO__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0\r
-#define SCSI_In__IO__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1\r
-#define SCSI_In__IO__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT\r
-#define SCSI_In__IO__PS CYREG_PRT5_PS\r
-#define SCSI_In__IO__SHIFT 3u\r
-#define SCSI_In__IO__SLW CYREG_PRT5_SLW\r
-#define SCSI_In__MSG__AG CYREG_PRT6_AG\r
-#define SCSI_In__MSG__AMUX CYREG_PRT6_AMUX\r
-#define SCSI_In__MSG__BIE CYREG_PRT6_BIE\r
-#define SCSI_In__MSG__BIT_MASK CYREG_PRT6_BIT_MASK\r
-#define SCSI_In__MSG__BYP CYREG_PRT6_BYP\r
-#define SCSI_In__MSG__CTL CYREG_PRT6_CTL\r
-#define SCSI_In__MSG__DM0 CYREG_PRT6_DM0\r
-#define SCSI_In__MSG__DM1 CYREG_PRT6_DM1\r
-#define SCSI_In__MSG__DM2 CYREG_PRT6_DM2\r
-#define SCSI_In__MSG__DR CYREG_PRT6_DR\r
-#define SCSI_In__MSG__INP_DIS CYREG_PRT6_INP_DIS\r
-#define SCSI_In__MSG__INTTYPE CYREG_PICU6_INTTYPE7\r
-#define SCSI_In__MSG__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
-#define SCSI_In__MSG__LCD_EN CYREG_PRT6_LCD_EN\r
-#define SCSI_In__MSG__MASK 0x80u\r
-#define SCSI_In__MSG__PC CYREG_PRT6_PC7\r
-#define SCSI_In__MSG__PORT 6u\r
-#define SCSI_In__MSG__PRT CYREG_PRT6_PRT\r
-#define SCSI_In__MSG__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
-#define SCSI_In__MSG__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
-#define SCSI_In__MSG__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
-#define SCSI_In__MSG__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
-#define SCSI_In__MSG__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
-#define SCSI_In__MSG__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
-#define SCSI_In__MSG__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
-#define SCSI_In__MSG__PS CYREG_PRT6_PS\r
-#define SCSI_In__MSG__SHIFT 7u\r
-#define SCSI_In__MSG__SLW CYREG_PRT6_SLW\r
-#define SCSI_In__REQ__AG CYREG_PRT5_AG\r
-#define SCSI_In__REQ__AMUX CYREG_PRT5_AMUX\r
-#define SCSI_In__REQ__BIE CYREG_PRT5_BIE\r
-#define SCSI_In__REQ__BIT_MASK CYREG_PRT5_BIT_MASK\r
-#define SCSI_In__REQ__BYP CYREG_PRT5_BYP\r
-#define SCSI_In__REQ__CTL CYREG_PRT5_CTL\r
-#define SCSI_In__REQ__DM0 CYREG_PRT5_DM0\r
-#define SCSI_In__REQ__DM1 CYREG_PRT5_DM1\r
-#define SCSI_In__REQ__DM2 CYREG_PRT5_DM2\r
-#define SCSI_In__REQ__DR CYREG_PRT5_DR\r
-#define SCSI_In__REQ__INP_DIS CYREG_PRT5_INP_DIS\r
-#define SCSI_In__REQ__INTTYPE CYREG_PICU5_INTTYPE2\r
-#define SCSI_In__REQ__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG\r
-#define SCSI_In__REQ__LCD_EN CYREG_PRT5_LCD_EN\r
-#define SCSI_In__REQ__MASK 0x04u\r
-#define SCSI_In__REQ__PC CYREG_PRT5_PC2\r
-#define SCSI_In__REQ__PORT 5u\r
-#define SCSI_In__REQ__PRT CYREG_PRT5_PRT\r
-#define SCSI_In__REQ__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL\r
-#define SCSI_In__REQ__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN\r
-#define SCSI_In__REQ__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0\r
-#define SCSI_In__REQ__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1\r
-#define SCSI_In__REQ__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0\r
-#define SCSI_In__REQ__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1\r
-#define SCSI_In__REQ__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT\r
-#define SCSI_In__REQ__PS CYREG_PRT5_PS\r
-#define SCSI_In__REQ__SHIFT 2u\r
-#define SCSI_In__REQ__SLW CYREG_PRT5_SLW\r
-#define SCSI_In_DBx__0__AG CYREG_PRT12_AG\r
-#define SCSI_In_DBx__0__BIE CYREG_PRT12_BIE\r
-#define SCSI_In_DBx__0__BIT_MASK CYREG_PRT12_BIT_MASK\r
-#define SCSI_In_DBx__0__BYP CYREG_PRT12_BYP\r
-#define SCSI_In_DBx__0__DM0 CYREG_PRT12_DM0\r
-#define SCSI_In_DBx__0__DM1 CYREG_PRT12_DM1\r
-#define SCSI_In_DBx__0__DM2 CYREG_PRT12_DM2\r
-#define SCSI_In_DBx__0__DR CYREG_PRT12_DR\r
-#define SCSI_In_DBx__0__INP_DIS CYREG_PRT12_INP_DIS\r
-#define SCSI_In_DBx__0__INTTYPE CYREG_PICU12_INTTYPE4\r
-#define SCSI_In_DBx__0__MASK 0x10u\r
-#define SCSI_In_DBx__0__PC CYREG_PRT12_PC4\r
-#define SCSI_In_DBx__0__PORT 12u\r
-#define SCSI_In_DBx__0__PRT CYREG_PRT12_PRT\r
-#define SCSI_In_DBx__0__PRTDSI__DBL_SYNC_IN CYREG_PRT12_DBL_SYNC_IN\r
-#define SCSI_In_DBx__0__PRTDSI__OE_SEL0 CYREG_PRT12_OE_SEL0\r
-#define SCSI_In_DBx__0__PRTDSI__OE_SEL1 CYREG_PRT12_OE_SEL1\r
-#define SCSI_In_DBx__0__PRTDSI__OUT_SEL0 CYREG_PRT12_OUT_SEL0\r
-#define SCSI_In_DBx__0__PRTDSI__OUT_SEL1 CYREG_PRT12_OUT_SEL1\r
-#define SCSI_In_DBx__0__PRTDSI__SYNC_OUT CYREG_PRT12_SYNC_OUT\r
-#define SCSI_In_DBx__0__PS CYREG_PRT12_PS\r
-#define SCSI_In_DBx__0__SHIFT 4u\r
-#define SCSI_In_DBx__0__SIO_CFG CYREG_PRT12_SIO_CFG\r
-#define SCSI_In_DBx__0__SIO_DIFF CYREG_PRT12_SIO_DIFF\r
-#define SCSI_In_DBx__0__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN\r
-#define SCSI_In_DBx__0__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ\r
-#define SCSI_In_DBx__0__SLW CYREG_PRT12_SLW\r
-#define SCSI_In_DBx__1__AG CYREG_PRT2_AG\r
-#define SCSI_In_DBx__1__AMUX CYREG_PRT2_AMUX\r
-#define SCSI_In_DBx__1__BIE CYREG_PRT2_BIE\r
-#define SCSI_In_DBx__1__BIT_MASK CYREG_PRT2_BIT_MASK\r
-#define SCSI_In_DBx__1__BYP CYREG_PRT2_BYP\r
-#define SCSI_In_DBx__1__CTL CYREG_PRT2_CTL\r
-#define SCSI_In_DBx__1__DM0 CYREG_PRT2_DM0\r
-#define SCSI_In_DBx__1__DM1 CYREG_PRT2_DM1\r
-#define SCSI_In_DBx__1__DM2 CYREG_PRT2_DM2\r
-#define SCSI_In_DBx__1__DR CYREG_PRT2_DR\r
-#define SCSI_In_DBx__1__INP_DIS CYREG_PRT2_INP_DIS\r
-#define SCSI_In_DBx__1__INTTYPE CYREG_PICU2_INTTYPE7\r
-#define SCSI_In_DBx__1__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG\r
-#define SCSI_In_DBx__1__LCD_EN CYREG_PRT2_LCD_EN\r
-#define SCSI_In_DBx__1__MASK 0x80u\r
-#define SCSI_In_DBx__1__PC CYREG_PRT2_PC7\r
-#define SCSI_In_DBx__1__PORT 2u\r
-#define SCSI_In_DBx__1__PRT CYREG_PRT2_PRT\r
-#define SCSI_In_DBx__1__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL\r
-#define SCSI_In_DBx__1__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN\r
-#define SCSI_In_DBx__1__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0\r
-#define SCSI_In_DBx__1__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1\r
-#define SCSI_In_DBx__1__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0\r
-#define SCSI_In_DBx__1__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1\r
-#define SCSI_In_DBx__1__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT\r
-#define SCSI_In_DBx__1__PS CYREG_PRT2_PS\r
-#define SCSI_In_DBx__1__SHIFT 7u\r
-#define SCSI_In_DBx__1__SLW CYREG_PRT2_SLW\r
-#define SCSI_In_DBx__2__AG CYREG_PRT2_AG\r
-#define SCSI_In_DBx__2__AMUX CYREG_PRT2_AMUX\r
-#define SCSI_In_DBx__2__BIE CYREG_PRT2_BIE\r
-#define SCSI_In_DBx__2__BIT_MASK CYREG_PRT2_BIT_MASK\r
-#define SCSI_In_DBx__2__BYP CYREG_PRT2_BYP\r
-#define SCSI_In_DBx__2__CTL CYREG_PRT2_CTL\r
-#define SCSI_In_DBx__2__DM0 CYREG_PRT2_DM0\r
-#define SCSI_In_DBx__2__DM1 CYREG_PRT2_DM1\r
-#define SCSI_In_DBx__2__DM2 CYREG_PRT2_DM2\r
-#define SCSI_In_DBx__2__DR CYREG_PRT2_DR\r
-#define SCSI_In_DBx__2__INP_DIS CYREG_PRT2_INP_DIS\r
-#define SCSI_In_DBx__2__INTTYPE CYREG_PICU2_INTTYPE6\r
-#define SCSI_In_DBx__2__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG\r
-#define SCSI_In_DBx__2__LCD_EN CYREG_PRT2_LCD_EN\r
-#define SCSI_In_DBx__2__MASK 0x40u\r
-#define SCSI_In_DBx__2__PC CYREG_PRT2_PC6\r
-#define SCSI_In_DBx__2__PORT 2u\r
-#define SCSI_In_DBx__2__PRT CYREG_PRT2_PRT\r
-#define SCSI_In_DBx__2__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL\r
-#define SCSI_In_DBx__2__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN\r
-#define SCSI_In_DBx__2__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0\r
-#define SCSI_In_DBx__2__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1\r
-#define SCSI_In_DBx__2__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0\r
-#define SCSI_In_DBx__2__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1\r
-#define SCSI_In_DBx__2__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT\r
-#define SCSI_In_DBx__2__PS CYREG_PRT2_PS\r
-#define SCSI_In_DBx__2__SHIFT 6u\r
-#define SCSI_In_DBx__2__SLW CYREG_PRT2_SLW\r
-#define SCSI_In_DBx__3__AG CYREG_PRT2_AG\r
-#define SCSI_In_DBx__3__AMUX CYREG_PRT2_AMUX\r
-#define SCSI_In_DBx__3__BIE CYREG_PRT2_BIE\r
-#define SCSI_In_DBx__3__BIT_MASK CYREG_PRT2_BIT_MASK\r
-#define SCSI_In_DBx__3__BYP CYREG_PRT2_BYP\r
-#define SCSI_In_DBx__3__CTL CYREG_PRT2_CTL\r
-#define SCSI_In_DBx__3__DM0 CYREG_PRT2_DM0\r
-#define SCSI_In_DBx__3__DM1 CYREG_PRT2_DM1\r
-#define SCSI_In_DBx__3__DM2 CYREG_PRT2_DM2\r
-#define SCSI_In_DBx__3__DR CYREG_PRT2_DR\r
-#define SCSI_In_DBx__3__INP_DIS CYREG_PRT2_INP_DIS\r
-#define SCSI_In_DBx__3__INTTYPE CYREG_PICU2_INTTYPE5\r
-#define SCSI_In_DBx__3__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG\r
-#define SCSI_In_DBx__3__LCD_EN CYREG_PRT2_LCD_EN\r
-#define SCSI_In_DBx__3__MASK 0x20u\r
-#define SCSI_In_DBx__3__PC CYREG_PRT2_PC5\r
-#define SCSI_In_DBx__3__PORT 2u\r
-#define SCSI_In_DBx__3__PRT CYREG_PRT2_PRT\r
-#define SCSI_In_DBx__3__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL\r
-#define SCSI_In_DBx__3__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN\r
-#define SCSI_In_DBx__3__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0\r
-#define SCSI_In_DBx__3__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1\r
-#define SCSI_In_DBx__3__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0\r
-#define SCSI_In_DBx__3__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1\r
-#define SCSI_In_DBx__3__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT\r
-#define SCSI_In_DBx__3__PS CYREG_PRT2_PS\r
-#define SCSI_In_DBx__3__SHIFT 5u\r
-#define SCSI_In_DBx__3__SLW CYREG_PRT2_SLW\r
-#define SCSI_In_DBx__4__AG CYREG_PRT2_AG\r
-#define SCSI_In_DBx__4__AMUX CYREG_PRT2_AMUX\r
-#define SCSI_In_DBx__4__BIE CYREG_PRT2_BIE\r
-#define SCSI_In_DBx__4__BIT_MASK CYREG_PRT2_BIT_MASK\r
-#define SCSI_In_DBx__4__BYP CYREG_PRT2_BYP\r
-#define SCSI_In_DBx__4__CTL CYREG_PRT2_CTL\r
-#define SCSI_In_DBx__4__DM0 CYREG_PRT2_DM0\r
-#define SCSI_In_DBx__4__DM1 CYREG_PRT2_DM1\r
-#define SCSI_In_DBx__4__DM2 CYREG_PRT2_DM2\r
-#define SCSI_In_DBx__4__DR CYREG_PRT2_DR\r
-#define SCSI_In_DBx__4__INP_DIS CYREG_PRT2_INP_DIS\r
-#define SCSI_In_DBx__4__INTTYPE CYREG_PICU2_INTTYPE4\r
-#define SCSI_In_DBx__4__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG\r
-#define SCSI_In_DBx__4__LCD_EN CYREG_PRT2_LCD_EN\r
-#define SCSI_In_DBx__4__MASK 0x10u\r
-#define SCSI_In_DBx__4__PC CYREG_PRT2_PC4\r
-#define SCSI_In_DBx__4__PORT 2u\r
-#define SCSI_In_DBx__4__PRT CYREG_PRT2_PRT\r
-#define SCSI_In_DBx__4__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL\r
-#define SCSI_In_DBx__4__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN\r
-#define SCSI_In_DBx__4__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0\r
-#define SCSI_In_DBx__4__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1\r
-#define SCSI_In_DBx__4__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0\r
-#define SCSI_In_DBx__4__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1\r
-#define SCSI_In_DBx__4__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT\r
-#define SCSI_In_DBx__4__PS CYREG_PRT2_PS\r
-#define SCSI_In_DBx__4__SHIFT 4u\r
-#define SCSI_In_DBx__4__SLW CYREG_PRT2_SLW\r
-#define SCSI_In_DBx__5__AG CYREG_PRT2_AG\r
-#define SCSI_In_DBx__5__AMUX CYREG_PRT2_AMUX\r
-#define SCSI_In_DBx__5__BIE CYREG_PRT2_BIE\r
-#define SCSI_In_DBx__5__BIT_MASK CYREG_PRT2_BIT_MASK\r
-#define SCSI_In_DBx__5__BYP CYREG_PRT2_BYP\r
-#define SCSI_In_DBx__5__CTL CYREG_PRT2_CTL\r
-#define SCSI_In_DBx__5__DM0 CYREG_PRT2_DM0\r
-#define SCSI_In_DBx__5__DM1 CYREG_PRT2_DM1\r
-#define SCSI_In_DBx__5__DM2 CYREG_PRT2_DM2\r
-#define SCSI_In_DBx__5__DR CYREG_PRT2_DR\r
-#define SCSI_In_DBx__5__INP_DIS CYREG_PRT2_INP_DIS\r
-#define SCSI_In_DBx__5__INTTYPE CYREG_PICU2_INTTYPE3\r
-#define SCSI_In_DBx__5__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG\r
-#define SCSI_In_DBx__5__LCD_EN CYREG_PRT2_LCD_EN\r
-#define SCSI_In_DBx__5__MASK 0x08u\r
-#define SCSI_In_DBx__5__PC CYREG_PRT2_PC3\r
-#define SCSI_In_DBx__5__PORT 2u\r
-#define SCSI_In_DBx__5__PRT CYREG_PRT2_PRT\r
-#define SCSI_In_DBx__5__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL\r
-#define SCSI_In_DBx__5__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN\r
-#define SCSI_In_DBx__5__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0\r
-#define SCSI_In_DBx__5__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1\r
-#define SCSI_In_DBx__5__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0\r
-#define SCSI_In_DBx__5__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1\r
-#define SCSI_In_DBx__5__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT\r
-#define SCSI_In_DBx__5__PS CYREG_PRT2_PS\r
-#define SCSI_In_DBx__5__SHIFT 3u\r
-#define SCSI_In_DBx__5__SLW CYREG_PRT2_SLW\r
-#define SCSI_In_DBx__6__AG CYREG_PRT2_AG\r
-#define SCSI_In_DBx__6__AMUX CYREG_PRT2_AMUX\r
-#define SCSI_In_DBx__6__BIE CYREG_PRT2_BIE\r
-#define SCSI_In_DBx__6__BIT_MASK CYREG_PRT2_BIT_MASK\r
-#define SCSI_In_DBx__6__BYP CYREG_PRT2_BYP\r
-#define SCSI_In_DBx__6__CTL CYREG_PRT2_CTL\r
-#define SCSI_In_DBx__6__DM0 CYREG_PRT2_DM0\r
-#define SCSI_In_DBx__6__DM1 CYREG_PRT2_DM1\r
-#define SCSI_In_DBx__6__DM2 CYREG_PRT2_DM2\r
-#define SCSI_In_DBx__6__DR CYREG_PRT2_DR\r
-#define SCSI_In_DBx__6__INP_DIS CYREG_PRT2_INP_DIS\r
-#define SCSI_In_DBx__6__INTTYPE CYREG_PICU2_INTTYPE2\r
-#define SCSI_In_DBx__6__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG\r
-#define SCSI_In_DBx__6__LCD_EN CYREG_PRT2_LCD_EN\r
-#define SCSI_In_DBx__6__MASK 0x04u\r
-#define SCSI_In_DBx__6__PC CYREG_PRT2_PC2\r
-#define SCSI_In_DBx__6__PORT 2u\r
-#define SCSI_In_DBx__6__PRT CYREG_PRT2_PRT\r
-#define SCSI_In_DBx__6__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL\r
-#define SCSI_In_DBx__6__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN\r
-#define SCSI_In_DBx__6__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0\r
-#define SCSI_In_DBx__6__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1\r
-#define SCSI_In_DBx__6__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0\r
-#define SCSI_In_DBx__6__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1\r
-#define SCSI_In_DBx__6__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT\r
-#define SCSI_In_DBx__6__PS CYREG_PRT2_PS\r
-#define SCSI_In_DBx__6__SHIFT 2u\r
-#define SCSI_In_DBx__6__SLW CYREG_PRT2_SLW\r
-#define SCSI_In_DBx__7__AG CYREG_PRT2_AG\r
-#define SCSI_In_DBx__7__AMUX CYREG_PRT2_AMUX\r
-#define SCSI_In_DBx__7__BIE CYREG_PRT2_BIE\r
-#define SCSI_In_DBx__7__BIT_MASK CYREG_PRT2_BIT_MASK\r
-#define SCSI_In_DBx__7__BYP CYREG_PRT2_BYP\r
-#define SCSI_In_DBx__7__CTL CYREG_PRT2_CTL\r
-#define SCSI_In_DBx__7__DM0 CYREG_PRT2_DM0\r
-#define SCSI_In_DBx__7__DM1 CYREG_PRT2_DM1\r
-#define SCSI_In_DBx__7__DM2 CYREG_PRT2_DM2\r
-#define SCSI_In_DBx__7__DR CYREG_PRT2_DR\r
-#define SCSI_In_DBx__7__INP_DIS CYREG_PRT2_INP_DIS\r
-#define SCSI_In_DBx__7__INTTYPE CYREG_PICU2_INTTYPE1\r
-#define SCSI_In_DBx__7__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG\r
-#define SCSI_In_DBx__7__LCD_EN CYREG_PRT2_LCD_EN\r
-#define SCSI_In_DBx__7__MASK 0x02u\r
-#define SCSI_In_DBx__7__PC CYREG_PRT2_PC1\r
-#define SCSI_In_DBx__7__PORT 2u\r
-#define SCSI_In_DBx__7__PRT CYREG_PRT2_PRT\r
-#define SCSI_In_DBx__7__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL\r
-#define SCSI_In_DBx__7__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN\r
-#define SCSI_In_DBx__7__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0\r
-#define SCSI_In_DBx__7__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1\r
-#define SCSI_In_DBx__7__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0\r
-#define SCSI_In_DBx__7__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1\r
-#define SCSI_In_DBx__7__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT\r
-#define SCSI_In_DBx__7__PS CYREG_PRT2_PS\r
-#define SCSI_In_DBx__7__SHIFT 1u\r
-#define SCSI_In_DBx__7__SLW CYREG_PRT2_SLW\r
-#define SCSI_In_DBx__DB0__AG CYREG_PRT12_AG\r
-#define SCSI_In_DBx__DB0__BIE CYREG_PRT12_BIE\r
-#define SCSI_In_DBx__DB0__BIT_MASK CYREG_PRT12_BIT_MASK\r
-#define SCSI_In_DBx__DB0__BYP CYREG_PRT12_BYP\r
-#define SCSI_In_DBx__DB0__DM0 CYREG_PRT12_DM0\r
-#define SCSI_In_DBx__DB0__DM1 CYREG_PRT12_DM1\r
-#define SCSI_In_DBx__DB0__DM2 CYREG_PRT12_DM2\r
-#define SCSI_In_DBx__DB0__DR CYREG_PRT12_DR\r
-#define SCSI_In_DBx__DB0__INP_DIS CYREG_PRT12_INP_DIS\r
-#define SCSI_In_DBx__DB0__INTTYPE CYREG_PICU12_INTTYPE4\r
-#define SCSI_In_DBx__DB0__MASK 0x10u\r
-#define SCSI_In_DBx__DB0__PC CYREG_PRT12_PC4\r
-#define SCSI_In_DBx__DB0__PORT 12u\r
-#define SCSI_In_DBx__DB0__PRT CYREG_PRT12_PRT\r
-#define SCSI_In_DBx__DB0__PRTDSI__DBL_SYNC_IN CYREG_PRT12_DBL_SYNC_IN\r
-#define SCSI_In_DBx__DB0__PRTDSI__OE_SEL0 CYREG_PRT12_OE_SEL0\r
-#define SCSI_In_DBx__DB0__PRTDSI__OE_SEL1 CYREG_PRT12_OE_SEL1\r
-#define SCSI_In_DBx__DB0__PRTDSI__OUT_SEL0 CYREG_PRT12_OUT_SEL0\r
-#define SCSI_In_DBx__DB0__PRTDSI__OUT_SEL1 CYREG_PRT12_OUT_SEL1\r
-#define SCSI_In_DBx__DB0__PRTDSI__SYNC_OUT CYREG_PRT12_SYNC_OUT\r
-#define SCSI_In_DBx__DB0__PS CYREG_PRT12_PS\r
-#define SCSI_In_DBx__DB0__SHIFT 4u\r
-#define SCSI_In_DBx__DB0__SIO_CFG CYREG_PRT12_SIO_CFG\r
-#define SCSI_In_DBx__DB0__SIO_DIFF CYREG_PRT12_SIO_DIFF\r
-#define SCSI_In_DBx__DB0__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN\r
-#define SCSI_In_DBx__DB0__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ\r
-#define SCSI_In_DBx__DB0__SLW CYREG_PRT12_SLW\r
-#define SCSI_In_DBx__DB1__AG CYREG_PRT2_AG\r
-#define SCSI_In_DBx__DB1__AMUX CYREG_PRT2_AMUX\r
-#define SCSI_In_DBx__DB1__BIE CYREG_PRT2_BIE\r
-#define SCSI_In_DBx__DB1__BIT_MASK CYREG_PRT2_BIT_MASK\r
-#define SCSI_In_DBx__DB1__BYP CYREG_PRT2_BYP\r
-#define SCSI_In_DBx__DB1__CTL CYREG_PRT2_CTL\r
-#define SCSI_In_DBx__DB1__DM0 CYREG_PRT2_DM0\r
-#define SCSI_In_DBx__DB1__DM1 CYREG_PRT2_DM1\r
-#define SCSI_In_DBx__DB1__DM2 CYREG_PRT2_DM2\r
-#define SCSI_In_DBx__DB1__DR CYREG_PRT2_DR\r
-#define SCSI_In_DBx__DB1__INP_DIS CYREG_PRT2_INP_DIS\r
-#define SCSI_In_DBx__DB1__INTTYPE CYREG_PICU2_INTTYPE7\r
-#define SCSI_In_DBx__DB1__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG\r
-#define SCSI_In_DBx__DB1__LCD_EN CYREG_PRT2_LCD_EN\r
-#define SCSI_In_DBx__DB1__MASK 0x80u\r
-#define SCSI_In_DBx__DB1__PC CYREG_PRT2_PC7\r
-#define SCSI_In_DBx__DB1__PORT 2u\r
-#define SCSI_In_DBx__DB1__PRT CYREG_PRT2_PRT\r
-#define SCSI_In_DBx__DB1__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL\r
-#define SCSI_In_DBx__DB1__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN\r
-#define SCSI_In_DBx__DB1__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0\r
-#define SCSI_In_DBx__DB1__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1\r
-#define SCSI_In_DBx__DB1__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0\r
-#define SCSI_In_DBx__DB1__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1\r
-#define SCSI_In_DBx__DB1__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT\r
-#define SCSI_In_DBx__DB1__PS CYREG_PRT2_PS\r
-#define SCSI_In_DBx__DB1__SHIFT 7u\r
-#define SCSI_In_DBx__DB1__SLW CYREG_PRT2_SLW\r
-#define SCSI_In_DBx__DB2__AG CYREG_PRT2_AG\r
-#define SCSI_In_DBx__DB2__AMUX CYREG_PRT2_AMUX\r
-#define SCSI_In_DBx__DB2__BIE CYREG_PRT2_BIE\r
-#define SCSI_In_DBx__DB2__BIT_MASK CYREG_PRT2_BIT_MASK\r
-#define SCSI_In_DBx__DB2__BYP CYREG_PRT2_BYP\r
-#define SCSI_In_DBx__DB2__CTL CYREG_PRT2_CTL\r
-#define SCSI_In_DBx__DB2__DM0 CYREG_PRT2_DM0\r
-#define SCSI_In_DBx__DB2__DM1 CYREG_PRT2_DM1\r
-#define SCSI_In_DBx__DB2__DM2 CYREG_PRT2_DM2\r
-#define SCSI_In_DBx__DB2__DR CYREG_PRT2_DR\r
-#define SCSI_In_DBx__DB2__INP_DIS CYREG_PRT2_INP_DIS\r
-#define SCSI_In_DBx__DB2__INTTYPE CYREG_PICU2_INTTYPE6\r
-#define SCSI_In_DBx__DB2__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG\r
-#define SCSI_In_DBx__DB2__LCD_EN CYREG_PRT2_LCD_EN\r
-#define SCSI_In_DBx__DB2__MASK 0x40u\r
-#define SCSI_In_DBx__DB2__PC CYREG_PRT2_PC6\r
-#define SCSI_In_DBx__DB2__PORT 2u\r
-#define SCSI_In_DBx__DB2__PRT CYREG_PRT2_PRT\r
-#define SCSI_In_DBx__DB2__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL\r
-#define SCSI_In_DBx__DB2__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN\r
-#define SCSI_In_DBx__DB2__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0\r
-#define SCSI_In_DBx__DB2__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1\r
-#define SCSI_In_DBx__DB2__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0\r
-#define SCSI_In_DBx__DB2__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1\r
-#define SCSI_In_DBx__DB2__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT\r
-#define SCSI_In_DBx__DB2__PS CYREG_PRT2_PS\r
-#define SCSI_In_DBx__DB2__SHIFT 6u\r
-#define SCSI_In_DBx__DB2__SLW CYREG_PRT2_SLW\r
-#define SCSI_In_DBx__DB3__AG CYREG_PRT2_AG\r
-#define SCSI_In_DBx__DB3__AMUX CYREG_PRT2_AMUX\r
-#define SCSI_In_DBx__DB3__BIE CYREG_PRT2_BIE\r
-#define SCSI_In_DBx__DB3__BIT_MASK CYREG_PRT2_BIT_MASK\r
-#define SCSI_In_DBx__DB3__BYP CYREG_PRT2_BYP\r
-#define SCSI_In_DBx__DB3__CTL CYREG_PRT2_CTL\r
-#define SCSI_In_DBx__DB3__DM0 CYREG_PRT2_DM0\r
-#define SCSI_In_DBx__DB3__DM1 CYREG_PRT2_DM1\r
-#define SCSI_In_DBx__DB3__DM2 CYREG_PRT2_DM2\r
-#define SCSI_In_DBx__DB3__DR CYREG_PRT2_DR\r
-#define SCSI_In_DBx__DB3__INP_DIS CYREG_PRT2_INP_DIS\r
-#define SCSI_In_DBx__DB3__INTTYPE CYREG_PICU2_INTTYPE5\r
-#define SCSI_In_DBx__DB3__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG\r
-#define SCSI_In_DBx__DB3__LCD_EN CYREG_PRT2_LCD_EN\r
-#define SCSI_In_DBx__DB3__MASK 0x20u\r
-#define SCSI_In_DBx__DB3__PC CYREG_PRT2_PC5\r
-#define SCSI_In_DBx__DB3__PORT 2u\r
-#define SCSI_In_DBx__DB3__PRT CYREG_PRT2_PRT\r
-#define SCSI_In_DBx__DB3__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL\r
-#define SCSI_In_DBx__DB3__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN\r
-#define SCSI_In_DBx__DB3__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0\r
-#define SCSI_In_DBx__DB3__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1\r
-#define SCSI_In_DBx__DB3__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0\r
-#define SCSI_In_DBx__DB3__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1\r
-#define SCSI_In_DBx__DB3__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT\r
-#define SCSI_In_DBx__DB3__PS CYREG_PRT2_PS\r
-#define SCSI_In_DBx__DB3__SHIFT 5u\r
-#define SCSI_In_DBx__DB3__SLW CYREG_PRT2_SLW\r
-#define SCSI_In_DBx__DB4__AG CYREG_PRT2_AG\r
-#define SCSI_In_DBx__DB4__AMUX CYREG_PRT2_AMUX\r
-#define SCSI_In_DBx__DB4__BIE CYREG_PRT2_BIE\r
-#define SCSI_In_DBx__DB4__BIT_MASK CYREG_PRT2_BIT_MASK\r
-#define SCSI_In_DBx__DB4__BYP CYREG_PRT2_BYP\r
-#define SCSI_In_DBx__DB4__CTL CYREG_PRT2_CTL\r
-#define SCSI_In_DBx__DB4__DM0 CYREG_PRT2_DM0\r
-#define SCSI_In_DBx__DB4__DM1 CYREG_PRT2_DM1\r
-#define SCSI_In_DBx__DB4__DM2 CYREG_PRT2_DM2\r
-#define SCSI_In_DBx__DB4__DR CYREG_PRT2_DR\r
-#define SCSI_In_DBx__DB4__INP_DIS CYREG_PRT2_INP_DIS\r
-#define SCSI_In_DBx__DB4__INTTYPE CYREG_PICU2_INTTYPE4\r
-#define SCSI_In_DBx__DB4__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG\r
-#define SCSI_In_DBx__DB4__LCD_EN CYREG_PRT2_LCD_EN\r
-#define SCSI_In_DBx__DB4__MASK 0x10u\r
-#define SCSI_In_DBx__DB4__PC CYREG_PRT2_PC4\r
-#define SCSI_In_DBx__DB4__PORT 2u\r
-#define SCSI_In_DBx__DB4__PRT CYREG_PRT2_PRT\r
-#define SCSI_In_DBx__DB4__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL\r
-#define SCSI_In_DBx__DB4__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN\r
-#define SCSI_In_DBx__DB4__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0\r
-#define SCSI_In_DBx__DB4__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1\r
-#define SCSI_In_DBx__DB4__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0\r
-#define SCSI_In_DBx__DB4__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1\r
-#define SCSI_In_DBx__DB4__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT\r
-#define SCSI_In_DBx__DB4__PS CYREG_PRT2_PS\r
-#define SCSI_In_DBx__DB4__SHIFT 4u\r
-#define SCSI_In_DBx__DB4__SLW CYREG_PRT2_SLW\r
-#define SCSI_In_DBx__DB5__AG CYREG_PRT2_AG\r
-#define SCSI_In_DBx__DB5__AMUX CYREG_PRT2_AMUX\r
-#define SCSI_In_DBx__DB5__BIE CYREG_PRT2_BIE\r
-#define SCSI_In_DBx__DB5__BIT_MASK CYREG_PRT2_BIT_MASK\r
-#define SCSI_In_DBx__DB5__BYP CYREG_PRT2_BYP\r
-#define SCSI_In_DBx__DB5__CTL CYREG_PRT2_CTL\r
-#define SCSI_In_DBx__DB5__DM0 CYREG_PRT2_DM0\r
-#define SCSI_In_DBx__DB5__DM1 CYREG_PRT2_DM1\r
-#define SCSI_In_DBx__DB5__DM2 CYREG_PRT2_DM2\r
-#define SCSI_In_DBx__DB5__DR CYREG_PRT2_DR\r
-#define SCSI_In_DBx__DB5__INP_DIS CYREG_PRT2_INP_DIS\r
-#define SCSI_In_DBx__DB5__INTTYPE CYREG_PICU2_INTTYPE3\r
-#define SCSI_In_DBx__DB5__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG\r
-#define SCSI_In_DBx__DB5__LCD_EN CYREG_PRT2_LCD_EN\r
-#define SCSI_In_DBx__DB5__MASK 0x08u\r
-#define SCSI_In_DBx__DB5__PC CYREG_PRT2_PC3\r
-#define SCSI_In_DBx__DB5__PORT 2u\r
-#define SCSI_In_DBx__DB5__PRT CYREG_PRT2_PRT\r
-#define SCSI_In_DBx__DB5__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL\r
-#define SCSI_In_DBx__DB5__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN\r
-#define SCSI_In_DBx__DB5__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0\r
-#define SCSI_In_DBx__DB5__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1\r
-#define SCSI_In_DBx__DB5__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0\r
-#define SCSI_In_DBx__DB5__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1\r
-#define SCSI_In_DBx__DB5__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT\r
-#define SCSI_In_DBx__DB5__PS CYREG_PRT2_PS\r
-#define SCSI_In_DBx__DB5__SHIFT 3u\r
-#define SCSI_In_DBx__DB5__SLW CYREG_PRT2_SLW\r
-#define SCSI_In_DBx__DB6__AG CYREG_PRT2_AG\r
-#define SCSI_In_DBx__DB6__AMUX CYREG_PRT2_AMUX\r
-#define SCSI_In_DBx__DB6__BIE CYREG_PRT2_BIE\r
-#define SCSI_In_DBx__DB6__BIT_MASK CYREG_PRT2_BIT_MASK\r
-#define SCSI_In_DBx__DB6__BYP CYREG_PRT2_BYP\r
-#define SCSI_In_DBx__DB6__CTL CYREG_PRT2_CTL\r
-#define SCSI_In_DBx__DB6__DM0 CYREG_PRT2_DM0\r
-#define SCSI_In_DBx__DB6__DM1 CYREG_PRT2_DM1\r
-#define SCSI_In_DBx__DB6__DM2 CYREG_PRT2_DM2\r
-#define SCSI_In_DBx__DB6__DR CYREG_PRT2_DR\r
-#define SCSI_In_DBx__DB6__INP_DIS CYREG_PRT2_INP_DIS\r
-#define SCSI_In_DBx__DB6__INTTYPE CYREG_PICU2_INTTYPE2\r
-#define SCSI_In_DBx__DB6__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG\r
-#define SCSI_In_DBx__DB6__LCD_EN CYREG_PRT2_LCD_EN\r
-#define SCSI_In_DBx__DB6__MASK 0x04u\r
-#define SCSI_In_DBx__DB6__PC CYREG_PRT2_PC2\r
-#define SCSI_In_DBx__DB6__PORT 2u\r
-#define SCSI_In_DBx__DB6__PRT CYREG_PRT2_PRT\r
-#define SCSI_In_DBx__DB6__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL\r
-#define SCSI_In_DBx__DB6__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN\r
-#define SCSI_In_DBx__DB6__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0\r
-#define SCSI_In_DBx__DB6__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1\r
-#define SCSI_In_DBx__DB6__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0\r
-#define SCSI_In_DBx__DB6__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1\r
-#define SCSI_In_DBx__DB6__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT\r
-#define SCSI_In_DBx__DB6__PS CYREG_PRT2_PS\r
-#define SCSI_In_DBx__DB6__SHIFT 2u\r
-#define SCSI_In_DBx__DB6__SLW CYREG_PRT2_SLW\r
-#define SCSI_In_DBx__DB7__AG CYREG_PRT2_AG\r
-#define SCSI_In_DBx__DB7__AMUX CYREG_PRT2_AMUX\r
-#define SCSI_In_DBx__DB7__BIE CYREG_PRT2_BIE\r
-#define SCSI_In_DBx__DB7__BIT_MASK CYREG_PRT2_BIT_MASK\r
-#define SCSI_In_DBx__DB7__BYP CYREG_PRT2_BYP\r
-#define SCSI_In_DBx__DB7__CTL CYREG_PRT2_CTL\r
-#define SCSI_In_DBx__DB7__DM0 CYREG_PRT2_DM0\r
-#define SCSI_In_DBx__DB7__DM1 CYREG_PRT2_DM1\r
-#define SCSI_In_DBx__DB7__DM2 CYREG_PRT2_DM2\r
-#define SCSI_In_DBx__DB7__DR CYREG_PRT2_DR\r
-#define SCSI_In_DBx__DB7__INP_DIS CYREG_PRT2_INP_DIS\r
-#define SCSI_In_DBx__DB7__INTTYPE CYREG_PICU2_INTTYPE1\r
-#define SCSI_In_DBx__DB7__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG\r
-#define SCSI_In_DBx__DB7__LCD_EN CYREG_PRT2_LCD_EN\r
-#define SCSI_In_DBx__DB7__MASK 0x02u\r
-#define SCSI_In_DBx__DB7__PC CYREG_PRT2_PC1\r
-#define SCSI_In_DBx__DB7__PORT 2u\r
-#define SCSI_In_DBx__DB7__PRT CYREG_PRT2_PRT\r
-#define SCSI_In_DBx__DB7__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL\r
-#define SCSI_In_DBx__DB7__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN\r
-#define SCSI_In_DBx__DB7__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0\r
-#define SCSI_In_DBx__DB7__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1\r
-#define SCSI_In_DBx__DB7__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0\r
-#define SCSI_In_DBx__DB7__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1\r
-#define SCSI_In_DBx__DB7__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT\r
-#define SCSI_In_DBx__DB7__PS CYREG_PRT2_PS\r
-#define SCSI_In_DBx__DB7__SHIFT 1u\r
-#define SCSI_In_DBx__DB7__SLW CYREG_PRT2_SLW\r
-\r
-/* SCSI_Noise */\r
-#define SCSI_Noise__0__AG CYREG_PRT12_AG\r
-#define SCSI_Noise__0__BIE CYREG_PRT12_BIE\r
-#define SCSI_Noise__0__BIT_MASK CYREG_PRT12_BIT_MASK\r
-#define SCSI_Noise__0__BYP CYREG_PRT12_BYP\r
-#define SCSI_Noise__0__DM0 CYREG_PRT12_DM0\r
-#define SCSI_Noise__0__DM1 CYREG_PRT12_DM1\r
-#define SCSI_Noise__0__DM2 CYREG_PRT12_DM2\r
-#define SCSI_Noise__0__DR CYREG_PRT12_DR\r
-#define SCSI_Noise__0__INP_DIS CYREG_PRT12_INP_DIS\r
-#define SCSI_Noise__0__INTTYPE CYREG_PICU12_INTTYPE5\r
-#define SCSI_Noise__0__MASK 0x20u\r
-#define SCSI_Noise__0__PC CYREG_PRT12_PC5\r
-#define SCSI_Noise__0__PORT 12u\r
-#define SCSI_Noise__0__PRT CYREG_PRT12_PRT\r
-#define SCSI_Noise__0__PRTDSI__DBL_SYNC_IN CYREG_PRT12_DBL_SYNC_IN\r
-#define SCSI_Noise__0__PRTDSI__OE_SEL0 CYREG_PRT12_OE_SEL0\r
-#define SCSI_Noise__0__PRTDSI__OE_SEL1 CYREG_PRT12_OE_SEL1\r
-#define SCSI_Noise__0__PRTDSI__OUT_SEL0 CYREG_PRT12_OUT_SEL0\r
-#define SCSI_Noise__0__PRTDSI__OUT_SEL1 CYREG_PRT12_OUT_SEL1\r
-#define SCSI_Noise__0__PRTDSI__SYNC_OUT CYREG_PRT12_SYNC_OUT\r
-#define SCSI_Noise__0__PS CYREG_PRT12_PS\r
-#define SCSI_Noise__0__SHIFT 5u\r
-#define SCSI_Noise__0__SIO_CFG CYREG_PRT12_SIO_CFG\r
-#define SCSI_Noise__0__SIO_DIFF CYREG_PRT12_SIO_DIFF\r
-#define SCSI_Noise__0__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN\r
-#define SCSI_Noise__0__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ\r
-#define SCSI_Noise__0__SLW CYREG_PRT12_SLW\r
-#define SCSI_Noise__1__AG CYREG_PRT6_AG\r
-#define SCSI_Noise__1__AMUX CYREG_PRT6_AMUX\r
-#define SCSI_Noise__1__BIE CYREG_PRT6_BIE\r
-#define SCSI_Noise__1__BIT_MASK CYREG_PRT6_BIT_MASK\r
-#define SCSI_Noise__1__BYP CYREG_PRT6_BYP\r
-#define SCSI_Noise__1__CTL CYREG_PRT6_CTL\r
-#define SCSI_Noise__1__DM0 CYREG_PRT6_DM0\r
-#define SCSI_Noise__1__DM1 CYREG_PRT6_DM1\r
-#define SCSI_Noise__1__DM2 CYREG_PRT6_DM2\r
-#define SCSI_Noise__1__DR CYREG_PRT6_DR\r
-#define SCSI_Noise__1__INP_DIS CYREG_PRT6_INP_DIS\r
-#define SCSI_Noise__1__INTTYPE CYREG_PICU6_INTTYPE4\r
-#define SCSI_Noise__1__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
-#define SCSI_Noise__1__LCD_EN CYREG_PRT6_LCD_EN\r
-#define SCSI_Noise__1__MASK 0x10u\r
-#define SCSI_Noise__1__PC CYREG_PRT6_PC4\r
-#define SCSI_Noise__1__PORT 6u\r
-#define SCSI_Noise__1__PRT CYREG_PRT6_PRT\r
-#define SCSI_Noise__1__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
-#define SCSI_Noise__1__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
-#define SCSI_Noise__1__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
-#define SCSI_Noise__1__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
-#define SCSI_Noise__1__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
-#define SCSI_Noise__1__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
-#define SCSI_Noise__1__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
-#define SCSI_Noise__1__PS CYREG_PRT6_PS\r
-#define SCSI_Noise__1__SHIFT 4u\r
-#define SCSI_Noise__1__SLW CYREG_PRT6_SLW\r
-#define SCSI_Noise__2__AG CYREG_PRT5_AG\r
-#define SCSI_Noise__2__AMUX CYREG_PRT5_AMUX\r
-#define SCSI_Noise__2__BIE CYREG_PRT5_BIE\r
-#define SCSI_Noise__2__BIT_MASK CYREG_PRT5_BIT_MASK\r
-#define SCSI_Noise__2__BYP CYREG_PRT5_BYP\r
-#define SCSI_Noise__2__CTL CYREG_PRT5_CTL\r
-#define SCSI_Noise__2__DM0 CYREG_PRT5_DM0\r
-#define SCSI_Noise__2__DM1 CYREG_PRT5_DM1\r
-#define SCSI_Noise__2__DM2 CYREG_PRT5_DM2\r
-#define SCSI_Noise__2__DR CYREG_PRT5_DR\r
-#define SCSI_Noise__2__INP_DIS CYREG_PRT5_INP_DIS\r
-#define SCSI_Noise__2__INTTYPE CYREG_PICU5_INTTYPE0\r
-#define SCSI_Noise__2__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG\r
-#define SCSI_Noise__2__LCD_EN CYREG_PRT5_LCD_EN\r
-#define SCSI_Noise__2__MASK 0x01u\r
-#define SCSI_Noise__2__PC CYREG_PRT5_PC0\r
-#define SCSI_Noise__2__PORT 5u\r
-#define SCSI_Noise__2__PRT CYREG_PRT5_PRT\r
-#define SCSI_Noise__2__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL\r
-#define SCSI_Noise__2__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN\r
-#define SCSI_Noise__2__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0\r
-#define SCSI_Noise__2__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1\r
-#define SCSI_Noise__2__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0\r
-#define SCSI_Noise__2__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1\r
-#define SCSI_Noise__2__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT\r
-#define SCSI_Noise__2__PS CYREG_PRT5_PS\r
-#define SCSI_Noise__2__SHIFT 0u\r
-#define SCSI_Noise__2__SLW CYREG_PRT5_SLW\r
-#define SCSI_Noise__3__AG CYREG_PRT6_AG\r
-#define SCSI_Noise__3__AMUX CYREG_PRT6_AMUX\r
-#define SCSI_Noise__3__BIE CYREG_PRT6_BIE\r
-#define SCSI_Noise__3__BIT_MASK CYREG_PRT6_BIT_MASK\r
-#define SCSI_Noise__3__BYP CYREG_PRT6_BYP\r
-#define SCSI_Noise__3__CTL CYREG_PRT6_CTL\r
-#define SCSI_Noise__3__DM0 CYREG_PRT6_DM0\r
-#define SCSI_Noise__3__DM1 CYREG_PRT6_DM1\r
-#define SCSI_Noise__3__DM2 CYREG_PRT6_DM2\r
-#define SCSI_Noise__3__DR CYREG_PRT6_DR\r
-#define SCSI_Noise__3__INP_DIS CYREG_PRT6_INP_DIS\r
-#define SCSI_Noise__3__INTTYPE CYREG_PICU6_INTTYPE6\r
-#define SCSI_Noise__3__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
-#define SCSI_Noise__3__LCD_EN CYREG_PRT6_LCD_EN\r
-#define SCSI_Noise__3__MASK 0x40u\r
-#define SCSI_Noise__3__PC CYREG_PRT6_PC6\r
-#define SCSI_Noise__3__PORT 6u\r
-#define SCSI_Noise__3__PRT CYREG_PRT6_PRT\r
-#define SCSI_Noise__3__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
-#define SCSI_Noise__3__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
-#define SCSI_Noise__3__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
-#define SCSI_Noise__3__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
-#define SCSI_Noise__3__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
-#define SCSI_Noise__3__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
-#define SCSI_Noise__3__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
-#define SCSI_Noise__3__PS CYREG_PRT6_PS\r
-#define SCSI_Noise__3__SHIFT 6u\r
-#define SCSI_Noise__3__SLW CYREG_PRT6_SLW\r
-#define SCSI_Noise__4__AG CYREG_PRT6_AG\r
-#define SCSI_Noise__4__AMUX CYREG_PRT6_AMUX\r
-#define SCSI_Noise__4__BIE CYREG_PRT6_BIE\r
-#define SCSI_Noise__4__BIT_MASK CYREG_PRT6_BIT_MASK\r
-#define SCSI_Noise__4__BYP CYREG_PRT6_BYP\r
-#define SCSI_Noise__4__CTL CYREG_PRT6_CTL\r
-#define SCSI_Noise__4__DM0 CYREG_PRT6_DM0\r
-#define SCSI_Noise__4__DM1 CYREG_PRT6_DM1\r
-#define SCSI_Noise__4__DM2 CYREG_PRT6_DM2\r
-#define SCSI_Noise__4__DR CYREG_PRT6_DR\r
-#define SCSI_Noise__4__INP_DIS CYREG_PRT6_INP_DIS\r
-#define SCSI_Noise__4__INTTYPE CYREG_PICU6_INTTYPE5\r
-#define SCSI_Noise__4__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
-#define SCSI_Noise__4__LCD_EN CYREG_PRT6_LCD_EN\r
-#define SCSI_Noise__4__MASK 0x20u\r
-#define SCSI_Noise__4__PC CYREG_PRT6_PC5\r
-#define SCSI_Noise__4__PORT 6u\r
-#define SCSI_Noise__4__PRT CYREG_PRT6_PRT\r
-#define SCSI_Noise__4__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
-#define SCSI_Noise__4__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
-#define SCSI_Noise__4__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
-#define SCSI_Noise__4__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
-#define SCSI_Noise__4__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
-#define SCSI_Noise__4__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
-#define SCSI_Noise__4__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
-#define SCSI_Noise__4__PS CYREG_PRT6_PS\r
-#define SCSI_Noise__4__SHIFT 5u\r
-#define SCSI_Noise__4__SLW CYREG_PRT6_SLW\r
-#define SCSI_Noise__ACK__AG CYREG_PRT6_AG\r
-#define SCSI_Noise__ACK__AMUX CYREG_PRT6_AMUX\r
-#define SCSI_Noise__ACK__BIE CYREG_PRT6_BIE\r
-#define SCSI_Noise__ACK__BIT_MASK CYREG_PRT6_BIT_MASK\r
-#define SCSI_Noise__ACK__BYP CYREG_PRT6_BYP\r
-#define SCSI_Noise__ACK__CTL CYREG_PRT6_CTL\r
-#define SCSI_Noise__ACK__DM0 CYREG_PRT6_DM0\r
-#define SCSI_Noise__ACK__DM1 CYREG_PRT6_DM1\r
-#define SCSI_Noise__ACK__DM2 CYREG_PRT6_DM2\r
-#define SCSI_Noise__ACK__DR CYREG_PRT6_DR\r
-#define SCSI_Noise__ACK__INP_DIS CYREG_PRT6_INP_DIS\r
-#define SCSI_Noise__ACK__INTTYPE CYREG_PICU6_INTTYPE5\r
-#define SCSI_Noise__ACK__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
-#define SCSI_Noise__ACK__LCD_EN CYREG_PRT6_LCD_EN\r
-#define SCSI_Noise__ACK__MASK 0x20u\r
-#define SCSI_Noise__ACK__PC CYREG_PRT6_PC5\r
-#define SCSI_Noise__ACK__PORT 6u\r
-#define SCSI_Noise__ACK__PRT CYREG_PRT6_PRT\r
-#define SCSI_Noise__ACK__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
-#define SCSI_Noise__ACK__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
-#define SCSI_Noise__ACK__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
-#define SCSI_Noise__ACK__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
-#define SCSI_Noise__ACK__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
-#define SCSI_Noise__ACK__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
-#define SCSI_Noise__ACK__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
-#define SCSI_Noise__ACK__PS CYREG_PRT6_PS\r
-#define SCSI_Noise__ACK__SHIFT 5u\r
-#define SCSI_Noise__ACK__SLW CYREG_PRT6_SLW\r
-#define SCSI_Noise__ATN__AG CYREG_PRT12_AG\r
-#define SCSI_Noise__ATN__BIE CYREG_PRT12_BIE\r
-#define SCSI_Noise__ATN__BIT_MASK CYREG_PRT12_BIT_MASK\r
-#define SCSI_Noise__ATN__BYP CYREG_PRT12_BYP\r
-#define SCSI_Noise__ATN__DM0 CYREG_PRT12_DM0\r
-#define SCSI_Noise__ATN__DM1 CYREG_PRT12_DM1\r
-#define SCSI_Noise__ATN__DM2 CYREG_PRT12_DM2\r
-#define SCSI_Noise__ATN__DR CYREG_PRT12_DR\r
-#define SCSI_Noise__ATN__INP_DIS CYREG_PRT12_INP_DIS\r
-#define SCSI_Noise__ATN__INTTYPE CYREG_PICU12_INTTYPE5\r
-#define SCSI_Noise__ATN__MASK 0x20u\r
-#define SCSI_Noise__ATN__PC CYREG_PRT12_PC5\r
-#define SCSI_Noise__ATN__PORT 12u\r
-#define SCSI_Noise__ATN__PRT CYREG_PRT12_PRT\r
-#define SCSI_Noise__ATN__PRTDSI__DBL_SYNC_IN CYREG_PRT12_DBL_SYNC_IN\r
-#define SCSI_Noise__ATN__PRTDSI__OE_SEL0 CYREG_PRT12_OE_SEL0\r
-#define SCSI_Noise__ATN__PRTDSI__OE_SEL1 CYREG_PRT12_OE_SEL1\r
-#define SCSI_Noise__ATN__PRTDSI__OUT_SEL0 CYREG_PRT12_OUT_SEL0\r
-#define SCSI_Noise__ATN__PRTDSI__OUT_SEL1 CYREG_PRT12_OUT_SEL1\r
-#define SCSI_Noise__ATN__PRTDSI__SYNC_OUT CYREG_PRT12_SYNC_OUT\r
-#define SCSI_Noise__ATN__PS CYREG_PRT12_PS\r
-#define SCSI_Noise__ATN__SHIFT 5u\r
-#define SCSI_Noise__ATN__SIO_CFG CYREG_PRT12_SIO_CFG\r
-#define SCSI_Noise__ATN__SIO_DIFF CYREG_PRT12_SIO_DIFF\r
-#define SCSI_Noise__ATN__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN\r
-#define SCSI_Noise__ATN__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ\r
-#define SCSI_Noise__ATN__SLW CYREG_PRT12_SLW\r
-#define SCSI_Noise__BSY__AG CYREG_PRT6_AG\r
-#define SCSI_Noise__BSY__AMUX CYREG_PRT6_AMUX\r
-#define SCSI_Noise__BSY__BIE CYREG_PRT6_BIE\r
-#define SCSI_Noise__BSY__BIT_MASK CYREG_PRT6_BIT_MASK\r
-#define SCSI_Noise__BSY__BYP CYREG_PRT6_BYP\r
-#define SCSI_Noise__BSY__CTL CYREG_PRT6_CTL\r
-#define SCSI_Noise__BSY__DM0 CYREG_PRT6_DM0\r
-#define SCSI_Noise__BSY__DM1 CYREG_PRT6_DM1\r
-#define SCSI_Noise__BSY__DM2 CYREG_PRT6_DM2\r
-#define SCSI_Noise__BSY__DR CYREG_PRT6_DR\r
-#define SCSI_Noise__BSY__INP_DIS CYREG_PRT6_INP_DIS\r
-#define SCSI_Noise__BSY__INTTYPE CYREG_PICU6_INTTYPE4\r
-#define SCSI_Noise__BSY__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
-#define SCSI_Noise__BSY__LCD_EN CYREG_PRT6_LCD_EN\r
-#define SCSI_Noise__BSY__MASK 0x10u\r
-#define SCSI_Noise__BSY__PC CYREG_PRT6_PC4\r
-#define SCSI_Noise__BSY__PORT 6u\r
-#define SCSI_Noise__BSY__PRT CYREG_PRT6_PRT\r
-#define SCSI_Noise__BSY__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
-#define SCSI_Noise__BSY__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
-#define SCSI_Noise__BSY__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
-#define SCSI_Noise__BSY__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
-#define SCSI_Noise__BSY__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
-#define SCSI_Noise__BSY__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
-#define SCSI_Noise__BSY__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
-#define SCSI_Noise__BSY__PS CYREG_PRT6_PS\r
-#define SCSI_Noise__BSY__SHIFT 4u\r
-#define SCSI_Noise__BSY__SLW CYREG_PRT6_SLW\r
-#define SCSI_Noise__RST__AG CYREG_PRT6_AG\r
-#define SCSI_Noise__RST__AMUX CYREG_PRT6_AMUX\r
-#define SCSI_Noise__RST__BIE CYREG_PRT6_BIE\r
-#define SCSI_Noise__RST__BIT_MASK CYREG_PRT6_BIT_MASK\r
-#define SCSI_Noise__RST__BYP CYREG_PRT6_BYP\r
-#define SCSI_Noise__RST__CTL CYREG_PRT6_CTL\r
-#define SCSI_Noise__RST__DM0 CYREG_PRT6_DM0\r
-#define SCSI_Noise__RST__DM1 CYREG_PRT6_DM1\r
-#define SCSI_Noise__RST__DM2 CYREG_PRT6_DM2\r
-#define SCSI_Noise__RST__DR CYREG_PRT6_DR\r
-#define SCSI_Noise__RST__INP_DIS CYREG_PRT6_INP_DIS\r
-#define SCSI_Noise__RST__INTTYPE CYREG_PICU6_INTTYPE6\r
-#define SCSI_Noise__RST__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
-#define SCSI_Noise__RST__LCD_EN CYREG_PRT6_LCD_EN\r
-#define SCSI_Noise__RST__MASK 0x40u\r
-#define SCSI_Noise__RST__PC CYREG_PRT6_PC6\r
-#define SCSI_Noise__RST__PORT 6u\r
-#define SCSI_Noise__RST__PRT CYREG_PRT6_PRT\r
-#define SCSI_Noise__RST__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
-#define SCSI_Noise__RST__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
-#define SCSI_Noise__RST__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
-#define SCSI_Noise__RST__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
-#define SCSI_Noise__RST__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
-#define SCSI_Noise__RST__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
-#define SCSI_Noise__RST__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
-#define SCSI_Noise__RST__PS CYREG_PRT6_PS\r
-#define SCSI_Noise__RST__SHIFT 6u\r
-#define SCSI_Noise__RST__SLW CYREG_PRT6_SLW\r
-#define SCSI_Noise__SEL__AG CYREG_PRT5_AG\r
-#define SCSI_Noise__SEL__AMUX CYREG_PRT5_AMUX\r
-#define SCSI_Noise__SEL__BIE CYREG_PRT5_BIE\r
-#define SCSI_Noise__SEL__BIT_MASK CYREG_PRT5_BIT_MASK\r
-#define SCSI_Noise__SEL__BYP CYREG_PRT5_BYP\r
-#define SCSI_Noise__SEL__CTL CYREG_PRT5_CTL\r
-#define SCSI_Noise__SEL__DM0 CYREG_PRT5_DM0\r
-#define SCSI_Noise__SEL__DM1 CYREG_PRT5_DM1\r
-#define SCSI_Noise__SEL__DM2 CYREG_PRT5_DM2\r
-#define SCSI_Noise__SEL__DR CYREG_PRT5_DR\r
-#define SCSI_Noise__SEL__INP_DIS CYREG_PRT5_INP_DIS\r
-#define SCSI_Noise__SEL__INTTYPE CYREG_PICU5_INTTYPE0\r
-#define SCSI_Noise__SEL__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG\r
-#define SCSI_Noise__SEL__LCD_EN CYREG_PRT5_LCD_EN\r
-#define SCSI_Noise__SEL__MASK 0x01u\r
-#define SCSI_Noise__SEL__PC CYREG_PRT5_PC0\r
-#define SCSI_Noise__SEL__PORT 5u\r
-#define SCSI_Noise__SEL__PRT CYREG_PRT5_PRT\r
-#define SCSI_Noise__SEL__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL\r
-#define SCSI_Noise__SEL__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN\r
-#define SCSI_Noise__SEL__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0\r
-#define SCSI_Noise__SEL__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1\r
-#define SCSI_Noise__SEL__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0\r
-#define SCSI_Noise__SEL__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1\r
-#define SCSI_Noise__SEL__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT\r
-#define SCSI_Noise__SEL__PS CYREG_PRT5_PS\r
-#define SCSI_Noise__SEL__SHIFT 0u\r
-#define SCSI_Noise__SEL__SLW CYREG_PRT5_SLW\r
-\r
-/* SCSI_Out */\r
-#define SCSI_Out__0__AG CYREG_PRT4_AG\r
-#define SCSI_Out__0__AMUX CYREG_PRT4_AMUX\r
-#define SCSI_Out__0__BIE CYREG_PRT4_BIE\r
-#define SCSI_Out__0__BIT_MASK CYREG_PRT4_BIT_MASK\r
-#define SCSI_Out__0__BYP CYREG_PRT4_BYP\r
-#define SCSI_Out__0__CTL CYREG_PRT4_CTL\r
-#define SCSI_Out__0__DM0 CYREG_PRT4_DM0\r
-#define SCSI_Out__0__DM1 CYREG_PRT4_DM1\r
-#define SCSI_Out__0__DM2 CYREG_PRT4_DM2\r
-#define SCSI_Out__0__DR CYREG_PRT4_DR\r
-#define SCSI_Out__0__INP_DIS CYREG_PRT4_INP_DIS\r
-#define SCSI_Out__0__INTTYPE CYREG_PICU4_INTTYPE3\r
-#define SCSI_Out__0__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG\r
-#define SCSI_Out__0__LCD_EN CYREG_PRT4_LCD_EN\r
-#define SCSI_Out__0__MASK 0x08u\r
-#define SCSI_Out__0__PC CYREG_PRT4_PC3\r
-#define SCSI_Out__0__PORT 4u\r
-#define SCSI_Out__0__PRT CYREG_PRT4_PRT\r
-#define SCSI_Out__0__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL\r
-#define SCSI_Out__0__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN\r
-#define SCSI_Out__0__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0\r
-#define SCSI_Out__0__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1\r
-#define SCSI_Out__0__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0\r
-#define SCSI_Out__0__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1\r
-#define SCSI_Out__0__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT\r
-#define SCSI_Out__0__PS CYREG_PRT4_PS\r
-#define SCSI_Out__0__SHIFT 3u\r
-#define SCSI_Out__0__SLW CYREG_PRT4_SLW\r
-#define SCSI_Out__1__AG CYREG_PRT4_AG\r
-#define SCSI_Out__1__AMUX CYREG_PRT4_AMUX\r
-#define SCSI_Out__1__BIE CYREG_PRT4_BIE\r
-#define SCSI_Out__1__BIT_MASK CYREG_PRT4_BIT_MASK\r
-#define SCSI_Out__1__BYP CYREG_PRT4_BYP\r
-#define SCSI_Out__1__CTL CYREG_PRT4_CTL\r
-#define SCSI_Out__1__DM0 CYREG_PRT4_DM0\r
-#define SCSI_Out__1__DM1 CYREG_PRT4_DM1\r
-#define SCSI_Out__1__DM2 CYREG_PRT4_DM2\r
-#define SCSI_Out__1__DR CYREG_PRT4_DR\r
-#define SCSI_Out__1__INP_DIS CYREG_PRT4_INP_DIS\r
-#define SCSI_Out__1__INTTYPE CYREG_PICU4_INTTYPE2\r
-#define SCSI_Out__1__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG\r
-#define SCSI_Out__1__LCD_EN CYREG_PRT4_LCD_EN\r
-#define SCSI_Out__1__MASK 0x04u\r
-#define SCSI_Out__1__PC CYREG_PRT4_PC2\r
-#define SCSI_Out__1__PORT 4u\r
-#define SCSI_Out__1__PRT CYREG_PRT4_PRT\r
-#define SCSI_Out__1__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL\r
-#define SCSI_Out__1__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN\r
-#define SCSI_Out__1__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0\r
-#define SCSI_Out__1__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1\r
-#define SCSI_Out__1__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0\r
-#define SCSI_Out__1__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1\r
-#define SCSI_Out__1__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT\r
-#define SCSI_Out__1__PS CYREG_PRT4_PS\r
-#define SCSI_Out__1__SHIFT 2u\r
-#define SCSI_Out__1__SLW CYREG_PRT4_SLW\r
-#define SCSI_Out__2__AG CYREG_PRT0_AG\r
-#define SCSI_Out__2__AMUX CYREG_PRT0_AMUX\r
-#define SCSI_Out__2__BIE CYREG_PRT0_BIE\r
-#define SCSI_Out__2__BIT_MASK CYREG_PRT0_BIT_MASK\r
-#define SCSI_Out__2__BYP CYREG_PRT0_BYP\r
-#define SCSI_Out__2__CTL CYREG_PRT0_CTL\r
-#define SCSI_Out__2__DM0 CYREG_PRT0_DM0\r
-#define SCSI_Out__2__DM1 CYREG_PRT0_DM1\r
-#define SCSI_Out__2__DM2 CYREG_PRT0_DM2\r
-#define SCSI_Out__2__DR CYREG_PRT0_DR\r
-#define SCSI_Out__2__INP_DIS CYREG_PRT0_INP_DIS\r
-#define SCSI_Out__2__INTTYPE CYREG_PICU0_INTTYPE7\r
-#define SCSI_Out__2__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG\r
-#define SCSI_Out__2__LCD_EN CYREG_PRT0_LCD_EN\r
-#define SCSI_Out__2__MASK 0x80u\r
-#define SCSI_Out__2__PC CYREG_PRT0_PC7\r
-#define SCSI_Out__2__PORT 0u\r
-#define SCSI_Out__2__PRT CYREG_PRT0_PRT\r
-#define SCSI_Out__2__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL\r
-#define SCSI_Out__2__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN\r
-#define SCSI_Out__2__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0\r
-#define SCSI_Out__2__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1\r
-#define SCSI_Out__2__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0\r
-#define SCSI_Out__2__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1\r
-#define SCSI_Out__2__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT\r
-#define SCSI_Out__2__PS CYREG_PRT0_PS\r
-#define SCSI_Out__2__SHIFT 7u\r
-#define SCSI_Out__2__SLW CYREG_PRT0_SLW\r
-#define SCSI_Out__3__AG CYREG_PRT0_AG\r
-#define SCSI_Out__3__AMUX CYREG_PRT0_AMUX\r
-#define SCSI_Out__3__BIE CYREG_PRT0_BIE\r
-#define SCSI_Out__3__BIT_MASK CYREG_PRT0_BIT_MASK\r
-#define SCSI_Out__3__BYP CYREG_PRT0_BYP\r
-#define SCSI_Out__3__CTL CYREG_PRT0_CTL\r
-#define SCSI_Out__3__DM0 CYREG_PRT0_DM0\r
-#define SCSI_Out__3__DM1 CYREG_PRT0_DM1\r
-#define SCSI_Out__3__DM2 CYREG_PRT0_DM2\r
-#define SCSI_Out__3__DR CYREG_PRT0_DR\r
-#define SCSI_Out__3__INP_DIS CYREG_PRT0_INP_DIS\r
-#define SCSI_Out__3__INTTYPE CYREG_PICU0_INTTYPE6\r
-#define SCSI_Out__3__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG\r
-#define SCSI_Out__3__LCD_EN CYREG_PRT0_LCD_EN\r
-#define SCSI_Out__3__MASK 0x40u\r
-#define SCSI_Out__3__PC CYREG_PRT0_PC6\r
-#define SCSI_Out__3__PORT 0u\r
-#define SCSI_Out__3__PRT CYREG_PRT0_PRT\r
-#define SCSI_Out__3__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL\r
-#define SCSI_Out__3__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN\r
-#define SCSI_Out__3__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0\r
-#define SCSI_Out__3__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1\r
-#define SCSI_Out__3__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0\r
-#define SCSI_Out__3__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1\r
-#define SCSI_Out__3__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT\r
-#define SCSI_Out__3__PS CYREG_PRT0_PS\r
-#define SCSI_Out__3__SHIFT 6u\r
-#define SCSI_Out__3__SLW CYREG_PRT0_SLW\r
-#define SCSI_Out__4__AG CYREG_PRT0_AG\r
-#define SCSI_Out__4__AMUX CYREG_PRT0_AMUX\r
-#define SCSI_Out__4__BIE CYREG_PRT0_BIE\r
-#define SCSI_Out__4__BIT_MASK CYREG_PRT0_BIT_MASK\r
-#define SCSI_Out__4__BYP CYREG_PRT0_BYP\r
-#define SCSI_Out__4__CTL CYREG_PRT0_CTL\r
-#define SCSI_Out__4__DM0 CYREG_PRT0_DM0\r
-#define SCSI_Out__4__DM1 CYREG_PRT0_DM1\r
-#define SCSI_Out__4__DM2 CYREG_PRT0_DM2\r
-#define SCSI_Out__4__DR CYREG_PRT0_DR\r
-#define SCSI_Out__4__INP_DIS CYREG_PRT0_INP_DIS\r
-#define SCSI_Out__4__INTTYPE CYREG_PICU0_INTTYPE5\r
-#define SCSI_Out__4__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG\r
-#define SCSI_Out__4__LCD_EN CYREG_PRT0_LCD_EN\r
-#define SCSI_Out__4__MASK 0x20u\r
-#define SCSI_Out__4__PC CYREG_PRT0_PC5\r
-#define SCSI_Out__4__PORT 0u\r
-#define SCSI_Out__4__PRT CYREG_PRT0_PRT\r
-#define SCSI_Out__4__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL\r
-#define SCSI_Out__4__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN\r
-#define SCSI_Out__4__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0\r
-#define SCSI_Out__4__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1\r
-#define SCSI_Out__4__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0\r
-#define SCSI_Out__4__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1\r
-#define SCSI_Out__4__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT\r
-#define SCSI_Out__4__PS CYREG_PRT0_PS\r
-#define SCSI_Out__4__SHIFT 5u\r
-#define SCSI_Out__4__SLW CYREG_PRT0_SLW\r
-#define SCSI_Out__5__AG CYREG_PRT0_AG\r
-#define SCSI_Out__5__AMUX CYREG_PRT0_AMUX\r
-#define SCSI_Out__5__BIE CYREG_PRT0_BIE\r
-#define SCSI_Out__5__BIT_MASK CYREG_PRT0_BIT_MASK\r
-#define SCSI_Out__5__BYP CYREG_PRT0_BYP\r
-#define SCSI_Out__5__CTL CYREG_PRT0_CTL\r
-#define SCSI_Out__5__DM0 CYREG_PRT0_DM0\r
-#define SCSI_Out__5__DM1 CYREG_PRT0_DM1\r
-#define SCSI_Out__5__DM2 CYREG_PRT0_DM2\r
-#define SCSI_Out__5__DR CYREG_PRT0_DR\r
-#define SCSI_Out__5__INP_DIS CYREG_PRT0_INP_DIS\r
-#define SCSI_Out__5__INTTYPE CYREG_PICU0_INTTYPE4\r
-#define SCSI_Out__5__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG\r
-#define SCSI_Out__5__LCD_EN CYREG_PRT0_LCD_EN\r
-#define SCSI_Out__5__MASK 0x10u\r
-#define SCSI_Out__5__PC CYREG_PRT0_PC4\r
-#define SCSI_Out__5__PORT 0u\r
-#define SCSI_Out__5__PRT CYREG_PRT0_PRT\r
-#define SCSI_Out__5__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL\r
-#define SCSI_Out__5__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN\r
-#define SCSI_Out__5__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0\r
-#define SCSI_Out__5__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1\r
-#define SCSI_Out__5__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0\r
-#define SCSI_Out__5__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1\r
-#define SCSI_Out__5__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT\r
-#define SCSI_Out__5__PS CYREG_PRT0_PS\r
-#define SCSI_Out__5__SHIFT 4u\r
-#define SCSI_Out__5__SLW CYREG_PRT0_SLW\r
-#define SCSI_Out__6__AG CYREG_PRT0_AG\r
-#define SCSI_Out__6__AMUX CYREG_PRT0_AMUX\r
-#define SCSI_Out__6__BIE CYREG_PRT0_BIE\r
-#define SCSI_Out__6__BIT_MASK CYREG_PRT0_BIT_MASK\r
-#define SCSI_Out__6__BYP CYREG_PRT0_BYP\r
-#define SCSI_Out__6__CTL CYREG_PRT0_CTL\r
-#define SCSI_Out__6__DM0 CYREG_PRT0_DM0\r
-#define SCSI_Out__6__DM1 CYREG_PRT0_DM1\r
-#define SCSI_Out__6__DM2 CYREG_PRT0_DM2\r
-#define SCSI_Out__6__DR CYREG_PRT0_DR\r
-#define SCSI_Out__6__INP_DIS CYREG_PRT0_INP_DIS\r
-#define SCSI_Out__6__INTTYPE CYREG_PICU0_INTTYPE3\r
-#define SCSI_Out__6__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG\r
-#define SCSI_Out__6__LCD_EN CYREG_PRT0_LCD_EN\r
-#define SCSI_Out__6__MASK 0x08u\r
-#define SCSI_Out__6__PC CYREG_PRT0_PC3\r
-#define SCSI_Out__6__PORT 0u\r
-#define SCSI_Out__6__PRT CYREG_PRT0_PRT\r
-#define SCSI_Out__6__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL\r
-#define SCSI_Out__6__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN\r
-#define SCSI_Out__6__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0\r
-#define SCSI_Out__6__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1\r
-#define SCSI_Out__6__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0\r
-#define SCSI_Out__6__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1\r
-#define SCSI_Out__6__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT\r
-#define SCSI_Out__6__PS CYREG_PRT0_PS\r
-#define SCSI_Out__6__SHIFT 3u\r
-#define SCSI_Out__6__SLW CYREG_PRT0_SLW\r
-#define SCSI_Out__7__AG CYREG_PRT0_AG\r
-#define SCSI_Out__7__AMUX CYREG_PRT0_AMUX\r
-#define SCSI_Out__7__BIE CYREG_PRT0_BIE\r
-#define SCSI_Out__7__BIT_MASK CYREG_PRT0_BIT_MASK\r
-#define SCSI_Out__7__BYP CYREG_PRT0_BYP\r
-#define SCSI_Out__7__CTL CYREG_PRT0_CTL\r
-#define SCSI_Out__7__DM0 CYREG_PRT0_DM0\r
-#define SCSI_Out__7__DM1 CYREG_PRT0_DM1\r
-#define SCSI_Out__7__DM2 CYREG_PRT0_DM2\r
-#define SCSI_Out__7__DR CYREG_PRT0_DR\r
-#define SCSI_Out__7__INP_DIS CYREG_PRT0_INP_DIS\r
-#define SCSI_Out__7__INTTYPE CYREG_PICU0_INTTYPE2\r
-#define SCSI_Out__7__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG\r
-#define SCSI_Out__7__LCD_EN CYREG_PRT0_LCD_EN\r
-#define SCSI_Out__7__MASK 0x04u\r
-#define SCSI_Out__7__PC CYREG_PRT0_PC2\r
-#define SCSI_Out__7__PORT 0u\r
-#define SCSI_Out__7__PRT CYREG_PRT0_PRT\r
-#define SCSI_Out__7__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL\r
-#define SCSI_Out__7__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN\r
-#define SCSI_Out__7__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0\r
-#define SCSI_Out__7__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1\r
-#define SCSI_Out__7__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0\r
-#define SCSI_Out__7__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1\r
-#define SCSI_Out__7__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT\r
-#define SCSI_Out__7__PS CYREG_PRT0_PS\r
-#define SCSI_Out__7__SHIFT 2u\r
-#define SCSI_Out__7__SLW CYREG_PRT0_SLW\r
-#define SCSI_Out__8__AG CYREG_PRT0_AG\r
-#define SCSI_Out__8__AMUX CYREG_PRT0_AMUX\r
-#define SCSI_Out__8__BIE CYREG_PRT0_BIE\r
-#define SCSI_Out__8__BIT_MASK CYREG_PRT0_BIT_MASK\r
-#define SCSI_Out__8__BYP CYREG_PRT0_BYP\r
-#define SCSI_Out__8__CTL CYREG_PRT0_CTL\r
-#define SCSI_Out__8__DM0 CYREG_PRT0_DM0\r
-#define SCSI_Out__8__DM1 CYREG_PRT0_DM1\r
-#define SCSI_Out__8__DM2 CYREG_PRT0_DM2\r
-#define SCSI_Out__8__DR CYREG_PRT0_DR\r
-#define SCSI_Out__8__INP_DIS CYREG_PRT0_INP_DIS\r
-#define SCSI_Out__8__INTTYPE CYREG_PICU0_INTTYPE1\r
-#define SCSI_Out__8__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG\r
-#define SCSI_Out__8__LCD_EN CYREG_PRT0_LCD_EN\r
-#define SCSI_Out__8__MASK 0x02u\r
-#define SCSI_Out__8__PC CYREG_PRT0_PC1\r
-#define SCSI_Out__8__PORT 0u\r
-#define SCSI_Out__8__PRT CYREG_PRT0_PRT\r
-#define SCSI_Out__8__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL\r
-#define SCSI_Out__8__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN\r
-#define SCSI_Out__8__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0\r
-#define SCSI_Out__8__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1\r
-#define SCSI_Out__8__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0\r
-#define SCSI_Out__8__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1\r
-#define SCSI_Out__8__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT\r
-#define SCSI_Out__8__PS CYREG_PRT0_PS\r
-#define SCSI_Out__8__SHIFT 1u\r
-#define SCSI_Out__8__SLW CYREG_PRT0_SLW\r
-#define SCSI_Out__9__AG CYREG_PRT0_AG\r
-#define SCSI_Out__9__AMUX CYREG_PRT0_AMUX\r
-#define SCSI_Out__9__BIE CYREG_PRT0_BIE\r
-#define SCSI_Out__9__BIT_MASK CYREG_PRT0_BIT_MASK\r
-#define SCSI_Out__9__BYP CYREG_PRT0_BYP\r
-#define SCSI_Out__9__CTL CYREG_PRT0_CTL\r
-#define SCSI_Out__9__DM0 CYREG_PRT0_DM0\r
-#define SCSI_Out__9__DM1 CYREG_PRT0_DM1\r
-#define SCSI_Out__9__DM2 CYREG_PRT0_DM2\r
-#define SCSI_Out__9__DR CYREG_PRT0_DR\r
-#define SCSI_Out__9__INP_DIS CYREG_PRT0_INP_DIS\r
-#define SCSI_Out__9__INTTYPE CYREG_PICU0_INTTYPE0\r
-#define SCSI_Out__9__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG\r
-#define SCSI_Out__9__LCD_EN CYREG_PRT0_LCD_EN\r
-#define SCSI_Out__9__MASK 0x01u\r
-#define SCSI_Out__9__PC CYREG_PRT0_PC0\r
-#define SCSI_Out__9__PORT 0u\r
-#define SCSI_Out__9__PRT CYREG_PRT0_PRT\r
-#define SCSI_Out__9__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL\r
-#define SCSI_Out__9__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN\r
-#define SCSI_Out__9__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0\r
-#define SCSI_Out__9__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1\r
-#define SCSI_Out__9__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0\r
-#define SCSI_Out__9__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1\r
-#define SCSI_Out__9__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT\r
-#define SCSI_Out__9__PS CYREG_PRT0_PS\r
-#define SCSI_Out__9__SHIFT 0u\r
-#define SCSI_Out__9__SLW CYREG_PRT0_SLW\r
-#define SCSI_Out__ACK__AG CYREG_PRT0_AG\r
-#define SCSI_Out__ACK__AMUX CYREG_PRT0_AMUX\r
-#define SCSI_Out__ACK__BIE CYREG_PRT0_BIE\r
-#define SCSI_Out__ACK__BIT_MASK CYREG_PRT0_BIT_MASK\r
-#define SCSI_Out__ACK__BYP CYREG_PRT0_BYP\r
-#define SCSI_Out__ACK__CTL CYREG_PRT0_CTL\r
-#define SCSI_Out__ACK__DM0 CYREG_PRT0_DM0\r
-#define SCSI_Out__ACK__DM1 CYREG_PRT0_DM1\r
-#define SCSI_Out__ACK__DM2 CYREG_PRT0_DM2\r
-#define SCSI_Out__ACK__DR CYREG_PRT0_DR\r
-#define SCSI_Out__ACK__INP_DIS CYREG_PRT0_INP_DIS\r
-#define SCSI_Out__ACK__INTTYPE CYREG_PICU0_INTTYPE6\r
-#define SCSI_Out__ACK__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG\r
-#define SCSI_Out__ACK__LCD_EN CYREG_PRT0_LCD_EN\r
-#define SCSI_Out__ACK__MASK 0x40u\r
-#define SCSI_Out__ACK__PC CYREG_PRT0_PC6\r
-#define SCSI_Out__ACK__PORT 0u\r
-#define SCSI_Out__ACK__PRT CYREG_PRT0_PRT\r
-#define SCSI_Out__ACK__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL\r
-#define SCSI_Out__ACK__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN\r
-#define SCSI_Out__ACK__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0\r
-#define SCSI_Out__ACK__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1\r
-#define SCSI_Out__ACK__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0\r
-#define SCSI_Out__ACK__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1\r
-#define SCSI_Out__ACK__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT\r
-#define SCSI_Out__ACK__PS CYREG_PRT0_PS\r
-#define SCSI_Out__ACK__SHIFT 6u\r
-#define SCSI_Out__ACK__SLW CYREG_PRT0_SLW\r
-#define SCSI_Out__ATN__AG CYREG_PRT4_AG\r
-#define SCSI_Out__ATN__AMUX CYREG_PRT4_AMUX\r
-#define SCSI_Out__ATN__BIE CYREG_PRT4_BIE\r
-#define SCSI_Out__ATN__BIT_MASK CYREG_PRT4_BIT_MASK\r
-#define SCSI_Out__ATN__BYP CYREG_PRT4_BYP\r
-#define SCSI_Out__ATN__CTL CYREG_PRT4_CTL\r
-#define SCSI_Out__ATN__DM0 CYREG_PRT4_DM0\r
-#define SCSI_Out__ATN__DM1 CYREG_PRT4_DM1\r
-#define SCSI_Out__ATN__DM2 CYREG_PRT4_DM2\r
-#define SCSI_Out__ATN__DR CYREG_PRT4_DR\r
-#define SCSI_Out__ATN__INP_DIS CYREG_PRT4_INP_DIS\r
-#define SCSI_Out__ATN__INTTYPE CYREG_PICU4_INTTYPE2\r
-#define SCSI_Out__ATN__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG\r
-#define SCSI_Out__ATN__LCD_EN CYREG_PRT4_LCD_EN\r
-#define SCSI_Out__ATN__MASK 0x04u\r
-#define SCSI_Out__ATN__PC CYREG_PRT4_PC2\r
-#define SCSI_Out__ATN__PORT 4u\r
-#define SCSI_Out__ATN__PRT CYREG_PRT4_PRT\r
-#define SCSI_Out__ATN__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL\r
-#define SCSI_Out__ATN__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN\r
-#define SCSI_Out__ATN__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0\r
-#define SCSI_Out__ATN__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1\r
-#define SCSI_Out__ATN__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0\r
-#define SCSI_Out__ATN__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1\r
-#define SCSI_Out__ATN__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT\r
-#define SCSI_Out__ATN__PS CYREG_PRT4_PS\r
-#define SCSI_Out__ATN__SHIFT 2u\r
-#define SCSI_Out__ATN__SLW CYREG_PRT4_SLW\r
-#define SCSI_Out__BSY__AG CYREG_PRT0_AG\r
-#define SCSI_Out__BSY__AMUX CYREG_PRT0_AMUX\r
-#define SCSI_Out__BSY__BIE CYREG_PRT0_BIE\r
-#define SCSI_Out__BSY__BIT_MASK CYREG_PRT0_BIT_MASK\r
-#define SCSI_Out__BSY__BYP CYREG_PRT0_BYP\r
-#define SCSI_Out__BSY__CTL CYREG_PRT0_CTL\r
-#define SCSI_Out__BSY__DM0 CYREG_PRT0_DM0\r
-#define SCSI_Out__BSY__DM1 CYREG_PRT0_DM1\r
-#define SCSI_Out__BSY__DM2 CYREG_PRT0_DM2\r
-#define SCSI_Out__BSY__DR CYREG_PRT0_DR\r
-#define SCSI_Out__BSY__INP_DIS CYREG_PRT0_INP_DIS\r
-#define SCSI_Out__BSY__INTTYPE CYREG_PICU0_INTTYPE7\r
-#define SCSI_Out__BSY__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG\r
-#define SCSI_Out__BSY__LCD_EN CYREG_PRT0_LCD_EN\r
-#define SCSI_Out__BSY__MASK 0x80u\r
-#define SCSI_Out__BSY__PC CYREG_PRT0_PC7\r
-#define SCSI_Out__BSY__PORT 0u\r
-#define SCSI_Out__BSY__PRT CYREG_PRT0_PRT\r
-#define SCSI_Out__BSY__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL\r
-#define SCSI_Out__BSY__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN\r
-#define SCSI_Out__BSY__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0\r
-#define SCSI_Out__BSY__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1\r
-#define SCSI_Out__BSY__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0\r
-#define SCSI_Out__BSY__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1\r
-#define SCSI_Out__BSY__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT\r
-#define SCSI_Out__BSY__PS CYREG_PRT0_PS\r
-#define SCSI_Out__BSY__SHIFT 7u\r
-#define SCSI_Out__BSY__SLW CYREG_PRT0_SLW\r
-#define SCSI_Out__CD_raw__AG CYREG_PRT0_AG\r
-#define SCSI_Out__CD_raw__AMUX CYREG_PRT0_AMUX\r
-#define SCSI_Out__CD_raw__BIE CYREG_PRT0_BIE\r
-#define SCSI_Out__CD_raw__BIT_MASK CYREG_PRT0_BIT_MASK\r
-#define SCSI_Out__CD_raw__BYP CYREG_PRT0_BYP\r
-#define SCSI_Out__CD_raw__CTL CYREG_PRT0_CTL\r
-#define SCSI_Out__CD_raw__DM0 CYREG_PRT0_DM0\r
-#define SCSI_Out__CD_raw__DM1 CYREG_PRT0_DM1\r
-#define SCSI_Out__CD_raw__DM2 CYREG_PRT0_DM2\r
-#define SCSI_Out__CD_raw__DR CYREG_PRT0_DR\r
-#define SCSI_Out__CD_raw__INP_DIS CYREG_PRT0_INP_DIS\r
-#define SCSI_Out__CD_raw__INTTYPE CYREG_PICU0_INTTYPE2\r
-#define SCSI_Out__CD_raw__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG\r
-#define SCSI_Out__CD_raw__LCD_EN CYREG_PRT0_LCD_EN\r
-#define SCSI_Out__CD_raw__MASK 0x04u\r
-#define SCSI_Out__CD_raw__PC CYREG_PRT0_PC2\r
-#define SCSI_Out__CD_raw__PORT 0u\r
-#define SCSI_Out__CD_raw__PRT CYREG_PRT0_PRT\r
-#define SCSI_Out__CD_raw__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL\r
-#define SCSI_Out__CD_raw__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN\r
-#define SCSI_Out__CD_raw__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0\r
-#define SCSI_Out__CD_raw__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1\r
-#define SCSI_Out__CD_raw__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0\r
-#define SCSI_Out__CD_raw__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1\r
-#define SCSI_Out__CD_raw__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT\r
-#define SCSI_Out__CD_raw__PS CYREG_PRT0_PS\r
-#define SCSI_Out__CD_raw__SHIFT 2u\r
-#define SCSI_Out__CD_raw__SLW CYREG_PRT0_SLW\r
-#define SCSI_Out__DBP_raw__AG CYREG_PRT4_AG\r
-#define SCSI_Out__DBP_raw__AMUX CYREG_PRT4_AMUX\r
-#define SCSI_Out__DBP_raw__BIE CYREG_PRT4_BIE\r
-#define SCSI_Out__DBP_raw__BIT_MASK CYREG_PRT4_BIT_MASK\r
-#define SCSI_Out__DBP_raw__BYP CYREG_PRT4_BYP\r
-#define SCSI_Out__DBP_raw__CTL CYREG_PRT4_CTL\r
-#define SCSI_Out__DBP_raw__DM0 CYREG_PRT4_DM0\r
-#define SCSI_Out__DBP_raw__DM1 CYREG_PRT4_DM1\r
-#define SCSI_Out__DBP_raw__DM2 CYREG_PRT4_DM2\r
-#define SCSI_Out__DBP_raw__DR CYREG_PRT4_DR\r
-#define SCSI_Out__DBP_raw__INP_DIS CYREG_PRT4_INP_DIS\r
-#define SCSI_Out__DBP_raw__INTTYPE CYREG_PICU4_INTTYPE3\r
-#define SCSI_Out__DBP_raw__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG\r
-#define SCSI_Out__DBP_raw__LCD_EN CYREG_PRT4_LCD_EN\r
-#define SCSI_Out__DBP_raw__MASK 0x08u\r
-#define SCSI_Out__DBP_raw__PC CYREG_PRT4_PC3\r
-#define SCSI_Out__DBP_raw__PORT 4u\r
-#define SCSI_Out__DBP_raw__PRT CYREG_PRT4_PRT\r
-#define SCSI_Out__DBP_raw__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL\r
-#define SCSI_Out__DBP_raw__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN\r
-#define SCSI_Out__DBP_raw__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0\r
-#define SCSI_Out__DBP_raw__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1\r
-#define SCSI_Out__DBP_raw__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0\r
-#define SCSI_Out__DBP_raw__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1\r
-#define SCSI_Out__DBP_raw__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT\r
-#define SCSI_Out__DBP_raw__PS CYREG_PRT4_PS\r
-#define SCSI_Out__DBP_raw__SHIFT 3u\r
-#define SCSI_Out__DBP_raw__SLW CYREG_PRT4_SLW\r
-#define SCSI_Out__IO_raw__AG CYREG_PRT0_AG\r
-#define SCSI_Out__IO_raw__AMUX CYREG_PRT0_AMUX\r
-#define SCSI_Out__IO_raw__BIE CYREG_PRT0_BIE\r
-#define SCSI_Out__IO_raw__BIT_MASK CYREG_PRT0_BIT_MASK\r
-#define SCSI_Out__IO_raw__BYP CYREG_PRT0_BYP\r
-#define SCSI_Out__IO_raw__CTL CYREG_PRT0_CTL\r
-#define SCSI_Out__IO_raw__DM0 CYREG_PRT0_DM0\r
-#define SCSI_Out__IO_raw__DM1 CYREG_PRT0_DM1\r
-#define SCSI_Out__IO_raw__DM2 CYREG_PRT0_DM2\r
-#define SCSI_Out__IO_raw__DR CYREG_PRT0_DR\r
-#define SCSI_Out__IO_raw__INP_DIS CYREG_PRT0_INP_DIS\r
-#define SCSI_Out__IO_raw__INTTYPE CYREG_PICU0_INTTYPE0\r
-#define SCSI_Out__IO_raw__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG\r
-#define SCSI_Out__IO_raw__LCD_EN CYREG_PRT0_LCD_EN\r
-#define SCSI_Out__IO_raw__MASK 0x01u\r
-#define SCSI_Out__IO_raw__PC CYREG_PRT0_PC0\r
-#define SCSI_Out__IO_raw__PORT 0u\r
-#define SCSI_Out__IO_raw__PRT CYREG_PRT0_PRT\r
-#define SCSI_Out__IO_raw__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL\r
-#define SCSI_Out__IO_raw__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN\r
-#define SCSI_Out__IO_raw__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0\r
-#define SCSI_Out__IO_raw__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1\r
-#define SCSI_Out__IO_raw__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0\r
-#define SCSI_Out__IO_raw__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1\r
-#define SCSI_Out__IO_raw__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT\r
-#define SCSI_Out__IO_raw__PS CYREG_PRT0_PS\r
-#define SCSI_Out__IO_raw__SHIFT 0u\r
-#define SCSI_Out__IO_raw__SLW CYREG_PRT0_SLW\r
-#define SCSI_Out__MSG_raw__AG CYREG_PRT0_AG\r
-#define SCSI_Out__MSG_raw__AMUX CYREG_PRT0_AMUX\r
-#define SCSI_Out__MSG_raw__BIE CYREG_PRT0_BIE\r
-#define SCSI_Out__MSG_raw__BIT_MASK CYREG_PRT0_BIT_MASK\r
-#define SCSI_Out__MSG_raw__BYP CYREG_PRT0_BYP\r
-#define SCSI_Out__MSG_raw__CTL CYREG_PRT0_CTL\r
-#define SCSI_Out__MSG_raw__DM0 CYREG_PRT0_DM0\r
-#define SCSI_Out__MSG_raw__DM1 CYREG_PRT0_DM1\r
-#define SCSI_Out__MSG_raw__DM2 CYREG_PRT0_DM2\r
-#define SCSI_Out__MSG_raw__DR CYREG_PRT0_DR\r
-#define SCSI_Out__MSG_raw__INP_DIS CYREG_PRT0_INP_DIS\r
-#define SCSI_Out__MSG_raw__INTTYPE CYREG_PICU0_INTTYPE4\r
-#define SCSI_Out__MSG_raw__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG\r
-#define SCSI_Out__MSG_raw__LCD_EN CYREG_PRT0_LCD_EN\r
-#define SCSI_Out__MSG_raw__MASK 0x10u\r
-#define SCSI_Out__MSG_raw__PC CYREG_PRT0_PC4\r
-#define SCSI_Out__MSG_raw__PORT 0u\r
-#define SCSI_Out__MSG_raw__PRT CYREG_PRT0_PRT\r
-#define SCSI_Out__MSG_raw__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL\r
-#define SCSI_Out__MSG_raw__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN\r
-#define SCSI_Out__MSG_raw__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0\r
-#define SCSI_Out__MSG_raw__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1\r
-#define SCSI_Out__MSG_raw__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0\r
-#define SCSI_Out__MSG_raw__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1\r
-#define SCSI_Out__MSG_raw__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT\r
-#define SCSI_Out__MSG_raw__PS CYREG_PRT0_PS\r
-#define SCSI_Out__MSG_raw__SHIFT 4u\r
-#define SCSI_Out__MSG_raw__SLW CYREG_PRT0_SLW\r
-#define SCSI_Out__REQ__AG CYREG_PRT0_AG\r
-#define SCSI_Out__REQ__AMUX CYREG_PRT0_AMUX\r
-#define SCSI_Out__REQ__BIE CYREG_PRT0_BIE\r
-#define SCSI_Out__REQ__BIT_MASK CYREG_PRT0_BIT_MASK\r
-#define SCSI_Out__REQ__BYP CYREG_PRT0_BYP\r
-#define SCSI_Out__REQ__CTL CYREG_PRT0_CTL\r
-#define SCSI_Out__REQ__DM0 CYREG_PRT0_DM0\r
-#define SCSI_Out__REQ__DM1 CYREG_PRT0_DM1\r
-#define SCSI_Out__REQ__DM2 CYREG_PRT0_DM2\r
-#define SCSI_Out__REQ__DR CYREG_PRT0_DR\r
-#define SCSI_Out__REQ__INP_DIS CYREG_PRT0_INP_DIS\r
-#define SCSI_Out__REQ__INTTYPE CYREG_PICU0_INTTYPE1\r
-#define SCSI_Out__REQ__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG\r
-#define SCSI_Out__REQ__LCD_EN CYREG_PRT0_LCD_EN\r
-#define SCSI_Out__REQ__MASK 0x02u\r
-#define SCSI_Out__REQ__PC CYREG_PRT0_PC1\r
-#define SCSI_Out__REQ__PORT 0u\r
-#define SCSI_Out__REQ__PRT CYREG_PRT0_PRT\r
-#define SCSI_Out__REQ__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL\r
-#define SCSI_Out__REQ__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN\r
-#define SCSI_Out__REQ__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0\r
-#define SCSI_Out__REQ__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1\r
-#define SCSI_Out__REQ__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0\r
-#define SCSI_Out__REQ__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1\r
-#define SCSI_Out__REQ__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT\r
-#define SCSI_Out__REQ__PS CYREG_PRT0_PS\r
-#define SCSI_Out__REQ__SHIFT 1u\r
-#define SCSI_Out__REQ__SLW CYREG_PRT0_SLW\r
-#define SCSI_Out__RST__AG CYREG_PRT0_AG\r
-#define SCSI_Out__RST__AMUX CYREG_PRT0_AMUX\r
-#define SCSI_Out__RST__BIE CYREG_PRT0_BIE\r
-#define SCSI_Out__RST__BIT_MASK CYREG_PRT0_BIT_MASK\r
-#define SCSI_Out__RST__BYP CYREG_PRT0_BYP\r
-#define SCSI_Out__RST__CTL CYREG_PRT0_CTL\r
-#define SCSI_Out__RST__DM0 CYREG_PRT0_DM0\r
-#define SCSI_Out__RST__DM1 CYREG_PRT0_DM1\r
-#define SCSI_Out__RST__DM2 CYREG_PRT0_DM2\r
-#define SCSI_Out__RST__DR CYREG_PRT0_DR\r
-#define SCSI_Out__RST__INP_DIS CYREG_PRT0_INP_DIS\r
-#define SCSI_Out__RST__INTTYPE CYREG_PICU0_INTTYPE5\r
-#define SCSI_Out__RST__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG\r
-#define SCSI_Out__RST__LCD_EN CYREG_PRT0_LCD_EN\r
-#define SCSI_Out__RST__MASK 0x20u\r
-#define SCSI_Out__RST__PC CYREG_PRT0_PC5\r
-#define SCSI_Out__RST__PORT 0u\r
-#define SCSI_Out__RST__PRT CYREG_PRT0_PRT\r
-#define SCSI_Out__RST__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL\r
-#define SCSI_Out__RST__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN\r
-#define SCSI_Out__RST__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0\r
-#define SCSI_Out__RST__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1\r
-#define SCSI_Out__RST__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0\r
-#define SCSI_Out__RST__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1\r
-#define SCSI_Out__RST__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT\r
-#define SCSI_Out__RST__PS CYREG_PRT0_PS\r
-#define SCSI_Out__RST__SHIFT 5u\r
-#define SCSI_Out__RST__SLW CYREG_PRT0_SLW\r
-#define SCSI_Out__SEL__AG CYREG_PRT0_AG\r
-#define SCSI_Out__SEL__AMUX CYREG_PRT0_AMUX\r
-#define SCSI_Out__SEL__BIE CYREG_PRT0_BIE\r
-#define SCSI_Out__SEL__BIT_MASK CYREG_PRT0_BIT_MASK\r
-#define SCSI_Out__SEL__BYP CYREG_PRT0_BYP\r
-#define SCSI_Out__SEL__CTL CYREG_PRT0_CTL\r
-#define SCSI_Out__SEL__DM0 CYREG_PRT0_DM0\r
-#define SCSI_Out__SEL__DM1 CYREG_PRT0_DM1\r
-#define SCSI_Out__SEL__DM2 CYREG_PRT0_DM2\r
-#define SCSI_Out__SEL__DR CYREG_PRT0_DR\r
-#define SCSI_Out__SEL__INP_DIS CYREG_PRT0_INP_DIS\r
-#define SCSI_Out__SEL__INTTYPE CYREG_PICU0_INTTYPE3\r
-#define SCSI_Out__SEL__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG\r
-#define SCSI_Out__SEL__LCD_EN CYREG_PRT0_LCD_EN\r
-#define SCSI_Out__SEL__MASK 0x08u\r
-#define SCSI_Out__SEL__PC CYREG_PRT0_PC3\r
-#define SCSI_Out__SEL__PORT 0u\r
-#define SCSI_Out__SEL__PRT CYREG_PRT0_PRT\r
-#define SCSI_Out__SEL__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL\r
-#define SCSI_Out__SEL__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN\r
-#define SCSI_Out__SEL__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0\r
-#define SCSI_Out__SEL__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1\r
-#define SCSI_Out__SEL__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0\r
-#define SCSI_Out__SEL__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1\r
-#define SCSI_Out__SEL__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT\r
-#define SCSI_Out__SEL__PS CYREG_PRT0_PS\r
-#define SCSI_Out__SEL__SHIFT 3u\r
-#define SCSI_Out__SEL__SLW CYREG_PRT0_SLW\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__0__MASK 0x01u\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__0__POS 0\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__1__MASK 0x02u\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__1__POS 1\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB08_09_ACTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB08_09_CTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB08_09_CTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB08_09_CTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B1_UDB08_09_CTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B1_UDB08_09_MSK\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B1_UDB08_09_MSK\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B1_UDB08_09_MSK\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB08_09_MSK\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__2__MASK 0x04u\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__2__POS 2\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__3__MASK 0x08u\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__3__POS 3\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__4__MASK 0x10u\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__4__POS 4\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__5__MASK 0x20u\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__5__POS 5\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__6__MASK 0x40u\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__6__POS 6\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__7__MASK 0x80u\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__7__POS 7\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B1_UDB08_ACTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG CYREG_B1_UDB08_CTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B1_UDB08_ST_CTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG CYREG_B1_UDB08_CTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG CYREG_B1_UDB08_ST_CTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__MASK 0xFFu\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB08_MSK_ACTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B1_UDB08_MSK_ACTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG CYREG_B1_UDB08_MSK\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK 0x01u\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__0__POS 0\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB08_09_ACTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB08_09_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB08_09_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB08_09_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB08_09_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB08_09_MSK\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB08_09_MSK\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB08_09_MSK\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB08_09_MSK\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB08_ACTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB08_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB08_ST_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB08_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB08_ST_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK 0x01u\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB08_MSK\r
-#define SCSI_Out_DBx__0__AG CYREG_PRT6_AG\r
-#define SCSI_Out_DBx__0__AMUX CYREG_PRT6_AMUX\r
-#define SCSI_Out_DBx__0__BIE CYREG_PRT6_BIE\r
-#define SCSI_Out_DBx__0__BIT_MASK CYREG_PRT6_BIT_MASK\r
-#define SCSI_Out_DBx__0__BYP CYREG_PRT6_BYP\r
-#define SCSI_Out_DBx__0__CTL CYREG_PRT6_CTL\r
-#define SCSI_Out_DBx__0__DM0 CYREG_PRT6_DM0\r
-#define SCSI_Out_DBx__0__DM1 CYREG_PRT6_DM1\r
-#define SCSI_Out_DBx__0__DM2 CYREG_PRT6_DM2\r
-#define SCSI_Out_DBx__0__DR CYREG_PRT6_DR\r
-#define SCSI_Out_DBx__0__INP_DIS CYREG_PRT6_INP_DIS\r
-#define SCSI_Out_DBx__0__INTTYPE CYREG_PICU6_INTTYPE3\r
-#define SCSI_Out_DBx__0__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
-#define SCSI_Out_DBx__0__LCD_EN CYREG_PRT6_LCD_EN\r
-#define SCSI_Out_DBx__0__MASK 0x08u\r
-#define SCSI_Out_DBx__0__PC CYREG_PRT6_PC3\r
-#define SCSI_Out_DBx__0__PORT 6u\r
-#define SCSI_Out_DBx__0__PRT CYREG_PRT6_PRT\r
-#define SCSI_Out_DBx__0__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
-#define SCSI_Out_DBx__0__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
-#define SCSI_Out_DBx__0__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
-#define SCSI_Out_DBx__0__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
-#define SCSI_Out_DBx__0__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
-#define SCSI_Out_DBx__0__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
-#define SCSI_Out_DBx__0__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
-#define SCSI_Out_DBx__0__PS CYREG_PRT6_PS\r
-#define SCSI_Out_DBx__0__SHIFT 3u\r
-#define SCSI_Out_DBx__0__SLW CYREG_PRT6_SLW\r
-#define SCSI_Out_DBx__1__AG CYREG_PRT6_AG\r
-#define SCSI_Out_DBx__1__AMUX CYREG_PRT6_AMUX\r
-#define SCSI_Out_DBx__1__BIE CYREG_PRT6_BIE\r
-#define SCSI_Out_DBx__1__BIT_MASK CYREG_PRT6_BIT_MASK\r
-#define SCSI_Out_DBx__1__BYP CYREG_PRT6_BYP\r
-#define SCSI_Out_DBx__1__CTL CYREG_PRT6_CTL\r
-#define SCSI_Out_DBx__1__DM0 CYREG_PRT6_DM0\r
-#define SCSI_Out_DBx__1__DM1 CYREG_PRT6_DM1\r
-#define SCSI_Out_DBx__1__DM2 CYREG_PRT6_DM2\r
-#define SCSI_Out_DBx__1__DR CYREG_PRT6_DR\r
-#define SCSI_Out_DBx__1__INP_DIS CYREG_PRT6_INP_DIS\r
-#define SCSI_Out_DBx__1__INTTYPE CYREG_PICU6_INTTYPE2\r
-#define SCSI_Out_DBx__1__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
-#define SCSI_Out_DBx__1__LCD_EN CYREG_PRT6_LCD_EN\r
-#define SCSI_Out_DBx__1__MASK 0x04u\r
-#define SCSI_Out_DBx__1__PC CYREG_PRT6_PC2\r
-#define SCSI_Out_DBx__1__PORT 6u\r
-#define SCSI_Out_DBx__1__PRT CYREG_PRT6_PRT\r
-#define SCSI_Out_DBx__1__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
-#define SCSI_Out_DBx__1__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
-#define SCSI_Out_DBx__1__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
-#define SCSI_Out_DBx__1__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
-#define SCSI_Out_DBx__1__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
-#define SCSI_Out_DBx__1__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
-#define SCSI_Out_DBx__1__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
-#define SCSI_Out_DBx__1__PS CYREG_PRT6_PS\r
-#define SCSI_Out_DBx__1__SHIFT 2u\r
-#define SCSI_Out_DBx__1__SLW CYREG_PRT6_SLW\r
-#define SCSI_Out_DBx__2__AG CYREG_PRT6_AG\r
-#define SCSI_Out_DBx__2__AMUX CYREG_PRT6_AMUX\r
-#define SCSI_Out_DBx__2__BIE CYREG_PRT6_BIE\r
-#define SCSI_Out_DBx__2__BIT_MASK CYREG_PRT6_BIT_MASK\r
-#define SCSI_Out_DBx__2__BYP CYREG_PRT6_BYP\r
-#define SCSI_Out_DBx__2__CTL CYREG_PRT6_CTL\r
-#define SCSI_Out_DBx__2__DM0 CYREG_PRT6_DM0\r
-#define SCSI_Out_DBx__2__DM1 CYREG_PRT6_DM1\r
-#define SCSI_Out_DBx__2__DM2 CYREG_PRT6_DM2\r
-#define SCSI_Out_DBx__2__DR CYREG_PRT6_DR\r
-#define SCSI_Out_DBx__2__INP_DIS CYREG_PRT6_INP_DIS\r
-#define SCSI_Out_DBx__2__INTTYPE CYREG_PICU6_INTTYPE1\r
-#define SCSI_Out_DBx__2__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
-#define SCSI_Out_DBx__2__LCD_EN CYREG_PRT6_LCD_EN\r
-#define SCSI_Out_DBx__2__MASK 0x02u\r
-#define SCSI_Out_DBx__2__PC CYREG_PRT6_PC1\r
-#define SCSI_Out_DBx__2__PORT 6u\r
-#define SCSI_Out_DBx__2__PRT CYREG_PRT6_PRT\r
-#define SCSI_Out_DBx__2__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
-#define SCSI_Out_DBx__2__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
-#define SCSI_Out_DBx__2__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
-#define SCSI_Out_DBx__2__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
-#define SCSI_Out_DBx__2__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
-#define SCSI_Out_DBx__2__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
-#define SCSI_Out_DBx__2__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
-#define SCSI_Out_DBx__2__PS CYREG_PRT6_PS\r
-#define SCSI_Out_DBx__2__SHIFT 1u\r
-#define SCSI_Out_DBx__2__SLW CYREG_PRT6_SLW\r
-#define SCSI_Out_DBx__3__AG CYREG_PRT6_AG\r
-#define SCSI_Out_DBx__3__AMUX CYREG_PRT6_AMUX\r
-#define SCSI_Out_DBx__3__BIE CYREG_PRT6_BIE\r
-#define SCSI_Out_DBx__3__BIT_MASK CYREG_PRT6_BIT_MASK\r
-#define SCSI_Out_DBx__3__BYP CYREG_PRT6_BYP\r
-#define SCSI_Out_DBx__3__CTL CYREG_PRT6_CTL\r
-#define SCSI_Out_DBx__3__DM0 CYREG_PRT6_DM0\r
-#define SCSI_Out_DBx__3__DM1 CYREG_PRT6_DM1\r
-#define SCSI_Out_DBx__3__DM2 CYREG_PRT6_DM2\r
-#define SCSI_Out_DBx__3__DR CYREG_PRT6_DR\r
-#define SCSI_Out_DBx__3__INP_DIS CYREG_PRT6_INP_DIS\r
-#define SCSI_Out_DBx__3__INTTYPE CYREG_PICU6_INTTYPE0\r
-#define SCSI_Out_DBx__3__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
-#define SCSI_Out_DBx__3__LCD_EN CYREG_PRT6_LCD_EN\r
-#define SCSI_Out_DBx__3__MASK 0x01u\r
-#define SCSI_Out_DBx__3__PC CYREG_PRT6_PC0\r
-#define SCSI_Out_DBx__3__PORT 6u\r
-#define SCSI_Out_DBx__3__PRT CYREG_PRT6_PRT\r
-#define SCSI_Out_DBx__3__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
-#define SCSI_Out_DBx__3__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
-#define SCSI_Out_DBx__3__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
-#define SCSI_Out_DBx__3__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
-#define SCSI_Out_DBx__3__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
-#define SCSI_Out_DBx__3__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
-#define SCSI_Out_DBx__3__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
-#define SCSI_Out_DBx__3__PS CYREG_PRT6_PS\r
-#define SCSI_Out_DBx__3__SHIFT 0u\r
-#define SCSI_Out_DBx__3__SLW CYREG_PRT6_SLW\r
-#define SCSI_Out_DBx__4__AG CYREG_PRT4_AG\r
-#define SCSI_Out_DBx__4__AMUX CYREG_PRT4_AMUX\r
-#define SCSI_Out_DBx__4__BIE CYREG_PRT4_BIE\r
-#define SCSI_Out_DBx__4__BIT_MASK CYREG_PRT4_BIT_MASK\r
-#define SCSI_Out_DBx__4__BYP CYREG_PRT4_BYP\r
-#define SCSI_Out_DBx__4__CTL CYREG_PRT4_CTL\r
-#define SCSI_Out_DBx__4__DM0 CYREG_PRT4_DM0\r
-#define SCSI_Out_DBx__4__DM1 CYREG_PRT4_DM1\r
-#define SCSI_Out_DBx__4__DM2 CYREG_PRT4_DM2\r
-#define SCSI_Out_DBx__4__DR CYREG_PRT4_DR\r
-#define SCSI_Out_DBx__4__INP_DIS CYREG_PRT4_INP_DIS\r
-#define SCSI_Out_DBx__4__INTTYPE CYREG_PICU4_INTTYPE7\r
-#define SCSI_Out_DBx__4__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG\r
-#define SCSI_Out_DBx__4__LCD_EN CYREG_PRT4_LCD_EN\r
-#define SCSI_Out_DBx__4__MASK 0x80u\r
-#define SCSI_Out_DBx__4__PC CYREG_PRT4_PC7\r
-#define SCSI_Out_DBx__4__PORT 4u\r
-#define SCSI_Out_DBx__4__PRT CYREG_PRT4_PRT\r
-#define SCSI_Out_DBx__4__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL\r
-#define SCSI_Out_DBx__4__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN\r
-#define SCSI_Out_DBx__4__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0\r
-#define SCSI_Out_DBx__4__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1\r
-#define SCSI_Out_DBx__4__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0\r
-#define SCSI_Out_DBx__4__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1\r
-#define SCSI_Out_DBx__4__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT\r
-#define SCSI_Out_DBx__4__PS CYREG_PRT4_PS\r
-#define SCSI_Out_DBx__4__SHIFT 7u\r
-#define SCSI_Out_DBx__4__SLW CYREG_PRT4_SLW\r
-#define SCSI_Out_DBx__5__AG CYREG_PRT4_AG\r
-#define SCSI_Out_DBx__5__AMUX CYREG_PRT4_AMUX\r
-#define SCSI_Out_DBx__5__BIE CYREG_PRT4_BIE\r
-#define SCSI_Out_DBx__5__BIT_MASK CYREG_PRT4_BIT_MASK\r
-#define SCSI_Out_DBx__5__BYP CYREG_PRT4_BYP\r
-#define SCSI_Out_DBx__5__CTL CYREG_PRT4_CTL\r
-#define SCSI_Out_DBx__5__DM0 CYREG_PRT4_DM0\r
-#define SCSI_Out_DBx__5__DM1 CYREG_PRT4_DM1\r
-#define SCSI_Out_DBx__5__DM2 CYREG_PRT4_DM2\r
-#define SCSI_Out_DBx__5__DR CYREG_PRT4_DR\r
-#define SCSI_Out_DBx__5__INP_DIS CYREG_PRT4_INP_DIS\r
-#define SCSI_Out_DBx__5__INTTYPE CYREG_PICU4_INTTYPE6\r
-#define SCSI_Out_DBx__5__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG\r
-#define SCSI_Out_DBx__5__LCD_EN CYREG_PRT4_LCD_EN\r
-#define SCSI_Out_DBx__5__MASK 0x40u\r
-#define SCSI_Out_DBx__5__PC CYREG_PRT4_PC6\r
-#define SCSI_Out_DBx__5__PORT 4u\r
-#define SCSI_Out_DBx__5__PRT CYREG_PRT4_PRT\r
-#define SCSI_Out_DBx__5__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL\r
-#define SCSI_Out_DBx__5__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN\r
-#define SCSI_Out_DBx__5__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0\r
-#define SCSI_Out_DBx__5__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1\r
-#define SCSI_Out_DBx__5__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0\r
-#define SCSI_Out_DBx__5__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1\r
-#define SCSI_Out_DBx__5__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT\r
-#define SCSI_Out_DBx__5__PS CYREG_PRT4_PS\r
-#define SCSI_Out_DBx__5__SHIFT 6u\r
-#define SCSI_Out_DBx__5__SLW CYREG_PRT4_SLW\r
-#define SCSI_Out_DBx__6__AG CYREG_PRT4_AG\r
-#define SCSI_Out_DBx__6__AMUX CYREG_PRT4_AMUX\r
-#define SCSI_Out_DBx__6__BIE CYREG_PRT4_BIE\r
-#define SCSI_Out_DBx__6__BIT_MASK CYREG_PRT4_BIT_MASK\r
-#define SCSI_Out_DBx__6__BYP CYREG_PRT4_BYP\r
-#define SCSI_Out_DBx__6__CTL CYREG_PRT4_CTL\r
-#define SCSI_Out_DBx__6__DM0 CYREG_PRT4_DM0\r
-#define SCSI_Out_DBx__6__DM1 CYREG_PRT4_DM1\r
-#define SCSI_Out_DBx__6__DM2 CYREG_PRT4_DM2\r
-#define SCSI_Out_DBx__6__DR CYREG_PRT4_DR\r
-#define SCSI_Out_DBx__6__INP_DIS CYREG_PRT4_INP_DIS\r
-#define SCSI_Out_DBx__6__INTTYPE CYREG_PICU4_INTTYPE5\r
-#define SCSI_Out_DBx__6__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG\r
-#define SCSI_Out_DBx__6__LCD_EN CYREG_PRT4_LCD_EN\r
-#define SCSI_Out_DBx__6__MASK 0x20u\r
-#define SCSI_Out_DBx__6__PC CYREG_PRT4_PC5\r
-#define SCSI_Out_DBx__6__PORT 4u\r
-#define SCSI_Out_DBx__6__PRT CYREG_PRT4_PRT\r
-#define SCSI_Out_DBx__6__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL\r
-#define SCSI_Out_DBx__6__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN\r
-#define SCSI_Out_DBx__6__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0\r
-#define SCSI_Out_DBx__6__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1\r
-#define SCSI_Out_DBx__6__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0\r
-#define SCSI_Out_DBx__6__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1\r
-#define SCSI_Out_DBx__6__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT\r
-#define SCSI_Out_DBx__6__PS CYREG_PRT4_PS\r
-#define SCSI_Out_DBx__6__SHIFT 5u\r
-#define SCSI_Out_DBx__6__SLW CYREG_PRT4_SLW\r
-#define SCSI_Out_DBx__7__AG CYREG_PRT4_AG\r
-#define SCSI_Out_DBx__7__AMUX CYREG_PRT4_AMUX\r
-#define SCSI_Out_DBx__7__BIE CYREG_PRT4_BIE\r
-#define SCSI_Out_DBx__7__BIT_MASK CYREG_PRT4_BIT_MASK\r
-#define SCSI_Out_DBx__7__BYP CYREG_PRT4_BYP\r
-#define SCSI_Out_DBx__7__CTL CYREG_PRT4_CTL\r
-#define SCSI_Out_DBx__7__DM0 CYREG_PRT4_DM0\r
-#define SCSI_Out_DBx__7__DM1 CYREG_PRT4_DM1\r
-#define SCSI_Out_DBx__7__DM2 CYREG_PRT4_DM2\r
-#define SCSI_Out_DBx__7__DR CYREG_PRT4_DR\r
-#define SCSI_Out_DBx__7__INP_DIS CYREG_PRT4_INP_DIS\r
-#define SCSI_Out_DBx__7__INTTYPE CYREG_PICU4_INTTYPE4\r
-#define SCSI_Out_DBx__7__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG\r
-#define SCSI_Out_DBx__7__LCD_EN CYREG_PRT4_LCD_EN\r
-#define SCSI_Out_DBx__7__MASK 0x10u\r
-#define SCSI_Out_DBx__7__PC CYREG_PRT4_PC4\r
-#define SCSI_Out_DBx__7__PORT 4u\r
-#define SCSI_Out_DBx__7__PRT CYREG_PRT4_PRT\r
-#define SCSI_Out_DBx__7__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL\r
-#define SCSI_Out_DBx__7__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN\r
-#define SCSI_Out_DBx__7__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0\r
-#define SCSI_Out_DBx__7__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1\r
-#define SCSI_Out_DBx__7__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0\r
-#define SCSI_Out_DBx__7__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1\r
-#define SCSI_Out_DBx__7__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT\r
-#define SCSI_Out_DBx__7__PS CYREG_PRT4_PS\r
-#define SCSI_Out_DBx__7__SHIFT 4u\r
-#define SCSI_Out_DBx__7__SLW CYREG_PRT4_SLW\r
-#define SCSI_Out_DBx__DB0__AG CYREG_PRT6_AG\r
-#define SCSI_Out_DBx__DB0__AMUX CYREG_PRT6_AMUX\r
-#define SCSI_Out_DBx__DB0__BIE CYREG_PRT6_BIE\r
-#define SCSI_Out_DBx__DB0__BIT_MASK CYREG_PRT6_BIT_MASK\r
-#define SCSI_Out_DBx__DB0__BYP CYREG_PRT6_BYP\r
-#define SCSI_Out_DBx__DB0__CTL CYREG_PRT6_CTL\r
-#define SCSI_Out_DBx__DB0__DM0 CYREG_PRT6_DM0\r
-#define SCSI_Out_DBx__DB0__DM1 CYREG_PRT6_DM1\r
-#define SCSI_Out_DBx__DB0__DM2 CYREG_PRT6_DM2\r
-#define SCSI_Out_DBx__DB0__DR CYREG_PRT6_DR\r
-#define SCSI_Out_DBx__DB0__INP_DIS CYREG_PRT6_INP_DIS\r
-#define SCSI_Out_DBx__DB0__INTTYPE CYREG_PICU6_INTTYPE3\r
-#define SCSI_Out_DBx__DB0__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
-#define SCSI_Out_DBx__DB0__LCD_EN CYREG_PRT6_LCD_EN\r
-#define SCSI_Out_DBx__DB0__MASK 0x08u\r
-#define SCSI_Out_DBx__DB0__PC CYREG_PRT6_PC3\r
-#define SCSI_Out_DBx__DB0__PORT 6u\r
-#define SCSI_Out_DBx__DB0__PRT CYREG_PRT6_PRT\r
-#define SCSI_Out_DBx__DB0__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
-#define SCSI_Out_DBx__DB0__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
-#define SCSI_Out_DBx__DB0__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
-#define SCSI_Out_DBx__DB0__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
-#define SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
-#define SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
-#define SCSI_Out_DBx__DB0__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
-#define SCSI_Out_DBx__DB0__PS CYREG_PRT6_PS\r
-#define SCSI_Out_DBx__DB0__SHIFT 3u\r
-#define SCSI_Out_DBx__DB0__SLW CYREG_PRT6_SLW\r
-#define SCSI_Out_DBx__DB1__AG CYREG_PRT6_AG\r
-#define SCSI_Out_DBx__DB1__AMUX CYREG_PRT6_AMUX\r
-#define SCSI_Out_DBx__DB1__BIE CYREG_PRT6_BIE\r
-#define SCSI_Out_DBx__DB1__BIT_MASK CYREG_PRT6_BIT_MASK\r
-#define SCSI_Out_DBx__DB1__BYP CYREG_PRT6_BYP\r
-#define SCSI_Out_DBx__DB1__CTL CYREG_PRT6_CTL\r
-#define SCSI_Out_DBx__DB1__DM0 CYREG_PRT6_DM0\r
-#define SCSI_Out_DBx__DB1__DM1 CYREG_PRT6_DM1\r
-#define SCSI_Out_DBx__DB1__DM2 CYREG_PRT6_DM2\r
-#define SCSI_Out_DBx__DB1__DR CYREG_PRT6_DR\r
-#define SCSI_Out_DBx__DB1__INP_DIS CYREG_PRT6_INP_DIS\r
-#define SCSI_Out_DBx__DB1__INTTYPE CYREG_PICU6_INTTYPE2\r
-#define SCSI_Out_DBx__DB1__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
-#define SCSI_Out_DBx__DB1__LCD_EN CYREG_PRT6_LCD_EN\r
-#define SCSI_Out_DBx__DB1__MASK 0x04u\r
-#define SCSI_Out_DBx__DB1__PC CYREG_PRT6_PC2\r
-#define SCSI_Out_DBx__DB1__PORT 6u\r
-#define SCSI_Out_DBx__DB1__PRT CYREG_PRT6_PRT\r
-#define SCSI_Out_DBx__DB1__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
-#define SCSI_Out_DBx__DB1__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
-#define SCSI_Out_DBx__DB1__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
-#define SCSI_Out_DBx__DB1__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
-#define SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
-#define SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
-#define SCSI_Out_DBx__DB1__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
-#define SCSI_Out_DBx__DB1__PS CYREG_PRT6_PS\r
-#define SCSI_Out_DBx__DB1__SHIFT 2u\r
-#define SCSI_Out_DBx__DB1__SLW CYREG_PRT6_SLW\r
-#define SCSI_Out_DBx__DB2__AG CYREG_PRT6_AG\r
-#define SCSI_Out_DBx__DB2__AMUX CYREG_PRT6_AMUX\r
-#define SCSI_Out_DBx__DB2__BIE CYREG_PRT6_BIE\r
-#define SCSI_Out_DBx__DB2__BIT_MASK CYREG_PRT6_BIT_MASK\r
-#define SCSI_Out_DBx__DB2__BYP CYREG_PRT6_BYP\r
-#define SCSI_Out_DBx__DB2__CTL CYREG_PRT6_CTL\r
-#define SCSI_Out_DBx__DB2__DM0 CYREG_PRT6_DM0\r
-#define SCSI_Out_DBx__DB2__DM1 CYREG_PRT6_DM1\r
-#define SCSI_Out_DBx__DB2__DM2 CYREG_PRT6_DM2\r
-#define SCSI_Out_DBx__DB2__DR CYREG_PRT6_DR\r
-#define SCSI_Out_DBx__DB2__INP_DIS CYREG_PRT6_INP_DIS\r
-#define SCSI_Out_DBx__DB2__INTTYPE CYREG_PICU6_INTTYPE1\r
-#define SCSI_Out_DBx__DB2__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
-#define SCSI_Out_DBx__DB2__LCD_EN CYREG_PRT6_LCD_EN\r
-#define SCSI_Out_DBx__DB2__MASK 0x02u\r
-#define SCSI_Out_DBx__DB2__PC CYREG_PRT6_PC1\r
-#define SCSI_Out_DBx__DB2__PORT 6u\r
-#define SCSI_Out_DBx__DB2__PRT CYREG_PRT6_PRT\r
-#define SCSI_Out_DBx__DB2__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
-#define SCSI_Out_DBx__DB2__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
-#define SCSI_Out_DBx__DB2__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
-#define SCSI_Out_DBx__DB2__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
-#define SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
-#define SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
-#define SCSI_Out_DBx__DB2__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
-#define SCSI_Out_DBx__DB2__PS CYREG_PRT6_PS\r
-#define SCSI_Out_DBx__DB2__SHIFT 1u\r
-#define SCSI_Out_DBx__DB2__SLW CYREG_PRT6_SLW\r
-#define SCSI_Out_DBx__DB3__AG CYREG_PRT6_AG\r
-#define SCSI_Out_DBx__DB3__AMUX CYREG_PRT6_AMUX\r
-#define SCSI_Out_DBx__DB3__BIE CYREG_PRT6_BIE\r
-#define SCSI_Out_DBx__DB3__BIT_MASK CYREG_PRT6_BIT_MASK\r
-#define SCSI_Out_DBx__DB3__BYP CYREG_PRT6_BYP\r
-#define SCSI_Out_DBx__DB3__CTL CYREG_PRT6_CTL\r
-#define SCSI_Out_DBx__DB3__DM0 CYREG_PRT6_DM0\r
-#define SCSI_Out_DBx__DB3__DM1 CYREG_PRT6_DM1\r
-#define SCSI_Out_DBx__DB3__DM2 CYREG_PRT6_DM2\r
-#define SCSI_Out_DBx__DB3__DR CYREG_PRT6_DR\r
-#define SCSI_Out_DBx__DB3__INP_DIS CYREG_PRT6_INP_DIS\r
-#define SCSI_Out_DBx__DB3__INTTYPE CYREG_PICU6_INTTYPE0\r
-#define SCSI_Out_DBx__DB3__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
-#define SCSI_Out_DBx__DB3__LCD_EN CYREG_PRT6_LCD_EN\r
-#define SCSI_Out_DBx__DB3__MASK 0x01u\r
-#define SCSI_Out_DBx__DB3__PC CYREG_PRT6_PC0\r
-#define SCSI_Out_DBx__DB3__PORT 6u\r
-#define SCSI_Out_DBx__DB3__PRT CYREG_PRT6_PRT\r
-#define SCSI_Out_DBx__DB3__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
-#define SCSI_Out_DBx__DB3__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
-#define SCSI_Out_DBx__DB3__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
-#define SCSI_Out_DBx__DB3__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
-#define SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
-#define SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
-#define SCSI_Out_DBx__DB3__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
-#define SCSI_Out_DBx__DB3__PS CYREG_PRT6_PS\r
-#define SCSI_Out_DBx__DB3__SHIFT 0u\r
-#define SCSI_Out_DBx__DB3__SLW CYREG_PRT6_SLW\r
-#define SCSI_Out_DBx__DB4__AG CYREG_PRT4_AG\r
-#define SCSI_Out_DBx__DB4__AMUX CYREG_PRT4_AMUX\r
-#define SCSI_Out_DBx__DB4__BIE CYREG_PRT4_BIE\r
-#define SCSI_Out_DBx__DB4__BIT_MASK CYREG_PRT4_BIT_MASK\r
-#define SCSI_Out_DBx__DB4__BYP CYREG_PRT4_BYP\r
-#define SCSI_Out_DBx__DB4__CTL CYREG_PRT4_CTL\r
-#define SCSI_Out_DBx__DB4__DM0 CYREG_PRT4_DM0\r
-#define SCSI_Out_DBx__DB4__DM1 CYREG_PRT4_DM1\r
-#define SCSI_Out_DBx__DB4__DM2 CYREG_PRT4_DM2\r
-#define SCSI_Out_DBx__DB4__DR CYREG_PRT4_DR\r
-#define SCSI_Out_DBx__DB4__INP_DIS CYREG_PRT4_INP_DIS\r
-#define SCSI_Out_DBx__DB4__INTTYPE CYREG_PICU4_INTTYPE7\r
-#define SCSI_Out_DBx__DB4__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG\r
-#define SCSI_Out_DBx__DB4__LCD_EN CYREG_PRT4_LCD_EN\r
-#define SCSI_Out_DBx__DB4__MASK 0x80u\r
-#define SCSI_Out_DBx__DB4__PC CYREG_PRT4_PC7\r
-#define SCSI_Out_DBx__DB4__PORT 4u\r
-#define SCSI_Out_DBx__DB4__PRT CYREG_PRT4_PRT\r
-#define SCSI_Out_DBx__DB4__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL\r
-#define SCSI_Out_DBx__DB4__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN\r
-#define SCSI_Out_DBx__DB4__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0\r
-#define SCSI_Out_DBx__DB4__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1\r
-#define SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0\r
-#define SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1\r
-#define SCSI_Out_DBx__DB4__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT\r
-#define SCSI_Out_DBx__DB4__PS CYREG_PRT4_PS\r
-#define SCSI_Out_DBx__DB4__SHIFT 7u\r
-#define SCSI_Out_DBx__DB4__SLW CYREG_PRT4_SLW\r
-#define SCSI_Out_DBx__DB5__AG CYREG_PRT4_AG\r
-#define SCSI_Out_DBx__DB5__AMUX CYREG_PRT4_AMUX\r
-#define SCSI_Out_DBx__DB5__BIE CYREG_PRT4_BIE\r
-#define SCSI_Out_DBx__DB5__BIT_MASK CYREG_PRT4_BIT_MASK\r
-#define SCSI_Out_DBx__DB5__BYP CYREG_PRT4_BYP\r
-#define SCSI_Out_DBx__DB5__CTL CYREG_PRT4_CTL\r
-#define SCSI_Out_DBx__DB5__DM0 CYREG_PRT4_DM0\r
-#define SCSI_Out_DBx__DB5__DM1 CYREG_PRT4_DM1\r
-#define SCSI_Out_DBx__DB5__DM2 CYREG_PRT4_DM2\r
-#define SCSI_Out_DBx__DB5__DR CYREG_PRT4_DR\r
-#define SCSI_Out_DBx__DB5__INP_DIS CYREG_PRT4_INP_DIS\r
-#define SCSI_Out_DBx__DB5__INTTYPE CYREG_PICU4_INTTYPE6\r
-#define SCSI_Out_DBx__DB5__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG\r
-#define SCSI_Out_DBx__DB5__LCD_EN CYREG_PRT4_LCD_EN\r
-#define SCSI_Out_DBx__DB5__MASK 0x40u\r
-#define SCSI_Out_DBx__DB5__PC CYREG_PRT4_PC6\r
-#define SCSI_Out_DBx__DB5__PORT 4u\r
-#define SCSI_Out_DBx__DB5__PRT CYREG_PRT4_PRT\r
-#define SCSI_Out_DBx__DB5__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL\r
-#define SCSI_Out_DBx__DB5__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN\r
-#define SCSI_Out_DBx__DB5__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0\r
-#define SCSI_Out_DBx__DB5__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1\r
-#define SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0\r
-#define SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1\r
-#define SCSI_Out_DBx__DB5__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT\r
-#define SCSI_Out_DBx__DB5__PS CYREG_PRT4_PS\r
-#define SCSI_Out_DBx__DB5__SHIFT 6u\r
-#define SCSI_Out_DBx__DB5__SLW CYREG_PRT4_SLW\r
-#define SCSI_Out_DBx__DB6__AG CYREG_PRT4_AG\r
-#define SCSI_Out_DBx__DB6__AMUX CYREG_PRT4_AMUX\r
-#define SCSI_Out_DBx__DB6__BIE CYREG_PRT4_BIE\r
-#define SCSI_Out_DBx__DB6__BIT_MASK CYREG_PRT4_BIT_MASK\r
-#define SCSI_Out_DBx__DB6__BYP CYREG_PRT4_BYP\r
-#define SCSI_Out_DBx__DB6__CTL CYREG_PRT4_CTL\r
-#define SCSI_Out_DBx__DB6__DM0 CYREG_PRT4_DM0\r
-#define SCSI_Out_DBx__DB6__DM1 CYREG_PRT4_DM1\r
-#define SCSI_Out_DBx__DB6__DM2 CYREG_PRT4_DM2\r
-#define SCSI_Out_DBx__DB6__DR CYREG_PRT4_DR\r
-#define SCSI_Out_DBx__DB6__INP_DIS CYREG_PRT4_INP_DIS\r
-#define SCSI_Out_DBx__DB6__INTTYPE CYREG_PICU4_INTTYPE5\r
-#define SCSI_Out_DBx__DB6__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG\r
-#define SCSI_Out_DBx__DB6__LCD_EN CYREG_PRT4_LCD_EN\r
-#define SCSI_Out_DBx__DB6__MASK 0x20u\r
-#define SCSI_Out_DBx__DB6__PC CYREG_PRT4_PC5\r
-#define SCSI_Out_DBx__DB6__PORT 4u\r
-#define SCSI_Out_DBx__DB6__PRT CYREG_PRT4_PRT\r
-#define SCSI_Out_DBx__DB6__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL\r
-#define SCSI_Out_DBx__DB6__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN\r
-#define SCSI_Out_DBx__DB6__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0\r
-#define SCSI_Out_DBx__DB6__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1\r
-#define SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0\r
-#define SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1\r
-#define SCSI_Out_DBx__DB6__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT\r
-#define SCSI_Out_DBx__DB6__PS CYREG_PRT4_PS\r
-#define SCSI_Out_DBx__DB6__SHIFT 5u\r
-#define SCSI_Out_DBx__DB6__SLW CYREG_PRT4_SLW\r
-#define SCSI_Out_DBx__DB7__AG CYREG_PRT4_AG\r
-#define SCSI_Out_DBx__DB7__AMUX CYREG_PRT4_AMUX\r
-#define SCSI_Out_DBx__DB7__BIE CYREG_PRT4_BIE\r
-#define SCSI_Out_DBx__DB7__BIT_MASK CYREG_PRT4_BIT_MASK\r
-#define SCSI_Out_DBx__DB7__BYP CYREG_PRT4_BYP\r
-#define SCSI_Out_DBx__DB7__CTL CYREG_PRT4_CTL\r
-#define SCSI_Out_DBx__DB7__DM0 CYREG_PRT4_DM0\r
-#define SCSI_Out_DBx__DB7__DM1 CYREG_PRT4_DM1\r
-#define SCSI_Out_DBx__DB7__DM2 CYREG_PRT4_DM2\r
-#define SCSI_Out_DBx__DB7__DR CYREG_PRT4_DR\r
-#define SCSI_Out_DBx__DB7__INP_DIS CYREG_PRT4_INP_DIS\r
-#define SCSI_Out_DBx__DB7__INTTYPE CYREG_PICU4_INTTYPE4\r
-#define SCSI_Out_DBx__DB7__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG\r
-#define SCSI_Out_DBx__DB7__LCD_EN CYREG_PRT4_LCD_EN\r
-#define SCSI_Out_DBx__DB7__MASK 0x10u\r
-#define SCSI_Out_DBx__DB7__PC CYREG_PRT4_PC4\r
-#define SCSI_Out_DBx__DB7__PORT 4u\r
-#define SCSI_Out_DBx__DB7__PRT CYREG_PRT4_PRT\r
-#define SCSI_Out_DBx__DB7__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL\r
-#define SCSI_Out_DBx__DB7__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN\r
-#define SCSI_Out_DBx__DB7__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0\r
-#define SCSI_Out_DBx__DB7__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1\r
-#define SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0\r
-#define SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1\r
-#define SCSI_Out_DBx__DB7__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT\r
-#define SCSI_Out_DBx__DB7__PS CYREG_PRT4_PS\r
-#define SCSI_Out_DBx__DB7__SHIFT 4u\r
-#define SCSI_Out_DBx__DB7__SLW CYREG_PRT4_SLW\r
-\r
-/* SCSI_Parity_Error */\r
-#define SCSI_Parity_Error_sts_sts_reg__0__MASK 0x01u\r
-#define SCSI_Parity_Error_sts_sts_reg__0__POS 0\r
-#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB01_02_ACTL\r
-#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB01_02_ST\r
-#define SCSI_Parity_Error_sts_sts_reg__MASK 0x01u\r
-#define SCSI_Parity_Error_sts_sts_reg__MASK_REG CYREG_B0_UDB01_MSK\r
-#define SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB01_ACTL\r
-#define SCSI_Parity_Error_sts_sts_reg__STATUS_REG CYREG_B0_UDB01_ST\r
-\r
-/* SCSI_RST_ISR */\r
-#define SCSI_RST_ISR__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
-#define SCSI_RST_ISR__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
-#define SCSI_RST_ISR__INTC_MASK 0x02u\r
-#define SCSI_RST_ISR__INTC_NUMBER 1u\r
-#define SCSI_RST_ISR__INTC_PRIOR_NUM 7u\r
-#define SCSI_RST_ISR__INTC_PRIOR_REG CYREG_NVIC_PRI_1\r
-#define SCSI_RST_ISR__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
-#define SCSI_RST_ISR__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
-\r
-/* SCSI_RX_DMA */\r
-#define SCSI_RX_DMA__DRQ_CTL CYREG_IDMUX_DRQ_CTL0\r
-#define SCSI_RX_DMA__DRQ_NUMBER 0u\r
-#define SCSI_RX_DMA__NUMBEROF_TDS 0u\r
-#define SCSI_RX_DMA__PRIORITY 2u\r
-#define SCSI_RX_DMA__TERMIN_EN 0u\r
-#define SCSI_RX_DMA__TERMIN_SEL 0u\r
-#define SCSI_RX_DMA__TERMOUT0_EN 1u\r
-#define SCSI_RX_DMA__TERMOUT0_SEL 0u\r
-#define SCSI_RX_DMA__TERMOUT1_EN 0u\r
-#define SCSI_RX_DMA__TERMOUT1_SEL 0u\r
-#define SCSI_RX_DMA_COMPLETE__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
-#define SCSI_RX_DMA_COMPLETE__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
-#define SCSI_RX_DMA_COMPLETE__INTC_MASK 0x04u\r
-#define SCSI_RX_DMA_COMPLETE__INTC_NUMBER 2u\r
-#define SCSI_RX_DMA_COMPLETE__INTC_PRIOR_NUM 7u\r
-#define SCSI_RX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_2\r
-#define SCSI_RX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
-#define SCSI_RX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
-\r
-/* SCSI_SEL_ISR */\r
-#define SCSI_SEL_ISR__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
-#define SCSI_SEL_ISR__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
-#define SCSI_SEL_ISR__INTC_MASK 0x08u\r
-#define SCSI_SEL_ISR__INTC_NUMBER 3u\r
-#define SCSI_SEL_ISR__INTC_PRIOR_NUM 7u\r
-#define SCSI_SEL_ISR__INTC_PRIOR_REG CYREG_NVIC_PRI_3\r
-#define SCSI_SEL_ISR__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
-#define SCSI_SEL_ISR__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
-\r
-/* SCSI_TX_DMA */\r
-#define SCSI_TX_DMA__DRQ_CTL CYREG_IDMUX_DRQ_CTL0\r
-#define SCSI_TX_DMA__DRQ_NUMBER 1u\r
-#define SCSI_TX_DMA__NUMBEROF_TDS 0u\r
-#define SCSI_TX_DMA__PRIORITY 2u\r
-#define SCSI_TX_DMA__TERMIN_EN 0u\r
-#define SCSI_TX_DMA__TERMIN_SEL 0u\r
-#define SCSI_TX_DMA__TERMOUT0_EN 1u\r
-#define SCSI_TX_DMA__TERMOUT0_SEL 1u\r
-#define SCSI_TX_DMA__TERMOUT1_EN 0u\r
-#define SCSI_TX_DMA__TERMOUT1_SEL 0u\r
-#define SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
-#define SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
-#define SCSI_TX_DMA_COMPLETE__INTC_MASK 0x10u\r
-#define SCSI_TX_DMA_COMPLETE__INTC_NUMBER 4u\r
-#define SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM 7u\r
-#define SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_4\r
-#define SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
-#define SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
-\r
-/* SDCard_BSPIM */\r
-#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB04_05_ACTL\r
-#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB04_05_CTL\r
-#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB04_05_CTL\r
-#define SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB04_05_CTL\r
-#define SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B1_UDB04_05_CTL\r
-#define SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B1_UDB04_05_MSK\r
-#define SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B1_UDB04_05_MSK\r
-#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B1_UDB04_05_MSK\r
-#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB04_05_MSK\r
-#define SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B1_UDB04_ACTL\r
-#define SDCard_BSPIM_BitCounter__CONTROL_REG CYREG_B1_UDB04_CTL\r
-#define SDCard_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B1_UDB04_ST_CTL\r
-#define SDCard_BSPIM_BitCounter__COUNT_REG CYREG_B1_UDB04_CTL\r
-#define SDCard_BSPIM_BitCounter__COUNT_ST_REG CYREG_B1_UDB04_ST_CTL\r
-#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL\r
-#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL\r
-#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B1_UDB04_MSK\r
-#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB04_05_ACTL\r
-#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B1_UDB04_05_ST\r
-#define SDCard_BSPIM_BitCounter_ST__MASK_REG CYREG_B1_UDB04_MSK\r
-#define SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL\r
-#define SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL\r
-#define SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B1_UDB04_ACTL\r
-#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B1_UDB04_ST_CTL\r
-#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B1_UDB04_ST_CTL\r
-#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B1_UDB04_ST\r
-#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB08_09_ACTL\r
-#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B1_UDB08_09_ST\r
-#define SDCard_BSPIM_RxStsReg__4__MASK 0x10u\r
-#define SDCard_BSPIM_RxStsReg__4__POS 4\r
-#define SDCard_BSPIM_RxStsReg__5__MASK 0x20u\r
-#define SDCard_BSPIM_RxStsReg__5__POS 5\r
-#define SDCard_BSPIM_RxStsReg__6__MASK 0x40u\r
-#define SDCard_BSPIM_RxStsReg__6__POS 6\r
-#define SDCard_BSPIM_RxStsReg__MASK 0x70u\r
-#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B1_UDB08_MSK\r
-#define SDCard_BSPIM_RxStsReg__MASK_ST_AUX_CTL_REG CYREG_B1_UDB08_MSK_ACTL\r
-#define SDCard_BSPIM_RxStsReg__PER_ST_AUX_CTL_REG CYREG_B1_UDB08_MSK_ACTL\r
-#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB08_ACTL\r
-#define SDCard_BSPIM_RxStsReg__STATUS_CNT_REG CYREG_B1_UDB08_ST_CTL\r
-#define SDCard_BSPIM_RxStsReg__STATUS_CONTROL_REG CYREG_B1_UDB08_ST_CTL\r
-#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B1_UDB08_ST\r
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B1_UDB04_05_A0\r
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B1_UDB04_05_A1\r
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG CYREG_B1_UDB04_05_D0\r
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG CYREG_B1_UDB04_05_D1\r
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG CYREG_B1_UDB04_05_ACTL\r
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG CYREG_B1_UDB04_05_F0\r
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG CYREG_B1_UDB04_05_F1\r
-#define SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG CYREG_B1_UDB04_A0_A1\r
-#define SDCard_BSPIM_sR8_Dp_u0__A0_REG CYREG_B1_UDB04_A0\r
-#define SDCard_BSPIM_sR8_Dp_u0__A1_REG CYREG_B1_UDB04_A1\r
-#define SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG CYREG_B1_UDB04_D0_D1\r
-#define SDCard_BSPIM_sR8_Dp_u0__D0_REG CYREG_B1_UDB04_D0\r
-#define SDCard_BSPIM_sR8_Dp_u0__D1_REG CYREG_B1_UDB04_D1\r
-#define SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG CYREG_B1_UDB04_ACTL\r
-#define SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG CYREG_B1_UDB04_F0_F1\r
-#define SDCard_BSPIM_sR8_Dp_u0__F0_REG CYREG_B1_UDB04_F0\r
-#define SDCard_BSPIM_sR8_Dp_u0__F1_REG CYREG_B1_UDB04_F1\r
-#define SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL\r
-#define SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL\r
-#define SDCard_BSPIM_TxStsReg__0__MASK 0x01u\r
-#define SDCard_BSPIM_TxStsReg__0__POS 0\r
-#define SDCard_BSPIM_TxStsReg__1__MASK 0x02u\r
-#define SDCard_BSPIM_TxStsReg__1__POS 1\r
-#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB07_08_ACTL\r
-#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B1_UDB07_08_ST\r
-#define SDCard_BSPIM_TxStsReg__2__MASK 0x04u\r
-#define SDCard_BSPIM_TxStsReg__2__POS 2\r
-#define SDCard_BSPIM_TxStsReg__3__MASK 0x08u\r
-#define SDCard_BSPIM_TxStsReg__3__POS 3\r
-#define SDCard_BSPIM_TxStsReg__4__MASK 0x10u\r
-#define SDCard_BSPIM_TxStsReg__4__POS 4\r
-#define SDCard_BSPIM_TxStsReg__MASK 0x1Fu\r
-#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B1_UDB07_MSK\r
-#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB07_ACTL\r
-#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B1_UDB07_ST\r
-\r
-/* SD_CD */\r
-#define SD_CD__0__INTTYPE CYREG_PICU3_INTTYPE6\r
-#define SD_CD__0__MASK 0x40u\r
-#define SD_CD__0__PC CYREG_PRT3_PC6\r
-#define SD_CD__0__PORT 3u\r
-#define SD_CD__0__SHIFT 6u\r
-#define SD_CD__AG CYREG_PRT3_AG\r
-#define SD_CD__AMUX CYREG_PRT3_AMUX\r
-#define SD_CD__BIE CYREG_PRT3_BIE\r
-#define SD_CD__BIT_MASK CYREG_PRT3_BIT_MASK\r
-#define SD_CD__BYP CYREG_PRT3_BYP\r
-#define SD_CD__CTL CYREG_PRT3_CTL\r
-#define SD_CD__DM0 CYREG_PRT3_DM0\r
-#define SD_CD__DM1 CYREG_PRT3_DM1\r
-#define SD_CD__DM2 CYREG_PRT3_DM2\r
-#define SD_CD__DR CYREG_PRT3_DR\r
-#define SD_CD__INP_DIS CYREG_PRT3_INP_DIS\r
-#define SD_CD__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU3_BASE\r
-#define SD_CD__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG\r
-#define SD_CD__LCD_EN CYREG_PRT3_LCD_EN\r
-#define SD_CD__MASK 0x40u\r
-#define SD_CD__PORT 3u\r
-#define SD_CD__PRT CYREG_PRT3_PRT\r
-#define SD_CD__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL\r
-#define SD_CD__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN\r
-#define SD_CD__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0\r
-#define SD_CD__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1\r
-#define SD_CD__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0\r
-#define SD_CD__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1\r
-#define SD_CD__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT\r
-#define SD_CD__PS CYREG_PRT3_PS\r
-#define SD_CD__SHIFT 6u\r
-#define SD_CD__SLW CYREG_PRT3_SLW\r
-\r
-/* SD_CS */\r
-#define SD_CS__0__INTTYPE CYREG_PICU3_INTTYPE4\r
-#define SD_CS__0__MASK 0x10u\r
-#define SD_CS__0__PC CYREG_PRT3_PC4\r
-#define SD_CS__0__PORT 3u\r
-#define SD_CS__0__SHIFT 4u\r
-#define SD_CS__AG CYREG_PRT3_AG\r
-#define SD_CS__AMUX CYREG_PRT3_AMUX\r
-#define SD_CS__BIE CYREG_PRT3_BIE\r
-#define SD_CS__BIT_MASK CYREG_PRT3_BIT_MASK\r
-#define SD_CS__BYP CYREG_PRT3_BYP\r
-#define SD_CS__CTL CYREG_PRT3_CTL\r
-#define SD_CS__DM0 CYREG_PRT3_DM0\r
-#define SD_CS__DM1 CYREG_PRT3_DM1\r
-#define SD_CS__DM2 CYREG_PRT3_DM2\r
-#define SD_CS__DR CYREG_PRT3_DR\r
-#define SD_CS__INP_DIS CYREG_PRT3_INP_DIS\r
-#define SD_CS__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU3_BASE\r
-#define SD_CS__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG\r
-#define SD_CS__LCD_EN CYREG_PRT3_LCD_EN\r
-#define SD_CS__MASK 0x10u\r
-#define SD_CS__PORT 3u\r
-#define SD_CS__PRT CYREG_PRT3_PRT\r
-#define SD_CS__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL\r
-#define SD_CS__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN\r
-#define SD_CS__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0\r
-#define SD_CS__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1\r
-#define SD_CS__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0\r
-#define SD_CS__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1\r
-#define SD_CS__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT\r
-#define SD_CS__PS CYREG_PRT3_PS\r
-#define SD_CS__SHIFT 4u\r
-#define SD_CS__SLW CYREG_PRT3_SLW\r
-\r
-/* SD_DAT1 */\r
-#define SD_DAT1__0__INTTYPE CYREG_PICU3_INTTYPE0\r
-#define SD_DAT1__0__MASK 0x01u\r
-#define SD_DAT1__0__PC CYREG_PRT3_PC0\r
-#define SD_DAT1__0__PORT 3u\r
-#define SD_DAT1__0__SHIFT 0u\r
-#define SD_DAT1__AG CYREG_PRT3_AG\r
-#define SD_DAT1__AMUX CYREG_PRT3_AMUX\r
-#define SD_DAT1__BIE CYREG_PRT3_BIE\r
-#define SD_DAT1__BIT_MASK CYREG_PRT3_BIT_MASK\r
-#define SD_DAT1__BYP CYREG_PRT3_BYP\r
-#define SD_DAT1__CTL CYREG_PRT3_CTL\r
-#define SD_DAT1__DM0 CYREG_PRT3_DM0\r
-#define SD_DAT1__DM1 CYREG_PRT3_DM1\r
-#define SD_DAT1__DM2 CYREG_PRT3_DM2\r
-#define SD_DAT1__DR CYREG_PRT3_DR\r
-#define SD_DAT1__INP_DIS CYREG_PRT3_INP_DIS\r
-#define SD_DAT1__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU3_BASE\r
-#define SD_DAT1__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG\r
-#define SD_DAT1__LCD_EN CYREG_PRT3_LCD_EN\r
-#define SD_DAT1__MASK 0x01u\r
-#define SD_DAT1__PORT 3u\r
-#define SD_DAT1__PRT CYREG_PRT3_PRT\r
-#define SD_DAT1__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL\r
-#define SD_DAT1__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN\r
-#define SD_DAT1__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0\r
-#define SD_DAT1__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1\r
-#define SD_DAT1__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0\r
-#define SD_DAT1__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1\r
-#define SD_DAT1__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT\r
-#define SD_DAT1__PS CYREG_PRT3_PS\r
-#define SD_DAT1__SHIFT 0u\r
-#define SD_DAT1__SLW CYREG_PRT3_SLW\r
-\r
-/* SD_DAT2 */\r
-#define SD_DAT2__0__INTTYPE CYREG_PICU3_INTTYPE5\r
-#define SD_DAT2__0__MASK 0x20u\r
-#define SD_DAT2__0__PC CYREG_PRT3_PC5\r
-#define SD_DAT2__0__PORT 3u\r
-#define SD_DAT2__0__SHIFT 5u\r
-#define SD_DAT2__AG CYREG_PRT3_AG\r
-#define SD_DAT2__AMUX CYREG_PRT3_AMUX\r
-#define SD_DAT2__BIE CYREG_PRT3_BIE\r
-#define SD_DAT2__BIT_MASK CYREG_PRT3_BIT_MASK\r
-#define SD_DAT2__BYP CYREG_PRT3_BYP\r
-#define SD_DAT2__CTL CYREG_PRT3_CTL\r
-#define SD_DAT2__DM0 CYREG_PRT3_DM0\r
-#define SD_DAT2__DM1 CYREG_PRT3_DM1\r
-#define SD_DAT2__DM2 CYREG_PRT3_DM2\r
-#define SD_DAT2__DR CYREG_PRT3_DR\r
-#define SD_DAT2__INP_DIS CYREG_PRT3_INP_DIS\r
-#define SD_DAT2__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU3_BASE\r
-#define SD_DAT2__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG\r
-#define SD_DAT2__LCD_EN CYREG_PRT3_LCD_EN\r
-#define SD_DAT2__MASK 0x20u\r
-#define SD_DAT2__PORT 3u\r
-#define SD_DAT2__PRT CYREG_PRT3_PRT\r
-#define SD_DAT2__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL\r
-#define SD_DAT2__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN\r
-#define SD_DAT2__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0\r
-#define SD_DAT2__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1\r
-#define SD_DAT2__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0\r
-#define SD_DAT2__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1\r
-#define SD_DAT2__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT\r
-#define SD_DAT2__PS CYREG_PRT3_PS\r
-#define SD_DAT2__SHIFT 5u\r
-#define SD_DAT2__SLW CYREG_PRT3_SLW\r
-\r
-/* SD_Data_Clk */\r
-#define SD_Data_Clk__CFG0 CYREG_CLKDIST_DCFG0_CFG0\r
-#define SD_Data_Clk__CFG1 CYREG_CLKDIST_DCFG0_CFG1\r
-#define SD_Data_Clk__CFG2 CYREG_CLKDIST_DCFG0_CFG2\r
-#define SD_Data_Clk__CFG2_SRC_SEL_MASK 0x07u\r
-#define SD_Data_Clk__INDEX 0x00u\r
-#define SD_Data_Clk__PM_ACT_CFG CYREG_PM_ACT_CFG2\r
-#define SD_Data_Clk__PM_ACT_MSK 0x01u\r
-#define SD_Data_Clk__PM_STBY_CFG CYREG_PM_STBY_CFG2\r
-#define SD_Data_Clk__PM_STBY_MSK 0x01u\r
-\r
-/* SD_MISO */\r
-#define SD_MISO__0__INTTYPE CYREG_PICU3_INTTYPE1\r
-#define SD_MISO__0__MASK 0x02u\r
-#define SD_MISO__0__PC CYREG_PRT3_PC1\r
-#define SD_MISO__0__PORT 3u\r
-#define SD_MISO__0__SHIFT 1u\r
-#define SD_MISO__AG CYREG_PRT3_AG\r
-#define SD_MISO__AMUX CYREG_PRT3_AMUX\r
-#define SD_MISO__BIE CYREG_PRT3_BIE\r
-#define SD_MISO__BIT_MASK CYREG_PRT3_BIT_MASK\r
-#define SD_MISO__BYP CYREG_PRT3_BYP\r
-#define SD_MISO__CTL CYREG_PRT3_CTL\r
-#define SD_MISO__DM0 CYREG_PRT3_DM0\r
-#define SD_MISO__DM1 CYREG_PRT3_DM1\r
-#define SD_MISO__DM2 CYREG_PRT3_DM2\r
-#define SD_MISO__DR CYREG_PRT3_DR\r
-#define SD_MISO__INP_DIS CYREG_PRT3_INP_DIS\r
-#define SD_MISO__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU3_BASE\r
-#define SD_MISO__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG\r
-#define SD_MISO__LCD_EN CYREG_PRT3_LCD_EN\r
-#define SD_MISO__MASK 0x02u\r
-#define SD_MISO__PORT 3u\r
-#define SD_MISO__PRT CYREG_PRT3_PRT\r
-#define SD_MISO__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL\r
-#define SD_MISO__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN\r
-#define SD_MISO__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0\r
-#define SD_MISO__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1\r
-#define SD_MISO__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0\r
-#define SD_MISO__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1\r
-#define SD_MISO__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT\r
-#define SD_MISO__PS CYREG_PRT3_PS\r
-#define SD_MISO__SHIFT 1u\r
-#define SD_MISO__SLW CYREG_PRT3_SLW\r
-\r
-/* SD_MOSI */\r
-#define SD_MOSI__0__INTTYPE CYREG_PICU3_INTTYPE3\r
-#define SD_MOSI__0__MASK 0x08u\r
-#define SD_MOSI__0__PC CYREG_PRT3_PC3\r
-#define SD_MOSI__0__PORT 3u\r
-#define SD_MOSI__0__SHIFT 3u\r
-#define SD_MOSI__AG CYREG_PRT3_AG\r
-#define SD_MOSI__AMUX CYREG_PRT3_AMUX\r
-#define SD_MOSI__BIE CYREG_PRT3_BIE\r
-#define SD_MOSI__BIT_MASK CYREG_PRT3_BIT_MASK\r
-#define SD_MOSI__BYP CYREG_PRT3_BYP\r
-#define SD_MOSI__CTL CYREG_PRT3_CTL\r
-#define SD_MOSI__DM0 CYREG_PRT3_DM0\r
-#define SD_MOSI__DM1 CYREG_PRT3_DM1\r
-#define SD_MOSI__DM2 CYREG_PRT3_DM2\r
-#define SD_MOSI__DR CYREG_PRT3_DR\r
-#define SD_MOSI__INP_DIS CYREG_PRT3_INP_DIS\r
-#define SD_MOSI__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU3_BASE\r
-#define SD_MOSI__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG\r
-#define SD_MOSI__LCD_EN CYREG_PRT3_LCD_EN\r
-#define SD_MOSI__MASK 0x08u\r
-#define SD_MOSI__PORT 3u\r
-#define SD_MOSI__PRT CYREG_PRT3_PRT\r
-#define SD_MOSI__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL\r
-#define SD_MOSI__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN\r
-#define SD_MOSI__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0\r
-#define SD_MOSI__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1\r
-#define SD_MOSI__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0\r
-#define SD_MOSI__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1\r
-#define SD_MOSI__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT\r
-#define SD_MOSI__PS CYREG_PRT3_PS\r
-#define SD_MOSI__SHIFT 3u\r
-#define SD_MOSI__SLW CYREG_PRT3_SLW\r
-\r
-/* SD_RX_DMA */\r
-#define SD_RX_DMA__DRQ_CTL CYREG_IDMUX_DRQ_CTL0\r
-#define SD_RX_DMA__DRQ_NUMBER 2u\r
-#define SD_RX_DMA__NUMBEROF_TDS 0u\r
-#define SD_RX_DMA__PRIORITY 0u\r
-#define SD_RX_DMA__TERMIN_EN 0u\r
-#define SD_RX_DMA__TERMIN_SEL 0u\r
-#define SD_RX_DMA__TERMOUT0_EN 1u\r
-#define SD_RX_DMA__TERMOUT0_SEL 2u\r
-#define SD_RX_DMA__TERMOUT1_EN 0u\r
-#define SD_RX_DMA__TERMOUT1_SEL 0u\r
-#define SD_RX_DMA_COMPLETE__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
-#define SD_RX_DMA_COMPLETE__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
-#define SD_RX_DMA_COMPLETE__INTC_MASK 0x20u\r
-#define SD_RX_DMA_COMPLETE__INTC_NUMBER 5u\r
-#define SD_RX_DMA_COMPLETE__INTC_PRIOR_NUM 7u\r
-#define SD_RX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_5\r
-#define SD_RX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
-#define SD_RX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
-\r
-/* SD_SCK */\r
-#define SD_SCK__0__INTTYPE CYREG_PICU3_INTTYPE2\r
-#define SD_SCK__0__MASK 0x04u\r
-#define SD_SCK__0__PC CYREG_PRT3_PC2\r
-#define SD_SCK__0__PORT 3u\r
-#define SD_SCK__0__SHIFT 2u\r
-#define SD_SCK__AG CYREG_PRT3_AG\r
-#define SD_SCK__AMUX CYREG_PRT3_AMUX\r
-#define SD_SCK__BIE CYREG_PRT3_BIE\r
-#define SD_SCK__BIT_MASK CYREG_PRT3_BIT_MASK\r
-#define SD_SCK__BYP CYREG_PRT3_BYP\r
-#define SD_SCK__CTL CYREG_PRT3_CTL\r
-#define SD_SCK__DM0 CYREG_PRT3_DM0\r
-#define SD_SCK__DM1 CYREG_PRT3_DM1\r
-#define SD_SCK__DM2 CYREG_PRT3_DM2\r
-#define SD_SCK__DR CYREG_PRT3_DR\r
-#define SD_SCK__INP_DIS CYREG_PRT3_INP_DIS\r
-#define SD_SCK__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU3_BASE\r
-#define SD_SCK__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG\r
-#define SD_SCK__LCD_EN CYREG_PRT3_LCD_EN\r
-#define SD_SCK__MASK 0x04u\r
-#define SD_SCK__PORT 3u\r
-#define SD_SCK__PRT CYREG_PRT3_PRT\r
-#define SD_SCK__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL\r
-#define SD_SCK__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN\r
-#define SD_SCK__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0\r
-#define SD_SCK__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1\r
-#define SD_SCK__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0\r
-#define SD_SCK__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1\r
-#define SD_SCK__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT\r
-#define SD_SCK__PS CYREG_PRT3_PS\r
-#define SD_SCK__SHIFT 2u\r
-#define SD_SCK__SLW CYREG_PRT3_SLW\r
-\r
-/* SD_TX_DMA */\r
-#define SD_TX_DMA__DRQ_CTL CYREG_IDMUX_DRQ_CTL0\r
-#define SD_TX_DMA__DRQ_NUMBER 3u\r
-#define SD_TX_DMA__NUMBEROF_TDS 0u\r
-#define SD_TX_DMA__PRIORITY 1u\r
-#define SD_TX_DMA__TERMIN_EN 0u\r
-#define SD_TX_DMA__TERMIN_SEL 0u\r
-#define SD_TX_DMA__TERMOUT0_EN 1u\r
-#define SD_TX_DMA__TERMOUT0_SEL 3u\r
-#define SD_TX_DMA__TERMOUT1_EN 0u\r
-#define SD_TX_DMA__TERMOUT1_SEL 0u\r
-#define SD_TX_DMA_COMPLETE__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
-#define SD_TX_DMA_COMPLETE__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
-#define SD_TX_DMA_COMPLETE__INTC_MASK 0x40u\r
-#define SD_TX_DMA_COMPLETE__INTC_NUMBER 6u\r
-#define SD_TX_DMA_COMPLETE__INTC_PRIOR_NUM 7u\r
-#define SD_TX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_6\r
-#define SD_TX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
-#define SD_TX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
+/* SD_CS */\r
+#define SD_CS__0__INTTYPE CYREG_PICU3_INTTYPE4\r
+#define SD_CS__0__MASK 0x10u\r
+#define SD_CS__0__PC CYREG_PRT3_PC4\r
+#define SD_CS__0__PORT 3u\r
+#define SD_CS__0__SHIFT 4u\r
+#define SD_CS__AG CYREG_PRT3_AG\r
+#define SD_CS__AMUX CYREG_PRT3_AMUX\r
+#define SD_CS__BIE CYREG_PRT3_BIE\r
+#define SD_CS__BIT_MASK CYREG_PRT3_BIT_MASK\r
+#define SD_CS__BYP CYREG_PRT3_BYP\r
+#define SD_CS__CTL CYREG_PRT3_CTL\r
+#define SD_CS__DM0 CYREG_PRT3_DM0\r
+#define SD_CS__DM1 CYREG_PRT3_DM1\r
+#define SD_CS__DM2 CYREG_PRT3_DM2\r
+#define SD_CS__DR CYREG_PRT3_DR\r
+#define SD_CS__INP_DIS CYREG_PRT3_INP_DIS\r
+#define SD_CS__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU3_BASE\r
+#define SD_CS__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG\r
+#define SD_CS__LCD_EN CYREG_PRT3_LCD_EN\r
+#define SD_CS__MASK 0x10u\r
+#define SD_CS__PORT 3u\r
+#define SD_CS__PRT CYREG_PRT3_PRT\r
+#define SD_CS__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL\r
+#define SD_CS__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN\r
+#define SD_CS__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0\r
+#define SD_CS__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1\r
+#define SD_CS__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0\r
+#define SD_CS__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1\r
+#define SD_CS__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT\r
+#define SD_CS__PS CYREG_PRT3_PS\r
+#define SD_CS__SHIFT 4u\r
+#define SD_CS__SLW CYREG_PRT3_SLW\r
\r
/* USBFS */\r
#define USBFS_arb_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
#define USBFS_USB__USBIO_CR0 CYREG_USB_USBIO_CR0\r
#define USBFS_USB__USBIO_CR1 CYREG_USB_USBIO_CR1\r
\r
+/* SDCard */\r
+#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB04_05_ACTL\r
+#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB04_05_CTL\r
+#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB04_05_CTL\r
+#define SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB04_05_CTL\r
+#define SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B1_UDB04_05_CTL\r
+#define SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B1_UDB04_05_MSK\r
+#define SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B1_UDB04_05_MSK\r
+#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B1_UDB04_05_MSK\r
+#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB04_05_MSK\r
+#define SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B1_UDB04_ACTL\r
+#define SDCard_BSPIM_BitCounter__CONTROL_REG CYREG_B1_UDB04_CTL\r
+#define SDCard_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B1_UDB04_ST_CTL\r
+#define SDCard_BSPIM_BitCounter__COUNT_REG CYREG_B1_UDB04_CTL\r
+#define SDCard_BSPIM_BitCounter__COUNT_ST_REG CYREG_B1_UDB04_ST_CTL\r
+#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL\r
+#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL\r
+#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B1_UDB04_MSK\r
+#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB04_05_ACTL\r
+#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B1_UDB04_05_ST\r
+#define SDCard_BSPIM_BitCounter_ST__MASK_REG CYREG_B1_UDB04_MSK\r
+#define SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL\r
+#define SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL\r
+#define SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B1_UDB04_ACTL\r
+#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B1_UDB04_ST_CTL\r
+#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B1_UDB04_ST_CTL\r
+#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B1_UDB04_ST\r
+#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB08_09_ACTL\r
+#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B1_UDB08_09_ST\r
+#define SDCard_BSPIM_RxStsReg__4__MASK 0x10u\r
+#define SDCard_BSPIM_RxStsReg__4__POS 4\r
+#define SDCard_BSPIM_RxStsReg__5__MASK 0x20u\r
+#define SDCard_BSPIM_RxStsReg__5__POS 5\r
+#define SDCard_BSPIM_RxStsReg__6__MASK 0x40u\r
+#define SDCard_BSPIM_RxStsReg__6__POS 6\r
+#define SDCard_BSPIM_RxStsReg__MASK 0x70u\r
+#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B1_UDB08_MSK\r
+#define SDCard_BSPIM_RxStsReg__MASK_ST_AUX_CTL_REG CYREG_B1_UDB08_MSK_ACTL\r
+#define SDCard_BSPIM_RxStsReg__PER_ST_AUX_CTL_REG CYREG_B1_UDB08_MSK_ACTL\r
+#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB08_ACTL\r
+#define SDCard_BSPIM_RxStsReg__STATUS_CNT_REG CYREG_B1_UDB08_ST_CTL\r
+#define SDCard_BSPIM_RxStsReg__STATUS_CONTROL_REG CYREG_B1_UDB08_ST_CTL\r
+#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B1_UDB08_ST\r
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B1_UDB04_05_A0\r
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B1_UDB04_05_A1\r
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG CYREG_B1_UDB04_05_D0\r
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG CYREG_B1_UDB04_05_D1\r
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG CYREG_B1_UDB04_05_ACTL\r
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG CYREG_B1_UDB04_05_F0\r
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG CYREG_B1_UDB04_05_F1\r
+#define SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG CYREG_B1_UDB04_A0_A1\r
+#define SDCard_BSPIM_sR8_Dp_u0__A0_REG CYREG_B1_UDB04_A0\r
+#define SDCard_BSPIM_sR8_Dp_u0__A1_REG CYREG_B1_UDB04_A1\r
+#define SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG CYREG_B1_UDB04_D0_D1\r
+#define SDCard_BSPIM_sR8_Dp_u0__D0_REG CYREG_B1_UDB04_D0\r
+#define SDCard_BSPIM_sR8_Dp_u0__D1_REG CYREG_B1_UDB04_D1\r
+#define SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG CYREG_B1_UDB04_ACTL\r
+#define SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG CYREG_B1_UDB04_F0_F1\r
+#define SDCard_BSPIM_sR8_Dp_u0__F0_REG CYREG_B1_UDB04_F0\r
+#define SDCard_BSPIM_sR8_Dp_u0__F1_REG CYREG_B1_UDB04_F1\r
+#define SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL\r
+#define SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL\r
+#define SDCard_BSPIM_TxStsReg__0__MASK 0x01u\r
+#define SDCard_BSPIM_TxStsReg__0__POS 0\r
+#define SDCard_BSPIM_TxStsReg__1__MASK 0x02u\r
+#define SDCard_BSPIM_TxStsReg__1__POS 1\r
+#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB07_08_ACTL\r
+#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B1_UDB07_08_ST\r
+#define SDCard_BSPIM_TxStsReg__2__MASK 0x04u\r
+#define SDCard_BSPIM_TxStsReg__2__POS 2\r
+#define SDCard_BSPIM_TxStsReg__3__MASK 0x08u\r
+#define SDCard_BSPIM_TxStsReg__3__POS 3\r
+#define SDCard_BSPIM_TxStsReg__4__MASK 0x10u\r
+#define SDCard_BSPIM_TxStsReg__4__POS 4\r
+#define SDCard_BSPIM_TxStsReg__MASK 0x1Fu\r
+#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B1_UDB07_MSK\r
+#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB07_ACTL\r
+#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B1_UDB07_ST\r
+\r
+/* SD_SCK */\r
+#define SD_SCK__0__INTTYPE CYREG_PICU3_INTTYPE2\r
+#define SD_SCK__0__MASK 0x04u\r
+#define SD_SCK__0__PC CYREG_PRT3_PC2\r
+#define SD_SCK__0__PORT 3u\r
+#define SD_SCK__0__SHIFT 2u\r
+#define SD_SCK__AG CYREG_PRT3_AG\r
+#define SD_SCK__AMUX CYREG_PRT3_AMUX\r
+#define SD_SCK__BIE CYREG_PRT3_BIE\r
+#define SD_SCK__BIT_MASK CYREG_PRT3_BIT_MASK\r
+#define SD_SCK__BYP CYREG_PRT3_BYP\r
+#define SD_SCK__CTL CYREG_PRT3_CTL\r
+#define SD_SCK__DM0 CYREG_PRT3_DM0\r
+#define SD_SCK__DM1 CYREG_PRT3_DM1\r
+#define SD_SCK__DM2 CYREG_PRT3_DM2\r
+#define SD_SCK__DR CYREG_PRT3_DR\r
+#define SD_SCK__INP_DIS CYREG_PRT3_INP_DIS\r
+#define SD_SCK__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU3_BASE\r
+#define SD_SCK__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG\r
+#define SD_SCK__LCD_EN CYREG_PRT3_LCD_EN\r
+#define SD_SCK__MASK 0x04u\r
+#define SD_SCK__PORT 3u\r
+#define SD_SCK__PRT CYREG_PRT3_PRT\r
+#define SD_SCK__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL\r
+#define SD_SCK__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN\r
+#define SD_SCK__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0\r
+#define SD_SCK__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1\r
+#define SD_SCK__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0\r
+#define SD_SCK__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1\r
+#define SD_SCK__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT\r
+#define SD_SCK__PS CYREG_PRT3_PS\r
+#define SD_SCK__SHIFT 2u\r
+#define SD_SCK__SLW CYREG_PRT3_SLW\r
+\r
+/* SCSI_In */\r
+#define SCSI_In__0__AG CYREG_PRT2_AG\r
+#define SCSI_In__0__AMUX CYREG_PRT2_AMUX\r
+#define SCSI_In__0__BIE CYREG_PRT2_BIE\r
+#define SCSI_In__0__BIT_MASK CYREG_PRT2_BIT_MASK\r
+#define SCSI_In__0__BYP CYREG_PRT2_BYP\r
+#define SCSI_In__0__CTL CYREG_PRT2_CTL\r
+#define SCSI_In__0__DM0 CYREG_PRT2_DM0\r
+#define SCSI_In__0__DM1 CYREG_PRT2_DM1\r
+#define SCSI_In__0__DM2 CYREG_PRT2_DM2\r
+#define SCSI_In__0__DR CYREG_PRT2_DR\r
+#define SCSI_In__0__INP_DIS CYREG_PRT2_INP_DIS\r
+#define SCSI_In__0__INTTYPE CYREG_PICU2_INTTYPE0\r
+#define SCSI_In__0__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG\r
+#define SCSI_In__0__LCD_EN CYREG_PRT2_LCD_EN\r
+#define SCSI_In__0__MASK 0x01u\r
+#define SCSI_In__0__PC CYREG_PRT2_PC0\r
+#define SCSI_In__0__PORT 2u\r
+#define SCSI_In__0__PRT CYREG_PRT2_PRT\r
+#define SCSI_In__0__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL\r
+#define SCSI_In__0__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN\r
+#define SCSI_In__0__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0\r
+#define SCSI_In__0__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1\r
+#define SCSI_In__0__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0\r
+#define SCSI_In__0__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1\r
+#define SCSI_In__0__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT\r
+#define SCSI_In__0__PS CYREG_PRT2_PS\r
+#define SCSI_In__0__SHIFT 0u\r
+#define SCSI_In__0__SLW CYREG_PRT2_SLW\r
+#define SCSI_In__1__AG CYREG_PRT6_AG\r
+#define SCSI_In__1__AMUX CYREG_PRT6_AMUX\r
+#define SCSI_In__1__BIE CYREG_PRT6_BIE\r
+#define SCSI_In__1__BIT_MASK CYREG_PRT6_BIT_MASK\r
+#define SCSI_In__1__BYP CYREG_PRT6_BYP\r
+#define SCSI_In__1__CTL CYREG_PRT6_CTL\r
+#define SCSI_In__1__DM0 CYREG_PRT6_DM0\r
+#define SCSI_In__1__DM1 CYREG_PRT6_DM1\r
+#define SCSI_In__1__DM2 CYREG_PRT6_DM2\r
+#define SCSI_In__1__DR CYREG_PRT6_DR\r
+#define SCSI_In__1__INP_DIS CYREG_PRT6_INP_DIS\r
+#define SCSI_In__1__INTTYPE CYREG_PICU6_INTTYPE7\r
+#define SCSI_In__1__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
+#define SCSI_In__1__LCD_EN CYREG_PRT6_LCD_EN\r
+#define SCSI_In__1__MASK 0x80u\r
+#define SCSI_In__1__PC CYREG_PRT6_PC7\r
+#define SCSI_In__1__PORT 6u\r
+#define SCSI_In__1__PRT CYREG_PRT6_PRT\r
+#define SCSI_In__1__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
+#define SCSI_In__1__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
+#define SCSI_In__1__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
+#define SCSI_In__1__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
+#define SCSI_In__1__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
+#define SCSI_In__1__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
+#define SCSI_In__1__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
+#define SCSI_In__1__PS CYREG_PRT6_PS\r
+#define SCSI_In__1__SHIFT 7u\r
+#define SCSI_In__1__SLW CYREG_PRT6_SLW\r
+#define SCSI_In__2__AG CYREG_PRT5_AG\r
+#define SCSI_In__2__AMUX CYREG_PRT5_AMUX\r
+#define SCSI_In__2__BIE CYREG_PRT5_BIE\r
+#define SCSI_In__2__BIT_MASK CYREG_PRT5_BIT_MASK\r
+#define SCSI_In__2__BYP CYREG_PRT5_BYP\r
+#define SCSI_In__2__CTL CYREG_PRT5_CTL\r
+#define SCSI_In__2__DM0 CYREG_PRT5_DM0\r
+#define SCSI_In__2__DM1 CYREG_PRT5_DM1\r
+#define SCSI_In__2__DM2 CYREG_PRT5_DM2\r
+#define SCSI_In__2__DR CYREG_PRT5_DR\r
+#define SCSI_In__2__INP_DIS CYREG_PRT5_INP_DIS\r
+#define SCSI_In__2__INTTYPE CYREG_PICU5_INTTYPE1\r
+#define SCSI_In__2__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG\r
+#define SCSI_In__2__LCD_EN CYREG_PRT5_LCD_EN\r
+#define SCSI_In__2__MASK 0x02u\r
+#define SCSI_In__2__PC CYREG_PRT5_PC1\r
+#define SCSI_In__2__PORT 5u\r
+#define SCSI_In__2__PRT CYREG_PRT5_PRT\r
+#define SCSI_In__2__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL\r
+#define SCSI_In__2__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN\r
+#define SCSI_In__2__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0\r
+#define SCSI_In__2__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1\r
+#define SCSI_In__2__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0\r
+#define SCSI_In__2__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1\r
+#define SCSI_In__2__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT\r
+#define SCSI_In__2__PS CYREG_PRT5_PS\r
+#define SCSI_In__2__SHIFT 1u\r
+#define SCSI_In__2__SLW CYREG_PRT5_SLW\r
+#define SCSI_In__3__AG CYREG_PRT5_AG\r
+#define SCSI_In__3__AMUX CYREG_PRT5_AMUX\r
+#define SCSI_In__3__BIE CYREG_PRT5_BIE\r
+#define SCSI_In__3__BIT_MASK CYREG_PRT5_BIT_MASK\r
+#define SCSI_In__3__BYP CYREG_PRT5_BYP\r
+#define SCSI_In__3__CTL CYREG_PRT5_CTL\r
+#define SCSI_In__3__DM0 CYREG_PRT5_DM0\r
+#define SCSI_In__3__DM1 CYREG_PRT5_DM1\r
+#define SCSI_In__3__DM2 CYREG_PRT5_DM2\r
+#define SCSI_In__3__DR CYREG_PRT5_DR\r
+#define SCSI_In__3__INP_DIS CYREG_PRT5_INP_DIS\r
+#define SCSI_In__3__INTTYPE CYREG_PICU5_INTTYPE2\r
+#define SCSI_In__3__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG\r
+#define SCSI_In__3__LCD_EN CYREG_PRT5_LCD_EN\r
+#define SCSI_In__3__MASK 0x04u\r
+#define SCSI_In__3__PC CYREG_PRT5_PC2\r
+#define SCSI_In__3__PORT 5u\r
+#define SCSI_In__3__PRT CYREG_PRT5_PRT\r
+#define SCSI_In__3__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL\r
+#define SCSI_In__3__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN\r
+#define SCSI_In__3__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0\r
+#define SCSI_In__3__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1\r
+#define SCSI_In__3__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0\r
+#define SCSI_In__3__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1\r
+#define SCSI_In__3__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT\r
+#define SCSI_In__3__PS CYREG_PRT5_PS\r
+#define SCSI_In__3__SHIFT 2u\r
+#define SCSI_In__3__SLW CYREG_PRT5_SLW\r
+#define SCSI_In__4__AG CYREG_PRT5_AG\r
+#define SCSI_In__4__AMUX CYREG_PRT5_AMUX\r
+#define SCSI_In__4__BIE CYREG_PRT5_BIE\r
+#define SCSI_In__4__BIT_MASK CYREG_PRT5_BIT_MASK\r
+#define SCSI_In__4__BYP CYREG_PRT5_BYP\r
+#define SCSI_In__4__CTL CYREG_PRT5_CTL\r
+#define SCSI_In__4__DM0 CYREG_PRT5_DM0\r
+#define SCSI_In__4__DM1 CYREG_PRT5_DM1\r
+#define SCSI_In__4__DM2 CYREG_PRT5_DM2\r
+#define SCSI_In__4__DR CYREG_PRT5_DR\r
+#define SCSI_In__4__INP_DIS CYREG_PRT5_INP_DIS\r
+#define SCSI_In__4__INTTYPE CYREG_PICU5_INTTYPE3\r
+#define SCSI_In__4__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG\r
+#define SCSI_In__4__LCD_EN CYREG_PRT5_LCD_EN\r
+#define SCSI_In__4__MASK 0x08u\r
+#define SCSI_In__4__PC CYREG_PRT5_PC3\r
+#define SCSI_In__4__PORT 5u\r
+#define SCSI_In__4__PRT CYREG_PRT5_PRT\r
+#define SCSI_In__4__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL\r
+#define SCSI_In__4__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN\r
+#define SCSI_In__4__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0\r
+#define SCSI_In__4__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1\r
+#define SCSI_In__4__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0\r
+#define SCSI_In__4__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1\r
+#define SCSI_In__4__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT\r
+#define SCSI_In__4__PS CYREG_PRT5_PS\r
+#define SCSI_In__4__SHIFT 3u\r
+#define SCSI_In__4__SLW CYREG_PRT5_SLW\r
+#define SCSI_In__CD__AG CYREG_PRT5_AG\r
+#define SCSI_In__CD__AMUX CYREG_PRT5_AMUX\r
+#define SCSI_In__CD__BIE CYREG_PRT5_BIE\r
+#define SCSI_In__CD__BIT_MASK CYREG_PRT5_BIT_MASK\r
+#define SCSI_In__CD__BYP CYREG_PRT5_BYP\r
+#define SCSI_In__CD__CTL CYREG_PRT5_CTL\r
+#define SCSI_In__CD__DM0 CYREG_PRT5_DM0\r
+#define SCSI_In__CD__DM1 CYREG_PRT5_DM1\r
+#define SCSI_In__CD__DM2 CYREG_PRT5_DM2\r
+#define SCSI_In__CD__DR CYREG_PRT5_DR\r
+#define SCSI_In__CD__INP_DIS CYREG_PRT5_INP_DIS\r
+#define SCSI_In__CD__INTTYPE CYREG_PICU5_INTTYPE1\r
+#define SCSI_In__CD__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG\r
+#define SCSI_In__CD__LCD_EN CYREG_PRT5_LCD_EN\r
+#define SCSI_In__CD__MASK 0x02u\r
+#define SCSI_In__CD__PC CYREG_PRT5_PC1\r
+#define SCSI_In__CD__PORT 5u\r
+#define SCSI_In__CD__PRT CYREG_PRT5_PRT\r
+#define SCSI_In__CD__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL\r
+#define SCSI_In__CD__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN\r
+#define SCSI_In__CD__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0\r
+#define SCSI_In__CD__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1\r
+#define SCSI_In__CD__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0\r
+#define SCSI_In__CD__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1\r
+#define SCSI_In__CD__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT\r
+#define SCSI_In__CD__PS CYREG_PRT5_PS\r
+#define SCSI_In__CD__SHIFT 1u\r
+#define SCSI_In__CD__SLW CYREG_PRT5_SLW\r
+#define SCSI_In__DBP__AG CYREG_PRT2_AG\r
+#define SCSI_In__DBP__AMUX CYREG_PRT2_AMUX\r
+#define SCSI_In__DBP__BIE CYREG_PRT2_BIE\r
+#define SCSI_In__DBP__BIT_MASK CYREG_PRT2_BIT_MASK\r
+#define SCSI_In__DBP__BYP CYREG_PRT2_BYP\r
+#define SCSI_In__DBP__CTL CYREG_PRT2_CTL\r
+#define SCSI_In__DBP__DM0 CYREG_PRT2_DM0\r
+#define SCSI_In__DBP__DM1 CYREG_PRT2_DM1\r
+#define SCSI_In__DBP__DM2 CYREG_PRT2_DM2\r
+#define SCSI_In__DBP__DR CYREG_PRT2_DR\r
+#define SCSI_In__DBP__INP_DIS CYREG_PRT2_INP_DIS\r
+#define SCSI_In__DBP__INTTYPE CYREG_PICU2_INTTYPE0\r
+#define SCSI_In__DBP__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG\r
+#define SCSI_In__DBP__LCD_EN CYREG_PRT2_LCD_EN\r
+#define SCSI_In__DBP__MASK 0x01u\r
+#define SCSI_In__DBP__PC CYREG_PRT2_PC0\r
+#define SCSI_In__DBP__PORT 2u\r
+#define SCSI_In__DBP__PRT CYREG_PRT2_PRT\r
+#define SCSI_In__DBP__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL\r
+#define SCSI_In__DBP__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN\r
+#define SCSI_In__DBP__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0\r
+#define SCSI_In__DBP__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1\r
+#define SCSI_In__DBP__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0\r
+#define SCSI_In__DBP__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1\r
+#define SCSI_In__DBP__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT\r
+#define SCSI_In__DBP__PS CYREG_PRT2_PS\r
+#define SCSI_In__DBP__SHIFT 0u\r
+#define SCSI_In__DBP__SLW CYREG_PRT2_SLW\r
+#define SCSI_In__IO__AG CYREG_PRT5_AG\r
+#define SCSI_In__IO__AMUX CYREG_PRT5_AMUX\r
+#define SCSI_In__IO__BIE CYREG_PRT5_BIE\r
+#define SCSI_In__IO__BIT_MASK CYREG_PRT5_BIT_MASK\r
+#define SCSI_In__IO__BYP CYREG_PRT5_BYP\r
+#define SCSI_In__IO__CTL CYREG_PRT5_CTL\r
+#define SCSI_In__IO__DM0 CYREG_PRT5_DM0\r
+#define SCSI_In__IO__DM1 CYREG_PRT5_DM1\r
+#define SCSI_In__IO__DM2 CYREG_PRT5_DM2\r
+#define SCSI_In__IO__DR CYREG_PRT5_DR\r
+#define SCSI_In__IO__INP_DIS CYREG_PRT5_INP_DIS\r
+#define SCSI_In__IO__INTTYPE CYREG_PICU5_INTTYPE3\r
+#define SCSI_In__IO__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG\r
+#define SCSI_In__IO__LCD_EN CYREG_PRT5_LCD_EN\r
+#define SCSI_In__IO__MASK 0x08u\r
+#define SCSI_In__IO__PC CYREG_PRT5_PC3\r
+#define SCSI_In__IO__PORT 5u\r
+#define SCSI_In__IO__PRT CYREG_PRT5_PRT\r
+#define SCSI_In__IO__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL\r
+#define SCSI_In__IO__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN\r
+#define SCSI_In__IO__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0\r
+#define SCSI_In__IO__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1\r
+#define SCSI_In__IO__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0\r
+#define SCSI_In__IO__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1\r
+#define SCSI_In__IO__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT\r
+#define SCSI_In__IO__PS CYREG_PRT5_PS\r
+#define SCSI_In__IO__SHIFT 3u\r
+#define SCSI_In__IO__SLW CYREG_PRT5_SLW\r
+#define SCSI_In__MSG__AG CYREG_PRT6_AG\r
+#define SCSI_In__MSG__AMUX CYREG_PRT6_AMUX\r
+#define SCSI_In__MSG__BIE CYREG_PRT6_BIE\r
+#define SCSI_In__MSG__BIT_MASK CYREG_PRT6_BIT_MASK\r
+#define SCSI_In__MSG__BYP CYREG_PRT6_BYP\r
+#define SCSI_In__MSG__CTL CYREG_PRT6_CTL\r
+#define SCSI_In__MSG__DM0 CYREG_PRT6_DM0\r
+#define SCSI_In__MSG__DM1 CYREG_PRT6_DM1\r
+#define SCSI_In__MSG__DM2 CYREG_PRT6_DM2\r
+#define SCSI_In__MSG__DR CYREG_PRT6_DR\r
+#define SCSI_In__MSG__INP_DIS CYREG_PRT6_INP_DIS\r
+#define SCSI_In__MSG__INTTYPE CYREG_PICU6_INTTYPE7\r
+#define SCSI_In__MSG__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
+#define SCSI_In__MSG__LCD_EN CYREG_PRT6_LCD_EN\r
+#define SCSI_In__MSG__MASK 0x80u\r
+#define SCSI_In__MSG__PC CYREG_PRT6_PC7\r
+#define SCSI_In__MSG__PORT 6u\r
+#define SCSI_In__MSG__PRT CYREG_PRT6_PRT\r
+#define SCSI_In__MSG__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
+#define SCSI_In__MSG__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
+#define SCSI_In__MSG__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
+#define SCSI_In__MSG__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
+#define SCSI_In__MSG__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
+#define SCSI_In__MSG__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
+#define SCSI_In__MSG__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
+#define SCSI_In__MSG__PS CYREG_PRT6_PS\r
+#define SCSI_In__MSG__SHIFT 7u\r
+#define SCSI_In__MSG__SLW CYREG_PRT6_SLW\r
+#define SCSI_In__REQ__AG CYREG_PRT5_AG\r
+#define SCSI_In__REQ__AMUX CYREG_PRT5_AMUX\r
+#define SCSI_In__REQ__BIE CYREG_PRT5_BIE\r
+#define SCSI_In__REQ__BIT_MASK CYREG_PRT5_BIT_MASK\r
+#define SCSI_In__REQ__BYP CYREG_PRT5_BYP\r
+#define SCSI_In__REQ__CTL CYREG_PRT5_CTL\r
+#define SCSI_In__REQ__DM0 CYREG_PRT5_DM0\r
+#define SCSI_In__REQ__DM1 CYREG_PRT5_DM1\r
+#define SCSI_In__REQ__DM2 CYREG_PRT5_DM2\r
+#define SCSI_In__REQ__DR CYREG_PRT5_DR\r
+#define SCSI_In__REQ__INP_DIS CYREG_PRT5_INP_DIS\r
+#define SCSI_In__REQ__INTTYPE CYREG_PICU5_INTTYPE2\r
+#define SCSI_In__REQ__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG\r
+#define SCSI_In__REQ__LCD_EN CYREG_PRT5_LCD_EN\r
+#define SCSI_In__REQ__MASK 0x04u\r
+#define SCSI_In__REQ__PC CYREG_PRT5_PC2\r
+#define SCSI_In__REQ__PORT 5u\r
+#define SCSI_In__REQ__PRT CYREG_PRT5_PRT\r
+#define SCSI_In__REQ__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL\r
+#define SCSI_In__REQ__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN\r
+#define SCSI_In__REQ__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0\r
+#define SCSI_In__REQ__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1\r
+#define SCSI_In__REQ__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0\r
+#define SCSI_In__REQ__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1\r
+#define SCSI_In__REQ__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT\r
+#define SCSI_In__REQ__PS CYREG_PRT5_PS\r
+#define SCSI_In__REQ__SHIFT 2u\r
+#define SCSI_In__REQ__SLW CYREG_PRT5_SLW\r
+#define SCSI_In_DBx__0__AG CYREG_PRT12_AG\r
+#define SCSI_In_DBx__0__BIE CYREG_PRT12_BIE\r
+#define SCSI_In_DBx__0__BIT_MASK CYREG_PRT12_BIT_MASK\r
+#define SCSI_In_DBx__0__BYP CYREG_PRT12_BYP\r
+#define SCSI_In_DBx__0__DM0 CYREG_PRT12_DM0\r
+#define SCSI_In_DBx__0__DM1 CYREG_PRT12_DM1\r
+#define SCSI_In_DBx__0__DM2 CYREG_PRT12_DM2\r
+#define SCSI_In_DBx__0__DR CYREG_PRT12_DR\r
+#define SCSI_In_DBx__0__INP_DIS CYREG_PRT12_INP_DIS\r
+#define SCSI_In_DBx__0__INTTYPE CYREG_PICU12_INTTYPE4\r
+#define SCSI_In_DBx__0__MASK 0x10u\r
+#define SCSI_In_DBx__0__PC CYREG_PRT12_PC4\r
+#define SCSI_In_DBx__0__PORT 12u\r
+#define SCSI_In_DBx__0__PRT CYREG_PRT12_PRT\r
+#define SCSI_In_DBx__0__PRTDSI__DBL_SYNC_IN CYREG_PRT12_DBL_SYNC_IN\r
+#define SCSI_In_DBx__0__PRTDSI__OE_SEL0 CYREG_PRT12_OE_SEL0\r
+#define SCSI_In_DBx__0__PRTDSI__OE_SEL1 CYREG_PRT12_OE_SEL1\r
+#define SCSI_In_DBx__0__PRTDSI__OUT_SEL0 CYREG_PRT12_OUT_SEL0\r
+#define SCSI_In_DBx__0__PRTDSI__OUT_SEL1 CYREG_PRT12_OUT_SEL1\r
+#define SCSI_In_DBx__0__PRTDSI__SYNC_OUT CYREG_PRT12_SYNC_OUT\r
+#define SCSI_In_DBx__0__PS CYREG_PRT12_PS\r
+#define SCSI_In_DBx__0__SHIFT 4u\r
+#define SCSI_In_DBx__0__SIO_CFG CYREG_PRT12_SIO_CFG\r
+#define SCSI_In_DBx__0__SIO_DIFF CYREG_PRT12_SIO_DIFF\r
+#define SCSI_In_DBx__0__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN\r
+#define SCSI_In_DBx__0__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ\r
+#define SCSI_In_DBx__0__SLW CYREG_PRT12_SLW\r
+#define SCSI_In_DBx__1__AG CYREG_PRT2_AG\r
+#define SCSI_In_DBx__1__AMUX CYREG_PRT2_AMUX\r
+#define SCSI_In_DBx__1__BIE CYREG_PRT2_BIE\r
+#define SCSI_In_DBx__1__BIT_MASK CYREG_PRT2_BIT_MASK\r
+#define SCSI_In_DBx__1__BYP CYREG_PRT2_BYP\r
+#define SCSI_In_DBx__1__CTL CYREG_PRT2_CTL\r
+#define SCSI_In_DBx__1__DM0 CYREG_PRT2_DM0\r
+#define SCSI_In_DBx__1__DM1 CYREG_PRT2_DM1\r
+#define SCSI_In_DBx__1__DM2 CYREG_PRT2_DM2\r
+#define SCSI_In_DBx__1__DR CYREG_PRT2_DR\r
+#define SCSI_In_DBx__1__INP_DIS CYREG_PRT2_INP_DIS\r
+#define SCSI_In_DBx__1__INTTYPE CYREG_PICU2_INTTYPE7\r
+#define SCSI_In_DBx__1__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG\r
+#define SCSI_In_DBx__1__LCD_EN CYREG_PRT2_LCD_EN\r
+#define SCSI_In_DBx__1__MASK 0x80u\r
+#define SCSI_In_DBx__1__PC CYREG_PRT2_PC7\r
+#define SCSI_In_DBx__1__PORT 2u\r
+#define SCSI_In_DBx__1__PRT CYREG_PRT2_PRT\r
+#define SCSI_In_DBx__1__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL\r
+#define SCSI_In_DBx__1__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN\r
+#define SCSI_In_DBx__1__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0\r
+#define SCSI_In_DBx__1__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1\r
+#define SCSI_In_DBx__1__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0\r
+#define SCSI_In_DBx__1__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1\r
+#define SCSI_In_DBx__1__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT\r
+#define SCSI_In_DBx__1__PS CYREG_PRT2_PS\r
+#define SCSI_In_DBx__1__SHIFT 7u\r
+#define SCSI_In_DBx__1__SLW CYREG_PRT2_SLW\r
+#define SCSI_In_DBx__2__AG CYREG_PRT2_AG\r
+#define SCSI_In_DBx__2__AMUX CYREG_PRT2_AMUX\r
+#define SCSI_In_DBx__2__BIE CYREG_PRT2_BIE\r
+#define SCSI_In_DBx__2__BIT_MASK CYREG_PRT2_BIT_MASK\r
+#define SCSI_In_DBx__2__BYP CYREG_PRT2_BYP\r
+#define SCSI_In_DBx__2__CTL CYREG_PRT2_CTL\r
+#define SCSI_In_DBx__2__DM0 CYREG_PRT2_DM0\r
+#define SCSI_In_DBx__2__DM1 CYREG_PRT2_DM1\r
+#define SCSI_In_DBx__2__DM2 CYREG_PRT2_DM2\r
+#define SCSI_In_DBx__2__DR CYREG_PRT2_DR\r
+#define SCSI_In_DBx__2__INP_DIS CYREG_PRT2_INP_DIS\r
+#define SCSI_In_DBx__2__INTTYPE CYREG_PICU2_INTTYPE6\r
+#define SCSI_In_DBx__2__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG\r
+#define SCSI_In_DBx__2__LCD_EN CYREG_PRT2_LCD_EN\r
+#define SCSI_In_DBx__2__MASK 0x40u\r
+#define SCSI_In_DBx__2__PC CYREG_PRT2_PC6\r
+#define SCSI_In_DBx__2__PORT 2u\r
+#define SCSI_In_DBx__2__PRT CYREG_PRT2_PRT\r
+#define SCSI_In_DBx__2__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL\r
+#define SCSI_In_DBx__2__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN\r
+#define SCSI_In_DBx__2__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0\r
+#define SCSI_In_DBx__2__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1\r
+#define SCSI_In_DBx__2__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0\r
+#define SCSI_In_DBx__2__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1\r
+#define SCSI_In_DBx__2__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT\r
+#define SCSI_In_DBx__2__PS CYREG_PRT2_PS\r
+#define SCSI_In_DBx__2__SHIFT 6u\r
+#define SCSI_In_DBx__2__SLW CYREG_PRT2_SLW\r
+#define SCSI_In_DBx__3__AG CYREG_PRT2_AG\r
+#define SCSI_In_DBx__3__AMUX CYREG_PRT2_AMUX\r
+#define SCSI_In_DBx__3__BIE CYREG_PRT2_BIE\r
+#define SCSI_In_DBx__3__BIT_MASK CYREG_PRT2_BIT_MASK\r
+#define SCSI_In_DBx__3__BYP CYREG_PRT2_BYP\r
+#define SCSI_In_DBx__3__CTL CYREG_PRT2_CTL\r
+#define SCSI_In_DBx__3__DM0 CYREG_PRT2_DM0\r
+#define SCSI_In_DBx__3__DM1 CYREG_PRT2_DM1\r
+#define SCSI_In_DBx__3__DM2 CYREG_PRT2_DM2\r
+#define SCSI_In_DBx__3__DR CYREG_PRT2_DR\r
+#define SCSI_In_DBx__3__INP_DIS CYREG_PRT2_INP_DIS\r
+#define SCSI_In_DBx__3__INTTYPE CYREG_PICU2_INTTYPE5\r
+#define SCSI_In_DBx__3__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG\r
+#define SCSI_In_DBx__3__LCD_EN CYREG_PRT2_LCD_EN\r
+#define SCSI_In_DBx__3__MASK 0x20u\r
+#define SCSI_In_DBx__3__PC CYREG_PRT2_PC5\r
+#define SCSI_In_DBx__3__PORT 2u\r
+#define SCSI_In_DBx__3__PRT CYREG_PRT2_PRT\r
+#define SCSI_In_DBx__3__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL\r
+#define SCSI_In_DBx__3__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN\r
+#define SCSI_In_DBx__3__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0\r
+#define SCSI_In_DBx__3__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1\r
+#define SCSI_In_DBx__3__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0\r
+#define SCSI_In_DBx__3__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1\r
+#define SCSI_In_DBx__3__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT\r
+#define SCSI_In_DBx__3__PS CYREG_PRT2_PS\r
+#define SCSI_In_DBx__3__SHIFT 5u\r
+#define SCSI_In_DBx__3__SLW CYREG_PRT2_SLW\r
+#define SCSI_In_DBx__4__AG CYREG_PRT2_AG\r
+#define SCSI_In_DBx__4__AMUX CYREG_PRT2_AMUX\r
+#define SCSI_In_DBx__4__BIE CYREG_PRT2_BIE\r
+#define SCSI_In_DBx__4__BIT_MASK CYREG_PRT2_BIT_MASK\r
+#define SCSI_In_DBx__4__BYP CYREG_PRT2_BYP\r
+#define SCSI_In_DBx__4__CTL CYREG_PRT2_CTL\r
+#define SCSI_In_DBx__4__DM0 CYREG_PRT2_DM0\r
+#define SCSI_In_DBx__4__DM1 CYREG_PRT2_DM1\r
+#define SCSI_In_DBx__4__DM2 CYREG_PRT2_DM2\r
+#define SCSI_In_DBx__4__DR CYREG_PRT2_DR\r
+#define SCSI_In_DBx__4__INP_DIS CYREG_PRT2_INP_DIS\r
+#define SCSI_In_DBx__4__INTTYPE CYREG_PICU2_INTTYPE4\r
+#define SCSI_In_DBx__4__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG\r
+#define SCSI_In_DBx__4__LCD_EN CYREG_PRT2_LCD_EN\r
+#define SCSI_In_DBx__4__MASK 0x10u\r
+#define SCSI_In_DBx__4__PC CYREG_PRT2_PC4\r
+#define SCSI_In_DBx__4__PORT 2u\r
+#define SCSI_In_DBx__4__PRT CYREG_PRT2_PRT\r
+#define SCSI_In_DBx__4__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL\r
+#define SCSI_In_DBx__4__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN\r
+#define SCSI_In_DBx__4__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0\r
+#define SCSI_In_DBx__4__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1\r
+#define SCSI_In_DBx__4__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0\r
+#define SCSI_In_DBx__4__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1\r
+#define SCSI_In_DBx__4__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT\r
+#define SCSI_In_DBx__4__PS CYREG_PRT2_PS\r
+#define SCSI_In_DBx__4__SHIFT 4u\r
+#define SCSI_In_DBx__4__SLW CYREG_PRT2_SLW\r
+#define SCSI_In_DBx__5__AG CYREG_PRT2_AG\r
+#define SCSI_In_DBx__5__AMUX CYREG_PRT2_AMUX\r
+#define SCSI_In_DBx__5__BIE CYREG_PRT2_BIE\r
+#define SCSI_In_DBx__5__BIT_MASK CYREG_PRT2_BIT_MASK\r
+#define SCSI_In_DBx__5__BYP CYREG_PRT2_BYP\r
+#define SCSI_In_DBx__5__CTL CYREG_PRT2_CTL\r
+#define SCSI_In_DBx__5__DM0 CYREG_PRT2_DM0\r
+#define SCSI_In_DBx__5__DM1 CYREG_PRT2_DM1\r
+#define SCSI_In_DBx__5__DM2 CYREG_PRT2_DM2\r
+#define SCSI_In_DBx__5__DR CYREG_PRT2_DR\r
+#define SCSI_In_DBx__5__INP_DIS CYREG_PRT2_INP_DIS\r
+#define SCSI_In_DBx__5__INTTYPE CYREG_PICU2_INTTYPE3\r
+#define SCSI_In_DBx__5__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG\r
+#define SCSI_In_DBx__5__LCD_EN CYREG_PRT2_LCD_EN\r
+#define SCSI_In_DBx__5__MASK 0x08u\r
+#define SCSI_In_DBx__5__PC CYREG_PRT2_PC3\r
+#define SCSI_In_DBx__5__PORT 2u\r
+#define SCSI_In_DBx__5__PRT CYREG_PRT2_PRT\r
+#define SCSI_In_DBx__5__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL\r
+#define SCSI_In_DBx__5__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN\r
+#define SCSI_In_DBx__5__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0\r
+#define SCSI_In_DBx__5__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1\r
+#define SCSI_In_DBx__5__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0\r
+#define SCSI_In_DBx__5__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1\r
+#define SCSI_In_DBx__5__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT\r
+#define SCSI_In_DBx__5__PS CYREG_PRT2_PS\r
+#define SCSI_In_DBx__5__SHIFT 3u\r
+#define SCSI_In_DBx__5__SLW CYREG_PRT2_SLW\r
+#define SCSI_In_DBx__6__AG CYREG_PRT2_AG\r
+#define SCSI_In_DBx__6__AMUX CYREG_PRT2_AMUX\r
+#define SCSI_In_DBx__6__BIE CYREG_PRT2_BIE\r
+#define SCSI_In_DBx__6__BIT_MASK CYREG_PRT2_BIT_MASK\r
+#define SCSI_In_DBx__6__BYP CYREG_PRT2_BYP\r
+#define SCSI_In_DBx__6__CTL CYREG_PRT2_CTL\r
+#define SCSI_In_DBx__6__DM0 CYREG_PRT2_DM0\r
+#define SCSI_In_DBx__6__DM1 CYREG_PRT2_DM1\r
+#define SCSI_In_DBx__6__DM2 CYREG_PRT2_DM2\r
+#define SCSI_In_DBx__6__DR CYREG_PRT2_DR\r
+#define SCSI_In_DBx__6__INP_DIS CYREG_PRT2_INP_DIS\r
+#define SCSI_In_DBx__6__INTTYPE CYREG_PICU2_INTTYPE2\r
+#define SCSI_In_DBx__6__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG\r
+#define SCSI_In_DBx__6__LCD_EN CYREG_PRT2_LCD_EN\r
+#define SCSI_In_DBx__6__MASK 0x04u\r
+#define SCSI_In_DBx__6__PC CYREG_PRT2_PC2\r
+#define SCSI_In_DBx__6__PORT 2u\r
+#define SCSI_In_DBx__6__PRT CYREG_PRT2_PRT\r
+#define SCSI_In_DBx__6__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL\r
+#define SCSI_In_DBx__6__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN\r
+#define SCSI_In_DBx__6__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0\r
+#define SCSI_In_DBx__6__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1\r
+#define SCSI_In_DBx__6__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0\r
+#define SCSI_In_DBx__6__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1\r
+#define SCSI_In_DBx__6__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT\r
+#define SCSI_In_DBx__6__PS CYREG_PRT2_PS\r
+#define SCSI_In_DBx__6__SHIFT 2u\r
+#define SCSI_In_DBx__6__SLW CYREG_PRT2_SLW\r
+#define SCSI_In_DBx__7__AG CYREG_PRT2_AG\r
+#define SCSI_In_DBx__7__AMUX CYREG_PRT2_AMUX\r
+#define SCSI_In_DBx__7__BIE CYREG_PRT2_BIE\r
+#define SCSI_In_DBx__7__BIT_MASK CYREG_PRT2_BIT_MASK\r
+#define SCSI_In_DBx__7__BYP CYREG_PRT2_BYP\r
+#define SCSI_In_DBx__7__CTL CYREG_PRT2_CTL\r
+#define SCSI_In_DBx__7__DM0 CYREG_PRT2_DM0\r
+#define SCSI_In_DBx__7__DM1 CYREG_PRT2_DM1\r
+#define SCSI_In_DBx__7__DM2 CYREG_PRT2_DM2\r
+#define SCSI_In_DBx__7__DR CYREG_PRT2_DR\r
+#define SCSI_In_DBx__7__INP_DIS CYREG_PRT2_INP_DIS\r
+#define SCSI_In_DBx__7__INTTYPE CYREG_PICU2_INTTYPE1\r
+#define SCSI_In_DBx__7__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG\r
+#define SCSI_In_DBx__7__LCD_EN CYREG_PRT2_LCD_EN\r
+#define SCSI_In_DBx__7__MASK 0x02u\r
+#define SCSI_In_DBx__7__PC CYREG_PRT2_PC1\r
+#define SCSI_In_DBx__7__PORT 2u\r
+#define SCSI_In_DBx__7__PRT CYREG_PRT2_PRT\r
+#define SCSI_In_DBx__7__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL\r
+#define SCSI_In_DBx__7__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN\r
+#define SCSI_In_DBx__7__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0\r
+#define SCSI_In_DBx__7__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1\r
+#define SCSI_In_DBx__7__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0\r
+#define SCSI_In_DBx__7__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1\r
+#define SCSI_In_DBx__7__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT\r
+#define SCSI_In_DBx__7__PS CYREG_PRT2_PS\r
+#define SCSI_In_DBx__7__SHIFT 1u\r
+#define SCSI_In_DBx__7__SLW CYREG_PRT2_SLW\r
+#define SCSI_In_DBx__DB0__AG CYREG_PRT12_AG\r
+#define SCSI_In_DBx__DB0__BIE CYREG_PRT12_BIE\r
+#define SCSI_In_DBx__DB0__BIT_MASK CYREG_PRT12_BIT_MASK\r
+#define SCSI_In_DBx__DB0__BYP CYREG_PRT12_BYP\r
+#define SCSI_In_DBx__DB0__DM0 CYREG_PRT12_DM0\r
+#define SCSI_In_DBx__DB0__DM1 CYREG_PRT12_DM1\r
+#define SCSI_In_DBx__DB0__DM2 CYREG_PRT12_DM2\r
+#define SCSI_In_DBx__DB0__DR CYREG_PRT12_DR\r
+#define SCSI_In_DBx__DB0__INP_DIS CYREG_PRT12_INP_DIS\r
+#define SCSI_In_DBx__DB0__INTTYPE CYREG_PICU12_INTTYPE4\r
+#define SCSI_In_DBx__DB0__MASK 0x10u\r
+#define SCSI_In_DBx__DB0__PC CYREG_PRT12_PC4\r
+#define SCSI_In_DBx__DB0__PORT 12u\r
+#define SCSI_In_DBx__DB0__PRT CYREG_PRT12_PRT\r
+#define SCSI_In_DBx__DB0__PRTDSI__DBL_SYNC_IN CYREG_PRT12_DBL_SYNC_IN\r
+#define SCSI_In_DBx__DB0__PRTDSI__OE_SEL0 CYREG_PRT12_OE_SEL0\r
+#define SCSI_In_DBx__DB0__PRTDSI__OE_SEL1 CYREG_PRT12_OE_SEL1\r
+#define SCSI_In_DBx__DB0__PRTDSI__OUT_SEL0 CYREG_PRT12_OUT_SEL0\r
+#define SCSI_In_DBx__DB0__PRTDSI__OUT_SEL1 CYREG_PRT12_OUT_SEL1\r
+#define SCSI_In_DBx__DB0__PRTDSI__SYNC_OUT CYREG_PRT12_SYNC_OUT\r
+#define SCSI_In_DBx__DB0__PS CYREG_PRT12_PS\r
+#define SCSI_In_DBx__DB0__SHIFT 4u\r
+#define SCSI_In_DBx__DB0__SIO_CFG CYREG_PRT12_SIO_CFG\r
+#define SCSI_In_DBx__DB0__SIO_DIFF CYREG_PRT12_SIO_DIFF\r
+#define SCSI_In_DBx__DB0__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN\r
+#define SCSI_In_DBx__DB0__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ\r
+#define SCSI_In_DBx__DB0__SLW CYREG_PRT12_SLW\r
+#define SCSI_In_DBx__DB1__AG CYREG_PRT2_AG\r
+#define SCSI_In_DBx__DB1__AMUX CYREG_PRT2_AMUX\r
+#define SCSI_In_DBx__DB1__BIE CYREG_PRT2_BIE\r
+#define SCSI_In_DBx__DB1__BIT_MASK CYREG_PRT2_BIT_MASK\r
+#define SCSI_In_DBx__DB1__BYP CYREG_PRT2_BYP\r
+#define SCSI_In_DBx__DB1__CTL CYREG_PRT2_CTL\r
+#define SCSI_In_DBx__DB1__DM0 CYREG_PRT2_DM0\r
+#define SCSI_In_DBx__DB1__DM1 CYREG_PRT2_DM1\r
+#define SCSI_In_DBx__DB1__DM2 CYREG_PRT2_DM2\r
+#define SCSI_In_DBx__DB1__DR CYREG_PRT2_DR\r
+#define SCSI_In_DBx__DB1__INP_DIS CYREG_PRT2_INP_DIS\r
+#define SCSI_In_DBx__DB1__INTTYPE CYREG_PICU2_INTTYPE7\r
+#define SCSI_In_DBx__DB1__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG\r
+#define SCSI_In_DBx__DB1__LCD_EN CYREG_PRT2_LCD_EN\r
+#define SCSI_In_DBx__DB1__MASK 0x80u\r
+#define SCSI_In_DBx__DB1__PC CYREG_PRT2_PC7\r
+#define SCSI_In_DBx__DB1__PORT 2u\r
+#define SCSI_In_DBx__DB1__PRT CYREG_PRT2_PRT\r
+#define SCSI_In_DBx__DB1__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL\r
+#define SCSI_In_DBx__DB1__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN\r
+#define SCSI_In_DBx__DB1__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0\r
+#define SCSI_In_DBx__DB1__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1\r
+#define SCSI_In_DBx__DB1__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0\r
+#define SCSI_In_DBx__DB1__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1\r
+#define SCSI_In_DBx__DB1__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT\r
+#define SCSI_In_DBx__DB1__PS CYREG_PRT2_PS\r
+#define SCSI_In_DBx__DB1__SHIFT 7u\r
+#define SCSI_In_DBx__DB1__SLW CYREG_PRT2_SLW\r
+#define SCSI_In_DBx__DB2__AG CYREG_PRT2_AG\r
+#define SCSI_In_DBx__DB2__AMUX CYREG_PRT2_AMUX\r
+#define SCSI_In_DBx__DB2__BIE CYREG_PRT2_BIE\r
+#define SCSI_In_DBx__DB2__BIT_MASK CYREG_PRT2_BIT_MASK\r
+#define SCSI_In_DBx__DB2__BYP CYREG_PRT2_BYP\r
+#define SCSI_In_DBx__DB2__CTL CYREG_PRT2_CTL\r
+#define SCSI_In_DBx__DB2__DM0 CYREG_PRT2_DM0\r
+#define SCSI_In_DBx__DB2__DM1 CYREG_PRT2_DM1\r
+#define SCSI_In_DBx__DB2__DM2 CYREG_PRT2_DM2\r
+#define SCSI_In_DBx__DB2__DR CYREG_PRT2_DR\r
+#define SCSI_In_DBx__DB2__INP_DIS CYREG_PRT2_INP_DIS\r
+#define SCSI_In_DBx__DB2__INTTYPE CYREG_PICU2_INTTYPE6\r
+#define SCSI_In_DBx__DB2__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG\r
+#define SCSI_In_DBx__DB2__LCD_EN CYREG_PRT2_LCD_EN\r
+#define SCSI_In_DBx__DB2__MASK 0x40u\r
+#define SCSI_In_DBx__DB2__PC CYREG_PRT2_PC6\r
+#define SCSI_In_DBx__DB2__PORT 2u\r
+#define SCSI_In_DBx__DB2__PRT CYREG_PRT2_PRT\r
+#define SCSI_In_DBx__DB2__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL\r
+#define SCSI_In_DBx__DB2__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN\r
+#define SCSI_In_DBx__DB2__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0\r
+#define SCSI_In_DBx__DB2__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1\r
+#define SCSI_In_DBx__DB2__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0\r
+#define SCSI_In_DBx__DB2__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1\r
+#define SCSI_In_DBx__DB2__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT\r
+#define SCSI_In_DBx__DB2__PS CYREG_PRT2_PS\r
+#define SCSI_In_DBx__DB2__SHIFT 6u\r
+#define SCSI_In_DBx__DB2__SLW CYREG_PRT2_SLW\r
+#define SCSI_In_DBx__DB3__AG CYREG_PRT2_AG\r
+#define SCSI_In_DBx__DB3__AMUX CYREG_PRT2_AMUX\r
+#define SCSI_In_DBx__DB3__BIE CYREG_PRT2_BIE\r
+#define SCSI_In_DBx__DB3__BIT_MASK CYREG_PRT2_BIT_MASK\r
+#define SCSI_In_DBx__DB3__BYP CYREG_PRT2_BYP\r
+#define SCSI_In_DBx__DB3__CTL CYREG_PRT2_CTL\r
+#define SCSI_In_DBx__DB3__DM0 CYREG_PRT2_DM0\r
+#define SCSI_In_DBx__DB3__DM1 CYREG_PRT2_DM1\r
+#define SCSI_In_DBx__DB3__DM2 CYREG_PRT2_DM2\r
+#define SCSI_In_DBx__DB3__DR CYREG_PRT2_DR\r
+#define SCSI_In_DBx__DB3__INP_DIS CYREG_PRT2_INP_DIS\r
+#define SCSI_In_DBx__DB3__INTTYPE CYREG_PICU2_INTTYPE5\r
+#define SCSI_In_DBx__DB3__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG\r
+#define SCSI_In_DBx__DB3__LCD_EN CYREG_PRT2_LCD_EN\r
+#define SCSI_In_DBx__DB3__MASK 0x20u\r
+#define SCSI_In_DBx__DB3__PC CYREG_PRT2_PC5\r
+#define SCSI_In_DBx__DB3__PORT 2u\r
+#define SCSI_In_DBx__DB3__PRT CYREG_PRT2_PRT\r
+#define SCSI_In_DBx__DB3__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL\r
+#define SCSI_In_DBx__DB3__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN\r
+#define SCSI_In_DBx__DB3__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0\r
+#define SCSI_In_DBx__DB3__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1\r
+#define SCSI_In_DBx__DB3__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0\r
+#define SCSI_In_DBx__DB3__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1\r
+#define SCSI_In_DBx__DB3__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT\r
+#define SCSI_In_DBx__DB3__PS CYREG_PRT2_PS\r
+#define SCSI_In_DBx__DB3__SHIFT 5u\r
+#define SCSI_In_DBx__DB3__SLW CYREG_PRT2_SLW\r
+#define SCSI_In_DBx__DB4__AG CYREG_PRT2_AG\r
+#define SCSI_In_DBx__DB4__AMUX CYREG_PRT2_AMUX\r
+#define SCSI_In_DBx__DB4__BIE CYREG_PRT2_BIE\r
+#define SCSI_In_DBx__DB4__BIT_MASK CYREG_PRT2_BIT_MASK\r
+#define SCSI_In_DBx__DB4__BYP CYREG_PRT2_BYP\r
+#define SCSI_In_DBx__DB4__CTL CYREG_PRT2_CTL\r
+#define SCSI_In_DBx__DB4__DM0 CYREG_PRT2_DM0\r
+#define SCSI_In_DBx__DB4__DM1 CYREG_PRT2_DM1\r
+#define SCSI_In_DBx__DB4__DM2 CYREG_PRT2_DM2\r
+#define SCSI_In_DBx__DB4__DR CYREG_PRT2_DR\r
+#define SCSI_In_DBx__DB4__INP_DIS CYREG_PRT2_INP_DIS\r
+#define SCSI_In_DBx__DB4__INTTYPE CYREG_PICU2_INTTYPE4\r
+#define SCSI_In_DBx__DB4__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG\r
+#define SCSI_In_DBx__DB4__LCD_EN CYREG_PRT2_LCD_EN\r
+#define SCSI_In_DBx__DB4__MASK 0x10u\r
+#define SCSI_In_DBx__DB4__PC CYREG_PRT2_PC4\r
+#define SCSI_In_DBx__DB4__PORT 2u\r
+#define SCSI_In_DBx__DB4__PRT CYREG_PRT2_PRT\r
+#define SCSI_In_DBx__DB4__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL\r
+#define SCSI_In_DBx__DB4__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN\r
+#define SCSI_In_DBx__DB4__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0\r
+#define SCSI_In_DBx__DB4__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1\r
+#define SCSI_In_DBx__DB4__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0\r
+#define SCSI_In_DBx__DB4__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1\r
+#define SCSI_In_DBx__DB4__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT\r
+#define SCSI_In_DBx__DB4__PS CYREG_PRT2_PS\r
+#define SCSI_In_DBx__DB4__SHIFT 4u\r
+#define SCSI_In_DBx__DB4__SLW CYREG_PRT2_SLW\r
+#define SCSI_In_DBx__DB5__AG CYREG_PRT2_AG\r
+#define SCSI_In_DBx__DB5__AMUX CYREG_PRT2_AMUX\r
+#define SCSI_In_DBx__DB5__BIE CYREG_PRT2_BIE\r
+#define SCSI_In_DBx__DB5__BIT_MASK CYREG_PRT2_BIT_MASK\r
+#define SCSI_In_DBx__DB5__BYP CYREG_PRT2_BYP\r
+#define SCSI_In_DBx__DB5__CTL CYREG_PRT2_CTL\r
+#define SCSI_In_DBx__DB5__DM0 CYREG_PRT2_DM0\r
+#define SCSI_In_DBx__DB5__DM1 CYREG_PRT2_DM1\r
+#define SCSI_In_DBx__DB5__DM2 CYREG_PRT2_DM2\r
+#define SCSI_In_DBx__DB5__DR CYREG_PRT2_DR\r
+#define SCSI_In_DBx__DB5__INP_DIS CYREG_PRT2_INP_DIS\r
+#define SCSI_In_DBx__DB5__INTTYPE CYREG_PICU2_INTTYPE3\r
+#define SCSI_In_DBx__DB5__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG\r
+#define SCSI_In_DBx__DB5__LCD_EN CYREG_PRT2_LCD_EN\r
+#define SCSI_In_DBx__DB5__MASK 0x08u\r
+#define SCSI_In_DBx__DB5__PC CYREG_PRT2_PC3\r
+#define SCSI_In_DBx__DB5__PORT 2u\r
+#define SCSI_In_DBx__DB5__PRT CYREG_PRT2_PRT\r
+#define SCSI_In_DBx__DB5__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL\r
+#define SCSI_In_DBx__DB5__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN\r
+#define SCSI_In_DBx__DB5__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0\r
+#define SCSI_In_DBx__DB5__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1\r
+#define SCSI_In_DBx__DB5__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0\r
+#define SCSI_In_DBx__DB5__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1\r
+#define SCSI_In_DBx__DB5__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT\r
+#define SCSI_In_DBx__DB5__PS CYREG_PRT2_PS\r
+#define SCSI_In_DBx__DB5__SHIFT 3u\r
+#define SCSI_In_DBx__DB5__SLW CYREG_PRT2_SLW\r
+#define SCSI_In_DBx__DB6__AG CYREG_PRT2_AG\r
+#define SCSI_In_DBx__DB6__AMUX CYREG_PRT2_AMUX\r
+#define SCSI_In_DBx__DB6__BIE CYREG_PRT2_BIE\r
+#define SCSI_In_DBx__DB6__BIT_MASK CYREG_PRT2_BIT_MASK\r
+#define SCSI_In_DBx__DB6__BYP CYREG_PRT2_BYP\r
+#define SCSI_In_DBx__DB6__CTL CYREG_PRT2_CTL\r
+#define SCSI_In_DBx__DB6__DM0 CYREG_PRT2_DM0\r
+#define SCSI_In_DBx__DB6__DM1 CYREG_PRT2_DM1\r
+#define SCSI_In_DBx__DB6__DM2 CYREG_PRT2_DM2\r
+#define SCSI_In_DBx__DB6__DR CYREG_PRT2_DR\r
+#define SCSI_In_DBx__DB6__INP_DIS CYREG_PRT2_INP_DIS\r
+#define SCSI_In_DBx__DB6__INTTYPE CYREG_PICU2_INTTYPE2\r
+#define SCSI_In_DBx__DB6__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG\r
+#define SCSI_In_DBx__DB6__LCD_EN CYREG_PRT2_LCD_EN\r
+#define SCSI_In_DBx__DB6__MASK 0x04u\r
+#define SCSI_In_DBx__DB6__PC CYREG_PRT2_PC2\r
+#define SCSI_In_DBx__DB6__PORT 2u\r
+#define SCSI_In_DBx__DB6__PRT CYREG_PRT2_PRT\r
+#define SCSI_In_DBx__DB6__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL\r
+#define SCSI_In_DBx__DB6__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN\r
+#define SCSI_In_DBx__DB6__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0\r
+#define SCSI_In_DBx__DB6__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1\r
+#define SCSI_In_DBx__DB6__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0\r
+#define SCSI_In_DBx__DB6__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1\r
+#define SCSI_In_DBx__DB6__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT\r
+#define SCSI_In_DBx__DB6__PS CYREG_PRT2_PS\r
+#define SCSI_In_DBx__DB6__SHIFT 2u\r
+#define SCSI_In_DBx__DB6__SLW CYREG_PRT2_SLW\r
+#define SCSI_In_DBx__DB7__AG CYREG_PRT2_AG\r
+#define SCSI_In_DBx__DB7__AMUX CYREG_PRT2_AMUX\r
+#define SCSI_In_DBx__DB7__BIE CYREG_PRT2_BIE\r
+#define SCSI_In_DBx__DB7__BIT_MASK CYREG_PRT2_BIT_MASK\r
+#define SCSI_In_DBx__DB7__BYP CYREG_PRT2_BYP\r
+#define SCSI_In_DBx__DB7__CTL CYREG_PRT2_CTL\r
+#define SCSI_In_DBx__DB7__DM0 CYREG_PRT2_DM0\r
+#define SCSI_In_DBx__DB7__DM1 CYREG_PRT2_DM1\r
+#define SCSI_In_DBx__DB7__DM2 CYREG_PRT2_DM2\r
+#define SCSI_In_DBx__DB7__DR CYREG_PRT2_DR\r
+#define SCSI_In_DBx__DB7__INP_DIS CYREG_PRT2_INP_DIS\r
+#define SCSI_In_DBx__DB7__INTTYPE CYREG_PICU2_INTTYPE1\r
+#define SCSI_In_DBx__DB7__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG\r
+#define SCSI_In_DBx__DB7__LCD_EN CYREG_PRT2_LCD_EN\r
+#define SCSI_In_DBx__DB7__MASK 0x02u\r
+#define SCSI_In_DBx__DB7__PC CYREG_PRT2_PC1\r
+#define SCSI_In_DBx__DB7__PORT 2u\r
+#define SCSI_In_DBx__DB7__PRT CYREG_PRT2_PRT\r
+#define SCSI_In_DBx__DB7__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL\r
+#define SCSI_In_DBx__DB7__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN\r
+#define SCSI_In_DBx__DB7__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0\r
+#define SCSI_In_DBx__DB7__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1\r
+#define SCSI_In_DBx__DB7__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0\r
+#define SCSI_In_DBx__DB7__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1\r
+#define SCSI_In_DBx__DB7__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT\r
+#define SCSI_In_DBx__DB7__PS CYREG_PRT2_PS\r
+#define SCSI_In_DBx__DB7__SHIFT 1u\r
+#define SCSI_In_DBx__DB7__SLW CYREG_PRT2_SLW\r
+\r
+/* SD_DAT1 */\r
+#define SD_DAT1__0__INTTYPE CYREG_PICU3_INTTYPE0\r
+#define SD_DAT1__0__MASK 0x01u\r
+#define SD_DAT1__0__PC CYREG_PRT3_PC0\r
+#define SD_DAT1__0__PORT 3u\r
+#define SD_DAT1__0__SHIFT 0u\r
+#define SD_DAT1__AG CYREG_PRT3_AG\r
+#define SD_DAT1__AMUX CYREG_PRT3_AMUX\r
+#define SD_DAT1__BIE CYREG_PRT3_BIE\r
+#define SD_DAT1__BIT_MASK CYREG_PRT3_BIT_MASK\r
+#define SD_DAT1__BYP CYREG_PRT3_BYP\r
+#define SD_DAT1__CTL CYREG_PRT3_CTL\r
+#define SD_DAT1__DM0 CYREG_PRT3_DM0\r
+#define SD_DAT1__DM1 CYREG_PRT3_DM1\r
+#define SD_DAT1__DM2 CYREG_PRT3_DM2\r
+#define SD_DAT1__DR CYREG_PRT3_DR\r
+#define SD_DAT1__INP_DIS CYREG_PRT3_INP_DIS\r
+#define SD_DAT1__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU3_BASE\r
+#define SD_DAT1__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG\r
+#define SD_DAT1__LCD_EN CYREG_PRT3_LCD_EN\r
+#define SD_DAT1__MASK 0x01u\r
+#define SD_DAT1__PORT 3u\r
+#define SD_DAT1__PRT CYREG_PRT3_PRT\r
+#define SD_DAT1__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL\r
+#define SD_DAT1__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN\r
+#define SD_DAT1__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0\r
+#define SD_DAT1__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1\r
+#define SD_DAT1__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0\r
+#define SD_DAT1__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1\r
+#define SD_DAT1__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT\r
+#define SD_DAT1__PS CYREG_PRT3_PS\r
+#define SD_DAT1__SHIFT 0u\r
+#define SD_DAT1__SLW CYREG_PRT3_SLW\r
+\r
+/* SD_DAT2 */\r
+#define SD_DAT2__0__INTTYPE CYREG_PICU3_INTTYPE5\r
+#define SD_DAT2__0__MASK 0x20u\r
+#define SD_DAT2__0__PC CYREG_PRT3_PC5\r
+#define SD_DAT2__0__PORT 3u\r
+#define SD_DAT2__0__SHIFT 5u\r
+#define SD_DAT2__AG CYREG_PRT3_AG\r
+#define SD_DAT2__AMUX CYREG_PRT3_AMUX\r
+#define SD_DAT2__BIE CYREG_PRT3_BIE\r
+#define SD_DAT2__BIT_MASK CYREG_PRT3_BIT_MASK\r
+#define SD_DAT2__BYP CYREG_PRT3_BYP\r
+#define SD_DAT2__CTL CYREG_PRT3_CTL\r
+#define SD_DAT2__DM0 CYREG_PRT3_DM0\r
+#define SD_DAT2__DM1 CYREG_PRT3_DM1\r
+#define SD_DAT2__DM2 CYREG_PRT3_DM2\r
+#define SD_DAT2__DR CYREG_PRT3_DR\r
+#define SD_DAT2__INP_DIS CYREG_PRT3_INP_DIS\r
+#define SD_DAT2__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU3_BASE\r
+#define SD_DAT2__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG\r
+#define SD_DAT2__LCD_EN CYREG_PRT3_LCD_EN\r
+#define SD_DAT2__MASK 0x20u\r
+#define SD_DAT2__PORT 3u\r
+#define SD_DAT2__PRT CYREG_PRT3_PRT\r
+#define SD_DAT2__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL\r
+#define SD_DAT2__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN\r
+#define SD_DAT2__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0\r
+#define SD_DAT2__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1\r
+#define SD_DAT2__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0\r
+#define SD_DAT2__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1\r
+#define SD_DAT2__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT\r
+#define SD_DAT2__PS CYREG_PRT3_PS\r
+#define SD_DAT2__SHIFT 5u\r
+#define SD_DAT2__SLW CYREG_PRT3_SLW\r
+\r
+/* SD_MISO */\r
+#define SD_MISO__0__INTTYPE CYREG_PICU3_INTTYPE1\r
+#define SD_MISO__0__MASK 0x02u\r
+#define SD_MISO__0__PC CYREG_PRT3_PC1\r
+#define SD_MISO__0__PORT 3u\r
+#define SD_MISO__0__SHIFT 1u\r
+#define SD_MISO__AG CYREG_PRT3_AG\r
+#define SD_MISO__AMUX CYREG_PRT3_AMUX\r
+#define SD_MISO__BIE CYREG_PRT3_BIE\r
+#define SD_MISO__BIT_MASK CYREG_PRT3_BIT_MASK\r
+#define SD_MISO__BYP CYREG_PRT3_BYP\r
+#define SD_MISO__CTL CYREG_PRT3_CTL\r
+#define SD_MISO__DM0 CYREG_PRT3_DM0\r
+#define SD_MISO__DM1 CYREG_PRT3_DM1\r
+#define SD_MISO__DM2 CYREG_PRT3_DM2\r
+#define SD_MISO__DR CYREG_PRT3_DR\r
+#define SD_MISO__INP_DIS CYREG_PRT3_INP_DIS\r
+#define SD_MISO__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU3_BASE\r
+#define SD_MISO__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG\r
+#define SD_MISO__LCD_EN CYREG_PRT3_LCD_EN\r
+#define SD_MISO__MASK 0x02u\r
+#define SD_MISO__PORT 3u\r
+#define SD_MISO__PRT CYREG_PRT3_PRT\r
+#define SD_MISO__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL\r
+#define SD_MISO__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN\r
+#define SD_MISO__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0\r
+#define SD_MISO__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1\r
+#define SD_MISO__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0\r
+#define SD_MISO__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1\r
+#define SD_MISO__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT\r
+#define SD_MISO__PS CYREG_PRT3_PS\r
+#define SD_MISO__SHIFT 1u\r
+#define SD_MISO__SLW CYREG_PRT3_SLW\r
+\r
+/* SD_MOSI */\r
+#define SD_MOSI__0__INTTYPE CYREG_PICU3_INTTYPE3\r
+#define SD_MOSI__0__MASK 0x08u\r
+#define SD_MOSI__0__PC CYREG_PRT3_PC3\r
+#define SD_MOSI__0__PORT 3u\r
+#define SD_MOSI__0__SHIFT 3u\r
+#define SD_MOSI__AG CYREG_PRT3_AG\r
+#define SD_MOSI__AMUX CYREG_PRT3_AMUX\r
+#define SD_MOSI__BIE CYREG_PRT3_BIE\r
+#define SD_MOSI__BIT_MASK CYREG_PRT3_BIT_MASK\r
+#define SD_MOSI__BYP CYREG_PRT3_BYP\r
+#define SD_MOSI__CTL CYREG_PRT3_CTL\r
+#define SD_MOSI__DM0 CYREG_PRT3_DM0\r
+#define SD_MOSI__DM1 CYREG_PRT3_DM1\r
+#define SD_MOSI__DM2 CYREG_PRT3_DM2\r
+#define SD_MOSI__DR CYREG_PRT3_DR\r
+#define SD_MOSI__INP_DIS CYREG_PRT3_INP_DIS\r
+#define SD_MOSI__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU3_BASE\r
+#define SD_MOSI__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG\r
+#define SD_MOSI__LCD_EN CYREG_PRT3_LCD_EN\r
+#define SD_MOSI__MASK 0x08u\r
+#define SD_MOSI__PORT 3u\r
+#define SD_MOSI__PRT CYREG_PRT3_PRT\r
+#define SD_MOSI__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL\r
+#define SD_MOSI__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN\r
+#define SD_MOSI__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0\r
+#define SD_MOSI__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1\r
+#define SD_MOSI__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0\r
+#define SD_MOSI__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1\r
+#define SD_MOSI__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT\r
+#define SD_MOSI__PS CYREG_PRT3_PS\r
+#define SD_MOSI__SHIFT 3u\r
+#define SD_MOSI__SLW CYREG_PRT3_SLW\r
+\r
+/* SCSI_CLK */\r
+#define SCSI_CLK__CFG0 CYREG_CLKDIST_DCFG1_CFG0\r
+#define SCSI_CLK__CFG1 CYREG_CLKDIST_DCFG1_CFG1\r
+#define SCSI_CLK__CFG2 CYREG_CLKDIST_DCFG1_CFG2\r
+#define SCSI_CLK__CFG2_SRC_SEL_MASK 0x07u\r
+#define SCSI_CLK__INDEX 0x01u\r
+#define SCSI_CLK__PM_ACT_CFG CYREG_PM_ACT_CFG2\r
+#define SCSI_CLK__PM_ACT_MSK 0x02u\r
+#define SCSI_CLK__PM_STBY_CFG CYREG_PM_STBY_CFG2\r
+#define SCSI_CLK__PM_STBY_MSK 0x02u\r
+\r
+/* SCSI_Out */\r
+#define SCSI_Out__0__AG CYREG_PRT4_AG\r
+#define SCSI_Out__0__AMUX CYREG_PRT4_AMUX\r
+#define SCSI_Out__0__BIE CYREG_PRT4_BIE\r
+#define SCSI_Out__0__BIT_MASK CYREG_PRT4_BIT_MASK\r
+#define SCSI_Out__0__BYP CYREG_PRT4_BYP\r
+#define SCSI_Out__0__CTL CYREG_PRT4_CTL\r
+#define SCSI_Out__0__DM0 CYREG_PRT4_DM0\r
+#define SCSI_Out__0__DM1 CYREG_PRT4_DM1\r
+#define SCSI_Out__0__DM2 CYREG_PRT4_DM2\r
+#define SCSI_Out__0__DR CYREG_PRT4_DR\r
+#define SCSI_Out__0__INP_DIS CYREG_PRT4_INP_DIS\r
+#define SCSI_Out__0__INTTYPE CYREG_PICU4_INTTYPE3\r
+#define SCSI_Out__0__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG\r
+#define SCSI_Out__0__LCD_EN CYREG_PRT4_LCD_EN\r
+#define SCSI_Out__0__MASK 0x08u\r
+#define SCSI_Out__0__PC CYREG_PRT4_PC3\r
+#define SCSI_Out__0__PORT 4u\r
+#define SCSI_Out__0__PRT CYREG_PRT4_PRT\r
+#define SCSI_Out__0__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL\r
+#define SCSI_Out__0__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN\r
+#define SCSI_Out__0__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0\r
+#define SCSI_Out__0__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1\r
+#define SCSI_Out__0__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0\r
+#define SCSI_Out__0__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1\r
+#define SCSI_Out__0__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT\r
+#define SCSI_Out__0__PS CYREG_PRT4_PS\r
+#define SCSI_Out__0__SHIFT 3u\r
+#define SCSI_Out__0__SLW CYREG_PRT4_SLW\r
+#define SCSI_Out__1__AG CYREG_PRT4_AG\r
+#define SCSI_Out__1__AMUX CYREG_PRT4_AMUX\r
+#define SCSI_Out__1__BIE CYREG_PRT4_BIE\r
+#define SCSI_Out__1__BIT_MASK CYREG_PRT4_BIT_MASK\r
+#define SCSI_Out__1__BYP CYREG_PRT4_BYP\r
+#define SCSI_Out__1__CTL CYREG_PRT4_CTL\r
+#define SCSI_Out__1__DM0 CYREG_PRT4_DM0\r
+#define SCSI_Out__1__DM1 CYREG_PRT4_DM1\r
+#define SCSI_Out__1__DM2 CYREG_PRT4_DM2\r
+#define SCSI_Out__1__DR CYREG_PRT4_DR\r
+#define SCSI_Out__1__INP_DIS CYREG_PRT4_INP_DIS\r
+#define SCSI_Out__1__INTTYPE CYREG_PICU4_INTTYPE2\r
+#define SCSI_Out__1__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG\r
+#define SCSI_Out__1__LCD_EN CYREG_PRT4_LCD_EN\r
+#define SCSI_Out__1__MASK 0x04u\r
+#define SCSI_Out__1__PC CYREG_PRT4_PC2\r
+#define SCSI_Out__1__PORT 4u\r
+#define SCSI_Out__1__PRT CYREG_PRT4_PRT\r
+#define SCSI_Out__1__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL\r
+#define SCSI_Out__1__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN\r
+#define SCSI_Out__1__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0\r
+#define SCSI_Out__1__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1\r
+#define SCSI_Out__1__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0\r
+#define SCSI_Out__1__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1\r
+#define SCSI_Out__1__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT\r
+#define SCSI_Out__1__PS CYREG_PRT4_PS\r
+#define SCSI_Out__1__SHIFT 2u\r
+#define SCSI_Out__1__SLW CYREG_PRT4_SLW\r
+#define SCSI_Out__2__AG CYREG_PRT0_AG\r
+#define SCSI_Out__2__AMUX CYREG_PRT0_AMUX\r
+#define SCSI_Out__2__BIE CYREG_PRT0_BIE\r
+#define SCSI_Out__2__BIT_MASK CYREG_PRT0_BIT_MASK\r
+#define SCSI_Out__2__BYP CYREG_PRT0_BYP\r
+#define SCSI_Out__2__CTL CYREG_PRT0_CTL\r
+#define SCSI_Out__2__DM0 CYREG_PRT0_DM0\r
+#define SCSI_Out__2__DM1 CYREG_PRT0_DM1\r
+#define SCSI_Out__2__DM2 CYREG_PRT0_DM2\r
+#define SCSI_Out__2__DR CYREG_PRT0_DR\r
+#define SCSI_Out__2__INP_DIS CYREG_PRT0_INP_DIS\r
+#define SCSI_Out__2__INTTYPE CYREG_PICU0_INTTYPE7\r
+#define SCSI_Out__2__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG\r
+#define SCSI_Out__2__LCD_EN CYREG_PRT0_LCD_EN\r
+#define SCSI_Out__2__MASK 0x80u\r
+#define SCSI_Out__2__PC CYREG_PRT0_PC7\r
+#define SCSI_Out__2__PORT 0u\r
+#define SCSI_Out__2__PRT CYREG_PRT0_PRT\r
+#define SCSI_Out__2__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL\r
+#define SCSI_Out__2__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN\r
+#define SCSI_Out__2__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0\r
+#define SCSI_Out__2__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1\r
+#define SCSI_Out__2__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0\r
+#define SCSI_Out__2__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1\r
+#define SCSI_Out__2__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT\r
+#define SCSI_Out__2__PS CYREG_PRT0_PS\r
+#define SCSI_Out__2__SHIFT 7u\r
+#define SCSI_Out__2__SLW CYREG_PRT0_SLW\r
+#define SCSI_Out__3__AG CYREG_PRT0_AG\r
+#define SCSI_Out__3__AMUX CYREG_PRT0_AMUX\r
+#define SCSI_Out__3__BIE CYREG_PRT0_BIE\r
+#define SCSI_Out__3__BIT_MASK CYREG_PRT0_BIT_MASK\r
+#define SCSI_Out__3__BYP CYREG_PRT0_BYP\r
+#define SCSI_Out__3__CTL CYREG_PRT0_CTL\r
+#define SCSI_Out__3__DM0 CYREG_PRT0_DM0\r
+#define SCSI_Out__3__DM1 CYREG_PRT0_DM1\r
+#define SCSI_Out__3__DM2 CYREG_PRT0_DM2\r
+#define SCSI_Out__3__DR CYREG_PRT0_DR\r
+#define SCSI_Out__3__INP_DIS CYREG_PRT0_INP_DIS\r
+#define SCSI_Out__3__INTTYPE CYREG_PICU0_INTTYPE6\r
+#define SCSI_Out__3__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG\r
+#define SCSI_Out__3__LCD_EN CYREG_PRT0_LCD_EN\r
+#define SCSI_Out__3__MASK 0x40u\r
+#define SCSI_Out__3__PC CYREG_PRT0_PC6\r
+#define SCSI_Out__3__PORT 0u\r
+#define SCSI_Out__3__PRT CYREG_PRT0_PRT\r
+#define SCSI_Out__3__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL\r
+#define SCSI_Out__3__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN\r
+#define SCSI_Out__3__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0\r
+#define SCSI_Out__3__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1\r
+#define SCSI_Out__3__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0\r
+#define SCSI_Out__3__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1\r
+#define SCSI_Out__3__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT\r
+#define SCSI_Out__3__PS CYREG_PRT0_PS\r
+#define SCSI_Out__3__SHIFT 6u\r
+#define SCSI_Out__3__SLW CYREG_PRT0_SLW\r
+#define SCSI_Out__4__AG CYREG_PRT0_AG\r
+#define SCSI_Out__4__AMUX CYREG_PRT0_AMUX\r
+#define SCSI_Out__4__BIE CYREG_PRT0_BIE\r
+#define SCSI_Out__4__BIT_MASK CYREG_PRT0_BIT_MASK\r
+#define SCSI_Out__4__BYP CYREG_PRT0_BYP\r
+#define SCSI_Out__4__CTL CYREG_PRT0_CTL\r
+#define SCSI_Out__4__DM0 CYREG_PRT0_DM0\r
+#define SCSI_Out__4__DM1 CYREG_PRT0_DM1\r
+#define SCSI_Out__4__DM2 CYREG_PRT0_DM2\r
+#define SCSI_Out__4__DR CYREG_PRT0_DR\r
+#define SCSI_Out__4__INP_DIS CYREG_PRT0_INP_DIS\r
+#define SCSI_Out__4__INTTYPE CYREG_PICU0_INTTYPE5\r
+#define SCSI_Out__4__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG\r
+#define SCSI_Out__4__LCD_EN CYREG_PRT0_LCD_EN\r
+#define SCSI_Out__4__MASK 0x20u\r
+#define SCSI_Out__4__PC CYREG_PRT0_PC5\r
+#define SCSI_Out__4__PORT 0u\r
+#define SCSI_Out__4__PRT CYREG_PRT0_PRT\r
+#define SCSI_Out__4__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL\r
+#define SCSI_Out__4__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN\r
+#define SCSI_Out__4__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0\r
+#define SCSI_Out__4__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1\r
+#define SCSI_Out__4__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0\r
+#define SCSI_Out__4__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1\r
+#define SCSI_Out__4__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT\r
+#define SCSI_Out__4__PS CYREG_PRT0_PS\r
+#define SCSI_Out__4__SHIFT 5u\r
+#define SCSI_Out__4__SLW CYREG_PRT0_SLW\r
+#define SCSI_Out__5__AG CYREG_PRT0_AG\r
+#define SCSI_Out__5__AMUX CYREG_PRT0_AMUX\r
+#define SCSI_Out__5__BIE CYREG_PRT0_BIE\r
+#define SCSI_Out__5__BIT_MASK CYREG_PRT0_BIT_MASK\r
+#define SCSI_Out__5__BYP CYREG_PRT0_BYP\r
+#define SCSI_Out__5__CTL CYREG_PRT0_CTL\r
+#define SCSI_Out__5__DM0 CYREG_PRT0_DM0\r
+#define SCSI_Out__5__DM1 CYREG_PRT0_DM1\r
+#define SCSI_Out__5__DM2 CYREG_PRT0_DM2\r
+#define SCSI_Out__5__DR CYREG_PRT0_DR\r
+#define SCSI_Out__5__INP_DIS CYREG_PRT0_INP_DIS\r
+#define SCSI_Out__5__INTTYPE CYREG_PICU0_INTTYPE4\r
+#define SCSI_Out__5__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG\r
+#define SCSI_Out__5__LCD_EN CYREG_PRT0_LCD_EN\r
+#define SCSI_Out__5__MASK 0x10u\r
+#define SCSI_Out__5__PC CYREG_PRT0_PC4\r
+#define SCSI_Out__5__PORT 0u\r
+#define SCSI_Out__5__PRT CYREG_PRT0_PRT\r
+#define SCSI_Out__5__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL\r
+#define SCSI_Out__5__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN\r
+#define SCSI_Out__5__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0\r
+#define SCSI_Out__5__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1\r
+#define SCSI_Out__5__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0\r
+#define SCSI_Out__5__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1\r
+#define SCSI_Out__5__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT\r
+#define SCSI_Out__5__PS CYREG_PRT0_PS\r
+#define SCSI_Out__5__SHIFT 4u\r
+#define SCSI_Out__5__SLW CYREG_PRT0_SLW\r
+#define SCSI_Out__6__AG CYREG_PRT0_AG\r
+#define SCSI_Out__6__AMUX CYREG_PRT0_AMUX\r
+#define SCSI_Out__6__BIE CYREG_PRT0_BIE\r
+#define SCSI_Out__6__BIT_MASK CYREG_PRT0_BIT_MASK\r
+#define SCSI_Out__6__BYP CYREG_PRT0_BYP\r
+#define SCSI_Out__6__CTL CYREG_PRT0_CTL\r
+#define SCSI_Out__6__DM0 CYREG_PRT0_DM0\r
+#define SCSI_Out__6__DM1 CYREG_PRT0_DM1\r
+#define SCSI_Out__6__DM2 CYREG_PRT0_DM2\r
+#define SCSI_Out__6__DR CYREG_PRT0_DR\r
+#define SCSI_Out__6__INP_DIS CYREG_PRT0_INP_DIS\r
+#define SCSI_Out__6__INTTYPE CYREG_PICU0_INTTYPE3\r
+#define SCSI_Out__6__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG\r
+#define SCSI_Out__6__LCD_EN CYREG_PRT0_LCD_EN\r
+#define SCSI_Out__6__MASK 0x08u\r
+#define SCSI_Out__6__PC CYREG_PRT0_PC3\r
+#define SCSI_Out__6__PORT 0u\r
+#define SCSI_Out__6__PRT CYREG_PRT0_PRT\r
+#define SCSI_Out__6__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL\r
+#define SCSI_Out__6__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN\r
+#define SCSI_Out__6__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0\r
+#define SCSI_Out__6__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1\r
+#define SCSI_Out__6__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0\r
+#define SCSI_Out__6__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1\r
+#define SCSI_Out__6__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT\r
+#define SCSI_Out__6__PS CYREG_PRT0_PS\r
+#define SCSI_Out__6__SHIFT 3u\r
+#define SCSI_Out__6__SLW CYREG_PRT0_SLW\r
+#define SCSI_Out__7__AG CYREG_PRT0_AG\r
+#define SCSI_Out__7__AMUX CYREG_PRT0_AMUX\r
+#define SCSI_Out__7__BIE CYREG_PRT0_BIE\r
+#define SCSI_Out__7__BIT_MASK CYREG_PRT0_BIT_MASK\r
+#define SCSI_Out__7__BYP CYREG_PRT0_BYP\r
+#define SCSI_Out__7__CTL CYREG_PRT0_CTL\r
+#define SCSI_Out__7__DM0 CYREG_PRT0_DM0\r
+#define SCSI_Out__7__DM1 CYREG_PRT0_DM1\r
+#define SCSI_Out__7__DM2 CYREG_PRT0_DM2\r
+#define SCSI_Out__7__DR CYREG_PRT0_DR\r
+#define SCSI_Out__7__INP_DIS CYREG_PRT0_INP_DIS\r
+#define SCSI_Out__7__INTTYPE CYREG_PICU0_INTTYPE2\r
+#define SCSI_Out__7__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG\r
+#define SCSI_Out__7__LCD_EN CYREG_PRT0_LCD_EN\r
+#define SCSI_Out__7__MASK 0x04u\r
+#define SCSI_Out__7__PC CYREG_PRT0_PC2\r
+#define SCSI_Out__7__PORT 0u\r
+#define SCSI_Out__7__PRT CYREG_PRT0_PRT\r
+#define SCSI_Out__7__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL\r
+#define SCSI_Out__7__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN\r
+#define SCSI_Out__7__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0\r
+#define SCSI_Out__7__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1\r
+#define SCSI_Out__7__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0\r
+#define SCSI_Out__7__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1\r
+#define SCSI_Out__7__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT\r
+#define SCSI_Out__7__PS CYREG_PRT0_PS\r
+#define SCSI_Out__7__SHIFT 2u\r
+#define SCSI_Out__7__SLW CYREG_PRT0_SLW\r
+#define SCSI_Out__8__AG CYREG_PRT0_AG\r
+#define SCSI_Out__8__AMUX CYREG_PRT0_AMUX\r
+#define SCSI_Out__8__BIE CYREG_PRT0_BIE\r
+#define SCSI_Out__8__BIT_MASK CYREG_PRT0_BIT_MASK\r
+#define SCSI_Out__8__BYP CYREG_PRT0_BYP\r
+#define SCSI_Out__8__CTL CYREG_PRT0_CTL\r
+#define SCSI_Out__8__DM0 CYREG_PRT0_DM0\r
+#define SCSI_Out__8__DM1 CYREG_PRT0_DM1\r
+#define SCSI_Out__8__DM2 CYREG_PRT0_DM2\r
+#define SCSI_Out__8__DR CYREG_PRT0_DR\r
+#define SCSI_Out__8__INP_DIS CYREG_PRT0_INP_DIS\r
+#define SCSI_Out__8__INTTYPE CYREG_PICU0_INTTYPE1\r
+#define SCSI_Out__8__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG\r
+#define SCSI_Out__8__LCD_EN CYREG_PRT0_LCD_EN\r
+#define SCSI_Out__8__MASK 0x02u\r
+#define SCSI_Out__8__PC CYREG_PRT0_PC1\r
+#define SCSI_Out__8__PORT 0u\r
+#define SCSI_Out__8__PRT CYREG_PRT0_PRT\r
+#define SCSI_Out__8__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL\r
+#define SCSI_Out__8__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN\r
+#define SCSI_Out__8__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0\r
+#define SCSI_Out__8__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1\r
+#define SCSI_Out__8__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0\r
+#define SCSI_Out__8__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1\r
+#define SCSI_Out__8__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT\r
+#define SCSI_Out__8__PS CYREG_PRT0_PS\r
+#define SCSI_Out__8__SHIFT 1u\r
+#define SCSI_Out__8__SLW CYREG_PRT0_SLW\r
+#define SCSI_Out__9__AG CYREG_PRT0_AG\r
+#define SCSI_Out__9__AMUX CYREG_PRT0_AMUX\r
+#define SCSI_Out__9__BIE CYREG_PRT0_BIE\r
+#define SCSI_Out__9__BIT_MASK CYREG_PRT0_BIT_MASK\r
+#define SCSI_Out__9__BYP CYREG_PRT0_BYP\r
+#define SCSI_Out__9__CTL CYREG_PRT0_CTL\r
+#define SCSI_Out__9__DM0 CYREG_PRT0_DM0\r
+#define SCSI_Out__9__DM1 CYREG_PRT0_DM1\r
+#define SCSI_Out__9__DM2 CYREG_PRT0_DM2\r
+#define SCSI_Out__9__DR CYREG_PRT0_DR\r
+#define SCSI_Out__9__INP_DIS CYREG_PRT0_INP_DIS\r
+#define SCSI_Out__9__INTTYPE CYREG_PICU0_INTTYPE0\r
+#define SCSI_Out__9__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG\r
+#define SCSI_Out__9__LCD_EN CYREG_PRT0_LCD_EN\r
+#define SCSI_Out__9__MASK 0x01u\r
+#define SCSI_Out__9__PC CYREG_PRT0_PC0\r
+#define SCSI_Out__9__PORT 0u\r
+#define SCSI_Out__9__PRT CYREG_PRT0_PRT\r
+#define SCSI_Out__9__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL\r
+#define SCSI_Out__9__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN\r
+#define SCSI_Out__9__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0\r
+#define SCSI_Out__9__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1\r
+#define SCSI_Out__9__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0\r
+#define SCSI_Out__9__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1\r
+#define SCSI_Out__9__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT\r
+#define SCSI_Out__9__PS CYREG_PRT0_PS\r
+#define SCSI_Out__9__SHIFT 0u\r
+#define SCSI_Out__9__SLW CYREG_PRT0_SLW\r
+#define SCSI_Out__ACK__AG CYREG_PRT0_AG\r
+#define SCSI_Out__ACK__AMUX CYREG_PRT0_AMUX\r
+#define SCSI_Out__ACK__BIE CYREG_PRT0_BIE\r
+#define SCSI_Out__ACK__BIT_MASK CYREG_PRT0_BIT_MASK\r
+#define SCSI_Out__ACK__BYP CYREG_PRT0_BYP\r
+#define SCSI_Out__ACK__CTL CYREG_PRT0_CTL\r
+#define SCSI_Out__ACK__DM0 CYREG_PRT0_DM0\r
+#define SCSI_Out__ACK__DM1 CYREG_PRT0_DM1\r
+#define SCSI_Out__ACK__DM2 CYREG_PRT0_DM2\r
+#define SCSI_Out__ACK__DR CYREG_PRT0_DR\r
+#define SCSI_Out__ACK__INP_DIS CYREG_PRT0_INP_DIS\r
+#define SCSI_Out__ACK__INTTYPE CYREG_PICU0_INTTYPE6\r
+#define SCSI_Out__ACK__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG\r
+#define SCSI_Out__ACK__LCD_EN CYREG_PRT0_LCD_EN\r
+#define SCSI_Out__ACK__MASK 0x40u\r
+#define SCSI_Out__ACK__PC CYREG_PRT0_PC6\r
+#define SCSI_Out__ACK__PORT 0u\r
+#define SCSI_Out__ACK__PRT CYREG_PRT0_PRT\r
+#define SCSI_Out__ACK__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL\r
+#define SCSI_Out__ACK__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN\r
+#define SCSI_Out__ACK__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0\r
+#define SCSI_Out__ACK__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1\r
+#define SCSI_Out__ACK__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0\r
+#define SCSI_Out__ACK__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1\r
+#define SCSI_Out__ACK__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT\r
+#define SCSI_Out__ACK__PS CYREG_PRT0_PS\r
+#define SCSI_Out__ACK__SHIFT 6u\r
+#define SCSI_Out__ACK__SLW CYREG_PRT0_SLW\r
+#define SCSI_Out__ATN__AG CYREG_PRT4_AG\r
+#define SCSI_Out__ATN__AMUX CYREG_PRT4_AMUX\r
+#define SCSI_Out__ATN__BIE CYREG_PRT4_BIE\r
+#define SCSI_Out__ATN__BIT_MASK CYREG_PRT4_BIT_MASK\r
+#define SCSI_Out__ATN__BYP CYREG_PRT4_BYP\r
+#define SCSI_Out__ATN__CTL CYREG_PRT4_CTL\r
+#define SCSI_Out__ATN__DM0 CYREG_PRT4_DM0\r
+#define SCSI_Out__ATN__DM1 CYREG_PRT4_DM1\r
+#define SCSI_Out__ATN__DM2 CYREG_PRT4_DM2\r
+#define SCSI_Out__ATN__DR CYREG_PRT4_DR\r
+#define SCSI_Out__ATN__INP_DIS CYREG_PRT4_INP_DIS\r
+#define SCSI_Out__ATN__INTTYPE CYREG_PICU4_INTTYPE2\r
+#define SCSI_Out__ATN__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG\r
+#define SCSI_Out__ATN__LCD_EN CYREG_PRT4_LCD_EN\r
+#define SCSI_Out__ATN__MASK 0x04u\r
+#define SCSI_Out__ATN__PC CYREG_PRT4_PC2\r
+#define SCSI_Out__ATN__PORT 4u\r
+#define SCSI_Out__ATN__PRT CYREG_PRT4_PRT\r
+#define SCSI_Out__ATN__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL\r
+#define SCSI_Out__ATN__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN\r
+#define SCSI_Out__ATN__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0\r
+#define SCSI_Out__ATN__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1\r
+#define SCSI_Out__ATN__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0\r
+#define SCSI_Out__ATN__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1\r
+#define SCSI_Out__ATN__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT\r
+#define SCSI_Out__ATN__PS CYREG_PRT4_PS\r
+#define SCSI_Out__ATN__SHIFT 2u\r
+#define SCSI_Out__ATN__SLW CYREG_PRT4_SLW\r
+#define SCSI_Out__BSY__AG CYREG_PRT0_AG\r
+#define SCSI_Out__BSY__AMUX CYREG_PRT0_AMUX\r
+#define SCSI_Out__BSY__BIE CYREG_PRT0_BIE\r
+#define SCSI_Out__BSY__BIT_MASK CYREG_PRT0_BIT_MASK\r
+#define SCSI_Out__BSY__BYP CYREG_PRT0_BYP\r
+#define SCSI_Out__BSY__CTL CYREG_PRT0_CTL\r
+#define SCSI_Out__BSY__DM0 CYREG_PRT0_DM0\r
+#define SCSI_Out__BSY__DM1 CYREG_PRT0_DM1\r
+#define SCSI_Out__BSY__DM2 CYREG_PRT0_DM2\r
+#define SCSI_Out__BSY__DR CYREG_PRT0_DR\r
+#define SCSI_Out__BSY__INP_DIS CYREG_PRT0_INP_DIS\r
+#define SCSI_Out__BSY__INTTYPE CYREG_PICU0_INTTYPE7\r
+#define SCSI_Out__BSY__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG\r
+#define SCSI_Out__BSY__LCD_EN CYREG_PRT0_LCD_EN\r
+#define SCSI_Out__BSY__MASK 0x80u\r
+#define SCSI_Out__BSY__PC CYREG_PRT0_PC7\r
+#define SCSI_Out__BSY__PORT 0u\r
+#define SCSI_Out__BSY__PRT CYREG_PRT0_PRT\r
+#define SCSI_Out__BSY__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL\r
+#define SCSI_Out__BSY__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN\r
+#define SCSI_Out__BSY__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0\r
+#define SCSI_Out__BSY__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1\r
+#define SCSI_Out__BSY__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0\r
+#define SCSI_Out__BSY__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1\r
+#define SCSI_Out__BSY__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT\r
+#define SCSI_Out__BSY__PS CYREG_PRT0_PS\r
+#define SCSI_Out__BSY__SHIFT 7u\r
+#define SCSI_Out__BSY__SLW CYREG_PRT0_SLW\r
+#define SCSI_Out__CD_raw__AG CYREG_PRT0_AG\r
+#define SCSI_Out__CD_raw__AMUX CYREG_PRT0_AMUX\r
+#define SCSI_Out__CD_raw__BIE CYREG_PRT0_BIE\r
+#define SCSI_Out__CD_raw__BIT_MASK CYREG_PRT0_BIT_MASK\r
+#define SCSI_Out__CD_raw__BYP CYREG_PRT0_BYP\r
+#define SCSI_Out__CD_raw__CTL CYREG_PRT0_CTL\r
+#define SCSI_Out__CD_raw__DM0 CYREG_PRT0_DM0\r
+#define SCSI_Out__CD_raw__DM1 CYREG_PRT0_DM1\r
+#define SCSI_Out__CD_raw__DM2 CYREG_PRT0_DM2\r
+#define SCSI_Out__CD_raw__DR CYREG_PRT0_DR\r
+#define SCSI_Out__CD_raw__INP_DIS CYREG_PRT0_INP_DIS\r
+#define SCSI_Out__CD_raw__INTTYPE CYREG_PICU0_INTTYPE2\r
+#define SCSI_Out__CD_raw__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG\r
+#define SCSI_Out__CD_raw__LCD_EN CYREG_PRT0_LCD_EN\r
+#define SCSI_Out__CD_raw__MASK 0x04u\r
+#define SCSI_Out__CD_raw__PC CYREG_PRT0_PC2\r
+#define SCSI_Out__CD_raw__PORT 0u\r
+#define SCSI_Out__CD_raw__PRT CYREG_PRT0_PRT\r
+#define SCSI_Out__CD_raw__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL\r
+#define SCSI_Out__CD_raw__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN\r
+#define SCSI_Out__CD_raw__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0\r
+#define SCSI_Out__CD_raw__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1\r
+#define SCSI_Out__CD_raw__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0\r
+#define SCSI_Out__CD_raw__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1\r
+#define SCSI_Out__CD_raw__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT\r
+#define SCSI_Out__CD_raw__PS CYREG_PRT0_PS\r
+#define SCSI_Out__CD_raw__SHIFT 2u\r
+#define SCSI_Out__CD_raw__SLW CYREG_PRT0_SLW\r
+#define SCSI_Out__DBP_raw__AG CYREG_PRT4_AG\r
+#define SCSI_Out__DBP_raw__AMUX CYREG_PRT4_AMUX\r
+#define SCSI_Out__DBP_raw__BIE CYREG_PRT4_BIE\r
+#define SCSI_Out__DBP_raw__BIT_MASK CYREG_PRT4_BIT_MASK\r
+#define SCSI_Out__DBP_raw__BYP CYREG_PRT4_BYP\r
+#define SCSI_Out__DBP_raw__CTL CYREG_PRT4_CTL\r
+#define SCSI_Out__DBP_raw__DM0 CYREG_PRT4_DM0\r
+#define SCSI_Out__DBP_raw__DM1 CYREG_PRT4_DM1\r
+#define SCSI_Out__DBP_raw__DM2 CYREG_PRT4_DM2\r
+#define SCSI_Out__DBP_raw__DR CYREG_PRT4_DR\r
+#define SCSI_Out__DBP_raw__INP_DIS CYREG_PRT4_INP_DIS\r
+#define SCSI_Out__DBP_raw__INTTYPE CYREG_PICU4_INTTYPE3\r
+#define SCSI_Out__DBP_raw__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG\r
+#define SCSI_Out__DBP_raw__LCD_EN CYREG_PRT4_LCD_EN\r
+#define SCSI_Out__DBP_raw__MASK 0x08u\r
+#define SCSI_Out__DBP_raw__PC CYREG_PRT4_PC3\r
+#define SCSI_Out__DBP_raw__PORT 4u\r
+#define SCSI_Out__DBP_raw__PRT CYREG_PRT4_PRT\r
+#define SCSI_Out__DBP_raw__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL\r
+#define SCSI_Out__DBP_raw__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN\r
+#define SCSI_Out__DBP_raw__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0\r
+#define SCSI_Out__DBP_raw__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1\r
+#define SCSI_Out__DBP_raw__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0\r
+#define SCSI_Out__DBP_raw__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1\r
+#define SCSI_Out__DBP_raw__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT\r
+#define SCSI_Out__DBP_raw__PS CYREG_PRT4_PS\r
+#define SCSI_Out__DBP_raw__SHIFT 3u\r
+#define SCSI_Out__DBP_raw__SLW CYREG_PRT4_SLW\r
+#define SCSI_Out__IO_raw__AG CYREG_PRT0_AG\r
+#define SCSI_Out__IO_raw__AMUX CYREG_PRT0_AMUX\r
+#define SCSI_Out__IO_raw__BIE CYREG_PRT0_BIE\r
+#define SCSI_Out__IO_raw__BIT_MASK CYREG_PRT0_BIT_MASK\r
+#define SCSI_Out__IO_raw__BYP CYREG_PRT0_BYP\r
+#define SCSI_Out__IO_raw__CTL CYREG_PRT0_CTL\r
+#define SCSI_Out__IO_raw__DM0 CYREG_PRT0_DM0\r
+#define SCSI_Out__IO_raw__DM1 CYREG_PRT0_DM1\r
+#define SCSI_Out__IO_raw__DM2 CYREG_PRT0_DM2\r
+#define SCSI_Out__IO_raw__DR CYREG_PRT0_DR\r
+#define SCSI_Out__IO_raw__INP_DIS CYREG_PRT0_INP_DIS\r
+#define SCSI_Out__IO_raw__INTTYPE CYREG_PICU0_INTTYPE0\r
+#define SCSI_Out__IO_raw__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG\r
+#define SCSI_Out__IO_raw__LCD_EN CYREG_PRT0_LCD_EN\r
+#define SCSI_Out__IO_raw__MASK 0x01u\r
+#define SCSI_Out__IO_raw__PC CYREG_PRT0_PC0\r
+#define SCSI_Out__IO_raw__PORT 0u\r
+#define SCSI_Out__IO_raw__PRT CYREG_PRT0_PRT\r
+#define SCSI_Out__IO_raw__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL\r
+#define SCSI_Out__IO_raw__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN\r
+#define SCSI_Out__IO_raw__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0\r
+#define SCSI_Out__IO_raw__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1\r
+#define SCSI_Out__IO_raw__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0\r
+#define SCSI_Out__IO_raw__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1\r
+#define SCSI_Out__IO_raw__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT\r
+#define SCSI_Out__IO_raw__PS CYREG_PRT0_PS\r
+#define SCSI_Out__IO_raw__SHIFT 0u\r
+#define SCSI_Out__IO_raw__SLW CYREG_PRT0_SLW\r
+#define SCSI_Out__MSG_raw__AG CYREG_PRT0_AG\r
+#define SCSI_Out__MSG_raw__AMUX CYREG_PRT0_AMUX\r
+#define SCSI_Out__MSG_raw__BIE CYREG_PRT0_BIE\r
+#define SCSI_Out__MSG_raw__BIT_MASK CYREG_PRT0_BIT_MASK\r
+#define SCSI_Out__MSG_raw__BYP CYREG_PRT0_BYP\r
+#define SCSI_Out__MSG_raw__CTL CYREG_PRT0_CTL\r
+#define SCSI_Out__MSG_raw__DM0 CYREG_PRT0_DM0\r
+#define SCSI_Out__MSG_raw__DM1 CYREG_PRT0_DM1\r
+#define SCSI_Out__MSG_raw__DM2 CYREG_PRT0_DM2\r
+#define SCSI_Out__MSG_raw__DR CYREG_PRT0_DR\r
+#define SCSI_Out__MSG_raw__INP_DIS CYREG_PRT0_INP_DIS\r
+#define SCSI_Out__MSG_raw__INTTYPE CYREG_PICU0_INTTYPE4\r
+#define SCSI_Out__MSG_raw__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG\r
+#define SCSI_Out__MSG_raw__LCD_EN CYREG_PRT0_LCD_EN\r
+#define SCSI_Out__MSG_raw__MASK 0x10u\r
+#define SCSI_Out__MSG_raw__PC CYREG_PRT0_PC4\r
+#define SCSI_Out__MSG_raw__PORT 0u\r
+#define SCSI_Out__MSG_raw__PRT CYREG_PRT0_PRT\r
+#define SCSI_Out__MSG_raw__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL\r
+#define SCSI_Out__MSG_raw__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN\r
+#define SCSI_Out__MSG_raw__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0\r
+#define SCSI_Out__MSG_raw__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1\r
+#define SCSI_Out__MSG_raw__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0\r
+#define SCSI_Out__MSG_raw__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1\r
+#define SCSI_Out__MSG_raw__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT\r
+#define SCSI_Out__MSG_raw__PS CYREG_PRT0_PS\r
+#define SCSI_Out__MSG_raw__SHIFT 4u\r
+#define SCSI_Out__MSG_raw__SLW CYREG_PRT0_SLW\r
+#define SCSI_Out__REQ__AG CYREG_PRT0_AG\r
+#define SCSI_Out__REQ__AMUX CYREG_PRT0_AMUX\r
+#define SCSI_Out__REQ__BIE CYREG_PRT0_BIE\r
+#define SCSI_Out__REQ__BIT_MASK CYREG_PRT0_BIT_MASK\r
+#define SCSI_Out__REQ__BYP CYREG_PRT0_BYP\r
+#define SCSI_Out__REQ__CTL CYREG_PRT0_CTL\r
+#define SCSI_Out__REQ__DM0 CYREG_PRT0_DM0\r
+#define SCSI_Out__REQ__DM1 CYREG_PRT0_DM1\r
+#define SCSI_Out__REQ__DM2 CYREG_PRT0_DM2\r
+#define SCSI_Out__REQ__DR CYREG_PRT0_DR\r
+#define SCSI_Out__REQ__INP_DIS CYREG_PRT0_INP_DIS\r
+#define SCSI_Out__REQ__INTTYPE CYREG_PICU0_INTTYPE1\r
+#define SCSI_Out__REQ__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG\r
+#define SCSI_Out__REQ__LCD_EN CYREG_PRT0_LCD_EN\r
+#define SCSI_Out__REQ__MASK 0x02u\r
+#define SCSI_Out__REQ__PC CYREG_PRT0_PC1\r
+#define SCSI_Out__REQ__PORT 0u\r
+#define SCSI_Out__REQ__PRT CYREG_PRT0_PRT\r
+#define SCSI_Out__REQ__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL\r
+#define SCSI_Out__REQ__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN\r
+#define SCSI_Out__REQ__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0\r
+#define SCSI_Out__REQ__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1\r
+#define SCSI_Out__REQ__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0\r
+#define SCSI_Out__REQ__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1\r
+#define SCSI_Out__REQ__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT\r
+#define SCSI_Out__REQ__PS CYREG_PRT0_PS\r
+#define SCSI_Out__REQ__SHIFT 1u\r
+#define SCSI_Out__REQ__SLW CYREG_PRT0_SLW\r
+#define SCSI_Out__RST__AG CYREG_PRT0_AG\r
+#define SCSI_Out__RST__AMUX CYREG_PRT0_AMUX\r
+#define SCSI_Out__RST__BIE CYREG_PRT0_BIE\r
+#define SCSI_Out__RST__BIT_MASK CYREG_PRT0_BIT_MASK\r
+#define SCSI_Out__RST__BYP CYREG_PRT0_BYP\r
+#define SCSI_Out__RST__CTL CYREG_PRT0_CTL\r
+#define SCSI_Out__RST__DM0 CYREG_PRT0_DM0\r
+#define SCSI_Out__RST__DM1 CYREG_PRT0_DM1\r
+#define SCSI_Out__RST__DM2 CYREG_PRT0_DM2\r
+#define SCSI_Out__RST__DR CYREG_PRT0_DR\r
+#define SCSI_Out__RST__INP_DIS CYREG_PRT0_INP_DIS\r
+#define SCSI_Out__RST__INTTYPE CYREG_PICU0_INTTYPE5\r
+#define SCSI_Out__RST__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG\r
+#define SCSI_Out__RST__LCD_EN CYREG_PRT0_LCD_EN\r
+#define SCSI_Out__RST__MASK 0x20u\r
+#define SCSI_Out__RST__PC CYREG_PRT0_PC5\r
+#define SCSI_Out__RST__PORT 0u\r
+#define SCSI_Out__RST__PRT CYREG_PRT0_PRT\r
+#define SCSI_Out__RST__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL\r
+#define SCSI_Out__RST__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN\r
+#define SCSI_Out__RST__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0\r
+#define SCSI_Out__RST__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1\r
+#define SCSI_Out__RST__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0\r
+#define SCSI_Out__RST__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1\r
+#define SCSI_Out__RST__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT\r
+#define SCSI_Out__RST__PS CYREG_PRT0_PS\r
+#define SCSI_Out__RST__SHIFT 5u\r
+#define SCSI_Out__RST__SLW CYREG_PRT0_SLW\r
+#define SCSI_Out__SEL__AG CYREG_PRT0_AG\r
+#define SCSI_Out__SEL__AMUX CYREG_PRT0_AMUX\r
+#define SCSI_Out__SEL__BIE CYREG_PRT0_BIE\r
+#define SCSI_Out__SEL__BIT_MASK CYREG_PRT0_BIT_MASK\r
+#define SCSI_Out__SEL__BYP CYREG_PRT0_BYP\r
+#define SCSI_Out__SEL__CTL CYREG_PRT0_CTL\r
+#define SCSI_Out__SEL__DM0 CYREG_PRT0_DM0\r
+#define SCSI_Out__SEL__DM1 CYREG_PRT0_DM1\r
+#define SCSI_Out__SEL__DM2 CYREG_PRT0_DM2\r
+#define SCSI_Out__SEL__DR CYREG_PRT0_DR\r
+#define SCSI_Out__SEL__INP_DIS CYREG_PRT0_INP_DIS\r
+#define SCSI_Out__SEL__INTTYPE CYREG_PICU0_INTTYPE3\r
+#define SCSI_Out__SEL__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG\r
+#define SCSI_Out__SEL__LCD_EN CYREG_PRT0_LCD_EN\r
+#define SCSI_Out__SEL__MASK 0x08u\r
+#define SCSI_Out__SEL__PC CYREG_PRT0_PC3\r
+#define SCSI_Out__SEL__PORT 0u\r
+#define SCSI_Out__SEL__PRT CYREG_PRT0_PRT\r
+#define SCSI_Out__SEL__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL\r
+#define SCSI_Out__SEL__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN\r
+#define SCSI_Out__SEL__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0\r
+#define SCSI_Out__SEL__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1\r
+#define SCSI_Out__SEL__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0\r
+#define SCSI_Out__SEL__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1\r
+#define SCSI_Out__SEL__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT\r
+#define SCSI_Out__SEL__PS CYREG_PRT0_PS\r
+#define SCSI_Out__SEL__SHIFT 3u\r
+#define SCSI_Out__SEL__SLW CYREG_PRT0_SLW\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__0__MASK 0x01u\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__0__POS 0\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__1__MASK 0x02u\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__1__POS 1\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB08_09_ACTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB08_09_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB08_09_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB08_09_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B1_UDB08_09_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B1_UDB08_09_MSK\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B1_UDB08_09_MSK\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B1_UDB08_09_MSK\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB08_09_MSK\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__2__MASK 0x04u\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__2__POS 2\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__3__MASK 0x08u\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__3__POS 3\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__4__MASK 0x10u\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__4__POS 4\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__5__MASK 0x20u\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__5__POS 5\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__6__MASK 0x40u\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__6__POS 6\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__7__MASK 0x80u\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__7__POS 7\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B1_UDB08_ACTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG CYREG_B1_UDB08_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B1_UDB08_ST_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG CYREG_B1_UDB08_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG CYREG_B1_UDB08_ST_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__MASK 0xFFu\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB08_MSK_ACTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B1_UDB08_MSK_ACTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG CYREG_B1_UDB08_MSK\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK 0x01u\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__0__POS 0\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB08_09_ACTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB08_09_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB08_09_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB08_09_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB08_09_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB08_09_MSK\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB08_09_MSK\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB08_09_MSK\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB08_09_MSK\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB08_ACTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB08_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB08_ST_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB08_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB08_ST_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK 0x01u\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB08_MSK\r
+#define SCSI_Out_DBx__0__AG CYREG_PRT6_AG\r
+#define SCSI_Out_DBx__0__AMUX CYREG_PRT6_AMUX\r
+#define SCSI_Out_DBx__0__BIE CYREG_PRT6_BIE\r
+#define SCSI_Out_DBx__0__BIT_MASK CYREG_PRT6_BIT_MASK\r
+#define SCSI_Out_DBx__0__BYP CYREG_PRT6_BYP\r
+#define SCSI_Out_DBx__0__CTL CYREG_PRT6_CTL\r
+#define SCSI_Out_DBx__0__DM0 CYREG_PRT6_DM0\r
+#define SCSI_Out_DBx__0__DM1 CYREG_PRT6_DM1\r
+#define SCSI_Out_DBx__0__DM2 CYREG_PRT6_DM2\r
+#define SCSI_Out_DBx__0__DR CYREG_PRT6_DR\r
+#define SCSI_Out_DBx__0__INP_DIS CYREG_PRT6_INP_DIS\r
+#define SCSI_Out_DBx__0__INTTYPE CYREG_PICU6_INTTYPE3\r
+#define SCSI_Out_DBx__0__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
+#define SCSI_Out_DBx__0__LCD_EN CYREG_PRT6_LCD_EN\r
+#define SCSI_Out_DBx__0__MASK 0x08u\r
+#define SCSI_Out_DBx__0__PC CYREG_PRT6_PC3\r
+#define SCSI_Out_DBx__0__PORT 6u\r
+#define SCSI_Out_DBx__0__PRT CYREG_PRT6_PRT\r
+#define SCSI_Out_DBx__0__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
+#define SCSI_Out_DBx__0__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
+#define SCSI_Out_DBx__0__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
+#define SCSI_Out_DBx__0__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
+#define SCSI_Out_DBx__0__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
+#define SCSI_Out_DBx__0__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
+#define SCSI_Out_DBx__0__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
+#define SCSI_Out_DBx__0__PS CYREG_PRT6_PS\r
+#define SCSI_Out_DBx__0__SHIFT 3u\r
+#define SCSI_Out_DBx__0__SLW CYREG_PRT6_SLW\r
+#define SCSI_Out_DBx__1__AG CYREG_PRT6_AG\r
+#define SCSI_Out_DBx__1__AMUX CYREG_PRT6_AMUX\r
+#define SCSI_Out_DBx__1__BIE CYREG_PRT6_BIE\r
+#define SCSI_Out_DBx__1__BIT_MASK CYREG_PRT6_BIT_MASK\r
+#define SCSI_Out_DBx__1__BYP CYREG_PRT6_BYP\r
+#define SCSI_Out_DBx__1__CTL CYREG_PRT6_CTL\r
+#define SCSI_Out_DBx__1__DM0 CYREG_PRT6_DM0\r
+#define SCSI_Out_DBx__1__DM1 CYREG_PRT6_DM1\r
+#define SCSI_Out_DBx__1__DM2 CYREG_PRT6_DM2\r
+#define SCSI_Out_DBx__1__DR CYREG_PRT6_DR\r
+#define SCSI_Out_DBx__1__INP_DIS CYREG_PRT6_INP_DIS\r
+#define SCSI_Out_DBx__1__INTTYPE CYREG_PICU6_INTTYPE2\r
+#define SCSI_Out_DBx__1__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
+#define SCSI_Out_DBx__1__LCD_EN CYREG_PRT6_LCD_EN\r
+#define SCSI_Out_DBx__1__MASK 0x04u\r
+#define SCSI_Out_DBx__1__PC CYREG_PRT6_PC2\r
+#define SCSI_Out_DBx__1__PORT 6u\r
+#define SCSI_Out_DBx__1__PRT CYREG_PRT6_PRT\r
+#define SCSI_Out_DBx__1__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
+#define SCSI_Out_DBx__1__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
+#define SCSI_Out_DBx__1__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
+#define SCSI_Out_DBx__1__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
+#define SCSI_Out_DBx__1__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
+#define SCSI_Out_DBx__1__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
+#define SCSI_Out_DBx__1__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
+#define SCSI_Out_DBx__1__PS CYREG_PRT6_PS\r
+#define SCSI_Out_DBx__1__SHIFT 2u\r
+#define SCSI_Out_DBx__1__SLW CYREG_PRT6_SLW\r
+#define SCSI_Out_DBx__2__AG CYREG_PRT6_AG\r
+#define SCSI_Out_DBx__2__AMUX CYREG_PRT6_AMUX\r
+#define SCSI_Out_DBx__2__BIE CYREG_PRT6_BIE\r
+#define SCSI_Out_DBx__2__BIT_MASK CYREG_PRT6_BIT_MASK\r
+#define SCSI_Out_DBx__2__BYP CYREG_PRT6_BYP\r
+#define SCSI_Out_DBx__2__CTL CYREG_PRT6_CTL\r
+#define SCSI_Out_DBx__2__DM0 CYREG_PRT6_DM0\r
+#define SCSI_Out_DBx__2__DM1 CYREG_PRT6_DM1\r
+#define SCSI_Out_DBx__2__DM2 CYREG_PRT6_DM2\r
+#define SCSI_Out_DBx__2__DR CYREG_PRT6_DR\r
+#define SCSI_Out_DBx__2__INP_DIS CYREG_PRT6_INP_DIS\r
+#define SCSI_Out_DBx__2__INTTYPE CYREG_PICU6_INTTYPE1\r
+#define SCSI_Out_DBx__2__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
+#define SCSI_Out_DBx__2__LCD_EN CYREG_PRT6_LCD_EN\r
+#define SCSI_Out_DBx__2__MASK 0x02u\r
+#define SCSI_Out_DBx__2__PC CYREG_PRT6_PC1\r
+#define SCSI_Out_DBx__2__PORT 6u\r
+#define SCSI_Out_DBx__2__PRT CYREG_PRT6_PRT\r
+#define SCSI_Out_DBx__2__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
+#define SCSI_Out_DBx__2__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
+#define SCSI_Out_DBx__2__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
+#define SCSI_Out_DBx__2__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
+#define SCSI_Out_DBx__2__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
+#define SCSI_Out_DBx__2__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
+#define SCSI_Out_DBx__2__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
+#define SCSI_Out_DBx__2__PS CYREG_PRT6_PS\r
+#define SCSI_Out_DBx__2__SHIFT 1u\r
+#define SCSI_Out_DBx__2__SLW CYREG_PRT6_SLW\r
+#define SCSI_Out_DBx__3__AG CYREG_PRT6_AG\r
+#define SCSI_Out_DBx__3__AMUX CYREG_PRT6_AMUX\r
+#define SCSI_Out_DBx__3__BIE CYREG_PRT6_BIE\r
+#define SCSI_Out_DBx__3__BIT_MASK CYREG_PRT6_BIT_MASK\r
+#define SCSI_Out_DBx__3__BYP CYREG_PRT6_BYP\r
+#define SCSI_Out_DBx__3__CTL CYREG_PRT6_CTL\r
+#define SCSI_Out_DBx__3__DM0 CYREG_PRT6_DM0\r
+#define SCSI_Out_DBx__3__DM1 CYREG_PRT6_DM1\r
+#define SCSI_Out_DBx__3__DM2 CYREG_PRT6_DM2\r
+#define SCSI_Out_DBx__3__DR CYREG_PRT6_DR\r
+#define SCSI_Out_DBx__3__INP_DIS CYREG_PRT6_INP_DIS\r
+#define SCSI_Out_DBx__3__INTTYPE CYREG_PICU6_INTTYPE0\r
+#define SCSI_Out_DBx__3__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
+#define SCSI_Out_DBx__3__LCD_EN CYREG_PRT6_LCD_EN\r
+#define SCSI_Out_DBx__3__MASK 0x01u\r
+#define SCSI_Out_DBx__3__PC CYREG_PRT6_PC0\r
+#define SCSI_Out_DBx__3__PORT 6u\r
+#define SCSI_Out_DBx__3__PRT CYREG_PRT6_PRT\r
+#define SCSI_Out_DBx__3__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
+#define SCSI_Out_DBx__3__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
+#define SCSI_Out_DBx__3__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
+#define SCSI_Out_DBx__3__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
+#define SCSI_Out_DBx__3__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
+#define SCSI_Out_DBx__3__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
+#define SCSI_Out_DBx__3__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
+#define SCSI_Out_DBx__3__PS CYREG_PRT6_PS\r
+#define SCSI_Out_DBx__3__SHIFT 0u\r
+#define SCSI_Out_DBx__3__SLW CYREG_PRT6_SLW\r
+#define SCSI_Out_DBx__4__AG CYREG_PRT4_AG\r
+#define SCSI_Out_DBx__4__AMUX CYREG_PRT4_AMUX\r
+#define SCSI_Out_DBx__4__BIE CYREG_PRT4_BIE\r
+#define SCSI_Out_DBx__4__BIT_MASK CYREG_PRT4_BIT_MASK\r
+#define SCSI_Out_DBx__4__BYP CYREG_PRT4_BYP\r
+#define SCSI_Out_DBx__4__CTL CYREG_PRT4_CTL\r
+#define SCSI_Out_DBx__4__DM0 CYREG_PRT4_DM0\r
+#define SCSI_Out_DBx__4__DM1 CYREG_PRT4_DM1\r
+#define SCSI_Out_DBx__4__DM2 CYREG_PRT4_DM2\r
+#define SCSI_Out_DBx__4__DR CYREG_PRT4_DR\r
+#define SCSI_Out_DBx__4__INP_DIS CYREG_PRT4_INP_DIS\r
+#define SCSI_Out_DBx__4__INTTYPE CYREG_PICU4_INTTYPE7\r
+#define SCSI_Out_DBx__4__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG\r
+#define SCSI_Out_DBx__4__LCD_EN CYREG_PRT4_LCD_EN\r
+#define SCSI_Out_DBx__4__MASK 0x80u\r
+#define SCSI_Out_DBx__4__PC CYREG_PRT4_PC7\r
+#define SCSI_Out_DBx__4__PORT 4u\r
+#define SCSI_Out_DBx__4__PRT CYREG_PRT4_PRT\r
+#define SCSI_Out_DBx__4__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL\r
+#define SCSI_Out_DBx__4__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN\r
+#define SCSI_Out_DBx__4__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0\r
+#define SCSI_Out_DBx__4__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1\r
+#define SCSI_Out_DBx__4__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0\r
+#define SCSI_Out_DBx__4__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1\r
+#define SCSI_Out_DBx__4__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT\r
+#define SCSI_Out_DBx__4__PS CYREG_PRT4_PS\r
+#define SCSI_Out_DBx__4__SHIFT 7u\r
+#define SCSI_Out_DBx__4__SLW CYREG_PRT4_SLW\r
+#define SCSI_Out_DBx__5__AG CYREG_PRT4_AG\r
+#define SCSI_Out_DBx__5__AMUX CYREG_PRT4_AMUX\r
+#define SCSI_Out_DBx__5__BIE CYREG_PRT4_BIE\r
+#define SCSI_Out_DBx__5__BIT_MASK CYREG_PRT4_BIT_MASK\r
+#define SCSI_Out_DBx__5__BYP CYREG_PRT4_BYP\r
+#define SCSI_Out_DBx__5__CTL CYREG_PRT4_CTL\r
+#define SCSI_Out_DBx__5__DM0 CYREG_PRT4_DM0\r
+#define SCSI_Out_DBx__5__DM1 CYREG_PRT4_DM1\r
+#define SCSI_Out_DBx__5__DM2 CYREG_PRT4_DM2\r
+#define SCSI_Out_DBx__5__DR CYREG_PRT4_DR\r
+#define SCSI_Out_DBx__5__INP_DIS CYREG_PRT4_INP_DIS\r
+#define SCSI_Out_DBx__5__INTTYPE CYREG_PICU4_INTTYPE6\r
+#define SCSI_Out_DBx__5__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG\r
+#define SCSI_Out_DBx__5__LCD_EN CYREG_PRT4_LCD_EN\r
+#define SCSI_Out_DBx__5__MASK 0x40u\r
+#define SCSI_Out_DBx__5__PC CYREG_PRT4_PC6\r
+#define SCSI_Out_DBx__5__PORT 4u\r
+#define SCSI_Out_DBx__5__PRT CYREG_PRT4_PRT\r
+#define SCSI_Out_DBx__5__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL\r
+#define SCSI_Out_DBx__5__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN\r
+#define SCSI_Out_DBx__5__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0\r
+#define SCSI_Out_DBx__5__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1\r
+#define SCSI_Out_DBx__5__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0\r
+#define SCSI_Out_DBx__5__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1\r
+#define SCSI_Out_DBx__5__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT\r
+#define SCSI_Out_DBx__5__PS CYREG_PRT4_PS\r
+#define SCSI_Out_DBx__5__SHIFT 6u\r
+#define SCSI_Out_DBx__5__SLW CYREG_PRT4_SLW\r
+#define SCSI_Out_DBx__6__AG CYREG_PRT4_AG\r
+#define SCSI_Out_DBx__6__AMUX CYREG_PRT4_AMUX\r
+#define SCSI_Out_DBx__6__BIE CYREG_PRT4_BIE\r
+#define SCSI_Out_DBx__6__BIT_MASK CYREG_PRT4_BIT_MASK\r
+#define SCSI_Out_DBx__6__BYP CYREG_PRT4_BYP\r
+#define SCSI_Out_DBx__6__CTL CYREG_PRT4_CTL\r
+#define SCSI_Out_DBx__6__DM0 CYREG_PRT4_DM0\r
+#define SCSI_Out_DBx__6__DM1 CYREG_PRT4_DM1\r
+#define SCSI_Out_DBx__6__DM2 CYREG_PRT4_DM2\r
+#define SCSI_Out_DBx__6__DR CYREG_PRT4_DR\r
+#define SCSI_Out_DBx__6__INP_DIS CYREG_PRT4_INP_DIS\r
+#define SCSI_Out_DBx__6__INTTYPE CYREG_PICU4_INTTYPE5\r
+#define SCSI_Out_DBx__6__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG\r
+#define SCSI_Out_DBx__6__LCD_EN CYREG_PRT4_LCD_EN\r
+#define SCSI_Out_DBx__6__MASK 0x20u\r
+#define SCSI_Out_DBx__6__PC CYREG_PRT4_PC5\r
+#define SCSI_Out_DBx__6__PORT 4u\r
+#define SCSI_Out_DBx__6__PRT CYREG_PRT4_PRT\r
+#define SCSI_Out_DBx__6__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL\r
+#define SCSI_Out_DBx__6__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN\r
+#define SCSI_Out_DBx__6__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0\r
+#define SCSI_Out_DBx__6__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1\r
+#define SCSI_Out_DBx__6__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0\r
+#define SCSI_Out_DBx__6__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1\r
+#define SCSI_Out_DBx__6__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT\r
+#define SCSI_Out_DBx__6__PS CYREG_PRT4_PS\r
+#define SCSI_Out_DBx__6__SHIFT 5u\r
+#define SCSI_Out_DBx__6__SLW CYREG_PRT4_SLW\r
+#define SCSI_Out_DBx__7__AG CYREG_PRT4_AG\r
+#define SCSI_Out_DBx__7__AMUX CYREG_PRT4_AMUX\r
+#define SCSI_Out_DBx__7__BIE CYREG_PRT4_BIE\r
+#define SCSI_Out_DBx__7__BIT_MASK CYREG_PRT4_BIT_MASK\r
+#define SCSI_Out_DBx__7__BYP CYREG_PRT4_BYP\r
+#define SCSI_Out_DBx__7__CTL CYREG_PRT4_CTL\r
+#define SCSI_Out_DBx__7__DM0 CYREG_PRT4_DM0\r
+#define SCSI_Out_DBx__7__DM1 CYREG_PRT4_DM1\r
+#define SCSI_Out_DBx__7__DM2 CYREG_PRT4_DM2\r
+#define SCSI_Out_DBx__7__DR CYREG_PRT4_DR\r
+#define SCSI_Out_DBx__7__INP_DIS CYREG_PRT4_INP_DIS\r
+#define SCSI_Out_DBx__7__INTTYPE CYREG_PICU4_INTTYPE4\r
+#define SCSI_Out_DBx__7__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG\r
+#define SCSI_Out_DBx__7__LCD_EN CYREG_PRT4_LCD_EN\r
+#define SCSI_Out_DBx__7__MASK 0x10u\r
+#define SCSI_Out_DBx__7__PC CYREG_PRT4_PC4\r
+#define SCSI_Out_DBx__7__PORT 4u\r
+#define SCSI_Out_DBx__7__PRT CYREG_PRT4_PRT\r
+#define SCSI_Out_DBx__7__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL\r
+#define SCSI_Out_DBx__7__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN\r
+#define SCSI_Out_DBx__7__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0\r
+#define SCSI_Out_DBx__7__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1\r
+#define SCSI_Out_DBx__7__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0\r
+#define SCSI_Out_DBx__7__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1\r
+#define SCSI_Out_DBx__7__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT\r
+#define SCSI_Out_DBx__7__PS CYREG_PRT4_PS\r
+#define SCSI_Out_DBx__7__SHIFT 4u\r
+#define SCSI_Out_DBx__7__SLW CYREG_PRT4_SLW\r
+#define SCSI_Out_DBx__DB0__AG CYREG_PRT6_AG\r
+#define SCSI_Out_DBx__DB0__AMUX CYREG_PRT6_AMUX\r
+#define SCSI_Out_DBx__DB0__BIE CYREG_PRT6_BIE\r
+#define SCSI_Out_DBx__DB0__BIT_MASK CYREG_PRT6_BIT_MASK\r
+#define SCSI_Out_DBx__DB0__BYP CYREG_PRT6_BYP\r
+#define SCSI_Out_DBx__DB0__CTL CYREG_PRT6_CTL\r
+#define SCSI_Out_DBx__DB0__DM0 CYREG_PRT6_DM0\r
+#define SCSI_Out_DBx__DB0__DM1 CYREG_PRT6_DM1\r
+#define SCSI_Out_DBx__DB0__DM2 CYREG_PRT6_DM2\r
+#define SCSI_Out_DBx__DB0__DR CYREG_PRT6_DR\r
+#define SCSI_Out_DBx__DB0__INP_DIS CYREG_PRT6_INP_DIS\r
+#define SCSI_Out_DBx__DB0__INTTYPE CYREG_PICU6_INTTYPE3\r
+#define SCSI_Out_DBx__DB0__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
+#define SCSI_Out_DBx__DB0__LCD_EN CYREG_PRT6_LCD_EN\r
+#define SCSI_Out_DBx__DB0__MASK 0x08u\r
+#define SCSI_Out_DBx__DB0__PC CYREG_PRT6_PC3\r
+#define SCSI_Out_DBx__DB0__PORT 6u\r
+#define SCSI_Out_DBx__DB0__PRT CYREG_PRT6_PRT\r
+#define SCSI_Out_DBx__DB0__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
+#define SCSI_Out_DBx__DB0__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
+#define SCSI_Out_DBx__DB0__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
+#define SCSI_Out_DBx__DB0__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
+#define SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
+#define SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
+#define SCSI_Out_DBx__DB0__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
+#define SCSI_Out_DBx__DB0__PS CYREG_PRT6_PS\r
+#define SCSI_Out_DBx__DB0__SHIFT 3u\r
+#define SCSI_Out_DBx__DB0__SLW CYREG_PRT6_SLW\r
+#define SCSI_Out_DBx__DB1__AG CYREG_PRT6_AG\r
+#define SCSI_Out_DBx__DB1__AMUX CYREG_PRT6_AMUX\r
+#define SCSI_Out_DBx__DB1__BIE CYREG_PRT6_BIE\r
+#define SCSI_Out_DBx__DB1__BIT_MASK CYREG_PRT6_BIT_MASK\r
+#define SCSI_Out_DBx__DB1__BYP CYREG_PRT6_BYP\r
+#define SCSI_Out_DBx__DB1__CTL CYREG_PRT6_CTL\r
+#define SCSI_Out_DBx__DB1__DM0 CYREG_PRT6_DM0\r
+#define SCSI_Out_DBx__DB1__DM1 CYREG_PRT6_DM1\r
+#define SCSI_Out_DBx__DB1__DM2 CYREG_PRT6_DM2\r
+#define SCSI_Out_DBx__DB1__DR CYREG_PRT6_DR\r
+#define SCSI_Out_DBx__DB1__INP_DIS CYREG_PRT6_INP_DIS\r
+#define SCSI_Out_DBx__DB1__INTTYPE CYREG_PICU6_INTTYPE2\r
+#define SCSI_Out_DBx__DB1__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
+#define SCSI_Out_DBx__DB1__LCD_EN CYREG_PRT6_LCD_EN\r
+#define SCSI_Out_DBx__DB1__MASK 0x04u\r
+#define SCSI_Out_DBx__DB1__PC CYREG_PRT6_PC2\r
+#define SCSI_Out_DBx__DB1__PORT 6u\r
+#define SCSI_Out_DBx__DB1__PRT CYREG_PRT6_PRT\r
+#define SCSI_Out_DBx__DB1__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
+#define SCSI_Out_DBx__DB1__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
+#define SCSI_Out_DBx__DB1__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
+#define SCSI_Out_DBx__DB1__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
+#define SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
+#define SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
+#define SCSI_Out_DBx__DB1__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
+#define SCSI_Out_DBx__DB1__PS CYREG_PRT6_PS\r
+#define SCSI_Out_DBx__DB1__SHIFT 2u\r
+#define SCSI_Out_DBx__DB1__SLW CYREG_PRT6_SLW\r
+#define SCSI_Out_DBx__DB2__AG CYREG_PRT6_AG\r
+#define SCSI_Out_DBx__DB2__AMUX CYREG_PRT6_AMUX\r
+#define SCSI_Out_DBx__DB2__BIE CYREG_PRT6_BIE\r
+#define SCSI_Out_DBx__DB2__BIT_MASK CYREG_PRT6_BIT_MASK\r
+#define SCSI_Out_DBx__DB2__BYP CYREG_PRT6_BYP\r
+#define SCSI_Out_DBx__DB2__CTL CYREG_PRT6_CTL\r
+#define SCSI_Out_DBx__DB2__DM0 CYREG_PRT6_DM0\r
+#define SCSI_Out_DBx__DB2__DM1 CYREG_PRT6_DM1\r
+#define SCSI_Out_DBx__DB2__DM2 CYREG_PRT6_DM2\r
+#define SCSI_Out_DBx__DB2__DR CYREG_PRT6_DR\r
+#define SCSI_Out_DBx__DB2__INP_DIS CYREG_PRT6_INP_DIS\r
+#define SCSI_Out_DBx__DB2__INTTYPE CYREG_PICU6_INTTYPE1\r
+#define SCSI_Out_DBx__DB2__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
+#define SCSI_Out_DBx__DB2__LCD_EN CYREG_PRT6_LCD_EN\r
+#define SCSI_Out_DBx__DB2__MASK 0x02u\r
+#define SCSI_Out_DBx__DB2__PC CYREG_PRT6_PC1\r
+#define SCSI_Out_DBx__DB2__PORT 6u\r
+#define SCSI_Out_DBx__DB2__PRT CYREG_PRT6_PRT\r
+#define SCSI_Out_DBx__DB2__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
+#define SCSI_Out_DBx__DB2__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
+#define SCSI_Out_DBx__DB2__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
+#define SCSI_Out_DBx__DB2__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
+#define SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
+#define SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
+#define SCSI_Out_DBx__DB2__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
+#define SCSI_Out_DBx__DB2__PS CYREG_PRT6_PS\r
+#define SCSI_Out_DBx__DB2__SHIFT 1u\r
+#define SCSI_Out_DBx__DB2__SLW CYREG_PRT6_SLW\r
+#define SCSI_Out_DBx__DB3__AG CYREG_PRT6_AG\r
+#define SCSI_Out_DBx__DB3__AMUX CYREG_PRT6_AMUX\r
+#define SCSI_Out_DBx__DB3__BIE CYREG_PRT6_BIE\r
+#define SCSI_Out_DBx__DB3__BIT_MASK CYREG_PRT6_BIT_MASK\r
+#define SCSI_Out_DBx__DB3__BYP CYREG_PRT6_BYP\r
+#define SCSI_Out_DBx__DB3__CTL CYREG_PRT6_CTL\r
+#define SCSI_Out_DBx__DB3__DM0 CYREG_PRT6_DM0\r
+#define SCSI_Out_DBx__DB3__DM1 CYREG_PRT6_DM1\r
+#define SCSI_Out_DBx__DB3__DM2 CYREG_PRT6_DM2\r
+#define SCSI_Out_DBx__DB3__DR CYREG_PRT6_DR\r
+#define SCSI_Out_DBx__DB3__INP_DIS CYREG_PRT6_INP_DIS\r
+#define SCSI_Out_DBx__DB3__INTTYPE CYREG_PICU6_INTTYPE0\r
+#define SCSI_Out_DBx__DB3__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
+#define SCSI_Out_DBx__DB3__LCD_EN CYREG_PRT6_LCD_EN\r
+#define SCSI_Out_DBx__DB3__MASK 0x01u\r
+#define SCSI_Out_DBx__DB3__PC CYREG_PRT6_PC0\r
+#define SCSI_Out_DBx__DB3__PORT 6u\r
+#define SCSI_Out_DBx__DB3__PRT CYREG_PRT6_PRT\r
+#define SCSI_Out_DBx__DB3__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
+#define SCSI_Out_DBx__DB3__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
+#define SCSI_Out_DBx__DB3__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
+#define SCSI_Out_DBx__DB3__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
+#define SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
+#define SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
+#define SCSI_Out_DBx__DB3__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
+#define SCSI_Out_DBx__DB3__PS CYREG_PRT6_PS\r
+#define SCSI_Out_DBx__DB3__SHIFT 0u\r
+#define SCSI_Out_DBx__DB3__SLW CYREG_PRT6_SLW\r
+#define SCSI_Out_DBx__DB4__AG CYREG_PRT4_AG\r
+#define SCSI_Out_DBx__DB4__AMUX CYREG_PRT4_AMUX\r
+#define SCSI_Out_DBx__DB4__BIE CYREG_PRT4_BIE\r
+#define SCSI_Out_DBx__DB4__BIT_MASK CYREG_PRT4_BIT_MASK\r
+#define SCSI_Out_DBx__DB4__BYP CYREG_PRT4_BYP\r
+#define SCSI_Out_DBx__DB4__CTL CYREG_PRT4_CTL\r
+#define SCSI_Out_DBx__DB4__DM0 CYREG_PRT4_DM0\r
+#define SCSI_Out_DBx__DB4__DM1 CYREG_PRT4_DM1\r
+#define SCSI_Out_DBx__DB4__DM2 CYREG_PRT4_DM2\r
+#define SCSI_Out_DBx__DB4__DR CYREG_PRT4_DR\r
+#define SCSI_Out_DBx__DB4__INP_DIS CYREG_PRT4_INP_DIS\r
+#define SCSI_Out_DBx__DB4__INTTYPE CYREG_PICU4_INTTYPE7\r
+#define SCSI_Out_DBx__DB4__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG\r
+#define SCSI_Out_DBx__DB4__LCD_EN CYREG_PRT4_LCD_EN\r
+#define SCSI_Out_DBx__DB4__MASK 0x80u\r
+#define SCSI_Out_DBx__DB4__PC CYREG_PRT4_PC7\r
+#define SCSI_Out_DBx__DB4__PORT 4u\r
+#define SCSI_Out_DBx__DB4__PRT CYREG_PRT4_PRT\r
+#define SCSI_Out_DBx__DB4__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL\r
+#define SCSI_Out_DBx__DB4__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN\r
+#define SCSI_Out_DBx__DB4__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0\r
+#define SCSI_Out_DBx__DB4__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1\r
+#define SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0\r
+#define SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1\r
+#define SCSI_Out_DBx__DB4__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT\r
+#define SCSI_Out_DBx__DB4__PS CYREG_PRT4_PS\r
+#define SCSI_Out_DBx__DB4__SHIFT 7u\r
+#define SCSI_Out_DBx__DB4__SLW CYREG_PRT4_SLW\r
+#define SCSI_Out_DBx__DB5__AG CYREG_PRT4_AG\r
+#define SCSI_Out_DBx__DB5__AMUX CYREG_PRT4_AMUX\r
+#define SCSI_Out_DBx__DB5__BIE CYREG_PRT4_BIE\r
+#define SCSI_Out_DBx__DB5__BIT_MASK CYREG_PRT4_BIT_MASK\r
+#define SCSI_Out_DBx__DB5__BYP CYREG_PRT4_BYP\r
+#define SCSI_Out_DBx__DB5__CTL CYREG_PRT4_CTL\r
+#define SCSI_Out_DBx__DB5__DM0 CYREG_PRT4_DM0\r
+#define SCSI_Out_DBx__DB5__DM1 CYREG_PRT4_DM1\r
+#define SCSI_Out_DBx__DB5__DM2 CYREG_PRT4_DM2\r
+#define SCSI_Out_DBx__DB5__DR CYREG_PRT4_DR\r
+#define SCSI_Out_DBx__DB5__INP_DIS CYREG_PRT4_INP_DIS\r
+#define SCSI_Out_DBx__DB5__INTTYPE CYREG_PICU4_INTTYPE6\r
+#define SCSI_Out_DBx__DB5__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG\r
+#define SCSI_Out_DBx__DB5__LCD_EN CYREG_PRT4_LCD_EN\r
+#define SCSI_Out_DBx__DB5__MASK 0x40u\r
+#define SCSI_Out_DBx__DB5__PC CYREG_PRT4_PC6\r
+#define SCSI_Out_DBx__DB5__PORT 4u\r
+#define SCSI_Out_DBx__DB5__PRT CYREG_PRT4_PRT\r
+#define SCSI_Out_DBx__DB5__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL\r
+#define SCSI_Out_DBx__DB5__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN\r
+#define SCSI_Out_DBx__DB5__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0\r
+#define SCSI_Out_DBx__DB5__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1\r
+#define SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0\r
+#define SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1\r
+#define SCSI_Out_DBx__DB5__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT\r
+#define SCSI_Out_DBx__DB5__PS CYREG_PRT4_PS\r
+#define SCSI_Out_DBx__DB5__SHIFT 6u\r
+#define SCSI_Out_DBx__DB5__SLW CYREG_PRT4_SLW\r
+#define SCSI_Out_DBx__DB6__AG CYREG_PRT4_AG\r
+#define SCSI_Out_DBx__DB6__AMUX CYREG_PRT4_AMUX\r
+#define SCSI_Out_DBx__DB6__BIE CYREG_PRT4_BIE\r
+#define SCSI_Out_DBx__DB6__BIT_MASK CYREG_PRT4_BIT_MASK\r
+#define SCSI_Out_DBx__DB6__BYP CYREG_PRT4_BYP\r
+#define SCSI_Out_DBx__DB6__CTL CYREG_PRT4_CTL\r
+#define SCSI_Out_DBx__DB6__DM0 CYREG_PRT4_DM0\r
+#define SCSI_Out_DBx__DB6__DM1 CYREG_PRT4_DM1\r
+#define SCSI_Out_DBx__DB6__DM2 CYREG_PRT4_DM2\r
+#define SCSI_Out_DBx__DB6__DR CYREG_PRT4_DR\r
+#define SCSI_Out_DBx__DB6__INP_DIS CYREG_PRT4_INP_DIS\r
+#define SCSI_Out_DBx__DB6__INTTYPE CYREG_PICU4_INTTYPE5\r
+#define SCSI_Out_DBx__DB6__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG\r
+#define SCSI_Out_DBx__DB6__LCD_EN CYREG_PRT4_LCD_EN\r
+#define SCSI_Out_DBx__DB6__MASK 0x20u\r
+#define SCSI_Out_DBx__DB6__PC CYREG_PRT4_PC5\r
+#define SCSI_Out_DBx__DB6__PORT 4u\r
+#define SCSI_Out_DBx__DB6__PRT CYREG_PRT4_PRT\r
+#define SCSI_Out_DBx__DB6__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL\r
+#define SCSI_Out_DBx__DB6__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN\r
+#define SCSI_Out_DBx__DB6__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0\r
+#define SCSI_Out_DBx__DB6__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1\r
+#define SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0\r
+#define SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1\r
+#define SCSI_Out_DBx__DB6__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT\r
+#define SCSI_Out_DBx__DB6__PS CYREG_PRT4_PS\r
+#define SCSI_Out_DBx__DB6__SHIFT 5u\r
+#define SCSI_Out_DBx__DB6__SLW CYREG_PRT4_SLW\r
+#define SCSI_Out_DBx__DB7__AG CYREG_PRT4_AG\r
+#define SCSI_Out_DBx__DB7__AMUX CYREG_PRT4_AMUX\r
+#define SCSI_Out_DBx__DB7__BIE CYREG_PRT4_BIE\r
+#define SCSI_Out_DBx__DB7__BIT_MASK CYREG_PRT4_BIT_MASK\r
+#define SCSI_Out_DBx__DB7__BYP CYREG_PRT4_BYP\r
+#define SCSI_Out_DBx__DB7__CTL CYREG_PRT4_CTL\r
+#define SCSI_Out_DBx__DB7__DM0 CYREG_PRT4_DM0\r
+#define SCSI_Out_DBx__DB7__DM1 CYREG_PRT4_DM1\r
+#define SCSI_Out_DBx__DB7__DM2 CYREG_PRT4_DM2\r
+#define SCSI_Out_DBx__DB7__DR CYREG_PRT4_DR\r
+#define SCSI_Out_DBx__DB7__INP_DIS CYREG_PRT4_INP_DIS\r
+#define SCSI_Out_DBx__DB7__INTTYPE CYREG_PICU4_INTTYPE4\r
+#define SCSI_Out_DBx__DB7__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG\r
+#define SCSI_Out_DBx__DB7__LCD_EN CYREG_PRT4_LCD_EN\r
+#define SCSI_Out_DBx__DB7__MASK 0x10u\r
+#define SCSI_Out_DBx__DB7__PC CYREG_PRT4_PC4\r
+#define SCSI_Out_DBx__DB7__PORT 4u\r
+#define SCSI_Out_DBx__DB7__PRT CYREG_PRT4_PRT\r
+#define SCSI_Out_DBx__DB7__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL\r
+#define SCSI_Out_DBx__DB7__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN\r
+#define SCSI_Out_DBx__DB7__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0\r
+#define SCSI_Out_DBx__DB7__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1\r
+#define SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0\r
+#define SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1\r
+#define SCSI_Out_DBx__DB7__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT\r
+#define SCSI_Out_DBx__DB7__PS CYREG_PRT4_PS\r
+#define SCSI_Out_DBx__DB7__SHIFT 4u\r
+#define SCSI_Out_DBx__DB7__SLW CYREG_PRT4_SLW\r
+\r
+/* SD_RX_DMA */\r
+#define SD_RX_DMA__DRQ_CTL CYREG_IDMUX_DRQ_CTL0\r
+#define SD_RX_DMA__DRQ_NUMBER 2u\r
+#define SD_RX_DMA__NUMBEROF_TDS 0u\r
+#define SD_RX_DMA__PRIORITY 0u\r
+#define SD_RX_DMA__TERMIN_EN 0u\r
+#define SD_RX_DMA__TERMIN_SEL 0u\r
+#define SD_RX_DMA__TERMOUT0_EN 1u\r
+#define SD_RX_DMA__TERMOUT0_SEL 2u\r
+#define SD_RX_DMA__TERMOUT1_EN 0u\r
+#define SD_RX_DMA__TERMOUT1_SEL 0u\r
+#define SD_RX_DMA_COMPLETE__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
+#define SD_RX_DMA_COMPLETE__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
+#define SD_RX_DMA_COMPLETE__INTC_MASK 0x20u\r
+#define SD_RX_DMA_COMPLETE__INTC_NUMBER 5u\r
+#define SD_RX_DMA_COMPLETE__INTC_PRIOR_NUM 7u\r
+#define SD_RX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_5\r
+#define SD_RX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
+#define SD_RX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
+\r
+/* SD_TX_DMA */\r
+#define SD_TX_DMA__DRQ_CTL CYREG_IDMUX_DRQ_CTL0\r
+#define SD_TX_DMA__DRQ_NUMBER 3u\r
+#define SD_TX_DMA__NUMBEROF_TDS 0u\r
+#define SD_TX_DMA__PRIORITY 1u\r
+#define SD_TX_DMA__TERMIN_EN 0u\r
+#define SD_TX_DMA__TERMIN_SEL 0u\r
+#define SD_TX_DMA__TERMOUT0_EN 1u\r
+#define SD_TX_DMA__TERMOUT0_SEL 3u\r
+#define SD_TX_DMA__TERMOUT1_EN 0u\r
+#define SD_TX_DMA__TERMOUT1_SEL 0u\r
+#define SD_TX_DMA_COMPLETE__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
+#define SD_TX_DMA_COMPLETE__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
+#define SD_TX_DMA_COMPLETE__INTC_MASK 0x40u\r
+#define SD_TX_DMA_COMPLETE__INTC_NUMBER 6u\r
+#define SD_TX_DMA_COMPLETE__INTC_PRIOR_NUM 7u\r
+#define SD_TX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_6\r
+#define SD_TX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
+#define SD_TX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
+\r
+/* SCSI_Noise */\r
+#define SCSI_Noise__0__AG CYREG_PRT12_AG\r
+#define SCSI_Noise__0__BIE CYREG_PRT12_BIE\r
+#define SCSI_Noise__0__BIT_MASK CYREG_PRT12_BIT_MASK\r
+#define SCSI_Noise__0__BYP CYREG_PRT12_BYP\r
+#define SCSI_Noise__0__DM0 CYREG_PRT12_DM0\r
+#define SCSI_Noise__0__DM1 CYREG_PRT12_DM1\r
+#define SCSI_Noise__0__DM2 CYREG_PRT12_DM2\r
+#define SCSI_Noise__0__DR CYREG_PRT12_DR\r
+#define SCSI_Noise__0__INP_DIS CYREG_PRT12_INP_DIS\r
+#define SCSI_Noise__0__INTTYPE CYREG_PICU12_INTTYPE5\r
+#define SCSI_Noise__0__MASK 0x20u\r
+#define SCSI_Noise__0__PC CYREG_PRT12_PC5\r
+#define SCSI_Noise__0__PORT 12u\r
+#define SCSI_Noise__0__PRT CYREG_PRT12_PRT\r
+#define SCSI_Noise__0__PRTDSI__DBL_SYNC_IN CYREG_PRT12_DBL_SYNC_IN\r
+#define SCSI_Noise__0__PRTDSI__OE_SEL0 CYREG_PRT12_OE_SEL0\r
+#define SCSI_Noise__0__PRTDSI__OE_SEL1 CYREG_PRT12_OE_SEL1\r
+#define SCSI_Noise__0__PRTDSI__OUT_SEL0 CYREG_PRT12_OUT_SEL0\r
+#define SCSI_Noise__0__PRTDSI__OUT_SEL1 CYREG_PRT12_OUT_SEL1\r
+#define SCSI_Noise__0__PRTDSI__SYNC_OUT CYREG_PRT12_SYNC_OUT\r
+#define SCSI_Noise__0__PS CYREG_PRT12_PS\r
+#define SCSI_Noise__0__SHIFT 5u\r
+#define SCSI_Noise__0__SIO_CFG CYREG_PRT12_SIO_CFG\r
+#define SCSI_Noise__0__SIO_DIFF CYREG_PRT12_SIO_DIFF\r
+#define SCSI_Noise__0__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN\r
+#define SCSI_Noise__0__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ\r
+#define SCSI_Noise__0__SLW CYREG_PRT12_SLW\r
+#define SCSI_Noise__1__AG CYREG_PRT6_AG\r
+#define SCSI_Noise__1__AMUX CYREG_PRT6_AMUX\r
+#define SCSI_Noise__1__BIE CYREG_PRT6_BIE\r
+#define SCSI_Noise__1__BIT_MASK CYREG_PRT6_BIT_MASK\r
+#define SCSI_Noise__1__BYP CYREG_PRT6_BYP\r
+#define SCSI_Noise__1__CTL CYREG_PRT6_CTL\r
+#define SCSI_Noise__1__DM0 CYREG_PRT6_DM0\r
+#define SCSI_Noise__1__DM1 CYREG_PRT6_DM1\r
+#define SCSI_Noise__1__DM2 CYREG_PRT6_DM2\r
+#define SCSI_Noise__1__DR CYREG_PRT6_DR\r
+#define SCSI_Noise__1__INP_DIS CYREG_PRT6_INP_DIS\r
+#define SCSI_Noise__1__INTTYPE CYREG_PICU6_INTTYPE4\r
+#define SCSI_Noise__1__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
+#define SCSI_Noise__1__LCD_EN CYREG_PRT6_LCD_EN\r
+#define SCSI_Noise__1__MASK 0x10u\r
+#define SCSI_Noise__1__PC CYREG_PRT6_PC4\r
+#define SCSI_Noise__1__PORT 6u\r
+#define SCSI_Noise__1__PRT CYREG_PRT6_PRT\r
+#define SCSI_Noise__1__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
+#define SCSI_Noise__1__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
+#define SCSI_Noise__1__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
+#define SCSI_Noise__1__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
+#define SCSI_Noise__1__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
+#define SCSI_Noise__1__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
+#define SCSI_Noise__1__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
+#define SCSI_Noise__1__PS CYREG_PRT6_PS\r
+#define SCSI_Noise__1__SHIFT 4u\r
+#define SCSI_Noise__1__SLW CYREG_PRT6_SLW\r
+#define SCSI_Noise__2__AG CYREG_PRT5_AG\r
+#define SCSI_Noise__2__AMUX CYREG_PRT5_AMUX\r
+#define SCSI_Noise__2__BIE CYREG_PRT5_BIE\r
+#define SCSI_Noise__2__BIT_MASK CYREG_PRT5_BIT_MASK\r
+#define SCSI_Noise__2__BYP CYREG_PRT5_BYP\r
+#define SCSI_Noise__2__CTL CYREG_PRT5_CTL\r
+#define SCSI_Noise__2__DM0 CYREG_PRT5_DM0\r
+#define SCSI_Noise__2__DM1 CYREG_PRT5_DM1\r
+#define SCSI_Noise__2__DM2 CYREG_PRT5_DM2\r
+#define SCSI_Noise__2__DR CYREG_PRT5_DR\r
+#define SCSI_Noise__2__INP_DIS CYREG_PRT5_INP_DIS\r
+#define SCSI_Noise__2__INTTYPE CYREG_PICU5_INTTYPE0\r
+#define SCSI_Noise__2__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG\r
+#define SCSI_Noise__2__LCD_EN CYREG_PRT5_LCD_EN\r
+#define SCSI_Noise__2__MASK 0x01u\r
+#define SCSI_Noise__2__PC CYREG_PRT5_PC0\r
+#define SCSI_Noise__2__PORT 5u\r
+#define SCSI_Noise__2__PRT CYREG_PRT5_PRT\r
+#define SCSI_Noise__2__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL\r
+#define SCSI_Noise__2__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN\r
+#define SCSI_Noise__2__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0\r
+#define SCSI_Noise__2__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1\r
+#define SCSI_Noise__2__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0\r
+#define SCSI_Noise__2__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1\r
+#define SCSI_Noise__2__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT\r
+#define SCSI_Noise__2__PS CYREG_PRT5_PS\r
+#define SCSI_Noise__2__SHIFT 0u\r
+#define SCSI_Noise__2__SLW CYREG_PRT5_SLW\r
+#define SCSI_Noise__3__AG CYREG_PRT6_AG\r
+#define SCSI_Noise__3__AMUX CYREG_PRT6_AMUX\r
+#define SCSI_Noise__3__BIE CYREG_PRT6_BIE\r
+#define SCSI_Noise__3__BIT_MASK CYREG_PRT6_BIT_MASK\r
+#define SCSI_Noise__3__BYP CYREG_PRT6_BYP\r
+#define SCSI_Noise__3__CTL CYREG_PRT6_CTL\r
+#define SCSI_Noise__3__DM0 CYREG_PRT6_DM0\r
+#define SCSI_Noise__3__DM1 CYREG_PRT6_DM1\r
+#define SCSI_Noise__3__DM2 CYREG_PRT6_DM2\r
+#define SCSI_Noise__3__DR CYREG_PRT6_DR\r
+#define SCSI_Noise__3__INP_DIS CYREG_PRT6_INP_DIS\r
+#define SCSI_Noise__3__INTTYPE CYREG_PICU6_INTTYPE6\r
+#define SCSI_Noise__3__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
+#define SCSI_Noise__3__LCD_EN CYREG_PRT6_LCD_EN\r
+#define SCSI_Noise__3__MASK 0x40u\r
+#define SCSI_Noise__3__PC CYREG_PRT6_PC6\r
+#define SCSI_Noise__3__PORT 6u\r
+#define SCSI_Noise__3__PRT CYREG_PRT6_PRT\r
+#define SCSI_Noise__3__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
+#define SCSI_Noise__3__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
+#define SCSI_Noise__3__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
+#define SCSI_Noise__3__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
+#define SCSI_Noise__3__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
+#define SCSI_Noise__3__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
+#define SCSI_Noise__3__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
+#define SCSI_Noise__3__PS CYREG_PRT6_PS\r
+#define SCSI_Noise__3__SHIFT 6u\r
+#define SCSI_Noise__3__SLW CYREG_PRT6_SLW\r
+#define SCSI_Noise__4__AG CYREG_PRT6_AG\r
+#define SCSI_Noise__4__AMUX CYREG_PRT6_AMUX\r
+#define SCSI_Noise__4__BIE CYREG_PRT6_BIE\r
+#define SCSI_Noise__4__BIT_MASK CYREG_PRT6_BIT_MASK\r
+#define SCSI_Noise__4__BYP CYREG_PRT6_BYP\r
+#define SCSI_Noise__4__CTL CYREG_PRT6_CTL\r
+#define SCSI_Noise__4__DM0 CYREG_PRT6_DM0\r
+#define SCSI_Noise__4__DM1 CYREG_PRT6_DM1\r
+#define SCSI_Noise__4__DM2 CYREG_PRT6_DM2\r
+#define SCSI_Noise__4__DR CYREG_PRT6_DR\r
+#define SCSI_Noise__4__INP_DIS CYREG_PRT6_INP_DIS\r
+#define SCSI_Noise__4__INTTYPE CYREG_PICU6_INTTYPE5\r
+#define SCSI_Noise__4__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
+#define SCSI_Noise__4__LCD_EN CYREG_PRT6_LCD_EN\r
+#define SCSI_Noise__4__MASK 0x20u\r
+#define SCSI_Noise__4__PC CYREG_PRT6_PC5\r
+#define SCSI_Noise__4__PORT 6u\r
+#define SCSI_Noise__4__PRT CYREG_PRT6_PRT\r
+#define SCSI_Noise__4__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
+#define SCSI_Noise__4__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
+#define SCSI_Noise__4__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
+#define SCSI_Noise__4__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
+#define SCSI_Noise__4__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
+#define SCSI_Noise__4__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
+#define SCSI_Noise__4__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
+#define SCSI_Noise__4__PS CYREG_PRT6_PS\r
+#define SCSI_Noise__4__SHIFT 5u\r
+#define SCSI_Noise__4__SLW CYREG_PRT6_SLW\r
+#define SCSI_Noise__ACK__AG CYREG_PRT6_AG\r
+#define SCSI_Noise__ACK__AMUX CYREG_PRT6_AMUX\r
+#define SCSI_Noise__ACK__BIE CYREG_PRT6_BIE\r
+#define SCSI_Noise__ACK__BIT_MASK CYREG_PRT6_BIT_MASK\r
+#define SCSI_Noise__ACK__BYP CYREG_PRT6_BYP\r
+#define SCSI_Noise__ACK__CTL CYREG_PRT6_CTL\r
+#define SCSI_Noise__ACK__DM0 CYREG_PRT6_DM0\r
+#define SCSI_Noise__ACK__DM1 CYREG_PRT6_DM1\r
+#define SCSI_Noise__ACK__DM2 CYREG_PRT6_DM2\r
+#define SCSI_Noise__ACK__DR CYREG_PRT6_DR\r
+#define SCSI_Noise__ACK__INP_DIS CYREG_PRT6_INP_DIS\r
+#define SCSI_Noise__ACK__INTTYPE CYREG_PICU6_INTTYPE5\r
+#define SCSI_Noise__ACK__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
+#define SCSI_Noise__ACK__LCD_EN CYREG_PRT6_LCD_EN\r
+#define SCSI_Noise__ACK__MASK 0x20u\r
+#define SCSI_Noise__ACK__PC CYREG_PRT6_PC5\r
+#define SCSI_Noise__ACK__PORT 6u\r
+#define SCSI_Noise__ACK__PRT CYREG_PRT6_PRT\r
+#define SCSI_Noise__ACK__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
+#define SCSI_Noise__ACK__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
+#define SCSI_Noise__ACK__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
+#define SCSI_Noise__ACK__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
+#define SCSI_Noise__ACK__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
+#define SCSI_Noise__ACK__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
+#define SCSI_Noise__ACK__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
+#define SCSI_Noise__ACK__PS CYREG_PRT6_PS\r
+#define SCSI_Noise__ACK__SHIFT 5u\r
+#define SCSI_Noise__ACK__SLW CYREG_PRT6_SLW\r
+#define SCSI_Noise__ATN__AG CYREG_PRT12_AG\r
+#define SCSI_Noise__ATN__BIE CYREG_PRT12_BIE\r
+#define SCSI_Noise__ATN__BIT_MASK CYREG_PRT12_BIT_MASK\r
+#define SCSI_Noise__ATN__BYP CYREG_PRT12_BYP\r
+#define SCSI_Noise__ATN__DM0 CYREG_PRT12_DM0\r
+#define SCSI_Noise__ATN__DM1 CYREG_PRT12_DM1\r
+#define SCSI_Noise__ATN__DM2 CYREG_PRT12_DM2\r
+#define SCSI_Noise__ATN__DR CYREG_PRT12_DR\r
+#define SCSI_Noise__ATN__INP_DIS CYREG_PRT12_INP_DIS\r
+#define SCSI_Noise__ATN__INTTYPE CYREG_PICU12_INTTYPE5\r
+#define SCSI_Noise__ATN__MASK 0x20u\r
+#define SCSI_Noise__ATN__PC CYREG_PRT12_PC5\r
+#define SCSI_Noise__ATN__PORT 12u\r
+#define SCSI_Noise__ATN__PRT CYREG_PRT12_PRT\r
+#define SCSI_Noise__ATN__PRTDSI__DBL_SYNC_IN CYREG_PRT12_DBL_SYNC_IN\r
+#define SCSI_Noise__ATN__PRTDSI__OE_SEL0 CYREG_PRT12_OE_SEL0\r
+#define SCSI_Noise__ATN__PRTDSI__OE_SEL1 CYREG_PRT12_OE_SEL1\r
+#define SCSI_Noise__ATN__PRTDSI__OUT_SEL0 CYREG_PRT12_OUT_SEL0\r
+#define SCSI_Noise__ATN__PRTDSI__OUT_SEL1 CYREG_PRT12_OUT_SEL1\r
+#define SCSI_Noise__ATN__PRTDSI__SYNC_OUT CYREG_PRT12_SYNC_OUT\r
+#define SCSI_Noise__ATN__PS CYREG_PRT12_PS\r
+#define SCSI_Noise__ATN__SHIFT 5u\r
+#define SCSI_Noise__ATN__SIO_CFG CYREG_PRT12_SIO_CFG\r
+#define SCSI_Noise__ATN__SIO_DIFF CYREG_PRT12_SIO_DIFF\r
+#define SCSI_Noise__ATN__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN\r
+#define SCSI_Noise__ATN__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ\r
+#define SCSI_Noise__ATN__SLW CYREG_PRT12_SLW\r
+#define SCSI_Noise__BSY__AG CYREG_PRT6_AG\r
+#define SCSI_Noise__BSY__AMUX CYREG_PRT6_AMUX\r
+#define SCSI_Noise__BSY__BIE CYREG_PRT6_BIE\r
+#define SCSI_Noise__BSY__BIT_MASK CYREG_PRT6_BIT_MASK\r
+#define SCSI_Noise__BSY__BYP CYREG_PRT6_BYP\r
+#define SCSI_Noise__BSY__CTL CYREG_PRT6_CTL\r
+#define SCSI_Noise__BSY__DM0 CYREG_PRT6_DM0\r
+#define SCSI_Noise__BSY__DM1 CYREG_PRT6_DM1\r
+#define SCSI_Noise__BSY__DM2 CYREG_PRT6_DM2\r
+#define SCSI_Noise__BSY__DR CYREG_PRT6_DR\r
+#define SCSI_Noise__BSY__INP_DIS CYREG_PRT6_INP_DIS\r
+#define SCSI_Noise__BSY__INTTYPE CYREG_PICU6_INTTYPE4\r
+#define SCSI_Noise__BSY__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
+#define SCSI_Noise__BSY__LCD_EN CYREG_PRT6_LCD_EN\r
+#define SCSI_Noise__BSY__MASK 0x10u\r
+#define SCSI_Noise__BSY__PC CYREG_PRT6_PC4\r
+#define SCSI_Noise__BSY__PORT 6u\r
+#define SCSI_Noise__BSY__PRT CYREG_PRT6_PRT\r
+#define SCSI_Noise__BSY__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
+#define SCSI_Noise__BSY__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
+#define SCSI_Noise__BSY__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
+#define SCSI_Noise__BSY__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
+#define SCSI_Noise__BSY__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
+#define SCSI_Noise__BSY__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
+#define SCSI_Noise__BSY__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
+#define SCSI_Noise__BSY__PS CYREG_PRT6_PS\r
+#define SCSI_Noise__BSY__SHIFT 4u\r
+#define SCSI_Noise__BSY__SLW CYREG_PRT6_SLW\r
+#define SCSI_Noise__RST__AG CYREG_PRT6_AG\r
+#define SCSI_Noise__RST__AMUX CYREG_PRT6_AMUX\r
+#define SCSI_Noise__RST__BIE CYREG_PRT6_BIE\r
+#define SCSI_Noise__RST__BIT_MASK CYREG_PRT6_BIT_MASK\r
+#define SCSI_Noise__RST__BYP CYREG_PRT6_BYP\r
+#define SCSI_Noise__RST__CTL CYREG_PRT6_CTL\r
+#define SCSI_Noise__RST__DM0 CYREG_PRT6_DM0\r
+#define SCSI_Noise__RST__DM1 CYREG_PRT6_DM1\r
+#define SCSI_Noise__RST__DM2 CYREG_PRT6_DM2\r
+#define SCSI_Noise__RST__DR CYREG_PRT6_DR\r
+#define SCSI_Noise__RST__INP_DIS CYREG_PRT6_INP_DIS\r
+#define SCSI_Noise__RST__INTTYPE CYREG_PICU6_INTTYPE6\r
+#define SCSI_Noise__RST__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
+#define SCSI_Noise__RST__LCD_EN CYREG_PRT6_LCD_EN\r
+#define SCSI_Noise__RST__MASK 0x40u\r
+#define SCSI_Noise__RST__PC CYREG_PRT6_PC6\r
+#define SCSI_Noise__RST__PORT 6u\r
+#define SCSI_Noise__RST__PRT CYREG_PRT6_PRT\r
+#define SCSI_Noise__RST__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
+#define SCSI_Noise__RST__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
+#define SCSI_Noise__RST__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
+#define SCSI_Noise__RST__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
+#define SCSI_Noise__RST__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
+#define SCSI_Noise__RST__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
+#define SCSI_Noise__RST__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
+#define SCSI_Noise__RST__PS CYREG_PRT6_PS\r
+#define SCSI_Noise__RST__SHIFT 6u\r
+#define SCSI_Noise__RST__SLW CYREG_PRT6_SLW\r
+#define SCSI_Noise__SEL__AG CYREG_PRT5_AG\r
+#define SCSI_Noise__SEL__AMUX CYREG_PRT5_AMUX\r
+#define SCSI_Noise__SEL__BIE CYREG_PRT5_BIE\r
+#define SCSI_Noise__SEL__BIT_MASK CYREG_PRT5_BIT_MASK\r
+#define SCSI_Noise__SEL__BYP CYREG_PRT5_BYP\r
+#define SCSI_Noise__SEL__CTL CYREG_PRT5_CTL\r
+#define SCSI_Noise__SEL__DM0 CYREG_PRT5_DM0\r
+#define SCSI_Noise__SEL__DM1 CYREG_PRT5_DM1\r
+#define SCSI_Noise__SEL__DM2 CYREG_PRT5_DM2\r
+#define SCSI_Noise__SEL__DR CYREG_PRT5_DR\r
+#define SCSI_Noise__SEL__INP_DIS CYREG_PRT5_INP_DIS\r
+#define SCSI_Noise__SEL__INTTYPE CYREG_PICU5_INTTYPE0\r
+#define SCSI_Noise__SEL__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG\r
+#define SCSI_Noise__SEL__LCD_EN CYREG_PRT5_LCD_EN\r
+#define SCSI_Noise__SEL__MASK 0x01u\r
+#define SCSI_Noise__SEL__PC CYREG_PRT5_PC0\r
+#define SCSI_Noise__SEL__PORT 5u\r
+#define SCSI_Noise__SEL__PRT CYREG_PRT5_PRT\r
+#define SCSI_Noise__SEL__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL\r
+#define SCSI_Noise__SEL__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN\r
+#define SCSI_Noise__SEL__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0\r
+#define SCSI_Noise__SEL__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1\r
+#define SCSI_Noise__SEL__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0\r
+#define SCSI_Noise__SEL__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1\r
+#define SCSI_Noise__SEL__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT\r
+#define SCSI_Noise__SEL__PS CYREG_PRT5_PS\r
+#define SCSI_Noise__SEL__SHIFT 0u\r
+#define SCSI_Noise__SEL__SLW CYREG_PRT5_SLW\r
+\r
/* scsiTarget */\r
#define scsiTarget_datapath__16BIT_A0_REG CYREG_B0_UDB00_01_A0\r
#define scsiTarget_datapath__16BIT_A1_REG CYREG_B0_UDB00_01_A1\r
#define scsiTarget_StatusReg__STATUS_CONTROL_REG CYREG_B0_UDB07_ST_CTL\r
#define scsiTarget_StatusReg__STATUS_REG CYREG_B0_UDB07_ST\r
\r
+/* Debug_Timer */\r
+#define Debug_Timer_Interrupt__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
+#define Debug_Timer_Interrupt__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
+#define Debug_Timer_Interrupt__INTC_MASK 0x01u\r
+#define Debug_Timer_Interrupt__INTC_NUMBER 0u\r
+#define Debug_Timer_Interrupt__INTC_PRIOR_NUM 7u\r
+#define Debug_Timer_Interrupt__INTC_PRIOR_REG CYREG_NVIC_PRI_0\r
+#define Debug_Timer_Interrupt__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
+#define Debug_Timer_Interrupt__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
+#define Debug_Timer_TimerHW__CAP0 CYREG_TMR0_CAP0\r
+#define Debug_Timer_TimerHW__CAP1 CYREG_TMR0_CAP1\r
+#define Debug_Timer_TimerHW__CFG0 CYREG_TMR0_CFG0\r
+#define Debug_Timer_TimerHW__CFG1 CYREG_TMR0_CFG1\r
+#define Debug_Timer_TimerHW__CFG2 CYREG_TMR0_CFG2\r
+#define Debug_Timer_TimerHW__CNT_CMP0 CYREG_TMR0_CNT_CMP0\r
+#define Debug_Timer_TimerHW__CNT_CMP1 CYREG_TMR0_CNT_CMP1\r
+#define Debug_Timer_TimerHW__PER0 CYREG_TMR0_PER0\r
+#define Debug_Timer_TimerHW__PER1 CYREG_TMR0_PER1\r
+#define Debug_Timer_TimerHW__PM_ACT_CFG CYREG_PM_ACT_CFG3\r
+#define Debug_Timer_TimerHW__PM_ACT_MSK 0x01u\r
+#define Debug_Timer_TimerHW__PM_STBY_CFG CYREG_PM_STBY_CFG3\r
+#define Debug_Timer_TimerHW__PM_STBY_MSK 0x01u\r
+#define Debug_Timer_TimerHW__RT0 CYREG_TMR0_RT0\r
+#define Debug_Timer_TimerHW__RT1 CYREG_TMR0_RT1\r
+#define Debug_Timer_TimerHW__SR0 CYREG_TMR0_SR0\r
+\r
+/* SCSI_RX_DMA */\r
+#define SCSI_RX_DMA__DRQ_CTL CYREG_IDMUX_DRQ_CTL0\r
+#define SCSI_RX_DMA__DRQ_NUMBER 0u\r
+#define SCSI_RX_DMA__NUMBEROF_TDS 0u\r
+#define SCSI_RX_DMA__PRIORITY 2u\r
+#define SCSI_RX_DMA__TERMIN_EN 0u\r
+#define SCSI_RX_DMA__TERMIN_SEL 0u\r
+#define SCSI_RX_DMA__TERMOUT0_EN 1u\r
+#define SCSI_RX_DMA__TERMOUT0_SEL 0u\r
+#define SCSI_RX_DMA__TERMOUT1_EN 0u\r
+#define SCSI_RX_DMA__TERMOUT1_SEL 0u\r
+#define SCSI_RX_DMA_COMPLETE__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
+#define SCSI_RX_DMA_COMPLETE__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
+#define SCSI_RX_DMA_COMPLETE__INTC_MASK 0x04u\r
+#define SCSI_RX_DMA_COMPLETE__INTC_NUMBER 2u\r
+#define SCSI_RX_DMA_COMPLETE__INTC_PRIOR_NUM 7u\r
+#define SCSI_RX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_2\r
+#define SCSI_RX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
+#define SCSI_RX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
+\r
+/* SCSI_TX_DMA */\r
+#define SCSI_TX_DMA__DRQ_CTL CYREG_IDMUX_DRQ_CTL0\r
+#define SCSI_TX_DMA__DRQ_NUMBER 1u\r
+#define SCSI_TX_DMA__NUMBEROF_TDS 0u\r
+#define SCSI_TX_DMA__PRIORITY 2u\r
+#define SCSI_TX_DMA__TERMIN_EN 0u\r
+#define SCSI_TX_DMA__TERMIN_SEL 0u\r
+#define SCSI_TX_DMA__TERMOUT0_EN 1u\r
+#define SCSI_TX_DMA__TERMOUT0_SEL 1u\r
+#define SCSI_TX_DMA__TERMOUT1_EN 0u\r
+#define SCSI_TX_DMA__TERMOUT1_SEL 0u\r
+#define SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
+#define SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
+#define SCSI_TX_DMA_COMPLETE__INTC_MASK 0x10u\r
+#define SCSI_TX_DMA_COMPLETE__INTC_NUMBER 4u\r
+#define SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM 7u\r
+#define SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_4\r
+#define SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
+#define SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
+\r
+/* SD_Data_Clk */\r
+#define SD_Data_Clk__CFG0 CYREG_CLKDIST_DCFG0_CFG0\r
+#define SD_Data_Clk__CFG1 CYREG_CLKDIST_DCFG0_CFG1\r
+#define SD_Data_Clk__CFG2 CYREG_CLKDIST_DCFG0_CFG2\r
+#define SD_Data_Clk__CFG2_SRC_SEL_MASK 0x07u\r
+#define SD_Data_Clk__INDEX 0x00u\r
+#define SD_Data_Clk__PM_ACT_CFG CYREG_PM_ACT_CFG2\r
+#define SD_Data_Clk__PM_ACT_MSK 0x01u\r
+#define SD_Data_Clk__PM_STBY_CFG CYREG_PM_STBY_CFG2\r
+#define SD_Data_Clk__PM_STBY_MSK 0x01u\r
+\r
/* timer_clock */\r
#define timer_clock__CFG0 CYREG_CLKDIST_DCFG2_CFG0\r
#define timer_clock__CFG1 CYREG_CLKDIST_DCFG2_CFG1\r
#define timer_clock__PM_STBY_CFG CYREG_PM_STBY_CFG2\r
#define timer_clock__PM_STBY_MSK 0x04u\r
\r
+/* SCSI_RST_ISR */\r
+#define SCSI_RST_ISR__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
+#define SCSI_RST_ISR__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
+#define SCSI_RST_ISR__INTC_MASK 0x02u\r
+#define SCSI_RST_ISR__INTC_NUMBER 1u\r
+#define SCSI_RST_ISR__INTC_PRIOR_NUM 7u\r
+#define SCSI_RST_ISR__INTC_PRIOR_REG CYREG_NVIC_PRI_1\r
+#define SCSI_RST_ISR__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
+#define SCSI_RST_ISR__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
+\r
+/* SCSI_SEL_ISR */\r
+#define SCSI_SEL_ISR__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
+#define SCSI_SEL_ISR__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
+#define SCSI_SEL_ISR__INTC_MASK 0x08u\r
+#define SCSI_SEL_ISR__INTC_NUMBER 3u\r
+#define SCSI_SEL_ISR__INTC_PRIOR_NUM 7u\r
+#define SCSI_SEL_ISR__INTC_PRIOR_REG CYREG_NVIC_PRI_3\r
+#define SCSI_SEL_ISR__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
+#define SCSI_SEL_ISR__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
+\r
+/* SCSI_Filtered */\r
+#define SCSI_Filtered_sts_sts_reg__0__MASK 0x01u\r
+#define SCSI_Filtered_sts_sts_reg__0__POS 0\r
+#define SCSI_Filtered_sts_sts_reg__1__MASK 0x02u\r
+#define SCSI_Filtered_sts_sts_reg__1__POS 1\r
+#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB02_03_ACTL\r
+#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB02_03_ST\r
+#define SCSI_Filtered_sts_sts_reg__2__MASK 0x04u\r
+#define SCSI_Filtered_sts_sts_reg__2__POS 2\r
+#define SCSI_Filtered_sts_sts_reg__3__MASK 0x08u\r
+#define SCSI_Filtered_sts_sts_reg__3__POS 3\r
+#define SCSI_Filtered_sts_sts_reg__4__MASK 0x10u\r
+#define SCSI_Filtered_sts_sts_reg__4__POS 4\r
+#define SCSI_Filtered_sts_sts_reg__MASK 0x1Fu\r
+#define SCSI_Filtered_sts_sts_reg__MASK_REG CYREG_B0_UDB02_MSK\r
+#define SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB02_ACTL\r
+#define SCSI_Filtered_sts_sts_reg__STATUS_REG CYREG_B0_UDB02_ST\r
+\r
+/* SCSI_CTL_PHASE */\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK 0x01u\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS 0\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK 0x02u\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS 1\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB05_06_ACTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB05_06_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB05_06_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB05_06_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB05_06_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB05_06_MSK\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB05_06_MSK\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB05_06_MSK\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB05_06_MSK\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK 0x04u\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS 2\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB05_ACTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB05_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB05_ST_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB05_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB05_ST_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK 0x07u\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB05_MSK\r
+\r
+/* SCSI_Glitch_Ctl */\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK 0x01u\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS 0\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB07_08_ACTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB07_08_CTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB07_08_CTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB07_08_CTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB07_08_CTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB07_08_MSK\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB07_08_MSK\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB07_08_MSK\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB07_08_MSK\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB07_ACTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB07_CTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB07_ST_CTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB07_CTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB07_ST_CTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK 0x01u\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB07_MSK_ACTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB07_MSK_ACTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB07_MSK\r
+\r
+/* SCSI_Parity_Error */\r
+#define SCSI_Parity_Error_sts_sts_reg__0__MASK 0x01u\r
+#define SCSI_Parity_Error_sts_sts_reg__0__POS 0\r
+#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB01_02_ACTL\r
+#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB01_02_ST\r
+#define SCSI_Parity_Error_sts_sts_reg__MASK 0x01u\r
+#define SCSI_Parity_Error_sts_sts_reg__MASK_REG CYREG_B0_UDB01_MSK\r
+#define SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB01_ACTL\r
+#define SCSI_Parity_Error_sts_sts_reg__STATUS_REG CYREG_B0_UDB01_ST\r
+\r
/* Miscellaneous */\r
#define BCLK__BUS_CLK__HZ 50000000U\r
#define BCLK__BUS_CLK__KHZ 50000U\r
#define BCLK__BUS_CLK__MHZ 50U\r
#define CY_PROJECT_NAME "SCSI2SD"\r
-#define CY_VERSION "PSoC Creator 4.1"\r
+#define CY_VERSION "PSoC Creator 4.2"\r
#define CYDEV_CHIP_DIE_LEOPARD 1u\r
-#define CYDEV_CHIP_DIE_PSOC4A 16u\r
+#define CYDEV_CHIP_DIE_PSOC4A 18u\r
#define CYDEV_CHIP_DIE_PSOC5LP 2u\r
#define CYDEV_CHIP_DIE_PSOC5TM 3u\r
#define CYDEV_CHIP_DIE_TMA4 4u\r
#define CYDEV_CHIP_FAMILY_USED CYDEV_CHIP_FAMILY_PSOC5\r
#define CYDEV_CHIP_JTAG_ID 0x2E133069u\r
#define CYDEV_CHIP_MEMBER_3A 1u\r
-#define CYDEV_CHIP_MEMBER_4A 16u\r
-#define CYDEV_CHIP_MEMBER_4D 12u\r
+#define CYDEV_CHIP_MEMBER_4A 18u\r
+#define CYDEV_CHIP_MEMBER_4D 13u\r
#define CYDEV_CHIP_MEMBER_4E 6u\r
-#define CYDEV_CHIP_MEMBER_4F 17u\r
+#define CYDEV_CHIP_MEMBER_4F 19u\r
#define CYDEV_CHIP_MEMBER_4G 4u\r
-#define CYDEV_CHIP_MEMBER_4H 15u\r
-#define CYDEV_CHIP_MEMBER_4I 21u\r
-#define CYDEV_CHIP_MEMBER_4J 13u\r
-#define CYDEV_CHIP_MEMBER_4K 14u\r
-#define CYDEV_CHIP_MEMBER_4L 20u\r
-#define CYDEV_CHIP_MEMBER_4M 19u\r
-#define CYDEV_CHIP_MEMBER_4N 9u\r
+#define CYDEV_CHIP_MEMBER_4H 17u\r
+#define CYDEV_CHIP_MEMBER_4I 23u\r
+#define CYDEV_CHIP_MEMBER_4J 14u\r
+#define CYDEV_CHIP_MEMBER_4K 15u\r
+#define CYDEV_CHIP_MEMBER_4L 22u\r
+#define CYDEV_CHIP_MEMBER_4M 21u\r
+#define CYDEV_CHIP_MEMBER_4N 10u\r
#define CYDEV_CHIP_MEMBER_4O 7u\r
-#define CYDEV_CHIP_MEMBER_4P 18u\r
-#define CYDEV_CHIP_MEMBER_4Q 11u\r
+#define CYDEV_CHIP_MEMBER_4P 20u\r
+#define CYDEV_CHIP_MEMBER_4Q 12u\r
#define CYDEV_CHIP_MEMBER_4R 8u\r
-#define CYDEV_CHIP_MEMBER_4S 10u\r
+#define CYDEV_CHIP_MEMBER_4S 11u\r
+#define CYDEV_CHIP_MEMBER_4T 9u\r
#define CYDEV_CHIP_MEMBER_4U 5u\r
+#define CYDEV_CHIP_MEMBER_4V 16u\r
#define CYDEV_CHIP_MEMBER_5A 3u\r
#define CYDEV_CHIP_MEMBER_5B 2u\r
-#define CYDEV_CHIP_MEMBER_6A 22u\r
-#define CYDEV_CHIP_MEMBER_FM3 26u\r
-#define CYDEV_CHIP_MEMBER_FM4 27u\r
-#define CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE1 23u\r
-#define CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE2 24u\r
-#define CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE3 25u\r
+#define CYDEV_CHIP_MEMBER_6A 24u\r
+#define CYDEV_CHIP_MEMBER_FM3 28u\r
+#define CYDEV_CHIP_MEMBER_FM4 29u\r
+#define CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE1 25u\r
+#define CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE2 26u\r
+#define CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE3 27u\r
#define CYDEV_CHIP_MEMBER_UNKNOWN 0u\r
#define CYDEV_CHIP_MEMBER_USED CYDEV_CHIP_MEMBER_5B\r
#define CYDEV_CHIP_DIE_EXPECT CYDEV_CHIP_MEMBER_USED\r
#define CYDEV_CHIP_REVISION_4A_ES0 17u\r
#define CYDEV_CHIP_REVISION_4A_PRODUCTION 17u\r
#define CYDEV_CHIP_REVISION_4D_PRODUCTION 0u\r
+#define CYDEV_CHIP_REVISION_4E_CCG2_NO_USBPD 0u\r
#define CYDEV_CHIP_REVISION_4E_PRODUCTION 0u\r
#define CYDEV_CHIP_REVISION_4F_PRODUCTION 0u\r
#define CYDEV_CHIP_REVISION_4F_PRODUCTION_256DMA 0u\r
#define CYDEV_CHIP_REVISION_4Q_PRODUCTION 0u\r
#define CYDEV_CHIP_REVISION_4R_PRODUCTION 0u\r
#define CYDEV_CHIP_REVISION_4S_PRODUCTION 0u\r
+#define CYDEV_CHIP_REVISION_4T_PRODUCTION 0u\r
#define CYDEV_CHIP_REVISION_4U_PRODUCTION 0u\r
+#define CYDEV_CHIP_REVISION_4V_PRODUCTION 0u\r
#define CYDEV_CHIP_REVISION_5A_ES0 0u\r
#define CYDEV_CHIP_REVISION_5A_ES1 1u\r
#define CYDEV_CHIP_REVISION_5A_PRODUCTION 1u\r
#define CYDEV_CHIP_REVISION_5B_ES0 0u\r
#define CYDEV_CHIP_REVISION_5B_PRODUCTION 0u\r
-#define CYDEV_CHIP_REVISION_6A_NO_UDB 0u\r
-#define CYDEV_CHIP_REVISION_6A_PRODUCTION 0u\r
+#define CYDEV_CHIP_REVISION_6A_ES 17u\r
+#define CYDEV_CHIP_REVISION_6A_NO_UDB 33u\r
+#define CYDEV_CHIP_REVISION_6A_PRODUCTION 33u\r
#define CYDEV_CHIP_REVISION_FM3_PRODUCTION 0u\r
#define CYDEV_CHIP_REVISION_FM4_PRODUCTION 0u\r
#define CYDEV_CHIP_REVISION_PDL_FM0P_TYPE1_PRODUCTION 0u\r
/*******************************************************************************\r
* File Name: cyfitter_cfg.c\r
* \r
-* PSoC Creator 4.1\r
+* PSoC Creator 4.2\r
*\r
* Description:\r
* This file contains device initialization code.\r
* This file is automatically generated by PSoC Creator.\r
*\r
********************************************************************************\r
-* Copyright (c) 2007-2017 Cypress Semiconductor. All rights reserved.\r
+* Copyright (c) 2007-2018 Cypress Semiconductor. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions, \r
* disclaimers, and limitations in the end user license agreement accompanying \r
* the software package with which this file was provided.\r
#define CYCLOCKSTART_32KHZ_ERROR 2u\r
#define CYCLOCKSTART_PLL_ERROR 3u\r
#define CYCLOCKSTART_FLL_ERROR 4u\r
+#define CYCLOCKSTART_WCO_ERROR 5u\r
\r
\r
#ifdef CY_NEED_CYCLOCKSTARTUPERROR\r
CY_CFG_UNUSED\r
static void CyClockStartupError(uint8 errorCode)\r
{\r
- /* To remove the compiler warning if errorCode not used. */\r
-#if defined(CY_PSOC3) && (CY_PSOC3)\r
+ /* To remove the compiler warning if errorCode not used. */\r
errorCode = errorCode;\r
-#else\r
- (void)errorCode;\r
-#endif /* CY_PSOC3 */\r
\r
/* If we have a clock startup error (bad MHz crystal, PLL lock, etc.), */\r
/* we will end up here to allow the customer to implement something to */\r
\r
\r
/* Set Flash Cycles based on max possible frequency in case a glitch occurs during ClockSetup(). */\r
- CY_SET_XTND_REG8((void CYFAR *)(CYREG_CACHE_CC_CTL), (((CYDEV_INSTRUCT_CACHE_ENABLED) != 0) ? 0x01u : 0x00u));\r
+ CY_SET_XTND_REG8((void CYFAR *)(CYREG_CACHE_CC_CTL), (((CYDEV_INSTRUCT_CACHE_ENABLED) != 0) ? 0x61u : 0x60u));\r
/* Setup clocks based on selections from Clock DWR */\r
ClockSetup();\r
/* Set Flash Cycles based on newly configured 50.00MHz Bus Clock. */\r
/*******************************************************************************\r
* File Name: cyfitter_cfg.h\r
* \r
-* PSoC Creator 4.1\r
+* PSoC Creator 4.2\r
*\r
* Description:\r
* This file provides basic startup and mux configuration settings\r
* This file is automatically generated by PSoC Creator.\r
*\r
********************************************************************************\r
-* Copyright (c) 2007-2017 Cypress Semiconductor. All rights reserved.\r
+* Copyright (c) 2007-2018 Cypress Semiconductor. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions, \r
* disclaimers, and limitations in the end user license agreement accompanying \r
* the software package with which this file was provided.\r
/*******************************************************************************\r
* File Name: cyfittergnu.inc\r
* \r
-* PSoC Creator 4.1\r
+* PSoC Creator 4.2\r
*\r
* Description:\r
* \r
* This file is automatically generated by PSoC Creator.\r
*\r
********************************************************************************\r
-* Copyright (c) 2007-2017 Cypress Semiconductor. All rights reserved.\r
+* Copyright (c) 2007-2018 Cypress Semiconductor. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions, \r
* disclaimers, and limitations in the end user license agreement accompanying \r
* the software package with which this file was provided.\r
.include "cydevicegnu.inc"\r
.include "cydevicegnu_trm.inc"\r
\r
-/* Debug_Timer_Interrupt */\r
-.set Debug_Timer_Interrupt__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
-.set Debug_Timer_Interrupt__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
-.set Debug_Timer_Interrupt__INTC_MASK, 0x01\r
-.set Debug_Timer_Interrupt__INTC_NUMBER, 0\r
-.set Debug_Timer_Interrupt__INTC_PRIOR_NUM, 7\r
-.set Debug_Timer_Interrupt__INTC_PRIOR_REG, CYREG_NVIC_PRI_0\r
-.set Debug_Timer_Interrupt__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
-.set Debug_Timer_Interrupt__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
-\r
-/* Debug_Timer_TimerHW */\r
-.set Debug_Timer_TimerHW__CAP0, CYREG_TMR0_CAP0\r
-.set Debug_Timer_TimerHW__CAP1, CYREG_TMR0_CAP1\r
-.set Debug_Timer_TimerHW__CFG0, CYREG_TMR0_CFG0\r
-.set Debug_Timer_TimerHW__CFG1, CYREG_TMR0_CFG1\r
-.set Debug_Timer_TimerHW__CFG2, CYREG_TMR0_CFG2\r
-.set Debug_Timer_TimerHW__CNT_CMP0, CYREG_TMR0_CNT_CMP0\r
-.set Debug_Timer_TimerHW__CNT_CMP1, CYREG_TMR0_CNT_CMP1\r
-.set Debug_Timer_TimerHW__PER0, CYREG_TMR0_PER0\r
-.set Debug_Timer_TimerHW__PER1, CYREG_TMR0_PER1\r
-.set Debug_Timer_TimerHW__PM_ACT_CFG, CYREG_PM_ACT_CFG3\r
-.set Debug_Timer_TimerHW__PM_ACT_MSK, 0x01\r
-.set Debug_Timer_TimerHW__PM_STBY_CFG, CYREG_PM_STBY_CFG3\r
-.set Debug_Timer_TimerHW__PM_STBY_MSK, 0x01\r
-.set Debug_Timer_TimerHW__RT0, CYREG_TMR0_RT0\r
-.set Debug_Timer_TimerHW__RT1, CYREG_TMR0_RT1\r
-.set Debug_Timer_TimerHW__SR0, CYREG_TMR0_SR0\r
-\r
/* LED1 */\r
.set LED1__0__INTTYPE, CYREG_PICU12_INTTYPE3\r
.set LED1__0__MASK, 0x08\r
.set LED1__SIO_REG_HIFREQ, CYREG_PRT12_SIO_REG_HIFREQ\r
.set LED1__SLW, CYREG_PRT12_SLW\r
\r
-/* SCSI_CLK */\r
-.set SCSI_CLK__CFG0, CYREG_CLKDIST_DCFG1_CFG0\r
-.set SCSI_CLK__CFG1, CYREG_CLKDIST_DCFG1_CFG1\r
-.set SCSI_CLK__CFG2, CYREG_CLKDIST_DCFG1_CFG2\r
-.set SCSI_CLK__CFG2_SRC_SEL_MASK, 0x07\r
-.set SCSI_CLK__INDEX, 0x01\r
-.set SCSI_CLK__PM_ACT_CFG, CYREG_PM_ACT_CFG2\r
-.set SCSI_CLK__PM_ACT_MSK, 0x02\r
-.set SCSI_CLK__PM_STBY_CFG, CYREG_PM_STBY_CFG2\r
-.set SCSI_CLK__PM_STBY_MSK, 0x02\r
-\r
-/* SCSI_CTL_PHASE */\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK, 0x01\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS, 0\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK, 0x02\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS, 1\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB05_06_ACTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB05_06_CTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB05_06_CTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB05_06_CTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB05_06_CTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB05_06_MSK\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB05_06_MSK\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB05_06_MSK\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB05_06_MSK\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK, 0x04\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS, 2\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB05_ACTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB05_CTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB05_ST_CTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB05_CTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB05_ST_CTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK, 0x07\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB05_MSK_ACTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB05_MSK_ACTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB05_MSK\r
-\r
-/* SCSI_Filtered */\r
-.set SCSI_Filtered_sts_sts_reg__0__MASK, 0x01\r
-.set SCSI_Filtered_sts_sts_reg__0__POS, 0\r
-.set SCSI_Filtered_sts_sts_reg__1__MASK, 0x02\r
-.set SCSI_Filtered_sts_sts_reg__1__POS, 1\r
-.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB02_03_ACTL\r
-.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB02_03_ST\r
-.set SCSI_Filtered_sts_sts_reg__2__MASK, 0x04\r
-.set SCSI_Filtered_sts_sts_reg__2__POS, 2\r
-.set SCSI_Filtered_sts_sts_reg__3__MASK, 0x08\r
-.set SCSI_Filtered_sts_sts_reg__3__POS, 3\r
-.set SCSI_Filtered_sts_sts_reg__4__MASK, 0x10\r
-.set SCSI_Filtered_sts_sts_reg__4__POS, 4\r
-.set SCSI_Filtered_sts_sts_reg__MASK, 0x1F\r
-.set SCSI_Filtered_sts_sts_reg__MASK_REG, CYREG_B0_UDB02_MSK\r
-.set SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB02_ACTL\r
-.set SCSI_Filtered_sts_sts_reg__STATUS_REG, CYREG_B0_UDB02_ST\r
+/* SD_CD */\r
+.set SD_CD__0__INTTYPE, CYREG_PICU3_INTTYPE6\r
+.set SD_CD__0__MASK, 0x40\r
+.set SD_CD__0__PC, CYREG_PRT3_PC6\r
+.set SD_CD__0__PORT, 3\r
+.set SD_CD__0__SHIFT, 6\r
+.set SD_CD__AG, CYREG_PRT3_AG\r
+.set SD_CD__AMUX, CYREG_PRT3_AMUX\r
+.set SD_CD__BIE, CYREG_PRT3_BIE\r
+.set SD_CD__BIT_MASK, CYREG_PRT3_BIT_MASK\r
+.set SD_CD__BYP, CYREG_PRT3_BYP\r
+.set SD_CD__CTL, CYREG_PRT3_CTL\r
+.set SD_CD__DM0, CYREG_PRT3_DM0\r
+.set SD_CD__DM1, CYREG_PRT3_DM1\r
+.set SD_CD__DM2, CYREG_PRT3_DM2\r
+.set SD_CD__DR, CYREG_PRT3_DR\r
+.set SD_CD__INP_DIS, CYREG_PRT3_INP_DIS\r
+.set SD_CD__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU3_BASE\r
+.set SD_CD__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG\r
+.set SD_CD__LCD_EN, CYREG_PRT3_LCD_EN\r
+.set SD_CD__MASK, 0x40\r
+.set SD_CD__PORT, 3\r
+.set SD_CD__PRT, CYREG_PRT3_PRT\r
+.set SD_CD__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL\r
+.set SD_CD__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN\r
+.set SD_CD__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0\r
+.set SD_CD__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1\r
+.set SD_CD__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0\r
+.set SD_CD__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1\r
+.set SD_CD__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT\r
+.set SD_CD__PS, CYREG_PRT3_PS\r
+.set SD_CD__SHIFT, 6\r
+.set SD_CD__SLW, CYREG_PRT3_SLW\r
\r
-/* SCSI_Glitch_Ctl */\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK, 0x01\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS, 0\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB07_08_ACTL\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB07_08_CTL\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB07_08_CTL\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB07_08_CTL\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB07_08_CTL\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB07_08_MSK\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB07_08_MSK\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB07_08_MSK\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB07_08_MSK\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB07_ACTL\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB07_CTL\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB07_ST_CTL\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB07_CTL\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB07_ST_CTL\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK, 0x01\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB07_MSK_ACTL\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB07_MSK_ACTL\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB07_MSK\r
-\r
-/* SCSI_In */\r
-.set SCSI_In__0__AG, CYREG_PRT2_AG\r
-.set SCSI_In__0__AMUX, CYREG_PRT2_AMUX\r
-.set SCSI_In__0__BIE, CYREG_PRT2_BIE\r
-.set SCSI_In__0__BIT_MASK, CYREG_PRT2_BIT_MASK\r
-.set SCSI_In__0__BYP, CYREG_PRT2_BYP\r
-.set SCSI_In__0__CTL, CYREG_PRT2_CTL\r
-.set SCSI_In__0__DM0, CYREG_PRT2_DM0\r
-.set SCSI_In__0__DM1, CYREG_PRT2_DM1\r
-.set SCSI_In__0__DM2, CYREG_PRT2_DM2\r
-.set SCSI_In__0__DR, CYREG_PRT2_DR\r
-.set SCSI_In__0__INP_DIS, CYREG_PRT2_INP_DIS\r
-.set SCSI_In__0__INTTYPE, CYREG_PICU2_INTTYPE0\r
-.set SCSI_In__0__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG\r
-.set SCSI_In__0__LCD_EN, CYREG_PRT2_LCD_EN\r
-.set SCSI_In__0__MASK, 0x01\r
-.set SCSI_In__0__PC, CYREG_PRT2_PC0\r
-.set SCSI_In__0__PORT, 2\r
-.set SCSI_In__0__PRT, CYREG_PRT2_PRT\r
-.set SCSI_In__0__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL\r
-.set SCSI_In__0__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN\r
-.set SCSI_In__0__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0\r
-.set SCSI_In__0__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1\r
-.set SCSI_In__0__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0\r
-.set SCSI_In__0__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1\r
-.set SCSI_In__0__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT\r
-.set SCSI_In__0__PS, CYREG_PRT2_PS\r
-.set SCSI_In__0__SHIFT, 0\r
-.set SCSI_In__0__SLW, CYREG_PRT2_SLW\r
-.set SCSI_In__1__AG, CYREG_PRT6_AG\r
-.set SCSI_In__1__AMUX, CYREG_PRT6_AMUX\r
-.set SCSI_In__1__BIE, CYREG_PRT6_BIE\r
-.set SCSI_In__1__BIT_MASK, CYREG_PRT6_BIT_MASK\r
-.set SCSI_In__1__BYP, CYREG_PRT6_BYP\r
-.set SCSI_In__1__CTL, CYREG_PRT6_CTL\r
-.set SCSI_In__1__DM0, CYREG_PRT6_DM0\r
-.set SCSI_In__1__DM1, CYREG_PRT6_DM1\r
-.set SCSI_In__1__DM2, CYREG_PRT6_DM2\r
-.set SCSI_In__1__DR, CYREG_PRT6_DR\r
-.set SCSI_In__1__INP_DIS, CYREG_PRT6_INP_DIS\r
-.set SCSI_In__1__INTTYPE, CYREG_PICU6_INTTYPE7\r
-.set SCSI_In__1__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG\r
-.set SCSI_In__1__LCD_EN, CYREG_PRT6_LCD_EN\r
-.set SCSI_In__1__MASK, 0x80\r
-.set SCSI_In__1__PC, CYREG_PRT6_PC7\r
-.set SCSI_In__1__PORT, 6\r
-.set SCSI_In__1__PRT, CYREG_PRT6_PRT\r
-.set SCSI_In__1__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL\r
-.set SCSI_In__1__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN\r
-.set SCSI_In__1__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0\r
-.set SCSI_In__1__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1\r
-.set SCSI_In__1__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0\r
-.set SCSI_In__1__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1\r
-.set SCSI_In__1__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT\r
-.set SCSI_In__1__PS, CYREG_PRT6_PS\r
-.set SCSI_In__1__SHIFT, 7\r
-.set SCSI_In__1__SLW, CYREG_PRT6_SLW\r
-.set SCSI_In__2__AG, CYREG_PRT5_AG\r
-.set SCSI_In__2__AMUX, CYREG_PRT5_AMUX\r
-.set SCSI_In__2__BIE, CYREG_PRT5_BIE\r
-.set SCSI_In__2__BIT_MASK, CYREG_PRT5_BIT_MASK\r
-.set SCSI_In__2__BYP, CYREG_PRT5_BYP\r
-.set SCSI_In__2__CTL, CYREG_PRT5_CTL\r
-.set SCSI_In__2__DM0, CYREG_PRT5_DM0\r
-.set SCSI_In__2__DM1, CYREG_PRT5_DM1\r
-.set SCSI_In__2__DM2, CYREG_PRT5_DM2\r
-.set SCSI_In__2__DR, CYREG_PRT5_DR\r
-.set SCSI_In__2__INP_DIS, CYREG_PRT5_INP_DIS\r
-.set SCSI_In__2__INTTYPE, CYREG_PICU5_INTTYPE1\r
-.set SCSI_In__2__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG\r
-.set SCSI_In__2__LCD_EN, CYREG_PRT5_LCD_EN\r
-.set SCSI_In__2__MASK, 0x02\r
-.set SCSI_In__2__PC, CYREG_PRT5_PC1\r
-.set SCSI_In__2__PORT, 5\r
-.set SCSI_In__2__PRT, CYREG_PRT5_PRT\r
-.set SCSI_In__2__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL\r
-.set SCSI_In__2__PRTDSI__DBL_SYNC_IN, CYREG_PRT5_DBL_SYNC_IN\r
-.set SCSI_In__2__PRTDSI__OE_SEL0, CYREG_PRT5_OE_SEL0\r
-.set SCSI_In__2__PRTDSI__OE_SEL1, CYREG_PRT5_OE_SEL1\r
-.set SCSI_In__2__PRTDSI__OUT_SEL0, CYREG_PRT5_OUT_SEL0\r
-.set SCSI_In__2__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1\r
-.set SCSI_In__2__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT\r
-.set SCSI_In__2__PS, CYREG_PRT5_PS\r
-.set SCSI_In__2__SHIFT, 1\r
-.set SCSI_In__2__SLW, CYREG_PRT5_SLW\r
-.set SCSI_In__3__AG, CYREG_PRT5_AG\r
-.set SCSI_In__3__AMUX, CYREG_PRT5_AMUX\r
-.set SCSI_In__3__BIE, CYREG_PRT5_BIE\r
-.set SCSI_In__3__BIT_MASK, CYREG_PRT5_BIT_MASK\r
-.set SCSI_In__3__BYP, CYREG_PRT5_BYP\r
-.set SCSI_In__3__CTL, CYREG_PRT5_CTL\r
-.set SCSI_In__3__DM0, CYREG_PRT5_DM0\r
-.set SCSI_In__3__DM1, CYREG_PRT5_DM1\r
-.set SCSI_In__3__DM2, CYREG_PRT5_DM2\r
-.set SCSI_In__3__DR, CYREG_PRT5_DR\r
-.set SCSI_In__3__INP_DIS, CYREG_PRT5_INP_DIS\r
-.set SCSI_In__3__INTTYPE, CYREG_PICU5_INTTYPE2\r
-.set SCSI_In__3__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG\r
-.set SCSI_In__3__LCD_EN, CYREG_PRT5_LCD_EN\r
-.set SCSI_In__3__MASK, 0x04\r
-.set SCSI_In__3__PC, CYREG_PRT5_PC2\r
-.set SCSI_In__3__PORT, 5\r
-.set SCSI_In__3__PRT, CYREG_PRT5_PRT\r
-.set SCSI_In__3__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL\r
-.set SCSI_In__3__PRTDSI__DBL_SYNC_IN, CYREG_PRT5_DBL_SYNC_IN\r
-.set SCSI_In__3__PRTDSI__OE_SEL0, CYREG_PRT5_OE_SEL0\r
-.set SCSI_In__3__PRTDSI__OE_SEL1, CYREG_PRT5_OE_SEL1\r
-.set SCSI_In__3__PRTDSI__OUT_SEL0, CYREG_PRT5_OUT_SEL0\r
-.set SCSI_In__3__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1\r
-.set SCSI_In__3__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT\r
-.set SCSI_In__3__PS, CYREG_PRT5_PS\r
-.set SCSI_In__3__SHIFT, 2\r
-.set SCSI_In__3__SLW, CYREG_PRT5_SLW\r
-.set SCSI_In__4__AG, CYREG_PRT5_AG\r
-.set SCSI_In__4__AMUX, CYREG_PRT5_AMUX\r
-.set SCSI_In__4__BIE, CYREG_PRT5_BIE\r
-.set SCSI_In__4__BIT_MASK, CYREG_PRT5_BIT_MASK\r
-.set SCSI_In__4__BYP, CYREG_PRT5_BYP\r
-.set SCSI_In__4__CTL, CYREG_PRT5_CTL\r
-.set SCSI_In__4__DM0, CYREG_PRT5_DM0\r
-.set SCSI_In__4__DM1, CYREG_PRT5_DM1\r
-.set SCSI_In__4__DM2, CYREG_PRT5_DM2\r
-.set SCSI_In__4__DR, CYREG_PRT5_DR\r
-.set SCSI_In__4__INP_DIS, CYREG_PRT5_INP_DIS\r
-.set SCSI_In__4__INTTYPE, CYREG_PICU5_INTTYPE3\r
-.set SCSI_In__4__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG\r
-.set SCSI_In__4__LCD_EN, CYREG_PRT5_LCD_EN\r
-.set SCSI_In__4__MASK, 0x08\r
-.set SCSI_In__4__PC, CYREG_PRT5_PC3\r
-.set SCSI_In__4__PORT, 5\r
-.set SCSI_In__4__PRT, CYREG_PRT5_PRT\r
-.set SCSI_In__4__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL\r
-.set SCSI_In__4__PRTDSI__DBL_SYNC_IN, CYREG_PRT5_DBL_SYNC_IN\r
-.set SCSI_In__4__PRTDSI__OE_SEL0, CYREG_PRT5_OE_SEL0\r
-.set SCSI_In__4__PRTDSI__OE_SEL1, CYREG_PRT5_OE_SEL1\r
-.set SCSI_In__4__PRTDSI__OUT_SEL0, CYREG_PRT5_OUT_SEL0\r
-.set SCSI_In__4__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1\r
-.set SCSI_In__4__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT\r
-.set SCSI_In__4__PS, CYREG_PRT5_PS\r
-.set SCSI_In__4__SHIFT, 3\r
-.set SCSI_In__4__SLW, CYREG_PRT5_SLW\r
-.set SCSI_In__CD__AG, CYREG_PRT5_AG\r
-.set SCSI_In__CD__AMUX, CYREG_PRT5_AMUX\r
-.set SCSI_In__CD__BIE, CYREG_PRT5_BIE\r
-.set SCSI_In__CD__BIT_MASK, CYREG_PRT5_BIT_MASK\r
-.set SCSI_In__CD__BYP, CYREG_PRT5_BYP\r
-.set SCSI_In__CD__CTL, CYREG_PRT5_CTL\r
-.set SCSI_In__CD__DM0, CYREG_PRT5_DM0\r
-.set SCSI_In__CD__DM1, CYREG_PRT5_DM1\r
-.set SCSI_In__CD__DM2, CYREG_PRT5_DM2\r
-.set SCSI_In__CD__DR, CYREG_PRT5_DR\r
-.set SCSI_In__CD__INP_DIS, CYREG_PRT5_INP_DIS\r
-.set SCSI_In__CD__INTTYPE, CYREG_PICU5_INTTYPE1\r
-.set SCSI_In__CD__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG\r
-.set SCSI_In__CD__LCD_EN, CYREG_PRT5_LCD_EN\r
-.set SCSI_In__CD__MASK, 0x02\r
-.set SCSI_In__CD__PC, CYREG_PRT5_PC1\r
-.set SCSI_In__CD__PORT, 5\r
-.set SCSI_In__CD__PRT, CYREG_PRT5_PRT\r
-.set SCSI_In__CD__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL\r
-.set SCSI_In__CD__PRTDSI__DBL_SYNC_IN, CYREG_PRT5_DBL_SYNC_IN\r
-.set SCSI_In__CD__PRTDSI__OE_SEL0, CYREG_PRT5_OE_SEL0\r
-.set SCSI_In__CD__PRTDSI__OE_SEL1, CYREG_PRT5_OE_SEL1\r
-.set SCSI_In__CD__PRTDSI__OUT_SEL0, CYREG_PRT5_OUT_SEL0\r
-.set SCSI_In__CD__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1\r
-.set SCSI_In__CD__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT\r
-.set SCSI_In__CD__PS, CYREG_PRT5_PS\r
-.set SCSI_In__CD__SHIFT, 1\r
-.set SCSI_In__CD__SLW, CYREG_PRT5_SLW\r
-.set SCSI_In__DBP__AG, CYREG_PRT2_AG\r
-.set SCSI_In__DBP__AMUX, CYREG_PRT2_AMUX\r
-.set SCSI_In__DBP__BIE, CYREG_PRT2_BIE\r
-.set SCSI_In__DBP__BIT_MASK, CYREG_PRT2_BIT_MASK\r
-.set SCSI_In__DBP__BYP, CYREG_PRT2_BYP\r
-.set SCSI_In__DBP__CTL, CYREG_PRT2_CTL\r
-.set SCSI_In__DBP__DM0, CYREG_PRT2_DM0\r
-.set SCSI_In__DBP__DM1, CYREG_PRT2_DM1\r
-.set SCSI_In__DBP__DM2, CYREG_PRT2_DM2\r
-.set SCSI_In__DBP__DR, CYREG_PRT2_DR\r
-.set SCSI_In__DBP__INP_DIS, CYREG_PRT2_INP_DIS\r
-.set SCSI_In__DBP__INTTYPE, CYREG_PICU2_INTTYPE0\r
-.set SCSI_In__DBP__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG\r
-.set SCSI_In__DBP__LCD_EN, CYREG_PRT2_LCD_EN\r
-.set SCSI_In__DBP__MASK, 0x01\r
-.set SCSI_In__DBP__PC, CYREG_PRT2_PC0\r
-.set SCSI_In__DBP__PORT, 2\r
-.set SCSI_In__DBP__PRT, CYREG_PRT2_PRT\r
-.set SCSI_In__DBP__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL\r
-.set SCSI_In__DBP__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN\r
-.set SCSI_In__DBP__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0\r
-.set SCSI_In__DBP__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1\r
-.set SCSI_In__DBP__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0\r
-.set SCSI_In__DBP__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1\r
-.set SCSI_In__DBP__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT\r
-.set SCSI_In__DBP__PS, CYREG_PRT2_PS\r
-.set SCSI_In__DBP__SHIFT, 0\r
-.set SCSI_In__DBP__SLW, CYREG_PRT2_SLW\r
-.set SCSI_In__IO__AG, CYREG_PRT5_AG\r
-.set SCSI_In__IO__AMUX, CYREG_PRT5_AMUX\r
-.set SCSI_In__IO__BIE, CYREG_PRT5_BIE\r
-.set SCSI_In__IO__BIT_MASK, CYREG_PRT5_BIT_MASK\r
-.set SCSI_In__IO__BYP, CYREG_PRT5_BYP\r
-.set SCSI_In__IO__CTL, CYREG_PRT5_CTL\r
-.set SCSI_In__IO__DM0, CYREG_PRT5_DM0\r
-.set SCSI_In__IO__DM1, CYREG_PRT5_DM1\r
-.set SCSI_In__IO__DM2, CYREG_PRT5_DM2\r
-.set SCSI_In__IO__DR, CYREG_PRT5_DR\r
-.set SCSI_In__IO__INP_DIS, CYREG_PRT5_INP_DIS\r
-.set SCSI_In__IO__INTTYPE, CYREG_PICU5_INTTYPE3\r
-.set SCSI_In__IO__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG\r
-.set SCSI_In__IO__LCD_EN, CYREG_PRT5_LCD_EN\r
-.set SCSI_In__IO__MASK, 0x08\r
-.set SCSI_In__IO__PC, CYREG_PRT5_PC3\r
-.set SCSI_In__IO__PORT, 5\r
-.set SCSI_In__IO__PRT, CYREG_PRT5_PRT\r
-.set SCSI_In__IO__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL\r
-.set SCSI_In__IO__PRTDSI__DBL_SYNC_IN, CYREG_PRT5_DBL_SYNC_IN\r
-.set SCSI_In__IO__PRTDSI__OE_SEL0, CYREG_PRT5_OE_SEL0\r
-.set SCSI_In__IO__PRTDSI__OE_SEL1, CYREG_PRT5_OE_SEL1\r
-.set SCSI_In__IO__PRTDSI__OUT_SEL0, CYREG_PRT5_OUT_SEL0\r
-.set SCSI_In__IO__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1\r
-.set SCSI_In__IO__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT\r
-.set SCSI_In__IO__PS, CYREG_PRT5_PS\r
-.set SCSI_In__IO__SHIFT, 3\r
-.set SCSI_In__IO__SLW, CYREG_PRT5_SLW\r
-.set SCSI_In__MSG__AG, CYREG_PRT6_AG\r
-.set SCSI_In__MSG__AMUX, CYREG_PRT6_AMUX\r
-.set SCSI_In__MSG__BIE, CYREG_PRT6_BIE\r
-.set SCSI_In__MSG__BIT_MASK, CYREG_PRT6_BIT_MASK\r
-.set SCSI_In__MSG__BYP, CYREG_PRT6_BYP\r
-.set SCSI_In__MSG__CTL, CYREG_PRT6_CTL\r
-.set SCSI_In__MSG__DM0, CYREG_PRT6_DM0\r
-.set SCSI_In__MSG__DM1, CYREG_PRT6_DM1\r
-.set SCSI_In__MSG__DM2, CYREG_PRT6_DM2\r
-.set SCSI_In__MSG__DR, CYREG_PRT6_DR\r
-.set SCSI_In__MSG__INP_DIS, CYREG_PRT6_INP_DIS\r
-.set SCSI_In__MSG__INTTYPE, CYREG_PICU6_INTTYPE7\r
-.set SCSI_In__MSG__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG\r
-.set SCSI_In__MSG__LCD_EN, CYREG_PRT6_LCD_EN\r
-.set SCSI_In__MSG__MASK, 0x80\r
-.set SCSI_In__MSG__PC, CYREG_PRT6_PC7\r
-.set SCSI_In__MSG__PORT, 6\r
-.set SCSI_In__MSG__PRT, CYREG_PRT6_PRT\r
-.set SCSI_In__MSG__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL\r
-.set SCSI_In__MSG__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN\r
-.set SCSI_In__MSG__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0\r
-.set SCSI_In__MSG__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1\r
-.set SCSI_In__MSG__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0\r
-.set SCSI_In__MSG__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1\r
-.set SCSI_In__MSG__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT\r
-.set SCSI_In__MSG__PS, CYREG_PRT6_PS\r
-.set SCSI_In__MSG__SHIFT, 7\r
-.set SCSI_In__MSG__SLW, CYREG_PRT6_SLW\r
-.set SCSI_In__REQ__AG, CYREG_PRT5_AG\r
-.set SCSI_In__REQ__AMUX, CYREG_PRT5_AMUX\r
-.set SCSI_In__REQ__BIE, CYREG_PRT5_BIE\r
-.set SCSI_In__REQ__BIT_MASK, CYREG_PRT5_BIT_MASK\r
-.set SCSI_In__REQ__BYP, CYREG_PRT5_BYP\r
-.set SCSI_In__REQ__CTL, CYREG_PRT5_CTL\r
-.set SCSI_In__REQ__DM0, CYREG_PRT5_DM0\r
-.set SCSI_In__REQ__DM1, CYREG_PRT5_DM1\r
-.set SCSI_In__REQ__DM2, CYREG_PRT5_DM2\r
-.set SCSI_In__REQ__DR, CYREG_PRT5_DR\r
-.set SCSI_In__REQ__INP_DIS, CYREG_PRT5_INP_DIS\r
-.set SCSI_In__REQ__INTTYPE, CYREG_PICU5_INTTYPE2\r
-.set SCSI_In__REQ__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG\r
-.set SCSI_In__REQ__LCD_EN, CYREG_PRT5_LCD_EN\r
-.set SCSI_In__REQ__MASK, 0x04\r
-.set SCSI_In__REQ__PC, CYREG_PRT5_PC2\r
-.set SCSI_In__REQ__PORT, 5\r
-.set SCSI_In__REQ__PRT, CYREG_PRT5_PRT\r
-.set SCSI_In__REQ__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL\r
-.set SCSI_In__REQ__PRTDSI__DBL_SYNC_IN, CYREG_PRT5_DBL_SYNC_IN\r
-.set SCSI_In__REQ__PRTDSI__OE_SEL0, CYREG_PRT5_OE_SEL0\r
-.set SCSI_In__REQ__PRTDSI__OE_SEL1, CYREG_PRT5_OE_SEL1\r
-.set SCSI_In__REQ__PRTDSI__OUT_SEL0, CYREG_PRT5_OUT_SEL0\r
-.set SCSI_In__REQ__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1\r
-.set SCSI_In__REQ__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT\r
-.set SCSI_In__REQ__PS, CYREG_PRT5_PS\r
-.set SCSI_In__REQ__SHIFT, 2\r
-.set SCSI_In__REQ__SLW, CYREG_PRT5_SLW\r
-.set SCSI_In_DBx__0__AG, CYREG_PRT12_AG\r
-.set SCSI_In_DBx__0__BIE, CYREG_PRT12_BIE\r
-.set SCSI_In_DBx__0__BIT_MASK, CYREG_PRT12_BIT_MASK\r
-.set SCSI_In_DBx__0__BYP, CYREG_PRT12_BYP\r
-.set SCSI_In_DBx__0__DM0, CYREG_PRT12_DM0\r
-.set SCSI_In_DBx__0__DM1, CYREG_PRT12_DM1\r
-.set SCSI_In_DBx__0__DM2, CYREG_PRT12_DM2\r
-.set SCSI_In_DBx__0__DR, CYREG_PRT12_DR\r
-.set SCSI_In_DBx__0__INP_DIS, CYREG_PRT12_INP_DIS\r
-.set SCSI_In_DBx__0__INTTYPE, CYREG_PICU12_INTTYPE4\r
-.set SCSI_In_DBx__0__MASK, 0x10\r
-.set SCSI_In_DBx__0__PC, CYREG_PRT12_PC4\r
-.set SCSI_In_DBx__0__PORT, 12\r
-.set SCSI_In_DBx__0__PRT, CYREG_PRT12_PRT\r
-.set SCSI_In_DBx__0__PRTDSI__DBL_SYNC_IN, CYREG_PRT12_DBL_SYNC_IN\r
-.set SCSI_In_DBx__0__PRTDSI__OE_SEL0, CYREG_PRT12_OE_SEL0\r
-.set SCSI_In_DBx__0__PRTDSI__OE_SEL1, CYREG_PRT12_OE_SEL1\r
-.set SCSI_In_DBx__0__PRTDSI__OUT_SEL0, CYREG_PRT12_OUT_SEL0\r
-.set SCSI_In_DBx__0__PRTDSI__OUT_SEL1, CYREG_PRT12_OUT_SEL1\r
-.set SCSI_In_DBx__0__PRTDSI__SYNC_OUT, CYREG_PRT12_SYNC_OUT\r
-.set SCSI_In_DBx__0__PS, CYREG_PRT12_PS\r
-.set SCSI_In_DBx__0__SHIFT, 4\r
-.set SCSI_In_DBx__0__SIO_CFG, CYREG_PRT12_SIO_CFG\r
-.set SCSI_In_DBx__0__SIO_DIFF, CYREG_PRT12_SIO_DIFF\r
-.set SCSI_In_DBx__0__SIO_HYST_EN, CYREG_PRT12_SIO_HYST_EN\r
-.set SCSI_In_DBx__0__SIO_REG_HIFREQ, CYREG_PRT12_SIO_REG_HIFREQ\r
-.set SCSI_In_DBx__0__SLW, CYREG_PRT12_SLW\r
-.set SCSI_In_DBx__1__AG, CYREG_PRT2_AG\r
-.set SCSI_In_DBx__1__AMUX, CYREG_PRT2_AMUX\r
-.set SCSI_In_DBx__1__BIE, CYREG_PRT2_BIE\r
-.set SCSI_In_DBx__1__BIT_MASK, CYREG_PRT2_BIT_MASK\r
-.set SCSI_In_DBx__1__BYP, CYREG_PRT2_BYP\r
-.set SCSI_In_DBx__1__CTL, CYREG_PRT2_CTL\r
-.set SCSI_In_DBx__1__DM0, CYREG_PRT2_DM0\r
-.set SCSI_In_DBx__1__DM1, CYREG_PRT2_DM1\r
-.set SCSI_In_DBx__1__DM2, CYREG_PRT2_DM2\r
-.set SCSI_In_DBx__1__DR, CYREG_PRT2_DR\r
-.set SCSI_In_DBx__1__INP_DIS, CYREG_PRT2_INP_DIS\r
-.set SCSI_In_DBx__1__INTTYPE, CYREG_PICU2_INTTYPE7\r
-.set SCSI_In_DBx__1__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG\r
-.set SCSI_In_DBx__1__LCD_EN, CYREG_PRT2_LCD_EN\r
-.set SCSI_In_DBx__1__MASK, 0x80\r
-.set SCSI_In_DBx__1__PC, CYREG_PRT2_PC7\r
-.set SCSI_In_DBx__1__PORT, 2\r
-.set SCSI_In_DBx__1__PRT, CYREG_PRT2_PRT\r
-.set SCSI_In_DBx__1__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL\r
-.set SCSI_In_DBx__1__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN\r
-.set SCSI_In_DBx__1__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0\r
-.set SCSI_In_DBx__1__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1\r
-.set SCSI_In_DBx__1__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0\r
-.set SCSI_In_DBx__1__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1\r
-.set SCSI_In_DBx__1__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT\r
-.set SCSI_In_DBx__1__PS, CYREG_PRT2_PS\r
-.set SCSI_In_DBx__1__SHIFT, 7\r
-.set SCSI_In_DBx__1__SLW, CYREG_PRT2_SLW\r
-.set SCSI_In_DBx__2__AG, CYREG_PRT2_AG\r
-.set SCSI_In_DBx__2__AMUX, CYREG_PRT2_AMUX\r
-.set SCSI_In_DBx__2__BIE, CYREG_PRT2_BIE\r
-.set SCSI_In_DBx__2__BIT_MASK, CYREG_PRT2_BIT_MASK\r
-.set SCSI_In_DBx__2__BYP, CYREG_PRT2_BYP\r
-.set SCSI_In_DBx__2__CTL, CYREG_PRT2_CTL\r
-.set SCSI_In_DBx__2__DM0, CYREG_PRT2_DM0\r
-.set SCSI_In_DBx__2__DM1, CYREG_PRT2_DM1\r
-.set SCSI_In_DBx__2__DM2, CYREG_PRT2_DM2\r
-.set SCSI_In_DBx__2__DR, CYREG_PRT2_DR\r
-.set SCSI_In_DBx__2__INP_DIS, CYREG_PRT2_INP_DIS\r
-.set SCSI_In_DBx__2__INTTYPE, CYREG_PICU2_INTTYPE6\r
-.set SCSI_In_DBx__2__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG\r
-.set SCSI_In_DBx__2__LCD_EN, CYREG_PRT2_LCD_EN\r
-.set SCSI_In_DBx__2__MASK, 0x40\r
-.set SCSI_In_DBx__2__PC, CYREG_PRT2_PC6\r
-.set SCSI_In_DBx__2__PORT, 2\r
-.set SCSI_In_DBx__2__PRT, CYREG_PRT2_PRT\r
-.set SCSI_In_DBx__2__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL\r
-.set SCSI_In_DBx__2__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN\r
-.set SCSI_In_DBx__2__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0\r
-.set SCSI_In_DBx__2__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1\r
-.set SCSI_In_DBx__2__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0\r
-.set SCSI_In_DBx__2__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1\r
-.set SCSI_In_DBx__2__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT\r
-.set SCSI_In_DBx__2__PS, CYREG_PRT2_PS\r
-.set SCSI_In_DBx__2__SHIFT, 6\r
-.set SCSI_In_DBx__2__SLW, CYREG_PRT2_SLW\r
-.set SCSI_In_DBx__3__AG, CYREG_PRT2_AG\r
-.set SCSI_In_DBx__3__AMUX, CYREG_PRT2_AMUX\r
-.set SCSI_In_DBx__3__BIE, CYREG_PRT2_BIE\r
-.set SCSI_In_DBx__3__BIT_MASK, CYREG_PRT2_BIT_MASK\r
-.set SCSI_In_DBx__3__BYP, CYREG_PRT2_BYP\r
-.set SCSI_In_DBx__3__CTL, CYREG_PRT2_CTL\r
-.set SCSI_In_DBx__3__DM0, CYREG_PRT2_DM0\r
-.set SCSI_In_DBx__3__DM1, CYREG_PRT2_DM1\r
-.set SCSI_In_DBx__3__DM2, CYREG_PRT2_DM2\r
-.set SCSI_In_DBx__3__DR, CYREG_PRT2_DR\r
-.set SCSI_In_DBx__3__INP_DIS, CYREG_PRT2_INP_DIS\r
-.set SCSI_In_DBx__3__INTTYPE, CYREG_PICU2_INTTYPE5\r
-.set SCSI_In_DBx__3__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG\r
-.set SCSI_In_DBx__3__LCD_EN, CYREG_PRT2_LCD_EN\r
-.set SCSI_In_DBx__3__MASK, 0x20\r
-.set SCSI_In_DBx__3__PC, CYREG_PRT2_PC5\r
-.set SCSI_In_DBx__3__PORT, 2\r
-.set SCSI_In_DBx__3__PRT, CYREG_PRT2_PRT\r
-.set SCSI_In_DBx__3__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL\r
-.set SCSI_In_DBx__3__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN\r
-.set SCSI_In_DBx__3__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0\r
-.set SCSI_In_DBx__3__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1\r
-.set SCSI_In_DBx__3__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0\r
-.set SCSI_In_DBx__3__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1\r
-.set SCSI_In_DBx__3__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT\r
-.set SCSI_In_DBx__3__PS, CYREG_PRT2_PS\r
-.set SCSI_In_DBx__3__SHIFT, 5\r
-.set SCSI_In_DBx__3__SLW, CYREG_PRT2_SLW\r
-.set SCSI_In_DBx__4__AG, CYREG_PRT2_AG\r
-.set SCSI_In_DBx__4__AMUX, CYREG_PRT2_AMUX\r
-.set SCSI_In_DBx__4__BIE, CYREG_PRT2_BIE\r
-.set SCSI_In_DBx__4__BIT_MASK, CYREG_PRT2_BIT_MASK\r
-.set SCSI_In_DBx__4__BYP, CYREG_PRT2_BYP\r
-.set SCSI_In_DBx__4__CTL, CYREG_PRT2_CTL\r
-.set SCSI_In_DBx__4__DM0, CYREG_PRT2_DM0\r
-.set SCSI_In_DBx__4__DM1, CYREG_PRT2_DM1\r
-.set SCSI_In_DBx__4__DM2, CYREG_PRT2_DM2\r
-.set SCSI_In_DBx__4__DR, CYREG_PRT2_DR\r
-.set SCSI_In_DBx__4__INP_DIS, CYREG_PRT2_INP_DIS\r
-.set SCSI_In_DBx__4__INTTYPE, CYREG_PICU2_INTTYPE4\r
-.set SCSI_In_DBx__4__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG\r
-.set SCSI_In_DBx__4__LCD_EN, CYREG_PRT2_LCD_EN\r
-.set SCSI_In_DBx__4__MASK, 0x10\r
-.set SCSI_In_DBx__4__PC, CYREG_PRT2_PC4\r
-.set SCSI_In_DBx__4__PORT, 2\r
-.set SCSI_In_DBx__4__PRT, CYREG_PRT2_PRT\r
-.set SCSI_In_DBx__4__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL\r
-.set SCSI_In_DBx__4__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN\r
-.set SCSI_In_DBx__4__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0\r
-.set SCSI_In_DBx__4__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1\r
-.set SCSI_In_DBx__4__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0\r
-.set SCSI_In_DBx__4__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1\r
-.set SCSI_In_DBx__4__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT\r
-.set SCSI_In_DBx__4__PS, CYREG_PRT2_PS\r
-.set SCSI_In_DBx__4__SHIFT, 4\r
-.set SCSI_In_DBx__4__SLW, CYREG_PRT2_SLW\r
-.set SCSI_In_DBx__5__AG, CYREG_PRT2_AG\r
-.set SCSI_In_DBx__5__AMUX, CYREG_PRT2_AMUX\r
-.set SCSI_In_DBx__5__BIE, CYREG_PRT2_BIE\r
-.set SCSI_In_DBx__5__BIT_MASK, CYREG_PRT2_BIT_MASK\r
-.set SCSI_In_DBx__5__BYP, CYREG_PRT2_BYP\r
-.set SCSI_In_DBx__5__CTL, CYREG_PRT2_CTL\r
-.set SCSI_In_DBx__5__DM0, CYREG_PRT2_DM0\r
-.set SCSI_In_DBx__5__DM1, CYREG_PRT2_DM1\r
-.set SCSI_In_DBx__5__DM2, CYREG_PRT2_DM2\r
-.set SCSI_In_DBx__5__DR, CYREG_PRT2_DR\r
-.set SCSI_In_DBx__5__INP_DIS, CYREG_PRT2_INP_DIS\r
-.set SCSI_In_DBx__5__INTTYPE, CYREG_PICU2_INTTYPE3\r
-.set SCSI_In_DBx__5__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG\r
-.set SCSI_In_DBx__5__LCD_EN, CYREG_PRT2_LCD_EN\r
-.set SCSI_In_DBx__5__MASK, 0x08\r
-.set SCSI_In_DBx__5__PC, CYREG_PRT2_PC3\r
-.set SCSI_In_DBx__5__PORT, 2\r
-.set SCSI_In_DBx__5__PRT, CYREG_PRT2_PRT\r
-.set SCSI_In_DBx__5__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL\r
-.set SCSI_In_DBx__5__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN\r
-.set SCSI_In_DBx__5__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0\r
-.set SCSI_In_DBx__5__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1\r
-.set SCSI_In_DBx__5__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0\r
-.set SCSI_In_DBx__5__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1\r
-.set SCSI_In_DBx__5__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT\r
-.set SCSI_In_DBx__5__PS, CYREG_PRT2_PS\r
-.set SCSI_In_DBx__5__SHIFT, 3\r
-.set SCSI_In_DBx__5__SLW, CYREG_PRT2_SLW\r
-.set SCSI_In_DBx__6__AG, CYREG_PRT2_AG\r
-.set SCSI_In_DBx__6__AMUX, CYREG_PRT2_AMUX\r
-.set SCSI_In_DBx__6__BIE, CYREG_PRT2_BIE\r
-.set SCSI_In_DBx__6__BIT_MASK, CYREG_PRT2_BIT_MASK\r
-.set SCSI_In_DBx__6__BYP, CYREG_PRT2_BYP\r
-.set SCSI_In_DBx__6__CTL, CYREG_PRT2_CTL\r
-.set SCSI_In_DBx__6__DM0, CYREG_PRT2_DM0\r
-.set SCSI_In_DBx__6__DM1, CYREG_PRT2_DM1\r
-.set SCSI_In_DBx__6__DM2, CYREG_PRT2_DM2\r
-.set SCSI_In_DBx__6__DR, CYREG_PRT2_DR\r
-.set SCSI_In_DBx__6__INP_DIS, CYREG_PRT2_INP_DIS\r
-.set SCSI_In_DBx__6__INTTYPE, CYREG_PICU2_INTTYPE2\r
-.set SCSI_In_DBx__6__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG\r
-.set SCSI_In_DBx__6__LCD_EN, CYREG_PRT2_LCD_EN\r
-.set SCSI_In_DBx__6__MASK, 0x04\r
-.set SCSI_In_DBx__6__PC, CYREG_PRT2_PC2\r
-.set SCSI_In_DBx__6__PORT, 2\r
-.set SCSI_In_DBx__6__PRT, CYREG_PRT2_PRT\r
-.set SCSI_In_DBx__6__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL\r
-.set SCSI_In_DBx__6__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN\r
-.set SCSI_In_DBx__6__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0\r
-.set SCSI_In_DBx__6__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1\r
-.set SCSI_In_DBx__6__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0\r
-.set SCSI_In_DBx__6__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1\r
-.set SCSI_In_DBx__6__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT\r
-.set SCSI_In_DBx__6__PS, CYREG_PRT2_PS\r
-.set SCSI_In_DBx__6__SHIFT, 2\r
-.set SCSI_In_DBx__6__SLW, CYREG_PRT2_SLW\r
-.set SCSI_In_DBx__7__AG, CYREG_PRT2_AG\r
-.set SCSI_In_DBx__7__AMUX, CYREG_PRT2_AMUX\r
-.set SCSI_In_DBx__7__BIE, CYREG_PRT2_BIE\r
-.set SCSI_In_DBx__7__BIT_MASK, CYREG_PRT2_BIT_MASK\r
-.set SCSI_In_DBx__7__BYP, CYREG_PRT2_BYP\r
-.set SCSI_In_DBx__7__CTL, CYREG_PRT2_CTL\r
-.set SCSI_In_DBx__7__DM0, CYREG_PRT2_DM0\r
-.set SCSI_In_DBx__7__DM1, CYREG_PRT2_DM1\r
-.set SCSI_In_DBx__7__DM2, CYREG_PRT2_DM2\r
-.set SCSI_In_DBx__7__DR, CYREG_PRT2_DR\r
-.set SCSI_In_DBx__7__INP_DIS, CYREG_PRT2_INP_DIS\r
-.set SCSI_In_DBx__7__INTTYPE, CYREG_PICU2_INTTYPE1\r
-.set SCSI_In_DBx__7__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG\r
-.set SCSI_In_DBx__7__LCD_EN, CYREG_PRT2_LCD_EN\r
-.set SCSI_In_DBx__7__MASK, 0x02\r
-.set SCSI_In_DBx__7__PC, CYREG_PRT2_PC1\r
-.set SCSI_In_DBx__7__PORT, 2\r
-.set SCSI_In_DBx__7__PRT, CYREG_PRT2_PRT\r
-.set SCSI_In_DBx__7__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL\r
-.set SCSI_In_DBx__7__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN\r
-.set SCSI_In_DBx__7__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0\r
-.set SCSI_In_DBx__7__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1\r
-.set SCSI_In_DBx__7__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0\r
-.set SCSI_In_DBx__7__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1\r
-.set SCSI_In_DBx__7__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT\r
-.set SCSI_In_DBx__7__PS, CYREG_PRT2_PS\r
-.set SCSI_In_DBx__7__SHIFT, 1\r
-.set SCSI_In_DBx__7__SLW, CYREG_PRT2_SLW\r
-.set SCSI_In_DBx__DB0__AG, CYREG_PRT12_AG\r
-.set SCSI_In_DBx__DB0__BIE, CYREG_PRT12_BIE\r
-.set SCSI_In_DBx__DB0__BIT_MASK, CYREG_PRT12_BIT_MASK\r
-.set SCSI_In_DBx__DB0__BYP, CYREG_PRT12_BYP\r
-.set SCSI_In_DBx__DB0__DM0, CYREG_PRT12_DM0\r
-.set SCSI_In_DBx__DB0__DM1, CYREG_PRT12_DM1\r
-.set SCSI_In_DBx__DB0__DM2, CYREG_PRT12_DM2\r
-.set SCSI_In_DBx__DB0__DR, CYREG_PRT12_DR\r
-.set SCSI_In_DBx__DB0__INP_DIS, CYREG_PRT12_INP_DIS\r
-.set SCSI_In_DBx__DB0__INTTYPE, CYREG_PICU12_INTTYPE4\r
-.set SCSI_In_DBx__DB0__MASK, 0x10\r
-.set SCSI_In_DBx__DB0__PC, CYREG_PRT12_PC4\r
-.set SCSI_In_DBx__DB0__PORT, 12\r
-.set SCSI_In_DBx__DB0__PRT, CYREG_PRT12_PRT\r
-.set SCSI_In_DBx__DB0__PRTDSI__DBL_SYNC_IN, CYREG_PRT12_DBL_SYNC_IN\r
-.set SCSI_In_DBx__DB0__PRTDSI__OE_SEL0, CYREG_PRT12_OE_SEL0\r
-.set SCSI_In_DBx__DB0__PRTDSI__OE_SEL1, CYREG_PRT12_OE_SEL1\r
-.set SCSI_In_DBx__DB0__PRTDSI__OUT_SEL0, CYREG_PRT12_OUT_SEL0\r
-.set SCSI_In_DBx__DB0__PRTDSI__OUT_SEL1, CYREG_PRT12_OUT_SEL1\r
-.set SCSI_In_DBx__DB0__PRTDSI__SYNC_OUT, CYREG_PRT12_SYNC_OUT\r
-.set SCSI_In_DBx__DB0__PS, CYREG_PRT12_PS\r
-.set SCSI_In_DBx__DB0__SHIFT, 4\r
-.set SCSI_In_DBx__DB0__SIO_CFG, CYREG_PRT12_SIO_CFG\r
-.set SCSI_In_DBx__DB0__SIO_DIFF, CYREG_PRT12_SIO_DIFF\r
-.set SCSI_In_DBx__DB0__SIO_HYST_EN, CYREG_PRT12_SIO_HYST_EN\r
-.set SCSI_In_DBx__DB0__SIO_REG_HIFREQ, CYREG_PRT12_SIO_REG_HIFREQ\r
-.set SCSI_In_DBx__DB0__SLW, CYREG_PRT12_SLW\r
-.set SCSI_In_DBx__DB1__AG, CYREG_PRT2_AG\r
-.set SCSI_In_DBx__DB1__AMUX, CYREG_PRT2_AMUX\r
-.set SCSI_In_DBx__DB1__BIE, CYREG_PRT2_BIE\r
-.set SCSI_In_DBx__DB1__BIT_MASK, CYREG_PRT2_BIT_MASK\r
-.set SCSI_In_DBx__DB1__BYP, CYREG_PRT2_BYP\r
-.set SCSI_In_DBx__DB1__CTL, CYREG_PRT2_CTL\r
-.set SCSI_In_DBx__DB1__DM0, CYREG_PRT2_DM0\r
-.set SCSI_In_DBx__DB1__DM1, CYREG_PRT2_DM1\r
-.set SCSI_In_DBx__DB1__DM2, CYREG_PRT2_DM2\r
-.set SCSI_In_DBx__DB1__DR, CYREG_PRT2_DR\r
-.set SCSI_In_DBx__DB1__INP_DIS, CYREG_PRT2_INP_DIS\r
-.set SCSI_In_DBx__DB1__INTTYPE, CYREG_PICU2_INTTYPE7\r
-.set SCSI_In_DBx__DB1__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG\r
-.set SCSI_In_DBx__DB1__LCD_EN, CYREG_PRT2_LCD_EN\r
-.set SCSI_In_DBx__DB1__MASK, 0x80\r
-.set SCSI_In_DBx__DB1__PC, CYREG_PRT2_PC7\r
-.set SCSI_In_DBx__DB1__PORT, 2\r
-.set SCSI_In_DBx__DB1__PRT, CYREG_PRT2_PRT\r
-.set SCSI_In_DBx__DB1__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL\r
-.set SCSI_In_DBx__DB1__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN\r
-.set SCSI_In_DBx__DB1__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0\r
-.set SCSI_In_DBx__DB1__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1\r
-.set SCSI_In_DBx__DB1__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0\r
-.set SCSI_In_DBx__DB1__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1\r
-.set SCSI_In_DBx__DB1__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT\r
-.set SCSI_In_DBx__DB1__PS, CYREG_PRT2_PS\r
-.set SCSI_In_DBx__DB1__SHIFT, 7\r
-.set SCSI_In_DBx__DB1__SLW, CYREG_PRT2_SLW\r
-.set SCSI_In_DBx__DB2__AG, CYREG_PRT2_AG\r
-.set SCSI_In_DBx__DB2__AMUX, CYREG_PRT2_AMUX\r
-.set SCSI_In_DBx__DB2__BIE, CYREG_PRT2_BIE\r
-.set SCSI_In_DBx__DB2__BIT_MASK, CYREG_PRT2_BIT_MASK\r
-.set SCSI_In_DBx__DB2__BYP, CYREG_PRT2_BYP\r
-.set SCSI_In_DBx__DB2__CTL, CYREG_PRT2_CTL\r
-.set SCSI_In_DBx__DB2__DM0, CYREG_PRT2_DM0\r
-.set SCSI_In_DBx__DB2__DM1, CYREG_PRT2_DM1\r
-.set SCSI_In_DBx__DB2__DM2, CYREG_PRT2_DM2\r
-.set SCSI_In_DBx__DB2__DR, CYREG_PRT2_DR\r
-.set SCSI_In_DBx__DB2__INP_DIS, CYREG_PRT2_INP_DIS\r
-.set SCSI_In_DBx__DB2__INTTYPE, CYREG_PICU2_INTTYPE6\r
-.set SCSI_In_DBx__DB2__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG\r
-.set SCSI_In_DBx__DB2__LCD_EN, CYREG_PRT2_LCD_EN\r
-.set SCSI_In_DBx__DB2__MASK, 0x40\r
-.set SCSI_In_DBx__DB2__PC, CYREG_PRT2_PC6\r
-.set SCSI_In_DBx__DB2__PORT, 2\r
-.set SCSI_In_DBx__DB2__PRT, CYREG_PRT2_PRT\r
-.set SCSI_In_DBx__DB2__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL\r
-.set SCSI_In_DBx__DB2__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN\r
-.set SCSI_In_DBx__DB2__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0\r
-.set SCSI_In_DBx__DB2__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1\r
-.set SCSI_In_DBx__DB2__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0\r
-.set SCSI_In_DBx__DB2__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1\r
-.set SCSI_In_DBx__DB2__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT\r
-.set SCSI_In_DBx__DB2__PS, CYREG_PRT2_PS\r
-.set SCSI_In_DBx__DB2__SHIFT, 6\r
-.set SCSI_In_DBx__DB2__SLW, CYREG_PRT2_SLW\r
-.set SCSI_In_DBx__DB3__AG, CYREG_PRT2_AG\r
-.set SCSI_In_DBx__DB3__AMUX, CYREG_PRT2_AMUX\r
-.set SCSI_In_DBx__DB3__BIE, CYREG_PRT2_BIE\r
-.set SCSI_In_DBx__DB3__BIT_MASK, CYREG_PRT2_BIT_MASK\r
-.set SCSI_In_DBx__DB3__BYP, CYREG_PRT2_BYP\r
-.set SCSI_In_DBx__DB3__CTL, CYREG_PRT2_CTL\r
-.set SCSI_In_DBx__DB3__DM0, CYREG_PRT2_DM0\r
-.set SCSI_In_DBx__DB3__DM1, CYREG_PRT2_DM1\r
-.set SCSI_In_DBx__DB3__DM2, CYREG_PRT2_DM2\r
-.set SCSI_In_DBx__DB3__DR, CYREG_PRT2_DR\r
-.set SCSI_In_DBx__DB3__INP_DIS, CYREG_PRT2_INP_DIS\r
-.set SCSI_In_DBx__DB3__INTTYPE, CYREG_PICU2_INTTYPE5\r
-.set SCSI_In_DBx__DB3__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG\r
-.set SCSI_In_DBx__DB3__LCD_EN, CYREG_PRT2_LCD_EN\r
-.set SCSI_In_DBx__DB3__MASK, 0x20\r
-.set SCSI_In_DBx__DB3__PC, CYREG_PRT2_PC5\r
-.set SCSI_In_DBx__DB3__PORT, 2\r
-.set SCSI_In_DBx__DB3__PRT, CYREG_PRT2_PRT\r
-.set SCSI_In_DBx__DB3__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL\r
-.set SCSI_In_DBx__DB3__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN\r
-.set SCSI_In_DBx__DB3__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0\r
-.set SCSI_In_DBx__DB3__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1\r
-.set SCSI_In_DBx__DB3__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0\r
-.set SCSI_In_DBx__DB3__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1\r
-.set SCSI_In_DBx__DB3__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT\r
-.set SCSI_In_DBx__DB3__PS, CYREG_PRT2_PS\r
-.set SCSI_In_DBx__DB3__SHIFT, 5\r
-.set SCSI_In_DBx__DB3__SLW, CYREG_PRT2_SLW\r
-.set SCSI_In_DBx__DB4__AG, CYREG_PRT2_AG\r
-.set SCSI_In_DBx__DB4__AMUX, CYREG_PRT2_AMUX\r
-.set SCSI_In_DBx__DB4__BIE, CYREG_PRT2_BIE\r
-.set SCSI_In_DBx__DB4__BIT_MASK, CYREG_PRT2_BIT_MASK\r
-.set SCSI_In_DBx__DB4__BYP, CYREG_PRT2_BYP\r
-.set SCSI_In_DBx__DB4__CTL, CYREG_PRT2_CTL\r
-.set SCSI_In_DBx__DB4__DM0, CYREG_PRT2_DM0\r
-.set SCSI_In_DBx__DB4__DM1, CYREG_PRT2_DM1\r
-.set SCSI_In_DBx__DB4__DM2, CYREG_PRT2_DM2\r
-.set SCSI_In_DBx__DB4__DR, CYREG_PRT2_DR\r
-.set SCSI_In_DBx__DB4__INP_DIS, CYREG_PRT2_INP_DIS\r
-.set SCSI_In_DBx__DB4__INTTYPE, CYREG_PICU2_INTTYPE4\r
-.set SCSI_In_DBx__DB4__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG\r
-.set SCSI_In_DBx__DB4__LCD_EN, CYREG_PRT2_LCD_EN\r
-.set SCSI_In_DBx__DB4__MASK, 0x10\r
-.set SCSI_In_DBx__DB4__PC, CYREG_PRT2_PC4\r
-.set SCSI_In_DBx__DB4__PORT, 2\r
-.set SCSI_In_DBx__DB4__PRT, CYREG_PRT2_PRT\r
-.set SCSI_In_DBx__DB4__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL\r
-.set SCSI_In_DBx__DB4__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN\r
-.set SCSI_In_DBx__DB4__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0\r
-.set SCSI_In_DBx__DB4__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1\r
-.set SCSI_In_DBx__DB4__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0\r
-.set SCSI_In_DBx__DB4__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1\r
-.set SCSI_In_DBx__DB4__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT\r
-.set SCSI_In_DBx__DB4__PS, CYREG_PRT2_PS\r
-.set SCSI_In_DBx__DB4__SHIFT, 4\r
-.set SCSI_In_DBx__DB4__SLW, CYREG_PRT2_SLW\r
-.set SCSI_In_DBx__DB5__AG, CYREG_PRT2_AG\r
-.set SCSI_In_DBx__DB5__AMUX, CYREG_PRT2_AMUX\r
-.set SCSI_In_DBx__DB5__BIE, CYREG_PRT2_BIE\r
-.set SCSI_In_DBx__DB5__BIT_MASK, CYREG_PRT2_BIT_MASK\r
-.set SCSI_In_DBx__DB5__BYP, CYREG_PRT2_BYP\r
-.set SCSI_In_DBx__DB5__CTL, CYREG_PRT2_CTL\r
-.set SCSI_In_DBx__DB5__DM0, CYREG_PRT2_DM0\r
-.set SCSI_In_DBx__DB5__DM1, CYREG_PRT2_DM1\r
-.set SCSI_In_DBx__DB5__DM2, CYREG_PRT2_DM2\r
-.set SCSI_In_DBx__DB5__DR, CYREG_PRT2_DR\r
-.set SCSI_In_DBx__DB5__INP_DIS, CYREG_PRT2_INP_DIS\r
-.set SCSI_In_DBx__DB5__INTTYPE, CYREG_PICU2_INTTYPE3\r
-.set SCSI_In_DBx__DB5__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG\r
-.set SCSI_In_DBx__DB5__LCD_EN, CYREG_PRT2_LCD_EN\r
-.set SCSI_In_DBx__DB5__MASK, 0x08\r
-.set SCSI_In_DBx__DB5__PC, CYREG_PRT2_PC3\r
-.set SCSI_In_DBx__DB5__PORT, 2\r
-.set SCSI_In_DBx__DB5__PRT, CYREG_PRT2_PRT\r
-.set SCSI_In_DBx__DB5__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL\r
-.set SCSI_In_DBx__DB5__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN\r
-.set SCSI_In_DBx__DB5__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0\r
-.set SCSI_In_DBx__DB5__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1\r
-.set SCSI_In_DBx__DB5__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0\r
-.set SCSI_In_DBx__DB5__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1\r
-.set SCSI_In_DBx__DB5__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT\r
-.set SCSI_In_DBx__DB5__PS, CYREG_PRT2_PS\r
-.set SCSI_In_DBx__DB5__SHIFT, 3\r
-.set SCSI_In_DBx__DB5__SLW, CYREG_PRT2_SLW\r
-.set SCSI_In_DBx__DB6__AG, CYREG_PRT2_AG\r
-.set SCSI_In_DBx__DB6__AMUX, CYREG_PRT2_AMUX\r
-.set SCSI_In_DBx__DB6__BIE, CYREG_PRT2_BIE\r
-.set SCSI_In_DBx__DB6__BIT_MASK, CYREG_PRT2_BIT_MASK\r
-.set SCSI_In_DBx__DB6__BYP, CYREG_PRT2_BYP\r
-.set SCSI_In_DBx__DB6__CTL, CYREG_PRT2_CTL\r
-.set SCSI_In_DBx__DB6__DM0, CYREG_PRT2_DM0\r
-.set SCSI_In_DBx__DB6__DM1, CYREG_PRT2_DM1\r
-.set SCSI_In_DBx__DB6__DM2, CYREG_PRT2_DM2\r
-.set SCSI_In_DBx__DB6__DR, CYREG_PRT2_DR\r
-.set SCSI_In_DBx__DB6__INP_DIS, CYREG_PRT2_INP_DIS\r
-.set SCSI_In_DBx__DB6__INTTYPE, CYREG_PICU2_INTTYPE2\r
-.set SCSI_In_DBx__DB6__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG\r
-.set SCSI_In_DBx__DB6__LCD_EN, CYREG_PRT2_LCD_EN\r
-.set SCSI_In_DBx__DB6__MASK, 0x04\r
-.set SCSI_In_DBx__DB6__PC, CYREG_PRT2_PC2\r
-.set SCSI_In_DBx__DB6__PORT, 2\r
-.set SCSI_In_DBx__DB6__PRT, CYREG_PRT2_PRT\r
-.set SCSI_In_DBx__DB6__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL\r
-.set SCSI_In_DBx__DB6__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN\r
-.set SCSI_In_DBx__DB6__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0\r
-.set SCSI_In_DBx__DB6__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1\r
-.set SCSI_In_DBx__DB6__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0\r
-.set SCSI_In_DBx__DB6__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1\r
-.set SCSI_In_DBx__DB6__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT\r
-.set SCSI_In_DBx__DB6__PS, CYREG_PRT2_PS\r
-.set SCSI_In_DBx__DB6__SHIFT, 2\r
-.set SCSI_In_DBx__DB6__SLW, CYREG_PRT2_SLW\r
-.set SCSI_In_DBx__DB7__AG, CYREG_PRT2_AG\r
-.set SCSI_In_DBx__DB7__AMUX, CYREG_PRT2_AMUX\r
-.set SCSI_In_DBx__DB7__BIE, CYREG_PRT2_BIE\r
-.set SCSI_In_DBx__DB7__BIT_MASK, CYREG_PRT2_BIT_MASK\r
-.set SCSI_In_DBx__DB7__BYP, CYREG_PRT2_BYP\r
-.set SCSI_In_DBx__DB7__CTL, CYREG_PRT2_CTL\r
-.set SCSI_In_DBx__DB7__DM0, CYREG_PRT2_DM0\r
-.set SCSI_In_DBx__DB7__DM1, CYREG_PRT2_DM1\r
-.set SCSI_In_DBx__DB7__DM2, CYREG_PRT2_DM2\r
-.set SCSI_In_DBx__DB7__DR, CYREG_PRT2_DR\r
-.set SCSI_In_DBx__DB7__INP_DIS, CYREG_PRT2_INP_DIS\r
-.set SCSI_In_DBx__DB7__INTTYPE, CYREG_PICU2_INTTYPE1\r
-.set SCSI_In_DBx__DB7__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG\r
-.set SCSI_In_DBx__DB7__LCD_EN, CYREG_PRT2_LCD_EN\r
-.set SCSI_In_DBx__DB7__MASK, 0x02\r
-.set SCSI_In_DBx__DB7__PC, CYREG_PRT2_PC1\r
-.set SCSI_In_DBx__DB7__PORT, 2\r
-.set SCSI_In_DBx__DB7__PRT, CYREG_PRT2_PRT\r
-.set SCSI_In_DBx__DB7__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL\r
-.set SCSI_In_DBx__DB7__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN\r
-.set SCSI_In_DBx__DB7__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0\r
-.set SCSI_In_DBx__DB7__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1\r
-.set SCSI_In_DBx__DB7__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0\r
-.set SCSI_In_DBx__DB7__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1\r
-.set SCSI_In_DBx__DB7__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT\r
-.set SCSI_In_DBx__DB7__PS, CYREG_PRT2_PS\r
-.set SCSI_In_DBx__DB7__SHIFT, 1\r
-.set SCSI_In_DBx__DB7__SLW, CYREG_PRT2_SLW\r
-\r
-/* SCSI_Noise */\r
-.set SCSI_Noise__0__AG, CYREG_PRT12_AG\r
-.set SCSI_Noise__0__BIE, CYREG_PRT12_BIE\r
-.set SCSI_Noise__0__BIT_MASK, CYREG_PRT12_BIT_MASK\r
-.set SCSI_Noise__0__BYP, CYREG_PRT12_BYP\r
-.set SCSI_Noise__0__DM0, CYREG_PRT12_DM0\r
-.set SCSI_Noise__0__DM1, CYREG_PRT12_DM1\r
-.set SCSI_Noise__0__DM2, CYREG_PRT12_DM2\r
-.set SCSI_Noise__0__DR, CYREG_PRT12_DR\r
-.set SCSI_Noise__0__INP_DIS, CYREG_PRT12_INP_DIS\r
-.set SCSI_Noise__0__INTTYPE, CYREG_PICU12_INTTYPE5\r
-.set SCSI_Noise__0__MASK, 0x20\r
-.set SCSI_Noise__0__PC, CYREG_PRT12_PC5\r
-.set SCSI_Noise__0__PORT, 12\r
-.set SCSI_Noise__0__PRT, CYREG_PRT12_PRT\r
-.set SCSI_Noise__0__PRTDSI__DBL_SYNC_IN, CYREG_PRT12_DBL_SYNC_IN\r
-.set SCSI_Noise__0__PRTDSI__OE_SEL0, CYREG_PRT12_OE_SEL0\r
-.set SCSI_Noise__0__PRTDSI__OE_SEL1, CYREG_PRT12_OE_SEL1\r
-.set SCSI_Noise__0__PRTDSI__OUT_SEL0, CYREG_PRT12_OUT_SEL0\r
-.set SCSI_Noise__0__PRTDSI__OUT_SEL1, CYREG_PRT12_OUT_SEL1\r
-.set SCSI_Noise__0__PRTDSI__SYNC_OUT, CYREG_PRT12_SYNC_OUT\r
-.set SCSI_Noise__0__PS, CYREG_PRT12_PS\r
-.set SCSI_Noise__0__SHIFT, 5\r
-.set SCSI_Noise__0__SIO_CFG, CYREG_PRT12_SIO_CFG\r
-.set SCSI_Noise__0__SIO_DIFF, CYREG_PRT12_SIO_DIFF\r
-.set SCSI_Noise__0__SIO_HYST_EN, CYREG_PRT12_SIO_HYST_EN\r
-.set SCSI_Noise__0__SIO_REG_HIFREQ, CYREG_PRT12_SIO_REG_HIFREQ\r
-.set SCSI_Noise__0__SLW, CYREG_PRT12_SLW\r
-.set SCSI_Noise__1__AG, CYREG_PRT6_AG\r
-.set SCSI_Noise__1__AMUX, CYREG_PRT6_AMUX\r
-.set SCSI_Noise__1__BIE, CYREG_PRT6_BIE\r
-.set SCSI_Noise__1__BIT_MASK, CYREG_PRT6_BIT_MASK\r
-.set SCSI_Noise__1__BYP, CYREG_PRT6_BYP\r
-.set SCSI_Noise__1__CTL, CYREG_PRT6_CTL\r
-.set SCSI_Noise__1__DM0, CYREG_PRT6_DM0\r
-.set SCSI_Noise__1__DM1, CYREG_PRT6_DM1\r
-.set SCSI_Noise__1__DM2, CYREG_PRT6_DM2\r
-.set SCSI_Noise__1__DR, CYREG_PRT6_DR\r
-.set SCSI_Noise__1__INP_DIS, CYREG_PRT6_INP_DIS\r
-.set SCSI_Noise__1__INTTYPE, CYREG_PICU6_INTTYPE4\r
-.set SCSI_Noise__1__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG\r
-.set SCSI_Noise__1__LCD_EN, CYREG_PRT6_LCD_EN\r
-.set SCSI_Noise__1__MASK, 0x10\r
-.set SCSI_Noise__1__PC, CYREG_PRT6_PC4\r
-.set SCSI_Noise__1__PORT, 6\r
-.set SCSI_Noise__1__PRT, CYREG_PRT6_PRT\r
-.set SCSI_Noise__1__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL\r
-.set SCSI_Noise__1__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN\r
-.set SCSI_Noise__1__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0\r
-.set SCSI_Noise__1__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1\r
-.set SCSI_Noise__1__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0\r
-.set SCSI_Noise__1__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1\r
-.set SCSI_Noise__1__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT\r
-.set SCSI_Noise__1__PS, CYREG_PRT6_PS\r
-.set SCSI_Noise__1__SHIFT, 4\r
-.set SCSI_Noise__1__SLW, CYREG_PRT6_SLW\r
-.set SCSI_Noise__2__AG, CYREG_PRT5_AG\r
-.set SCSI_Noise__2__AMUX, CYREG_PRT5_AMUX\r
-.set SCSI_Noise__2__BIE, CYREG_PRT5_BIE\r
-.set SCSI_Noise__2__BIT_MASK, CYREG_PRT5_BIT_MASK\r
-.set SCSI_Noise__2__BYP, CYREG_PRT5_BYP\r
-.set SCSI_Noise__2__CTL, CYREG_PRT5_CTL\r
-.set SCSI_Noise__2__DM0, CYREG_PRT5_DM0\r
-.set SCSI_Noise__2__DM1, CYREG_PRT5_DM1\r
-.set SCSI_Noise__2__DM2, CYREG_PRT5_DM2\r
-.set SCSI_Noise__2__DR, CYREG_PRT5_DR\r
-.set SCSI_Noise__2__INP_DIS, CYREG_PRT5_INP_DIS\r
-.set SCSI_Noise__2__INTTYPE, CYREG_PICU5_INTTYPE0\r
-.set SCSI_Noise__2__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG\r
-.set SCSI_Noise__2__LCD_EN, CYREG_PRT5_LCD_EN\r
-.set SCSI_Noise__2__MASK, 0x01\r
-.set SCSI_Noise__2__PC, CYREG_PRT5_PC0\r
-.set SCSI_Noise__2__PORT, 5\r
-.set SCSI_Noise__2__PRT, CYREG_PRT5_PRT\r
-.set SCSI_Noise__2__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL\r
-.set SCSI_Noise__2__PRTDSI__DBL_SYNC_IN, CYREG_PRT5_DBL_SYNC_IN\r
-.set SCSI_Noise__2__PRTDSI__OE_SEL0, CYREG_PRT5_OE_SEL0\r
-.set SCSI_Noise__2__PRTDSI__OE_SEL1, CYREG_PRT5_OE_SEL1\r
-.set SCSI_Noise__2__PRTDSI__OUT_SEL0, CYREG_PRT5_OUT_SEL0\r
-.set SCSI_Noise__2__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1\r
-.set SCSI_Noise__2__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT\r
-.set SCSI_Noise__2__PS, CYREG_PRT5_PS\r
-.set SCSI_Noise__2__SHIFT, 0\r
-.set SCSI_Noise__2__SLW, CYREG_PRT5_SLW\r
-.set SCSI_Noise__3__AG, CYREG_PRT6_AG\r
-.set SCSI_Noise__3__AMUX, CYREG_PRT6_AMUX\r
-.set SCSI_Noise__3__BIE, CYREG_PRT6_BIE\r
-.set SCSI_Noise__3__BIT_MASK, CYREG_PRT6_BIT_MASK\r
-.set SCSI_Noise__3__BYP, CYREG_PRT6_BYP\r
-.set SCSI_Noise__3__CTL, CYREG_PRT6_CTL\r
-.set SCSI_Noise__3__DM0, CYREG_PRT6_DM0\r
-.set SCSI_Noise__3__DM1, CYREG_PRT6_DM1\r
-.set SCSI_Noise__3__DM2, CYREG_PRT6_DM2\r
-.set SCSI_Noise__3__DR, CYREG_PRT6_DR\r
-.set SCSI_Noise__3__INP_DIS, CYREG_PRT6_INP_DIS\r
-.set SCSI_Noise__3__INTTYPE, CYREG_PICU6_INTTYPE6\r
-.set SCSI_Noise__3__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG\r
-.set SCSI_Noise__3__LCD_EN, CYREG_PRT6_LCD_EN\r
-.set SCSI_Noise__3__MASK, 0x40\r
-.set SCSI_Noise__3__PC, CYREG_PRT6_PC6\r
-.set SCSI_Noise__3__PORT, 6\r
-.set SCSI_Noise__3__PRT, CYREG_PRT6_PRT\r
-.set SCSI_Noise__3__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL\r
-.set SCSI_Noise__3__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN\r
-.set SCSI_Noise__3__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0\r
-.set SCSI_Noise__3__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1\r
-.set SCSI_Noise__3__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0\r
-.set SCSI_Noise__3__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1\r
-.set SCSI_Noise__3__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT\r
-.set SCSI_Noise__3__PS, CYREG_PRT6_PS\r
-.set SCSI_Noise__3__SHIFT, 6\r
-.set SCSI_Noise__3__SLW, CYREG_PRT6_SLW\r
-.set SCSI_Noise__4__AG, CYREG_PRT6_AG\r
-.set SCSI_Noise__4__AMUX, CYREG_PRT6_AMUX\r
-.set SCSI_Noise__4__BIE, CYREG_PRT6_BIE\r
-.set SCSI_Noise__4__BIT_MASK, CYREG_PRT6_BIT_MASK\r
-.set SCSI_Noise__4__BYP, CYREG_PRT6_BYP\r
-.set SCSI_Noise__4__CTL, CYREG_PRT6_CTL\r
-.set SCSI_Noise__4__DM0, CYREG_PRT6_DM0\r
-.set SCSI_Noise__4__DM1, CYREG_PRT6_DM1\r
-.set SCSI_Noise__4__DM2, CYREG_PRT6_DM2\r
-.set SCSI_Noise__4__DR, CYREG_PRT6_DR\r
-.set SCSI_Noise__4__INP_DIS, CYREG_PRT6_INP_DIS\r
-.set SCSI_Noise__4__INTTYPE, CYREG_PICU6_INTTYPE5\r
-.set SCSI_Noise__4__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG\r
-.set SCSI_Noise__4__LCD_EN, CYREG_PRT6_LCD_EN\r
-.set SCSI_Noise__4__MASK, 0x20\r
-.set SCSI_Noise__4__PC, CYREG_PRT6_PC5\r
-.set SCSI_Noise__4__PORT, 6\r
-.set SCSI_Noise__4__PRT, CYREG_PRT6_PRT\r
-.set SCSI_Noise__4__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL\r
-.set SCSI_Noise__4__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN\r
-.set SCSI_Noise__4__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0\r
-.set SCSI_Noise__4__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1\r
-.set SCSI_Noise__4__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0\r
-.set SCSI_Noise__4__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1\r
-.set SCSI_Noise__4__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT\r
-.set SCSI_Noise__4__PS, CYREG_PRT6_PS\r
-.set SCSI_Noise__4__SHIFT, 5\r
-.set SCSI_Noise__4__SLW, CYREG_PRT6_SLW\r
-.set SCSI_Noise__ACK__AG, CYREG_PRT6_AG\r
-.set SCSI_Noise__ACK__AMUX, CYREG_PRT6_AMUX\r
-.set SCSI_Noise__ACK__BIE, CYREG_PRT6_BIE\r
-.set SCSI_Noise__ACK__BIT_MASK, CYREG_PRT6_BIT_MASK\r
-.set SCSI_Noise__ACK__BYP, CYREG_PRT6_BYP\r
-.set SCSI_Noise__ACK__CTL, CYREG_PRT6_CTL\r
-.set SCSI_Noise__ACK__DM0, CYREG_PRT6_DM0\r
-.set SCSI_Noise__ACK__DM1, CYREG_PRT6_DM1\r
-.set SCSI_Noise__ACK__DM2, CYREG_PRT6_DM2\r
-.set SCSI_Noise__ACK__DR, CYREG_PRT6_DR\r
-.set SCSI_Noise__ACK__INP_DIS, CYREG_PRT6_INP_DIS\r
-.set SCSI_Noise__ACK__INTTYPE, CYREG_PICU6_INTTYPE5\r
-.set SCSI_Noise__ACK__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG\r
-.set SCSI_Noise__ACK__LCD_EN, CYREG_PRT6_LCD_EN\r
-.set SCSI_Noise__ACK__MASK, 0x20\r
-.set SCSI_Noise__ACK__PC, CYREG_PRT6_PC5\r
-.set SCSI_Noise__ACK__PORT, 6\r
-.set SCSI_Noise__ACK__PRT, CYREG_PRT6_PRT\r
-.set SCSI_Noise__ACK__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL\r
-.set SCSI_Noise__ACK__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN\r
-.set SCSI_Noise__ACK__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0\r
-.set SCSI_Noise__ACK__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1\r
-.set SCSI_Noise__ACK__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0\r
-.set SCSI_Noise__ACK__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1\r
-.set SCSI_Noise__ACK__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT\r
-.set SCSI_Noise__ACK__PS, CYREG_PRT6_PS\r
-.set SCSI_Noise__ACK__SHIFT, 5\r
-.set SCSI_Noise__ACK__SLW, CYREG_PRT6_SLW\r
-.set SCSI_Noise__ATN__AG, CYREG_PRT12_AG\r
-.set SCSI_Noise__ATN__BIE, CYREG_PRT12_BIE\r
-.set SCSI_Noise__ATN__BIT_MASK, CYREG_PRT12_BIT_MASK\r
-.set SCSI_Noise__ATN__BYP, CYREG_PRT12_BYP\r
-.set SCSI_Noise__ATN__DM0, CYREG_PRT12_DM0\r
-.set SCSI_Noise__ATN__DM1, CYREG_PRT12_DM1\r
-.set SCSI_Noise__ATN__DM2, CYREG_PRT12_DM2\r
-.set SCSI_Noise__ATN__DR, CYREG_PRT12_DR\r
-.set SCSI_Noise__ATN__INP_DIS, CYREG_PRT12_INP_DIS\r
-.set SCSI_Noise__ATN__INTTYPE, CYREG_PICU12_INTTYPE5\r
-.set SCSI_Noise__ATN__MASK, 0x20\r
-.set SCSI_Noise__ATN__PC, CYREG_PRT12_PC5\r
-.set SCSI_Noise__ATN__PORT, 12\r
-.set SCSI_Noise__ATN__PRT, CYREG_PRT12_PRT\r
-.set SCSI_Noise__ATN__PRTDSI__DBL_SYNC_IN, CYREG_PRT12_DBL_SYNC_IN\r
-.set SCSI_Noise__ATN__PRTDSI__OE_SEL0, CYREG_PRT12_OE_SEL0\r
-.set SCSI_Noise__ATN__PRTDSI__OE_SEL1, CYREG_PRT12_OE_SEL1\r
-.set SCSI_Noise__ATN__PRTDSI__OUT_SEL0, CYREG_PRT12_OUT_SEL0\r
-.set SCSI_Noise__ATN__PRTDSI__OUT_SEL1, CYREG_PRT12_OUT_SEL1\r
-.set SCSI_Noise__ATN__PRTDSI__SYNC_OUT, CYREG_PRT12_SYNC_OUT\r
-.set SCSI_Noise__ATN__PS, CYREG_PRT12_PS\r
-.set SCSI_Noise__ATN__SHIFT, 5\r
-.set SCSI_Noise__ATN__SIO_CFG, CYREG_PRT12_SIO_CFG\r
-.set SCSI_Noise__ATN__SIO_DIFF, CYREG_PRT12_SIO_DIFF\r
-.set SCSI_Noise__ATN__SIO_HYST_EN, CYREG_PRT12_SIO_HYST_EN\r
-.set SCSI_Noise__ATN__SIO_REG_HIFREQ, CYREG_PRT12_SIO_REG_HIFREQ\r
-.set SCSI_Noise__ATN__SLW, CYREG_PRT12_SLW\r
-.set SCSI_Noise__BSY__AG, CYREG_PRT6_AG\r
-.set SCSI_Noise__BSY__AMUX, CYREG_PRT6_AMUX\r
-.set SCSI_Noise__BSY__BIE, CYREG_PRT6_BIE\r
-.set SCSI_Noise__BSY__BIT_MASK, CYREG_PRT6_BIT_MASK\r
-.set SCSI_Noise__BSY__BYP, CYREG_PRT6_BYP\r
-.set SCSI_Noise__BSY__CTL, CYREG_PRT6_CTL\r
-.set SCSI_Noise__BSY__DM0, CYREG_PRT6_DM0\r
-.set SCSI_Noise__BSY__DM1, CYREG_PRT6_DM1\r
-.set SCSI_Noise__BSY__DM2, CYREG_PRT6_DM2\r
-.set SCSI_Noise__BSY__DR, CYREG_PRT6_DR\r
-.set SCSI_Noise__BSY__INP_DIS, CYREG_PRT6_INP_DIS\r
-.set SCSI_Noise__BSY__INTTYPE, CYREG_PICU6_INTTYPE4\r
-.set SCSI_Noise__BSY__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG\r
-.set SCSI_Noise__BSY__LCD_EN, CYREG_PRT6_LCD_EN\r
-.set SCSI_Noise__BSY__MASK, 0x10\r
-.set SCSI_Noise__BSY__PC, CYREG_PRT6_PC4\r
-.set SCSI_Noise__BSY__PORT, 6\r
-.set SCSI_Noise__BSY__PRT, CYREG_PRT6_PRT\r
-.set SCSI_Noise__BSY__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL\r
-.set SCSI_Noise__BSY__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN\r
-.set SCSI_Noise__BSY__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0\r
-.set SCSI_Noise__BSY__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1\r
-.set SCSI_Noise__BSY__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0\r
-.set SCSI_Noise__BSY__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1\r
-.set SCSI_Noise__BSY__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT\r
-.set SCSI_Noise__BSY__PS, CYREG_PRT6_PS\r
-.set SCSI_Noise__BSY__SHIFT, 4\r
-.set SCSI_Noise__BSY__SLW, CYREG_PRT6_SLW\r
-.set SCSI_Noise__RST__AG, CYREG_PRT6_AG\r
-.set SCSI_Noise__RST__AMUX, CYREG_PRT6_AMUX\r
-.set SCSI_Noise__RST__BIE, CYREG_PRT6_BIE\r
-.set SCSI_Noise__RST__BIT_MASK, CYREG_PRT6_BIT_MASK\r
-.set SCSI_Noise__RST__BYP, CYREG_PRT6_BYP\r
-.set SCSI_Noise__RST__CTL, CYREG_PRT6_CTL\r
-.set SCSI_Noise__RST__DM0, CYREG_PRT6_DM0\r
-.set SCSI_Noise__RST__DM1, CYREG_PRT6_DM1\r
-.set SCSI_Noise__RST__DM2, CYREG_PRT6_DM2\r
-.set SCSI_Noise__RST__DR, CYREG_PRT6_DR\r
-.set SCSI_Noise__RST__INP_DIS, CYREG_PRT6_INP_DIS\r
-.set SCSI_Noise__RST__INTTYPE, CYREG_PICU6_INTTYPE6\r
-.set SCSI_Noise__RST__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG\r
-.set SCSI_Noise__RST__LCD_EN, CYREG_PRT6_LCD_EN\r
-.set SCSI_Noise__RST__MASK, 0x40\r
-.set SCSI_Noise__RST__PC, CYREG_PRT6_PC6\r
-.set SCSI_Noise__RST__PORT, 6\r
-.set SCSI_Noise__RST__PRT, CYREG_PRT6_PRT\r
-.set SCSI_Noise__RST__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL\r
-.set SCSI_Noise__RST__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN\r
-.set SCSI_Noise__RST__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0\r
-.set SCSI_Noise__RST__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1\r
-.set SCSI_Noise__RST__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0\r
-.set SCSI_Noise__RST__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1\r
-.set SCSI_Noise__RST__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT\r
-.set SCSI_Noise__RST__PS, CYREG_PRT6_PS\r
-.set SCSI_Noise__RST__SHIFT, 6\r
-.set SCSI_Noise__RST__SLW, CYREG_PRT6_SLW\r
-.set SCSI_Noise__SEL__AG, CYREG_PRT5_AG\r
-.set SCSI_Noise__SEL__AMUX, CYREG_PRT5_AMUX\r
-.set SCSI_Noise__SEL__BIE, CYREG_PRT5_BIE\r
-.set SCSI_Noise__SEL__BIT_MASK, CYREG_PRT5_BIT_MASK\r
-.set SCSI_Noise__SEL__BYP, CYREG_PRT5_BYP\r
-.set SCSI_Noise__SEL__CTL, CYREG_PRT5_CTL\r
-.set SCSI_Noise__SEL__DM0, CYREG_PRT5_DM0\r
-.set SCSI_Noise__SEL__DM1, CYREG_PRT5_DM1\r
-.set SCSI_Noise__SEL__DM2, CYREG_PRT5_DM2\r
-.set SCSI_Noise__SEL__DR, CYREG_PRT5_DR\r
-.set SCSI_Noise__SEL__INP_DIS, CYREG_PRT5_INP_DIS\r
-.set SCSI_Noise__SEL__INTTYPE, CYREG_PICU5_INTTYPE0\r
-.set SCSI_Noise__SEL__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG\r
-.set SCSI_Noise__SEL__LCD_EN, CYREG_PRT5_LCD_EN\r
-.set SCSI_Noise__SEL__MASK, 0x01\r
-.set SCSI_Noise__SEL__PC, CYREG_PRT5_PC0\r
-.set SCSI_Noise__SEL__PORT, 5\r
-.set SCSI_Noise__SEL__PRT, CYREG_PRT5_PRT\r
-.set SCSI_Noise__SEL__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL\r
-.set SCSI_Noise__SEL__PRTDSI__DBL_SYNC_IN, CYREG_PRT5_DBL_SYNC_IN\r
-.set SCSI_Noise__SEL__PRTDSI__OE_SEL0, CYREG_PRT5_OE_SEL0\r
-.set SCSI_Noise__SEL__PRTDSI__OE_SEL1, CYREG_PRT5_OE_SEL1\r
-.set SCSI_Noise__SEL__PRTDSI__OUT_SEL0, CYREG_PRT5_OUT_SEL0\r
-.set SCSI_Noise__SEL__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1\r
-.set SCSI_Noise__SEL__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT\r
-.set SCSI_Noise__SEL__PS, CYREG_PRT5_PS\r
-.set SCSI_Noise__SEL__SHIFT, 0\r
-.set SCSI_Noise__SEL__SLW, CYREG_PRT5_SLW\r
-\r
-/* SCSI_Out */\r
-.set SCSI_Out__0__AG, CYREG_PRT4_AG\r
-.set SCSI_Out__0__AMUX, CYREG_PRT4_AMUX\r
-.set SCSI_Out__0__BIE, CYREG_PRT4_BIE\r
-.set SCSI_Out__0__BIT_MASK, CYREG_PRT4_BIT_MASK\r
-.set SCSI_Out__0__BYP, CYREG_PRT4_BYP\r
-.set SCSI_Out__0__CTL, CYREG_PRT4_CTL\r
-.set SCSI_Out__0__DM0, CYREG_PRT4_DM0\r
-.set SCSI_Out__0__DM1, CYREG_PRT4_DM1\r
-.set SCSI_Out__0__DM2, CYREG_PRT4_DM2\r
-.set SCSI_Out__0__DR, CYREG_PRT4_DR\r
-.set SCSI_Out__0__INP_DIS, CYREG_PRT4_INP_DIS\r
-.set SCSI_Out__0__INTTYPE, CYREG_PICU4_INTTYPE3\r
-.set SCSI_Out__0__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG\r
-.set SCSI_Out__0__LCD_EN, CYREG_PRT4_LCD_EN\r
-.set SCSI_Out__0__MASK, 0x08\r
-.set SCSI_Out__0__PC, CYREG_PRT4_PC3\r
-.set SCSI_Out__0__PORT, 4\r
-.set SCSI_Out__0__PRT, CYREG_PRT4_PRT\r
-.set SCSI_Out__0__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL\r
-.set SCSI_Out__0__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN\r
-.set SCSI_Out__0__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0\r
-.set SCSI_Out__0__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1\r
-.set SCSI_Out__0__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0\r
-.set SCSI_Out__0__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1\r
-.set SCSI_Out__0__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT\r
-.set SCSI_Out__0__PS, CYREG_PRT4_PS\r
-.set SCSI_Out__0__SHIFT, 3\r
-.set SCSI_Out__0__SLW, CYREG_PRT4_SLW\r
-.set SCSI_Out__1__AG, CYREG_PRT4_AG\r
-.set SCSI_Out__1__AMUX, CYREG_PRT4_AMUX\r
-.set SCSI_Out__1__BIE, CYREG_PRT4_BIE\r
-.set SCSI_Out__1__BIT_MASK, CYREG_PRT4_BIT_MASK\r
-.set SCSI_Out__1__BYP, CYREG_PRT4_BYP\r
-.set SCSI_Out__1__CTL, CYREG_PRT4_CTL\r
-.set SCSI_Out__1__DM0, CYREG_PRT4_DM0\r
-.set SCSI_Out__1__DM1, CYREG_PRT4_DM1\r
-.set SCSI_Out__1__DM2, CYREG_PRT4_DM2\r
-.set SCSI_Out__1__DR, CYREG_PRT4_DR\r
-.set SCSI_Out__1__INP_DIS, CYREG_PRT4_INP_DIS\r
-.set SCSI_Out__1__INTTYPE, CYREG_PICU4_INTTYPE2\r
-.set SCSI_Out__1__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG\r
-.set SCSI_Out__1__LCD_EN, CYREG_PRT4_LCD_EN\r
-.set SCSI_Out__1__MASK, 0x04\r
-.set SCSI_Out__1__PC, CYREG_PRT4_PC2\r
-.set SCSI_Out__1__PORT, 4\r
-.set SCSI_Out__1__PRT, CYREG_PRT4_PRT\r
-.set SCSI_Out__1__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL\r
-.set SCSI_Out__1__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN\r
-.set SCSI_Out__1__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0\r
-.set SCSI_Out__1__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1\r
-.set SCSI_Out__1__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0\r
-.set SCSI_Out__1__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1\r
-.set SCSI_Out__1__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT\r
-.set SCSI_Out__1__PS, CYREG_PRT4_PS\r
-.set SCSI_Out__1__SHIFT, 2\r
-.set SCSI_Out__1__SLW, CYREG_PRT4_SLW\r
-.set SCSI_Out__2__AG, CYREG_PRT0_AG\r
-.set SCSI_Out__2__AMUX, CYREG_PRT0_AMUX\r
-.set SCSI_Out__2__BIE, CYREG_PRT0_BIE\r
-.set SCSI_Out__2__BIT_MASK, CYREG_PRT0_BIT_MASK\r
-.set SCSI_Out__2__BYP, CYREG_PRT0_BYP\r
-.set SCSI_Out__2__CTL, CYREG_PRT0_CTL\r
-.set SCSI_Out__2__DM0, CYREG_PRT0_DM0\r
-.set SCSI_Out__2__DM1, CYREG_PRT0_DM1\r
-.set SCSI_Out__2__DM2, CYREG_PRT0_DM2\r
-.set SCSI_Out__2__DR, CYREG_PRT0_DR\r
-.set SCSI_Out__2__INP_DIS, CYREG_PRT0_INP_DIS\r
-.set SCSI_Out__2__INTTYPE, CYREG_PICU0_INTTYPE7\r
-.set SCSI_Out__2__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG\r
-.set SCSI_Out__2__LCD_EN, CYREG_PRT0_LCD_EN\r
-.set SCSI_Out__2__MASK, 0x80\r
-.set SCSI_Out__2__PC, CYREG_PRT0_PC7\r
-.set SCSI_Out__2__PORT, 0\r
-.set SCSI_Out__2__PRT, CYREG_PRT0_PRT\r
-.set SCSI_Out__2__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL\r
-.set SCSI_Out__2__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN\r
-.set SCSI_Out__2__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0\r
-.set SCSI_Out__2__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1\r
-.set SCSI_Out__2__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0\r
-.set SCSI_Out__2__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1\r
-.set SCSI_Out__2__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT\r
-.set SCSI_Out__2__PS, CYREG_PRT0_PS\r
-.set SCSI_Out__2__SHIFT, 7\r
-.set SCSI_Out__2__SLW, CYREG_PRT0_SLW\r
-.set SCSI_Out__3__AG, CYREG_PRT0_AG\r
-.set SCSI_Out__3__AMUX, CYREG_PRT0_AMUX\r
-.set SCSI_Out__3__BIE, CYREG_PRT0_BIE\r
-.set SCSI_Out__3__BIT_MASK, CYREG_PRT0_BIT_MASK\r
-.set SCSI_Out__3__BYP, CYREG_PRT0_BYP\r
-.set SCSI_Out__3__CTL, CYREG_PRT0_CTL\r
-.set SCSI_Out__3__DM0, CYREG_PRT0_DM0\r
-.set SCSI_Out__3__DM1, CYREG_PRT0_DM1\r
-.set SCSI_Out__3__DM2, CYREG_PRT0_DM2\r
-.set SCSI_Out__3__DR, CYREG_PRT0_DR\r
-.set SCSI_Out__3__INP_DIS, CYREG_PRT0_INP_DIS\r
-.set SCSI_Out__3__INTTYPE, CYREG_PICU0_INTTYPE6\r
-.set SCSI_Out__3__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG\r
-.set SCSI_Out__3__LCD_EN, CYREG_PRT0_LCD_EN\r
-.set SCSI_Out__3__MASK, 0x40\r
-.set SCSI_Out__3__PC, CYREG_PRT0_PC6\r
-.set SCSI_Out__3__PORT, 0\r
-.set SCSI_Out__3__PRT, CYREG_PRT0_PRT\r
-.set SCSI_Out__3__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL\r
-.set SCSI_Out__3__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN\r
-.set SCSI_Out__3__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0\r
-.set SCSI_Out__3__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1\r
-.set SCSI_Out__3__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0\r
-.set SCSI_Out__3__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1\r
-.set SCSI_Out__3__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT\r
-.set SCSI_Out__3__PS, CYREG_PRT0_PS\r
-.set SCSI_Out__3__SHIFT, 6\r
-.set SCSI_Out__3__SLW, CYREG_PRT0_SLW\r
-.set SCSI_Out__4__AG, CYREG_PRT0_AG\r
-.set SCSI_Out__4__AMUX, CYREG_PRT0_AMUX\r
-.set SCSI_Out__4__BIE, CYREG_PRT0_BIE\r
-.set SCSI_Out__4__BIT_MASK, CYREG_PRT0_BIT_MASK\r
-.set SCSI_Out__4__BYP, CYREG_PRT0_BYP\r
-.set SCSI_Out__4__CTL, CYREG_PRT0_CTL\r
-.set SCSI_Out__4__DM0, CYREG_PRT0_DM0\r
-.set SCSI_Out__4__DM1, CYREG_PRT0_DM1\r
-.set SCSI_Out__4__DM2, CYREG_PRT0_DM2\r
-.set SCSI_Out__4__DR, CYREG_PRT0_DR\r
-.set SCSI_Out__4__INP_DIS, CYREG_PRT0_INP_DIS\r
-.set SCSI_Out__4__INTTYPE, CYREG_PICU0_INTTYPE5\r
-.set SCSI_Out__4__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG\r
-.set SCSI_Out__4__LCD_EN, CYREG_PRT0_LCD_EN\r
-.set SCSI_Out__4__MASK, 0x20\r
-.set SCSI_Out__4__PC, CYREG_PRT0_PC5\r
-.set SCSI_Out__4__PORT, 0\r
-.set SCSI_Out__4__PRT, CYREG_PRT0_PRT\r
-.set SCSI_Out__4__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL\r
-.set SCSI_Out__4__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN\r
-.set SCSI_Out__4__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0\r
-.set SCSI_Out__4__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1\r
-.set SCSI_Out__4__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0\r
-.set SCSI_Out__4__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1\r
-.set SCSI_Out__4__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT\r
-.set SCSI_Out__4__PS, CYREG_PRT0_PS\r
-.set SCSI_Out__4__SHIFT, 5\r
-.set SCSI_Out__4__SLW, CYREG_PRT0_SLW\r
-.set SCSI_Out__5__AG, CYREG_PRT0_AG\r
-.set SCSI_Out__5__AMUX, CYREG_PRT0_AMUX\r
-.set SCSI_Out__5__BIE, CYREG_PRT0_BIE\r
-.set SCSI_Out__5__BIT_MASK, CYREG_PRT0_BIT_MASK\r
-.set SCSI_Out__5__BYP, CYREG_PRT0_BYP\r
-.set SCSI_Out__5__CTL, CYREG_PRT0_CTL\r
-.set SCSI_Out__5__DM0, CYREG_PRT0_DM0\r
-.set SCSI_Out__5__DM1, CYREG_PRT0_DM1\r
-.set SCSI_Out__5__DM2, CYREG_PRT0_DM2\r
-.set SCSI_Out__5__DR, CYREG_PRT0_DR\r
-.set SCSI_Out__5__INP_DIS, CYREG_PRT0_INP_DIS\r
-.set SCSI_Out__5__INTTYPE, CYREG_PICU0_INTTYPE4\r
-.set SCSI_Out__5__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG\r
-.set SCSI_Out__5__LCD_EN, CYREG_PRT0_LCD_EN\r
-.set SCSI_Out__5__MASK, 0x10\r
-.set SCSI_Out__5__PC, CYREG_PRT0_PC4\r
-.set SCSI_Out__5__PORT, 0\r
-.set SCSI_Out__5__PRT, CYREG_PRT0_PRT\r
-.set SCSI_Out__5__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL\r
-.set SCSI_Out__5__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN\r
-.set SCSI_Out__5__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0\r
-.set SCSI_Out__5__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1\r
-.set SCSI_Out__5__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0\r
-.set SCSI_Out__5__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1\r
-.set SCSI_Out__5__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT\r
-.set SCSI_Out__5__PS, CYREG_PRT0_PS\r
-.set SCSI_Out__5__SHIFT, 4\r
-.set SCSI_Out__5__SLW, CYREG_PRT0_SLW\r
-.set SCSI_Out__6__AG, CYREG_PRT0_AG\r
-.set SCSI_Out__6__AMUX, CYREG_PRT0_AMUX\r
-.set SCSI_Out__6__BIE, CYREG_PRT0_BIE\r
-.set SCSI_Out__6__BIT_MASK, CYREG_PRT0_BIT_MASK\r
-.set SCSI_Out__6__BYP, CYREG_PRT0_BYP\r
-.set SCSI_Out__6__CTL, CYREG_PRT0_CTL\r
-.set SCSI_Out__6__DM0, CYREG_PRT0_DM0\r
-.set SCSI_Out__6__DM1, CYREG_PRT0_DM1\r
-.set SCSI_Out__6__DM2, CYREG_PRT0_DM2\r
-.set SCSI_Out__6__DR, CYREG_PRT0_DR\r
-.set SCSI_Out__6__INP_DIS, CYREG_PRT0_INP_DIS\r
-.set SCSI_Out__6__INTTYPE, CYREG_PICU0_INTTYPE3\r
-.set SCSI_Out__6__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG\r
-.set SCSI_Out__6__LCD_EN, CYREG_PRT0_LCD_EN\r
-.set SCSI_Out__6__MASK, 0x08\r
-.set SCSI_Out__6__PC, CYREG_PRT0_PC3\r
-.set SCSI_Out__6__PORT, 0\r
-.set SCSI_Out__6__PRT, CYREG_PRT0_PRT\r
-.set SCSI_Out__6__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL\r
-.set SCSI_Out__6__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN\r
-.set SCSI_Out__6__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0\r
-.set SCSI_Out__6__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1\r
-.set SCSI_Out__6__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0\r
-.set SCSI_Out__6__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1\r
-.set SCSI_Out__6__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT\r
-.set SCSI_Out__6__PS, CYREG_PRT0_PS\r
-.set SCSI_Out__6__SHIFT, 3\r
-.set SCSI_Out__6__SLW, CYREG_PRT0_SLW\r
-.set SCSI_Out__7__AG, CYREG_PRT0_AG\r
-.set SCSI_Out__7__AMUX, CYREG_PRT0_AMUX\r
-.set SCSI_Out__7__BIE, CYREG_PRT0_BIE\r
-.set SCSI_Out__7__BIT_MASK, CYREG_PRT0_BIT_MASK\r
-.set SCSI_Out__7__BYP, CYREG_PRT0_BYP\r
-.set SCSI_Out__7__CTL, CYREG_PRT0_CTL\r
-.set SCSI_Out__7__DM0, CYREG_PRT0_DM0\r
-.set SCSI_Out__7__DM1, CYREG_PRT0_DM1\r
-.set SCSI_Out__7__DM2, CYREG_PRT0_DM2\r
-.set SCSI_Out__7__DR, CYREG_PRT0_DR\r
-.set SCSI_Out__7__INP_DIS, CYREG_PRT0_INP_DIS\r
-.set SCSI_Out__7__INTTYPE, CYREG_PICU0_INTTYPE2\r
-.set SCSI_Out__7__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG\r
-.set SCSI_Out__7__LCD_EN, CYREG_PRT0_LCD_EN\r
-.set SCSI_Out__7__MASK, 0x04\r
-.set SCSI_Out__7__PC, CYREG_PRT0_PC2\r
-.set SCSI_Out__7__PORT, 0\r
-.set SCSI_Out__7__PRT, CYREG_PRT0_PRT\r
-.set SCSI_Out__7__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL\r
-.set SCSI_Out__7__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN\r
-.set SCSI_Out__7__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0\r
-.set SCSI_Out__7__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1\r
-.set SCSI_Out__7__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0\r
-.set SCSI_Out__7__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1\r
-.set SCSI_Out__7__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT\r
-.set SCSI_Out__7__PS, CYREG_PRT0_PS\r
-.set SCSI_Out__7__SHIFT, 2\r
-.set SCSI_Out__7__SLW, CYREG_PRT0_SLW\r
-.set SCSI_Out__8__AG, CYREG_PRT0_AG\r
-.set SCSI_Out__8__AMUX, CYREG_PRT0_AMUX\r
-.set SCSI_Out__8__BIE, CYREG_PRT0_BIE\r
-.set SCSI_Out__8__BIT_MASK, CYREG_PRT0_BIT_MASK\r
-.set SCSI_Out__8__BYP, CYREG_PRT0_BYP\r
-.set SCSI_Out__8__CTL, CYREG_PRT0_CTL\r
-.set SCSI_Out__8__DM0, CYREG_PRT0_DM0\r
-.set SCSI_Out__8__DM1, CYREG_PRT0_DM1\r
-.set SCSI_Out__8__DM2, CYREG_PRT0_DM2\r
-.set SCSI_Out__8__DR, CYREG_PRT0_DR\r
-.set SCSI_Out__8__INP_DIS, CYREG_PRT0_INP_DIS\r
-.set SCSI_Out__8__INTTYPE, CYREG_PICU0_INTTYPE1\r
-.set SCSI_Out__8__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG\r
-.set SCSI_Out__8__LCD_EN, CYREG_PRT0_LCD_EN\r
-.set SCSI_Out__8__MASK, 0x02\r
-.set SCSI_Out__8__PC, CYREG_PRT0_PC1\r
-.set SCSI_Out__8__PORT, 0\r
-.set SCSI_Out__8__PRT, CYREG_PRT0_PRT\r
-.set SCSI_Out__8__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL\r
-.set SCSI_Out__8__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN\r
-.set SCSI_Out__8__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0\r
-.set SCSI_Out__8__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1\r
-.set SCSI_Out__8__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0\r
-.set SCSI_Out__8__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1\r
-.set SCSI_Out__8__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT\r
-.set SCSI_Out__8__PS, CYREG_PRT0_PS\r
-.set SCSI_Out__8__SHIFT, 1\r
-.set SCSI_Out__8__SLW, CYREG_PRT0_SLW\r
-.set SCSI_Out__9__AG, CYREG_PRT0_AG\r
-.set SCSI_Out__9__AMUX, CYREG_PRT0_AMUX\r
-.set SCSI_Out__9__BIE, CYREG_PRT0_BIE\r
-.set SCSI_Out__9__BIT_MASK, CYREG_PRT0_BIT_MASK\r
-.set SCSI_Out__9__BYP, CYREG_PRT0_BYP\r
-.set SCSI_Out__9__CTL, CYREG_PRT0_CTL\r
-.set SCSI_Out__9__DM0, CYREG_PRT0_DM0\r
-.set SCSI_Out__9__DM1, CYREG_PRT0_DM1\r
-.set SCSI_Out__9__DM2, CYREG_PRT0_DM2\r
-.set SCSI_Out__9__DR, CYREG_PRT0_DR\r
-.set SCSI_Out__9__INP_DIS, CYREG_PRT0_INP_DIS\r
-.set SCSI_Out__9__INTTYPE, CYREG_PICU0_INTTYPE0\r
-.set SCSI_Out__9__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG\r
-.set SCSI_Out__9__LCD_EN, CYREG_PRT0_LCD_EN\r
-.set SCSI_Out__9__MASK, 0x01\r
-.set SCSI_Out__9__PC, CYREG_PRT0_PC0\r
-.set SCSI_Out__9__PORT, 0\r
-.set SCSI_Out__9__PRT, CYREG_PRT0_PRT\r
-.set SCSI_Out__9__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL\r
-.set SCSI_Out__9__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN\r
-.set SCSI_Out__9__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0\r
-.set SCSI_Out__9__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1\r
-.set SCSI_Out__9__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0\r
-.set SCSI_Out__9__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1\r
-.set SCSI_Out__9__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT\r
-.set SCSI_Out__9__PS, CYREG_PRT0_PS\r
-.set SCSI_Out__9__SHIFT, 0\r
-.set SCSI_Out__9__SLW, CYREG_PRT0_SLW\r
-.set SCSI_Out__ACK__AG, CYREG_PRT0_AG\r
-.set SCSI_Out__ACK__AMUX, CYREG_PRT0_AMUX\r
-.set SCSI_Out__ACK__BIE, CYREG_PRT0_BIE\r
-.set SCSI_Out__ACK__BIT_MASK, CYREG_PRT0_BIT_MASK\r
-.set SCSI_Out__ACK__BYP, CYREG_PRT0_BYP\r
-.set SCSI_Out__ACK__CTL, CYREG_PRT0_CTL\r
-.set SCSI_Out__ACK__DM0, CYREG_PRT0_DM0\r
-.set SCSI_Out__ACK__DM1, CYREG_PRT0_DM1\r
-.set SCSI_Out__ACK__DM2, CYREG_PRT0_DM2\r
-.set SCSI_Out__ACK__DR, CYREG_PRT0_DR\r
-.set SCSI_Out__ACK__INP_DIS, CYREG_PRT0_INP_DIS\r
-.set SCSI_Out__ACK__INTTYPE, CYREG_PICU0_INTTYPE6\r
-.set SCSI_Out__ACK__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG\r
-.set SCSI_Out__ACK__LCD_EN, CYREG_PRT0_LCD_EN\r
-.set SCSI_Out__ACK__MASK, 0x40\r
-.set SCSI_Out__ACK__PC, CYREG_PRT0_PC6\r
-.set SCSI_Out__ACK__PORT, 0\r
-.set SCSI_Out__ACK__PRT, CYREG_PRT0_PRT\r
-.set SCSI_Out__ACK__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL\r
-.set SCSI_Out__ACK__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN\r
-.set SCSI_Out__ACK__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0\r
-.set SCSI_Out__ACK__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1\r
-.set SCSI_Out__ACK__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0\r
-.set SCSI_Out__ACK__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1\r
-.set SCSI_Out__ACK__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT\r
-.set SCSI_Out__ACK__PS, CYREG_PRT0_PS\r
-.set SCSI_Out__ACK__SHIFT, 6\r
-.set SCSI_Out__ACK__SLW, CYREG_PRT0_SLW\r
-.set SCSI_Out__ATN__AG, CYREG_PRT4_AG\r
-.set SCSI_Out__ATN__AMUX, CYREG_PRT4_AMUX\r
-.set SCSI_Out__ATN__BIE, CYREG_PRT4_BIE\r
-.set SCSI_Out__ATN__BIT_MASK, CYREG_PRT4_BIT_MASK\r
-.set SCSI_Out__ATN__BYP, CYREG_PRT4_BYP\r
-.set SCSI_Out__ATN__CTL, CYREG_PRT4_CTL\r
-.set SCSI_Out__ATN__DM0, CYREG_PRT4_DM0\r
-.set SCSI_Out__ATN__DM1, CYREG_PRT4_DM1\r
-.set SCSI_Out__ATN__DM2, CYREG_PRT4_DM2\r
-.set SCSI_Out__ATN__DR, CYREG_PRT4_DR\r
-.set SCSI_Out__ATN__INP_DIS, CYREG_PRT4_INP_DIS\r
-.set SCSI_Out__ATN__INTTYPE, CYREG_PICU4_INTTYPE2\r
-.set SCSI_Out__ATN__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG\r
-.set SCSI_Out__ATN__LCD_EN, CYREG_PRT4_LCD_EN\r
-.set SCSI_Out__ATN__MASK, 0x04\r
-.set SCSI_Out__ATN__PC, CYREG_PRT4_PC2\r
-.set SCSI_Out__ATN__PORT, 4\r
-.set SCSI_Out__ATN__PRT, CYREG_PRT4_PRT\r
-.set SCSI_Out__ATN__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL\r
-.set SCSI_Out__ATN__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN\r
-.set SCSI_Out__ATN__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0\r
-.set SCSI_Out__ATN__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1\r
-.set SCSI_Out__ATN__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0\r
-.set SCSI_Out__ATN__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1\r
-.set SCSI_Out__ATN__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT\r
-.set SCSI_Out__ATN__PS, CYREG_PRT4_PS\r
-.set SCSI_Out__ATN__SHIFT, 2\r
-.set SCSI_Out__ATN__SLW, CYREG_PRT4_SLW\r
-.set SCSI_Out__BSY__AG, CYREG_PRT0_AG\r
-.set SCSI_Out__BSY__AMUX, CYREG_PRT0_AMUX\r
-.set SCSI_Out__BSY__BIE, CYREG_PRT0_BIE\r
-.set SCSI_Out__BSY__BIT_MASK, CYREG_PRT0_BIT_MASK\r
-.set SCSI_Out__BSY__BYP, CYREG_PRT0_BYP\r
-.set SCSI_Out__BSY__CTL, CYREG_PRT0_CTL\r
-.set SCSI_Out__BSY__DM0, CYREG_PRT0_DM0\r
-.set SCSI_Out__BSY__DM1, CYREG_PRT0_DM1\r
-.set SCSI_Out__BSY__DM2, CYREG_PRT0_DM2\r
-.set SCSI_Out__BSY__DR, CYREG_PRT0_DR\r
-.set SCSI_Out__BSY__INP_DIS, CYREG_PRT0_INP_DIS\r
-.set SCSI_Out__BSY__INTTYPE, CYREG_PICU0_INTTYPE7\r
-.set SCSI_Out__BSY__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG\r
-.set SCSI_Out__BSY__LCD_EN, CYREG_PRT0_LCD_EN\r
-.set SCSI_Out__BSY__MASK, 0x80\r
-.set SCSI_Out__BSY__PC, CYREG_PRT0_PC7\r
-.set SCSI_Out__BSY__PORT, 0\r
-.set SCSI_Out__BSY__PRT, CYREG_PRT0_PRT\r
-.set SCSI_Out__BSY__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL\r
-.set SCSI_Out__BSY__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN\r
-.set SCSI_Out__BSY__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0\r
-.set SCSI_Out__BSY__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1\r
-.set SCSI_Out__BSY__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0\r
-.set SCSI_Out__BSY__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1\r
-.set SCSI_Out__BSY__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT\r
-.set SCSI_Out__BSY__PS, CYREG_PRT0_PS\r
-.set SCSI_Out__BSY__SHIFT, 7\r
-.set SCSI_Out__BSY__SLW, CYREG_PRT0_SLW\r
-.set SCSI_Out__CD_raw__AG, CYREG_PRT0_AG\r
-.set SCSI_Out__CD_raw__AMUX, CYREG_PRT0_AMUX\r
-.set SCSI_Out__CD_raw__BIE, CYREG_PRT0_BIE\r
-.set SCSI_Out__CD_raw__BIT_MASK, CYREG_PRT0_BIT_MASK\r
-.set SCSI_Out__CD_raw__BYP, CYREG_PRT0_BYP\r
-.set SCSI_Out__CD_raw__CTL, CYREG_PRT0_CTL\r
-.set SCSI_Out__CD_raw__DM0, CYREG_PRT0_DM0\r
-.set SCSI_Out__CD_raw__DM1, CYREG_PRT0_DM1\r
-.set SCSI_Out__CD_raw__DM2, CYREG_PRT0_DM2\r
-.set SCSI_Out__CD_raw__DR, CYREG_PRT0_DR\r
-.set SCSI_Out__CD_raw__INP_DIS, CYREG_PRT0_INP_DIS\r
-.set SCSI_Out__CD_raw__INTTYPE, CYREG_PICU0_INTTYPE2\r
-.set SCSI_Out__CD_raw__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG\r
-.set SCSI_Out__CD_raw__LCD_EN, CYREG_PRT0_LCD_EN\r
-.set SCSI_Out__CD_raw__MASK, 0x04\r
-.set SCSI_Out__CD_raw__PC, CYREG_PRT0_PC2\r
-.set SCSI_Out__CD_raw__PORT, 0\r
-.set SCSI_Out__CD_raw__PRT, CYREG_PRT0_PRT\r
-.set SCSI_Out__CD_raw__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL\r
-.set SCSI_Out__CD_raw__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN\r
-.set SCSI_Out__CD_raw__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0\r
-.set SCSI_Out__CD_raw__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1\r
-.set SCSI_Out__CD_raw__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0\r
-.set SCSI_Out__CD_raw__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1\r
-.set SCSI_Out__CD_raw__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT\r
-.set SCSI_Out__CD_raw__PS, CYREG_PRT0_PS\r
-.set SCSI_Out__CD_raw__SHIFT, 2\r
-.set SCSI_Out__CD_raw__SLW, CYREG_PRT0_SLW\r
-.set SCSI_Out__DBP_raw__AG, CYREG_PRT4_AG\r
-.set SCSI_Out__DBP_raw__AMUX, CYREG_PRT4_AMUX\r
-.set SCSI_Out__DBP_raw__BIE, CYREG_PRT4_BIE\r
-.set SCSI_Out__DBP_raw__BIT_MASK, CYREG_PRT4_BIT_MASK\r
-.set SCSI_Out__DBP_raw__BYP, CYREG_PRT4_BYP\r
-.set SCSI_Out__DBP_raw__CTL, CYREG_PRT4_CTL\r
-.set SCSI_Out__DBP_raw__DM0, CYREG_PRT4_DM0\r
-.set SCSI_Out__DBP_raw__DM1, CYREG_PRT4_DM1\r
-.set SCSI_Out__DBP_raw__DM2, CYREG_PRT4_DM2\r
-.set SCSI_Out__DBP_raw__DR, CYREG_PRT4_DR\r
-.set SCSI_Out__DBP_raw__INP_DIS, CYREG_PRT4_INP_DIS\r
-.set SCSI_Out__DBP_raw__INTTYPE, CYREG_PICU4_INTTYPE3\r
-.set SCSI_Out__DBP_raw__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG\r
-.set SCSI_Out__DBP_raw__LCD_EN, CYREG_PRT4_LCD_EN\r
-.set SCSI_Out__DBP_raw__MASK, 0x08\r
-.set SCSI_Out__DBP_raw__PC, CYREG_PRT4_PC3\r
-.set SCSI_Out__DBP_raw__PORT, 4\r
-.set SCSI_Out__DBP_raw__PRT, CYREG_PRT4_PRT\r
-.set SCSI_Out__DBP_raw__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL\r
-.set SCSI_Out__DBP_raw__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN\r
-.set SCSI_Out__DBP_raw__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0\r
-.set SCSI_Out__DBP_raw__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1\r
-.set SCSI_Out__DBP_raw__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0\r
-.set SCSI_Out__DBP_raw__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1\r
-.set SCSI_Out__DBP_raw__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT\r
-.set SCSI_Out__DBP_raw__PS, CYREG_PRT4_PS\r
-.set SCSI_Out__DBP_raw__SHIFT, 3\r
-.set SCSI_Out__DBP_raw__SLW, CYREG_PRT4_SLW\r
-.set SCSI_Out__IO_raw__AG, CYREG_PRT0_AG\r
-.set SCSI_Out__IO_raw__AMUX, CYREG_PRT0_AMUX\r
-.set SCSI_Out__IO_raw__BIE, CYREG_PRT0_BIE\r
-.set SCSI_Out__IO_raw__BIT_MASK, CYREG_PRT0_BIT_MASK\r
-.set SCSI_Out__IO_raw__BYP, CYREG_PRT0_BYP\r
-.set SCSI_Out__IO_raw__CTL, CYREG_PRT0_CTL\r
-.set SCSI_Out__IO_raw__DM0, CYREG_PRT0_DM0\r
-.set SCSI_Out__IO_raw__DM1, CYREG_PRT0_DM1\r
-.set SCSI_Out__IO_raw__DM2, CYREG_PRT0_DM2\r
-.set SCSI_Out__IO_raw__DR, CYREG_PRT0_DR\r
-.set SCSI_Out__IO_raw__INP_DIS, CYREG_PRT0_INP_DIS\r
-.set SCSI_Out__IO_raw__INTTYPE, CYREG_PICU0_INTTYPE0\r
-.set SCSI_Out__IO_raw__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG\r
-.set SCSI_Out__IO_raw__LCD_EN, CYREG_PRT0_LCD_EN\r
-.set SCSI_Out__IO_raw__MASK, 0x01\r
-.set SCSI_Out__IO_raw__PC, CYREG_PRT0_PC0\r
-.set SCSI_Out__IO_raw__PORT, 0\r
-.set SCSI_Out__IO_raw__PRT, CYREG_PRT0_PRT\r
-.set SCSI_Out__IO_raw__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL\r
-.set SCSI_Out__IO_raw__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN\r
-.set SCSI_Out__IO_raw__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0\r
-.set SCSI_Out__IO_raw__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1\r
-.set SCSI_Out__IO_raw__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0\r
-.set SCSI_Out__IO_raw__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1\r
-.set SCSI_Out__IO_raw__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT\r
-.set SCSI_Out__IO_raw__PS, CYREG_PRT0_PS\r
-.set SCSI_Out__IO_raw__SHIFT, 0\r
-.set SCSI_Out__IO_raw__SLW, CYREG_PRT0_SLW\r
-.set SCSI_Out__MSG_raw__AG, CYREG_PRT0_AG\r
-.set SCSI_Out__MSG_raw__AMUX, CYREG_PRT0_AMUX\r
-.set SCSI_Out__MSG_raw__BIE, CYREG_PRT0_BIE\r
-.set SCSI_Out__MSG_raw__BIT_MASK, CYREG_PRT0_BIT_MASK\r
-.set SCSI_Out__MSG_raw__BYP, CYREG_PRT0_BYP\r
-.set SCSI_Out__MSG_raw__CTL, CYREG_PRT0_CTL\r
-.set SCSI_Out__MSG_raw__DM0, CYREG_PRT0_DM0\r
-.set SCSI_Out__MSG_raw__DM1, CYREG_PRT0_DM1\r
-.set SCSI_Out__MSG_raw__DM2, CYREG_PRT0_DM2\r
-.set SCSI_Out__MSG_raw__DR, CYREG_PRT0_DR\r
-.set SCSI_Out__MSG_raw__INP_DIS, CYREG_PRT0_INP_DIS\r
-.set SCSI_Out__MSG_raw__INTTYPE, CYREG_PICU0_INTTYPE4\r
-.set SCSI_Out__MSG_raw__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG\r
-.set SCSI_Out__MSG_raw__LCD_EN, CYREG_PRT0_LCD_EN\r
-.set SCSI_Out__MSG_raw__MASK, 0x10\r
-.set SCSI_Out__MSG_raw__PC, CYREG_PRT0_PC4\r
-.set SCSI_Out__MSG_raw__PORT, 0\r
-.set SCSI_Out__MSG_raw__PRT, CYREG_PRT0_PRT\r
-.set SCSI_Out__MSG_raw__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL\r
-.set SCSI_Out__MSG_raw__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN\r
-.set SCSI_Out__MSG_raw__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0\r
-.set SCSI_Out__MSG_raw__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1\r
-.set SCSI_Out__MSG_raw__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0\r
-.set SCSI_Out__MSG_raw__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1\r
-.set SCSI_Out__MSG_raw__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT\r
-.set SCSI_Out__MSG_raw__PS, CYREG_PRT0_PS\r
-.set SCSI_Out__MSG_raw__SHIFT, 4\r
-.set SCSI_Out__MSG_raw__SLW, CYREG_PRT0_SLW\r
-.set SCSI_Out__REQ__AG, CYREG_PRT0_AG\r
-.set SCSI_Out__REQ__AMUX, CYREG_PRT0_AMUX\r
-.set SCSI_Out__REQ__BIE, CYREG_PRT0_BIE\r
-.set SCSI_Out__REQ__BIT_MASK, CYREG_PRT0_BIT_MASK\r
-.set SCSI_Out__REQ__BYP, CYREG_PRT0_BYP\r
-.set SCSI_Out__REQ__CTL, CYREG_PRT0_CTL\r
-.set SCSI_Out__REQ__DM0, CYREG_PRT0_DM0\r
-.set SCSI_Out__REQ__DM1, CYREG_PRT0_DM1\r
-.set SCSI_Out__REQ__DM2, CYREG_PRT0_DM2\r
-.set SCSI_Out__REQ__DR, CYREG_PRT0_DR\r
-.set SCSI_Out__REQ__INP_DIS, CYREG_PRT0_INP_DIS\r
-.set SCSI_Out__REQ__INTTYPE, CYREG_PICU0_INTTYPE1\r
-.set SCSI_Out__REQ__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG\r
-.set SCSI_Out__REQ__LCD_EN, CYREG_PRT0_LCD_EN\r
-.set SCSI_Out__REQ__MASK, 0x02\r
-.set SCSI_Out__REQ__PC, CYREG_PRT0_PC1\r
-.set SCSI_Out__REQ__PORT, 0\r
-.set SCSI_Out__REQ__PRT, CYREG_PRT0_PRT\r
-.set SCSI_Out__REQ__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL\r
-.set SCSI_Out__REQ__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN\r
-.set SCSI_Out__REQ__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0\r
-.set SCSI_Out__REQ__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1\r
-.set SCSI_Out__REQ__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0\r
-.set SCSI_Out__REQ__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1\r
-.set SCSI_Out__REQ__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT\r
-.set SCSI_Out__REQ__PS, CYREG_PRT0_PS\r
-.set SCSI_Out__REQ__SHIFT, 1\r
-.set SCSI_Out__REQ__SLW, CYREG_PRT0_SLW\r
-.set SCSI_Out__RST__AG, CYREG_PRT0_AG\r
-.set SCSI_Out__RST__AMUX, CYREG_PRT0_AMUX\r
-.set SCSI_Out__RST__BIE, CYREG_PRT0_BIE\r
-.set SCSI_Out__RST__BIT_MASK, CYREG_PRT0_BIT_MASK\r
-.set SCSI_Out__RST__BYP, CYREG_PRT0_BYP\r
-.set SCSI_Out__RST__CTL, CYREG_PRT0_CTL\r
-.set SCSI_Out__RST__DM0, CYREG_PRT0_DM0\r
-.set SCSI_Out__RST__DM1, CYREG_PRT0_DM1\r
-.set SCSI_Out__RST__DM2, CYREG_PRT0_DM2\r
-.set SCSI_Out__RST__DR, CYREG_PRT0_DR\r
-.set SCSI_Out__RST__INP_DIS, CYREG_PRT0_INP_DIS\r
-.set SCSI_Out__RST__INTTYPE, CYREG_PICU0_INTTYPE5\r
-.set SCSI_Out__RST__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG\r
-.set SCSI_Out__RST__LCD_EN, CYREG_PRT0_LCD_EN\r
-.set SCSI_Out__RST__MASK, 0x20\r
-.set SCSI_Out__RST__PC, CYREG_PRT0_PC5\r
-.set SCSI_Out__RST__PORT, 0\r
-.set SCSI_Out__RST__PRT, CYREG_PRT0_PRT\r
-.set SCSI_Out__RST__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL\r
-.set SCSI_Out__RST__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN\r
-.set SCSI_Out__RST__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0\r
-.set SCSI_Out__RST__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1\r
-.set SCSI_Out__RST__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0\r
-.set SCSI_Out__RST__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1\r
-.set SCSI_Out__RST__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT\r
-.set SCSI_Out__RST__PS, CYREG_PRT0_PS\r
-.set SCSI_Out__RST__SHIFT, 5\r
-.set SCSI_Out__RST__SLW, CYREG_PRT0_SLW\r
-.set SCSI_Out__SEL__AG, CYREG_PRT0_AG\r
-.set SCSI_Out__SEL__AMUX, CYREG_PRT0_AMUX\r
-.set SCSI_Out__SEL__BIE, CYREG_PRT0_BIE\r
-.set SCSI_Out__SEL__BIT_MASK, CYREG_PRT0_BIT_MASK\r
-.set SCSI_Out__SEL__BYP, CYREG_PRT0_BYP\r
-.set SCSI_Out__SEL__CTL, CYREG_PRT0_CTL\r
-.set SCSI_Out__SEL__DM0, CYREG_PRT0_DM0\r
-.set SCSI_Out__SEL__DM1, CYREG_PRT0_DM1\r
-.set SCSI_Out__SEL__DM2, CYREG_PRT0_DM2\r
-.set SCSI_Out__SEL__DR, CYREG_PRT0_DR\r
-.set SCSI_Out__SEL__INP_DIS, CYREG_PRT0_INP_DIS\r
-.set SCSI_Out__SEL__INTTYPE, CYREG_PICU0_INTTYPE3\r
-.set SCSI_Out__SEL__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG\r
-.set SCSI_Out__SEL__LCD_EN, CYREG_PRT0_LCD_EN\r
-.set SCSI_Out__SEL__MASK, 0x08\r
-.set SCSI_Out__SEL__PC, CYREG_PRT0_PC3\r
-.set SCSI_Out__SEL__PORT, 0\r
-.set SCSI_Out__SEL__PRT, CYREG_PRT0_PRT\r
-.set SCSI_Out__SEL__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL\r
-.set SCSI_Out__SEL__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN\r
-.set SCSI_Out__SEL__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0\r
-.set SCSI_Out__SEL__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1\r
-.set SCSI_Out__SEL__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0\r
-.set SCSI_Out__SEL__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1\r
-.set SCSI_Out__SEL__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT\r
-.set SCSI_Out__SEL__PS, CYREG_PRT0_PS\r
-.set SCSI_Out__SEL__SHIFT, 3\r
-.set SCSI_Out__SEL__SLW, CYREG_PRT0_SLW\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__0__MASK, 0x01\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__0__POS, 0\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__1__MASK, 0x02\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__1__POS, 1\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB08_09_ACTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB08_09_CTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB08_09_CTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB08_09_CTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB08_09_CTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B1_UDB08_09_MSK\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB08_09_MSK\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB08_09_MSK\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB08_09_MSK\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__2__MASK, 0x04\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__2__POS, 2\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__3__MASK, 0x08\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__3__POS, 3\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__4__MASK, 0x10\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__4__POS, 4\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__5__MASK, 0x20\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__5__POS, 5\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__6__MASK, 0x40\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__6__POS, 6\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__7__MASK, 0x80\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__7__POS, 7\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B1_UDB08_ACTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG, CYREG_B1_UDB08_CTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B1_UDB08_ST_CTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG, CYREG_B1_UDB08_CTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B1_UDB08_ST_CTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__MASK, 0xFF\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB08_MSK_ACTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB08_MSK_ACTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG, CYREG_B1_UDB08_MSK\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK, 0x01\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__0__POS, 0\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB08_09_ACTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB08_09_CTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB08_09_CTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB08_09_CTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB08_09_CTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB08_09_MSK\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB08_09_MSK\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB08_09_MSK\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB08_09_MSK\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB08_ACTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB08_CTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB08_ST_CTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB08_CTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB08_ST_CTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK, 0x01\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB08_MSK_ACTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB08_MSK_ACTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB08_MSK\r
-.set SCSI_Out_DBx__0__AG, CYREG_PRT6_AG\r
-.set SCSI_Out_DBx__0__AMUX, CYREG_PRT6_AMUX\r
-.set SCSI_Out_DBx__0__BIE, CYREG_PRT6_BIE\r
-.set SCSI_Out_DBx__0__BIT_MASK, CYREG_PRT6_BIT_MASK\r
-.set SCSI_Out_DBx__0__BYP, CYREG_PRT6_BYP\r
-.set SCSI_Out_DBx__0__CTL, CYREG_PRT6_CTL\r
-.set SCSI_Out_DBx__0__DM0, CYREG_PRT6_DM0\r
-.set SCSI_Out_DBx__0__DM1, CYREG_PRT6_DM1\r
-.set SCSI_Out_DBx__0__DM2, CYREG_PRT6_DM2\r
-.set SCSI_Out_DBx__0__DR, CYREG_PRT6_DR\r
-.set SCSI_Out_DBx__0__INP_DIS, CYREG_PRT6_INP_DIS\r
-.set SCSI_Out_DBx__0__INTTYPE, CYREG_PICU6_INTTYPE3\r
-.set SCSI_Out_DBx__0__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG\r
-.set SCSI_Out_DBx__0__LCD_EN, CYREG_PRT6_LCD_EN\r
-.set SCSI_Out_DBx__0__MASK, 0x08\r
-.set SCSI_Out_DBx__0__PC, CYREG_PRT6_PC3\r
-.set SCSI_Out_DBx__0__PORT, 6\r
-.set SCSI_Out_DBx__0__PRT, CYREG_PRT6_PRT\r
-.set SCSI_Out_DBx__0__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL\r
-.set SCSI_Out_DBx__0__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN\r
-.set SCSI_Out_DBx__0__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0\r
-.set SCSI_Out_DBx__0__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1\r
-.set SCSI_Out_DBx__0__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0\r
-.set SCSI_Out_DBx__0__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1\r
-.set SCSI_Out_DBx__0__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT\r
-.set SCSI_Out_DBx__0__PS, CYREG_PRT6_PS\r
-.set SCSI_Out_DBx__0__SHIFT, 3\r
-.set SCSI_Out_DBx__0__SLW, CYREG_PRT6_SLW\r
-.set SCSI_Out_DBx__1__AG, CYREG_PRT6_AG\r
-.set SCSI_Out_DBx__1__AMUX, CYREG_PRT6_AMUX\r
-.set SCSI_Out_DBx__1__BIE, CYREG_PRT6_BIE\r
-.set SCSI_Out_DBx__1__BIT_MASK, CYREG_PRT6_BIT_MASK\r
-.set SCSI_Out_DBx__1__BYP, CYREG_PRT6_BYP\r
-.set SCSI_Out_DBx__1__CTL, CYREG_PRT6_CTL\r
-.set SCSI_Out_DBx__1__DM0, CYREG_PRT6_DM0\r
-.set SCSI_Out_DBx__1__DM1, CYREG_PRT6_DM1\r
-.set SCSI_Out_DBx__1__DM2, CYREG_PRT6_DM2\r
-.set SCSI_Out_DBx__1__DR, CYREG_PRT6_DR\r
-.set SCSI_Out_DBx__1__INP_DIS, CYREG_PRT6_INP_DIS\r
-.set SCSI_Out_DBx__1__INTTYPE, CYREG_PICU6_INTTYPE2\r
-.set SCSI_Out_DBx__1__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG\r
-.set SCSI_Out_DBx__1__LCD_EN, CYREG_PRT6_LCD_EN\r
-.set SCSI_Out_DBx__1__MASK, 0x04\r
-.set SCSI_Out_DBx__1__PC, CYREG_PRT6_PC2\r
-.set SCSI_Out_DBx__1__PORT, 6\r
-.set SCSI_Out_DBx__1__PRT, CYREG_PRT6_PRT\r
-.set SCSI_Out_DBx__1__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL\r
-.set SCSI_Out_DBx__1__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN\r
-.set SCSI_Out_DBx__1__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0\r
-.set SCSI_Out_DBx__1__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1\r
-.set SCSI_Out_DBx__1__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0\r
-.set SCSI_Out_DBx__1__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1\r
-.set SCSI_Out_DBx__1__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT\r
-.set SCSI_Out_DBx__1__PS, CYREG_PRT6_PS\r
-.set SCSI_Out_DBx__1__SHIFT, 2\r
-.set SCSI_Out_DBx__1__SLW, CYREG_PRT6_SLW\r
-.set SCSI_Out_DBx__2__AG, CYREG_PRT6_AG\r
-.set SCSI_Out_DBx__2__AMUX, CYREG_PRT6_AMUX\r
-.set SCSI_Out_DBx__2__BIE, CYREG_PRT6_BIE\r
-.set SCSI_Out_DBx__2__BIT_MASK, CYREG_PRT6_BIT_MASK\r
-.set SCSI_Out_DBx__2__BYP, CYREG_PRT6_BYP\r
-.set SCSI_Out_DBx__2__CTL, CYREG_PRT6_CTL\r
-.set SCSI_Out_DBx__2__DM0, CYREG_PRT6_DM0\r
-.set SCSI_Out_DBx__2__DM1, CYREG_PRT6_DM1\r
-.set SCSI_Out_DBx__2__DM2, CYREG_PRT6_DM2\r
-.set SCSI_Out_DBx__2__DR, CYREG_PRT6_DR\r
-.set SCSI_Out_DBx__2__INP_DIS, CYREG_PRT6_INP_DIS\r
-.set SCSI_Out_DBx__2__INTTYPE, CYREG_PICU6_INTTYPE1\r
-.set SCSI_Out_DBx__2__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG\r
-.set SCSI_Out_DBx__2__LCD_EN, CYREG_PRT6_LCD_EN\r
-.set SCSI_Out_DBx__2__MASK, 0x02\r
-.set SCSI_Out_DBx__2__PC, CYREG_PRT6_PC1\r
-.set SCSI_Out_DBx__2__PORT, 6\r
-.set SCSI_Out_DBx__2__PRT, CYREG_PRT6_PRT\r
-.set SCSI_Out_DBx__2__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL\r
-.set SCSI_Out_DBx__2__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN\r
-.set SCSI_Out_DBx__2__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0\r
-.set SCSI_Out_DBx__2__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1\r
-.set SCSI_Out_DBx__2__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0\r
-.set SCSI_Out_DBx__2__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1\r
-.set SCSI_Out_DBx__2__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT\r
-.set SCSI_Out_DBx__2__PS, CYREG_PRT6_PS\r
-.set SCSI_Out_DBx__2__SHIFT, 1\r
-.set SCSI_Out_DBx__2__SLW, CYREG_PRT6_SLW\r
-.set SCSI_Out_DBx__3__AG, CYREG_PRT6_AG\r
-.set SCSI_Out_DBx__3__AMUX, CYREG_PRT6_AMUX\r
-.set SCSI_Out_DBx__3__BIE, CYREG_PRT6_BIE\r
-.set SCSI_Out_DBx__3__BIT_MASK, CYREG_PRT6_BIT_MASK\r
-.set SCSI_Out_DBx__3__BYP, CYREG_PRT6_BYP\r
-.set SCSI_Out_DBx__3__CTL, CYREG_PRT6_CTL\r
-.set SCSI_Out_DBx__3__DM0, CYREG_PRT6_DM0\r
-.set SCSI_Out_DBx__3__DM1, CYREG_PRT6_DM1\r
-.set SCSI_Out_DBx__3__DM2, CYREG_PRT6_DM2\r
-.set SCSI_Out_DBx__3__DR, CYREG_PRT6_DR\r
-.set SCSI_Out_DBx__3__INP_DIS, CYREG_PRT6_INP_DIS\r
-.set SCSI_Out_DBx__3__INTTYPE, CYREG_PICU6_INTTYPE0\r
-.set SCSI_Out_DBx__3__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG\r
-.set SCSI_Out_DBx__3__LCD_EN, CYREG_PRT6_LCD_EN\r
-.set SCSI_Out_DBx__3__MASK, 0x01\r
-.set SCSI_Out_DBx__3__PC, CYREG_PRT6_PC0\r
-.set SCSI_Out_DBx__3__PORT, 6\r
-.set SCSI_Out_DBx__3__PRT, CYREG_PRT6_PRT\r
-.set SCSI_Out_DBx__3__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL\r
-.set SCSI_Out_DBx__3__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN\r
-.set SCSI_Out_DBx__3__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0\r
-.set SCSI_Out_DBx__3__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1\r
-.set SCSI_Out_DBx__3__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0\r
-.set SCSI_Out_DBx__3__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1\r
-.set SCSI_Out_DBx__3__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT\r
-.set SCSI_Out_DBx__3__PS, CYREG_PRT6_PS\r
-.set SCSI_Out_DBx__3__SHIFT, 0\r
-.set SCSI_Out_DBx__3__SLW, CYREG_PRT6_SLW\r
-.set SCSI_Out_DBx__4__AG, CYREG_PRT4_AG\r
-.set SCSI_Out_DBx__4__AMUX, CYREG_PRT4_AMUX\r
-.set SCSI_Out_DBx__4__BIE, CYREG_PRT4_BIE\r
-.set SCSI_Out_DBx__4__BIT_MASK, CYREG_PRT4_BIT_MASK\r
-.set SCSI_Out_DBx__4__BYP, CYREG_PRT4_BYP\r
-.set SCSI_Out_DBx__4__CTL, CYREG_PRT4_CTL\r
-.set SCSI_Out_DBx__4__DM0, CYREG_PRT4_DM0\r
-.set SCSI_Out_DBx__4__DM1, CYREG_PRT4_DM1\r
-.set SCSI_Out_DBx__4__DM2, CYREG_PRT4_DM2\r
-.set SCSI_Out_DBx__4__DR, CYREG_PRT4_DR\r
-.set SCSI_Out_DBx__4__INP_DIS, CYREG_PRT4_INP_DIS\r
-.set SCSI_Out_DBx__4__INTTYPE, CYREG_PICU4_INTTYPE7\r
-.set SCSI_Out_DBx__4__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG\r
-.set SCSI_Out_DBx__4__LCD_EN, CYREG_PRT4_LCD_EN\r
-.set SCSI_Out_DBx__4__MASK, 0x80\r
-.set SCSI_Out_DBx__4__PC, CYREG_PRT4_PC7\r
-.set SCSI_Out_DBx__4__PORT, 4\r
-.set SCSI_Out_DBx__4__PRT, CYREG_PRT4_PRT\r
-.set SCSI_Out_DBx__4__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL\r
-.set SCSI_Out_DBx__4__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN\r
-.set SCSI_Out_DBx__4__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0\r
-.set SCSI_Out_DBx__4__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1\r
-.set SCSI_Out_DBx__4__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0\r
-.set SCSI_Out_DBx__4__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1\r
-.set SCSI_Out_DBx__4__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT\r
-.set SCSI_Out_DBx__4__PS, CYREG_PRT4_PS\r
-.set SCSI_Out_DBx__4__SHIFT, 7\r
-.set SCSI_Out_DBx__4__SLW, CYREG_PRT4_SLW\r
-.set SCSI_Out_DBx__5__AG, CYREG_PRT4_AG\r
-.set SCSI_Out_DBx__5__AMUX, CYREG_PRT4_AMUX\r
-.set SCSI_Out_DBx__5__BIE, CYREG_PRT4_BIE\r
-.set SCSI_Out_DBx__5__BIT_MASK, CYREG_PRT4_BIT_MASK\r
-.set SCSI_Out_DBx__5__BYP, CYREG_PRT4_BYP\r
-.set SCSI_Out_DBx__5__CTL, CYREG_PRT4_CTL\r
-.set SCSI_Out_DBx__5__DM0, CYREG_PRT4_DM0\r
-.set SCSI_Out_DBx__5__DM1, CYREG_PRT4_DM1\r
-.set SCSI_Out_DBx__5__DM2, CYREG_PRT4_DM2\r
-.set SCSI_Out_DBx__5__DR, CYREG_PRT4_DR\r
-.set SCSI_Out_DBx__5__INP_DIS, CYREG_PRT4_INP_DIS\r
-.set SCSI_Out_DBx__5__INTTYPE, CYREG_PICU4_INTTYPE6\r
-.set SCSI_Out_DBx__5__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG\r
-.set SCSI_Out_DBx__5__LCD_EN, CYREG_PRT4_LCD_EN\r
-.set SCSI_Out_DBx__5__MASK, 0x40\r
-.set SCSI_Out_DBx__5__PC, CYREG_PRT4_PC6\r
-.set SCSI_Out_DBx__5__PORT, 4\r
-.set SCSI_Out_DBx__5__PRT, CYREG_PRT4_PRT\r
-.set SCSI_Out_DBx__5__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL\r
-.set SCSI_Out_DBx__5__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN\r
-.set SCSI_Out_DBx__5__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0\r
-.set SCSI_Out_DBx__5__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1\r
-.set SCSI_Out_DBx__5__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0\r
-.set SCSI_Out_DBx__5__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1\r
-.set SCSI_Out_DBx__5__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT\r
-.set SCSI_Out_DBx__5__PS, CYREG_PRT4_PS\r
-.set SCSI_Out_DBx__5__SHIFT, 6\r
-.set SCSI_Out_DBx__5__SLW, CYREG_PRT4_SLW\r
-.set SCSI_Out_DBx__6__AG, CYREG_PRT4_AG\r
-.set SCSI_Out_DBx__6__AMUX, CYREG_PRT4_AMUX\r
-.set SCSI_Out_DBx__6__BIE, CYREG_PRT4_BIE\r
-.set SCSI_Out_DBx__6__BIT_MASK, CYREG_PRT4_BIT_MASK\r
-.set SCSI_Out_DBx__6__BYP, CYREG_PRT4_BYP\r
-.set SCSI_Out_DBx__6__CTL, CYREG_PRT4_CTL\r
-.set SCSI_Out_DBx__6__DM0, CYREG_PRT4_DM0\r
-.set SCSI_Out_DBx__6__DM1, CYREG_PRT4_DM1\r
-.set SCSI_Out_DBx__6__DM2, CYREG_PRT4_DM2\r
-.set SCSI_Out_DBx__6__DR, CYREG_PRT4_DR\r
-.set SCSI_Out_DBx__6__INP_DIS, CYREG_PRT4_INP_DIS\r
-.set SCSI_Out_DBx__6__INTTYPE, CYREG_PICU4_INTTYPE5\r
-.set SCSI_Out_DBx__6__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG\r
-.set SCSI_Out_DBx__6__LCD_EN, CYREG_PRT4_LCD_EN\r
-.set SCSI_Out_DBx__6__MASK, 0x20\r
-.set SCSI_Out_DBx__6__PC, CYREG_PRT4_PC5\r
-.set SCSI_Out_DBx__6__PORT, 4\r
-.set SCSI_Out_DBx__6__PRT, CYREG_PRT4_PRT\r
-.set SCSI_Out_DBx__6__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL\r
-.set SCSI_Out_DBx__6__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN\r
-.set SCSI_Out_DBx__6__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0\r
-.set SCSI_Out_DBx__6__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1\r
-.set SCSI_Out_DBx__6__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0\r
-.set SCSI_Out_DBx__6__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1\r
-.set SCSI_Out_DBx__6__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT\r
-.set SCSI_Out_DBx__6__PS, CYREG_PRT4_PS\r
-.set SCSI_Out_DBx__6__SHIFT, 5\r
-.set SCSI_Out_DBx__6__SLW, CYREG_PRT4_SLW\r
-.set SCSI_Out_DBx__7__AG, CYREG_PRT4_AG\r
-.set SCSI_Out_DBx__7__AMUX, CYREG_PRT4_AMUX\r
-.set SCSI_Out_DBx__7__BIE, CYREG_PRT4_BIE\r
-.set SCSI_Out_DBx__7__BIT_MASK, CYREG_PRT4_BIT_MASK\r
-.set SCSI_Out_DBx__7__BYP, CYREG_PRT4_BYP\r
-.set SCSI_Out_DBx__7__CTL, CYREG_PRT4_CTL\r
-.set SCSI_Out_DBx__7__DM0, CYREG_PRT4_DM0\r
-.set SCSI_Out_DBx__7__DM1, CYREG_PRT4_DM1\r
-.set SCSI_Out_DBx__7__DM2, CYREG_PRT4_DM2\r
-.set SCSI_Out_DBx__7__DR, CYREG_PRT4_DR\r
-.set SCSI_Out_DBx__7__INP_DIS, CYREG_PRT4_INP_DIS\r
-.set SCSI_Out_DBx__7__INTTYPE, CYREG_PICU4_INTTYPE4\r
-.set SCSI_Out_DBx__7__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG\r
-.set SCSI_Out_DBx__7__LCD_EN, CYREG_PRT4_LCD_EN\r
-.set SCSI_Out_DBx__7__MASK, 0x10\r
-.set SCSI_Out_DBx__7__PC, CYREG_PRT4_PC4\r
-.set SCSI_Out_DBx__7__PORT, 4\r
-.set SCSI_Out_DBx__7__PRT, CYREG_PRT4_PRT\r
-.set SCSI_Out_DBx__7__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL\r
-.set SCSI_Out_DBx__7__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN\r
-.set SCSI_Out_DBx__7__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0\r
-.set SCSI_Out_DBx__7__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1\r
-.set SCSI_Out_DBx__7__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0\r
-.set SCSI_Out_DBx__7__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1\r
-.set SCSI_Out_DBx__7__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT\r
-.set SCSI_Out_DBx__7__PS, CYREG_PRT4_PS\r
-.set SCSI_Out_DBx__7__SHIFT, 4\r
-.set SCSI_Out_DBx__7__SLW, CYREG_PRT4_SLW\r
-.set SCSI_Out_DBx__DB0__AG, CYREG_PRT6_AG\r
-.set SCSI_Out_DBx__DB0__AMUX, CYREG_PRT6_AMUX\r
-.set SCSI_Out_DBx__DB0__BIE, CYREG_PRT6_BIE\r
-.set SCSI_Out_DBx__DB0__BIT_MASK, CYREG_PRT6_BIT_MASK\r
-.set SCSI_Out_DBx__DB0__BYP, CYREG_PRT6_BYP\r
-.set SCSI_Out_DBx__DB0__CTL, CYREG_PRT6_CTL\r
-.set SCSI_Out_DBx__DB0__DM0, CYREG_PRT6_DM0\r
-.set SCSI_Out_DBx__DB0__DM1, CYREG_PRT6_DM1\r
-.set SCSI_Out_DBx__DB0__DM2, CYREG_PRT6_DM2\r
-.set SCSI_Out_DBx__DB0__DR, CYREG_PRT6_DR\r
-.set SCSI_Out_DBx__DB0__INP_DIS, CYREG_PRT6_INP_DIS\r
-.set SCSI_Out_DBx__DB0__INTTYPE, CYREG_PICU6_INTTYPE3\r
-.set SCSI_Out_DBx__DB0__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG\r
-.set SCSI_Out_DBx__DB0__LCD_EN, CYREG_PRT6_LCD_EN\r
-.set SCSI_Out_DBx__DB0__MASK, 0x08\r
-.set SCSI_Out_DBx__DB0__PC, CYREG_PRT6_PC3\r
-.set SCSI_Out_DBx__DB0__PORT, 6\r
-.set SCSI_Out_DBx__DB0__PRT, CYREG_PRT6_PRT\r
-.set SCSI_Out_DBx__DB0__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL\r
-.set SCSI_Out_DBx__DB0__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN\r
-.set SCSI_Out_DBx__DB0__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0\r
-.set SCSI_Out_DBx__DB0__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1\r
-.set SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0\r
-.set SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1\r
-.set SCSI_Out_DBx__DB0__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT\r
-.set SCSI_Out_DBx__DB0__PS, CYREG_PRT6_PS\r
-.set SCSI_Out_DBx__DB0__SHIFT, 3\r
-.set SCSI_Out_DBx__DB0__SLW, CYREG_PRT6_SLW\r
-.set SCSI_Out_DBx__DB1__AG, CYREG_PRT6_AG\r
-.set SCSI_Out_DBx__DB1__AMUX, CYREG_PRT6_AMUX\r
-.set SCSI_Out_DBx__DB1__BIE, CYREG_PRT6_BIE\r
-.set SCSI_Out_DBx__DB1__BIT_MASK, CYREG_PRT6_BIT_MASK\r
-.set SCSI_Out_DBx__DB1__BYP, CYREG_PRT6_BYP\r
-.set SCSI_Out_DBx__DB1__CTL, CYREG_PRT6_CTL\r
-.set SCSI_Out_DBx__DB1__DM0, CYREG_PRT6_DM0\r
-.set SCSI_Out_DBx__DB1__DM1, CYREG_PRT6_DM1\r
-.set SCSI_Out_DBx__DB1__DM2, CYREG_PRT6_DM2\r
-.set SCSI_Out_DBx__DB1__DR, CYREG_PRT6_DR\r
-.set SCSI_Out_DBx__DB1__INP_DIS, CYREG_PRT6_INP_DIS\r
-.set SCSI_Out_DBx__DB1__INTTYPE, CYREG_PICU6_INTTYPE2\r
-.set SCSI_Out_DBx__DB1__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG\r
-.set SCSI_Out_DBx__DB1__LCD_EN, CYREG_PRT6_LCD_EN\r
-.set SCSI_Out_DBx__DB1__MASK, 0x04\r
-.set SCSI_Out_DBx__DB1__PC, CYREG_PRT6_PC2\r
-.set SCSI_Out_DBx__DB1__PORT, 6\r
-.set SCSI_Out_DBx__DB1__PRT, CYREG_PRT6_PRT\r
-.set SCSI_Out_DBx__DB1__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL\r
-.set SCSI_Out_DBx__DB1__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN\r
-.set SCSI_Out_DBx__DB1__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0\r
-.set SCSI_Out_DBx__DB1__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1\r
-.set SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0\r
-.set SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1\r
-.set SCSI_Out_DBx__DB1__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT\r
-.set SCSI_Out_DBx__DB1__PS, CYREG_PRT6_PS\r
-.set SCSI_Out_DBx__DB1__SHIFT, 2\r
-.set SCSI_Out_DBx__DB1__SLW, CYREG_PRT6_SLW\r
-.set SCSI_Out_DBx__DB2__AG, CYREG_PRT6_AG\r
-.set SCSI_Out_DBx__DB2__AMUX, CYREG_PRT6_AMUX\r
-.set SCSI_Out_DBx__DB2__BIE, CYREG_PRT6_BIE\r
-.set SCSI_Out_DBx__DB2__BIT_MASK, CYREG_PRT6_BIT_MASK\r
-.set SCSI_Out_DBx__DB2__BYP, CYREG_PRT6_BYP\r
-.set SCSI_Out_DBx__DB2__CTL, CYREG_PRT6_CTL\r
-.set SCSI_Out_DBx__DB2__DM0, CYREG_PRT6_DM0\r
-.set SCSI_Out_DBx__DB2__DM1, CYREG_PRT6_DM1\r
-.set SCSI_Out_DBx__DB2__DM2, CYREG_PRT6_DM2\r
-.set SCSI_Out_DBx__DB2__DR, CYREG_PRT6_DR\r
-.set SCSI_Out_DBx__DB2__INP_DIS, CYREG_PRT6_INP_DIS\r
-.set SCSI_Out_DBx__DB2__INTTYPE, CYREG_PICU6_INTTYPE1\r
-.set SCSI_Out_DBx__DB2__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG\r
-.set SCSI_Out_DBx__DB2__LCD_EN, CYREG_PRT6_LCD_EN\r
-.set SCSI_Out_DBx__DB2__MASK, 0x02\r
-.set SCSI_Out_DBx__DB2__PC, CYREG_PRT6_PC1\r
-.set SCSI_Out_DBx__DB2__PORT, 6\r
-.set SCSI_Out_DBx__DB2__PRT, CYREG_PRT6_PRT\r
-.set SCSI_Out_DBx__DB2__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL\r
-.set SCSI_Out_DBx__DB2__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN\r
-.set SCSI_Out_DBx__DB2__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0\r
-.set SCSI_Out_DBx__DB2__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1\r
-.set SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0\r
-.set SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1\r
-.set SCSI_Out_DBx__DB2__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT\r
-.set SCSI_Out_DBx__DB2__PS, CYREG_PRT6_PS\r
-.set SCSI_Out_DBx__DB2__SHIFT, 1\r
-.set SCSI_Out_DBx__DB2__SLW, CYREG_PRT6_SLW\r
-.set SCSI_Out_DBx__DB3__AG, CYREG_PRT6_AG\r
-.set SCSI_Out_DBx__DB3__AMUX, CYREG_PRT6_AMUX\r
-.set SCSI_Out_DBx__DB3__BIE, CYREG_PRT6_BIE\r
-.set SCSI_Out_DBx__DB3__BIT_MASK, CYREG_PRT6_BIT_MASK\r
-.set SCSI_Out_DBx__DB3__BYP, CYREG_PRT6_BYP\r
-.set SCSI_Out_DBx__DB3__CTL, CYREG_PRT6_CTL\r
-.set SCSI_Out_DBx__DB3__DM0, CYREG_PRT6_DM0\r
-.set SCSI_Out_DBx__DB3__DM1, CYREG_PRT6_DM1\r
-.set SCSI_Out_DBx__DB3__DM2, CYREG_PRT6_DM2\r
-.set SCSI_Out_DBx__DB3__DR, CYREG_PRT6_DR\r
-.set SCSI_Out_DBx__DB3__INP_DIS, CYREG_PRT6_INP_DIS\r
-.set SCSI_Out_DBx__DB3__INTTYPE, CYREG_PICU6_INTTYPE0\r
-.set SCSI_Out_DBx__DB3__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG\r
-.set SCSI_Out_DBx__DB3__LCD_EN, CYREG_PRT6_LCD_EN\r
-.set SCSI_Out_DBx__DB3__MASK, 0x01\r
-.set SCSI_Out_DBx__DB3__PC, CYREG_PRT6_PC0\r
-.set SCSI_Out_DBx__DB3__PORT, 6\r
-.set SCSI_Out_DBx__DB3__PRT, CYREG_PRT6_PRT\r
-.set SCSI_Out_DBx__DB3__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL\r
-.set SCSI_Out_DBx__DB3__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN\r
-.set SCSI_Out_DBx__DB3__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0\r
-.set SCSI_Out_DBx__DB3__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1\r
-.set SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0\r
-.set SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1\r
-.set SCSI_Out_DBx__DB3__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT\r
-.set SCSI_Out_DBx__DB3__PS, CYREG_PRT6_PS\r
-.set SCSI_Out_DBx__DB3__SHIFT, 0\r
-.set SCSI_Out_DBx__DB3__SLW, CYREG_PRT6_SLW\r
-.set SCSI_Out_DBx__DB4__AG, CYREG_PRT4_AG\r
-.set SCSI_Out_DBx__DB4__AMUX, CYREG_PRT4_AMUX\r
-.set SCSI_Out_DBx__DB4__BIE, CYREG_PRT4_BIE\r
-.set SCSI_Out_DBx__DB4__BIT_MASK, CYREG_PRT4_BIT_MASK\r
-.set SCSI_Out_DBx__DB4__BYP, CYREG_PRT4_BYP\r
-.set SCSI_Out_DBx__DB4__CTL, CYREG_PRT4_CTL\r
-.set SCSI_Out_DBx__DB4__DM0, CYREG_PRT4_DM0\r
-.set SCSI_Out_DBx__DB4__DM1, CYREG_PRT4_DM1\r
-.set SCSI_Out_DBx__DB4__DM2, CYREG_PRT4_DM2\r
-.set SCSI_Out_DBx__DB4__DR, CYREG_PRT4_DR\r
-.set SCSI_Out_DBx__DB4__INP_DIS, CYREG_PRT4_INP_DIS\r
-.set SCSI_Out_DBx__DB4__INTTYPE, CYREG_PICU4_INTTYPE7\r
-.set SCSI_Out_DBx__DB4__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG\r
-.set SCSI_Out_DBx__DB4__LCD_EN, CYREG_PRT4_LCD_EN\r
-.set SCSI_Out_DBx__DB4__MASK, 0x80\r
-.set SCSI_Out_DBx__DB4__PC, CYREG_PRT4_PC7\r
-.set SCSI_Out_DBx__DB4__PORT, 4\r
-.set SCSI_Out_DBx__DB4__PRT, CYREG_PRT4_PRT\r
-.set SCSI_Out_DBx__DB4__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL\r
-.set SCSI_Out_DBx__DB4__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN\r
-.set SCSI_Out_DBx__DB4__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0\r
-.set SCSI_Out_DBx__DB4__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1\r
-.set SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0\r
-.set SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1\r
-.set SCSI_Out_DBx__DB4__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT\r
-.set SCSI_Out_DBx__DB4__PS, CYREG_PRT4_PS\r
-.set SCSI_Out_DBx__DB4__SHIFT, 7\r
-.set SCSI_Out_DBx__DB4__SLW, CYREG_PRT4_SLW\r
-.set SCSI_Out_DBx__DB5__AG, CYREG_PRT4_AG\r
-.set SCSI_Out_DBx__DB5__AMUX, CYREG_PRT4_AMUX\r
-.set SCSI_Out_DBx__DB5__BIE, CYREG_PRT4_BIE\r
-.set SCSI_Out_DBx__DB5__BIT_MASK, CYREG_PRT4_BIT_MASK\r
-.set SCSI_Out_DBx__DB5__BYP, CYREG_PRT4_BYP\r
-.set SCSI_Out_DBx__DB5__CTL, CYREG_PRT4_CTL\r
-.set SCSI_Out_DBx__DB5__DM0, CYREG_PRT4_DM0\r
-.set SCSI_Out_DBx__DB5__DM1, CYREG_PRT4_DM1\r
-.set SCSI_Out_DBx__DB5__DM2, CYREG_PRT4_DM2\r
-.set SCSI_Out_DBx__DB5__DR, CYREG_PRT4_DR\r
-.set SCSI_Out_DBx__DB5__INP_DIS, CYREG_PRT4_INP_DIS\r
-.set SCSI_Out_DBx__DB5__INTTYPE, CYREG_PICU4_INTTYPE6\r
-.set SCSI_Out_DBx__DB5__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG\r
-.set SCSI_Out_DBx__DB5__LCD_EN, CYREG_PRT4_LCD_EN\r
-.set SCSI_Out_DBx__DB5__MASK, 0x40\r
-.set SCSI_Out_DBx__DB5__PC, CYREG_PRT4_PC6\r
-.set SCSI_Out_DBx__DB5__PORT, 4\r
-.set SCSI_Out_DBx__DB5__PRT, CYREG_PRT4_PRT\r
-.set SCSI_Out_DBx__DB5__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL\r
-.set SCSI_Out_DBx__DB5__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN\r
-.set SCSI_Out_DBx__DB5__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0\r
-.set SCSI_Out_DBx__DB5__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1\r
-.set SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0\r
-.set SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1\r
-.set SCSI_Out_DBx__DB5__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT\r
-.set SCSI_Out_DBx__DB5__PS, CYREG_PRT4_PS\r
-.set SCSI_Out_DBx__DB5__SHIFT, 6\r
-.set SCSI_Out_DBx__DB5__SLW, CYREG_PRT4_SLW\r
-.set SCSI_Out_DBx__DB6__AG, CYREG_PRT4_AG\r
-.set SCSI_Out_DBx__DB6__AMUX, CYREG_PRT4_AMUX\r
-.set SCSI_Out_DBx__DB6__BIE, CYREG_PRT4_BIE\r
-.set SCSI_Out_DBx__DB6__BIT_MASK, CYREG_PRT4_BIT_MASK\r
-.set SCSI_Out_DBx__DB6__BYP, CYREG_PRT4_BYP\r
-.set SCSI_Out_DBx__DB6__CTL, CYREG_PRT4_CTL\r
-.set SCSI_Out_DBx__DB6__DM0, CYREG_PRT4_DM0\r
-.set SCSI_Out_DBx__DB6__DM1, CYREG_PRT4_DM1\r
-.set SCSI_Out_DBx__DB6__DM2, CYREG_PRT4_DM2\r
-.set SCSI_Out_DBx__DB6__DR, CYREG_PRT4_DR\r
-.set SCSI_Out_DBx__DB6__INP_DIS, CYREG_PRT4_INP_DIS\r
-.set SCSI_Out_DBx__DB6__INTTYPE, CYREG_PICU4_INTTYPE5\r
-.set SCSI_Out_DBx__DB6__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG\r
-.set SCSI_Out_DBx__DB6__LCD_EN, CYREG_PRT4_LCD_EN\r
-.set SCSI_Out_DBx__DB6__MASK, 0x20\r
-.set SCSI_Out_DBx__DB6__PC, CYREG_PRT4_PC5\r
-.set SCSI_Out_DBx__DB6__PORT, 4\r
-.set SCSI_Out_DBx__DB6__PRT, CYREG_PRT4_PRT\r
-.set SCSI_Out_DBx__DB6__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL\r
-.set SCSI_Out_DBx__DB6__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN\r
-.set SCSI_Out_DBx__DB6__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0\r
-.set SCSI_Out_DBx__DB6__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1\r
-.set SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0\r
-.set SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1\r
-.set SCSI_Out_DBx__DB6__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT\r
-.set SCSI_Out_DBx__DB6__PS, CYREG_PRT4_PS\r
-.set SCSI_Out_DBx__DB6__SHIFT, 5\r
-.set SCSI_Out_DBx__DB6__SLW, CYREG_PRT4_SLW\r
-.set SCSI_Out_DBx__DB7__AG, CYREG_PRT4_AG\r
-.set SCSI_Out_DBx__DB7__AMUX, CYREG_PRT4_AMUX\r
-.set SCSI_Out_DBx__DB7__BIE, CYREG_PRT4_BIE\r
-.set SCSI_Out_DBx__DB7__BIT_MASK, CYREG_PRT4_BIT_MASK\r
-.set SCSI_Out_DBx__DB7__BYP, CYREG_PRT4_BYP\r
-.set SCSI_Out_DBx__DB7__CTL, CYREG_PRT4_CTL\r
-.set SCSI_Out_DBx__DB7__DM0, CYREG_PRT4_DM0\r
-.set SCSI_Out_DBx__DB7__DM1, CYREG_PRT4_DM1\r
-.set SCSI_Out_DBx__DB7__DM2, CYREG_PRT4_DM2\r
-.set SCSI_Out_DBx__DB7__DR, CYREG_PRT4_DR\r
-.set SCSI_Out_DBx__DB7__INP_DIS, CYREG_PRT4_INP_DIS\r
-.set SCSI_Out_DBx__DB7__INTTYPE, CYREG_PICU4_INTTYPE4\r
-.set SCSI_Out_DBx__DB7__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG\r
-.set SCSI_Out_DBx__DB7__LCD_EN, CYREG_PRT4_LCD_EN\r
-.set SCSI_Out_DBx__DB7__MASK, 0x10\r
-.set SCSI_Out_DBx__DB7__PC, CYREG_PRT4_PC4\r
-.set SCSI_Out_DBx__DB7__PORT, 4\r
-.set SCSI_Out_DBx__DB7__PRT, CYREG_PRT4_PRT\r
-.set SCSI_Out_DBx__DB7__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL\r
-.set SCSI_Out_DBx__DB7__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN\r
-.set SCSI_Out_DBx__DB7__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0\r
-.set SCSI_Out_DBx__DB7__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1\r
-.set SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0\r
-.set SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1\r
-.set SCSI_Out_DBx__DB7__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT\r
-.set SCSI_Out_DBx__DB7__PS, CYREG_PRT4_PS\r
-.set SCSI_Out_DBx__DB7__SHIFT, 4\r
-.set SCSI_Out_DBx__DB7__SLW, CYREG_PRT4_SLW\r
-\r
-/* SCSI_Parity_Error */\r
-.set SCSI_Parity_Error_sts_sts_reg__0__MASK, 0x01\r
-.set SCSI_Parity_Error_sts_sts_reg__0__POS, 0\r
-.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB01_02_ACTL\r
-.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB01_02_ST\r
-.set SCSI_Parity_Error_sts_sts_reg__MASK, 0x01\r
-.set SCSI_Parity_Error_sts_sts_reg__MASK_REG, CYREG_B0_UDB01_MSK\r
-.set SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB01_ACTL\r
-.set SCSI_Parity_Error_sts_sts_reg__STATUS_REG, CYREG_B0_UDB01_ST\r
-\r
-/* SCSI_RST_ISR */\r
-.set SCSI_RST_ISR__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
-.set SCSI_RST_ISR__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
-.set SCSI_RST_ISR__INTC_MASK, 0x02\r
-.set SCSI_RST_ISR__INTC_NUMBER, 1\r
-.set SCSI_RST_ISR__INTC_PRIOR_NUM, 7\r
-.set SCSI_RST_ISR__INTC_PRIOR_REG, CYREG_NVIC_PRI_1\r
-.set SCSI_RST_ISR__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
-.set SCSI_RST_ISR__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
-\r
-/* SCSI_RX_DMA */\r
-.set SCSI_RX_DMA__DRQ_CTL, CYREG_IDMUX_DRQ_CTL0\r
-.set SCSI_RX_DMA__DRQ_NUMBER, 0\r
-.set SCSI_RX_DMA__NUMBEROF_TDS, 0\r
-.set SCSI_RX_DMA__PRIORITY, 2\r
-.set SCSI_RX_DMA__TERMIN_EN, 0\r
-.set SCSI_RX_DMA__TERMIN_SEL, 0\r
-.set SCSI_RX_DMA__TERMOUT0_EN, 1\r
-.set SCSI_RX_DMA__TERMOUT0_SEL, 0\r
-.set SCSI_RX_DMA__TERMOUT1_EN, 0\r
-.set SCSI_RX_DMA__TERMOUT1_SEL, 0\r
-.set SCSI_RX_DMA_COMPLETE__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
-.set SCSI_RX_DMA_COMPLETE__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
-.set SCSI_RX_DMA_COMPLETE__INTC_MASK, 0x04\r
-.set SCSI_RX_DMA_COMPLETE__INTC_NUMBER, 2\r
-.set SCSI_RX_DMA_COMPLETE__INTC_PRIOR_NUM, 7\r
-.set SCSI_RX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_2\r
-.set SCSI_RX_DMA_COMPLETE__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
-.set SCSI_RX_DMA_COMPLETE__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
-\r
-/* SCSI_SEL_ISR */\r
-.set SCSI_SEL_ISR__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
-.set SCSI_SEL_ISR__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
-.set SCSI_SEL_ISR__INTC_MASK, 0x08\r
-.set SCSI_SEL_ISR__INTC_NUMBER, 3\r
-.set SCSI_SEL_ISR__INTC_PRIOR_NUM, 7\r
-.set SCSI_SEL_ISR__INTC_PRIOR_REG, CYREG_NVIC_PRI_3\r
-.set SCSI_SEL_ISR__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
-.set SCSI_SEL_ISR__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
-\r
-/* SCSI_TX_DMA */\r
-.set SCSI_TX_DMA__DRQ_CTL, CYREG_IDMUX_DRQ_CTL0\r
-.set SCSI_TX_DMA__DRQ_NUMBER, 1\r
-.set SCSI_TX_DMA__NUMBEROF_TDS, 0\r
-.set SCSI_TX_DMA__PRIORITY, 2\r
-.set SCSI_TX_DMA__TERMIN_EN, 0\r
-.set SCSI_TX_DMA__TERMIN_SEL, 0\r
-.set SCSI_TX_DMA__TERMOUT0_EN, 1\r
-.set SCSI_TX_DMA__TERMOUT0_SEL, 1\r
-.set SCSI_TX_DMA__TERMOUT1_EN, 0\r
-.set SCSI_TX_DMA__TERMOUT1_SEL, 0\r
-.set SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
-.set SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
-.set SCSI_TX_DMA_COMPLETE__INTC_MASK, 0x10\r
-.set SCSI_TX_DMA_COMPLETE__INTC_NUMBER, 4\r
-.set SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM, 7\r
-.set SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_4\r
-.set SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
-.set SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
-\r
-/* SDCard_BSPIM */\r
-.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB04_05_ACTL\r
-.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB04_05_CTL\r
-.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB04_05_CTL\r
-.set SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB04_05_CTL\r
-.set SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB04_05_CTL\r
-.set SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B1_UDB04_05_MSK\r
-.set SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB04_05_MSK\r
-.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB04_05_MSK\r
-.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB04_05_MSK\r
-.set SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B1_UDB04_ACTL\r
-.set SDCard_BSPIM_BitCounter__CONTROL_REG, CYREG_B1_UDB04_CTL\r
-.set SDCard_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B1_UDB04_ST_CTL\r
-.set SDCard_BSPIM_BitCounter__COUNT_REG, CYREG_B1_UDB04_CTL\r
-.set SDCard_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B1_UDB04_ST_CTL\r
-.set SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL\r
-.set SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL\r
-.set SDCard_BSPIM_BitCounter__PERIOD_REG, CYREG_B1_UDB04_MSK\r
-.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB04_05_ACTL\r
-.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B1_UDB04_05_ST\r
-.set SDCard_BSPIM_BitCounter_ST__MASK_REG, CYREG_B1_UDB04_MSK\r
-.set SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL\r
-.set SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL\r
-.set SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B1_UDB04_ACTL\r
-.set SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B1_UDB04_ST_CTL\r
-.set SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B1_UDB04_ST_CTL\r
-.set SDCard_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B1_UDB04_ST\r
-.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB08_09_ACTL\r
-.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB08_09_ST\r
-.set SDCard_BSPIM_RxStsReg__4__MASK, 0x10\r
-.set SDCard_BSPIM_RxStsReg__4__POS, 4\r
-.set SDCard_BSPIM_RxStsReg__5__MASK, 0x20\r
-.set SDCard_BSPIM_RxStsReg__5__POS, 5\r
-.set SDCard_BSPIM_RxStsReg__6__MASK, 0x40\r
-.set SDCard_BSPIM_RxStsReg__6__POS, 6\r
-.set SDCard_BSPIM_RxStsReg__MASK, 0x70\r
-.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B1_UDB08_MSK\r
-.set SDCard_BSPIM_RxStsReg__MASK_ST_AUX_CTL_REG, CYREG_B1_UDB08_MSK_ACTL\r
-.set SDCard_BSPIM_RxStsReg__PER_ST_AUX_CTL_REG, CYREG_B1_UDB08_MSK_ACTL\r
-.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB08_ACTL\r
-.set SDCard_BSPIM_RxStsReg__STATUS_CNT_REG, CYREG_B1_UDB08_ST_CTL\r
-.set SDCard_BSPIM_RxStsReg__STATUS_CONTROL_REG, CYREG_B1_UDB08_ST_CTL\r
-.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B1_UDB08_ST\r
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG, CYREG_B1_UDB04_05_A0\r
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG, CYREG_B1_UDB04_05_A1\r
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG, CYREG_B1_UDB04_05_D0\r
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG, CYREG_B1_UDB04_05_D1\r
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG, CYREG_B1_UDB04_05_ACTL\r
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG, CYREG_B1_UDB04_05_F0\r
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG, CYREG_B1_UDB04_05_F1\r
-.set SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG, CYREG_B1_UDB04_A0_A1\r
-.set SDCard_BSPIM_sR8_Dp_u0__A0_REG, CYREG_B1_UDB04_A0\r
-.set SDCard_BSPIM_sR8_Dp_u0__A1_REG, CYREG_B1_UDB04_A1\r
-.set SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG, CYREG_B1_UDB04_D0_D1\r
-.set SDCard_BSPIM_sR8_Dp_u0__D0_REG, CYREG_B1_UDB04_D0\r
-.set SDCard_BSPIM_sR8_Dp_u0__D1_REG, CYREG_B1_UDB04_D1\r
-.set SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG, CYREG_B1_UDB04_ACTL\r
-.set SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG, CYREG_B1_UDB04_F0_F1\r
-.set SDCard_BSPIM_sR8_Dp_u0__F0_REG, CYREG_B1_UDB04_F0\r
-.set SDCard_BSPIM_sR8_Dp_u0__F1_REG, CYREG_B1_UDB04_F1\r
-.set SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL\r
-.set SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL\r
-.set SDCard_BSPIM_TxStsReg__0__MASK, 0x01\r
-.set SDCard_BSPIM_TxStsReg__0__POS, 0\r
-.set SDCard_BSPIM_TxStsReg__1__MASK, 0x02\r
-.set SDCard_BSPIM_TxStsReg__1__POS, 1\r
-.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB07_08_ACTL\r
-.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB07_08_ST\r
-.set SDCard_BSPIM_TxStsReg__2__MASK, 0x04\r
-.set SDCard_BSPIM_TxStsReg__2__POS, 2\r
-.set SDCard_BSPIM_TxStsReg__3__MASK, 0x08\r
-.set SDCard_BSPIM_TxStsReg__3__POS, 3\r
-.set SDCard_BSPIM_TxStsReg__4__MASK, 0x10\r
-.set SDCard_BSPIM_TxStsReg__4__POS, 4\r
-.set SDCard_BSPIM_TxStsReg__MASK, 0x1F\r
-.set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B1_UDB07_MSK\r
-.set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB07_ACTL\r
-.set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B1_UDB07_ST\r
-\r
-/* SD_CD */\r
-.set SD_CD__0__INTTYPE, CYREG_PICU3_INTTYPE6\r
-.set SD_CD__0__MASK, 0x40\r
-.set SD_CD__0__PC, CYREG_PRT3_PC6\r
-.set SD_CD__0__PORT, 3\r
-.set SD_CD__0__SHIFT, 6\r
-.set SD_CD__AG, CYREG_PRT3_AG\r
-.set SD_CD__AMUX, CYREG_PRT3_AMUX\r
-.set SD_CD__BIE, CYREG_PRT3_BIE\r
-.set SD_CD__BIT_MASK, CYREG_PRT3_BIT_MASK\r
-.set SD_CD__BYP, CYREG_PRT3_BYP\r
-.set SD_CD__CTL, CYREG_PRT3_CTL\r
-.set SD_CD__DM0, CYREG_PRT3_DM0\r
-.set SD_CD__DM1, CYREG_PRT3_DM1\r
-.set SD_CD__DM2, CYREG_PRT3_DM2\r
-.set SD_CD__DR, CYREG_PRT3_DR\r
-.set SD_CD__INP_DIS, CYREG_PRT3_INP_DIS\r
-.set SD_CD__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU3_BASE\r
-.set SD_CD__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG\r
-.set SD_CD__LCD_EN, CYREG_PRT3_LCD_EN\r
-.set SD_CD__MASK, 0x40\r
-.set SD_CD__PORT, 3\r
-.set SD_CD__PRT, CYREG_PRT3_PRT\r
-.set SD_CD__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL\r
-.set SD_CD__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN\r
-.set SD_CD__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0\r
-.set SD_CD__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1\r
-.set SD_CD__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0\r
-.set SD_CD__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1\r
-.set SD_CD__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT\r
-.set SD_CD__PS, CYREG_PRT3_PS\r
-.set SD_CD__SHIFT, 6\r
-.set SD_CD__SLW, CYREG_PRT3_SLW\r
-\r
-/* SD_CS */\r
-.set SD_CS__0__INTTYPE, CYREG_PICU3_INTTYPE4\r
-.set SD_CS__0__MASK, 0x10\r
-.set SD_CS__0__PC, CYREG_PRT3_PC4\r
-.set SD_CS__0__PORT, 3\r
-.set SD_CS__0__SHIFT, 4\r
-.set SD_CS__AG, CYREG_PRT3_AG\r
-.set SD_CS__AMUX, CYREG_PRT3_AMUX\r
-.set SD_CS__BIE, CYREG_PRT3_BIE\r
-.set SD_CS__BIT_MASK, CYREG_PRT3_BIT_MASK\r
-.set SD_CS__BYP, CYREG_PRT3_BYP\r
-.set SD_CS__CTL, CYREG_PRT3_CTL\r
-.set SD_CS__DM0, CYREG_PRT3_DM0\r
-.set SD_CS__DM1, CYREG_PRT3_DM1\r
-.set SD_CS__DM2, CYREG_PRT3_DM2\r
-.set SD_CS__DR, CYREG_PRT3_DR\r
-.set SD_CS__INP_DIS, CYREG_PRT3_INP_DIS\r
-.set SD_CS__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU3_BASE\r
-.set SD_CS__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG\r
-.set SD_CS__LCD_EN, CYREG_PRT3_LCD_EN\r
-.set SD_CS__MASK, 0x10\r
-.set SD_CS__PORT, 3\r
-.set SD_CS__PRT, CYREG_PRT3_PRT\r
-.set SD_CS__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL\r
-.set SD_CS__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN\r
-.set SD_CS__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0\r
-.set SD_CS__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1\r
-.set SD_CS__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0\r
-.set SD_CS__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1\r
-.set SD_CS__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT\r
-.set SD_CS__PS, CYREG_PRT3_PS\r
-.set SD_CS__SHIFT, 4\r
-.set SD_CS__SLW, CYREG_PRT3_SLW\r
-\r
-/* SD_DAT1 */\r
-.set SD_DAT1__0__INTTYPE, CYREG_PICU3_INTTYPE0\r
-.set SD_DAT1__0__MASK, 0x01\r
-.set SD_DAT1__0__PC, CYREG_PRT3_PC0\r
-.set SD_DAT1__0__PORT, 3\r
-.set SD_DAT1__0__SHIFT, 0\r
-.set SD_DAT1__AG, CYREG_PRT3_AG\r
-.set SD_DAT1__AMUX, CYREG_PRT3_AMUX\r
-.set SD_DAT1__BIE, CYREG_PRT3_BIE\r
-.set SD_DAT1__BIT_MASK, CYREG_PRT3_BIT_MASK\r
-.set SD_DAT1__BYP, CYREG_PRT3_BYP\r
-.set SD_DAT1__CTL, CYREG_PRT3_CTL\r
-.set SD_DAT1__DM0, CYREG_PRT3_DM0\r
-.set SD_DAT1__DM1, CYREG_PRT3_DM1\r
-.set SD_DAT1__DM2, CYREG_PRT3_DM2\r
-.set SD_DAT1__DR, CYREG_PRT3_DR\r
-.set SD_DAT1__INP_DIS, CYREG_PRT3_INP_DIS\r
-.set SD_DAT1__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU3_BASE\r
-.set SD_DAT1__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG\r
-.set SD_DAT1__LCD_EN, CYREG_PRT3_LCD_EN\r
-.set SD_DAT1__MASK, 0x01\r
-.set SD_DAT1__PORT, 3\r
-.set SD_DAT1__PRT, CYREG_PRT3_PRT\r
-.set SD_DAT1__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL\r
-.set SD_DAT1__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN\r
-.set SD_DAT1__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0\r
-.set SD_DAT1__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1\r
-.set SD_DAT1__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0\r
-.set SD_DAT1__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1\r
-.set SD_DAT1__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT\r
-.set SD_DAT1__PS, CYREG_PRT3_PS\r
-.set SD_DAT1__SHIFT, 0\r
-.set SD_DAT1__SLW, CYREG_PRT3_SLW\r
-\r
-/* SD_DAT2 */\r
-.set SD_DAT2__0__INTTYPE, CYREG_PICU3_INTTYPE5\r
-.set SD_DAT2__0__MASK, 0x20\r
-.set SD_DAT2__0__PC, CYREG_PRT3_PC5\r
-.set SD_DAT2__0__PORT, 3\r
-.set SD_DAT2__0__SHIFT, 5\r
-.set SD_DAT2__AG, CYREG_PRT3_AG\r
-.set SD_DAT2__AMUX, CYREG_PRT3_AMUX\r
-.set SD_DAT2__BIE, CYREG_PRT3_BIE\r
-.set SD_DAT2__BIT_MASK, CYREG_PRT3_BIT_MASK\r
-.set SD_DAT2__BYP, CYREG_PRT3_BYP\r
-.set SD_DAT2__CTL, CYREG_PRT3_CTL\r
-.set SD_DAT2__DM0, CYREG_PRT3_DM0\r
-.set SD_DAT2__DM1, CYREG_PRT3_DM1\r
-.set SD_DAT2__DM2, CYREG_PRT3_DM2\r
-.set SD_DAT2__DR, CYREG_PRT3_DR\r
-.set SD_DAT2__INP_DIS, CYREG_PRT3_INP_DIS\r
-.set SD_DAT2__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU3_BASE\r
-.set SD_DAT2__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG\r
-.set SD_DAT2__LCD_EN, CYREG_PRT3_LCD_EN\r
-.set SD_DAT2__MASK, 0x20\r
-.set SD_DAT2__PORT, 3\r
-.set SD_DAT2__PRT, CYREG_PRT3_PRT\r
-.set SD_DAT2__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL\r
-.set SD_DAT2__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN\r
-.set SD_DAT2__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0\r
-.set SD_DAT2__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1\r
-.set SD_DAT2__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0\r
-.set SD_DAT2__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1\r
-.set SD_DAT2__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT\r
-.set SD_DAT2__PS, CYREG_PRT3_PS\r
-.set SD_DAT2__SHIFT, 5\r
-.set SD_DAT2__SLW, CYREG_PRT3_SLW\r
-\r
-/* SD_Data_Clk */\r
-.set SD_Data_Clk__CFG0, CYREG_CLKDIST_DCFG0_CFG0\r
-.set SD_Data_Clk__CFG1, CYREG_CLKDIST_DCFG0_CFG1\r
-.set SD_Data_Clk__CFG2, CYREG_CLKDIST_DCFG0_CFG2\r
-.set SD_Data_Clk__CFG2_SRC_SEL_MASK, 0x07\r
-.set SD_Data_Clk__INDEX, 0x00\r
-.set SD_Data_Clk__PM_ACT_CFG, CYREG_PM_ACT_CFG2\r
-.set SD_Data_Clk__PM_ACT_MSK, 0x01\r
-.set SD_Data_Clk__PM_STBY_CFG, CYREG_PM_STBY_CFG2\r
-.set SD_Data_Clk__PM_STBY_MSK, 0x01\r
-\r
-/* SD_MISO */\r
-.set SD_MISO__0__INTTYPE, CYREG_PICU3_INTTYPE1\r
-.set SD_MISO__0__MASK, 0x02\r
-.set SD_MISO__0__PC, CYREG_PRT3_PC1\r
-.set SD_MISO__0__PORT, 3\r
-.set SD_MISO__0__SHIFT, 1\r
-.set SD_MISO__AG, CYREG_PRT3_AG\r
-.set SD_MISO__AMUX, CYREG_PRT3_AMUX\r
-.set SD_MISO__BIE, CYREG_PRT3_BIE\r
-.set SD_MISO__BIT_MASK, CYREG_PRT3_BIT_MASK\r
-.set SD_MISO__BYP, CYREG_PRT3_BYP\r
-.set SD_MISO__CTL, CYREG_PRT3_CTL\r
-.set SD_MISO__DM0, CYREG_PRT3_DM0\r
-.set SD_MISO__DM1, CYREG_PRT3_DM1\r
-.set SD_MISO__DM2, CYREG_PRT3_DM2\r
-.set SD_MISO__DR, CYREG_PRT3_DR\r
-.set SD_MISO__INP_DIS, CYREG_PRT3_INP_DIS\r
-.set SD_MISO__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU3_BASE\r
-.set SD_MISO__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG\r
-.set SD_MISO__LCD_EN, CYREG_PRT3_LCD_EN\r
-.set SD_MISO__MASK, 0x02\r
-.set SD_MISO__PORT, 3\r
-.set SD_MISO__PRT, CYREG_PRT3_PRT\r
-.set SD_MISO__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL\r
-.set SD_MISO__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN\r
-.set SD_MISO__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0\r
-.set SD_MISO__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1\r
-.set SD_MISO__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0\r
-.set SD_MISO__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1\r
-.set SD_MISO__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT\r
-.set SD_MISO__PS, CYREG_PRT3_PS\r
-.set SD_MISO__SHIFT, 1\r
-.set SD_MISO__SLW, CYREG_PRT3_SLW\r
-\r
-/* SD_MOSI */\r
-.set SD_MOSI__0__INTTYPE, CYREG_PICU3_INTTYPE3\r
-.set SD_MOSI__0__MASK, 0x08\r
-.set SD_MOSI__0__PC, CYREG_PRT3_PC3\r
-.set SD_MOSI__0__PORT, 3\r
-.set SD_MOSI__0__SHIFT, 3\r
-.set SD_MOSI__AG, CYREG_PRT3_AG\r
-.set SD_MOSI__AMUX, CYREG_PRT3_AMUX\r
-.set SD_MOSI__BIE, CYREG_PRT3_BIE\r
-.set SD_MOSI__BIT_MASK, CYREG_PRT3_BIT_MASK\r
-.set SD_MOSI__BYP, CYREG_PRT3_BYP\r
-.set SD_MOSI__CTL, CYREG_PRT3_CTL\r
-.set SD_MOSI__DM0, CYREG_PRT3_DM0\r
-.set SD_MOSI__DM1, CYREG_PRT3_DM1\r
-.set SD_MOSI__DM2, CYREG_PRT3_DM2\r
-.set SD_MOSI__DR, CYREG_PRT3_DR\r
-.set SD_MOSI__INP_DIS, CYREG_PRT3_INP_DIS\r
-.set SD_MOSI__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU3_BASE\r
-.set SD_MOSI__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG\r
-.set SD_MOSI__LCD_EN, CYREG_PRT3_LCD_EN\r
-.set SD_MOSI__MASK, 0x08\r
-.set SD_MOSI__PORT, 3\r
-.set SD_MOSI__PRT, CYREG_PRT3_PRT\r
-.set SD_MOSI__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL\r
-.set SD_MOSI__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN\r
-.set SD_MOSI__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0\r
-.set SD_MOSI__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1\r
-.set SD_MOSI__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0\r
-.set SD_MOSI__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1\r
-.set SD_MOSI__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT\r
-.set SD_MOSI__PS, CYREG_PRT3_PS\r
-.set SD_MOSI__SHIFT, 3\r
-.set SD_MOSI__SLW, CYREG_PRT3_SLW\r
-\r
-/* SD_RX_DMA */\r
-.set SD_RX_DMA__DRQ_CTL, CYREG_IDMUX_DRQ_CTL0\r
-.set SD_RX_DMA__DRQ_NUMBER, 2\r
-.set SD_RX_DMA__NUMBEROF_TDS, 0\r
-.set SD_RX_DMA__PRIORITY, 0\r
-.set SD_RX_DMA__TERMIN_EN, 0\r
-.set SD_RX_DMA__TERMIN_SEL, 0\r
-.set SD_RX_DMA__TERMOUT0_EN, 1\r
-.set SD_RX_DMA__TERMOUT0_SEL, 2\r
-.set SD_RX_DMA__TERMOUT1_EN, 0\r
-.set SD_RX_DMA__TERMOUT1_SEL, 0\r
-.set SD_RX_DMA_COMPLETE__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
-.set SD_RX_DMA_COMPLETE__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
-.set SD_RX_DMA_COMPLETE__INTC_MASK, 0x20\r
-.set SD_RX_DMA_COMPLETE__INTC_NUMBER, 5\r
-.set SD_RX_DMA_COMPLETE__INTC_PRIOR_NUM, 7\r
-.set SD_RX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_5\r
-.set SD_RX_DMA_COMPLETE__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
-.set SD_RX_DMA_COMPLETE__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
-\r
-/* SD_SCK */\r
-.set SD_SCK__0__INTTYPE, CYREG_PICU3_INTTYPE2\r
-.set SD_SCK__0__MASK, 0x04\r
-.set SD_SCK__0__PC, CYREG_PRT3_PC2\r
-.set SD_SCK__0__PORT, 3\r
-.set SD_SCK__0__SHIFT, 2\r
-.set SD_SCK__AG, CYREG_PRT3_AG\r
-.set SD_SCK__AMUX, CYREG_PRT3_AMUX\r
-.set SD_SCK__BIE, CYREG_PRT3_BIE\r
-.set SD_SCK__BIT_MASK, CYREG_PRT3_BIT_MASK\r
-.set SD_SCK__BYP, CYREG_PRT3_BYP\r
-.set SD_SCK__CTL, CYREG_PRT3_CTL\r
-.set SD_SCK__DM0, CYREG_PRT3_DM0\r
-.set SD_SCK__DM1, CYREG_PRT3_DM1\r
-.set SD_SCK__DM2, CYREG_PRT3_DM2\r
-.set SD_SCK__DR, CYREG_PRT3_DR\r
-.set SD_SCK__INP_DIS, CYREG_PRT3_INP_DIS\r
-.set SD_SCK__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU3_BASE\r
-.set SD_SCK__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG\r
-.set SD_SCK__LCD_EN, CYREG_PRT3_LCD_EN\r
-.set SD_SCK__MASK, 0x04\r
-.set SD_SCK__PORT, 3\r
-.set SD_SCK__PRT, CYREG_PRT3_PRT\r
-.set SD_SCK__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL\r
-.set SD_SCK__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN\r
-.set SD_SCK__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0\r
-.set SD_SCK__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1\r
-.set SD_SCK__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0\r
-.set SD_SCK__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1\r
-.set SD_SCK__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT\r
-.set SD_SCK__PS, CYREG_PRT3_PS\r
-.set SD_SCK__SHIFT, 2\r
-.set SD_SCK__SLW, CYREG_PRT3_SLW\r
-\r
-/* SD_TX_DMA */\r
-.set SD_TX_DMA__DRQ_CTL, CYREG_IDMUX_DRQ_CTL0\r
-.set SD_TX_DMA__DRQ_NUMBER, 3\r
-.set SD_TX_DMA__NUMBEROF_TDS, 0\r
-.set SD_TX_DMA__PRIORITY, 1\r
-.set SD_TX_DMA__TERMIN_EN, 0\r
-.set SD_TX_DMA__TERMIN_SEL, 0\r
-.set SD_TX_DMA__TERMOUT0_EN, 1\r
-.set SD_TX_DMA__TERMOUT0_SEL, 3\r
-.set SD_TX_DMA__TERMOUT1_EN, 0\r
-.set SD_TX_DMA__TERMOUT1_SEL, 0\r
-.set SD_TX_DMA_COMPLETE__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
-.set SD_TX_DMA_COMPLETE__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
-.set SD_TX_DMA_COMPLETE__INTC_MASK, 0x40\r
-.set SD_TX_DMA_COMPLETE__INTC_NUMBER, 6\r
-.set SD_TX_DMA_COMPLETE__INTC_PRIOR_NUM, 7\r
-.set SD_TX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_6\r
-.set SD_TX_DMA_COMPLETE__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
-.set SD_TX_DMA_COMPLETE__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
+/* SD_CS */\r
+.set SD_CS__0__INTTYPE, CYREG_PICU3_INTTYPE4\r
+.set SD_CS__0__MASK, 0x10\r
+.set SD_CS__0__PC, CYREG_PRT3_PC4\r
+.set SD_CS__0__PORT, 3\r
+.set SD_CS__0__SHIFT, 4\r
+.set SD_CS__AG, CYREG_PRT3_AG\r
+.set SD_CS__AMUX, CYREG_PRT3_AMUX\r
+.set SD_CS__BIE, CYREG_PRT3_BIE\r
+.set SD_CS__BIT_MASK, CYREG_PRT3_BIT_MASK\r
+.set SD_CS__BYP, CYREG_PRT3_BYP\r
+.set SD_CS__CTL, CYREG_PRT3_CTL\r
+.set SD_CS__DM0, CYREG_PRT3_DM0\r
+.set SD_CS__DM1, CYREG_PRT3_DM1\r
+.set SD_CS__DM2, CYREG_PRT3_DM2\r
+.set SD_CS__DR, CYREG_PRT3_DR\r
+.set SD_CS__INP_DIS, CYREG_PRT3_INP_DIS\r
+.set SD_CS__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU3_BASE\r
+.set SD_CS__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG\r
+.set SD_CS__LCD_EN, CYREG_PRT3_LCD_EN\r
+.set SD_CS__MASK, 0x10\r
+.set SD_CS__PORT, 3\r
+.set SD_CS__PRT, CYREG_PRT3_PRT\r
+.set SD_CS__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL\r
+.set SD_CS__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN\r
+.set SD_CS__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0\r
+.set SD_CS__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1\r
+.set SD_CS__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0\r
+.set SD_CS__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1\r
+.set SD_CS__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT\r
+.set SD_CS__PS, CYREG_PRT3_PS\r
+.set SD_CS__SHIFT, 4\r
+.set SD_CS__SLW, CYREG_PRT3_SLW\r
\r
/* USBFS */\r
.set USBFS_arb_int__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
.set USBFS_USB__USBIO_CR0, CYREG_USB_USBIO_CR0\r
.set USBFS_USB__USBIO_CR1, CYREG_USB_USBIO_CR1\r
\r
+/* SDCard */\r
+.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB04_05_ACTL\r
+.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB04_05_CTL\r
+.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB04_05_CTL\r
+.set SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB04_05_CTL\r
+.set SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB04_05_CTL\r
+.set SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B1_UDB04_05_MSK\r
+.set SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB04_05_MSK\r
+.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB04_05_MSK\r
+.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB04_05_MSK\r
+.set SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B1_UDB04_ACTL\r
+.set SDCard_BSPIM_BitCounter__CONTROL_REG, CYREG_B1_UDB04_CTL\r
+.set SDCard_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B1_UDB04_ST_CTL\r
+.set SDCard_BSPIM_BitCounter__COUNT_REG, CYREG_B1_UDB04_CTL\r
+.set SDCard_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B1_UDB04_ST_CTL\r
+.set SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL\r
+.set SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL\r
+.set SDCard_BSPIM_BitCounter__PERIOD_REG, CYREG_B1_UDB04_MSK\r
+.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB04_05_ACTL\r
+.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B1_UDB04_05_ST\r
+.set SDCard_BSPIM_BitCounter_ST__MASK_REG, CYREG_B1_UDB04_MSK\r
+.set SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL\r
+.set SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL\r
+.set SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B1_UDB04_ACTL\r
+.set SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B1_UDB04_ST_CTL\r
+.set SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B1_UDB04_ST_CTL\r
+.set SDCard_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B1_UDB04_ST\r
+.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB08_09_ACTL\r
+.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB08_09_ST\r
+.set SDCard_BSPIM_RxStsReg__4__MASK, 0x10\r
+.set SDCard_BSPIM_RxStsReg__4__POS, 4\r
+.set SDCard_BSPIM_RxStsReg__5__MASK, 0x20\r
+.set SDCard_BSPIM_RxStsReg__5__POS, 5\r
+.set SDCard_BSPIM_RxStsReg__6__MASK, 0x40\r
+.set SDCard_BSPIM_RxStsReg__6__POS, 6\r
+.set SDCard_BSPIM_RxStsReg__MASK, 0x70\r
+.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B1_UDB08_MSK\r
+.set SDCard_BSPIM_RxStsReg__MASK_ST_AUX_CTL_REG, CYREG_B1_UDB08_MSK_ACTL\r
+.set SDCard_BSPIM_RxStsReg__PER_ST_AUX_CTL_REG, CYREG_B1_UDB08_MSK_ACTL\r
+.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB08_ACTL\r
+.set SDCard_BSPIM_RxStsReg__STATUS_CNT_REG, CYREG_B1_UDB08_ST_CTL\r
+.set SDCard_BSPIM_RxStsReg__STATUS_CONTROL_REG, CYREG_B1_UDB08_ST_CTL\r
+.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B1_UDB08_ST\r
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG, CYREG_B1_UDB04_05_A0\r
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG, CYREG_B1_UDB04_05_A1\r
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG, CYREG_B1_UDB04_05_D0\r
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG, CYREG_B1_UDB04_05_D1\r
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG, CYREG_B1_UDB04_05_ACTL\r
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG, CYREG_B1_UDB04_05_F0\r
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG, CYREG_B1_UDB04_05_F1\r
+.set SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG, CYREG_B1_UDB04_A0_A1\r
+.set SDCard_BSPIM_sR8_Dp_u0__A0_REG, CYREG_B1_UDB04_A0\r
+.set SDCard_BSPIM_sR8_Dp_u0__A1_REG, CYREG_B1_UDB04_A1\r
+.set SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG, CYREG_B1_UDB04_D0_D1\r
+.set SDCard_BSPIM_sR8_Dp_u0__D0_REG, CYREG_B1_UDB04_D0\r
+.set SDCard_BSPIM_sR8_Dp_u0__D1_REG, CYREG_B1_UDB04_D1\r
+.set SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG, CYREG_B1_UDB04_ACTL\r
+.set SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG, CYREG_B1_UDB04_F0_F1\r
+.set SDCard_BSPIM_sR8_Dp_u0__F0_REG, CYREG_B1_UDB04_F0\r
+.set SDCard_BSPIM_sR8_Dp_u0__F1_REG, CYREG_B1_UDB04_F1\r
+.set SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL\r
+.set SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL\r
+.set SDCard_BSPIM_TxStsReg__0__MASK, 0x01\r
+.set SDCard_BSPIM_TxStsReg__0__POS, 0\r
+.set SDCard_BSPIM_TxStsReg__1__MASK, 0x02\r
+.set SDCard_BSPIM_TxStsReg__1__POS, 1\r
+.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB07_08_ACTL\r
+.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB07_08_ST\r
+.set SDCard_BSPIM_TxStsReg__2__MASK, 0x04\r
+.set SDCard_BSPIM_TxStsReg__2__POS, 2\r
+.set SDCard_BSPIM_TxStsReg__3__MASK, 0x08\r
+.set SDCard_BSPIM_TxStsReg__3__POS, 3\r
+.set SDCard_BSPIM_TxStsReg__4__MASK, 0x10\r
+.set SDCard_BSPIM_TxStsReg__4__POS, 4\r
+.set SDCard_BSPIM_TxStsReg__MASK, 0x1F\r
+.set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B1_UDB07_MSK\r
+.set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB07_ACTL\r
+.set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B1_UDB07_ST\r
+\r
+/* SD_SCK */\r
+.set SD_SCK__0__INTTYPE, CYREG_PICU3_INTTYPE2\r
+.set SD_SCK__0__MASK, 0x04\r
+.set SD_SCK__0__PC, CYREG_PRT3_PC2\r
+.set SD_SCK__0__PORT, 3\r
+.set SD_SCK__0__SHIFT, 2\r
+.set SD_SCK__AG, CYREG_PRT3_AG\r
+.set SD_SCK__AMUX, CYREG_PRT3_AMUX\r
+.set SD_SCK__BIE, CYREG_PRT3_BIE\r
+.set SD_SCK__BIT_MASK, CYREG_PRT3_BIT_MASK\r
+.set SD_SCK__BYP, CYREG_PRT3_BYP\r
+.set SD_SCK__CTL, CYREG_PRT3_CTL\r
+.set SD_SCK__DM0, CYREG_PRT3_DM0\r
+.set SD_SCK__DM1, CYREG_PRT3_DM1\r
+.set SD_SCK__DM2, CYREG_PRT3_DM2\r
+.set SD_SCK__DR, CYREG_PRT3_DR\r
+.set SD_SCK__INP_DIS, CYREG_PRT3_INP_DIS\r
+.set SD_SCK__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU3_BASE\r
+.set SD_SCK__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG\r
+.set SD_SCK__LCD_EN, CYREG_PRT3_LCD_EN\r
+.set SD_SCK__MASK, 0x04\r
+.set SD_SCK__PORT, 3\r
+.set SD_SCK__PRT, CYREG_PRT3_PRT\r
+.set SD_SCK__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL\r
+.set SD_SCK__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN\r
+.set SD_SCK__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0\r
+.set SD_SCK__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1\r
+.set SD_SCK__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0\r
+.set SD_SCK__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1\r
+.set SD_SCK__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT\r
+.set SD_SCK__PS, CYREG_PRT3_PS\r
+.set SD_SCK__SHIFT, 2\r
+.set SD_SCK__SLW, CYREG_PRT3_SLW\r
+\r
+/* SCSI_In */\r
+.set SCSI_In__0__AG, CYREG_PRT2_AG\r
+.set SCSI_In__0__AMUX, CYREG_PRT2_AMUX\r
+.set SCSI_In__0__BIE, CYREG_PRT2_BIE\r
+.set SCSI_In__0__BIT_MASK, CYREG_PRT2_BIT_MASK\r
+.set SCSI_In__0__BYP, CYREG_PRT2_BYP\r
+.set SCSI_In__0__CTL, CYREG_PRT2_CTL\r
+.set SCSI_In__0__DM0, CYREG_PRT2_DM0\r
+.set SCSI_In__0__DM1, CYREG_PRT2_DM1\r
+.set SCSI_In__0__DM2, CYREG_PRT2_DM2\r
+.set SCSI_In__0__DR, CYREG_PRT2_DR\r
+.set SCSI_In__0__INP_DIS, CYREG_PRT2_INP_DIS\r
+.set SCSI_In__0__INTTYPE, CYREG_PICU2_INTTYPE0\r
+.set SCSI_In__0__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG\r
+.set SCSI_In__0__LCD_EN, CYREG_PRT2_LCD_EN\r
+.set SCSI_In__0__MASK, 0x01\r
+.set SCSI_In__0__PC, CYREG_PRT2_PC0\r
+.set SCSI_In__0__PORT, 2\r
+.set SCSI_In__0__PRT, CYREG_PRT2_PRT\r
+.set SCSI_In__0__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL\r
+.set SCSI_In__0__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN\r
+.set SCSI_In__0__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0\r
+.set SCSI_In__0__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1\r
+.set SCSI_In__0__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0\r
+.set SCSI_In__0__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1\r
+.set SCSI_In__0__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT\r
+.set SCSI_In__0__PS, CYREG_PRT2_PS\r
+.set SCSI_In__0__SHIFT, 0\r
+.set SCSI_In__0__SLW, CYREG_PRT2_SLW\r
+.set SCSI_In__1__AG, CYREG_PRT6_AG\r
+.set SCSI_In__1__AMUX, CYREG_PRT6_AMUX\r
+.set SCSI_In__1__BIE, CYREG_PRT6_BIE\r
+.set SCSI_In__1__BIT_MASK, CYREG_PRT6_BIT_MASK\r
+.set SCSI_In__1__BYP, CYREG_PRT6_BYP\r
+.set SCSI_In__1__CTL, CYREG_PRT6_CTL\r
+.set SCSI_In__1__DM0, CYREG_PRT6_DM0\r
+.set SCSI_In__1__DM1, CYREG_PRT6_DM1\r
+.set SCSI_In__1__DM2, CYREG_PRT6_DM2\r
+.set SCSI_In__1__DR, CYREG_PRT6_DR\r
+.set SCSI_In__1__INP_DIS, CYREG_PRT6_INP_DIS\r
+.set SCSI_In__1__INTTYPE, CYREG_PICU6_INTTYPE7\r
+.set SCSI_In__1__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG\r
+.set SCSI_In__1__LCD_EN, CYREG_PRT6_LCD_EN\r
+.set SCSI_In__1__MASK, 0x80\r
+.set SCSI_In__1__PC, CYREG_PRT6_PC7\r
+.set SCSI_In__1__PORT, 6\r
+.set SCSI_In__1__PRT, CYREG_PRT6_PRT\r
+.set SCSI_In__1__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL\r
+.set SCSI_In__1__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN\r
+.set SCSI_In__1__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0\r
+.set SCSI_In__1__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1\r
+.set SCSI_In__1__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0\r
+.set SCSI_In__1__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1\r
+.set SCSI_In__1__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT\r
+.set SCSI_In__1__PS, CYREG_PRT6_PS\r
+.set SCSI_In__1__SHIFT, 7\r
+.set SCSI_In__1__SLW, CYREG_PRT6_SLW\r
+.set SCSI_In__2__AG, CYREG_PRT5_AG\r
+.set SCSI_In__2__AMUX, CYREG_PRT5_AMUX\r
+.set SCSI_In__2__BIE, CYREG_PRT5_BIE\r
+.set SCSI_In__2__BIT_MASK, CYREG_PRT5_BIT_MASK\r
+.set SCSI_In__2__BYP, CYREG_PRT5_BYP\r
+.set SCSI_In__2__CTL, CYREG_PRT5_CTL\r
+.set SCSI_In__2__DM0, CYREG_PRT5_DM0\r
+.set SCSI_In__2__DM1, CYREG_PRT5_DM1\r
+.set SCSI_In__2__DM2, CYREG_PRT5_DM2\r
+.set SCSI_In__2__DR, CYREG_PRT5_DR\r
+.set SCSI_In__2__INP_DIS, CYREG_PRT5_INP_DIS\r
+.set SCSI_In__2__INTTYPE, CYREG_PICU5_INTTYPE1\r
+.set SCSI_In__2__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG\r
+.set SCSI_In__2__LCD_EN, CYREG_PRT5_LCD_EN\r
+.set SCSI_In__2__MASK, 0x02\r
+.set SCSI_In__2__PC, CYREG_PRT5_PC1\r
+.set SCSI_In__2__PORT, 5\r
+.set SCSI_In__2__PRT, CYREG_PRT5_PRT\r
+.set SCSI_In__2__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL\r
+.set SCSI_In__2__PRTDSI__DBL_SYNC_IN, CYREG_PRT5_DBL_SYNC_IN\r
+.set SCSI_In__2__PRTDSI__OE_SEL0, CYREG_PRT5_OE_SEL0\r
+.set SCSI_In__2__PRTDSI__OE_SEL1, CYREG_PRT5_OE_SEL1\r
+.set SCSI_In__2__PRTDSI__OUT_SEL0, CYREG_PRT5_OUT_SEL0\r
+.set SCSI_In__2__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1\r
+.set SCSI_In__2__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT\r
+.set SCSI_In__2__PS, CYREG_PRT5_PS\r
+.set SCSI_In__2__SHIFT, 1\r
+.set SCSI_In__2__SLW, CYREG_PRT5_SLW\r
+.set SCSI_In__3__AG, CYREG_PRT5_AG\r
+.set SCSI_In__3__AMUX, CYREG_PRT5_AMUX\r
+.set SCSI_In__3__BIE, CYREG_PRT5_BIE\r
+.set SCSI_In__3__BIT_MASK, CYREG_PRT5_BIT_MASK\r
+.set SCSI_In__3__BYP, CYREG_PRT5_BYP\r
+.set SCSI_In__3__CTL, CYREG_PRT5_CTL\r
+.set SCSI_In__3__DM0, CYREG_PRT5_DM0\r
+.set SCSI_In__3__DM1, CYREG_PRT5_DM1\r
+.set SCSI_In__3__DM2, CYREG_PRT5_DM2\r
+.set SCSI_In__3__DR, CYREG_PRT5_DR\r
+.set SCSI_In__3__INP_DIS, CYREG_PRT5_INP_DIS\r
+.set SCSI_In__3__INTTYPE, CYREG_PICU5_INTTYPE2\r
+.set SCSI_In__3__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG\r
+.set SCSI_In__3__LCD_EN, CYREG_PRT5_LCD_EN\r
+.set SCSI_In__3__MASK, 0x04\r
+.set SCSI_In__3__PC, CYREG_PRT5_PC2\r
+.set SCSI_In__3__PORT, 5\r
+.set SCSI_In__3__PRT, CYREG_PRT5_PRT\r
+.set SCSI_In__3__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL\r
+.set SCSI_In__3__PRTDSI__DBL_SYNC_IN, CYREG_PRT5_DBL_SYNC_IN\r
+.set SCSI_In__3__PRTDSI__OE_SEL0, CYREG_PRT5_OE_SEL0\r
+.set SCSI_In__3__PRTDSI__OE_SEL1, CYREG_PRT5_OE_SEL1\r
+.set SCSI_In__3__PRTDSI__OUT_SEL0, CYREG_PRT5_OUT_SEL0\r
+.set SCSI_In__3__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1\r
+.set SCSI_In__3__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT\r
+.set SCSI_In__3__PS, CYREG_PRT5_PS\r
+.set SCSI_In__3__SHIFT, 2\r
+.set SCSI_In__3__SLW, CYREG_PRT5_SLW\r
+.set SCSI_In__4__AG, CYREG_PRT5_AG\r
+.set SCSI_In__4__AMUX, CYREG_PRT5_AMUX\r
+.set SCSI_In__4__BIE, CYREG_PRT5_BIE\r
+.set SCSI_In__4__BIT_MASK, CYREG_PRT5_BIT_MASK\r
+.set SCSI_In__4__BYP, CYREG_PRT5_BYP\r
+.set SCSI_In__4__CTL, CYREG_PRT5_CTL\r
+.set SCSI_In__4__DM0, CYREG_PRT5_DM0\r
+.set SCSI_In__4__DM1, CYREG_PRT5_DM1\r
+.set SCSI_In__4__DM2, CYREG_PRT5_DM2\r
+.set SCSI_In__4__DR, CYREG_PRT5_DR\r
+.set SCSI_In__4__INP_DIS, CYREG_PRT5_INP_DIS\r
+.set SCSI_In__4__INTTYPE, CYREG_PICU5_INTTYPE3\r
+.set SCSI_In__4__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG\r
+.set SCSI_In__4__LCD_EN, CYREG_PRT5_LCD_EN\r
+.set SCSI_In__4__MASK, 0x08\r
+.set SCSI_In__4__PC, CYREG_PRT5_PC3\r
+.set SCSI_In__4__PORT, 5\r
+.set SCSI_In__4__PRT, CYREG_PRT5_PRT\r
+.set SCSI_In__4__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL\r
+.set SCSI_In__4__PRTDSI__DBL_SYNC_IN, CYREG_PRT5_DBL_SYNC_IN\r
+.set SCSI_In__4__PRTDSI__OE_SEL0, CYREG_PRT5_OE_SEL0\r
+.set SCSI_In__4__PRTDSI__OE_SEL1, CYREG_PRT5_OE_SEL1\r
+.set SCSI_In__4__PRTDSI__OUT_SEL0, CYREG_PRT5_OUT_SEL0\r
+.set SCSI_In__4__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1\r
+.set SCSI_In__4__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT\r
+.set SCSI_In__4__PS, CYREG_PRT5_PS\r
+.set SCSI_In__4__SHIFT, 3\r
+.set SCSI_In__4__SLW, CYREG_PRT5_SLW\r
+.set SCSI_In__CD__AG, CYREG_PRT5_AG\r
+.set SCSI_In__CD__AMUX, CYREG_PRT5_AMUX\r
+.set SCSI_In__CD__BIE, CYREG_PRT5_BIE\r
+.set SCSI_In__CD__BIT_MASK, CYREG_PRT5_BIT_MASK\r
+.set SCSI_In__CD__BYP, CYREG_PRT5_BYP\r
+.set SCSI_In__CD__CTL, CYREG_PRT5_CTL\r
+.set SCSI_In__CD__DM0, CYREG_PRT5_DM0\r
+.set SCSI_In__CD__DM1, CYREG_PRT5_DM1\r
+.set SCSI_In__CD__DM2, CYREG_PRT5_DM2\r
+.set SCSI_In__CD__DR, CYREG_PRT5_DR\r
+.set SCSI_In__CD__INP_DIS, CYREG_PRT5_INP_DIS\r
+.set SCSI_In__CD__INTTYPE, CYREG_PICU5_INTTYPE1\r
+.set SCSI_In__CD__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG\r
+.set SCSI_In__CD__LCD_EN, CYREG_PRT5_LCD_EN\r
+.set SCSI_In__CD__MASK, 0x02\r
+.set SCSI_In__CD__PC, CYREG_PRT5_PC1\r
+.set SCSI_In__CD__PORT, 5\r
+.set SCSI_In__CD__PRT, CYREG_PRT5_PRT\r
+.set SCSI_In__CD__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL\r
+.set SCSI_In__CD__PRTDSI__DBL_SYNC_IN, CYREG_PRT5_DBL_SYNC_IN\r
+.set SCSI_In__CD__PRTDSI__OE_SEL0, CYREG_PRT5_OE_SEL0\r
+.set SCSI_In__CD__PRTDSI__OE_SEL1, CYREG_PRT5_OE_SEL1\r
+.set SCSI_In__CD__PRTDSI__OUT_SEL0, CYREG_PRT5_OUT_SEL0\r
+.set SCSI_In__CD__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1\r
+.set SCSI_In__CD__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT\r
+.set SCSI_In__CD__PS, CYREG_PRT5_PS\r
+.set SCSI_In__CD__SHIFT, 1\r
+.set SCSI_In__CD__SLW, CYREG_PRT5_SLW\r
+.set SCSI_In__DBP__AG, CYREG_PRT2_AG\r
+.set SCSI_In__DBP__AMUX, CYREG_PRT2_AMUX\r
+.set SCSI_In__DBP__BIE, CYREG_PRT2_BIE\r
+.set SCSI_In__DBP__BIT_MASK, CYREG_PRT2_BIT_MASK\r
+.set SCSI_In__DBP__BYP, CYREG_PRT2_BYP\r
+.set SCSI_In__DBP__CTL, CYREG_PRT2_CTL\r
+.set SCSI_In__DBP__DM0, CYREG_PRT2_DM0\r
+.set SCSI_In__DBP__DM1, CYREG_PRT2_DM1\r
+.set SCSI_In__DBP__DM2, CYREG_PRT2_DM2\r
+.set SCSI_In__DBP__DR, CYREG_PRT2_DR\r
+.set SCSI_In__DBP__INP_DIS, CYREG_PRT2_INP_DIS\r
+.set SCSI_In__DBP__INTTYPE, CYREG_PICU2_INTTYPE0\r
+.set SCSI_In__DBP__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG\r
+.set SCSI_In__DBP__LCD_EN, CYREG_PRT2_LCD_EN\r
+.set SCSI_In__DBP__MASK, 0x01\r
+.set SCSI_In__DBP__PC, CYREG_PRT2_PC0\r
+.set SCSI_In__DBP__PORT, 2\r
+.set SCSI_In__DBP__PRT, CYREG_PRT2_PRT\r
+.set SCSI_In__DBP__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL\r
+.set SCSI_In__DBP__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN\r
+.set SCSI_In__DBP__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0\r
+.set SCSI_In__DBP__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1\r
+.set SCSI_In__DBP__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0\r
+.set SCSI_In__DBP__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1\r
+.set SCSI_In__DBP__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT\r
+.set SCSI_In__DBP__PS, CYREG_PRT2_PS\r
+.set SCSI_In__DBP__SHIFT, 0\r
+.set SCSI_In__DBP__SLW, CYREG_PRT2_SLW\r
+.set SCSI_In__IO__AG, CYREG_PRT5_AG\r
+.set SCSI_In__IO__AMUX, CYREG_PRT5_AMUX\r
+.set SCSI_In__IO__BIE, CYREG_PRT5_BIE\r
+.set SCSI_In__IO__BIT_MASK, CYREG_PRT5_BIT_MASK\r
+.set SCSI_In__IO__BYP, CYREG_PRT5_BYP\r
+.set SCSI_In__IO__CTL, CYREG_PRT5_CTL\r
+.set SCSI_In__IO__DM0, CYREG_PRT5_DM0\r
+.set SCSI_In__IO__DM1, CYREG_PRT5_DM1\r
+.set SCSI_In__IO__DM2, CYREG_PRT5_DM2\r
+.set SCSI_In__IO__DR, CYREG_PRT5_DR\r
+.set SCSI_In__IO__INP_DIS, CYREG_PRT5_INP_DIS\r
+.set SCSI_In__IO__INTTYPE, CYREG_PICU5_INTTYPE3\r
+.set SCSI_In__IO__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG\r
+.set SCSI_In__IO__LCD_EN, CYREG_PRT5_LCD_EN\r
+.set SCSI_In__IO__MASK, 0x08\r
+.set SCSI_In__IO__PC, CYREG_PRT5_PC3\r
+.set SCSI_In__IO__PORT, 5\r
+.set SCSI_In__IO__PRT, CYREG_PRT5_PRT\r
+.set SCSI_In__IO__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL\r
+.set SCSI_In__IO__PRTDSI__DBL_SYNC_IN, CYREG_PRT5_DBL_SYNC_IN\r
+.set SCSI_In__IO__PRTDSI__OE_SEL0, CYREG_PRT5_OE_SEL0\r
+.set SCSI_In__IO__PRTDSI__OE_SEL1, CYREG_PRT5_OE_SEL1\r
+.set SCSI_In__IO__PRTDSI__OUT_SEL0, CYREG_PRT5_OUT_SEL0\r
+.set SCSI_In__IO__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1\r
+.set SCSI_In__IO__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT\r
+.set SCSI_In__IO__PS, CYREG_PRT5_PS\r
+.set SCSI_In__IO__SHIFT, 3\r
+.set SCSI_In__IO__SLW, CYREG_PRT5_SLW\r
+.set SCSI_In__MSG__AG, CYREG_PRT6_AG\r
+.set SCSI_In__MSG__AMUX, CYREG_PRT6_AMUX\r
+.set SCSI_In__MSG__BIE, CYREG_PRT6_BIE\r
+.set SCSI_In__MSG__BIT_MASK, CYREG_PRT6_BIT_MASK\r
+.set SCSI_In__MSG__BYP, CYREG_PRT6_BYP\r
+.set SCSI_In__MSG__CTL, CYREG_PRT6_CTL\r
+.set SCSI_In__MSG__DM0, CYREG_PRT6_DM0\r
+.set SCSI_In__MSG__DM1, CYREG_PRT6_DM1\r
+.set SCSI_In__MSG__DM2, CYREG_PRT6_DM2\r
+.set SCSI_In__MSG__DR, CYREG_PRT6_DR\r
+.set SCSI_In__MSG__INP_DIS, CYREG_PRT6_INP_DIS\r
+.set SCSI_In__MSG__INTTYPE, CYREG_PICU6_INTTYPE7\r
+.set SCSI_In__MSG__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG\r
+.set SCSI_In__MSG__LCD_EN, CYREG_PRT6_LCD_EN\r
+.set SCSI_In__MSG__MASK, 0x80\r
+.set SCSI_In__MSG__PC, CYREG_PRT6_PC7\r
+.set SCSI_In__MSG__PORT, 6\r
+.set SCSI_In__MSG__PRT, CYREG_PRT6_PRT\r
+.set SCSI_In__MSG__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL\r
+.set SCSI_In__MSG__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN\r
+.set SCSI_In__MSG__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0\r
+.set SCSI_In__MSG__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1\r
+.set SCSI_In__MSG__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0\r
+.set SCSI_In__MSG__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1\r
+.set SCSI_In__MSG__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT\r
+.set SCSI_In__MSG__PS, CYREG_PRT6_PS\r
+.set SCSI_In__MSG__SHIFT, 7\r
+.set SCSI_In__MSG__SLW, CYREG_PRT6_SLW\r
+.set SCSI_In__REQ__AG, CYREG_PRT5_AG\r
+.set SCSI_In__REQ__AMUX, CYREG_PRT5_AMUX\r
+.set SCSI_In__REQ__BIE, CYREG_PRT5_BIE\r
+.set SCSI_In__REQ__BIT_MASK, CYREG_PRT5_BIT_MASK\r
+.set SCSI_In__REQ__BYP, CYREG_PRT5_BYP\r
+.set SCSI_In__REQ__CTL, CYREG_PRT5_CTL\r
+.set SCSI_In__REQ__DM0, CYREG_PRT5_DM0\r
+.set SCSI_In__REQ__DM1, CYREG_PRT5_DM1\r
+.set SCSI_In__REQ__DM2, CYREG_PRT5_DM2\r
+.set SCSI_In__REQ__DR, CYREG_PRT5_DR\r
+.set SCSI_In__REQ__INP_DIS, CYREG_PRT5_INP_DIS\r
+.set SCSI_In__REQ__INTTYPE, CYREG_PICU5_INTTYPE2\r
+.set SCSI_In__REQ__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG\r
+.set SCSI_In__REQ__LCD_EN, CYREG_PRT5_LCD_EN\r
+.set SCSI_In__REQ__MASK, 0x04\r
+.set SCSI_In__REQ__PC, CYREG_PRT5_PC2\r
+.set SCSI_In__REQ__PORT, 5\r
+.set SCSI_In__REQ__PRT, CYREG_PRT5_PRT\r
+.set SCSI_In__REQ__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL\r
+.set SCSI_In__REQ__PRTDSI__DBL_SYNC_IN, CYREG_PRT5_DBL_SYNC_IN\r
+.set SCSI_In__REQ__PRTDSI__OE_SEL0, CYREG_PRT5_OE_SEL0\r
+.set SCSI_In__REQ__PRTDSI__OE_SEL1, CYREG_PRT5_OE_SEL1\r
+.set SCSI_In__REQ__PRTDSI__OUT_SEL0, CYREG_PRT5_OUT_SEL0\r
+.set SCSI_In__REQ__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1\r
+.set SCSI_In__REQ__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT\r
+.set SCSI_In__REQ__PS, CYREG_PRT5_PS\r
+.set SCSI_In__REQ__SHIFT, 2\r
+.set SCSI_In__REQ__SLW, CYREG_PRT5_SLW\r
+.set SCSI_In_DBx__0__AG, CYREG_PRT12_AG\r
+.set SCSI_In_DBx__0__BIE, CYREG_PRT12_BIE\r
+.set SCSI_In_DBx__0__BIT_MASK, CYREG_PRT12_BIT_MASK\r
+.set SCSI_In_DBx__0__BYP, CYREG_PRT12_BYP\r
+.set SCSI_In_DBx__0__DM0, CYREG_PRT12_DM0\r
+.set SCSI_In_DBx__0__DM1, CYREG_PRT12_DM1\r
+.set SCSI_In_DBx__0__DM2, CYREG_PRT12_DM2\r
+.set SCSI_In_DBx__0__DR, CYREG_PRT12_DR\r
+.set SCSI_In_DBx__0__INP_DIS, CYREG_PRT12_INP_DIS\r
+.set SCSI_In_DBx__0__INTTYPE, CYREG_PICU12_INTTYPE4\r
+.set SCSI_In_DBx__0__MASK, 0x10\r
+.set SCSI_In_DBx__0__PC, CYREG_PRT12_PC4\r
+.set SCSI_In_DBx__0__PORT, 12\r
+.set SCSI_In_DBx__0__PRT, CYREG_PRT12_PRT\r
+.set SCSI_In_DBx__0__PRTDSI__DBL_SYNC_IN, CYREG_PRT12_DBL_SYNC_IN\r
+.set SCSI_In_DBx__0__PRTDSI__OE_SEL0, CYREG_PRT12_OE_SEL0\r
+.set SCSI_In_DBx__0__PRTDSI__OE_SEL1, CYREG_PRT12_OE_SEL1\r
+.set SCSI_In_DBx__0__PRTDSI__OUT_SEL0, CYREG_PRT12_OUT_SEL0\r
+.set SCSI_In_DBx__0__PRTDSI__OUT_SEL1, CYREG_PRT12_OUT_SEL1\r
+.set SCSI_In_DBx__0__PRTDSI__SYNC_OUT, CYREG_PRT12_SYNC_OUT\r
+.set SCSI_In_DBx__0__PS, CYREG_PRT12_PS\r
+.set SCSI_In_DBx__0__SHIFT, 4\r
+.set SCSI_In_DBx__0__SIO_CFG, CYREG_PRT12_SIO_CFG\r
+.set SCSI_In_DBx__0__SIO_DIFF, CYREG_PRT12_SIO_DIFF\r
+.set SCSI_In_DBx__0__SIO_HYST_EN, CYREG_PRT12_SIO_HYST_EN\r
+.set SCSI_In_DBx__0__SIO_REG_HIFREQ, CYREG_PRT12_SIO_REG_HIFREQ\r
+.set SCSI_In_DBx__0__SLW, CYREG_PRT12_SLW\r
+.set SCSI_In_DBx__1__AG, CYREG_PRT2_AG\r
+.set SCSI_In_DBx__1__AMUX, CYREG_PRT2_AMUX\r
+.set SCSI_In_DBx__1__BIE, CYREG_PRT2_BIE\r
+.set SCSI_In_DBx__1__BIT_MASK, CYREG_PRT2_BIT_MASK\r
+.set SCSI_In_DBx__1__BYP, CYREG_PRT2_BYP\r
+.set SCSI_In_DBx__1__CTL, CYREG_PRT2_CTL\r
+.set SCSI_In_DBx__1__DM0, CYREG_PRT2_DM0\r
+.set SCSI_In_DBx__1__DM1, CYREG_PRT2_DM1\r
+.set SCSI_In_DBx__1__DM2, CYREG_PRT2_DM2\r
+.set SCSI_In_DBx__1__DR, CYREG_PRT2_DR\r
+.set SCSI_In_DBx__1__INP_DIS, CYREG_PRT2_INP_DIS\r
+.set SCSI_In_DBx__1__INTTYPE, CYREG_PICU2_INTTYPE7\r
+.set SCSI_In_DBx__1__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG\r
+.set SCSI_In_DBx__1__LCD_EN, CYREG_PRT2_LCD_EN\r
+.set SCSI_In_DBx__1__MASK, 0x80\r
+.set SCSI_In_DBx__1__PC, CYREG_PRT2_PC7\r
+.set SCSI_In_DBx__1__PORT, 2\r
+.set SCSI_In_DBx__1__PRT, CYREG_PRT2_PRT\r
+.set SCSI_In_DBx__1__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL\r
+.set SCSI_In_DBx__1__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN\r
+.set SCSI_In_DBx__1__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0\r
+.set SCSI_In_DBx__1__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1\r
+.set SCSI_In_DBx__1__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0\r
+.set SCSI_In_DBx__1__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1\r
+.set SCSI_In_DBx__1__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT\r
+.set SCSI_In_DBx__1__PS, CYREG_PRT2_PS\r
+.set SCSI_In_DBx__1__SHIFT, 7\r
+.set SCSI_In_DBx__1__SLW, CYREG_PRT2_SLW\r
+.set SCSI_In_DBx__2__AG, CYREG_PRT2_AG\r
+.set SCSI_In_DBx__2__AMUX, CYREG_PRT2_AMUX\r
+.set SCSI_In_DBx__2__BIE, CYREG_PRT2_BIE\r
+.set SCSI_In_DBx__2__BIT_MASK, CYREG_PRT2_BIT_MASK\r
+.set SCSI_In_DBx__2__BYP, CYREG_PRT2_BYP\r
+.set SCSI_In_DBx__2__CTL, CYREG_PRT2_CTL\r
+.set SCSI_In_DBx__2__DM0, CYREG_PRT2_DM0\r
+.set SCSI_In_DBx__2__DM1, CYREG_PRT2_DM1\r
+.set SCSI_In_DBx__2__DM2, CYREG_PRT2_DM2\r
+.set SCSI_In_DBx__2__DR, CYREG_PRT2_DR\r
+.set SCSI_In_DBx__2__INP_DIS, CYREG_PRT2_INP_DIS\r
+.set SCSI_In_DBx__2__INTTYPE, CYREG_PICU2_INTTYPE6\r
+.set SCSI_In_DBx__2__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG\r
+.set SCSI_In_DBx__2__LCD_EN, CYREG_PRT2_LCD_EN\r
+.set SCSI_In_DBx__2__MASK, 0x40\r
+.set SCSI_In_DBx__2__PC, CYREG_PRT2_PC6\r
+.set SCSI_In_DBx__2__PORT, 2\r
+.set SCSI_In_DBx__2__PRT, CYREG_PRT2_PRT\r
+.set SCSI_In_DBx__2__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL\r
+.set SCSI_In_DBx__2__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN\r
+.set SCSI_In_DBx__2__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0\r
+.set SCSI_In_DBx__2__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1\r
+.set SCSI_In_DBx__2__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0\r
+.set SCSI_In_DBx__2__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1\r
+.set SCSI_In_DBx__2__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT\r
+.set SCSI_In_DBx__2__PS, CYREG_PRT2_PS\r
+.set SCSI_In_DBx__2__SHIFT, 6\r
+.set SCSI_In_DBx__2__SLW, CYREG_PRT2_SLW\r
+.set SCSI_In_DBx__3__AG, CYREG_PRT2_AG\r
+.set SCSI_In_DBx__3__AMUX, CYREG_PRT2_AMUX\r
+.set SCSI_In_DBx__3__BIE, CYREG_PRT2_BIE\r
+.set SCSI_In_DBx__3__BIT_MASK, CYREG_PRT2_BIT_MASK\r
+.set SCSI_In_DBx__3__BYP, CYREG_PRT2_BYP\r
+.set SCSI_In_DBx__3__CTL, CYREG_PRT2_CTL\r
+.set SCSI_In_DBx__3__DM0, CYREG_PRT2_DM0\r
+.set SCSI_In_DBx__3__DM1, CYREG_PRT2_DM1\r
+.set SCSI_In_DBx__3__DM2, CYREG_PRT2_DM2\r
+.set SCSI_In_DBx__3__DR, CYREG_PRT2_DR\r
+.set SCSI_In_DBx__3__INP_DIS, CYREG_PRT2_INP_DIS\r
+.set SCSI_In_DBx__3__INTTYPE, CYREG_PICU2_INTTYPE5\r
+.set SCSI_In_DBx__3__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG\r
+.set SCSI_In_DBx__3__LCD_EN, CYREG_PRT2_LCD_EN\r
+.set SCSI_In_DBx__3__MASK, 0x20\r
+.set SCSI_In_DBx__3__PC, CYREG_PRT2_PC5\r
+.set SCSI_In_DBx__3__PORT, 2\r
+.set SCSI_In_DBx__3__PRT, CYREG_PRT2_PRT\r
+.set SCSI_In_DBx__3__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL\r
+.set SCSI_In_DBx__3__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN\r
+.set SCSI_In_DBx__3__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0\r
+.set SCSI_In_DBx__3__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1\r
+.set SCSI_In_DBx__3__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0\r
+.set SCSI_In_DBx__3__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1\r
+.set SCSI_In_DBx__3__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT\r
+.set SCSI_In_DBx__3__PS, CYREG_PRT2_PS\r
+.set SCSI_In_DBx__3__SHIFT, 5\r
+.set SCSI_In_DBx__3__SLW, CYREG_PRT2_SLW\r
+.set SCSI_In_DBx__4__AG, CYREG_PRT2_AG\r
+.set SCSI_In_DBx__4__AMUX, CYREG_PRT2_AMUX\r
+.set SCSI_In_DBx__4__BIE, CYREG_PRT2_BIE\r
+.set SCSI_In_DBx__4__BIT_MASK, CYREG_PRT2_BIT_MASK\r
+.set SCSI_In_DBx__4__BYP, CYREG_PRT2_BYP\r
+.set SCSI_In_DBx__4__CTL, CYREG_PRT2_CTL\r
+.set SCSI_In_DBx__4__DM0, CYREG_PRT2_DM0\r
+.set SCSI_In_DBx__4__DM1, CYREG_PRT2_DM1\r
+.set SCSI_In_DBx__4__DM2, CYREG_PRT2_DM2\r
+.set SCSI_In_DBx__4__DR, CYREG_PRT2_DR\r
+.set SCSI_In_DBx__4__INP_DIS, CYREG_PRT2_INP_DIS\r
+.set SCSI_In_DBx__4__INTTYPE, CYREG_PICU2_INTTYPE4\r
+.set SCSI_In_DBx__4__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG\r
+.set SCSI_In_DBx__4__LCD_EN, CYREG_PRT2_LCD_EN\r
+.set SCSI_In_DBx__4__MASK, 0x10\r
+.set SCSI_In_DBx__4__PC, CYREG_PRT2_PC4\r
+.set SCSI_In_DBx__4__PORT, 2\r
+.set SCSI_In_DBx__4__PRT, CYREG_PRT2_PRT\r
+.set SCSI_In_DBx__4__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL\r
+.set SCSI_In_DBx__4__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN\r
+.set SCSI_In_DBx__4__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0\r
+.set SCSI_In_DBx__4__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1\r
+.set SCSI_In_DBx__4__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0\r
+.set SCSI_In_DBx__4__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1\r
+.set SCSI_In_DBx__4__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT\r
+.set SCSI_In_DBx__4__PS, CYREG_PRT2_PS\r
+.set SCSI_In_DBx__4__SHIFT, 4\r
+.set SCSI_In_DBx__4__SLW, CYREG_PRT2_SLW\r
+.set SCSI_In_DBx__5__AG, CYREG_PRT2_AG\r
+.set SCSI_In_DBx__5__AMUX, CYREG_PRT2_AMUX\r
+.set SCSI_In_DBx__5__BIE, CYREG_PRT2_BIE\r
+.set SCSI_In_DBx__5__BIT_MASK, CYREG_PRT2_BIT_MASK\r
+.set SCSI_In_DBx__5__BYP, CYREG_PRT2_BYP\r
+.set SCSI_In_DBx__5__CTL, CYREG_PRT2_CTL\r
+.set SCSI_In_DBx__5__DM0, CYREG_PRT2_DM0\r
+.set SCSI_In_DBx__5__DM1, CYREG_PRT2_DM1\r
+.set SCSI_In_DBx__5__DM2, CYREG_PRT2_DM2\r
+.set SCSI_In_DBx__5__DR, CYREG_PRT2_DR\r
+.set SCSI_In_DBx__5__INP_DIS, CYREG_PRT2_INP_DIS\r
+.set SCSI_In_DBx__5__INTTYPE, CYREG_PICU2_INTTYPE3\r
+.set SCSI_In_DBx__5__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG\r
+.set SCSI_In_DBx__5__LCD_EN, CYREG_PRT2_LCD_EN\r
+.set SCSI_In_DBx__5__MASK, 0x08\r
+.set SCSI_In_DBx__5__PC, CYREG_PRT2_PC3\r
+.set SCSI_In_DBx__5__PORT, 2\r
+.set SCSI_In_DBx__5__PRT, CYREG_PRT2_PRT\r
+.set SCSI_In_DBx__5__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL\r
+.set SCSI_In_DBx__5__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN\r
+.set SCSI_In_DBx__5__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0\r
+.set SCSI_In_DBx__5__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1\r
+.set SCSI_In_DBx__5__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0\r
+.set SCSI_In_DBx__5__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1\r
+.set SCSI_In_DBx__5__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT\r
+.set SCSI_In_DBx__5__PS, CYREG_PRT2_PS\r
+.set SCSI_In_DBx__5__SHIFT, 3\r
+.set SCSI_In_DBx__5__SLW, CYREG_PRT2_SLW\r
+.set SCSI_In_DBx__6__AG, CYREG_PRT2_AG\r
+.set SCSI_In_DBx__6__AMUX, CYREG_PRT2_AMUX\r
+.set SCSI_In_DBx__6__BIE, CYREG_PRT2_BIE\r
+.set SCSI_In_DBx__6__BIT_MASK, CYREG_PRT2_BIT_MASK\r
+.set SCSI_In_DBx__6__BYP, CYREG_PRT2_BYP\r
+.set SCSI_In_DBx__6__CTL, CYREG_PRT2_CTL\r
+.set SCSI_In_DBx__6__DM0, CYREG_PRT2_DM0\r
+.set SCSI_In_DBx__6__DM1, CYREG_PRT2_DM1\r
+.set SCSI_In_DBx__6__DM2, CYREG_PRT2_DM2\r
+.set SCSI_In_DBx__6__DR, CYREG_PRT2_DR\r
+.set SCSI_In_DBx__6__INP_DIS, CYREG_PRT2_INP_DIS\r
+.set SCSI_In_DBx__6__INTTYPE, CYREG_PICU2_INTTYPE2\r
+.set SCSI_In_DBx__6__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG\r
+.set SCSI_In_DBx__6__LCD_EN, CYREG_PRT2_LCD_EN\r
+.set SCSI_In_DBx__6__MASK, 0x04\r
+.set SCSI_In_DBx__6__PC, CYREG_PRT2_PC2\r
+.set SCSI_In_DBx__6__PORT, 2\r
+.set SCSI_In_DBx__6__PRT, CYREG_PRT2_PRT\r
+.set SCSI_In_DBx__6__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL\r
+.set SCSI_In_DBx__6__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN\r
+.set SCSI_In_DBx__6__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0\r
+.set SCSI_In_DBx__6__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1\r
+.set SCSI_In_DBx__6__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0\r
+.set SCSI_In_DBx__6__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1\r
+.set SCSI_In_DBx__6__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT\r
+.set SCSI_In_DBx__6__PS, CYREG_PRT2_PS\r
+.set SCSI_In_DBx__6__SHIFT, 2\r
+.set SCSI_In_DBx__6__SLW, CYREG_PRT2_SLW\r
+.set SCSI_In_DBx__7__AG, CYREG_PRT2_AG\r
+.set SCSI_In_DBx__7__AMUX, CYREG_PRT2_AMUX\r
+.set SCSI_In_DBx__7__BIE, CYREG_PRT2_BIE\r
+.set SCSI_In_DBx__7__BIT_MASK, CYREG_PRT2_BIT_MASK\r
+.set SCSI_In_DBx__7__BYP, CYREG_PRT2_BYP\r
+.set SCSI_In_DBx__7__CTL, CYREG_PRT2_CTL\r
+.set SCSI_In_DBx__7__DM0, CYREG_PRT2_DM0\r
+.set SCSI_In_DBx__7__DM1, CYREG_PRT2_DM1\r
+.set SCSI_In_DBx__7__DM2, CYREG_PRT2_DM2\r
+.set SCSI_In_DBx__7__DR, CYREG_PRT2_DR\r
+.set SCSI_In_DBx__7__INP_DIS, CYREG_PRT2_INP_DIS\r
+.set SCSI_In_DBx__7__INTTYPE, CYREG_PICU2_INTTYPE1\r
+.set SCSI_In_DBx__7__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG\r
+.set SCSI_In_DBx__7__LCD_EN, CYREG_PRT2_LCD_EN\r
+.set SCSI_In_DBx__7__MASK, 0x02\r
+.set SCSI_In_DBx__7__PC, CYREG_PRT2_PC1\r
+.set SCSI_In_DBx__7__PORT, 2\r
+.set SCSI_In_DBx__7__PRT, CYREG_PRT2_PRT\r
+.set SCSI_In_DBx__7__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL\r
+.set SCSI_In_DBx__7__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN\r
+.set SCSI_In_DBx__7__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0\r
+.set SCSI_In_DBx__7__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1\r
+.set SCSI_In_DBx__7__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0\r
+.set SCSI_In_DBx__7__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1\r
+.set SCSI_In_DBx__7__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT\r
+.set SCSI_In_DBx__7__PS, CYREG_PRT2_PS\r
+.set SCSI_In_DBx__7__SHIFT, 1\r
+.set SCSI_In_DBx__7__SLW, CYREG_PRT2_SLW\r
+.set SCSI_In_DBx__DB0__AG, CYREG_PRT12_AG\r
+.set SCSI_In_DBx__DB0__BIE, CYREG_PRT12_BIE\r
+.set SCSI_In_DBx__DB0__BIT_MASK, CYREG_PRT12_BIT_MASK\r
+.set SCSI_In_DBx__DB0__BYP, CYREG_PRT12_BYP\r
+.set SCSI_In_DBx__DB0__DM0, CYREG_PRT12_DM0\r
+.set SCSI_In_DBx__DB0__DM1, CYREG_PRT12_DM1\r
+.set SCSI_In_DBx__DB0__DM2, CYREG_PRT12_DM2\r
+.set SCSI_In_DBx__DB0__DR, CYREG_PRT12_DR\r
+.set SCSI_In_DBx__DB0__INP_DIS, CYREG_PRT12_INP_DIS\r
+.set SCSI_In_DBx__DB0__INTTYPE, CYREG_PICU12_INTTYPE4\r
+.set SCSI_In_DBx__DB0__MASK, 0x10\r
+.set SCSI_In_DBx__DB0__PC, CYREG_PRT12_PC4\r
+.set SCSI_In_DBx__DB0__PORT, 12\r
+.set SCSI_In_DBx__DB0__PRT, CYREG_PRT12_PRT\r
+.set SCSI_In_DBx__DB0__PRTDSI__DBL_SYNC_IN, CYREG_PRT12_DBL_SYNC_IN\r
+.set SCSI_In_DBx__DB0__PRTDSI__OE_SEL0, CYREG_PRT12_OE_SEL0\r
+.set SCSI_In_DBx__DB0__PRTDSI__OE_SEL1, CYREG_PRT12_OE_SEL1\r
+.set SCSI_In_DBx__DB0__PRTDSI__OUT_SEL0, CYREG_PRT12_OUT_SEL0\r
+.set SCSI_In_DBx__DB0__PRTDSI__OUT_SEL1, CYREG_PRT12_OUT_SEL1\r
+.set SCSI_In_DBx__DB0__PRTDSI__SYNC_OUT, CYREG_PRT12_SYNC_OUT\r
+.set SCSI_In_DBx__DB0__PS, CYREG_PRT12_PS\r
+.set SCSI_In_DBx__DB0__SHIFT, 4\r
+.set SCSI_In_DBx__DB0__SIO_CFG, CYREG_PRT12_SIO_CFG\r
+.set SCSI_In_DBx__DB0__SIO_DIFF, CYREG_PRT12_SIO_DIFF\r
+.set SCSI_In_DBx__DB0__SIO_HYST_EN, CYREG_PRT12_SIO_HYST_EN\r
+.set SCSI_In_DBx__DB0__SIO_REG_HIFREQ, CYREG_PRT12_SIO_REG_HIFREQ\r
+.set SCSI_In_DBx__DB0__SLW, CYREG_PRT12_SLW\r
+.set SCSI_In_DBx__DB1__AG, CYREG_PRT2_AG\r
+.set SCSI_In_DBx__DB1__AMUX, CYREG_PRT2_AMUX\r
+.set SCSI_In_DBx__DB1__BIE, CYREG_PRT2_BIE\r
+.set SCSI_In_DBx__DB1__BIT_MASK, CYREG_PRT2_BIT_MASK\r
+.set SCSI_In_DBx__DB1__BYP, CYREG_PRT2_BYP\r
+.set SCSI_In_DBx__DB1__CTL, CYREG_PRT2_CTL\r
+.set SCSI_In_DBx__DB1__DM0, CYREG_PRT2_DM0\r
+.set SCSI_In_DBx__DB1__DM1, CYREG_PRT2_DM1\r
+.set SCSI_In_DBx__DB1__DM2, CYREG_PRT2_DM2\r
+.set SCSI_In_DBx__DB1__DR, CYREG_PRT2_DR\r
+.set SCSI_In_DBx__DB1__INP_DIS, CYREG_PRT2_INP_DIS\r
+.set SCSI_In_DBx__DB1__INTTYPE, CYREG_PICU2_INTTYPE7\r
+.set SCSI_In_DBx__DB1__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG\r
+.set SCSI_In_DBx__DB1__LCD_EN, CYREG_PRT2_LCD_EN\r
+.set SCSI_In_DBx__DB1__MASK, 0x80\r
+.set SCSI_In_DBx__DB1__PC, CYREG_PRT2_PC7\r
+.set SCSI_In_DBx__DB1__PORT, 2\r
+.set SCSI_In_DBx__DB1__PRT, CYREG_PRT2_PRT\r
+.set SCSI_In_DBx__DB1__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL\r
+.set SCSI_In_DBx__DB1__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN\r
+.set SCSI_In_DBx__DB1__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0\r
+.set SCSI_In_DBx__DB1__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1\r
+.set SCSI_In_DBx__DB1__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0\r
+.set SCSI_In_DBx__DB1__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1\r
+.set SCSI_In_DBx__DB1__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT\r
+.set SCSI_In_DBx__DB1__PS, CYREG_PRT2_PS\r
+.set SCSI_In_DBx__DB1__SHIFT, 7\r
+.set SCSI_In_DBx__DB1__SLW, CYREG_PRT2_SLW\r
+.set SCSI_In_DBx__DB2__AG, CYREG_PRT2_AG\r
+.set SCSI_In_DBx__DB2__AMUX, CYREG_PRT2_AMUX\r
+.set SCSI_In_DBx__DB2__BIE, CYREG_PRT2_BIE\r
+.set SCSI_In_DBx__DB2__BIT_MASK, CYREG_PRT2_BIT_MASK\r
+.set SCSI_In_DBx__DB2__BYP, CYREG_PRT2_BYP\r
+.set SCSI_In_DBx__DB2__CTL, CYREG_PRT2_CTL\r
+.set SCSI_In_DBx__DB2__DM0, CYREG_PRT2_DM0\r
+.set SCSI_In_DBx__DB2__DM1, CYREG_PRT2_DM1\r
+.set SCSI_In_DBx__DB2__DM2, CYREG_PRT2_DM2\r
+.set SCSI_In_DBx__DB2__DR, CYREG_PRT2_DR\r
+.set SCSI_In_DBx__DB2__INP_DIS, CYREG_PRT2_INP_DIS\r
+.set SCSI_In_DBx__DB2__INTTYPE, CYREG_PICU2_INTTYPE6\r
+.set SCSI_In_DBx__DB2__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG\r
+.set SCSI_In_DBx__DB2__LCD_EN, CYREG_PRT2_LCD_EN\r
+.set SCSI_In_DBx__DB2__MASK, 0x40\r
+.set SCSI_In_DBx__DB2__PC, CYREG_PRT2_PC6\r
+.set SCSI_In_DBx__DB2__PORT, 2\r
+.set SCSI_In_DBx__DB2__PRT, CYREG_PRT2_PRT\r
+.set SCSI_In_DBx__DB2__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL\r
+.set SCSI_In_DBx__DB2__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN\r
+.set SCSI_In_DBx__DB2__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0\r
+.set SCSI_In_DBx__DB2__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1\r
+.set SCSI_In_DBx__DB2__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0\r
+.set SCSI_In_DBx__DB2__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1\r
+.set SCSI_In_DBx__DB2__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT\r
+.set SCSI_In_DBx__DB2__PS, CYREG_PRT2_PS\r
+.set SCSI_In_DBx__DB2__SHIFT, 6\r
+.set SCSI_In_DBx__DB2__SLW, CYREG_PRT2_SLW\r
+.set SCSI_In_DBx__DB3__AG, CYREG_PRT2_AG\r
+.set SCSI_In_DBx__DB3__AMUX, CYREG_PRT2_AMUX\r
+.set SCSI_In_DBx__DB3__BIE, CYREG_PRT2_BIE\r
+.set SCSI_In_DBx__DB3__BIT_MASK, CYREG_PRT2_BIT_MASK\r
+.set SCSI_In_DBx__DB3__BYP, CYREG_PRT2_BYP\r
+.set SCSI_In_DBx__DB3__CTL, CYREG_PRT2_CTL\r
+.set SCSI_In_DBx__DB3__DM0, CYREG_PRT2_DM0\r
+.set SCSI_In_DBx__DB3__DM1, CYREG_PRT2_DM1\r
+.set SCSI_In_DBx__DB3__DM2, CYREG_PRT2_DM2\r
+.set SCSI_In_DBx__DB3__DR, CYREG_PRT2_DR\r
+.set SCSI_In_DBx__DB3__INP_DIS, CYREG_PRT2_INP_DIS\r
+.set SCSI_In_DBx__DB3__INTTYPE, CYREG_PICU2_INTTYPE5\r
+.set SCSI_In_DBx__DB3__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG\r
+.set SCSI_In_DBx__DB3__LCD_EN, CYREG_PRT2_LCD_EN\r
+.set SCSI_In_DBx__DB3__MASK, 0x20\r
+.set SCSI_In_DBx__DB3__PC, CYREG_PRT2_PC5\r
+.set SCSI_In_DBx__DB3__PORT, 2\r
+.set SCSI_In_DBx__DB3__PRT, CYREG_PRT2_PRT\r
+.set SCSI_In_DBx__DB3__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL\r
+.set SCSI_In_DBx__DB3__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN\r
+.set SCSI_In_DBx__DB3__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0\r
+.set SCSI_In_DBx__DB3__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1\r
+.set SCSI_In_DBx__DB3__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0\r
+.set SCSI_In_DBx__DB3__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1\r
+.set SCSI_In_DBx__DB3__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT\r
+.set SCSI_In_DBx__DB3__PS, CYREG_PRT2_PS\r
+.set SCSI_In_DBx__DB3__SHIFT, 5\r
+.set SCSI_In_DBx__DB3__SLW, CYREG_PRT2_SLW\r
+.set SCSI_In_DBx__DB4__AG, CYREG_PRT2_AG\r
+.set SCSI_In_DBx__DB4__AMUX, CYREG_PRT2_AMUX\r
+.set SCSI_In_DBx__DB4__BIE, CYREG_PRT2_BIE\r
+.set SCSI_In_DBx__DB4__BIT_MASK, CYREG_PRT2_BIT_MASK\r
+.set SCSI_In_DBx__DB4__BYP, CYREG_PRT2_BYP\r
+.set SCSI_In_DBx__DB4__CTL, CYREG_PRT2_CTL\r
+.set SCSI_In_DBx__DB4__DM0, CYREG_PRT2_DM0\r
+.set SCSI_In_DBx__DB4__DM1, CYREG_PRT2_DM1\r
+.set SCSI_In_DBx__DB4__DM2, CYREG_PRT2_DM2\r
+.set SCSI_In_DBx__DB4__DR, CYREG_PRT2_DR\r
+.set SCSI_In_DBx__DB4__INP_DIS, CYREG_PRT2_INP_DIS\r
+.set SCSI_In_DBx__DB4__INTTYPE, CYREG_PICU2_INTTYPE4\r
+.set SCSI_In_DBx__DB4__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG\r
+.set SCSI_In_DBx__DB4__LCD_EN, CYREG_PRT2_LCD_EN\r
+.set SCSI_In_DBx__DB4__MASK, 0x10\r
+.set SCSI_In_DBx__DB4__PC, CYREG_PRT2_PC4\r
+.set SCSI_In_DBx__DB4__PORT, 2\r
+.set SCSI_In_DBx__DB4__PRT, CYREG_PRT2_PRT\r
+.set SCSI_In_DBx__DB4__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL\r
+.set SCSI_In_DBx__DB4__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN\r
+.set SCSI_In_DBx__DB4__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0\r
+.set SCSI_In_DBx__DB4__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1\r
+.set SCSI_In_DBx__DB4__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0\r
+.set SCSI_In_DBx__DB4__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1\r
+.set SCSI_In_DBx__DB4__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT\r
+.set SCSI_In_DBx__DB4__PS, CYREG_PRT2_PS\r
+.set SCSI_In_DBx__DB4__SHIFT, 4\r
+.set SCSI_In_DBx__DB4__SLW, CYREG_PRT2_SLW\r
+.set SCSI_In_DBx__DB5__AG, CYREG_PRT2_AG\r
+.set SCSI_In_DBx__DB5__AMUX, CYREG_PRT2_AMUX\r
+.set SCSI_In_DBx__DB5__BIE, CYREG_PRT2_BIE\r
+.set SCSI_In_DBx__DB5__BIT_MASK, CYREG_PRT2_BIT_MASK\r
+.set SCSI_In_DBx__DB5__BYP, CYREG_PRT2_BYP\r
+.set SCSI_In_DBx__DB5__CTL, CYREG_PRT2_CTL\r
+.set SCSI_In_DBx__DB5__DM0, CYREG_PRT2_DM0\r
+.set SCSI_In_DBx__DB5__DM1, CYREG_PRT2_DM1\r
+.set SCSI_In_DBx__DB5__DM2, CYREG_PRT2_DM2\r
+.set SCSI_In_DBx__DB5__DR, CYREG_PRT2_DR\r
+.set SCSI_In_DBx__DB5__INP_DIS, CYREG_PRT2_INP_DIS\r
+.set SCSI_In_DBx__DB5__INTTYPE, CYREG_PICU2_INTTYPE3\r
+.set SCSI_In_DBx__DB5__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG\r
+.set SCSI_In_DBx__DB5__LCD_EN, CYREG_PRT2_LCD_EN\r
+.set SCSI_In_DBx__DB5__MASK, 0x08\r
+.set SCSI_In_DBx__DB5__PC, CYREG_PRT2_PC3\r
+.set SCSI_In_DBx__DB5__PORT, 2\r
+.set SCSI_In_DBx__DB5__PRT, CYREG_PRT2_PRT\r
+.set SCSI_In_DBx__DB5__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL\r
+.set SCSI_In_DBx__DB5__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN\r
+.set SCSI_In_DBx__DB5__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0\r
+.set SCSI_In_DBx__DB5__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1\r
+.set SCSI_In_DBx__DB5__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0\r
+.set SCSI_In_DBx__DB5__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1\r
+.set SCSI_In_DBx__DB5__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT\r
+.set SCSI_In_DBx__DB5__PS, CYREG_PRT2_PS\r
+.set SCSI_In_DBx__DB5__SHIFT, 3\r
+.set SCSI_In_DBx__DB5__SLW, CYREG_PRT2_SLW\r
+.set SCSI_In_DBx__DB6__AG, CYREG_PRT2_AG\r
+.set SCSI_In_DBx__DB6__AMUX, CYREG_PRT2_AMUX\r
+.set SCSI_In_DBx__DB6__BIE, CYREG_PRT2_BIE\r
+.set SCSI_In_DBx__DB6__BIT_MASK, CYREG_PRT2_BIT_MASK\r
+.set SCSI_In_DBx__DB6__BYP, CYREG_PRT2_BYP\r
+.set SCSI_In_DBx__DB6__CTL, CYREG_PRT2_CTL\r
+.set SCSI_In_DBx__DB6__DM0, CYREG_PRT2_DM0\r
+.set SCSI_In_DBx__DB6__DM1, CYREG_PRT2_DM1\r
+.set SCSI_In_DBx__DB6__DM2, CYREG_PRT2_DM2\r
+.set SCSI_In_DBx__DB6__DR, CYREG_PRT2_DR\r
+.set SCSI_In_DBx__DB6__INP_DIS, CYREG_PRT2_INP_DIS\r
+.set SCSI_In_DBx__DB6__INTTYPE, CYREG_PICU2_INTTYPE2\r
+.set SCSI_In_DBx__DB6__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG\r
+.set SCSI_In_DBx__DB6__LCD_EN, CYREG_PRT2_LCD_EN\r
+.set SCSI_In_DBx__DB6__MASK, 0x04\r
+.set SCSI_In_DBx__DB6__PC, CYREG_PRT2_PC2\r
+.set SCSI_In_DBx__DB6__PORT, 2\r
+.set SCSI_In_DBx__DB6__PRT, CYREG_PRT2_PRT\r
+.set SCSI_In_DBx__DB6__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL\r
+.set SCSI_In_DBx__DB6__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN\r
+.set SCSI_In_DBx__DB6__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0\r
+.set SCSI_In_DBx__DB6__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1\r
+.set SCSI_In_DBx__DB6__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0\r
+.set SCSI_In_DBx__DB6__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1\r
+.set SCSI_In_DBx__DB6__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT\r
+.set SCSI_In_DBx__DB6__PS, CYREG_PRT2_PS\r
+.set SCSI_In_DBx__DB6__SHIFT, 2\r
+.set SCSI_In_DBx__DB6__SLW, CYREG_PRT2_SLW\r
+.set SCSI_In_DBx__DB7__AG, CYREG_PRT2_AG\r
+.set SCSI_In_DBx__DB7__AMUX, CYREG_PRT2_AMUX\r
+.set SCSI_In_DBx__DB7__BIE, CYREG_PRT2_BIE\r
+.set SCSI_In_DBx__DB7__BIT_MASK, CYREG_PRT2_BIT_MASK\r
+.set SCSI_In_DBx__DB7__BYP, CYREG_PRT2_BYP\r
+.set SCSI_In_DBx__DB7__CTL, CYREG_PRT2_CTL\r
+.set SCSI_In_DBx__DB7__DM0, CYREG_PRT2_DM0\r
+.set SCSI_In_DBx__DB7__DM1, CYREG_PRT2_DM1\r
+.set SCSI_In_DBx__DB7__DM2, CYREG_PRT2_DM2\r
+.set SCSI_In_DBx__DB7__DR, CYREG_PRT2_DR\r
+.set SCSI_In_DBx__DB7__INP_DIS, CYREG_PRT2_INP_DIS\r
+.set SCSI_In_DBx__DB7__INTTYPE, CYREG_PICU2_INTTYPE1\r
+.set SCSI_In_DBx__DB7__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG\r
+.set SCSI_In_DBx__DB7__LCD_EN, CYREG_PRT2_LCD_EN\r
+.set SCSI_In_DBx__DB7__MASK, 0x02\r
+.set SCSI_In_DBx__DB7__PC, CYREG_PRT2_PC1\r
+.set SCSI_In_DBx__DB7__PORT, 2\r
+.set SCSI_In_DBx__DB7__PRT, CYREG_PRT2_PRT\r
+.set SCSI_In_DBx__DB7__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL\r
+.set SCSI_In_DBx__DB7__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN\r
+.set SCSI_In_DBx__DB7__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0\r
+.set SCSI_In_DBx__DB7__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1\r
+.set SCSI_In_DBx__DB7__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0\r
+.set SCSI_In_DBx__DB7__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1\r
+.set SCSI_In_DBx__DB7__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT\r
+.set SCSI_In_DBx__DB7__PS, CYREG_PRT2_PS\r
+.set SCSI_In_DBx__DB7__SHIFT, 1\r
+.set SCSI_In_DBx__DB7__SLW, CYREG_PRT2_SLW\r
+\r
+/* SD_DAT1 */\r
+.set SD_DAT1__0__INTTYPE, CYREG_PICU3_INTTYPE0\r
+.set SD_DAT1__0__MASK, 0x01\r
+.set SD_DAT1__0__PC, CYREG_PRT3_PC0\r
+.set SD_DAT1__0__PORT, 3\r
+.set SD_DAT1__0__SHIFT, 0\r
+.set SD_DAT1__AG, CYREG_PRT3_AG\r
+.set SD_DAT1__AMUX, CYREG_PRT3_AMUX\r
+.set SD_DAT1__BIE, CYREG_PRT3_BIE\r
+.set SD_DAT1__BIT_MASK, CYREG_PRT3_BIT_MASK\r
+.set SD_DAT1__BYP, CYREG_PRT3_BYP\r
+.set SD_DAT1__CTL, CYREG_PRT3_CTL\r
+.set SD_DAT1__DM0, CYREG_PRT3_DM0\r
+.set SD_DAT1__DM1, CYREG_PRT3_DM1\r
+.set SD_DAT1__DM2, CYREG_PRT3_DM2\r
+.set SD_DAT1__DR, CYREG_PRT3_DR\r
+.set SD_DAT1__INP_DIS, CYREG_PRT3_INP_DIS\r
+.set SD_DAT1__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU3_BASE\r
+.set SD_DAT1__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG\r
+.set SD_DAT1__LCD_EN, CYREG_PRT3_LCD_EN\r
+.set SD_DAT1__MASK, 0x01\r
+.set SD_DAT1__PORT, 3\r
+.set SD_DAT1__PRT, CYREG_PRT3_PRT\r
+.set SD_DAT1__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL\r
+.set SD_DAT1__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN\r
+.set SD_DAT1__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0\r
+.set SD_DAT1__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1\r
+.set SD_DAT1__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0\r
+.set SD_DAT1__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1\r
+.set SD_DAT1__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT\r
+.set SD_DAT1__PS, CYREG_PRT3_PS\r
+.set SD_DAT1__SHIFT, 0\r
+.set SD_DAT1__SLW, CYREG_PRT3_SLW\r
+\r
+/* SD_DAT2 */\r
+.set SD_DAT2__0__INTTYPE, CYREG_PICU3_INTTYPE5\r
+.set SD_DAT2__0__MASK, 0x20\r
+.set SD_DAT2__0__PC, CYREG_PRT3_PC5\r
+.set SD_DAT2__0__PORT, 3\r
+.set SD_DAT2__0__SHIFT, 5\r
+.set SD_DAT2__AG, CYREG_PRT3_AG\r
+.set SD_DAT2__AMUX, CYREG_PRT3_AMUX\r
+.set SD_DAT2__BIE, CYREG_PRT3_BIE\r
+.set SD_DAT2__BIT_MASK, CYREG_PRT3_BIT_MASK\r
+.set SD_DAT2__BYP, CYREG_PRT3_BYP\r
+.set SD_DAT2__CTL, CYREG_PRT3_CTL\r
+.set SD_DAT2__DM0, CYREG_PRT3_DM0\r
+.set SD_DAT2__DM1, CYREG_PRT3_DM1\r
+.set SD_DAT2__DM2, CYREG_PRT3_DM2\r
+.set SD_DAT2__DR, CYREG_PRT3_DR\r
+.set SD_DAT2__INP_DIS, CYREG_PRT3_INP_DIS\r
+.set SD_DAT2__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU3_BASE\r
+.set SD_DAT2__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG\r
+.set SD_DAT2__LCD_EN, CYREG_PRT3_LCD_EN\r
+.set SD_DAT2__MASK, 0x20\r
+.set SD_DAT2__PORT, 3\r
+.set SD_DAT2__PRT, CYREG_PRT3_PRT\r
+.set SD_DAT2__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL\r
+.set SD_DAT2__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN\r
+.set SD_DAT2__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0\r
+.set SD_DAT2__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1\r
+.set SD_DAT2__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0\r
+.set SD_DAT2__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1\r
+.set SD_DAT2__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT\r
+.set SD_DAT2__PS, CYREG_PRT3_PS\r
+.set SD_DAT2__SHIFT, 5\r
+.set SD_DAT2__SLW, CYREG_PRT3_SLW\r
+\r
+/* SD_MISO */\r
+.set SD_MISO__0__INTTYPE, CYREG_PICU3_INTTYPE1\r
+.set SD_MISO__0__MASK, 0x02\r
+.set SD_MISO__0__PC, CYREG_PRT3_PC1\r
+.set SD_MISO__0__PORT, 3\r
+.set SD_MISO__0__SHIFT, 1\r
+.set SD_MISO__AG, CYREG_PRT3_AG\r
+.set SD_MISO__AMUX, CYREG_PRT3_AMUX\r
+.set SD_MISO__BIE, CYREG_PRT3_BIE\r
+.set SD_MISO__BIT_MASK, CYREG_PRT3_BIT_MASK\r
+.set SD_MISO__BYP, CYREG_PRT3_BYP\r
+.set SD_MISO__CTL, CYREG_PRT3_CTL\r
+.set SD_MISO__DM0, CYREG_PRT3_DM0\r
+.set SD_MISO__DM1, CYREG_PRT3_DM1\r
+.set SD_MISO__DM2, CYREG_PRT3_DM2\r
+.set SD_MISO__DR, CYREG_PRT3_DR\r
+.set SD_MISO__INP_DIS, CYREG_PRT3_INP_DIS\r
+.set SD_MISO__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU3_BASE\r
+.set SD_MISO__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG\r
+.set SD_MISO__LCD_EN, CYREG_PRT3_LCD_EN\r
+.set SD_MISO__MASK, 0x02\r
+.set SD_MISO__PORT, 3\r
+.set SD_MISO__PRT, CYREG_PRT3_PRT\r
+.set SD_MISO__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL\r
+.set SD_MISO__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN\r
+.set SD_MISO__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0\r
+.set SD_MISO__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1\r
+.set SD_MISO__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0\r
+.set SD_MISO__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1\r
+.set SD_MISO__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT\r
+.set SD_MISO__PS, CYREG_PRT3_PS\r
+.set SD_MISO__SHIFT, 1\r
+.set SD_MISO__SLW, CYREG_PRT3_SLW\r
+\r
+/* SD_MOSI */\r
+.set SD_MOSI__0__INTTYPE, CYREG_PICU3_INTTYPE3\r
+.set SD_MOSI__0__MASK, 0x08\r
+.set SD_MOSI__0__PC, CYREG_PRT3_PC3\r
+.set SD_MOSI__0__PORT, 3\r
+.set SD_MOSI__0__SHIFT, 3\r
+.set SD_MOSI__AG, CYREG_PRT3_AG\r
+.set SD_MOSI__AMUX, CYREG_PRT3_AMUX\r
+.set SD_MOSI__BIE, CYREG_PRT3_BIE\r
+.set SD_MOSI__BIT_MASK, CYREG_PRT3_BIT_MASK\r
+.set SD_MOSI__BYP, CYREG_PRT3_BYP\r
+.set SD_MOSI__CTL, CYREG_PRT3_CTL\r
+.set SD_MOSI__DM0, CYREG_PRT3_DM0\r
+.set SD_MOSI__DM1, CYREG_PRT3_DM1\r
+.set SD_MOSI__DM2, CYREG_PRT3_DM2\r
+.set SD_MOSI__DR, CYREG_PRT3_DR\r
+.set SD_MOSI__INP_DIS, CYREG_PRT3_INP_DIS\r
+.set SD_MOSI__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU3_BASE\r
+.set SD_MOSI__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG\r
+.set SD_MOSI__LCD_EN, CYREG_PRT3_LCD_EN\r
+.set SD_MOSI__MASK, 0x08\r
+.set SD_MOSI__PORT, 3\r
+.set SD_MOSI__PRT, CYREG_PRT3_PRT\r
+.set SD_MOSI__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL\r
+.set SD_MOSI__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN\r
+.set SD_MOSI__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0\r
+.set SD_MOSI__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1\r
+.set SD_MOSI__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0\r
+.set SD_MOSI__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1\r
+.set SD_MOSI__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT\r
+.set SD_MOSI__PS, CYREG_PRT3_PS\r
+.set SD_MOSI__SHIFT, 3\r
+.set SD_MOSI__SLW, CYREG_PRT3_SLW\r
+\r
+/* SCSI_CLK */\r
+.set SCSI_CLK__CFG0, CYREG_CLKDIST_DCFG1_CFG0\r
+.set SCSI_CLK__CFG1, CYREG_CLKDIST_DCFG1_CFG1\r
+.set SCSI_CLK__CFG2, CYREG_CLKDIST_DCFG1_CFG2\r
+.set SCSI_CLK__CFG2_SRC_SEL_MASK, 0x07\r
+.set SCSI_CLK__INDEX, 0x01\r
+.set SCSI_CLK__PM_ACT_CFG, CYREG_PM_ACT_CFG2\r
+.set SCSI_CLK__PM_ACT_MSK, 0x02\r
+.set SCSI_CLK__PM_STBY_CFG, CYREG_PM_STBY_CFG2\r
+.set SCSI_CLK__PM_STBY_MSK, 0x02\r
+\r
+/* SCSI_Out */\r
+.set SCSI_Out__0__AG, CYREG_PRT4_AG\r
+.set SCSI_Out__0__AMUX, CYREG_PRT4_AMUX\r
+.set SCSI_Out__0__BIE, CYREG_PRT4_BIE\r
+.set SCSI_Out__0__BIT_MASK, CYREG_PRT4_BIT_MASK\r
+.set SCSI_Out__0__BYP, CYREG_PRT4_BYP\r
+.set SCSI_Out__0__CTL, CYREG_PRT4_CTL\r
+.set SCSI_Out__0__DM0, CYREG_PRT4_DM0\r
+.set SCSI_Out__0__DM1, CYREG_PRT4_DM1\r
+.set SCSI_Out__0__DM2, CYREG_PRT4_DM2\r
+.set SCSI_Out__0__DR, CYREG_PRT4_DR\r
+.set SCSI_Out__0__INP_DIS, CYREG_PRT4_INP_DIS\r
+.set SCSI_Out__0__INTTYPE, CYREG_PICU4_INTTYPE3\r
+.set SCSI_Out__0__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG\r
+.set SCSI_Out__0__LCD_EN, CYREG_PRT4_LCD_EN\r
+.set SCSI_Out__0__MASK, 0x08\r
+.set SCSI_Out__0__PC, CYREG_PRT4_PC3\r
+.set SCSI_Out__0__PORT, 4\r
+.set SCSI_Out__0__PRT, CYREG_PRT4_PRT\r
+.set SCSI_Out__0__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL\r
+.set SCSI_Out__0__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN\r
+.set SCSI_Out__0__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0\r
+.set SCSI_Out__0__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1\r
+.set SCSI_Out__0__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0\r
+.set SCSI_Out__0__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1\r
+.set SCSI_Out__0__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT\r
+.set SCSI_Out__0__PS, CYREG_PRT4_PS\r
+.set SCSI_Out__0__SHIFT, 3\r
+.set SCSI_Out__0__SLW, CYREG_PRT4_SLW\r
+.set SCSI_Out__1__AG, CYREG_PRT4_AG\r
+.set SCSI_Out__1__AMUX, CYREG_PRT4_AMUX\r
+.set SCSI_Out__1__BIE, CYREG_PRT4_BIE\r
+.set SCSI_Out__1__BIT_MASK, CYREG_PRT4_BIT_MASK\r
+.set SCSI_Out__1__BYP, CYREG_PRT4_BYP\r
+.set SCSI_Out__1__CTL, CYREG_PRT4_CTL\r
+.set SCSI_Out__1__DM0, CYREG_PRT4_DM0\r
+.set SCSI_Out__1__DM1, CYREG_PRT4_DM1\r
+.set SCSI_Out__1__DM2, CYREG_PRT4_DM2\r
+.set SCSI_Out__1__DR, CYREG_PRT4_DR\r
+.set SCSI_Out__1__INP_DIS, CYREG_PRT4_INP_DIS\r
+.set SCSI_Out__1__INTTYPE, CYREG_PICU4_INTTYPE2\r
+.set SCSI_Out__1__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG\r
+.set SCSI_Out__1__LCD_EN, CYREG_PRT4_LCD_EN\r
+.set SCSI_Out__1__MASK, 0x04\r
+.set SCSI_Out__1__PC, CYREG_PRT4_PC2\r
+.set SCSI_Out__1__PORT, 4\r
+.set SCSI_Out__1__PRT, CYREG_PRT4_PRT\r
+.set SCSI_Out__1__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL\r
+.set SCSI_Out__1__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN\r
+.set SCSI_Out__1__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0\r
+.set SCSI_Out__1__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1\r
+.set SCSI_Out__1__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0\r
+.set SCSI_Out__1__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1\r
+.set SCSI_Out__1__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT\r
+.set SCSI_Out__1__PS, CYREG_PRT4_PS\r
+.set SCSI_Out__1__SHIFT, 2\r
+.set SCSI_Out__1__SLW, CYREG_PRT4_SLW\r
+.set SCSI_Out__2__AG, CYREG_PRT0_AG\r
+.set SCSI_Out__2__AMUX, CYREG_PRT0_AMUX\r
+.set SCSI_Out__2__BIE, CYREG_PRT0_BIE\r
+.set SCSI_Out__2__BIT_MASK, CYREG_PRT0_BIT_MASK\r
+.set SCSI_Out__2__BYP, CYREG_PRT0_BYP\r
+.set SCSI_Out__2__CTL, CYREG_PRT0_CTL\r
+.set SCSI_Out__2__DM0, CYREG_PRT0_DM0\r
+.set SCSI_Out__2__DM1, CYREG_PRT0_DM1\r
+.set SCSI_Out__2__DM2, CYREG_PRT0_DM2\r
+.set SCSI_Out__2__DR, CYREG_PRT0_DR\r
+.set SCSI_Out__2__INP_DIS, CYREG_PRT0_INP_DIS\r
+.set SCSI_Out__2__INTTYPE, CYREG_PICU0_INTTYPE7\r
+.set SCSI_Out__2__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG\r
+.set SCSI_Out__2__LCD_EN, CYREG_PRT0_LCD_EN\r
+.set SCSI_Out__2__MASK, 0x80\r
+.set SCSI_Out__2__PC, CYREG_PRT0_PC7\r
+.set SCSI_Out__2__PORT, 0\r
+.set SCSI_Out__2__PRT, CYREG_PRT0_PRT\r
+.set SCSI_Out__2__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL\r
+.set SCSI_Out__2__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN\r
+.set SCSI_Out__2__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0\r
+.set SCSI_Out__2__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1\r
+.set SCSI_Out__2__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0\r
+.set SCSI_Out__2__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1\r
+.set SCSI_Out__2__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT\r
+.set SCSI_Out__2__PS, CYREG_PRT0_PS\r
+.set SCSI_Out__2__SHIFT, 7\r
+.set SCSI_Out__2__SLW, CYREG_PRT0_SLW\r
+.set SCSI_Out__3__AG, CYREG_PRT0_AG\r
+.set SCSI_Out__3__AMUX, CYREG_PRT0_AMUX\r
+.set SCSI_Out__3__BIE, CYREG_PRT0_BIE\r
+.set SCSI_Out__3__BIT_MASK, CYREG_PRT0_BIT_MASK\r
+.set SCSI_Out__3__BYP, CYREG_PRT0_BYP\r
+.set SCSI_Out__3__CTL, CYREG_PRT0_CTL\r
+.set SCSI_Out__3__DM0, CYREG_PRT0_DM0\r
+.set SCSI_Out__3__DM1, CYREG_PRT0_DM1\r
+.set SCSI_Out__3__DM2, CYREG_PRT0_DM2\r
+.set SCSI_Out__3__DR, CYREG_PRT0_DR\r
+.set SCSI_Out__3__INP_DIS, CYREG_PRT0_INP_DIS\r
+.set SCSI_Out__3__INTTYPE, CYREG_PICU0_INTTYPE6\r
+.set SCSI_Out__3__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG\r
+.set SCSI_Out__3__LCD_EN, CYREG_PRT0_LCD_EN\r
+.set SCSI_Out__3__MASK, 0x40\r
+.set SCSI_Out__3__PC, CYREG_PRT0_PC6\r
+.set SCSI_Out__3__PORT, 0\r
+.set SCSI_Out__3__PRT, CYREG_PRT0_PRT\r
+.set SCSI_Out__3__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL\r
+.set SCSI_Out__3__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN\r
+.set SCSI_Out__3__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0\r
+.set SCSI_Out__3__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1\r
+.set SCSI_Out__3__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0\r
+.set SCSI_Out__3__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1\r
+.set SCSI_Out__3__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT\r
+.set SCSI_Out__3__PS, CYREG_PRT0_PS\r
+.set SCSI_Out__3__SHIFT, 6\r
+.set SCSI_Out__3__SLW, CYREG_PRT0_SLW\r
+.set SCSI_Out__4__AG, CYREG_PRT0_AG\r
+.set SCSI_Out__4__AMUX, CYREG_PRT0_AMUX\r
+.set SCSI_Out__4__BIE, CYREG_PRT0_BIE\r
+.set SCSI_Out__4__BIT_MASK, CYREG_PRT0_BIT_MASK\r
+.set SCSI_Out__4__BYP, CYREG_PRT0_BYP\r
+.set SCSI_Out__4__CTL, CYREG_PRT0_CTL\r
+.set SCSI_Out__4__DM0, CYREG_PRT0_DM0\r
+.set SCSI_Out__4__DM1, CYREG_PRT0_DM1\r
+.set SCSI_Out__4__DM2, CYREG_PRT0_DM2\r
+.set SCSI_Out__4__DR, CYREG_PRT0_DR\r
+.set SCSI_Out__4__INP_DIS, CYREG_PRT0_INP_DIS\r
+.set SCSI_Out__4__INTTYPE, CYREG_PICU0_INTTYPE5\r
+.set SCSI_Out__4__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG\r
+.set SCSI_Out__4__LCD_EN, CYREG_PRT0_LCD_EN\r
+.set SCSI_Out__4__MASK, 0x20\r
+.set SCSI_Out__4__PC, CYREG_PRT0_PC5\r
+.set SCSI_Out__4__PORT, 0\r
+.set SCSI_Out__4__PRT, CYREG_PRT0_PRT\r
+.set SCSI_Out__4__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL\r
+.set SCSI_Out__4__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN\r
+.set SCSI_Out__4__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0\r
+.set SCSI_Out__4__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1\r
+.set SCSI_Out__4__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0\r
+.set SCSI_Out__4__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1\r
+.set SCSI_Out__4__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT\r
+.set SCSI_Out__4__PS, CYREG_PRT0_PS\r
+.set SCSI_Out__4__SHIFT, 5\r
+.set SCSI_Out__4__SLW, CYREG_PRT0_SLW\r
+.set SCSI_Out__5__AG, CYREG_PRT0_AG\r
+.set SCSI_Out__5__AMUX, CYREG_PRT0_AMUX\r
+.set SCSI_Out__5__BIE, CYREG_PRT0_BIE\r
+.set SCSI_Out__5__BIT_MASK, CYREG_PRT0_BIT_MASK\r
+.set SCSI_Out__5__BYP, CYREG_PRT0_BYP\r
+.set SCSI_Out__5__CTL, CYREG_PRT0_CTL\r
+.set SCSI_Out__5__DM0, CYREG_PRT0_DM0\r
+.set SCSI_Out__5__DM1, CYREG_PRT0_DM1\r
+.set SCSI_Out__5__DM2, CYREG_PRT0_DM2\r
+.set SCSI_Out__5__DR, CYREG_PRT0_DR\r
+.set SCSI_Out__5__INP_DIS, CYREG_PRT0_INP_DIS\r
+.set SCSI_Out__5__INTTYPE, CYREG_PICU0_INTTYPE4\r
+.set SCSI_Out__5__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG\r
+.set SCSI_Out__5__LCD_EN, CYREG_PRT0_LCD_EN\r
+.set SCSI_Out__5__MASK, 0x10\r
+.set SCSI_Out__5__PC, CYREG_PRT0_PC4\r
+.set SCSI_Out__5__PORT, 0\r
+.set SCSI_Out__5__PRT, CYREG_PRT0_PRT\r
+.set SCSI_Out__5__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL\r
+.set SCSI_Out__5__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN\r
+.set SCSI_Out__5__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0\r
+.set SCSI_Out__5__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1\r
+.set SCSI_Out__5__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0\r
+.set SCSI_Out__5__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1\r
+.set SCSI_Out__5__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT\r
+.set SCSI_Out__5__PS, CYREG_PRT0_PS\r
+.set SCSI_Out__5__SHIFT, 4\r
+.set SCSI_Out__5__SLW, CYREG_PRT0_SLW\r
+.set SCSI_Out__6__AG, CYREG_PRT0_AG\r
+.set SCSI_Out__6__AMUX, CYREG_PRT0_AMUX\r
+.set SCSI_Out__6__BIE, CYREG_PRT0_BIE\r
+.set SCSI_Out__6__BIT_MASK, CYREG_PRT0_BIT_MASK\r
+.set SCSI_Out__6__BYP, CYREG_PRT0_BYP\r
+.set SCSI_Out__6__CTL, CYREG_PRT0_CTL\r
+.set SCSI_Out__6__DM0, CYREG_PRT0_DM0\r
+.set SCSI_Out__6__DM1, CYREG_PRT0_DM1\r
+.set SCSI_Out__6__DM2, CYREG_PRT0_DM2\r
+.set SCSI_Out__6__DR, CYREG_PRT0_DR\r
+.set SCSI_Out__6__INP_DIS, CYREG_PRT0_INP_DIS\r
+.set SCSI_Out__6__INTTYPE, CYREG_PICU0_INTTYPE3\r
+.set SCSI_Out__6__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG\r
+.set SCSI_Out__6__LCD_EN, CYREG_PRT0_LCD_EN\r
+.set SCSI_Out__6__MASK, 0x08\r
+.set SCSI_Out__6__PC, CYREG_PRT0_PC3\r
+.set SCSI_Out__6__PORT, 0\r
+.set SCSI_Out__6__PRT, CYREG_PRT0_PRT\r
+.set SCSI_Out__6__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL\r
+.set SCSI_Out__6__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN\r
+.set SCSI_Out__6__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0\r
+.set SCSI_Out__6__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1\r
+.set SCSI_Out__6__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0\r
+.set SCSI_Out__6__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1\r
+.set SCSI_Out__6__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT\r
+.set SCSI_Out__6__PS, CYREG_PRT0_PS\r
+.set SCSI_Out__6__SHIFT, 3\r
+.set SCSI_Out__6__SLW, CYREG_PRT0_SLW\r
+.set SCSI_Out__7__AG, CYREG_PRT0_AG\r
+.set SCSI_Out__7__AMUX, CYREG_PRT0_AMUX\r
+.set SCSI_Out__7__BIE, CYREG_PRT0_BIE\r
+.set SCSI_Out__7__BIT_MASK, CYREG_PRT0_BIT_MASK\r
+.set SCSI_Out__7__BYP, CYREG_PRT0_BYP\r
+.set SCSI_Out__7__CTL, CYREG_PRT0_CTL\r
+.set SCSI_Out__7__DM0, CYREG_PRT0_DM0\r
+.set SCSI_Out__7__DM1, CYREG_PRT0_DM1\r
+.set SCSI_Out__7__DM2, CYREG_PRT0_DM2\r
+.set SCSI_Out__7__DR, CYREG_PRT0_DR\r
+.set SCSI_Out__7__INP_DIS, CYREG_PRT0_INP_DIS\r
+.set SCSI_Out__7__INTTYPE, CYREG_PICU0_INTTYPE2\r
+.set SCSI_Out__7__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG\r
+.set SCSI_Out__7__LCD_EN, CYREG_PRT0_LCD_EN\r
+.set SCSI_Out__7__MASK, 0x04\r
+.set SCSI_Out__7__PC, CYREG_PRT0_PC2\r
+.set SCSI_Out__7__PORT, 0\r
+.set SCSI_Out__7__PRT, CYREG_PRT0_PRT\r
+.set SCSI_Out__7__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL\r
+.set SCSI_Out__7__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN\r
+.set SCSI_Out__7__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0\r
+.set SCSI_Out__7__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1\r
+.set SCSI_Out__7__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0\r
+.set SCSI_Out__7__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1\r
+.set SCSI_Out__7__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT\r
+.set SCSI_Out__7__PS, CYREG_PRT0_PS\r
+.set SCSI_Out__7__SHIFT, 2\r
+.set SCSI_Out__7__SLW, CYREG_PRT0_SLW\r
+.set SCSI_Out__8__AG, CYREG_PRT0_AG\r
+.set SCSI_Out__8__AMUX, CYREG_PRT0_AMUX\r
+.set SCSI_Out__8__BIE, CYREG_PRT0_BIE\r
+.set SCSI_Out__8__BIT_MASK, CYREG_PRT0_BIT_MASK\r
+.set SCSI_Out__8__BYP, CYREG_PRT0_BYP\r
+.set SCSI_Out__8__CTL, CYREG_PRT0_CTL\r
+.set SCSI_Out__8__DM0, CYREG_PRT0_DM0\r
+.set SCSI_Out__8__DM1, CYREG_PRT0_DM1\r
+.set SCSI_Out__8__DM2, CYREG_PRT0_DM2\r
+.set SCSI_Out__8__DR, CYREG_PRT0_DR\r
+.set SCSI_Out__8__INP_DIS, CYREG_PRT0_INP_DIS\r
+.set SCSI_Out__8__INTTYPE, CYREG_PICU0_INTTYPE1\r
+.set SCSI_Out__8__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG\r
+.set SCSI_Out__8__LCD_EN, CYREG_PRT0_LCD_EN\r
+.set SCSI_Out__8__MASK, 0x02\r
+.set SCSI_Out__8__PC, CYREG_PRT0_PC1\r
+.set SCSI_Out__8__PORT, 0\r
+.set SCSI_Out__8__PRT, CYREG_PRT0_PRT\r
+.set SCSI_Out__8__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL\r
+.set SCSI_Out__8__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN\r
+.set SCSI_Out__8__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0\r
+.set SCSI_Out__8__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1\r
+.set SCSI_Out__8__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0\r
+.set SCSI_Out__8__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1\r
+.set SCSI_Out__8__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT\r
+.set SCSI_Out__8__PS, CYREG_PRT0_PS\r
+.set SCSI_Out__8__SHIFT, 1\r
+.set SCSI_Out__8__SLW, CYREG_PRT0_SLW\r
+.set SCSI_Out__9__AG, CYREG_PRT0_AG\r
+.set SCSI_Out__9__AMUX, CYREG_PRT0_AMUX\r
+.set SCSI_Out__9__BIE, CYREG_PRT0_BIE\r
+.set SCSI_Out__9__BIT_MASK, CYREG_PRT0_BIT_MASK\r
+.set SCSI_Out__9__BYP, CYREG_PRT0_BYP\r
+.set SCSI_Out__9__CTL, CYREG_PRT0_CTL\r
+.set SCSI_Out__9__DM0, CYREG_PRT0_DM0\r
+.set SCSI_Out__9__DM1, CYREG_PRT0_DM1\r
+.set SCSI_Out__9__DM2, CYREG_PRT0_DM2\r
+.set SCSI_Out__9__DR, CYREG_PRT0_DR\r
+.set SCSI_Out__9__INP_DIS, CYREG_PRT0_INP_DIS\r
+.set SCSI_Out__9__INTTYPE, CYREG_PICU0_INTTYPE0\r
+.set SCSI_Out__9__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG\r
+.set SCSI_Out__9__LCD_EN, CYREG_PRT0_LCD_EN\r
+.set SCSI_Out__9__MASK, 0x01\r
+.set SCSI_Out__9__PC, CYREG_PRT0_PC0\r
+.set SCSI_Out__9__PORT, 0\r
+.set SCSI_Out__9__PRT, CYREG_PRT0_PRT\r
+.set SCSI_Out__9__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL\r
+.set SCSI_Out__9__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN\r
+.set SCSI_Out__9__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0\r
+.set SCSI_Out__9__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1\r
+.set SCSI_Out__9__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0\r
+.set SCSI_Out__9__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1\r
+.set SCSI_Out__9__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT\r
+.set SCSI_Out__9__PS, CYREG_PRT0_PS\r
+.set SCSI_Out__9__SHIFT, 0\r
+.set SCSI_Out__9__SLW, CYREG_PRT0_SLW\r
+.set SCSI_Out__ACK__AG, CYREG_PRT0_AG\r
+.set SCSI_Out__ACK__AMUX, CYREG_PRT0_AMUX\r
+.set SCSI_Out__ACK__BIE, CYREG_PRT0_BIE\r
+.set SCSI_Out__ACK__BIT_MASK, CYREG_PRT0_BIT_MASK\r
+.set SCSI_Out__ACK__BYP, CYREG_PRT0_BYP\r
+.set SCSI_Out__ACK__CTL, CYREG_PRT0_CTL\r
+.set SCSI_Out__ACK__DM0, CYREG_PRT0_DM0\r
+.set SCSI_Out__ACK__DM1, CYREG_PRT0_DM1\r
+.set SCSI_Out__ACK__DM2, CYREG_PRT0_DM2\r
+.set SCSI_Out__ACK__DR, CYREG_PRT0_DR\r
+.set SCSI_Out__ACK__INP_DIS, CYREG_PRT0_INP_DIS\r
+.set SCSI_Out__ACK__INTTYPE, CYREG_PICU0_INTTYPE6\r
+.set SCSI_Out__ACK__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG\r
+.set SCSI_Out__ACK__LCD_EN, CYREG_PRT0_LCD_EN\r
+.set SCSI_Out__ACK__MASK, 0x40\r
+.set SCSI_Out__ACK__PC, CYREG_PRT0_PC6\r
+.set SCSI_Out__ACK__PORT, 0\r
+.set SCSI_Out__ACK__PRT, CYREG_PRT0_PRT\r
+.set SCSI_Out__ACK__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL\r
+.set SCSI_Out__ACK__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN\r
+.set SCSI_Out__ACK__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0\r
+.set SCSI_Out__ACK__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1\r
+.set SCSI_Out__ACK__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0\r
+.set SCSI_Out__ACK__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1\r
+.set SCSI_Out__ACK__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT\r
+.set SCSI_Out__ACK__PS, CYREG_PRT0_PS\r
+.set SCSI_Out__ACK__SHIFT, 6\r
+.set SCSI_Out__ACK__SLW, CYREG_PRT0_SLW\r
+.set SCSI_Out__ATN__AG, CYREG_PRT4_AG\r
+.set SCSI_Out__ATN__AMUX, CYREG_PRT4_AMUX\r
+.set SCSI_Out__ATN__BIE, CYREG_PRT4_BIE\r
+.set SCSI_Out__ATN__BIT_MASK, CYREG_PRT4_BIT_MASK\r
+.set SCSI_Out__ATN__BYP, CYREG_PRT4_BYP\r
+.set SCSI_Out__ATN__CTL, CYREG_PRT4_CTL\r
+.set SCSI_Out__ATN__DM0, CYREG_PRT4_DM0\r
+.set SCSI_Out__ATN__DM1, CYREG_PRT4_DM1\r
+.set SCSI_Out__ATN__DM2, CYREG_PRT4_DM2\r
+.set SCSI_Out__ATN__DR, CYREG_PRT4_DR\r
+.set SCSI_Out__ATN__INP_DIS, CYREG_PRT4_INP_DIS\r
+.set SCSI_Out__ATN__INTTYPE, CYREG_PICU4_INTTYPE2\r
+.set SCSI_Out__ATN__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG\r
+.set SCSI_Out__ATN__LCD_EN, CYREG_PRT4_LCD_EN\r
+.set SCSI_Out__ATN__MASK, 0x04\r
+.set SCSI_Out__ATN__PC, CYREG_PRT4_PC2\r
+.set SCSI_Out__ATN__PORT, 4\r
+.set SCSI_Out__ATN__PRT, CYREG_PRT4_PRT\r
+.set SCSI_Out__ATN__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL\r
+.set SCSI_Out__ATN__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN\r
+.set SCSI_Out__ATN__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0\r
+.set SCSI_Out__ATN__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1\r
+.set SCSI_Out__ATN__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0\r
+.set SCSI_Out__ATN__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1\r
+.set SCSI_Out__ATN__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT\r
+.set SCSI_Out__ATN__PS, CYREG_PRT4_PS\r
+.set SCSI_Out__ATN__SHIFT, 2\r
+.set SCSI_Out__ATN__SLW, CYREG_PRT4_SLW\r
+.set SCSI_Out__BSY__AG, CYREG_PRT0_AG\r
+.set SCSI_Out__BSY__AMUX, CYREG_PRT0_AMUX\r
+.set SCSI_Out__BSY__BIE, CYREG_PRT0_BIE\r
+.set SCSI_Out__BSY__BIT_MASK, CYREG_PRT0_BIT_MASK\r
+.set SCSI_Out__BSY__BYP, CYREG_PRT0_BYP\r
+.set SCSI_Out__BSY__CTL, CYREG_PRT0_CTL\r
+.set SCSI_Out__BSY__DM0, CYREG_PRT0_DM0\r
+.set SCSI_Out__BSY__DM1, CYREG_PRT0_DM1\r
+.set SCSI_Out__BSY__DM2, CYREG_PRT0_DM2\r
+.set SCSI_Out__BSY__DR, CYREG_PRT0_DR\r
+.set SCSI_Out__BSY__INP_DIS, CYREG_PRT0_INP_DIS\r
+.set SCSI_Out__BSY__INTTYPE, CYREG_PICU0_INTTYPE7\r
+.set SCSI_Out__BSY__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG\r
+.set SCSI_Out__BSY__LCD_EN, CYREG_PRT0_LCD_EN\r
+.set SCSI_Out__BSY__MASK, 0x80\r
+.set SCSI_Out__BSY__PC, CYREG_PRT0_PC7\r
+.set SCSI_Out__BSY__PORT, 0\r
+.set SCSI_Out__BSY__PRT, CYREG_PRT0_PRT\r
+.set SCSI_Out__BSY__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL\r
+.set SCSI_Out__BSY__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN\r
+.set SCSI_Out__BSY__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0\r
+.set SCSI_Out__BSY__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1\r
+.set SCSI_Out__BSY__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0\r
+.set SCSI_Out__BSY__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1\r
+.set SCSI_Out__BSY__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT\r
+.set SCSI_Out__BSY__PS, CYREG_PRT0_PS\r
+.set SCSI_Out__BSY__SHIFT, 7\r
+.set SCSI_Out__BSY__SLW, CYREG_PRT0_SLW\r
+.set SCSI_Out__CD_raw__AG, CYREG_PRT0_AG\r
+.set SCSI_Out__CD_raw__AMUX, CYREG_PRT0_AMUX\r
+.set SCSI_Out__CD_raw__BIE, CYREG_PRT0_BIE\r
+.set SCSI_Out__CD_raw__BIT_MASK, CYREG_PRT0_BIT_MASK\r
+.set SCSI_Out__CD_raw__BYP, CYREG_PRT0_BYP\r
+.set SCSI_Out__CD_raw__CTL, CYREG_PRT0_CTL\r
+.set SCSI_Out__CD_raw__DM0, CYREG_PRT0_DM0\r
+.set SCSI_Out__CD_raw__DM1, CYREG_PRT0_DM1\r
+.set SCSI_Out__CD_raw__DM2, CYREG_PRT0_DM2\r
+.set SCSI_Out__CD_raw__DR, CYREG_PRT0_DR\r
+.set SCSI_Out__CD_raw__INP_DIS, CYREG_PRT0_INP_DIS\r
+.set SCSI_Out__CD_raw__INTTYPE, CYREG_PICU0_INTTYPE2\r
+.set SCSI_Out__CD_raw__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG\r
+.set SCSI_Out__CD_raw__LCD_EN, CYREG_PRT0_LCD_EN\r
+.set SCSI_Out__CD_raw__MASK, 0x04\r
+.set SCSI_Out__CD_raw__PC, CYREG_PRT0_PC2\r
+.set SCSI_Out__CD_raw__PORT, 0\r
+.set SCSI_Out__CD_raw__PRT, CYREG_PRT0_PRT\r
+.set SCSI_Out__CD_raw__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL\r
+.set SCSI_Out__CD_raw__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN\r
+.set SCSI_Out__CD_raw__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0\r
+.set SCSI_Out__CD_raw__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1\r
+.set SCSI_Out__CD_raw__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0\r
+.set SCSI_Out__CD_raw__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1\r
+.set SCSI_Out__CD_raw__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT\r
+.set SCSI_Out__CD_raw__PS, CYREG_PRT0_PS\r
+.set SCSI_Out__CD_raw__SHIFT, 2\r
+.set SCSI_Out__CD_raw__SLW, CYREG_PRT0_SLW\r
+.set SCSI_Out__DBP_raw__AG, CYREG_PRT4_AG\r
+.set SCSI_Out__DBP_raw__AMUX, CYREG_PRT4_AMUX\r
+.set SCSI_Out__DBP_raw__BIE, CYREG_PRT4_BIE\r
+.set SCSI_Out__DBP_raw__BIT_MASK, CYREG_PRT4_BIT_MASK\r
+.set SCSI_Out__DBP_raw__BYP, CYREG_PRT4_BYP\r
+.set SCSI_Out__DBP_raw__CTL, CYREG_PRT4_CTL\r
+.set SCSI_Out__DBP_raw__DM0, CYREG_PRT4_DM0\r
+.set SCSI_Out__DBP_raw__DM1, CYREG_PRT4_DM1\r
+.set SCSI_Out__DBP_raw__DM2, CYREG_PRT4_DM2\r
+.set SCSI_Out__DBP_raw__DR, CYREG_PRT4_DR\r
+.set SCSI_Out__DBP_raw__INP_DIS, CYREG_PRT4_INP_DIS\r
+.set SCSI_Out__DBP_raw__INTTYPE, CYREG_PICU4_INTTYPE3\r
+.set SCSI_Out__DBP_raw__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG\r
+.set SCSI_Out__DBP_raw__LCD_EN, CYREG_PRT4_LCD_EN\r
+.set SCSI_Out__DBP_raw__MASK, 0x08\r
+.set SCSI_Out__DBP_raw__PC, CYREG_PRT4_PC3\r
+.set SCSI_Out__DBP_raw__PORT, 4\r
+.set SCSI_Out__DBP_raw__PRT, CYREG_PRT4_PRT\r
+.set SCSI_Out__DBP_raw__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL\r
+.set SCSI_Out__DBP_raw__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN\r
+.set SCSI_Out__DBP_raw__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0\r
+.set SCSI_Out__DBP_raw__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1\r
+.set SCSI_Out__DBP_raw__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0\r
+.set SCSI_Out__DBP_raw__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1\r
+.set SCSI_Out__DBP_raw__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT\r
+.set SCSI_Out__DBP_raw__PS, CYREG_PRT4_PS\r
+.set SCSI_Out__DBP_raw__SHIFT, 3\r
+.set SCSI_Out__DBP_raw__SLW, CYREG_PRT4_SLW\r
+.set SCSI_Out__IO_raw__AG, CYREG_PRT0_AG\r
+.set SCSI_Out__IO_raw__AMUX, CYREG_PRT0_AMUX\r
+.set SCSI_Out__IO_raw__BIE, CYREG_PRT0_BIE\r
+.set SCSI_Out__IO_raw__BIT_MASK, CYREG_PRT0_BIT_MASK\r
+.set SCSI_Out__IO_raw__BYP, CYREG_PRT0_BYP\r
+.set SCSI_Out__IO_raw__CTL, CYREG_PRT0_CTL\r
+.set SCSI_Out__IO_raw__DM0, CYREG_PRT0_DM0\r
+.set SCSI_Out__IO_raw__DM1, CYREG_PRT0_DM1\r
+.set SCSI_Out__IO_raw__DM2, CYREG_PRT0_DM2\r
+.set SCSI_Out__IO_raw__DR, CYREG_PRT0_DR\r
+.set SCSI_Out__IO_raw__INP_DIS, CYREG_PRT0_INP_DIS\r
+.set SCSI_Out__IO_raw__INTTYPE, CYREG_PICU0_INTTYPE0\r
+.set SCSI_Out__IO_raw__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG\r
+.set SCSI_Out__IO_raw__LCD_EN, CYREG_PRT0_LCD_EN\r
+.set SCSI_Out__IO_raw__MASK, 0x01\r
+.set SCSI_Out__IO_raw__PC, CYREG_PRT0_PC0\r
+.set SCSI_Out__IO_raw__PORT, 0\r
+.set SCSI_Out__IO_raw__PRT, CYREG_PRT0_PRT\r
+.set SCSI_Out__IO_raw__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL\r
+.set SCSI_Out__IO_raw__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN\r
+.set SCSI_Out__IO_raw__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0\r
+.set SCSI_Out__IO_raw__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1\r
+.set SCSI_Out__IO_raw__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0\r
+.set SCSI_Out__IO_raw__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1\r
+.set SCSI_Out__IO_raw__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT\r
+.set SCSI_Out__IO_raw__PS, CYREG_PRT0_PS\r
+.set SCSI_Out__IO_raw__SHIFT, 0\r
+.set SCSI_Out__IO_raw__SLW, CYREG_PRT0_SLW\r
+.set SCSI_Out__MSG_raw__AG, CYREG_PRT0_AG\r
+.set SCSI_Out__MSG_raw__AMUX, CYREG_PRT0_AMUX\r
+.set SCSI_Out__MSG_raw__BIE, CYREG_PRT0_BIE\r
+.set SCSI_Out__MSG_raw__BIT_MASK, CYREG_PRT0_BIT_MASK\r
+.set SCSI_Out__MSG_raw__BYP, CYREG_PRT0_BYP\r
+.set SCSI_Out__MSG_raw__CTL, CYREG_PRT0_CTL\r
+.set SCSI_Out__MSG_raw__DM0, CYREG_PRT0_DM0\r
+.set SCSI_Out__MSG_raw__DM1, CYREG_PRT0_DM1\r
+.set SCSI_Out__MSG_raw__DM2, CYREG_PRT0_DM2\r
+.set SCSI_Out__MSG_raw__DR, CYREG_PRT0_DR\r
+.set SCSI_Out__MSG_raw__INP_DIS, CYREG_PRT0_INP_DIS\r
+.set SCSI_Out__MSG_raw__INTTYPE, CYREG_PICU0_INTTYPE4\r
+.set SCSI_Out__MSG_raw__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG\r
+.set SCSI_Out__MSG_raw__LCD_EN, CYREG_PRT0_LCD_EN\r
+.set SCSI_Out__MSG_raw__MASK, 0x10\r
+.set SCSI_Out__MSG_raw__PC, CYREG_PRT0_PC4\r
+.set SCSI_Out__MSG_raw__PORT, 0\r
+.set SCSI_Out__MSG_raw__PRT, CYREG_PRT0_PRT\r
+.set SCSI_Out__MSG_raw__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL\r
+.set SCSI_Out__MSG_raw__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN\r
+.set SCSI_Out__MSG_raw__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0\r
+.set SCSI_Out__MSG_raw__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1\r
+.set SCSI_Out__MSG_raw__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0\r
+.set SCSI_Out__MSG_raw__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1\r
+.set SCSI_Out__MSG_raw__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT\r
+.set SCSI_Out__MSG_raw__PS, CYREG_PRT0_PS\r
+.set SCSI_Out__MSG_raw__SHIFT, 4\r
+.set SCSI_Out__MSG_raw__SLW, CYREG_PRT0_SLW\r
+.set SCSI_Out__REQ__AG, CYREG_PRT0_AG\r
+.set SCSI_Out__REQ__AMUX, CYREG_PRT0_AMUX\r
+.set SCSI_Out__REQ__BIE, CYREG_PRT0_BIE\r
+.set SCSI_Out__REQ__BIT_MASK, CYREG_PRT0_BIT_MASK\r
+.set SCSI_Out__REQ__BYP, CYREG_PRT0_BYP\r
+.set SCSI_Out__REQ__CTL, CYREG_PRT0_CTL\r
+.set SCSI_Out__REQ__DM0, CYREG_PRT0_DM0\r
+.set SCSI_Out__REQ__DM1, CYREG_PRT0_DM1\r
+.set SCSI_Out__REQ__DM2, CYREG_PRT0_DM2\r
+.set SCSI_Out__REQ__DR, CYREG_PRT0_DR\r
+.set SCSI_Out__REQ__INP_DIS, CYREG_PRT0_INP_DIS\r
+.set SCSI_Out__REQ__INTTYPE, CYREG_PICU0_INTTYPE1\r
+.set SCSI_Out__REQ__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG\r
+.set SCSI_Out__REQ__LCD_EN, CYREG_PRT0_LCD_EN\r
+.set SCSI_Out__REQ__MASK, 0x02\r
+.set SCSI_Out__REQ__PC, CYREG_PRT0_PC1\r
+.set SCSI_Out__REQ__PORT, 0\r
+.set SCSI_Out__REQ__PRT, CYREG_PRT0_PRT\r
+.set SCSI_Out__REQ__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL\r
+.set SCSI_Out__REQ__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN\r
+.set SCSI_Out__REQ__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0\r
+.set SCSI_Out__REQ__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1\r
+.set SCSI_Out__REQ__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0\r
+.set SCSI_Out__REQ__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1\r
+.set SCSI_Out__REQ__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT\r
+.set SCSI_Out__REQ__PS, CYREG_PRT0_PS\r
+.set SCSI_Out__REQ__SHIFT, 1\r
+.set SCSI_Out__REQ__SLW, CYREG_PRT0_SLW\r
+.set SCSI_Out__RST__AG, CYREG_PRT0_AG\r
+.set SCSI_Out__RST__AMUX, CYREG_PRT0_AMUX\r
+.set SCSI_Out__RST__BIE, CYREG_PRT0_BIE\r
+.set SCSI_Out__RST__BIT_MASK, CYREG_PRT0_BIT_MASK\r
+.set SCSI_Out__RST__BYP, CYREG_PRT0_BYP\r
+.set SCSI_Out__RST__CTL, CYREG_PRT0_CTL\r
+.set SCSI_Out__RST__DM0, CYREG_PRT0_DM0\r
+.set SCSI_Out__RST__DM1, CYREG_PRT0_DM1\r
+.set SCSI_Out__RST__DM2, CYREG_PRT0_DM2\r
+.set SCSI_Out__RST__DR, CYREG_PRT0_DR\r
+.set SCSI_Out__RST__INP_DIS, CYREG_PRT0_INP_DIS\r
+.set SCSI_Out__RST__INTTYPE, CYREG_PICU0_INTTYPE5\r
+.set SCSI_Out__RST__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG\r
+.set SCSI_Out__RST__LCD_EN, CYREG_PRT0_LCD_EN\r
+.set SCSI_Out__RST__MASK, 0x20\r
+.set SCSI_Out__RST__PC, CYREG_PRT0_PC5\r
+.set SCSI_Out__RST__PORT, 0\r
+.set SCSI_Out__RST__PRT, CYREG_PRT0_PRT\r
+.set SCSI_Out__RST__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL\r
+.set SCSI_Out__RST__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN\r
+.set SCSI_Out__RST__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0\r
+.set SCSI_Out__RST__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1\r
+.set SCSI_Out__RST__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0\r
+.set SCSI_Out__RST__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1\r
+.set SCSI_Out__RST__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT\r
+.set SCSI_Out__RST__PS, CYREG_PRT0_PS\r
+.set SCSI_Out__RST__SHIFT, 5\r
+.set SCSI_Out__RST__SLW, CYREG_PRT0_SLW\r
+.set SCSI_Out__SEL__AG, CYREG_PRT0_AG\r
+.set SCSI_Out__SEL__AMUX, CYREG_PRT0_AMUX\r
+.set SCSI_Out__SEL__BIE, CYREG_PRT0_BIE\r
+.set SCSI_Out__SEL__BIT_MASK, CYREG_PRT0_BIT_MASK\r
+.set SCSI_Out__SEL__BYP, CYREG_PRT0_BYP\r
+.set SCSI_Out__SEL__CTL, CYREG_PRT0_CTL\r
+.set SCSI_Out__SEL__DM0, CYREG_PRT0_DM0\r
+.set SCSI_Out__SEL__DM1, CYREG_PRT0_DM1\r
+.set SCSI_Out__SEL__DM2, CYREG_PRT0_DM2\r
+.set SCSI_Out__SEL__DR, CYREG_PRT0_DR\r
+.set SCSI_Out__SEL__INP_DIS, CYREG_PRT0_INP_DIS\r
+.set SCSI_Out__SEL__INTTYPE, CYREG_PICU0_INTTYPE3\r
+.set SCSI_Out__SEL__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG\r
+.set SCSI_Out__SEL__LCD_EN, CYREG_PRT0_LCD_EN\r
+.set SCSI_Out__SEL__MASK, 0x08\r
+.set SCSI_Out__SEL__PC, CYREG_PRT0_PC3\r
+.set SCSI_Out__SEL__PORT, 0\r
+.set SCSI_Out__SEL__PRT, CYREG_PRT0_PRT\r
+.set SCSI_Out__SEL__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL\r
+.set SCSI_Out__SEL__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN\r
+.set SCSI_Out__SEL__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0\r
+.set SCSI_Out__SEL__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1\r
+.set SCSI_Out__SEL__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0\r
+.set SCSI_Out__SEL__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1\r
+.set SCSI_Out__SEL__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT\r
+.set SCSI_Out__SEL__PS, CYREG_PRT0_PS\r
+.set SCSI_Out__SEL__SHIFT, 3\r
+.set SCSI_Out__SEL__SLW, CYREG_PRT0_SLW\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__0__MASK, 0x01\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__0__POS, 0\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__1__MASK, 0x02\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__1__POS, 1\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB08_09_ACTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB08_09_CTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB08_09_CTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB08_09_CTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB08_09_CTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B1_UDB08_09_MSK\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB08_09_MSK\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB08_09_MSK\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB08_09_MSK\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__2__MASK, 0x04\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__2__POS, 2\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__3__MASK, 0x08\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__3__POS, 3\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__4__MASK, 0x10\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__4__POS, 4\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__5__MASK, 0x20\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__5__POS, 5\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__6__MASK, 0x40\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__6__POS, 6\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__7__MASK, 0x80\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__7__POS, 7\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B1_UDB08_ACTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG, CYREG_B1_UDB08_CTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B1_UDB08_ST_CTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG, CYREG_B1_UDB08_CTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B1_UDB08_ST_CTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__MASK, 0xFF\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB08_MSK_ACTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB08_MSK_ACTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG, CYREG_B1_UDB08_MSK\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK, 0x01\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__0__POS, 0\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB08_09_ACTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB08_09_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB08_09_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB08_09_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB08_09_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB08_09_MSK\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB08_09_MSK\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB08_09_MSK\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB08_09_MSK\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB08_ACTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB08_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB08_ST_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB08_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB08_ST_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK, 0x01\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB08_MSK_ACTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB08_MSK_ACTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB08_MSK\r
+.set SCSI_Out_DBx__0__AG, CYREG_PRT6_AG\r
+.set SCSI_Out_DBx__0__AMUX, CYREG_PRT6_AMUX\r
+.set SCSI_Out_DBx__0__BIE, CYREG_PRT6_BIE\r
+.set SCSI_Out_DBx__0__BIT_MASK, CYREG_PRT6_BIT_MASK\r
+.set SCSI_Out_DBx__0__BYP, CYREG_PRT6_BYP\r
+.set SCSI_Out_DBx__0__CTL, CYREG_PRT6_CTL\r
+.set SCSI_Out_DBx__0__DM0, CYREG_PRT6_DM0\r
+.set SCSI_Out_DBx__0__DM1, CYREG_PRT6_DM1\r
+.set SCSI_Out_DBx__0__DM2, CYREG_PRT6_DM2\r
+.set SCSI_Out_DBx__0__DR, CYREG_PRT6_DR\r
+.set SCSI_Out_DBx__0__INP_DIS, CYREG_PRT6_INP_DIS\r
+.set SCSI_Out_DBx__0__INTTYPE, CYREG_PICU6_INTTYPE3\r
+.set SCSI_Out_DBx__0__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG\r
+.set SCSI_Out_DBx__0__LCD_EN, CYREG_PRT6_LCD_EN\r
+.set SCSI_Out_DBx__0__MASK, 0x08\r
+.set SCSI_Out_DBx__0__PC, CYREG_PRT6_PC3\r
+.set SCSI_Out_DBx__0__PORT, 6\r
+.set SCSI_Out_DBx__0__PRT, CYREG_PRT6_PRT\r
+.set SCSI_Out_DBx__0__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL\r
+.set SCSI_Out_DBx__0__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN\r
+.set SCSI_Out_DBx__0__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0\r
+.set SCSI_Out_DBx__0__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1\r
+.set SCSI_Out_DBx__0__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0\r
+.set SCSI_Out_DBx__0__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1\r
+.set SCSI_Out_DBx__0__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT\r
+.set SCSI_Out_DBx__0__PS, CYREG_PRT6_PS\r
+.set SCSI_Out_DBx__0__SHIFT, 3\r
+.set SCSI_Out_DBx__0__SLW, CYREG_PRT6_SLW\r
+.set SCSI_Out_DBx__1__AG, CYREG_PRT6_AG\r
+.set SCSI_Out_DBx__1__AMUX, CYREG_PRT6_AMUX\r
+.set SCSI_Out_DBx__1__BIE, CYREG_PRT6_BIE\r
+.set SCSI_Out_DBx__1__BIT_MASK, CYREG_PRT6_BIT_MASK\r
+.set SCSI_Out_DBx__1__BYP, CYREG_PRT6_BYP\r
+.set SCSI_Out_DBx__1__CTL, CYREG_PRT6_CTL\r
+.set SCSI_Out_DBx__1__DM0, CYREG_PRT6_DM0\r
+.set SCSI_Out_DBx__1__DM1, CYREG_PRT6_DM1\r
+.set SCSI_Out_DBx__1__DM2, CYREG_PRT6_DM2\r
+.set SCSI_Out_DBx__1__DR, CYREG_PRT6_DR\r
+.set SCSI_Out_DBx__1__INP_DIS, CYREG_PRT6_INP_DIS\r
+.set SCSI_Out_DBx__1__INTTYPE, CYREG_PICU6_INTTYPE2\r
+.set SCSI_Out_DBx__1__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG\r
+.set SCSI_Out_DBx__1__LCD_EN, CYREG_PRT6_LCD_EN\r
+.set SCSI_Out_DBx__1__MASK, 0x04\r
+.set SCSI_Out_DBx__1__PC, CYREG_PRT6_PC2\r
+.set SCSI_Out_DBx__1__PORT, 6\r
+.set SCSI_Out_DBx__1__PRT, CYREG_PRT6_PRT\r
+.set SCSI_Out_DBx__1__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL\r
+.set SCSI_Out_DBx__1__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN\r
+.set SCSI_Out_DBx__1__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0\r
+.set SCSI_Out_DBx__1__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1\r
+.set SCSI_Out_DBx__1__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0\r
+.set SCSI_Out_DBx__1__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1\r
+.set SCSI_Out_DBx__1__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT\r
+.set SCSI_Out_DBx__1__PS, CYREG_PRT6_PS\r
+.set SCSI_Out_DBx__1__SHIFT, 2\r
+.set SCSI_Out_DBx__1__SLW, CYREG_PRT6_SLW\r
+.set SCSI_Out_DBx__2__AG, CYREG_PRT6_AG\r
+.set SCSI_Out_DBx__2__AMUX, CYREG_PRT6_AMUX\r
+.set SCSI_Out_DBx__2__BIE, CYREG_PRT6_BIE\r
+.set SCSI_Out_DBx__2__BIT_MASK, CYREG_PRT6_BIT_MASK\r
+.set SCSI_Out_DBx__2__BYP, CYREG_PRT6_BYP\r
+.set SCSI_Out_DBx__2__CTL, CYREG_PRT6_CTL\r
+.set SCSI_Out_DBx__2__DM0, CYREG_PRT6_DM0\r
+.set SCSI_Out_DBx__2__DM1, CYREG_PRT6_DM1\r
+.set SCSI_Out_DBx__2__DM2, CYREG_PRT6_DM2\r
+.set SCSI_Out_DBx__2__DR, CYREG_PRT6_DR\r
+.set SCSI_Out_DBx__2__INP_DIS, CYREG_PRT6_INP_DIS\r
+.set SCSI_Out_DBx__2__INTTYPE, CYREG_PICU6_INTTYPE1\r
+.set SCSI_Out_DBx__2__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG\r
+.set SCSI_Out_DBx__2__LCD_EN, CYREG_PRT6_LCD_EN\r
+.set SCSI_Out_DBx__2__MASK, 0x02\r
+.set SCSI_Out_DBx__2__PC, CYREG_PRT6_PC1\r
+.set SCSI_Out_DBx__2__PORT, 6\r
+.set SCSI_Out_DBx__2__PRT, CYREG_PRT6_PRT\r
+.set SCSI_Out_DBx__2__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL\r
+.set SCSI_Out_DBx__2__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN\r
+.set SCSI_Out_DBx__2__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0\r
+.set SCSI_Out_DBx__2__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1\r
+.set SCSI_Out_DBx__2__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0\r
+.set SCSI_Out_DBx__2__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1\r
+.set SCSI_Out_DBx__2__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT\r
+.set SCSI_Out_DBx__2__PS, CYREG_PRT6_PS\r
+.set SCSI_Out_DBx__2__SHIFT, 1\r
+.set SCSI_Out_DBx__2__SLW, CYREG_PRT6_SLW\r
+.set SCSI_Out_DBx__3__AG, CYREG_PRT6_AG\r
+.set SCSI_Out_DBx__3__AMUX, CYREG_PRT6_AMUX\r
+.set SCSI_Out_DBx__3__BIE, CYREG_PRT6_BIE\r
+.set SCSI_Out_DBx__3__BIT_MASK, CYREG_PRT6_BIT_MASK\r
+.set SCSI_Out_DBx__3__BYP, CYREG_PRT6_BYP\r
+.set SCSI_Out_DBx__3__CTL, CYREG_PRT6_CTL\r
+.set SCSI_Out_DBx__3__DM0, CYREG_PRT6_DM0\r
+.set SCSI_Out_DBx__3__DM1, CYREG_PRT6_DM1\r
+.set SCSI_Out_DBx__3__DM2, CYREG_PRT6_DM2\r
+.set SCSI_Out_DBx__3__DR, CYREG_PRT6_DR\r
+.set SCSI_Out_DBx__3__INP_DIS, CYREG_PRT6_INP_DIS\r
+.set SCSI_Out_DBx__3__INTTYPE, CYREG_PICU6_INTTYPE0\r
+.set SCSI_Out_DBx__3__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG\r
+.set SCSI_Out_DBx__3__LCD_EN, CYREG_PRT6_LCD_EN\r
+.set SCSI_Out_DBx__3__MASK, 0x01\r
+.set SCSI_Out_DBx__3__PC, CYREG_PRT6_PC0\r
+.set SCSI_Out_DBx__3__PORT, 6\r
+.set SCSI_Out_DBx__3__PRT, CYREG_PRT6_PRT\r
+.set SCSI_Out_DBx__3__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL\r
+.set SCSI_Out_DBx__3__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN\r
+.set SCSI_Out_DBx__3__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0\r
+.set SCSI_Out_DBx__3__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1\r
+.set SCSI_Out_DBx__3__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0\r
+.set SCSI_Out_DBx__3__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1\r
+.set SCSI_Out_DBx__3__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT\r
+.set SCSI_Out_DBx__3__PS, CYREG_PRT6_PS\r
+.set SCSI_Out_DBx__3__SHIFT, 0\r
+.set SCSI_Out_DBx__3__SLW, CYREG_PRT6_SLW\r
+.set SCSI_Out_DBx__4__AG, CYREG_PRT4_AG\r
+.set SCSI_Out_DBx__4__AMUX, CYREG_PRT4_AMUX\r
+.set SCSI_Out_DBx__4__BIE, CYREG_PRT4_BIE\r
+.set SCSI_Out_DBx__4__BIT_MASK, CYREG_PRT4_BIT_MASK\r
+.set SCSI_Out_DBx__4__BYP, CYREG_PRT4_BYP\r
+.set SCSI_Out_DBx__4__CTL, CYREG_PRT4_CTL\r
+.set SCSI_Out_DBx__4__DM0, CYREG_PRT4_DM0\r
+.set SCSI_Out_DBx__4__DM1, CYREG_PRT4_DM1\r
+.set SCSI_Out_DBx__4__DM2, CYREG_PRT4_DM2\r
+.set SCSI_Out_DBx__4__DR, CYREG_PRT4_DR\r
+.set SCSI_Out_DBx__4__INP_DIS, CYREG_PRT4_INP_DIS\r
+.set SCSI_Out_DBx__4__INTTYPE, CYREG_PICU4_INTTYPE7\r
+.set SCSI_Out_DBx__4__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG\r
+.set SCSI_Out_DBx__4__LCD_EN, CYREG_PRT4_LCD_EN\r
+.set SCSI_Out_DBx__4__MASK, 0x80\r
+.set SCSI_Out_DBx__4__PC, CYREG_PRT4_PC7\r
+.set SCSI_Out_DBx__4__PORT, 4\r
+.set SCSI_Out_DBx__4__PRT, CYREG_PRT4_PRT\r
+.set SCSI_Out_DBx__4__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL\r
+.set SCSI_Out_DBx__4__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN\r
+.set SCSI_Out_DBx__4__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0\r
+.set SCSI_Out_DBx__4__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1\r
+.set SCSI_Out_DBx__4__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0\r
+.set SCSI_Out_DBx__4__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1\r
+.set SCSI_Out_DBx__4__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT\r
+.set SCSI_Out_DBx__4__PS, CYREG_PRT4_PS\r
+.set SCSI_Out_DBx__4__SHIFT, 7\r
+.set SCSI_Out_DBx__4__SLW, CYREG_PRT4_SLW\r
+.set SCSI_Out_DBx__5__AG, CYREG_PRT4_AG\r
+.set SCSI_Out_DBx__5__AMUX, CYREG_PRT4_AMUX\r
+.set SCSI_Out_DBx__5__BIE, CYREG_PRT4_BIE\r
+.set SCSI_Out_DBx__5__BIT_MASK, CYREG_PRT4_BIT_MASK\r
+.set SCSI_Out_DBx__5__BYP, CYREG_PRT4_BYP\r
+.set SCSI_Out_DBx__5__CTL, CYREG_PRT4_CTL\r
+.set SCSI_Out_DBx__5__DM0, CYREG_PRT4_DM0\r
+.set SCSI_Out_DBx__5__DM1, CYREG_PRT4_DM1\r
+.set SCSI_Out_DBx__5__DM2, CYREG_PRT4_DM2\r
+.set SCSI_Out_DBx__5__DR, CYREG_PRT4_DR\r
+.set SCSI_Out_DBx__5__INP_DIS, CYREG_PRT4_INP_DIS\r
+.set SCSI_Out_DBx__5__INTTYPE, CYREG_PICU4_INTTYPE6\r
+.set SCSI_Out_DBx__5__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG\r
+.set SCSI_Out_DBx__5__LCD_EN, CYREG_PRT4_LCD_EN\r
+.set SCSI_Out_DBx__5__MASK, 0x40\r
+.set SCSI_Out_DBx__5__PC, CYREG_PRT4_PC6\r
+.set SCSI_Out_DBx__5__PORT, 4\r
+.set SCSI_Out_DBx__5__PRT, CYREG_PRT4_PRT\r
+.set SCSI_Out_DBx__5__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL\r
+.set SCSI_Out_DBx__5__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN\r
+.set SCSI_Out_DBx__5__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0\r
+.set SCSI_Out_DBx__5__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1\r
+.set SCSI_Out_DBx__5__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0\r
+.set SCSI_Out_DBx__5__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1\r
+.set SCSI_Out_DBx__5__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT\r
+.set SCSI_Out_DBx__5__PS, CYREG_PRT4_PS\r
+.set SCSI_Out_DBx__5__SHIFT, 6\r
+.set SCSI_Out_DBx__5__SLW, CYREG_PRT4_SLW\r
+.set SCSI_Out_DBx__6__AG, CYREG_PRT4_AG\r
+.set SCSI_Out_DBx__6__AMUX, CYREG_PRT4_AMUX\r
+.set SCSI_Out_DBx__6__BIE, CYREG_PRT4_BIE\r
+.set SCSI_Out_DBx__6__BIT_MASK, CYREG_PRT4_BIT_MASK\r
+.set SCSI_Out_DBx__6__BYP, CYREG_PRT4_BYP\r
+.set SCSI_Out_DBx__6__CTL, CYREG_PRT4_CTL\r
+.set SCSI_Out_DBx__6__DM0, CYREG_PRT4_DM0\r
+.set SCSI_Out_DBx__6__DM1, CYREG_PRT4_DM1\r
+.set SCSI_Out_DBx__6__DM2, CYREG_PRT4_DM2\r
+.set SCSI_Out_DBx__6__DR, CYREG_PRT4_DR\r
+.set SCSI_Out_DBx__6__INP_DIS, CYREG_PRT4_INP_DIS\r
+.set SCSI_Out_DBx__6__INTTYPE, CYREG_PICU4_INTTYPE5\r
+.set SCSI_Out_DBx__6__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG\r
+.set SCSI_Out_DBx__6__LCD_EN, CYREG_PRT4_LCD_EN\r
+.set SCSI_Out_DBx__6__MASK, 0x20\r
+.set SCSI_Out_DBx__6__PC, CYREG_PRT4_PC5\r
+.set SCSI_Out_DBx__6__PORT, 4\r
+.set SCSI_Out_DBx__6__PRT, CYREG_PRT4_PRT\r
+.set SCSI_Out_DBx__6__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL\r
+.set SCSI_Out_DBx__6__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN\r
+.set SCSI_Out_DBx__6__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0\r
+.set SCSI_Out_DBx__6__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1\r
+.set SCSI_Out_DBx__6__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0\r
+.set SCSI_Out_DBx__6__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1\r
+.set SCSI_Out_DBx__6__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT\r
+.set SCSI_Out_DBx__6__PS, CYREG_PRT4_PS\r
+.set SCSI_Out_DBx__6__SHIFT, 5\r
+.set SCSI_Out_DBx__6__SLW, CYREG_PRT4_SLW\r
+.set SCSI_Out_DBx__7__AG, CYREG_PRT4_AG\r
+.set SCSI_Out_DBx__7__AMUX, CYREG_PRT4_AMUX\r
+.set SCSI_Out_DBx__7__BIE, CYREG_PRT4_BIE\r
+.set SCSI_Out_DBx__7__BIT_MASK, CYREG_PRT4_BIT_MASK\r
+.set SCSI_Out_DBx__7__BYP, CYREG_PRT4_BYP\r
+.set SCSI_Out_DBx__7__CTL, CYREG_PRT4_CTL\r
+.set SCSI_Out_DBx__7__DM0, CYREG_PRT4_DM0\r
+.set SCSI_Out_DBx__7__DM1, CYREG_PRT4_DM1\r
+.set SCSI_Out_DBx__7__DM2, CYREG_PRT4_DM2\r
+.set SCSI_Out_DBx__7__DR, CYREG_PRT4_DR\r
+.set SCSI_Out_DBx__7__INP_DIS, CYREG_PRT4_INP_DIS\r
+.set SCSI_Out_DBx__7__INTTYPE, CYREG_PICU4_INTTYPE4\r
+.set SCSI_Out_DBx__7__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG\r
+.set SCSI_Out_DBx__7__LCD_EN, CYREG_PRT4_LCD_EN\r
+.set SCSI_Out_DBx__7__MASK, 0x10\r
+.set SCSI_Out_DBx__7__PC, CYREG_PRT4_PC4\r
+.set SCSI_Out_DBx__7__PORT, 4\r
+.set SCSI_Out_DBx__7__PRT, CYREG_PRT4_PRT\r
+.set SCSI_Out_DBx__7__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL\r
+.set SCSI_Out_DBx__7__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN\r
+.set SCSI_Out_DBx__7__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0\r
+.set SCSI_Out_DBx__7__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1\r
+.set SCSI_Out_DBx__7__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0\r
+.set SCSI_Out_DBx__7__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1\r
+.set SCSI_Out_DBx__7__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT\r
+.set SCSI_Out_DBx__7__PS, CYREG_PRT4_PS\r
+.set SCSI_Out_DBx__7__SHIFT, 4\r
+.set SCSI_Out_DBx__7__SLW, CYREG_PRT4_SLW\r
+.set SCSI_Out_DBx__DB0__AG, CYREG_PRT6_AG\r
+.set SCSI_Out_DBx__DB0__AMUX, CYREG_PRT6_AMUX\r
+.set SCSI_Out_DBx__DB0__BIE, CYREG_PRT6_BIE\r
+.set SCSI_Out_DBx__DB0__BIT_MASK, CYREG_PRT6_BIT_MASK\r
+.set SCSI_Out_DBx__DB0__BYP, CYREG_PRT6_BYP\r
+.set SCSI_Out_DBx__DB0__CTL, CYREG_PRT6_CTL\r
+.set SCSI_Out_DBx__DB0__DM0, CYREG_PRT6_DM0\r
+.set SCSI_Out_DBx__DB0__DM1, CYREG_PRT6_DM1\r
+.set SCSI_Out_DBx__DB0__DM2, CYREG_PRT6_DM2\r
+.set SCSI_Out_DBx__DB0__DR, CYREG_PRT6_DR\r
+.set SCSI_Out_DBx__DB0__INP_DIS, CYREG_PRT6_INP_DIS\r
+.set SCSI_Out_DBx__DB0__INTTYPE, CYREG_PICU6_INTTYPE3\r
+.set SCSI_Out_DBx__DB0__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG\r
+.set SCSI_Out_DBx__DB0__LCD_EN, CYREG_PRT6_LCD_EN\r
+.set SCSI_Out_DBx__DB0__MASK, 0x08\r
+.set SCSI_Out_DBx__DB0__PC, CYREG_PRT6_PC3\r
+.set SCSI_Out_DBx__DB0__PORT, 6\r
+.set SCSI_Out_DBx__DB0__PRT, CYREG_PRT6_PRT\r
+.set SCSI_Out_DBx__DB0__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL\r
+.set SCSI_Out_DBx__DB0__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN\r
+.set SCSI_Out_DBx__DB0__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0\r
+.set SCSI_Out_DBx__DB0__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1\r
+.set SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0\r
+.set SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1\r
+.set SCSI_Out_DBx__DB0__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT\r
+.set SCSI_Out_DBx__DB0__PS, CYREG_PRT6_PS\r
+.set SCSI_Out_DBx__DB0__SHIFT, 3\r
+.set SCSI_Out_DBx__DB0__SLW, CYREG_PRT6_SLW\r
+.set SCSI_Out_DBx__DB1__AG, CYREG_PRT6_AG\r
+.set SCSI_Out_DBx__DB1__AMUX, CYREG_PRT6_AMUX\r
+.set SCSI_Out_DBx__DB1__BIE, CYREG_PRT6_BIE\r
+.set SCSI_Out_DBx__DB1__BIT_MASK, CYREG_PRT6_BIT_MASK\r
+.set SCSI_Out_DBx__DB1__BYP, CYREG_PRT6_BYP\r
+.set SCSI_Out_DBx__DB1__CTL, CYREG_PRT6_CTL\r
+.set SCSI_Out_DBx__DB1__DM0, CYREG_PRT6_DM0\r
+.set SCSI_Out_DBx__DB1__DM1, CYREG_PRT6_DM1\r
+.set SCSI_Out_DBx__DB1__DM2, CYREG_PRT6_DM2\r
+.set SCSI_Out_DBx__DB1__DR, CYREG_PRT6_DR\r
+.set SCSI_Out_DBx__DB1__INP_DIS, CYREG_PRT6_INP_DIS\r
+.set SCSI_Out_DBx__DB1__INTTYPE, CYREG_PICU6_INTTYPE2\r
+.set SCSI_Out_DBx__DB1__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG\r
+.set SCSI_Out_DBx__DB1__LCD_EN, CYREG_PRT6_LCD_EN\r
+.set SCSI_Out_DBx__DB1__MASK, 0x04\r
+.set SCSI_Out_DBx__DB1__PC, CYREG_PRT6_PC2\r
+.set SCSI_Out_DBx__DB1__PORT, 6\r
+.set SCSI_Out_DBx__DB1__PRT, CYREG_PRT6_PRT\r
+.set SCSI_Out_DBx__DB1__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL\r
+.set SCSI_Out_DBx__DB1__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN\r
+.set SCSI_Out_DBx__DB1__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0\r
+.set SCSI_Out_DBx__DB1__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1\r
+.set SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0\r
+.set SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1\r
+.set SCSI_Out_DBx__DB1__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT\r
+.set SCSI_Out_DBx__DB1__PS, CYREG_PRT6_PS\r
+.set SCSI_Out_DBx__DB1__SHIFT, 2\r
+.set SCSI_Out_DBx__DB1__SLW, CYREG_PRT6_SLW\r
+.set SCSI_Out_DBx__DB2__AG, CYREG_PRT6_AG\r
+.set SCSI_Out_DBx__DB2__AMUX, CYREG_PRT6_AMUX\r
+.set SCSI_Out_DBx__DB2__BIE, CYREG_PRT6_BIE\r
+.set SCSI_Out_DBx__DB2__BIT_MASK, CYREG_PRT6_BIT_MASK\r
+.set SCSI_Out_DBx__DB2__BYP, CYREG_PRT6_BYP\r
+.set SCSI_Out_DBx__DB2__CTL, CYREG_PRT6_CTL\r
+.set SCSI_Out_DBx__DB2__DM0, CYREG_PRT6_DM0\r
+.set SCSI_Out_DBx__DB2__DM1, CYREG_PRT6_DM1\r
+.set SCSI_Out_DBx__DB2__DM2, CYREG_PRT6_DM2\r
+.set SCSI_Out_DBx__DB2__DR, CYREG_PRT6_DR\r
+.set SCSI_Out_DBx__DB2__INP_DIS, CYREG_PRT6_INP_DIS\r
+.set SCSI_Out_DBx__DB2__INTTYPE, CYREG_PICU6_INTTYPE1\r
+.set SCSI_Out_DBx__DB2__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG\r
+.set SCSI_Out_DBx__DB2__LCD_EN, CYREG_PRT6_LCD_EN\r
+.set SCSI_Out_DBx__DB2__MASK, 0x02\r
+.set SCSI_Out_DBx__DB2__PC, CYREG_PRT6_PC1\r
+.set SCSI_Out_DBx__DB2__PORT, 6\r
+.set SCSI_Out_DBx__DB2__PRT, CYREG_PRT6_PRT\r
+.set SCSI_Out_DBx__DB2__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL\r
+.set SCSI_Out_DBx__DB2__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN\r
+.set SCSI_Out_DBx__DB2__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0\r
+.set SCSI_Out_DBx__DB2__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1\r
+.set SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0\r
+.set SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1\r
+.set SCSI_Out_DBx__DB2__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT\r
+.set SCSI_Out_DBx__DB2__PS, CYREG_PRT6_PS\r
+.set SCSI_Out_DBx__DB2__SHIFT, 1\r
+.set SCSI_Out_DBx__DB2__SLW, CYREG_PRT6_SLW\r
+.set SCSI_Out_DBx__DB3__AG, CYREG_PRT6_AG\r
+.set SCSI_Out_DBx__DB3__AMUX, CYREG_PRT6_AMUX\r
+.set SCSI_Out_DBx__DB3__BIE, CYREG_PRT6_BIE\r
+.set SCSI_Out_DBx__DB3__BIT_MASK, CYREG_PRT6_BIT_MASK\r
+.set SCSI_Out_DBx__DB3__BYP, CYREG_PRT6_BYP\r
+.set SCSI_Out_DBx__DB3__CTL, CYREG_PRT6_CTL\r
+.set SCSI_Out_DBx__DB3__DM0, CYREG_PRT6_DM0\r
+.set SCSI_Out_DBx__DB3__DM1, CYREG_PRT6_DM1\r
+.set SCSI_Out_DBx__DB3__DM2, CYREG_PRT6_DM2\r
+.set SCSI_Out_DBx__DB3__DR, CYREG_PRT6_DR\r
+.set SCSI_Out_DBx__DB3__INP_DIS, CYREG_PRT6_INP_DIS\r
+.set SCSI_Out_DBx__DB3__INTTYPE, CYREG_PICU6_INTTYPE0\r
+.set SCSI_Out_DBx__DB3__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG\r
+.set SCSI_Out_DBx__DB3__LCD_EN, CYREG_PRT6_LCD_EN\r
+.set SCSI_Out_DBx__DB3__MASK, 0x01\r
+.set SCSI_Out_DBx__DB3__PC, CYREG_PRT6_PC0\r
+.set SCSI_Out_DBx__DB3__PORT, 6\r
+.set SCSI_Out_DBx__DB3__PRT, CYREG_PRT6_PRT\r
+.set SCSI_Out_DBx__DB3__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL\r
+.set SCSI_Out_DBx__DB3__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN\r
+.set SCSI_Out_DBx__DB3__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0\r
+.set SCSI_Out_DBx__DB3__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1\r
+.set SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0\r
+.set SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1\r
+.set SCSI_Out_DBx__DB3__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT\r
+.set SCSI_Out_DBx__DB3__PS, CYREG_PRT6_PS\r
+.set SCSI_Out_DBx__DB3__SHIFT, 0\r
+.set SCSI_Out_DBx__DB3__SLW, CYREG_PRT6_SLW\r
+.set SCSI_Out_DBx__DB4__AG, CYREG_PRT4_AG\r
+.set SCSI_Out_DBx__DB4__AMUX, CYREG_PRT4_AMUX\r
+.set SCSI_Out_DBx__DB4__BIE, CYREG_PRT4_BIE\r
+.set SCSI_Out_DBx__DB4__BIT_MASK, CYREG_PRT4_BIT_MASK\r
+.set SCSI_Out_DBx__DB4__BYP, CYREG_PRT4_BYP\r
+.set SCSI_Out_DBx__DB4__CTL, CYREG_PRT4_CTL\r
+.set SCSI_Out_DBx__DB4__DM0, CYREG_PRT4_DM0\r
+.set SCSI_Out_DBx__DB4__DM1, CYREG_PRT4_DM1\r
+.set SCSI_Out_DBx__DB4__DM2, CYREG_PRT4_DM2\r
+.set SCSI_Out_DBx__DB4__DR, CYREG_PRT4_DR\r
+.set SCSI_Out_DBx__DB4__INP_DIS, CYREG_PRT4_INP_DIS\r
+.set SCSI_Out_DBx__DB4__INTTYPE, CYREG_PICU4_INTTYPE7\r
+.set SCSI_Out_DBx__DB4__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG\r
+.set SCSI_Out_DBx__DB4__LCD_EN, CYREG_PRT4_LCD_EN\r
+.set SCSI_Out_DBx__DB4__MASK, 0x80\r
+.set SCSI_Out_DBx__DB4__PC, CYREG_PRT4_PC7\r
+.set SCSI_Out_DBx__DB4__PORT, 4\r
+.set SCSI_Out_DBx__DB4__PRT, CYREG_PRT4_PRT\r
+.set SCSI_Out_DBx__DB4__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL\r
+.set SCSI_Out_DBx__DB4__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN\r
+.set SCSI_Out_DBx__DB4__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0\r
+.set SCSI_Out_DBx__DB4__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1\r
+.set SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0\r
+.set SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1\r
+.set SCSI_Out_DBx__DB4__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT\r
+.set SCSI_Out_DBx__DB4__PS, CYREG_PRT4_PS\r
+.set SCSI_Out_DBx__DB4__SHIFT, 7\r
+.set SCSI_Out_DBx__DB4__SLW, CYREG_PRT4_SLW\r
+.set SCSI_Out_DBx__DB5__AG, CYREG_PRT4_AG\r
+.set SCSI_Out_DBx__DB5__AMUX, CYREG_PRT4_AMUX\r
+.set SCSI_Out_DBx__DB5__BIE, CYREG_PRT4_BIE\r
+.set SCSI_Out_DBx__DB5__BIT_MASK, CYREG_PRT4_BIT_MASK\r
+.set SCSI_Out_DBx__DB5__BYP, CYREG_PRT4_BYP\r
+.set SCSI_Out_DBx__DB5__CTL, CYREG_PRT4_CTL\r
+.set SCSI_Out_DBx__DB5__DM0, CYREG_PRT4_DM0\r
+.set SCSI_Out_DBx__DB5__DM1, CYREG_PRT4_DM1\r
+.set SCSI_Out_DBx__DB5__DM2, CYREG_PRT4_DM2\r
+.set SCSI_Out_DBx__DB5__DR, CYREG_PRT4_DR\r
+.set SCSI_Out_DBx__DB5__INP_DIS, CYREG_PRT4_INP_DIS\r
+.set SCSI_Out_DBx__DB5__INTTYPE, CYREG_PICU4_INTTYPE6\r
+.set SCSI_Out_DBx__DB5__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG\r
+.set SCSI_Out_DBx__DB5__LCD_EN, CYREG_PRT4_LCD_EN\r
+.set SCSI_Out_DBx__DB5__MASK, 0x40\r
+.set SCSI_Out_DBx__DB5__PC, CYREG_PRT4_PC6\r
+.set SCSI_Out_DBx__DB5__PORT, 4\r
+.set SCSI_Out_DBx__DB5__PRT, CYREG_PRT4_PRT\r
+.set SCSI_Out_DBx__DB5__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL\r
+.set SCSI_Out_DBx__DB5__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN\r
+.set SCSI_Out_DBx__DB5__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0\r
+.set SCSI_Out_DBx__DB5__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1\r
+.set SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0\r
+.set SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1\r
+.set SCSI_Out_DBx__DB5__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT\r
+.set SCSI_Out_DBx__DB5__PS, CYREG_PRT4_PS\r
+.set SCSI_Out_DBx__DB5__SHIFT, 6\r
+.set SCSI_Out_DBx__DB5__SLW, CYREG_PRT4_SLW\r
+.set SCSI_Out_DBx__DB6__AG, CYREG_PRT4_AG\r
+.set SCSI_Out_DBx__DB6__AMUX, CYREG_PRT4_AMUX\r
+.set SCSI_Out_DBx__DB6__BIE, CYREG_PRT4_BIE\r
+.set SCSI_Out_DBx__DB6__BIT_MASK, CYREG_PRT4_BIT_MASK\r
+.set SCSI_Out_DBx__DB6__BYP, CYREG_PRT4_BYP\r
+.set SCSI_Out_DBx__DB6__CTL, CYREG_PRT4_CTL\r
+.set SCSI_Out_DBx__DB6__DM0, CYREG_PRT4_DM0\r
+.set SCSI_Out_DBx__DB6__DM1, CYREG_PRT4_DM1\r
+.set SCSI_Out_DBx__DB6__DM2, CYREG_PRT4_DM2\r
+.set SCSI_Out_DBx__DB6__DR, CYREG_PRT4_DR\r
+.set SCSI_Out_DBx__DB6__INP_DIS, CYREG_PRT4_INP_DIS\r
+.set SCSI_Out_DBx__DB6__INTTYPE, CYREG_PICU4_INTTYPE5\r
+.set SCSI_Out_DBx__DB6__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG\r
+.set SCSI_Out_DBx__DB6__LCD_EN, CYREG_PRT4_LCD_EN\r
+.set SCSI_Out_DBx__DB6__MASK, 0x20\r
+.set SCSI_Out_DBx__DB6__PC, CYREG_PRT4_PC5\r
+.set SCSI_Out_DBx__DB6__PORT, 4\r
+.set SCSI_Out_DBx__DB6__PRT, CYREG_PRT4_PRT\r
+.set SCSI_Out_DBx__DB6__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL\r
+.set SCSI_Out_DBx__DB6__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN\r
+.set SCSI_Out_DBx__DB6__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0\r
+.set SCSI_Out_DBx__DB6__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1\r
+.set SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0\r
+.set SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1\r
+.set SCSI_Out_DBx__DB6__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT\r
+.set SCSI_Out_DBx__DB6__PS, CYREG_PRT4_PS\r
+.set SCSI_Out_DBx__DB6__SHIFT, 5\r
+.set SCSI_Out_DBx__DB6__SLW, CYREG_PRT4_SLW\r
+.set SCSI_Out_DBx__DB7__AG, CYREG_PRT4_AG\r
+.set SCSI_Out_DBx__DB7__AMUX, CYREG_PRT4_AMUX\r
+.set SCSI_Out_DBx__DB7__BIE, CYREG_PRT4_BIE\r
+.set SCSI_Out_DBx__DB7__BIT_MASK, CYREG_PRT4_BIT_MASK\r
+.set SCSI_Out_DBx__DB7__BYP, CYREG_PRT4_BYP\r
+.set SCSI_Out_DBx__DB7__CTL, CYREG_PRT4_CTL\r
+.set SCSI_Out_DBx__DB7__DM0, CYREG_PRT4_DM0\r
+.set SCSI_Out_DBx__DB7__DM1, CYREG_PRT4_DM1\r
+.set SCSI_Out_DBx__DB7__DM2, CYREG_PRT4_DM2\r
+.set SCSI_Out_DBx__DB7__DR, CYREG_PRT4_DR\r
+.set SCSI_Out_DBx__DB7__INP_DIS, CYREG_PRT4_INP_DIS\r
+.set SCSI_Out_DBx__DB7__INTTYPE, CYREG_PICU4_INTTYPE4\r
+.set SCSI_Out_DBx__DB7__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG\r
+.set SCSI_Out_DBx__DB7__LCD_EN, CYREG_PRT4_LCD_EN\r
+.set SCSI_Out_DBx__DB7__MASK, 0x10\r
+.set SCSI_Out_DBx__DB7__PC, CYREG_PRT4_PC4\r
+.set SCSI_Out_DBx__DB7__PORT, 4\r
+.set SCSI_Out_DBx__DB7__PRT, CYREG_PRT4_PRT\r
+.set SCSI_Out_DBx__DB7__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL\r
+.set SCSI_Out_DBx__DB7__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN\r
+.set SCSI_Out_DBx__DB7__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0\r
+.set SCSI_Out_DBx__DB7__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1\r
+.set SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0\r
+.set SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1\r
+.set SCSI_Out_DBx__DB7__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT\r
+.set SCSI_Out_DBx__DB7__PS, CYREG_PRT4_PS\r
+.set SCSI_Out_DBx__DB7__SHIFT, 4\r
+.set SCSI_Out_DBx__DB7__SLW, CYREG_PRT4_SLW\r
+\r
+/* SD_RX_DMA */\r
+.set SD_RX_DMA__DRQ_CTL, CYREG_IDMUX_DRQ_CTL0\r
+.set SD_RX_DMA__DRQ_NUMBER, 2\r
+.set SD_RX_DMA__NUMBEROF_TDS, 0\r
+.set SD_RX_DMA__PRIORITY, 0\r
+.set SD_RX_DMA__TERMIN_EN, 0\r
+.set SD_RX_DMA__TERMIN_SEL, 0\r
+.set SD_RX_DMA__TERMOUT0_EN, 1\r
+.set SD_RX_DMA__TERMOUT0_SEL, 2\r
+.set SD_RX_DMA__TERMOUT1_EN, 0\r
+.set SD_RX_DMA__TERMOUT1_SEL, 0\r
+.set SD_RX_DMA_COMPLETE__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
+.set SD_RX_DMA_COMPLETE__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
+.set SD_RX_DMA_COMPLETE__INTC_MASK, 0x20\r
+.set SD_RX_DMA_COMPLETE__INTC_NUMBER, 5\r
+.set SD_RX_DMA_COMPLETE__INTC_PRIOR_NUM, 7\r
+.set SD_RX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_5\r
+.set SD_RX_DMA_COMPLETE__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
+.set SD_RX_DMA_COMPLETE__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
+\r
+/* SD_TX_DMA */\r
+.set SD_TX_DMA__DRQ_CTL, CYREG_IDMUX_DRQ_CTL0\r
+.set SD_TX_DMA__DRQ_NUMBER, 3\r
+.set SD_TX_DMA__NUMBEROF_TDS, 0\r
+.set SD_TX_DMA__PRIORITY, 1\r
+.set SD_TX_DMA__TERMIN_EN, 0\r
+.set SD_TX_DMA__TERMIN_SEL, 0\r
+.set SD_TX_DMA__TERMOUT0_EN, 1\r
+.set SD_TX_DMA__TERMOUT0_SEL, 3\r
+.set SD_TX_DMA__TERMOUT1_EN, 0\r
+.set SD_TX_DMA__TERMOUT1_SEL, 0\r
+.set SD_TX_DMA_COMPLETE__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
+.set SD_TX_DMA_COMPLETE__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
+.set SD_TX_DMA_COMPLETE__INTC_MASK, 0x40\r
+.set SD_TX_DMA_COMPLETE__INTC_NUMBER, 6\r
+.set SD_TX_DMA_COMPLETE__INTC_PRIOR_NUM, 7\r
+.set SD_TX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_6\r
+.set SD_TX_DMA_COMPLETE__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
+.set SD_TX_DMA_COMPLETE__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
+\r
+/* SCSI_Noise */\r
+.set SCSI_Noise__0__AG, CYREG_PRT12_AG\r
+.set SCSI_Noise__0__BIE, CYREG_PRT12_BIE\r
+.set SCSI_Noise__0__BIT_MASK, CYREG_PRT12_BIT_MASK\r
+.set SCSI_Noise__0__BYP, CYREG_PRT12_BYP\r
+.set SCSI_Noise__0__DM0, CYREG_PRT12_DM0\r
+.set SCSI_Noise__0__DM1, CYREG_PRT12_DM1\r
+.set SCSI_Noise__0__DM2, CYREG_PRT12_DM2\r
+.set SCSI_Noise__0__DR, CYREG_PRT12_DR\r
+.set SCSI_Noise__0__INP_DIS, CYREG_PRT12_INP_DIS\r
+.set SCSI_Noise__0__INTTYPE, CYREG_PICU12_INTTYPE5\r
+.set SCSI_Noise__0__MASK, 0x20\r
+.set SCSI_Noise__0__PC, CYREG_PRT12_PC5\r
+.set SCSI_Noise__0__PORT, 12\r
+.set SCSI_Noise__0__PRT, CYREG_PRT12_PRT\r
+.set SCSI_Noise__0__PRTDSI__DBL_SYNC_IN, CYREG_PRT12_DBL_SYNC_IN\r
+.set SCSI_Noise__0__PRTDSI__OE_SEL0, CYREG_PRT12_OE_SEL0\r
+.set SCSI_Noise__0__PRTDSI__OE_SEL1, CYREG_PRT12_OE_SEL1\r
+.set SCSI_Noise__0__PRTDSI__OUT_SEL0, CYREG_PRT12_OUT_SEL0\r
+.set SCSI_Noise__0__PRTDSI__OUT_SEL1, CYREG_PRT12_OUT_SEL1\r
+.set SCSI_Noise__0__PRTDSI__SYNC_OUT, CYREG_PRT12_SYNC_OUT\r
+.set SCSI_Noise__0__PS, CYREG_PRT12_PS\r
+.set SCSI_Noise__0__SHIFT, 5\r
+.set SCSI_Noise__0__SIO_CFG, CYREG_PRT12_SIO_CFG\r
+.set SCSI_Noise__0__SIO_DIFF, CYREG_PRT12_SIO_DIFF\r
+.set SCSI_Noise__0__SIO_HYST_EN, CYREG_PRT12_SIO_HYST_EN\r
+.set SCSI_Noise__0__SIO_REG_HIFREQ, CYREG_PRT12_SIO_REG_HIFREQ\r
+.set SCSI_Noise__0__SLW, CYREG_PRT12_SLW\r
+.set SCSI_Noise__1__AG, CYREG_PRT6_AG\r
+.set SCSI_Noise__1__AMUX, CYREG_PRT6_AMUX\r
+.set SCSI_Noise__1__BIE, CYREG_PRT6_BIE\r
+.set SCSI_Noise__1__BIT_MASK, CYREG_PRT6_BIT_MASK\r
+.set SCSI_Noise__1__BYP, CYREG_PRT6_BYP\r
+.set SCSI_Noise__1__CTL, CYREG_PRT6_CTL\r
+.set SCSI_Noise__1__DM0, CYREG_PRT6_DM0\r
+.set SCSI_Noise__1__DM1, CYREG_PRT6_DM1\r
+.set SCSI_Noise__1__DM2, CYREG_PRT6_DM2\r
+.set SCSI_Noise__1__DR, CYREG_PRT6_DR\r
+.set SCSI_Noise__1__INP_DIS, CYREG_PRT6_INP_DIS\r
+.set SCSI_Noise__1__INTTYPE, CYREG_PICU6_INTTYPE4\r
+.set SCSI_Noise__1__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG\r
+.set SCSI_Noise__1__LCD_EN, CYREG_PRT6_LCD_EN\r
+.set SCSI_Noise__1__MASK, 0x10\r
+.set SCSI_Noise__1__PC, CYREG_PRT6_PC4\r
+.set SCSI_Noise__1__PORT, 6\r
+.set SCSI_Noise__1__PRT, CYREG_PRT6_PRT\r
+.set SCSI_Noise__1__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL\r
+.set SCSI_Noise__1__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN\r
+.set SCSI_Noise__1__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0\r
+.set SCSI_Noise__1__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1\r
+.set SCSI_Noise__1__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0\r
+.set SCSI_Noise__1__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1\r
+.set SCSI_Noise__1__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT\r
+.set SCSI_Noise__1__PS, CYREG_PRT6_PS\r
+.set SCSI_Noise__1__SHIFT, 4\r
+.set SCSI_Noise__1__SLW, CYREG_PRT6_SLW\r
+.set SCSI_Noise__2__AG, CYREG_PRT5_AG\r
+.set SCSI_Noise__2__AMUX, CYREG_PRT5_AMUX\r
+.set SCSI_Noise__2__BIE, CYREG_PRT5_BIE\r
+.set SCSI_Noise__2__BIT_MASK, CYREG_PRT5_BIT_MASK\r
+.set SCSI_Noise__2__BYP, CYREG_PRT5_BYP\r
+.set SCSI_Noise__2__CTL, CYREG_PRT5_CTL\r
+.set SCSI_Noise__2__DM0, CYREG_PRT5_DM0\r
+.set SCSI_Noise__2__DM1, CYREG_PRT5_DM1\r
+.set SCSI_Noise__2__DM2, CYREG_PRT5_DM2\r
+.set SCSI_Noise__2__DR, CYREG_PRT5_DR\r
+.set SCSI_Noise__2__INP_DIS, CYREG_PRT5_INP_DIS\r
+.set SCSI_Noise__2__INTTYPE, CYREG_PICU5_INTTYPE0\r
+.set SCSI_Noise__2__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG\r
+.set SCSI_Noise__2__LCD_EN, CYREG_PRT5_LCD_EN\r
+.set SCSI_Noise__2__MASK, 0x01\r
+.set SCSI_Noise__2__PC, CYREG_PRT5_PC0\r
+.set SCSI_Noise__2__PORT, 5\r
+.set SCSI_Noise__2__PRT, CYREG_PRT5_PRT\r
+.set SCSI_Noise__2__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL\r
+.set SCSI_Noise__2__PRTDSI__DBL_SYNC_IN, CYREG_PRT5_DBL_SYNC_IN\r
+.set SCSI_Noise__2__PRTDSI__OE_SEL0, CYREG_PRT5_OE_SEL0\r
+.set SCSI_Noise__2__PRTDSI__OE_SEL1, CYREG_PRT5_OE_SEL1\r
+.set SCSI_Noise__2__PRTDSI__OUT_SEL0, CYREG_PRT5_OUT_SEL0\r
+.set SCSI_Noise__2__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1\r
+.set SCSI_Noise__2__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT\r
+.set SCSI_Noise__2__PS, CYREG_PRT5_PS\r
+.set SCSI_Noise__2__SHIFT, 0\r
+.set SCSI_Noise__2__SLW, CYREG_PRT5_SLW\r
+.set SCSI_Noise__3__AG, CYREG_PRT6_AG\r
+.set SCSI_Noise__3__AMUX, CYREG_PRT6_AMUX\r
+.set SCSI_Noise__3__BIE, CYREG_PRT6_BIE\r
+.set SCSI_Noise__3__BIT_MASK, CYREG_PRT6_BIT_MASK\r
+.set SCSI_Noise__3__BYP, CYREG_PRT6_BYP\r
+.set SCSI_Noise__3__CTL, CYREG_PRT6_CTL\r
+.set SCSI_Noise__3__DM0, CYREG_PRT6_DM0\r
+.set SCSI_Noise__3__DM1, CYREG_PRT6_DM1\r
+.set SCSI_Noise__3__DM2, CYREG_PRT6_DM2\r
+.set SCSI_Noise__3__DR, CYREG_PRT6_DR\r
+.set SCSI_Noise__3__INP_DIS, CYREG_PRT6_INP_DIS\r
+.set SCSI_Noise__3__INTTYPE, CYREG_PICU6_INTTYPE6\r
+.set SCSI_Noise__3__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG\r
+.set SCSI_Noise__3__LCD_EN, CYREG_PRT6_LCD_EN\r
+.set SCSI_Noise__3__MASK, 0x40\r
+.set SCSI_Noise__3__PC, CYREG_PRT6_PC6\r
+.set SCSI_Noise__3__PORT, 6\r
+.set SCSI_Noise__3__PRT, CYREG_PRT6_PRT\r
+.set SCSI_Noise__3__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL\r
+.set SCSI_Noise__3__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN\r
+.set SCSI_Noise__3__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0\r
+.set SCSI_Noise__3__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1\r
+.set SCSI_Noise__3__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0\r
+.set SCSI_Noise__3__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1\r
+.set SCSI_Noise__3__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT\r
+.set SCSI_Noise__3__PS, CYREG_PRT6_PS\r
+.set SCSI_Noise__3__SHIFT, 6\r
+.set SCSI_Noise__3__SLW, CYREG_PRT6_SLW\r
+.set SCSI_Noise__4__AG, CYREG_PRT6_AG\r
+.set SCSI_Noise__4__AMUX, CYREG_PRT6_AMUX\r
+.set SCSI_Noise__4__BIE, CYREG_PRT6_BIE\r
+.set SCSI_Noise__4__BIT_MASK, CYREG_PRT6_BIT_MASK\r
+.set SCSI_Noise__4__BYP, CYREG_PRT6_BYP\r
+.set SCSI_Noise__4__CTL, CYREG_PRT6_CTL\r
+.set SCSI_Noise__4__DM0, CYREG_PRT6_DM0\r
+.set SCSI_Noise__4__DM1, CYREG_PRT6_DM1\r
+.set SCSI_Noise__4__DM2, CYREG_PRT6_DM2\r
+.set SCSI_Noise__4__DR, CYREG_PRT6_DR\r
+.set SCSI_Noise__4__INP_DIS, CYREG_PRT6_INP_DIS\r
+.set SCSI_Noise__4__INTTYPE, CYREG_PICU6_INTTYPE5\r
+.set SCSI_Noise__4__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG\r
+.set SCSI_Noise__4__LCD_EN, CYREG_PRT6_LCD_EN\r
+.set SCSI_Noise__4__MASK, 0x20\r
+.set SCSI_Noise__4__PC, CYREG_PRT6_PC5\r
+.set SCSI_Noise__4__PORT, 6\r
+.set SCSI_Noise__4__PRT, CYREG_PRT6_PRT\r
+.set SCSI_Noise__4__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL\r
+.set SCSI_Noise__4__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN\r
+.set SCSI_Noise__4__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0\r
+.set SCSI_Noise__4__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1\r
+.set SCSI_Noise__4__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0\r
+.set SCSI_Noise__4__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1\r
+.set SCSI_Noise__4__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT\r
+.set SCSI_Noise__4__PS, CYREG_PRT6_PS\r
+.set SCSI_Noise__4__SHIFT, 5\r
+.set SCSI_Noise__4__SLW, CYREG_PRT6_SLW\r
+.set SCSI_Noise__ACK__AG, CYREG_PRT6_AG\r
+.set SCSI_Noise__ACK__AMUX, CYREG_PRT6_AMUX\r
+.set SCSI_Noise__ACK__BIE, CYREG_PRT6_BIE\r
+.set SCSI_Noise__ACK__BIT_MASK, CYREG_PRT6_BIT_MASK\r
+.set SCSI_Noise__ACK__BYP, CYREG_PRT6_BYP\r
+.set SCSI_Noise__ACK__CTL, CYREG_PRT6_CTL\r
+.set SCSI_Noise__ACK__DM0, CYREG_PRT6_DM0\r
+.set SCSI_Noise__ACK__DM1, CYREG_PRT6_DM1\r
+.set SCSI_Noise__ACK__DM2, CYREG_PRT6_DM2\r
+.set SCSI_Noise__ACK__DR, CYREG_PRT6_DR\r
+.set SCSI_Noise__ACK__INP_DIS, CYREG_PRT6_INP_DIS\r
+.set SCSI_Noise__ACK__INTTYPE, CYREG_PICU6_INTTYPE5\r
+.set SCSI_Noise__ACK__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG\r
+.set SCSI_Noise__ACK__LCD_EN, CYREG_PRT6_LCD_EN\r
+.set SCSI_Noise__ACK__MASK, 0x20\r
+.set SCSI_Noise__ACK__PC, CYREG_PRT6_PC5\r
+.set SCSI_Noise__ACK__PORT, 6\r
+.set SCSI_Noise__ACK__PRT, CYREG_PRT6_PRT\r
+.set SCSI_Noise__ACK__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL\r
+.set SCSI_Noise__ACK__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN\r
+.set SCSI_Noise__ACK__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0\r
+.set SCSI_Noise__ACK__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1\r
+.set SCSI_Noise__ACK__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0\r
+.set SCSI_Noise__ACK__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1\r
+.set SCSI_Noise__ACK__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT\r
+.set SCSI_Noise__ACK__PS, CYREG_PRT6_PS\r
+.set SCSI_Noise__ACK__SHIFT, 5\r
+.set SCSI_Noise__ACK__SLW, CYREG_PRT6_SLW\r
+.set SCSI_Noise__ATN__AG, CYREG_PRT12_AG\r
+.set SCSI_Noise__ATN__BIE, CYREG_PRT12_BIE\r
+.set SCSI_Noise__ATN__BIT_MASK, CYREG_PRT12_BIT_MASK\r
+.set SCSI_Noise__ATN__BYP, CYREG_PRT12_BYP\r
+.set SCSI_Noise__ATN__DM0, CYREG_PRT12_DM0\r
+.set SCSI_Noise__ATN__DM1, CYREG_PRT12_DM1\r
+.set SCSI_Noise__ATN__DM2, CYREG_PRT12_DM2\r
+.set SCSI_Noise__ATN__DR, CYREG_PRT12_DR\r
+.set SCSI_Noise__ATN__INP_DIS, CYREG_PRT12_INP_DIS\r
+.set SCSI_Noise__ATN__INTTYPE, CYREG_PICU12_INTTYPE5\r
+.set SCSI_Noise__ATN__MASK, 0x20\r
+.set SCSI_Noise__ATN__PC, CYREG_PRT12_PC5\r
+.set SCSI_Noise__ATN__PORT, 12\r
+.set SCSI_Noise__ATN__PRT, CYREG_PRT12_PRT\r
+.set SCSI_Noise__ATN__PRTDSI__DBL_SYNC_IN, CYREG_PRT12_DBL_SYNC_IN\r
+.set SCSI_Noise__ATN__PRTDSI__OE_SEL0, CYREG_PRT12_OE_SEL0\r
+.set SCSI_Noise__ATN__PRTDSI__OE_SEL1, CYREG_PRT12_OE_SEL1\r
+.set SCSI_Noise__ATN__PRTDSI__OUT_SEL0, CYREG_PRT12_OUT_SEL0\r
+.set SCSI_Noise__ATN__PRTDSI__OUT_SEL1, CYREG_PRT12_OUT_SEL1\r
+.set SCSI_Noise__ATN__PRTDSI__SYNC_OUT, CYREG_PRT12_SYNC_OUT\r
+.set SCSI_Noise__ATN__PS, CYREG_PRT12_PS\r
+.set SCSI_Noise__ATN__SHIFT, 5\r
+.set SCSI_Noise__ATN__SIO_CFG, CYREG_PRT12_SIO_CFG\r
+.set SCSI_Noise__ATN__SIO_DIFF, CYREG_PRT12_SIO_DIFF\r
+.set SCSI_Noise__ATN__SIO_HYST_EN, CYREG_PRT12_SIO_HYST_EN\r
+.set SCSI_Noise__ATN__SIO_REG_HIFREQ, CYREG_PRT12_SIO_REG_HIFREQ\r
+.set SCSI_Noise__ATN__SLW, CYREG_PRT12_SLW\r
+.set SCSI_Noise__BSY__AG, CYREG_PRT6_AG\r
+.set SCSI_Noise__BSY__AMUX, CYREG_PRT6_AMUX\r
+.set SCSI_Noise__BSY__BIE, CYREG_PRT6_BIE\r
+.set SCSI_Noise__BSY__BIT_MASK, CYREG_PRT6_BIT_MASK\r
+.set SCSI_Noise__BSY__BYP, CYREG_PRT6_BYP\r
+.set SCSI_Noise__BSY__CTL, CYREG_PRT6_CTL\r
+.set SCSI_Noise__BSY__DM0, CYREG_PRT6_DM0\r
+.set SCSI_Noise__BSY__DM1, CYREG_PRT6_DM1\r
+.set SCSI_Noise__BSY__DM2, CYREG_PRT6_DM2\r
+.set SCSI_Noise__BSY__DR, CYREG_PRT6_DR\r
+.set SCSI_Noise__BSY__INP_DIS, CYREG_PRT6_INP_DIS\r
+.set SCSI_Noise__BSY__INTTYPE, CYREG_PICU6_INTTYPE4\r
+.set SCSI_Noise__BSY__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG\r
+.set SCSI_Noise__BSY__LCD_EN, CYREG_PRT6_LCD_EN\r
+.set SCSI_Noise__BSY__MASK, 0x10\r
+.set SCSI_Noise__BSY__PC, CYREG_PRT6_PC4\r
+.set SCSI_Noise__BSY__PORT, 6\r
+.set SCSI_Noise__BSY__PRT, CYREG_PRT6_PRT\r
+.set SCSI_Noise__BSY__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL\r
+.set SCSI_Noise__BSY__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN\r
+.set SCSI_Noise__BSY__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0\r
+.set SCSI_Noise__BSY__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1\r
+.set SCSI_Noise__BSY__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0\r
+.set SCSI_Noise__BSY__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1\r
+.set SCSI_Noise__BSY__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT\r
+.set SCSI_Noise__BSY__PS, CYREG_PRT6_PS\r
+.set SCSI_Noise__BSY__SHIFT, 4\r
+.set SCSI_Noise__BSY__SLW, CYREG_PRT6_SLW\r
+.set SCSI_Noise__RST__AG, CYREG_PRT6_AG\r
+.set SCSI_Noise__RST__AMUX, CYREG_PRT6_AMUX\r
+.set SCSI_Noise__RST__BIE, CYREG_PRT6_BIE\r
+.set SCSI_Noise__RST__BIT_MASK, CYREG_PRT6_BIT_MASK\r
+.set SCSI_Noise__RST__BYP, CYREG_PRT6_BYP\r
+.set SCSI_Noise__RST__CTL, CYREG_PRT6_CTL\r
+.set SCSI_Noise__RST__DM0, CYREG_PRT6_DM0\r
+.set SCSI_Noise__RST__DM1, CYREG_PRT6_DM1\r
+.set SCSI_Noise__RST__DM2, CYREG_PRT6_DM2\r
+.set SCSI_Noise__RST__DR, CYREG_PRT6_DR\r
+.set SCSI_Noise__RST__INP_DIS, CYREG_PRT6_INP_DIS\r
+.set SCSI_Noise__RST__INTTYPE, CYREG_PICU6_INTTYPE6\r
+.set SCSI_Noise__RST__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG\r
+.set SCSI_Noise__RST__LCD_EN, CYREG_PRT6_LCD_EN\r
+.set SCSI_Noise__RST__MASK, 0x40\r
+.set SCSI_Noise__RST__PC, CYREG_PRT6_PC6\r
+.set SCSI_Noise__RST__PORT, 6\r
+.set SCSI_Noise__RST__PRT, CYREG_PRT6_PRT\r
+.set SCSI_Noise__RST__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL\r
+.set SCSI_Noise__RST__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN\r
+.set SCSI_Noise__RST__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0\r
+.set SCSI_Noise__RST__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1\r
+.set SCSI_Noise__RST__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0\r
+.set SCSI_Noise__RST__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1\r
+.set SCSI_Noise__RST__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT\r
+.set SCSI_Noise__RST__PS, CYREG_PRT6_PS\r
+.set SCSI_Noise__RST__SHIFT, 6\r
+.set SCSI_Noise__RST__SLW, CYREG_PRT6_SLW\r
+.set SCSI_Noise__SEL__AG, CYREG_PRT5_AG\r
+.set SCSI_Noise__SEL__AMUX, CYREG_PRT5_AMUX\r
+.set SCSI_Noise__SEL__BIE, CYREG_PRT5_BIE\r
+.set SCSI_Noise__SEL__BIT_MASK, CYREG_PRT5_BIT_MASK\r
+.set SCSI_Noise__SEL__BYP, CYREG_PRT5_BYP\r
+.set SCSI_Noise__SEL__CTL, CYREG_PRT5_CTL\r
+.set SCSI_Noise__SEL__DM0, CYREG_PRT5_DM0\r
+.set SCSI_Noise__SEL__DM1, CYREG_PRT5_DM1\r
+.set SCSI_Noise__SEL__DM2, CYREG_PRT5_DM2\r
+.set SCSI_Noise__SEL__DR, CYREG_PRT5_DR\r
+.set SCSI_Noise__SEL__INP_DIS, CYREG_PRT5_INP_DIS\r
+.set SCSI_Noise__SEL__INTTYPE, CYREG_PICU5_INTTYPE0\r
+.set SCSI_Noise__SEL__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG\r
+.set SCSI_Noise__SEL__LCD_EN, CYREG_PRT5_LCD_EN\r
+.set SCSI_Noise__SEL__MASK, 0x01\r
+.set SCSI_Noise__SEL__PC, CYREG_PRT5_PC0\r
+.set SCSI_Noise__SEL__PORT, 5\r
+.set SCSI_Noise__SEL__PRT, CYREG_PRT5_PRT\r
+.set SCSI_Noise__SEL__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL\r
+.set SCSI_Noise__SEL__PRTDSI__DBL_SYNC_IN, CYREG_PRT5_DBL_SYNC_IN\r
+.set SCSI_Noise__SEL__PRTDSI__OE_SEL0, CYREG_PRT5_OE_SEL0\r
+.set SCSI_Noise__SEL__PRTDSI__OE_SEL1, CYREG_PRT5_OE_SEL1\r
+.set SCSI_Noise__SEL__PRTDSI__OUT_SEL0, CYREG_PRT5_OUT_SEL0\r
+.set SCSI_Noise__SEL__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1\r
+.set SCSI_Noise__SEL__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT\r
+.set SCSI_Noise__SEL__PS, CYREG_PRT5_PS\r
+.set SCSI_Noise__SEL__SHIFT, 0\r
+.set SCSI_Noise__SEL__SLW, CYREG_PRT5_SLW\r
+\r
/* scsiTarget */\r
.set scsiTarget_datapath__16BIT_A0_REG, CYREG_B0_UDB00_01_A0\r
.set scsiTarget_datapath__16BIT_A1_REG, CYREG_B0_UDB00_01_A1\r
.set scsiTarget_StatusReg__STATUS_CONTROL_REG, CYREG_B0_UDB07_ST_CTL\r
.set scsiTarget_StatusReg__STATUS_REG, CYREG_B0_UDB07_ST\r
\r
+/* Debug_Timer */\r
+.set Debug_Timer_Interrupt__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
+.set Debug_Timer_Interrupt__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
+.set Debug_Timer_Interrupt__INTC_MASK, 0x01\r
+.set Debug_Timer_Interrupt__INTC_NUMBER, 0\r
+.set Debug_Timer_Interrupt__INTC_PRIOR_NUM, 7\r
+.set Debug_Timer_Interrupt__INTC_PRIOR_REG, CYREG_NVIC_PRI_0\r
+.set Debug_Timer_Interrupt__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
+.set Debug_Timer_Interrupt__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
+.set Debug_Timer_TimerHW__CAP0, CYREG_TMR0_CAP0\r
+.set Debug_Timer_TimerHW__CAP1, CYREG_TMR0_CAP1\r
+.set Debug_Timer_TimerHW__CFG0, CYREG_TMR0_CFG0\r
+.set Debug_Timer_TimerHW__CFG1, CYREG_TMR0_CFG1\r
+.set Debug_Timer_TimerHW__CFG2, CYREG_TMR0_CFG2\r
+.set Debug_Timer_TimerHW__CNT_CMP0, CYREG_TMR0_CNT_CMP0\r
+.set Debug_Timer_TimerHW__CNT_CMP1, CYREG_TMR0_CNT_CMP1\r
+.set Debug_Timer_TimerHW__PER0, CYREG_TMR0_PER0\r
+.set Debug_Timer_TimerHW__PER1, CYREG_TMR0_PER1\r
+.set Debug_Timer_TimerHW__PM_ACT_CFG, CYREG_PM_ACT_CFG3\r
+.set Debug_Timer_TimerHW__PM_ACT_MSK, 0x01\r
+.set Debug_Timer_TimerHW__PM_STBY_CFG, CYREG_PM_STBY_CFG3\r
+.set Debug_Timer_TimerHW__PM_STBY_MSK, 0x01\r
+.set Debug_Timer_TimerHW__RT0, CYREG_TMR0_RT0\r
+.set Debug_Timer_TimerHW__RT1, CYREG_TMR0_RT1\r
+.set Debug_Timer_TimerHW__SR0, CYREG_TMR0_SR0\r
+\r
+/* SCSI_RX_DMA */\r
+.set SCSI_RX_DMA__DRQ_CTL, CYREG_IDMUX_DRQ_CTL0\r
+.set SCSI_RX_DMA__DRQ_NUMBER, 0\r
+.set SCSI_RX_DMA__NUMBEROF_TDS, 0\r
+.set SCSI_RX_DMA__PRIORITY, 2\r
+.set SCSI_RX_DMA__TERMIN_EN, 0\r
+.set SCSI_RX_DMA__TERMIN_SEL, 0\r
+.set SCSI_RX_DMA__TERMOUT0_EN, 1\r
+.set SCSI_RX_DMA__TERMOUT0_SEL, 0\r
+.set SCSI_RX_DMA__TERMOUT1_EN, 0\r
+.set SCSI_RX_DMA__TERMOUT1_SEL, 0\r
+.set SCSI_RX_DMA_COMPLETE__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
+.set SCSI_RX_DMA_COMPLETE__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
+.set SCSI_RX_DMA_COMPLETE__INTC_MASK, 0x04\r
+.set SCSI_RX_DMA_COMPLETE__INTC_NUMBER, 2\r
+.set SCSI_RX_DMA_COMPLETE__INTC_PRIOR_NUM, 7\r
+.set SCSI_RX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_2\r
+.set SCSI_RX_DMA_COMPLETE__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
+.set SCSI_RX_DMA_COMPLETE__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
+\r
+/* SCSI_TX_DMA */\r
+.set SCSI_TX_DMA__DRQ_CTL, CYREG_IDMUX_DRQ_CTL0\r
+.set SCSI_TX_DMA__DRQ_NUMBER, 1\r
+.set SCSI_TX_DMA__NUMBEROF_TDS, 0\r
+.set SCSI_TX_DMA__PRIORITY, 2\r
+.set SCSI_TX_DMA__TERMIN_EN, 0\r
+.set SCSI_TX_DMA__TERMIN_SEL, 0\r
+.set SCSI_TX_DMA__TERMOUT0_EN, 1\r
+.set SCSI_TX_DMA__TERMOUT0_SEL, 1\r
+.set SCSI_TX_DMA__TERMOUT1_EN, 0\r
+.set SCSI_TX_DMA__TERMOUT1_SEL, 0\r
+.set SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
+.set SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
+.set SCSI_TX_DMA_COMPLETE__INTC_MASK, 0x10\r
+.set SCSI_TX_DMA_COMPLETE__INTC_NUMBER, 4\r
+.set SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM, 7\r
+.set SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_4\r
+.set SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
+.set SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
+\r
+/* SD_Data_Clk */\r
+.set SD_Data_Clk__CFG0, CYREG_CLKDIST_DCFG0_CFG0\r
+.set SD_Data_Clk__CFG1, CYREG_CLKDIST_DCFG0_CFG1\r
+.set SD_Data_Clk__CFG2, CYREG_CLKDIST_DCFG0_CFG2\r
+.set SD_Data_Clk__CFG2_SRC_SEL_MASK, 0x07\r
+.set SD_Data_Clk__INDEX, 0x00\r
+.set SD_Data_Clk__PM_ACT_CFG, CYREG_PM_ACT_CFG2\r
+.set SD_Data_Clk__PM_ACT_MSK, 0x01\r
+.set SD_Data_Clk__PM_STBY_CFG, CYREG_PM_STBY_CFG2\r
+.set SD_Data_Clk__PM_STBY_MSK, 0x01\r
+\r
/* timer_clock */\r
.set timer_clock__CFG0, CYREG_CLKDIST_DCFG2_CFG0\r
.set timer_clock__CFG1, CYREG_CLKDIST_DCFG2_CFG1\r
.set timer_clock__PM_STBY_CFG, CYREG_PM_STBY_CFG2\r
.set timer_clock__PM_STBY_MSK, 0x04\r
\r
+/* SCSI_RST_ISR */\r
+.set SCSI_RST_ISR__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
+.set SCSI_RST_ISR__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
+.set SCSI_RST_ISR__INTC_MASK, 0x02\r
+.set SCSI_RST_ISR__INTC_NUMBER, 1\r
+.set SCSI_RST_ISR__INTC_PRIOR_NUM, 7\r
+.set SCSI_RST_ISR__INTC_PRIOR_REG, CYREG_NVIC_PRI_1\r
+.set SCSI_RST_ISR__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
+.set SCSI_RST_ISR__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
+\r
+/* SCSI_SEL_ISR */\r
+.set SCSI_SEL_ISR__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
+.set SCSI_SEL_ISR__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
+.set SCSI_SEL_ISR__INTC_MASK, 0x08\r
+.set SCSI_SEL_ISR__INTC_NUMBER, 3\r
+.set SCSI_SEL_ISR__INTC_PRIOR_NUM, 7\r
+.set SCSI_SEL_ISR__INTC_PRIOR_REG, CYREG_NVIC_PRI_3\r
+.set SCSI_SEL_ISR__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
+.set SCSI_SEL_ISR__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
+\r
+/* SCSI_Filtered */\r
+.set SCSI_Filtered_sts_sts_reg__0__MASK, 0x01\r
+.set SCSI_Filtered_sts_sts_reg__0__POS, 0\r
+.set SCSI_Filtered_sts_sts_reg__1__MASK, 0x02\r
+.set SCSI_Filtered_sts_sts_reg__1__POS, 1\r
+.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB02_03_ACTL\r
+.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB02_03_ST\r
+.set SCSI_Filtered_sts_sts_reg__2__MASK, 0x04\r
+.set SCSI_Filtered_sts_sts_reg__2__POS, 2\r
+.set SCSI_Filtered_sts_sts_reg__3__MASK, 0x08\r
+.set SCSI_Filtered_sts_sts_reg__3__POS, 3\r
+.set SCSI_Filtered_sts_sts_reg__4__MASK, 0x10\r
+.set SCSI_Filtered_sts_sts_reg__4__POS, 4\r
+.set SCSI_Filtered_sts_sts_reg__MASK, 0x1F\r
+.set SCSI_Filtered_sts_sts_reg__MASK_REG, CYREG_B0_UDB02_MSK\r
+.set SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB02_ACTL\r
+.set SCSI_Filtered_sts_sts_reg__STATUS_REG, CYREG_B0_UDB02_ST\r
+\r
+/* SCSI_CTL_PHASE */\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK, 0x01\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS, 0\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK, 0x02\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS, 1\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB05_06_ACTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB05_06_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB05_06_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB05_06_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB05_06_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB05_06_MSK\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB05_06_MSK\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB05_06_MSK\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB05_06_MSK\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK, 0x04\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS, 2\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB05_ACTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB05_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB05_ST_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB05_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB05_ST_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK, 0x07\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB05_MSK_ACTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB05_MSK_ACTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB05_MSK\r
+\r
+/* SCSI_Glitch_Ctl */\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK, 0x01\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS, 0\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB07_08_ACTL\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB07_08_CTL\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB07_08_CTL\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB07_08_CTL\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB07_08_CTL\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB07_08_MSK\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB07_08_MSK\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB07_08_MSK\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB07_08_MSK\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB07_ACTL\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB07_CTL\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB07_ST_CTL\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB07_CTL\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB07_ST_CTL\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK, 0x01\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB07_MSK_ACTL\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB07_MSK_ACTL\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB07_MSK\r
+\r
+/* SCSI_Parity_Error */\r
+.set SCSI_Parity_Error_sts_sts_reg__0__MASK, 0x01\r
+.set SCSI_Parity_Error_sts_sts_reg__0__POS, 0\r
+.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB01_02_ACTL\r
+.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB01_02_ST\r
+.set SCSI_Parity_Error_sts_sts_reg__MASK, 0x01\r
+.set SCSI_Parity_Error_sts_sts_reg__MASK_REG, CYREG_B0_UDB01_MSK\r
+.set SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB01_ACTL\r
+.set SCSI_Parity_Error_sts_sts_reg__STATUS_REG, CYREG_B0_UDB01_ST\r
+\r
/* Miscellaneous */\r
.set BCLK__BUS_CLK__HZ, 50000000\r
.set BCLK__BUS_CLK__KHZ, 50000\r
.set BCLK__BUS_CLK__MHZ, 50\r
.set CYDEV_CHIP_DIE_LEOPARD, 1\r
-.set CYDEV_CHIP_DIE_PSOC4A, 16\r
+.set CYDEV_CHIP_DIE_PSOC4A, 18\r
.set CYDEV_CHIP_DIE_PSOC5LP, 2\r
.set CYDEV_CHIP_DIE_PSOC5TM, 3\r
.set CYDEV_CHIP_DIE_TMA4, 4\r
.set CYDEV_CHIP_FAMILY_USED, CYDEV_CHIP_FAMILY_PSOC5\r
.set CYDEV_CHIP_JTAG_ID, 0x2E133069\r
.set CYDEV_CHIP_MEMBER_3A, 1\r
-.set CYDEV_CHIP_MEMBER_4A, 16\r
-.set CYDEV_CHIP_MEMBER_4D, 12\r
+.set CYDEV_CHIP_MEMBER_4A, 18\r
+.set CYDEV_CHIP_MEMBER_4D, 13\r
.set CYDEV_CHIP_MEMBER_4E, 6\r
-.set CYDEV_CHIP_MEMBER_4F, 17\r
+.set CYDEV_CHIP_MEMBER_4F, 19\r
.set CYDEV_CHIP_MEMBER_4G, 4\r
-.set CYDEV_CHIP_MEMBER_4H, 15\r
-.set CYDEV_CHIP_MEMBER_4I, 21\r
-.set CYDEV_CHIP_MEMBER_4J, 13\r
-.set CYDEV_CHIP_MEMBER_4K, 14\r
-.set CYDEV_CHIP_MEMBER_4L, 20\r
-.set CYDEV_CHIP_MEMBER_4M, 19\r
-.set CYDEV_CHIP_MEMBER_4N, 9\r
+.set CYDEV_CHIP_MEMBER_4H, 17\r
+.set CYDEV_CHIP_MEMBER_4I, 23\r
+.set CYDEV_CHIP_MEMBER_4J, 14\r
+.set CYDEV_CHIP_MEMBER_4K, 15\r
+.set CYDEV_CHIP_MEMBER_4L, 22\r
+.set CYDEV_CHIP_MEMBER_4M, 21\r
+.set CYDEV_CHIP_MEMBER_4N, 10\r
.set CYDEV_CHIP_MEMBER_4O, 7\r
-.set CYDEV_CHIP_MEMBER_4P, 18\r
-.set CYDEV_CHIP_MEMBER_4Q, 11\r
+.set CYDEV_CHIP_MEMBER_4P, 20\r
+.set CYDEV_CHIP_MEMBER_4Q, 12\r
.set CYDEV_CHIP_MEMBER_4R, 8\r
-.set CYDEV_CHIP_MEMBER_4S, 10\r
+.set CYDEV_CHIP_MEMBER_4S, 11\r
+.set CYDEV_CHIP_MEMBER_4T, 9\r
.set CYDEV_CHIP_MEMBER_4U, 5\r
+.set CYDEV_CHIP_MEMBER_4V, 16\r
.set CYDEV_CHIP_MEMBER_5A, 3\r
.set CYDEV_CHIP_MEMBER_5B, 2\r
-.set CYDEV_CHIP_MEMBER_6A, 22\r
-.set CYDEV_CHIP_MEMBER_FM3, 26\r
-.set CYDEV_CHIP_MEMBER_FM4, 27\r
-.set CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE1, 23\r
-.set CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE2, 24\r
-.set CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE3, 25\r
+.set CYDEV_CHIP_MEMBER_6A, 24\r
+.set CYDEV_CHIP_MEMBER_FM3, 28\r
+.set CYDEV_CHIP_MEMBER_FM4, 29\r
+.set CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE1, 25\r
+.set CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE2, 26\r
+.set CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE3, 27\r
.set CYDEV_CHIP_MEMBER_UNKNOWN, 0\r
.set CYDEV_CHIP_MEMBER_USED, CYDEV_CHIP_MEMBER_5B\r
.set CYDEV_CHIP_DIE_EXPECT, CYDEV_CHIP_MEMBER_USED\r
.set CYDEV_CHIP_REVISION_4A_ES0, 17\r
.set CYDEV_CHIP_REVISION_4A_PRODUCTION, 17\r
.set CYDEV_CHIP_REVISION_4D_PRODUCTION, 0\r
+.set CYDEV_CHIP_REVISION_4E_CCG2_NO_USBPD, 0\r
.set CYDEV_CHIP_REVISION_4E_PRODUCTION, 0\r
.set CYDEV_CHIP_REVISION_4F_PRODUCTION, 0\r
.set CYDEV_CHIP_REVISION_4F_PRODUCTION_256DMA, 0\r
.set CYDEV_CHIP_REVISION_4Q_PRODUCTION, 0\r
.set CYDEV_CHIP_REVISION_4R_PRODUCTION, 0\r
.set CYDEV_CHIP_REVISION_4S_PRODUCTION, 0\r
+.set CYDEV_CHIP_REVISION_4T_PRODUCTION, 0\r
.set CYDEV_CHIP_REVISION_4U_PRODUCTION, 0\r
+.set CYDEV_CHIP_REVISION_4V_PRODUCTION, 0\r
.set CYDEV_CHIP_REVISION_5A_ES0, 0\r
.set CYDEV_CHIP_REVISION_5A_ES1, 1\r
.set CYDEV_CHIP_REVISION_5A_PRODUCTION, 1\r
.set CYDEV_CHIP_REVISION_5B_ES0, 0\r
.set CYDEV_CHIP_REVISION_5B_PRODUCTION, 0\r
-.set CYDEV_CHIP_REVISION_6A_NO_UDB, 0\r
-.set CYDEV_CHIP_REVISION_6A_PRODUCTION, 0\r
+.set CYDEV_CHIP_REVISION_6A_ES, 17\r
+.set CYDEV_CHIP_REVISION_6A_NO_UDB, 33\r
+.set CYDEV_CHIP_REVISION_6A_PRODUCTION, 33\r
.set CYDEV_CHIP_REVISION_FM3_PRODUCTION, 0\r
.set CYDEV_CHIP_REVISION_FM4_PRODUCTION, 0\r
.set CYDEV_CHIP_REVISION_PDL_FM0P_TYPE1_PRODUCTION, 0\r
;\r
; File Name: cyfitteriar.inc\r
; \r
-; PSoC Creator 4.1\r
+; PSoC Creator 4.2\r
;\r
; Description:\r
; \r
;\r
;-------------------------------------------------------------------------------\r
-; Copyright (c) 2007-2017 Cypress Semiconductor. All rights reserved.\r
+; Copyright (c) 2007-2018 Cypress Semiconductor. All rights reserved.\r
; You may use this file only in accordance with the license, terms, conditions, \r
; disclaimers, and limitations in the end user license agreement accompanying \r
; the software package with which this file was provided.\r
INCLUDE cydeviceiar.inc\r
INCLUDE cydeviceiar_trm.inc\r
\r
-/* Debug_Timer_Interrupt */\r
-Debug_Timer_Interrupt__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
-Debug_Timer_Interrupt__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
-Debug_Timer_Interrupt__INTC_MASK EQU 0x01\r
-Debug_Timer_Interrupt__INTC_NUMBER EQU 0\r
-Debug_Timer_Interrupt__INTC_PRIOR_NUM EQU 7\r
-Debug_Timer_Interrupt__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_0\r
-Debug_Timer_Interrupt__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
-Debug_Timer_Interrupt__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
-\r
-/* Debug_Timer_TimerHW */\r
-Debug_Timer_TimerHW__CAP0 EQU CYREG_TMR0_CAP0\r
-Debug_Timer_TimerHW__CAP1 EQU CYREG_TMR0_CAP1\r
-Debug_Timer_TimerHW__CFG0 EQU CYREG_TMR0_CFG0\r
-Debug_Timer_TimerHW__CFG1 EQU CYREG_TMR0_CFG1\r
-Debug_Timer_TimerHW__CFG2 EQU CYREG_TMR0_CFG2\r
-Debug_Timer_TimerHW__CNT_CMP0 EQU CYREG_TMR0_CNT_CMP0\r
-Debug_Timer_TimerHW__CNT_CMP1 EQU CYREG_TMR0_CNT_CMP1\r
-Debug_Timer_TimerHW__PER0 EQU CYREG_TMR0_PER0\r
-Debug_Timer_TimerHW__PER1 EQU CYREG_TMR0_PER1\r
-Debug_Timer_TimerHW__PM_ACT_CFG EQU CYREG_PM_ACT_CFG3\r
-Debug_Timer_TimerHW__PM_ACT_MSK EQU 0x01\r
-Debug_Timer_TimerHW__PM_STBY_CFG EQU CYREG_PM_STBY_CFG3\r
-Debug_Timer_TimerHW__PM_STBY_MSK EQU 0x01\r
-Debug_Timer_TimerHW__RT0 EQU CYREG_TMR0_RT0\r
-Debug_Timer_TimerHW__RT1 EQU CYREG_TMR0_RT1\r
-Debug_Timer_TimerHW__SR0 EQU CYREG_TMR0_SR0\r
-\r
/* LED1 */\r
LED1__0__INTTYPE EQU CYREG_PICU12_INTTYPE3\r
LED1__0__MASK EQU 0x08\r
LED1__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ\r
LED1__SLW EQU CYREG_PRT12_SLW\r
\r
-/* SCSI_CLK */\r
-SCSI_CLK__CFG0 EQU CYREG_CLKDIST_DCFG1_CFG0\r
-SCSI_CLK__CFG1 EQU CYREG_CLKDIST_DCFG1_CFG1\r
-SCSI_CLK__CFG2 EQU CYREG_CLKDIST_DCFG1_CFG2\r
-SCSI_CLK__CFG2_SRC_SEL_MASK EQU 0x07\r
-SCSI_CLK__INDEX EQU 0x01\r
-SCSI_CLK__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2\r
-SCSI_CLK__PM_ACT_MSK EQU 0x02\r
-SCSI_CLK__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2\r
-SCSI_CLK__PM_STBY_MSK EQU 0x02\r
-\r
-/* SCSI_CTL_PHASE */\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS EQU 0\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK EQU 0x02\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS EQU 1\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB05_06_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB05_06_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB05_06_MSK\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB05_06_MSK\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK EQU 0x04\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS EQU 2\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB05_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB05_ST_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB05_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB05_ST_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__MASK EQU 0x07\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB05_MSK\r
-\r
-/* SCSI_Filtered */\r
-SCSI_Filtered_sts_sts_reg__0__MASK EQU 0x01\r
-SCSI_Filtered_sts_sts_reg__0__POS EQU 0\r
-SCSI_Filtered_sts_sts_reg__1__MASK EQU 0x02\r
-SCSI_Filtered_sts_sts_reg__1__POS EQU 1\r
-SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL\r
-SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB02_03_ST\r
-SCSI_Filtered_sts_sts_reg__2__MASK EQU 0x04\r
-SCSI_Filtered_sts_sts_reg__2__POS EQU 2\r
-SCSI_Filtered_sts_sts_reg__3__MASK EQU 0x08\r
-SCSI_Filtered_sts_sts_reg__3__POS EQU 3\r
-SCSI_Filtered_sts_sts_reg__4__MASK EQU 0x10\r
-SCSI_Filtered_sts_sts_reg__4__POS EQU 4\r
-SCSI_Filtered_sts_sts_reg__MASK EQU 0x1F\r
-SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB02_MSK\r
-SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL\r
-SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB02_ST\r
+/* SD_CD */\r
+SD_CD__0__INTTYPE EQU CYREG_PICU3_INTTYPE6\r
+SD_CD__0__MASK EQU 0x40\r
+SD_CD__0__PC EQU CYREG_PRT3_PC6\r
+SD_CD__0__PORT EQU 3\r
+SD_CD__0__SHIFT EQU 6\r
+SD_CD__AG EQU CYREG_PRT3_AG\r
+SD_CD__AMUX EQU CYREG_PRT3_AMUX\r
+SD_CD__BIE EQU CYREG_PRT3_BIE\r
+SD_CD__BIT_MASK EQU CYREG_PRT3_BIT_MASK\r
+SD_CD__BYP EQU CYREG_PRT3_BYP\r
+SD_CD__CTL EQU CYREG_PRT3_CTL\r
+SD_CD__DM0 EQU CYREG_PRT3_DM0\r
+SD_CD__DM1 EQU CYREG_PRT3_DM1\r
+SD_CD__DM2 EQU CYREG_PRT3_DM2\r
+SD_CD__DR EQU CYREG_PRT3_DR\r
+SD_CD__INP_DIS EQU CYREG_PRT3_INP_DIS\r
+SD_CD__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE\r
+SD_CD__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG\r
+SD_CD__LCD_EN EQU CYREG_PRT3_LCD_EN\r
+SD_CD__MASK EQU 0x40\r
+SD_CD__PORT EQU 3\r
+SD_CD__PRT EQU CYREG_PRT3_PRT\r
+SD_CD__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL\r
+SD_CD__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN\r
+SD_CD__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0\r
+SD_CD__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1\r
+SD_CD__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0\r
+SD_CD__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1\r
+SD_CD__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT\r
+SD_CD__PS EQU CYREG_PRT3_PS\r
+SD_CD__SHIFT EQU 6\r
+SD_CD__SLW EQU CYREG_PRT3_SLW\r
\r
-/* SCSI_Glitch_Ctl */\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS EQU 0\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB07_08_CTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB07_08_CTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB07_08_CTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB07_08_CTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB07_08_MSK\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB07_08_MSK\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB07_08_MSK\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB07_08_MSK\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB07_CTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB07_ST_CTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB07_CTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB07_ST_CTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK EQU 0x01\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB07_MSK\r
-\r
-/* SCSI_In */\r
-SCSI_In__0__AG EQU CYREG_PRT2_AG\r
-SCSI_In__0__AMUX EQU CYREG_PRT2_AMUX\r
-SCSI_In__0__BIE EQU CYREG_PRT2_BIE\r
-SCSI_In__0__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
-SCSI_In__0__BYP EQU CYREG_PRT2_BYP\r
-SCSI_In__0__CTL EQU CYREG_PRT2_CTL\r
-SCSI_In__0__DM0 EQU CYREG_PRT2_DM0\r
-SCSI_In__0__DM1 EQU CYREG_PRT2_DM1\r
-SCSI_In__0__DM2 EQU CYREG_PRT2_DM2\r
-SCSI_In__0__DR EQU CYREG_PRT2_DR\r
-SCSI_In__0__INP_DIS EQU CYREG_PRT2_INP_DIS\r
-SCSI_In__0__INTTYPE EQU CYREG_PICU2_INTTYPE0\r
-SCSI_In__0__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
-SCSI_In__0__LCD_EN EQU CYREG_PRT2_LCD_EN\r
-SCSI_In__0__MASK EQU 0x01\r
-SCSI_In__0__PC EQU CYREG_PRT2_PC0\r
-SCSI_In__0__PORT EQU 2\r
-SCSI_In__0__PRT EQU CYREG_PRT2_PRT\r
-SCSI_In__0__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
-SCSI_In__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
-SCSI_In__0__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
-SCSI_In__0__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
-SCSI_In__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
-SCSI_In__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
-SCSI_In__0__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
-SCSI_In__0__PS EQU CYREG_PRT2_PS\r
-SCSI_In__0__SHIFT EQU 0\r
-SCSI_In__0__SLW EQU CYREG_PRT2_SLW\r
-SCSI_In__1__AG EQU CYREG_PRT6_AG\r
-SCSI_In__1__AMUX EQU CYREG_PRT6_AMUX\r
-SCSI_In__1__BIE EQU CYREG_PRT6_BIE\r
-SCSI_In__1__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
-SCSI_In__1__BYP EQU CYREG_PRT6_BYP\r
-SCSI_In__1__CTL EQU CYREG_PRT6_CTL\r
-SCSI_In__1__DM0 EQU CYREG_PRT6_DM0\r
-SCSI_In__1__DM1 EQU CYREG_PRT6_DM1\r
-SCSI_In__1__DM2 EQU CYREG_PRT6_DM2\r
-SCSI_In__1__DR EQU CYREG_PRT6_DR\r
-SCSI_In__1__INP_DIS EQU CYREG_PRT6_INP_DIS\r
-SCSI_In__1__INTTYPE EQU CYREG_PICU6_INTTYPE7\r
-SCSI_In__1__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
-SCSI_In__1__LCD_EN EQU CYREG_PRT6_LCD_EN\r
-SCSI_In__1__MASK EQU 0x80\r
-SCSI_In__1__PC EQU CYREG_PRT6_PC7\r
-SCSI_In__1__PORT EQU 6\r
-SCSI_In__1__PRT EQU CYREG_PRT6_PRT\r
-SCSI_In__1__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
-SCSI_In__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
-SCSI_In__1__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
-SCSI_In__1__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
-SCSI_In__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
-SCSI_In__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
-SCSI_In__1__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
-SCSI_In__1__PS EQU CYREG_PRT6_PS\r
-SCSI_In__1__SHIFT EQU 7\r
-SCSI_In__1__SLW EQU CYREG_PRT6_SLW\r
-SCSI_In__2__AG EQU CYREG_PRT5_AG\r
-SCSI_In__2__AMUX EQU CYREG_PRT5_AMUX\r
-SCSI_In__2__BIE EQU CYREG_PRT5_BIE\r
-SCSI_In__2__BIT_MASK EQU CYREG_PRT5_BIT_MASK\r
-SCSI_In__2__BYP EQU CYREG_PRT5_BYP\r
-SCSI_In__2__CTL EQU CYREG_PRT5_CTL\r
-SCSI_In__2__DM0 EQU CYREG_PRT5_DM0\r
-SCSI_In__2__DM1 EQU CYREG_PRT5_DM1\r
-SCSI_In__2__DM2 EQU CYREG_PRT5_DM2\r
-SCSI_In__2__DR EQU CYREG_PRT5_DR\r
-SCSI_In__2__INP_DIS EQU CYREG_PRT5_INP_DIS\r
-SCSI_In__2__INTTYPE EQU CYREG_PICU5_INTTYPE1\r
-SCSI_In__2__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG\r
-SCSI_In__2__LCD_EN EQU CYREG_PRT5_LCD_EN\r
-SCSI_In__2__MASK EQU 0x02\r
-SCSI_In__2__PC EQU CYREG_PRT5_PC1\r
-SCSI_In__2__PORT EQU 5\r
-SCSI_In__2__PRT EQU CYREG_PRT5_PRT\r
-SCSI_In__2__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL\r
-SCSI_In__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN\r
-SCSI_In__2__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0\r
-SCSI_In__2__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1\r
-SCSI_In__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0\r
-SCSI_In__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1\r
-SCSI_In__2__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT\r
-SCSI_In__2__PS EQU CYREG_PRT5_PS\r
-SCSI_In__2__SHIFT EQU 1\r
-SCSI_In__2__SLW EQU CYREG_PRT5_SLW\r
-SCSI_In__3__AG EQU CYREG_PRT5_AG\r
-SCSI_In__3__AMUX EQU CYREG_PRT5_AMUX\r
-SCSI_In__3__BIE EQU CYREG_PRT5_BIE\r
-SCSI_In__3__BIT_MASK EQU CYREG_PRT5_BIT_MASK\r
-SCSI_In__3__BYP EQU CYREG_PRT5_BYP\r
-SCSI_In__3__CTL EQU CYREG_PRT5_CTL\r
-SCSI_In__3__DM0 EQU CYREG_PRT5_DM0\r
-SCSI_In__3__DM1 EQU CYREG_PRT5_DM1\r
-SCSI_In__3__DM2 EQU CYREG_PRT5_DM2\r
-SCSI_In__3__DR EQU CYREG_PRT5_DR\r
-SCSI_In__3__INP_DIS EQU CYREG_PRT5_INP_DIS\r
-SCSI_In__3__INTTYPE EQU CYREG_PICU5_INTTYPE2\r
-SCSI_In__3__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG\r
-SCSI_In__3__LCD_EN EQU CYREG_PRT5_LCD_EN\r
-SCSI_In__3__MASK EQU 0x04\r
-SCSI_In__3__PC EQU CYREG_PRT5_PC2\r
-SCSI_In__3__PORT EQU 5\r
-SCSI_In__3__PRT EQU CYREG_PRT5_PRT\r
-SCSI_In__3__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL\r
-SCSI_In__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN\r
-SCSI_In__3__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0\r
-SCSI_In__3__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1\r
-SCSI_In__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0\r
-SCSI_In__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1\r
-SCSI_In__3__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT\r
-SCSI_In__3__PS EQU CYREG_PRT5_PS\r
-SCSI_In__3__SHIFT EQU 2\r
-SCSI_In__3__SLW EQU CYREG_PRT5_SLW\r
-SCSI_In__4__AG EQU CYREG_PRT5_AG\r
-SCSI_In__4__AMUX EQU CYREG_PRT5_AMUX\r
-SCSI_In__4__BIE EQU CYREG_PRT5_BIE\r
-SCSI_In__4__BIT_MASK EQU CYREG_PRT5_BIT_MASK\r
-SCSI_In__4__BYP EQU CYREG_PRT5_BYP\r
-SCSI_In__4__CTL EQU CYREG_PRT5_CTL\r
-SCSI_In__4__DM0 EQU CYREG_PRT5_DM0\r
-SCSI_In__4__DM1 EQU CYREG_PRT5_DM1\r
-SCSI_In__4__DM2 EQU CYREG_PRT5_DM2\r
-SCSI_In__4__DR EQU CYREG_PRT5_DR\r
-SCSI_In__4__INP_DIS EQU CYREG_PRT5_INP_DIS\r
-SCSI_In__4__INTTYPE EQU CYREG_PICU5_INTTYPE3\r
-SCSI_In__4__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG\r
-SCSI_In__4__LCD_EN EQU CYREG_PRT5_LCD_EN\r
-SCSI_In__4__MASK EQU 0x08\r
-SCSI_In__4__PC EQU CYREG_PRT5_PC3\r
-SCSI_In__4__PORT EQU 5\r
-SCSI_In__4__PRT EQU CYREG_PRT5_PRT\r
-SCSI_In__4__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL\r
-SCSI_In__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN\r
-SCSI_In__4__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0\r
-SCSI_In__4__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1\r
-SCSI_In__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0\r
-SCSI_In__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1\r
-SCSI_In__4__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT\r
-SCSI_In__4__PS EQU CYREG_PRT5_PS\r
-SCSI_In__4__SHIFT EQU 3\r
-SCSI_In__4__SLW EQU CYREG_PRT5_SLW\r
-SCSI_In__CD__AG EQU CYREG_PRT5_AG\r
-SCSI_In__CD__AMUX EQU CYREG_PRT5_AMUX\r
-SCSI_In__CD__BIE EQU CYREG_PRT5_BIE\r
-SCSI_In__CD__BIT_MASK EQU CYREG_PRT5_BIT_MASK\r
-SCSI_In__CD__BYP EQU CYREG_PRT5_BYP\r
-SCSI_In__CD__CTL EQU CYREG_PRT5_CTL\r
-SCSI_In__CD__DM0 EQU CYREG_PRT5_DM0\r
-SCSI_In__CD__DM1 EQU CYREG_PRT5_DM1\r
-SCSI_In__CD__DM2 EQU CYREG_PRT5_DM2\r
-SCSI_In__CD__DR EQU CYREG_PRT5_DR\r
-SCSI_In__CD__INP_DIS EQU CYREG_PRT5_INP_DIS\r
-SCSI_In__CD__INTTYPE EQU CYREG_PICU5_INTTYPE1\r
-SCSI_In__CD__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG\r
-SCSI_In__CD__LCD_EN EQU CYREG_PRT5_LCD_EN\r
-SCSI_In__CD__MASK EQU 0x02\r
-SCSI_In__CD__PC EQU CYREG_PRT5_PC1\r
-SCSI_In__CD__PORT EQU 5\r
-SCSI_In__CD__PRT EQU CYREG_PRT5_PRT\r
-SCSI_In__CD__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL\r
-SCSI_In__CD__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN\r
-SCSI_In__CD__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0\r
-SCSI_In__CD__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1\r
-SCSI_In__CD__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0\r
-SCSI_In__CD__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1\r
-SCSI_In__CD__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT\r
-SCSI_In__CD__PS EQU CYREG_PRT5_PS\r
-SCSI_In__CD__SHIFT EQU 1\r
-SCSI_In__CD__SLW EQU CYREG_PRT5_SLW\r
-SCSI_In__DBP__AG EQU CYREG_PRT2_AG\r
-SCSI_In__DBP__AMUX EQU CYREG_PRT2_AMUX\r
-SCSI_In__DBP__BIE EQU CYREG_PRT2_BIE\r
-SCSI_In__DBP__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
-SCSI_In__DBP__BYP EQU CYREG_PRT2_BYP\r
-SCSI_In__DBP__CTL EQU CYREG_PRT2_CTL\r
-SCSI_In__DBP__DM0 EQU CYREG_PRT2_DM0\r
-SCSI_In__DBP__DM1 EQU CYREG_PRT2_DM1\r
-SCSI_In__DBP__DM2 EQU CYREG_PRT2_DM2\r
-SCSI_In__DBP__DR EQU CYREG_PRT2_DR\r
-SCSI_In__DBP__INP_DIS EQU CYREG_PRT2_INP_DIS\r
-SCSI_In__DBP__INTTYPE EQU CYREG_PICU2_INTTYPE0\r
-SCSI_In__DBP__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
-SCSI_In__DBP__LCD_EN EQU CYREG_PRT2_LCD_EN\r
-SCSI_In__DBP__MASK EQU 0x01\r
-SCSI_In__DBP__PC EQU CYREG_PRT2_PC0\r
-SCSI_In__DBP__PORT EQU 2\r
-SCSI_In__DBP__PRT EQU CYREG_PRT2_PRT\r
-SCSI_In__DBP__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
-SCSI_In__DBP__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
-SCSI_In__DBP__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
-SCSI_In__DBP__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
-SCSI_In__DBP__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
-SCSI_In__DBP__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
-SCSI_In__DBP__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
-SCSI_In__DBP__PS EQU CYREG_PRT2_PS\r
-SCSI_In__DBP__SHIFT EQU 0\r
-SCSI_In__DBP__SLW EQU CYREG_PRT2_SLW\r
-SCSI_In__IO__AG EQU CYREG_PRT5_AG\r
-SCSI_In__IO__AMUX EQU CYREG_PRT5_AMUX\r
-SCSI_In__IO__BIE EQU CYREG_PRT5_BIE\r
-SCSI_In__IO__BIT_MASK EQU CYREG_PRT5_BIT_MASK\r
-SCSI_In__IO__BYP EQU CYREG_PRT5_BYP\r
-SCSI_In__IO__CTL EQU CYREG_PRT5_CTL\r
-SCSI_In__IO__DM0 EQU CYREG_PRT5_DM0\r
-SCSI_In__IO__DM1 EQU CYREG_PRT5_DM1\r
-SCSI_In__IO__DM2 EQU CYREG_PRT5_DM2\r
-SCSI_In__IO__DR EQU CYREG_PRT5_DR\r
-SCSI_In__IO__INP_DIS EQU CYREG_PRT5_INP_DIS\r
-SCSI_In__IO__INTTYPE EQU CYREG_PICU5_INTTYPE3\r
-SCSI_In__IO__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG\r
-SCSI_In__IO__LCD_EN EQU CYREG_PRT5_LCD_EN\r
-SCSI_In__IO__MASK EQU 0x08\r
-SCSI_In__IO__PC EQU CYREG_PRT5_PC3\r
-SCSI_In__IO__PORT EQU 5\r
-SCSI_In__IO__PRT EQU CYREG_PRT5_PRT\r
-SCSI_In__IO__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL\r
-SCSI_In__IO__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN\r
-SCSI_In__IO__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0\r
-SCSI_In__IO__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1\r
-SCSI_In__IO__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0\r
-SCSI_In__IO__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1\r
-SCSI_In__IO__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT\r
-SCSI_In__IO__PS EQU CYREG_PRT5_PS\r
-SCSI_In__IO__SHIFT EQU 3\r
-SCSI_In__IO__SLW EQU CYREG_PRT5_SLW\r
-SCSI_In__MSG__AG EQU CYREG_PRT6_AG\r
-SCSI_In__MSG__AMUX EQU CYREG_PRT6_AMUX\r
-SCSI_In__MSG__BIE EQU CYREG_PRT6_BIE\r
-SCSI_In__MSG__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
-SCSI_In__MSG__BYP EQU CYREG_PRT6_BYP\r
-SCSI_In__MSG__CTL EQU CYREG_PRT6_CTL\r
-SCSI_In__MSG__DM0 EQU CYREG_PRT6_DM0\r
-SCSI_In__MSG__DM1 EQU CYREG_PRT6_DM1\r
-SCSI_In__MSG__DM2 EQU CYREG_PRT6_DM2\r
-SCSI_In__MSG__DR EQU CYREG_PRT6_DR\r
-SCSI_In__MSG__INP_DIS EQU CYREG_PRT6_INP_DIS\r
-SCSI_In__MSG__INTTYPE EQU CYREG_PICU6_INTTYPE7\r
-SCSI_In__MSG__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
-SCSI_In__MSG__LCD_EN EQU CYREG_PRT6_LCD_EN\r
-SCSI_In__MSG__MASK EQU 0x80\r
-SCSI_In__MSG__PC EQU CYREG_PRT6_PC7\r
-SCSI_In__MSG__PORT EQU 6\r
-SCSI_In__MSG__PRT EQU CYREG_PRT6_PRT\r
-SCSI_In__MSG__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
-SCSI_In__MSG__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
-SCSI_In__MSG__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
-SCSI_In__MSG__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
-SCSI_In__MSG__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
-SCSI_In__MSG__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
-SCSI_In__MSG__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
-SCSI_In__MSG__PS EQU CYREG_PRT6_PS\r
-SCSI_In__MSG__SHIFT EQU 7\r
-SCSI_In__MSG__SLW EQU CYREG_PRT6_SLW\r
-SCSI_In__REQ__AG EQU CYREG_PRT5_AG\r
-SCSI_In__REQ__AMUX EQU CYREG_PRT5_AMUX\r
-SCSI_In__REQ__BIE EQU CYREG_PRT5_BIE\r
-SCSI_In__REQ__BIT_MASK EQU CYREG_PRT5_BIT_MASK\r
-SCSI_In__REQ__BYP EQU CYREG_PRT5_BYP\r
-SCSI_In__REQ__CTL EQU CYREG_PRT5_CTL\r
-SCSI_In__REQ__DM0 EQU CYREG_PRT5_DM0\r
-SCSI_In__REQ__DM1 EQU CYREG_PRT5_DM1\r
-SCSI_In__REQ__DM2 EQU CYREG_PRT5_DM2\r
-SCSI_In__REQ__DR EQU CYREG_PRT5_DR\r
-SCSI_In__REQ__INP_DIS EQU CYREG_PRT5_INP_DIS\r
-SCSI_In__REQ__INTTYPE EQU CYREG_PICU5_INTTYPE2\r
-SCSI_In__REQ__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG\r
-SCSI_In__REQ__LCD_EN EQU CYREG_PRT5_LCD_EN\r
-SCSI_In__REQ__MASK EQU 0x04\r
-SCSI_In__REQ__PC EQU CYREG_PRT5_PC2\r
-SCSI_In__REQ__PORT EQU 5\r
-SCSI_In__REQ__PRT EQU CYREG_PRT5_PRT\r
-SCSI_In__REQ__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL\r
-SCSI_In__REQ__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN\r
-SCSI_In__REQ__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0\r
-SCSI_In__REQ__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1\r
-SCSI_In__REQ__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0\r
-SCSI_In__REQ__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1\r
-SCSI_In__REQ__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT\r
-SCSI_In__REQ__PS EQU CYREG_PRT5_PS\r
-SCSI_In__REQ__SHIFT EQU 2\r
-SCSI_In__REQ__SLW EQU CYREG_PRT5_SLW\r
-SCSI_In_DBx__0__AG EQU CYREG_PRT12_AG\r
-SCSI_In_DBx__0__BIE EQU CYREG_PRT12_BIE\r
-SCSI_In_DBx__0__BIT_MASK EQU CYREG_PRT12_BIT_MASK\r
-SCSI_In_DBx__0__BYP EQU CYREG_PRT12_BYP\r
-SCSI_In_DBx__0__DM0 EQU CYREG_PRT12_DM0\r
-SCSI_In_DBx__0__DM1 EQU CYREG_PRT12_DM1\r
-SCSI_In_DBx__0__DM2 EQU CYREG_PRT12_DM2\r
-SCSI_In_DBx__0__DR EQU CYREG_PRT12_DR\r
-SCSI_In_DBx__0__INP_DIS EQU CYREG_PRT12_INP_DIS\r
-SCSI_In_DBx__0__INTTYPE EQU CYREG_PICU12_INTTYPE4\r
-SCSI_In_DBx__0__MASK EQU 0x10\r
-SCSI_In_DBx__0__PC EQU CYREG_PRT12_PC4\r
-SCSI_In_DBx__0__PORT EQU 12\r
-SCSI_In_DBx__0__PRT EQU CYREG_PRT12_PRT\r
-SCSI_In_DBx__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN\r
-SCSI_In_DBx__0__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0\r
-SCSI_In_DBx__0__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1\r
-SCSI_In_DBx__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0\r
-SCSI_In_DBx__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1\r
-SCSI_In_DBx__0__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT\r
-SCSI_In_DBx__0__PS EQU CYREG_PRT12_PS\r
-SCSI_In_DBx__0__SHIFT EQU 4\r
-SCSI_In_DBx__0__SIO_CFG EQU CYREG_PRT12_SIO_CFG\r
-SCSI_In_DBx__0__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF\r
-SCSI_In_DBx__0__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN\r
-SCSI_In_DBx__0__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ\r
-SCSI_In_DBx__0__SLW EQU CYREG_PRT12_SLW\r
-SCSI_In_DBx__1__AG EQU CYREG_PRT2_AG\r
-SCSI_In_DBx__1__AMUX EQU CYREG_PRT2_AMUX\r
-SCSI_In_DBx__1__BIE EQU CYREG_PRT2_BIE\r
-SCSI_In_DBx__1__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
-SCSI_In_DBx__1__BYP EQU CYREG_PRT2_BYP\r
-SCSI_In_DBx__1__CTL EQU CYREG_PRT2_CTL\r
-SCSI_In_DBx__1__DM0 EQU CYREG_PRT2_DM0\r
-SCSI_In_DBx__1__DM1 EQU CYREG_PRT2_DM1\r
-SCSI_In_DBx__1__DM2 EQU CYREG_PRT2_DM2\r
-SCSI_In_DBx__1__DR EQU CYREG_PRT2_DR\r
-SCSI_In_DBx__1__INP_DIS EQU CYREG_PRT2_INP_DIS\r
-SCSI_In_DBx__1__INTTYPE EQU CYREG_PICU2_INTTYPE7\r
-SCSI_In_DBx__1__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
-SCSI_In_DBx__1__LCD_EN EQU CYREG_PRT2_LCD_EN\r
-SCSI_In_DBx__1__MASK EQU 0x80\r
-SCSI_In_DBx__1__PC EQU CYREG_PRT2_PC7\r
-SCSI_In_DBx__1__PORT EQU 2\r
-SCSI_In_DBx__1__PRT EQU CYREG_PRT2_PRT\r
-SCSI_In_DBx__1__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
-SCSI_In_DBx__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
-SCSI_In_DBx__1__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
-SCSI_In_DBx__1__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
-SCSI_In_DBx__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
-SCSI_In_DBx__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
-SCSI_In_DBx__1__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
-SCSI_In_DBx__1__PS EQU CYREG_PRT2_PS\r
-SCSI_In_DBx__1__SHIFT EQU 7\r
-SCSI_In_DBx__1__SLW EQU CYREG_PRT2_SLW\r
-SCSI_In_DBx__2__AG EQU CYREG_PRT2_AG\r
-SCSI_In_DBx__2__AMUX EQU CYREG_PRT2_AMUX\r
-SCSI_In_DBx__2__BIE EQU CYREG_PRT2_BIE\r
-SCSI_In_DBx__2__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
-SCSI_In_DBx__2__BYP EQU CYREG_PRT2_BYP\r
-SCSI_In_DBx__2__CTL EQU CYREG_PRT2_CTL\r
-SCSI_In_DBx__2__DM0 EQU CYREG_PRT2_DM0\r
-SCSI_In_DBx__2__DM1 EQU CYREG_PRT2_DM1\r
-SCSI_In_DBx__2__DM2 EQU CYREG_PRT2_DM2\r
-SCSI_In_DBx__2__DR EQU CYREG_PRT2_DR\r
-SCSI_In_DBx__2__INP_DIS EQU CYREG_PRT2_INP_DIS\r
-SCSI_In_DBx__2__INTTYPE EQU CYREG_PICU2_INTTYPE6\r
-SCSI_In_DBx__2__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
-SCSI_In_DBx__2__LCD_EN EQU CYREG_PRT2_LCD_EN\r
-SCSI_In_DBx__2__MASK EQU 0x40\r
-SCSI_In_DBx__2__PC EQU CYREG_PRT2_PC6\r
-SCSI_In_DBx__2__PORT EQU 2\r
-SCSI_In_DBx__2__PRT EQU CYREG_PRT2_PRT\r
-SCSI_In_DBx__2__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
-SCSI_In_DBx__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
-SCSI_In_DBx__2__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
-SCSI_In_DBx__2__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
-SCSI_In_DBx__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
-SCSI_In_DBx__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
-SCSI_In_DBx__2__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
-SCSI_In_DBx__2__PS EQU CYREG_PRT2_PS\r
-SCSI_In_DBx__2__SHIFT EQU 6\r
-SCSI_In_DBx__2__SLW EQU CYREG_PRT2_SLW\r
-SCSI_In_DBx__3__AG EQU CYREG_PRT2_AG\r
-SCSI_In_DBx__3__AMUX EQU CYREG_PRT2_AMUX\r
-SCSI_In_DBx__3__BIE EQU CYREG_PRT2_BIE\r
-SCSI_In_DBx__3__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
-SCSI_In_DBx__3__BYP EQU CYREG_PRT2_BYP\r
-SCSI_In_DBx__3__CTL EQU CYREG_PRT2_CTL\r
-SCSI_In_DBx__3__DM0 EQU CYREG_PRT2_DM0\r
-SCSI_In_DBx__3__DM1 EQU CYREG_PRT2_DM1\r
-SCSI_In_DBx__3__DM2 EQU CYREG_PRT2_DM2\r
-SCSI_In_DBx__3__DR EQU CYREG_PRT2_DR\r
-SCSI_In_DBx__3__INP_DIS EQU CYREG_PRT2_INP_DIS\r
-SCSI_In_DBx__3__INTTYPE EQU CYREG_PICU2_INTTYPE5\r
-SCSI_In_DBx__3__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
-SCSI_In_DBx__3__LCD_EN EQU CYREG_PRT2_LCD_EN\r
-SCSI_In_DBx__3__MASK EQU 0x20\r
-SCSI_In_DBx__3__PC EQU CYREG_PRT2_PC5\r
-SCSI_In_DBx__3__PORT EQU 2\r
-SCSI_In_DBx__3__PRT EQU CYREG_PRT2_PRT\r
-SCSI_In_DBx__3__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
-SCSI_In_DBx__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
-SCSI_In_DBx__3__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
-SCSI_In_DBx__3__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
-SCSI_In_DBx__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
-SCSI_In_DBx__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
-SCSI_In_DBx__3__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
-SCSI_In_DBx__3__PS EQU CYREG_PRT2_PS\r
-SCSI_In_DBx__3__SHIFT EQU 5\r
-SCSI_In_DBx__3__SLW EQU CYREG_PRT2_SLW\r
-SCSI_In_DBx__4__AG EQU CYREG_PRT2_AG\r
-SCSI_In_DBx__4__AMUX EQU CYREG_PRT2_AMUX\r
-SCSI_In_DBx__4__BIE EQU CYREG_PRT2_BIE\r
-SCSI_In_DBx__4__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
-SCSI_In_DBx__4__BYP EQU CYREG_PRT2_BYP\r
-SCSI_In_DBx__4__CTL EQU CYREG_PRT2_CTL\r
-SCSI_In_DBx__4__DM0 EQU CYREG_PRT2_DM0\r
-SCSI_In_DBx__4__DM1 EQU CYREG_PRT2_DM1\r
-SCSI_In_DBx__4__DM2 EQU CYREG_PRT2_DM2\r
-SCSI_In_DBx__4__DR EQU CYREG_PRT2_DR\r
-SCSI_In_DBx__4__INP_DIS EQU CYREG_PRT2_INP_DIS\r
-SCSI_In_DBx__4__INTTYPE EQU CYREG_PICU2_INTTYPE4\r
-SCSI_In_DBx__4__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
-SCSI_In_DBx__4__LCD_EN EQU CYREG_PRT2_LCD_EN\r
-SCSI_In_DBx__4__MASK EQU 0x10\r
-SCSI_In_DBx__4__PC EQU CYREG_PRT2_PC4\r
-SCSI_In_DBx__4__PORT EQU 2\r
-SCSI_In_DBx__4__PRT EQU CYREG_PRT2_PRT\r
-SCSI_In_DBx__4__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
-SCSI_In_DBx__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
-SCSI_In_DBx__4__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
-SCSI_In_DBx__4__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
-SCSI_In_DBx__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
-SCSI_In_DBx__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
-SCSI_In_DBx__4__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
-SCSI_In_DBx__4__PS EQU CYREG_PRT2_PS\r
-SCSI_In_DBx__4__SHIFT EQU 4\r
-SCSI_In_DBx__4__SLW EQU CYREG_PRT2_SLW\r
-SCSI_In_DBx__5__AG EQU CYREG_PRT2_AG\r
-SCSI_In_DBx__5__AMUX EQU CYREG_PRT2_AMUX\r
-SCSI_In_DBx__5__BIE EQU CYREG_PRT2_BIE\r
-SCSI_In_DBx__5__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
-SCSI_In_DBx__5__BYP EQU CYREG_PRT2_BYP\r
-SCSI_In_DBx__5__CTL EQU CYREG_PRT2_CTL\r
-SCSI_In_DBx__5__DM0 EQU CYREG_PRT2_DM0\r
-SCSI_In_DBx__5__DM1 EQU CYREG_PRT2_DM1\r
-SCSI_In_DBx__5__DM2 EQU CYREG_PRT2_DM2\r
-SCSI_In_DBx__5__DR EQU CYREG_PRT2_DR\r
-SCSI_In_DBx__5__INP_DIS EQU CYREG_PRT2_INP_DIS\r
-SCSI_In_DBx__5__INTTYPE EQU CYREG_PICU2_INTTYPE3\r
-SCSI_In_DBx__5__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
-SCSI_In_DBx__5__LCD_EN EQU CYREG_PRT2_LCD_EN\r
-SCSI_In_DBx__5__MASK EQU 0x08\r
-SCSI_In_DBx__5__PC EQU CYREG_PRT2_PC3\r
-SCSI_In_DBx__5__PORT EQU 2\r
-SCSI_In_DBx__5__PRT EQU CYREG_PRT2_PRT\r
-SCSI_In_DBx__5__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
-SCSI_In_DBx__5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
-SCSI_In_DBx__5__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
-SCSI_In_DBx__5__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
-SCSI_In_DBx__5__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
-SCSI_In_DBx__5__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
-SCSI_In_DBx__5__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
-SCSI_In_DBx__5__PS EQU CYREG_PRT2_PS\r
-SCSI_In_DBx__5__SHIFT EQU 3\r
-SCSI_In_DBx__5__SLW EQU CYREG_PRT2_SLW\r
-SCSI_In_DBx__6__AG EQU CYREG_PRT2_AG\r
-SCSI_In_DBx__6__AMUX EQU CYREG_PRT2_AMUX\r
-SCSI_In_DBx__6__BIE EQU CYREG_PRT2_BIE\r
-SCSI_In_DBx__6__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
-SCSI_In_DBx__6__BYP EQU CYREG_PRT2_BYP\r
-SCSI_In_DBx__6__CTL EQU CYREG_PRT2_CTL\r
-SCSI_In_DBx__6__DM0 EQU CYREG_PRT2_DM0\r
-SCSI_In_DBx__6__DM1 EQU CYREG_PRT2_DM1\r
-SCSI_In_DBx__6__DM2 EQU CYREG_PRT2_DM2\r
-SCSI_In_DBx__6__DR EQU CYREG_PRT2_DR\r
-SCSI_In_DBx__6__INP_DIS EQU CYREG_PRT2_INP_DIS\r
-SCSI_In_DBx__6__INTTYPE EQU CYREG_PICU2_INTTYPE2\r
-SCSI_In_DBx__6__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
-SCSI_In_DBx__6__LCD_EN EQU CYREG_PRT2_LCD_EN\r
-SCSI_In_DBx__6__MASK EQU 0x04\r
-SCSI_In_DBx__6__PC EQU CYREG_PRT2_PC2\r
-SCSI_In_DBx__6__PORT EQU 2\r
-SCSI_In_DBx__6__PRT EQU CYREG_PRT2_PRT\r
-SCSI_In_DBx__6__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
-SCSI_In_DBx__6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
-SCSI_In_DBx__6__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
-SCSI_In_DBx__6__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
-SCSI_In_DBx__6__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
-SCSI_In_DBx__6__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
-SCSI_In_DBx__6__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
-SCSI_In_DBx__6__PS EQU CYREG_PRT2_PS\r
-SCSI_In_DBx__6__SHIFT EQU 2\r
-SCSI_In_DBx__6__SLW EQU CYREG_PRT2_SLW\r
-SCSI_In_DBx__7__AG EQU CYREG_PRT2_AG\r
-SCSI_In_DBx__7__AMUX EQU CYREG_PRT2_AMUX\r
-SCSI_In_DBx__7__BIE EQU CYREG_PRT2_BIE\r
-SCSI_In_DBx__7__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
-SCSI_In_DBx__7__BYP EQU CYREG_PRT2_BYP\r
-SCSI_In_DBx__7__CTL EQU CYREG_PRT2_CTL\r
-SCSI_In_DBx__7__DM0 EQU CYREG_PRT2_DM0\r
-SCSI_In_DBx__7__DM1 EQU CYREG_PRT2_DM1\r
-SCSI_In_DBx__7__DM2 EQU CYREG_PRT2_DM2\r
-SCSI_In_DBx__7__DR EQU CYREG_PRT2_DR\r
-SCSI_In_DBx__7__INP_DIS EQU CYREG_PRT2_INP_DIS\r
-SCSI_In_DBx__7__INTTYPE EQU CYREG_PICU2_INTTYPE1\r
-SCSI_In_DBx__7__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
-SCSI_In_DBx__7__LCD_EN EQU CYREG_PRT2_LCD_EN\r
-SCSI_In_DBx__7__MASK EQU 0x02\r
-SCSI_In_DBx__7__PC EQU CYREG_PRT2_PC1\r
-SCSI_In_DBx__7__PORT EQU 2\r
-SCSI_In_DBx__7__PRT EQU CYREG_PRT2_PRT\r
-SCSI_In_DBx__7__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
-SCSI_In_DBx__7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
-SCSI_In_DBx__7__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
-SCSI_In_DBx__7__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
-SCSI_In_DBx__7__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
-SCSI_In_DBx__7__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
-SCSI_In_DBx__7__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
-SCSI_In_DBx__7__PS EQU CYREG_PRT2_PS\r
-SCSI_In_DBx__7__SHIFT EQU 1\r
-SCSI_In_DBx__7__SLW EQU CYREG_PRT2_SLW\r
-SCSI_In_DBx__DB0__AG EQU CYREG_PRT12_AG\r
-SCSI_In_DBx__DB0__BIE EQU CYREG_PRT12_BIE\r
-SCSI_In_DBx__DB0__BIT_MASK EQU CYREG_PRT12_BIT_MASK\r
-SCSI_In_DBx__DB0__BYP EQU CYREG_PRT12_BYP\r
-SCSI_In_DBx__DB0__DM0 EQU CYREG_PRT12_DM0\r
-SCSI_In_DBx__DB0__DM1 EQU CYREG_PRT12_DM1\r
-SCSI_In_DBx__DB0__DM2 EQU CYREG_PRT12_DM2\r
-SCSI_In_DBx__DB0__DR EQU CYREG_PRT12_DR\r
-SCSI_In_DBx__DB0__INP_DIS EQU CYREG_PRT12_INP_DIS\r
-SCSI_In_DBx__DB0__INTTYPE EQU CYREG_PICU12_INTTYPE4\r
-SCSI_In_DBx__DB0__MASK EQU 0x10\r
-SCSI_In_DBx__DB0__PC EQU CYREG_PRT12_PC4\r
-SCSI_In_DBx__DB0__PORT EQU 12\r
-SCSI_In_DBx__DB0__PRT EQU CYREG_PRT12_PRT\r
-SCSI_In_DBx__DB0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN\r
-SCSI_In_DBx__DB0__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0\r
-SCSI_In_DBx__DB0__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1\r
-SCSI_In_DBx__DB0__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0\r
-SCSI_In_DBx__DB0__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1\r
-SCSI_In_DBx__DB0__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT\r
-SCSI_In_DBx__DB0__PS EQU CYREG_PRT12_PS\r
-SCSI_In_DBx__DB0__SHIFT EQU 4\r
-SCSI_In_DBx__DB0__SIO_CFG EQU CYREG_PRT12_SIO_CFG\r
-SCSI_In_DBx__DB0__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF\r
-SCSI_In_DBx__DB0__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN\r
-SCSI_In_DBx__DB0__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ\r
-SCSI_In_DBx__DB0__SLW EQU CYREG_PRT12_SLW\r
-SCSI_In_DBx__DB1__AG EQU CYREG_PRT2_AG\r
-SCSI_In_DBx__DB1__AMUX EQU CYREG_PRT2_AMUX\r
-SCSI_In_DBx__DB1__BIE EQU CYREG_PRT2_BIE\r
-SCSI_In_DBx__DB1__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
-SCSI_In_DBx__DB1__BYP EQU CYREG_PRT2_BYP\r
-SCSI_In_DBx__DB1__CTL EQU CYREG_PRT2_CTL\r
-SCSI_In_DBx__DB1__DM0 EQU CYREG_PRT2_DM0\r
-SCSI_In_DBx__DB1__DM1 EQU CYREG_PRT2_DM1\r
-SCSI_In_DBx__DB1__DM2 EQU CYREG_PRT2_DM2\r
-SCSI_In_DBx__DB1__DR EQU CYREG_PRT2_DR\r
-SCSI_In_DBx__DB1__INP_DIS EQU CYREG_PRT2_INP_DIS\r
-SCSI_In_DBx__DB1__INTTYPE EQU CYREG_PICU2_INTTYPE7\r
-SCSI_In_DBx__DB1__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
-SCSI_In_DBx__DB1__LCD_EN EQU CYREG_PRT2_LCD_EN\r
-SCSI_In_DBx__DB1__MASK EQU 0x80\r
-SCSI_In_DBx__DB1__PC EQU CYREG_PRT2_PC7\r
-SCSI_In_DBx__DB1__PORT EQU 2\r
-SCSI_In_DBx__DB1__PRT EQU CYREG_PRT2_PRT\r
-SCSI_In_DBx__DB1__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
-SCSI_In_DBx__DB1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
-SCSI_In_DBx__DB1__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
-SCSI_In_DBx__DB1__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
-SCSI_In_DBx__DB1__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
-SCSI_In_DBx__DB1__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
-SCSI_In_DBx__DB1__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
-SCSI_In_DBx__DB1__PS EQU CYREG_PRT2_PS\r
-SCSI_In_DBx__DB1__SHIFT EQU 7\r
-SCSI_In_DBx__DB1__SLW EQU CYREG_PRT2_SLW\r
-SCSI_In_DBx__DB2__AG EQU CYREG_PRT2_AG\r
-SCSI_In_DBx__DB2__AMUX EQU CYREG_PRT2_AMUX\r
-SCSI_In_DBx__DB2__BIE EQU CYREG_PRT2_BIE\r
-SCSI_In_DBx__DB2__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
-SCSI_In_DBx__DB2__BYP EQU CYREG_PRT2_BYP\r
-SCSI_In_DBx__DB2__CTL EQU CYREG_PRT2_CTL\r
-SCSI_In_DBx__DB2__DM0 EQU CYREG_PRT2_DM0\r
-SCSI_In_DBx__DB2__DM1 EQU CYREG_PRT2_DM1\r
-SCSI_In_DBx__DB2__DM2 EQU CYREG_PRT2_DM2\r
-SCSI_In_DBx__DB2__DR EQU CYREG_PRT2_DR\r
-SCSI_In_DBx__DB2__INP_DIS EQU CYREG_PRT2_INP_DIS\r
-SCSI_In_DBx__DB2__INTTYPE EQU CYREG_PICU2_INTTYPE6\r
-SCSI_In_DBx__DB2__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
-SCSI_In_DBx__DB2__LCD_EN EQU CYREG_PRT2_LCD_EN\r
-SCSI_In_DBx__DB2__MASK EQU 0x40\r
-SCSI_In_DBx__DB2__PC EQU CYREG_PRT2_PC6\r
-SCSI_In_DBx__DB2__PORT EQU 2\r
-SCSI_In_DBx__DB2__PRT EQU CYREG_PRT2_PRT\r
-SCSI_In_DBx__DB2__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
-SCSI_In_DBx__DB2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
-SCSI_In_DBx__DB2__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
-SCSI_In_DBx__DB2__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
-SCSI_In_DBx__DB2__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
-SCSI_In_DBx__DB2__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
-SCSI_In_DBx__DB2__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
-SCSI_In_DBx__DB2__PS EQU CYREG_PRT2_PS\r
-SCSI_In_DBx__DB2__SHIFT EQU 6\r
-SCSI_In_DBx__DB2__SLW EQU CYREG_PRT2_SLW\r
-SCSI_In_DBx__DB3__AG EQU CYREG_PRT2_AG\r
-SCSI_In_DBx__DB3__AMUX EQU CYREG_PRT2_AMUX\r
-SCSI_In_DBx__DB3__BIE EQU CYREG_PRT2_BIE\r
-SCSI_In_DBx__DB3__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
-SCSI_In_DBx__DB3__BYP EQU CYREG_PRT2_BYP\r
-SCSI_In_DBx__DB3__CTL EQU CYREG_PRT2_CTL\r
-SCSI_In_DBx__DB3__DM0 EQU CYREG_PRT2_DM0\r
-SCSI_In_DBx__DB3__DM1 EQU CYREG_PRT2_DM1\r
-SCSI_In_DBx__DB3__DM2 EQU CYREG_PRT2_DM2\r
-SCSI_In_DBx__DB3__DR EQU CYREG_PRT2_DR\r
-SCSI_In_DBx__DB3__INP_DIS EQU CYREG_PRT2_INP_DIS\r
-SCSI_In_DBx__DB3__INTTYPE EQU CYREG_PICU2_INTTYPE5\r
-SCSI_In_DBx__DB3__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
-SCSI_In_DBx__DB3__LCD_EN EQU CYREG_PRT2_LCD_EN\r
-SCSI_In_DBx__DB3__MASK EQU 0x20\r
-SCSI_In_DBx__DB3__PC EQU CYREG_PRT2_PC5\r
-SCSI_In_DBx__DB3__PORT EQU 2\r
-SCSI_In_DBx__DB3__PRT EQU CYREG_PRT2_PRT\r
-SCSI_In_DBx__DB3__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
-SCSI_In_DBx__DB3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
-SCSI_In_DBx__DB3__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
-SCSI_In_DBx__DB3__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
-SCSI_In_DBx__DB3__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
-SCSI_In_DBx__DB3__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
-SCSI_In_DBx__DB3__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
-SCSI_In_DBx__DB3__PS EQU CYREG_PRT2_PS\r
-SCSI_In_DBx__DB3__SHIFT EQU 5\r
-SCSI_In_DBx__DB3__SLW EQU CYREG_PRT2_SLW\r
-SCSI_In_DBx__DB4__AG EQU CYREG_PRT2_AG\r
-SCSI_In_DBx__DB4__AMUX EQU CYREG_PRT2_AMUX\r
-SCSI_In_DBx__DB4__BIE EQU CYREG_PRT2_BIE\r
-SCSI_In_DBx__DB4__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
-SCSI_In_DBx__DB4__BYP EQU CYREG_PRT2_BYP\r
-SCSI_In_DBx__DB4__CTL EQU CYREG_PRT2_CTL\r
-SCSI_In_DBx__DB4__DM0 EQU CYREG_PRT2_DM0\r
-SCSI_In_DBx__DB4__DM1 EQU CYREG_PRT2_DM1\r
-SCSI_In_DBx__DB4__DM2 EQU CYREG_PRT2_DM2\r
-SCSI_In_DBx__DB4__DR EQU CYREG_PRT2_DR\r
-SCSI_In_DBx__DB4__INP_DIS EQU CYREG_PRT2_INP_DIS\r
-SCSI_In_DBx__DB4__INTTYPE EQU CYREG_PICU2_INTTYPE4\r
-SCSI_In_DBx__DB4__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
-SCSI_In_DBx__DB4__LCD_EN EQU CYREG_PRT2_LCD_EN\r
-SCSI_In_DBx__DB4__MASK EQU 0x10\r
-SCSI_In_DBx__DB4__PC EQU CYREG_PRT2_PC4\r
-SCSI_In_DBx__DB4__PORT EQU 2\r
-SCSI_In_DBx__DB4__PRT EQU CYREG_PRT2_PRT\r
-SCSI_In_DBx__DB4__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
-SCSI_In_DBx__DB4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
-SCSI_In_DBx__DB4__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
-SCSI_In_DBx__DB4__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
-SCSI_In_DBx__DB4__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
-SCSI_In_DBx__DB4__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
-SCSI_In_DBx__DB4__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
-SCSI_In_DBx__DB4__PS EQU CYREG_PRT2_PS\r
-SCSI_In_DBx__DB4__SHIFT EQU 4\r
-SCSI_In_DBx__DB4__SLW EQU CYREG_PRT2_SLW\r
-SCSI_In_DBx__DB5__AG EQU CYREG_PRT2_AG\r
-SCSI_In_DBx__DB5__AMUX EQU CYREG_PRT2_AMUX\r
-SCSI_In_DBx__DB5__BIE EQU CYREG_PRT2_BIE\r
-SCSI_In_DBx__DB5__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
-SCSI_In_DBx__DB5__BYP EQU CYREG_PRT2_BYP\r
-SCSI_In_DBx__DB5__CTL EQU CYREG_PRT2_CTL\r
-SCSI_In_DBx__DB5__DM0 EQU CYREG_PRT2_DM0\r
-SCSI_In_DBx__DB5__DM1 EQU CYREG_PRT2_DM1\r
-SCSI_In_DBx__DB5__DM2 EQU CYREG_PRT2_DM2\r
-SCSI_In_DBx__DB5__DR EQU CYREG_PRT2_DR\r
-SCSI_In_DBx__DB5__INP_DIS EQU CYREG_PRT2_INP_DIS\r
-SCSI_In_DBx__DB5__INTTYPE EQU CYREG_PICU2_INTTYPE3\r
-SCSI_In_DBx__DB5__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
-SCSI_In_DBx__DB5__LCD_EN EQU CYREG_PRT2_LCD_EN\r
-SCSI_In_DBx__DB5__MASK EQU 0x08\r
-SCSI_In_DBx__DB5__PC EQU CYREG_PRT2_PC3\r
-SCSI_In_DBx__DB5__PORT EQU 2\r
-SCSI_In_DBx__DB5__PRT EQU CYREG_PRT2_PRT\r
-SCSI_In_DBx__DB5__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
-SCSI_In_DBx__DB5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
-SCSI_In_DBx__DB5__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
-SCSI_In_DBx__DB5__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
-SCSI_In_DBx__DB5__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
-SCSI_In_DBx__DB5__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
-SCSI_In_DBx__DB5__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
-SCSI_In_DBx__DB5__PS EQU CYREG_PRT2_PS\r
-SCSI_In_DBx__DB5__SHIFT EQU 3\r
-SCSI_In_DBx__DB5__SLW EQU CYREG_PRT2_SLW\r
-SCSI_In_DBx__DB6__AG EQU CYREG_PRT2_AG\r
-SCSI_In_DBx__DB6__AMUX EQU CYREG_PRT2_AMUX\r
-SCSI_In_DBx__DB6__BIE EQU CYREG_PRT2_BIE\r
-SCSI_In_DBx__DB6__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
-SCSI_In_DBx__DB6__BYP EQU CYREG_PRT2_BYP\r
-SCSI_In_DBx__DB6__CTL EQU CYREG_PRT2_CTL\r
-SCSI_In_DBx__DB6__DM0 EQU CYREG_PRT2_DM0\r
-SCSI_In_DBx__DB6__DM1 EQU CYREG_PRT2_DM1\r
-SCSI_In_DBx__DB6__DM2 EQU CYREG_PRT2_DM2\r
-SCSI_In_DBx__DB6__DR EQU CYREG_PRT2_DR\r
-SCSI_In_DBx__DB6__INP_DIS EQU CYREG_PRT2_INP_DIS\r
-SCSI_In_DBx__DB6__INTTYPE EQU CYREG_PICU2_INTTYPE2\r
-SCSI_In_DBx__DB6__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
-SCSI_In_DBx__DB6__LCD_EN EQU CYREG_PRT2_LCD_EN\r
-SCSI_In_DBx__DB6__MASK EQU 0x04\r
-SCSI_In_DBx__DB6__PC EQU CYREG_PRT2_PC2\r
-SCSI_In_DBx__DB6__PORT EQU 2\r
-SCSI_In_DBx__DB6__PRT EQU CYREG_PRT2_PRT\r
-SCSI_In_DBx__DB6__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
-SCSI_In_DBx__DB6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
-SCSI_In_DBx__DB6__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
-SCSI_In_DBx__DB6__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
-SCSI_In_DBx__DB6__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
-SCSI_In_DBx__DB6__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
-SCSI_In_DBx__DB6__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
-SCSI_In_DBx__DB6__PS EQU CYREG_PRT2_PS\r
-SCSI_In_DBx__DB6__SHIFT EQU 2\r
-SCSI_In_DBx__DB6__SLW EQU CYREG_PRT2_SLW\r
-SCSI_In_DBx__DB7__AG EQU CYREG_PRT2_AG\r
-SCSI_In_DBx__DB7__AMUX EQU CYREG_PRT2_AMUX\r
-SCSI_In_DBx__DB7__BIE EQU CYREG_PRT2_BIE\r
-SCSI_In_DBx__DB7__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
-SCSI_In_DBx__DB7__BYP EQU CYREG_PRT2_BYP\r
-SCSI_In_DBx__DB7__CTL EQU CYREG_PRT2_CTL\r
-SCSI_In_DBx__DB7__DM0 EQU CYREG_PRT2_DM0\r
-SCSI_In_DBx__DB7__DM1 EQU CYREG_PRT2_DM1\r
-SCSI_In_DBx__DB7__DM2 EQU CYREG_PRT2_DM2\r
-SCSI_In_DBx__DB7__DR EQU CYREG_PRT2_DR\r
-SCSI_In_DBx__DB7__INP_DIS EQU CYREG_PRT2_INP_DIS\r
-SCSI_In_DBx__DB7__INTTYPE EQU CYREG_PICU2_INTTYPE1\r
-SCSI_In_DBx__DB7__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
-SCSI_In_DBx__DB7__LCD_EN EQU CYREG_PRT2_LCD_EN\r
-SCSI_In_DBx__DB7__MASK EQU 0x02\r
-SCSI_In_DBx__DB7__PC EQU CYREG_PRT2_PC1\r
-SCSI_In_DBx__DB7__PORT EQU 2\r
-SCSI_In_DBx__DB7__PRT EQU CYREG_PRT2_PRT\r
-SCSI_In_DBx__DB7__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
-SCSI_In_DBx__DB7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
-SCSI_In_DBx__DB7__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
-SCSI_In_DBx__DB7__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
-SCSI_In_DBx__DB7__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
-SCSI_In_DBx__DB7__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
-SCSI_In_DBx__DB7__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
-SCSI_In_DBx__DB7__PS EQU CYREG_PRT2_PS\r
-SCSI_In_DBx__DB7__SHIFT EQU 1\r
-SCSI_In_DBx__DB7__SLW EQU CYREG_PRT2_SLW\r
-\r
-/* SCSI_Noise */\r
-SCSI_Noise__0__AG EQU CYREG_PRT12_AG\r
-SCSI_Noise__0__BIE EQU CYREG_PRT12_BIE\r
-SCSI_Noise__0__BIT_MASK EQU CYREG_PRT12_BIT_MASK\r
-SCSI_Noise__0__BYP EQU CYREG_PRT12_BYP\r
-SCSI_Noise__0__DM0 EQU CYREG_PRT12_DM0\r
-SCSI_Noise__0__DM1 EQU CYREG_PRT12_DM1\r
-SCSI_Noise__0__DM2 EQU CYREG_PRT12_DM2\r
-SCSI_Noise__0__DR EQU CYREG_PRT12_DR\r
-SCSI_Noise__0__INP_DIS EQU CYREG_PRT12_INP_DIS\r
-SCSI_Noise__0__INTTYPE EQU CYREG_PICU12_INTTYPE5\r
-SCSI_Noise__0__MASK EQU 0x20\r
-SCSI_Noise__0__PC EQU CYREG_PRT12_PC5\r
-SCSI_Noise__0__PORT EQU 12\r
-SCSI_Noise__0__PRT EQU CYREG_PRT12_PRT\r
-SCSI_Noise__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN\r
-SCSI_Noise__0__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0\r
-SCSI_Noise__0__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1\r
-SCSI_Noise__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0\r
-SCSI_Noise__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1\r
-SCSI_Noise__0__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT\r
-SCSI_Noise__0__PS EQU CYREG_PRT12_PS\r
-SCSI_Noise__0__SHIFT EQU 5\r
-SCSI_Noise__0__SIO_CFG EQU CYREG_PRT12_SIO_CFG\r
-SCSI_Noise__0__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF\r
-SCSI_Noise__0__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN\r
-SCSI_Noise__0__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ\r
-SCSI_Noise__0__SLW EQU CYREG_PRT12_SLW\r
-SCSI_Noise__1__AG EQU CYREG_PRT6_AG\r
-SCSI_Noise__1__AMUX EQU CYREG_PRT6_AMUX\r
-SCSI_Noise__1__BIE EQU CYREG_PRT6_BIE\r
-SCSI_Noise__1__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
-SCSI_Noise__1__BYP EQU CYREG_PRT6_BYP\r
-SCSI_Noise__1__CTL EQU CYREG_PRT6_CTL\r
-SCSI_Noise__1__DM0 EQU CYREG_PRT6_DM0\r
-SCSI_Noise__1__DM1 EQU CYREG_PRT6_DM1\r
-SCSI_Noise__1__DM2 EQU CYREG_PRT6_DM2\r
-SCSI_Noise__1__DR EQU CYREG_PRT6_DR\r
-SCSI_Noise__1__INP_DIS EQU CYREG_PRT6_INP_DIS\r
-SCSI_Noise__1__INTTYPE EQU CYREG_PICU6_INTTYPE4\r
-SCSI_Noise__1__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
-SCSI_Noise__1__LCD_EN EQU CYREG_PRT6_LCD_EN\r
-SCSI_Noise__1__MASK EQU 0x10\r
-SCSI_Noise__1__PC EQU CYREG_PRT6_PC4\r
-SCSI_Noise__1__PORT EQU 6\r
-SCSI_Noise__1__PRT EQU CYREG_PRT6_PRT\r
-SCSI_Noise__1__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
-SCSI_Noise__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
-SCSI_Noise__1__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
-SCSI_Noise__1__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
-SCSI_Noise__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
-SCSI_Noise__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
-SCSI_Noise__1__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
-SCSI_Noise__1__PS EQU CYREG_PRT6_PS\r
-SCSI_Noise__1__SHIFT EQU 4\r
-SCSI_Noise__1__SLW EQU CYREG_PRT6_SLW\r
-SCSI_Noise__2__AG EQU CYREG_PRT5_AG\r
-SCSI_Noise__2__AMUX EQU CYREG_PRT5_AMUX\r
-SCSI_Noise__2__BIE EQU CYREG_PRT5_BIE\r
-SCSI_Noise__2__BIT_MASK EQU CYREG_PRT5_BIT_MASK\r
-SCSI_Noise__2__BYP EQU CYREG_PRT5_BYP\r
-SCSI_Noise__2__CTL EQU CYREG_PRT5_CTL\r
-SCSI_Noise__2__DM0 EQU CYREG_PRT5_DM0\r
-SCSI_Noise__2__DM1 EQU CYREG_PRT5_DM1\r
-SCSI_Noise__2__DM2 EQU CYREG_PRT5_DM2\r
-SCSI_Noise__2__DR EQU CYREG_PRT5_DR\r
-SCSI_Noise__2__INP_DIS EQU CYREG_PRT5_INP_DIS\r
-SCSI_Noise__2__INTTYPE EQU CYREG_PICU5_INTTYPE0\r
-SCSI_Noise__2__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG\r
-SCSI_Noise__2__LCD_EN EQU CYREG_PRT5_LCD_EN\r
-SCSI_Noise__2__MASK EQU 0x01\r
-SCSI_Noise__2__PC EQU CYREG_PRT5_PC0\r
-SCSI_Noise__2__PORT EQU 5\r
-SCSI_Noise__2__PRT EQU CYREG_PRT5_PRT\r
-SCSI_Noise__2__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL\r
-SCSI_Noise__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN\r
-SCSI_Noise__2__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0\r
-SCSI_Noise__2__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1\r
-SCSI_Noise__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0\r
-SCSI_Noise__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1\r
-SCSI_Noise__2__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT\r
-SCSI_Noise__2__PS EQU CYREG_PRT5_PS\r
-SCSI_Noise__2__SHIFT EQU 0\r
-SCSI_Noise__2__SLW EQU CYREG_PRT5_SLW\r
-SCSI_Noise__3__AG EQU CYREG_PRT6_AG\r
-SCSI_Noise__3__AMUX EQU CYREG_PRT6_AMUX\r
-SCSI_Noise__3__BIE EQU CYREG_PRT6_BIE\r
-SCSI_Noise__3__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
-SCSI_Noise__3__BYP EQU CYREG_PRT6_BYP\r
-SCSI_Noise__3__CTL EQU CYREG_PRT6_CTL\r
-SCSI_Noise__3__DM0 EQU CYREG_PRT6_DM0\r
-SCSI_Noise__3__DM1 EQU CYREG_PRT6_DM1\r
-SCSI_Noise__3__DM2 EQU CYREG_PRT6_DM2\r
-SCSI_Noise__3__DR EQU CYREG_PRT6_DR\r
-SCSI_Noise__3__INP_DIS EQU CYREG_PRT6_INP_DIS\r
-SCSI_Noise__3__INTTYPE EQU CYREG_PICU6_INTTYPE6\r
-SCSI_Noise__3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
-SCSI_Noise__3__LCD_EN EQU CYREG_PRT6_LCD_EN\r
-SCSI_Noise__3__MASK EQU 0x40\r
-SCSI_Noise__3__PC EQU CYREG_PRT6_PC6\r
-SCSI_Noise__3__PORT EQU 6\r
-SCSI_Noise__3__PRT EQU CYREG_PRT6_PRT\r
-SCSI_Noise__3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
-SCSI_Noise__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
-SCSI_Noise__3__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
-SCSI_Noise__3__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
-SCSI_Noise__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
-SCSI_Noise__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
-SCSI_Noise__3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
-SCSI_Noise__3__PS EQU CYREG_PRT6_PS\r
-SCSI_Noise__3__SHIFT EQU 6\r
-SCSI_Noise__3__SLW EQU CYREG_PRT6_SLW\r
-SCSI_Noise__4__AG EQU CYREG_PRT6_AG\r
-SCSI_Noise__4__AMUX EQU CYREG_PRT6_AMUX\r
-SCSI_Noise__4__BIE EQU CYREG_PRT6_BIE\r
-SCSI_Noise__4__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
-SCSI_Noise__4__BYP EQU CYREG_PRT6_BYP\r
-SCSI_Noise__4__CTL EQU CYREG_PRT6_CTL\r
-SCSI_Noise__4__DM0 EQU CYREG_PRT6_DM0\r
-SCSI_Noise__4__DM1 EQU CYREG_PRT6_DM1\r
-SCSI_Noise__4__DM2 EQU CYREG_PRT6_DM2\r
-SCSI_Noise__4__DR EQU CYREG_PRT6_DR\r
-SCSI_Noise__4__INP_DIS EQU CYREG_PRT6_INP_DIS\r
-SCSI_Noise__4__INTTYPE EQU CYREG_PICU6_INTTYPE5\r
-SCSI_Noise__4__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
-SCSI_Noise__4__LCD_EN EQU CYREG_PRT6_LCD_EN\r
-SCSI_Noise__4__MASK EQU 0x20\r
-SCSI_Noise__4__PC EQU CYREG_PRT6_PC5\r
-SCSI_Noise__4__PORT EQU 6\r
-SCSI_Noise__4__PRT EQU CYREG_PRT6_PRT\r
-SCSI_Noise__4__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
-SCSI_Noise__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
-SCSI_Noise__4__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
-SCSI_Noise__4__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
-SCSI_Noise__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
-SCSI_Noise__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
-SCSI_Noise__4__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
-SCSI_Noise__4__PS EQU CYREG_PRT6_PS\r
-SCSI_Noise__4__SHIFT EQU 5\r
-SCSI_Noise__4__SLW EQU CYREG_PRT6_SLW\r
-SCSI_Noise__ACK__AG EQU CYREG_PRT6_AG\r
-SCSI_Noise__ACK__AMUX EQU CYREG_PRT6_AMUX\r
-SCSI_Noise__ACK__BIE EQU CYREG_PRT6_BIE\r
-SCSI_Noise__ACK__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
-SCSI_Noise__ACK__BYP EQU CYREG_PRT6_BYP\r
-SCSI_Noise__ACK__CTL EQU CYREG_PRT6_CTL\r
-SCSI_Noise__ACK__DM0 EQU CYREG_PRT6_DM0\r
-SCSI_Noise__ACK__DM1 EQU CYREG_PRT6_DM1\r
-SCSI_Noise__ACK__DM2 EQU CYREG_PRT6_DM2\r
-SCSI_Noise__ACK__DR EQU CYREG_PRT6_DR\r
-SCSI_Noise__ACK__INP_DIS EQU CYREG_PRT6_INP_DIS\r
-SCSI_Noise__ACK__INTTYPE EQU CYREG_PICU6_INTTYPE5\r
-SCSI_Noise__ACK__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
-SCSI_Noise__ACK__LCD_EN EQU CYREG_PRT6_LCD_EN\r
-SCSI_Noise__ACK__MASK EQU 0x20\r
-SCSI_Noise__ACK__PC EQU CYREG_PRT6_PC5\r
-SCSI_Noise__ACK__PORT EQU 6\r
-SCSI_Noise__ACK__PRT EQU CYREG_PRT6_PRT\r
-SCSI_Noise__ACK__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
-SCSI_Noise__ACK__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
-SCSI_Noise__ACK__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
-SCSI_Noise__ACK__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
-SCSI_Noise__ACK__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
-SCSI_Noise__ACK__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
-SCSI_Noise__ACK__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
-SCSI_Noise__ACK__PS EQU CYREG_PRT6_PS\r
-SCSI_Noise__ACK__SHIFT EQU 5\r
-SCSI_Noise__ACK__SLW EQU CYREG_PRT6_SLW\r
-SCSI_Noise__ATN__AG EQU CYREG_PRT12_AG\r
-SCSI_Noise__ATN__BIE EQU CYREG_PRT12_BIE\r
-SCSI_Noise__ATN__BIT_MASK EQU CYREG_PRT12_BIT_MASK\r
-SCSI_Noise__ATN__BYP EQU CYREG_PRT12_BYP\r
-SCSI_Noise__ATN__DM0 EQU CYREG_PRT12_DM0\r
-SCSI_Noise__ATN__DM1 EQU CYREG_PRT12_DM1\r
-SCSI_Noise__ATN__DM2 EQU CYREG_PRT12_DM2\r
-SCSI_Noise__ATN__DR EQU CYREG_PRT12_DR\r
-SCSI_Noise__ATN__INP_DIS EQU CYREG_PRT12_INP_DIS\r
-SCSI_Noise__ATN__INTTYPE EQU CYREG_PICU12_INTTYPE5\r
-SCSI_Noise__ATN__MASK EQU 0x20\r
-SCSI_Noise__ATN__PC EQU CYREG_PRT12_PC5\r
-SCSI_Noise__ATN__PORT EQU 12\r
-SCSI_Noise__ATN__PRT EQU CYREG_PRT12_PRT\r
-SCSI_Noise__ATN__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN\r
-SCSI_Noise__ATN__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0\r
-SCSI_Noise__ATN__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1\r
-SCSI_Noise__ATN__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0\r
-SCSI_Noise__ATN__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1\r
-SCSI_Noise__ATN__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT\r
-SCSI_Noise__ATN__PS EQU CYREG_PRT12_PS\r
-SCSI_Noise__ATN__SHIFT EQU 5\r
-SCSI_Noise__ATN__SIO_CFG EQU CYREG_PRT12_SIO_CFG\r
-SCSI_Noise__ATN__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF\r
-SCSI_Noise__ATN__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN\r
-SCSI_Noise__ATN__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ\r
-SCSI_Noise__ATN__SLW EQU CYREG_PRT12_SLW\r
-SCSI_Noise__BSY__AG EQU CYREG_PRT6_AG\r
-SCSI_Noise__BSY__AMUX EQU CYREG_PRT6_AMUX\r
-SCSI_Noise__BSY__BIE EQU CYREG_PRT6_BIE\r
-SCSI_Noise__BSY__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
-SCSI_Noise__BSY__BYP EQU CYREG_PRT6_BYP\r
-SCSI_Noise__BSY__CTL EQU CYREG_PRT6_CTL\r
-SCSI_Noise__BSY__DM0 EQU CYREG_PRT6_DM0\r
-SCSI_Noise__BSY__DM1 EQU CYREG_PRT6_DM1\r
-SCSI_Noise__BSY__DM2 EQU CYREG_PRT6_DM2\r
-SCSI_Noise__BSY__DR EQU CYREG_PRT6_DR\r
-SCSI_Noise__BSY__INP_DIS EQU CYREG_PRT6_INP_DIS\r
-SCSI_Noise__BSY__INTTYPE EQU CYREG_PICU6_INTTYPE4\r
-SCSI_Noise__BSY__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
-SCSI_Noise__BSY__LCD_EN EQU CYREG_PRT6_LCD_EN\r
-SCSI_Noise__BSY__MASK EQU 0x10\r
-SCSI_Noise__BSY__PC EQU CYREG_PRT6_PC4\r
-SCSI_Noise__BSY__PORT EQU 6\r
-SCSI_Noise__BSY__PRT EQU CYREG_PRT6_PRT\r
-SCSI_Noise__BSY__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
-SCSI_Noise__BSY__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
-SCSI_Noise__BSY__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
-SCSI_Noise__BSY__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
-SCSI_Noise__BSY__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
-SCSI_Noise__BSY__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
-SCSI_Noise__BSY__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
-SCSI_Noise__BSY__PS EQU CYREG_PRT6_PS\r
-SCSI_Noise__BSY__SHIFT EQU 4\r
-SCSI_Noise__BSY__SLW EQU CYREG_PRT6_SLW\r
-SCSI_Noise__RST__AG EQU CYREG_PRT6_AG\r
-SCSI_Noise__RST__AMUX EQU CYREG_PRT6_AMUX\r
-SCSI_Noise__RST__BIE EQU CYREG_PRT6_BIE\r
-SCSI_Noise__RST__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
-SCSI_Noise__RST__BYP EQU CYREG_PRT6_BYP\r
-SCSI_Noise__RST__CTL EQU CYREG_PRT6_CTL\r
-SCSI_Noise__RST__DM0 EQU CYREG_PRT6_DM0\r
-SCSI_Noise__RST__DM1 EQU CYREG_PRT6_DM1\r
-SCSI_Noise__RST__DM2 EQU CYREG_PRT6_DM2\r
-SCSI_Noise__RST__DR EQU CYREG_PRT6_DR\r
-SCSI_Noise__RST__INP_DIS EQU CYREG_PRT6_INP_DIS\r
-SCSI_Noise__RST__INTTYPE EQU CYREG_PICU6_INTTYPE6\r
-SCSI_Noise__RST__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
-SCSI_Noise__RST__LCD_EN EQU CYREG_PRT6_LCD_EN\r
-SCSI_Noise__RST__MASK EQU 0x40\r
-SCSI_Noise__RST__PC EQU CYREG_PRT6_PC6\r
-SCSI_Noise__RST__PORT EQU 6\r
-SCSI_Noise__RST__PRT EQU CYREG_PRT6_PRT\r
-SCSI_Noise__RST__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
-SCSI_Noise__RST__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
-SCSI_Noise__RST__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
-SCSI_Noise__RST__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
-SCSI_Noise__RST__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
-SCSI_Noise__RST__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
-SCSI_Noise__RST__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
-SCSI_Noise__RST__PS EQU CYREG_PRT6_PS\r
-SCSI_Noise__RST__SHIFT EQU 6\r
-SCSI_Noise__RST__SLW EQU CYREG_PRT6_SLW\r
-SCSI_Noise__SEL__AG EQU CYREG_PRT5_AG\r
-SCSI_Noise__SEL__AMUX EQU CYREG_PRT5_AMUX\r
-SCSI_Noise__SEL__BIE EQU CYREG_PRT5_BIE\r
-SCSI_Noise__SEL__BIT_MASK EQU CYREG_PRT5_BIT_MASK\r
-SCSI_Noise__SEL__BYP EQU CYREG_PRT5_BYP\r
-SCSI_Noise__SEL__CTL EQU CYREG_PRT5_CTL\r
-SCSI_Noise__SEL__DM0 EQU CYREG_PRT5_DM0\r
-SCSI_Noise__SEL__DM1 EQU CYREG_PRT5_DM1\r
-SCSI_Noise__SEL__DM2 EQU CYREG_PRT5_DM2\r
-SCSI_Noise__SEL__DR EQU CYREG_PRT5_DR\r
-SCSI_Noise__SEL__INP_DIS EQU CYREG_PRT5_INP_DIS\r
-SCSI_Noise__SEL__INTTYPE EQU CYREG_PICU5_INTTYPE0\r
-SCSI_Noise__SEL__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG\r
-SCSI_Noise__SEL__LCD_EN EQU CYREG_PRT5_LCD_EN\r
-SCSI_Noise__SEL__MASK EQU 0x01\r
-SCSI_Noise__SEL__PC EQU CYREG_PRT5_PC0\r
-SCSI_Noise__SEL__PORT EQU 5\r
-SCSI_Noise__SEL__PRT EQU CYREG_PRT5_PRT\r
-SCSI_Noise__SEL__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL\r
-SCSI_Noise__SEL__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN\r
-SCSI_Noise__SEL__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0\r
-SCSI_Noise__SEL__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1\r
-SCSI_Noise__SEL__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0\r
-SCSI_Noise__SEL__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1\r
-SCSI_Noise__SEL__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT\r
-SCSI_Noise__SEL__PS EQU CYREG_PRT5_PS\r
-SCSI_Noise__SEL__SHIFT EQU 0\r
-SCSI_Noise__SEL__SLW EQU CYREG_PRT5_SLW\r
-\r
-/* SCSI_Out */\r
-SCSI_Out__0__AG EQU CYREG_PRT4_AG\r
-SCSI_Out__0__AMUX EQU CYREG_PRT4_AMUX\r
-SCSI_Out__0__BIE EQU CYREG_PRT4_BIE\r
-SCSI_Out__0__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
-SCSI_Out__0__BYP EQU CYREG_PRT4_BYP\r
-SCSI_Out__0__CTL EQU CYREG_PRT4_CTL\r
-SCSI_Out__0__DM0 EQU CYREG_PRT4_DM0\r
-SCSI_Out__0__DM1 EQU CYREG_PRT4_DM1\r
-SCSI_Out__0__DM2 EQU CYREG_PRT4_DM2\r
-SCSI_Out__0__DR EQU CYREG_PRT4_DR\r
-SCSI_Out__0__INP_DIS EQU CYREG_PRT4_INP_DIS\r
-SCSI_Out__0__INTTYPE EQU CYREG_PICU4_INTTYPE3\r
-SCSI_Out__0__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
-SCSI_Out__0__LCD_EN EQU CYREG_PRT4_LCD_EN\r
-SCSI_Out__0__MASK EQU 0x08\r
-SCSI_Out__0__PC EQU CYREG_PRT4_PC3\r
-SCSI_Out__0__PORT EQU 4\r
-SCSI_Out__0__PRT EQU CYREG_PRT4_PRT\r
-SCSI_Out__0__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
-SCSI_Out__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
-SCSI_Out__0__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
-SCSI_Out__0__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
-SCSI_Out__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
-SCSI_Out__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
-SCSI_Out__0__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
-SCSI_Out__0__PS EQU CYREG_PRT4_PS\r
-SCSI_Out__0__SHIFT EQU 3\r
-SCSI_Out__0__SLW EQU CYREG_PRT4_SLW\r
-SCSI_Out__1__AG EQU CYREG_PRT4_AG\r
-SCSI_Out__1__AMUX EQU CYREG_PRT4_AMUX\r
-SCSI_Out__1__BIE EQU CYREG_PRT4_BIE\r
-SCSI_Out__1__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
-SCSI_Out__1__BYP EQU CYREG_PRT4_BYP\r
-SCSI_Out__1__CTL EQU CYREG_PRT4_CTL\r
-SCSI_Out__1__DM0 EQU CYREG_PRT4_DM0\r
-SCSI_Out__1__DM1 EQU CYREG_PRT4_DM1\r
-SCSI_Out__1__DM2 EQU CYREG_PRT4_DM2\r
-SCSI_Out__1__DR EQU CYREG_PRT4_DR\r
-SCSI_Out__1__INP_DIS EQU CYREG_PRT4_INP_DIS\r
-SCSI_Out__1__INTTYPE EQU CYREG_PICU4_INTTYPE2\r
-SCSI_Out__1__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
-SCSI_Out__1__LCD_EN EQU CYREG_PRT4_LCD_EN\r
-SCSI_Out__1__MASK EQU 0x04\r
-SCSI_Out__1__PC EQU CYREG_PRT4_PC2\r
-SCSI_Out__1__PORT EQU 4\r
-SCSI_Out__1__PRT EQU CYREG_PRT4_PRT\r
-SCSI_Out__1__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
-SCSI_Out__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
-SCSI_Out__1__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
-SCSI_Out__1__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
-SCSI_Out__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
-SCSI_Out__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
-SCSI_Out__1__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
-SCSI_Out__1__PS EQU CYREG_PRT4_PS\r
-SCSI_Out__1__SHIFT EQU 2\r
-SCSI_Out__1__SLW EQU CYREG_PRT4_SLW\r
-SCSI_Out__2__AG EQU CYREG_PRT0_AG\r
-SCSI_Out__2__AMUX EQU CYREG_PRT0_AMUX\r
-SCSI_Out__2__BIE EQU CYREG_PRT0_BIE\r
-SCSI_Out__2__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
-SCSI_Out__2__BYP EQU CYREG_PRT0_BYP\r
-SCSI_Out__2__CTL EQU CYREG_PRT0_CTL\r
-SCSI_Out__2__DM0 EQU CYREG_PRT0_DM0\r
-SCSI_Out__2__DM1 EQU CYREG_PRT0_DM1\r
-SCSI_Out__2__DM2 EQU CYREG_PRT0_DM2\r
-SCSI_Out__2__DR EQU CYREG_PRT0_DR\r
-SCSI_Out__2__INP_DIS EQU CYREG_PRT0_INP_DIS\r
-SCSI_Out__2__INTTYPE EQU CYREG_PICU0_INTTYPE7\r
-SCSI_Out__2__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
-SCSI_Out__2__LCD_EN EQU CYREG_PRT0_LCD_EN\r
-SCSI_Out__2__MASK EQU 0x80\r
-SCSI_Out__2__PC EQU CYREG_PRT0_PC7\r
-SCSI_Out__2__PORT EQU 0\r
-SCSI_Out__2__PRT EQU CYREG_PRT0_PRT\r
-SCSI_Out__2__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
-SCSI_Out__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
-SCSI_Out__2__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
-SCSI_Out__2__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
-SCSI_Out__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
-SCSI_Out__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
-SCSI_Out__2__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
-SCSI_Out__2__PS EQU CYREG_PRT0_PS\r
-SCSI_Out__2__SHIFT EQU 7\r
-SCSI_Out__2__SLW EQU CYREG_PRT0_SLW\r
-SCSI_Out__3__AG EQU CYREG_PRT0_AG\r
-SCSI_Out__3__AMUX EQU CYREG_PRT0_AMUX\r
-SCSI_Out__3__BIE EQU CYREG_PRT0_BIE\r
-SCSI_Out__3__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
-SCSI_Out__3__BYP EQU CYREG_PRT0_BYP\r
-SCSI_Out__3__CTL EQU CYREG_PRT0_CTL\r
-SCSI_Out__3__DM0 EQU CYREG_PRT0_DM0\r
-SCSI_Out__3__DM1 EQU CYREG_PRT0_DM1\r
-SCSI_Out__3__DM2 EQU CYREG_PRT0_DM2\r
-SCSI_Out__3__DR EQU CYREG_PRT0_DR\r
-SCSI_Out__3__INP_DIS EQU CYREG_PRT0_INP_DIS\r
-SCSI_Out__3__INTTYPE EQU CYREG_PICU0_INTTYPE6\r
-SCSI_Out__3__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
-SCSI_Out__3__LCD_EN EQU CYREG_PRT0_LCD_EN\r
-SCSI_Out__3__MASK EQU 0x40\r
-SCSI_Out__3__PC EQU CYREG_PRT0_PC6\r
-SCSI_Out__3__PORT EQU 0\r
-SCSI_Out__3__PRT EQU CYREG_PRT0_PRT\r
-SCSI_Out__3__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
-SCSI_Out__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
-SCSI_Out__3__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
-SCSI_Out__3__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
-SCSI_Out__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
-SCSI_Out__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
-SCSI_Out__3__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
-SCSI_Out__3__PS EQU CYREG_PRT0_PS\r
-SCSI_Out__3__SHIFT EQU 6\r
-SCSI_Out__3__SLW EQU CYREG_PRT0_SLW\r
-SCSI_Out__4__AG EQU CYREG_PRT0_AG\r
-SCSI_Out__4__AMUX EQU CYREG_PRT0_AMUX\r
-SCSI_Out__4__BIE EQU CYREG_PRT0_BIE\r
-SCSI_Out__4__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
-SCSI_Out__4__BYP EQU CYREG_PRT0_BYP\r
-SCSI_Out__4__CTL EQU CYREG_PRT0_CTL\r
-SCSI_Out__4__DM0 EQU CYREG_PRT0_DM0\r
-SCSI_Out__4__DM1 EQU CYREG_PRT0_DM1\r
-SCSI_Out__4__DM2 EQU CYREG_PRT0_DM2\r
-SCSI_Out__4__DR EQU CYREG_PRT0_DR\r
-SCSI_Out__4__INP_DIS EQU CYREG_PRT0_INP_DIS\r
-SCSI_Out__4__INTTYPE EQU CYREG_PICU0_INTTYPE5\r
-SCSI_Out__4__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
-SCSI_Out__4__LCD_EN EQU CYREG_PRT0_LCD_EN\r
-SCSI_Out__4__MASK EQU 0x20\r
-SCSI_Out__4__PC EQU CYREG_PRT0_PC5\r
-SCSI_Out__4__PORT EQU 0\r
-SCSI_Out__4__PRT EQU CYREG_PRT0_PRT\r
-SCSI_Out__4__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
-SCSI_Out__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
-SCSI_Out__4__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
-SCSI_Out__4__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
-SCSI_Out__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
-SCSI_Out__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
-SCSI_Out__4__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
-SCSI_Out__4__PS EQU CYREG_PRT0_PS\r
-SCSI_Out__4__SHIFT EQU 5\r
-SCSI_Out__4__SLW EQU CYREG_PRT0_SLW\r
-SCSI_Out__5__AG EQU CYREG_PRT0_AG\r
-SCSI_Out__5__AMUX EQU CYREG_PRT0_AMUX\r
-SCSI_Out__5__BIE EQU CYREG_PRT0_BIE\r
-SCSI_Out__5__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
-SCSI_Out__5__BYP EQU CYREG_PRT0_BYP\r
-SCSI_Out__5__CTL EQU CYREG_PRT0_CTL\r
-SCSI_Out__5__DM0 EQU CYREG_PRT0_DM0\r
-SCSI_Out__5__DM1 EQU CYREG_PRT0_DM1\r
-SCSI_Out__5__DM2 EQU CYREG_PRT0_DM2\r
-SCSI_Out__5__DR EQU CYREG_PRT0_DR\r
-SCSI_Out__5__INP_DIS EQU CYREG_PRT0_INP_DIS\r
-SCSI_Out__5__INTTYPE EQU CYREG_PICU0_INTTYPE4\r
-SCSI_Out__5__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
-SCSI_Out__5__LCD_EN EQU CYREG_PRT0_LCD_EN\r
-SCSI_Out__5__MASK EQU 0x10\r
-SCSI_Out__5__PC EQU CYREG_PRT0_PC4\r
-SCSI_Out__5__PORT EQU 0\r
-SCSI_Out__5__PRT EQU CYREG_PRT0_PRT\r
-SCSI_Out__5__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
-SCSI_Out__5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
-SCSI_Out__5__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
-SCSI_Out__5__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
-SCSI_Out__5__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
-SCSI_Out__5__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
-SCSI_Out__5__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
-SCSI_Out__5__PS EQU CYREG_PRT0_PS\r
-SCSI_Out__5__SHIFT EQU 4\r
-SCSI_Out__5__SLW EQU CYREG_PRT0_SLW\r
-SCSI_Out__6__AG EQU CYREG_PRT0_AG\r
-SCSI_Out__6__AMUX EQU CYREG_PRT0_AMUX\r
-SCSI_Out__6__BIE EQU CYREG_PRT0_BIE\r
-SCSI_Out__6__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
-SCSI_Out__6__BYP EQU CYREG_PRT0_BYP\r
-SCSI_Out__6__CTL EQU CYREG_PRT0_CTL\r
-SCSI_Out__6__DM0 EQU CYREG_PRT0_DM0\r
-SCSI_Out__6__DM1 EQU CYREG_PRT0_DM1\r
-SCSI_Out__6__DM2 EQU CYREG_PRT0_DM2\r
-SCSI_Out__6__DR EQU CYREG_PRT0_DR\r
-SCSI_Out__6__INP_DIS EQU CYREG_PRT0_INP_DIS\r
-SCSI_Out__6__INTTYPE EQU CYREG_PICU0_INTTYPE3\r
-SCSI_Out__6__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
-SCSI_Out__6__LCD_EN EQU CYREG_PRT0_LCD_EN\r
-SCSI_Out__6__MASK EQU 0x08\r
-SCSI_Out__6__PC EQU CYREG_PRT0_PC3\r
-SCSI_Out__6__PORT EQU 0\r
-SCSI_Out__6__PRT EQU CYREG_PRT0_PRT\r
-SCSI_Out__6__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
-SCSI_Out__6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
-SCSI_Out__6__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
-SCSI_Out__6__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
-SCSI_Out__6__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
-SCSI_Out__6__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
-SCSI_Out__6__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
-SCSI_Out__6__PS EQU CYREG_PRT0_PS\r
-SCSI_Out__6__SHIFT EQU 3\r
-SCSI_Out__6__SLW EQU CYREG_PRT0_SLW\r
-SCSI_Out__7__AG EQU CYREG_PRT0_AG\r
-SCSI_Out__7__AMUX EQU CYREG_PRT0_AMUX\r
-SCSI_Out__7__BIE EQU CYREG_PRT0_BIE\r
-SCSI_Out__7__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
-SCSI_Out__7__BYP EQU CYREG_PRT0_BYP\r
-SCSI_Out__7__CTL EQU CYREG_PRT0_CTL\r
-SCSI_Out__7__DM0 EQU CYREG_PRT0_DM0\r
-SCSI_Out__7__DM1 EQU CYREG_PRT0_DM1\r
-SCSI_Out__7__DM2 EQU CYREG_PRT0_DM2\r
-SCSI_Out__7__DR EQU CYREG_PRT0_DR\r
-SCSI_Out__7__INP_DIS EQU CYREG_PRT0_INP_DIS\r
-SCSI_Out__7__INTTYPE EQU CYREG_PICU0_INTTYPE2\r
-SCSI_Out__7__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
-SCSI_Out__7__LCD_EN EQU CYREG_PRT0_LCD_EN\r
-SCSI_Out__7__MASK EQU 0x04\r
-SCSI_Out__7__PC EQU CYREG_PRT0_PC2\r
-SCSI_Out__7__PORT EQU 0\r
-SCSI_Out__7__PRT EQU CYREG_PRT0_PRT\r
-SCSI_Out__7__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
-SCSI_Out__7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
-SCSI_Out__7__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
-SCSI_Out__7__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
-SCSI_Out__7__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
-SCSI_Out__7__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
-SCSI_Out__7__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
-SCSI_Out__7__PS EQU CYREG_PRT0_PS\r
-SCSI_Out__7__SHIFT EQU 2\r
-SCSI_Out__7__SLW EQU CYREG_PRT0_SLW\r
-SCSI_Out__8__AG EQU CYREG_PRT0_AG\r
-SCSI_Out__8__AMUX EQU CYREG_PRT0_AMUX\r
-SCSI_Out__8__BIE EQU CYREG_PRT0_BIE\r
-SCSI_Out__8__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
-SCSI_Out__8__BYP EQU CYREG_PRT0_BYP\r
-SCSI_Out__8__CTL EQU CYREG_PRT0_CTL\r
-SCSI_Out__8__DM0 EQU CYREG_PRT0_DM0\r
-SCSI_Out__8__DM1 EQU CYREG_PRT0_DM1\r
-SCSI_Out__8__DM2 EQU CYREG_PRT0_DM2\r
-SCSI_Out__8__DR EQU CYREG_PRT0_DR\r
-SCSI_Out__8__INP_DIS EQU CYREG_PRT0_INP_DIS\r
-SCSI_Out__8__INTTYPE EQU CYREG_PICU0_INTTYPE1\r
-SCSI_Out__8__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
-SCSI_Out__8__LCD_EN EQU CYREG_PRT0_LCD_EN\r
-SCSI_Out__8__MASK EQU 0x02\r
-SCSI_Out__8__PC EQU CYREG_PRT0_PC1\r
-SCSI_Out__8__PORT EQU 0\r
-SCSI_Out__8__PRT EQU CYREG_PRT0_PRT\r
-SCSI_Out__8__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
-SCSI_Out__8__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
-SCSI_Out__8__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
-SCSI_Out__8__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
-SCSI_Out__8__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
-SCSI_Out__8__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
-SCSI_Out__8__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
-SCSI_Out__8__PS EQU CYREG_PRT0_PS\r
-SCSI_Out__8__SHIFT EQU 1\r
-SCSI_Out__8__SLW EQU CYREG_PRT0_SLW\r
-SCSI_Out__9__AG EQU CYREG_PRT0_AG\r
-SCSI_Out__9__AMUX EQU CYREG_PRT0_AMUX\r
-SCSI_Out__9__BIE EQU CYREG_PRT0_BIE\r
-SCSI_Out__9__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
-SCSI_Out__9__BYP EQU CYREG_PRT0_BYP\r
-SCSI_Out__9__CTL EQU CYREG_PRT0_CTL\r
-SCSI_Out__9__DM0 EQU CYREG_PRT0_DM0\r
-SCSI_Out__9__DM1 EQU CYREG_PRT0_DM1\r
-SCSI_Out__9__DM2 EQU CYREG_PRT0_DM2\r
-SCSI_Out__9__DR EQU CYREG_PRT0_DR\r
-SCSI_Out__9__INP_DIS EQU CYREG_PRT0_INP_DIS\r
-SCSI_Out__9__INTTYPE EQU CYREG_PICU0_INTTYPE0\r
-SCSI_Out__9__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
-SCSI_Out__9__LCD_EN EQU CYREG_PRT0_LCD_EN\r
-SCSI_Out__9__MASK EQU 0x01\r
-SCSI_Out__9__PC EQU CYREG_PRT0_PC0\r
-SCSI_Out__9__PORT EQU 0\r
-SCSI_Out__9__PRT EQU CYREG_PRT0_PRT\r
-SCSI_Out__9__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
-SCSI_Out__9__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
-SCSI_Out__9__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
-SCSI_Out__9__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
-SCSI_Out__9__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
-SCSI_Out__9__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
-SCSI_Out__9__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
-SCSI_Out__9__PS EQU CYREG_PRT0_PS\r
-SCSI_Out__9__SHIFT EQU 0\r
-SCSI_Out__9__SLW EQU CYREG_PRT0_SLW\r
-SCSI_Out__ACK__AG EQU CYREG_PRT0_AG\r
-SCSI_Out__ACK__AMUX EQU CYREG_PRT0_AMUX\r
-SCSI_Out__ACK__BIE EQU CYREG_PRT0_BIE\r
-SCSI_Out__ACK__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
-SCSI_Out__ACK__BYP EQU CYREG_PRT0_BYP\r
-SCSI_Out__ACK__CTL EQU CYREG_PRT0_CTL\r
-SCSI_Out__ACK__DM0 EQU CYREG_PRT0_DM0\r
-SCSI_Out__ACK__DM1 EQU CYREG_PRT0_DM1\r
-SCSI_Out__ACK__DM2 EQU CYREG_PRT0_DM2\r
-SCSI_Out__ACK__DR EQU CYREG_PRT0_DR\r
-SCSI_Out__ACK__INP_DIS EQU CYREG_PRT0_INP_DIS\r
-SCSI_Out__ACK__INTTYPE EQU CYREG_PICU0_INTTYPE6\r
-SCSI_Out__ACK__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
-SCSI_Out__ACK__LCD_EN EQU CYREG_PRT0_LCD_EN\r
-SCSI_Out__ACK__MASK EQU 0x40\r
-SCSI_Out__ACK__PC EQU CYREG_PRT0_PC6\r
-SCSI_Out__ACK__PORT EQU 0\r
-SCSI_Out__ACK__PRT EQU CYREG_PRT0_PRT\r
-SCSI_Out__ACK__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
-SCSI_Out__ACK__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
-SCSI_Out__ACK__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
-SCSI_Out__ACK__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
-SCSI_Out__ACK__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
-SCSI_Out__ACK__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
-SCSI_Out__ACK__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
-SCSI_Out__ACK__PS EQU CYREG_PRT0_PS\r
-SCSI_Out__ACK__SHIFT EQU 6\r
-SCSI_Out__ACK__SLW EQU CYREG_PRT0_SLW\r
-SCSI_Out__ATN__AG EQU CYREG_PRT4_AG\r
-SCSI_Out__ATN__AMUX EQU CYREG_PRT4_AMUX\r
-SCSI_Out__ATN__BIE EQU CYREG_PRT4_BIE\r
-SCSI_Out__ATN__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
-SCSI_Out__ATN__BYP EQU CYREG_PRT4_BYP\r
-SCSI_Out__ATN__CTL EQU CYREG_PRT4_CTL\r
-SCSI_Out__ATN__DM0 EQU CYREG_PRT4_DM0\r
-SCSI_Out__ATN__DM1 EQU CYREG_PRT4_DM1\r
-SCSI_Out__ATN__DM2 EQU CYREG_PRT4_DM2\r
-SCSI_Out__ATN__DR EQU CYREG_PRT4_DR\r
-SCSI_Out__ATN__INP_DIS EQU CYREG_PRT4_INP_DIS\r
-SCSI_Out__ATN__INTTYPE EQU CYREG_PICU4_INTTYPE2\r
-SCSI_Out__ATN__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
-SCSI_Out__ATN__LCD_EN EQU CYREG_PRT4_LCD_EN\r
-SCSI_Out__ATN__MASK EQU 0x04\r
-SCSI_Out__ATN__PC EQU CYREG_PRT4_PC2\r
-SCSI_Out__ATN__PORT EQU 4\r
-SCSI_Out__ATN__PRT EQU CYREG_PRT4_PRT\r
-SCSI_Out__ATN__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
-SCSI_Out__ATN__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
-SCSI_Out__ATN__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
-SCSI_Out__ATN__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
-SCSI_Out__ATN__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
-SCSI_Out__ATN__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
-SCSI_Out__ATN__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
-SCSI_Out__ATN__PS EQU CYREG_PRT4_PS\r
-SCSI_Out__ATN__SHIFT EQU 2\r
-SCSI_Out__ATN__SLW EQU CYREG_PRT4_SLW\r
-SCSI_Out__BSY__AG EQU CYREG_PRT0_AG\r
-SCSI_Out__BSY__AMUX EQU CYREG_PRT0_AMUX\r
-SCSI_Out__BSY__BIE EQU CYREG_PRT0_BIE\r
-SCSI_Out__BSY__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
-SCSI_Out__BSY__BYP EQU CYREG_PRT0_BYP\r
-SCSI_Out__BSY__CTL EQU CYREG_PRT0_CTL\r
-SCSI_Out__BSY__DM0 EQU CYREG_PRT0_DM0\r
-SCSI_Out__BSY__DM1 EQU CYREG_PRT0_DM1\r
-SCSI_Out__BSY__DM2 EQU CYREG_PRT0_DM2\r
-SCSI_Out__BSY__DR EQU CYREG_PRT0_DR\r
-SCSI_Out__BSY__INP_DIS EQU CYREG_PRT0_INP_DIS\r
-SCSI_Out__BSY__INTTYPE EQU CYREG_PICU0_INTTYPE7\r
-SCSI_Out__BSY__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
-SCSI_Out__BSY__LCD_EN EQU CYREG_PRT0_LCD_EN\r
-SCSI_Out__BSY__MASK EQU 0x80\r
-SCSI_Out__BSY__PC EQU CYREG_PRT0_PC7\r
-SCSI_Out__BSY__PORT EQU 0\r
-SCSI_Out__BSY__PRT EQU CYREG_PRT0_PRT\r
-SCSI_Out__BSY__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
-SCSI_Out__BSY__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
-SCSI_Out__BSY__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
-SCSI_Out__BSY__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
-SCSI_Out__BSY__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
-SCSI_Out__BSY__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
-SCSI_Out__BSY__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
-SCSI_Out__BSY__PS EQU CYREG_PRT0_PS\r
-SCSI_Out__BSY__SHIFT EQU 7\r
-SCSI_Out__BSY__SLW EQU CYREG_PRT0_SLW\r
-SCSI_Out__CD_raw__AG EQU CYREG_PRT0_AG\r
-SCSI_Out__CD_raw__AMUX EQU CYREG_PRT0_AMUX\r
-SCSI_Out__CD_raw__BIE EQU CYREG_PRT0_BIE\r
-SCSI_Out__CD_raw__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
-SCSI_Out__CD_raw__BYP EQU CYREG_PRT0_BYP\r
-SCSI_Out__CD_raw__CTL EQU CYREG_PRT0_CTL\r
-SCSI_Out__CD_raw__DM0 EQU CYREG_PRT0_DM0\r
-SCSI_Out__CD_raw__DM1 EQU CYREG_PRT0_DM1\r
-SCSI_Out__CD_raw__DM2 EQU CYREG_PRT0_DM2\r
-SCSI_Out__CD_raw__DR EQU CYREG_PRT0_DR\r
-SCSI_Out__CD_raw__INP_DIS EQU CYREG_PRT0_INP_DIS\r
-SCSI_Out__CD_raw__INTTYPE EQU CYREG_PICU0_INTTYPE2\r
-SCSI_Out__CD_raw__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
-SCSI_Out__CD_raw__LCD_EN EQU CYREG_PRT0_LCD_EN\r
-SCSI_Out__CD_raw__MASK EQU 0x04\r
-SCSI_Out__CD_raw__PC EQU CYREG_PRT0_PC2\r
-SCSI_Out__CD_raw__PORT EQU 0\r
-SCSI_Out__CD_raw__PRT EQU CYREG_PRT0_PRT\r
-SCSI_Out__CD_raw__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
-SCSI_Out__CD_raw__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
-SCSI_Out__CD_raw__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
-SCSI_Out__CD_raw__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
-SCSI_Out__CD_raw__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
-SCSI_Out__CD_raw__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
-SCSI_Out__CD_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
-SCSI_Out__CD_raw__PS EQU CYREG_PRT0_PS\r
-SCSI_Out__CD_raw__SHIFT EQU 2\r
-SCSI_Out__CD_raw__SLW EQU CYREG_PRT0_SLW\r
-SCSI_Out__DBP_raw__AG EQU CYREG_PRT4_AG\r
-SCSI_Out__DBP_raw__AMUX EQU CYREG_PRT4_AMUX\r
-SCSI_Out__DBP_raw__BIE EQU CYREG_PRT4_BIE\r
-SCSI_Out__DBP_raw__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
-SCSI_Out__DBP_raw__BYP EQU CYREG_PRT4_BYP\r
-SCSI_Out__DBP_raw__CTL EQU CYREG_PRT4_CTL\r
-SCSI_Out__DBP_raw__DM0 EQU CYREG_PRT4_DM0\r
-SCSI_Out__DBP_raw__DM1 EQU CYREG_PRT4_DM1\r
-SCSI_Out__DBP_raw__DM2 EQU CYREG_PRT4_DM2\r
-SCSI_Out__DBP_raw__DR EQU CYREG_PRT4_DR\r
-SCSI_Out__DBP_raw__INP_DIS EQU CYREG_PRT4_INP_DIS\r
-SCSI_Out__DBP_raw__INTTYPE EQU CYREG_PICU4_INTTYPE3\r
-SCSI_Out__DBP_raw__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
-SCSI_Out__DBP_raw__LCD_EN EQU CYREG_PRT4_LCD_EN\r
-SCSI_Out__DBP_raw__MASK EQU 0x08\r
-SCSI_Out__DBP_raw__PC EQU CYREG_PRT4_PC3\r
-SCSI_Out__DBP_raw__PORT EQU 4\r
-SCSI_Out__DBP_raw__PRT EQU CYREG_PRT4_PRT\r
-SCSI_Out__DBP_raw__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
-SCSI_Out__DBP_raw__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
-SCSI_Out__DBP_raw__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
-SCSI_Out__DBP_raw__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
-SCSI_Out__DBP_raw__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
-SCSI_Out__DBP_raw__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
-SCSI_Out__DBP_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
-SCSI_Out__DBP_raw__PS EQU CYREG_PRT4_PS\r
-SCSI_Out__DBP_raw__SHIFT EQU 3\r
-SCSI_Out__DBP_raw__SLW EQU CYREG_PRT4_SLW\r
-SCSI_Out__IO_raw__AG EQU CYREG_PRT0_AG\r
-SCSI_Out__IO_raw__AMUX EQU CYREG_PRT0_AMUX\r
-SCSI_Out__IO_raw__BIE EQU CYREG_PRT0_BIE\r
-SCSI_Out__IO_raw__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
-SCSI_Out__IO_raw__BYP EQU CYREG_PRT0_BYP\r
-SCSI_Out__IO_raw__CTL EQU CYREG_PRT0_CTL\r
-SCSI_Out__IO_raw__DM0 EQU CYREG_PRT0_DM0\r
-SCSI_Out__IO_raw__DM1 EQU CYREG_PRT0_DM1\r
-SCSI_Out__IO_raw__DM2 EQU CYREG_PRT0_DM2\r
-SCSI_Out__IO_raw__DR EQU CYREG_PRT0_DR\r
-SCSI_Out__IO_raw__INP_DIS EQU CYREG_PRT0_INP_DIS\r
-SCSI_Out__IO_raw__INTTYPE EQU CYREG_PICU0_INTTYPE0\r
-SCSI_Out__IO_raw__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
-SCSI_Out__IO_raw__LCD_EN EQU CYREG_PRT0_LCD_EN\r
-SCSI_Out__IO_raw__MASK EQU 0x01\r
-SCSI_Out__IO_raw__PC EQU CYREG_PRT0_PC0\r
-SCSI_Out__IO_raw__PORT EQU 0\r
-SCSI_Out__IO_raw__PRT EQU CYREG_PRT0_PRT\r
-SCSI_Out__IO_raw__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
-SCSI_Out__IO_raw__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
-SCSI_Out__IO_raw__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
-SCSI_Out__IO_raw__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
-SCSI_Out__IO_raw__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
-SCSI_Out__IO_raw__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
-SCSI_Out__IO_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
-SCSI_Out__IO_raw__PS EQU CYREG_PRT0_PS\r
-SCSI_Out__IO_raw__SHIFT EQU 0\r
-SCSI_Out__IO_raw__SLW EQU CYREG_PRT0_SLW\r
-SCSI_Out__MSG_raw__AG EQU CYREG_PRT0_AG\r
-SCSI_Out__MSG_raw__AMUX EQU CYREG_PRT0_AMUX\r
-SCSI_Out__MSG_raw__BIE EQU CYREG_PRT0_BIE\r
-SCSI_Out__MSG_raw__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
-SCSI_Out__MSG_raw__BYP EQU CYREG_PRT0_BYP\r
-SCSI_Out__MSG_raw__CTL EQU CYREG_PRT0_CTL\r
-SCSI_Out__MSG_raw__DM0 EQU CYREG_PRT0_DM0\r
-SCSI_Out__MSG_raw__DM1 EQU CYREG_PRT0_DM1\r
-SCSI_Out__MSG_raw__DM2 EQU CYREG_PRT0_DM2\r
-SCSI_Out__MSG_raw__DR EQU CYREG_PRT0_DR\r
-SCSI_Out__MSG_raw__INP_DIS EQU CYREG_PRT0_INP_DIS\r
-SCSI_Out__MSG_raw__INTTYPE EQU CYREG_PICU0_INTTYPE4\r
-SCSI_Out__MSG_raw__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
-SCSI_Out__MSG_raw__LCD_EN EQU CYREG_PRT0_LCD_EN\r
-SCSI_Out__MSG_raw__MASK EQU 0x10\r
-SCSI_Out__MSG_raw__PC EQU CYREG_PRT0_PC4\r
-SCSI_Out__MSG_raw__PORT EQU 0\r
-SCSI_Out__MSG_raw__PRT EQU CYREG_PRT0_PRT\r
-SCSI_Out__MSG_raw__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
-SCSI_Out__MSG_raw__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
-SCSI_Out__MSG_raw__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
-SCSI_Out__MSG_raw__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
-SCSI_Out__MSG_raw__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
-SCSI_Out__MSG_raw__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
-SCSI_Out__MSG_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
-SCSI_Out__MSG_raw__PS EQU CYREG_PRT0_PS\r
-SCSI_Out__MSG_raw__SHIFT EQU 4\r
-SCSI_Out__MSG_raw__SLW EQU CYREG_PRT0_SLW\r
-SCSI_Out__REQ__AG EQU CYREG_PRT0_AG\r
-SCSI_Out__REQ__AMUX EQU CYREG_PRT0_AMUX\r
-SCSI_Out__REQ__BIE EQU CYREG_PRT0_BIE\r
-SCSI_Out__REQ__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
-SCSI_Out__REQ__BYP EQU CYREG_PRT0_BYP\r
-SCSI_Out__REQ__CTL EQU CYREG_PRT0_CTL\r
-SCSI_Out__REQ__DM0 EQU CYREG_PRT0_DM0\r
-SCSI_Out__REQ__DM1 EQU CYREG_PRT0_DM1\r
-SCSI_Out__REQ__DM2 EQU CYREG_PRT0_DM2\r
-SCSI_Out__REQ__DR EQU CYREG_PRT0_DR\r
-SCSI_Out__REQ__INP_DIS EQU CYREG_PRT0_INP_DIS\r
-SCSI_Out__REQ__INTTYPE EQU CYREG_PICU0_INTTYPE1\r
-SCSI_Out__REQ__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
-SCSI_Out__REQ__LCD_EN EQU CYREG_PRT0_LCD_EN\r
-SCSI_Out__REQ__MASK EQU 0x02\r
-SCSI_Out__REQ__PC EQU CYREG_PRT0_PC1\r
-SCSI_Out__REQ__PORT EQU 0\r
-SCSI_Out__REQ__PRT EQU CYREG_PRT0_PRT\r
-SCSI_Out__REQ__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
-SCSI_Out__REQ__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
-SCSI_Out__REQ__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
-SCSI_Out__REQ__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
-SCSI_Out__REQ__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
-SCSI_Out__REQ__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
-SCSI_Out__REQ__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
-SCSI_Out__REQ__PS EQU CYREG_PRT0_PS\r
-SCSI_Out__REQ__SHIFT EQU 1\r
-SCSI_Out__REQ__SLW EQU CYREG_PRT0_SLW\r
-SCSI_Out__RST__AG EQU CYREG_PRT0_AG\r
-SCSI_Out__RST__AMUX EQU CYREG_PRT0_AMUX\r
-SCSI_Out__RST__BIE EQU CYREG_PRT0_BIE\r
-SCSI_Out__RST__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
-SCSI_Out__RST__BYP EQU CYREG_PRT0_BYP\r
-SCSI_Out__RST__CTL EQU CYREG_PRT0_CTL\r
-SCSI_Out__RST__DM0 EQU CYREG_PRT0_DM0\r
-SCSI_Out__RST__DM1 EQU CYREG_PRT0_DM1\r
-SCSI_Out__RST__DM2 EQU CYREG_PRT0_DM2\r
-SCSI_Out__RST__DR EQU CYREG_PRT0_DR\r
-SCSI_Out__RST__INP_DIS EQU CYREG_PRT0_INP_DIS\r
-SCSI_Out__RST__INTTYPE EQU CYREG_PICU0_INTTYPE5\r
-SCSI_Out__RST__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
-SCSI_Out__RST__LCD_EN EQU CYREG_PRT0_LCD_EN\r
-SCSI_Out__RST__MASK EQU 0x20\r
-SCSI_Out__RST__PC EQU CYREG_PRT0_PC5\r
-SCSI_Out__RST__PORT EQU 0\r
-SCSI_Out__RST__PRT EQU CYREG_PRT0_PRT\r
-SCSI_Out__RST__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
-SCSI_Out__RST__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
-SCSI_Out__RST__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
-SCSI_Out__RST__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
-SCSI_Out__RST__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
-SCSI_Out__RST__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
-SCSI_Out__RST__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
-SCSI_Out__RST__PS EQU CYREG_PRT0_PS\r
-SCSI_Out__RST__SHIFT EQU 5\r
-SCSI_Out__RST__SLW EQU CYREG_PRT0_SLW\r
-SCSI_Out__SEL__AG EQU CYREG_PRT0_AG\r
-SCSI_Out__SEL__AMUX EQU CYREG_PRT0_AMUX\r
-SCSI_Out__SEL__BIE EQU CYREG_PRT0_BIE\r
-SCSI_Out__SEL__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
-SCSI_Out__SEL__BYP EQU CYREG_PRT0_BYP\r
-SCSI_Out__SEL__CTL EQU CYREG_PRT0_CTL\r
-SCSI_Out__SEL__DM0 EQU CYREG_PRT0_DM0\r
-SCSI_Out__SEL__DM1 EQU CYREG_PRT0_DM1\r
-SCSI_Out__SEL__DM2 EQU CYREG_PRT0_DM2\r
-SCSI_Out__SEL__DR EQU CYREG_PRT0_DR\r
-SCSI_Out__SEL__INP_DIS EQU CYREG_PRT0_INP_DIS\r
-SCSI_Out__SEL__INTTYPE EQU CYREG_PICU0_INTTYPE3\r
-SCSI_Out__SEL__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
-SCSI_Out__SEL__LCD_EN EQU CYREG_PRT0_LCD_EN\r
-SCSI_Out__SEL__MASK EQU 0x08\r
-SCSI_Out__SEL__PC EQU CYREG_PRT0_PC3\r
-SCSI_Out__SEL__PORT EQU 0\r
-SCSI_Out__SEL__PRT EQU CYREG_PRT0_PRT\r
-SCSI_Out__SEL__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
-SCSI_Out__SEL__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
-SCSI_Out__SEL__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
-SCSI_Out__SEL__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
-SCSI_Out__SEL__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
-SCSI_Out__SEL__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
-SCSI_Out__SEL__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
-SCSI_Out__SEL__PS EQU CYREG_PRT0_PS\r
-SCSI_Out__SEL__SHIFT EQU 3\r
-SCSI_Out__SEL__SLW EQU CYREG_PRT0_SLW\r
-SCSI_Out_Bits_Sync_ctrl_reg__0__MASK EQU 0x01\r
-SCSI_Out_Bits_Sync_ctrl_reg__0__POS EQU 0\r
-SCSI_Out_Bits_Sync_ctrl_reg__1__MASK EQU 0x02\r
-SCSI_Out_Bits_Sync_ctrl_reg__1__POS EQU 1\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB08_09_ACTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB08_09_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB08_09_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB08_09_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB08_09_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB08_09_MSK\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB08_09_MSK\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB08_09_MSK\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB08_09_MSK\r
-SCSI_Out_Bits_Sync_ctrl_reg__2__MASK EQU 0x04\r
-SCSI_Out_Bits_Sync_ctrl_reg__2__POS EQU 2\r
-SCSI_Out_Bits_Sync_ctrl_reg__3__MASK EQU 0x08\r
-SCSI_Out_Bits_Sync_ctrl_reg__3__POS EQU 3\r
-SCSI_Out_Bits_Sync_ctrl_reg__4__MASK EQU 0x10\r
-SCSI_Out_Bits_Sync_ctrl_reg__4__POS EQU 4\r
-SCSI_Out_Bits_Sync_ctrl_reg__5__MASK EQU 0x20\r
-SCSI_Out_Bits_Sync_ctrl_reg__5__POS EQU 5\r
-SCSI_Out_Bits_Sync_ctrl_reg__6__MASK EQU 0x40\r
-SCSI_Out_Bits_Sync_ctrl_reg__6__POS EQU 6\r
-SCSI_Out_Bits_Sync_ctrl_reg__7__MASK EQU 0x80\r
-SCSI_Out_Bits_Sync_ctrl_reg__7__POS EQU 7\r
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB08_ACTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B1_UDB08_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B1_UDB08_ST_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B1_UDB08_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B1_UDB08_ST_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__MASK EQU 0xFF\r
-SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB08_MSK_ACTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB08_MSK_ACTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B1_UDB08_MSK\r
-SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01\r
-SCSI_Out_Ctl_Sync_ctrl_reg__0__POS EQU 0\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB08_09_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB08_09_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB08_09_MSK\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB08_09_MSK\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK\r
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB08_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB08_ST_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB08_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB08_ST_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__MASK EQU 0x01\r
-SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB08_MSK\r
-SCSI_Out_DBx__0__AG EQU CYREG_PRT6_AG\r
-SCSI_Out_DBx__0__AMUX EQU CYREG_PRT6_AMUX\r
-SCSI_Out_DBx__0__BIE EQU CYREG_PRT6_BIE\r
-SCSI_Out_DBx__0__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
-SCSI_Out_DBx__0__BYP EQU CYREG_PRT6_BYP\r
-SCSI_Out_DBx__0__CTL EQU CYREG_PRT6_CTL\r
-SCSI_Out_DBx__0__DM0 EQU CYREG_PRT6_DM0\r
-SCSI_Out_DBx__0__DM1 EQU CYREG_PRT6_DM1\r
-SCSI_Out_DBx__0__DM2 EQU CYREG_PRT6_DM2\r
-SCSI_Out_DBx__0__DR EQU CYREG_PRT6_DR\r
-SCSI_Out_DBx__0__INP_DIS EQU CYREG_PRT6_INP_DIS\r
-SCSI_Out_DBx__0__INTTYPE EQU CYREG_PICU6_INTTYPE3\r
-SCSI_Out_DBx__0__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
-SCSI_Out_DBx__0__LCD_EN EQU CYREG_PRT6_LCD_EN\r
-SCSI_Out_DBx__0__MASK EQU 0x08\r
-SCSI_Out_DBx__0__PC EQU CYREG_PRT6_PC3\r
-SCSI_Out_DBx__0__PORT EQU 6\r
-SCSI_Out_DBx__0__PRT EQU CYREG_PRT6_PRT\r
-SCSI_Out_DBx__0__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
-SCSI_Out_DBx__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
-SCSI_Out_DBx__0__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
-SCSI_Out_DBx__0__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
-SCSI_Out_DBx__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
-SCSI_Out_DBx__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
-SCSI_Out_DBx__0__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
-SCSI_Out_DBx__0__PS EQU CYREG_PRT6_PS\r
-SCSI_Out_DBx__0__SHIFT EQU 3\r
-SCSI_Out_DBx__0__SLW EQU CYREG_PRT6_SLW\r
-SCSI_Out_DBx__1__AG EQU CYREG_PRT6_AG\r
-SCSI_Out_DBx__1__AMUX EQU CYREG_PRT6_AMUX\r
-SCSI_Out_DBx__1__BIE EQU CYREG_PRT6_BIE\r
-SCSI_Out_DBx__1__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
-SCSI_Out_DBx__1__BYP EQU CYREG_PRT6_BYP\r
-SCSI_Out_DBx__1__CTL EQU CYREG_PRT6_CTL\r
-SCSI_Out_DBx__1__DM0 EQU CYREG_PRT6_DM0\r
-SCSI_Out_DBx__1__DM1 EQU CYREG_PRT6_DM1\r
-SCSI_Out_DBx__1__DM2 EQU CYREG_PRT6_DM2\r
-SCSI_Out_DBx__1__DR EQU CYREG_PRT6_DR\r
-SCSI_Out_DBx__1__INP_DIS EQU CYREG_PRT6_INP_DIS\r
-SCSI_Out_DBx__1__INTTYPE EQU CYREG_PICU6_INTTYPE2\r
-SCSI_Out_DBx__1__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
-SCSI_Out_DBx__1__LCD_EN EQU CYREG_PRT6_LCD_EN\r
-SCSI_Out_DBx__1__MASK EQU 0x04\r
-SCSI_Out_DBx__1__PC EQU CYREG_PRT6_PC2\r
-SCSI_Out_DBx__1__PORT EQU 6\r
-SCSI_Out_DBx__1__PRT EQU CYREG_PRT6_PRT\r
-SCSI_Out_DBx__1__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
-SCSI_Out_DBx__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
-SCSI_Out_DBx__1__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
-SCSI_Out_DBx__1__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
-SCSI_Out_DBx__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
-SCSI_Out_DBx__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
-SCSI_Out_DBx__1__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
-SCSI_Out_DBx__1__PS EQU CYREG_PRT6_PS\r
-SCSI_Out_DBx__1__SHIFT EQU 2\r
-SCSI_Out_DBx__1__SLW EQU CYREG_PRT6_SLW\r
-SCSI_Out_DBx__2__AG EQU CYREG_PRT6_AG\r
-SCSI_Out_DBx__2__AMUX EQU CYREG_PRT6_AMUX\r
-SCSI_Out_DBx__2__BIE EQU CYREG_PRT6_BIE\r
-SCSI_Out_DBx__2__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
-SCSI_Out_DBx__2__BYP EQU CYREG_PRT6_BYP\r
-SCSI_Out_DBx__2__CTL EQU CYREG_PRT6_CTL\r
-SCSI_Out_DBx__2__DM0 EQU CYREG_PRT6_DM0\r
-SCSI_Out_DBx__2__DM1 EQU CYREG_PRT6_DM1\r
-SCSI_Out_DBx__2__DM2 EQU CYREG_PRT6_DM2\r
-SCSI_Out_DBx__2__DR EQU CYREG_PRT6_DR\r
-SCSI_Out_DBx__2__INP_DIS EQU CYREG_PRT6_INP_DIS\r
-SCSI_Out_DBx__2__INTTYPE EQU CYREG_PICU6_INTTYPE1\r
-SCSI_Out_DBx__2__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
-SCSI_Out_DBx__2__LCD_EN EQU CYREG_PRT6_LCD_EN\r
-SCSI_Out_DBx__2__MASK EQU 0x02\r
-SCSI_Out_DBx__2__PC EQU CYREG_PRT6_PC1\r
-SCSI_Out_DBx__2__PORT EQU 6\r
-SCSI_Out_DBx__2__PRT EQU CYREG_PRT6_PRT\r
-SCSI_Out_DBx__2__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
-SCSI_Out_DBx__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
-SCSI_Out_DBx__2__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
-SCSI_Out_DBx__2__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
-SCSI_Out_DBx__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
-SCSI_Out_DBx__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
-SCSI_Out_DBx__2__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
-SCSI_Out_DBx__2__PS EQU CYREG_PRT6_PS\r
-SCSI_Out_DBx__2__SHIFT EQU 1\r
-SCSI_Out_DBx__2__SLW EQU CYREG_PRT6_SLW\r
-SCSI_Out_DBx__3__AG EQU CYREG_PRT6_AG\r
-SCSI_Out_DBx__3__AMUX EQU CYREG_PRT6_AMUX\r
-SCSI_Out_DBx__3__BIE EQU CYREG_PRT6_BIE\r
-SCSI_Out_DBx__3__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
-SCSI_Out_DBx__3__BYP EQU CYREG_PRT6_BYP\r
-SCSI_Out_DBx__3__CTL EQU CYREG_PRT6_CTL\r
-SCSI_Out_DBx__3__DM0 EQU CYREG_PRT6_DM0\r
-SCSI_Out_DBx__3__DM1 EQU CYREG_PRT6_DM1\r
-SCSI_Out_DBx__3__DM2 EQU CYREG_PRT6_DM2\r
-SCSI_Out_DBx__3__DR EQU CYREG_PRT6_DR\r
-SCSI_Out_DBx__3__INP_DIS EQU CYREG_PRT6_INP_DIS\r
-SCSI_Out_DBx__3__INTTYPE EQU CYREG_PICU6_INTTYPE0\r
-SCSI_Out_DBx__3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
-SCSI_Out_DBx__3__LCD_EN EQU CYREG_PRT6_LCD_EN\r
-SCSI_Out_DBx__3__MASK EQU 0x01\r
-SCSI_Out_DBx__3__PC EQU CYREG_PRT6_PC0\r
-SCSI_Out_DBx__3__PORT EQU 6\r
-SCSI_Out_DBx__3__PRT EQU CYREG_PRT6_PRT\r
-SCSI_Out_DBx__3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
-SCSI_Out_DBx__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
-SCSI_Out_DBx__3__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
-SCSI_Out_DBx__3__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
-SCSI_Out_DBx__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
-SCSI_Out_DBx__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
-SCSI_Out_DBx__3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
-SCSI_Out_DBx__3__PS EQU CYREG_PRT6_PS\r
-SCSI_Out_DBx__3__SHIFT EQU 0\r
-SCSI_Out_DBx__3__SLW EQU CYREG_PRT6_SLW\r
-SCSI_Out_DBx__4__AG EQU CYREG_PRT4_AG\r
-SCSI_Out_DBx__4__AMUX EQU CYREG_PRT4_AMUX\r
-SCSI_Out_DBx__4__BIE EQU CYREG_PRT4_BIE\r
-SCSI_Out_DBx__4__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
-SCSI_Out_DBx__4__BYP EQU CYREG_PRT4_BYP\r
-SCSI_Out_DBx__4__CTL EQU CYREG_PRT4_CTL\r
-SCSI_Out_DBx__4__DM0 EQU CYREG_PRT4_DM0\r
-SCSI_Out_DBx__4__DM1 EQU CYREG_PRT4_DM1\r
-SCSI_Out_DBx__4__DM2 EQU CYREG_PRT4_DM2\r
-SCSI_Out_DBx__4__DR EQU CYREG_PRT4_DR\r
-SCSI_Out_DBx__4__INP_DIS EQU CYREG_PRT4_INP_DIS\r
-SCSI_Out_DBx__4__INTTYPE EQU CYREG_PICU4_INTTYPE7\r
-SCSI_Out_DBx__4__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
-SCSI_Out_DBx__4__LCD_EN EQU CYREG_PRT4_LCD_EN\r
-SCSI_Out_DBx__4__MASK EQU 0x80\r
-SCSI_Out_DBx__4__PC EQU CYREG_PRT4_PC7\r
-SCSI_Out_DBx__4__PORT EQU 4\r
-SCSI_Out_DBx__4__PRT EQU CYREG_PRT4_PRT\r
-SCSI_Out_DBx__4__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
-SCSI_Out_DBx__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
-SCSI_Out_DBx__4__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
-SCSI_Out_DBx__4__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
-SCSI_Out_DBx__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
-SCSI_Out_DBx__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
-SCSI_Out_DBx__4__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
-SCSI_Out_DBx__4__PS EQU CYREG_PRT4_PS\r
-SCSI_Out_DBx__4__SHIFT EQU 7\r
-SCSI_Out_DBx__4__SLW EQU CYREG_PRT4_SLW\r
-SCSI_Out_DBx__5__AG EQU CYREG_PRT4_AG\r
-SCSI_Out_DBx__5__AMUX EQU CYREG_PRT4_AMUX\r
-SCSI_Out_DBx__5__BIE EQU CYREG_PRT4_BIE\r
-SCSI_Out_DBx__5__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
-SCSI_Out_DBx__5__BYP EQU CYREG_PRT4_BYP\r
-SCSI_Out_DBx__5__CTL EQU CYREG_PRT4_CTL\r
-SCSI_Out_DBx__5__DM0 EQU CYREG_PRT4_DM0\r
-SCSI_Out_DBx__5__DM1 EQU CYREG_PRT4_DM1\r
-SCSI_Out_DBx__5__DM2 EQU CYREG_PRT4_DM2\r
-SCSI_Out_DBx__5__DR EQU CYREG_PRT4_DR\r
-SCSI_Out_DBx__5__INP_DIS EQU CYREG_PRT4_INP_DIS\r
-SCSI_Out_DBx__5__INTTYPE EQU CYREG_PICU4_INTTYPE6\r
-SCSI_Out_DBx__5__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
-SCSI_Out_DBx__5__LCD_EN EQU CYREG_PRT4_LCD_EN\r
-SCSI_Out_DBx__5__MASK EQU 0x40\r
-SCSI_Out_DBx__5__PC EQU CYREG_PRT4_PC6\r
-SCSI_Out_DBx__5__PORT EQU 4\r
-SCSI_Out_DBx__5__PRT EQU CYREG_PRT4_PRT\r
-SCSI_Out_DBx__5__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
-SCSI_Out_DBx__5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
-SCSI_Out_DBx__5__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
-SCSI_Out_DBx__5__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
-SCSI_Out_DBx__5__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
-SCSI_Out_DBx__5__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
-SCSI_Out_DBx__5__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
-SCSI_Out_DBx__5__PS EQU CYREG_PRT4_PS\r
-SCSI_Out_DBx__5__SHIFT EQU 6\r
-SCSI_Out_DBx__5__SLW EQU CYREG_PRT4_SLW\r
-SCSI_Out_DBx__6__AG EQU CYREG_PRT4_AG\r
-SCSI_Out_DBx__6__AMUX EQU CYREG_PRT4_AMUX\r
-SCSI_Out_DBx__6__BIE EQU CYREG_PRT4_BIE\r
-SCSI_Out_DBx__6__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
-SCSI_Out_DBx__6__BYP EQU CYREG_PRT4_BYP\r
-SCSI_Out_DBx__6__CTL EQU CYREG_PRT4_CTL\r
-SCSI_Out_DBx__6__DM0 EQU CYREG_PRT4_DM0\r
-SCSI_Out_DBx__6__DM1 EQU CYREG_PRT4_DM1\r
-SCSI_Out_DBx__6__DM2 EQU CYREG_PRT4_DM2\r
-SCSI_Out_DBx__6__DR EQU CYREG_PRT4_DR\r
-SCSI_Out_DBx__6__INP_DIS EQU CYREG_PRT4_INP_DIS\r
-SCSI_Out_DBx__6__INTTYPE EQU CYREG_PICU4_INTTYPE5\r
-SCSI_Out_DBx__6__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
-SCSI_Out_DBx__6__LCD_EN EQU CYREG_PRT4_LCD_EN\r
-SCSI_Out_DBx__6__MASK EQU 0x20\r
-SCSI_Out_DBx__6__PC EQU CYREG_PRT4_PC5\r
-SCSI_Out_DBx__6__PORT EQU 4\r
-SCSI_Out_DBx__6__PRT EQU CYREG_PRT4_PRT\r
-SCSI_Out_DBx__6__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
-SCSI_Out_DBx__6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
-SCSI_Out_DBx__6__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
-SCSI_Out_DBx__6__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
-SCSI_Out_DBx__6__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
-SCSI_Out_DBx__6__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
-SCSI_Out_DBx__6__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
-SCSI_Out_DBx__6__PS EQU CYREG_PRT4_PS\r
-SCSI_Out_DBx__6__SHIFT EQU 5\r
-SCSI_Out_DBx__6__SLW EQU CYREG_PRT4_SLW\r
-SCSI_Out_DBx__7__AG EQU CYREG_PRT4_AG\r
-SCSI_Out_DBx__7__AMUX EQU CYREG_PRT4_AMUX\r
-SCSI_Out_DBx__7__BIE EQU CYREG_PRT4_BIE\r
-SCSI_Out_DBx__7__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
-SCSI_Out_DBx__7__BYP EQU CYREG_PRT4_BYP\r
-SCSI_Out_DBx__7__CTL EQU CYREG_PRT4_CTL\r
-SCSI_Out_DBx__7__DM0 EQU CYREG_PRT4_DM0\r
-SCSI_Out_DBx__7__DM1 EQU CYREG_PRT4_DM1\r
-SCSI_Out_DBx__7__DM2 EQU CYREG_PRT4_DM2\r
-SCSI_Out_DBx__7__DR EQU CYREG_PRT4_DR\r
-SCSI_Out_DBx__7__INP_DIS EQU CYREG_PRT4_INP_DIS\r
-SCSI_Out_DBx__7__INTTYPE EQU CYREG_PICU4_INTTYPE4\r
-SCSI_Out_DBx__7__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
-SCSI_Out_DBx__7__LCD_EN EQU CYREG_PRT4_LCD_EN\r
-SCSI_Out_DBx__7__MASK EQU 0x10\r
-SCSI_Out_DBx__7__PC EQU CYREG_PRT4_PC4\r
-SCSI_Out_DBx__7__PORT EQU 4\r
-SCSI_Out_DBx__7__PRT EQU CYREG_PRT4_PRT\r
-SCSI_Out_DBx__7__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
-SCSI_Out_DBx__7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
-SCSI_Out_DBx__7__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
-SCSI_Out_DBx__7__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
-SCSI_Out_DBx__7__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
-SCSI_Out_DBx__7__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
-SCSI_Out_DBx__7__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
-SCSI_Out_DBx__7__PS EQU CYREG_PRT4_PS\r
-SCSI_Out_DBx__7__SHIFT EQU 4\r
-SCSI_Out_DBx__7__SLW EQU CYREG_PRT4_SLW\r
-SCSI_Out_DBx__DB0__AG EQU CYREG_PRT6_AG\r
-SCSI_Out_DBx__DB0__AMUX EQU CYREG_PRT6_AMUX\r
-SCSI_Out_DBx__DB0__BIE EQU CYREG_PRT6_BIE\r
-SCSI_Out_DBx__DB0__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
-SCSI_Out_DBx__DB0__BYP EQU CYREG_PRT6_BYP\r
-SCSI_Out_DBx__DB0__CTL EQU CYREG_PRT6_CTL\r
-SCSI_Out_DBx__DB0__DM0 EQU CYREG_PRT6_DM0\r
-SCSI_Out_DBx__DB0__DM1 EQU CYREG_PRT6_DM1\r
-SCSI_Out_DBx__DB0__DM2 EQU CYREG_PRT6_DM2\r
-SCSI_Out_DBx__DB0__DR EQU CYREG_PRT6_DR\r
-SCSI_Out_DBx__DB0__INP_DIS EQU CYREG_PRT6_INP_DIS\r
-SCSI_Out_DBx__DB0__INTTYPE EQU CYREG_PICU6_INTTYPE3\r
-SCSI_Out_DBx__DB0__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
-SCSI_Out_DBx__DB0__LCD_EN EQU CYREG_PRT6_LCD_EN\r
-SCSI_Out_DBx__DB0__MASK EQU 0x08\r
-SCSI_Out_DBx__DB0__PC EQU CYREG_PRT6_PC3\r
-SCSI_Out_DBx__DB0__PORT EQU 6\r
-SCSI_Out_DBx__DB0__PRT EQU CYREG_PRT6_PRT\r
-SCSI_Out_DBx__DB0__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
-SCSI_Out_DBx__DB0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
-SCSI_Out_DBx__DB0__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
-SCSI_Out_DBx__DB0__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
-SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
-SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
-SCSI_Out_DBx__DB0__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
-SCSI_Out_DBx__DB0__PS EQU CYREG_PRT6_PS\r
-SCSI_Out_DBx__DB0__SHIFT EQU 3\r
-SCSI_Out_DBx__DB0__SLW EQU CYREG_PRT6_SLW\r
-SCSI_Out_DBx__DB1__AG EQU CYREG_PRT6_AG\r
-SCSI_Out_DBx__DB1__AMUX EQU CYREG_PRT6_AMUX\r
-SCSI_Out_DBx__DB1__BIE EQU CYREG_PRT6_BIE\r
-SCSI_Out_DBx__DB1__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
-SCSI_Out_DBx__DB1__BYP EQU CYREG_PRT6_BYP\r
-SCSI_Out_DBx__DB1__CTL EQU CYREG_PRT6_CTL\r
-SCSI_Out_DBx__DB1__DM0 EQU CYREG_PRT6_DM0\r
-SCSI_Out_DBx__DB1__DM1 EQU CYREG_PRT6_DM1\r
-SCSI_Out_DBx__DB1__DM2 EQU CYREG_PRT6_DM2\r
-SCSI_Out_DBx__DB1__DR EQU CYREG_PRT6_DR\r
-SCSI_Out_DBx__DB1__INP_DIS EQU CYREG_PRT6_INP_DIS\r
-SCSI_Out_DBx__DB1__INTTYPE EQU CYREG_PICU6_INTTYPE2\r
-SCSI_Out_DBx__DB1__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
-SCSI_Out_DBx__DB1__LCD_EN EQU CYREG_PRT6_LCD_EN\r
-SCSI_Out_DBx__DB1__MASK EQU 0x04\r
-SCSI_Out_DBx__DB1__PC EQU CYREG_PRT6_PC2\r
-SCSI_Out_DBx__DB1__PORT EQU 6\r
-SCSI_Out_DBx__DB1__PRT EQU CYREG_PRT6_PRT\r
-SCSI_Out_DBx__DB1__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
-SCSI_Out_DBx__DB1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
-SCSI_Out_DBx__DB1__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
-SCSI_Out_DBx__DB1__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
-SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
-SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
-SCSI_Out_DBx__DB1__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
-SCSI_Out_DBx__DB1__PS EQU CYREG_PRT6_PS\r
-SCSI_Out_DBx__DB1__SHIFT EQU 2\r
-SCSI_Out_DBx__DB1__SLW EQU CYREG_PRT6_SLW\r
-SCSI_Out_DBx__DB2__AG EQU CYREG_PRT6_AG\r
-SCSI_Out_DBx__DB2__AMUX EQU CYREG_PRT6_AMUX\r
-SCSI_Out_DBx__DB2__BIE EQU CYREG_PRT6_BIE\r
-SCSI_Out_DBx__DB2__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
-SCSI_Out_DBx__DB2__BYP EQU CYREG_PRT6_BYP\r
-SCSI_Out_DBx__DB2__CTL EQU CYREG_PRT6_CTL\r
-SCSI_Out_DBx__DB2__DM0 EQU CYREG_PRT6_DM0\r
-SCSI_Out_DBx__DB2__DM1 EQU CYREG_PRT6_DM1\r
-SCSI_Out_DBx__DB2__DM2 EQU CYREG_PRT6_DM2\r
-SCSI_Out_DBx__DB2__DR EQU CYREG_PRT6_DR\r
-SCSI_Out_DBx__DB2__INP_DIS EQU CYREG_PRT6_INP_DIS\r
-SCSI_Out_DBx__DB2__INTTYPE EQU CYREG_PICU6_INTTYPE1\r
-SCSI_Out_DBx__DB2__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
-SCSI_Out_DBx__DB2__LCD_EN EQU CYREG_PRT6_LCD_EN\r
-SCSI_Out_DBx__DB2__MASK EQU 0x02\r
-SCSI_Out_DBx__DB2__PC EQU CYREG_PRT6_PC1\r
-SCSI_Out_DBx__DB2__PORT EQU 6\r
-SCSI_Out_DBx__DB2__PRT EQU CYREG_PRT6_PRT\r
-SCSI_Out_DBx__DB2__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
-SCSI_Out_DBx__DB2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
-SCSI_Out_DBx__DB2__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
-SCSI_Out_DBx__DB2__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
-SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
-SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
-SCSI_Out_DBx__DB2__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
-SCSI_Out_DBx__DB2__PS EQU CYREG_PRT6_PS\r
-SCSI_Out_DBx__DB2__SHIFT EQU 1\r
-SCSI_Out_DBx__DB2__SLW EQU CYREG_PRT6_SLW\r
-SCSI_Out_DBx__DB3__AG EQU CYREG_PRT6_AG\r
-SCSI_Out_DBx__DB3__AMUX EQU CYREG_PRT6_AMUX\r
-SCSI_Out_DBx__DB3__BIE EQU CYREG_PRT6_BIE\r
-SCSI_Out_DBx__DB3__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
-SCSI_Out_DBx__DB3__BYP EQU CYREG_PRT6_BYP\r
-SCSI_Out_DBx__DB3__CTL EQU CYREG_PRT6_CTL\r
-SCSI_Out_DBx__DB3__DM0 EQU CYREG_PRT6_DM0\r
-SCSI_Out_DBx__DB3__DM1 EQU CYREG_PRT6_DM1\r
-SCSI_Out_DBx__DB3__DM2 EQU CYREG_PRT6_DM2\r
-SCSI_Out_DBx__DB3__DR EQU CYREG_PRT6_DR\r
-SCSI_Out_DBx__DB3__INP_DIS EQU CYREG_PRT6_INP_DIS\r
-SCSI_Out_DBx__DB3__INTTYPE EQU CYREG_PICU6_INTTYPE0\r
-SCSI_Out_DBx__DB3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
-SCSI_Out_DBx__DB3__LCD_EN EQU CYREG_PRT6_LCD_EN\r
-SCSI_Out_DBx__DB3__MASK EQU 0x01\r
-SCSI_Out_DBx__DB3__PC EQU CYREG_PRT6_PC0\r
-SCSI_Out_DBx__DB3__PORT EQU 6\r
-SCSI_Out_DBx__DB3__PRT EQU CYREG_PRT6_PRT\r
-SCSI_Out_DBx__DB3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
-SCSI_Out_DBx__DB3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
-SCSI_Out_DBx__DB3__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
-SCSI_Out_DBx__DB3__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
-SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
-SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
-SCSI_Out_DBx__DB3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
-SCSI_Out_DBx__DB3__PS EQU CYREG_PRT6_PS\r
-SCSI_Out_DBx__DB3__SHIFT EQU 0\r
-SCSI_Out_DBx__DB3__SLW EQU CYREG_PRT6_SLW\r
-SCSI_Out_DBx__DB4__AG EQU CYREG_PRT4_AG\r
-SCSI_Out_DBx__DB4__AMUX EQU CYREG_PRT4_AMUX\r
-SCSI_Out_DBx__DB4__BIE EQU CYREG_PRT4_BIE\r
-SCSI_Out_DBx__DB4__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
-SCSI_Out_DBx__DB4__BYP EQU CYREG_PRT4_BYP\r
-SCSI_Out_DBx__DB4__CTL EQU CYREG_PRT4_CTL\r
-SCSI_Out_DBx__DB4__DM0 EQU CYREG_PRT4_DM0\r
-SCSI_Out_DBx__DB4__DM1 EQU CYREG_PRT4_DM1\r
-SCSI_Out_DBx__DB4__DM2 EQU CYREG_PRT4_DM2\r
-SCSI_Out_DBx__DB4__DR EQU CYREG_PRT4_DR\r
-SCSI_Out_DBx__DB4__INP_DIS EQU CYREG_PRT4_INP_DIS\r
-SCSI_Out_DBx__DB4__INTTYPE EQU CYREG_PICU4_INTTYPE7\r
-SCSI_Out_DBx__DB4__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
-SCSI_Out_DBx__DB4__LCD_EN EQU CYREG_PRT4_LCD_EN\r
-SCSI_Out_DBx__DB4__MASK EQU 0x80\r
-SCSI_Out_DBx__DB4__PC EQU CYREG_PRT4_PC7\r
-SCSI_Out_DBx__DB4__PORT EQU 4\r
-SCSI_Out_DBx__DB4__PRT EQU CYREG_PRT4_PRT\r
-SCSI_Out_DBx__DB4__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
-SCSI_Out_DBx__DB4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
-SCSI_Out_DBx__DB4__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
-SCSI_Out_DBx__DB4__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
-SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
-SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
-SCSI_Out_DBx__DB4__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
-SCSI_Out_DBx__DB4__PS EQU CYREG_PRT4_PS\r
-SCSI_Out_DBx__DB4__SHIFT EQU 7\r
-SCSI_Out_DBx__DB4__SLW EQU CYREG_PRT4_SLW\r
-SCSI_Out_DBx__DB5__AG EQU CYREG_PRT4_AG\r
-SCSI_Out_DBx__DB5__AMUX EQU CYREG_PRT4_AMUX\r
-SCSI_Out_DBx__DB5__BIE EQU CYREG_PRT4_BIE\r
-SCSI_Out_DBx__DB5__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
-SCSI_Out_DBx__DB5__BYP EQU CYREG_PRT4_BYP\r
-SCSI_Out_DBx__DB5__CTL EQU CYREG_PRT4_CTL\r
-SCSI_Out_DBx__DB5__DM0 EQU CYREG_PRT4_DM0\r
-SCSI_Out_DBx__DB5__DM1 EQU CYREG_PRT4_DM1\r
-SCSI_Out_DBx__DB5__DM2 EQU CYREG_PRT4_DM2\r
-SCSI_Out_DBx__DB5__DR EQU CYREG_PRT4_DR\r
-SCSI_Out_DBx__DB5__INP_DIS EQU CYREG_PRT4_INP_DIS\r
-SCSI_Out_DBx__DB5__INTTYPE EQU CYREG_PICU4_INTTYPE6\r
-SCSI_Out_DBx__DB5__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
-SCSI_Out_DBx__DB5__LCD_EN EQU CYREG_PRT4_LCD_EN\r
-SCSI_Out_DBx__DB5__MASK EQU 0x40\r
-SCSI_Out_DBx__DB5__PC EQU CYREG_PRT4_PC6\r
-SCSI_Out_DBx__DB5__PORT EQU 4\r
-SCSI_Out_DBx__DB5__PRT EQU CYREG_PRT4_PRT\r
-SCSI_Out_DBx__DB5__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
-SCSI_Out_DBx__DB5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
-SCSI_Out_DBx__DB5__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
-SCSI_Out_DBx__DB5__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
-SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
-SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
-SCSI_Out_DBx__DB5__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
-SCSI_Out_DBx__DB5__PS EQU CYREG_PRT4_PS\r
-SCSI_Out_DBx__DB5__SHIFT EQU 6\r
-SCSI_Out_DBx__DB5__SLW EQU CYREG_PRT4_SLW\r
-SCSI_Out_DBx__DB6__AG EQU CYREG_PRT4_AG\r
-SCSI_Out_DBx__DB6__AMUX EQU CYREG_PRT4_AMUX\r
-SCSI_Out_DBx__DB6__BIE EQU CYREG_PRT4_BIE\r
-SCSI_Out_DBx__DB6__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
-SCSI_Out_DBx__DB6__BYP EQU CYREG_PRT4_BYP\r
-SCSI_Out_DBx__DB6__CTL EQU CYREG_PRT4_CTL\r
-SCSI_Out_DBx__DB6__DM0 EQU CYREG_PRT4_DM0\r
-SCSI_Out_DBx__DB6__DM1 EQU CYREG_PRT4_DM1\r
-SCSI_Out_DBx__DB6__DM2 EQU CYREG_PRT4_DM2\r
-SCSI_Out_DBx__DB6__DR EQU CYREG_PRT4_DR\r
-SCSI_Out_DBx__DB6__INP_DIS EQU CYREG_PRT4_INP_DIS\r
-SCSI_Out_DBx__DB6__INTTYPE EQU CYREG_PICU4_INTTYPE5\r
-SCSI_Out_DBx__DB6__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
-SCSI_Out_DBx__DB6__LCD_EN EQU CYREG_PRT4_LCD_EN\r
-SCSI_Out_DBx__DB6__MASK EQU 0x20\r
-SCSI_Out_DBx__DB6__PC EQU CYREG_PRT4_PC5\r
-SCSI_Out_DBx__DB6__PORT EQU 4\r
-SCSI_Out_DBx__DB6__PRT EQU CYREG_PRT4_PRT\r
-SCSI_Out_DBx__DB6__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
-SCSI_Out_DBx__DB6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
-SCSI_Out_DBx__DB6__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
-SCSI_Out_DBx__DB6__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
-SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
-SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
-SCSI_Out_DBx__DB6__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
-SCSI_Out_DBx__DB6__PS EQU CYREG_PRT4_PS\r
-SCSI_Out_DBx__DB6__SHIFT EQU 5\r
-SCSI_Out_DBx__DB6__SLW EQU CYREG_PRT4_SLW\r
-SCSI_Out_DBx__DB7__AG EQU CYREG_PRT4_AG\r
-SCSI_Out_DBx__DB7__AMUX EQU CYREG_PRT4_AMUX\r
-SCSI_Out_DBx__DB7__BIE EQU CYREG_PRT4_BIE\r
-SCSI_Out_DBx__DB7__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
-SCSI_Out_DBx__DB7__BYP EQU CYREG_PRT4_BYP\r
-SCSI_Out_DBx__DB7__CTL EQU CYREG_PRT4_CTL\r
-SCSI_Out_DBx__DB7__DM0 EQU CYREG_PRT4_DM0\r
-SCSI_Out_DBx__DB7__DM1 EQU CYREG_PRT4_DM1\r
-SCSI_Out_DBx__DB7__DM2 EQU CYREG_PRT4_DM2\r
-SCSI_Out_DBx__DB7__DR EQU CYREG_PRT4_DR\r
-SCSI_Out_DBx__DB7__INP_DIS EQU CYREG_PRT4_INP_DIS\r
-SCSI_Out_DBx__DB7__INTTYPE EQU CYREG_PICU4_INTTYPE4\r
-SCSI_Out_DBx__DB7__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
-SCSI_Out_DBx__DB7__LCD_EN EQU CYREG_PRT4_LCD_EN\r
-SCSI_Out_DBx__DB7__MASK EQU 0x10\r
-SCSI_Out_DBx__DB7__PC EQU CYREG_PRT4_PC4\r
-SCSI_Out_DBx__DB7__PORT EQU 4\r
-SCSI_Out_DBx__DB7__PRT EQU CYREG_PRT4_PRT\r
-SCSI_Out_DBx__DB7__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
-SCSI_Out_DBx__DB7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
-SCSI_Out_DBx__DB7__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
-SCSI_Out_DBx__DB7__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
-SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
-SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
-SCSI_Out_DBx__DB7__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
-SCSI_Out_DBx__DB7__PS EQU CYREG_PRT4_PS\r
-SCSI_Out_DBx__DB7__SHIFT EQU 4\r
-SCSI_Out_DBx__DB7__SLW EQU CYREG_PRT4_SLW\r
-\r
-/* SCSI_Parity_Error */\r
-SCSI_Parity_Error_sts_sts_reg__0__MASK EQU 0x01\r
-SCSI_Parity_Error_sts_sts_reg__0__POS EQU 0\r
-SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB01_02_ACTL\r
-SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB01_02_ST\r
-SCSI_Parity_Error_sts_sts_reg__MASK EQU 0x01\r
-SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB01_MSK\r
-SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB01_ACTL\r
-SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB01_ST\r
-\r
-/* SCSI_RST_ISR */\r
-SCSI_RST_ISR__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
-SCSI_RST_ISR__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
-SCSI_RST_ISR__INTC_MASK EQU 0x02\r
-SCSI_RST_ISR__INTC_NUMBER EQU 1\r
-SCSI_RST_ISR__INTC_PRIOR_NUM EQU 7\r
-SCSI_RST_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_1\r
-SCSI_RST_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
-SCSI_RST_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
-\r
-/* SCSI_RX_DMA */\r
-SCSI_RX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0\r
-SCSI_RX_DMA__DRQ_NUMBER EQU 0\r
-SCSI_RX_DMA__NUMBEROF_TDS EQU 0\r
-SCSI_RX_DMA__PRIORITY EQU 2\r
-SCSI_RX_DMA__TERMIN_EN EQU 0\r
-SCSI_RX_DMA__TERMIN_SEL EQU 0\r
-SCSI_RX_DMA__TERMOUT0_EN EQU 1\r
-SCSI_RX_DMA__TERMOUT0_SEL EQU 0\r
-SCSI_RX_DMA__TERMOUT1_EN EQU 0\r
-SCSI_RX_DMA__TERMOUT1_SEL EQU 0\r
-SCSI_RX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
-SCSI_RX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
-SCSI_RX_DMA_COMPLETE__INTC_MASK EQU 0x04\r
-SCSI_RX_DMA_COMPLETE__INTC_NUMBER EQU 2\r
-SCSI_RX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7\r
-SCSI_RX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_2\r
-SCSI_RX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
-SCSI_RX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
-\r
-/* SCSI_SEL_ISR */\r
-SCSI_SEL_ISR__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
-SCSI_SEL_ISR__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
-SCSI_SEL_ISR__INTC_MASK EQU 0x08\r
-SCSI_SEL_ISR__INTC_NUMBER EQU 3\r
-SCSI_SEL_ISR__INTC_PRIOR_NUM EQU 7\r
-SCSI_SEL_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_3\r
-SCSI_SEL_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
-SCSI_SEL_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
-\r
-/* SCSI_TX_DMA */\r
-SCSI_TX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0\r
-SCSI_TX_DMA__DRQ_NUMBER EQU 1\r
-SCSI_TX_DMA__NUMBEROF_TDS EQU 0\r
-SCSI_TX_DMA__PRIORITY EQU 2\r
-SCSI_TX_DMA__TERMIN_EN EQU 0\r
-SCSI_TX_DMA__TERMIN_SEL EQU 0\r
-SCSI_TX_DMA__TERMOUT0_EN EQU 1\r
-SCSI_TX_DMA__TERMOUT0_SEL EQU 1\r
-SCSI_TX_DMA__TERMOUT1_EN EQU 0\r
-SCSI_TX_DMA__TERMOUT1_SEL EQU 0\r
-SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
-SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
-SCSI_TX_DMA_COMPLETE__INTC_MASK EQU 0x10\r
-SCSI_TX_DMA_COMPLETE__INTC_NUMBER EQU 4\r
-SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7\r
-SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_4\r
-SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
-SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
-\r
-/* SDCard_BSPIM */\r
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL\r
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB04_05_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB04_05_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB04_05_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB04_05_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB04_05_MSK\r
-SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB04_05_MSK\r
-SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB04_05_MSK\r
-SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB04_05_MSK\r
-SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL\r
-SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB04_CTL\r
-SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB04_ST_CTL\r
-SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB04_CTL\r
-SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB04_ST_CTL\r
-SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL\r
-SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL\r
-SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB04_MSK\r
-SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL\r
-SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB04_05_ST\r
-SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB04_MSK\r
-SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL\r
-SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB04_ST_CTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB04_ST_CTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB04_ST\r
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB08_09_ACTL\r
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB08_09_ST\r
-SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10\r
-SDCard_BSPIM_RxStsReg__4__POS EQU 4\r
-SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20\r
-SDCard_BSPIM_RxStsReg__5__POS EQU 5\r
-SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40\r
-SDCard_BSPIM_RxStsReg__6__POS EQU 6\r
-SDCard_BSPIM_RxStsReg__MASK EQU 0x70\r
-SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB08_MSK\r
-SDCard_BSPIM_RxStsReg__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB08_MSK_ACTL\r
-SDCard_BSPIM_RxStsReg__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB08_MSK_ACTL\r
-SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB08_ACTL\r
-SDCard_BSPIM_RxStsReg__STATUS_CNT_REG EQU CYREG_B1_UDB08_ST_CTL\r
-SDCard_BSPIM_RxStsReg__STATUS_CONTROL_REG EQU CYREG_B1_UDB08_ST_CTL\r
-SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB08_ST\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB04_05_A0\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB04_05_A1\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B1_UDB04_05_D0\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B1_UDB04_05_D1\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B1_UDB04_05_F0\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B1_UDB04_05_F1\r
-SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B1_UDB04_A0_A1\r
-SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B1_UDB04_A0\r
-SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B1_UDB04_A1\r
-SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B1_UDB04_D0_D1\r
-SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B1_UDB04_D0\r
-SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B1_UDB04_D1\r
-SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL\r
-SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B1_UDB04_F0_F1\r
-SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B1_UDB04_F0\r
-SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B1_UDB04_F1\r
-SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL\r
-SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL\r
-SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01\r
-SDCard_BSPIM_TxStsReg__0__POS EQU 0\r
-SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02\r
-SDCard_BSPIM_TxStsReg__1__POS EQU 1\r
-SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL\r
-SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST\r
-SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04\r
-SDCard_BSPIM_TxStsReg__2__POS EQU 2\r
-SDCard_BSPIM_TxStsReg__3__MASK EQU 0x08\r
-SDCard_BSPIM_TxStsReg__3__POS EQU 3\r
-SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10\r
-SDCard_BSPIM_TxStsReg__4__POS EQU 4\r
-SDCard_BSPIM_TxStsReg__MASK EQU 0x1F\r
-SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB07_MSK\r
-SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL\r
-SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB07_ST\r
-\r
-/* SD_CD */\r
-SD_CD__0__INTTYPE EQU CYREG_PICU3_INTTYPE6\r
-SD_CD__0__MASK EQU 0x40\r
-SD_CD__0__PC EQU CYREG_PRT3_PC6\r
-SD_CD__0__PORT EQU 3\r
-SD_CD__0__SHIFT EQU 6\r
-SD_CD__AG EQU CYREG_PRT3_AG\r
-SD_CD__AMUX EQU CYREG_PRT3_AMUX\r
-SD_CD__BIE EQU CYREG_PRT3_BIE\r
-SD_CD__BIT_MASK EQU CYREG_PRT3_BIT_MASK\r
-SD_CD__BYP EQU CYREG_PRT3_BYP\r
-SD_CD__CTL EQU CYREG_PRT3_CTL\r
-SD_CD__DM0 EQU CYREG_PRT3_DM0\r
-SD_CD__DM1 EQU CYREG_PRT3_DM1\r
-SD_CD__DM2 EQU CYREG_PRT3_DM2\r
-SD_CD__DR EQU CYREG_PRT3_DR\r
-SD_CD__INP_DIS EQU CYREG_PRT3_INP_DIS\r
-SD_CD__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE\r
-SD_CD__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG\r
-SD_CD__LCD_EN EQU CYREG_PRT3_LCD_EN\r
-SD_CD__MASK EQU 0x40\r
-SD_CD__PORT EQU 3\r
-SD_CD__PRT EQU CYREG_PRT3_PRT\r
-SD_CD__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL\r
-SD_CD__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN\r
-SD_CD__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0\r
-SD_CD__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1\r
-SD_CD__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0\r
-SD_CD__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1\r
-SD_CD__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT\r
-SD_CD__PS EQU CYREG_PRT3_PS\r
-SD_CD__SHIFT EQU 6\r
-SD_CD__SLW EQU CYREG_PRT3_SLW\r
-\r
-/* SD_CS */\r
-SD_CS__0__INTTYPE EQU CYREG_PICU3_INTTYPE4\r
-SD_CS__0__MASK EQU 0x10\r
-SD_CS__0__PC EQU CYREG_PRT3_PC4\r
-SD_CS__0__PORT EQU 3\r
-SD_CS__0__SHIFT EQU 4\r
-SD_CS__AG EQU CYREG_PRT3_AG\r
-SD_CS__AMUX EQU CYREG_PRT3_AMUX\r
-SD_CS__BIE EQU CYREG_PRT3_BIE\r
-SD_CS__BIT_MASK EQU CYREG_PRT3_BIT_MASK\r
-SD_CS__BYP EQU CYREG_PRT3_BYP\r
-SD_CS__CTL EQU CYREG_PRT3_CTL\r
-SD_CS__DM0 EQU CYREG_PRT3_DM0\r
-SD_CS__DM1 EQU CYREG_PRT3_DM1\r
-SD_CS__DM2 EQU CYREG_PRT3_DM2\r
-SD_CS__DR EQU CYREG_PRT3_DR\r
-SD_CS__INP_DIS EQU CYREG_PRT3_INP_DIS\r
-SD_CS__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE\r
-SD_CS__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG\r
-SD_CS__LCD_EN EQU CYREG_PRT3_LCD_EN\r
-SD_CS__MASK EQU 0x10\r
-SD_CS__PORT EQU 3\r
-SD_CS__PRT EQU CYREG_PRT3_PRT\r
-SD_CS__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL\r
-SD_CS__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN\r
-SD_CS__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0\r
-SD_CS__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1\r
-SD_CS__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0\r
-SD_CS__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1\r
-SD_CS__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT\r
-SD_CS__PS EQU CYREG_PRT3_PS\r
-SD_CS__SHIFT EQU 4\r
-SD_CS__SLW EQU CYREG_PRT3_SLW\r
-\r
-/* SD_DAT1 */\r
-SD_DAT1__0__INTTYPE EQU CYREG_PICU3_INTTYPE0\r
-SD_DAT1__0__MASK EQU 0x01\r
-SD_DAT1__0__PC EQU CYREG_PRT3_PC0\r
-SD_DAT1__0__PORT EQU 3\r
-SD_DAT1__0__SHIFT EQU 0\r
-SD_DAT1__AG EQU CYREG_PRT3_AG\r
-SD_DAT1__AMUX EQU CYREG_PRT3_AMUX\r
-SD_DAT1__BIE EQU CYREG_PRT3_BIE\r
-SD_DAT1__BIT_MASK EQU CYREG_PRT3_BIT_MASK\r
-SD_DAT1__BYP EQU CYREG_PRT3_BYP\r
-SD_DAT1__CTL EQU CYREG_PRT3_CTL\r
-SD_DAT1__DM0 EQU CYREG_PRT3_DM0\r
-SD_DAT1__DM1 EQU CYREG_PRT3_DM1\r
-SD_DAT1__DM2 EQU CYREG_PRT3_DM2\r
-SD_DAT1__DR EQU CYREG_PRT3_DR\r
-SD_DAT1__INP_DIS EQU CYREG_PRT3_INP_DIS\r
-SD_DAT1__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE\r
-SD_DAT1__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG\r
-SD_DAT1__LCD_EN EQU CYREG_PRT3_LCD_EN\r
-SD_DAT1__MASK EQU 0x01\r
-SD_DAT1__PORT EQU 3\r
-SD_DAT1__PRT EQU CYREG_PRT3_PRT\r
-SD_DAT1__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL\r
-SD_DAT1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN\r
-SD_DAT1__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0\r
-SD_DAT1__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1\r
-SD_DAT1__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0\r
-SD_DAT1__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1\r
-SD_DAT1__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT\r
-SD_DAT1__PS EQU CYREG_PRT3_PS\r
-SD_DAT1__SHIFT EQU 0\r
-SD_DAT1__SLW EQU CYREG_PRT3_SLW\r
-\r
-/* SD_DAT2 */\r
-SD_DAT2__0__INTTYPE EQU CYREG_PICU3_INTTYPE5\r
-SD_DAT2__0__MASK EQU 0x20\r
-SD_DAT2__0__PC EQU CYREG_PRT3_PC5\r
-SD_DAT2__0__PORT EQU 3\r
-SD_DAT2__0__SHIFT EQU 5\r
-SD_DAT2__AG EQU CYREG_PRT3_AG\r
-SD_DAT2__AMUX EQU CYREG_PRT3_AMUX\r
-SD_DAT2__BIE EQU CYREG_PRT3_BIE\r
-SD_DAT2__BIT_MASK EQU CYREG_PRT3_BIT_MASK\r
-SD_DAT2__BYP EQU CYREG_PRT3_BYP\r
-SD_DAT2__CTL EQU CYREG_PRT3_CTL\r
-SD_DAT2__DM0 EQU CYREG_PRT3_DM0\r
-SD_DAT2__DM1 EQU CYREG_PRT3_DM1\r
-SD_DAT2__DM2 EQU CYREG_PRT3_DM2\r
-SD_DAT2__DR EQU CYREG_PRT3_DR\r
-SD_DAT2__INP_DIS EQU CYREG_PRT3_INP_DIS\r
-SD_DAT2__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE\r
-SD_DAT2__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG\r
-SD_DAT2__LCD_EN EQU CYREG_PRT3_LCD_EN\r
-SD_DAT2__MASK EQU 0x20\r
-SD_DAT2__PORT EQU 3\r
-SD_DAT2__PRT EQU CYREG_PRT3_PRT\r
-SD_DAT2__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL\r
-SD_DAT2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN\r
-SD_DAT2__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0\r
-SD_DAT2__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1\r
-SD_DAT2__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0\r
-SD_DAT2__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1\r
-SD_DAT2__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT\r
-SD_DAT2__PS EQU CYREG_PRT3_PS\r
-SD_DAT2__SHIFT EQU 5\r
-SD_DAT2__SLW EQU CYREG_PRT3_SLW\r
-\r
-/* SD_Data_Clk */\r
-SD_Data_Clk__CFG0 EQU CYREG_CLKDIST_DCFG0_CFG0\r
-SD_Data_Clk__CFG1 EQU CYREG_CLKDIST_DCFG0_CFG1\r
-SD_Data_Clk__CFG2 EQU CYREG_CLKDIST_DCFG0_CFG2\r
-SD_Data_Clk__CFG2_SRC_SEL_MASK EQU 0x07\r
-SD_Data_Clk__INDEX EQU 0x00\r
-SD_Data_Clk__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2\r
-SD_Data_Clk__PM_ACT_MSK EQU 0x01\r
-SD_Data_Clk__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2\r
-SD_Data_Clk__PM_STBY_MSK EQU 0x01\r
-\r
-/* SD_MISO */\r
-SD_MISO__0__INTTYPE EQU CYREG_PICU3_INTTYPE1\r
-SD_MISO__0__MASK EQU 0x02\r
-SD_MISO__0__PC EQU CYREG_PRT3_PC1\r
-SD_MISO__0__PORT EQU 3\r
-SD_MISO__0__SHIFT EQU 1\r
-SD_MISO__AG EQU CYREG_PRT3_AG\r
-SD_MISO__AMUX EQU CYREG_PRT3_AMUX\r
-SD_MISO__BIE EQU CYREG_PRT3_BIE\r
-SD_MISO__BIT_MASK EQU CYREG_PRT3_BIT_MASK\r
-SD_MISO__BYP EQU CYREG_PRT3_BYP\r
-SD_MISO__CTL EQU CYREG_PRT3_CTL\r
-SD_MISO__DM0 EQU CYREG_PRT3_DM0\r
-SD_MISO__DM1 EQU CYREG_PRT3_DM1\r
-SD_MISO__DM2 EQU CYREG_PRT3_DM2\r
-SD_MISO__DR EQU CYREG_PRT3_DR\r
-SD_MISO__INP_DIS EQU CYREG_PRT3_INP_DIS\r
-SD_MISO__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE\r
-SD_MISO__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG\r
-SD_MISO__LCD_EN EQU CYREG_PRT3_LCD_EN\r
-SD_MISO__MASK EQU 0x02\r
-SD_MISO__PORT EQU 3\r
-SD_MISO__PRT EQU CYREG_PRT3_PRT\r
-SD_MISO__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL\r
-SD_MISO__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN\r
-SD_MISO__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0\r
-SD_MISO__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1\r
-SD_MISO__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0\r
-SD_MISO__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1\r
-SD_MISO__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT\r
-SD_MISO__PS EQU CYREG_PRT3_PS\r
-SD_MISO__SHIFT EQU 1\r
-SD_MISO__SLW EQU CYREG_PRT3_SLW\r
-\r
-/* SD_MOSI */\r
-SD_MOSI__0__INTTYPE EQU CYREG_PICU3_INTTYPE3\r
-SD_MOSI__0__MASK EQU 0x08\r
-SD_MOSI__0__PC EQU CYREG_PRT3_PC3\r
-SD_MOSI__0__PORT EQU 3\r
-SD_MOSI__0__SHIFT EQU 3\r
-SD_MOSI__AG EQU CYREG_PRT3_AG\r
-SD_MOSI__AMUX EQU CYREG_PRT3_AMUX\r
-SD_MOSI__BIE EQU CYREG_PRT3_BIE\r
-SD_MOSI__BIT_MASK EQU CYREG_PRT3_BIT_MASK\r
-SD_MOSI__BYP EQU CYREG_PRT3_BYP\r
-SD_MOSI__CTL EQU CYREG_PRT3_CTL\r
-SD_MOSI__DM0 EQU CYREG_PRT3_DM0\r
-SD_MOSI__DM1 EQU CYREG_PRT3_DM1\r
-SD_MOSI__DM2 EQU CYREG_PRT3_DM2\r
-SD_MOSI__DR EQU CYREG_PRT3_DR\r
-SD_MOSI__INP_DIS EQU CYREG_PRT3_INP_DIS\r
-SD_MOSI__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE\r
-SD_MOSI__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG\r
-SD_MOSI__LCD_EN EQU CYREG_PRT3_LCD_EN\r
-SD_MOSI__MASK EQU 0x08\r
-SD_MOSI__PORT EQU 3\r
-SD_MOSI__PRT EQU CYREG_PRT3_PRT\r
-SD_MOSI__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL\r
-SD_MOSI__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN\r
-SD_MOSI__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0\r
-SD_MOSI__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1\r
-SD_MOSI__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0\r
-SD_MOSI__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1\r
-SD_MOSI__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT\r
-SD_MOSI__PS EQU CYREG_PRT3_PS\r
-SD_MOSI__SHIFT EQU 3\r
-SD_MOSI__SLW EQU CYREG_PRT3_SLW\r
-\r
-/* SD_RX_DMA */\r
-SD_RX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0\r
-SD_RX_DMA__DRQ_NUMBER EQU 2\r
-SD_RX_DMA__NUMBEROF_TDS EQU 0\r
-SD_RX_DMA__PRIORITY EQU 0\r
-SD_RX_DMA__TERMIN_EN EQU 0\r
-SD_RX_DMA__TERMIN_SEL EQU 0\r
-SD_RX_DMA__TERMOUT0_EN EQU 1\r
-SD_RX_DMA__TERMOUT0_SEL EQU 2\r
-SD_RX_DMA__TERMOUT1_EN EQU 0\r
-SD_RX_DMA__TERMOUT1_SEL EQU 0\r
-SD_RX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
-SD_RX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
-SD_RX_DMA_COMPLETE__INTC_MASK EQU 0x20\r
-SD_RX_DMA_COMPLETE__INTC_NUMBER EQU 5\r
-SD_RX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7\r
-SD_RX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_5\r
-SD_RX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
-SD_RX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
-\r
-/* SD_SCK */\r
-SD_SCK__0__INTTYPE EQU CYREG_PICU3_INTTYPE2\r
-SD_SCK__0__MASK EQU 0x04\r
-SD_SCK__0__PC EQU CYREG_PRT3_PC2\r
-SD_SCK__0__PORT EQU 3\r
-SD_SCK__0__SHIFT EQU 2\r
-SD_SCK__AG EQU CYREG_PRT3_AG\r
-SD_SCK__AMUX EQU CYREG_PRT3_AMUX\r
-SD_SCK__BIE EQU CYREG_PRT3_BIE\r
-SD_SCK__BIT_MASK EQU CYREG_PRT3_BIT_MASK\r
-SD_SCK__BYP EQU CYREG_PRT3_BYP\r
-SD_SCK__CTL EQU CYREG_PRT3_CTL\r
-SD_SCK__DM0 EQU CYREG_PRT3_DM0\r
-SD_SCK__DM1 EQU CYREG_PRT3_DM1\r
-SD_SCK__DM2 EQU CYREG_PRT3_DM2\r
-SD_SCK__DR EQU CYREG_PRT3_DR\r
-SD_SCK__INP_DIS EQU CYREG_PRT3_INP_DIS\r
-SD_SCK__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE\r
-SD_SCK__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG\r
-SD_SCK__LCD_EN EQU CYREG_PRT3_LCD_EN\r
-SD_SCK__MASK EQU 0x04\r
-SD_SCK__PORT EQU 3\r
-SD_SCK__PRT EQU CYREG_PRT3_PRT\r
-SD_SCK__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL\r
-SD_SCK__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN\r
-SD_SCK__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0\r
-SD_SCK__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1\r
-SD_SCK__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0\r
-SD_SCK__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1\r
-SD_SCK__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT\r
-SD_SCK__PS EQU CYREG_PRT3_PS\r
-SD_SCK__SHIFT EQU 2\r
-SD_SCK__SLW EQU CYREG_PRT3_SLW\r
-\r
-/* SD_TX_DMA */\r
-SD_TX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0\r
-SD_TX_DMA__DRQ_NUMBER EQU 3\r
-SD_TX_DMA__NUMBEROF_TDS EQU 0\r
-SD_TX_DMA__PRIORITY EQU 1\r
-SD_TX_DMA__TERMIN_EN EQU 0\r
-SD_TX_DMA__TERMIN_SEL EQU 0\r
-SD_TX_DMA__TERMOUT0_EN EQU 1\r
-SD_TX_DMA__TERMOUT0_SEL EQU 3\r
-SD_TX_DMA__TERMOUT1_EN EQU 0\r
-SD_TX_DMA__TERMOUT1_SEL EQU 0\r
-SD_TX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
-SD_TX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
-SD_TX_DMA_COMPLETE__INTC_MASK EQU 0x40\r
-SD_TX_DMA_COMPLETE__INTC_NUMBER EQU 6\r
-SD_TX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7\r
-SD_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_6\r
-SD_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
-SD_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
+/* SD_CS */\r
+SD_CS__0__INTTYPE EQU CYREG_PICU3_INTTYPE4\r
+SD_CS__0__MASK EQU 0x10\r
+SD_CS__0__PC EQU CYREG_PRT3_PC4\r
+SD_CS__0__PORT EQU 3\r
+SD_CS__0__SHIFT EQU 4\r
+SD_CS__AG EQU CYREG_PRT3_AG\r
+SD_CS__AMUX EQU CYREG_PRT3_AMUX\r
+SD_CS__BIE EQU CYREG_PRT3_BIE\r
+SD_CS__BIT_MASK EQU CYREG_PRT3_BIT_MASK\r
+SD_CS__BYP EQU CYREG_PRT3_BYP\r
+SD_CS__CTL EQU CYREG_PRT3_CTL\r
+SD_CS__DM0 EQU CYREG_PRT3_DM0\r
+SD_CS__DM1 EQU CYREG_PRT3_DM1\r
+SD_CS__DM2 EQU CYREG_PRT3_DM2\r
+SD_CS__DR EQU CYREG_PRT3_DR\r
+SD_CS__INP_DIS EQU CYREG_PRT3_INP_DIS\r
+SD_CS__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE\r
+SD_CS__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG\r
+SD_CS__LCD_EN EQU CYREG_PRT3_LCD_EN\r
+SD_CS__MASK EQU 0x10\r
+SD_CS__PORT EQU 3\r
+SD_CS__PRT EQU CYREG_PRT3_PRT\r
+SD_CS__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL\r
+SD_CS__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN\r
+SD_CS__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0\r
+SD_CS__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1\r
+SD_CS__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0\r
+SD_CS__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1\r
+SD_CS__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT\r
+SD_CS__PS EQU CYREG_PRT3_PS\r
+SD_CS__SHIFT EQU 4\r
+SD_CS__SLW EQU CYREG_PRT3_SLW\r
\r
/* USBFS */\r
USBFS_arb_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
USBFS_USB__USBIO_CR0 EQU CYREG_USB_USBIO_CR0\r
USBFS_USB__USBIO_CR1 EQU CYREG_USB_USBIO_CR1\r
\r
+/* SDCard */\r
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL\r
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB04_05_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB04_05_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB04_05_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB04_05_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB04_05_MSK\r
+SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB04_05_MSK\r
+SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB04_05_MSK\r
+SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB04_05_MSK\r
+SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL\r
+SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB04_CTL\r
+SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB04_ST_CTL\r
+SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB04_CTL\r
+SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB04_ST_CTL\r
+SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL\r
+SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL\r
+SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB04_MSK\r
+SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL\r
+SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB04_05_ST\r
+SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB04_MSK\r
+SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL\r
+SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB04_ST_CTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB04_ST_CTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB04_ST\r
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB08_09_ACTL\r
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB08_09_ST\r
+SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10\r
+SDCard_BSPIM_RxStsReg__4__POS EQU 4\r
+SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20\r
+SDCard_BSPIM_RxStsReg__5__POS EQU 5\r
+SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40\r
+SDCard_BSPIM_RxStsReg__6__POS EQU 6\r
+SDCard_BSPIM_RxStsReg__MASK EQU 0x70\r
+SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB08_MSK\r
+SDCard_BSPIM_RxStsReg__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB08_MSK_ACTL\r
+SDCard_BSPIM_RxStsReg__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB08_MSK_ACTL\r
+SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB08_ACTL\r
+SDCard_BSPIM_RxStsReg__STATUS_CNT_REG EQU CYREG_B1_UDB08_ST_CTL\r
+SDCard_BSPIM_RxStsReg__STATUS_CONTROL_REG EQU CYREG_B1_UDB08_ST_CTL\r
+SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB08_ST\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB04_05_A0\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB04_05_A1\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B1_UDB04_05_D0\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B1_UDB04_05_D1\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B1_UDB04_05_F0\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B1_UDB04_05_F1\r
+SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B1_UDB04_A0_A1\r
+SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B1_UDB04_A0\r
+SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B1_UDB04_A1\r
+SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B1_UDB04_D0_D1\r
+SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B1_UDB04_D0\r
+SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B1_UDB04_D1\r
+SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL\r
+SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B1_UDB04_F0_F1\r
+SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B1_UDB04_F0\r
+SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B1_UDB04_F1\r
+SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL\r
+SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL\r
+SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01\r
+SDCard_BSPIM_TxStsReg__0__POS EQU 0\r
+SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02\r
+SDCard_BSPIM_TxStsReg__1__POS EQU 1\r
+SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL\r
+SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST\r
+SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04\r
+SDCard_BSPIM_TxStsReg__2__POS EQU 2\r
+SDCard_BSPIM_TxStsReg__3__MASK EQU 0x08\r
+SDCard_BSPIM_TxStsReg__3__POS EQU 3\r
+SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10\r
+SDCard_BSPIM_TxStsReg__4__POS EQU 4\r
+SDCard_BSPIM_TxStsReg__MASK EQU 0x1F\r
+SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB07_MSK\r
+SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL\r
+SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB07_ST\r
+\r
+/* SD_SCK */\r
+SD_SCK__0__INTTYPE EQU CYREG_PICU3_INTTYPE2\r
+SD_SCK__0__MASK EQU 0x04\r
+SD_SCK__0__PC EQU CYREG_PRT3_PC2\r
+SD_SCK__0__PORT EQU 3\r
+SD_SCK__0__SHIFT EQU 2\r
+SD_SCK__AG EQU CYREG_PRT3_AG\r
+SD_SCK__AMUX EQU CYREG_PRT3_AMUX\r
+SD_SCK__BIE EQU CYREG_PRT3_BIE\r
+SD_SCK__BIT_MASK EQU CYREG_PRT3_BIT_MASK\r
+SD_SCK__BYP EQU CYREG_PRT3_BYP\r
+SD_SCK__CTL EQU CYREG_PRT3_CTL\r
+SD_SCK__DM0 EQU CYREG_PRT3_DM0\r
+SD_SCK__DM1 EQU CYREG_PRT3_DM1\r
+SD_SCK__DM2 EQU CYREG_PRT3_DM2\r
+SD_SCK__DR EQU CYREG_PRT3_DR\r
+SD_SCK__INP_DIS EQU CYREG_PRT3_INP_DIS\r
+SD_SCK__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE\r
+SD_SCK__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG\r
+SD_SCK__LCD_EN EQU CYREG_PRT3_LCD_EN\r
+SD_SCK__MASK EQU 0x04\r
+SD_SCK__PORT EQU 3\r
+SD_SCK__PRT EQU CYREG_PRT3_PRT\r
+SD_SCK__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL\r
+SD_SCK__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN\r
+SD_SCK__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0\r
+SD_SCK__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1\r
+SD_SCK__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0\r
+SD_SCK__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1\r
+SD_SCK__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT\r
+SD_SCK__PS EQU CYREG_PRT3_PS\r
+SD_SCK__SHIFT EQU 2\r
+SD_SCK__SLW EQU CYREG_PRT3_SLW\r
+\r
+/* SCSI_In */\r
+SCSI_In__0__AG EQU CYREG_PRT2_AG\r
+SCSI_In__0__AMUX EQU CYREG_PRT2_AMUX\r
+SCSI_In__0__BIE EQU CYREG_PRT2_BIE\r
+SCSI_In__0__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
+SCSI_In__0__BYP EQU CYREG_PRT2_BYP\r
+SCSI_In__0__CTL EQU CYREG_PRT2_CTL\r
+SCSI_In__0__DM0 EQU CYREG_PRT2_DM0\r
+SCSI_In__0__DM1 EQU CYREG_PRT2_DM1\r
+SCSI_In__0__DM2 EQU CYREG_PRT2_DM2\r
+SCSI_In__0__DR EQU CYREG_PRT2_DR\r
+SCSI_In__0__INP_DIS EQU CYREG_PRT2_INP_DIS\r
+SCSI_In__0__INTTYPE EQU CYREG_PICU2_INTTYPE0\r
+SCSI_In__0__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
+SCSI_In__0__LCD_EN EQU CYREG_PRT2_LCD_EN\r
+SCSI_In__0__MASK EQU 0x01\r
+SCSI_In__0__PC EQU CYREG_PRT2_PC0\r
+SCSI_In__0__PORT EQU 2\r
+SCSI_In__0__PRT EQU CYREG_PRT2_PRT\r
+SCSI_In__0__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
+SCSI_In__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
+SCSI_In__0__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
+SCSI_In__0__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
+SCSI_In__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
+SCSI_In__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
+SCSI_In__0__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
+SCSI_In__0__PS EQU CYREG_PRT2_PS\r
+SCSI_In__0__SHIFT EQU 0\r
+SCSI_In__0__SLW EQU CYREG_PRT2_SLW\r
+SCSI_In__1__AG EQU CYREG_PRT6_AG\r
+SCSI_In__1__AMUX EQU CYREG_PRT6_AMUX\r
+SCSI_In__1__BIE EQU CYREG_PRT6_BIE\r
+SCSI_In__1__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
+SCSI_In__1__BYP EQU CYREG_PRT6_BYP\r
+SCSI_In__1__CTL EQU CYREG_PRT6_CTL\r
+SCSI_In__1__DM0 EQU CYREG_PRT6_DM0\r
+SCSI_In__1__DM1 EQU CYREG_PRT6_DM1\r
+SCSI_In__1__DM2 EQU CYREG_PRT6_DM2\r
+SCSI_In__1__DR EQU CYREG_PRT6_DR\r
+SCSI_In__1__INP_DIS EQU CYREG_PRT6_INP_DIS\r
+SCSI_In__1__INTTYPE EQU CYREG_PICU6_INTTYPE7\r
+SCSI_In__1__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
+SCSI_In__1__LCD_EN EQU CYREG_PRT6_LCD_EN\r
+SCSI_In__1__MASK EQU 0x80\r
+SCSI_In__1__PC EQU CYREG_PRT6_PC7\r
+SCSI_In__1__PORT EQU 6\r
+SCSI_In__1__PRT EQU CYREG_PRT6_PRT\r
+SCSI_In__1__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
+SCSI_In__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
+SCSI_In__1__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
+SCSI_In__1__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
+SCSI_In__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
+SCSI_In__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
+SCSI_In__1__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
+SCSI_In__1__PS EQU CYREG_PRT6_PS\r
+SCSI_In__1__SHIFT EQU 7\r
+SCSI_In__1__SLW EQU CYREG_PRT6_SLW\r
+SCSI_In__2__AG EQU CYREG_PRT5_AG\r
+SCSI_In__2__AMUX EQU CYREG_PRT5_AMUX\r
+SCSI_In__2__BIE EQU CYREG_PRT5_BIE\r
+SCSI_In__2__BIT_MASK EQU CYREG_PRT5_BIT_MASK\r
+SCSI_In__2__BYP EQU CYREG_PRT5_BYP\r
+SCSI_In__2__CTL EQU CYREG_PRT5_CTL\r
+SCSI_In__2__DM0 EQU CYREG_PRT5_DM0\r
+SCSI_In__2__DM1 EQU CYREG_PRT5_DM1\r
+SCSI_In__2__DM2 EQU CYREG_PRT5_DM2\r
+SCSI_In__2__DR EQU CYREG_PRT5_DR\r
+SCSI_In__2__INP_DIS EQU CYREG_PRT5_INP_DIS\r
+SCSI_In__2__INTTYPE EQU CYREG_PICU5_INTTYPE1\r
+SCSI_In__2__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG\r
+SCSI_In__2__LCD_EN EQU CYREG_PRT5_LCD_EN\r
+SCSI_In__2__MASK EQU 0x02\r
+SCSI_In__2__PC EQU CYREG_PRT5_PC1\r
+SCSI_In__2__PORT EQU 5\r
+SCSI_In__2__PRT EQU CYREG_PRT5_PRT\r
+SCSI_In__2__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL\r
+SCSI_In__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN\r
+SCSI_In__2__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0\r
+SCSI_In__2__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1\r
+SCSI_In__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0\r
+SCSI_In__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1\r
+SCSI_In__2__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT\r
+SCSI_In__2__PS EQU CYREG_PRT5_PS\r
+SCSI_In__2__SHIFT EQU 1\r
+SCSI_In__2__SLW EQU CYREG_PRT5_SLW\r
+SCSI_In__3__AG EQU CYREG_PRT5_AG\r
+SCSI_In__3__AMUX EQU CYREG_PRT5_AMUX\r
+SCSI_In__3__BIE EQU CYREG_PRT5_BIE\r
+SCSI_In__3__BIT_MASK EQU CYREG_PRT5_BIT_MASK\r
+SCSI_In__3__BYP EQU CYREG_PRT5_BYP\r
+SCSI_In__3__CTL EQU CYREG_PRT5_CTL\r
+SCSI_In__3__DM0 EQU CYREG_PRT5_DM0\r
+SCSI_In__3__DM1 EQU CYREG_PRT5_DM1\r
+SCSI_In__3__DM2 EQU CYREG_PRT5_DM2\r
+SCSI_In__3__DR EQU CYREG_PRT5_DR\r
+SCSI_In__3__INP_DIS EQU CYREG_PRT5_INP_DIS\r
+SCSI_In__3__INTTYPE EQU CYREG_PICU5_INTTYPE2\r
+SCSI_In__3__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG\r
+SCSI_In__3__LCD_EN EQU CYREG_PRT5_LCD_EN\r
+SCSI_In__3__MASK EQU 0x04\r
+SCSI_In__3__PC EQU CYREG_PRT5_PC2\r
+SCSI_In__3__PORT EQU 5\r
+SCSI_In__3__PRT EQU CYREG_PRT5_PRT\r
+SCSI_In__3__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL\r
+SCSI_In__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN\r
+SCSI_In__3__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0\r
+SCSI_In__3__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1\r
+SCSI_In__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0\r
+SCSI_In__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1\r
+SCSI_In__3__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT\r
+SCSI_In__3__PS EQU CYREG_PRT5_PS\r
+SCSI_In__3__SHIFT EQU 2\r
+SCSI_In__3__SLW EQU CYREG_PRT5_SLW\r
+SCSI_In__4__AG EQU CYREG_PRT5_AG\r
+SCSI_In__4__AMUX EQU CYREG_PRT5_AMUX\r
+SCSI_In__4__BIE EQU CYREG_PRT5_BIE\r
+SCSI_In__4__BIT_MASK EQU CYREG_PRT5_BIT_MASK\r
+SCSI_In__4__BYP EQU CYREG_PRT5_BYP\r
+SCSI_In__4__CTL EQU CYREG_PRT5_CTL\r
+SCSI_In__4__DM0 EQU CYREG_PRT5_DM0\r
+SCSI_In__4__DM1 EQU CYREG_PRT5_DM1\r
+SCSI_In__4__DM2 EQU CYREG_PRT5_DM2\r
+SCSI_In__4__DR EQU CYREG_PRT5_DR\r
+SCSI_In__4__INP_DIS EQU CYREG_PRT5_INP_DIS\r
+SCSI_In__4__INTTYPE EQU CYREG_PICU5_INTTYPE3\r
+SCSI_In__4__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG\r
+SCSI_In__4__LCD_EN EQU CYREG_PRT5_LCD_EN\r
+SCSI_In__4__MASK EQU 0x08\r
+SCSI_In__4__PC EQU CYREG_PRT5_PC3\r
+SCSI_In__4__PORT EQU 5\r
+SCSI_In__4__PRT EQU CYREG_PRT5_PRT\r
+SCSI_In__4__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL\r
+SCSI_In__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN\r
+SCSI_In__4__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0\r
+SCSI_In__4__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1\r
+SCSI_In__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0\r
+SCSI_In__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1\r
+SCSI_In__4__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT\r
+SCSI_In__4__PS EQU CYREG_PRT5_PS\r
+SCSI_In__4__SHIFT EQU 3\r
+SCSI_In__4__SLW EQU CYREG_PRT5_SLW\r
+SCSI_In__CD__AG EQU CYREG_PRT5_AG\r
+SCSI_In__CD__AMUX EQU CYREG_PRT5_AMUX\r
+SCSI_In__CD__BIE EQU CYREG_PRT5_BIE\r
+SCSI_In__CD__BIT_MASK EQU CYREG_PRT5_BIT_MASK\r
+SCSI_In__CD__BYP EQU CYREG_PRT5_BYP\r
+SCSI_In__CD__CTL EQU CYREG_PRT5_CTL\r
+SCSI_In__CD__DM0 EQU CYREG_PRT5_DM0\r
+SCSI_In__CD__DM1 EQU CYREG_PRT5_DM1\r
+SCSI_In__CD__DM2 EQU CYREG_PRT5_DM2\r
+SCSI_In__CD__DR EQU CYREG_PRT5_DR\r
+SCSI_In__CD__INP_DIS EQU CYREG_PRT5_INP_DIS\r
+SCSI_In__CD__INTTYPE EQU CYREG_PICU5_INTTYPE1\r
+SCSI_In__CD__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG\r
+SCSI_In__CD__LCD_EN EQU CYREG_PRT5_LCD_EN\r
+SCSI_In__CD__MASK EQU 0x02\r
+SCSI_In__CD__PC EQU CYREG_PRT5_PC1\r
+SCSI_In__CD__PORT EQU 5\r
+SCSI_In__CD__PRT EQU CYREG_PRT5_PRT\r
+SCSI_In__CD__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL\r
+SCSI_In__CD__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN\r
+SCSI_In__CD__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0\r
+SCSI_In__CD__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1\r
+SCSI_In__CD__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0\r
+SCSI_In__CD__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1\r
+SCSI_In__CD__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT\r
+SCSI_In__CD__PS EQU CYREG_PRT5_PS\r
+SCSI_In__CD__SHIFT EQU 1\r
+SCSI_In__CD__SLW EQU CYREG_PRT5_SLW\r
+SCSI_In__DBP__AG EQU CYREG_PRT2_AG\r
+SCSI_In__DBP__AMUX EQU CYREG_PRT2_AMUX\r
+SCSI_In__DBP__BIE EQU CYREG_PRT2_BIE\r
+SCSI_In__DBP__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
+SCSI_In__DBP__BYP EQU CYREG_PRT2_BYP\r
+SCSI_In__DBP__CTL EQU CYREG_PRT2_CTL\r
+SCSI_In__DBP__DM0 EQU CYREG_PRT2_DM0\r
+SCSI_In__DBP__DM1 EQU CYREG_PRT2_DM1\r
+SCSI_In__DBP__DM2 EQU CYREG_PRT2_DM2\r
+SCSI_In__DBP__DR EQU CYREG_PRT2_DR\r
+SCSI_In__DBP__INP_DIS EQU CYREG_PRT2_INP_DIS\r
+SCSI_In__DBP__INTTYPE EQU CYREG_PICU2_INTTYPE0\r
+SCSI_In__DBP__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
+SCSI_In__DBP__LCD_EN EQU CYREG_PRT2_LCD_EN\r
+SCSI_In__DBP__MASK EQU 0x01\r
+SCSI_In__DBP__PC EQU CYREG_PRT2_PC0\r
+SCSI_In__DBP__PORT EQU 2\r
+SCSI_In__DBP__PRT EQU CYREG_PRT2_PRT\r
+SCSI_In__DBP__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
+SCSI_In__DBP__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
+SCSI_In__DBP__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
+SCSI_In__DBP__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
+SCSI_In__DBP__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
+SCSI_In__DBP__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
+SCSI_In__DBP__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
+SCSI_In__DBP__PS EQU CYREG_PRT2_PS\r
+SCSI_In__DBP__SHIFT EQU 0\r
+SCSI_In__DBP__SLW EQU CYREG_PRT2_SLW\r
+SCSI_In__IO__AG EQU CYREG_PRT5_AG\r
+SCSI_In__IO__AMUX EQU CYREG_PRT5_AMUX\r
+SCSI_In__IO__BIE EQU CYREG_PRT5_BIE\r
+SCSI_In__IO__BIT_MASK EQU CYREG_PRT5_BIT_MASK\r
+SCSI_In__IO__BYP EQU CYREG_PRT5_BYP\r
+SCSI_In__IO__CTL EQU CYREG_PRT5_CTL\r
+SCSI_In__IO__DM0 EQU CYREG_PRT5_DM0\r
+SCSI_In__IO__DM1 EQU CYREG_PRT5_DM1\r
+SCSI_In__IO__DM2 EQU CYREG_PRT5_DM2\r
+SCSI_In__IO__DR EQU CYREG_PRT5_DR\r
+SCSI_In__IO__INP_DIS EQU CYREG_PRT5_INP_DIS\r
+SCSI_In__IO__INTTYPE EQU CYREG_PICU5_INTTYPE3\r
+SCSI_In__IO__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG\r
+SCSI_In__IO__LCD_EN EQU CYREG_PRT5_LCD_EN\r
+SCSI_In__IO__MASK EQU 0x08\r
+SCSI_In__IO__PC EQU CYREG_PRT5_PC3\r
+SCSI_In__IO__PORT EQU 5\r
+SCSI_In__IO__PRT EQU CYREG_PRT5_PRT\r
+SCSI_In__IO__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL\r
+SCSI_In__IO__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN\r
+SCSI_In__IO__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0\r
+SCSI_In__IO__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1\r
+SCSI_In__IO__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0\r
+SCSI_In__IO__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1\r
+SCSI_In__IO__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT\r
+SCSI_In__IO__PS EQU CYREG_PRT5_PS\r
+SCSI_In__IO__SHIFT EQU 3\r
+SCSI_In__IO__SLW EQU CYREG_PRT5_SLW\r
+SCSI_In__MSG__AG EQU CYREG_PRT6_AG\r
+SCSI_In__MSG__AMUX EQU CYREG_PRT6_AMUX\r
+SCSI_In__MSG__BIE EQU CYREG_PRT6_BIE\r
+SCSI_In__MSG__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
+SCSI_In__MSG__BYP EQU CYREG_PRT6_BYP\r
+SCSI_In__MSG__CTL EQU CYREG_PRT6_CTL\r
+SCSI_In__MSG__DM0 EQU CYREG_PRT6_DM0\r
+SCSI_In__MSG__DM1 EQU CYREG_PRT6_DM1\r
+SCSI_In__MSG__DM2 EQU CYREG_PRT6_DM2\r
+SCSI_In__MSG__DR EQU CYREG_PRT6_DR\r
+SCSI_In__MSG__INP_DIS EQU CYREG_PRT6_INP_DIS\r
+SCSI_In__MSG__INTTYPE EQU CYREG_PICU6_INTTYPE7\r
+SCSI_In__MSG__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
+SCSI_In__MSG__LCD_EN EQU CYREG_PRT6_LCD_EN\r
+SCSI_In__MSG__MASK EQU 0x80\r
+SCSI_In__MSG__PC EQU CYREG_PRT6_PC7\r
+SCSI_In__MSG__PORT EQU 6\r
+SCSI_In__MSG__PRT EQU CYREG_PRT6_PRT\r
+SCSI_In__MSG__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
+SCSI_In__MSG__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
+SCSI_In__MSG__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
+SCSI_In__MSG__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
+SCSI_In__MSG__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
+SCSI_In__MSG__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
+SCSI_In__MSG__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
+SCSI_In__MSG__PS EQU CYREG_PRT6_PS\r
+SCSI_In__MSG__SHIFT EQU 7\r
+SCSI_In__MSG__SLW EQU CYREG_PRT6_SLW\r
+SCSI_In__REQ__AG EQU CYREG_PRT5_AG\r
+SCSI_In__REQ__AMUX EQU CYREG_PRT5_AMUX\r
+SCSI_In__REQ__BIE EQU CYREG_PRT5_BIE\r
+SCSI_In__REQ__BIT_MASK EQU CYREG_PRT5_BIT_MASK\r
+SCSI_In__REQ__BYP EQU CYREG_PRT5_BYP\r
+SCSI_In__REQ__CTL EQU CYREG_PRT5_CTL\r
+SCSI_In__REQ__DM0 EQU CYREG_PRT5_DM0\r
+SCSI_In__REQ__DM1 EQU CYREG_PRT5_DM1\r
+SCSI_In__REQ__DM2 EQU CYREG_PRT5_DM2\r
+SCSI_In__REQ__DR EQU CYREG_PRT5_DR\r
+SCSI_In__REQ__INP_DIS EQU CYREG_PRT5_INP_DIS\r
+SCSI_In__REQ__INTTYPE EQU CYREG_PICU5_INTTYPE2\r
+SCSI_In__REQ__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG\r
+SCSI_In__REQ__LCD_EN EQU CYREG_PRT5_LCD_EN\r
+SCSI_In__REQ__MASK EQU 0x04\r
+SCSI_In__REQ__PC EQU CYREG_PRT5_PC2\r
+SCSI_In__REQ__PORT EQU 5\r
+SCSI_In__REQ__PRT EQU CYREG_PRT5_PRT\r
+SCSI_In__REQ__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL\r
+SCSI_In__REQ__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN\r
+SCSI_In__REQ__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0\r
+SCSI_In__REQ__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1\r
+SCSI_In__REQ__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0\r
+SCSI_In__REQ__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1\r
+SCSI_In__REQ__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT\r
+SCSI_In__REQ__PS EQU CYREG_PRT5_PS\r
+SCSI_In__REQ__SHIFT EQU 2\r
+SCSI_In__REQ__SLW EQU CYREG_PRT5_SLW\r
+SCSI_In_DBx__0__AG EQU CYREG_PRT12_AG\r
+SCSI_In_DBx__0__BIE EQU CYREG_PRT12_BIE\r
+SCSI_In_DBx__0__BIT_MASK EQU CYREG_PRT12_BIT_MASK\r
+SCSI_In_DBx__0__BYP EQU CYREG_PRT12_BYP\r
+SCSI_In_DBx__0__DM0 EQU CYREG_PRT12_DM0\r
+SCSI_In_DBx__0__DM1 EQU CYREG_PRT12_DM1\r
+SCSI_In_DBx__0__DM2 EQU CYREG_PRT12_DM2\r
+SCSI_In_DBx__0__DR EQU CYREG_PRT12_DR\r
+SCSI_In_DBx__0__INP_DIS EQU CYREG_PRT12_INP_DIS\r
+SCSI_In_DBx__0__INTTYPE EQU CYREG_PICU12_INTTYPE4\r
+SCSI_In_DBx__0__MASK EQU 0x10\r
+SCSI_In_DBx__0__PC EQU CYREG_PRT12_PC4\r
+SCSI_In_DBx__0__PORT EQU 12\r
+SCSI_In_DBx__0__PRT EQU CYREG_PRT12_PRT\r
+SCSI_In_DBx__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN\r
+SCSI_In_DBx__0__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0\r
+SCSI_In_DBx__0__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1\r
+SCSI_In_DBx__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0\r
+SCSI_In_DBx__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1\r
+SCSI_In_DBx__0__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT\r
+SCSI_In_DBx__0__PS EQU CYREG_PRT12_PS\r
+SCSI_In_DBx__0__SHIFT EQU 4\r
+SCSI_In_DBx__0__SIO_CFG EQU CYREG_PRT12_SIO_CFG\r
+SCSI_In_DBx__0__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF\r
+SCSI_In_DBx__0__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN\r
+SCSI_In_DBx__0__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ\r
+SCSI_In_DBx__0__SLW EQU CYREG_PRT12_SLW\r
+SCSI_In_DBx__1__AG EQU CYREG_PRT2_AG\r
+SCSI_In_DBx__1__AMUX EQU CYREG_PRT2_AMUX\r
+SCSI_In_DBx__1__BIE EQU CYREG_PRT2_BIE\r
+SCSI_In_DBx__1__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
+SCSI_In_DBx__1__BYP EQU CYREG_PRT2_BYP\r
+SCSI_In_DBx__1__CTL EQU CYREG_PRT2_CTL\r
+SCSI_In_DBx__1__DM0 EQU CYREG_PRT2_DM0\r
+SCSI_In_DBx__1__DM1 EQU CYREG_PRT2_DM1\r
+SCSI_In_DBx__1__DM2 EQU CYREG_PRT2_DM2\r
+SCSI_In_DBx__1__DR EQU CYREG_PRT2_DR\r
+SCSI_In_DBx__1__INP_DIS EQU CYREG_PRT2_INP_DIS\r
+SCSI_In_DBx__1__INTTYPE EQU CYREG_PICU2_INTTYPE7\r
+SCSI_In_DBx__1__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
+SCSI_In_DBx__1__LCD_EN EQU CYREG_PRT2_LCD_EN\r
+SCSI_In_DBx__1__MASK EQU 0x80\r
+SCSI_In_DBx__1__PC EQU CYREG_PRT2_PC7\r
+SCSI_In_DBx__1__PORT EQU 2\r
+SCSI_In_DBx__1__PRT EQU CYREG_PRT2_PRT\r
+SCSI_In_DBx__1__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
+SCSI_In_DBx__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
+SCSI_In_DBx__1__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
+SCSI_In_DBx__1__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
+SCSI_In_DBx__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
+SCSI_In_DBx__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
+SCSI_In_DBx__1__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
+SCSI_In_DBx__1__PS EQU CYREG_PRT2_PS\r
+SCSI_In_DBx__1__SHIFT EQU 7\r
+SCSI_In_DBx__1__SLW EQU CYREG_PRT2_SLW\r
+SCSI_In_DBx__2__AG EQU CYREG_PRT2_AG\r
+SCSI_In_DBx__2__AMUX EQU CYREG_PRT2_AMUX\r
+SCSI_In_DBx__2__BIE EQU CYREG_PRT2_BIE\r
+SCSI_In_DBx__2__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
+SCSI_In_DBx__2__BYP EQU CYREG_PRT2_BYP\r
+SCSI_In_DBx__2__CTL EQU CYREG_PRT2_CTL\r
+SCSI_In_DBx__2__DM0 EQU CYREG_PRT2_DM0\r
+SCSI_In_DBx__2__DM1 EQU CYREG_PRT2_DM1\r
+SCSI_In_DBx__2__DM2 EQU CYREG_PRT2_DM2\r
+SCSI_In_DBx__2__DR EQU CYREG_PRT2_DR\r
+SCSI_In_DBx__2__INP_DIS EQU CYREG_PRT2_INP_DIS\r
+SCSI_In_DBx__2__INTTYPE EQU CYREG_PICU2_INTTYPE6\r
+SCSI_In_DBx__2__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
+SCSI_In_DBx__2__LCD_EN EQU CYREG_PRT2_LCD_EN\r
+SCSI_In_DBx__2__MASK EQU 0x40\r
+SCSI_In_DBx__2__PC EQU CYREG_PRT2_PC6\r
+SCSI_In_DBx__2__PORT EQU 2\r
+SCSI_In_DBx__2__PRT EQU CYREG_PRT2_PRT\r
+SCSI_In_DBx__2__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
+SCSI_In_DBx__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
+SCSI_In_DBx__2__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
+SCSI_In_DBx__2__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
+SCSI_In_DBx__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
+SCSI_In_DBx__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
+SCSI_In_DBx__2__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
+SCSI_In_DBx__2__PS EQU CYREG_PRT2_PS\r
+SCSI_In_DBx__2__SHIFT EQU 6\r
+SCSI_In_DBx__2__SLW EQU CYREG_PRT2_SLW\r
+SCSI_In_DBx__3__AG EQU CYREG_PRT2_AG\r
+SCSI_In_DBx__3__AMUX EQU CYREG_PRT2_AMUX\r
+SCSI_In_DBx__3__BIE EQU CYREG_PRT2_BIE\r
+SCSI_In_DBx__3__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
+SCSI_In_DBx__3__BYP EQU CYREG_PRT2_BYP\r
+SCSI_In_DBx__3__CTL EQU CYREG_PRT2_CTL\r
+SCSI_In_DBx__3__DM0 EQU CYREG_PRT2_DM0\r
+SCSI_In_DBx__3__DM1 EQU CYREG_PRT2_DM1\r
+SCSI_In_DBx__3__DM2 EQU CYREG_PRT2_DM2\r
+SCSI_In_DBx__3__DR EQU CYREG_PRT2_DR\r
+SCSI_In_DBx__3__INP_DIS EQU CYREG_PRT2_INP_DIS\r
+SCSI_In_DBx__3__INTTYPE EQU CYREG_PICU2_INTTYPE5\r
+SCSI_In_DBx__3__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
+SCSI_In_DBx__3__LCD_EN EQU CYREG_PRT2_LCD_EN\r
+SCSI_In_DBx__3__MASK EQU 0x20\r
+SCSI_In_DBx__3__PC EQU CYREG_PRT2_PC5\r
+SCSI_In_DBx__3__PORT EQU 2\r
+SCSI_In_DBx__3__PRT EQU CYREG_PRT2_PRT\r
+SCSI_In_DBx__3__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
+SCSI_In_DBx__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
+SCSI_In_DBx__3__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
+SCSI_In_DBx__3__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
+SCSI_In_DBx__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
+SCSI_In_DBx__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
+SCSI_In_DBx__3__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
+SCSI_In_DBx__3__PS EQU CYREG_PRT2_PS\r
+SCSI_In_DBx__3__SHIFT EQU 5\r
+SCSI_In_DBx__3__SLW EQU CYREG_PRT2_SLW\r
+SCSI_In_DBx__4__AG EQU CYREG_PRT2_AG\r
+SCSI_In_DBx__4__AMUX EQU CYREG_PRT2_AMUX\r
+SCSI_In_DBx__4__BIE EQU CYREG_PRT2_BIE\r
+SCSI_In_DBx__4__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
+SCSI_In_DBx__4__BYP EQU CYREG_PRT2_BYP\r
+SCSI_In_DBx__4__CTL EQU CYREG_PRT2_CTL\r
+SCSI_In_DBx__4__DM0 EQU CYREG_PRT2_DM0\r
+SCSI_In_DBx__4__DM1 EQU CYREG_PRT2_DM1\r
+SCSI_In_DBx__4__DM2 EQU CYREG_PRT2_DM2\r
+SCSI_In_DBx__4__DR EQU CYREG_PRT2_DR\r
+SCSI_In_DBx__4__INP_DIS EQU CYREG_PRT2_INP_DIS\r
+SCSI_In_DBx__4__INTTYPE EQU CYREG_PICU2_INTTYPE4\r
+SCSI_In_DBx__4__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
+SCSI_In_DBx__4__LCD_EN EQU CYREG_PRT2_LCD_EN\r
+SCSI_In_DBx__4__MASK EQU 0x10\r
+SCSI_In_DBx__4__PC EQU CYREG_PRT2_PC4\r
+SCSI_In_DBx__4__PORT EQU 2\r
+SCSI_In_DBx__4__PRT EQU CYREG_PRT2_PRT\r
+SCSI_In_DBx__4__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
+SCSI_In_DBx__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
+SCSI_In_DBx__4__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
+SCSI_In_DBx__4__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
+SCSI_In_DBx__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
+SCSI_In_DBx__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
+SCSI_In_DBx__4__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
+SCSI_In_DBx__4__PS EQU CYREG_PRT2_PS\r
+SCSI_In_DBx__4__SHIFT EQU 4\r
+SCSI_In_DBx__4__SLW EQU CYREG_PRT2_SLW\r
+SCSI_In_DBx__5__AG EQU CYREG_PRT2_AG\r
+SCSI_In_DBx__5__AMUX EQU CYREG_PRT2_AMUX\r
+SCSI_In_DBx__5__BIE EQU CYREG_PRT2_BIE\r
+SCSI_In_DBx__5__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
+SCSI_In_DBx__5__BYP EQU CYREG_PRT2_BYP\r
+SCSI_In_DBx__5__CTL EQU CYREG_PRT2_CTL\r
+SCSI_In_DBx__5__DM0 EQU CYREG_PRT2_DM0\r
+SCSI_In_DBx__5__DM1 EQU CYREG_PRT2_DM1\r
+SCSI_In_DBx__5__DM2 EQU CYREG_PRT2_DM2\r
+SCSI_In_DBx__5__DR EQU CYREG_PRT2_DR\r
+SCSI_In_DBx__5__INP_DIS EQU CYREG_PRT2_INP_DIS\r
+SCSI_In_DBx__5__INTTYPE EQU CYREG_PICU2_INTTYPE3\r
+SCSI_In_DBx__5__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
+SCSI_In_DBx__5__LCD_EN EQU CYREG_PRT2_LCD_EN\r
+SCSI_In_DBx__5__MASK EQU 0x08\r
+SCSI_In_DBx__5__PC EQU CYREG_PRT2_PC3\r
+SCSI_In_DBx__5__PORT EQU 2\r
+SCSI_In_DBx__5__PRT EQU CYREG_PRT2_PRT\r
+SCSI_In_DBx__5__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
+SCSI_In_DBx__5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
+SCSI_In_DBx__5__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
+SCSI_In_DBx__5__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
+SCSI_In_DBx__5__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
+SCSI_In_DBx__5__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
+SCSI_In_DBx__5__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
+SCSI_In_DBx__5__PS EQU CYREG_PRT2_PS\r
+SCSI_In_DBx__5__SHIFT EQU 3\r
+SCSI_In_DBx__5__SLW EQU CYREG_PRT2_SLW\r
+SCSI_In_DBx__6__AG EQU CYREG_PRT2_AG\r
+SCSI_In_DBx__6__AMUX EQU CYREG_PRT2_AMUX\r
+SCSI_In_DBx__6__BIE EQU CYREG_PRT2_BIE\r
+SCSI_In_DBx__6__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
+SCSI_In_DBx__6__BYP EQU CYREG_PRT2_BYP\r
+SCSI_In_DBx__6__CTL EQU CYREG_PRT2_CTL\r
+SCSI_In_DBx__6__DM0 EQU CYREG_PRT2_DM0\r
+SCSI_In_DBx__6__DM1 EQU CYREG_PRT2_DM1\r
+SCSI_In_DBx__6__DM2 EQU CYREG_PRT2_DM2\r
+SCSI_In_DBx__6__DR EQU CYREG_PRT2_DR\r
+SCSI_In_DBx__6__INP_DIS EQU CYREG_PRT2_INP_DIS\r
+SCSI_In_DBx__6__INTTYPE EQU CYREG_PICU2_INTTYPE2\r
+SCSI_In_DBx__6__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
+SCSI_In_DBx__6__LCD_EN EQU CYREG_PRT2_LCD_EN\r
+SCSI_In_DBx__6__MASK EQU 0x04\r
+SCSI_In_DBx__6__PC EQU CYREG_PRT2_PC2\r
+SCSI_In_DBx__6__PORT EQU 2\r
+SCSI_In_DBx__6__PRT EQU CYREG_PRT2_PRT\r
+SCSI_In_DBx__6__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
+SCSI_In_DBx__6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
+SCSI_In_DBx__6__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
+SCSI_In_DBx__6__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
+SCSI_In_DBx__6__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
+SCSI_In_DBx__6__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
+SCSI_In_DBx__6__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
+SCSI_In_DBx__6__PS EQU CYREG_PRT2_PS\r
+SCSI_In_DBx__6__SHIFT EQU 2\r
+SCSI_In_DBx__6__SLW EQU CYREG_PRT2_SLW\r
+SCSI_In_DBx__7__AG EQU CYREG_PRT2_AG\r
+SCSI_In_DBx__7__AMUX EQU CYREG_PRT2_AMUX\r
+SCSI_In_DBx__7__BIE EQU CYREG_PRT2_BIE\r
+SCSI_In_DBx__7__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
+SCSI_In_DBx__7__BYP EQU CYREG_PRT2_BYP\r
+SCSI_In_DBx__7__CTL EQU CYREG_PRT2_CTL\r
+SCSI_In_DBx__7__DM0 EQU CYREG_PRT2_DM0\r
+SCSI_In_DBx__7__DM1 EQU CYREG_PRT2_DM1\r
+SCSI_In_DBx__7__DM2 EQU CYREG_PRT2_DM2\r
+SCSI_In_DBx__7__DR EQU CYREG_PRT2_DR\r
+SCSI_In_DBx__7__INP_DIS EQU CYREG_PRT2_INP_DIS\r
+SCSI_In_DBx__7__INTTYPE EQU CYREG_PICU2_INTTYPE1\r
+SCSI_In_DBx__7__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
+SCSI_In_DBx__7__LCD_EN EQU CYREG_PRT2_LCD_EN\r
+SCSI_In_DBx__7__MASK EQU 0x02\r
+SCSI_In_DBx__7__PC EQU CYREG_PRT2_PC1\r
+SCSI_In_DBx__7__PORT EQU 2\r
+SCSI_In_DBx__7__PRT EQU CYREG_PRT2_PRT\r
+SCSI_In_DBx__7__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
+SCSI_In_DBx__7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
+SCSI_In_DBx__7__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
+SCSI_In_DBx__7__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
+SCSI_In_DBx__7__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
+SCSI_In_DBx__7__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
+SCSI_In_DBx__7__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
+SCSI_In_DBx__7__PS EQU CYREG_PRT2_PS\r
+SCSI_In_DBx__7__SHIFT EQU 1\r
+SCSI_In_DBx__7__SLW EQU CYREG_PRT2_SLW\r
+SCSI_In_DBx__DB0__AG EQU CYREG_PRT12_AG\r
+SCSI_In_DBx__DB0__BIE EQU CYREG_PRT12_BIE\r
+SCSI_In_DBx__DB0__BIT_MASK EQU CYREG_PRT12_BIT_MASK\r
+SCSI_In_DBx__DB0__BYP EQU CYREG_PRT12_BYP\r
+SCSI_In_DBx__DB0__DM0 EQU CYREG_PRT12_DM0\r
+SCSI_In_DBx__DB0__DM1 EQU CYREG_PRT12_DM1\r
+SCSI_In_DBx__DB0__DM2 EQU CYREG_PRT12_DM2\r
+SCSI_In_DBx__DB0__DR EQU CYREG_PRT12_DR\r
+SCSI_In_DBx__DB0__INP_DIS EQU CYREG_PRT12_INP_DIS\r
+SCSI_In_DBx__DB0__INTTYPE EQU CYREG_PICU12_INTTYPE4\r
+SCSI_In_DBx__DB0__MASK EQU 0x10\r
+SCSI_In_DBx__DB0__PC EQU CYREG_PRT12_PC4\r
+SCSI_In_DBx__DB0__PORT EQU 12\r
+SCSI_In_DBx__DB0__PRT EQU CYREG_PRT12_PRT\r
+SCSI_In_DBx__DB0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN\r
+SCSI_In_DBx__DB0__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0\r
+SCSI_In_DBx__DB0__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1\r
+SCSI_In_DBx__DB0__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0\r
+SCSI_In_DBx__DB0__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1\r
+SCSI_In_DBx__DB0__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT\r
+SCSI_In_DBx__DB0__PS EQU CYREG_PRT12_PS\r
+SCSI_In_DBx__DB0__SHIFT EQU 4\r
+SCSI_In_DBx__DB0__SIO_CFG EQU CYREG_PRT12_SIO_CFG\r
+SCSI_In_DBx__DB0__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF\r
+SCSI_In_DBx__DB0__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN\r
+SCSI_In_DBx__DB0__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ\r
+SCSI_In_DBx__DB0__SLW EQU CYREG_PRT12_SLW\r
+SCSI_In_DBx__DB1__AG EQU CYREG_PRT2_AG\r
+SCSI_In_DBx__DB1__AMUX EQU CYREG_PRT2_AMUX\r
+SCSI_In_DBx__DB1__BIE EQU CYREG_PRT2_BIE\r
+SCSI_In_DBx__DB1__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
+SCSI_In_DBx__DB1__BYP EQU CYREG_PRT2_BYP\r
+SCSI_In_DBx__DB1__CTL EQU CYREG_PRT2_CTL\r
+SCSI_In_DBx__DB1__DM0 EQU CYREG_PRT2_DM0\r
+SCSI_In_DBx__DB1__DM1 EQU CYREG_PRT2_DM1\r
+SCSI_In_DBx__DB1__DM2 EQU CYREG_PRT2_DM2\r
+SCSI_In_DBx__DB1__DR EQU CYREG_PRT2_DR\r
+SCSI_In_DBx__DB1__INP_DIS EQU CYREG_PRT2_INP_DIS\r
+SCSI_In_DBx__DB1__INTTYPE EQU CYREG_PICU2_INTTYPE7\r
+SCSI_In_DBx__DB1__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
+SCSI_In_DBx__DB1__LCD_EN EQU CYREG_PRT2_LCD_EN\r
+SCSI_In_DBx__DB1__MASK EQU 0x80\r
+SCSI_In_DBx__DB1__PC EQU CYREG_PRT2_PC7\r
+SCSI_In_DBx__DB1__PORT EQU 2\r
+SCSI_In_DBx__DB1__PRT EQU CYREG_PRT2_PRT\r
+SCSI_In_DBx__DB1__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
+SCSI_In_DBx__DB1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
+SCSI_In_DBx__DB1__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
+SCSI_In_DBx__DB1__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
+SCSI_In_DBx__DB1__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
+SCSI_In_DBx__DB1__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
+SCSI_In_DBx__DB1__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
+SCSI_In_DBx__DB1__PS EQU CYREG_PRT2_PS\r
+SCSI_In_DBx__DB1__SHIFT EQU 7\r
+SCSI_In_DBx__DB1__SLW EQU CYREG_PRT2_SLW\r
+SCSI_In_DBx__DB2__AG EQU CYREG_PRT2_AG\r
+SCSI_In_DBx__DB2__AMUX EQU CYREG_PRT2_AMUX\r
+SCSI_In_DBx__DB2__BIE EQU CYREG_PRT2_BIE\r
+SCSI_In_DBx__DB2__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
+SCSI_In_DBx__DB2__BYP EQU CYREG_PRT2_BYP\r
+SCSI_In_DBx__DB2__CTL EQU CYREG_PRT2_CTL\r
+SCSI_In_DBx__DB2__DM0 EQU CYREG_PRT2_DM0\r
+SCSI_In_DBx__DB2__DM1 EQU CYREG_PRT2_DM1\r
+SCSI_In_DBx__DB2__DM2 EQU CYREG_PRT2_DM2\r
+SCSI_In_DBx__DB2__DR EQU CYREG_PRT2_DR\r
+SCSI_In_DBx__DB2__INP_DIS EQU CYREG_PRT2_INP_DIS\r
+SCSI_In_DBx__DB2__INTTYPE EQU CYREG_PICU2_INTTYPE6\r
+SCSI_In_DBx__DB2__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
+SCSI_In_DBx__DB2__LCD_EN EQU CYREG_PRT2_LCD_EN\r
+SCSI_In_DBx__DB2__MASK EQU 0x40\r
+SCSI_In_DBx__DB2__PC EQU CYREG_PRT2_PC6\r
+SCSI_In_DBx__DB2__PORT EQU 2\r
+SCSI_In_DBx__DB2__PRT EQU CYREG_PRT2_PRT\r
+SCSI_In_DBx__DB2__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
+SCSI_In_DBx__DB2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
+SCSI_In_DBx__DB2__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
+SCSI_In_DBx__DB2__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
+SCSI_In_DBx__DB2__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
+SCSI_In_DBx__DB2__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
+SCSI_In_DBx__DB2__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
+SCSI_In_DBx__DB2__PS EQU CYREG_PRT2_PS\r
+SCSI_In_DBx__DB2__SHIFT EQU 6\r
+SCSI_In_DBx__DB2__SLW EQU CYREG_PRT2_SLW\r
+SCSI_In_DBx__DB3__AG EQU CYREG_PRT2_AG\r
+SCSI_In_DBx__DB3__AMUX EQU CYREG_PRT2_AMUX\r
+SCSI_In_DBx__DB3__BIE EQU CYREG_PRT2_BIE\r
+SCSI_In_DBx__DB3__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
+SCSI_In_DBx__DB3__BYP EQU CYREG_PRT2_BYP\r
+SCSI_In_DBx__DB3__CTL EQU CYREG_PRT2_CTL\r
+SCSI_In_DBx__DB3__DM0 EQU CYREG_PRT2_DM0\r
+SCSI_In_DBx__DB3__DM1 EQU CYREG_PRT2_DM1\r
+SCSI_In_DBx__DB3__DM2 EQU CYREG_PRT2_DM2\r
+SCSI_In_DBx__DB3__DR EQU CYREG_PRT2_DR\r
+SCSI_In_DBx__DB3__INP_DIS EQU CYREG_PRT2_INP_DIS\r
+SCSI_In_DBx__DB3__INTTYPE EQU CYREG_PICU2_INTTYPE5\r
+SCSI_In_DBx__DB3__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
+SCSI_In_DBx__DB3__LCD_EN EQU CYREG_PRT2_LCD_EN\r
+SCSI_In_DBx__DB3__MASK EQU 0x20\r
+SCSI_In_DBx__DB3__PC EQU CYREG_PRT2_PC5\r
+SCSI_In_DBx__DB3__PORT EQU 2\r
+SCSI_In_DBx__DB3__PRT EQU CYREG_PRT2_PRT\r
+SCSI_In_DBx__DB3__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
+SCSI_In_DBx__DB3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
+SCSI_In_DBx__DB3__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
+SCSI_In_DBx__DB3__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
+SCSI_In_DBx__DB3__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
+SCSI_In_DBx__DB3__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
+SCSI_In_DBx__DB3__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
+SCSI_In_DBx__DB3__PS EQU CYREG_PRT2_PS\r
+SCSI_In_DBx__DB3__SHIFT EQU 5\r
+SCSI_In_DBx__DB3__SLW EQU CYREG_PRT2_SLW\r
+SCSI_In_DBx__DB4__AG EQU CYREG_PRT2_AG\r
+SCSI_In_DBx__DB4__AMUX EQU CYREG_PRT2_AMUX\r
+SCSI_In_DBx__DB4__BIE EQU CYREG_PRT2_BIE\r
+SCSI_In_DBx__DB4__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
+SCSI_In_DBx__DB4__BYP EQU CYREG_PRT2_BYP\r
+SCSI_In_DBx__DB4__CTL EQU CYREG_PRT2_CTL\r
+SCSI_In_DBx__DB4__DM0 EQU CYREG_PRT2_DM0\r
+SCSI_In_DBx__DB4__DM1 EQU CYREG_PRT2_DM1\r
+SCSI_In_DBx__DB4__DM2 EQU CYREG_PRT2_DM2\r
+SCSI_In_DBx__DB4__DR EQU CYREG_PRT2_DR\r
+SCSI_In_DBx__DB4__INP_DIS EQU CYREG_PRT2_INP_DIS\r
+SCSI_In_DBx__DB4__INTTYPE EQU CYREG_PICU2_INTTYPE4\r
+SCSI_In_DBx__DB4__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
+SCSI_In_DBx__DB4__LCD_EN EQU CYREG_PRT2_LCD_EN\r
+SCSI_In_DBx__DB4__MASK EQU 0x10\r
+SCSI_In_DBx__DB4__PC EQU CYREG_PRT2_PC4\r
+SCSI_In_DBx__DB4__PORT EQU 2\r
+SCSI_In_DBx__DB4__PRT EQU CYREG_PRT2_PRT\r
+SCSI_In_DBx__DB4__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
+SCSI_In_DBx__DB4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
+SCSI_In_DBx__DB4__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
+SCSI_In_DBx__DB4__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
+SCSI_In_DBx__DB4__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
+SCSI_In_DBx__DB4__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
+SCSI_In_DBx__DB4__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
+SCSI_In_DBx__DB4__PS EQU CYREG_PRT2_PS\r
+SCSI_In_DBx__DB4__SHIFT EQU 4\r
+SCSI_In_DBx__DB4__SLW EQU CYREG_PRT2_SLW\r
+SCSI_In_DBx__DB5__AG EQU CYREG_PRT2_AG\r
+SCSI_In_DBx__DB5__AMUX EQU CYREG_PRT2_AMUX\r
+SCSI_In_DBx__DB5__BIE EQU CYREG_PRT2_BIE\r
+SCSI_In_DBx__DB5__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
+SCSI_In_DBx__DB5__BYP EQU CYREG_PRT2_BYP\r
+SCSI_In_DBx__DB5__CTL EQU CYREG_PRT2_CTL\r
+SCSI_In_DBx__DB5__DM0 EQU CYREG_PRT2_DM0\r
+SCSI_In_DBx__DB5__DM1 EQU CYREG_PRT2_DM1\r
+SCSI_In_DBx__DB5__DM2 EQU CYREG_PRT2_DM2\r
+SCSI_In_DBx__DB5__DR EQU CYREG_PRT2_DR\r
+SCSI_In_DBx__DB5__INP_DIS EQU CYREG_PRT2_INP_DIS\r
+SCSI_In_DBx__DB5__INTTYPE EQU CYREG_PICU2_INTTYPE3\r
+SCSI_In_DBx__DB5__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
+SCSI_In_DBx__DB5__LCD_EN EQU CYREG_PRT2_LCD_EN\r
+SCSI_In_DBx__DB5__MASK EQU 0x08\r
+SCSI_In_DBx__DB5__PC EQU CYREG_PRT2_PC3\r
+SCSI_In_DBx__DB5__PORT EQU 2\r
+SCSI_In_DBx__DB5__PRT EQU CYREG_PRT2_PRT\r
+SCSI_In_DBx__DB5__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
+SCSI_In_DBx__DB5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
+SCSI_In_DBx__DB5__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
+SCSI_In_DBx__DB5__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
+SCSI_In_DBx__DB5__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
+SCSI_In_DBx__DB5__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
+SCSI_In_DBx__DB5__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
+SCSI_In_DBx__DB5__PS EQU CYREG_PRT2_PS\r
+SCSI_In_DBx__DB5__SHIFT EQU 3\r
+SCSI_In_DBx__DB5__SLW EQU CYREG_PRT2_SLW\r
+SCSI_In_DBx__DB6__AG EQU CYREG_PRT2_AG\r
+SCSI_In_DBx__DB6__AMUX EQU CYREG_PRT2_AMUX\r
+SCSI_In_DBx__DB6__BIE EQU CYREG_PRT2_BIE\r
+SCSI_In_DBx__DB6__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
+SCSI_In_DBx__DB6__BYP EQU CYREG_PRT2_BYP\r
+SCSI_In_DBx__DB6__CTL EQU CYREG_PRT2_CTL\r
+SCSI_In_DBx__DB6__DM0 EQU CYREG_PRT2_DM0\r
+SCSI_In_DBx__DB6__DM1 EQU CYREG_PRT2_DM1\r
+SCSI_In_DBx__DB6__DM2 EQU CYREG_PRT2_DM2\r
+SCSI_In_DBx__DB6__DR EQU CYREG_PRT2_DR\r
+SCSI_In_DBx__DB6__INP_DIS EQU CYREG_PRT2_INP_DIS\r
+SCSI_In_DBx__DB6__INTTYPE EQU CYREG_PICU2_INTTYPE2\r
+SCSI_In_DBx__DB6__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
+SCSI_In_DBx__DB6__LCD_EN EQU CYREG_PRT2_LCD_EN\r
+SCSI_In_DBx__DB6__MASK EQU 0x04\r
+SCSI_In_DBx__DB6__PC EQU CYREG_PRT2_PC2\r
+SCSI_In_DBx__DB6__PORT EQU 2\r
+SCSI_In_DBx__DB6__PRT EQU CYREG_PRT2_PRT\r
+SCSI_In_DBx__DB6__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
+SCSI_In_DBx__DB6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
+SCSI_In_DBx__DB6__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
+SCSI_In_DBx__DB6__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
+SCSI_In_DBx__DB6__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
+SCSI_In_DBx__DB6__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
+SCSI_In_DBx__DB6__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
+SCSI_In_DBx__DB6__PS EQU CYREG_PRT2_PS\r
+SCSI_In_DBx__DB6__SHIFT EQU 2\r
+SCSI_In_DBx__DB6__SLW EQU CYREG_PRT2_SLW\r
+SCSI_In_DBx__DB7__AG EQU CYREG_PRT2_AG\r
+SCSI_In_DBx__DB7__AMUX EQU CYREG_PRT2_AMUX\r
+SCSI_In_DBx__DB7__BIE EQU CYREG_PRT2_BIE\r
+SCSI_In_DBx__DB7__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
+SCSI_In_DBx__DB7__BYP EQU CYREG_PRT2_BYP\r
+SCSI_In_DBx__DB7__CTL EQU CYREG_PRT2_CTL\r
+SCSI_In_DBx__DB7__DM0 EQU CYREG_PRT2_DM0\r
+SCSI_In_DBx__DB7__DM1 EQU CYREG_PRT2_DM1\r
+SCSI_In_DBx__DB7__DM2 EQU CYREG_PRT2_DM2\r
+SCSI_In_DBx__DB7__DR EQU CYREG_PRT2_DR\r
+SCSI_In_DBx__DB7__INP_DIS EQU CYREG_PRT2_INP_DIS\r
+SCSI_In_DBx__DB7__INTTYPE EQU CYREG_PICU2_INTTYPE1\r
+SCSI_In_DBx__DB7__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
+SCSI_In_DBx__DB7__LCD_EN EQU CYREG_PRT2_LCD_EN\r
+SCSI_In_DBx__DB7__MASK EQU 0x02\r
+SCSI_In_DBx__DB7__PC EQU CYREG_PRT2_PC1\r
+SCSI_In_DBx__DB7__PORT EQU 2\r
+SCSI_In_DBx__DB7__PRT EQU CYREG_PRT2_PRT\r
+SCSI_In_DBx__DB7__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
+SCSI_In_DBx__DB7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
+SCSI_In_DBx__DB7__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
+SCSI_In_DBx__DB7__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
+SCSI_In_DBx__DB7__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
+SCSI_In_DBx__DB7__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
+SCSI_In_DBx__DB7__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
+SCSI_In_DBx__DB7__PS EQU CYREG_PRT2_PS\r
+SCSI_In_DBx__DB7__SHIFT EQU 1\r
+SCSI_In_DBx__DB7__SLW EQU CYREG_PRT2_SLW\r
+\r
+/* SD_DAT1 */\r
+SD_DAT1__0__INTTYPE EQU CYREG_PICU3_INTTYPE0\r
+SD_DAT1__0__MASK EQU 0x01\r
+SD_DAT1__0__PC EQU CYREG_PRT3_PC0\r
+SD_DAT1__0__PORT EQU 3\r
+SD_DAT1__0__SHIFT EQU 0\r
+SD_DAT1__AG EQU CYREG_PRT3_AG\r
+SD_DAT1__AMUX EQU CYREG_PRT3_AMUX\r
+SD_DAT1__BIE EQU CYREG_PRT3_BIE\r
+SD_DAT1__BIT_MASK EQU CYREG_PRT3_BIT_MASK\r
+SD_DAT1__BYP EQU CYREG_PRT3_BYP\r
+SD_DAT1__CTL EQU CYREG_PRT3_CTL\r
+SD_DAT1__DM0 EQU CYREG_PRT3_DM0\r
+SD_DAT1__DM1 EQU CYREG_PRT3_DM1\r
+SD_DAT1__DM2 EQU CYREG_PRT3_DM2\r
+SD_DAT1__DR EQU CYREG_PRT3_DR\r
+SD_DAT1__INP_DIS EQU CYREG_PRT3_INP_DIS\r
+SD_DAT1__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE\r
+SD_DAT1__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG\r
+SD_DAT1__LCD_EN EQU CYREG_PRT3_LCD_EN\r
+SD_DAT1__MASK EQU 0x01\r
+SD_DAT1__PORT EQU 3\r
+SD_DAT1__PRT EQU CYREG_PRT3_PRT\r
+SD_DAT1__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL\r
+SD_DAT1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN\r
+SD_DAT1__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0\r
+SD_DAT1__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1\r
+SD_DAT1__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0\r
+SD_DAT1__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1\r
+SD_DAT1__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT\r
+SD_DAT1__PS EQU CYREG_PRT3_PS\r
+SD_DAT1__SHIFT EQU 0\r
+SD_DAT1__SLW EQU CYREG_PRT3_SLW\r
+\r
+/* SD_DAT2 */\r
+SD_DAT2__0__INTTYPE EQU CYREG_PICU3_INTTYPE5\r
+SD_DAT2__0__MASK EQU 0x20\r
+SD_DAT2__0__PC EQU CYREG_PRT3_PC5\r
+SD_DAT2__0__PORT EQU 3\r
+SD_DAT2__0__SHIFT EQU 5\r
+SD_DAT2__AG EQU CYREG_PRT3_AG\r
+SD_DAT2__AMUX EQU CYREG_PRT3_AMUX\r
+SD_DAT2__BIE EQU CYREG_PRT3_BIE\r
+SD_DAT2__BIT_MASK EQU CYREG_PRT3_BIT_MASK\r
+SD_DAT2__BYP EQU CYREG_PRT3_BYP\r
+SD_DAT2__CTL EQU CYREG_PRT3_CTL\r
+SD_DAT2__DM0 EQU CYREG_PRT3_DM0\r
+SD_DAT2__DM1 EQU CYREG_PRT3_DM1\r
+SD_DAT2__DM2 EQU CYREG_PRT3_DM2\r
+SD_DAT2__DR EQU CYREG_PRT3_DR\r
+SD_DAT2__INP_DIS EQU CYREG_PRT3_INP_DIS\r
+SD_DAT2__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE\r
+SD_DAT2__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG\r
+SD_DAT2__LCD_EN EQU CYREG_PRT3_LCD_EN\r
+SD_DAT2__MASK EQU 0x20\r
+SD_DAT2__PORT EQU 3\r
+SD_DAT2__PRT EQU CYREG_PRT3_PRT\r
+SD_DAT2__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL\r
+SD_DAT2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN\r
+SD_DAT2__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0\r
+SD_DAT2__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1\r
+SD_DAT2__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0\r
+SD_DAT2__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1\r
+SD_DAT2__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT\r
+SD_DAT2__PS EQU CYREG_PRT3_PS\r
+SD_DAT2__SHIFT EQU 5\r
+SD_DAT2__SLW EQU CYREG_PRT3_SLW\r
+\r
+/* SD_MISO */\r
+SD_MISO__0__INTTYPE EQU CYREG_PICU3_INTTYPE1\r
+SD_MISO__0__MASK EQU 0x02\r
+SD_MISO__0__PC EQU CYREG_PRT3_PC1\r
+SD_MISO__0__PORT EQU 3\r
+SD_MISO__0__SHIFT EQU 1\r
+SD_MISO__AG EQU CYREG_PRT3_AG\r
+SD_MISO__AMUX EQU CYREG_PRT3_AMUX\r
+SD_MISO__BIE EQU CYREG_PRT3_BIE\r
+SD_MISO__BIT_MASK EQU CYREG_PRT3_BIT_MASK\r
+SD_MISO__BYP EQU CYREG_PRT3_BYP\r
+SD_MISO__CTL EQU CYREG_PRT3_CTL\r
+SD_MISO__DM0 EQU CYREG_PRT3_DM0\r
+SD_MISO__DM1 EQU CYREG_PRT3_DM1\r
+SD_MISO__DM2 EQU CYREG_PRT3_DM2\r
+SD_MISO__DR EQU CYREG_PRT3_DR\r
+SD_MISO__INP_DIS EQU CYREG_PRT3_INP_DIS\r
+SD_MISO__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE\r
+SD_MISO__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG\r
+SD_MISO__LCD_EN EQU CYREG_PRT3_LCD_EN\r
+SD_MISO__MASK EQU 0x02\r
+SD_MISO__PORT EQU 3\r
+SD_MISO__PRT EQU CYREG_PRT3_PRT\r
+SD_MISO__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL\r
+SD_MISO__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN\r
+SD_MISO__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0\r
+SD_MISO__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1\r
+SD_MISO__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0\r
+SD_MISO__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1\r
+SD_MISO__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT\r
+SD_MISO__PS EQU CYREG_PRT3_PS\r
+SD_MISO__SHIFT EQU 1\r
+SD_MISO__SLW EQU CYREG_PRT3_SLW\r
+\r
+/* SD_MOSI */\r
+SD_MOSI__0__INTTYPE EQU CYREG_PICU3_INTTYPE3\r
+SD_MOSI__0__MASK EQU 0x08\r
+SD_MOSI__0__PC EQU CYREG_PRT3_PC3\r
+SD_MOSI__0__PORT EQU 3\r
+SD_MOSI__0__SHIFT EQU 3\r
+SD_MOSI__AG EQU CYREG_PRT3_AG\r
+SD_MOSI__AMUX EQU CYREG_PRT3_AMUX\r
+SD_MOSI__BIE EQU CYREG_PRT3_BIE\r
+SD_MOSI__BIT_MASK EQU CYREG_PRT3_BIT_MASK\r
+SD_MOSI__BYP EQU CYREG_PRT3_BYP\r
+SD_MOSI__CTL EQU CYREG_PRT3_CTL\r
+SD_MOSI__DM0 EQU CYREG_PRT3_DM0\r
+SD_MOSI__DM1 EQU CYREG_PRT3_DM1\r
+SD_MOSI__DM2 EQU CYREG_PRT3_DM2\r
+SD_MOSI__DR EQU CYREG_PRT3_DR\r
+SD_MOSI__INP_DIS EQU CYREG_PRT3_INP_DIS\r
+SD_MOSI__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE\r
+SD_MOSI__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG\r
+SD_MOSI__LCD_EN EQU CYREG_PRT3_LCD_EN\r
+SD_MOSI__MASK EQU 0x08\r
+SD_MOSI__PORT EQU 3\r
+SD_MOSI__PRT EQU CYREG_PRT3_PRT\r
+SD_MOSI__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL\r
+SD_MOSI__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN\r
+SD_MOSI__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0\r
+SD_MOSI__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1\r
+SD_MOSI__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0\r
+SD_MOSI__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1\r
+SD_MOSI__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT\r
+SD_MOSI__PS EQU CYREG_PRT3_PS\r
+SD_MOSI__SHIFT EQU 3\r
+SD_MOSI__SLW EQU CYREG_PRT3_SLW\r
+\r
+/* SCSI_CLK */\r
+SCSI_CLK__CFG0 EQU CYREG_CLKDIST_DCFG1_CFG0\r
+SCSI_CLK__CFG1 EQU CYREG_CLKDIST_DCFG1_CFG1\r
+SCSI_CLK__CFG2 EQU CYREG_CLKDIST_DCFG1_CFG2\r
+SCSI_CLK__CFG2_SRC_SEL_MASK EQU 0x07\r
+SCSI_CLK__INDEX EQU 0x01\r
+SCSI_CLK__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2\r
+SCSI_CLK__PM_ACT_MSK EQU 0x02\r
+SCSI_CLK__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2\r
+SCSI_CLK__PM_STBY_MSK EQU 0x02\r
+\r
+/* SCSI_Out */\r
+SCSI_Out__0__AG EQU CYREG_PRT4_AG\r
+SCSI_Out__0__AMUX EQU CYREG_PRT4_AMUX\r
+SCSI_Out__0__BIE EQU CYREG_PRT4_BIE\r
+SCSI_Out__0__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
+SCSI_Out__0__BYP EQU CYREG_PRT4_BYP\r
+SCSI_Out__0__CTL EQU CYREG_PRT4_CTL\r
+SCSI_Out__0__DM0 EQU CYREG_PRT4_DM0\r
+SCSI_Out__0__DM1 EQU CYREG_PRT4_DM1\r
+SCSI_Out__0__DM2 EQU CYREG_PRT4_DM2\r
+SCSI_Out__0__DR EQU CYREG_PRT4_DR\r
+SCSI_Out__0__INP_DIS EQU CYREG_PRT4_INP_DIS\r
+SCSI_Out__0__INTTYPE EQU CYREG_PICU4_INTTYPE3\r
+SCSI_Out__0__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
+SCSI_Out__0__LCD_EN EQU CYREG_PRT4_LCD_EN\r
+SCSI_Out__0__MASK EQU 0x08\r
+SCSI_Out__0__PC EQU CYREG_PRT4_PC3\r
+SCSI_Out__0__PORT EQU 4\r
+SCSI_Out__0__PRT EQU CYREG_PRT4_PRT\r
+SCSI_Out__0__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
+SCSI_Out__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
+SCSI_Out__0__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
+SCSI_Out__0__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
+SCSI_Out__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
+SCSI_Out__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
+SCSI_Out__0__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
+SCSI_Out__0__PS EQU CYREG_PRT4_PS\r
+SCSI_Out__0__SHIFT EQU 3\r
+SCSI_Out__0__SLW EQU CYREG_PRT4_SLW\r
+SCSI_Out__1__AG EQU CYREG_PRT4_AG\r
+SCSI_Out__1__AMUX EQU CYREG_PRT4_AMUX\r
+SCSI_Out__1__BIE EQU CYREG_PRT4_BIE\r
+SCSI_Out__1__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
+SCSI_Out__1__BYP EQU CYREG_PRT4_BYP\r
+SCSI_Out__1__CTL EQU CYREG_PRT4_CTL\r
+SCSI_Out__1__DM0 EQU CYREG_PRT4_DM0\r
+SCSI_Out__1__DM1 EQU CYREG_PRT4_DM1\r
+SCSI_Out__1__DM2 EQU CYREG_PRT4_DM2\r
+SCSI_Out__1__DR EQU CYREG_PRT4_DR\r
+SCSI_Out__1__INP_DIS EQU CYREG_PRT4_INP_DIS\r
+SCSI_Out__1__INTTYPE EQU CYREG_PICU4_INTTYPE2\r
+SCSI_Out__1__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
+SCSI_Out__1__LCD_EN EQU CYREG_PRT4_LCD_EN\r
+SCSI_Out__1__MASK EQU 0x04\r
+SCSI_Out__1__PC EQU CYREG_PRT4_PC2\r
+SCSI_Out__1__PORT EQU 4\r
+SCSI_Out__1__PRT EQU CYREG_PRT4_PRT\r
+SCSI_Out__1__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
+SCSI_Out__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
+SCSI_Out__1__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
+SCSI_Out__1__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
+SCSI_Out__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
+SCSI_Out__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
+SCSI_Out__1__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
+SCSI_Out__1__PS EQU CYREG_PRT4_PS\r
+SCSI_Out__1__SHIFT EQU 2\r
+SCSI_Out__1__SLW EQU CYREG_PRT4_SLW\r
+SCSI_Out__2__AG EQU CYREG_PRT0_AG\r
+SCSI_Out__2__AMUX EQU CYREG_PRT0_AMUX\r
+SCSI_Out__2__BIE EQU CYREG_PRT0_BIE\r
+SCSI_Out__2__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
+SCSI_Out__2__BYP EQU CYREG_PRT0_BYP\r
+SCSI_Out__2__CTL EQU CYREG_PRT0_CTL\r
+SCSI_Out__2__DM0 EQU CYREG_PRT0_DM0\r
+SCSI_Out__2__DM1 EQU CYREG_PRT0_DM1\r
+SCSI_Out__2__DM2 EQU CYREG_PRT0_DM2\r
+SCSI_Out__2__DR EQU CYREG_PRT0_DR\r
+SCSI_Out__2__INP_DIS EQU CYREG_PRT0_INP_DIS\r
+SCSI_Out__2__INTTYPE EQU CYREG_PICU0_INTTYPE7\r
+SCSI_Out__2__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
+SCSI_Out__2__LCD_EN EQU CYREG_PRT0_LCD_EN\r
+SCSI_Out__2__MASK EQU 0x80\r
+SCSI_Out__2__PC EQU CYREG_PRT0_PC7\r
+SCSI_Out__2__PORT EQU 0\r
+SCSI_Out__2__PRT EQU CYREG_PRT0_PRT\r
+SCSI_Out__2__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
+SCSI_Out__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
+SCSI_Out__2__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
+SCSI_Out__2__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
+SCSI_Out__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
+SCSI_Out__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
+SCSI_Out__2__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
+SCSI_Out__2__PS EQU CYREG_PRT0_PS\r
+SCSI_Out__2__SHIFT EQU 7\r
+SCSI_Out__2__SLW EQU CYREG_PRT0_SLW\r
+SCSI_Out__3__AG EQU CYREG_PRT0_AG\r
+SCSI_Out__3__AMUX EQU CYREG_PRT0_AMUX\r
+SCSI_Out__3__BIE EQU CYREG_PRT0_BIE\r
+SCSI_Out__3__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
+SCSI_Out__3__BYP EQU CYREG_PRT0_BYP\r
+SCSI_Out__3__CTL EQU CYREG_PRT0_CTL\r
+SCSI_Out__3__DM0 EQU CYREG_PRT0_DM0\r
+SCSI_Out__3__DM1 EQU CYREG_PRT0_DM1\r
+SCSI_Out__3__DM2 EQU CYREG_PRT0_DM2\r
+SCSI_Out__3__DR EQU CYREG_PRT0_DR\r
+SCSI_Out__3__INP_DIS EQU CYREG_PRT0_INP_DIS\r
+SCSI_Out__3__INTTYPE EQU CYREG_PICU0_INTTYPE6\r
+SCSI_Out__3__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
+SCSI_Out__3__LCD_EN EQU CYREG_PRT0_LCD_EN\r
+SCSI_Out__3__MASK EQU 0x40\r
+SCSI_Out__3__PC EQU CYREG_PRT0_PC6\r
+SCSI_Out__3__PORT EQU 0\r
+SCSI_Out__3__PRT EQU CYREG_PRT0_PRT\r
+SCSI_Out__3__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
+SCSI_Out__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
+SCSI_Out__3__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
+SCSI_Out__3__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
+SCSI_Out__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
+SCSI_Out__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
+SCSI_Out__3__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
+SCSI_Out__3__PS EQU CYREG_PRT0_PS\r
+SCSI_Out__3__SHIFT EQU 6\r
+SCSI_Out__3__SLW EQU CYREG_PRT0_SLW\r
+SCSI_Out__4__AG EQU CYREG_PRT0_AG\r
+SCSI_Out__4__AMUX EQU CYREG_PRT0_AMUX\r
+SCSI_Out__4__BIE EQU CYREG_PRT0_BIE\r
+SCSI_Out__4__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
+SCSI_Out__4__BYP EQU CYREG_PRT0_BYP\r
+SCSI_Out__4__CTL EQU CYREG_PRT0_CTL\r
+SCSI_Out__4__DM0 EQU CYREG_PRT0_DM0\r
+SCSI_Out__4__DM1 EQU CYREG_PRT0_DM1\r
+SCSI_Out__4__DM2 EQU CYREG_PRT0_DM2\r
+SCSI_Out__4__DR EQU CYREG_PRT0_DR\r
+SCSI_Out__4__INP_DIS EQU CYREG_PRT0_INP_DIS\r
+SCSI_Out__4__INTTYPE EQU CYREG_PICU0_INTTYPE5\r
+SCSI_Out__4__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
+SCSI_Out__4__LCD_EN EQU CYREG_PRT0_LCD_EN\r
+SCSI_Out__4__MASK EQU 0x20\r
+SCSI_Out__4__PC EQU CYREG_PRT0_PC5\r
+SCSI_Out__4__PORT EQU 0\r
+SCSI_Out__4__PRT EQU CYREG_PRT0_PRT\r
+SCSI_Out__4__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
+SCSI_Out__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
+SCSI_Out__4__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
+SCSI_Out__4__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
+SCSI_Out__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
+SCSI_Out__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
+SCSI_Out__4__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
+SCSI_Out__4__PS EQU CYREG_PRT0_PS\r
+SCSI_Out__4__SHIFT EQU 5\r
+SCSI_Out__4__SLW EQU CYREG_PRT0_SLW\r
+SCSI_Out__5__AG EQU CYREG_PRT0_AG\r
+SCSI_Out__5__AMUX EQU CYREG_PRT0_AMUX\r
+SCSI_Out__5__BIE EQU CYREG_PRT0_BIE\r
+SCSI_Out__5__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
+SCSI_Out__5__BYP EQU CYREG_PRT0_BYP\r
+SCSI_Out__5__CTL EQU CYREG_PRT0_CTL\r
+SCSI_Out__5__DM0 EQU CYREG_PRT0_DM0\r
+SCSI_Out__5__DM1 EQU CYREG_PRT0_DM1\r
+SCSI_Out__5__DM2 EQU CYREG_PRT0_DM2\r
+SCSI_Out__5__DR EQU CYREG_PRT0_DR\r
+SCSI_Out__5__INP_DIS EQU CYREG_PRT0_INP_DIS\r
+SCSI_Out__5__INTTYPE EQU CYREG_PICU0_INTTYPE4\r
+SCSI_Out__5__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
+SCSI_Out__5__LCD_EN EQU CYREG_PRT0_LCD_EN\r
+SCSI_Out__5__MASK EQU 0x10\r
+SCSI_Out__5__PC EQU CYREG_PRT0_PC4\r
+SCSI_Out__5__PORT EQU 0\r
+SCSI_Out__5__PRT EQU CYREG_PRT0_PRT\r
+SCSI_Out__5__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
+SCSI_Out__5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
+SCSI_Out__5__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
+SCSI_Out__5__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
+SCSI_Out__5__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
+SCSI_Out__5__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
+SCSI_Out__5__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
+SCSI_Out__5__PS EQU CYREG_PRT0_PS\r
+SCSI_Out__5__SHIFT EQU 4\r
+SCSI_Out__5__SLW EQU CYREG_PRT0_SLW\r
+SCSI_Out__6__AG EQU CYREG_PRT0_AG\r
+SCSI_Out__6__AMUX EQU CYREG_PRT0_AMUX\r
+SCSI_Out__6__BIE EQU CYREG_PRT0_BIE\r
+SCSI_Out__6__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
+SCSI_Out__6__BYP EQU CYREG_PRT0_BYP\r
+SCSI_Out__6__CTL EQU CYREG_PRT0_CTL\r
+SCSI_Out__6__DM0 EQU CYREG_PRT0_DM0\r
+SCSI_Out__6__DM1 EQU CYREG_PRT0_DM1\r
+SCSI_Out__6__DM2 EQU CYREG_PRT0_DM2\r
+SCSI_Out__6__DR EQU CYREG_PRT0_DR\r
+SCSI_Out__6__INP_DIS EQU CYREG_PRT0_INP_DIS\r
+SCSI_Out__6__INTTYPE EQU CYREG_PICU0_INTTYPE3\r
+SCSI_Out__6__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
+SCSI_Out__6__LCD_EN EQU CYREG_PRT0_LCD_EN\r
+SCSI_Out__6__MASK EQU 0x08\r
+SCSI_Out__6__PC EQU CYREG_PRT0_PC3\r
+SCSI_Out__6__PORT EQU 0\r
+SCSI_Out__6__PRT EQU CYREG_PRT0_PRT\r
+SCSI_Out__6__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
+SCSI_Out__6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
+SCSI_Out__6__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
+SCSI_Out__6__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
+SCSI_Out__6__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
+SCSI_Out__6__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
+SCSI_Out__6__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
+SCSI_Out__6__PS EQU CYREG_PRT0_PS\r
+SCSI_Out__6__SHIFT EQU 3\r
+SCSI_Out__6__SLW EQU CYREG_PRT0_SLW\r
+SCSI_Out__7__AG EQU CYREG_PRT0_AG\r
+SCSI_Out__7__AMUX EQU CYREG_PRT0_AMUX\r
+SCSI_Out__7__BIE EQU CYREG_PRT0_BIE\r
+SCSI_Out__7__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
+SCSI_Out__7__BYP EQU CYREG_PRT0_BYP\r
+SCSI_Out__7__CTL EQU CYREG_PRT0_CTL\r
+SCSI_Out__7__DM0 EQU CYREG_PRT0_DM0\r
+SCSI_Out__7__DM1 EQU CYREG_PRT0_DM1\r
+SCSI_Out__7__DM2 EQU CYREG_PRT0_DM2\r
+SCSI_Out__7__DR EQU CYREG_PRT0_DR\r
+SCSI_Out__7__INP_DIS EQU CYREG_PRT0_INP_DIS\r
+SCSI_Out__7__INTTYPE EQU CYREG_PICU0_INTTYPE2\r
+SCSI_Out__7__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
+SCSI_Out__7__LCD_EN EQU CYREG_PRT0_LCD_EN\r
+SCSI_Out__7__MASK EQU 0x04\r
+SCSI_Out__7__PC EQU CYREG_PRT0_PC2\r
+SCSI_Out__7__PORT EQU 0\r
+SCSI_Out__7__PRT EQU CYREG_PRT0_PRT\r
+SCSI_Out__7__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
+SCSI_Out__7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
+SCSI_Out__7__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
+SCSI_Out__7__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
+SCSI_Out__7__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
+SCSI_Out__7__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
+SCSI_Out__7__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
+SCSI_Out__7__PS EQU CYREG_PRT0_PS\r
+SCSI_Out__7__SHIFT EQU 2\r
+SCSI_Out__7__SLW EQU CYREG_PRT0_SLW\r
+SCSI_Out__8__AG EQU CYREG_PRT0_AG\r
+SCSI_Out__8__AMUX EQU CYREG_PRT0_AMUX\r
+SCSI_Out__8__BIE EQU CYREG_PRT0_BIE\r
+SCSI_Out__8__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
+SCSI_Out__8__BYP EQU CYREG_PRT0_BYP\r
+SCSI_Out__8__CTL EQU CYREG_PRT0_CTL\r
+SCSI_Out__8__DM0 EQU CYREG_PRT0_DM0\r
+SCSI_Out__8__DM1 EQU CYREG_PRT0_DM1\r
+SCSI_Out__8__DM2 EQU CYREG_PRT0_DM2\r
+SCSI_Out__8__DR EQU CYREG_PRT0_DR\r
+SCSI_Out__8__INP_DIS EQU CYREG_PRT0_INP_DIS\r
+SCSI_Out__8__INTTYPE EQU CYREG_PICU0_INTTYPE1\r
+SCSI_Out__8__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
+SCSI_Out__8__LCD_EN EQU CYREG_PRT0_LCD_EN\r
+SCSI_Out__8__MASK EQU 0x02\r
+SCSI_Out__8__PC EQU CYREG_PRT0_PC1\r
+SCSI_Out__8__PORT EQU 0\r
+SCSI_Out__8__PRT EQU CYREG_PRT0_PRT\r
+SCSI_Out__8__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
+SCSI_Out__8__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
+SCSI_Out__8__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
+SCSI_Out__8__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
+SCSI_Out__8__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
+SCSI_Out__8__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
+SCSI_Out__8__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
+SCSI_Out__8__PS EQU CYREG_PRT0_PS\r
+SCSI_Out__8__SHIFT EQU 1\r
+SCSI_Out__8__SLW EQU CYREG_PRT0_SLW\r
+SCSI_Out__9__AG EQU CYREG_PRT0_AG\r
+SCSI_Out__9__AMUX EQU CYREG_PRT0_AMUX\r
+SCSI_Out__9__BIE EQU CYREG_PRT0_BIE\r
+SCSI_Out__9__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
+SCSI_Out__9__BYP EQU CYREG_PRT0_BYP\r
+SCSI_Out__9__CTL EQU CYREG_PRT0_CTL\r
+SCSI_Out__9__DM0 EQU CYREG_PRT0_DM0\r
+SCSI_Out__9__DM1 EQU CYREG_PRT0_DM1\r
+SCSI_Out__9__DM2 EQU CYREG_PRT0_DM2\r
+SCSI_Out__9__DR EQU CYREG_PRT0_DR\r
+SCSI_Out__9__INP_DIS EQU CYREG_PRT0_INP_DIS\r
+SCSI_Out__9__INTTYPE EQU CYREG_PICU0_INTTYPE0\r
+SCSI_Out__9__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
+SCSI_Out__9__LCD_EN EQU CYREG_PRT0_LCD_EN\r
+SCSI_Out__9__MASK EQU 0x01\r
+SCSI_Out__9__PC EQU CYREG_PRT0_PC0\r
+SCSI_Out__9__PORT EQU 0\r
+SCSI_Out__9__PRT EQU CYREG_PRT0_PRT\r
+SCSI_Out__9__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
+SCSI_Out__9__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
+SCSI_Out__9__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
+SCSI_Out__9__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
+SCSI_Out__9__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
+SCSI_Out__9__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
+SCSI_Out__9__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
+SCSI_Out__9__PS EQU CYREG_PRT0_PS\r
+SCSI_Out__9__SHIFT EQU 0\r
+SCSI_Out__9__SLW EQU CYREG_PRT0_SLW\r
+SCSI_Out__ACK__AG EQU CYREG_PRT0_AG\r
+SCSI_Out__ACK__AMUX EQU CYREG_PRT0_AMUX\r
+SCSI_Out__ACK__BIE EQU CYREG_PRT0_BIE\r
+SCSI_Out__ACK__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
+SCSI_Out__ACK__BYP EQU CYREG_PRT0_BYP\r
+SCSI_Out__ACK__CTL EQU CYREG_PRT0_CTL\r
+SCSI_Out__ACK__DM0 EQU CYREG_PRT0_DM0\r
+SCSI_Out__ACK__DM1 EQU CYREG_PRT0_DM1\r
+SCSI_Out__ACK__DM2 EQU CYREG_PRT0_DM2\r
+SCSI_Out__ACK__DR EQU CYREG_PRT0_DR\r
+SCSI_Out__ACK__INP_DIS EQU CYREG_PRT0_INP_DIS\r
+SCSI_Out__ACK__INTTYPE EQU CYREG_PICU0_INTTYPE6\r
+SCSI_Out__ACK__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
+SCSI_Out__ACK__LCD_EN EQU CYREG_PRT0_LCD_EN\r
+SCSI_Out__ACK__MASK EQU 0x40\r
+SCSI_Out__ACK__PC EQU CYREG_PRT0_PC6\r
+SCSI_Out__ACK__PORT EQU 0\r
+SCSI_Out__ACK__PRT EQU CYREG_PRT0_PRT\r
+SCSI_Out__ACK__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
+SCSI_Out__ACK__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
+SCSI_Out__ACK__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
+SCSI_Out__ACK__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
+SCSI_Out__ACK__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
+SCSI_Out__ACK__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
+SCSI_Out__ACK__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
+SCSI_Out__ACK__PS EQU CYREG_PRT0_PS\r
+SCSI_Out__ACK__SHIFT EQU 6\r
+SCSI_Out__ACK__SLW EQU CYREG_PRT0_SLW\r
+SCSI_Out__ATN__AG EQU CYREG_PRT4_AG\r
+SCSI_Out__ATN__AMUX EQU CYREG_PRT4_AMUX\r
+SCSI_Out__ATN__BIE EQU CYREG_PRT4_BIE\r
+SCSI_Out__ATN__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
+SCSI_Out__ATN__BYP EQU CYREG_PRT4_BYP\r
+SCSI_Out__ATN__CTL EQU CYREG_PRT4_CTL\r
+SCSI_Out__ATN__DM0 EQU CYREG_PRT4_DM0\r
+SCSI_Out__ATN__DM1 EQU CYREG_PRT4_DM1\r
+SCSI_Out__ATN__DM2 EQU CYREG_PRT4_DM2\r
+SCSI_Out__ATN__DR EQU CYREG_PRT4_DR\r
+SCSI_Out__ATN__INP_DIS EQU CYREG_PRT4_INP_DIS\r
+SCSI_Out__ATN__INTTYPE EQU CYREG_PICU4_INTTYPE2\r
+SCSI_Out__ATN__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
+SCSI_Out__ATN__LCD_EN EQU CYREG_PRT4_LCD_EN\r
+SCSI_Out__ATN__MASK EQU 0x04\r
+SCSI_Out__ATN__PC EQU CYREG_PRT4_PC2\r
+SCSI_Out__ATN__PORT EQU 4\r
+SCSI_Out__ATN__PRT EQU CYREG_PRT4_PRT\r
+SCSI_Out__ATN__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
+SCSI_Out__ATN__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
+SCSI_Out__ATN__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
+SCSI_Out__ATN__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
+SCSI_Out__ATN__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
+SCSI_Out__ATN__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
+SCSI_Out__ATN__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
+SCSI_Out__ATN__PS EQU CYREG_PRT4_PS\r
+SCSI_Out__ATN__SHIFT EQU 2\r
+SCSI_Out__ATN__SLW EQU CYREG_PRT4_SLW\r
+SCSI_Out__BSY__AG EQU CYREG_PRT0_AG\r
+SCSI_Out__BSY__AMUX EQU CYREG_PRT0_AMUX\r
+SCSI_Out__BSY__BIE EQU CYREG_PRT0_BIE\r
+SCSI_Out__BSY__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
+SCSI_Out__BSY__BYP EQU CYREG_PRT0_BYP\r
+SCSI_Out__BSY__CTL EQU CYREG_PRT0_CTL\r
+SCSI_Out__BSY__DM0 EQU CYREG_PRT0_DM0\r
+SCSI_Out__BSY__DM1 EQU CYREG_PRT0_DM1\r
+SCSI_Out__BSY__DM2 EQU CYREG_PRT0_DM2\r
+SCSI_Out__BSY__DR EQU CYREG_PRT0_DR\r
+SCSI_Out__BSY__INP_DIS EQU CYREG_PRT0_INP_DIS\r
+SCSI_Out__BSY__INTTYPE EQU CYREG_PICU0_INTTYPE7\r
+SCSI_Out__BSY__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
+SCSI_Out__BSY__LCD_EN EQU CYREG_PRT0_LCD_EN\r
+SCSI_Out__BSY__MASK EQU 0x80\r
+SCSI_Out__BSY__PC EQU CYREG_PRT0_PC7\r
+SCSI_Out__BSY__PORT EQU 0\r
+SCSI_Out__BSY__PRT EQU CYREG_PRT0_PRT\r
+SCSI_Out__BSY__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
+SCSI_Out__BSY__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
+SCSI_Out__BSY__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
+SCSI_Out__BSY__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
+SCSI_Out__BSY__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
+SCSI_Out__BSY__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
+SCSI_Out__BSY__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
+SCSI_Out__BSY__PS EQU CYREG_PRT0_PS\r
+SCSI_Out__BSY__SHIFT EQU 7\r
+SCSI_Out__BSY__SLW EQU CYREG_PRT0_SLW\r
+SCSI_Out__CD_raw__AG EQU CYREG_PRT0_AG\r
+SCSI_Out__CD_raw__AMUX EQU CYREG_PRT0_AMUX\r
+SCSI_Out__CD_raw__BIE EQU CYREG_PRT0_BIE\r
+SCSI_Out__CD_raw__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
+SCSI_Out__CD_raw__BYP EQU CYREG_PRT0_BYP\r
+SCSI_Out__CD_raw__CTL EQU CYREG_PRT0_CTL\r
+SCSI_Out__CD_raw__DM0 EQU CYREG_PRT0_DM0\r
+SCSI_Out__CD_raw__DM1 EQU CYREG_PRT0_DM1\r
+SCSI_Out__CD_raw__DM2 EQU CYREG_PRT0_DM2\r
+SCSI_Out__CD_raw__DR EQU CYREG_PRT0_DR\r
+SCSI_Out__CD_raw__INP_DIS EQU CYREG_PRT0_INP_DIS\r
+SCSI_Out__CD_raw__INTTYPE EQU CYREG_PICU0_INTTYPE2\r
+SCSI_Out__CD_raw__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
+SCSI_Out__CD_raw__LCD_EN EQU CYREG_PRT0_LCD_EN\r
+SCSI_Out__CD_raw__MASK EQU 0x04\r
+SCSI_Out__CD_raw__PC EQU CYREG_PRT0_PC2\r
+SCSI_Out__CD_raw__PORT EQU 0\r
+SCSI_Out__CD_raw__PRT EQU CYREG_PRT0_PRT\r
+SCSI_Out__CD_raw__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
+SCSI_Out__CD_raw__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
+SCSI_Out__CD_raw__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
+SCSI_Out__CD_raw__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
+SCSI_Out__CD_raw__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
+SCSI_Out__CD_raw__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
+SCSI_Out__CD_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
+SCSI_Out__CD_raw__PS EQU CYREG_PRT0_PS\r
+SCSI_Out__CD_raw__SHIFT EQU 2\r
+SCSI_Out__CD_raw__SLW EQU CYREG_PRT0_SLW\r
+SCSI_Out__DBP_raw__AG EQU CYREG_PRT4_AG\r
+SCSI_Out__DBP_raw__AMUX EQU CYREG_PRT4_AMUX\r
+SCSI_Out__DBP_raw__BIE EQU CYREG_PRT4_BIE\r
+SCSI_Out__DBP_raw__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
+SCSI_Out__DBP_raw__BYP EQU CYREG_PRT4_BYP\r
+SCSI_Out__DBP_raw__CTL EQU CYREG_PRT4_CTL\r
+SCSI_Out__DBP_raw__DM0 EQU CYREG_PRT4_DM0\r
+SCSI_Out__DBP_raw__DM1 EQU CYREG_PRT4_DM1\r
+SCSI_Out__DBP_raw__DM2 EQU CYREG_PRT4_DM2\r
+SCSI_Out__DBP_raw__DR EQU CYREG_PRT4_DR\r
+SCSI_Out__DBP_raw__INP_DIS EQU CYREG_PRT4_INP_DIS\r
+SCSI_Out__DBP_raw__INTTYPE EQU CYREG_PICU4_INTTYPE3\r
+SCSI_Out__DBP_raw__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
+SCSI_Out__DBP_raw__LCD_EN EQU CYREG_PRT4_LCD_EN\r
+SCSI_Out__DBP_raw__MASK EQU 0x08\r
+SCSI_Out__DBP_raw__PC EQU CYREG_PRT4_PC3\r
+SCSI_Out__DBP_raw__PORT EQU 4\r
+SCSI_Out__DBP_raw__PRT EQU CYREG_PRT4_PRT\r
+SCSI_Out__DBP_raw__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
+SCSI_Out__DBP_raw__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
+SCSI_Out__DBP_raw__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
+SCSI_Out__DBP_raw__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
+SCSI_Out__DBP_raw__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
+SCSI_Out__DBP_raw__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
+SCSI_Out__DBP_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
+SCSI_Out__DBP_raw__PS EQU CYREG_PRT4_PS\r
+SCSI_Out__DBP_raw__SHIFT EQU 3\r
+SCSI_Out__DBP_raw__SLW EQU CYREG_PRT4_SLW\r
+SCSI_Out__IO_raw__AG EQU CYREG_PRT0_AG\r
+SCSI_Out__IO_raw__AMUX EQU CYREG_PRT0_AMUX\r
+SCSI_Out__IO_raw__BIE EQU CYREG_PRT0_BIE\r
+SCSI_Out__IO_raw__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
+SCSI_Out__IO_raw__BYP EQU CYREG_PRT0_BYP\r
+SCSI_Out__IO_raw__CTL EQU CYREG_PRT0_CTL\r
+SCSI_Out__IO_raw__DM0 EQU CYREG_PRT0_DM0\r
+SCSI_Out__IO_raw__DM1 EQU CYREG_PRT0_DM1\r
+SCSI_Out__IO_raw__DM2 EQU CYREG_PRT0_DM2\r
+SCSI_Out__IO_raw__DR EQU CYREG_PRT0_DR\r
+SCSI_Out__IO_raw__INP_DIS EQU CYREG_PRT0_INP_DIS\r
+SCSI_Out__IO_raw__INTTYPE EQU CYREG_PICU0_INTTYPE0\r
+SCSI_Out__IO_raw__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
+SCSI_Out__IO_raw__LCD_EN EQU CYREG_PRT0_LCD_EN\r
+SCSI_Out__IO_raw__MASK EQU 0x01\r
+SCSI_Out__IO_raw__PC EQU CYREG_PRT0_PC0\r
+SCSI_Out__IO_raw__PORT EQU 0\r
+SCSI_Out__IO_raw__PRT EQU CYREG_PRT0_PRT\r
+SCSI_Out__IO_raw__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
+SCSI_Out__IO_raw__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
+SCSI_Out__IO_raw__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
+SCSI_Out__IO_raw__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
+SCSI_Out__IO_raw__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
+SCSI_Out__IO_raw__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
+SCSI_Out__IO_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
+SCSI_Out__IO_raw__PS EQU CYREG_PRT0_PS\r
+SCSI_Out__IO_raw__SHIFT EQU 0\r
+SCSI_Out__IO_raw__SLW EQU CYREG_PRT0_SLW\r
+SCSI_Out__MSG_raw__AG EQU CYREG_PRT0_AG\r
+SCSI_Out__MSG_raw__AMUX EQU CYREG_PRT0_AMUX\r
+SCSI_Out__MSG_raw__BIE EQU CYREG_PRT0_BIE\r
+SCSI_Out__MSG_raw__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
+SCSI_Out__MSG_raw__BYP EQU CYREG_PRT0_BYP\r
+SCSI_Out__MSG_raw__CTL EQU CYREG_PRT0_CTL\r
+SCSI_Out__MSG_raw__DM0 EQU CYREG_PRT0_DM0\r
+SCSI_Out__MSG_raw__DM1 EQU CYREG_PRT0_DM1\r
+SCSI_Out__MSG_raw__DM2 EQU CYREG_PRT0_DM2\r
+SCSI_Out__MSG_raw__DR EQU CYREG_PRT0_DR\r
+SCSI_Out__MSG_raw__INP_DIS EQU CYREG_PRT0_INP_DIS\r
+SCSI_Out__MSG_raw__INTTYPE EQU CYREG_PICU0_INTTYPE4\r
+SCSI_Out__MSG_raw__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
+SCSI_Out__MSG_raw__LCD_EN EQU CYREG_PRT0_LCD_EN\r
+SCSI_Out__MSG_raw__MASK EQU 0x10\r
+SCSI_Out__MSG_raw__PC EQU CYREG_PRT0_PC4\r
+SCSI_Out__MSG_raw__PORT EQU 0\r
+SCSI_Out__MSG_raw__PRT EQU CYREG_PRT0_PRT\r
+SCSI_Out__MSG_raw__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
+SCSI_Out__MSG_raw__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
+SCSI_Out__MSG_raw__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
+SCSI_Out__MSG_raw__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
+SCSI_Out__MSG_raw__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
+SCSI_Out__MSG_raw__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
+SCSI_Out__MSG_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
+SCSI_Out__MSG_raw__PS EQU CYREG_PRT0_PS\r
+SCSI_Out__MSG_raw__SHIFT EQU 4\r
+SCSI_Out__MSG_raw__SLW EQU CYREG_PRT0_SLW\r
+SCSI_Out__REQ__AG EQU CYREG_PRT0_AG\r
+SCSI_Out__REQ__AMUX EQU CYREG_PRT0_AMUX\r
+SCSI_Out__REQ__BIE EQU CYREG_PRT0_BIE\r
+SCSI_Out__REQ__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
+SCSI_Out__REQ__BYP EQU CYREG_PRT0_BYP\r
+SCSI_Out__REQ__CTL EQU CYREG_PRT0_CTL\r
+SCSI_Out__REQ__DM0 EQU CYREG_PRT0_DM0\r
+SCSI_Out__REQ__DM1 EQU CYREG_PRT0_DM1\r
+SCSI_Out__REQ__DM2 EQU CYREG_PRT0_DM2\r
+SCSI_Out__REQ__DR EQU CYREG_PRT0_DR\r
+SCSI_Out__REQ__INP_DIS EQU CYREG_PRT0_INP_DIS\r
+SCSI_Out__REQ__INTTYPE EQU CYREG_PICU0_INTTYPE1\r
+SCSI_Out__REQ__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
+SCSI_Out__REQ__LCD_EN EQU CYREG_PRT0_LCD_EN\r
+SCSI_Out__REQ__MASK EQU 0x02\r
+SCSI_Out__REQ__PC EQU CYREG_PRT0_PC1\r
+SCSI_Out__REQ__PORT EQU 0\r
+SCSI_Out__REQ__PRT EQU CYREG_PRT0_PRT\r
+SCSI_Out__REQ__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
+SCSI_Out__REQ__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
+SCSI_Out__REQ__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
+SCSI_Out__REQ__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
+SCSI_Out__REQ__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
+SCSI_Out__REQ__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
+SCSI_Out__REQ__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
+SCSI_Out__REQ__PS EQU CYREG_PRT0_PS\r
+SCSI_Out__REQ__SHIFT EQU 1\r
+SCSI_Out__REQ__SLW EQU CYREG_PRT0_SLW\r
+SCSI_Out__RST__AG EQU CYREG_PRT0_AG\r
+SCSI_Out__RST__AMUX EQU CYREG_PRT0_AMUX\r
+SCSI_Out__RST__BIE EQU CYREG_PRT0_BIE\r
+SCSI_Out__RST__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
+SCSI_Out__RST__BYP EQU CYREG_PRT0_BYP\r
+SCSI_Out__RST__CTL EQU CYREG_PRT0_CTL\r
+SCSI_Out__RST__DM0 EQU CYREG_PRT0_DM0\r
+SCSI_Out__RST__DM1 EQU CYREG_PRT0_DM1\r
+SCSI_Out__RST__DM2 EQU CYREG_PRT0_DM2\r
+SCSI_Out__RST__DR EQU CYREG_PRT0_DR\r
+SCSI_Out__RST__INP_DIS EQU CYREG_PRT0_INP_DIS\r
+SCSI_Out__RST__INTTYPE EQU CYREG_PICU0_INTTYPE5\r
+SCSI_Out__RST__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
+SCSI_Out__RST__LCD_EN EQU CYREG_PRT0_LCD_EN\r
+SCSI_Out__RST__MASK EQU 0x20\r
+SCSI_Out__RST__PC EQU CYREG_PRT0_PC5\r
+SCSI_Out__RST__PORT EQU 0\r
+SCSI_Out__RST__PRT EQU CYREG_PRT0_PRT\r
+SCSI_Out__RST__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
+SCSI_Out__RST__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
+SCSI_Out__RST__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
+SCSI_Out__RST__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
+SCSI_Out__RST__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
+SCSI_Out__RST__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
+SCSI_Out__RST__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
+SCSI_Out__RST__PS EQU CYREG_PRT0_PS\r
+SCSI_Out__RST__SHIFT EQU 5\r
+SCSI_Out__RST__SLW EQU CYREG_PRT0_SLW\r
+SCSI_Out__SEL__AG EQU CYREG_PRT0_AG\r
+SCSI_Out__SEL__AMUX EQU CYREG_PRT0_AMUX\r
+SCSI_Out__SEL__BIE EQU CYREG_PRT0_BIE\r
+SCSI_Out__SEL__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
+SCSI_Out__SEL__BYP EQU CYREG_PRT0_BYP\r
+SCSI_Out__SEL__CTL EQU CYREG_PRT0_CTL\r
+SCSI_Out__SEL__DM0 EQU CYREG_PRT0_DM0\r
+SCSI_Out__SEL__DM1 EQU CYREG_PRT0_DM1\r
+SCSI_Out__SEL__DM2 EQU CYREG_PRT0_DM2\r
+SCSI_Out__SEL__DR EQU CYREG_PRT0_DR\r
+SCSI_Out__SEL__INP_DIS EQU CYREG_PRT0_INP_DIS\r
+SCSI_Out__SEL__INTTYPE EQU CYREG_PICU0_INTTYPE3\r
+SCSI_Out__SEL__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
+SCSI_Out__SEL__LCD_EN EQU CYREG_PRT0_LCD_EN\r
+SCSI_Out__SEL__MASK EQU 0x08\r
+SCSI_Out__SEL__PC EQU CYREG_PRT0_PC3\r
+SCSI_Out__SEL__PORT EQU 0\r
+SCSI_Out__SEL__PRT EQU CYREG_PRT0_PRT\r
+SCSI_Out__SEL__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
+SCSI_Out__SEL__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
+SCSI_Out__SEL__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
+SCSI_Out__SEL__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
+SCSI_Out__SEL__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
+SCSI_Out__SEL__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
+SCSI_Out__SEL__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
+SCSI_Out__SEL__PS EQU CYREG_PRT0_PS\r
+SCSI_Out__SEL__SHIFT EQU 3\r
+SCSI_Out__SEL__SLW EQU CYREG_PRT0_SLW\r
+SCSI_Out_Bits_Sync_ctrl_reg__0__MASK EQU 0x01\r
+SCSI_Out_Bits_Sync_ctrl_reg__0__POS EQU 0\r
+SCSI_Out_Bits_Sync_ctrl_reg__1__MASK EQU 0x02\r
+SCSI_Out_Bits_Sync_ctrl_reg__1__POS EQU 1\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB08_09_ACTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB08_09_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB08_09_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB08_09_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB08_09_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB08_09_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB08_09_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB08_09_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB08_09_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__2__MASK EQU 0x04\r
+SCSI_Out_Bits_Sync_ctrl_reg__2__POS EQU 2\r
+SCSI_Out_Bits_Sync_ctrl_reg__3__MASK EQU 0x08\r
+SCSI_Out_Bits_Sync_ctrl_reg__3__POS EQU 3\r
+SCSI_Out_Bits_Sync_ctrl_reg__4__MASK EQU 0x10\r
+SCSI_Out_Bits_Sync_ctrl_reg__4__POS EQU 4\r
+SCSI_Out_Bits_Sync_ctrl_reg__5__MASK EQU 0x20\r
+SCSI_Out_Bits_Sync_ctrl_reg__5__POS EQU 5\r
+SCSI_Out_Bits_Sync_ctrl_reg__6__MASK EQU 0x40\r
+SCSI_Out_Bits_Sync_ctrl_reg__6__POS EQU 6\r
+SCSI_Out_Bits_Sync_ctrl_reg__7__MASK EQU 0x80\r
+SCSI_Out_Bits_Sync_ctrl_reg__7__POS EQU 7\r
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB08_ACTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B1_UDB08_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B1_UDB08_ST_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B1_UDB08_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B1_UDB08_ST_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__MASK EQU 0xFF\r
+SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB08_MSK_ACTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB08_MSK_ACTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B1_UDB08_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01\r
+SCSI_Out_Ctl_Sync_ctrl_reg__0__POS EQU 0\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB08_09_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB08_09_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB08_09_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB08_09_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB08_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB08_ST_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB08_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB08_ST_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__MASK EQU 0x01\r
+SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB08_MSK\r
+SCSI_Out_DBx__0__AG EQU CYREG_PRT6_AG\r
+SCSI_Out_DBx__0__AMUX EQU CYREG_PRT6_AMUX\r
+SCSI_Out_DBx__0__BIE EQU CYREG_PRT6_BIE\r
+SCSI_Out_DBx__0__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
+SCSI_Out_DBx__0__BYP EQU CYREG_PRT6_BYP\r
+SCSI_Out_DBx__0__CTL EQU CYREG_PRT6_CTL\r
+SCSI_Out_DBx__0__DM0 EQU CYREG_PRT6_DM0\r
+SCSI_Out_DBx__0__DM1 EQU CYREG_PRT6_DM1\r
+SCSI_Out_DBx__0__DM2 EQU CYREG_PRT6_DM2\r
+SCSI_Out_DBx__0__DR EQU CYREG_PRT6_DR\r
+SCSI_Out_DBx__0__INP_DIS EQU CYREG_PRT6_INP_DIS\r
+SCSI_Out_DBx__0__INTTYPE EQU CYREG_PICU6_INTTYPE3\r
+SCSI_Out_DBx__0__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
+SCSI_Out_DBx__0__LCD_EN EQU CYREG_PRT6_LCD_EN\r
+SCSI_Out_DBx__0__MASK EQU 0x08\r
+SCSI_Out_DBx__0__PC EQU CYREG_PRT6_PC3\r
+SCSI_Out_DBx__0__PORT EQU 6\r
+SCSI_Out_DBx__0__PRT EQU CYREG_PRT6_PRT\r
+SCSI_Out_DBx__0__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
+SCSI_Out_DBx__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
+SCSI_Out_DBx__0__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
+SCSI_Out_DBx__0__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
+SCSI_Out_DBx__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
+SCSI_Out_DBx__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
+SCSI_Out_DBx__0__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
+SCSI_Out_DBx__0__PS EQU CYREG_PRT6_PS\r
+SCSI_Out_DBx__0__SHIFT EQU 3\r
+SCSI_Out_DBx__0__SLW EQU CYREG_PRT6_SLW\r
+SCSI_Out_DBx__1__AG EQU CYREG_PRT6_AG\r
+SCSI_Out_DBx__1__AMUX EQU CYREG_PRT6_AMUX\r
+SCSI_Out_DBx__1__BIE EQU CYREG_PRT6_BIE\r
+SCSI_Out_DBx__1__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
+SCSI_Out_DBx__1__BYP EQU CYREG_PRT6_BYP\r
+SCSI_Out_DBx__1__CTL EQU CYREG_PRT6_CTL\r
+SCSI_Out_DBx__1__DM0 EQU CYREG_PRT6_DM0\r
+SCSI_Out_DBx__1__DM1 EQU CYREG_PRT6_DM1\r
+SCSI_Out_DBx__1__DM2 EQU CYREG_PRT6_DM2\r
+SCSI_Out_DBx__1__DR EQU CYREG_PRT6_DR\r
+SCSI_Out_DBx__1__INP_DIS EQU CYREG_PRT6_INP_DIS\r
+SCSI_Out_DBx__1__INTTYPE EQU CYREG_PICU6_INTTYPE2\r
+SCSI_Out_DBx__1__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
+SCSI_Out_DBx__1__LCD_EN EQU CYREG_PRT6_LCD_EN\r
+SCSI_Out_DBx__1__MASK EQU 0x04\r
+SCSI_Out_DBx__1__PC EQU CYREG_PRT6_PC2\r
+SCSI_Out_DBx__1__PORT EQU 6\r
+SCSI_Out_DBx__1__PRT EQU CYREG_PRT6_PRT\r
+SCSI_Out_DBx__1__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
+SCSI_Out_DBx__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
+SCSI_Out_DBx__1__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
+SCSI_Out_DBx__1__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
+SCSI_Out_DBx__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
+SCSI_Out_DBx__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
+SCSI_Out_DBx__1__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
+SCSI_Out_DBx__1__PS EQU CYREG_PRT6_PS\r
+SCSI_Out_DBx__1__SHIFT EQU 2\r
+SCSI_Out_DBx__1__SLW EQU CYREG_PRT6_SLW\r
+SCSI_Out_DBx__2__AG EQU CYREG_PRT6_AG\r
+SCSI_Out_DBx__2__AMUX EQU CYREG_PRT6_AMUX\r
+SCSI_Out_DBx__2__BIE EQU CYREG_PRT6_BIE\r
+SCSI_Out_DBx__2__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
+SCSI_Out_DBx__2__BYP EQU CYREG_PRT6_BYP\r
+SCSI_Out_DBx__2__CTL EQU CYREG_PRT6_CTL\r
+SCSI_Out_DBx__2__DM0 EQU CYREG_PRT6_DM0\r
+SCSI_Out_DBx__2__DM1 EQU CYREG_PRT6_DM1\r
+SCSI_Out_DBx__2__DM2 EQU CYREG_PRT6_DM2\r
+SCSI_Out_DBx__2__DR EQU CYREG_PRT6_DR\r
+SCSI_Out_DBx__2__INP_DIS EQU CYREG_PRT6_INP_DIS\r
+SCSI_Out_DBx__2__INTTYPE EQU CYREG_PICU6_INTTYPE1\r
+SCSI_Out_DBx__2__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
+SCSI_Out_DBx__2__LCD_EN EQU CYREG_PRT6_LCD_EN\r
+SCSI_Out_DBx__2__MASK EQU 0x02\r
+SCSI_Out_DBx__2__PC EQU CYREG_PRT6_PC1\r
+SCSI_Out_DBx__2__PORT EQU 6\r
+SCSI_Out_DBx__2__PRT EQU CYREG_PRT6_PRT\r
+SCSI_Out_DBx__2__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
+SCSI_Out_DBx__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
+SCSI_Out_DBx__2__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
+SCSI_Out_DBx__2__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
+SCSI_Out_DBx__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
+SCSI_Out_DBx__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
+SCSI_Out_DBx__2__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
+SCSI_Out_DBx__2__PS EQU CYREG_PRT6_PS\r
+SCSI_Out_DBx__2__SHIFT EQU 1\r
+SCSI_Out_DBx__2__SLW EQU CYREG_PRT6_SLW\r
+SCSI_Out_DBx__3__AG EQU CYREG_PRT6_AG\r
+SCSI_Out_DBx__3__AMUX EQU CYREG_PRT6_AMUX\r
+SCSI_Out_DBx__3__BIE EQU CYREG_PRT6_BIE\r
+SCSI_Out_DBx__3__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
+SCSI_Out_DBx__3__BYP EQU CYREG_PRT6_BYP\r
+SCSI_Out_DBx__3__CTL EQU CYREG_PRT6_CTL\r
+SCSI_Out_DBx__3__DM0 EQU CYREG_PRT6_DM0\r
+SCSI_Out_DBx__3__DM1 EQU CYREG_PRT6_DM1\r
+SCSI_Out_DBx__3__DM2 EQU CYREG_PRT6_DM2\r
+SCSI_Out_DBx__3__DR EQU CYREG_PRT6_DR\r
+SCSI_Out_DBx__3__INP_DIS EQU CYREG_PRT6_INP_DIS\r
+SCSI_Out_DBx__3__INTTYPE EQU CYREG_PICU6_INTTYPE0\r
+SCSI_Out_DBx__3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
+SCSI_Out_DBx__3__LCD_EN EQU CYREG_PRT6_LCD_EN\r
+SCSI_Out_DBx__3__MASK EQU 0x01\r
+SCSI_Out_DBx__3__PC EQU CYREG_PRT6_PC0\r
+SCSI_Out_DBx__3__PORT EQU 6\r
+SCSI_Out_DBx__3__PRT EQU CYREG_PRT6_PRT\r
+SCSI_Out_DBx__3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
+SCSI_Out_DBx__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
+SCSI_Out_DBx__3__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
+SCSI_Out_DBx__3__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
+SCSI_Out_DBx__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
+SCSI_Out_DBx__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
+SCSI_Out_DBx__3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
+SCSI_Out_DBx__3__PS EQU CYREG_PRT6_PS\r
+SCSI_Out_DBx__3__SHIFT EQU 0\r
+SCSI_Out_DBx__3__SLW EQU CYREG_PRT6_SLW\r
+SCSI_Out_DBx__4__AG EQU CYREG_PRT4_AG\r
+SCSI_Out_DBx__4__AMUX EQU CYREG_PRT4_AMUX\r
+SCSI_Out_DBx__4__BIE EQU CYREG_PRT4_BIE\r
+SCSI_Out_DBx__4__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
+SCSI_Out_DBx__4__BYP EQU CYREG_PRT4_BYP\r
+SCSI_Out_DBx__4__CTL EQU CYREG_PRT4_CTL\r
+SCSI_Out_DBx__4__DM0 EQU CYREG_PRT4_DM0\r
+SCSI_Out_DBx__4__DM1 EQU CYREG_PRT4_DM1\r
+SCSI_Out_DBx__4__DM2 EQU CYREG_PRT4_DM2\r
+SCSI_Out_DBx__4__DR EQU CYREG_PRT4_DR\r
+SCSI_Out_DBx__4__INP_DIS EQU CYREG_PRT4_INP_DIS\r
+SCSI_Out_DBx__4__INTTYPE EQU CYREG_PICU4_INTTYPE7\r
+SCSI_Out_DBx__4__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
+SCSI_Out_DBx__4__LCD_EN EQU CYREG_PRT4_LCD_EN\r
+SCSI_Out_DBx__4__MASK EQU 0x80\r
+SCSI_Out_DBx__4__PC EQU CYREG_PRT4_PC7\r
+SCSI_Out_DBx__4__PORT EQU 4\r
+SCSI_Out_DBx__4__PRT EQU CYREG_PRT4_PRT\r
+SCSI_Out_DBx__4__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
+SCSI_Out_DBx__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
+SCSI_Out_DBx__4__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
+SCSI_Out_DBx__4__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
+SCSI_Out_DBx__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
+SCSI_Out_DBx__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
+SCSI_Out_DBx__4__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
+SCSI_Out_DBx__4__PS EQU CYREG_PRT4_PS\r
+SCSI_Out_DBx__4__SHIFT EQU 7\r
+SCSI_Out_DBx__4__SLW EQU CYREG_PRT4_SLW\r
+SCSI_Out_DBx__5__AG EQU CYREG_PRT4_AG\r
+SCSI_Out_DBx__5__AMUX EQU CYREG_PRT4_AMUX\r
+SCSI_Out_DBx__5__BIE EQU CYREG_PRT4_BIE\r
+SCSI_Out_DBx__5__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
+SCSI_Out_DBx__5__BYP EQU CYREG_PRT4_BYP\r
+SCSI_Out_DBx__5__CTL EQU CYREG_PRT4_CTL\r
+SCSI_Out_DBx__5__DM0 EQU CYREG_PRT4_DM0\r
+SCSI_Out_DBx__5__DM1 EQU CYREG_PRT4_DM1\r
+SCSI_Out_DBx__5__DM2 EQU CYREG_PRT4_DM2\r
+SCSI_Out_DBx__5__DR EQU CYREG_PRT4_DR\r
+SCSI_Out_DBx__5__INP_DIS EQU CYREG_PRT4_INP_DIS\r
+SCSI_Out_DBx__5__INTTYPE EQU CYREG_PICU4_INTTYPE6\r
+SCSI_Out_DBx__5__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
+SCSI_Out_DBx__5__LCD_EN EQU CYREG_PRT4_LCD_EN\r
+SCSI_Out_DBx__5__MASK EQU 0x40\r
+SCSI_Out_DBx__5__PC EQU CYREG_PRT4_PC6\r
+SCSI_Out_DBx__5__PORT EQU 4\r
+SCSI_Out_DBx__5__PRT EQU CYREG_PRT4_PRT\r
+SCSI_Out_DBx__5__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
+SCSI_Out_DBx__5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
+SCSI_Out_DBx__5__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
+SCSI_Out_DBx__5__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
+SCSI_Out_DBx__5__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
+SCSI_Out_DBx__5__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
+SCSI_Out_DBx__5__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
+SCSI_Out_DBx__5__PS EQU CYREG_PRT4_PS\r
+SCSI_Out_DBx__5__SHIFT EQU 6\r
+SCSI_Out_DBx__5__SLW EQU CYREG_PRT4_SLW\r
+SCSI_Out_DBx__6__AG EQU CYREG_PRT4_AG\r
+SCSI_Out_DBx__6__AMUX EQU CYREG_PRT4_AMUX\r
+SCSI_Out_DBx__6__BIE EQU CYREG_PRT4_BIE\r
+SCSI_Out_DBx__6__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
+SCSI_Out_DBx__6__BYP EQU CYREG_PRT4_BYP\r
+SCSI_Out_DBx__6__CTL EQU CYREG_PRT4_CTL\r
+SCSI_Out_DBx__6__DM0 EQU CYREG_PRT4_DM0\r
+SCSI_Out_DBx__6__DM1 EQU CYREG_PRT4_DM1\r
+SCSI_Out_DBx__6__DM2 EQU CYREG_PRT4_DM2\r
+SCSI_Out_DBx__6__DR EQU CYREG_PRT4_DR\r
+SCSI_Out_DBx__6__INP_DIS EQU CYREG_PRT4_INP_DIS\r
+SCSI_Out_DBx__6__INTTYPE EQU CYREG_PICU4_INTTYPE5\r
+SCSI_Out_DBx__6__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
+SCSI_Out_DBx__6__LCD_EN EQU CYREG_PRT4_LCD_EN\r
+SCSI_Out_DBx__6__MASK EQU 0x20\r
+SCSI_Out_DBx__6__PC EQU CYREG_PRT4_PC5\r
+SCSI_Out_DBx__6__PORT EQU 4\r
+SCSI_Out_DBx__6__PRT EQU CYREG_PRT4_PRT\r
+SCSI_Out_DBx__6__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
+SCSI_Out_DBx__6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
+SCSI_Out_DBx__6__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
+SCSI_Out_DBx__6__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
+SCSI_Out_DBx__6__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
+SCSI_Out_DBx__6__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
+SCSI_Out_DBx__6__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
+SCSI_Out_DBx__6__PS EQU CYREG_PRT4_PS\r
+SCSI_Out_DBx__6__SHIFT EQU 5\r
+SCSI_Out_DBx__6__SLW EQU CYREG_PRT4_SLW\r
+SCSI_Out_DBx__7__AG EQU CYREG_PRT4_AG\r
+SCSI_Out_DBx__7__AMUX EQU CYREG_PRT4_AMUX\r
+SCSI_Out_DBx__7__BIE EQU CYREG_PRT4_BIE\r
+SCSI_Out_DBx__7__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
+SCSI_Out_DBx__7__BYP EQU CYREG_PRT4_BYP\r
+SCSI_Out_DBx__7__CTL EQU CYREG_PRT4_CTL\r
+SCSI_Out_DBx__7__DM0 EQU CYREG_PRT4_DM0\r
+SCSI_Out_DBx__7__DM1 EQU CYREG_PRT4_DM1\r
+SCSI_Out_DBx__7__DM2 EQU CYREG_PRT4_DM2\r
+SCSI_Out_DBx__7__DR EQU CYREG_PRT4_DR\r
+SCSI_Out_DBx__7__INP_DIS EQU CYREG_PRT4_INP_DIS\r
+SCSI_Out_DBx__7__INTTYPE EQU CYREG_PICU4_INTTYPE4\r
+SCSI_Out_DBx__7__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
+SCSI_Out_DBx__7__LCD_EN EQU CYREG_PRT4_LCD_EN\r
+SCSI_Out_DBx__7__MASK EQU 0x10\r
+SCSI_Out_DBx__7__PC EQU CYREG_PRT4_PC4\r
+SCSI_Out_DBx__7__PORT EQU 4\r
+SCSI_Out_DBx__7__PRT EQU CYREG_PRT4_PRT\r
+SCSI_Out_DBx__7__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
+SCSI_Out_DBx__7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
+SCSI_Out_DBx__7__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
+SCSI_Out_DBx__7__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
+SCSI_Out_DBx__7__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
+SCSI_Out_DBx__7__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
+SCSI_Out_DBx__7__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
+SCSI_Out_DBx__7__PS EQU CYREG_PRT4_PS\r
+SCSI_Out_DBx__7__SHIFT EQU 4\r
+SCSI_Out_DBx__7__SLW EQU CYREG_PRT4_SLW\r
+SCSI_Out_DBx__DB0__AG EQU CYREG_PRT6_AG\r
+SCSI_Out_DBx__DB0__AMUX EQU CYREG_PRT6_AMUX\r
+SCSI_Out_DBx__DB0__BIE EQU CYREG_PRT6_BIE\r
+SCSI_Out_DBx__DB0__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
+SCSI_Out_DBx__DB0__BYP EQU CYREG_PRT6_BYP\r
+SCSI_Out_DBx__DB0__CTL EQU CYREG_PRT6_CTL\r
+SCSI_Out_DBx__DB0__DM0 EQU CYREG_PRT6_DM0\r
+SCSI_Out_DBx__DB0__DM1 EQU CYREG_PRT6_DM1\r
+SCSI_Out_DBx__DB0__DM2 EQU CYREG_PRT6_DM2\r
+SCSI_Out_DBx__DB0__DR EQU CYREG_PRT6_DR\r
+SCSI_Out_DBx__DB0__INP_DIS EQU CYREG_PRT6_INP_DIS\r
+SCSI_Out_DBx__DB0__INTTYPE EQU CYREG_PICU6_INTTYPE3\r
+SCSI_Out_DBx__DB0__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
+SCSI_Out_DBx__DB0__LCD_EN EQU CYREG_PRT6_LCD_EN\r
+SCSI_Out_DBx__DB0__MASK EQU 0x08\r
+SCSI_Out_DBx__DB0__PC EQU CYREG_PRT6_PC3\r
+SCSI_Out_DBx__DB0__PORT EQU 6\r
+SCSI_Out_DBx__DB0__PRT EQU CYREG_PRT6_PRT\r
+SCSI_Out_DBx__DB0__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
+SCSI_Out_DBx__DB0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
+SCSI_Out_DBx__DB0__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
+SCSI_Out_DBx__DB0__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
+SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
+SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
+SCSI_Out_DBx__DB0__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
+SCSI_Out_DBx__DB0__PS EQU CYREG_PRT6_PS\r
+SCSI_Out_DBx__DB0__SHIFT EQU 3\r
+SCSI_Out_DBx__DB0__SLW EQU CYREG_PRT6_SLW\r
+SCSI_Out_DBx__DB1__AG EQU CYREG_PRT6_AG\r
+SCSI_Out_DBx__DB1__AMUX EQU CYREG_PRT6_AMUX\r
+SCSI_Out_DBx__DB1__BIE EQU CYREG_PRT6_BIE\r
+SCSI_Out_DBx__DB1__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
+SCSI_Out_DBx__DB1__BYP EQU CYREG_PRT6_BYP\r
+SCSI_Out_DBx__DB1__CTL EQU CYREG_PRT6_CTL\r
+SCSI_Out_DBx__DB1__DM0 EQU CYREG_PRT6_DM0\r
+SCSI_Out_DBx__DB1__DM1 EQU CYREG_PRT6_DM1\r
+SCSI_Out_DBx__DB1__DM2 EQU CYREG_PRT6_DM2\r
+SCSI_Out_DBx__DB1__DR EQU CYREG_PRT6_DR\r
+SCSI_Out_DBx__DB1__INP_DIS EQU CYREG_PRT6_INP_DIS\r
+SCSI_Out_DBx__DB1__INTTYPE EQU CYREG_PICU6_INTTYPE2\r
+SCSI_Out_DBx__DB1__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
+SCSI_Out_DBx__DB1__LCD_EN EQU CYREG_PRT6_LCD_EN\r
+SCSI_Out_DBx__DB1__MASK EQU 0x04\r
+SCSI_Out_DBx__DB1__PC EQU CYREG_PRT6_PC2\r
+SCSI_Out_DBx__DB1__PORT EQU 6\r
+SCSI_Out_DBx__DB1__PRT EQU CYREG_PRT6_PRT\r
+SCSI_Out_DBx__DB1__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
+SCSI_Out_DBx__DB1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
+SCSI_Out_DBx__DB1__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
+SCSI_Out_DBx__DB1__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
+SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
+SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
+SCSI_Out_DBx__DB1__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
+SCSI_Out_DBx__DB1__PS EQU CYREG_PRT6_PS\r
+SCSI_Out_DBx__DB1__SHIFT EQU 2\r
+SCSI_Out_DBx__DB1__SLW EQU CYREG_PRT6_SLW\r
+SCSI_Out_DBx__DB2__AG EQU CYREG_PRT6_AG\r
+SCSI_Out_DBx__DB2__AMUX EQU CYREG_PRT6_AMUX\r
+SCSI_Out_DBx__DB2__BIE EQU CYREG_PRT6_BIE\r
+SCSI_Out_DBx__DB2__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
+SCSI_Out_DBx__DB2__BYP EQU CYREG_PRT6_BYP\r
+SCSI_Out_DBx__DB2__CTL EQU CYREG_PRT6_CTL\r
+SCSI_Out_DBx__DB2__DM0 EQU CYREG_PRT6_DM0\r
+SCSI_Out_DBx__DB2__DM1 EQU CYREG_PRT6_DM1\r
+SCSI_Out_DBx__DB2__DM2 EQU CYREG_PRT6_DM2\r
+SCSI_Out_DBx__DB2__DR EQU CYREG_PRT6_DR\r
+SCSI_Out_DBx__DB2__INP_DIS EQU CYREG_PRT6_INP_DIS\r
+SCSI_Out_DBx__DB2__INTTYPE EQU CYREG_PICU6_INTTYPE1\r
+SCSI_Out_DBx__DB2__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
+SCSI_Out_DBx__DB2__LCD_EN EQU CYREG_PRT6_LCD_EN\r
+SCSI_Out_DBx__DB2__MASK EQU 0x02\r
+SCSI_Out_DBx__DB2__PC EQU CYREG_PRT6_PC1\r
+SCSI_Out_DBx__DB2__PORT EQU 6\r
+SCSI_Out_DBx__DB2__PRT EQU CYREG_PRT6_PRT\r
+SCSI_Out_DBx__DB2__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
+SCSI_Out_DBx__DB2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
+SCSI_Out_DBx__DB2__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
+SCSI_Out_DBx__DB2__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
+SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
+SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
+SCSI_Out_DBx__DB2__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
+SCSI_Out_DBx__DB2__PS EQU CYREG_PRT6_PS\r
+SCSI_Out_DBx__DB2__SHIFT EQU 1\r
+SCSI_Out_DBx__DB2__SLW EQU CYREG_PRT6_SLW\r
+SCSI_Out_DBx__DB3__AG EQU CYREG_PRT6_AG\r
+SCSI_Out_DBx__DB3__AMUX EQU CYREG_PRT6_AMUX\r
+SCSI_Out_DBx__DB3__BIE EQU CYREG_PRT6_BIE\r
+SCSI_Out_DBx__DB3__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
+SCSI_Out_DBx__DB3__BYP EQU CYREG_PRT6_BYP\r
+SCSI_Out_DBx__DB3__CTL EQU CYREG_PRT6_CTL\r
+SCSI_Out_DBx__DB3__DM0 EQU CYREG_PRT6_DM0\r
+SCSI_Out_DBx__DB3__DM1 EQU CYREG_PRT6_DM1\r
+SCSI_Out_DBx__DB3__DM2 EQU CYREG_PRT6_DM2\r
+SCSI_Out_DBx__DB3__DR EQU CYREG_PRT6_DR\r
+SCSI_Out_DBx__DB3__INP_DIS EQU CYREG_PRT6_INP_DIS\r
+SCSI_Out_DBx__DB3__INTTYPE EQU CYREG_PICU6_INTTYPE0\r
+SCSI_Out_DBx__DB3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
+SCSI_Out_DBx__DB3__LCD_EN EQU CYREG_PRT6_LCD_EN\r
+SCSI_Out_DBx__DB3__MASK EQU 0x01\r
+SCSI_Out_DBx__DB3__PC EQU CYREG_PRT6_PC0\r
+SCSI_Out_DBx__DB3__PORT EQU 6\r
+SCSI_Out_DBx__DB3__PRT EQU CYREG_PRT6_PRT\r
+SCSI_Out_DBx__DB3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
+SCSI_Out_DBx__DB3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
+SCSI_Out_DBx__DB3__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
+SCSI_Out_DBx__DB3__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
+SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
+SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
+SCSI_Out_DBx__DB3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
+SCSI_Out_DBx__DB3__PS EQU CYREG_PRT6_PS\r
+SCSI_Out_DBx__DB3__SHIFT EQU 0\r
+SCSI_Out_DBx__DB3__SLW EQU CYREG_PRT6_SLW\r
+SCSI_Out_DBx__DB4__AG EQU CYREG_PRT4_AG\r
+SCSI_Out_DBx__DB4__AMUX EQU CYREG_PRT4_AMUX\r
+SCSI_Out_DBx__DB4__BIE EQU CYREG_PRT4_BIE\r
+SCSI_Out_DBx__DB4__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
+SCSI_Out_DBx__DB4__BYP EQU CYREG_PRT4_BYP\r
+SCSI_Out_DBx__DB4__CTL EQU CYREG_PRT4_CTL\r
+SCSI_Out_DBx__DB4__DM0 EQU CYREG_PRT4_DM0\r
+SCSI_Out_DBx__DB4__DM1 EQU CYREG_PRT4_DM1\r
+SCSI_Out_DBx__DB4__DM2 EQU CYREG_PRT4_DM2\r
+SCSI_Out_DBx__DB4__DR EQU CYREG_PRT4_DR\r
+SCSI_Out_DBx__DB4__INP_DIS EQU CYREG_PRT4_INP_DIS\r
+SCSI_Out_DBx__DB4__INTTYPE EQU CYREG_PICU4_INTTYPE7\r
+SCSI_Out_DBx__DB4__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
+SCSI_Out_DBx__DB4__LCD_EN EQU CYREG_PRT4_LCD_EN\r
+SCSI_Out_DBx__DB4__MASK EQU 0x80\r
+SCSI_Out_DBx__DB4__PC EQU CYREG_PRT4_PC7\r
+SCSI_Out_DBx__DB4__PORT EQU 4\r
+SCSI_Out_DBx__DB4__PRT EQU CYREG_PRT4_PRT\r
+SCSI_Out_DBx__DB4__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
+SCSI_Out_DBx__DB4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
+SCSI_Out_DBx__DB4__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
+SCSI_Out_DBx__DB4__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
+SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
+SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
+SCSI_Out_DBx__DB4__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
+SCSI_Out_DBx__DB4__PS EQU CYREG_PRT4_PS\r
+SCSI_Out_DBx__DB4__SHIFT EQU 7\r
+SCSI_Out_DBx__DB4__SLW EQU CYREG_PRT4_SLW\r
+SCSI_Out_DBx__DB5__AG EQU CYREG_PRT4_AG\r
+SCSI_Out_DBx__DB5__AMUX EQU CYREG_PRT4_AMUX\r
+SCSI_Out_DBx__DB5__BIE EQU CYREG_PRT4_BIE\r
+SCSI_Out_DBx__DB5__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
+SCSI_Out_DBx__DB5__BYP EQU CYREG_PRT4_BYP\r
+SCSI_Out_DBx__DB5__CTL EQU CYREG_PRT4_CTL\r
+SCSI_Out_DBx__DB5__DM0 EQU CYREG_PRT4_DM0\r
+SCSI_Out_DBx__DB5__DM1 EQU CYREG_PRT4_DM1\r
+SCSI_Out_DBx__DB5__DM2 EQU CYREG_PRT4_DM2\r
+SCSI_Out_DBx__DB5__DR EQU CYREG_PRT4_DR\r
+SCSI_Out_DBx__DB5__INP_DIS EQU CYREG_PRT4_INP_DIS\r
+SCSI_Out_DBx__DB5__INTTYPE EQU CYREG_PICU4_INTTYPE6\r
+SCSI_Out_DBx__DB5__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
+SCSI_Out_DBx__DB5__LCD_EN EQU CYREG_PRT4_LCD_EN\r
+SCSI_Out_DBx__DB5__MASK EQU 0x40\r
+SCSI_Out_DBx__DB5__PC EQU CYREG_PRT4_PC6\r
+SCSI_Out_DBx__DB5__PORT EQU 4\r
+SCSI_Out_DBx__DB5__PRT EQU CYREG_PRT4_PRT\r
+SCSI_Out_DBx__DB5__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
+SCSI_Out_DBx__DB5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
+SCSI_Out_DBx__DB5__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
+SCSI_Out_DBx__DB5__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
+SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
+SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
+SCSI_Out_DBx__DB5__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
+SCSI_Out_DBx__DB5__PS EQU CYREG_PRT4_PS\r
+SCSI_Out_DBx__DB5__SHIFT EQU 6\r
+SCSI_Out_DBx__DB5__SLW EQU CYREG_PRT4_SLW\r
+SCSI_Out_DBx__DB6__AG EQU CYREG_PRT4_AG\r
+SCSI_Out_DBx__DB6__AMUX EQU CYREG_PRT4_AMUX\r
+SCSI_Out_DBx__DB6__BIE EQU CYREG_PRT4_BIE\r
+SCSI_Out_DBx__DB6__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
+SCSI_Out_DBx__DB6__BYP EQU CYREG_PRT4_BYP\r
+SCSI_Out_DBx__DB6__CTL EQU CYREG_PRT4_CTL\r
+SCSI_Out_DBx__DB6__DM0 EQU CYREG_PRT4_DM0\r
+SCSI_Out_DBx__DB6__DM1 EQU CYREG_PRT4_DM1\r
+SCSI_Out_DBx__DB6__DM2 EQU CYREG_PRT4_DM2\r
+SCSI_Out_DBx__DB6__DR EQU CYREG_PRT4_DR\r
+SCSI_Out_DBx__DB6__INP_DIS EQU CYREG_PRT4_INP_DIS\r
+SCSI_Out_DBx__DB6__INTTYPE EQU CYREG_PICU4_INTTYPE5\r
+SCSI_Out_DBx__DB6__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
+SCSI_Out_DBx__DB6__LCD_EN EQU CYREG_PRT4_LCD_EN\r
+SCSI_Out_DBx__DB6__MASK EQU 0x20\r
+SCSI_Out_DBx__DB6__PC EQU CYREG_PRT4_PC5\r
+SCSI_Out_DBx__DB6__PORT EQU 4\r
+SCSI_Out_DBx__DB6__PRT EQU CYREG_PRT4_PRT\r
+SCSI_Out_DBx__DB6__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
+SCSI_Out_DBx__DB6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
+SCSI_Out_DBx__DB6__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
+SCSI_Out_DBx__DB6__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
+SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
+SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
+SCSI_Out_DBx__DB6__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
+SCSI_Out_DBx__DB6__PS EQU CYREG_PRT4_PS\r
+SCSI_Out_DBx__DB6__SHIFT EQU 5\r
+SCSI_Out_DBx__DB6__SLW EQU CYREG_PRT4_SLW\r
+SCSI_Out_DBx__DB7__AG EQU CYREG_PRT4_AG\r
+SCSI_Out_DBx__DB7__AMUX EQU CYREG_PRT4_AMUX\r
+SCSI_Out_DBx__DB7__BIE EQU CYREG_PRT4_BIE\r
+SCSI_Out_DBx__DB7__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
+SCSI_Out_DBx__DB7__BYP EQU CYREG_PRT4_BYP\r
+SCSI_Out_DBx__DB7__CTL EQU CYREG_PRT4_CTL\r
+SCSI_Out_DBx__DB7__DM0 EQU CYREG_PRT4_DM0\r
+SCSI_Out_DBx__DB7__DM1 EQU CYREG_PRT4_DM1\r
+SCSI_Out_DBx__DB7__DM2 EQU CYREG_PRT4_DM2\r
+SCSI_Out_DBx__DB7__DR EQU CYREG_PRT4_DR\r
+SCSI_Out_DBx__DB7__INP_DIS EQU CYREG_PRT4_INP_DIS\r
+SCSI_Out_DBx__DB7__INTTYPE EQU CYREG_PICU4_INTTYPE4\r
+SCSI_Out_DBx__DB7__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
+SCSI_Out_DBx__DB7__LCD_EN EQU CYREG_PRT4_LCD_EN\r
+SCSI_Out_DBx__DB7__MASK EQU 0x10\r
+SCSI_Out_DBx__DB7__PC EQU CYREG_PRT4_PC4\r
+SCSI_Out_DBx__DB7__PORT EQU 4\r
+SCSI_Out_DBx__DB7__PRT EQU CYREG_PRT4_PRT\r
+SCSI_Out_DBx__DB7__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
+SCSI_Out_DBx__DB7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
+SCSI_Out_DBx__DB7__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
+SCSI_Out_DBx__DB7__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
+SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
+SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
+SCSI_Out_DBx__DB7__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
+SCSI_Out_DBx__DB7__PS EQU CYREG_PRT4_PS\r
+SCSI_Out_DBx__DB7__SHIFT EQU 4\r
+SCSI_Out_DBx__DB7__SLW EQU CYREG_PRT4_SLW\r
+\r
+/* SD_RX_DMA */\r
+SD_RX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0\r
+SD_RX_DMA__DRQ_NUMBER EQU 2\r
+SD_RX_DMA__NUMBEROF_TDS EQU 0\r
+SD_RX_DMA__PRIORITY EQU 0\r
+SD_RX_DMA__TERMIN_EN EQU 0\r
+SD_RX_DMA__TERMIN_SEL EQU 0\r
+SD_RX_DMA__TERMOUT0_EN EQU 1\r
+SD_RX_DMA__TERMOUT0_SEL EQU 2\r
+SD_RX_DMA__TERMOUT1_EN EQU 0\r
+SD_RX_DMA__TERMOUT1_SEL EQU 0\r
+SD_RX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
+SD_RX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
+SD_RX_DMA_COMPLETE__INTC_MASK EQU 0x20\r
+SD_RX_DMA_COMPLETE__INTC_NUMBER EQU 5\r
+SD_RX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7\r
+SD_RX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_5\r
+SD_RX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
+SD_RX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
+\r
+/* SD_TX_DMA */\r
+SD_TX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0\r
+SD_TX_DMA__DRQ_NUMBER EQU 3\r
+SD_TX_DMA__NUMBEROF_TDS EQU 0\r
+SD_TX_DMA__PRIORITY EQU 1\r
+SD_TX_DMA__TERMIN_EN EQU 0\r
+SD_TX_DMA__TERMIN_SEL EQU 0\r
+SD_TX_DMA__TERMOUT0_EN EQU 1\r
+SD_TX_DMA__TERMOUT0_SEL EQU 3\r
+SD_TX_DMA__TERMOUT1_EN EQU 0\r
+SD_TX_DMA__TERMOUT1_SEL EQU 0\r
+SD_TX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
+SD_TX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
+SD_TX_DMA_COMPLETE__INTC_MASK EQU 0x40\r
+SD_TX_DMA_COMPLETE__INTC_NUMBER EQU 6\r
+SD_TX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7\r
+SD_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_6\r
+SD_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
+SD_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
+\r
+/* SCSI_Noise */\r
+SCSI_Noise__0__AG EQU CYREG_PRT12_AG\r
+SCSI_Noise__0__BIE EQU CYREG_PRT12_BIE\r
+SCSI_Noise__0__BIT_MASK EQU CYREG_PRT12_BIT_MASK\r
+SCSI_Noise__0__BYP EQU CYREG_PRT12_BYP\r
+SCSI_Noise__0__DM0 EQU CYREG_PRT12_DM0\r
+SCSI_Noise__0__DM1 EQU CYREG_PRT12_DM1\r
+SCSI_Noise__0__DM2 EQU CYREG_PRT12_DM2\r
+SCSI_Noise__0__DR EQU CYREG_PRT12_DR\r
+SCSI_Noise__0__INP_DIS EQU CYREG_PRT12_INP_DIS\r
+SCSI_Noise__0__INTTYPE EQU CYREG_PICU12_INTTYPE5\r
+SCSI_Noise__0__MASK EQU 0x20\r
+SCSI_Noise__0__PC EQU CYREG_PRT12_PC5\r
+SCSI_Noise__0__PORT EQU 12\r
+SCSI_Noise__0__PRT EQU CYREG_PRT12_PRT\r
+SCSI_Noise__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN\r
+SCSI_Noise__0__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0\r
+SCSI_Noise__0__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1\r
+SCSI_Noise__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0\r
+SCSI_Noise__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1\r
+SCSI_Noise__0__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT\r
+SCSI_Noise__0__PS EQU CYREG_PRT12_PS\r
+SCSI_Noise__0__SHIFT EQU 5\r
+SCSI_Noise__0__SIO_CFG EQU CYREG_PRT12_SIO_CFG\r
+SCSI_Noise__0__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF\r
+SCSI_Noise__0__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN\r
+SCSI_Noise__0__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ\r
+SCSI_Noise__0__SLW EQU CYREG_PRT12_SLW\r
+SCSI_Noise__1__AG EQU CYREG_PRT6_AG\r
+SCSI_Noise__1__AMUX EQU CYREG_PRT6_AMUX\r
+SCSI_Noise__1__BIE EQU CYREG_PRT6_BIE\r
+SCSI_Noise__1__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
+SCSI_Noise__1__BYP EQU CYREG_PRT6_BYP\r
+SCSI_Noise__1__CTL EQU CYREG_PRT6_CTL\r
+SCSI_Noise__1__DM0 EQU CYREG_PRT6_DM0\r
+SCSI_Noise__1__DM1 EQU CYREG_PRT6_DM1\r
+SCSI_Noise__1__DM2 EQU CYREG_PRT6_DM2\r
+SCSI_Noise__1__DR EQU CYREG_PRT6_DR\r
+SCSI_Noise__1__INP_DIS EQU CYREG_PRT6_INP_DIS\r
+SCSI_Noise__1__INTTYPE EQU CYREG_PICU6_INTTYPE4\r
+SCSI_Noise__1__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
+SCSI_Noise__1__LCD_EN EQU CYREG_PRT6_LCD_EN\r
+SCSI_Noise__1__MASK EQU 0x10\r
+SCSI_Noise__1__PC EQU CYREG_PRT6_PC4\r
+SCSI_Noise__1__PORT EQU 6\r
+SCSI_Noise__1__PRT EQU CYREG_PRT6_PRT\r
+SCSI_Noise__1__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
+SCSI_Noise__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
+SCSI_Noise__1__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
+SCSI_Noise__1__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
+SCSI_Noise__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
+SCSI_Noise__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
+SCSI_Noise__1__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
+SCSI_Noise__1__PS EQU CYREG_PRT6_PS\r
+SCSI_Noise__1__SHIFT EQU 4\r
+SCSI_Noise__1__SLW EQU CYREG_PRT6_SLW\r
+SCSI_Noise__2__AG EQU CYREG_PRT5_AG\r
+SCSI_Noise__2__AMUX EQU CYREG_PRT5_AMUX\r
+SCSI_Noise__2__BIE EQU CYREG_PRT5_BIE\r
+SCSI_Noise__2__BIT_MASK EQU CYREG_PRT5_BIT_MASK\r
+SCSI_Noise__2__BYP EQU CYREG_PRT5_BYP\r
+SCSI_Noise__2__CTL EQU CYREG_PRT5_CTL\r
+SCSI_Noise__2__DM0 EQU CYREG_PRT5_DM0\r
+SCSI_Noise__2__DM1 EQU CYREG_PRT5_DM1\r
+SCSI_Noise__2__DM2 EQU CYREG_PRT5_DM2\r
+SCSI_Noise__2__DR EQU CYREG_PRT5_DR\r
+SCSI_Noise__2__INP_DIS EQU CYREG_PRT5_INP_DIS\r
+SCSI_Noise__2__INTTYPE EQU CYREG_PICU5_INTTYPE0\r
+SCSI_Noise__2__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG\r
+SCSI_Noise__2__LCD_EN EQU CYREG_PRT5_LCD_EN\r
+SCSI_Noise__2__MASK EQU 0x01\r
+SCSI_Noise__2__PC EQU CYREG_PRT5_PC0\r
+SCSI_Noise__2__PORT EQU 5\r
+SCSI_Noise__2__PRT EQU CYREG_PRT5_PRT\r
+SCSI_Noise__2__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL\r
+SCSI_Noise__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN\r
+SCSI_Noise__2__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0\r
+SCSI_Noise__2__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1\r
+SCSI_Noise__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0\r
+SCSI_Noise__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1\r
+SCSI_Noise__2__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT\r
+SCSI_Noise__2__PS EQU CYREG_PRT5_PS\r
+SCSI_Noise__2__SHIFT EQU 0\r
+SCSI_Noise__2__SLW EQU CYREG_PRT5_SLW\r
+SCSI_Noise__3__AG EQU CYREG_PRT6_AG\r
+SCSI_Noise__3__AMUX EQU CYREG_PRT6_AMUX\r
+SCSI_Noise__3__BIE EQU CYREG_PRT6_BIE\r
+SCSI_Noise__3__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
+SCSI_Noise__3__BYP EQU CYREG_PRT6_BYP\r
+SCSI_Noise__3__CTL EQU CYREG_PRT6_CTL\r
+SCSI_Noise__3__DM0 EQU CYREG_PRT6_DM0\r
+SCSI_Noise__3__DM1 EQU CYREG_PRT6_DM1\r
+SCSI_Noise__3__DM2 EQU CYREG_PRT6_DM2\r
+SCSI_Noise__3__DR EQU CYREG_PRT6_DR\r
+SCSI_Noise__3__INP_DIS EQU CYREG_PRT6_INP_DIS\r
+SCSI_Noise__3__INTTYPE EQU CYREG_PICU6_INTTYPE6\r
+SCSI_Noise__3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
+SCSI_Noise__3__LCD_EN EQU CYREG_PRT6_LCD_EN\r
+SCSI_Noise__3__MASK EQU 0x40\r
+SCSI_Noise__3__PC EQU CYREG_PRT6_PC6\r
+SCSI_Noise__3__PORT EQU 6\r
+SCSI_Noise__3__PRT EQU CYREG_PRT6_PRT\r
+SCSI_Noise__3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
+SCSI_Noise__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
+SCSI_Noise__3__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
+SCSI_Noise__3__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
+SCSI_Noise__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
+SCSI_Noise__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
+SCSI_Noise__3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
+SCSI_Noise__3__PS EQU CYREG_PRT6_PS\r
+SCSI_Noise__3__SHIFT EQU 6\r
+SCSI_Noise__3__SLW EQU CYREG_PRT6_SLW\r
+SCSI_Noise__4__AG EQU CYREG_PRT6_AG\r
+SCSI_Noise__4__AMUX EQU CYREG_PRT6_AMUX\r
+SCSI_Noise__4__BIE EQU CYREG_PRT6_BIE\r
+SCSI_Noise__4__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
+SCSI_Noise__4__BYP EQU CYREG_PRT6_BYP\r
+SCSI_Noise__4__CTL EQU CYREG_PRT6_CTL\r
+SCSI_Noise__4__DM0 EQU CYREG_PRT6_DM0\r
+SCSI_Noise__4__DM1 EQU CYREG_PRT6_DM1\r
+SCSI_Noise__4__DM2 EQU CYREG_PRT6_DM2\r
+SCSI_Noise__4__DR EQU CYREG_PRT6_DR\r
+SCSI_Noise__4__INP_DIS EQU CYREG_PRT6_INP_DIS\r
+SCSI_Noise__4__INTTYPE EQU CYREG_PICU6_INTTYPE5\r
+SCSI_Noise__4__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
+SCSI_Noise__4__LCD_EN EQU CYREG_PRT6_LCD_EN\r
+SCSI_Noise__4__MASK EQU 0x20\r
+SCSI_Noise__4__PC EQU CYREG_PRT6_PC5\r
+SCSI_Noise__4__PORT EQU 6\r
+SCSI_Noise__4__PRT EQU CYREG_PRT6_PRT\r
+SCSI_Noise__4__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
+SCSI_Noise__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
+SCSI_Noise__4__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
+SCSI_Noise__4__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
+SCSI_Noise__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
+SCSI_Noise__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
+SCSI_Noise__4__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
+SCSI_Noise__4__PS EQU CYREG_PRT6_PS\r
+SCSI_Noise__4__SHIFT EQU 5\r
+SCSI_Noise__4__SLW EQU CYREG_PRT6_SLW\r
+SCSI_Noise__ACK__AG EQU CYREG_PRT6_AG\r
+SCSI_Noise__ACK__AMUX EQU CYREG_PRT6_AMUX\r
+SCSI_Noise__ACK__BIE EQU CYREG_PRT6_BIE\r
+SCSI_Noise__ACK__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
+SCSI_Noise__ACK__BYP EQU CYREG_PRT6_BYP\r
+SCSI_Noise__ACK__CTL EQU CYREG_PRT6_CTL\r
+SCSI_Noise__ACK__DM0 EQU CYREG_PRT6_DM0\r
+SCSI_Noise__ACK__DM1 EQU CYREG_PRT6_DM1\r
+SCSI_Noise__ACK__DM2 EQU CYREG_PRT6_DM2\r
+SCSI_Noise__ACK__DR EQU CYREG_PRT6_DR\r
+SCSI_Noise__ACK__INP_DIS EQU CYREG_PRT6_INP_DIS\r
+SCSI_Noise__ACK__INTTYPE EQU CYREG_PICU6_INTTYPE5\r
+SCSI_Noise__ACK__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
+SCSI_Noise__ACK__LCD_EN EQU CYREG_PRT6_LCD_EN\r
+SCSI_Noise__ACK__MASK EQU 0x20\r
+SCSI_Noise__ACK__PC EQU CYREG_PRT6_PC5\r
+SCSI_Noise__ACK__PORT EQU 6\r
+SCSI_Noise__ACK__PRT EQU CYREG_PRT6_PRT\r
+SCSI_Noise__ACK__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
+SCSI_Noise__ACK__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
+SCSI_Noise__ACK__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
+SCSI_Noise__ACK__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
+SCSI_Noise__ACK__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
+SCSI_Noise__ACK__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
+SCSI_Noise__ACK__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
+SCSI_Noise__ACK__PS EQU CYREG_PRT6_PS\r
+SCSI_Noise__ACK__SHIFT EQU 5\r
+SCSI_Noise__ACK__SLW EQU CYREG_PRT6_SLW\r
+SCSI_Noise__ATN__AG EQU CYREG_PRT12_AG\r
+SCSI_Noise__ATN__BIE EQU CYREG_PRT12_BIE\r
+SCSI_Noise__ATN__BIT_MASK EQU CYREG_PRT12_BIT_MASK\r
+SCSI_Noise__ATN__BYP EQU CYREG_PRT12_BYP\r
+SCSI_Noise__ATN__DM0 EQU CYREG_PRT12_DM0\r
+SCSI_Noise__ATN__DM1 EQU CYREG_PRT12_DM1\r
+SCSI_Noise__ATN__DM2 EQU CYREG_PRT12_DM2\r
+SCSI_Noise__ATN__DR EQU CYREG_PRT12_DR\r
+SCSI_Noise__ATN__INP_DIS EQU CYREG_PRT12_INP_DIS\r
+SCSI_Noise__ATN__INTTYPE EQU CYREG_PICU12_INTTYPE5\r
+SCSI_Noise__ATN__MASK EQU 0x20\r
+SCSI_Noise__ATN__PC EQU CYREG_PRT12_PC5\r
+SCSI_Noise__ATN__PORT EQU 12\r
+SCSI_Noise__ATN__PRT EQU CYREG_PRT12_PRT\r
+SCSI_Noise__ATN__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN\r
+SCSI_Noise__ATN__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0\r
+SCSI_Noise__ATN__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1\r
+SCSI_Noise__ATN__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0\r
+SCSI_Noise__ATN__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1\r
+SCSI_Noise__ATN__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT\r
+SCSI_Noise__ATN__PS EQU CYREG_PRT12_PS\r
+SCSI_Noise__ATN__SHIFT EQU 5\r
+SCSI_Noise__ATN__SIO_CFG EQU CYREG_PRT12_SIO_CFG\r
+SCSI_Noise__ATN__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF\r
+SCSI_Noise__ATN__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN\r
+SCSI_Noise__ATN__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ\r
+SCSI_Noise__ATN__SLW EQU CYREG_PRT12_SLW\r
+SCSI_Noise__BSY__AG EQU CYREG_PRT6_AG\r
+SCSI_Noise__BSY__AMUX EQU CYREG_PRT6_AMUX\r
+SCSI_Noise__BSY__BIE EQU CYREG_PRT6_BIE\r
+SCSI_Noise__BSY__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
+SCSI_Noise__BSY__BYP EQU CYREG_PRT6_BYP\r
+SCSI_Noise__BSY__CTL EQU CYREG_PRT6_CTL\r
+SCSI_Noise__BSY__DM0 EQU CYREG_PRT6_DM0\r
+SCSI_Noise__BSY__DM1 EQU CYREG_PRT6_DM1\r
+SCSI_Noise__BSY__DM2 EQU CYREG_PRT6_DM2\r
+SCSI_Noise__BSY__DR EQU CYREG_PRT6_DR\r
+SCSI_Noise__BSY__INP_DIS EQU CYREG_PRT6_INP_DIS\r
+SCSI_Noise__BSY__INTTYPE EQU CYREG_PICU6_INTTYPE4\r
+SCSI_Noise__BSY__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
+SCSI_Noise__BSY__LCD_EN EQU CYREG_PRT6_LCD_EN\r
+SCSI_Noise__BSY__MASK EQU 0x10\r
+SCSI_Noise__BSY__PC EQU CYREG_PRT6_PC4\r
+SCSI_Noise__BSY__PORT EQU 6\r
+SCSI_Noise__BSY__PRT EQU CYREG_PRT6_PRT\r
+SCSI_Noise__BSY__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
+SCSI_Noise__BSY__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
+SCSI_Noise__BSY__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
+SCSI_Noise__BSY__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
+SCSI_Noise__BSY__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
+SCSI_Noise__BSY__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
+SCSI_Noise__BSY__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
+SCSI_Noise__BSY__PS EQU CYREG_PRT6_PS\r
+SCSI_Noise__BSY__SHIFT EQU 4\r
+SCSI_Noise__BSY__SLW EQU CYREG_PRT6_SLW\r
+SCSI_Noise__RST__AG EQU CYREG_PRT6_AG\r
+SCSI_Noise__RST__AMUX EQU CYREG_PRT6_AMUX\r
+SCSI_Noise__RST__BIE EQU CYREG_PRT6_BIE\r
+SCSI_Noise__RST__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
+SCSI_Noise__RST__BYP EQU CYREG_PRT6_BYP\r
+SCSI_Noise__RST__CTL EQU CYREG_PRT6_CTL\r
+SCSI_Noise__RST__DM0 EQU CYREG_PRT6_DM0\r
+SCSI_Noise__RST__DM1 EQU CYREG_PRT6_DM1\r
+SCSI_Noise__RST__DM2 EQU CYREG_PRT6_DM2\r
+SCSI_Noise__RST__DR EQU CYREG_PRT6_DR\r
+SCSI_Noise__RST__INP_DIS EQU CYREG_PRT6_INP_DIS\r
+SCSI_Noise__RST__INTTYPE EQU CYREG_PICU6_INTTYPE6\r
+SCSI_Noise__RST__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
+SCSI_Noise__RST__LCD_EN EQU CYREG_PRT6_LCD_EN\r
+SCSI_Noise__RST__MASK EQU 0x40\r
+SCSI_Noise__RST__PC EQU CYREG_PRT6_PC6\r
+SCSI_Noise__RST__PORT EQU 6\r
+SCSI_Noise__RST__PRT EQU CYREG_PRT6_PRT\r
+SCSI_Noise__RST__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
+SCSI_Noise__RST__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
+SCSI_Noise__RST__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
+SCSI_Noise__RST__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
+SCSI_Noise__RST__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
+SCSI_Noise__RST__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
+SCSI_Noise__RST__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
+SCSI_Noise__RST__PS EQU CYREG_PRT6_PS\r
+SCSI_Noise__RST__SHIFT EQU 6\r
+SCSI_Noise__RST__SLW EQU CYREG_PRT6_SLW\r
+SCSI_Noise__SEL__AG EQU CYREG_PRT5_AG\r
+SCSI_Noise__SEL__AMUX EQU CYREG_PRT5_AMUX\r
+SCSI_Noise__SEL__BIE EQU CYREG_PRT5_BIE\r
+SCSI_Noise__SEL__BIT_MASK EQU CYREG_PRT5_BIT_MASK\r
+SCSI_Noise__SEL__BYP EQU CYREG_PRT5_BYP\r
+SCSI_Noise__SEL__CTL EQU CYREG_PRT5_CTL\r
+SCSI_Noise__SEL__DM0 EQU CYREG_PRT5_DM0\r
+SCSI_Noise__SEL__DM1 EQU CYREG_PRT5_DM1\r
+SCSI_Noise__SEL__DM2 EQU CYREG_PRT5_DM2\r
+SCSI_Noise__SEL__DR EQU CYREG_PRT5_DR\r
+SCSI_Noise__SEL__INP_DIS EQU CYREG_PRT5_INP_DIS\r
+SCSI_Noise__SEL__INTTYPE EQU CYREG_PICU5_INTTYPE0\r
+SCSI_Noise__SEL__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG\r
+SCSI_Noise__SEL__LCD_EN EQU CYREG_PRT5_LCD_EN\r
+SCSI_Noise__SEL__MASK EQU 0x01\r
+SCSI_Noise__SEL__PC EQU CYREG_PRT5_PC0\r
+SCSI_Noise__SEL__PORT EQU 5\r
+SCSI_Noise__SEL__PRT EQU CYREG_PRT5_PRT\r
+SCSI_Noise__SEL__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL\r
+SCSI_Noise__SEL__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN\r
+SCSI_Noise__SEL__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0\r
+SCSI_Noise__SEL__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1\r
+SCSI_Noise__SEL__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0\r
+SCSI_Noise__SEL__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1\r
+SCSI_Noise__SEL__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT\r
+SCSI_Noise__SEL__PS EQU CYREG_PRT5_PS\r
+SCSI_Noise__SEL__SHIFT EQU 0\r
+SCSI_Noise__SEL__SLW EQU CYREG_PRT5_SLW\r
+\r
/* scsiTarget */\r
scsiTarget_datapath__16BIT_A0_REG EQU CYREG_B0_UDB00_01_A0\r
scsiTarget_datapath__16BIT_A1_REG EQU CYREG_B0_UDB00_01_A1\r
scsiTarget_StatusReg__STATUS_CONTROL_REG EQU CYREG_B0_UDB07_ST_CTL\r
scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB07_ST\r
\r
+/* Debug_Timer */\r
+Debug_Timer_Interrupt__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
+Debug_Timer_Interrupt__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
+Debug_Timer_Interrupt__INTC_MASK EQU 0x01\r
+Debug_Timer_Interrupt__INTC_NUMBER EQU 0\r
+Debug_Timer_Interrupt__INTC_PRIOR_NUM EQU 7\r
+Debug_Timer_Interrupt__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_0\r
+Debug_Timer_Interrupt__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
+Debug_Timer_Interrupt__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
+Debug_Timer_TimerHW__CAP0 EQU CYREG_TMR0_CAP0\r
+Debug_Timer_TimerHW__CAP1 EQU CYREG_TMR0_CAP1\r
+Debug_Timer_TimerHW__CFG0 EQU CYREG_TMR0_CFG0\r
+Debug_Timer_TimerHW__CFG1 EQU CYREG_TMR0_CFG1\r
+Debug_Timer_TimerHW__CFG2 EQU CYREG_TMR0_CFG2\r
+Debug_Timer_TimerHW__CNT_CMP0 EQU CYREG_TMR0_CNT_CMP0\r
+Debug_Timer_TimerHW__CNT_CMP1 EQU CYREG_TMR0_CNT_CMP1\r
+Debug_Timer_TimerHW__PER0 EQU CYREG_TMR0_PER0\r
+Debug_Timer_TimerHW__PER1 EQU CYREG_TMR0_PER1\r
+Debug_Timer_TimerHW__PM_ACT_CFG EQU CYREG_PM_ACT_CFG3\r
+Debug_Timer_TimerHW__PM_ACT_MSK EQU 0x01\r
+Debug_Timer_TimerHW__PM_STBY_CFG EQU CYREG_PM_STBY_CFG3\r
+Debug_Timer_TimerHW__PM_STBY_MSK EQU 0x01\r
+Debug_Timer_TimerHW__RT0 EQU CYREG_TMR0_RT0\r
+Debug_Timer_TimerHW__RT1 EQU CYREG_TMR0_RT1\r
+Debug_Timer_TimerHW__SR0 EQU CYREG_TMR0_SR0\r
+\r
+/* SCSI_RX_DMA */\r
+SCSI_RX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0\r
+SCSI_RX_DMA__DRQ_NUMBER EQU 0\r
+SCSI_RX_DMA__NUMBEROF_TDS EQU 0\r
+SCSI_RX_DMA__PRIORITY EQU 2\r
+SCSI_RX_DMA__TERMIN_EN EQU 0\r
+SCSI_RX_DMA__TERMIN_SEL EQU 0\r
+SCSI_RX_DMA__TERMOUT0_EN EQU 1\r
+SCSI_RX_DMA__TERMOUT0_SEL EQU 0\r
+SCSI_RX_DMA__TERMOUT1_EN EQU 0\r
+SCSI_RX_DMA__TERMOUT1_SEL EQU 0\r
+SCSI_RX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
+SCSI_RX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
+SCSI_RX_DMA_COMPLETE__INTC_MASK EQU 0x04\r
+SCSI_RX_DMA_COMPLETE__INTC_NUMBER EQU 2\r
+SCSI_RX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7\r
+SCSI_RX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_2\r
+SCSI_RX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
+SCSI_RX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
+\r
+/* SCSI_TX_DMA */\r
+SCSI_TX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0\r
+SCSI_TX_DMA__DRQ_NUMBER EQU 1\r
+SCSI_TX_DMA__NUMBEROF_TDS EQU 0\r
+SCSI_TX_DMA__PRIORITY EQU 2\r
+SCSI_TX_DMA__TERMIN_EN EQU 0\r
+SCSI_TX_DMA__TERMIN_SEL EQU 0\r
+SCSI_TX_DMA__TERMOUT0_EN EQU 1\r
+SCSI_TX_DMA__TERMOUT0_SEL EQU 1\r
+SCSI_TX_DMA__TERMOUT1_EN EQU 0\r
+SCSI_TX_DMA__TERMOUT1_SEL EQU 0\r
+SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
+SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
+SCSI_TX_DMA_COMPLETE__INTC_MASK EQU 0x10\r
+SCSI_TX_DMA_COMPLETE__INTC_NUMBER EQU 4\r
+SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7\r
+SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_4\r
+SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
+SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
+\r
+/* SD_Data_Clk */\r
+SD_Data_Clk__CFG0 EQU CYREG_CLKDIST_DCFG0_CFG0\r
+SD_Data_Clk__CFG1 EQU CYREG_CLKDIST_DCFG0_CFG1\r
+SD_Data_Clk__CFG2 EQU CYREG_CLKDIST_DCFG0_CFG2\r
+SD_Data_Clk__CFG2_SRC_SEL_MASK EQU 0x07\r
+SD_Data_Clk__INDEX EQU 0x00\r
+SD_Data_Clk__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2\r
+SD_Data_Clk__PM_ACT_MSK EQU 0x01\r
+SD_Data_Clk__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2\r
+SD_Data_Clk__PM_STBY_MSK EQU 0x01\r
+\r
/* timer_clock */\r
timer_clock__CFG0 EQU CYREG_CLKDIST_DCFG2_CFG0\r
timer_clock__CFG1 EQU CYREG_CLKDIST_DCFG2_CFG1\r
timer_clock__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2\r
timer_clock__PM_STBY_MSK EQU 0x04\r
\r
+/* SCSI_RST_ISR */\r
+SCSI_RST_ISR__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
+SCSI_RST_ISR__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
+SCSI_RST_ISR__INTC_MASK EQU 0x02\r
+SCSI_RST_ISR__INTC_NUMBER EQU 1\r
+SCSI_RST_ISR__INTC_PRIOR_NUM EQU 7\r
+SCSI_RST_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_1\r
+SCSI_RST_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
+SCSI_RST_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
+\r
+/* SCSI_SEL_ISR */\r
+SCSI_SEL_ISR__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
+SCSI_SEL_ISR__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
+SCSI_SEL_ISR__INTC_MASK EQU 0x08\r
+SCSI_SEL_ISR__INTC_NUMBER EQU 3\r
+SCSI_SEL_ISR__INTC_PRIOR_NUM EQU 7\r
+SCSI_SEL_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_3\r
+SCSI_SEL_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
+SCSI_SEL_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
+\r
+/* SCSI_Filtered */\r
+SCSI_Filtered_sts_sts_reg__0__MASK EQU 0x01\r
+SCSI_Filtered_sts_sts_reg__0__POS EQU 0\r
+SCSI_Filtered_sts_sts_reg__1__MASK EQU 0x02\r
+SCSI_Filtered_sts_sts_reg__1__POS EQU 1\r
+SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL\r
+SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB02_03_ST\r
+SCSI_Filtered_sts_sts_reg__2__MASK EQU 0x04\r
+SCSI_Filtered_sts_sts_reg__2__POS EQU 2\r
+SCSI_Filtered_sts_sts_reg__3__MASK EQU 0x08\r
+SCSI_Filtered_sts_sts_reg__3__POS EQU 3\r
+SCSI_Filtered_sts_sts_reg__4__MASK EQU 0x10\r
+SCSI_Filtered_sts_sts_reg__4__POS EQU 4\r
+SCSI_Filtered_sts_sts_reg__MASK EQU 0x1F\r
+SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB02_MSK\r
+SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL\r
+SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB02_ST\r
+\r
+/* SCSI_CTL_PHASE */\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS EQU 0\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK EQU 0x02\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS EQU 1\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB05_06_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB05_06_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB05_06_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB05_06_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK EQU 0x04\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS EQU 2\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB05_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB05_ST_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB05_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB05_ST_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__MASK EQU 0x07\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB05_MSK\r
+\r
+/* SCSI_Glitch_Ctl */\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS EQU 0\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB07_08_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB07_08_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB07_08_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB07_08_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB07_08_MSK\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB07_08_MSK\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB07_08_MSK\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB07_08_MSK\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB07_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB07_ST_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB07_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB07_ST_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK EQU 0x01\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB07_MSK\r
+\r
+/* SCSI_Parity_Error */\r
+SCSI_Parity_Error_sts_sts_reg__0__MASK EQU 0x01\r
+SCSI_Parity_Error_sts_sts_reg__0__POS EQU 0\r
+SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB01_02_ACTL\r
+SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB01_02_ST\r
+SCSI_Parity_Error_sts_sts_reg__MASK EQU 0x01\r
+SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB01_MSK\r
+SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB01_ACTL\r
+SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB01_ST\r
+\r
/* Miscellaneous */\r
BCLK__BUS_CLK__HZ EQU 50000000\r
BCLK__BUS_CLK__KHZ EQU 50000\r
BCLK__BUS_CLK__MHZ EQU 50\r
CYDEV_CHIP_DIE_LEOPARD EQU 1\r
-CYDEV_CHIP_DIE_PSOC4A EQU 16\r
+CYDEV_CHIP_DIE_PSOC4A EQU 18\r
CYDEV_CHIP_DIE_PSOC5LP EQU 2\r
CYDEV_CHIP_DIE_PSOC5TM EQU 3\r
CYDEV_CHIP_DIE_TMA4 EQU 4\r
CYDEV_CHIP_FAMILY_USED EQU CYDEV_CHIP_FAMILY_PSOC5\r
CYDEV_CHIP_JTAG_ID EQU 0x2E133069\r
CYDEV_CHIP_MEMBER_3A EQU 1\r
-CYDEV_CHIP_MEMBER_4A EQU 16\r
-CYDEV_CHIP_MEMBER_4D EQU 12\r
+CYDEV_CHIP_MEMBER_4A EQU 18\r
+CYDEV_CHIP_MEMBER_4D EQU 13\r
CYDEV_CHIP_MEMBER_4E EQU 6\r
-CYDEV_CHIP_MEMBER_4F EQU 17\r
+CYDEV_CHIP_MEMBER_4F EQU 19\r
CYDEV_CHIP_MEMBER_4G EQU 4\r
-CYDEV_CHIP_MEMBER_4H EQU 15\r
-CYDEV_CHIP_MEMBER_4I EQU 21\r
-CYDEV_CHIP_MEMBER_4J EQU 13\r
-CYDEV_CHIP_MEMBER_4K EQU 14\r
-CYDEV_CHIP_MEMBER_4L EQU 20\r
-CYDEV_CHIP_MEMBER_4M EQU 19\r
-CYDEV_CHIP_MEMBER_4N EQU 9\r
+CYDEV_CHIP_MEMBER_4H EQU 17\r
+CYDEV_CHIP_MEMBER_4I EQU 23\r
+CYDEV_CHIP_MEMBER_4J EQU 14\r
+CYDEV_CHIP_MEMBER_4K EQU 15\r
+CYDEV_CHIP_MEMBER_4L EQU 22\r
+CYDEV_CHIP_MEMBER_4M EQU 21\r
+CYDEV_CHIP_MEMBER_4N EQU 10\r
CYDEV_CHIP_MEMBER_4O EQU 7\r
-CYDEV_CHIP_MEMBER_4P EQU 18\r
-CYDEV_CHIP_MEMBER_4Q EQU 11\r
+CYDEV_CHIP_MEMBER_4P EQU 20\r
+CYDEV_CHIP_MEMBER_4Q EQU 12\r
CYDEV_CHIP_MEMBER_4R EQU 8\r
-CYDEV_CHIP_MEMBER_4S EQU 10\r
+CYDEV_CHIP_MEMBER_4S EQU 11\r
+CYDEV_CHIP_MEMBER_4T EQU 9\r
CYDEV_CHIP_MEMBER_4U EQU 5\r
+CYDEV_CHIP_MEMBER_4V EQU 16\r
CYDEV_CHIP_MEMBER_5A EQU 3\r
CYDEV_CHIP_MEMBER_5B EQU 2\r
-CYDEV_CHIP_MEMBER_6A EQU 22\r
-CYDEV_CHIP_MEMBER_FM3 EQU 26\r
-CYDEV_CHIP_MEMBER_FM4 EQU 27\r
-CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE1 EQU 23\r
-CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE2 EQU 24\r
-CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE3 EQU 25\r
+CYDEV_CHIP_MEMBER_6A EQU 24\r
+CYDEV_CHIP_MEMBER_FM3 EQU 28\r
+CYDEV_CHIP_MEMBER_FM4 EQU 29\r
+CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE1 EQU 25\r
+CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE2 EQU 26\r
+CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE3 EQU 27\r
CYDEV_CHIP_MEMBER_UNKNOWN EQU 0\r
CYDEV_CHIP_MEMBER_USED EQU CYDEV_CHIP_MEMBER_5B\r
CYDEV_CHIP_DIE_EXPECT EQU CYDEV_CHIP_MEMBER_USED\r
CYDEV_CHIP_REVISION_4A_ES0 EQU 17\r
CYDEV_CHIP_REVISION_4A_PRODUCTION EQU 17\r
CYDEV_CHIP_REVISION_4D_PRODUCTION EQU 0\r
+CYDEV_CHIP_REVISION_4E_CCG2_NO_USBPD EQU 0\r
CYDEV_CHIP_REVISION_4E_PRODUCTION EQU 0\r
CYDEV_CHIP_REVISION_4F_PRODUCTION EQU 0\r
CYDEV_CHIP_REVISION_4F_PRODUCTION_256DMA EQU 0\r
CYDEV_CHIP_REVISION_4Q_PRODUCTION EQU 0\r
CYDEV_CHIP_REVISION_4R_PRODUCTION EQU 0\r
CYDEV_CHIP_REVISION_4S_PRODUCTION EQU 0\r
+CYDEV_CHIP_REVISION_4T_PRODUCTION EQU 0\r
CYDEV_CHIP_REVISION_4U_PRODUCTION EQU 0\r
+CYDEV_CHIP_REVISION_4V_PRODUCTION EQU 0\r
CYDEV_CHIP_REVISION_5A_ES0 EQU 0\r
CYDEV_CHIP_REVISION_5A_ES1 EQU 1\r
CYDEV_CHIP_REVISION_5A_PRODUCTION EQU 1\r
CYDEV_CHIP_REVISION_5B_ES0 EQU 0\r
CYDEV_CHIP_REVISION_5B_PRODUCTION EQU 0\r
-CYDEV_CHIP_REVISION_6A_NO_UDB EQU 0\r
-CYDEV_CHIP_REVISION_6A_PRODUCTION EQU 0\r
+CYDEV_CHIP_REVISION_6A_ES EQU 17\r
+CYDEV_CHIP_REVISION_6A_NO_UDB EQU 33\r
+CYDEV_CHIP_REVISION_6A_PRODUCTION EQU 33\r
CYDEV_CHIP_REVISION_FM3_PRODUCTION EQU 0\r
CYDEV_CHIP_REVISION_FM4_PRODUCTION EQU 0\r
CYDEV_CHIP_REVISION_PDL_FM0P_TYPE1_PRODUCTION EQU 0\r
;\r
; File Name: cyfitterrv.inc\r
; \r
-; PSoC Creator 4.1\r
+; PSoC Creator 4.2\r
;\r
; Description:\r
; \r
;\r
;-------------------------------------------------------------------------------\r
-; Copyright (c) 2007-2017 Cypress Semiconductor. All rights reserved.\r
+; Copyright (c) 2007-2018 Cypress Semiconductor. All rights reserved.\r
; You may use this file only in accordance with the license, terms, conditions, \r
; disclaimers, and limitations in the end user license agreement accompanying \r
; the software package with which this file was provided.\r
GET cydevicerv.inc\r
GET cydevicerv_trm.inc\r
\r
-; Debug_Timer_Interrupt\r
-Debug_Timer_Interrupt__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
-Debug_Timer_Interrupt__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
-Debug_Timer_Interrupt__INTC_MASK EQU 0x01\r
-Debug_Timer_Interrupt__INTC_NUMBER EQU 0\r
-Debug_Timer_Interrupt__INTC_PRIOR_NUM EQU 7\r
-Debug_Timer_Interrupt__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_0\r
-Debug_Timer_Interrupt__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
-Debug_Timer_Interrupt__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
-\r
-; Debug_Timer_TimerHW\r
-Debug_Timer_TimerHW__CAP0 EQU CYREG_TMR0_CAP0\r
-Debug_Timer_TimerHW__CAP1 EQU CYREG_TMR0_CAP1\r
-Debug_Timer_TimerHW__CFG0 EQU CYREG_TMR0_CFG0\r
-Debug_Timer_TimerHW__CFG1 EQU CYREG_TMR0_CFG1\r
-Debug_Timer_TimerHW__CFG2 EQU CYREG_TMR0_CFG2\r
-Debug_Timer_TimerHW__CNT_CMP0 EQU CYREG_TMR0_CNT_CMP0\r
-Debug_Timer_TimerHW__CNT_CMP1 EQU CYREG_TMR0_CNT_CMP1\r
-Debug_Timer_TimerHW__PER0 EQU CYREG_TMR0_PER0\r
-Debug_Timer_TimerHW__PER1 EQU CYREG_TMR0_PER1\r
-Debug_Timer_TimerHW__PM_ACT_CFG EQU CYREG_PM_ACT_CFG3\r
-Debug_Timer_TimerHW__PM_ACT_MSK EQU 0x01\r
-Debug_Timer_TimerHW__PM_STBY_CFG EQU CYREG_PM_STBY_CFG3\r
-Debug_Timer_TimerHW__PM_STBY_MSK EQU 0x01\r
-Debug_Timer_TimerHW__RT0 EQU CYREG_TMR0_RT0\r
-Debug_Timer_TimerHW__RT1 EQU CYREG_TMR0_RT1\r
-Debug_Timer_TimerHW__SR0 EQU CYREG_TMR0_SR0\r
-\r
; LED1\r
LED1__0__INTTYPE EQU CYREG_PICU12_INTTYPE3\r
LED1__0__MASK EQU 0x08\r
LED1__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ\r
LED1__SLW EQU CYREG_PRT12_SLW\r
\r
-; SCSI_CLK\r
-SCSI_CLK__CFG0 EQU CYREG_CLKDIST_DCFG1_CFG0\r
-SCSI_CLK__CFG1 EQU CYREG_CLKDIST_DCFG1_CFG1\r
-SCSI_CLK__CFG2 EQU CYREG_CLKDIST_DCFG1_CFG2\r
-SCSI_CLK__CFG2_SRC_SEL_MASK EQU 0x07\r
-SCSI_CLK__INDEX EQU 0x01\r
-SCSI_CLK__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2\r
-SCSI_CLK__PM_ACT_MSK EQU 0x02\r
-SCSI_CLK__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2\r
-SCSI_CLK__PM_STBY_MSK EQU 0x02\r
-\r
-; SCSI_CTL_PHASE\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS EQU 0\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK EQU 0x02\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS EQU 1\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB05_06_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB05_06_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB05_06_MSK\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB05_06_MSK\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK EQU 0x04\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS EQU 2\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB05_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB05_ST_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB05_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB05_ST_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__MASK EQU 0x07\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB05_MSK\r
-\r
-; SCSI_Filtered\r
-SCSI_Filtered_sts_sts_reg__0__MASK EQU 0x01\r
-SCSI_Filtered_sts_sts_reg__0__POS EQU 0\r
-SCSI_Filtered_sts_sts_reg__1__MASK EQU 0x02\r
-SCSI_Filtered_sts_sts_reg__1__POS EQU 1\r
-SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL\r
-SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB02_03_ST\r
-SCSI_Filtered_sts_sts_reg__2__MASK EQU 0x04\r
-SCSI_Filtered_sts_sts_reg__2__POS EQU 2\r
-SCSI_Filtered_sts_sts_reg__3__MASK EQU 0x08\r
-SCSI_Filtered_sts_sts_reg__3__POS EQU 3\r
-SCSI_Filtered_sts_sts_reg__4__MASK EQU 0x10\r
-SCSI_Filtered_sts_sts_reg__4__POS EQU 4\r
-SCSI_Filtered_sts_sts_reg__MASK EQU 0x1F\r
-SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB02_MSK\r
-SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL\r
-SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB02_ST\r
+; SD_CD\r
+SD_CD__0__INTTYPE EQU CYREG_PICU3_INTTYPE6\r
+SD_CD__0__MASK EQU 0x40\r
+SD_CD__0__PC EQU CYREG_PRT3_PC6\r
+SD_CD__0__PORT EQU 3\r
+SD_CD__0__SHIFT EQU 6\r
+SD_CD__AG EQU CYREG_PRT3_AG\r
+SD_CD__AMUX EQU CYREG_PRT3_AMUX\r
+SD_CD__BIE EQU CYREG_PRT3_BIE\r
+SD_CD__BIT_MASK EQU CYREG_PRT3_BIT_MASK\r
+SD_CD__BYP EQU CYREG_PRT3_BYP\r
+SD_CD__CTL EQU CYREG_PRT3_CTL\r
+SD_CD__DM0 EQU CYREG_PRT3_DM0\r
+SD_CD__DM1 EQU CYREG_PRT3_DM1\r
+SD_CD__DM2 EQU CYREG_PRT3_DM2\r
+SD_CD__DR EQU CYREG_PRT3_DR\r
+SD_CD__INP_DIS EQU CYREG_PRT3_INP_DIS\r
+SD_CD__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE\r
+SD_CD__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG\r
+SD_CD__LCD_EN EQU CYREG_PRT3_LCD_EN\r
+SD_CD__MASK EQU 0x40\r
+SD_CD__PORT EQU 3\r
+SD_CD__PRT EQU CYREG_PRT3_PRT\r
+SD_CD__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL\r
+SD_CD__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN\r
+SD_CD__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0\r
+SD_CD__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1\r
+SD_CD__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0\r
+SD_CD__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1\r
+SD_CD__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT\r
+SD_CD__PS EQU CYREG_PRT3_PS\r
+SD_CD__SHIFT EQU 6\r
+SD_CD__SLW EQU CYREG_PRT3_SLW\r
\r
-; SCSI_Glitch_Ctl\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS EQU 0\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB07_08_CTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB07_08_CTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB07_08_CTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB07_08_CTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB07_08_MSK\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB07_08_MSK\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB07_08_MSK\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB07_08_MSK\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB07_CTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB07_ST_CTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB07_CTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB07_ST_CTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK EQU 0x01\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB07_MSK\r
-\r
-; SCSI_In\r
-SCSI_In__0__AG EQU CYREG_PRT2_AG\r
-SCSI_In__0__AMUX EQU CYREG_PRT2_AMUX\r
-SCSI_In__0__BIE EQU CYREG_PRT2_BIE\r
-SCSI_In__0__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
-SCSI_In__0__BYP EQU CYREG_PRT2_BYP\r
-SCSI_In__0__CTL EQU CYREG_PRT2_CTL\r
-SCSI_In__0__DM0 EQU CYREG_PRT2_DM0\r
-SCSI_In__0__DM1 EQU CYREG_PRT2_DM1\r
-SCSI_In__0__DM2 EQU CYREG_PRT2_DM2\r
-SCSI_In__0__DR EQU CYREG_PRT2_DR\r
-SCSI_In__0__INP_DIS EQU CYREG_PRT2_INP_DIS\r
-SCSI_In__0__INTTYPE EQU CYREG_PICU2_INTTYPE0\r
-SCSI_In__0__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
-SCSI_In__0__LCD_EN EQU CYREG_PRT2_LCD_EN\r
-SCSI_In__0__MASK EQU 0x01\r
-SCSI_In__0__PC EQU CYREG_PRT2_PC0\r
-SCSI_In__0__PORT EQU 2\r
-SCSI_In__0__PRT EQU CYREG_PRT2_PRT\r
-SCSI_In__0__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
-SCSI_In__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
-SCSI_In__0__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
-SCSI_In__0__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
-SCSI_In__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
-SCSI_In__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
-SCSI_In__0__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
-SCSI_In__0__PS EQU CYREG_PRT2_PS\r
-SCSI_In__0__SHIFT EQU 0\r
-SCSI_In__0__SLW EQU CYREG_PRT2_SLW\r
-SCSI_In__1__AG EQU CYREG_PRT6_AG\r
-SCSI_In__1__AMUX EQU CYREG_PRT6_AMUX\r
-SCSI_In__1__BIE EQU CYREG_PRT6_BIE\r
-SCSI_In__1__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
-SCSI_In__1__BYP EQU CYREG_PRT6_BYP\r
-SCSI_In__1__CTL EQU CYREG_PRT6_CTL\r
-SCSI_In__1__DM0 EQU CYREG_PRT6_DM0\r
-SCSI_In__1__DM1 EQU CYREG_PRT6_DM1\r
-SCSI_In__1__DM2 EQU CYREG_PRT6_DM2\r
-SCSI_In__1__DR EQU CYREG_PRT6_DR\r
-SCSI_In__1__INP_DIS EQU CYREG_PRT6_INP_DIS\r
-SCSI_In__1__INTTYPE EQU CYREG_PICU6_INTTYPE7\r
-SCSI_In__1__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
-SCSI_In__1__LCD_EN EQU CYREG_PRT6_LCD_EN\r
-SCSI_In__1__MASK EQU 0x80\r
-SCSI_In__1__PC EQU CYREG_PRT6_PC7\r
-SCSI_In__1__PORT EQU 6\r
-SCSI_In__1__PRT EQU CYREG_PRT6_PRT\r
-SCSI_In__1__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
-SCSI_In__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
-SCSI_In__1__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
-SCSI_In__1__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
-SCSI_In__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
-SCSI_In__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
-SCSI_In__1__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
-SCSI_In__1__PS EQU CYREG_PRT6_PS\r
-SCSI_In__1__SHIFT EQU 7\r
-SCSI_In__1__SLW EQU CYREG_PRT6_SLW\r
-SCSI_In__2__AG EQU CYREG_PRT5_AG\r
-SCSI_In__2__AMUX EQU CYREG_PRT5_AMUX\r
-SCSI_In__2__BIE EQU CYREG_PRT5_BIE\r
-SCSI_In__2__BIT_MASK EQU CYREG_PRT5_BIT_MASK\r
-SCSI_In__2__BYP EQU CYREG_PRT5_BYP\r
-SCSI_In__2__CTL EQU CYREG_PRT5_CTL\r
-SCSI_In__2__DM0 EQU CYREG_PRT5_DM0\r
-SCSI_In__2__DM1 EQU CYREG_PRT5_DM1\r
-SCSI_In__2__DM2 EQU CYREG_PRT5_DM2\r
-SCSI_In__2__DR EQU CYREG_PRT5_DR\r
-SCSI_In__2__INP_DIS EQU CYREG_PRT5_INP_DIS\r
-SCSI_In__2__INTTYPE EQU CYREG_PICU5_INTTYPE1\r
-SCSI_In__2__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG\r
-SCSI_In__2__LCD_EN EQU CYREG_PRT5_LCD_EN\r
-SCSI_In__2__MASK EQU 0x02\r
-SCSI_In__2__PC EQU CYREG_PRT5_PC1\r
-SCSI_In__2__PORT EQU 5\r
-SCSI_In__2__PRT EQU CYREG_PRT5_PRT\r
-SCSI_In__2__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL\r
-SCSI_In__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN\r
-SCSI_In__2__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0\r
-SCSI_In__2__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1\r
-SCSI_In__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0\r
-SCSI_In__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1\r
-SCSI_In__2__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT\r
-SCSI_In__2__PS EQU CYREG_PRT5_PS\r
-SCSI_In__2__SHIFT EQU 1\r
-SCSI_In__2__SLW EQU CYREG_PRT5_SLW\r
-SCSI_In__3__AG EQU CYREG_PRT5_AG\r
-SCSI_In__3__AMUX EQU CYREG_PRT5_AMUX\r
-SCSI_In__3__BIE EQU CYREG_PRT5_BIE\r
-SCSI_In__3__BIT_MASK EQU CYREG_PRT5_BIT_MASK\r
-SCSI_In__3__BYP EQU CYREG_PRT5_BYP\r
-SCSI_In__3__CTL EQU CYREG_PRT5_CTL\r
-SCSI_In__3__DM0 EQU CYREG_PRT5_DM0\r
-SCSI_In__3__DM1 EQU CYREG_PRT5_DM1\r
-SCSI_In__3__DM2 EQU CYREG_PRT5_DM2\r
-SCSI_In__3__DR EQU CYREG_PRT5_DR\r
-SCSI_In__3__INP_DIS EQU CYREG_PRT5_INP_DIS\r
-SCSI_In__3__INTTYPE EQU CYREG_PICU5_INTTYPE2\r
-SCSI_In__3__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG\r
-SCSI_In__3__LCD_EN EQU CYREG_PRT5_LCD_EN\r
-SCSI_In__3__MASK EQU 0x04\r
-SCSI_In__3__PC EQU CYREG_PRT5_PC2\r
-SCSI_In__3__PORT EQU 5\r
-SCSI_In__3__PRT EQU CYREG_PRT5_PRT\r
-SCSI_In__3__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL\r
-SCSI_In__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN\r
-SCSI_In__3__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0\r
-SCSI_In__3__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1\r
-SCSI_In__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0\r
-SCSI_In__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1\r
-SCSI_In__3__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT\r
-SCSI_In__3__PS EQU CYREG_PRT5_PS\r
-SCSI_In__3__SHIFT EQU 2\r
-SCSI_In__3__SLW EQU CYREG_PRT5_SLW\r
-SCSI_In__4__AG EQU CYREG_PRT5_AG\r
-SCSI_In__4__AMUX EQU CYREG_PRT5_AMUX\r
-SCSI_In__4__BIE EQU CYREG_PRT5_BIE\r
-SCSI_In__4__BIT_MASK EQU CYREG_PRT5_BIT_MASK\r
-SCSI_In__4__BYP EQU CYREG_PRT5_BYP\r
-SCSI_In__4__CTL EQU CYREG_PRT5_CTL\r
-SCSI_In__4__DM0 EQU CYREG_PRT5_DM0\r
-SCSI_In__4__DM1 EQU CYREG_PRT5_DM1\r
-SCSI_In__4__DM2 EQU CYREG_PRT5_DM2\r
-SCSI_In__4__DR EQU CYREG_PRT5_DR\r
-SCSI_In__4__INP_DIS EQU CYREG_PRT5_INP_DIS\r
-SCSI_In__4__INTTYPE EQU CYREG_PICU5_INTTYPE3\r
-SCSI_In__4__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG\r
-SCSI_In__4__LCD_EN EQU CYREG_PRT5_LCD_EN\r
-SCSI_In__4__MASK EQU 0x08\r
-SCSI_In__4__PC EQU CYREG_PRT5_PC3\r
-SCSI_In__4__PORT EQU 5\r
-SCSI_In__4__PRT EQU CYREG_PRT5_PRT\r
-SCSI_In__4__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL\r
-SCSI_In__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN\r
-SCSI_In__4__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0\r
-SCSI_In__4__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1\r
-SCSI_In__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0\r
-SCSI_In__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1\r
-SCSI_In__4__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT\r
-SCSI_In__4__PS EQU CYREG_PRT5_PS\r
-SCSI_In__4__SHIFT EQU 3\r
-SCSI_In__4__SLW EQU CYREG_PRT5_SLW\r
-SCSI_In__CD__AG EQU CYREG_PRT5_AG\r
-SCSI_In__CD__AMUX EQU CYREG_PRT5_AMUX\r
-SCSI_In__CD__BIE EQU CYREG_PRT5_BIE\r
-SCSI_In__CD__BIT_MASK EQU CYREG_PRT5_BIT_MASK\r
-SCSI_In__CD__BYP EQU CYREG_PRT5_BYP\r
-SCSI_In__CD__CTL EQU CYREG_PRT5_CTL\r
-SCSI_In__CD__DM0 EQU CYREG_PRT5_DM0\r
-SCSI_In__CD__DM1 EQU CYREG_PRT5_DM1\r
-SCSI_In__CD__DM2 EQU CYREG_PRT5_DM2\r
-SCSI_In__CD__DR EQU CYREG_PRT5_DR\r
-SCSI_In__CD__INP_DIS EQU CYREG_PRT5_INP_DIS\r
-SCSI_In__CD__INTTYPE EQU CYREG_PICU5_INTTYPE1\r
-SCSI_In__CD__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG\r
-SCSI_In__CD__LCD_EN EQU CYREG_PRT5_LCD_EN\r
-SCSI_In__CD__MASK EQU 0x02\r
-SCSI_In__CD__PC EQU CYREG_PRT5_PC1\r
-SCSI_In__CD__PORT EQU 5\r
-SCSI_In__CD__PRT EQU CYREG_PRT5_PRT\r
-SCSI_In__CD__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL\r
-SCSI_In__CD__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN\r
-SCSI_In__CD__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0\r
-SCSI_In__CD__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1\r
-SCSI_In__CD__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0\r
-SCSI_In__CD__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1\r
-SCSI_In__CD__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT\r
-SCSI_In__CD__PS EQU CYREG_PRT5_PS\r
-SCSI_In__CD__SHIFT EQU 1\r
-SCSI_In__CD__SLW EQU CYREG_PRT5_SLW\r
-SCSI_In__DBP__AG EQU CYREG_PRT2_AG\r
-SCSI_In__DBP__AMUX EQU CYREG_PRT2_AMUX\r
-SCSI_In__DBP__BIE EQU CYREG_PRT2_BIE\r
-SCSI_In__DBP__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
-SCSI_In__DBP__BYP EQU CYREG_PRT2_BYP\r
-SCSI_In__DBP__CTL EQU CYREG_PRT2_CTL\r
-SCSI_In__DBP__DM0 EQU CYREG_PRT2_DM0\r
-SCSI_In__DBP__DM1 EQU CYREG_PRT2_DM1\r
-SCSI_In__DBP__DM2 EQU CYREG_PRT2_DM2\r
-SCSI_In__DBP__DR EQU CYREG_PRT2_DR\r
-SCSI_In__DBP__INP_DIS EQU CYREG_PRT2_INP_DIS\r
-SCSI_In__DBP__INTTYPE EQU CYREG_PICU2_INTTYPE0\r
-SCSI_In__DBP__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
-SCSI_In__DBP__LCD_EN EQU CYREG_PRT2_LCD_EN\r
-SCSI_In__DBP__MASK EQU 0x01\r
-SCSI_In__DBP__PC EQU CYREG_PRT2_PC0\r
-SCSI_In__DBP__PORT EQU 2\r
-SCSI_In__DBP__PRT EQU CYREG_PRT2_PRT\r
-SCSI_In__DBP__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
-SCSI_In__DBP__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
-SCSI_In__DBP__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
-SCSI_In__DBP__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
-SCSI_In__DBP__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
-SCSI_In__DBP__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
-SCSI_In__DBP__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
-SCSI_In__DBP__PS EQU CYREG_PRT2_PS\r
-SCSI_In__DBP__SHIFT EQU 0\r
-SCSI_In__DBP__SLW EQU CYREG_PRT2_SLW\r
-SCSI_In__IO__AG EQU CYREG_PRT5_AG\r
-SCSI_In__IO__AMUX EQU CYREG_PRT5_AMUX\r
-SCSI_In__IO__BIE EQU CYREG_PRT5_BIE\r
-SCSI_In__IO__BIT_MASK EQU CYREG_PRT5_BIT_MASK\r
-SCSI_In__IO__BYP EQU CYREG_PRT5_BYP\r
-SCSI_In__IO__CTL EQU CYREG_PRT5_CTL\r
-SCSI_In__IO__DM0 EQU CYREG_PRT5_DM0\r
-SCSI_In__IO__DM1 EQU CYREG_PRT5_DM1\r
-SCSI_In__IO__DM2 EQU CYREG_PRT5_DM2\r
-SCSI_In__IO__DR EQU CYREG_PRT5_DR\r
-SCSI_In__IO__INP_DIS EQU CYREG_PRT5_INP_DIS\r
-SCSI_In__IO__INTTYPE EQU CYREG_PICU5_INTTYPE3\r
-SCSI_In__IO__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG\r
-SCSI_In__IO__LCD_EN EQU CYREG_PRT5_LCD_EN\r
-SCSI_In__IO__MASK EQU 0x08\r
-SCSI_In__IO__PC EQU CYREG_PRT5_PC3\r
-SCSI_In__IO__PORT EQU 5\r
-SCSI_In__IO__PRT EQU CYREG_PRT5_PRT\r
-SCSI_In__IO__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL\r
-SCSI_In__IO__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN\r
-SCSI_In__IO__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0\r
-SCSI_In__IO__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1\r
-SCSI_In__IO__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0\r
-SCSI_In__IO__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1\r
-SCSI_In__IO__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT\r
-SCSI_In__IO__PS EQU CYREG_PRT5_PS\r
-SCSI_In__IO__SHIFT EQU 3\r
-SCSI_In__IO__SLW EQU CYREG_PRT5_SLW\r
-SCSI_In__MSG__AG EQU CYREG_PRT6_AG\r
-SCSI_In__MSG__AMUX EQU CYREG_PRT6_AMUX\r
-SCSI_In__MSG__BIE EQU CYREG_PRT6_BIE\r
-SCSI_In__MSG__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
-SCSI_In__MSG__BYP EQU CYREG_PRT6_BYP\r
-SCSI_In__MSG__CTL EQU CYREG_PRT6_CTL\r
-SCSI_In__MSG__DM0 EQU CYREG_PRT6_DM0\r
-SCSI_In__MSG__DM1 EQU CYREG_PRT6_DM1\r
-SCSI_In__MSG__DM2 EQU CYREG_PRT6_DM2\r
-SCSI_In__MSG__DR EQU CYREG_PRT6_DR\r
-SCSI_In__MSG__INP_DIS EQU CYREG_PRT6_INP_DIS\r
-SCSI_In__MSG__INTTYPE EQU CYREG_PICU6_INTTYPE7\r
-SCSI_In__MSG__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
-SCSI_In__MSG__LCD_EN EQU CYREG_PRT6_LCD_EN\r
-SCSI_In__MSG__MASK EQU 0x80\r
-SCSI_In__MSG__PC EQU CYREG_PRT6_PC7\r
-SCSI_In__MSG__PORT EQU 6\r
-SCSI_In__MSG__PRT EQU CYREG_PRT6_PRT\r
-SCSI_In__MSG__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
-SCSI_In__MSG__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
-SCSI_In__MSG__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
-SCSI_In__MSG__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
-SCSI_In__MSG__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
-SCSI_In__MSG__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
-SCSI_In__MSG__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
-SCSI_In__MSG__PS EQU CYREG_PRT6_PS\r
-SCSI_In__MSG__SHIFT EQU 7\r
-SCSI_In__MSG__SLW EQU CYREG_PRT6_SLW\r
-SCSI_In__REQ__AG EQU CYREG_PRT5_AG\r
-SCSI_In__REQ__AMUX EQU CYREG_PRT5_AMUX\r
-SCSI_In__REQ__BIE EQU CYREG_PRT5_BIE\r
-SCSI_In__REQ__BIT_MASK EQU CYREG_PRT5_BIT_MASK\r
-SCSI_In__REQ__BYP EQU CYREG_PRT5_BYP\r
-SCSI_In__REQ__CTL EQU CYREG_PRT5_CTL\r
-SCSI_In__REQ__DM0 EQU CYREG_PRT5_DM0\r
-SCSI_In__REQ__DM1 EQU CYREG_PRT5_DM1\r
-SCSI_In__REQ__DM2 EQU CYREG_PRT5_DM2\r
-SCSI_In__REQ__DR EQU CYREG_PRT5_DR\r
-SCSI_In__REQ__INP_DIS EQU CYREG_PRT5_INP_DIS\r
-SCSI_In__REQ__INTTYPE EQU CYREG_PICU5_INTTYPE2\r
-SCSI_In__REQ__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG\r
-SCSI_In__REQ__LCD_EN EQU CYREG_PRT5_LCD_EN\r
-SCSI_In__REQ__MASK EQU 0x04\r
-SCSI_In__REQ__PC EQU CYREG_PRT5_PC2\r
-SCSI_In__REQ__PORT EQU 5\r
-SCSI_In__REQ__PRT EQU CYREG_PRT5_PRT\r
-SCSI_In__REQ__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL\r
-SCSI_In__REQ__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN\r
-SCSI_In__REQ__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0\r
-SCSI_In__REQ__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1\r
-SCSI_In__REQ__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0\r
-SCSI_In__REQ__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1\r
-SCSI_In__REQ__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT\r
-SCSI_In__REQ__PS EQU CYREG_PRT5_PS\r
-SCSI_In__REQ__SHIFT EQU 2\r
-SCSI_In__REQ__SLW EQU CYREG_PRT5_SLW\r
-SCSI_In_DBx__0__AG EQU CYREG_PRT12_AG\r
-SCSI_In_DBx__0__BIE EQU CYREG_PRT12_BIE\r
-SCSI_In_DBx__0__BIT_MASK EQU CYREG_PRT12_BIT_MASK\r
-SCSI_In_DBx__0__BYP EQU CYREG_PRT12_BYP\r
-SCSI_In_DBx__0__DM0 EQU CYREG_PRT12_DM0\r
-SCSI_In_DBx__0__DM1 EQU CYREG_PRT12_DM1\r
-SCSI_In_DBx__0__DM2 EQU CYREG_PRT12_DM2\r
-SCSI_In_DBx__0__DR EQU CYREG_PRT12_DR\r
-SCSI_In_DBx__0__INP_DIS EQU CYREG_PRT12_INP_DIS\r
-SCSI_In_DBx__0__INTTYPE EQU CYREG_PICU12_INTTYPE4\r
-SCSI_In_DBx__0__MASK EQU 0x10\r
-SCSI_In_DBx__0__PC EQU CYREG_PRT12_PC4\r
-SCSI_In_DBx__0__PORT EQU 12\r
-SCSI_In_DBx__0__PRT EQU CYREG_PRT12_PRT\r
-SCSI_In_DBx__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN\r
-SCSI_In_DBx__0__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0\r
-SCSI_In_DBx__0__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1\r
-SCSI_In_DBx__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0\r
-SCSI_In_DBx__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1\r
-SCSI_In_DBx__0__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT\r
-SCSI_In_DBx__0__PS EQU CYREG_PRT12_PS\r
-SCSI_In_DBx__0__SHIFT EQU 4\r
-SCSI_In_DBx__0__SIO_CFG EQU CYREG_PRT12_SIO_CFG\r
-SCSI_In_DBx__0__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF\r
-SCSI_In_DBx__0__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN\r
-SCSI_In_DBx__0__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ\r
-SCSI_In_DBx__0__SLW EQU CYREG_PRT12_SLW\r
-SCSI_In_DBx__1__AG EQU CYREG_PRT2_AG\r
-SCSI_In_DBx__1__AMUX EQU CYREG_PRT2_AMUX\r
-SCSI_In_DBx__1__BIE EQU CYREG_PRT2_BIE\r
-SCSI_In_DBx__1__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
-SCSI_In_DBx__1__BYP EQU CYREG_PRT2_BYP\r
-SCSI_In_DBx__1__CTL EQU CYREG_PRT2_CTL\r
-SCSI_In_DBx__1__DM0 EQU CYREG_PRT2_DM0\r
-SCSI_In_DBx__1__DM1 EQU CYREG_PRT2_DM1\r
-SCSI_In_DBx__1__DM2 EQU CYREG_PRT2_DM2\r
-SCSI_In_DBx__1__DR EQU CYREG_PRT2_DR\r
-SCSI_In_DBx__1__INP_DIS EQU CYREG_PRT2_INP_DIS\r
-SCSI_In_DBx__1__INTTYPE EQU CYREG_PICU2_INTTYPE7\r
-SCSI_In_DBx__1__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
-SCSI_In_DBx__1__LCD_EN EQU CYREG_PRT2_LCD_EN\r
-SCSI_In_DBx__1__MASK EQU 0x80\r
-SCSI_In_DBx__1__PC EQU CYREG_PRT2_PC7\r
-SCSI_In_DBx__1__PORT EQU 2\r
-SCSI_In_DBx__1__PRT EQU CYREG_PRT2_PRT\r
-SCSI_In_DBx__1__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
-SCSI_In_DBx__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
-SCSI_In_DBx__1__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
-SCSI_In_DBx__1__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
-SCSI_In_DBx__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
-SCSI_In_DBx__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
-SCSI_In_DBx__1__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
-SCSI_In_DBx__1__PS EQU CYREG_PRT2_PS\r
-SCSI_In_DBx__1__SHIFT EQU 7\r
-SCSI_In_DBx__1__SLW EQU CYREG_PRT2_SLW\r
-SCSI_In_DBx__2__AG EQU CYREG_PRT2_AG\r
-SCSI_In_DBx__2__AMUX EQU CYREG_PRT2_AMUX\r
-SCSI_In_DBx__2__BIE EQU CYREG_PRT2_BIE\r
-SCSI_In_DBx__2__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
-SCSI_In_DBx__2__BYP EQU CYREG_PRT2_BYP\r
-SCSI_In_DBx__2__CTL EQU CYREG_PRT2_CTL\r
-SCSI_In_DBx__2__DM0 EQU CYREG_PRT2_DM0\r
-SCSI_In_DBx__2__DM1 EQU CYREG_PRT2_DM1\r
-SCSI_In_DBx__2__DM2 EQU CYREG_PRT2_DM2\r
-SCSI_In_DBx__2__DR EQU CYREG_PRT2_DR\r
-SCSI_In_DBx__2__INP_DIS EQU CYREG_PRT2_INP_DIS\r
-SCSI_In_DBx__2__INTTYPE EQU CYREG_PICU2_INTTYPE6\r
-SCSI_In_DBx__2__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
-SCSI_In_DBx__2__LCD_EN EQU CYREG_PRT2_LCD_EN\r
-SCSI_In_DBx__2__MASK EQU 0x40\r
-SCSI_In_DBx__2__PC EQU CYREG_PRT2_PC6\r
-SCSI_In_DBx__2__PORT EQU 2\r
-SCSI_In_DBx__2__PRT EQU CYREG_PRT2_PRT\r
-SCSI_In_DBx__2__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
-SCSI_In_DBx__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
-SCSI_In_DBx__2__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
-SCSI_In_DBx__2__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
-SCSI_In_DBx__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
-SCSI_In_DBx__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
-SCSI_In_DBx__2__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
-SCSI_In_DBx__2__PS EQU CYREG_PRT2_PS\r
-SCSI_In_DBx__2__SHIFT EQU 6\r
-SCSI_In_DBx__2__SLW EQU CYREG_PRT2_SLW\r
-SCSI_In_DBx__3__AG EQU CYREG_PRT2_AG\r
-SCSI_In_DBx__3__AMUX EQU CYREG_PRT2_AMUX\r
-SCSI_In_DBx__3__BIE EQU CYREG_PRT2_BIE\r
-SCSI_In_DBx__3__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
-SCSI_In_DBx__3__BYP EQU CYREG_PRT2_BYP\r
-SCSI_In_DBx__3__CTL EQU CYREG_PRT2_CTL\r
-SCSI_In_DBx__3__DM0 EQU CYREG_PRT2_DM0\r
-SCSI_In_DBx__3__DM1 EQU CYREG_PRT2_DM1\r
-SCSI_In_DBx__3__DM2 EQU CYREG_PRT2_DM2\r
-SCSI_In_DBx__3__DR EQU CYREG_PRT2_DR\r
-SCSI_In_DBx__3__INP_DIS EQU CYREG_PRT2_INP_DIS\r
-SCSI_In_DBx__3__INTTYPE EQU CYREG_PICU2_INTTYPE5\r
-SCSI_In_DBx__3__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
-SCSI_In_DBx__3__LCD_EN EQU CYREG_PRT2_LCD_EN\r
-SCSI_In_DBx__3__MASK EQU 0x20\r
-SCSI_In_DBx__3__PC EQU CYREG_PRT2_PC5\r
-SCSI_In_DBx__3__PORT EQU 2\r
-SCSI_In_DBx__3__PRT EQU CYREG_PRT2_PRT\r
-SCSI_In_DBx__3__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
-SCSI_In_DBx__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
-SCSI_In_DBx__3__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
-SCSI_In_DBx__3__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
-SCSI_In_DBx__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
-SCSI_In_DBx__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
-SCSI_In_DBx__3__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
-SCSI_In_DBx__3__PS EQU CYREG_PRT2_PS\r
-SCSI_In_DBx__3__SHIFT EQU 5\r
-SCSI_In_DBx__3__SLW EQU CYREG_PRT2_SLW\r
-SCSI_In_DBx__4__AG EQU CYREG_PRT2_AG\r
-SCSI_In_DBx__4__AMUX EQU CYREG_PRT2_AMUX\r
-SCSI_In_DBx__4__BIE EQU CYREG_PRT2_BIE\r
-SCSI_In_DBx__4__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
-SCSI_In_DBx__4__BYP EQU CYREG_PRT2_BYP\r
-SCSI_In_DBx__4__CTL EQU CYREG_PRT2_CTL\r
-SCSI_In_DBx__4__DM0 EQU CYREG_PRT2_DM0\r
-SCSI_In_DBx__4__DM1 EQU CYREG_PRT2_DM1\r
-SCSI_In_DBx__4__DM2 EQU CYREG_PRT2_DM2\r
-SCSI_In_DBx__4__DR EQU CYREG_PRT2_DR\r
-SCSI_In_DBx__4__INP_DIS EQU CYREG_PRT2_INP_DIS\r
-SCSI_In_DBx__4__INTTYPE EQU CYREG_PICU2_INTTYPE4\r
-SCSI_In_DBx__4__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
-SCSI_In_DBx__4__LCD_EN EQU CYREG_PRT2_LCD_EN\r
-SCSI_In_DBx__4__MASK EQU 0x10\r
-SCSI_In_DBx__4__PC EQU CYREG_PRT2_PC4\r
-SCSI_In_DBx__4__PORT EQU 2\r
-SCSI_In_DBx__4__PRT EQU CYREG_PRT2_PRT\r
-SCSI_In_DBx__4__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
-SCSI_In_DBx__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
-SCSI_In_DBx__4__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
-SCSI_In_DBx__4__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
-SCSI_In_DBx__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
-SCSI_In_DBx__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
-SCSI_In_DBx__4__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
-SCSI_In_DBx__4__PS EQU CYREG_PRT2_PS\r
-SCSI_In_DBx__4__SHIFT EQU 4\r
-SCSI_In_DBx__4__SLW EQU CYREG_PRT2_SLW\r
-SCSI_In_DBx__5__AG EQU CYREG_PRT2_AG\r
-SCSI_In_DBx__5__AMUX EQU CYREG_PRT2_AMUX\r
-SCSI_In_DBx__5__BIE EQU CYREG_PRT2_BIE\r
-SCSI_In_DBx__5__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
-SCSI_In_DBx__5__BYP EQU CYREG_PRT2_BYP\r
-SCSI_In_DBx__5__CTL EQU CYREG_PRT2_CTL\r
-SCSI_In_DBx__5__DM0 EQU CYREG_PRT2_DM0\r
-SCSI_In_DBx__5__DM1 EQU CYREG_PRT2_DM1\r
-SCSI_In_DBx__5__DM2 EQU CYREG_PRT2_DM2\r
-SCSI_In_DBx__5__DR EQU CYREG_PRT2_DR\r
-SCSI_In_DBx__5__INP_DIS EQU CYREG_PRT2_INP_DIS\r
-SCSI_In_DBx__5__INTTYPE EQU CYREG_PICU2_INTTYPE3\r
-SCSI_In_DBx__5__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
-SCSI_In_DBx__5__LCD_EN EQU CYREG_PRT2_LCD_EN\r
-SCSI_In_DBx__5__MASK EQU 0x08\r
-SCSI_In_DBx__5__PC EQU CYREG_PRT2_PC3\r
-SCSI_In_DBx__5__PORT EQU 2\r
-SCSI_In_DBx__5__PRT EQU CYREG_PRT2_PRT\r
-SCSI_In_DBx__5__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
-SCSI_In_DBx__5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
-SCSI_In_DBx__5__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
-SCSI_In_DBx__5__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
-SCSI_In_DBx__5__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
-SCSI_In_DBx__5__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
-SCSI_In_DBx__5__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
-SCSI_In_DBx__5__PS EQU CYREG_PRT2_PS\r
-SCSI_In_DBx__5__SHIFT EQU 3\r
-SCSI_In_DBx__5__SLW EQU CYREG_PRT2_SLW\r
-SCSI_In_DBx__6__AG EQU CYREG_PRT2_AG\r
-SCSI_In_DBx__6__AMUX EQU CYREG_PRT2_AMUX\r
-SCSI_In_DBx__6__BIE EQU CYREG_PRT2_BIE\r
-SCSI_In_DBx__6__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
-SCSI_In_DBx__6__BYP EQU CYREG_PRT2_BYP\r
-SCSI_In_DBx__6__CTL EQU CYREG_PRT2_CTL\r
-SCSI_In_DBx__6__DM0 EQU CYREG_PRT2_DM0\r
-SCSI_In_DBx__6__DM1 EQU CYREG_PRT2_DM1\r
-SCSI_In_DBx__6__DM2 EQU CYREG_PRT2_DM2\r
-SCSI_In_DBx__6__DR EQU CYREG_PRT2_DR\r
-SCSI_In_DBx__6__INP_DIS EQU CYREG_PRT2_INP_DIS\r
-SCSI_In_DBx__6__INTTYPE EQU CYREG_PICU2_INTTYPE2\r
-SCSI_In_DBx__6__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
-SCSI_In_DBx__6__LCD_EN EQU CYREG_PRT2_LCD_EN\r
-SCSI_In_DBx__6__MASK EQU 0x04\r
-SCSI_In_DBx__6__PC EQU CYREG_PRT2_PC2\r
-SCSI_In_DBx__6__PORT EQU 2\r
-SCSI_In_DBx__6__PRT EQU CYREG_PRT2_PRT\r
-SCSI_In_DBx__6__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
-SCSI_In_DBx__6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
-SCSI_In_DBx__6__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
-SCSI_In_DBx__6__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
-SCSI_In_DBx__6__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
-SCSI_In_DBx__6__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
-SCSI_In_DBx__6__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
-SCSI_In_DBx__6__PS EQU CYREG_PRT2_PS\r
-SCSI_In_DBx__6__SHIFT EQU 2\r
-SCSI_In_DBx__6__SLW EQU CYREG_PRT2_SLW\r
-SCSI_In_DBx__7__AG EQU CYREG_PRT2_AG\r
-SCSI_In_DBx__7__AMUX EQU CYREG_PRT2_AMUX\r
-SCSI_In_DBx__7__BIE EQU CYREG_PRT2_BIE\r
-SCSI_In_DBx__7__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
-SCSI_In_DBx__7__BYP EQU CYREG_PRT2_BYP\r
-SCSI_In_DBx__7__CTL EQU CYREG_PRT2_CTL\r
-SCSI_In_DBx__7__DM0 EQU CYREG_PRT2_DM0\r
-SCSI_In_DBx__7__DM1 EQU CYREG_PRT2_DM1\r
-SCSI_In_DBx__7__DM2 EQU CYREG_PRT2_DM2\r
-SCSI_In_DBx__7__DR EQU CYREG_PRT2_DR\r
-SCSI_In_DBx__7__INP_DIS EQU CYREG_PRT2_INP_DIS\r
-SCSI_In_DBx__7__INTTYPE EQU CYREG_PICU2_INTTYPE1\r
-SCSI_In_DBx__7__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
-SCSI_In_DBx__7__LCD_EN EQU CYREG_PRT2_LCD_EN\r
-SCSI_In_DBx__7__MASK EQU 0x02\r
-SCSI_In_DBx__7__PC EQU CYREG_PRT2_PC1\r
-SCSI_In_DBx__7__PORT EQU 2\r
-SCSI_In_DBx__7__PRT EQU CYREG_PRT2_PRT\r
-SCSI_In_DBx__7__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
-SCSI_In_DBx__7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
-SCSI_In_DBx__7__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
-SCSI_In_DBx__7__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
-SCSI_In_DBx__7__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
-SCSI_In_DBx__7__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
-SCSI_In_DBx__7__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
-SCSI_In_DBx__7__PS EQU CYREG_PRT2_PS\r
-SCSI_In_DBx__7__SHIFT EQU 1\r
-SCSI_In_DBx__7__SLW EQU CYREG_PRT2_SLW\r
-SCSI_In_DBx__DB0__AG EQU CYREG_PRT12_AG\r
-SCSI_In_DBx__DB0__BIE EQU CYREG_PRT12_BIE\r
-SCSI_In_DBx__DB0__BIT_MASK EQU CYREG_PRT12_BIT_MASK\r
-SCSI_In_DBx__DB0__BYP EQU CYREG_PRT12_BYP\r
-SCSI_In_DBx__DB0__DM0 EQU CYREG_PRT12_DM0\r
-SCSI_In_DBx__DB0__DM1 EQU CYREG_PRT12_DM1\r
-SCSI_In_DBx__DB0__DM2 EQU CYREG_PRT12_DM2\r
-SCSI_In_DBx__DB0__DR EQU CYREG_PRT12_DR\r
-SCSI_In_DBx__DB0__INP_DIS EQU CYREG_PRT12_INP_DIS\r
-SCSI_In_DBx__DB0__INTTYPE EQU CYREG_PICU12_INTTYPE4\r
-SCSI_In_DBx__DB0__MASK EQU 0x10\r
-SCSI_In_DBx__DB0__PC EQU CYREG_PRT12_PC4\r
-SCSI_In_DBx__DB0__PORT EQU 12\r
-SCSI_In_DBx__DB0__PRT EQU CYREG_PRT12_PRT\r
-SCSI_In_DBx__DB0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN\r
-SCSI_In_DBx__DB0__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0\r
-SCSI_In_DBx__DB0__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1\r
-SCSI_In_DBx__DB0__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0\r
-SCSI_In_DBx__DB0__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1\r
-SCSI_In_DBx__DB0__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT\r
-SCSI_In_DBx__DB0__PS EQU CYREG_PRT12_PS\r
-SCSI_In_DBx__DB0__SHIFT EQU 4\r
-SCSI_In_DBx__DB0__SIO_CFG EQU CYREG_PRT12_SIO_CFG\r
-SCSI_In_DBx__DB0__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF\r
-SCSI_In_DBx__DB0__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN\r
-SCSI_In_DBx__DB0__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ\r
-SCSI_In_DBx__DB0__SLW EQU CYREG_PRT12_SLW\r
-SCSI_In_DBx__DB1__AG EQU CYREG_PRT2_AG\r
-SCSI_In_DBx__DB1__AMUX EQU CYREG_PRT2_AMUX\r
-SCSI_In_DBx__DB1__BIE EQU CYREG_PRT2_BIE\r
-SCSI_In_DBx__DB1__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
-SCSI_In_DBx__DB1__BYP EQU CYREG_PRT2_BYP\r
-SCSI_In_DBx__DB1__CTL EQU CYREG_PRT2_CTL\r
-SCSI_In_DBx__DB1__DM0 EQU CYREG_PRT2_DM0\r
-SCSI_In_DBx__DB1__DM1 EQU CYREG_PRT2_DM1\r
-SCSI_In_DBx__DB1__DM2 EQU CYREG_PRT2_DM2\r
-SCSI_In_DBx__DB1__DR EQU CYREG_PRT2_DR\r
-SCSI_In_DBx__DB1__INP_DIS EQU CYREG_PRT2_INP_DIS\r
-SCSI_In_DBx__DB1__INTTYPE EQU CYREG_PICU2_INTTYPE7\r
-SCSI_In_DBx__DB1__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
-SCSI_In_DBx__DB1__LCD_EN EQU CYREG_PRT2_LCD_EN\r
-SCSI_In_DBx__DB1__MASK EQU 0x80\r
-SCSI_In_DBx__DB1__PC EQU CYREG_PRT2_PC7\r
-SCSI_In_DBx__DB1__PORT EQU 2\r
-SCSI_In_DBx__DB1__PRT EQU CYREG_PRT2_PRT\r
-SCSI_In_DBx__DB1__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
-SCSI_In_DBx__DB1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
-SCSI_In_DBx__DB1__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
-SCSI_In_DBx__DB1__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
-SCSI_In_DBx__DB1__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
-SCSI_In_DBx__DB1__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
-SCSI_In_DBx__DB1__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
-SCSI_In_DBx__DB1__PS EQU CYREG_PRT2_PS\r
-SCSI_In_DBx__DB1__SHIFT EQU 7\r
-SCSI_In_DBx__DB1__SLW EQU CYREG_PRT2_SLW\r
-SCSI_In_DBx__DB2__AG EQU CYREG_PRT2_AG\r
-SCSI_In_DBx__DB2__AMUX EQU CYREG_PRT2_AMUX\r
-SCSI_In_DBx__DB2__BIE EQU CYREG_PRT2_BIE\r
-SCSI_In_DBx__DB2__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
-SCSI_In_DBx__DB2__BYP EQU CYREG_PRT2_BYP\r
-SCSI_In_DBx__DB2__CTL EQU CYREG_PRT2_CTL\r
-SCSI_In_DBx__DB2__DM0 EQU CYREG_PRT2_DM0\r
-SCSI_In_DBx__DB2__DM1 EQU CYREG_PRT2_DM1\r
-SCSI_In_DBx__DB2__DM2 EQU CYREG_PRT2_DM2\r
-SCSI_In_DBx__DB2__DR EQU CYREG_PRT2_DR\r
-SCSI_In_DBx__DB2__INP_DIS EQU CYREG_PRT2_INP_DIS\r
-SCSI_In_DBx__DB2__INTTYPE EQU CYREG_PICU2_INTTYPE6\r
-SCSI_In_DBx__DB2__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
-SCSI_In_DBx__DB2__LCD_EN EQU CYREG_PRT2_LCD_EN\r
-SCSI_In_DBx__DB2__MASK EQU 0x40\r
-SCSI_In_DBx__DB2__PC EQU CYREG_PRT2_PC6\r
-SCSI_In_DBx__DB2__PORT EQU 2\r
-SCSI_In_DBx__DB2__PRT EQU CYREG_PRT2_PRT\r
-SCSI_In_DBx__DB2__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
-SCSI_In_DBx__DB2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
-SCSI_In_DBx__DB2__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
-SCSI_In_DBx__DB2__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
-SCSI_In_DBx__DB2__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
-SCSI_In_DBx__DB2__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
-SCSI_In_DBx__DB2__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
-SCSI_In_DBx__DB2__PS EQU CYREG_PRT2_PS\r
-SCSI_In_DBx__DB2__SHIFT EQU 6\r
-SCSI_In_DBx__DB2__SLW EQU CYREG_PRT2_SLW\r
-SCSI_In_DBx__DB3__AG EQU CYREG_PRT2_AG\r
-SCSI_In_DBx__DB3__AMUX EQU CYREG_PRT2_AMUX\r
-SCSI_In_DBx__DB3__BIE EQU CYREG_PRT2_BIE\r
-SCSI_In_DBx__DB3__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
-SCSI_In_DBx__DB3__BYP EQU CYREG_PRT2_BYP\r
-SCSI_In_DBx__DB3__CTL EQU CYREG_PRT2_CTL\r
-SCSI_In_DBx__DB3__DM0 EQU CYREG_PRT2_DM0\r
-SCSI_In_DBx__DB3__DM1 EQU CYREG_PRT2_DM1\r
-SCSI_In_DBx__DB3__DM2 EQU CYREG_PRT2_DM2\r
-SCSI_In_DBx__DB3__DR EQU CYREG_PRT2_DR\r
-SCSI_In_DBx__DB3__INP_DIS EQU CYREG_PRT2_INP_DIS\r
-SCSI_In_DBx__DB3__INTTYPE EQU CYREG_PICU2_INTTYPE5\r
-SCSI_In_DBx__DB3__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
-SCSI_In_DBx__DB3__LCD_EN EQU CYREG_PRT2_LCD_EN\r
-SCSI_In_DBx__DB3__MASK EQU 0x20\r
-SCSI_In_DBx__DB3__PC EQU CYREG_PRT2_PC5\r
-SCSI_In_DBx__DB3__PORT EQU 2\r
-SCSI_In_DBx__DB3__PRT EQU CYREG_PRT2_PRT\r
-SCSI_In_DBx__DB3__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
-SCSI_In_DBx__DB3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
-SCSI_In_DBx__DB3__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
-SCSI_In_DBx__DB3__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
-SCSI_In_DBx__DB3__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
-SCSI_In_DBx__DB3__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
-SCSI_In_DBx__DB3__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
-SCSI_In_DBx__DB3__PS EQU CYREG_PRT2_PS\r
-SCSI_In_DBx__DB3__SHIFT EQU 5\r
-SCSI_In_DBx__DB3__SLW EQU CYREG_PRT2_SLW\r
-SCSI_In_DBx__DB4__AG EQU CYREG_PRT2_AG\r
-SCSI_In_DBx__DB4__AMUX EQU CYREG_PRT2_AMUX\r
-SCSI_In_DBx__DB4__BIE EQU CYREG_PRT2_BIE\r
-SCSI_In_DBx__DB4__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
-SCSI_In_DBx__DB4__BYP EQU CYREG_PRT2_BYP\r
-SCSI_In_DBx__DB4__CTL EQU CYREG_PRT2_CTL\r
-SCSI_In_DBx__DB4__DM0 EQU CYREG_PRT2_DM0\r
-SCSI_In_DBx__DB4__DM1 EQU CYREG_PRT2_DM1\r
-SCSI_In_DBx__DB4__DM2 EQU CYREG_PRT2_DM2\r
-SCSI_In_DBx__DB4__DR EQU CYREG_PRT2_DR\r
-SCSI_In_DBx__DB4__INP_DIS EQU CYREG_PRT2_INP_DIS\r
-SCSI_In_DBx__DB4__INTTYPE EQU CYREG_PICU2_INTTYPE4\r
-SCSI_In_DBx__DB4__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
-SCSI_In_DBx__DB4__LCD_EN EQU CYREG_PRT2_LCD_EN\r
-SCSI_In_DBx__DB4__MASK EQU 0x10\r
-SCSI_In_DBx__DB4__PC EQU CYREG_PRT2_PC4\r
-SCSI_In_DBx__DB4__PORT EQU 2\r
-SCSI_In_DBx__DB4__PRT EQU CYREG_PRT2_PRT\r
-SCSI_In_DBx__DB4__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
-SCSI_In_DBx__DB4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
-SCSI_In_DBx__DB4__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
-SCSI_In_DBx__DB4__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
-SCSI_In_DBx__DB4__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
-SCSI_In_DBx__DB4__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
-SCSI_In_DBx__DB4__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
-SCSI_In_DBx__DB4__PS EQU CYREG_PRT2_PS\r
-SCSI_In_DBx__DB4__SHIFT EQU 4\r
-SCSI_In_DBx__DB4__SLW EQU CYREG_PRT2_SLW\r
-SCSI_In_DBx__DB5__AG EQU CYREG_PRT2_AG\r
-SCSI_In_DBx__DB5__AMUX EQU CYREG_PRT2_AMUX\r
-SCSI_In_DBx__DB5__BIE EQU CYREG_PRT2_BIE\r
-SCSI_In_DBx__DB5__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
-SCSI_In_DBx__DB5__BYP EQU CYREG_PRT2_BYP\r
-SCSI_In_DBx__DB5__CTL EQU CYREG_PRT2_CTL\r
-SCSI_In_DBx__DB5__DM0 EQU CYREG_PRT2_DM0\r
-SCSI_In_DBx__DB5__DM1 EQU CYREG_PRT2_DM1\r
-SCSI_In_DBx__DB5__DM2 EQU CYREG_PRT2_DM2\r
-SCSI_In_DBx__DB5__DR EQU CYREG_PRT2_DR\r
-SCSI_In_DBx__DB5__INP_DIS EQU CYREG_PRT2_INP_DIS\r
-SCSI_In_DBx__DB5__INTTYPE EQU CYREG_PICU2_INTTYPE3\r
-SCSI_In_DBx__DB5__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
-SCSI_In_DBx__DB5__LCD_EN EQU CYREG_PRT2_LCD_EN\r
-SCSI_In_DBx__DB5__MASK EQU 0x08\r
-SCSI_In_DBx__DB5__PC EQU CYREG_PRT2_PC3\r
-SCSI_In_DBx__DB5__PORT EQU 2\r
-SCSI_In_DBx__DB5__PRT EQU CYREG_PRT2_PRT\r
-SCSI_In_DBx__DB5__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
-SCSI_In_DBx__DB5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
-SCSI_In_DBx__DB5__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
-SCSI_In_DBx__DB5__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
-SCSI_In_DBx__DB5__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
-SCSI_In_DBx__DB5__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
-SCSI_In_DBx__DB5__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
-SCSI_In_DBx__DB5__PS EQU CYREG_PRT2_PS\r
-SCSI_In_DBx__DB5__SHIFT EQU 3\r
-SCSI_In_DBx__DB5__SLW EQU CYREG_PRT2_SLW\r
-SCSI_In_DBx__DB6__AG EQU CYREG_PRT2_AG\r
-SCSI_In_DBx__DB6__AMUX EQU CYREG_PRT2_AMUX\r
-SCSI_In_DBx__DB6__BIE EQU CYREG_PRT2_BIE\r
-SCSI_In_DBx__DB6__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
-SCSI_In_DBx__DB6__BYP EQU CYREG_PRT2_BYP\r
-SCSI_In_DBx__DB6__CTL EQU CYREG_PRT2_CTL\r
-SCSI_In_DBx__DB6__DM0 EQU CYREG_PRT2_DM0\r
-SCSI_In_DBx__DB6__DM1 EQU CYREG_PRT2_DM1\r
-SCSI_In_DBx__DB6__DM2 EQU CYREG_PRT2_DM2\r
-SCSI_In_DBx__DB6__DR EQU CYREG_PRT2_DR\r
-SCSI_In_DBx__DB6__INP_DIS EQU CYREG_PRT2_INP_DIS\r
-SCSI_In_DBx__DB6__INTTYPE EQU CYREG_PICU2_INTTYPE2\r
-SCSI_In_DBx__DB6__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
-SCSI_In_DBx__DB6__LCD_EN EQU CYREG_PRT2_LCD_EN\r
-SCSI_In_DBx__DB6__MASK EQU 0x04\r
-SCSI_In_DBx__DB6__PC EQU CYREG_PRT2_PC2\r
-SCSI_In_DBx__DB6__PORT EQU 2\r
-SCSI_In_DBx__DB6__PRT EQU CYREG_PRT2_PRT\r
-SCSI_In_DBx__DB6__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
-SCSI_In_DBx__DB6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
-SCSI_In_DBx__DB6__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
-SCSI_In_DBx__DB6__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
-SCSI_In_DBx__DB6__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
-SCSI_In_DBx__DB6__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
-SCSI_In_DBx__DB6__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
-SCSI_In_DBx__DB6__PS EQU CYREG_PRT2_PS\r
-SCSI_In_DBx__DB6__SHIFT EQU 2\r
-SCSI_In_DBx__DB6__SLW EQU CYREG_PRT2_SLW\r
-SCSI_In_DBx__DB7__AG EQU CYREG_PRT2_AG\r
-SCSI_In_DBx__DB7__AMUX EQU CYREG_PRT2_AMUX\r
-SCSI_In_DBx__DB7__BIE EQU CYREG_PRT2_BIE\r
-SCSI_In_DBx__DB7__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
-SCSI_In_DBx__DB7__BYP EQU CYREG_PRT2_BYP\r
-SCSI_In_DBx__DB7__CTL EQU CYREG_PRT2_CTL\r
-SCSI_In_DBx__DB7__DM0 EQU CYREG_PRT2_DM0\r
-SCSI_In_DBx__DB7__DM1 EQU CYREG_PRT2_DM1\r
-SCSI_In_DBx__DB7__DM2 EQU CYREG_PRT2_DM2\r
-SCSI_In_DBx__DB7__DR EQU CYREG_PRT2_DR\r
-SCSI_In_DBx__DB7__INP_DIS EQU CYREG_PRT2_INP_DIS\r
-SCSI_In_DBx__DB7__INTTYPE EQU CYREG_PICU2_INTTYPE1\r
-SCSI_In_DBx__DB7__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
-SCSI_In_DBx__DB7__LCD_EN EQU CYREG_PRT2_LCD_EN\r
-SCSI_In_DBx__DB7__MASK EQU 0x02\r
-SCSI_In_DBx__DB7__PC EQU CYREG_PRT2_PC1\r
-SCSI_In_DBx__DB7__PORT EQU 2\r
-SCSI_In_DBx__DB7__PRT EQU CYREG_PRT2_PRT\r
-SCSI_In_DBx__DB7__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
-SCSI_In_DBx__DB7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
-SCSI_In_DBx__DB7__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
-SCSI_In_DBx__DB7__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
-SCSI_In_DBx__DB7__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
-SCSI_In_DBx__DB7__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
-SCSI_In_DBx__DB7__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
-SCSI_In_DBx__DB7__PS EQU CYREG_PRT2_PS\r
-SCSI_In_DBx__DB7__SHIFT EQU 1\r
-SCSI_In_DBx__DB7__SLW EQU CYREG_PRT2_SLW\r
-\r
-; SCSI_Noise\r
-SCSI_Noise__0__AG EQU CYREG_PRT12_AG\r
-SCSI_Noise__0__BIE EQU CYREG_PRT12_BIE\r
-SCSI_Noise__0__BIT_MASK EQU CYREG_PRT12_BIT_MASK\r
-SCSI_Noise__0__BYP EQU CYREG_PRT12_BYP\r
-SCSI_Noise__0__DM0 EQU CYREG_PRT12_DM0\r
-SCSI_Noise__0__DM1 EQU CYREG_PRT12_DM1\r
-SCSI_Noise__0__DM2 EQU CYREG_PRT12_DM2\r
-SCSI_Noise__0__DR EQU CYREG_PRT12_DR\r
-SCSI_Noise__0__INP_DIS EQU CYREG_PRT12_INP_DIS\r
-SCSI_Noise__0__INTTYPE EQU CYREG_PICU12_INTTYPE5\r
-SCSI_Noise__0__MASK EQU 0x20\r
-SCSI_Noise__0__PC EQU CYREG_PRT12_PC5\r
-SCSI_Noise__0__PORT EQU 12\r
-SCSI_Noise__0__PRT EQU CYREG_PRT12_PRT\r
-SCSI_Noise__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN\r
-SCSI_Noise__0__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0\r
-SCSI_Noise__0__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1\r
-SCSI_Noise__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0\r
-SCSI_Noise__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1\r
-SCSI_Noise__0__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT\r
-SCSI_Noise__0__PS EQU CYREG_PRT12_PS\r
-SCSI_Noise__0__SHIFT EQU 5\r
-SCSI_Noise__0__SIO_CFG EQU CYREG_PRT12_SIO_CFG\r
-SCSI_Noise__0__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF\r
-SCSI_Noise__0__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN\r
-SCSI_Noise__0__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ\r
-SCSI_Noise__0__SLW EQU CYREG_PRT12_SLW\r
-SCSI_Noise__1__AG EQU CYREG_PRT6_AG\r
-SCSI_Noise__1__AMUX EQU CYREG_PRT6_AMUX\r
-SCSI_Noise__1__BIE EQU CYREG_PRT6_BIE\r
-SCSI_Noise__1__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
-SCSI_Noise__1__BYP EQU CYREG_PRT6_BYP\r
-SCSI_Noise__1__CTL EQU CYREG_PRT6_CTL\r
-SCSI_Noise__1__DM0 EQU CYREG_PRT6_DM0\r
-SCSI_Noise__1__DM1 EQU CYREG_PRT6_DM1\r
-SCSI_Noise__1__DM2 EQU CYREG_PRT6_DM2\r
-SCSI_Noise__1__DR EQU CYREG_PRT6_DR\r
-SCSI_Noise__1__INP_DIS EQU CYREG_PRT6_INP_DIS\r
-SCSI_Noise__1__INTTYPE EQU CYREG_PICU6_INTTYPE4\r
-SCSI_Noise__1__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
-SCSI_Noise__1__LCD_EN EQU CYREG_PRT6_LCD_EN\r
-SCSI_Noise__1__MASK EQU 0x10\r
-SCSI_Noise__1__PC EQU CYREG_PRT6_PC4\r
-SCSI_Noise__1__PORT EQU 6\r
-SCSI_Noise__1__PRT EQU CYREG_PRT6_PRT\r
-SCSI_Noise__1__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
-SCSI_Noise__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
-SCSI_Noise__1__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
-SCSI_Noise__1__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
-SCSI_Noise__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
-SCSI_Noise__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
-SCSI_Noise__1__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
-SCSI_Noise__1__PS EQU CYREG_PRT6_PS\r
-SCSI_Noise__1__SHIFT EQU 4\r
-SCSI_Noise__1__SLW EQU CYREG_PRT6_SLW\r
-SCSI_Noise__2__AG EQU CYREG_PRT5_AG\r
-SCSI_Noise__2__AMUX EQU CYREG_PRT5_AMUX\r
-SCSI_Noise__2__BIE EQU CYREG_PRT5_BIE\r
-SCSI_Noise__2__BIT_MASK EQU CYREG_PRT5_BIT_MASK\r
-SCSI_Noise__2__BYP EQU CYREG_PRT5_BYP\r
-SCSI_Noise__2__CTL EQU CYREG_PRT5_CTL\r
-SCSI_Noise__2__DM0 EQU CYREG_PRT5_DM0\r
-SCSI_Noise__2__DM1 EQU CYREG_PRT5_DM1\r
-SCSI_Noise__2__DM2 EQU CYREG_PRT5_DM2\r
-SCSI_Noise__2__DR EQU CYREG_PRT5_DR\r
-SCSI_Noise__2__INP_DIS EQU CYREG_PRT5_INP_DIS\r
-SCSI_Noise__2__INTTYPE EQU CYREG_PICU5_INTTYPE0\r
-SCSI_Noise__2__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG\r
-SCSI_Noise__2__LCD_EN EQU CYREG_PRT5_LCD_EN\r
-SCSI_Noise__2__MASK EQU 0x01\r
-SCSI_Noise__2__PC EQU CYREG_PRT5_PC0\r
-SCSI_Noise__2__PORT EQU 5\r
-SCSI_Noise__2__PRT EQU CYREG_PRT5_PRT\r
-SCSI_Noise__2__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL\r
-SCSI_Noise__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN\r
-SCSI_Noise__2__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0\r
-SCSI_Noise__2__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1\r
-SCSI_Noise__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0\r
-SCSI_Noise__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1\r
-SCSI_Noise__2__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT\r
-SCSI_Noise__2__PS EQU CYREG_PRT5_PS\r
-SCSI_Noise__2__SHIFT EQU 0\r
-SCSI_Noise__2__SLW EQU CYREG_PRT5_SLW\r
-SCSI_Noise__3__AG EQU CYREG_PRT6_AG\r
-SCSI_Noise__3__AMUX EQU CYREG_PRT6_AMUX\r
-SCSI_Noise__3__BIE EQU CYREG_PRT6_BIE\r
-SCSI_Noise__3__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
-SCSI_Noise__3__BYP EQU CYREG_PRT6_BYP\r
-SCSI_Noise__3__CTL EQU CYREG_PRT6_CTL\r
-SCSI_Noise__3__DM0 EQU CYREG_PRT6_DM0\r
-SCSI_Noise__3__DM1 EQU CYREG_PRT6_DM1\r
-SCSI_Noise__3__DM2 EQU CYREG_PRT6_DM2\r
-SCSI_Noise__3__DR EQU CYREG_PRT6_DR\r
-SCSI_Noise__3__INP_DIS EQU CYREG_PRT6_INP_DIS\r
-SCSI_Noise__3__INTTYPE EQU CYREG_PICU6_INTTYPE6\r
-SCSI_Noise__3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
-SCSI_Noise__3__LCD_EN EQU CYREG_PRT6_LCD_EN\r
-SCSI_Noise__3__MASK EQU 0x40\r
-SCSI_Noise__3__PC EQU CYREG_PRT6_PC6\r
-SCSI_Noise__3__PORT EQU 6\r
-SCSI_Noise__3__PRT EQU CYREG_PRT6_PRT\r
-SCSI_Noise__3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
-SCSI_Noise__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
-SCSI_Noise__3__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
-SCSI_Noise__3__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
-SCSI_Noise__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
-SCSI_Noise__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
-SCSI_Noise__3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
-SCSI_Noise__3__PS EQU CYREG_PRT6_PS\r
-SCSI_Noise__3__SHIFT EQU 6\r
-SCSI_Noise__3__SLW EQU CYREG_PRT6_SLW\r
-SCSI_Noise__4__AG EQU CYREG_PRT6_AG\r
-SCSI_Noise__4__AMUX EQU CYREG_PRT6_AMUX\r
-SCSI_Noise__4__BIE EQU CYREG_PRT6_BIE\r
-SCSI_Noise__4__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
-SCSI_Noise__4__BYP EQU CYREG_PRT6_BYP\r
-SCSI_Noise__4__CTL EQU CYREG_PRT6_CTL\r
-SCSI_Noise__4__DM0 EQU CYREG_PRT6_DM0\r
-SCSI_Noise__4__DM1 EQU CYREG_PRT6_DM1\r
-SCSI_Noise__4__DM2 EQU CYREG_PRT6_DM2\r
-SCSI_Noise__4__DR EQU CYREG_PRT6_DR\r
-SCSI_Noise__4__INP_DIS EQU CYREG_PRT6_INP_DIS\r
-SCSI_Noise__4__INTTYPE EQU CYREG_PICU6_INTTYPE5\r
-SCSI_Noise__4__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
-SCSI_Noise__4__LCD_EN EQU CYREG_PRT6_LCD_EN\r
-SCSI_Noise__4__MASK EQU 0x20\r
-SCSI_Noise__4__PC EQU CYREG_PRT6_PC5\r
-SCSI_Noise__4__PORT EQU 6\r
-SCSI_Noise__4__PRT EQU CYREG_PRT6_PRT\r
-SCSI_Noise__4__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
-SCSI_Noise__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
-SCSI_Noise__4__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
-SCSI_Noise__4__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
-SCSI_Noise__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
-SCSI_Noise__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
-SCSI_Noise__4__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
-SCSI_Noise__4__PS EQU CYREG_PRT6_PS\r
-SCSI_Noise__4__SHIFT EQU 5\r
-SCSI_Noise__4__SLW EQU CYREG_PRT6_SLW\r
-SCSI_Noise__ACK__AG EQU CYREG_PRT6_AG\r
-SCSI_Noise__ACK__AMUX EQU CYREG_PRT6_AMUX\r
-SCSI_Noise__ACK__BIE EQU CYREG_PRT6_BIE\r
-SCSI_Noise__ACK__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
-SCSI_Noise__ACK__BYP EQU CYREG_PRT6_BYP\r
-SCSI_Noise__ACK__CTL EQU CYREG_PRT6_CTL\r
-SCSI_Noise__ACK__DM0 EQU CYREG_PRT6_DM0\r
-SCSI_Noise__ACK__DM1 EQU CYREG_PRT6_DM1\r
-SCSI_Noise__ACK__DM2 EQU CYREG_PRT6_DM2\r
-SCSI_Noise__ACK__DR EQU CYREG_PRT6_DR\r
-SCSI_Noise__ACK__INP_DIS EQU CYREG_PRT6_INP_DIS\r
-SCSI_Noise__ACK__INTTYPE EQU CYREG_PICU6_INTTYPE5\r
-SCSI_Noise__ACK__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
-SCSI_Noise__ACK__LCD_EN EQU CYREG_PRT6_LCD_EN\r
-SCSI_Noise__ACK__MASK EQU 0x20\r
-SCSI_Noise__ACK__PC EQU CYREG_PRT6_PC5\r
-SCSI_Noise__ACK__PORT EQU 6\r
-SCSI_Noise__ACK__PRT EQU CYREG_PRT6_PRT\r
-SCSI_Noise__ACK__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
-SCSI_Noise__ACK__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
-SCSI_Noise__ACK__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
-SCSI_Noise__ACK__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
-SCSI_Noise__ACK__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
-SCSI_Noise__ACK__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
-SCSI_Noise__ACK__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
-SCSI_Noise__ACK__PS EQU CYREG_PRT6_PS\r
-SCSI_Noise__ACK__SHIFT EQU 5\r
-SCSI_Noise__ACK__SLW EQU CYREG_PRT6_SLW\r
-SCSI_Noise__ATN__AG EQU CYREG_PRT12_AG\r
-SCSI_Noise__ATN__BIE EQU CYREG_PRT12_BIE\r
-SCSI_Noise__ATN__BIT_MASK EQU CYREG_PRT12_BIT_MASK\r
-SCSI_Noise__ATN__BYP EQU CYREG_PRT12_BYP\r
-SCSI_Noise__ATN__DM0 EQU CYREG_PRT12_DM0\r
-SCSI_Noise__ATN__DM1 EQU CYREG_PRT12_DM1\r
-SCSI_Noise__ATN__DM2 EQU CYREG_PRT12_DM2\r
-SCSI_Noise__ATN__DR EQU CYREG_PRT12_DR\r
-SCSI_Noise__ATN__INP_DIS EQU CYREG_PRT12_INP_DIS\r
-SCSI_Noise__ATN__INTTYPE EQU CYREG_PICU12_INTTYPE5\r
-SCSI_Noise__ATN__MASK EQU 0x20\r
-SCSI_Noise__ATN__PC EQU CYREG_PRT12_PC5\r
-SCSI_Noise__ATN__PORT EQU 12\r
-SCSI_Noise__ATN__PRT EQU CYREG_PRT12_PRT\r
-SCSI_Noise__ATN__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN\r
-SCSI_Noise__ATN__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0\r
-SCSI_Noise__ATN__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1\r
-SCSI_Noise__ATN__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0\r
-SCSI_Noise__ATN__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1\r
-SCSI_Noise__ATN__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT\r
-SCSI_Noise__ATN__PS EQU CYREG_PRT12_PS\r
-SCSI_Noise__ATN__SHIFT EQU 5\r
-SCSI_Noise__ATN__SIO_CFG EQU CYREG_PRT12_SIO_CFG\r
-SCSI_Noise__ATN__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF\r
-SCSI_Noise__ATN__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN\r
-SCSI_Noise__ATN__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ\r
-SCSI_Noise__ATN__SLW EQU CYREG_PRT12_SLW\r
-SCSI_Noise__BSY__AG EQU CYREG_PRT6_AG\r
-SCSI_Noise__BSY__AMUX EQU CYREG_PRT6_AMUX\r
-SCSI_Noise__BSY__BIE EQU CYREG_PRT6_BIE\r
-SCSI_Noise__BSY__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
-SCSI_Noise__BSY__BYP EQU CYREG_PRT6_BYP\r
-SCSI_Noise__BSY__CTL EQU CYREG_PRT6_CTL\r
-SCSI_Noise__BSY__DM0 EQU CYREG_PRT6_DM0\r
-SCSI_Noise__BSY__DM1 EQU CYREG_PRT6_DM1\r
-SCSI_Noise__BSY__DM2 EQU CYREG_PRT6_DM2\r
-SCSI_Noise__BSY__DR EQU CYREG_PRT6_DR\r
-SCSI_Noise__BSY__INP_DIS EQU CYREG_PRT6_INP_DIS\r
-SCSI_Noise__BSY__INTTYPE EQU CYREG_PICU6_INTTYPE4\r
-SCSI_Noise__BSY__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
-SCSI_Noise__BSY__LCD_EN EQU CYREG_PRT6_LCD_EN\r
-SCSI_Noise__BSY__MASK EQU 0x10\r
-SCSI_Noise__BSY__PC EQU CYREG_PRT6_PC4\r
-SCSI_Noise__BSY__PORT EQU 6\r
-SCSI_Noise__BSY__PRT EQU CYREG_PRT6_PRT\r
-SCSI_Noise__BSY__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
-SCSI_Noise__BSY__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
-SCSI_Noise__BSY__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
-SCSI_Noise__BSY__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
-SCSI_Noise__BSY__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
-SCSI_Noise__BSY__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
-SCSI_Noise__BSY__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
-SCSI_Noise__BSY__PS EQU CYREG_PRT6_PS\r
-SCSI_Noise__BSY__SHIFT EQU 4\r
-SCSI_Noise__BSY__SLW EQU CYREG_PRT6_SLW\r
-SCSI_Noise__RST__AG EQU CYREG_PRT6_AG\r
-SCSI_Noise__RST__AMUX EQU CYREG_PRT6_AMUX\r
-SCSI_Noise__RST__BIE EQU CYREG_PRT6_BIE\r
-SCSI_Noise__RST__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
-SCSI_Noise__RST__BYP EQU CYREG_PRT6_BYP\r
-SCSI_Noise__RST__CTL EQU CYREG_PRT6_CTL\r
-SCSI_Noise__RST__DM0 EQU CYREG_PRT6_DM0\r
-SCSI_Noise__RST__DM1 EQU CYREG_PRT6_DM1\r
-SCSI_Noise__RST__DM2 EQU CYREG_PRT6_DM2\r
-SCSI_Noise__RST__DR EQU CYREG_PRT6_DR\r
-SCSI_Noise__RST__INP_DIS EQU CYREG_PRT6_INP_DIS\r
-SCSI_Noise__RST__INTTYPE EQU CYREG_PICU6_INTTYPE6\r
-SCSI_Noise__RST__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
-SCSI_Noise__RST__LCD_EN EQU CYREG_PRT6_LCD_EN\r
-SCSI_Noise__RST__MASK EQU 0x40\r
-SCSI_Noise__RST__PC EQU CYREG_PRT6_PC6\r
-SCSI_Noise__RST__PORT EQU 6\r
-SCSI_Noise__RST__PRT EQU CYREG_PRT6_PRT\r
-SCSI_Noise__RST__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
-SCSI_Noise__RST__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
-SCSI_Noise__RST__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
-SCSI_Noise__RST__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
-SCSI_Noise__RST__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
-SCSI_Noise__RST__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
-SCSI_Noise__RST__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
-SCSI_Noise__RST__PS EQU CYREG_PRT6_PS\r
-SCSI_Noise__RST__SHIFT EQU 6\r
-SCSI_Noise__RST__SLW EQU CYREG_PRT6_SLW\r
-SCSI_Noise__SEL__AG EQU CYREG_PRT5_AG\r
-SCSI_Noise__SEL__AMUX EQU CYREG_PRT5_AMUX\r
-SCSI_Noise__SEL__BIE EQU CYREG_PRT5_BIE\r
-SCSI_Noise__SEL__BIT_MASK EQU CYREG_PRT5_BIT_MASK\r
-SCSI_Noise__SEL__BYP EQU CYREG_PRT5_BYP\r
-SCSI_Noise__SEL__CTL EQU CYREG_PRT5_CTL\r
-SCSI_Noise__SEL__DM0 EQU CYREG_PRT5_DM0\r
-SCSI_Noise__SEL__DM1 EQU CYREG_PRT5_DM1\r
-SCSI_Noise__SEL__DM2 EQU CYREG_PRT5_DM2\r
-SCSI_Noise__SEL__DR EQU CYREG_PRT5_DR\r
-SCSI_Noise__SEL__INP_DIS EQU CYREG_PRT5_INP_DIS\r
-SCSI_Noise__SEL__INTTYPE EQU CYREG_PICU5_INTTYPE0\r
-SCSI_Noise__SEL__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG\r
-SCSI_Noise__SEL__LCD_EN EQU CYREG_PRT5_LCD_EN\r
-SCSI_Noise__SEL__MASK EQU 0x01\r
-SCSI_Noise__SEL__PC EQU CYREG_PRT5_PC0\r
-SCSI_Noise__SEL__PORT EQU 5\r
-SCSI_Noise__SEL__PRT EQU CYREG_PRT5_PRT\r
-SCSI_Noise__SEL__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL\r
-SCSI_Noise__SEL__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN\r
-SCSI_Noise__SEL__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0\r
-SCSI_Noise__SEL__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1\r
-SCSI_Noise__SEL__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0\r
-SCSI_Noise__SEL__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1\r
-SCSI_Noise__SEL__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT\r
-SCSI_Noise__SEL__PS EQU CYREG_PRT5_PS\r
-SCSI_Noise__SEL__SHIFT EQU 0\r
-SCSI_Noise__SEL__SLW EQU CYREG_PRT5_SLW\r
-\r
-; SCSI_Out\r
-SCSI_Out__0__AG EQU CYREG_PRT4_AG\r
-SCSI_Out__0__AMUX EQU CYREG_PRT4_AMUX\r
-SCSI_Out__0__BIE EQU CYREG_PRT4_BIE\r
-SCSI_Out__0__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
-SCSI_Out__0__BYP EQU CYREG_PRT4_BYP\r
-SCSI_Out__0__CTL EQU CYREG_PRT4_CTL\r
-SCSI_Out__0__DM0 EQU CYREG_PRT4_DM0\r
-SCSI_Out__0__DM1 EQU CYREG_PRT4_DM1\r
-SCSI_Out__0__DM2 EQU CYREG_PRT4_DM2\r
-SCSI_Out__0__DR EQU CYREG_PRT4_DR\r
-SCSI_Out__0__INP_DIS EQU CYREG_PRT4_INP_DIS\r
-SCSI_Out__0__INTTYPE EQU CYREG_PICU4_INTTYPE3\r
-SCSI_Out__0__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
-SCSI_Out__0__LCD_EN EQU CYREG_PRT4_LCD_EN\r
-SCSI_Out__0__MASK EQU 0x08\r
-SCSI_Out__0__PC EQU CYREG_PRT4_PC3\r
-SCSI_Out__0__PORT EQU 4\r
-SCSI_Out__0__PRT EQU CYREG_PRT4_PRT\r
-SCSI_Out__0__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
-SCSI_Out__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
-SCSI_Out__0__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
-SCSI_Out__0__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
-SCSI_Out__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
-SCSI_Out__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
-SCSI_Out__0__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
-SCSI_Out__0__PS EQU CYREG_PRT4_PS\r
-SCSI_Out__0__SHIFT EQU 3\r
-SCSI_Out__0__SLW EQU CYREG_PRT4_SLW\r
-SCSI_Out__1__AG EQU CYREG_PRT4_AG\r
-SCSI_Out__1__AMUX EQU CYREG_PRT4_AMUX\r
-SCSI_Out__1__BIE EQU CYREG_PRT4_BIE\r
-SCSI_Out__1__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
-SCSI_Out__1__BYP EQU CYREG_PRT4_BYP\r
-SCSI_Out__1__CTL EQU CYREG_PRT4_CTL\r
-SCSI_Out__1__DM0 EQU CYREG_PRT4_DM0\r
-SCSI_Out__1__DM1 EQU CYREG_PRT4_DM1\r
-SCSI_Out__1__DM2 EQU CYREG_PRT4_DM2\r
-SCSI_Out__1__DR EQU CYREG_PRT4_DR\r
-SCSI_Out__1__INP_DIS EQU CYREG_PRT4_INP_DIS\r
-SCSI_Out__1__INTTYPE EQU CYREG_PICU4_INTTYPE2\r
-SCSI_Out__1__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
-SCSI_Out__1__LCD_EN EQU CYREG_PRT4_LCD_EN\r
-SCSI_Out__1__MASK EQU 0x04\r
-SCSI_Out__1__PC EQU CYREG_PRT4_PC2\r
-SCSI_Out__1__PORT EQU 4\r
-SCSI_Out__1__PRT EQU CYREG_PRT4_PRT\r
-SCSI_Out__1__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
-SCSI_Out__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
-SCSI_Out__1__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
-SCSI_Out__1__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
-SCSI_Out__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
-SCSI_Out__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
-SCSI_Out__1__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
-SCSI_Out__1__PS EQU CYREG_PRT4_PS\r
-SCSI_Out__1__SHIFT EQU 2\r
-SCSI_Out__1__SLW EQU CYREG_PRT4_SLW\r
-SCSI_Out__2__AG EQU CYREG_PRT0_AG\r
-SCSI_Out__2__AMUX EQU CYREG_PRT0_AMUX\r
-SCSI_Out__2__BIE EQU CYREG_PRT0_BIE\r
-SCSI_Out__2__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
-SCSI_Out__2__BYP EQU CYREG_PRT0_BYP\r
-SCSI_Out__2__CTL EQU CYREG_PRT0_CTL\r
-SCSI_Out__2__DM0 EQU CYREG_PRT0_DM0\r
-SCSI_Out__2__DM1 EQU CYREG_PRT0_DM1\r
-SCSI_Out__2__DM2 EQU CYREG_PRT0_DM2\r
-SCSI_Out__2__DR EQU CYREG_PRT0_DR\r
-SCSI_Out__2__INP_DIS EQU CYREG_PRT0_INP_DIS\r
-SCSI_Out__2__INTTYPE EQU CYREG_PICU0_INTTYPE7\r
-SCSI_Out__2__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
-SCSI_Out__2__LCD_EN EQU CYREG_PRT0_LCD_EN\r
-SCSI_Out__2__MASK EQU 0x80\r
-SCSI_Out__2__PC EQU CYREG_PRT0_PC7\r
-SCSI_Out__2__PORT EQU 0\r
-SCSI_Out__2__PRT EQU CYREG_PRT0_PRT\r
-SCSI_Out__2__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
-SCSI_Out__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
-SCSI_Out__2__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
-SCSI_Out__2__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
-SCSI_Out__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
-SCSI_Out__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
-SCSI_Out__2__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
-SCSI_Out__2__PS EQU CYREG_PRT0_PS\r
-SCSI_Out__2__SHIFT EQU 7\r
-SCSI_Out__2__SLW EQU CYREG_PRT0_SLW\r
-SCSI_Out__3__AG EQU CYREG_PRT0_AG\r
-SCSI_Out__3__AMUX EQU CYREG_PRT0_AMUX\r
-SCSI_Out__3__BIE EQU CYREG_PRT0_BIE\r
-SCSI_Out__3__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
-SCSI_Out__3__BYP EQU CYREG_PRT0_BYP\r
-SCSI_Out__3__CTL EQU CYREG_PRT0_CTL\r
-SCSI_Out__3__DM0 EQU CYREG_PRT0_DM0\r
-SCSI_Out__3__DM1 EQU CYREG_PRT0_DM1\r
-SCSI_Out__3__DM2 EQU CYREG_PRT0_DM2\r
-SCSI_Out__3__DR EQU CYREG_PRT0_DR\r
-SCSI_Out__3__INP_DIS EQU CYREG_PRT0_INP_DIS\r
-SCSI_Out__3__INTTYPE EQU CYREG_PICU0_INTTYPE6\r
-SCSI_Out__3__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
-SCSI_Out__3__LCD_EN EQU CYREG_PRT0_LCD_EN\r
-SCSI_Out__3__MASK EQU 0x40\r
-SCSI_Out__3__PC EQU CYREG_PRT0_PC6\r
-SCSI_Out__3__PORT EQU 0\r
-SCSI_Out__3__PRT EQU CYREG_PRT0_PRT\r
-SCSI_Out__3__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
-SCSI_Out__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
-SCSI_Out__3__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
-SCSI_Out__3__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
-SCSI_Out__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
-SCSI_Out__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
-SCSI_Out__3__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
-SCSI_Out__3__PS EQU CYREG_PRT0_PS\r
-SCSI_Out__3__SHIFT EQU 6\r
-SCSI_Out__3__SLW EQU CYREG_PRT0_SLW\r
-SCSI_Out__4__AG EQU CYREG_PRT0_AG\r
-SCSI_Out__4__AMUX EQU CYREG_PRT0_AMUX\r
-SCSI_Out__4__BIE EQU CYREG_PRT0_BIE\r
-SCSI_Out__4__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
-SCSI_Out__4__BYP EQU CYREG_PRT0_BYP\r
-SCSI_Out__4__CTL EQU CYREG_PRT0_CTL\r
-SCSI_Out__4__DM0 EQU CYREG_PRT0_DM0\r
-SCSI_Out__4__DM1 EQU CYREG_PRT0_DM1\r
-SCSI_Out__4__DM2 EQU CYREG_PRT0_DM2\r
-SCSI_Out__4__DR EQU CYREG_PRT0_DR\r
-SCSI_Out__4__INP_DIS EQU CYREG_PRT0_INP_DIS\r
-SCSI_Out__4__INTTYPE EQU CYREG_PICU0_INTTYPE5\r
-SCSI_Out__4__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
-SCSI_Out__4__LCD_EN EQU CYREG_PRT0_LCD_EN\r
-SCSI_Out__4__MASK EQU 0x20\r
-SCSI_Out__4__PC EQU CYREG_PRT0_PC5\r
-SCSI_Out__4__PORT EQU 0\r
-SCSI_Out__4__PRT EQU CYREG_PRT0_PRT\r
-SCSI_Out__4__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
-SCSI_Out__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
-SCSI_Out__4__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
-SCSI_Out__4__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
-SCSI_Out__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
-SCSI_Out__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
-SCSI_Out__4__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
-SCSI_Out__4__PS EQU CYREG_PRT0_PS\r
-SCSI_Out__4__SHIFT EQU 5\r
-SCSI_Out__4__SLW EQU CYREG_PRT0_SLW\r
-SCSI_Out__5__AG EQU CYREG_PRT0_AG\r
-SCSI_Out__5__AMUX EQU CYREG_PRT0_AMUX\r
-SCSI_Out__5__BIE EQU CYREG_PRT0_BIE\r
-SCSI_Out__5__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
-SCSI_Out__5__BYP EQU CYREG_PRT0_BYP\r
-SCSI_Out__5__CTL EQU CYREG_PRT0_CTL\r
-SCSI_Out__5__DM0 EQU CYREG_PRT0_DM0\r
-SCSI_Out__5__DM1 EQU CYREG_PRT0_DM1\r
-SCSI_Out__5__DM2 EQU CYREG_PRT0_DM2\r
-SCSI_Out__5__DR EQU CYREG_PRT0_DR\r
-SCSI_Out__5__INP_DIS EQU CYREG_PRT0_INP_DIS\r
-SCSI_Out__5__INTTYPE EQU CYREG_PICU0_INTTYPE4\r
-SCSI_Out__5__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
-SCSI_Out__5__LCD_EN EQU CYREG_PRT0_LCD_EN\r
-SCSI_Out__5__MASK EQU 0x10\r
-SCSI_Out__5__PC EQU CYREG_PRT0_PC4\r
-SCSI_Out__5__PORT EQU 0\r
-SCSI_Out__5__PRT EQU CYREG_PRT0_PRT\r
-SCSI_Out__5__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
-SCSI_Out__5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
-SCSI_Out__5__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
-SCSI_Out__5__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
-SCSI_Out__5__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
-SCSI_Out__5__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
-SCSI_Out__5__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
-SCSI_Out__5__PS EQU CYREG_PRT0_PS\r
-SCSI_Out__5__SHIFT EQU 4\r
-SCSI_Out__5__SLW EQU CYREG_PRT0_SLW\r
-SCSI_Out__6__AG EQU CYREG_PRT0_AG\r
-SCSI_Out__6__AMUX EQU CYREG_PRT0_AMUX\r
-SCSI_Out__6__BIE EQU CYREG_PRT0_BIE\r
-SCSI_Out__6__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
-SCSI_Out__6__BYP EQU CYREG_PRT0_BYP\r
-SCSI_Out__6__CTL EQU CYREG_PRT0_CTL\r
-SCSI_Out__6__DM0 EQU CYREG_PRT0_DM0\r
-SCSI_Out__6__DM1 EQU CYREG_PRT0_DM1\r
-SCSI_Out__6__DM2 EQU CYREG_PRT0_DM2\r
-SCSI_Out__6__DR EQU CYREG_PRT0_DR\r
-SCSI_Out__6__INP_DIS EQU CYREG_PRT0_INP_DIS\r
-SCSI_Out__6__INTTYPE EQU CYREG_PICU0_INTTYPE3\r
-SCSI_Out__6__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
-SCSI_Out__6__LCD_EN EQU CYREG_PRT0_LCD_EN\r
-SCSI_Out__6__MASK EQU 0x08\r
-SCSI_Out__6__PC EQU CYREG_PRT0_PC3\r
-SCSI_Out__6__PORT EQU 0\r
-SCSI_Out__6__PRT EQU CYREG_PRT0_PRT\r
-SCSI_Out__6__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
-SCSI_Out__6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
-SCSI_Out__6__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
-SCSI_Out__6__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
-SCSI_Out__6__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
-SCSI_Out__6__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
-SCSI_Out__6__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
-SCSI_Out__6__PS EQU CYREG_PRT0_PS\r
-SCSI_Out__6__SHIFT EQU 3\r
-SCSI_Out__6__SLW EQU CYREG_PRT0_SLW\r
-SCSI_Out__7__AG EQU CYREG_PRT0_AG\r
-SCSI_Out__7__AMUX EQU CYREG_PRT0_AMUX\r
-SCSI_Out__7__BIE EQU CYREG_PRT0_BIE\r
-SCSI_Out__7__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
-SCSI_Out__7__BYP EQU CYREG_PRT0_BYP\r
-SCSI_Out__7__CTL EQU CYREG_PRT0_CTL\r
-SCSI_Out__7__DM0 EQU CYREG_PRT0_DM0\r
-SCSI_Out__7__DM1 EQU CYREG_PRT0_DM1\r
-SCSI_Out__7__DM2 EQU CYREG_PRT0_DM2\r
-SCSI_Out__7__DR EQU CYREG_PRT0_DR\r
-SCSI_Out__7__INP_DIS EQU CYREG_PRT0_INP_DIS\r
-SCSI_Out__7__INTTYPE EQU CYREG_PICU0_INTTYPE2\r
-SCSI_Out__7__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
-SCSI_Out__7__LCD_EN EQU CYREG_PRT0_LCD_EN\r
-SCSI_Out__7__MASK EQU 0x04\r
-SCSI_Out__7__PC EQU CYREG_PRT0_PC2\r
-SCSI_Out__7__PORT EQU 0\r
-SCSI_Out__7__PRT EQU CYREG_PRT0_PRT\r
-SCSI_Out__7__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
-SCSI_Out__7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
-SCSI_Out__7__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
-SCSI_Out__7__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
-SCSI_Out__7__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
-SCSI_Out__7__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
-SCSI_Out__7__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
-SCSI_Out__7__PS EQU CYREG_PRT0_PS\r
-SCSI_Out__7__SHIFT EQU 2\r
-SCSI_Out__7__SLW EQU CYREG_PRT0_SLW\r
-SCSI_Out__8__AG EQU CYREG_PRT0_AG\r
-SCSI_Out__8__AMUX EQU CYREG_PRT0_AMUX\r
-SCSI_Out__8__BIE EQU CYREG_PRT0_BIE\r
-SCSI_Out__8__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
-SCSI_Out__8__BYP EQU CYREG_PRT0_BYP\r
-SCSI_Out__8__CTL EQU CYREG_PRT0_CTL\r
-SCSI_Out__8__DM0 EQU CYREG_PRT0_DM0\r
-SCSI_Out__8__DM1 EQU CYREG_PRT0_DM1\r
-SCSI_Out__8__DM2 EQU CYREG_PRT0_DM2\r
-SCSI_Out__8__DR EQU CYREG_PRT0_DR\r
-SCSI_Out__8__INP_DIS EQU CYREG_PRT0_INP_DIS\r
-SCSI_Out__8__INTTYPE EQU CYREG_PICU0_INTTYPE1\r
-SCSI_Out__8__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
-SCSI_Out__8__LCD_EN EQU CYREG_PRT0_LCD_EN\r
-SCSI_Out__8__MASK EQU 0x02\r
-SCSI_Out__8__PC EQU CYREG_PRT0_PC1\r
-SCSI_Out__8__PORT EQU 0\r
-SCSI_Out__8__PRT EQU CYREG_PRT0_PRT\r
-SCSI_Out__8__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
-SCSI_Out__8__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
-SCSI_Out__8__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
-SCSI_Out__8__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
-SCSI_Out__8__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
-SCSI_Out__8__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
-SCSI_Out__8__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
-SCSI_Out__8__PS EQU CYREG_PRT0_PS\r
-SCSI_Out__8__SHIFT EQU 1\r
-SCSI_Out__8__SLW EQU CYREG_PRT0_SLW\r
-SCSI_Out__9__AG EQU CYREG_PRT0_AG\r
-SCSI_Out__9__AMUX EQU CYREG_PRT0_AMUX\r
-SCSI_Out__9__BIE EQU CYREG_PRT0_BIE\r
-SCSI_Out__9__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
-SCSI_Out__9__BYP EQU CYREG_PRT0_BYP\r
-SCSI_Out__9__CTL EQU CYREG_PRT0_CTL\r
-SCSI_Out__9__DM0 EQU CYREG_PRT0_DM0\r
-SCSI_Out__9__DM1 EQU CYREG_PRT0_DM1\r
-SCSI_Out__9__DM2 EQU CYREG_PRT0_DM2\r
-SCSI_Out__9__DR EQU CYREG_PRT0_DR\r
-SCSI_Out__9__INP_DIS EQU CYREG_PRT0_INP_DIS\r
-SCSI_Out__9__INTTYPE EQU CYREG_PICU0_INTTYPE0\r
-SCSI_Out__9__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
-SCSI_Out__9__LCD_EN EQU CYREG_PRT0_LCD_EN\r
-SCSI_Out__9__MASK EQU 0x01\r
-SCSI_Out__9__PC EQU CYREG_PRT0_PC0\r
-SCSI_Out__9__PORT EQU 0\r
-SCSI_Out__9__PRT EQU CYREG_PRT0_PRT\r
-SCSI_Out__9__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
-SCSI_Out__9__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
-SCSI_Out__9__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
-SCSI_Out__9__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
-SCSI_Out__9__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
-SCSI_Out__9__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
-SCSI_Out__9__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
-SCSI_Out__9__PS EQU CYREG_PRT0_PS\r
-SCSI_Out__9__SHIFT EQU 0\r
-SCSI_Out__9__SLW EQU CYREG_PRT0_SLW\r
-SCSI_Out__ACK__AG EQU CYREG_PRT0_AG\r
-SCSI_Out__ACK__AMUX EQU CYREG_PRT0_AMUX\r
-SCSI_Out__ACK__BIE EQU CYREG_PRT0_BIE\r
-SCSI_Out__ACK__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
-SCSI_Out__ACK__BYP EQU CYREG_PRT0_BYP\r
-SCSI_Out__ACK__CTL EQU CYREG_PRT0_CTL\r
-SCSI_Out__ACK__DM0 EQU CYREG_PRT0_DM0\r
-SCSI_Out__ACK__DM1 EQU CYREG_PRT0_DM1\r
-SCSI_Out__ACK__DM2 EQU CYREG_PRT0_DM2\r
-SCSI_Out__ACK__DR EQU CYREG_PRT0_DR\r
-SCSI_Out__ACK__INP_DIS EQU CYREG_PRT0_INP_DIS\r
-SCSI_Out__ACK__INTTYPE EQU CYREG_PICU0_INTTYPE6\r
-SCSI_Out__ACK__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
-SCSI_Out__ACK__LCD_EN EQU CYREG_PRT0_LCD_EN\r
-SCSI_Out__ACK__MASK EQU 0x40\r
-SCSI_Out__ACK__PC EQU CYREG_PRT0_PC6\r
-SCSI_Out__ACK__PORT EQU 0\r
-SCSI_Out__ACK__PRT EQU CYREG_PRT0_PRT\r
-SCSI_Out__ACK__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
-SCSI_Out__ACK__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
-SCSI_Out__ACK__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
-SCSI_Out__ACK__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
-SCSI_Out__ACK__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
-SCSI_Out__ACK__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
-SCSI_Out__ACK__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
-SCSI_Out__ACK__PS EQU CYREG_PRT0_PS\r
-SCSI_Out__ACK__SHIFT EQU 6\r
-SCSI_Out__ACK__SLW EQU CYREG_PRT0_SLW\r
-SCSI_Out__ATN__AG EQU CYREG_PRT4_AG\r
-SCSI_Out__ATN__AMUX EQU CYREG_PRT4_AMUX\r
-SCSI_Out__ATN__BIE EQU CYREG_PRT4_BIE\r
-SCSI_Out__ATN__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
-SCSI_Out__ATN__BYP EQU CYREG_PRT4_BYP\r
-SCSI_Out__ATN__CTL EQU CYREG_PRT4_CTL\r
-SCSI_Out__ATN__DM0 EQU CYREG_PRT4_DM0\r
-SCSI_Out__ATN__DM1 EQU CYREG_PRT4_DM1\r
-SCSI_Out__ATN__DM2 EQU CYREG_PRT4_DM2\r
-SCSI_Out__ATN__DR EQU CYREG_PRT4_DR\r
-SCSI_Out__ATN__INP_DIS EQU CYREG_PRT4_INP_DIS\r
-SCSI_Out__ATN__INTTYPE EQU CYREG_PICU4_INTTYPE2\r
-SCSI_Out__ATN__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
-SCSI_Out__ATN__LCD_EN EQU CYREG_PRT4_LCD_EN\r
-SCSI_Out__ATN__MASK EQU 0x04\r
-SCSI_Out__ATN__PC EQU CYREG_PRT4_PC2\r
-SCSI_Out__ATN__PORT EQU 4\r
-SCSI_Out__ATN__PRT EQU CYREG_PRT4_PRT\r
-SCSI_Out__ATN__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
-SCSI_Out__ATN__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
-SCSI_Out__ATN__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
-SCSI_Out__ATN__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
-SCSI_Out__ATN__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
-SCSI_Out__ATN__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
-SCSI_Out__ATN__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
-SCSI_Out__ATN__PS EQU CYREG_PRT4_PS\r
-SCSI_Out__ATN__SHIFT EQU 2\r
-SCSI_Out__ATN__SLW EQU CYREG_PRT4_SLW\r
-SCSI_Out__BSY__AG EQU CYREG_PRT0_AG\r
-SCSI_Out__BSY__AMUX EQU CYREG_PRT0_AMUX\r
-SCSI_Out__BSY__BIE EQU CYREG_PRT0_BIE\r
-SCSI_Out__BSY__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
-SCSI_Out__BSY__BYP EQU CYREG_PRT0_BYP\r
-SCSI_Out__BSY__CTL EQU CYREG_PRT0_CTL\r
-SCSI_Out__BSY__DM0 EQU CYREG_PRT0_DM0\r
-SCSI_Out__BSY__DM1 EQU CYREG_PRT0_DM1\r
-SCSI_Out__BSY__DM2 EQU CYREG_PRT0_DM2\r
-SCSI_Out__BSY__DR EQU CYREG_PRT0_DR\r
-SCSI_Out__BSY__INP_DIS EQU CYREG_PRT0_INP_DIS\r
-SCSI_Out__BSY__INTTYPE EQU CYREG_PICU0_INTTYPE7\r
-SCSI_Out__BSY__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
-SCSI_Out__BSY__LCD_EN EQU CYREG_PRT0_LCD_EN\r
-SCSI_Out__BSY__MASK EQU 0x80\r
-SCSI_Out__BSY__PC EQU CYREG_PRT0_PC7\r
-SCSI_Out__BSY__PORT EQU 0\r
-SCSI_Out__BSY__PRT EQU CYREG_PRT0_PRT\r
-SCSI_Out__BSY__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
-SCSI_Out__BSY__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
-SCSI_Out__BSY__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
-SCSI_Out__BSY__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
-SCSI_Out__BSY__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
-SCSI_Out__BSY__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
-SCSI_Out__BSY__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
-SCSI_Out__BSY__PS EQU CYREG_PRT0_PS\r
-SCSI_Out__BSY__SHIFT EQU 7\r
-SCSI_Out__BSY__SLW EQU CYREG_PRT0_SLW\r
-SCSI_Out__CD_raw__AG EQU CYREG_PRT0_AG\r
-SCSI_Out__CD_raw__AMUX EQU CYREG_PRT0_AMUX\r
-SCSI_Out__CD_raw__BIE EQU CYREG_PRT0_BIE\r
-SCSI_Out__CD_raw__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
-SCSI_Out__CD_raw__BYP EQU CYREG_PRT0_BYP\r
-SCSI_Out__CD_raw__CTL EQU CYREG_PRT0_CTL\r
-SCSI_Out__CD_raw__DM0 EQU CYREG_PRT0_DM0\r
-SCSI_Out__CD_raw__DM1 EQU CYREG_PRT0_DM1\r
-SCSI_Out__CD_raw__DM2 EQU CYREG_PRT0_DM2\r
-SCSI_Out__CD_raw__DR EQU CYREG_PRT0_DR\r
-SCSI_Out__CD_raw__INP_DIS EQU CYREG_PRT0_INP_DIS\r
-SCSI_Out__CD_raw__INTTYPE EQU CYREG_PICU0_INTTYPE2\r
-SCSI_Out__CD_raw__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
-SCSI_Out__CD_raw__LCD_EN EQU CYREG_PRT0_LCD_EN\r
-SCSI_Out__CD_raw__MASK EQU 0x04\r
-SCSI_Out__CD_raw__PC EQU CYREG_PRT0_PC2\r
-SCSI_Out__CD_raw__PORT EQU 0\r
-SCSI_Out__CD_raw__PRT EQU CYREG_PRT0_PRT\r
-SCSI_Out__CD_raw__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
-SCSI_Out__CD_raw__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
-SCSI_Out__CD_raw__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
-SCSI_Out__CD_raw__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
-SCSI_Out__CD_raw__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
-SCSI_Out__CD_raw__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
-SCSI_Out__CD_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
-SCSI_Out__CD_raw__PS EQU CYREG_PRT0_PS\r
-SCSI_Out__CD_raw__SHIFT EQU 2\r
-SCSI_Out__CD_raw__SLW EQU CYREG_PRT0_SLW\r
-SCSI_Out__DBP_raw__AG EQU CYREG_PRT4_AG\r
-SCSI_Out__DBP_raw__AMUX EQU CYREG_PRT4_AMUX\r
-SCSI_Out__DBP_raw__BIE EQU CYREG_PRT4_BIE\r
-SCSI_Out__DBP_raw__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
-SCSI_Out__DBP_raw__BYP EQU CYREG_PRT4_BYP\r
-SCSI_Out__DBP_raw__CTL EQU CYREG_PRT4_CTL\r
-SCSI_Out__DBP_raw__DM0 EQU CYREG_PRT4_DM0\r
-SCSI_Out__DBP_raw__DM1 EQU CYREG_PRT4_DM1\r
-SCSI_Out__DBP_raw__DM2 EQU CYREG_PRT4_DM2\r
-SCSI_Out__DBP_raw__DR EQU CYREG_PRT4_DR\r
-SCSI_Out__DBP_raw__INP_DIS EQU CYREG_PRT4_INP_DIS\r
-SCSI_Out__DBP_raw__INTTYPE EQU CYREG_PICU4_INTTYPE3\r
-SCSI_Out__DBP_raw__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
-SCSI_Out__DBP_raw__LCD_EN EQU CYREG_PRT4_LCD_EN\r
-SCSI_Out__DBP_raw__MASK EQU 0x08\r
-SCSI_Out__DBP_raw__PC EQU CYREG_PRT4_PC3\r
-SCSI_Out__DBP_raw__PORT EQU 4\r
-SCSI_Out__DBP_raw__PRT EQU CYREG_PRT4_PRT\r
-SCSI_Out__DBP_raw__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
-SCSI_Out__DBP_raw__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
-SCSI_Out__DBP_raw__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
-SCSI_Out__DBP_raw__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
-SCSI_Out__DBP_raw__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
-SCSI_Out__DBP_raw__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
-SCSI_Out__DBP_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
-SCSI_Out__DBP_raw__PS EQU CYREG_PRT4_PS\r
-SCSI_Out__DBP_raw__SHIFT EQU 3\r
-SCSI_Out__DBP_raw__SLW EQU CYREG_PRT4_SLW\r
-SCSI_Out__IO_raw__AG EQU CYREG_PRT0_AG\r
-SCSI_Out__IO_raw__AMUX EQU CYREG_PRT0_AMUX\r
-SCSI_Out__IO_raw__BIE EQU CYREG_PRT0_BIE\r
-SCSI_Out__IO_raw__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
-SCSI_Out__IO_raw__BYP EQU CYREG_PRT0_BYP\r
-SCSI_Out__IO_raw__CTL EQU CYREG_PRT0_CTL\r
-SCSI_Out__IO_raw__DM0 EQU CYREG_PRT0_DM0\r
-SCSI_Out__IO_raw__DM1 EQU CYREG_PRT0_DM1\r
-SCSI_Out__IO_raw__DM2 EQU CYREG_PRT0_DM2\r
-SCSI_Out__IO_raw__DR EQU CYREG_PRT0_DR\r
-SCSI_Out__IO_raw__INP_DIS EQU CYREG_PRT0_INP_DIS\r
-SCSI_Out__IO_raw__INTTYPE EQU CYREG_PICU0_INTTYPE0\r
-SCSI_Out__IO_raw__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
-SCSI_Out__IO_raw__LCD_EN EQU CYREG_PRT0_LCD_EN\r
-SCSI_Out__IO_raw__MASK EQU 0x01\r
-SCSI_Out__IO_raw__PC EQU CYREG_PRT0_PC0\r
-SCSI_Out__IO_raw__PORT EQU 0\r
-SCSI_Out__IO_raw__PRT EQU CYREG_PRT0_PRT\r
-SCSI_Out__IO_raw__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
-SCSI_Out__IO_raw__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
-SCSI_Out__IO_raw__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
-SCSI_Out__IO_raw__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
-SCSI_Out__IO_raw__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
-SCSI_Out__IO_raw__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
-SCSI_Out__IO_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
-SCSI_Out__IO_raw__PS EQU CYREG_PRT0_PS\r
-SCSI_Out__IO_raw__SHIFT EQU 0\r
-SCSI_Out__IO_raw__SLW EQU CYREG_PRT0_SLW\r
-SCSI_Out__MSG_raw__AG EQU CYREG_PRT0_AG\r
-SCSI_Out__MSG_raw__AMUX EQU CYREG_PRT0_AMUX\r
-SCSI_Out__MSG_raw__BIE EQU CYREG_PRT0_BIE\r
-SCSI_Out__MSG_raw__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
-SCSI_Out__MSG_raw__BYP EQU CYREG_PRT0_BYP\r
-SCSI_Out__MSG_raw__CTL EQU CYREG_PRT0_CTL\r
-SCSI_Out__MSG_raw__DM0 EQU CYREG_PRT0_DM0\r
-SCSI_Out__MSG_raw__DM1 EQU CYREG_PRT0_DM1\r
-SCSI_Out__MSG_raw__DM2 EQU CYREG_PRT0_DM2\r
-SCSI_Out__MSG_raw__DR EQU CYREG_PRT0_DR\r
-SCSI_Out__MSG_raw__INP_DIS EQU CYREG_PRT0_INP_DIS\r
-SCSI_Out__MSG_raw__INTTYPE EQU CYREG_PICU0_INTTYPE4\r
-SCSI_Out__MSG_raw__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
-SCSI_Out__MSG_raw__LCD_EN EQU CYREG_PRT0_LCD_EN\r
-SCSI_Out__MSG_raw__MASK EQU 0x10\r
-SCSI_Out__MSG_raw__PC EQU CYREG_PRT0_PC4\r
-SCSI_Out__MSG_raw__PORT EQU 0\r
-SCSI_Out__MSG_raw__PRT EQU CYREG_PRT0_PRT\r
-SCSI_Out__MSG_raw__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
-SCSI_Out__MSG_raw__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
-SCSI_Out__MSG_raw__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
-SCSI_Out__MSG_raw__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
-SCSI_Out__MSG_raw__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
-SCSI_Out__MSG_raw__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
-SCSI_Out__MSG_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
-SCSI_Out__MSG_raw__PS EQU CYREG_PRT0_PS\r
-SCSI_Out__MSG_raw__SHIFT EQU 4\r
-SCSI_Out__MSG_raw__SLW EQU CYREG_PRT0_SLW\r
-SCSI_Out__REQ__AG EQU CYREG_PRT0_AG\r
-SCSI_Out__REQ__AMUX EQU CYREG_PRT0_AMUX\r
-SCSI_Out__REQ__BIE EQU CYREG_PRT0_BIE\r
-SCSI_Out__REQ__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
-SCSI_Out__REQ__BYP EQU CYREG_PRT0_BYP\r
-SCSI_Out__REQ__CTL EQU CYREG_PRT0_CTL\r
-SCSI_Out__REQ__DM0 EQU CYREG_PRT0_DM0\r
-SCSI_Out__REQ__DM1 EQU CYREG_PRT0_DM1\r
-SCSI_Out__REQ__DM2 EQU CYREG_PRT0_DM2\r
-SCSI_Out__REQ__DR EQU CYREG_PRT0_DR\r
-SCSI_Out__REQ__INP_DIS EQU CYREG_PRT0_INP_DIS\r
-SCSI_Out__REQ__INTTYPE EQU CYREG_PICU0_INTTYPE1\r
-SCSI_Out__REQ__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
-SCSI_Out__REQ__LCD_EN EQU CYREG_PRT0_LCD_EN\r
-SCSI_Out__REQ__MASK EQU 0x02\r
-SCSI_Out__REQ__PC EQU CYREG_PRT0_PC1\r
-SCSI_Out__REQ__PORT EQU 0\r
-SCSI_Out__REQ__PRT EQU CYREG_PRT0_PRT\r
-SCSI_Out__REQ__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
-SCSI_Out__REQ__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
-SCSI_Out__REQ__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
-SCSI_Out__REQ__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
-SCSI_Out__REQ__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
-SCSI_Out__REQ__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
-SCSI_Out__REQ__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
-SCSI_Out__REQ__PS EQU CYREG_PRT0_PS\r
-SCSI_Out__REQ__SHIFT EQU 1\r
-SCSI_Out__REQ__SLW EQU CYREG_PRT0_SLW\r
-SCSI_Out__RST__AG EQU CYREG_PRT0_AG\r
-SCSI_Out__RST__AMUX EQU CYREG_PRT0_AMUX\r
-SCSI_Out__RST__BIE EQU CYREG_PRT0_BIE\r
-SCSI_Out__RST__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
-SCSI_Out__RST__BYP EQU CYREG_PRT0_BYP\r
-SCSI_Out__RST__CTL EQU CYREG_PRT0_CTL\r
-SCSI_Out__RST__DM0 EQU CYREG_PRT0_DM0\r
-SCSI_Out__RST__DM1 EQU CYREG_PRT0_DM1\r
-SCSI_Out__RST__DM2 EQU CYREG_PRT0_DM2\r
-SCSI_Out__RST__DR EQU CYREG_PRT0_DR\r
-SCSI_Out__RST__INP_DIS EQU CYREG_PRT0_INP_DIS\r
-SCSI_Out__RST__INTTYPE EQU CYREG_PICU0_INTTYPE5\r
-SCSI_Out__RST__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
-SCSI_Out__RST__LCD_EN EQU CYREG_PRT0_LCD_EN\r
-SCSI_Out__RST__MASK EQU 0x20\r
-SCSI_Out__RST__PC EQU CYREG_PRT0_PC5\r
-SCSI_Out__RST__PORT EQU 0\r
-SCSI_Out__RST__PRT EQU CYREG_PRT0_PRT\r
-SCSI_Out__RST__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
-SCSI_Out__RST__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
-SCSI_Out__RST__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
-SCSI_Out__RST__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
-SCSI_Out__RST__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
-SCSI_Out__RST__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
-SCSI_Out__RST__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
-SCSI_Out__RST__PS EQU CYREG_PRT0_PS\r
-SCSI_Out__RST__SHIFT EQU 5\r
-SCSI_Out__RST__SLW EQU CYREG_PRT0_SLW\r
-SCSI_Out__SEL__AG EQU CYREG_PRT0_AG\r
-SCSI_Out__SEL__AMUX EQU CYREG_PRT0_AMUX\r
-SCSI_Out__SEL__BIE EQU CYREG_PRT0_BIE\r
-SCSI_Out__SEL__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
-SCSI_Out__SEL__BYP EQU CYREG_PRT0_BYP\r
-SCSI_Out__SEL__CTL EQU CYREG_PRT0_CTL\r
-SCSI_Out__SEL__DM0 EQU CYREG_PRT0_DM0\r
-SCSI_Out__SEL__DM1 EQU CYREG_PRT0_DM1\r
-SCSI_Out__SEL__DM2 EQU CYREG_PRT0_DM2\r
-SCSI_Out__SEL__DR EQU CYREG_PRT0_DR\r
-SCSI_Out__SEL__INP_DIS EQU CYREG_PRT0_INP_DIS\r
-SCSI_Out__SEL__INTTYPE EQU CYREG_PICU0_INTTYPE3\r
-SCSI_Out__SEL__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
-SCSI_Out__SEL__LCD_EN EQU CYREG_PRT0_LCD_EN\r
-SCSI_Out__SEL__MASK EQU 0x08\r
-SCSI_Out__SEL__PC EQU CYREG_PRT0_PC3\r
-SCSI_Out__SEL__PORT EQU 0\r
-SCSI_Out__SEL__PRT EQU CYREG_PRT0_PRT\r
-SCSI_Out__SEL__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
-SCSI_Out__SEL__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
-SCSI_Out__SEL__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
-SCSI_Out__SEL__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
-SCSI_Out__SEL__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
-SCSI_Out__SEL__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
-SCSI_Out__SEL__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
-SCSI_Out__SEL__PS EQU CYREG_PRT0_PS\r
-SCSI_Out__SEL__SHIFT EQU 3\r
-SCSI_Out__SEL__SLW EQU CYREG_PRT0_SLW\r
-SCSI_Out_Bits_Sync_ctrl_reg__0__MASK EQU 0x01\r
-SCSI_Out_Bits_Sync_ctrl_reg__0__POS EQU 0\r
-SCSI_Out_Bits_Sync_ctrl_reg__1__MASK EQU 0x02\r
-SCSI_Out_Bits_Sync_ctrl_reg__1__POS EQU 1\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB08_09_ACTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB08_09_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB08_09_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB08_09_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB08_09_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB08_09_MSK\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB08_09_MSK\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB08_09_MSK\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB08_09_MSK\r
-SCSI_Out_Bits_Sync_ctrl_reg__2__MASK EQU 0x04\r
-SCSI_Out_Bits_Sync_ctrl_reg__2__POS EQU 2\r
-SCSI_Out_Bits_Sync_ctrl_reg__3__MASK EQU 0x08\r
-SCSI_Out_Bits_Sync_ctrl_reg__3__POS EQU 3\r
-SCSI_Out_Bits_Sync_ctrl_reg__4__MASK EQU 0x10\r
-SCSI_Out_Bits_Sync_ctrl_reg__4__POS EQU 4\r
-SCSI_Out_Bits_Sync_ctrl_reg__5__MASK EQU 0x20\r
-SCSI_Out_Bits_Sync_ctrl_reg__5__POS EQU 5\r
-SCSI_Out_Bits_Sync_ctrl_reg__6__MASK EQU 0x40\r
-SCSI_Out_Bits_Sync_ctrl_reg__6__POS EQU 6\r
-SCSI_Out_Bits_Sync_ctrl_reg__7__MASK EQU 0x80\r
-SCSI_Out_Bits_Sync_ctrl_reg__7__POS EQU 7\r
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB08_ACTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B1_UDB08_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B1_UDB08_ST_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B1_UDB08_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B1_UDB08_ST_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__MASK EQU 0xFF\r
-SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB08_MSK_ACTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB08_MSK_ACTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B1_UDB08_MSK\r
-SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01\r
-SCSI_Out_Ctl_Sync_ctrl_reg__0__POS EQU 0\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB08_09_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB08_09_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB08_09_MSK\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB08_09_MSK\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK\r
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB08_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB08_ST_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB08_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB08_ST_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__MASK EQU 0x01\r
-SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB08_MSK\r
-SCSI_Out_DBx__0__AG EQU CYREG_PRT6_AG\r
-SCSI_Out_DBx__0__AMUX EQU CYREG_PRT6_AMUX\r
-SCSI_Out_DBx__0__BIE EQU CYREG_PRT6_BIE\r
-SCSI_Out_DBx__0__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
-SCSI_Out_DBx__0__BYP EQU CYREG_PRT6_BYP\r
-SCSI_Out_DBx__0__CTL EQU CYREG_PRT6_CTL\r
-SCSI_Out_DBx__0__DM0 EQU CYREG_PRT6_DM0\r
-SCSI_Out_DBx__0__DM1 EQU CYREG_PRT6_DM1\r
-SCSI_Out_DBx__0__DM2 EQU CYREG_PRT6_DM2\r
-SCSI_Out_DBx__0__DR EQU CYREG_PRT6_DR\r
-SCSI_Out_DBx__0__INP_DIS EQU CYREG_PRT6_INP_DIS\r
-SCSI_Out_DBx__0__INTTYPE EQU CYREG_PICU6_INTTYPE3\r
-SCSI_Out_DBx__0__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
-SCSI_Out_DBx__0__LCD_EN EQU CYREG_PRT6_LCD_EN\r
-SCSI_Out_DBx__0__MASK EQU 0x08\r
-SCSI_Out_DBx__0__PC EQU CYREG_PRT6_PC3\r
-SCSI_Out_DBx__0__PORT EQU 6\r
-SCSI_Out_DBx__0__PRT EQU CYREG_PRT6_PRT\r
-SCSI_Out_DBx__0__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
-SCSI_Out_DBx__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
-SCSI_Out_DBx__0__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
-SCSI_Out_DBx__0__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
-SCSI_Out_DBx__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
-SCSI_Out_DBx__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
-SCSI_Out_DBx__0__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
-SCSI_Out_DBx__0__PS EQU CYREG_PRT6_PS\r
-SCSI_Out_DBx__0__SHIFT EQU 3\r
-SCSI_Out_DBx__0__SLW EQU CYREG_PRT6_SLW\r
-SCSI_Out_DBx__1__AG EQU CYREG_PRT6_AG\r
-SCSI_Out_DBx__1__AMUX EQU CYREG_PRT6_AMUX\r
-SCSI_Out_DBx__1__BIE EQU CYREG_PRT6_BIE\r
-SCSI_Out_DBx__1__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
-SCSI_Out_DBx__1__BYP EQU CYREG_PRT6_BYP\r
-SCSI_Out_DBx__1__CTL EQU CYREG_PRT6_CTL\r
-SCSI_Out_DBx__1__DM0 EQU CYREG_PRT6_DM0\r
-SCSI_Out_DBx__1__DM1 EQU CYREG_PRT6_DM1\r
-SCSI_Out_DBx__1__DM2 EQU CYREG_PRT6_DM2\r
-SCSI_Out_DBx__1__DR EQU CYREG_PRT6_DR\r
-SCSI_Out_DBx__1__INP_DIS EQU CYREG_PRT6_INP_DIS\r
-SCSI_Out_DBx__1__INTTYPE EQU CYREG_PICU6_INTTYPE2\r
-SCSI_Out_DBx__1__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
-SCSI_Out_DBx__1__LCD_EN EQU CYREG_PRT6_LCD_EN\r
-SCSI_Out_DBx__1__MASK EQU 0x04\r
-SCSI_Out_DBx__1__PC EQU CYREG_PRT6_PC2\r
-SCSI_Out_DBx__1__PORT EQU 6\r
-SCSI_Out_DBx__1__PRT EQU CYREG_PRT6_PRT\r
-SCSI_Out_DBx__1__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
-SCSI_Out_DBx__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
-SCSI_Out_DBx__1__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
-SCSI_Out_DBx__1__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
-SCSI_Out_DBx__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
-SCSI_Out_DBx__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
-SCSI_Out_DBx__1__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
-SCSI_Out_DBx__1__PS EQU CYREG_PRT6_PS\r
-SCSI_Out_DBx__1__SHIFT EQU 2\r
-SCSI_Out_DBx__1__SLW EQU CYREG_PRT6_SLW\r
-SCSI_Out_DBx__2__AG EQU CYREG_PRT6_AG\r
-SCSI_Out_DBx__2__AMUX EQU CYREG_PRT6_AMUX\r
-SCSI_Out_DBx__2__BIE EQU CYREG_PRT6_BIE\r
-SCSI_Out_DBx__2__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
-SCSI_Out_DBx__2__BYP EQU CYREG_PRT6_BYP\r
-SCSI_Out_DBx__2__CTL EQU CYREG_PRT6_CTL\r
-SCSI_Out_DBx__2__DM0 EQU CYREG_PRT6_DM0\r
-SCSI_Out_DBx__2__DM1 EQU CYREG_PRT6_DM1\r
-SCSI_Out_DBx__2__DM2 EQU CYREG_PRT6_DM2\r
-SCSI_Out_DBx__2__DR EQU CYREG_PRT6_DR\r
-SCSI_Out_DBx__2__INP_DIS EQU CYREG_PRT6_INP_DIS\r
-SCSI_Out_DBx__2__INTTYPE EQU CYREG_PICU6_INTTYPE1\r
-SCSI_Out_DBx__2__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
-SCSI_Out_DBx__2__LCD_EN EQU CYREG_PRT6_LCD_EN\r
-SCSI_Out_DBx__2__MASK EQU 0x02\r
-SCSI_Out_DBx__2__PC EQU CYREG_PRT6_PC1\r
-SCSI_Out_DBx__2__PORT EQU 6\r
-SCSI_Out_DBx__2__PRT EQU CYREG_PRT6_PRT\r
-SCSI_Out_DBx__2__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
-SCSI_Out_DBx__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
-SCSI_Out_DBx__2__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
-SCSI_Out_DBx__2__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
-SCSI_Out_DBx__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
-SCSI_Out_DBx__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
-SCSI_Out_DBx__2__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
-SCSI_Out_DBx__2__PS EQU CYREG_PRT6_PS\r
-SCSI_Out_DBx__2__SHIFT EQU 1\r
-SCSI_Out_DBx__2__SLW EQU CYREG_PRT6_SLW\r
-SCSI_Out_DBx__3__AG EQU CYREG_PRT6_AG\r
-SCSI_Out_DBx__3__AMUX EQU CYREG_PRT6_AMUX\r
-SCSI_Out_DBx__3__BIE EQU CYREG_PRT6_BIE\r
-SCSI_Out_DBx__3__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
-SCSI_Out_DBx__3__BYP EQU CYREG_PRT6_BYP\r
-SCSI_Out_DBx__3__CTL EQU CYREG_PRT6_CTL\r
-SCSI_Out_DBx__3__DM0 EQU CYREG_PRT6_DM0\r
-SCSI_Out_DBx__3__DM1 EQU CYREG_PRT6_DM1\r
-SCSI_Out_DBx__3__DM2 EQU CYREG_PRT6_DM2\r
-SCSI_Out_DBx__3__DR EQU CYREG_PRT6_DR\r
-SCSI_Out_DBx__3__INP_DIS EQU CYREG_PRT6_INP_DIS\r
-SCSI_Out_DBx__3__INTTYPE EQU CYREG_PICU6_INTTYPE0\r
-SCSI_Out_DBx__3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
-SCSI_Out_DBx__3__LCD_EN EQU CYREG_PRT6_LCD_EN\r
-SCSI_Out_DBx__3__MASK EQU 0x01\r
-SCSI_Out_DBx__3__PC EQU CYREG_PRT6_PC0\r
-SCSI_Out_DBx__3__PORT EQU 6\r
-SCSI_Out_DBx__3__PRT EQU CYREG_PRT6_PRT\r
-SCSI_Out_DBx__3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
-SCSI_Out_DBx__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
-SCSI_Out_DBx__3__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
-SCSI_Out_DBx__3__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
-SCSI_Out_DBx__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
-SCSI_Out_DBx__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
-SCSI_Out_DBx__3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
-SCSI_Out_DBx__3__PS EQU CYREG_PRT6_PS\r
-SCSI_Out_DBx__3__SHIFT EQU 0\r
-SCSI_Out_DBx__3__SLW EQU CYREG_PRT6_SLW\r
-SCSI_Out_DBx__4__AG EQU CYREG_PRT4_AG\r
-SCSI_Out_DBx__4__AMUX EQU CYREG_PRT4_AMUX\r
-SCSI_Out_DBx__4__BIE EQU CYREG_PRT4_BIE\r
-SCSI_Out_DBx__4__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
-SCSI_Out_DBx__4__BYP EQU CYREG_PRT4_BYP\r
-SCSI_Out_DBx__4__CTL EQU CYREG_PRT4_CTL\r
-SCSI_Out_DBx__4__DM0 EQU CYREG_PRT4_DM0\r
-SCSI_Out_DBx__4__DM1 EQU CYREG_PRT4_DM1\r
-SCSI_Out_DBx__4__DM2 EQU CYREG_PRT4_DM2\r
-SCSI_Out_DBx__4__DR EQU CYREG_PRT4_DR\r
-SCSI_Out_DBx__4__INP_DIS EQU CYREG_PRT4_INP_DIS\r
-SCSI_Out_DBx__4__INTTYPE EQU CYREG_PICU4_INTTYPE7\r
-SCSI_Out_DBx__4__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
-SCSI_Out_DBx__4__LCD_EN EQU CYREG_PRT4_LCD_EN\r
-SCSI_Out_DBx__4__MASK EQU 0x80\r
-SCSI_Out_DBx__4__PC EQU CYREG_PRT4_PC7\r
-SCSI_Out_DBx__4__PORT EQU 4\r
-SCSI_Out_DBx__4__PRT EQU CYREG_PRT4_PRT\r
-SCSI_Out_DBx__4__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
-SCSI_Out_DBx__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
-SCSI_Out_DBx__4__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
-SCSI_Out_DBx__4__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
-SCSI_Out_DBx__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
-SCSI_Out_DBx__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
-SCSI_Out_DBx__4__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
-SCSI_Out_DBx__4__PS EQU CYREG_PRT4_PS\r
-SCSI_Out_DBx__4__SHIFT EQU 7\r
-SCSI_Out_DBx__4__SLW EQU CYREG_PRT4_SLW\r
-SCSI_Out_DBx__5__AG EQU CYREG_PRT4_AG\r
-SCSI_Out_DBx__5__AMUX EQU CYREG_PRT4_AMUX\r
-SCSI_Out_DBx__5__BIE EQU CYREG_PRT4_BIE\r
-SCSI_Out_DBx__5__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
-SCSI_Out_DBx__5__BYP EQU CYREG_PRT4_BYP\r
-SCSI_Out_DBx__5__CTL EQU CYREG_PRT4_CTL\r
-SCSI_Out_DBx__5__DM0 EQU CYREG_PRT4_DM0\r
-SCSI_Out_DBx__5__DM1 EQU CYREG_PRT4_DM1\r
-SCSI_Out_DBx__5__DM2 EQU CYREG_PRT4_DM2\r
-SCSI_Out_DBx__5__DR EQU CYREG_PRT4_DR\r
-SCSI_Out_DBx__5__INP_DIS EQU CYREG_PRT4_INP_DIS\r
-SCSI_Out_DBx__5__INTTYPE EQU CYREG_PICU4_INTTYPE6\r
-SCSI_Out_DBx__5__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
-SCSI_Out_DBx__5__LCD_EN EQU CYREG_PRT4_LCD_EN\r
-SCSI_Out_DBx__5__MASK EQU 0x40\r
-SCSI_Out_DBx__5__PC EQU CYREG_PRT4_PC6\r
-SCSI_Out_DBx__5__PORT EQU 4\r
-SCSI_Out_DBx__5__PRT EQU CYREG_PRT4_PRT\r
-SCSI_Out_DBx__5__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
-SCSI_Out_DBx__5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
-SCSI_Out_DBx__5__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
-SCSI_Out_DBx__5__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
-SCSI_Out_DBx__5__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
-SCSI_Out_DBx__5__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
-SCSI_Out_DBx__5__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
-SCSI_Out_DBx__5__PS EQU CYREG_PRT4_PS\r
-SCSI_Out_DBx__5__SHIFT EQU 6\r
-SCSI_Out_DBx__5__SLW EQU CYREG_PRT4_SLW\r
-SCSI_Out_DBx__6__AG EQU CYREG_PRT4_AG\r
-SCSI_Out_DBx__6__AMUX EQU CYREG_PRT4_AMUX\r
-SCSI_Out_DBx__6__BIE EQU CYREG_PRT4_BIE\r
-SCSI_Out_DBx__6__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
-SCSI_Out_DBx__6__BYP EQU CYREG_PRT4_BYP\r
-SCSI_Out_DBx__6__CTL EQU CYREG_PRT4_CTL\r
-SCSI_Out_DBx__6__DM0 EQU CYREG_PRT4_DM0\r
-SCSI_Out_DBx__6__DM1 EQU CYREG_PRT4_DM1\r
-SCSI_Out_DBx__6__DM2 EQU CYREG_PRT4_DM2\r
-SCSI_Out_DBx__6__DR EQU CYREG_PRT4_DR\r
-SCSI_Out_DBx__6__INP_DIS EQU CYREG_PRT4_INP_DIS\r
-SCSI_Out_DBx__6__INTTYPE EQU CYREG_PICU4_INTTYPE5\r
-SCSI_Out_DBx__6__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
-SCSI_Out_DBx__6__LCD_EN EQU CYREG_PRT4_LCD_EN\r
-SCSI_Out_DBx__6__MASK EQU 0x20\r
-SCSI_Out_DBx__6__PC EQU CYREG_PRT4_PC5\r
-SCSI_Out_DBx__6__PORT EQU 4\r
-SCSI_Out_DBx__6__PRT EQU CYREG_PRT4_PRT\r
-SCSI_Out_DBx__6__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
-SCSI_Out_DBx__6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
-SCSI_Out_DBx__6__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
-SCSI_Out_DBx__6__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
-SCSI_Out_DBx__6__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
-SCSI_Out_DBx__6__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
-SCSI_Out_DBx__6__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
-SCSI_Out_DBx__6__PS EQU CYREG_PRT4_PS\r
-SCSI_Out_DBx__6__SHIFT EQU 5\r
-SCSI_Out_DBx__6__SLW EQU CYREG_PRT4_SLW\r
-SCSI_Out_DBx__7__AG EQU CYREG_PRT4_AG\r
-SCSI_Out_DBx__7__AMUX EQU CYREG_PRT4_AMUX\r
-SCSI_Out_DBx__7__BIE EQU CYREG_PRT4_BIE\r
-SCSI_Out_DBx__7__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
-SCSI_Out_DBx__7__BYP EQU CYREG_PRT4_BYP\r
-SCSI_Out_DBx__7__CTL EQU CYREG_PRT4_CTL\r
-SCSI_Out_DBx__7__DM0 EQU CYREG_PRT4_DM0\r
-SCSI_Out_DBx__7__DM1 EQU CYREG_PRT4_DM1\r
-SCSI_Out_DBx__7__DM2 EQU CYREG_PRT4_DM2\r
-SCSI_Out_DBx__7__DR EQU CYREG_PRT4_DR\r
-SCSI_Out_DBx__7__INP_DIS EQU CYREG_PRT4_INP_DIS\r
-SCSI_Out_DBx__7__INTTYPE EQU CYREG_PICU4_INTTYPE4\r
-SCSI_Out_DBx__7__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
-SCSI_Out_DBx__7__LCD_EN EQU CYREG_PRT4_LCD_EN\r
-SCSI_Out_DBx__7__MASK EQU 0x10\r
-SCSI_Out_DBx__7__PC EQU CYREG_PRT4_PC4\r
-SCSI_Out_DBx__7__PORT EQU 4\r
-SCSI_Out_DBx__7__PRT EQU CYREG_PRT4_PRT\r
-SCSI_Out_DBx__7__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
-SCSI_Out_DBx__7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
-SCSI_Out_DBx__7__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
-SCSI_Out_DBx__7__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
-SCSI_Out_DBx__7__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
-SCSI_Out_DBx__7__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
-SCSI_Out_DBx__7__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
-SCSI_Out_DBx__7__PS EQU CYREG_PRT4_PS\r
-SCSI_Out_DBx__7__SHIFT EQU 4\r
-SCSI_Out_DBx__7__SLW EQU CYREG_PRT4_SLW\r
-SCSI_Out_DBx__DB0__AG EQU CYREG_PRT6_AG\r
-SCSI_Out_DBx__DB0__AMUX EQU CYREG_PRT6_AMUX\r
-SCSI_Out_DBx__DB0__BIE EQU CYREG_PRT6_BIE\r
-SCSI_Out_DBx__DB0__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
-SCSI_Out_DBx__DB0__BYP EQU CYREG_PRT6_BYP\r
-SCSI_Out_DBx__DB0__CTL EQU CYREG_PRT6_CTL\r
-SCSI_Out_DBx__DB0__DM0 EQU CYREG_PRT6_DM0\r
-SCSI_Out_DBx__DB0__DM1 EQU CYREG_PRT6_DM1\r
-SCSI_Out_DBx__DB0__DM2 EQU CYREG_PRT6_DM2\r
-SCSI_Out_DBx__DB0__DR EQU CYREG_PRT6_DR\r
-SCSI_Out_DBx__DB0__INP_DIS EQU CYREG_PRT6_INP_DIS\r
-SCSI_Out_DBx__DB0__INTTYPE EQU CYREG_PICU6_INTTYPE3\r
-SCSI_Out_DBx__DB0__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
-SCSI_Out_DBx__DB0__LCD_EN EQU CYREG_PRT6_LCD_EN\r
-SCSI_Out_DBx__DB0__MASK EQU 0x08\r
-SCSI_Out_DBx__DB0__PC EQU CYREG_PRT6_PC3\r
-SCSI_Out_DBx__DB0__PORT EQU 6\r
-SCSI_Out_DBx__DB0__PRT EQU CYREG_PRT6_PRT\r
-SCSI_Out_DBx__DB0__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
-SCSI_Out_DBx__DB0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
-SCSI_Out_DBx__DB0__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
-SCSI_Out_DBx__DB0__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
-SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
-SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
-SCSI_Out_DBx__DB0__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
-SCSI_Out_DBx__DB0__PS EQU CYREG_PRT6_PS\r
-SCSI_Out_DBx__DB0__SHIFT EQU 3\r
-SCSI_Out_DBx__DB0__SLW EQU CYREG_PRT6_SLW\r
-SCSI_Out_DBx__DB1__AG EQU CYREG_PRT6_AG\r
-SCSI_Out_DBx__DB1__AMUX EQU CYREG_PRT6_AMUX\r
-SCSI_Out_DBx__DB1__BIE EQU CYREG_PRT6_BIE\r
-SCSI_Out_DBx__DB1__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
-SCSI_Out_DBx__DB1__BYP EQU CYREG_PRT6_BYP\r
-SCSI_Out_DBx__DB1__CTL EQU CYREG_PRT6_CTL\r
-SCSI_Out_DBx__DB1__DM0 EQU CYREG_PRT6_DM0\r
-SCSI_Out_DBx__DB1__DM1 EQU CYREG_PRT6_DM1\r
-SCSI_Out_DBx__DB1__DM2 EQU CYREG_PRT6_DM2\r
-SCSI_Out_DBx__DB1__DR EQU CYREG_PRT6_DR\r
-SCSI_Out_DBx__DB1__INP_DIS EQU CYREG_PRT6_INP_DIS\r
-SCSI_Out_DBx__DB1__INTTYPE EQU CYREG_PICU6_INTTYPE2\r
-SCSI_Out_DBx__DB1__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
-SCSI_Out_DBx__DB1__LCD_EN EQU CYREG_PRT6_LCD_EN\r
-SCSI_Out_DBx__DB1__MASK EQU 0x04\r
-SCSI_Out_DBx__DB1__PC EQU CYREG_PRT6_PC2\r
-SCSI_Out_DBx__DB1__PORT EQU 6\r
-SCSI_Out_DBx__DB1__PRT EQU CYREG_PRT6_PRT\r
-SCSI_Out_DBx__DB1__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
-SCSI_Out_DBx__DB1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
-SCSI_Out_DBx__DB1__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
-SCSI_Out_DBx__DB1__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
-SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
-SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
-SCSI_Out_DBx__DB1__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
-SCSI_Out_DBx__DB1__PS EQU CYREG_PRT6_PS\r
-SCSI_Out_DBx__DB1__SHIFT EQU 2\r
-SCSI_Out_DBx__DB1__SLW EQU CYREG_PRT6_SLW\r
-SCSI_Out_DBx__DB2__AG EQU CYREG_PRT6_AG\r
-SCSI_Out_DBx__DB2__AMUX EQU CYREG_PRT6_AMUX\r
-SCSI_Out_DBx__DB2__BIE EQU CYREG_PRT6_BIE\r
-SCSI_Out_DBx__DB2__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
-SCSI_Out_DBx__DB2__BYP EQU CYREG_PRT6_BYP\r
-SCSI_Out_DBx__DB2__CTL EQU CYREG_PRT6_CTL\r
-SCSI_Out_DBx__DB2__DM0 EQU CYREG_PRT6_DM0\r
-SCSI_Out_DBx__DB2__DM1 EQU CYREG_PRT6_DM1\r
-SCSI_Out_DBx__DB2__DM2 EQU CYREG_PRT6_DM2\r
-SCSI_Out_DBx__DB2__DR EQU CYREG_PRT6_DR\r
-SCSI_Out_DBx__DB2__INP_DIS EQU CYREG_PRT6_INP_DIS\r
-SCSI_Out_DBx__DB2__INTTYPE EQU CYREG_PICU6_INTTYPE1\r
-SCSI_Out_DBx__DB2__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
-SCSI_Out_DBx__DB2__LCD_EN EQU CYREG_PRT6_LCD_EN\r
-SCSI_Out_DBx__DB2__MASK EQU 0x02\r
-SCSI_Out_DBx__DB2__PC EQU CYREG_PRT6_PC1\r
-SCSI_Out_DBx__DB2__PORT EQU 6\r
-SCSI_Out_DBx__DB2__PRT EQU CYREG_PRT6_PRT\r
-SCSI_Out_DBx__DB2__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
-SCSI_Out_DBx__DB2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
-SCSI_Out_DBx__DB2__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
-SCSI_Out_DBx__DB2__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
-SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
-SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
-SCSI_Out_DBx__DB2__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
-SCSI_Out_DBx__DB2__PS EQU CYREG_PRT6_PS\r
-SCSI_Out_DBx__DB2__SHIFT EQU 1\r
-SCSI_Out_DBx__DB2__SLW EQU CYREG_PRT6_SLW\r
-SCSI_Out_DBx__DB3__AG EQU CYREG_PRT6_AG\r
-SCSI_Out_DBx__DB3__AMUX EQU CYREG_PRT6_AMUX\r
-SCSI_Out_DBx__DB3__BIE EQU CYREG_PRT6_BIE\r
-SCSI_Out_DBx__DB3__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
-SCSI_Out_DBx__DB3__BYP EQU CYREG_PRT6_BYP\r
-SCSI_Out_DBx__DB3__CTL EQU CYREG_PRT6_CTL\r
-SCSI_Out_DBx__DB3__DM0 EQU CYREG_PRT6_DM0\r
-SCSI_Out_DBx__DB3__DM1 EQU CYREG_PRT6_DM1\r
-SCSI_Out_DBx__DB3__DM2 EQU CYREG_PRT6_DM2\r
-SCSI_Out_DBx__DB3__DR EQU CYREG_PRT6_DR\r
-SCSI_Out_DBx__DB3__INP_DIS EQU CYREG_PRT6_INP_DIS\r
-SCSI_Out_DBx__DB3__INTTYPE EQU CYREG_PICU6_INTTYPE0\r
-SCSI_Out_DBx__DB3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
-SCSI_Out_DBx__DB3__LCD_EN EQU CYREG_PRT6_LCD_EN\r
-SCSI_Out_DBx__DB3__MASK EQU 0x01\r
-SCSI_Out_DBx__DB3__PC EQU CYREG_PRT6_PC0\r
-SCSI_Out_DBx__DB3__PORT EQU 6\r
-SCSI_Out_DBx__DB3__PRT EQU CYREG_PRT6_PRT\r
-SCSI_Out_DBx__DB3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
-SCSI_Out_DBx__DB3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
-SCSI_Out_DBx__DB3__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
-SCSI_Out_DBx__DB3__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
-SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
-SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
-SCSI_Out_DBx__DB3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
-SCSI_Out_DBx__DB3__PS EQU CYREG_PRT6_PS\r
-SCSI_Out_DBx__DB3__SHIFT EQU 0\r
-SCSI_Out_DBx__DB3__SLW EQU CYREG_PRT6_SLW\r
-SCSI_Out_DBx__DB4__AG EQU CYREG_PRT4_AG\r
-SCSI_Out_DBx__DB4__AMUX EQU CYREG_PRT4_AMUX\r
-SCSI_Out_DBx__DB4__BIE EQU CYREG_PRT4_BIE\r
-SCSI_Out_DBx__DB4__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
-SCSI_Out_DBx__DB4__BYP EQU CYREG_PRT4_BYP\r
-SCSI_Out_DBx__DB4__CTL EQU CYREG_PRT4_CTL\r
-SCSI_Out_DBx__DB4__DM0 EQU CYREG_PRT4_DM0\r
-SCSI_Out_DBx__DB4__DM1 EQU CYREG_PRT4_DM1\r
-SCSI_Out_DBx__DB4__DM2 EQU CYREG_PRT4_DM2\r
-SCSI_Out_DBx__DB4__DR EQU CYREG_PRT4_DR\r
-SCSI_Out_DBx__DB4__INP_DIS EQU CYREG_PRT4_INP_DIS\r
-SCSI_Out_DBx__DB4__INTTYPE EQU CYREG_PICU4_INTTYPE7\r
-SCSI_Out_DBx__DB4__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
-SCSI_Out_DBx__DB4__LCD_EN EQU CYREG_PRT4_LCD_EN\r
-SCSI_Out_DBx__DB4__MASK EQU 0x80\r
-SCSI_Out_DBx__DB4__PC EQU CYREG_PRT4_PC7\r
-SCSI_Out_DBx__DB4__PORT EQU 4\r
-SCSI_Out_DBx__DB4__PRT EQU CYREG_PRT4_PRT\r
-SCSI_Out_DBx__DB4__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
-SCSI_Out_DBx__DB4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
-SCSI_Out_DBx__DB4__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
-SCSI_Out_DBx__DB4__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
-SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
-SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
-SCSI_Out_DBx__DB4__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
-SCSI_Out_DBx__DB4__PS EQU CYREG_PRT4_PS\r
-SCSI_Out_DBx__DB4__SHIFT EQU 7\r
-SCSI_Out_DBx__DB4__SLW EQU CYREG_PRT4_SLW\r
-SCSI_Out_DBx__DB5__AG EQU CYREG_PRT4_AG\r
-SCSI_Out_DBx__DB5__AMUX EQU CYREG_PRT4_AMUX\r
-SCSI_Out_DBx__DB5__BIE EQU CYREG_PRT4_BIE\r
-SCSI_Out_DBx__DB5__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
-SCSI_Out_DBx__DB5__BYP EQU CYREG_PRT4_BYP\r
-SCSI_Out_DBx__DB5__CTL EQU CYREG_PRT4_CTL\r
-SCSI_Out_DBx__DB5__DM0 EQU CYREG_PRT4_DM0\r
-SCSI_Out_DBx__DB5__DM1 EQU CYREG_PRT4_DM1\r
-SCSI_Out_DBx__DB5__DM2 EQU CYREG_PRT4_DM2\r
-SCSI_Out_DBx__DB5__DR EQU CYREG_PRT4_DR\r
-SCSI_Out_DBx__DB5__INP_DIS EQU CYREG_PRT4_INP_DIS\r
-SCSI_Out_DBx__DB5__INTTYPE EQU CYREG_PICU4_INTTYPE6\r
-SCSI_Out_DBx__DB5__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
-SCSI_Out_DBx__DB5__LCD_EN EQU CYREG_PRT4_LCD_EN\r
-SCSI_Out_DBx__DB5__MASK EQU 0x40\r
-SCSI_Out_DBx__DB5__PC EQU CYREG_PRT4_PC6\r
-SCSI_Out_DBx__DB5__PORT EQU 4\r
-SCSI_Out_DBx__DB5__PRT EQU CYREG_PRT4_PRT\r
-SCSI_Out_DBx__DB5__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
-SCSI_Out_DBx__DB5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
-SCSI_Out_DBx__DB5__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
-SCSI_Out_DBx__DB5__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
-SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
-SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
-SCSI_Out_DBx__DB5__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
-SCSI_Out_DBx__DB5__PS EQU CYREG_PRT4_PS\r
-SCSI_Out_DBx__DB5__SHIFT EQU 6\r
-SCSI_Out_DBx__DB5__SLW EQU CYREG_PRT4_SLW\r
-SCSI_Out_DBx__DB6__AG EQU CYREG_PRT4_AG\r
-SCSI_Out_DBx__DB6__AMUX EQU CYREG_PRT4_AMUX\r
-SCSI_Out_DBx__DB6__BIE EQU CYREG_PRT4_BIE\r
-SCSI_Out_DBx__DB6__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
-SCSI_Out_DBx__DB6__BYP EQU CYREG_PRT4_BYP\r
-SCSI_Out_DBx__DB6__CTL EQU CYREG_PRT4_CTL\r
-SCSI_Out_DBx__DB6__DM0 EQU CYREG_PRT4_DM0\r
-SCSI_Out_DBx__DB6__DM1 EQU CYREG_PRT4_DM1\r
-SCSI_Out_DBx__DB6__DM2 EQU CYREG_PRT4_DM2\r
-SCSI_Out_DBx__DB6__DR EQU CYREG_PRT4_DR\r
-SCSI_Out_DBx__DB6__INP_DIS EQU CYREG_PRT4_INP_DIS\r
-SCSI_Out_DBx__DB6__INTTYPE EQU CYREG_PICU4_INTTYPE5\r
-SCSI_Out_DBx__DB6__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
-SCSI_Out_DBx__DB6__LCD_EN EQU CYREG_PRT4_LCD_EN\r
-SCSI_Out_DBx__DB6__MASK EQU 0x20\r
-SCSI_Out_DBx__DB6__PC EQU CYREG_PRT4_PC5\r
-SCSI_Out_DBx__DB6__PORT EQU 4\r
-SCSI_Out_DBx__DB6__PRT EQU CYREG_PRT4_PRT\r
-SCSI_Out_DBx__DB6__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
-SCSI_Out_DBx__DB6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
-SCSI_Out_DBx__DB6__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
-SCSI_Out_DBx__DB6__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
-SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
-SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
-SCSI_Out_DBx__DB6__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
-SCSI_Out_DBx__DB6__PS EQU CYREG_PRT4_PS\r
-SCSI_Out_DBx__DB6__SHIFT EQU 5\r
-SCSI_Out_DBx__DB6__SLW EQU CYREG_PRT4_SLW\r
-SCSI_Out_DBx__DB7__AG EQU CYREG_PRT4_AG\r
-SCSI_Out_DBx__DB7__AMUX EQU CYREG_PRT4_AMUX\r
-SCSI_Out_DBx__DB7__BIE EQU CYREG_PRT4_BIE\r
-SCSI_Out_DBx__DB7__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
-SCSI_Out_DBx__DB7__BYP EQU CYREG_PRT4_BYP\r
-SCSI_Out_DBx__DB7__CTL EQU CYREG_PRT4_CTL\r
-SCSI_Out_DBx__DB7__DM0 EQU CYREG_PRT4_DM0\r
-SCSI_Out_DBx__DB7__DM1 EQU CYREG_PRT4_DM1\r
-SCSI_Out_DBx__DB7__DM2 EQU CYREG_PRT4_DM2\r
-SCSI_Out_DBx__DB7__DR EQU CYREG_PRT4_DR\r
-SCSI_Out_DBx__DB7__INP_DIS EQU CYREG_PRT4_INP_DIS\r
-SCSI_Out_DBx__DB7__INTTYPE EQU CYREG_PICU4_INTTYPE4\r
-SCSI_Out_DBx__DB7__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
-SCSI_Out_DBx__DB7__LCD_EN EQU CYREG_PRT4_LCD_EN\r
-SCSI_Out_DBx__DB7__MASK EQU 0x10\r
-SCSI_Out_DBx__DB7__PC EQU CYREG_PRT4_PC4\r
-SCSI_Out_DBx__DB7__PORT EQU 4\r
-SCSI_Out_DBx__DB7__PRT EQU CYREG_PRT4_PRT\r
-SCSI_Out_DBx__DB7__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
-SCSI_Out_DBx__DB7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
-SCSI_Out_DBx__DB7__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
-SCSI_Out_DBx__DB7__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
-SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
-SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
-SCSI_Out_DBx__DB7__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
-SCSI_Out_DBx__DB7__PS EQU CYREG_PRT4_PS\r
-SCSI_Out_DBx__DB7__SHIFT EQU 4\r
-SCSI_Out_DBx__DB7__SLW EQU CYREG_PRT4_SLW\r
-\r
-; SCSI_Parity_Error\r
-SCSI_Parity_Error_sts_sts_reg__0__MASK EQU 0x01\r
-SCSI_Parity_Error_sts_sts_reg__0__POS EQU 0\r
-SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB01_02_ACTL\r
-SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB01_02_ST\r
-SCSI_Parity_Error_sts_sts_reg__MASK EQU 0x01\r
-SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB01_MSK\r
-SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB01_ACTL\r
-SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB01_ST\r
-\r
-; SCSI_RST_ISR\r
-SCSI_RST_ISR__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
-SCSI_RST_ISR__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
-SCSI_RST_ISR__INTC_MASK EQU 0x02\r
-SCSI_RST_ISR__INTC_NUMBER EQU 1\r
-SCSI_RST_ISR__INTC_PRIOR_NUM EQU 7\r
-SCSI_RST_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_1\r
-SCSI_RST_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
-SCSI_RST_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
-\r
-; SCSI_RX_DMA\r
-SCSI_RX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0\r
-SCSI_RX_DMA__DRQ_NUMBER EQU 0\r
-SCSI_RX_DMA__NUMBEROF_TDS EQU 0\r
-SCSI_RX_DMA__PRIORITY EQU 2\r
-SCSI_RX_DMA__TERMIN_EN EQU 0\r
-SCSI_RX_DMA__TERMIN_SEL EQU 0\r
-SCSI_RX_DMA__TERMOUT0_EN EQU 1\r
-SCSI_RX_DMA__TERMOUT0_SEL EQU 0\r
-SCSI_RX_DMA__TERMOUT1_EN EQU 0\r
-SCSI_RX_DMA__TERMOUT1_SEL EQU 0\r
-SCSI_RX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
-SCSI_RX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
-SCSI_RX_DMA_COMPLETE__INTC_MASK EQU 0x04\r
-SCSI_RX_DMA_COMPLETE__INTC_NUMBER EQU 2\r
-SCSI_RX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7\r
-SCSI_RX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_2\r
-SCSI_RX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
-SCSI_RX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
-\r
-; SCSI_SEL_ISR\r
-SCSI_SEL_ISR__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
-SCSI_SEL_ISR__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
-SCSI_SEL_ISR__INTC_MASK EQU 0x08\r
-SCSI_SEL_ISR__INTC_NUMBER EQU 3\r
-SCSI_SEL_ISR__INTC_PRIOR_NUM EQU 7\r
-SCSI_SEL_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_3\r
-SCSI_SEL_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
-SCSI_SEL_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
-\r
-; SCSI_TX_DMA\r
-SCSI_TX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0\r
-SCSI_TX_DMA__DRQ_NUMBER EQU 1\r
-SCSI_TX_DMA__NUMBEROF_TDS EQU 0\r
-SCSI_TX_DMA__PRIORITY EQU 2\r
-SCSI_TX_DMA__TERMIN_EN EQU 0\r
-SCSI_TX_DMA__TERMIN_SEL EQU 0\r
-SCSI_TX_DMA__TERMOUT0_EN EQU 1\r
-SCSI_TX_DMA__TERMOUT0_SEL EQU 1\r
-SCSI_TX_DMA__TERMOUT1_EN EQU 0\r
-SCSI_TX_DMA__TERMOUT1_SEL EQU 0\r
-SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
-SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
-SCSI_TX_DMA_COMPLETE__INTC_MASK EQU 0x10\r
-SCSI_TX_DMA_COMPLETE__INTC_NUMBER EQU 4\r
-SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7\r
-SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_4\r
-SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
-SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
-\r
-; SDCard_BSPIM\r
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL\r
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB04_05_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB04_05_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB04_05_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB04_05_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB04_05_MSK\r
-SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB04_05_MSK\r
-SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB04_05_MSK\r
-SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB04_05_MSK\r
-SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL\r
-SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB04_CTL\r
-SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB04_ST_CTL\r
-SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB04_CTL\r
-SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB04_ST_CTL\r
-SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL\r
-SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL\r
-SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB04_MSK\r
-SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL\r
-SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB04_05_ST\r
-SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB04_MSK\r
-SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL\r
-SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB04_ST_CTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB04_ST_CTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB04_ST\r
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB08_09_ACTL\r
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB08_09_ST\r
-SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10\r
-SDCard_BSPIM_RxStsReg__4__POS EQU 4\r
-SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20\r
-SDCard_BSPIM_RxStsReg__5__POS EQU 5\r
-SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40\r
-SDCard_BSPIM_RxStsReg__6__POS EQU 6\r
-SDCard_BSPIM_RxStsReg__MASK EQU 0x70\r
-SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB08_MSK\r
-SDCard_BSPIM_RxStsReg__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB08_MSK_ACTL\r
-SDCard_BSPIM_RxStsReg__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB08_MSK_ACTL\r
-SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB08_ACTL\r
-SDCard_BSPIM_RxStsReg__STATUS_CNT_REG EQU CYREG_B1_UDB08_ST_CTL\r
-SDCard_BSPIM_RxStsReg__STATUS_CONTROL_REG EQU CYREG_B1_UDB08_ST_CTL\r
-SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB08_ST\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB04_05_A0\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB04_05_A1\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B1_UDB04_05_D0\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B1_UDB04_05_D1\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B1_UDB04_05_F0\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B1_UDB04_05_F1\r
-SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B1_UDB04_A0_A1\r
-SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B1_UDB04_A0\r
-SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B1_UDB04_A1\r
-SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B1_UDB04_D0_D1\r
-SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B1_UDB04_D0\r
-SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B1_UDB04_D1\r
-SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL\r
-SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B1_UDB04_F0_F1\r
-SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B1_UDB04_F0\r
-SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B1_UDB04_F1\r
-SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL\r
-SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL\r
-SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01\r
-SDCard_BSPIM_TxStsReg__0__POS EQU 0\r
-SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02\r
-SDCard_BSPIM_TxStsReg__1__POS EQU 1\r
-SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL\r
-SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST\r
-SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04\r
-SDCard_BSPIM_TxStsReg__2__POS EQU 2\r
-SDCard_BSPIM_TxStsReg__3__MASK EQU 0x08\r
-SDCard_BSPIM_TxStsReg__3__POS EQU 3\r
-SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10\r
-SDCard_BSPIM_TxStsReg__4__POS EQU 4\r
-SDCard_BSPIM_TxStsReg__MASK EQU 0x1F\r
-SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB07_MSK\r
-SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL\r
-SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB07_ST\r
-\r
-; SD_CD\r
-SD_CD__0__INTTYPE EQU CYREG_PICU3_INTTYPE6\r
-SD_CD__0__MASK EQU 0x40\r
-SD_CD__0__PC EQU CYREG_PRT3_PC6\r
-SD_CD__0__PORT EQU 3\r
-SD_CD__0__SHIFT EQU 6\r
-SD_CD__AG EQU CYREG_PRT3_AG\r
-SD_CD__AMUX EQU CYREG_PRT3_AMUX\r
-SD_CD__BIE EQU CYREG_PRT3_BIE\r
-SD_CD__BIT_MASK EQU CYREG_PRT3_BIT_MASK\r
-SD_CD__BYP EQU CYREG_PRT3_BYP\r
-SD_CD__CTL EQU CYREG_PRT3_CTL\r
-SD_CD__DM0 EQU CYREG_PRT3_DM0\r
-SD_CD__DM1 EQU CYREG_PRT3_DM1\r
-SD_CD__DM2 EQU CYREG_PRT3_DM2\r
-SD_CD__DR EQU CYREG_PRT3_DR\r
-SD_CD__INP_DIS EQU CYREG_PRT3_INP_DIS\r
-SD_CD__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE\r
-SD_CD__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG\r
-SD_CD__LCD_EN EQU CYREG_PRT3_LCD_EN\r
-SD_CD__MASK EQU 0x40\r
-SD_CD__PORT EQU 3\r
-SD_CD__PRT EQU CYREG_PRT3_PRT\r
-SD_CD__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL\r
-SD_CD__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN\r
-SD_CD__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0\r
-SD_CD__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1\r
-SD_CD__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0\r
-SD_CD__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1\r
-SD_CD__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT\r
-SD_CD__PS EQU CYREG_PRT3_PS\r
-SD_CD__SHIFT EQU 6\r
-SD_CD__SLW EQU CYREG_PRT3_SLW\r
-\r
-; SD_CS\r
-SD_CS__0__INTTYPE EQU CYREG_PICU3_INTTYPE4\r
-SD_CS__0__MASK EQU 0x10\r
-SD_CS__0__PC EQU CYREG_PRT3_PC4\r
-SD_CS__0__PORT EQU 3\r
-SD_CS__0__SHIFT EQU 4\r
-SD_CS__AG EQU CYREG_PRT3_AG\r
-SD_CS__AMUX EQU CYREG_PRT3_AMUX\r
-SD_CS__BIE EQU CYREG_PRT3_BIE\r
-SD_CS__BIT_MASK EQU CYREG_PRT3_BIT_MASK\r
-SD_CS__BYP EQU CYREG_PRT3_BYP\r
-SD_CS__CTL EQU CYREG_PRT3_CTL\r
-SD_CS__DM0 EQU CYREG_PRT3_DM0\r
-SD_CS__DM1 EQU CYREG_PRT3_DM1\r
-SD_CS__DM2 EQU CYREG_PRT3_DM2\r
-SD_CS__DR EQU CYREG_PRT3_DR\r
-SD_CS__INP_DIS EQU CYREG_PRT3_INP_DIS\r
-SD_CS__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE\r
-SD_CS__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG\r
-SD_CS__LCD_EN EQU CYREG_PRT3_LCD_EN\r
-SD_CS__MASK EQU 0x10\r
-SD_CS__PORT EQU 3\r
-SD_CS__PRT EQU CYREG_PRT3_PRT\r
-SD_CS__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL\r
-SD_CS__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN\r
-SD_CS__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0\r
-SD_CS__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1\r
-SD_CS__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0\r
-SD_CS__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1\r
-SD_CS__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT\r
-SD_CS__PS EQU CYREG_PRT3_PS\r
-SD_CS__SHIFT EQU 4\r
-SD_CS__SLW EQU CYREG_PRT3_SLW\r
-\r
-; SD_DAT1\r
-SD_DAT1__0__INTTYPE EQU CYREG_PICU3_INTTYPE0\r
-SD_DAT1__0__MASK EQU 0x01\r
-SD_DAT1__0__PC EQU CYREG_PRT3_PC0\r
-SD_DAT1__0__PORT EQU 3\r
-SD_DAT1__0__SHIFT EQU 0\r
-SD_DAT1__AG EQU CYREG_PRT3_AG\r
-SD_DAT1__AMUX EQU CYREG_PRT3_AMUX\r
-SD_DAT1__BIE EQU CYREG_PRT3_BIE\r
-SD_DAT1__BIT_MASK EQU CYREG_PRT3_BIT_MASK\r
-SD_DAT1__BYP EQU CYREG_PRT3_BYP\r
-SD_DAT1__CTL EQU CYREG_PRT3_CTL\r
-SD_DAT1__DM0 EQU CYREG_PRT3_DM0\r
-SD_DAT1__DM1 EQU CYREG_PRT3_DM1\r
-SD_DAT1__DM2 EQU CYREG_PRT3_DM2\r
-SD_DAT1__DR EQU CYREG_PRT3_DR\r
-SD_DAT1__INP_DIS EQU CYREG_PRT3_INP_DIS\r
-SD_DAT1__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE\r
-SD_DAT1__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG\r
-SD_DAT1__LCD_EN EQU CYREG_PRT3_LCD_EN\r
-SD_DAT1__MASK EQU 0x01\r
-SD_DAT1__PORT EQU 3\r
-SD_DAT1__PRT EQU CYREG_PRT3_PRT\r
-SD_DAT1__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL\r
-SD_DAT1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN\r
-SD_DAT1__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0\r
-SD_DAT1__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1\r
-SD_DAT1__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0\r
-SD_DAT1__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1\r
-SD_DAT1__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT\r
-SD_DAT1__PS EQU CYREG_PRT3_PS\r
-SD_DAT1__SHIFT EQU 0\r
-SD_DAT1__SLW EQU CYREG_PRT3_SLW\r
-\r
-; SD_DAT2\r
-SD_DAT2__0__INTTYPE EQU CYREG_PICU3_INTTYPE5\r
-SD_DAT2__0__MASK EQU 0x20\r
-SD_DAT2__0__PC EQU CYREG_PRT3_PC5\r
-SD_DAT2__0__PORT EQU 3\r
-SD_DAT2__0__SHIFT EQU 5\r
-SD_DAT2__AG EQU CYREG_PRT3_AG\r
-SD_DAT2__AMUX EQU CYREG_PRT3_AMUX\r
-SD_DAT2__BIE EQU CYREG_PRT3_BIE\r
-SD_DAT2__BIT_MASK EQU CYREG_PRT3_BIT_MASK\r
-SD_DAT2__BYP EQU CYREG_PRT3_BYP\r
-SD_DAT2__CTL EQU CYREG_PRT3_CTL\r
-SD_DAT2__DM0 EQU CYREG_PRT3_DM0\r
-SD_DAT2__DM1 EQU CYREG_PRT3_DM1\r
-SD_DAT2__DM2 EQU CYREG_PRT3_DM2\r
-SD_DAT2__DR EQU CYREG_PRT3_DR\r
-SD_DAT2__INP_DIS EQU CYREG_PRT3_INP_DIS\r
-SD_DAT2__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE\r
-SD_DAT2__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG\r
-SD_DAT2__LCD_EN EQU CYREG_PRT3_LCD_EN\r
-SD_DAT2__MASK EQU 0x20\r
-SD_DAT2__PORT EQU 3\r
-SD_DAT2__PRT EQU CYREG_PRT3_PRT\r
-SD_DAT2__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL\r
-SD_DAT2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN\r
-SD_DAT2__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0\r
-SD_DAT2__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1\r
-SD_DAT2__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0\r
-SD_DAT2__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1\r
-SD_DAT2__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT\r
-SD_DAT2__PS EQU CYREG_PRT3_PS\r
-SD_DAT2__SHIFT EQU 5\r
-SD_DAT2__SLW EQU CYREG_PRT3_SLW\r
-\r
-; SD_Data_Clk\r
-SD_Data_Clk__CFG0 EQU CYREG_CLKDIST_DCFG0_CFG0\r
-SD_Data_Clk__CFG1 EQU CYREG_CLKDIST_DCFG0_CFG1\r
-SD_Data_Clk__CFG2 EQU CYREG_CLKDIST_DCFG0_CFG2\r
-SD_Data_Clk__CFG2_SRC_SEL_MASK EQU 0x07\r
-SD_Data_Clk__INDEX EQU 0x00\r
-SD_Data_Clk__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2\r
-SD_Data_Clk__PM_ACT_MSK EQU 0x01\r
-SD_Data_Clk__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2\r
-SD_Data_Clk__PM_STBY_MSK EQU 0x01\r
-\r
-; SD_MISO\r
-SD_MISO__0__INTTYPE EQU CYREG_PICU3_INTTYPE1\r
-SD_MISO__0__MASK EQU 0x02\r
-SD_MISO__0__PC EQU CYREG_PRT3_PC1\r
-SD_MISO__0__PORT EQU 3\r
-SD_MISO__0__SHIFT EQU 1\r
-SD_MISO__AG EQU CYREG_PRT3_AG\r
-SD_MISO__AMUX EQU CYREG_PRT3_AMUX\r
-SD_MISO__BIE EQU CYREG_PRT3_BIE\r
-SD_MISO__BIT_MASK EQU CYREG_PRT3_BIT_MASK\r
-SD_MISO__BYP EQU CYREG_PRT3_BYP\r
-SD_MISO__CTL EQU CYREG_PRT3_CTL\r
-SD_MISO__DM0 EQU CYREG_PRT3_DM0\r
-SD_MISO__DM1 EQU CYREG_PRT3_DM1\r
-SD_MISO__DM2 EQU CYREG_PRT3_DM2\r
-SD_MISO__DR EQU CYREG_PRT3_DR\r
-SD_MISO__INP_DIS EQU CYREG_PRT3_INP_DIS\r
-SD_MISO__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE\r
-SD_MISO__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG\r
-SD_MISO__LCD_EN EQU CYREG_PRT3_LCD_EN\r
-SD_MISO__MASK EQU 0x02\r
-SD_MISO__PORT EQU 3\r
-SD_MISO__PRT EQU CYREG_PRT3_PRT\r
-SD_MISO__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL\r
-SD_MISO__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN\r
-SD_MISO__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0\r
-SD_MISO__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1\r
-SD_MISO__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0\r
-SD_MISO__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1\r
-SD_MISO__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT\r
-SD_MISO__PS EQU CYREG_PRT3_PS\r
-SD_MISO__SHIFT EQU 1\r
-SD_MISO__SLW EQU CYREG_PRT3_SLW\r
-\r
-; SD_MOSI\r
-SD_MOSI__0__INTTYPE EQU CYREG_PICU3_INTTYPE3\r
-SD_MOSI__0__MASK EQU 0x08\r
-SD_MOSI__0__PC EQU CYREG_PRT3_PC3\r
-SD_MOSI__0__PORT EQU 3\r
-SD_MOSI__0__SHIFT EQU 3\r
-SD_MOSI__AG EQU CYREG_PRT3_AG\r
-SD_MOSI__AMUX EQU CYREG_PRT3_AMUX\r
-SD_MOSI__BIE EQU CYREG_PRT3_BIE\r
-SD_MOSI__BIT_MASK EQU CYREG_PRT3_BIT_MASK\r
-SD_MOSI__BYP EQU CYREG_PRT3_BYP\r
-SD_MOSI__CTL EQU CYREG_PRT3_CTL\r
-SD_MOSI__DM0 EQU CYREG_PRT3_DM0\r
-SD_MOSI__DM1 EQU CYREG_PRT3_DM1\r
-SD_MOSI__DM2 EQU CYREG_PRT3_DM2\r
-SD_MOSI__DR EQU CYREG_PRT3_DR\r
-SD_MOSI__INP_DIS EQU CYREG_PRT3_INP_DIS\r
-SD_MOSI__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE\r
-SD_MOSI__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG\r
-SD_MOSI__LCD_EN EQU CYREG_PRT3_LCD_EN\r
-SD_MOSI__MASK EQU 0x08\r
-SD_MOSI__PORT EQU 3\r
-SD_MOSI__PRT EQU CYREG_PRT3_PRT\r
-SD_MOSI__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL\r
-SD_MOSI__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN\r
-SD_MOSI__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0\r
-SD_MOSI__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1\r
-SD_MOSI__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0\r
-SD_MOSI__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1\r
-SD_MOSI__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT\r
-SD_MOSI__PS EQU CYREG_PRT3_PS\r
-SD_MOSI__SHIFT EQU 3\r
-SD_MOSI__SLW EQU CYREG_PRT3_SLW\r
-\r
-; SD_RX_DMA\r
-SD_RX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0\r
-SD_RX_DMA__DRQ_NUMBER EQU 2\r
-SD_RX_DMA__NUMBEROF_TDS EQU 0\r
-SD_RX_DMA__PRIORITY EQU 0\r
-SD_RX_DMA__TERMIN_EN EQU 0\r
-SD_RX_DMA__TERMIN_SEL EQU 0\r
-SD_RX_DMA__TERMOUT0_EN EQU 1\r
-SD_RX_DMA__TERMOUT0_SEL EQU 2\r
-SD_RX_DMA__TERMOUT1_EN EQU 0\r
-SD_RX_DMA__TERMOUT1_SEL EQU 0\r
-SD_RX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
-SD_RX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
-SD_RX_DMA_COMPLETE__INTC_MASK EQU 0x20\r
-SD_RX_DMA_COMPLETE__INTC_NUMBER EQU 5\r
-SD_RX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7\r
-SD_RX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_5\r
-SD_RX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
-SD_RX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
-\r
-; SD_SCK\r
-SD_SCK__0__INTTYPE EQU CYREG_PICU3_INTTYPE2\r
-SD_SCK__0__MASK EQU 0x04\r
-SD_SCK__0__PC EQU CYREG_PRT3_PC2\r
-SD_SCK__0__PORT EQU 3\r
-SD_SCK__0__SHIFT EQU 2\r
-SD_SCK__AG EQU CYREG_PRT3_AG\r
-SD_SCK__AMUX EQU CYREG_PRT3_AMUX\r
-SD_SCK__BIE EQU CYREG_PRT3_BIE\r
-SD_SCK__BIT_MASK EQU CYREG_PRT3_BIT_MASK\r
-SD_SCK__BYP EQU CYREG_PRT3_BYP\r
-SD_SCK__CTL EQU CYREG_PRT3_CTL\r
-SD_SCK__DM0 EQU CYREG_PRT3_DM0\r
-SD_SCK__DM1 EQU CYREG_PRT3_DM1\r
-SD_SCK__DM2 EQU CYREG_PRT3_DM2\r
-SD_SCK__DR EQU CYREG_PRT3_DR\r
-SD_SCK__INP_DIS EQU CYREG_PRT3_INP_DIS\r
-SD_SCK__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE\r
-SD_SCK__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG\r
-SD_SCK__LCD_EN EQU CYREG_PRT3_LCD_EN\r
-SD_SCK__MASK EQU 0x04\r
-SD_SCK__PORT EQU 3\r
-SD_SCK__PRT EQU CYREG_PRT3_PRT\r
-SD_SCK__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL\r
-SD_SCK__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN\r
-SD_SCK__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0\r
-SD_SCK__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1\r
-SD_SCK__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0\r
-SD_SCK__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1\r
-SD_SCK__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT\r
-SD_SCK__PS EQU CYREG_PRT3_PS\r
-SD_SCK__SHIFT EQU 2\r
-SD_SCK__SLW EQU CYREG_PRT3_SLW\r
-\r
-; SD_TX_DMA\r
-SD_TX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0\r
-SD_TX_DMA__DRQ_NUMBER EQU 3\r
-SD_TX_DMA__NUMBEROF_TDS EQU 0\r
-SD_TX_DMA__PRIORITY EQU 1\r
-SD_TX_DMA__TERMIN_EN EQU 0\r
-SD_TX_DMA__TERMIN_SEL EQU 0\r
-SD_TX_DMA__TERMOUT0_EN EQU 1\r
-SD_TX_DMA__TERMOUT0_SEL EQU 3\r
-SD_TX_DMA__TERMOUT1_EN EQU 0\r
-SD_TX_DMA__TERMOUT1_SEL EQU 0\r
-SD_TX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
-SD_TX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
-SD_TX_DMA_COMPLETE__INTC_MASK EQU 0x40\r
-SD_TX_DMA_COMPLETE__INTC_NUMBER EQU 6\r
-SD_TX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7\r
-SD_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_6\r
-SD_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
-SD_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
+; SD_CS\r
+SD_CS__0__INTTYPE EQU CYREG_PICU3_INTTYPE4\r
+SD_CS__0__MASK EQU 0x10\r
+SD_CS__0__PC EQU CYREG_PRT3_PC4\r
+SD_CS__0__PORT EQU 3\r
+SD_CS__0__SHIFT EQU 4\r
+SD_CS__AG EQU CYREG_PRT3_AG\r
+SD_CS__AMUX EQU CYREG_PRT3_AMUX\r
+SD_CS__BIE EQU CYREG_PRT3_BIE\r
+SD_CS__BIT_MASK EQU CYREG_PRT3_BIT_MASK\r
+SD_CS__BYP EQU CYREG_PRT3_BYP\r
+SD_CS__CTL EQU CYREG_PRT3_CTL\r
+SD_CS__DM0 EQU CYREG_PRT3_DM0\r
+SD_CS__DM1 EQU CYREG_PRT3_DM1\r
+SD_CS__DM2 EQU CYREG_PRT3_DM2\r
+SD_CS__DR EQU CYREG_PRT3_DR\r
+SD_CS__INP_DIS EQU CYREG_PRT3_INP_DIS\r
+SD_CS__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE\r
+SD_CS__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG\r
+SD_CS__LCD_EN EQU CYREG_PRT3_LCD_EN\r
+SD_CS__MASK EQU 0x10\r
+SD_CS__PORT EQU 3\r
+SD_CS__PRT EQU CYREG_PRT3_PRT\r
+SD_CS__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL\r
+SD_CS__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN\r
+SD_CS__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0\r
+SD_CS__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1\r
+SD_CS__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0\r
+SD_CS__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1\r
+SD_CS__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT\r
+SD_CS__PS EQU CYREG_PRT3_PS\r
+SD_CS__SHIFT EQU 4\r
+SD_CS__SLW EQU CYREG_PRT3_SLW\r
\r
; USBFS\r
USBFS_arb_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
USBFS_USB__USBIO_CR0 EQU CYREG_USB_USBIO_CR0\r
USBFS_USB__USBIO_CR1 EQU CYREG_USB_USBIO_CR1\r
\r
+; SDCard\r
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL\r
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB04_05_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB04_05_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB04_05_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB04_05_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB04_05_MSK\r
+SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB04_05_MSK\r
+SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB04_05_MSK\r
+SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB04_05_MSK\r
+SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL\r
+SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB04_CTL\r
+SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB04_ST_CTL\r
+SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB04_CTL\r
+SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB04_ST_CTL\r
+SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL\r
+SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL\r
+SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB04_MSK\r
+SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL\r
+SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB04_05_ST\r
+SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB04_MSK\r
+SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL\r
+SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB04_ST_CTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB04_ST_CTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB04_ST\r
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB08_09_ACTL\r
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB08_09_ST\r
+SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10\r
+SDCard_BSPIM_RxStsReg__4__POS EQU 4\r
+SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20\r
+SDCard_BSPIM_RxStsReg__5__POS EQU 5\r
+SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40\r
+SDCard_BSPIM_RxStsReg__6__POS EQU 6\r
+SDCard_BSPIM_RxStsReg__MASK EQU 0x70\r
+SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB08_MSK\r
+SDCard_BSPIM_RxStsReg__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB08_MSK_ACTL\r
+SDCard_BSPIM_RxStsReg__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB08_MSK_ACTL\r
+SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB08_ACTL\r
+SDCard_BSPIM_RxStsReg__STATUS_CNT_REG EQU CYREG_B1_UDB08_ST_CTL\r
+SDCard_BSPIM_RxStsReg__STATUS_CONTROL_REG EQU CYREG_B1_UDB08_ST_CTL\r
+SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB08_ST\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB04_05_A0\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB04_05_A1\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B1_UDB04_05_D0\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B1_UDB04_05_D1\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B1_UDB04_05_F0\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B1_UDB04_05_F1\r
+SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B1_UDB04_A0_A1\r
+SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B1_UDB04_A0\r
+SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B1_UDB04_A1\r
+SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B1_UDB04_D0_D1\r
+SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B1_UDB04_D0\r
+SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B1_UDB04_D1\r
+SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL\r
+SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B1_UDB04_F0_F1\r
+SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B1_UDB04_F0\r
+SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B1_UDB04_F1\r
+SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL\r
+SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL\r
+SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01\r
+SDCard_BSPIM_TxStsReg__0__POS EQU 0\r
+SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02\r
+SDCard_BSPIM_TxStsReg__1__POS EQU 1\r
+SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL\r
+SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST\r
+SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04\r
+SDCard_BSPIM_TxStsReg__2__POS EQU 2\r
+SDCard_BSPIM_TxStsReg__3__MASK EQU 0x08\r
+SDCard_BSPIM_TxStsReg__3__POS EQU 3\r
+SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10\r
+SDCard_BSPIM_TxStsReg__4__POS EQU 4\r
+SDCard_BSPIM_TxStsReg__MASK EQU 0x1F\r
+SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB07_MSK\r
+SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL\r
+SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB07_ST\r
+\r
+; SD_SCK\r
+SD_SCK__0__INTTYPE EQU CYREG_PICU3_INTTYPE2\r
+SD_SCK__0__MASK EQU 0x04\r
+SD_SCK__0__PC EQU CYREG_PRT3_PC2\r
+SD_SCK__0__PORT EQU 3\r
+SD_SCK__0__SHIFT EQU 2\r
+SD_SCK__AG EQU CYREG_PRT3_AG\r
+SD_SCK__AMUX EQU CYREG_PRT3_AMUX\r
+SD_SCK__BIE EQU CYREG_PRT3_BIE\r
+SD_SCK__BIT_MASK EQU CYREG_PRT3_BIT_MASK\r
+SD_SCK__BYP EQU CYREG_PRT3_BYP\r
+SD_SCK__CTL EQU CYREG_PRT3_CTL\r
+SD_SCK__DM0 EQU CYREG_PRT3_DM0\r
+SD_SCK__DM1 EQU CYREG_PRT3_DM1\r
+SD_SCK__DM2 EQU CYREG_PRT3_DM2\r
+SD_SCK__DR EQU CYREG_PRT3_DR\r
+SD_SCK__INP_DIS EQU CYREG_PRT3_INP_DIS\r
+SD_SCK__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE\r
+SD_SCK__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG\r
+SD_SCK__LCD_EN EQU CYREG_PRT3_LCD_EN\r
+SD_SCK__MASK EQU 0x04\r
+SD_SCK__PORT EQU 3\r
+SD_SCK__PRT EQU CYREG_PRT3_PRT\r
+SD_SCK__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL\r
+SD_SCK__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN\r
+SD_SCK__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0\r
+SD_SCK__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1\r
+SD_SCK__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0\r
+SD_SCK__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1\r
+SD_SCK__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT\r
+SD_SCK__PS EQU CYREG_PRT3_PS\r
+SD_SCK__SHIFT EQU 2\r
+SD_SCK__SLW EQU CYREG_PRT3_SLW\r
+\r
+; SCSI_In\r
+SCSI_In__0__AG EQU CYREG_PRT2_AG\r
+SCSI_In__0__AMUX EQU CYREG_PRT2_AMUX\r
+SCSI_In__0__BIE EQU CYREG_PRT2_BIE\r
+SCSI_In__0__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
+SCSI_In__0__BYP EQU CYREG_PRT2_BYP\r
+SCSI_In__0__CTL EQU CYREG_PRT2_CTL\r
+SCSI_In__0__DM0 EQU CYREG_PRT2_DM0\r
+SCSI_In__0__DM1 EQU CYREG_PRT2_DM1\r
+SCSI_In__0__DM2 EQU CYREG_PRT2_DM2\r
+SCSI_In__0__DR EQU CYREG_PRT2_DR\r
+SCSI_In__0__INP_DIS EQU CYREG_PRT2_INP_DIS\r
+SCSI_In__0__INTTYPE EQU CYREG_PICU2_INTTYPE0\r
+SCSI_In__0__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
+SCSI_In__0__LCD_EN EQU CYREG_PRT2_LCD_EN\r
+SCSI_In__0__MASK EQU 0x01\r
+SCSI_In__0__PC EQU CYREG_PRT2_PC0\r
+SCSI_In__0__PORT EQU 2\r
+SCSI_In__0__PRT EQU CYREG_PRT2_PRT\r
+SCSI_In__0__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
+SCSI_In__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
+SCSI_In__0__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
+SCSI_In__0__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
+SCSI_In__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
+SCSI_In__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
+SCSI_In__0__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
+SCSI_In__0__PS EQU CYREG_PRT2_PS\r
+SCSI_In__0__SHIFT EQU 0\r
+SCSI_In__0__SLW EQU CYREG_PRT2_SLW\r
+SCSI_In__1__AG EQU CYREG_PRT6_AG\r
+SCSI_In__1__AMUX EQU CYREG_PRT6_AMUX\r
+SCSI_In__1__BIE EQU CYREG_PRT6_BIE\r
+SCSI_In__1__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
+SCSI_In__1__BYP EQU CYREG_PRT6_BYP\r
+SCSI_In__1__CTL EQU CYREG_PRT6_CTL\r
+SCSI_In__1__DM0 EQU CYREG_PRT6_DM0\r
+SCSI_In__1__DM1 EQU CYREG_PRT6_DM1\r
+SCSI_In__1__DM2 EQU CYREG_PRT6_DM2\r
+SCSI_In__1__DR EQU CYREG_PRT6_DR\r
+SCSI_In__1__INP_DIS EQU CYREG_PRT6_INP_DIS\r
+SCSI_In__1__INTTYPE EQU CYREG_PICU6_INTTYPE7\r
+SCSI_In__1__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
+SCSI_In__1__LCD_EN EQU CYREG_PRT6_LCD_EN\r
+SCSI_In__1__MASK EQU 0x80\r
+SCSI_In__1__PC EQU CYREG_PRT6_PC7\r
+SCSI_In__1__PORT EQU 6\r
+SCSI_In__1__PRT EQU CYREG_PRT6_PRT\r
+SCSI_In__1__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
+SCSI_In__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
+SCSI_In__1__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
+SCSI_In__1__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
+SCSI_In__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
+SCSI_In__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
+SCSI_In__1__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
+SCSI_In__1__PS EQU CYREG_PRT6_PS\r
+SCSI_In__1__SHIFT EQU 7\r
+SCSI_In__1__SLW EQU CYREG_PRT6_SLW\r
+SCSI_In__2__AG EQU CYREG_PRT5_AG\r
+SCSI_In__2__AMUX EQU CYREG_PRT5_AMUX\r
+SCSI_In__2__BIE EQU CYREG_PRT5_BIE\r
+SCSI_In__2__BIT_MASK EQU CYREG_PRT5_BIT_MASK\r
+SCSI_In__2__BYP EQU CYREG_PRT5_BYP\r
+SCSI_In__2__CTL EQU CYREG_PRT5_CTL\r
+SCSI_In__2__DM0 EQU CYREG_PRT5_DM0\r
+SCSI_In__2__DM1 EQU CYREG_PRT5_DM1\r
+SCSI_In__2__DM2 EQU CYREG_PRT5_DM2\r
+SCSI_In__2__DR EQU CYREG_PRT5_DR\r
+SCSI_In__2__INP_DIS EQU CYREG_PRT5_INP_DIS\r
+SCSI_In__2__INTTYPE EQU CYREG_PICU5_INTTYPE1\r
+SCSI_In__2__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG\r
+SCSI_In__2__LCD_EN EQU CYREG_PRT5_LCD_EN\r
+SCSI_In__2__MASK EQU 0x02\r
+SCSI_In__2__PC EQU CYREG_PRT5_PC1\r
+SCSI_In__2__PORT EQU 5\r
+SCSI_In__2__PRT EQU CYREG_PRT5_PRT\r
+SCSI_In__2__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL\r
+SCSI_In__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN\r
+SCSI_In__2__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0\r
+SCSI_In__2__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1\r
+SCSI_In__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0\r
+SCSI_In__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1\r
+SCSI_In__2__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT\r
+SCSI_In__2__PS EQU CYREG_PRT5_PS\r
+SCSI_In__2__SHIFT EQU 1\r
+SCSI_In__2__SLW EQU CYREG_PRT5_SLW\r
+SCSI_In__3__AG EQU CYREG_PRT5_AG\r
+SCSI_In__3__AMUX EQU CYREG_PRT5_AMUX\r
+SCSI_In__3__BIE EQU CYREG_PRT5_BIE\r
+SCSI_In__3__BIT_MASK EQU CYREG_PRT5_BIT_MASK\r
+SCSI_In__3__BYP EQU CYREG_PRT5_BYP\r
+SCSI_In__3__CTL EQU CYREG_PRT5_CTL\r
+SCSI_In__3__DM0 EQU CYREG_PRT5_DM0\r
+SCSI_In__3__DM1 EQU CYREG_PRT5_DM1\r
+SCSI_In__3__DM2 EQU CYREG_PRT5_DM2\r
+SCSI_In__3__DR EQU CYREG_PRT5_DR\r
+SCSI_In__3__INP_DIS EQU CYREG_PRT5_INP_DIS\r
+SCSI_In__3__INTTYPE EQU CYREG_PICU5_INTTYPE2\r
+SCSI_In__3__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG\r
+SCSI_In__3__LCD_EN EQU CYREG_PRT5_LCD_EN\r
+SCSI_In__3__MASK EQU 0x04\r
+SCSI_In__3__PC EQU CYREG_PRT5_PC2\r
+SCSI_In__3__PORT EQU 5\r
+SCSI_In__3__PRT EQU CYREG_PRT5_PRT\r
+SCSI_In__3__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL\r
+SCSI_In__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN\r
+SCSI_In__3__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0\r
+SCSI_In__3__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1\r
+SCSI_In__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0\r
+SCSI_In__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1\r
+SCSI_In__3__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT\r
+SCSI_In__3__PS EQU CYREG_PRT5_PS\r
+SCSI_In__3__SHIFT EQU 2\r
+SCSI_In__3__SLW EQU CYREG_PRT5_SLW\r
+SCSI_In__4__AG EQU CYREG_PRT5_AG\r
+SCSI_In__4__AMUX EQU CYREG_PRT5_AMUX\r
+SCSI_In__4__BIE EQU CYREG_PRT5_BIE\r
+SCSI_In__4__BIT_MASK EQU CYREG_PRT5_BIT_MASK\r
+SCSI_In__4__BYP EQU CYREG_PRT5_BYP\r
+SCSI_In__4__CTL EQU CYREG_PRT5_CTL\r
+SCSI_In__4__DM0 EQU CYREG_PRT5_DM0\r
+SCSI_In__4__DM1 EQU CYREG_PRT5_DM1\r
+SCSI_In__4__DM2 EQU CYREG_PRT5_DM2\r
+SCSI_In__4__DR EQU CYREG_PRT5_DR\r
+SCSI_In__4__INP_DIS EQU CYREG_PRT5_INP_DIS\r
+SCSI_In__4__INTTYPE EQU CYREG_PICU5_INTTYPE3\r
+SCSI_In__4__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG\r
+SCSI_In__4__LCD_EN EQU CYREG_PRT5_LCD_EN\r
+SCSI_In__4__MASK EQU 0x08\r
+SCSI_In__4__PC EQU CYREG_PRT5_PC3\r
+SCSI_In__4__PORT EQU 5\r
+SCSI_In__4__PRT EQU CYREG_PRT5_PRT\r
+SCSI_In__4__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL\r
+SCSI_In__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN\r
+SCSI_In__4__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0\r
+SCSI_In__4__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1\r
+SCSI_In__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0\r
+SCSI_In__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1\r
+SCSI_In__4__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT\r
+SCSI_In__4__PS EQU CYREG_PRT5_PS\r
+SCSI_In__4__SHIFT EQU 3\r
+SCSI_In__4__SLW EQU CYREG_PRT5_SLW\r
+SCSI_In__CD__AG EQU CYREG_PRT5_AG\r
+SCSI_In__CD__AMUX EQU CYREG_PRT5_AMUX\r
+SCSI_In__CD__BIE EQU CYREG_PRT5_BIE\r
+SCSI_In__CD__BIT_MASK EQU CYREG_PRT5_BIT_MASK\r
+SCSI_In__CD__BYP EQU CYREG_PRT5_BYP\r
+SCSI_In__CD__CTL EQU CYREG_PRT5_CTL\r
+SCSI_In__CD__DM0 EQU CYREG_PRT5_DM0\r
+SCSI_In__CD__DM1 EQU CYREG_PRT5_DM1\r
+SCSI_In__CD__DM2 EQU CYREG_PRT5_DM2\r
+SCSI_In__CD__DR EQU CYREG_PRT5_DR\r
+SCSI_In__CD__INP_DIS EQU CYREG_PRT5_INP_DIS\r
+SCSI_In__CD__INTTYPE EQU CYREG_PICU5_INTTYPE1\r
+SCSI_In__CD__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG\r
+SCSI_In__CD__LCD_EN EQU CYREG_PRT5_LCD_EN\r
+SCSI_In__CD__MASK EQU 0x02\r
+SCSI_In__CD__PC EQU CYREG_PRT5_PC1\r
+SCSI_In__CD__PORT EQU 5\r
+SCSI_In__CD__PRT EQU CYREG_PRT5_PRT\r
+SCSI_In__CD__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL\r
+SCSI_In__CD__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN\r
+SCSI_In__CD__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0\r
+SCSI_In__CD__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1\r
+SCSI_In__CD__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0\r
+SCSI_In__CD__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1\r
+SCSI_In__CD__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT\r
+SCSI_In__CD__PS EQU CYREG_PRT5_PS\r
+SCSI_In__CD__SHIFT EQU 1\r
+SCSI_In__CD__SLW EQU CYREG_PRT5_SLW\r
+SCSI_In__DBP__AG EQU CYREG_PRT2_AG\r
+SCSI_In__DBP__AMUX EQU CYREG_PRT2_AMUX\r
+SCSI_In__DBP__BIE EQU CYREG_PRT2_BIE\r
+SCSI_In__DBP__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
+SCSI_In__DBP__BYP EQU CYREG_PRT2_BYP\r
+SCSI_In__DBP__CTL EQU CYREG_PRT2_CTL\r
+SCSI_In__DBP__DM0 EQU CYREG_PRT2_DM0\r
+SCSI_In__DBP__DM1 EQU CYREG_PRT2_DM1\r
+SCSI_In__DBP__DM2 EQU CYREG_PRT2_DM2\r
+SCSI_In__DBP__DR EQU CYREG_PRT2_DR\r
+SCSI_In__DBP__INP_DIS EQU CYREG_PRT2_INP_DIS\r
+SCSI_In__DBP__INTTYPE EQU CYREG_PICU2_INTTYPE0\r
+SCSI_In__DBP__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
+SCSI_In__DBP__LCD_EN EQU CYREG_PRT2_LCD_EN\r
+SCSI_In__DBP__MASK EQU 0x01\r
+SCSI_In__DBP__PC EQU CYREG_PRT2_PC0\r
+SCSI_In__DBP__PORT EQU 2\r
+SCSI_In__DBP__PRT EQU CYREG_PRT2_PRT\r
+SCSI_In__DBP__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
+SCSI_In__DBP__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
+SCSI_In__DBP__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
+SCSI_In__DBP__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
+SCSI_In__DBP__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
+SCSI_In__DBP__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
+SCSI_In__DBP__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
+SCSI_In__DBP__PS EQU CYREG_PRT2_PS\r
+SCSI_In__DBP__SHIFT EQU 0\r
+SCSI_In__DBP__SLW EQU CYREG_PRT2_SLW\r
+SCSI_In__IO__AG EQU CYREG_PRT5_AG\r
+SCSI_In__IO__AMUX EQU CYREG_PRT5_AMUX\r
+SCSI_In__IO__BIE EQU CYREG_PRT5_BIE\r
+SCSI_In__IO__BIT_MASK EQU CYREG_PRT5_BIT_MASK\r
+SCSI_In__IO__BYP EQU CYREG_PRT5_BYP\r
+SCSI_In__IO__CTL EQU CYREG_PRT5_CTL\r
+SCSI_In__IO__DM0 EQU CYREG_PRT5_DM0\r
+SCSI_In__IO__DM1 EQU CYREG_PRT5_DM1\r
+SCSI_In__IO__DM2 EQU CYREG_PRT5_DM2\r
+SCSI_In__IO__DR EQU CYREG_PRT5_DR\r
+SCSI_In__IO__INP_DIS EQU CYREG_PRT5_INP_DIS\r
+SCSI_In__IO__INTTYPE EQU CYREG_PICU5_INTTYPE3\r
+SCSI_In__IO__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG\r
+SCSI_In__IO__LCD_EN EQU CYREG_PRT5_LCD_EN\r
+SCSI_In__IO__MASK EQU 0x08\r
+SCSI_In__IO__PC EQU CYREG_PRT5_PC3\r
+SCSI_In__IO__PORT EQU 5\r
+SCSI_In__IO__PRT EQU CYREG_PRT5_PRT\r
+SCSI_In__IO__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL\r
+SCSI_In__IO__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN\r
+SCSI_In__IO__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0\r
+SCSI_In__IO__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1\r
+SCSI_In__IO__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0\r
+SCSI_In__IO__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1\r
+SCSI_In__IO__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT\r
+SCSI_In__IO__PS EQU CYREG_PRT5_PS\r
+SCSI_In__IO__SHIFT EQU 3\r
+SCSI_In__IO__SLW EQU CYREG_PRT5_SLW\r
+SCSI_In__MSG__AG EQU CYREG_PRT6_AG\r
+SCSI_In__MSG__AMUX EQU CYREG_PRT6_AMUX\r
+SCSI_In__MSG__BIE EQU CYREG_PRT6_BIE\r
+SCSI_In__MSG__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
+SCSI_In__MSG__BYP EQU CYREG_PRT6_BYP\r
+SCSI_In__MSG__CTL EQU CYREG_PRT6_CTL\r
+SCSI_In__MSG__DM0 EQU CYREG_PRT6_DM0\r
+SCSI_In__MSG__DM1 EQU CYREG_PRT6_DM1\r
+SCSI_In__MSG__DM2 EQU CYREG_PRT6_DM2\r
+SCSI_In__MSG__DR EQU CYREG_PRT6_DR\r
+SCSI_In__MSG__INP_DIS EQU CYREG_PRT6_INP_DIS\r
+SCSI_In__MSG__INTTYPE EQU CYREG_PICU6_INTTYPE7\r
+SCSI_In__MSG__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
+SCSI_In__MSG__LCD_EN EQU CYREG_PRT6_LCD_EN\r
+SCSI_In__MSG__MASK EQU 0x80\r
+SCSI_In__MSG__PC EQU CYREG_PRT6_PC7\r
+SCSI_In__MSG__PORT EQU 6\r
+SCSI_In__MSG__PRT EQU CYREG_PRT6_PRT\r
+SCSI_In__MSG__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
+SCSI_In__MSG__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
+SCSI_In__MSG__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
+SCSI_In__MSG__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
+SCSI_In__MSG__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
+SCSI_In__MSG__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
+SCSI_In__MSG__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
+SCSI_In__MSG__PS EQU CYREG_PRT6_PS\r
+SCSI_In__MSG__SHIFT EQU 7\r
+SCSI_In__MSG__SLW EQU CYREG_PRT6_SLW\r
+SCSI_In__REQ__AG EQU CYREG_PRT5_AG\r
+SCSI_In__REQ__AMUX EQU CYREG_PRT5_AMUX\r
+SCSI_In__REQ__BIE EQU CYREG_PRT5_BIE\r
+SCSI_In__REQ__BIT_MASK EQU CYREG_PRT5_BIT_MASK\r
+SCSI_In__REQ__BYP EQU CYREG_PRT5_BYP\r
+SCSI_In__REQ__CTL EQU CYREG_PRT5_CTL\r
+SCSI_In__REQ__DM0 EQU CYREG_PRT5_DM0\r
+SCSI_In__REQ__DM1 EQU CYREG_PRT5_DM1\r
+SCSI_In__REQ__DM2 EQU CYREG_PRT5_DM2\r
+SCSI_In__REQ__DR EQU CYREG_PRT5_DR\r
+SCSI_In__REQ__INP_DIS EQU CYREG_PRT5_INP_DIS\r
+SCSI_In__REQ__INTTYPE EQU CYREG_PICU5_INTTYPE2\r
+SCSI_In__REQ__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG\r
+SCSI_In__REQ__LCD_EN EQU CYREG_PRT5_LCD_EN\r
+SCSI_In__REQ__MASK EQU 0x04\r
+SCSI_In__REQ__PC EQU CYREG_PRT5_PC2\r
+SCSI_In__REQ__PORT EQU 5\r
+SCSI_In__REQ__PRT EQU CYREG_PRT5_PRT\r
+SCSI_In__REQ__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL\r
+SCSI_In__REQ__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN\r
+SCSI_In__REQ__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0\r
+SCSI_In__REQ__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1\r
+SCSI_In__REQ__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0\r
+SCSI_In__REQ__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1\r
+SCSI_In__REQ__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT\r
+SCSI_In__REQ__PS EQU CYREG_PRT5_PS\r
+SCSI_In__REQ__SHIFT EQU 2\r
+SCSI_In__REQ__SLW EQU CYREG_PRT5_SLW\r
+SCSI_In_DBx__0__AG EQU CYREG_PRT12_AG\r
+SCSI_In_DBx__0__BIE EQU CYREG_PRT12_BIE\r
+SCSI_In_DBx__0__BIT_MASK EQU CYREG_PRT12_BIT_MASK\r
+SCSI_In_DBx__0__BYP EQU CYREG_PRT12_BYP\r
+SCSI_In_DBx__0__DM0 EQU CYREG_PRT12_DM0\r
+SCSI_In_DBx__0__DM1 EQU CYREG_PRT12_DM1\r
+SCSI_In_DBx__0__DM2 EQU CYREG_PRT12_DM2\r
+SCSI_In_DBx__0__DR EQU CYREG_PRT12_DR\r
+SCSI_In_DBx__0__INP_DIS EQU CYREG_PRT12_INP_DIS\r
+SCSI_In_DBx__0__INTTYPE EQU CYREG_PICU12_INTTYPE4\r
+SCSI_In_DBx__0__MASK EQU 0x10\r
+SCSI_In_DBx__0__PC EQU CYREG_PRT12_PC4\r
+SCSI_In_DBx__0__PORT EQU 12\r
+SCSI_In_DBx__0__PRT EQU CYREG_PRT12_PRT\r
+SCSI_In_DBx__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN\r
+SCSI_In_DBx__0__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0\r
+SCSI_In_DBx__0__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1\r
+SCSI_In_DBx__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0\r
+SCSI_In_DBx__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1\r
+SCSI_In_DBx__0__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT\r
+SCSI_In_DBx__0__PS EQU CYREG_PRT12_PS\r
+SCSI_In_DBx__0__SHIFT EQU 4\r
+SCSI_In_DBx__0__SIO_CFG EQU CYREG_PRT12_SIO_CFG\r
+SCSI_In_DBx__0__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF\r
+SCSI_In_DBx__0__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN\r
+SCSI_In_DBx__0__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ\r
+SCSI_In_DBx__0__SLW EQU CYREG_PRT12_SLW\r
+SCSI_In_DBx__1__AG EQU CYREG_PRT2_AG\r
+SCSI_In_DBx__1__AMUX EQU CYREG_PRT2_AMUX\r
+SCSI_In_DBx__1__BIE EQU CYREG_PRT2_BIE\r
+SCSI_In_DBx__1__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
+SCSI_In_DBx__1__BYP EQU CYREG_PRT2_BYP\r
+SCSI_In_DBx__1__CTL EQU CYREG_PRT2_CTL\r
+SCSI_In_DBx__1__DM0 EQU CYREG_PRT2_DM0\r
+SCSI_In_DBx__1__DM1 EQU CYREG_PRT2_DM1\r
+SCSI_In_DBx__1__DM2 EQU CYREG_PRT2_DM2\r
+SCSI_In_DBx__1__DR EQU CYREG_PRT2_DR\r
+SCSI_In_DBx__1__INP_DIS EQU CYREG_PRT2_INP_DIS\r
+SCSI_In_DBx__1__INTTYPE EQU CYREG_PICU2_INTTYPE7\r
+SCSI_In_DBx__1__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
+SCSI_In_DBx__1__LCD_EN EQU CYREG_PRT2_LCD_EN\r
+SCSI_In_DBx__1__MASK EQU 0x80\r
+SCSI_In_DBx__1__PC EQU CYREG_PRT2_PC7\r
+SCSI_In_DBx__1__PORT EQU 2\r
+SCSI_In_DBx__1__PRT EQU CYREG_PRT2_PRT\r
+SCSI_In_DBx__1__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
+SCSI_In_DBx__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
+SCSI_In_DBx__1__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
+SCSI_In_DBx__1__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
+SCSI_In_DBx__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
+SCSI_In_DBx__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
+SCSI_In_DBx__1__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
+SCSI_In_DBx__1__PS EQU CYREG_PRT2_PS\r
+SCSI_In_DBx__1__SHIFT EQU 7\r
+SCSI_In_DBx__1__SLW EQU CYREG_PRT2_SLW\r
+SCSI_In_DBx__2__AG EQU CYREG_PRT2_AG\r
+SCSI_In_DBx__2__AMUX EQU CYREG_PRT2_AMUX\r
+SCSI_In_DBx__2__BIE EQU CYREG_PRT2_BIE\r
+SCSI_In_DBx__2__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
+SCSI_In_DBx__2__BYP EQU CYREG_PRT2_BYP\r
+SCSI_In_DBx__2__CTL EQU CYREG_PRT2_CTL\r
+SCSI_In_DBx__2__DM0 EQU CYREG_PRT2_DM0\r
+SCSI_In_DBx__2__DM1 EQU CYREG_PRT2_DM1\r
+SCSI_In_DBx__2__DM2 EQU CYREG_PRT2_DM2\r
+SCSI_In_DBx__2__DR EQU CYREG_PRT2_DR\r
+SCSI_In_DBx__2__INP_DIS EQU CYREG_PRT2_INP_DIS\r
+SCSI_In_DBx__2__INTTYPE EQU CYREG_PICU2_INTTYPE6\r
+SCSI_In_DBx__2__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
+SCSI_In_DBx__2__LCD_EN EQU CYREG_PRT2_LCD_EN\r
+SCSI_In_DBx__2__MASK EQU 0x40\r
+SCSI_In_DBx__2__PC EQU CYREG_PRT2_PC6\r
+SCSI_In_DBx__2__PORT EQU 2\r
+SCSI_In_DBx__2__PRT EQU CYREG_PRT2_PRT\r
+SCSI_In_DBx__2__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
+SCSI_In_DBx__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
+SCSI_In_DBx__2__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
+SCSI_In_DBx__2__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
+SCSI_In_DBx__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
+SCSI_In_DBx__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
+SCSI_In_DBx__2__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
+SCSI_In_DBx__2__PS EQU CYREG_PRT2_PS\r
+SCSI_In_DBx__2__SHIFT EQU 6\r
+SCSI_In_DBx__2__SLW EQU CYREG_PRT2_SLW\r
+SCSI_In_DBx__3__AG EQU CYREG_PRT2_AG\r
+SCSI_In_DBx__3__AMUX EQU CYREG_PRT2_AMUX\r
+SCSI_In_DBx__3__BIE EQU CYREG_PRT2_BIE\r
+SCSI_In_DBx__3__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
+SCSI_In_DBx__3__BYP EQU CYREG_PRT2_BYP\r
+SCSI_In_DBx__3__CTL EQU CYREG_PRT2_CTL\r
+SCSI_In_DBx__3__DM0 EQU CYREG_PRT2_DM0\r
+SCSI_In_DBx__3__DM1 EQU CYREG_PRT2_DM1\r
+SCSI_In_DBx__3__DM2 EQU CYREG_PRT2_DM2\r
+SCSI_In_DBx__3__DR EQU CYREG_PRT2_DR\r
+SCSI_In_DBx__3__INP_DIS EQU CYREG_PRT2_INP_DIS\r
+SCSI_In_DBx__3__INTTYPE EQU CYREG_PICU2_INTTYPE5\r
+SCSI_In_DBx__3__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
+SCSI_In_DBx__3__LCD_EN EQU CYREG_PRT2_LCD_EN\r
+SCSI_In_DBx__3__MASK EQU 0x20\r
+SCSI_In_DBx__3__PC EQU CYREG_PRT2_PC5\r
+SCSI_In_DBx__3__PORT EQU 2\r
+SCSI_In_DBx__3__PRT EQU CYREG_PRT2_PRT\r
+SCSI_In_DBx__3__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
+SCSI_In_DBx__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
+SCSI_In_DBx__3__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
+SCSI_In_DBx__3__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
+SCSI_In_DBx__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
+SCSI_In_DBx__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
+SCSI_In_DBx__3__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
+SCSI_In_DBx__3__PS EQU CYREG_PRT2_PS\r
+SCSI_In_DBx__3__SHIFT EQU 5\r
+SCSI_In_DBx__3__SLW EQU CYREG_PRT2_SLW\r
+SCSI_In_DBx__4__AG EQU CYREG_PRT2_AG\r
+SCSI_In_DBx__4__AMUX EQU CYREG_PRT2_AMUX\r
+SCSI_In_DBx__4__BIE EQU CYREG_PRT2_BIE\r
+SCSI_In_DBx__4__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
+SCSI_In_DBx__4__BYP EQU CYREG_PRT2_BYP\r
+SCSI_In_DBx__4__CTL EQU CYREG_PRT2_CTL\r
+SCSI_In_DBx__4__DM0 EQU CYREG_PRT2_DM0\r
+SCSI_In_DBx__4__DM1 EQU CYREG_PRT2_DM1\r
+SCSI_In_DBx__4__DM2 EQU CYREG_PRT2_DM2\r
+SCSI_In_DBx__4__DR EQU CYREG_PRT2_DR\r
+SCSI_In_DBx__4__INP_DIS EQU CYREG_PRT2_INP_DIS\r
+SCSI_In_DBx__4__INTTYPE EQU CYREG_PICU2_INTTYPE4\r
+SCSI_In_DBx__4__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
+SCSI_In_DBx__4__LCD_EN EQU CYREG_PRT2_LCD_EN\r
+SCSI_In_DBx__4__MASK EQU 0x10\r
+SCSI_In_DBx__4__PC EQU CYREG_PRT2_PC4\r
+SCSI_In_DBx__4__PORT EQU 2\r
+SCSI_In_DBx__4__PRT EQU CYREG_PRT2_PRT\r
+SCSI_In_DBx__4__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
+SCSI_In_DBx__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
+SCSI_In_DBx__4__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
+SCSI_In_DBx__4__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
+SCSI_In_DBx__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
+SCSI_In_DBx__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
+SCSI_In_DBx__4__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
+SCSI_In_DBx__4__PS EQU CYREG_PRT2_PS\r
+SCSI_In_DBx__4__SHIFT EQU 4\r
+SCSI_In_DBx__4__SLW EQU CYREG_PRT2_SLW\r
+SCSI_In_DBx__5__AG EQU CYREG_PRT2_AG\r
+SCSI_In_DBx__5__AMUX EQU CYREG_PRT2_AMUX\r
+SCSI_In_DBx__5__BIE EQU CYREG_PRT2_BIE\r
+SCSI_In_DBx__5__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
+SCSI_In_DBx__5__BYP EQU CYREG_PRT2_BYP\r
+SCSI_In_DBx__5__CTL EQU CYREG_PRT2_CTL\r
+SCSI_In_DBx__5__DM0 EQU CYREG_PRT2_DM0\r
+SCSI_In_DBx__5__DM1 EQU CYREG_PRT2_DM1\r
+SCSI_In_DBx__5__DM2 EQU CYREG_PRT2_DM2\r
+SCSI_In_DBx__5__DR EQU CYREG_PRT2_DR\r
+SCSI_In_DBx__5__INP_DIS EQU CYREG_PRT2_INP_DIS\r
+SCSI_In_DBx__5__INTTYPE EQU CYREG_PICU2_INTTYPE3\r
+SCSI_In_DBx__5__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
+SCSI_In_DBx__5__LCD_EN EQU CYREG_PRT2_LCD_EN\r
+SCSI_In_DBx__5__MASK EQU 0x08\r
+SCSI_In_DBx__5__PC EQU CYREG_PRT2_PC3\r
+SCSI_In_DBx__5__PORT EQU 2\r
+SCSI_In_DBx__5__PRT EQU CYREG_PRT2_PRT\r
+SCSI_In_DBx__5__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
+SCSI_In_DBx__5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
+SCSI_In_DBx__5__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
+SCSI_In_DBx__5__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
+SCSI_In_DBx__5__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
+SCSI_In_DBx__5__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
+SCSI_In_DBx__5__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
+SCSI_In_DBx__5__PS EQU CYREG_PRT2_PS\r
+SCSI_In_DBx__5__SHIFT EQU 3\r
+SCSI_In_DBx__5__SLW EQU CYREG_PRT2_SLW\r
+SCSI_In_DBx__6__AG EQU CYREG_PRT2_AG\r
+SCSI_In_DBx__6__AMUX EQU CYREG_PRT2_AMUX\r
+SCSI_In_DBx__6__BIE EQU CYREG_PRT2_BIE\r
+SCSI_In_DBx__6__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
+SCSI_In_DBx__6__BYP EQU CYREG_PRT2_BYP\r
+SCSI_In_DBx__6__CTL EQU CYREG_PRT2_CTL\r
+SCSI_In_DBx__6__DM0 EQU CYREG_PRT2_DM0\r
+SCSI_In_DBx__6__DM1 EQU CYREG_PRT2_DM1\r
+SCSI_In_DBx__6__DM2 EQU CYREG_PRT2_DM2\r
+SCSI_In_DBx__6__DR EQU CYREG_PRT2_DR\r
+SCSI_In_DBx__6__INP_DIS EQU CYREG_PRT2_INP_DIS\r
+SCSI_In_DBx__6__INTTYPE EQU CYREG_PICU2_INTTYPE2\r
+SCSI_In_DBx__6__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
+SCSI_In_DBx__6__LCD_EN EQU CYREG_PRT2_LCD_EN\r
+SCSI_In_DBx__6__MASK EQU 0x04\r
+SCSI_In_DBx__6__PC EQU CYREG_PRT2_PC2\r
+SCSI_In_DBx__6__PORT EQU 2\r
+SCSI_In_DBx__6__PRT EQU CYREG_PRT2_PRT\r
+SCSI_In_DBx__6__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
+SCSI_In_DBx__6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
+SCSI_In_DBx__6__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
+SCSI_In_DBx__6__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
+SCSI_In_DBx__6__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
+SCSI_In_DBx__6__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
+SCSI_In_DBx__6__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
+SCSI_In_DBx__6__PS EQU CYREG_PRT2_PS\r
+SCSI_In_DBx__6__SHIFT EQU 2\r
+SCSI_In_DBx__6__SLW EQU CYREG_PRT2_SLW\r
+SCSI_In_DBx__7__AG EQU CYREG_PRT2_AG\r
+SCSI_In_DBx__7__AMUX EQU CYREG_PRT2_AMUX\r
+SCSI_In_DBx__7__BIE EQU CYREG_PRT2_BIE\r
+SCSI_In_DBx__7__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
+SCSI_In_DBx__7__BYP EQU CYREG_PRT2_BYP\r
+SCSI_In_DBx__7__CTL EQU CYREG_PRT2_CTL\r
+SCSI_In_DBx__7__DM0 EQU CYREG_PRT2_DM0\r
+SCSI_In_DBx__7__DM1 EQU CYREG_PRT2_DM1\r
+SCSI_In_DBx__7__DM2 EQU CYREG_PRT2_DM2\r
+SCSI_In_DBx__7__DR EQU CYREG_PRT2_DR\r
+SCSI_In_DBx__7__INP_DIS EQU CYREG_PRT2_INP_DIS\r
+SCSI_In_DBx__7__INTTYPE EQU CYREG_PICU2_INTTYPE1\r
+SCSI_In_DBx__7__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
+SCSI_In_DBx__7__LCD_EN EQU CYREG_PRT2_LCD_EN\r
+SCSI_In_DBx__7__MASK EQU 0x02\r
+SCSI_In_DBx__7__PC EQU CYREG_PRT2_PC1\r
+SCSI_In_DBx__7__PORT EQU 2\r
+SCSI_In_DBx__7__PRT EQU CYREG_PRT2_PRT\r
+SCSI_In_DBx__7__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
+SCSI_In_DBx__7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
+SCSI_In_DBx__7__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
+SCSI_In_DBx__7__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
+SCSI_In_DBx__7__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
+SCSI_In_DBx__7__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
+SCSI_In_DBx__7__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
+SCSI_In_DBx__7__PS EQU CYREG_PRT2_PS\r
+SCSI_In_DBx__7__SHIFT EQU 1\r
+SCSI_In_DBx__7__SLW EQU CYREG_PRT2_SLW\r
+SCSI_In_DBx__DB0__AG EQU CYREG_PRT12_AG\r
+SCSI_In_DBx__DB0__BIE EQU CYREG_PRT12_BIE\r
+SCSI_In_DBx__DB0__BIT_MASK EQU CYREG_PRT12_BIT_MASK\r
+SCSI_In_DBx__DB0__BYP EQU CYREG_PRT12_BYP\r
+SCSI_In_DBx__DB0__DM0 EQU CYREG_PRT12_DM0\r
+SCSI_In_DBx__DB0__DM1 EQU CYREG_PRT12_DM1\r
+SCSI_In_DBx__DB0__DM2 EQU CYREG_PRT12_DM2\r
+SCSI_In_DBx__DB0__DR EQU CYREG_PRT12_DR\r
+SCSI_In_DBx__DB0__INP_DIS EQU CYREG_PRT12_INP_DIS\r
+SCSI_In_DBx__DB0__INTTYPE EQU CYREG_PICU12_INTTYPE4\r
+SCSI_In_DBx__DB0__MASK EQU 0x10\r
+SCSI_In_DBx__DB0__PC EQU CYREG_PRT12_PC4\r
+SCSI_In_DBx__DB0__PORT EQU 12\r
+SCSI_In_DBx__DB0__PRT EQU CYREG_PRT12_PRT\r
+SCSI_In_DBx__DB0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN\r
+SCSI_In_DBx__DB0__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0\r
+SCSI_In_DBx__DB0__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1\r
+SCSI_In_DBx__DB0__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0\r
+SCSI_In_DBx__DB0__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1\r
+SCSI_In_DBx__DB0__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT\r
+SCSI_In_DBx__DB0__PS EQU CYREG_PRT12_PS\r
+SCSI_In_DBx__DB0__SHIFT EQU 4\r
+SCSI_In_DBx__DB0__SIO_CFG EQU CYREG_PRT12_SIO_CFG\r
+SCSI_In_DBx__DB0__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF\r
+SCSI_In_DBx__DB0__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN\r
+SCSI_In_DBx__DB0__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ\r
+SCSI_In_DBx__DB0__SLW EQU CYREG_PRT12_SLW\r
+SCSI_In_DBx__DB1__AG EQU CYREG_PRT2_AG\r
+SCSI_In_DBx__DB1__AMUX EQU CYREG_PRT2_AMUX\r
+SCSI_In_DBx__DB1__BIE EQU CYREG_PRT2_BIE\r
+SCSI_In_DBx__DB1__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
+SCSI_In_DBx__DB1__BYP EQU CYREG_PRT2_BYP\r
+SCSI_In_DBx__DB1__CTL EQU CYREG_PRT2_CTL\r
+SCSI_In_DBx__DB1__DM0 EQU CYREG_PRT2_DM0\r
+SCSI_In_DBx__DB1__DM1 EQU CYREG_PRT2_DM1\r
+SCSI_In_DBx__DB1__DM2 EQU CYREG_PRT2_DM2\r
+SCSI_In_DBx__DB1__DR EQU CYREG_PRT2_DR\r
+SCSI_In_DBx__DB1__INP_DIS EQU CYREG_PRT2_INP_DIS\r
+SCSI_In_DBx__DB1__INTTYPE EQU CYREG_PICU2_INTTYPE7\r
+SCSI_In_DBx__DB1__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
+SCSI_In_DBx__DB1__LCD_EN EQU CYREG_PRT2_LCD_EN\r
+SCSI_In_DBx__DB1__MASK EQU 0x80\r
+SCSI_In_DBx__DB1__PC EQU CYREG_PRT2_PC7\r
+SCSI_In_DBx__DB1__PORT EQU 2\r
+SCSI_In_DBx__DB1__PRT EQU CYREG_PRT2_PRT\r
+SCSI_In_DBx__DB1__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
+SCSI_In_DBx__DB1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
+SCSI_In_DBx__DB1__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
+SCSI_In_DBx__DB1__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
+SCSI_In_DBx__DB1__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
+SCSI_In_DBx__DB1__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
+SCSI_In_DBx__DB1__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
+SCSI_In_DBx__DB1__PS EQU CYREG_PRT2_PS\r
+SCSI_In_DBx__DB1__SHIFT EQU 7\r
+SCSI_In_DBx__DB1__SLW EQU CYREG_PRT2_SLW\r
+SCSI_In_DBx__DB2__AG EQU CYREG_PRT2_AG\r
+SCSI_In_DBx__DB2__AMUX EQU CYREG_PRT2_AMUX\r
+SCSI_In_DBx__DB2__BIE EQU CYREG_PRT2_BIE\r
+SCSI_In_DBx__DB2__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
+SCSI_In_DBx__DB2__BYP EQU CYREG_PRT2_BYP\r
+SCSI_In_DBx__DB2__CTL EQU CYREG_PRT2_CTL\r
+SCSI_In_DBx__DB2__DM0 EQU CYREG_PRT2_DM0\r
+SCSI_In_DBx__DB2__DM1 EQU CYREG_PRT2_DM1\r
+SCSI_In_DBx__DB2__DM2 EQU CYREG_PRT2_DM2\r
+SCSI_In_DBx__DB2__DR EQU CYREG_PRT2_DR\r
+SCSI_In_DBx__DB2__INP_DIS EQU CYREG_PRT2_INP_DIS\r
+SCSI_In_DBx__DB2__INTTYPE EQU CYREG_PICU2_INTTYPE6\r
+SCSI_In_DBx__DB2__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
+SCSI_In_DBx__DB2__LCD_EN EQU CYREG_PRT2_LCD_EN\r
+SCSI_In_DBx__DB2__MASK EQU 0x40\r
+SCSI_In_DBx__DB2__PC EQU CYREG_PRT2_PC6\r
+SCSI_In_DBx__DB2__PORT EQU 2\r
+SCSI_In_DBx__DB2__PRT EQU CYREG_PRT2_PRT\r
+SCSI_In_DBx__DB2__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
+SCSI_In_DBx__DB2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
+SCSI_In_DBx__DB2__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
+SCSI_In_DBx__DB2__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
+SCSI_In_DBx__DB2__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
+SCSI_In_DBx__DB2__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
+SCSI_In_DBx__DB2__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
+SCSI_In_DBx__DB2__PS EQU CYREG_PRT2_PS\r
+SCSI_In_DBx__DB2__SHIFT EQU 6\r
+SCSI_In_DBx__DB2__SLW EQU CYREG_PRT2_SLW\r
+SCSI_In_DBx__DB3__AG EQU CYREG_PRT2_AG\r
+SCSI_In_DBx__DB3__AMUX EQU CYREG_PRT2_AMUX\r
+SCSI_In_DBx__DB3__BIE EQU CYREG_PRT2_BIE\r
+SCSI_In_DBx__DB3__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
+SCSI_In_DBx__DB3__BYP EQU CYREG_PRT2_BYP\r
+SCSI_In_DBx__DB3__CTL EQU CYREG_PRT2_CTL\r
+SCSI_In_DBx__DB3__DM0 EQU CYREG_PRT2_DM0\r
+SCSI_In_DBx__DB3__DM1 EQU CYREG_PRT2_DM1\r
+SCSI_In_DBx__DB3__DM2 EQU CYREG_PRT2_DM2\r
+SCSI_In_DBx__DB3__DR EQU CYREG_PRT2_DR\r
+SCSI_In_DBx__DB3__INP_DIS EQU CYREG_PRT2_INP_DIS\r
+SCSI_In_DBx__DB3__INTTYPE EQU CYREG_PICU2_INTTYPE5\r
+SCSI_In_DBx__DB3__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
+SCSI_In_DBx__DB3__LCD_EN EQU CYREG_PRT2_LCD_EN\r
+SCSI_In_DBx__DB3__MASK EQU 0x20\r
+SCSI_In_DBx__DB3__PC EQU CYREG_PRT2_PC5\r
+SCSI_In_DBx__DB3__PORT EQU 2\r
+SCSI_In_DBx__DB3__PRT EQU CYREG_PRT2_PRT\r
+SCSI_In_DBx__DB3__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
+SCSI_In_DBx__DB3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
+SCSI_In_DBx__DB3__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
+SCSI_In_DBx__DB3__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
+SCSI_In_DBx__DB3__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
+SCSI_In_DBx__DB3__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
+SCSI_In_DBx__DB3__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
+SCSI_In_DBx__DB3__PS EQU CYREG_PRT2_PS\r
+SCSI_In_DBx__DB3__SHIFT EQU 5\r
+SCSI_In_DBx__DB3__SLW EQU CYREG_PRT2_SLW\r
+SCSI_In_DBx__DB4__AG EQU CYREG_PRT2_AG\r
+SCSI_In_DBx__DB4__AMUX EQU CYREG_PRT2_AMUX\r
+SCSI_In_DBx__DB4__BIE EQU CYREG_PRT2_BIE\r
+SCSI_In_DBx__DB4__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
+SCSI_In_DBx__DB4__BYP EQU CYREG_PRT2_BYP\r
+SCSI_In_DBx__DB4__CTL EQU CYREG_PRT2_CTL\r
+SCSI_In_DBx__DB4__DM0 EQU CYREG_PRT2_DM0\r
+SCSI_In_DBx__DB4__DM1 EQU CYREG_PRT2_DM1\r
+SCSI_In_DBx__DB4__DM2 EQU CYREG_PRT2_DM2\r
+SCSI_In_DBx__DB4__DR EQU CYREG_PRT2_DR\r
+SCSI_In_DBx__DB4__INP_DIS EQU CYREG_PRT2_INP_DIS\r
+SCSI_In_DBx__DB4__INTTYPE EQU CYREG_PICU2_INTTYPE4\r
+SCSI_In_DBx__DB4__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
+SCSI_In_DBx__DB4__LCD_EN EQU CYREG_PRT2_LCD_EN\r
+SCSI_In_DBx__DB4__MASK EQU 0x10\r
+SCSI_In_DBx__DB4__PC EQU CYREG_PRT2_PC4\r
+SCSI_In_DBx__DB4__PORT EQU 2\r
+SCSI_In_DBx__DB4__PRT EQU CYREG_PRT2_PRT\r
+SCSI_In_DBx__DB4__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
+SCSI_In_DBx__DB4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
+SCSI_In_DBx__DB4__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
+SCSI_In_DBx__DB4__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
+SCSI_In_DBx__DB4__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
+SCSI_In_DBx__DB4__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
+SCSI_In_DBx__DB4__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
+SCSI_In_DBx__DB4__PS EQU CYREG_PRT2_PS\r
+SCSI_In_DBx__DB4__SHIFT EQU 4\r
+SCSI_In_DBx__DB4__SLW EQU CYREG_PRT2_SLW\r
+SCSI_In_DBx__DB5__AG EQU CYREG_PRT2_AG\r
+SCSI_In_DBx__DB5__AMUX EQU CYREG_PRT2_AMUX\r
+SCSI_In_DBx__DB5__BIE EQU CYREG_PRT2_BIE\r
+SCSI_In_DBx__DB5__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
+SCSI_In_DBx__DB5__BYP EQU CYREG_PRT2_BYP\r
+SCSI_In_DBx__DB5__CTL EQU CYREG_PRT2_CTL\r
+SCSI_In_DBx__DB5__DM0 EQU CYREG_PRT2_DM0\r
+SCSI_In_DBx__DB5__DM1 EQU CYREG_PRT2_DM1\r
+SCSI_In_DBx__DB5__DM2 EQU CYREG_PRT2_DM2\r
+SCSI_In_DBx__DB5__DR EQU CYREG_PRT2_DR\r
+SCSI_In_DBx__DB5__INP_DIS EQU CYREG_PRT2_INP_DIS\r
+SCSI_In_DBx__DB5__INTTYPE EQU CYREG_PICU2_INTTYPE3\r
+SCSI_In_DBx__DB5__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
+SCSI_In_DBx__DB5__LCD_EN EQU CYREG_PRT2_LCD_EN\r
+SCSI_In_DBx__DB5__MASK EQU 0x08\r
+SCSI_In_DBx__DB5__PC EQU CYREG_PRT2_PC3\r
+SCSI_In_DBx__DB5__PORT EQU 2\r
+SCSI_In_DBx__DB5__PRT EQU CYREG_PRT2_PRT\r
+SCSI_In_DBx__DB5__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
+SCSI_In_DBx__DB5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
+SCSI_In_DBx__DB5__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
+SCSI_In_DBx__DB5__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
+SCSI_In_DBx__DB5__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
+SCSI_In_DBx__DB5__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
+SCSI_In_DBx__DB5__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
+SCSI_In_DBx__DB5__PS EQU CYREG_PRT2_PS\r
+SCSI_In_DBx__DB5__SHIFT EQU 3\r
+SCSI_In_DBx__DB5__SLW EQU CYREG_PRT2_SLW\r
+SCSI_In_DBx__DB6__AG EQU CYREG_PRT2_AG\r
+SCSI_In_DBx__DB6__AMUX EQU CYREG_PRT2_AMUX\r
+SCSI_In_DBx__DB6__BIE EQU CYREG_PRT2_BIE\r
+SCSI_In_DBx__DB6__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
+SCSI_In_DBx__DB6__BYP EQU CYREG_PRT2_BYP\r
+SCSI_In_DBx__DB6__CTL EQU CYREG_PRT2_CTL\r
+SCSI_In_DBx__DB6__DM0 EQU CYREG_PRT2_DM0\r
+SCSI_In_DBx__DB6__DM1 EQU CYREG_PRT2_DM1\r
+SCSI_In_DBx__DB6__DM2 EQU CYREG_PRT2_DM2\r
+SCSI_In_DBx__DB6__DR EQU CYREG_PRT2_DR\r
+SCSI_In_DBx__DB6__INP_DIS EQU CYREG_PRT2_INP_DIS\r
+SCSI_In_DBx__DB6__INTTYPE EQU CYREG_PICU2_INTTYPE2\r
+SCSI_In_DBx__DB6__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
+SCSI_In_DBx__DB6__LCD_EN EQU CYREG_PRT2_LCD_EN\r
+SCSI_In_DBx__DB6__MASK EQU 0x04\r
+SCSI_In_DBx__DB6__PC EQU CYREG_PRT2_PC2\r
+SCSI_In_DBx__DB6__PORT EQU 2\r
+SCSI_In_DBx__DB6__PRT EQU CYREG_PRT2_PRT\r
+SCSI_In_DBx__DB6__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
+SCSI_In_DBx__DB6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
+SCSI_In_DBx__DB6__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
+SCSI_In_DBx__DB6__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
+SCSI_In_DBx__DB6__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
+SCSI_In_DBx__DB6__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
+SCSI_In_DBx__DB6__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
+SCSI_In_DBx__DB6__PS EQU CYREG_PRT2_PS\r
+SCSI_In_DBx__DB6__SHIFT EQU 2\r
+SCSI_In_DBx__DB6__SLW EQU CYREG_PRT2_SLW\r
+SCSI_In_DBx__DB7__AG EQU CYREG_PRT2_AG\r
+SCSI_In_DBx__DB7__AMUX EQU CYREG_PRT2_AMUX\r
+SCSI_In_DBx__DB7__BIE EQU CYREG_PRT2_BIE\r
+SCSI_In_DBx__DB7__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
+SCSI_In_DBx__DB7__BYP EQU CYREG_PRT2_BYP\r
+SCSI_In_DBx__DB7__CTL EQU CYREG_PRT2_CTL\r
+SCSI_In_DBx__DB7__DM0 EQU CYREG_PRT2_DM0\r
+SCSI_In_DBx__DB7__DM1 EQU CYREG_PRT2_DM1\r
+SCSI_In_DBx__DB7__DM2 EQU CYREG_PRT2_DM2\r
+SCSI_In_DBx__DB7__DR EQU CYREG_PRT2_DR\r
+SCSI_In_DBx__DB7__INP_DIS EQU CYREG_PRT2_INP_DIS\r
+SCSI_In_DBx__DB7__INTTYPE EQU CYREG_PICU2_INTTYPE1\r
+SCSI_In_DBx__DB7__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
+SCSI_In_DBx__DB7__LCD_EN EQU CYREG_PRT2_LCD_EN\r
+SCSI_In_DBx__DB7__MASK EQU 0x02\r
+SCSI_In_DBx__DB7__PC EQU CYREG_PRT2_PC1\r
+SCSI_In_DBx__DB7__PORT EQU 2\r
+SCSI_In_DBx__DB7__PRT EQU CYREG_PRT2_PRT\r
+SCSI_In_DBx__DB7__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
+SCSI_In_DBx__DB7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
+SCSI_In_DBx__DB7__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
+SCSI_In_DBx__DB7__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
+SCSI_In_DBx__DB7__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
+SCSI_In_DBx__DB7__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
+SCSI_In_DBx__DB7__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
+SCSI_In_DBx__DB7__PS EQU CYREG_PRT2_PS\r
+SCSI_In_DBx__DB7__SHIFT EQU 1\r
+SCSI_In_DBx__DB7__SLW EQU CYREG_PRT2_SLW\r
+\r
+; SD_DAT1\r
+SD_DAT1__0__INTTYPE EQU CYREG_PICU3_INTTYPE0\r
+SD_DAT1__0__MASK EQU 0x01\r
+SD_DAT1__0__PC EQU CYREG_PRT3_PC0\r
+SD_DAT1__0__PORT EQU 3\r
+SD_DAT1__0__SHIFT EQU 0\r
+SD_DAT1__AG EQU CYREG_PRT3_AG\r
+SD_DAT1__AMUX EQU CYREG_PRT3_AMUX\r
+SD_DAT1__BIE EQU CYREG_PRT3_BIE\r
+SD_DAT1__BIT_MASK EQU CYREG_PRT3_BIT_MASK\r
+SD_DAT1__BYP EQU CYREG_PRT3_BYP\r
+SD_DAT1__CTL EQU CYREG_PRT3_CTL\r
+SD_DAT1__DM0 EQU CYREG_PRT3_DM0\r
+SD_DAT1__DM1 EQU CYREG_PRT3_DM1\r
+SD_DAT1__DM2 EQU CYREG_PRT3_DM2\r
+SD_DAT1__DR EQU CYREG_PRT3_DR\r
+SD_DAT1__INP_DIS EQU CYREG_PRT3_INP_DIS\r
+SD_DAT1__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE\r
+SD_DAT1__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG\r
+SD_DAT1__LCD_EN EQU CYREG_PRT3_LCD_EN\r
+SD_DAT1__MASK EQU 0x01\r
+SD_DAT1__PORT EQU 3\r
+SD_DAT1__PRT EQU CYREG_PRT3_PRT\r
+SD_DAT1__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL\r
+SD_DAT1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN\r
+SD_DAT1__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0\r
+SD_DAT1__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1\r
+SD_DAT1__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0\r
+SD_DAT1__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1\r
+SD_DAT1__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT\r
+SD_DAT1__PS EQU CYREG_PRT3_PS\r
+SD_DAT1__SHIFT EQU 0\r
+SD_DAT1__SLW EQU CYREG_PRT3_SLW\r
+\r
+; SD_DAT2\r
+SD_DAT2__0__INTTYPE EQU CYREG_PICU3_INTTYPE5\r
+SD_DAT2__0__MASK EQU 0x20\r
+SD_DAT2__0__PC EQU CYREG_PRT3_PC5\r
+SD_DAT2__0__PORT EQU 3\r
+SD_DAT2__0__SHIFT EQU 5\r
+SD_DAT2__AG EQU CYREG_PRT3_AG\r
+SD_DAT2__AMUX EQU CYREG_PRT3_AMUX\r
+SD_DAT2__BIE EQU CYREG_PRT3_BIE\r
+SD_DAT2__BIT_MASK EQU CYREG_PRT3_BIT_MASK\r
+SD_DAT2__BYP EQU CYREG_PRT3_BYP\r
+SD_DAT2__CTL EQU CYREG_PRT3_CTL\r
+SD_DAT2__DM0 EQU CYREG_PRT3_DM0\r
+SD_DAT2__DM1 EQU CYREG_PRT3_DM1\r
+SD_DAT2__DM2 EQU CYREG_PRT3_DM2\r
+SD_DAT2__DR EQU CYREG_PRT3_DR\r
+SD_DAT2__INP_DIS EQU CYREG_PRT3_INP_DIS\r
+SD_DAT2__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE\r
+SD_DAT2__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG\r
+SD_DAT2__LCD_EN EQU CYREG_PRT3_LCD_EN\r
+SD_DAT2__MASK EQU 0x20\r
+SD_DAT2__PORT EQU 3\r
+SD_DAT2__PRT EQU CYREG_PRT3_PRT\r
+SD_DAT2__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL\r
+SD_DAT2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN\r
+SD_DAT2__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0\r
+SD_DAT2__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1\r
+SD_DAT2__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0\r
+SD_DAT2__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1\r
+SD_DAT2__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT\r
+SD_DAT2__PS EQU CYREG_PRT3_PS\r
+SD_DAT2__SHIFT EQU 5\r
+SD_DAT2__SLW EQU CYREG_PRT3_SLW\r
+\r
+; SD_MISO\r
+SD_MISO__0__INTTYPE EQU CYREG_PICU3_INTTYPE1\r
+SD_MISO__0__MASK EQU 0x02\r
+SD_MISO__0__PC EQU CYREG_PRT3_PC1\r
+SD_MISO__0__PORT EQU 3\r
+SD_MISO__0__SHIFT EQU 1\r
+SD_MISO__AG EQU CYREG_PRT3_AG\r
+SD_MISO__AMUX EQU CYREG_PRT3_AMUX\r
+SD_MISO__BIE EQU CYREG_PRT3_BIE\r
+SD_MISO__BIT_MASK EQU CYREG_PRT3_BIT_MASK\r
+SD_MISO__BYP EQU CYREG_PRT3_BYP\r
+SD_MISO__CTL EQU CYREG_PRT3_CTL\r
+SD_MISO__DM0 EQU CYREG_PRT3_DM0\r
+SD_MISO__DM1 EQU CYREG_PRT3_DM1\r
+SD_MISO__DM2 EQU CYREG_PRT3_DM2\r
+SD_MISO__DR EQU CYREG_PRT3_DR\r
+SD_MISO__INP_DIS EQU CYREG_PRT3_INP_DIS\r
+SD_MISO__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE\r
+SD_MISO__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG\r
+SD_MISO__LCD_EN EQU CYREG_PRT3_LCD_EN\r
+SD_MISO__MASK EQU 0x02\r
+SD_MISO__PORT EQU 3\r
+SD_MISO__PRT EQU CYREG_PRT3_PRT\r
+SD_MISO__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL\r
+SD_MISO__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN\r
+SD_MISO__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0\r
+SD_MISO__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1\r
+SD_MISO__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0\r
+SD_MISO__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1\r
+SD_MISO__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT\r
+SD_MISO__PS EQU CYREG_PRT3_PS\r
+SD_MISO__SHIFT EQU 1\r
+SD_MISO__SLW EQU CYREG_PRT3_SLW\r
+\r
+; SD_MOSI\r
+SD_MOSI__0__INTTYPE EQU CYREG_PICU3_INTTYPE3\r
+SD_MOSI__0__MASK EQU 0x08\r
+SD_MOSI__0__PC EQU CYREG_PRT3_PC3\r
+SD_MOSI__0__PORT EQU 3\r
+SD_MOSI__0__SHIFT EQU 3\r
+SD_MOSI__AG EQU CYREG_PRT3_AG\r
+SD_MOSI__AMUX EQU CYREG_PRT3_AMUX\r
+SD_MOSI__BIE EQU CYREG_PRT3_BIE\r
+SD_MOSI__BIT_MASK EQU CYREG_PRT3_BIT_MASK\r
+SD_MOSI__BYP EQU CYREG_PRT3_BYP\r
+SD_MOSI__CTL EQU CYREG_PRT3_CTL\r
+SD_MOSI__DM0 EQU CYREG_PRT3_DM0\r
+SD_MOSI__DM1 EQU CYREG_PRT3_DM1\r
+SD_MOSI__DM2 EQU CYREG_PRT3_DM2\r
+SD_MOSI__DR EQU CYREG_PRT3_DR\r
+SD_MOSI__INP_DIS EQU CYREG_PRT3_INP_DIS\r
+SD_MOSI__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE\r
+SD_MOSI__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG\r
+SD_MOSI__LCD_EN EQU CYREG_PRT3_LCD_EN\r
+SD_MOSI__MASK EQU 0x08\r
+SD_MOSI__PORT EQU 3\r
+SD_MOSI__PRT EQU CYREG_PRT3_PRT\r
+SD_MOSI__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL\r
+SD_MOSI__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN\r
+SD_MOSI__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0\r
+SD_MOSI__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1\r
+SD_MOSI__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0\r
+SD_MOSI__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1\r
+SD_MOSI__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT\r
+SD_MOSI__PS EQU CYREG_PRT3_PS\r
+SD_MOSI__SHIFT EQU 3\r
+SD_MOSI__SLW EQU CYREG_PRT3_SLW\r
+\r
+; SCSI_CLK\r
+SCSI_CLK__CFG0 EQU CYREG_CLKDIST_DCFG1_CFG0\r
+SCSI_CLK__CFG1 EQU CYREG_CLKDIST_DCFG1_CFG1\r
+SCSI_CLK__CFG2 EQU CYREG_CLKDIST_DCFG1_CFG2\r
+SCSI_CLK__CFG2_SRC_SEL_MASK EQU 0x07\r
+SCSI_CLK__INDEX EQU 0x01\r
+SCSI_CLK__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2\r
+SCSI_CLK__PM_ACT_MSK EQU 0x02\r
+SCSI_CLK__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2\r
+SCSI_CLK__PM_STBY_MSK EQU 0x02\r
+\r
+; SCSI_Out\r
+SCSI_Out__0__AG EQU CYREG_PRT4_AG\r
+SCSI_Out__0__AMUX EQU CYREG_PRT4_AMUX\r
+SCSI_Out__0__BIE EQU CYREG_PRT4_BIE\r
+SCSI_Out__0__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
+SCSI_Out__0__BYP EQU CYREG_PRT4_BYP\r
+SCSI_Out__0__CTL EQU CYREG_PRT4_CTL\r
+SCSI_Out__0__DM0 EQU CYREG_PRT4_DM0\r
+SCSI_Out__0__DM1 EQU CYREG_PRT4_DM1\r
+SCSI_Out__0__DM2 EQU CYREG_PRT4_DM2\r
+SCSI_Out__0__DR EQU CYREG_PRT4_DR\r
+SCSI_Out__0__INP_DIS EQU CYREG_PRT4_INP_DIS\r
+SCSI_Out__0__INTTYPE EQU CYREG_PICU4_INTTYPE3\r
+SCSI_Out__0__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
+SCSI_Out__0__LCD_EN EQU CYREG_PRT4_LCD_EN\r
+SCSI_Out__0__MASK EQU 0x08\r
+SCSI_Out__0__PC EQU CYREG_PRT4_PC3\r
+SCSI_Out__0__PORT EQU 4\r
+SCSI_Out__0__PRT EQU CYREG_PRT4_PRT\r
+SCSI_Out__0__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
+SCSI_Out__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
+SCSI_Out__0__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
+SCSI_Out__0__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
+SCSI_Out__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
+SCSI_Out__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
+SCSI_Out__0__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
+SCSI_Out__0__PS EQU CYREG_PRT4_PS\r
+SCSI_Out__0__SHIFT EQU 3\r
+SCSI_Out__0__SLW EQU CYREG_PRT4_SLW\r
+SCSI_Out__1__AG EQU CYREG_PRT4_AG\r
+SCSI_Out__1__AMUX EQU CYREG_PRT4_AMUX\r
+SCSI_Out__1__BIE EQU CYREG_PRT4_BIE\r
+SCSI_Out__1__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
+SCSI_Out__1__BYP EQU CYREG_PRT4_BYP\r
+SCSI_Out__1__CTL EQU CYREG_PRT4_CTL\r
+SCSI_Out__1__DM0 EQU CYREG_PRT4_DM0\r
+SCSI_Out__1__DM1 EQU CYREG_PRT4_DM1\r
+SCSI_Out__1__DM2 EQU CYREG_PRT4_DM2\r
+SCSI_Out__1__DR EQU CYREG_PRT4_DR\r
+SCSI_Out__1__INP_DIS EQU CYREG_PRT4_INP_DIS\r
+SCSI_Out__1__INTTYPE EQU CYREG_PICU4_INTTYPE2\r
+SCSI_Out__1__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
+SCSI_Out__1__LCD_EN EQU CYREG_PRT4_LCD_EN\r
+SCSI_Out__1__MASK EQU 0x04\r
+SCSI_Out__1__PC EQU CYREG_PRT4_PC2\r
+SCSI_Out__1__PORT EQU 4\r
+SCSI_Out__1__PRT EQU CYREG_PRT4_PRT\r
+SCSI_Out__1__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
+SCSI_Out__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
+SCSI_Out__1__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
+SCSI_Out__1__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
+SCSI_Out__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
+SCSI_Out__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
+SCSI_Out__1__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
+SCSI_Out__1__PS EQU CYREG_PRT4_PS\r
+SCSI_Out__1__SHIFT EQU 2\r
+SCSI_Out__1__SLW EQU CYREG_PRT4_SLW\r
+SCSI_Out__2__AG EQU CYREG_PRT0_AG\r
+SCSI_Out__2__AMUX EQU CYREG_PRT0_AMUX\r
+SCSI_Out__2__BIE EQU CYREG_PRT0_BIE\r
+SCSI_Out__2__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
+SCSI_Out__2__BYP EQU CYREG_PRT0_BYP\r
+SCSI_Out__2__CTL EQU CYREG_PRT0_CTL\r
+SCSI_Out__2__DM0 EQU CYREG_PRT0_DM0\r
+SCSI_Out__2__DM1 EQU CYREG_PRT0_DM1\r
+SCSI_Out__2__DM2 EQU CYREG_PRT0_DM2\r
+SCSI_Out__2__DR EQU CYREG_PRT0_DR\r
+SCSI_Out__2__INP_DIS EQU CYREG_PRT0_INP_DIS\r
+SCSI_Out__2__INTTYPE EQU CYREG_PICU0_INTTYPE7\r
+SCSI_Out__2__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
+SCSI_Out__2__LCD_EN EQU CYREG_PRT0_LCD_EN\r
+SCSI_Out__2__MASK EQU 0x80\r
+SCSI_Out__2__PC EQU CYREG_PRT0_PC7\r
+SCSI_Out__2__PORT EQU 0\r
+SCSI_Out__2__PRT EQU CYREG_PRT0_PRT\r
+SCSI_Out__2__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
+SCSI_Out__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
+SCSI_Out__2__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
+SCSI_Out__2__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
+SCSI_Out__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
+SCSI_Out__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
+SCSI_Out__2__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
+SCSI_Out__2__PS EQU CYREG_PRT0_PS\r
+SCSI_Out__2__SHIFT EQU 7\r
+SCSI_Out__2__SLW EQU CYREG_PRT0_SLW\r
+SCSI_Out__3__AG EQU CYREG_PRT0_AG\r
+SCSI_Out__3__AMUX EQU CYREG_PRT0_AMUX\r
+SCSI_Out__3__BIE EQU CYREG_PRT0_BIE\r
+SCSI_Out__3__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
+SCSI_Out__3__BYP EQU CYREG_PRT0_BYP\r
+SCSI_Out__3__CTL EQU CYREG_PRT0_CTL\r
+SCSI_Out__3__DM0 EQU CYREG_PRT0_DM0\r
+SCSI_Out__3__DM1 EQU CYREG_PRT0_DM1\r
+SCSI_Out__3__DM2 EQU CYREG_PRT0_DM2\r
+SCSI_Out__3__DR EQU CYREG_PRT0_DR\r
+SCSI_Out__3__INP_DIS EQU CYREG_PRT0_INP_DIS\r
+SCSI_Out__3__INTTYPE EQU CYREG_PICU0_INTTYPE6\r
+SCSI_Out__3__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
+SCSI_Out__3__LCD_EN EQU CYREG_PRT0_LCD_EN\r
+SCSI_Out__3__MASK EQU 0x40\r
+SCSI_Out__3__PC EQU CYREG_PRT0_PC6\r
+SCSI_Out__3__PORT EQU 0\r
+SCSI_Out__3__PRT EQU CYREG_PRT0_PRT\r
+SCSI_Out__3__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
+SCSI_Out__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
+SCSI_Out__3__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
+SCSI_Out__3__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
+SCSI_Out__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
+SCSI_Out__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
+SCSI_Out__3__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
+SCSI_Out__3__PS EQU CYREG_PRT0_PS\r
+SCSI_Out__3__SHIFT EQU 6\r
+SCSI_Out__3__SLW EQU CYREG_PRT0_SLW\r
+SCSI_Out__4__AG EQU CYREG_PRT0_AG\r
+SCSI_Out__4__AMUX EQU CYREG_PRT0_AMUX\r
+SCSI_Out__4__BIE EQU CYREG_PRT0_BIE\r
+SCSI_Out__4__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
+SCSI_Out__4__BYP EQU CYREG_PRT0_BYP\r
+SCSI_Out__4__CTL EQU CYREG_PRT0_CTL\r
+SCSI_Out__4__DM0 EQU CYREG_PRT0_DM0\r
+SCSI_Out__4__DM1 EQU CYREG_PRT0_DM1\r
+SCSI_Out__4__DM2 EQU CYREG_PRT0_DM2\r
+SCSI_Out__4__DR EQU CYREG_PRT0_DR\r
+SCSI_Out__4__INP_DIS EQU CYREG_PRT0_INP_DIS\r
+SCSI_Out__4__INTTYPE EQU CYREG_PICU0_INTTYPE5\r
+SCSI_Out__4__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
+SCSI_Out__4__LCD_EN EQU CYREG_PRT0_LCD_EN\r
+SCSI_Out__4__MASK EQU 0x20\r
+SCSI_Out__4__PC EQU CYREG_PRT0_PC5\r
+SCSI_Out__4__PORT EQU 0\r
+SCSI_Out__4__PRT EQU CYREG_PRT0_PRT\r
+SCSI_Out__4__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
+SCSI_Out__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
+SCSI_Out__4__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
+SCSI_Out__4__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
+SCSI_Out__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
+SCSI_Out__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
+SCSI_Out__4__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
+SCSI_Out__4__PS EQU CYREG_PRT0_PS\r
+SCSI_Out__4__SHIFT EQU 5\r
+SCSI_Out__4__SLW EQU CYREG_PRT0_SLW\r
+SCSI_Out__5__AG EQU CYREG_PRT0_AG\r
+SCSI_Out__5__AMUX EQU CYREG_PRT0_AMUX\r
+SCSI_Out__5__BIE EQU CYREG_PRT0_BIE\r
+SCSI_Out__5__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
+SCSI_Out__5__BYP EQU CYREG_PRT0_BYP\r
+SCSI_Out__5__CTL EQU CYREG_PRT0_CTL\r
+SCSI_Out__5__DM0 EQU CYREG_PRT0_DM0\r
+SCSI_Out__5__DM1 EQU CYREG_PRT0_DM1\r
+SCSI_Out__5__DM2 EQU CYREG_PRT0_DM2\r
+SCSI_Out__5__DR EQU CYREG_PRT0_DR\r
+SCSI_Out__5__INP_DIS EQU CYREG_PRT0_INP_DIS\r
+SCSI_Out__5__INTTYPE EQU CYREG_PICU0_INTTYPE4\r
+SCSI_Out__5__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
+SCSI_Out__5__LCD_EN EQU CYREG_PRT0_LCD_EN\r
+SCSI_Out__5__MASK EQU 0x10\r
+SCSI_Out__5__PC EQU CYREG_PRT0_PC4\r
+SCSI_Out__5__PORT EQU 0\r
+SCSI_Out__5__PRT EQU CYREG_PRT0_PRT\r
+SCSI_Out__5__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
+SCSI_Out__5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
+SCSI_Out__5__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
+SCSI_Out__5__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
+SCSI_Out__5__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
+SCSI_Out__5__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
+SCSI_Out__5__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
+SCSI_Out__5__PS EQU CYREG_PRT0_PS\r
+SCSI_Out__5__SHIFT EQU 4\r
+SCSI_Out__5__SLW EQU CYREG_PRT0_SLW\r
+SCSI_Out__6__AG EQU CYREG_PRT0_AG\r
+SCSI_Out__6__AMUX EQU CYREG_PRT0_AMUX\r
+SCSI_Out__6__BIE EQU CYREG_PRT0_BIE\r
+SCSI_Out__6__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
+SCSI_Out__6__BYP EQU CYREG_PRT0_BYP\r
+SCSI_Out__6__CTL EQU CYREG_PRT0_CTL\r
+SCSI_Out__6__DM0 EQU CYREG_PRT0_DM0\r
+SCSI_Out__6__DM1 EQU CYREG_PRT0_DM1\r
+SCSI_Out__6__DM2 EQU CYREG_PRT0_DM2\r
+SCSI_Out__6__DR EQU CYREG_PRT0_DR\r
+SCSI_Out__6__INP_DIS EQU CYREG_PRT0_INP_DIS\r
+SCSI_Out__6__INTTYPE EQU CYREG_PICU0_INTTYPE3\r
+SCSI_Out__6__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
+SCSI_Out__6__LCD_EN EQU CYREG_PRT0_LCD_EN\r
+SCSI_Out__6__MASK EQU 0x08\r
+SCSI_Out__6__PC EQU CYREG_PRT0_PC3\r
+SCSI_Out__6__PORT EQU 0\r
+SCSI_Out__6__PRT EQU CYREG_PRT0_PRT\r
+SCSI_Out__6__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
+SCSI_Out__6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
+SCSI_Out__6__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
+SCSI_Out__6__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
+SCSI_Out__6__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
+SCSI_Out__6__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
+SCSI_Out__6__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
+SCSI_Out__6__PS EQU CYREG_PRT0_PS\r
+SCSI_Out__6__SHIFT EQU 3\r
+SCSI_Out__6__SLW EQU CYREG_PRT0_SLW\r
+SCSI_Out__7__AG EQU CYREG_PRT0_AG\r
+SCSI_Out__7__AMUX EQU CYREG_PRT0_AMUX\r
+SCSI_Out__7__BIE EQU CYREG_PRT0_BIE\r
+SCSI_Out__7__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
+SCSI_Out__7__BYP EQU CYREG_PRT0_BYP\r
+SCSI_Out__7__CTL EQU CYREG_PRT0_CTL\r
+SCSI_Out__7__DM0 EQU CYREG_PRT0_DM0\r
+SCSI_Out__7__DM1 EQU CYREG_PRT0_DM1\r
+SCSI_Out__7__DM2 EQU CYREG_PRT0_DM2\r
+SCSI_Out__7__DR EQU CYREG_PRT0_DR\r
+SCSI_Out__7__INP_DIS EQU CYREG_PRT0_INP_DIS\r
+SCSI_Out__7__INTTYPE EQU CYREG_PICU0_INTTYPE2\r
+SCSI_Out__7__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
+SCSI_Out__7__LCD_EN EQU CYREG_PRT0_LCD_EN\r
+SCSI_Out__7__MASK EQU 0x04\r
+SCSI_Out__7__PC EQU CYREG_PRT0_PC2\r
+SCSI_Out__7__PORT EQU 0\r
+SCSI_Out__7__PRT EQU CYREG_PRT0_PRT\r
+SCSI_Out__7__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
+SCSI_Out__7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
+SCSI_Out__7__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
+SCSI_Out__7__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
+SCSI_Out__7__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
+SCSI_Out__7__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
+SCSI_Out__7__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
+SCSI_Out__7__PS EQU CYREG_PRT0_PS\r
+SCSI_Out__7__SHIFT EQU 2\r
+SCSI_Out__7__SLW EQU CYREG_PRT0_SLW\r
+SCSI_Out__8__AG EQU CYREG_PRT0_AG\r
+SCSI_Out__8__AMUX EQU CYREG_PRT0_AMUX\r
+SCSI_Out__8__BIE EQU CYREG_PRT0_BIE\r
+SCSI_Out__8__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
+SCSI_Out__8__BYP EQU CYREG_PRT0_BYP\r
+SCSI_Out__8__CTL EQU CYREG_PRT0_CTL\r
+SCSI_Out__8__DM0 EQU CYREG_PRT0_DM0\r
+SCSI_Out__8__DM1 EQU CYREG_PRT0_DM1\r
+SCSI_Out__8__DM2 EQU CYREG_PRT0_DM2\r
+SCSI_Out__8__DR EQU CYREG_PRT0_DR\r
+SCSI_Out__8__INP_DIS EQU CYREG_PRT0_INP_DIS\r
+SCSI_Out__8__INTTYPE EQU CYREG_PICU0_INTTYPE1\r
+SCSI_Out__8__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
+SCSI_Out__8__LCD_EN EQU CYREG_PRT0_LCD_EN\r
+SCSI_Out__8__MASK EQU 0x02\r
+SCSI_Out__8__PC EQU CYREG_PRT0_PC1\r
+SCSI_Out__8__PORT EQU 0\r
+SCSI_Out__8__PRT EQU CYREG_PRT0_PRT\r
+SCSI_Out__8__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
+SCSI_Out__8__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
+SCSI_Out__8__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
+SCSI_Out__8__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
+SCSI_Out__8__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
+SCSI_Out__8__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
+SCSI_Out__8__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
+SCSI_Out__8__PS EQU CYREG_PRT0_PS\r
+SCSI_Out__8__SHIFT EQU 1\r
+SCSI_Out__8__SLW EQU CYREG_PRT0_SLW\r
+SCSI_Out__9__AG EQU CYREG_PRT0_AG\r
+SCSI_Out__9__AMUX EQU CYREG_PRT0_AMUX\r
+SCSI_Out__9__BIE EQU CYREG_PRT0_BIE\r
+SCSI_Out__9__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
+SCSI_Out__9__BYP EQU CYREG_PRT0_BYP\r
+SCSI_Out__9__CTL EQU CYREG_PRT0_CTL\r
+SCSI_Out__9__DM0 EQU CYREG_PRT0_DM0\r
+SCSI_Out__9__DM1 EQU CYREG_PRT0_DM1\r
+SCSI_Out__9__DM2 EQU CYREG_PRT0_DM2\r
+SCSI_Out__9__DR EQU CYREG_PRT0_DR\r
+SCSI_Out__9__INP_DIS EQU CYREG_PRT0_INP_DIS\r
+SCSI_Out__9__INTTYPE EQU CYREG_PICU0_INTTYPE0\r
+SCSI_Out__9__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
+SCSI_Out__9__LCD_EN EQU CYREG_PRT0_LCD_EN\r
+SCSI_Out__9__MASK EQU 0x01\r
+SCSI_Out__9__PC EQU CYREG_PRT0_PC0\r
+SCSI_Out__9__PORT EQU 0\r
+SCSI_Out__9__PRT EQU CYREG_PRT0_PRT\r
+SCSI_Out__9__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
+SCSI_Out__9__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
+SCSI_Out__9__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
+SCSI_Out__9__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
+SCSI_Out__9__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
+SCSI_Out__9__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
+SCSI_Out__9__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
+SCSI_Out__9__PS EQU CYREG_PRT0_PS\r
+SCSI_Out__9__SHIFT EQU 0\r
+SCSI_Out__9__SLW EQU CYREG_PRT0_SLW\r
+SCSI_Out__ACK__AG EQU CYREG_PRT0_AG\r
+SCSI_Out__ACK__AMUX EQU CYREG_PRT0_AMUX\r
+SCSI_Out__ACK__BIE EQU CYREG_PRT0_BIE\r
+SCSI_Out__ACK__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
+SCSI_Out__ACK__BYP EQU CYREG_PRT0_BYP\r
+SCSI_Out__ACK__CTL EQU CYREG_PRT0_CTL\r
+SCSI_Out__ACK__DM0 EQU CYREG_PRT0_DM0\r
+SCSI_Out__ACK__DM1 EQU CYREG_PRT0_DM1\r
+SCSI_Out__ACK__DM2 EQU CYREG_PRT0_DM2\r
+SCSI_Out__ACK__DR EQU CYREG_PRT0_DR\r
+SCSI_Out__ACK__INP_DIS EQU CYREG_PRT0_INP_DIS\r
+SCSI_Out__ACK__INTTYPE EQU CYREG_PICU0_INTTYPE6\r
+SCSI_Out__ACK__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
+SCSI_Out__ACK__LCD_EN EQU CYREG_PRT0_LCD_EN\r
+SCSI_Out__ACK__MASK EQU 0x40\r
+SCSI_Out__ACK__PC EQU CYREG_PRT0_PC6\r
+SCSI_Out__ACK__PORT EQU 0\r
+SCSI_Out__ACK__PRT EQU CYREG_PRT0_PRT\r
+SCSI_Out__ACK__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
+SCSI_Out__ACK__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
+SCSI_Out__ACK__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
+SCSI_Out__ACK__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
+SCSI_Out__ACK__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
+SCSI_Out__ACK__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
+SCSI_Out__ACK__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
+SCSI_Out__ACK__PS EQU CYREG_PRT0_PS\r
+SCSI_Out__ACK__SHIFT EQU 6\r
+SCSI_Out__ACK__SLW EQU CYREG_PRT0_SLW\r
+SCSI_Out__ATN__AG EQU CYREG_PRT4_AG\r
+SCSI_Out__ATN__AMUX EQU CYREG_PRT4_AMUX\r
+SCSI_Out__ATN__BIE EQU CYREG_PRT4_BIE\r
+SCSI_Out__ATN__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
+SCSI_Out__ATN__BYP EQU CYREG_PRT4_BYP\r
+SCSI_Out__ATN__CTL EQU CYREG_PRT4_CTL\r
+SCSI_Out__ATN__DM0 EQU CYREG_PRT4_DM0\r
+SCSI_Out__ATN__DM1 EQU CYREG_PRT4_DM1\r
+SCSI_Out__ATN__DM2 EQU CYREG_PRT4_DM2\r
+SCSI_Out__ATN__DR EQU CYREG_PRT4_DR\r
+SCSI_Out__ATN__INP_DIS EQU CYREG_PRT4_INP_DIS\r
+SCSI_Out__ATN__INTTYPE EQU CYREG_PICU4_INTTYPE2\r
+SCSI_Out__ATN__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
+SCSI_Out__ATN__LCD_EN EQU CYREG_PRT4_LCD_EN\r
+SCSI_Out__ATN__MASK EQU 0x04\r
+SCSI_Out__ATN__PC EQU CYREG_PRT4_PC2\r
+SCSI_Out__ATN__PORT EQU 4\r
+SCSI_Out__ATN__PRT EQU CYREG_PRT4_PRT\r
+SCSI_Out__ATN__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
+SCSI_Out__ATN__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
+SCSI_Out__ATN__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
+SCSI_Out__ATN__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
+SCSI_Out__ATN__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
+SCSI_Out__ATN__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
+SCSI_Out__ATN__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
+SCSI_Out__ATN__PS EQU CYREG_PRT4_PS\r
+SCSI_Out__ATN__SHIFT EQU 2\r
+SCSI_Out__ATN__SLW EQU CYREG_PRT4_SLW\r
+SCSI_Out__BSY__AG EQU CYREG_PRT0_AG\r
+SCSI_Out__BSY__AMUX EQU CYREG_PRT0_AMUX\r
+SCSI_Out__BSY__BIE EQU CYREG_PRT0_BIE\r
+SCSI_Out__BSY__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
+SCSI_Out__BSY__BYP EQU CYREG_PRT0_BYP\r
+SCSI_Out__BSY__CTL EQU CYREG_PRT0_CTL\r
+SCSI_Out__BSY__DM0 EQU CYREG_PRT0_DM0\r
+SCSI_Out__BSY__DM1 EQU CYREG_PRT0_DM1\r
+SCSI_Out__BSY__DM2 EQU CYREG_PRT0_DM2\r
+SCSI_Out__BSY__DR EQU CYREG_PRT0_DR\r
+SCSI_Out__BSY__INP_DIS EQU CYREG_PRT0_INP_DIS\r
+SCSI_Out__BSY__INTTYPE EQU CYREG_PICU0_INTTYPE7\r
+SCSI_Out__BSY__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
+SCSI_Out__BSY__LCD_EN EQU CYREG_PRT0_LCD_EN\r
+SCSI_Out__BSY__MASK EQU 0x80\r
+SCSI_Out__BSY__PC EQU CYREG_PRT0_PC7\r
+SCSI_Out__BSY__PORT EQU 0\r
+SCSI_Out__BSY__PRT EQU CYREG_PRT0_PRT\r
+SCSI_Out__BSY__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
+SCSI_Out__BSY__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
+SCSI_Out__BSY__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
+SCSI_Out__BSY__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
+SCSI_Out__BSY__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
+SCSI_Out__BSY__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
+SCSI_Out__BSY__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
+SCSI_Out__BSY__PS EQU CYREG_PRT0_PS\r
+SCSI_Out__BSY__SHIFT EQU 7\r
+SCSI_Out__BSY__SLW EQU CYREG_PRT0_SLW\r
+SCSI_Out__CD_raw__AG EQU CYREG_PRT0_AG\r
+SCSI_Out__CD_raw__AMUX EQU CYREG_PRT0_AMUX\r
+SCSI_Out__CD_raw__BIE EQU CYREG_PRT0_BIE\r
+SCSI_Out__CD_raw__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
+SCSI_Out__CD_raw__BYP EQU CYREG_PRT0_BYP\r
+SCSI_Out__CD_raw__CTL EQU CYREG_PRT0_CTL\r
+SCSI_Out__CD_raw__DM0 EQU CYREG_PRT0_DM0\r
+SCSI_Out__CD_raw__DM1 EQU CYREG_PRT0_DM1\r
+SCSI_Out__CD_raw__DM2 EQU CYREG_PRT0_DM2\r
+SCSI_Out__CD_raw__DR EQU CYREG_PRT0_DR\r
+SCSI_Out__CD_raw__INP_DIS EQU CYREG_PRT0_INP_DIS\r
+SCSI_Out__CD_raw__INTTYPE EQU CYREG_PICU0_INTTYPE2\r
+SCSI_Out__CD_raw__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
+SCSI_Out__CD_raw__LCD_EN EQU CYREG_PRT0_LCD_EN\r
+SCSI_Out__CD_raw__MASK EQU 0x04\r
+SCSI_Out__CD_raw__PC EQU CYREG_PRT0_PC2\r
+SCSI_Out__CD_raw__PORT EQU 0\r
+SCSI_Out__CD_raw__PRT EQU CYREG_PRT0_PRT\r
+SCSI_Out__CD_raw__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
+SCSI_Out__CD_raw__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
+SCSI_Out__CD_raw__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
+SCSI_Out__CD_raw__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
+SCSI_Out__CD_raw__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
+SCSI_Out__CD_raw__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
+SCSI_Out__CD_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
+SCSI_Out__CD_raw__PS EQU CYREG_PRT0_PS\r
+SCSI_Out__CD_raw__SHIFT EQU 2\r
+SCSI_Out__CD_raw__SLW EQU CYREG_PRT0_SLW\r
+SCSI_Out__DBP_raw__AG EQU CYREG_PRT4_AG\r
+SCSI_Out__DBP_raw__AMUX EQU CYREG_PRT4_AMUX\r
+SCSI_Out__DBP_raw__BIE EQU CYREG_PRT4_BIE\r
+SCSI_Out__DBP_raw__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
+SCSI_Out__DBP_raw__BYP EQU CYREG_PRT4_BYP\r
+SCSI_Out__DBP_raw__CTL EQU CYREG_PRT4_CTL\r
+SCSI_Out__DBP_raw__DM0 EQU CYREG_PRT4_DM0\r
+SCSI_Out__DBP_raw__DM1 EQU CYREG_PRT4_DM1\r
+SCSI_Out__DBP_raw__DM2 EQU CYREG_PRT4_DM2\r
+SCSI_Out__DBP_raw__DR EQU CYREG_PRT4_DR\r
+SCSI_Out__DBP_raw__INP_DIS EQU CYREG_PRT4_INP_DIS\r
+SCSI_Out__DBP_raw__INTTYPE EQU CYREG_PICU4_INTTYPE3\r
+SCSI_Out__DBP_raw__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
+SCSI_Out__DBP_raw__LCD_EN EQU CYREG_PRT4_LCD_EN\r
+SCSI_Out__DBP_raw__MASK EQU 0x08\r
+SCSI_Out__DBP_raw__PC EQU CYREG_PRT4_PC3\r
+SCSI_Out__DBP_raw__PORT EQU 4\r
+SCSI_Out__DBP_raw__PRT EQU CYREG_PRT4_PRT\r
+SCSI_Out__DBP_raw__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
+SCSI_Out__DBP_raw__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
+SCSI_Out__DBP_raw__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
+SCSI_Out__DBP_raw__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
+SCSI_Out__DBP_raw__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
+SCSI_Out__DBP_raw__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
+SCSI_Out__DBP_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
+SCSI_Out__DBP_raw__PS EQU CYREG_PRT4_PS\r
+SCSI_Out__DBP_raw__SHIFT EQU 3\r
+SCSI_Out__DBP_raw__SLW EQU CYREG_PRT4_SLW\r
+SCSI_Out__IO_raw__AG EQU CYREG_PRT0_AG\r
+SCSI_Out__IO_raw__AMUX EQU CYREG_PRT0_AMUX\r
+SCSI_Out__IO_raw__BIE EQU CYREG_PRT0_BIE\r
+SCSI_Out__IO_raw__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
+SCSI_Out__IO_raw__BYP EQU CYREG_PRT0_BYP\r
+SCSI_Out__IO_raw__CTL EQU CYREG_PRT0_CTL\r
+SCSI_Out__IO_raw__DM0 EQU CYREG_PRT0_DM0\r
+SCSI_Out__IO_raw__DM1 EQU CYREG_PRT0_DM1\r
+SCSI_Out__IO_raw__DM2 EQU CYREG_PRT0_DM2\r
+SCSI_Out__IO_raw__DR EQU CYREG_PRT0_DR\r
+SCSI_Out__IO_raw__INP_DIS EQU CYREG_PRT0_INP_DIS\r
+SCSI_Out__IO_raw__INTTYPE EQU CYREG_PICU0_INTTYPE0\r
+SCSI_Out__IO_raw__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
+SCSI_Out__IO_raw__LCD_EN EQU CYREG_PRT0_LCD_EN\r
+SCSI_Out__IO_raw__MASK EQU 0x01\r
+SCSI_Out__IO_raw__PC EQU CYREG_PRT0_PC0\r
+SCSI_Out__IO_raw__PORT EQU 0\r
+SCSI_Out__IO_raw__PRT EQU CYREG_PRT0_PRT\r
+SCSI_Out__IO_raw__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
+SCSI_Out__IO_raw__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
+SCSI_Out__IO_raw__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
+SCSI_Out__IO_raw__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
+SCSI_Out__IO_raw__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
+SCSI_Out__IO_raw__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
+SCSI_Out__IO_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
+SCSI_Out__IO_raw__PS EQU CYREG_PRT0_PS\r
+SCSI_Out__IO_raw__SHIFT EQU 0\r
+SCSI_Out__IO_raw__SLW EQU CYREG_PRT0_SLW\r
+SCSI_Out__MSG_raw__AG EQU CYREG_PRT0_AG\r
+SCSI_Out__MSG_raw__AMUX EQU CYREG_PRT0_AMUX\r
+SCSI_Out__MSG_raw__BIE EQU CYREG_PRT0_BIE\r
+SCSI_Out__MSG_raw__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
+SCSI_Out__MSG_raw__BYP EQU CYREG_PRT0_BYP\r
+SCSI_Out__MSG_raw__CTL EQU CYREG_PRT0_CTL\r
+SCSI_Out__MSG_raw__DM0 EQU CYREG_PRT0_DM0\r
+SCSI_Out__MSG_raw__DM1 EQU CYREG_PRT0_DM1\r
+SCSI_Out__MSG_raw__DM2 EQU CYREG_PRT0_DM2\r
+SCSI_Out__MSG_raw__DR EQU CYREG_PRT0_DR\r
+SCSI_Out__MSG_raw__INP_DIS EQU CYREG_PRT0_INP_DIS\r
+SCSI_Out__MSG_raw__INTTYPE EQU CYREG_PICU0_INTTYPE4\r
+SCSI_Out__MSG_raw__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
+SCSI_Out__MSG_raw__LCD_EN EQU CYREG_PRT0_LCD_EN\r
+SCSI_Out__MSG_raw__MASK EQU 0x10\r
+SCSI_Out__MSG_raw__PC EQU CYREG_PRT0_PC4\r
+SCSI_Out__MSG_raw__PORT EQU 0\r
+SCSI_Out__MSG_raw__PRT EQU CYREG_PRT0_PRT\r
+SCSI_Out__MSG_raw__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
+SCSI_Out__MSG_raw__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
+SCSI_Out__MSG_raw__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
+SCSI_Out__MSG_raw__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
+SCSI_Out__MSG_raw__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
+SCSI_Out__MSG_raw__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
+SCSI_Out__MSG_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
+SCSI_Out__MSG_raw__PS EQU CYREG_PRT0_PS\r
+SCSI_Out__MSG_raw__SHIFT EQU 4\r
+SCSI_Out__MSG_raw__SLW EQU CYREG_PRT0_SLW\r
+SCSI_Out__REQ__AG EQU CYREG_PRT0_AG\r
+SCSI_Out__REQ__AMUX EQU CYREG_PRT0_AMUX\r
+SCSI_Out__REQ__BIE EQU CYREG_PRT0_BIE\r
+SCSI_Out__REQ__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
+SCSI_Out__REQ__BYP EQU CYREG_PRT0_BYP\r
+SCSI_Out__REQ__CTL EQU CYREG_PRT0_CTL\r
+SCSI_Out__REQ__DM0 EQU CYREG_PRT0_DM0\r
+SCSI_Out__REQ__DM1 EQU CYREG_PRT0_DM1\r
+SCSI_Out__REQ__DM2 EQU CYREG_PRT0_DM2\r
+SCSI_Out__REQ__DR EQU CYREG_PRT0_DR\r
+SCSI_Out__REQ__INP_DIS EQU CYREG_PRT0_INP_DIS\r
+SCSI_Out__REQ__INTTYPE EQU CYREG_PICU0_INTTYPE1\r
+SCSI_Out__REQ__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
+SCSI_Out__REQ__LCD_EN EQU CYREG_PRT0_LCD_EN\r
+SCSI_Out__REQ__MASK EQU 0x02\r
+SCSI_Out__REQ__PC EQU CYREG_PRT0_PC1\r
+SCSI_Out__REQ__PORT EQU 0\r
+SCSI_Out__REQ__PRT EQU CYREG_PRT0_PRT\r
+SCSI_Out__REQ__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
+SCSI_Out__REQ__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
+SCSI_Out__REQ__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
+SCSI_Out__REQ__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
+SCSI_Out__REQ__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
+SCSI_Out__REQ__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
+SCSI_Out__REQ__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
+SCSI_Out__REQ__PS EQU CYREG_PRT0_PS\r
+SCSI_Out__REQ__SHIFT EQU 1\r
+SCSI_Out__REQ__SLW EQU CYREG_PRT0_SLW\r
+SCSI_Out__RST__AG EQU CYREG_PRT0_AG\r
+SCSI_Out__RST__AMUX EQU CYREG_PRT0_AMUX\r
+SCSI_Out__RST__BIE EQU CYREG_PRT0_BIE\r
+SCSI_Out__RST__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
+SCSI_Out__RST__BYP EQU CYREG_PRT0_BYP\r
+SCSI_Out__RST__CTL EQU CYREG_PRT0_CTL\r
+SCSI_Out__RST__DM0 EQU CYREG_PRT0_DM0\r
+SCSI_Out__RST__DM1 EQU CYREG_PRT0_DM1\r
+SCSI_Out__RST__DM2 EQU CYREG_PRT0_DM2\r
+SCSI_Out__RST__DR EQU CYREG_PRT0_DR\r
+SCSI_Out__RST__INP_DIS EQU CYREG_PRT0_INP_DIS\r
+SCSI_Out__RST__INTTYPE EQU CYREG_PICU0_INTTYPE5\r
+SCSI_Out__RST__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
+SCSI_Out__RST__LCD_EN EQU CYREG_PRT0_LCD_EN\r
+SCSI_Out__RST__MASK EQU 0x20\r
+SCSI_Out__RST__PC EQU CYREG_PRT0_PC5\r
+SCSI_Out__RST__PORT EQU 0\r
+SCSI_Out__RST__PRT EQU CYREG_PRT0_PRT\r
+SCSI_Out__RST__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
+SCSI_Out__RST__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
+SCSI_Out__RST__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
+SCSI_Out__RST__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
+SCSI_Out__RST__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
+SCSI_Out__RST__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
+SCSI_Out__RST__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
+SCSI_Out__RST__PS EQU CYREG_PRT0_PS\r
+SCSI_Out__RST__SHIFT EQU 5\r
+SCSI_Out__RST__SLW EQU CYREG_PRT0_SLW\r
+SCSI_Out__SEL__AG EQU CYREG_PRT0_AG\r
+SCSI_Out__SEL__AMUX EQU CYREG_PRT0_AMUX\r
+SCSI_Out__SEL__BIE EQU CYREG_PRT0_BIE\r
+SCSI_Out__SEL__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
+SCSI_Out__SEL__BYP EQU CYREG_PRT0_BYP\r
+SCSI_Out__SEL__CTL EQU CYREG_PRT0_CTL\r
+SCSI_Out__SEL__DM0 EQU CYREG_PRT0_DM0\r
+SCSI_Out__SEL__DM1 EQU CYREG_PRT0_DM1\r
+SCSI_Out__SEL__DM2 EQU CYREG_PRT0_DM2\r
+SCSI_Out__SEL__DR EQU CYREG_PRT0_DR\r
+SCSI_Out__SEL__INP_DIS EQU CYREG_PRT0_INP_DIS\r
+SCSI_Out__SEL__INTTYPE EQU CYREG_PICU0_INTTYPE3\r
+SCSI_Out__SEL__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
+SCSI_Out__SEL__LCD_EN EQU CYREG_PRT0_LCD_EN\r
+SCSI_Out__SEL__MASK EQU 0x08\r
+SCSI_Out__SEL__PC EQU CYREG_PRT0_PC3\r
+SCSI_Out__SEL__PORT EQU 0\r
+SCSI_Out__SEL__PRT EQU CYREG_PRT0_PRT\r
+SCSI_Out__SEL__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
+SCSI_Out__SEL__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
+SCSI_Out__SEL__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
+SCSI_Out__SEL__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
+SCSI_Out__SEL__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
+SCSI_Out__SEL__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
+SCSI_Out__SEL__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
+SCSI_Out__SEL__PS EQU CYREG_PRT0_PS\r
+SCSI_Out__SEL__SHIFT EQU 3\r
+SCSI_Out__SEL__SLW EQU CYREG_PRT0_SLW\r
+SCSI_Out_Bits_Sync_ctrl_reg__0__MASK EQU 0x01\r
+SCSI_Out_Bits_Sync_ctrl_reg__0__POS EQU 0\r
+SCSI_Out_Bits_Sync_ctrl_reg__1__MASK EQU 0x02\r
+SCSI_Out_Bits_Sync_ctrl_reg__1__POS EQU 1\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB08_09_ACTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB08_09_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB08_09_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB08_09_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB08_09_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB08_09_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB08_09_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB08_09_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB08_09_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__2__MASK EQU 0x04\r
+SCSI_Out_Bits_Sync_ctrl_reg__2__POS EQU 2\r
+SCSI_Out_Bits_Sync_ctrl_reg__3__MASK EQU 0x08\r
+SCSI_Out_Bits_Sync_ctrl_reg__3__POS EQU 3\r
+SCSI_Out_Bits_Sync_ctrl_reg__4__MASK EQU 0x10\r
+SCSI_Out_Bits_Sync_ctrl_reg__4__POS EQU 4\r
+SCSI_Out_Bits_Sync_ctrl_reg__5__MASK EQU 0x20\r
+SCSI_Out_Bits_Sync_ctrl_reg__5__POS EQU 5\r
+SCSI_Out_Bits_Sync_ctrl_reg__6__MASK EQU 0x40\r
+SCSI_Out_Bits_Sync_ctrl_reg__6__POS EQU 6\r
+SCSI_Out_Bits_Sync_ctrl_reg__7__MASK EQU 0x80\r
+SCSI_Out_Bits_Sync_ctrl_reg__7__POS EQU 7\r
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB08_ACTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B1_UDB08_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B1_UDB08_ST_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B1_UDB08_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B1_UDB08_ST_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__MASK EQU 0xFF\r
+SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB08_MSK_ACTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB08_MSK_ACTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B1_UDB08_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01\r
+SCSI_Out_Ctl_Sync_ctrl_reg__0__POS EQU 0\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB08_09_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB08_09_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB08_09_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB08_09_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB08_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB08_ST_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB08_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB08_ST_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__MASK EQU 0x01\r
+SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB08_MSK\r
+SCSI_Out_DBx__0__AG EQU CYREG_PRT6_AG\r
+SCSI_Out_DBx__0__AMUX EQU CYREG_PRT6_AMUX\r
+SCSI_Out_DBx__0__BIE EQU CYREG_PRT6_BIE\r
+SCSI_Out_DBx__0__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
+SCSI_Out_DBx__0__BYP EQU CYREG_PRT6_BYP\r
+SCSI_Out_DBx__0__CTL EQU CYREG_PRT6_CTL\r
+SCSI_Out_DBx__0__DM0 EQU CYREG_PRT6_DM0\r
+SCSI_Out_DBx__0__DM1 EQU CYREG_PRT6_DM1\r
+SCSI_Out_DBx__0__DM2 EQU CYREG_PRT6_DM2\r
+SCSI_Out_DBx__0__DR EQU CYREG_PRT6_DR\r
+SCSI_Out_DBx__0__INP_DIS EQU CYREG_PRT6_INP_DIS\r
+SCSI_Out_DBx__0__INTTYPE EQU CYREG_PICU6_INTTYPE3\r
+SCSI_Out_DBx__0__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
+SCSI_Out_DBx__0__LCD_EN EQU CYREG_PRT6_LCD_EN\r
+SCSI_Out_DBx__0__MASK EQU 0x08\r
+SCSI_Out_DBx__0__PC EQU CYREG_PRT6_PC3\r
+SCSI_Out_DBx__0__PORT EQU 6\r
+SCSI_Out_DBx__0__PRT EQU CYREG_PRT6_PRT\r
+SCSI_Out_DBx__0__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
+SCSI_Out_DBx__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
+SCSI_Out_DBx__0__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
+SCSI_Out_DBx__0__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
+SCSI_Out_DBx__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
+SCSI_Out_DBx__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
+SCSI_Out_DBx__0__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
+SCSI_Out_DBx__0__PS EQU CYREG_PRT6_PS\r
+SCSI_Out_DBx__0__SHIFT EQU 3\r
+SCSI_Out_DBx__0__SLW EQU CYREG_PRT6_SLW\r
+SCSI_Out_DBx__1__AG EQU CYREG_PRT6_AG\r
+SCSI_Out_DBx__1__AMUX EQU CYREG_PRT6_AMUX\r
+SCSI_Out_DBx__1__BIE EQU CYREG_PRT6_BIE\r
+SCSI_Out_DBx__1__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
+SCSI_Out_DBx__1__BYP EQU CYREG_PRT6_BYP\r
+SCSI_Out_DBx__1__CTL EQU CYREG_PRT6_CTL\r
+SCSI_Out_DBx__1__DM0 EQU CYREG_PRT6_DM0\r
+SCSI_Out_DBx__1__DM1 EQU CYREG_PRT6_DM1\r
+SCSI_Out_DBx__1__DM2 EQU CYREG_PRT6_DM2\r
+SCSI_Out_DBx__1__DR EQU CYREG_PRT6_DR\r
+SCSI_Out_DBx__1__INP_DIS EQU CYREG_PRT6_INP_DIS\r
+SCSI_Out_DBx__1__INTTYPE EQU CYREG_PICU6_INTTYPE2\r
+SCSI_Out_DBx__1__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
+SCSI_Out_DBx__1__LCD_EN EQU CYREG_PRT6_LCD_EN\r
+SCSI_Out_DBx__1__MASK EQU 0x04\r
+SCSI_Out_DBx__1__PC EQU CYREG_PRT6_PC2\r
+SCSI_Out_DBx__1__PORT EQU 6\r
+SCSI_Out_DBx__1__PRT EQU CYREG_PRT6_PRT\r
+SCSI_Out_DBx__1__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
+SCSI_Out_DBx__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
+SCSI_Out_DBx__1__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
+SCSI_Out_DBx__1__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
+SCSI_Out_DBx__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
+SCSI_Out_DBx__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
+SCSI_Out_DBx__1__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
+SCSI_Out_DBx__1__PS EQU CYREG_PRT6_PS\r
+SCSI_Out_DBx__1__SHIFT EQU 2\r
+SCSI_Out_DBx__1__SLW EQU CYREG_PRT6_SLW\r
+SCSI_Out_DBx__2__AG EQU CYREG_PRT6_AG\r
+SCSI_Out_DBx__2__AMUX EQU CYREG_PRT6_AMUX\r
+SCSI_Out_DBx__2__BIE EQU CYREG_PRT6_BIE\r
+SCSI_Out_DBx__2__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
+SCSI_Out_DBx__2__BYP EQU CYREG_PRT6_BYP\r
+SCSI_Out_DBx__2__CTL EQU CYREG_PRT6_CTL\r
+SCSI_Out_DBx__2__DM0 EQU CYREG_PRT6_DM0\r
+SCSI_Out_DBx__2__DM1 EQU CYREG_PRT6_DM1\r
+SCSI_Out_DBx__2__DM2 EQU CYREG_PRT6_DM2\r
+SCSI_Out_DBx__2__DR EQU CYREG_PRT6_DR\r
+SCSI_Out_DBx__2__INP_DIS EQU CYREG_PRT6_INP_DIS\r
+SCSI_Out_DBx__2__INTTYPE EQU CYREG_PICU6_INTTYPE1\r
+SCSI_Out_DBx__2__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
+SCSI_Out_DBx__2__LCD_EN EQU CYREG_PRT6_LCD_EN\r
+SCSI_Out_DBx__2__MASK EQU 0x02\r
+SCSI_Out_DBx__2__PC EQU CYREG_PRT6_PC1\r
+SCSI_Out_DBx__2__PORT EQU 6\r
+SCSI_Out_DBx__2__PRT EQU CYREG_PRT6_PRT\r
+SCSI_Out_DBx__2__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
+SCSI_Out_DBx__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
+SCSI_Out_DBx__2__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
+SCSI_Out_DBx__2__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
+SCSI_Out_DBx__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
+SCSI_Out_DBx__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
+SCSI_Out_DBx__2__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
+SCSI_Out_DBx__2__PS EQU CYREG_PRT6_PS\r
+SCSI_Out_DBx__2__SHIFT EQU 1\r
+SCSI_Out_DBx__2__SLW EQU CYREG_PRT6_SLW\r
+SCSI_Out_DBx__3__AG EQU CYREG_PRT6_AG\r
+SCSI_Out_DBx__3__AMUX EQU CYREG_PRT6_AMUX\r
+SCSI_Out_DBx__3__BIE EQU CYREG_PRT6_BIE\r
+SCSI_Out_DBx__3__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
+SCSI_Out_DBx__3__BYP EQU CYREG_PRT6_BYP\r
+SCSI_Out_DBx__3__CTL EQU CYREG_PRT6_CTL\r
+SCSI_Out_DBx__3__DM0 EQU CYREG_PRT6_DM0\r
+SCSI_Out_DBx__3__DM1 EQU CYREG_PRT6_DM1\r
+SCSI_Out_DBx__3__DM2 EQU CYREG_PRT6_DM2\r
+SCSI_Out_DBx__3__DR EQU CYREG_PRT6_DR\r
+SCSI_Out_DBx__3__INP_DIS EQU CYREG_PRT6_INP_DIS\r
+SCSI_Out_DBx__3__INTTYPE EQU CYREG_PICU6_INTTYPE0\r
+SCSI_Out_DBx__3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
+SCSI_Out_DBx__3__LCD_EN EQU CYREG_PRT6_LCD_EN\r
+SCSI_Out_DBx__3__MASK EQU 0x01\r
+SCSI_Out_DBx__3__PC EQU CYREG_PRT6_PC0\r
+SCSI_Out_DBx__3__PORT EQU 6\r
+SCSI_Out_DBx__3__PRT EQU CYREG_PRT6_PRT\r
+SCSI_Out_DBx__3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
+SCSI_Out_DBx__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
+SCSI_Out_DBx__3__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
+SCSI_Out_DBx__3__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
+SCSI_Out_DBx__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
+SCSI_Out_DBx__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
+SCSI_Out_DBx__3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
+SCSI_Out_DBx__3__PS EQU CYREG_PRT6_PS\r
+SCSI_Out_DBx__3__SHIFT EQU 0\r
+SCSI_Out_DBx__3__SLW EQU CYREG_PRT6_SLW\r
+SCSI_Out_DBx__4__AG EQU CYREG_PRT4_AG\r
+SCSI_Out_DBx__4__AMUX EQU CYREG_PRT4_AMUX\r
+SCSI_Out_DBx__4__BIE EQU CYREG_PRT4_BIE\r
+SCSI_Out_DBx__4__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
+SCSI_Out_DBx__4__BYP EQU CYREG_PRT4_BYP\r
+SCSI_Out_DBx__4__CTL EQU CYREG_PRT4_CTL\r
+SCSI_Out_DBx__4__DM0 EQU CYREG_PRT4_DM0\r
+SCSI_Out_DBx__4__DM1 EQU CYREG_PRT4_DM1\r
+SCSI_Out_DBx__4__DM2 EQU CYREG_PRT4_DM2\r
+SCSI_Out_DBx__4__DR EQU CYREG_PRT4_DR\r
+SCSI_Out_DBx__4__INP_DIS EQU CYREG_PRT4_INP_DIS\r
+SCSI_Out_DBx__4__INTTYPE EQU CYREG_PICU4_INTTYPE7\r
+SCSI_Out_DBx__4__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
+SCSI_Out_DBx__4__LCD_EN EQU CYREG_PRT4_LCD_EN\r
+SCSI_Out_DBx__4__MASK EQU 0x80\r
+SCSI_Out_DBx__4__PC EQU CYREG_PRT4_PC7\r
+SCSI_Out_DBx__4__PORT EQU 4\r
+SCSI_Out_DBx__4__PRT EQU CYREG_PRT4_PRT\r
+SCSI_Out_DBx__4__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
+SCSI_Out_DBx__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
+SCSI_Out_DBx__4__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
+SCSI_Out_DBx__4__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
+SCSI_Out_DBx__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
+SCSI_Out_DBx__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
+SCSI_Out_DBx__4__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
+SCSI_Out_DBx__4__PS EQU CYREG_PRT4_PS\r
+SCSI_Out_DBx__4__SHIFT EQU 7\r
+SCSI_Out_DBx__4__SLW EQU CYREG_PRT4_SLW\r
+SCSI_Out_DBx__5__AG EQU CYREG_PRT4_AG\r
+SCSI_Out_DBx__5__AMUX EQU CYREG_PRT4_AMUX\r
+SCSI_Out_DBx__5__BIE EQU CYREG_PRT4_BIE\r
+SCSI_Out_DBx__5__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
+SCSI_Out_DBx__5__BYP EQU CYREG_PRT4_BYP\r
+SCSI_Out_DBx__5__CTL EQU CYREG_PRT4_CTL\r
+SCSI_Out_DBx__5__DM0 EQU CYREG_PRT4_DM0\r
+SCSI_Out_DBx__5__DM1 EQU CYREG_PRT4_DM1\r
+SCSI_Out_DBx__5__DM2 EQU CYREG_PRT4_DM2\r
+SCSI_Out_DBx__5__DR EQU CYREG_PRT4_DR\r
+SCSI_Out_DBx__5__INP_DIS EQU CYREG_PRT4_INP_DIS\r
+SCSI_Out_DBx__5__INTTYPE EQU CYREG_PICU4_INTTYPE6\r
+SCSI_Out_DBx__5__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
+SCSI_Out_DBx__5__LCD_EN EQU CYREG_PRT4_LCD_EN\r
+SCSI_Out_DBx__5__MASK EQU 0x40\r
+SCSI_Out_DBx__5__PC EQU CYREG_PRT4_PC6\r
+SCSI_Out_DBx__5__PORT EQU 4\r
+SCSI_Out_DBx__5__PRT EQU CYREG_PRT4_PRT\r
+SCSI_Out_DBx__5__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
+SCSI_Out_DBx__5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
+SCSI_Out_DBx__5__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
+SCSI_Out_DBx__5__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
+SCSI_Out_DBx__5__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
+SCSI_Out_DBx__5__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
+SCSI_Out_DBx__5__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
+SCSI_Out_DBx__5__PS EQU CYREG_PRT4_PS\r
+SCSI_Out_DBx__5__SHIFT EQU 6\r
+SCSI_Out_DBx__5__SLW EQU CYREG_PRT4_SLW\r
+SCSI_Out_DBx__6__AG EQU CYREG_PRT4_AG\r
+SCSI_Out_DBx__6__AMUX EQU CYREG_PRT4_AMUX\r
+SCSI_Out_DBx__6__BIE EQU CYREG_PRT4_BIE\r
+SCSI_Out_DBx__6__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
+SCSI_Out_DBx__6__BYP EQU CYREG_PRT4_BYP\r
+SCSI_Out_DBx__6__CTL EQU CYREG_PRT4_CTL\r
+SCSI_Out_DBx__6__DM0 EQU CYREG_PRT4_DM0\r
+SCSI_Out_DBx__6__DM1 EQU CYREG_PRT4_DM1\r
+SCSI_Out_DBx__6__DM2 EQU CYREG_PRT4_DM2\r
+SCSI_Out_DBx__6__DR EQU CYREG_PRT4_DR\r
+SCSI_Out_DBx__6__INP_DIS EQU CYREG_PRT4_INP_DIS\r
+SCSI_Out_DBx__6__INTTYPE EQU CYREG_PICU4_INTTYPE5\r
+SCSI_Out_DBx__6__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
+SCSI_Out_DBx__6__LCD_EN EQU CYREG_PRT4_LCD_EN\r
+SCSI_Out_DBx__6__MASK EQU 0x20\r
+SCSI_Out_DBx__6__PC EQU CYREG_PRT4_PC5\r
+SCSI_Out_DBx__6__PORT EQU 4\r
+SCSI_Out_DBx__6__PRT EQU CYREG_PRT4_PRT\r
+SCSI_Out_DBx__6__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
+SCSI_Out_DBx__6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
+SCSI_Out_DBx__6__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
+SCSI_Out_DBx__6__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
+SCSI_Out_DBx__6__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
+SCSI_Out_DBx__6__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
+SCSI_Out_DBx__6__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
+SCSI_Out_DBx__6__PS EQU CYREG_PRT4_PS\r
+SCSI_Out_DBx__6__SHIFT EQU 5\r
+SCSI_Out_DBx__6__SLW EQU CYREG_PRT4_SLW\r
+SCSI_Out_DBx__7__AG EQU CYREG_PRT4_AG\r
+SCSI_Out_DBx__7__AMUX EQU CYREG_PRT4_AMUX\r
+SCSI_Out_DBx__7__BIE EQU CYREG_PRT4_BIE\r
+SCSI_Out_DBx__7__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
+SCSI_Out_DBx__7__BYP EQU CYREG_PRT4_BYP\r
+SCSI_Out_DBx__7__CTL EQU CYREG_PRT4_CTL\r
+SCSI_Out_DBx__7__DM0 EQU CYREG_PRT4_DM0\r
+SCSI_Out_DBx__7__DM1 EQU CYREG_PRT4_DM1\r
+SCSI_Out_DBx__7__DM2 EQU CYREG_PRT4_DM2\r
+SCSI_Out_DBx__7__DR EQU CYREG_PRT4_DR\r
+SCSI_Out_DBx__7__INP_DIS EQU CYREG_PRT4_INP_DIS\r
+SCSI_Out_DBx__7__INTTYPE EQU CYREG_PICU4_INTTYPE4\r
+SCSI_Out_DBx__7__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
+SCSI_Out_DBx__7__LCD_EN EQU CYREG_PRT4_LCD_EN\r
+SCSI_Out_DBx__7__MASK EQU 0x10\r
+SCSI_Out_DBx__7__PC EQU CYREG_PRT4_PC4\r
+SCSI_Out_DBx__7__PORT EQU 4\r
+SCSI_Out_DBx__7__PRT EQU CYREG_PRT4_PRT\r
+SCSI_Out_DBx__7__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
+SCSI_Out_DBx__7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
+SCSI_Out_DBx__7__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
+SCSI_Out_DBx__7__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
+SCSI_Out_DBx__7__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
+SCSI_Out_DBx__7__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
+SCSI_Out_DBx__7__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
+SCSI_Out_DBx__7__PS EQU CYREG_PRT4_PS\r
+SCSI_Out_DBx__7__SHIFT EQU 4\r
+SCSI_Out_DBx__7__SLW EQU CYREG_PRT4_SLW\r
+SCSI_Out_DBx__DB0__AG EQU CYREG_PRT6_AG\r
+SCSI_Out_DBx__DB0__AMUX EQU CYREG_PRT6_AMUX\r
+SCSI_Out_DBx__DB0__BIE EQU CYREG_PRT6_BIE\r
+SCSI_Out_DBx__DB0__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
+SCSI_Out_DBx__DB0__BYP EQU CYREG_PRT6_BYP\r
+SCSI_Out_DBx__DB0__CTL EQU CYREG_PRT6_CTL\r
+SCSI_Out_DBx__DB0__DM0 EQU CYREG_PRT6_DM0\r
+SCSI_Out_DBx__DB0__DM1 EQU CYREG_PRT6_DM1\r
+SCSI_Out_DBx__DB0__DM2 EQU CYREG_PRT6_DM2\r
+SCSI_Out_DBx__DB0__DR EQU CYREG_PRT6_DR\r
+SCSI_Out_DBx__DB0__INP_DIS EQU CYREG_PRT6_INP_DIS\r
+SCSI_Out_DBx__DB0__INTTYPE EQU CYREG_PICU6_INTTYPE3\r
+SCSI_Out_DBx__DB0__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
+SCSI_Out_DBx__DB0__LCD_EN EQU CYREG_PRT6_LCD_EN\r
+SCSI_Out_DBx__DB0__MASK EQU 0x08\r
+SCSI_Out_DBx__DB0__PC EQU CYREG_PRT6_PC3\r
+SCSI_Out_DBx__DB0__PORT EQU 6\r
+SCSI_Out_DBx__DB0__PRT EQU CYREG_PRT6_PRT\r
+SCSI_Out_DBx__DB0__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
+SCSI_Out_DBx__DB0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
+SCSI_Out_DBx__DB0__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
+SCSI_Out_DBx__DB0__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
+SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
+SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
+SCSI_Out_DBx__DB0__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
+SCSI_Out_DBx__DB0__PS EQU CYREG_PRT6_PS\r
+SCSI_Out_DBx__DB0__SHIFT EQU 3\r
+SCSI_Out_DBx__DB0__SLW EQU CYREG_PRT6_SLW\r
+SCSI_Out_DBx__DB1__AG EQU CYREG_PRT6_AG\r
+SCSI_Out_DBx__DB1__AMUX EQU CYREG_PRT6_AMUX\r
+SCSI_Out_DBx__DB1__BIE EQU CYREG_PRT6_BIE\r
+SCSI_Out_DBx__DB1__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
+SCSI_Out_DBx__DB1__BYP EQU CYREG_PRT6_BYP\r
+SCSI_Out_DBx__DB1__CTL EQU CYREG_PRT6_CTL\r
+SCSI_Out_DBx__DB1__DM0 EQU CYREG_PRT6_DM0\r
+SCSI_Out_DBx__DB1__DM1 EQU CYREG_PRT6_DM1\r
+SCSI_Out_DBx__DB1__DM2 EQU CYREG_PRT6_DM2\r
+SCSI_Out_DBx__DB1__DR EQU CYREG_PRT6_DR\r
+SCSI_Out_DBx__DB1__INP_DIS EQU CYREG_PRT6_INP_DIS\r
+SCSI_Out_DBx__DB1__INTTYPE EQU CYREG_PICU6_INTTYPE2\r
+SCSI_Out_DBx__DB1__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
+SCSI_Out_DBx__DB1__LCD_EN EQU CYREG_PRT6_LCD_EN\r
+SCSI_Out_DBx__DB1__MASK EQU 0x04\r
+SCSI_Out_DBx__DB1__PC EQU CYREG_PRT6_PC2\r
+SCSI_Out_DBx__DB1__PORT EQU 6\r
+SCSI_Out_DBx__DB1__PRT EQU CYREG_PRT6_PRT\r
+SCSI_Out_DBx__DB1__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
+SCSI_Out_DBx__DB1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
+SCSI_Out_DBx__DB1__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
+SCSI_Out_DBx__DB1__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
+SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
+SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
+SCSI_Out_DBx__DB1__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
+SCSI_Out_DBx__DB1__PS EQU CYREG_PRT6_PS\r
+SCSI_Out_DBx__DB1__SHIFT EQU 2\r
+SCSI_Out_DBx__DB1__SLW EQU CYREG_PRT6_SLW\r
+SCSI_Out_DBx__DB2__AG EQU CYREG_PRT6_AG\r
+SCSI_Out_DBx__DB2__AMUX EQU CYREG_PRT6_AMUX\r
+SCSI_Out_DBx__DB2__BIE EQU CYREG_PRT6_BIE\r
+SCSI_Out_DBx__DB2__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
+SCSI_Out_DBx__DB2__BYP EQU CYREG_PRT6_BYP\r
+SCSI_Out_DBx__DB2__CTL EQU CYREG_PRT6_CTL\r
+SCSI_Out_DBx__DB2__DM0 EQU CYREG_PRT6_DM0\r
+SCSI_Out_DBx__DB2__DM1 EQU CYREG_PRT6_DM1\r
+SCSI_Out_DBx__DB2__DM2 EQU CYREG_PRT6_DM2\r
+SCSI_Out_DBx__DB2__DR EQU CYREG_PRT6_DR\r
+SCSI_Out_DBx__DB2__INP_DIS EQU CYREG_PRT6_INP_DIS\r
+SCSI_Out_DBx__DB2__INTTYPE EQU CYREG_PICU6_INTTYPE1\r
+SCSI_Out_DBx__DB2__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
+SCSI_Out_DBx__DB2__LCD_EN EQU CYREG_PRT6_LCD_EN\r
+SCSI_Out_DBx__DB2__MASK EQU 0x02\r
+SCSI_Out_DBx__DB2__PC EQU CYREG_PRT6_PC1\r
+SCSI_Out_DBx__DB2__PORT EQU 6\r
+SCSI_Out_DBx__DB2__PRT EQU CYREG_PRT6_PRT\r
+SCSI_Out_DBx__DB2__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
+SCSI_Out_DBx__DB2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
+SCSI_Out_DBx__DB2__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
+SCSI_Out_DBx__DB2__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
+SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
+SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
+SCSI_Out_DBx__DB2__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
+SCSI_Out_DBx__DB2__PS EQU CYREG_PRT6_PS\r
+SCSI_Out_DBx__DB2__SHIFT EQU 1\r
+SCSI_Out_DBx__DB2__SLW EQU CYREG_PRT6_SLW\r
+SCSI_Out_DBx__DB3__AG EQU CYREG_PRT6_AG\r
+SCSI_Out_DBx__DB3__AMUX EQU CYREG_PRT6_AMUX\r
+SCSI_Out_DBx__DB3__BIE EQU CYREG_PRT6_BIE\r
+SCSI_Out_DBx__DB3__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
+SCSI_Out_DBx__DB3__BYP EQU CYREG_PRT6_BYP\r
+SCSI_Out_DBx__DB3__CTL EQU CYREG_PRT6_CTL\r
+SCSI_Out_DBx__DB3__DM0 EQU CYREG_PRT6_DM0\r
+SCSI_Out_DBx__DB3__DM1 EQU CYREG_PRT6_DM1\r
+SCSI_Out_DBx__DB3__DM2 EQU CYREG_PRT6_DM2\r
+SCSI_Out_DBx__DB3__DR EQU CYREG_PRT6_DR\r
+SCSI_Out_DBx__DB3__INP_DIS EQU CYREG_PRT6_INP_DIS\r
+SCSI_Out_DBx__DB3__INTTYPE EQU CYREG_PICU6_INTTYPE0\r
+SCSI_Out_DBx__DB3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
+SCSI_Out_DBx__DB3__LCD_EN EQU CYREG_PRT6_LCD_EN\r
+SCSI_Out_DBx__DB3__MASK EQU 0x01\r
+SCSI_Out_DBx__DB3__PC EQU CYREG_PRT6_PC0\r
+SCSI_Out_DBx__DB3__PORT EQU 6\r
+SCSI_Out_DBx__DB3__PRT EQU CYREG_PRT6_PRT\r
+SCSI_Out_DBx__DB3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
+SCSI_Out_DBx__DB3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
+SCSI_Out_DBx__DB3__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
+SCSI_Out_DBx__DB3__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
+SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
+SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
+SCSI_Out_DBx__DB3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
+SCSI_Out_DBx__DB3__PS EQU CYREG_PRT6_PS\r
+SCSI_Out_DBx__DB3__SHIFT EQU 0\r
+SCSI_Out_DBx__DB3__SLW EQU CYREG_PRT6_SLW\r
+SCSI_Out_DBx__DB4__AG EQU CYREG_PRT4_AG\r
+SCSI_Out_DBx__DB4__AMUX EQU CYREG_PRT4_AMUX\r
+SCSI_Out_DBx__DB4__BIE EQU CYREG_PRT4_BIE\r
+SCSI_Out_DBx__DB4__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
+SCSI_Out_DBx__DB4__BYP EQU CYREG_PRT4_BYP\r
+SCSI_Out_DBx__DB4__CTL EQU CYREG_PRT4_CTL\r
+SCSI_Out_DBx__DB4__DM0 EQU CYREG_PRT4_DM0\r
+SCSI_Out_DBx__DB4__DM1 EQU CYREG_PRT4_DM1\r
+SCSI_Out_DBx__DB4__DM2 EQU CYREG_PRT4_DM2\r
+SCSI_Out_DBx__DB4__DR EQU CYREG_PRT4_DR\r
+SCSI_Out_DBx__DB4__INP_DIS EQU CYREG_PRT4_INP_DIS\r
+SCSI_Out_DBx__DB4__INTTYPE EQU CYREG_PICU4_INTTYPE7\r
+SCSI_Out_DBx__DB4__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
+SCSI_Out_DBx__DB4__LCD_EN EQU CYREG_PRT4_LCD_EN\r
+SCSI_Out_DBx__DB4__MASK EQU 0x80\r
+SCSI_Out_DBx__DB4__PC EQU CYREG_PRT4_PC7\r
+SCSI_Out_DBx__DB4__PORT EQU 4\r
+SCSI_Out_DBx__DB4__PRT EQU CYREG_PRT4_PRT\r
+SCSI_Out_DBx__DB4__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
+SCSI_Out_DBx__DB4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
+SCSI_Out_DBx__DB4__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
+SCSI_Out_DBx__DB4__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
+SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
+SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
+SCSI_Out_DBx__DB4__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
+SCSI_Out_DBx__DB4__PS EQU CYREG_PRT4_PS\r
+SCSI_Out_DBx__DB4__SHIFT EQU 7\r
+SCSI_Out_DBx__DB4__SLW EQU CYREG_PRT4_SLW\r
+SCSI_Out_DBx__DB5__AG EQU CYREG_PRT4_AG\r
+SCSI_Out_DBx__DB5__AMUX EQU CYREG_PRT4_AMUX\r
+SCSI_Out_DBx__DB5__BIE EQU CYREG_PRT4_BIE\r
+SCSI_Out_DBx__DB5__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
+SCSI_Out_DBx__DB5__BYP EQU CYREG_PRT4_BYP\r
+SCSI_Out_DBx__DB5__CTL EQU CYREG_PRT4_CTL\r
+SCSI_Out_DBx__DB5__DM0 EQU CYREG_PRT4_DM0\r
+SCSI_Out_DBx__DB5__DM1 EQU CYREG_PRT4_DM1\r
+SCSI_Out_DBx__DB5__DM2 EQU CYREG_PRT4_DM2\r
+SCSI_Out_DBx__DB5__DR EQU CYREG_PRT4_DR\r
+SCSI_Out_DBx__DB5__INP_DIS EQU CYREG_PRT4_INP_DIS\r
+SCSI_Out_DBx__DB5__INTTYPE EQU CYREG_PICU4_INTTYPE6\r
+SCSI_Out_DBx__DB5__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
+SCSI_Out_DBx__DB5__LCD_EN EQU CYREG_PRT4_LCD_EN\r
+SCSI_Out_DBx__DB5__MASK EQU 0x40\r
+SCSI_Out_DBx__DB5__PC EQU CYREG_PRT4_PC6\r
+SCSI_Out_DBx__DB5__PORT EQU 4\r
+SCSI_Out_DBx__DB5__PRT EQU CYREG_PRT4_PRT\r
+SCSI_Out_DBx__DB5__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
+SCSI_Out_DBx__DB5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
+SCSI_Out_DBx__DB5__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
+SCSI_Out_DBx__DB5__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
+SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
+SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
+SCSI_Out_DBx__DB5__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
+SCSI_Out_DBx__DB5__PS EQU CYREG_PRT4_PS\r
+SCSI_Out_DBx__DB5__SHIFT EQU 6\r
+SCSI_Out_DBx__DB5__SLW EQU CYREG_PRT4_SLW\r
+SCSI_Out_DBx__DB6__AG EQU CYREG_PRT4_AG\r
+SCSI_Out_DBx__DB6__AMUX EQU CYREG_PRT4_AMUX\r
+SCSI_Out_DBx__DB6__BIE EQU CYREG_PRT4_BIE\r
+SCSI_Out_DBx__DB6__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
+SCSI_Out_DBx__DB6__BYP EQU CYREG_PRT4_BYP\r
+SCSI_Out_DBx__DB6__CTL EQU CYREG_PRT4_CTL\r
+SCSI_Out_DBx__DB6__DM0 EQU CYREG_PRT4_DM0\r
+SCSI_Out_DBx__DB6__DM1 EQU CYREG_PRT4_DM1\r
+SCSI_Out_DBx__DB6__DM2 EQU CYREG_PRT4_DM2\r
+SCSI_Out_DBx__DB6__DR EQU CYREG_PRT4_DR\r
+SCSI_Out_DBx__DB6__INP_DIS EQU CYREG_PRT4_INP_DIS\r
+SCSI_Out_DBx__DB6__INTTYPE EQU CYREG_PICU4_INTTYPE5\r
+SCSI_Out_DBx__DB6__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
+SCSI_Out_DBx__DB6__LCD_EN EQU CYREG_PRT4_LCD_EN\r
+SCSI_Out_DBx__DB6__MASK EQU 0x20\r
+SCSI_Out_DBx__DB6__PC EQU CYREG_PRT4_PC5\r
+SCSI_Out_DBx__DB6__PORT EQU 4\r
+SCSI_Out_DBx__DB6__PRT EQU CYREG_PRT4_PRT\r
+SCSI_Out_DBx__DB6__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
+SCSI_Out_DBx__DB6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
+SCSI_Out_DBx__DB6__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
+SCSI_Out_DBx__DB6__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
+SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
+SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
+SCSI_Out_DBx__DB6__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
+SCSI_Out_DBx__DB6__PS EQU CYREG_PRT4_PS\r
+SCSI_Out_DBx__DB6__SHIFT EQU 5\r
+SCSI_Out_DBx__DB6__SLW EQU CYREG_PRT4_SLW\r
+SCSI_Out_DBx__DB7__AG EQU CYREG_PRT4_AG\r
+SCSI_Out_DBx__DB7__AMUX EQU CYREG_PRT4_AMUX\r
+SCSI_Out_DBx__DB7__BIE EQU CYREG_PRT4_BIE\r
+SCSI_Out_DBx__DB7__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
+SCSI_Out_DBx__DB7__BYP EQU CYREG_PRT4_BYP\r
+SCSI_Out_DBx__DB7__CTL EQU CYREG_PRT4_CTL\r
+SCSI_Out_DBx__DB7__DM0 EQU CYREG_PRT4_DM0\r
+SCSI_Out_DBx__DB7__DM1 EQU CYREG_PRT4_DM1\r
+SCSI_Out_DBx__DB7__DM2 EQU CYREG_PRT4_DM2\r
+SCSI_Out_DBx__DB7__DR EQU CYREG_PRT4_DR\r
+SCSI_Out_DBx__DB7__INP_DIS EQU CYREG_PRT4_INP_DIS\r
+SCSI_Out_DBx__DB7__INTTYPE EQU CYREG_PICU4_INTTYPE4\r
+SCSI_Out_DBx__DB7__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
+SCSI_Out_DBx__DB7__LCD_EN EQU CYREG_PRT4_LCD_EN\r
+SCSI_Out_DBx__DB7__MASK EQU 0x10\r
+SCSI_Out_DBx__DB7__PC EQU CYREG_PRT4_PC4\r
+SCSI_Out_DBx__DB7__PORT EQU 4\r
+SCSI_Out_DBx__DB7__PRT EQU CYREG_PRT4_PRT\r
+SCSI_Out_DBx__DB7__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
+SCSI_Out_DBx__DB7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
+SCSI_Out_DBx__DB7__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
+SCSI_Out_DBx__DB7__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
+SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
+SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
+SCSI_Out_DBx__DB7__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
+SCSI_Out_DBx__DB7__PS EQU CYREG_PRT4_PS\r
+SCSI_Out_DBx__DB7__SHIFT EQU 4\r
+SCSI_Out_DBx__DB7__SLW EQU CYREG_PRT4_SLW\r
+\r
+; SD_RX_DMA\r
+SD_RX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0\r
+SD_RX_DMA__DRQ_NUMBER EQU 2\r
+SD_RX_DMA__NUMBEROF_TDS EQU 0\r
+SD_RX_DMA__PRIORITY EQU 0\r
+SD_RX_DMA__TERMIN_EN EQU 0\r
+SD_RX_DMA__TERMIN_SEL EQU 0\r
+SD_RX_DMA__TERMOUT0_EN EQU 1\r
+SD_RX_DMA__TERMOUT0_SEL EQU 2\r
+SD_RX_DMA__TERMOUT1_EN EQU 0\r
+SD_RX_DMA__TERMOUT1_SEL EQU 0\r
+SD_RX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
+SD_RX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
+SD_RX_DMA_COMPLETE__INTC_MASK EQU 0x20\r
+SD_RX_DMA_COMPLETE__INTC_NUMBER EQU 5\r
+SD_RX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7\r
+SD_RX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_5\r
+SD_RX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
+SD_RX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
+\r
+; SD_TX_DMA\r
+SD_TX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0\r
+SD_TX_DMA__DRQ_NUMBER EQU 3\r
+SD_TX_DMA__NUMBEROF_TDS EQU 0\r
+SD_TX_DMA__PRIORITY EQU 1\r
+SD_TX_DMA__TERMIN_EN EQU 0\r
+SD_TX_DMA__TERMIN_SEL EQU 0\r
+SD_TX_DMA__TERMOUT0_EN EQU 1\r
+SD_TX_DMA__TERMOUT0_SEL EQU 3\r
+SD_TX_DMA__TERMOUT1_EN EQU 0\r
+SD_TX_DMA__TERMOUT1_SEL EQU 0\r
+SD_TX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
+SD_TX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
+SD_TX_DMA_COMPLETE__INTC_MASK EQU 0x40\r
+SD_TX_DMA_COMPLETE__INTC_NUMBER EQU 6\r
+SD_TX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7\r
+SD_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_6\r
+SD_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
+SD_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
+\r
+; SCSI_Noise\r
+SCSI_Noise__0__AG EQU CYREG_PRT12_AG\r
+SCSI_Noise__0__BIE EQU CYREG_PRT12_BIE\r
+SCSI_Noise__0__BIT_MASK EQU CYREG_PRT12_BIT_MASK\r
+SCSI_Noise__0__BYP EQU CYREG_PRT12_BYP\r
+SCSI_Noise__0__DM0 EQU CYREG_PRT12_DM0\r
+SCSI_Noise__0__DM1 EQU CYREG_PRT12_DM1\r
+SCSI_Noise__0__DM2 EQU CYREG_PRT12_DM2\r
+SCSI_Noise__0__DR EQU CYREG_PRT12_DR\r
+SCSI_Noise__0__INP_DIS EQU CYREG_PRT12_INP_DIS\r
+SCSI_Noise__0__INTTYPE EQU CYREG_PICU12_INTTYPE5\r
+SCSI_Noise__0__MASK EQU 0x20\r
+SCSI_Noise__0__PC EQU CYREG_PRT12_PC5\r
+SCSI_Noise__0__PORT EQU 12\r
+SCSI_Noise__0__PRT EQU CYREG_PRT12_PRT\r
+SCSI_Noise__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN\r
+SCSI_Noise__0__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0\r
+SCSI_Noise__0__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1\r
+SCSI_Noise__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0\r
+SCSI_Noise__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1\r
+SCSI_Noise__0__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT\r
+SCSI_Noise__0__PS EQU CYREG_PRT12_PS\r
+SCSI_Noise__0__SHIFT EQU 5\r
+SCSI_Noise__0__SIO_CFG EQU CYREG_PRT12_SIO_CFG\r
+SCSI_Noise__0__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF\r
+SCSI_Noise__0__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN\r
+SCSI_Noise__0__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ\r
+SCSI_Noise__0__SLW EQU CYREG_PRT12_SLW\r
+SCSI_Noise__1__AG EQU CYREG_PRT6_AG\r
+SCSI_Noise__1__AMUX EQU CYREG_PRT6_AMUX\r
+SCSI_Noise__1__BIE EQU CYREG_PRT6_BIE\r
+SCSI_Noise__1__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
+SCSI_Noise__1__BYP EQU CYREG_PRT6_BYP\r
+SCSI_Noise__1__CTL EQU CYREG_PRT6_CTL\r
+SCSI_Noise__1__DM0 EQU CYREG_PRT6_DM0\r
+SCSI_Noise__1__DM1 EQU CYREG_PRT6_DM1\r
+SCSI_Noise__1__DM2 EQU CYREG_PRT6_DM2\r
+SCSI_Noise__1__DR EQU CYREG_PRT6_DR\r
+SCSI_Noise__1__INP_DIS EQU CYREG_PRT6_INP_DIS\r
+SCSI_Noise__1__INTTYPE EQU CYREG_PICU6_INTTYPE4\r
+SCSI_Noise__1__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
+SCSI_Noise__1__LCD_EN EQU CYREG_PRT6_LCD_EN\r
+SCSI_Noise__1__MASK EQU 0x10\r
+SCSI_Noise__1__PC EQU CYREG_PRT6_PC4\r
+SCSI_Noise__1__PORT EQU 6\r
+SCSI_Noise__1__PRT EQU CYREG_PRT6_PRT\r
+SCSI_Noise__1__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
+SCSI_Noise__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
+SCSI_Noise__1__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
+SCSI_Noise__1__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
+SCSI_Noise__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
+SCSI_Noise__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
+SCSI_Noise__1__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
+SCSI_Noise__1__PS EQU CYREG_PRT6_PS\r
+SCSI_Noise__1__SHIFT EQU 4\r
+SCSI_Noise__1__SLW EQU CYREG_PRT6_SLW\r
+SCSI_Noise__2__AG EQU CYREG_PRT5_AG\r
+SCSI_Noise__2__AMUX EQU CYREG_PRT5_AMUX\r
+SCSI_Noise__2__BIE EQU CYREG_PRT5_BIE\r
+SCSI_Noise__2__BIT_MASK EQU CYREG_PRT5_BIT_MASK\r
+SCSI_Noise__2__BYP EQU CYREG_PRT5_BYP\r
+SCSI_Noise__2__CTL EQU CYREG_PRT5_CTL\r
+SCSI_Noise__2__DM0 EQU CYREG_PRT5_DM0\r
+SCSI_Noise__2__DM1 EQU CYREG_PRT5_DM1\r
+SCSI_Noise__2__DM2 EQU CYREG_PRT5_DM2\r
+SCSI_Noise__2__DR EQU CYREG_PRT5_DR\r
+SCSI_Noise__2__INP_DIS EQU CYREG_PRT5_INP_DIS\r
+SCSI_Noise__2__INTTYPE EQU CYREG_PICU5_INTTYPE0\r
+SCSI_Noise__2__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG\r
+SCSI_Noise__2__LCD_EN EQU CYREG_PRT5_LCD_EN\r
+SCSI_Noise__2__MASK EQU 0x01\r
+SCSI_Noise__2__PC EQU CYREG_PRT5_PC0\r
+SCSI_Noise__2__PORT EQU 5\r
+SCSI_Noise__2__PRT EQU CYREG_PRT5_PRT\r
+SCSI_Noise__2__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL\r
+SCSI_Noise__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN\r
+SCSI_Noise__2__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0\r
+SCSI_Noise__2__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1\r
+SCSI_Noise__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0\r
+SCSI_Noise__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1\r
+SCSI_Noise__2__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT\r
+SCSI_Noise__2__PS EQU CYREG_PRT5_PS\r
+SCSI_Noise__2__SHIFT EQU 0\r
+SCSI_Noise__2__SLW EQU CYREG_PRT5_SLW\r
+SCSI_Noise__3__AG EQU CYREG_PRT6_AG\r
+SCSI_Noise__3__AMUX EQU CYREG_PRT6_AMUX\r
+SCSI_Noise__3__BIE EQU CYREG_PRT6_BIE\r
+SCSI_Noise__3__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
+SCSI_Noise__3__BYP EQU CYREG_PRT6_BYP\r
+SCSI_Noise__3__CTL EQU CYREG_PRT6_CTL\r
+SCSI_Noise__3__DM0 EQU CYREG_PRT6_DM0\r
+SCSI_Noise__3__DM1 EQU CYREG_PRT6_DM1\r
+SCSI_Noise__3__DM2 EQU CYREG_PRT6_DM2\r
+SCSI_Noise__3__DR EQU CYREG_PRT6_DR\r
+SCSI_Noise__3__INP_DIS EQU CYREG_PRT6_INP_DIS\r
+SCSI_Noise__3__INTTYPE EQU CYREG_PICU6_INTTYPE6\r
+SCSI_Noise__3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
+SCSI_Noise__3__LCD_EN EQU CYREG_PRT6_LCD_EN\r
+SCSI_Noise__3__MASK EQU 0x40\r
+SCSI_Noise__3__PC EQU CYREG_PRT6_PC6\r
+SCSI_Noise__3__PORT EQU 6\r
+SCSI_Noise__3__PRT EQU CYREG_PRT6_PRT\r
+SCSI_Noise__3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
+SCSI_Noise__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
+SCSI_Noise__3__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
+SCSI_Noise__3__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
+SCSI_Noise__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
+SCSI_Noise__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
+SCSI_Noise__3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
+SCSI_Noise__3__PS EQU CYREG_PRT6_PS\r
+SCSI_Noise__3__SHIFT EQU 6\r
+SCSI_Noise__3__SLW EQU CYREG_PRT6_SLW\r
+SCSI_Noise__4__AG EQU CYREG_PRT6_AG\r
+SCSI_Noise__4__AMUX EQU CYREG_PRT6_AMUX\r
+SCSI_Noise__4__BIE EQU CYREG_PRT6_BIE\r
+SCSI_Noise__4__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
+SCSI_Noise__4__BYP EQU CYREG_PRT6_BYP\r
+SCSI_Noise__4__CTL EQU CYREG_PRT6_CTL\r
+SCSI_Noise__4__DM0 EQU CYREG_PRT6_DM0\r
+SCSI_Noise__4__DM1 EQU CYREG_PRT6_DM1\r
+SCSI_Noise__4__DM2 EQU CYREG_PRT6_DM2\r
+SCSI_Noise__4__DR EQU CYREG_PRT6_DR\r
+SCSI_Noise__4__INP_DIS EQU CYREG_PRT6_INP_DIS\r
+SCSI_Noise__4__INTTYPE EQU CYREG_PICU6_INTTYPE5\r
+SCSI_Noise__4__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
+SCSI_Noise__4__LCD_EN EQU CYREG_PRT6_LCD_EN\r
+SCSI_Noise__4__MASK EQU 0x20\r
+SCSI_Noise__4__PC EQU CYREG_PRT6_PC5\r
+SCSI_Noise__4__PORT EQU 6\r
+SCSI_Noise__4__PRT EQU CYREG_PRT6_PRT\r
+SCSI_Noise__4__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
+SCSI_Noise__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
+SCSI_Noise__4__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
+SCSI_Noise__4__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
+SCSI_Noise__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
+SCSI_Noise__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
+SCSI_Noise__4__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
+SCSI_Noise__4__PS EQU CYREG_PRT6_PS\r
+SCSI_Noise__4__SHIFT EQU 5\r
+SCSI_Noise__4__SLW EQU CYREG_PRT6_SLW\r
+SCSI_Noise__ACK__AG EQU CYREG_PRT6_AG\r
+SCSI_Noise__ACK__AMUX EQU CYREG_PRT6_AMUX\r
+SCSI_Noise__ACK__BIE EQU CYREG_PRT6_BIE\r
+SCSI_Noise__ACK__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
+SCSI_Noise__ACK__BYP EQU CYREG_PRT6_BYP\r
+SCSI_Noise__ACK__CTL EQU CYREG_PRT6_CTL\r
+SCSI_Noise__ACK__DM0 EQU CYREG_PRT6_DM0\r
+SCSI_Noise__ACK__DM1 EQU CYREG_PRT6_DM1\r
+SCSI_Noise__ACK__DM2 EQU CYREG_PRT6_DM2\r
+SCSI_Noise__ACK__DR EQU CYREG_PRT6_DR\r
+SCSI_Noise__ACK__INP_DIS EQU CYREG_PRT6_INP_DIS\r
+SCSI_Noise__ACK__INTTYPE EQU CYREG_PICU6_INTTYPE5\r
+SCSI_Noise__ACK__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
+SCSI_Noise__ACK__LCD_EN EQU CYREG_PRT6_LCD_EN\r
+SCSI_Noise__ACK__MASK EQU 0x20\r
+SCSI_Noise__ACK__PC EQU CYREG_PRT6_PC5\r
+SCSI_Noise__ACK__PORT EQU 6\r
+SCSI_Noise__ACK__PRT EQU CYREG_PRT6_PRT\r
+SCSI_Noise__ACK__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
+SCSI_Noise__ACK__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
+SCSI_Noise__ACK__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
+SCSI_Noise__ACK__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
+SCSI_Noise__ACK__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
+SCSI_Noise__ACK__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
+SCSI_Noise__ACK__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
+SCSI_Noise__ACK__PS EQU CYREG_PRT6_PS\r
+SCSI_Noise__ACK__SHIFT EQU 5\r
+SCSI_Noise__ACK__SLW EQU CYREG_PRT6_SLW\r
+SCSI_Noise__ATN__AG EQU CYREG_PRT12_AG\r
+SCSI_Noise__ATN__BIE EQU CYREG_PRT12_BIE\r
+SCSI_Noise__ATN__BIT_MASK EQU CYREG_PRT12_BIT_MASK\r
+SCSI_Noise__ATN__BYP EQU CYREG_PRT12_BYP\r
+SCSI_Noise__ATN__DM0 EQU CYREG_PRT12_DM0\r
+SCSI_Noise__ATN__DM1 EQU CYREG_PRT12_DM1\r
+SCSI_Noise__ATN__DM2 EQU CYREG_PRT12_DM2\r
+SCSI_Noise__ATN__DR EQU CYREG_PRT12_DR\r
+SCSI_Noise__ATN__INP_DIS EQU CYREG_PRT12_INP_DIS\r
+SCSI_Noise__ATN__INTTYPE EQU CYREG_PICU12_INTTYPE5\r
+SCSI_Noise__ATN__MASK EQU 0x20\r
+SCSI_Noise__ATN__PC EQU CYREG_PRT12_PC5\r
+SCSI_Noise__ATN__PORT EQU 12\r
+SCSI_Noise__ATN__PRT EQU CYREG_PRT12_PRT\r
+SCSI_Noise__ATN__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN\r
+SCSI_Noise__ATN__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0\r
+SCSI_Noise__ATN__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1\r
+SCSI_Noise__ATN__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0\r
+SCSI_Noise__ATN__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1\r
+SCSI_Noise__ATN__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT\r
+SCSI_Noise__ATN__PS EQU CYREG_PRT12_PS\r
+SCSI_Noise__ATN__SHIFT EQU 5\r
+SCSI_Noise__ATN__SIO_CFG EQU CYREG_PRT12_SIO_CFG\r
+SCSI_Noise__ATN__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF\r
+SCSI_Noise__ATN__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN\r
+SCSI_Noise__ATN__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ\r
+SCSI_Noise__ATN__SLW EQU CYREG_PRT12_SLW\r
+SCSI_Noise__BSY__AG EQU CYREG_PRT6_AG\r
+SCSI_Noise__BSY__AMUX EQU CYREG_PRT6_AMUX\r
+SCSI_Noise__BSY__BIE EQU CYREG_PRT6_BIE\r
+SCSI_Noise__BSY__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
+SCSI_Noise__BSY__BYP EQU CYREG_PRT6_BYP\r
+SCSI_Noise__BSY__CTL EQU CYREG_PRT6_CTL\r
+SCSI_Noise__BSY__DM0 EQU CYREG_PRT6_DM0\r
+SCSI_Noise__BSY__DM1 EQU CYREG_PRT6_DM1\r
+SCSI_Noise__BSY__DM2 EQU CYREG_PRT6_DM2\r
+SCSI_Noise__BSY__DR EQU CYREG_PRT6_DR\r
+SCSI_Noise__BSY__INP_DIS EQU CYREG_PRT6_INP_DIS\r
+SCSI_Noise__BSY__INTTYPE EQU CYREG_PICU6_INTTYPE4\r
+SCSI_Noise__BSY__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
+SCSI_Noise__BSY__LCD_EN EQU CYREG_PRT6_LCD_EN\r
+SCSI_Noise__BSY__MASK EQU 0x10\r
+SCSI_Noise__BSY__PC EQU CYREG_PRT6_PC4\r
+SCSI_Noise__BSY__PORT EQU 6\r
+SCSI_Noise__BSY__PRT EQU CYREG_PRT6_PRT\r
+SCSI_Noise__BSY__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
+SCSI_Noise__BSY__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
+SCSI_Noise__BSY__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
+SCSI_Noise__BSY__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
+SCSI_Noise__BSY__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
+SCSI_Noise__BSY__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
+SCSI_Noise__BSY__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
+SCSI_Noise__BSY__PS EQU CYREG_PRT6_PS\r
+SCSI_Noise__BSY__SHIFT EQU 4\r
+SCSI_Noise__BSY__SLW EQU CYREG_PRT6_SLW\r
+SCSI_Noise__RST__AG EQU CYREG_PRT6_AG\r
+SCSI_Noise__RST__AMUX EQU CYREG_PRT6_AMUX\r
+SCSI_Noise__RST__BIE EQU CYREG_PRT6_BIE\r
+SCSI_Noise__RST__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
+SCSI_Noise__RST__BYP EQU CYREG_PRT6_BYP\r
+SCSI_Noise__RST__CTL EQU CYREG_PRT6_CTL\r
+SCSI_Noise__RST__DM0 EQU CYREG_PRT6_DM0\r
+SCSI_Noise__RST__DM1 EQU CYREG_PRT6_DM1\r
+SCSI_Noise__RST__DM2 EQU CYREG_PRT6_DM2\r
+SCSI_Noise__RST__DR EQU CYREG_PRT6_DR\r
+SCSI_Noise__RST__INP_DIS EQU CYREG_PRT6_INP_DIS\r
+SCSI_Noise__RST__INTTYPE EQU CYREG_PICU6_INTTYPE6\r
+SCSI_Noise__RST__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
+SCSI_Noise__RST__LCD_EN EQU CYREG_PRT6_LCD_EN\r
+SCSI_Noise__RST__MASK EQU 0x40\r
+SCSI_Noise__RST__PC EQU CYREG_PRT6_PC6\r
+SCSI_Noise__RST__PORT EQU 6\r
+SCSI_Noise__RST__PRT EQU CYREG_PRT6_PRT\r
+SCSI_Noise__RST__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
+SCSI_Noise__RST__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
+SCSI_Noise__RST__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
+SCSI_Noise__RST__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
+SCSI_Noise__RST__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
+SCSI_Noise__RST__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
+SCSI_Noise__RST__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
+SCSI_Noise__RST__PS EQU CYREG_PRT6_PS\r
+SCSI_Noise__RST__SHIFT EQU 6\r
+SCSI_Noise__RST__SLW EQU CYREG_PRT6_SLW\r
+SCSI_Noise__SEL__AG EQU CYREG_PRT5_AG\r
+SCSI_Noise__SEL__AMUX EQU CYREG_PRT5_AMUX\r
+SCSI_Noise__SEL__BIE EQU CYREG_PRT5_BIE\r
+SCSI_Noise__SEL__BIT_MASK EQU CYREG_PRT5_BIT_MASK\r
+SCSI_Noise__SEL__BYP EQU CYREG_PRT5_BYP\r
+SCSI_Noise__SEL__CTL EQU CYREG_PRT5_CTL\r
+SCSI_Noise__SEL__DM0 EQU CYREG_PRT5_DM0\r
+SCSI_Noise__SEL__DM1 EQU CYREG_PRT5_DM1\r
+SCSI_Noise__SEL__DM2 EQU CYREG_PRT5_DM2\r
+SCSI_Noise__SEL__DR EQU CYREG_PRT5_DR\r
+SCSI_Noise__SEL__INP_DIS EQU CYREG_PRT5_INP_DIS\r
+SCSI_Noise__SEL__INTTYPE EQU CYREG_PICU5_INTTYPE0\r
+SCSI_Noise__SEL__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG\r
+SCSI_Noise__SEL__LCD_EN EQU CYREG_PRT5_LCD_EN\r
+SCSI_Noise__SEL__MASK EQU 0x01\r
+SCSI_Noise__SEL__PC EQU CYREG_PRT5_PC0\r
+SCSI_Noise__SEL__PORT EQU 5\r
+SCSI_Noise__SEL__PRT EQU CYREG_PRT5_PRT\r
+SCSI_Noise__SEL__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL\r
+SCSI_Noise__SEL__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN\r
+SCSI_Noise__SEL__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0\r
+SCSI_Noise__SEL__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1\r
+SCSI_Noise__SEL__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0\r
+SCSI_Noise__SEL__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1\r
+SCSI_Noise__SEL__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT\r
+SCSI_Noise__SEL__PS EQU CYREG_PRT5_PS\r
+SCSI_Noise__SEL__SHIFT EQU 0\r
+SCSI_Noise__SEL__SLW EQU CYREG_PRT5_SLW\r
+\r
; scsiTarget\r
scsiTarget_datapath__16BIT_A0_REG EQU CYREG_B0_UDB00_01_A0\r
scsiTarget_datapath__16BIT_A1_REG EQU CYREG_B0_UDB00_01_A1\r
scsiTarget_StatusReg__STATUS_CONTROL_REG EQU CYREG_B0_UDB07_ST_CTL\r
scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB07_ST\r
\r
+; Debug_Timer\r
+Debug_Timer_Interrupt__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
+Debug_Timer_Interrupt__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
+Debug_Timer_Interrupt__INTC_MASK EQU 0x01\r
+Debug_Timer_Interrupt__INTC_NUMBER EQU 0\r
+Debug_Timer_Interrupt__INTC_PRIOR_NUM EQU 7\r
+Debug_Timer_Interrupt__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_0\r
+Debug_Timer_Interrupt__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
+Debug_Timer_Interrupt__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
+Debug_Timer_TimerHW__CAP0 EQU CYREG_TMR0_CAP0\r
+Debug_Timer_TimerHW__CAP1 EQU CYREG_TMR0_CAP1\r
+Debug_Timer_TimerHW__CFG0 EQU CYREG_TMR0_CFG0\r
+Debug_Timer_TimerHW__CFG1 EQU CYREG_TMR0_CFG1\r
+Debug_Timer_TimerHW__CFG2 EQU CYREG_TMR0_CFG2\r
+Debug_Timer_TimerHW__CNT_CMP0 EQU CYREG_TMR0_CNT_CMP0\r
+Debug_Timer_TimerHW__CNT_CMP1 EQU CYREG_TMR0_CNT_CMP1\r
+Debug_Timer_TimerHW__PER0 EQU CYREG_TMR0_PER0\r
+Debug_Timer_TimerHW__PER1 EQU CYREG_TMR0_PER1\r
+Debug_Timer_TimerHW__PM_ACT_CFG EQU CYREG_PM_ACT_CFG3\r
+Debug_Timer_TimerHW__PM_ACT_MSK EQU 0x01\r
+Debug_Timer_TimerHW__PM_STBY_CFG EQU CYREG_PM_STBY_CFG3\r
+Debug_Timer_TimerHW__PM_STBY_MSK EQU 0x01\r
+Debug_Timer_TimerHW__RT0 EQU CYREG_TMR0_RT0\r
+Debug_Timer_TimerHW__RT1 EQU CYREG_TMR0_RT1\r
+Debug_Timer_TimerHW__SR0 EQU CYREG_TMR0_SR0\r
+\r
+; SCSI_RX_DMA\r
+SCSI_RX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0\r
+SCSI_RX_DMA__DRQ_NUMBER EQU 0\r
+SCSI_RX_DMA__NUMBEROF_TDS EQU 0\r
+SCSI_RX_DMA__PRIORITY EQU 2\r
+SCSI_RX_DMA__TERMIN_EN EQU 0\r
+SCSI_RX_DMA__TERMIN_SEL EQU 0\r
+SCSI_RX_DMA__TERMOUT0_EN EQU 1\r
+SCSI_RX_DMA__TERMOUT0_SEL EQU 0\r
+SCSI_RX_DMA__TERMOUT1_EN EQU 0\r
+SCSI_RX_DMA__TERMOUT1_SEL EQU 0\r
+SCSI_RX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
+SCSI_RX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
+SCSI_RX_DMA_COMPLETE__INTC_MASK EQU 0x04\r
+SCSI_RX_DMA_COMPLETE__INTC_NUMBER EQU 2\r
+SCSI_RX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7\r
+SCSI_RX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_2\r
+SCSI_RX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
+SCSI_RX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
+\r
+; SCSI_TX_DMA\r
+SCSI_TX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0\r
+SCSI_TX_DMA__DRQ_NUMBER EQU 1\r
+SCSI_TX_DMA__NUMBEROF_TDS EQU 0\r
+SCSI_TX_DMA__PRIORITY EQU 2\r
+SCSI_TX_DMA__TERMIN_EN EQU 0\r
+SCSI_TX_DMA__TERMIN_SEL EQU 0\r
+SCSI_TX_DMA__TERMOUT0_EN EQU 1\r
+SCSI_TX_DMA__TERMOUT0_SEL EQU 1\r
+SCSI_TX_DMA__TERMOUT1_EN EQU 0\r
+SCSI_TX_DMA__TERMOUT1_SEL EQU 0\r
+SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
+SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
+SCSI_TX_DMA_COMPLETE__INTC_MASK EQU 0x10\r
+SCSI_TX_DMA_COMPLETE__INTC_NUMBER EQU 4\r
+SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7\r
+SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_4\r
+SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
+SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
+\r
+; SD_Data_Clk\r
+SD_Data_Clk__CFG0 EQU CYREG_CLKDIST_DCFG0_CFG0\r
+SD_Data_Clk__CFG1 EQU CYREG_CLKDIST_DCFG0_CFG1\r
+SD_Data_Clk__CFG2 EQU CYREG_CLKDIST_DCFG0_CFG2\r
+SD_Data_Clk__CFG2_SRC_SEL_MASK EQU 0x07\r
+SD_Data_Clk__INDEX EQU 0x00\r
+SD_Data_Clk__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2\r
+SD_Data_Clk__PM_ACT_MSK EQU 0x01\r
+SD_Data_Clk__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2\r
+SD_Data_Clk__PM_STBY_MSK EQU 0x01\r
+\r
; timer_clock\r
timer_clock__CFG0 EQU CYREG_CLKDIST_DCFG2_CFG0\r
timer_clock__CFG1 EQU CYREG_CLKDIST_DCFG2_CFG1\r
timer_clock__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2\r
timer_clock__PM_STBY_MSK EQU 0x04\r
\r
+; SCSI_RST_ISR\r
+SCSI_RST_ISR__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
+SCSI_RST_ISR__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
+SCSI_RST_ISR__INTC_MASK EQU 0x02\r
+SCSI_RST_ISR__INTC_NUMBER EQU 1\r
+SCSI_RST_ISR__INTC_PRIOR_NUM EQU 7\r
+SCSI_RST_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_1\r
+SCSI_RST_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
+SCSI_RST_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
+\r
+; SCSI_SEL_ISR\r
+SCSI_SEL_ISR__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
+SCSI_SEL_ISR__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
+SCSI_SEL_ISR__INTC_MASK EQU 0x08\r
+SCSI_SEL_ISR__INTC_NUMBER EQU 3\r
+SCSI_SEL_ISR__INTC_PRIOR_NUM EQU 7\r
+SCSI_SEL_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_3\r
+SCSI_SEL_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
+SCSI_SEL_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
+\r
+; SCSI_Filtered\r
+SCSI_Filtered_sts_sts_reg__0__MASK EQU 0x01\r
+SCSI_Filtered_sts_sts_reg__0__POS EQU 0\r
+SCSI_Filtered_sts_sts_reg__1__MASK EQU 0x02\r
+SCSI_Filtered_sts_sts_reg__1__POS EQU 1\r
+SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL\r
+SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB02_03_ST\r
+SCSI_Filtered_sts_sts_reg__2__MASK EQU 0x04\r
+SCSI_Filtered_sts_sts_reg__2__POS EQU 2\r
+SCSI_Filtered_sts_sts_reg__3__MASK EQU 0x08\r
+SCSI_Filtered_sts_sts_reg__3__POS EQU 3\r
+SCSI_Filtered_sts_sts_reg__4__MASK EQU 0x10\r
+SCSI_Filtered_sts_sts_reg__4__POS EQU 4\r
+SCSI_Filtered_sts_sts_reg__MASK EQU 0x1F\r
+SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB02_MSK\r
+SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL\r
+SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB02_ST\r
+\r
+; SCSI_CTL_PHASE\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS EQU 0\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK EQU 0x02\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS EQU 1\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB05_06_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB05_06_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB05_06_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB05_06_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK EQU 0x04\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS EQU 2\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB05_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB05_ST_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB05_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB05_ST_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__MASK EQU 0x07\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB05_MSK\r
+\r
+; SCSI_Glitch_Ctl\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS EQU 0\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB07_08_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB07_08_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB07_08_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB07_08_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB07_08_MSK\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB07_08_MSK\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB07_08_MSK\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB07_08_MSK\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB07_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB07_ST_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB07_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB07_ST_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK EQU 0x01\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB07_MSK\r
+\r
+; SCSI_Parity_Error\r
+SCSI_Parity_Error_sts_sts_reg__0__MASK EQU 0x01\r
+SCSI_Parity_Error_sts_sts_reg__0__POS EQU 0\r
+SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB01_02_ACTL\r
+SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB01_02_ST\r
+SCSI_Parity_Error_sts_sts_reg__MASK EQU 0x01\r
+SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB01_MSK\r
+SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB01_ACTL\r
+SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB01_ST\r
+\r
; Miscellaneous\r
BCLK__BUS_CLK__HZ EQU 50000000\r
BCLK__BUS_CLK__KHZ EQU 50000\r
BCLK__BUS_CLK__MHZ EQU 50\r
CYDEV_CHIP_DIE_LEOPARD EQU 1\r
-CYDEV_CHIP_DIE_PSOC4A EQU 16\r
+CYDEV_CHIP_DIE_PSOC4A EQU 18\r
CYDEV_CHIP_DIE_PSOC5LP EQU 2\r
CYDEV_CHIP_DIE_PSOC5TM EQU 3\r
CYDEV_CHIP_DIE_TMA4 EQU 4\r
CYDEV_CHIP_FAMILY_USED EQU CYDEV_CHIP_FAMILY_PSOC5\r
CYDEV_CHIP_JTAG_ID EQU 0x2E133069\r
CYDEV_CHIP_MEMBER_3A EQU 1\r
-CYDEV_CHIP_MEMBER_4A EQU 16\r
-CYDEV_CHIP_MEMBER_4D EQU 12\r
+CYDEV_CHIP_MEMBER_4A EQU 18\r
+CYDEV_CHIP_MEMBER_4D EQU 13\r
CYDEV_CHIP_MEMBER_4E EQU 6\r
-CYDEV_CHIP_MEMBER_4F EQU 17\r
+CYDEV_CHIP_MEMBER_4F EQU 19\r
CYDEV_CHIP_MEMBER_4G EQU 4\r
-CYDEV_CHIP_MEMBER_4H EQU 15\r
-CYDEV_CHIP_MEMBER_4I EQU 21\r
-CYDEV_CHIP_MEMBER_4J EQU 13\r
-CYDEV_CHIP_MEMBER_4K EQU 14\r
-CYDEV_CHIP_MEMBER_4L EQU 20\r
-CYDEV_CHIP_MEMBER_4M EQU 19\r
-CYDEV_CHIP_MEMBER_4N EQU 9\r
+CYDEV_CHIP_MEMBER_4H EQU 17\r
+CYDEV_CHIP_MEMBER_4I EQU 23\r
+CYDEV_CHIP_MEMBER_4J EQU 14\r
+CYDEV_CHIP_MEMBER_4K EQU 15\r
+CYDEV_CHIP_MEMBER_4L EQU 22\r
+CYDEV_CHIP_MEMBER_4M EQU 21\r
+CYDEV_CHIP_MEMBER_4N EQU 10\r
CYDEV_CHIP_MEMBER_4O EQU 7\r
-CYDEV_CHIP_MEMBER_4P EQU 18\r
-CYDEV_CHIP_MEMBER_4Q EQU 11\r
+CYDEV_CHIP_MEMBER_4P EQU 20\r
+CYDEV_CHIP_MEMBER_4Q EQU 12\r
CYDEV_CHIP_MEMBER_4R EQU 8\r
-CYDEV_CHIP_MEMBER_4S EQU 10\r
+CYDEV_CHIP_MEMBER_4S EQU 11\r
+CYDEV_CHIP_MEMBER_4T EQU 9\r
CYDEV_CHIP_MEMBER_4U EQU 5\r
+CYDEV_CHIP_MEMBER_4V EQU 16\r
CYDEV_CHIP_MEMBER_5A EQU 3\r
CYDEV_CHIP_MEMBER_5B EQU 2\r
-CYDEV_CHIP_MEMBER_6A EQU 22\r
-CYDEV_CHIP_MEMBER_FM3 EQU 26\r
-CYDEV_CHIP_MEMBER_FM4 EQU 27\r
-CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE1 EQU 23\r
-CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE2 EQU 24\r
-CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE3 EQU 25\r
+CYDEV_CHIP_MEMBER_6A EQU 24\r
+CYDEV_CHIP_MEMBER_FM3 EQU 28\r
+CYDEV_CHIP_MEMBER_FM4 EQU 29\r
+CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE1 EQU 25\r
+CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE2 EQU 26\r
+CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE3 EQU 27\r
CYDEV_CHIP_MEMBER_UNKNOWN EQU 0\r
CYDEV_CHIP_MEMBER_USED EQU CYDEV_CHIP_MEMBER_5B\r
CYDEV_CHIP_DIE_EXPECT EQU CYDEV_CHIP_MEMBER_USED\r
CYDEV_CHIP_REVISION_4A_ES0 EQU 17\r
CYDEV_CHIP_REVISION_4A_PRODUCTION EQU 17\r
CYDEV_CHIP_REVISION_4D_PRODUCTION EQU 0\r
+CYDEV_CHIP_REVISION_4E_CCG2_NO_USBPD EQU 0\r
CYDEV_CHIP_REVISION_4E_PRODUCTION EQU 0\r
CYDEV_CHIP_REVISION_4F_PRODUCTION EQU 0\r
CYDEV_CHIP_REVISION_4F_PRODUCTION_256DMA EQU 0\r
CYDEV_CHIP_REVISION_4Q_PRODUCTION EQU 0\r
CYDEV_CHIP_REVISION_4R_PRODUCTION EQU 0\r
CYDEV_CHIP_REVISION_4S_PRODUCTION EQU 0\r
+CYDEV_CHIP_REVISION_4T_PRODUCTION EQU 0\r
CYDEV_CHIP_REVISION_4U_PRODUCTION EQU 0\r
+CYDEV_CHIP_REVISION_4V_PRODUCTION EQU 0\r
CYDEV_CHIP_REVISION_5A_ES0 EQU 0\r
CYDEV_CHIP_REVISION_5A_ES1 EQU 1\r
CYDEV_CHIP_REVISION_5A_PRODUCTION EQU 1\r
CYDEV_CHIP_REVISION_5B_ES0 EQU 0\r
CYDEV_CHIP_REVISION_5B_PRODUCTION EQU 0\r
-CYDEV_CHIP_REVISION_6A_NO_UDB EQU 0\r
-CYDEV_CHIP_REVISION_6A_PRODUCTION EQU 0\r
+CYDEV_CHIP_REVISION_6A_ES EQU 17\r
+CYDEV_CHIP_REVISION_6A_NO_UDB EQU 33\r
+CYDEV_CHIP_REVISION_6A_PRODUCTION EQU 33\r
CYDEV_CHIP_REVISION_FM3_PRODUCTION EQU 0\r
CYDEV_CHIP_REVISION_FM4_PRODUCTION EQU 0\r
CYDEV_CHIP_REVISION_PDL_FM0P_TYPE1_PRODUCTION EQU 0\r
/*******************************************************************************\r
* File Name: cymetadata.c\r
* \r
-* PSoC Creator 4.1\r
+* PSoC Creator 4.2\r
*\r
* Description:\r
* This file defines all extra memory spaces that need to be included.\r
* This file is automatically generated by PSoC Creator.\r
*\r
********************************************************************************\r
-* Copyright (c) 2007-2017 Cypress Semiconductor. All rights reserved.\r
+* Copyright (c) 2007-2018 Cypress Semiconductor. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions, \r
* disclaimers, and limitations in the end user license agreement accompanying \r
* the software package with which this file was provided.\r
/*******************************************************************************\r
* File Name: project.h\r
* \r
-* PSoC Creator 4.1\r
+* PSoC Creator 4.2\r
*\r
* Description:\r
* It contains references to all generated header files and should not be modified.\r
* This file is automatically generated by PSoC Creator.\r
*\r
********************************************************************************\r
-* Copyright (c) 2007-2017 Cypress Semiconductor. All rights reserved.\r
+* Copyright (c) 2007-2018 Cypress Semiconductor. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions, \r
* disclaimers, and limitations in the end user license agreement accompanying \r
* the software package with which this file was provided.\r
#include "cyPm.h"\r
#include "CySpc.h"\r
#include "cytypes.h"\r
+#include "cy_em_eeprom.h"\r
\r
/*[]*/\r
\r
<?xml version="1.0" encoding="utf-8"?>\r
<blockRegMap version="1" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://cypress.com/xsd/cyblockregmap cyblockregmap.xsd" xmlns="http://cypress.com/xsd/cyblockregmap">\r
+ <block name="SD_TX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
<block name="SD_RX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
<block name="SD_TX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
- <block name="SD_RX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
+ <block name="SCSI_Parity_Error" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">\r
+ <register name="SCSI_Parity_Error_STATUS_REG" address="0x40006461" bitWidth="8" desc="" hidden="false" />\r
+ <register name="SCSI_Parity_Error_MASK_REG" address="0x40006481" bitWidth="8" desc="" hidden="false" />\r
+ <register name="SCSI_Parity_Error_STATUS_AUX_CTL_REG" address="0x40006491" bitWidth="8" desc="" hidden="false">\r
+ <field name="FIFO0" from="5" to="5" access="RW" resetVal="" desc="FIFO0 clear" hidden="false">\r
+ <value name="ENABLED" value="1" desc="Enable counter" />\r
+ <value name="DISABLED" value="0" desc="Disable counter" />\r
+ </field>\r
+ <field name="INTRENBL" from="4" to="4" access="RW" resetVal="" desc="Enables or disables the Interrupt" hidden="false">\r
+ <value name="ENABLED" value="1" desc="Interrupt enabled" />\r
+ <value name="DISABLED" value="0" desc="Interrupt disabled" />\r
+ </field>\r
+ <field name="FIFO1LEVEL" from="3" to="3" access="RW" resetVal="" desc="FIFO level" hidden="false">\r
+ <value name="ENABLED" value="1" desc="FIFO LVL: input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full" />\r
+ <value name="DISABLED" value="0" desc="FIFO LVL: input mode: FIFO not full; output mode: FIFO not empty" />\r
+ </field>\r
+ <field name="FIFO0LEVEL" from="2" to="2" access="RW" resetVal="" desc="FIFO level" hidden="false">\r
+ <value name="ENABLED" value="1" desc="FIFO LVL: input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full" />\r
+ <value name="DISABLED" value="0" desc="FIFO LVL: input mode: FIFO not full; output mode: FIFO not empty" />\r
+ </field>\r
+ <field name="FIFO1CLEAR" from="1" to="1" access="RW" resetVal="" desc="FIFO clear" hidden="false">\r
+ <value name="ENABLED" value="1" desc="Clear FIFO state" />\r
+ <value name="DISABLED" value="0" desc="Normal FIFO operation" />\r
+ </field>\r
+ <field name="FIFO0CLEAR" from="0" to="0" access="RW" resetVal="" desc="FIFO clear" hidden="false">\r
+ <value name="ENABLED" value="1" desc="Clear FIFO state" />\r
+ <value name="DISABLED" value="0" desc="Normal FIFO operation" />\r
+ </field>\r
+ </register>\r
+ </block>\r
<block name="SCSI_RX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
<block name="SCSI_RX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
- <block name="SD_TX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
- <block name="SCSI_TX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
+ <block name="SD_RX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
+ <block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
<block name="timer_clock" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
<block name="Debug_Timer" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">\r
<block name="VirtualMux_2" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
<register name="Debug_Timer_PERIOD" address="0x40004F04" bitWidth="16" desc="TMRx.PER0 - Assigned Period" hidden="false" />\r
<register name="Debug_Timer_COUNTER" address="0x40004F06" bitWidth="16" desc="TMRx.CNT_CMP0 - Current Down Counter Value" hidden="false" />\r
</block>\r
- <block name="SCSI_Out_Ctl" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">\r
- <register name="SCSI_Out_Ctl_CONTROL_REG" address="0x40006478" bitWidth="8" desc="" hidden="false" />\r
- </block>\r
+ <block name="SCSI_TX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
<block name="SCSI_TX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
<block name="Debug_Timer_Interrupt" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
- <block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
+ <block name="mux_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
<block name="not_2" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
<block name="Clock_4" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
- <block name="cydff_2" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
+ <block name="Em_EEPROM_Dynamic" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
<block name="cy_boot" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
<block name="SCSI_Glitch_Ctl" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">\r
<register name="SCSI_Glitch_Ctl_CONTROL_REG" address="0x40006477" bitWidth="8" desc="" hidden="false" />\r
</block>\r
- <block name="mux_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
- <block name="SCSI_SEL_ISR" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
+ <block name="cydff_2" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
+ <block name="cy_constant_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
<block name="GlitchFilter_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
<block name="SCSI_Filtered" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">\r
<register name="SCSI_Filtered_STATUS_REG" address="0x40006462" bitWidth="8" desc="" hidden="false" />\r
</field>\r
</register>\r
</block>\r
- <block name="SCSI_Parity_Error" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">\r
- <register name="SCSI_Parity_Error_STATUS_REG" address="0x40006461" bitWidth="8" desc="" hidden="false" />\r
- <register name="SCSI_Parity_Error_MASK_REG" address="0x40006481" bitWidth="8" desc="" hidden="false" />\r
- <register name="SCSI_Parity_Error_STATUS_AUX_CTL_REG" address="0x40006491" bitWidth="8" desc="" hidden="false">\r
- <field name="FIFO0" from="5" to="5" access="RW" resetVal="" desc="FIFO0 clear" hidden="false">\r
- <value name="ENABLED" value="1" desc="Enable counter" />\r
- <value name="DISABLED" value="0" desc="Disable counter" />\r
- </field>\r
- <field name="INTRENBL" from="4" to="4" access="RW" resetVal="" desc="Enables or disables the Interrupt" hidden="false">\r
- <value name="ENABLED" value="1" desc="Interrupt enabled" />\r
- <value name="DISABLED" value="0" desc="Interrupt disabled" />\r
- </field>\r
- <field name="FIFO1LEVEL" from="3" to="3" access="RW" resetVal="" desc="FIFO level" hidden="false">\r
- <value name="ENABLED" value="1" desc="FIFO LVL: input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full" />\r
- <value name="DISABLED" value="0" desc="FIFO LVL: input mode: FIFO not full; output mode: FIFO not empty" />\r
- </field>\r
- <field name="FIFO0LEVEL" from="2" to="2" access="RW" resetVal="" desc="FIFO level" hidden="false">\r
- <value name="ENABLED" value="1" desc="FIFO LVL: input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full" />\r
- <value name="DISABLED" value="0" desc="FIFO LVL: input mode: FIFO not full; output mode: FIFO not empty" />\r
- </field>\r
- <field name="FIFO1CLEAR" from="1" to="1" access="RW" resetVal="" desc="FIFO clear" hidden="false">\r
- <value name="ENABLED" value="1" desc="Clear FIFO state" />\r
- <value name="DISABLED" value="0" desc="Normal FIFO operation" />\r
- </field>\r
- <field name="FIFO0CLEAR" from="0" to="0" access="RW" resetVal="" desc="FIFO clear" hidden="false">\r
- <value name="ENABLED" value="1" desc="Clear FIFO state" />\r
- <value name="DISABLED" value="0" desc="Normal FIFO operation" />\r
- </field>\r
- </register>\r
- </block>\r
+ <block name="SCSI_SEL_ISR" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
<block name="Clock_3" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
<block name="cydff_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
- <block name="cy_constant_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
+ <block name="SCSI_Out_Ctl" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">\r
+ <register name="SCSI_Out_Ctl_CONTROL_REG" address="0x40006478" bitWidth="8" desc="" hidden="false" />\r
+ </block>\r
<block name="SCSI_Out" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
<block name="SCSI_In" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
<block name="OddParityGen_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
<Group key="Component">\r
<Group key="v1">\r
<Data key="cy_boot" value="cy_boot_v5_50" />\r
+ <Data key="Em_EEPROM_Dynamic" value="Em_EEPROM_Dynamic_v2_0" />\r
<Data key="LIN_Dynamic" value="LIN_Dynamic_v3_40" />\r
</Group>\r
</Group>\r
</Group>\r
</Group>\r
<Group key="Interrupt">\r
- <Data key="4abaf846-60a1-4cfc-b1e0-6eb532fa6a05" value="0" />\r
- <Data key="791071b3-a348-49c4-b578-64e66d701d0f/d91ea660-bc91-4817-b29b-2fe86c305500" value="6" />\r
+ <Group key="4abaf846-60a1-4cfc-b1e0-6eb532fa6a05">\r
+ <Group key="CortexM3">\r
+ <Data key="Assigned" value="True" />\r
+ <Data key="Priority" value="0" />\r
+ <Data key="Vector" value="-1" />\r
+ </Group>\r
+ </Group>\r
+ <Group key="791071b3-a348-49c4-b578-64e66d701d0f/d91ea660-bc91-4817-b29b-2fe86c305500">\r
+ <Group key="CortexM3">\r
+ <Data key="Assigned" value="True" />\r
+ <Data key="Priority" value="6" />\r
+ <Data key="Vector" value="-1" />\r
+ </Group>\r
+ </Group>\r
</Group>\r
<Group key="Pin2">\r
<Group key="1bd12db2-da87-4f00-90d1-0a734e846c58">\r
<build_action v="OTHER;;;;" />\r
<PropertyDeltas />\r
</CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b>\r
+<CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFolderSerialize" version="3">\r
+<CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtBaseContainerSerialize" version="1">\r
+<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItemSerialize" version="2" name="Em_EEPROM_Dynamic" persistent="">\r
+<Hidden v="False" />\r
+</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>\r
+<CyGuid_0820c2e7-528d-4137-9a08-97257b946089 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItemListSerialize" version="2">\r
+<dependencies>\r
+<CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFileSerialize" version="3" xml_contents_version="1">\r
+<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItemSerialize" version="2" name="cy_em_eeprom.c" persistent="Generated_Source\PSoC5\cy_em_eeprom.c">\r
+<Hidden v="False" />\r
+</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>\r
+<build_action v="SOURCE_C;CortexM3;;;" />\r
+<PropertyDeltas />\r
+</CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b>\r
+<CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFileSerialize" version="3" xml_contents_version="1">\r
+<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItemSerialize" version="2" name="cy_em_eeprom.h" persistent="Generated_Source\PSoC5\cy_em_eeprom.h">\r
+<Hidden v="False" />\r
+</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>\r
+<build_action v="HEADER;;;;" />\r
+<PropertyDeltas />\r
+</CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b>\r
+</dependencies>\r
+</CyGuid_0820c2e7-528d-4137-9a08-97257b946089>\r
+</CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8>\r
+<filters />\r
+</CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0>\r
</dependencies>\r
</CyGuid_0820c2e7-528d-4137-9a08-97257b946089>\r
</CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8>\r
</platforms>\r
<project_current_platform v="c9323d49-d323-40b8-9b59-cc008d68a989" />\r
<last_selected_tab v="Cypress" />\r
-<WriteAppVersionLastSavedWith v="4.1.0.2686" />\r
-<WriteAppMarketingVersionLastSavedWith v=" 4.1" />\r
+<WriteAppVersionLastSavedWith v="4.2.0.641" />\r
+<WriteAppMarketingVersionLastSavedWith v=" 4.2" />\r
<project_id v="6e1f5cbb-a0ca-4f55-a1fa-7b20c5be3a3e" />\r
<GenerateDescriptionFiles v="False" />\r
</CyGuid_49cfd574-032a-4a64-b7be-d4eeeaf25e43>\r
<addressUnitBits>8</addressUnitBits>\r
<width>32</width>\r
<peripherals>\r
+ <peripheral>\r
+ <name>SCSI_Parity_Error</name>\r
+ <description>No description available</description>\r
+ <baseAddress>0x0</baseAddress>\r
+ <addressBlock>\r
+ <offset>0</offset>\r
+ <size>0x0</size>\r
+ <usage>registers</usage>\r
+ </addressBlock>\r
+ <registers>\r
+ <register>\r
+ <name>SCSI_Parity_Error_STATUS_REG</name>\r
+ <description>No description available</description>\r
+ <addressOffset>0x40006461</addressOffset>\r
+ <size>8</size>\r
+ <access>read-write</access>\r
+ <resetValue>0</resetValue>\r
+ <resetMask>0</resetMask>\r
+ </register>\r
+ <register>\r
+ <name>SCSI_Parity_Error_MASK_REG</name>\r
+ <description>No description available</description>\r
+ <addressOffset>0x40006481</addressOffset>\r
+ <size>8</size>\r
+ <access>read-write</access>\r
+ <resetValue>0</resetValue>\r
+ <resetMask>0</resetMask>\r
+ </register>\r
+ <register>\r
+ <name>SCSI_Parity_Error_STATUS_AUX_CTL_REG</name>\r
+ <description>No description available</description>\r
+ <addressOffset>0x40006491</addressOffset>\r
+ <size>8</size>\r
+ <access>read-write</access>\r
+ <resetValue>0</resetValue>\r
+ <resetMask>0</resetMask>\r
+ <fields>\r
+ <field>\r
+ <name>FIFO0</name>\r
+ <description>FIFO0 clear</description>\r
+ <lsb>5</lsb>\r
+ <msb>5</msb>\r
+ <access>read-write</access>\r
+ <enumeratedValues>\r
+ <enumeratedValue>\r
+ <name>ENABLED</name>\r
+ <description>Enable counter</description>\r
+ <value>1</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>DISABLED</name>\r
+ <description>Disable counter</description>\r
+ <value>0</value>\r
+ </enumeratedValue>\r
+ </enumeratedValues>\r
+ </field>\r
+ <field>\r
+ <name>INTRENBL</name>\r
+ <description>Enables or disables the Interrupt</description>\r
+ <lsb>4</lsb>\r
+ <msb>4</msb>\r
+ <access>read-write</access>\r
+ <enumeratedValues>\r
+ <enumeratedValue>\r
+ <name>ENABLED</name>\r
+ <description>Interrupt enabled</description>\r
+ <value>1</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>DISABLED</name>\r
+ <description>Interrupt disabled</description>\r
+ <value>0</value>\r
+ </enumeratedValue>\r
+ </enumeratedValues>\r
+ </field>\r
+ <field>\r
+ <name>FIFO1LEVEL</name>\r
+ <description>FIFO level</description>\r
+ <lsb>3</lsb>\r
+ <msb>3</msb>\r
+ <access>read-write</access>\r
+ <enumeratedValues>\r
+ <enumeratedValue>\r
+ <name>ENABLED</name>\r
+ <description>FIFO LVL: input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full</description>\r
+ <value>1</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>DISABLED</name>\r
+ <description>FIFO LVL: input mode: FIFO not full; output mode: FIFO not empty</description>\r
+ <value>0</value>\r
+ </enumeratedValue>\r
+ </enumeratedValues>\r
+ </field>\r
+ <field>\r
+ <name>FIFO0LEVEL</name>\r
+ <description>FIFO level</description>\r
+ <lsb>2</lsb>\r
+ <msb>2</msb>\r
+ <access>read-write</access>\r
+ <enumeratedValues>\r
+ <enumeratedValue>\r
+ <name>ENABLED</name>\r
+ <description>FIFO LVL: input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full</description>\r
+ <value>1</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>DISABLED</name>\r
+ <description>FIFO LVL: input mode: FIFO not full; output mode: FIFO not empty</description>\r
+ <value>0</value>\r
+ </enumeratedValue>\r
+ </enumeratedValues>\r
+ </field>\r
+ <field>\r
+ <name>FIFO1CLEAR</name>\r
+ <description>FIFO clear</description>\r
+ <lsb>1</lsb>\r
+ <msb>1</msb>\r
+ <access>read-write</access>\r
+ <enumeratedValues>\r
+ <enumeratedValue>\r
+ <name>ENABLED</name>\r
+ <description>Clear FIFO state</description>\r
+ <value>1</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>DISABLED</name>\r
+ <description>Normal FIFO operation</description>\r
+ <value>0</value>\r
+ </enumeratedValue>\r
+ </enumeratedValues>\r
+ </field>\r
+ <field>\r
+ <name>FIFO0CLEAR</name>\r
+ <description>FIFO clear</description>\r
+ <lsb>0</lsb>\r
+ <msb>0</msb>\r
+ <access>read-write</access>\r
+ <enumeratedValues>\r
+ <enumeratedValue>\r
+ <name>ENABLED</name>\r
+ <description>Clear FIFO state</description>\r
+ <value>1</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>DISABLED</name>\r
+ <description>Normal FIFO operation</description>\r
+ <value>0</value>\r
+ </enumeratedValue>\r
+ </enumeratedValues>\r
+ </field>\r
+ </fields>\r
+ </register>\r
+ </registers>\r
+ </peripheral>\r
<peripheral>\r
<name>Debug_Timer</name>\r
<description>No description available</description>\r
</register>\r
</registers>\r
</peripheral>\r
- <peripheral>\r
- <name>SCSI_Out_Ctl</name>\r
- <description>No description available</description>\r
- <baseAddress>0x40006478</baseAddress>\r
- <addressBlock>\r
- <offset>0</offset>\r
- <size>0x0</size>\r
- <usage>registers</usage>\r
- </addressBlock>\r
- <registers>\r
- <register>\r
- <name>SCSI_Out_Ctl_CONTROL_REG</name>\r
- <description>No description available</description>\r
- <addressOffset>0x0</addressOffset>\r
- <size>8</size>\r
- <access>read-write</access>\r
- <resetValue>0</resetValue>\r
- <resetMask>0</resetMask>\r
- </register>\r
- </registers>\r
- </peripheral>\r
<peripheral>\r
<name>SCSI_Glitch_Ctl</name>\r
<description>No description available</description>\r
- <baseAddress>0x40006477</baseAddress>\r
+ <baseAddress>0x0</baseAddress>\r
<addressBlock>\r
<offset>0</offset>\r
<size>0x0</size>\r
<register>\r
<name>SCSI_Glitch_Ctl_CONTROL_REG</name>\r
<description>No description available</description>\r
- <addressOffset>0x0</addressOffset>\r
+ <addressOffset>0x40006477</addressOffset>\r
<size>8</size>\r
<access>read-write</access>\r
<resetValue>0</resetValue>\r
<peripheral>\r
<name>SCSI_Filtered</name>\r
<description>No description available</description>\r
- <baseAddress>0x40006462</baseAddress>\r
+ <baseAddress>0x0</baseAddress>\r
<addressBlock>\r
<offset>0</offset>\r
<size>0x0</size>\r
<register>\r
<name>SCSI_Filtered_STATUS_REG</name>\r
<description>No description available</description>\r
- <addressOffset>0x0</addressOffset>\r
+ <addressOffset>0x40006462</addressOffset>\r
<size>8</size>\r
<access>read-write</access>\r
<resetValue>0</resetValue>\r
<register>\r
<name>SCSI_Filtered_MASK_REG</name>\r
<description>No description available</description>\r
- <addressOffset>0x20</addressOffset>\r
+ <addressOffset>0x40006482</addressOffset>\r
<size>8</size>\r
<access>read-write</access>\r
<resetValue>0</resetValue>\r
<register>\r
<name>SCSI_Filtered_STATUS_AUX_CTL_REG</name>\r
<description>No description available</description>\r
- <addressOffset>0x30</addressOffset>\r
+ <addressOffset>0x40006492</addressOffset>\r
<size>8</size>\r
<access>read-write</access>\r
<resetValue>0</resetValue>\r
</registers>\r
</peripheral>\r
<peripheral>\r
- <name>SCSI_Parity_Error</name>\r
+ <name>SCSI_Out_Ctl</name>\r
<description>No description available</description>\r
- <baseAddress>0x40006461</baseAddress>\r
+ <baseAddress>0x0</baseAddress>\r
<addressBlock>\r
<offset>0</offset>\r
<size>0x0</size>\r
</addressBlock>\r
<registers>\r
<register>\r
- <name>SCSI_Parity_Error_STATUS_REG</name>\r
- <description>No description available</description>\r
- <addressOffset>0x0</addressOffset>\r
- <size>8</size>\r
- <access>read-write</access>\r
- <resetValue>0</resetValue>\r
- <resetMask>0</resetMask>\r
- </register>\r
- <register>\r
- <name>SCSI_Parity_Error_MASK_REG</name>\r
- <description>No description available</description>\r
- <addressOffset>0x20</addressOffset>\r
- <size>8</size>\r
- <access>read-write</access>\r
- <resetValue>0</resetValue>\r
- <resetMask>0</resetMask>\r
- </register>\r
- <register>\r
- <name>SCSI_Parity_Error_STATUS_AUX_CTL_REG</name>\r
+ <name>SCSI_Out_Ctl_CONTROL_REG</name>\r
<description>No description available</description>\r
- <addressOffset>0x30</addressOffset>\r
+ <addressOffset>0x40006478</addressOffset>\r
<size>8</size>\r
<access>read-write</access>\r
<resetValue>0</resetValue>\r
<resetMask>0</resetMask>\r
- <fields>\r
- <field>\r
- <name>FIFO0</name>\r
- <description>FIFO0 clear</description>\r
- <lsb>5</lsb>\r
- <msb>5</msb>\r
- <access>read-write</access>\r
- <enumeratedValues>\r
- <enumeratedValue>\r
- <name>ENABLED</name>\r
- <description>Enable counter</description>\r
- <value>1</value>\r
- </enumeratedValue>\r
- <enumeratedValue>\r
- <name>DISABLED</name>\r
- <description>Disable counter</description>\r
- <value>0</value>\r
- </enumeratedValue>\r
- </enumeratedValues>\r
- </field>\r
- <field>\r
- <name>INTRENBL</name>\r
- <description>Enables or disables the Interrupt</description>\r
- <lsb>4</lsb>\r
- <msb>4</msb>\r
- <access>read-write</access>\r
- <enumeratedValues>\r
- <enumeratedValue>\r
- <name>ENABLED</name>\r
- <description>Interrupt enabled</description>\r
- <value>1</value>\r
- </enumeratedValue>\r
- <enumeratedValue>\r
- <name>DISABLED</name>\r
- <description>Interrupt disabled</description>\r
- <value>0</value>\r
- </enumeratedValue>\r
- </enumeratedValues>\r
- </field>\r
- <field>\r
- <name>FIFO1LEVEL</name>\r
- <description>FIFO level</description>\r
- <lsb>3</lsb>\r
- <msb>3</msb>\r
- <access>read-write</access>\r
- <enumeratedValues>\r
- <enumeratedValue>\r
- <name>ENABLED</name>\r
- <description>FIFO LVL: input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full</description>\r
- <value>1</value>\r
- </enumeratedValue>\r
- <enumeratedValue>\r
- <name>DISABLED</name>\r
- <description>FIFO LVL: input mode: FIFO not full; output mode: FIFO not empty</description>\r
- <value>0</value>\r
- </enumeratedValue>\r
- </enumeratedValues>\r
- </field>\r
- <field>\r
- <name>FIFO0LEVEL</name>\r
- <description>FIFO level</description>\r
- <lsb>2</lsb>\r
- <msb>2</msb>\r
- <access>read-write</access>\r
- <enumeratedValues>\r
- <enumeratedValue>\r
- <name>ENABLED</name>\r
- <description>FIFO LVL: input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full</description>\r
- <value>1</value>\r
- </enumeratedValue>\r
- <enumeratedValue>\r
- <name>DISABLED</name>\r
- <description>FIFO LVL: input mode: FIFO not full; output mode: FIFO not empty</description>\r
- <value>0</value>\r
- </enumeratedValue>\r
- </enumeratedValues>\r
- </field>\r
- <field>\r
- <name>FIFO1CLEAR</name>\r
- <description>FIFO clear</description>\r
- <lsb>1</lsb>\r
- <msb>1</msb>\r
- <access>read-write</access>\r
- <enumeratedValues>\r
- <enumeratedValue>\r
- <name>ENABLED</name>\r
- <description>Clear FIFO state</description>\r
- <value>1</value>\r
- </enumeratedValue>\r
- <enumeratedValue>\r
- <name>DISABLED</name>\r
- <description>Normal FIFO operation</description>\r
- <value>0</value>\r
- </enumeratedValue>\r
- </enumeratedValues>\r
- </field>\r
- <field>\r
- <name>FIFO0CLEAR</name>\r
- <description>FIFO clear</description>\r
- <lsb>0</lsb>\r
- <msb>0</msb>\r
- <access>read-write</access>\r
- <enumeratedValues>\r
- <enumeratedValue>\r
- <name>ENABLED</name>\r
- <description>Clear FIFO state</description>\r
- <value>1</value>\r
- </enumeratedValue>\r
- <enumeratedValue>\r
- <name>DISABLED</name>\r
- <description>Normal FIFO operation</description>\r
- <value>0</value>\r
- </enumeratedValue>\r
- </enumeratedValues>\r
- </field>\r
- </fields>\r
</register>\r
</registers>\r
</peripheral>\r
<peripheral>\r
<name>SCSI_CTL_PHASE</name>\r
<description>No description available</description>\r
- <baseAddress>0x40006475</baseAddress>\r
+ <baseAddress>0x0</baseAddress>\r
<addressBlock>\r
<offset>0</offset>\r
<size>0x0</size>\r
<register>\r
<name>SCSI_CTL_PHASE_CONTROL_REG</name>\r
<description>No description available</description>\r
- <addressOffset>0x0</addressOffset>\r
+ <addressOffset>0x40006475</addressOffset>\r
<size>8</size>\r
<access>read-write</access>\r
<resetValue>0</resetValue>\r
<peripheral>\r
<name>SCSI_Out_Bits</name>\r
<description>No description available</description>\r
- <baseAddress>0x40006578</baseAddress>\r
+ <baseAddress>0x0</baseAddress>\r
<addressBlock>\r
<offset>0</offset>\r
<size>0x0</size>\r
<register>\r
<name>SCSI_Out_Bits_CONTROL_REG</name>\r
<description>No description available</description>\r
- <addressOffset>0x0</addressOffset>\r
+ <addressOffset>0x40006578</addressOffset>\r
<size>8</size>\r
<access>read-write</access>\r
<resetValue>0</resetValue>\r
#define EXTLED__SLW CYREG_PRT0_SLW\r
\r
/* SDCard */\r
-#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB07_08_ACTL\r
-#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB07_08_CTL\r
-#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB07_08_CTL\r
-#define SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB07_08_CTL\r
-#define SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B1_UDB07_08_CTL\r
-#define SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B1_UDB07_08_MSK\r
-#define SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B1_UDB07_08_MSK\r
-#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B1_UDB07_08_MSK\r
-#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB07_08_MSK\r
-#define SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B1_UDB07_ACTL\r
-#define SDCard_BSPIM_BitCounter__CONTROL_REG CYREG_B1_UDB07_CTL\r
-#define SDCard_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B1_UDB07_ST_CTL\r
-#define SDCard_BSPIM_BitCounter__COUNT_REG CYREG_B1_UDB07_CTL\r
-#define SDCard_BSPIM_BitCounter__COUNT_ST_REG CYREG_B1_UDB07_ST_CTL\r
-#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB07_MSK_ACTL\r
-#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B1_UDB07_MSK_ACTL\r
-#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B1_UDB07_MSK\r
-#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB07_08_ACTL\r
-#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B1_UDB07_08_ST\r
-#define SDCard_BSPIM_BitCounter_ST__MASK_REG CYREG_B1_UDB07_MSK\r
-#define SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B1_UDB07_MSK_ACTL\r
-#define SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B1_UDB07_MSK_ACTL\r
-#define SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B1_UDB07_ACTL\r
-#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B1_UDB07_ST_CTL\r
-#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B1_UDB07_ST_CTL\r
-#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B1_UDB07_ST\r
-#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB04_05_ACTL\r
-#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B1_UDB04_05_ST\r
+#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB05_06_ACTL\r
+#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB05_06_CTL\r
+#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB05_06_CTL\r
+#define SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB05_06_CTL\r
+#define SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B1_UDB05_06_CTL\r
+#define SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B1_UDB05_06_MSK\r
+#define SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B1_UDB05_06_MSK\r
+#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B1_UDB05_06_MSK\r
+#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB05_06_MSK\r
+#define SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B1_UDB05_ACTL\r
+#define SDCard_BSPIM_BitCounter__CONTROL_REG CYREG_B1_UDB05_CTL\r
+#define SDCard_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B1_UDB05_ST_CTL\r
+#define SDCard_BSPIM_BitCounter__COUNT_REG CYREG_B1_UDB05_CTL\r
+#define SDCard_BSPIM_BitCounter__COUNT_ST_REG CYREG_B1_UDB05_ST_CTL\r
+#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB05_MSK_ACTL\r
+#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B1_UDB05_MSK_ACTL\r
+#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B1_UDB05_MSK\r
+#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB05_06_ACTL\r
+#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B1_UDB05_06_ST\r
+#define SDCard_BSPIM_BitCounter_ST__MASK_REG CYREG_B1_UDB05_MSK\r
+#define SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B1_UDB05_MSK_ACTL\r
+#define SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B1_UDB05_MSK_ACTL\r
+#define SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B1_UDB05_ACTL\r
+#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B1_UDB05_ST_CTL\r
+#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B1_UDB05_ST_CTL\r
+#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B1_UDB05_ST\r
+#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB07_08_ACTL\r
+#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B1_UDB07_08_ST\r
#define SDCard_BSPIM_RxStsReg__4__MASK 0x10u\r
#define SDCard_BSPIM_RxStsReg__4__POS 4\r
#define SDCard_BSPIM_RxStsReg__5__MASK 0x20u\r
#define SDCard_BSPIM_RxStsReg__6__MASK 0x40u\r
#define SDCard_BSPIM_RxStsReg__6__POS 6\r
#define SDCard_BSPIM_RxStsReg__MASK 0x70u\r
-#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B1_UDB04_MSK\r
-#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB04_ACTL\r
-#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B1_UDB04_ST\r
+#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B1_UDB07_MSK\r
+#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB07_ACTL\r
+#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B1_UDB07_ST\r
#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B1_UDB04_05_A0\r
#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B1_UDB04_05_A1\r
#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG CYREG_B1_UDB04_05_D0\r
#define SCSI_Out_Bits_Sync_ctrl_reg__0__POS 0\r
#define SCSI_Out_Bits_Sync_ctrl_reg__1__MASK 0x02u\r
#define SCSI_Out_Bits_Sync_ctrl_reg__1__POS 1\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB10_11_ACTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB10_11_CTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB10_11_CTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB10_11_CTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB10_11_CTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB10_11_MSK\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB10_11_MSK\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB10_11_MSK\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB10_11_MSK\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB14_15_ACTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB14_15_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB14_15_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB14_15_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB14_15_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB14_15_MSK\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB14_15_MSK\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB14_15_MSK\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB14_15_MSK\r
#define SCSI_Out_Bits_Sync_ctrl_reg__2__MASK 0x04u\r
#define SCSI_Out_Bits_Sync_ctrl_reg__2__POS 2\r
#define SCSI_Out_Bits_Sync_ctrl_reg__3__MASK 0x08u\r
#define SCSI_Out_Bits_Sync_ctrl_reg__6__POS 6\r
#define SCSI_Out_Bits_Sync_ctrl_reg__7__MASK 0x80u\r
#define SCSI_Out_Bits_Sync_ctrl_reg__7__POS 7\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB10_ACTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB10_CTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB10_ST_CTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB10_CTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB10_ST_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB14_ACTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB14_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB14_ST_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB14_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB14_ST_CTL\r
#define SCSI_Out_Bits_Sync_ctrl_reg__MASK 0xFFu\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB10_MSK_ACTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB10_MSK_ACTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB10_MSK\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB14_MSK_ACTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB14_MSK_ACTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB14_MSK\r
#define SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK 0x01u\r
#define SCSI_Out_Ctl_Sync_ctrl_reg__0__POS 0\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB07_08_ACTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB07_08_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB07_08_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB07_08_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB07_08_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB07_08_MSK\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB07_08_MSK\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB07_08_MSK\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB07_08_MSK\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB07_ACTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB07_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB07_ST_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB07_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB07_ST_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB12_13_ACTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB12_13_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB12_13_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB12_13_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB12_13_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB12_13_MSK\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB12_13_MSK\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB12_13_MSK\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB12_13_MSK\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB12_ACTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB12_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB12_ST_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB12_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB12_ST_CTL\r
#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK 0x01u\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB07_MSK_ACTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB07_MSK_ACTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB07_MSK\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB12_MSK\r
#define SCSI_Out_DBx__0__AG CYREG_PRT5_AG\r
#define SCSI_Out_DBx__0__AMUX CYREG_PRT5_AMUX\r
#define SCSI_Out_DBx__0__BIE CYREG_PRT5_BIE\r
#define scsiTarget_StatusReg__0__POS 0\r
#define scsiTarget_StatusReg__1__MASK 0x02u\r
#define scsiTarget_StatusReg__1__POS 1\r
-#define scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB07_08_ACTL\r
-#define scsiTarget_StatusReg__16BIT_STATUS_REG CYREG_B0_UDB07_08_ST\r
+#define scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB02_03_ACTL\r
+#define scsiTarget_StatusReg__16BIT_STATUS_REG CYREG_B0_UDB02_03_ST\r
#define scsiTarget_StatusReg__2__MASK 0x04u\r
#define scsiTarget_StatusReg__2__POS 2\r
#define scsiTarget_StatusReg__3__MASK 0x08u\r
#define scsiTarget_StatusReg__4__MASK 0x10u\r
#define scsiTarget_StatusReg__4__POS 4\r
#define scsiTarget_StatusReg__MASK 0x1Fu\r
-#define scsiTarget_StatusReg__MASK_REG CYREG_B0_UDB07_MSK\r
-#define scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG CYREG_B0_UDB07_MSK_ACTL\r
-#define scsiTarget_StatusReg__PER_ST_AUX_CTL_REG CYREG_B0_UDB07_MSK_ACTL\r
-#define scsiTarget_StatusReg__STATUS_AUX_CTL_REG CYREG_B0_UDB07_ACTL\r
-#define scsiTarget_StatusReg__STATUS_CNT_REG CYREG_B0_UDB07_ST_CTL\r
-#define scsiTarget_StatusReg__STATUS_CONTROL_REG CYREG_B0_UDB07_ST_CTL\r
-#define scsiTarget_StatusReg__STATUS_REG CYREG_B0_UDB07_ST\r
+#define scsiTarget_StatusReg__MASK_REG CYREG_B0_UDB02_MSK\r
+#define scsiTarget_StatusReg__STATUS_AUX_CTL_REG CYREG_B0_UDB02_ACTL\r
+#define scsiTarget_StatusReg__STATUS_REG CYREG_B0_UDB02_ST\r
\r
/* Debug_Timer */\r
#define Debug_Timer_Interrupt__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
#define SCSI_Filtered_sts_sts_reg__0__POS 0\r
#define SCSI_Filtered_sts_sts_reg__1__MASK 0x02u\r
#define SCSI_Filtered_sts_sts_reg__1__POS 1\r
-#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB13_14_ACTL\r
-#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB13_14_ST\r
+#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB11_12_ACTL\r
+#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB11_12_ST\r
#define SCSI_Filtered_sts_sts_reg__2__MASK 0x04u\r
#define SCSI_Filtered_sts_sts_reg__2__POS 2\r
#define SCSI_Filtered_sts_sts_reg__3__MASK 0x08u\r
#define SCSI_Filtered_sts_sts_reg__4__MASK 0x10u\r
#define SCSI_Filtered_sts_sts_reg__4__POS 4\r
#define SCSI_Filtered_sts_sts_reg__MASK 0x1Fu\r
-#define SCSI_Filtered_sts_sts_reg__MASK_REG CYREG_B0_UDB13_MSK\r
-#define SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB13_ACTL\r
-#define SCSI_Filtered_sts_sts_reg__STATUS_REG CYREG_B0_UDB13_ST\r
+#define SCSI_Filtered_sts_sts_reg__MASK_REG CYREG_B0_UDB11_MSK\r
+#define SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB11_ACTL\r
+#define SCSI_Filtered_sts_sts_reg__STATUS_REG CYREG_B0_UDB11_ST\r
\r
/* SCSI_CTL_PHASE */\r
#define SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK 0x01u\r
#define SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS 0\r
#define SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK 0x02u\r
#define SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS 1\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB02_03_ACTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB02_03_CTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB02_03_CTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB02_03_CTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB02_03_CTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB02_03_MSK\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB02_03_MSK\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB02_03_MSK\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB02_03_MSK\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB06_07_ACTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB06_07_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB06_07_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB06_07_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB06_07_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB06_07_MSK\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB06_07_MSK\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB06_07_MSK\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB06_07_MSK\r
#define SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK 0x04u\r
#define SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS 2\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB02_ACTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB02_CTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB02_ST_CTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB02_CTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB02_ST_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB06_ACTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB06_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB06_ST_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB06_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB06_ST_CTL\r
#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK 0x07u\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB02_MSK_ACTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB02_MSK_ACTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB02_MSK\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB06_MSK\r
\r
/* SCSI_Glitch_Ctl */\r
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK 0x01u\r
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS 0\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB03_04_ACTL\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB03_04_CTL\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB03_04_CTL\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB03_04_CTL\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB03_04_CTL\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB03_04_MSK\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB03_04_MSK\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB03_04_MSK\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB03_04_MSK\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB03_ACTL\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB03_CTL\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB03_ST_CTL\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB03_CTL\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB03_ST_CTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB04_05_ACTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB04_05_CTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB04_05_CTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB04_05_CTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB04_05_CTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB04_05_MSK\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB04_05_MSK\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB04_05_MSK\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB04_05_MSK\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB04_ACTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB04_CTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB04_ST_CTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB04_CTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB04_ST_CTL\r
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK 0x01u\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB03_MSK\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB04_MSK\r
\r
/* SCSI_Parity_Error */\r
#define SCSI_Parity_Error_sts_sts_reg__0__MASK 0x01u\r
#define SCSI_Parity_Error_sts_sts_reg__0__POS 0\r
-#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB11_12_ACTL\r
-#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB11_12_ST\r
+#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB05_06_ACTL\r
+#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB05_06_ST\r
#define SCSI_Parity_Error_sts_sts_reg__MASK 0x01u\r
-#define SCSI_Parity_Error_sts_sts_reg__MASK_REG CYREG_B0_UDB11_MSK\r
-#define SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB11_ACTL\r
-#define SCSI_Parity_Error_sts_sts_reg__STATUS_REG CYREG_B0_UDB11_ST\r
+#define SCSI_Parity_Error_sts_sts_reg__MASK_REG CYREG_B0_UDB05_MSK\r
+#define SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB05_ACTL\r
+#define SCSI_Parity_Error_sts_sts_reg__STATUS_REG CYREG_B0_UDB05_ST\r
\r
/* Miscellaneous */\r
#define BCLK__BUS_CLK__HZ 50000000U\r
static const uint32 CYCODE cy_cfg_addr_table[] = {\r
0x40004501u, /* Base address: 0x40004500 Count: 1 */\r
0x40004F02u, /* Base address: 0x40004F00 Count: 2 */\r
- 0x40005211u, /* Base address: 0x40005200 Count: 17 */\r
+ 0x4000520Eu, /* Base address: 0x40005200 Count: 14 */\r
0x40006401u, /* Base address: 0x40006400 Count: 1 */\r
0x40006501u, /* Base address: 0x40006500 Count: 1 */\r
- 0x40010047u, /* Base address: 0x40010000 Count: 71 */\r
- 0x40010142u, /* Base address: 0x40010100 Count: 66 */\r
- 0x40010254u, /* Base address: 0x40010200 Count: 84 */\r
- 0x4001035Cu, /* Base address: 0x40010300 Count: 92 */\r
- 0x4001044Fu, /* Base address: 0x40010400 Count: 79 */\r
- 0x4001055Au, /* Base address: 0x40010500 Count: 90 */\r
- 0x40010653u, /* Base address: 0x40010600 Count: 83 */\r
- 0x40010752u, /* Base address: 0x40010700 Count: 82 */\r
- 0x4001091Cu, /* Base address: 0x40010900 Count: 28 */\r
- 0x40010A4Eu, /* Base address: 0x40010A00 Count: 78 */\r
- 0x40010B4Fu, /* Base address: 0x40010B00 Count: 79 */\r
- 0x40010C4Cu, /* Base address: 0x40010C00 Count: 76 */\r
- 0x40010D50u, /* Base address: 0x40010D00 Count: 80 */\r
- 0x40010E51u, /* Base address: 0x40010E00 Count: 81 */\r
- 0x40010F3Au, /* Base address: 0x40010F00 Count: 58 */\r
- 0x40011460u, /* Base address: 0x40011400 Count: 96 */\r
- 0x4001154Du, /* Base address: 0x40011500 Count: 77 */\r
- 0x40011646u, /* Base address: 0x40011600 Count: 70 */\r
- 0x40011752u, /* Base address: 0x40011700 Count: 82 */\r
- 0x40011854u, /* Base address: 0x40011800 Count: 84 */\r
- 0x40011954u, /* Base address: 0x40011900 Count: 84 */\r
- 0x40011B0Eu, /* Base address: 0x40011B00 Count: 14 */\r
- 0x40014016u, /* Base address: 0x40014000 Count: 22 */\r
- 0x4001411Du, /* Base address: 0x40014100 Count: 29 */\r
- 0x4001420Fu, /* Base address: 0x40014200 Count: 15 */\r
- 0x4001430Fu, /* Base address: 0x40014300 Count: 15 */\r
- 0x4001440Fu, /* Base address: 0x40014400 Count: 15 */\r
- 0x4001451Du, /* Base address: 0x40014500 Count: 29 */\r
- 0x4001460Au, /* Base address: 0x40014600 Count: 10 */\r
- 0x40014712u, /* Base address: 0x40014700 Count: 18 */\r
+ 0x40010045u, /* Base address: 0x40010000 Count: 69 */\r
+ 0x4001013Du, /* Base address: 0x40010100 Count: 61 */\r
+ 0x40010247u, /* Base address: 0x40010200 Count: 71 */\r
+ 0x4001035Fu, /* Base address: 0x40010300 Count: 95 */\r
+ 0x4001045Fu, /* Base address: 0x40010400 Count: 95 */\r
+ 0x40010560u, /* Base address: 0x40010500 Count: 96 */\r
+ 0x40010650u, /* Base address: 0x40010600 Count: 80 */\r
+ 0x40010755u, /* Base address: 0x40010700 Count: 85 */\r
+ 0x40010912u, /* Base address: 0x40010900 Count: 18 */\r
+ 0x40010A46u, /* Base address: 0x40010A00 Count: 70 */\r
+ 0x40010B50u, /* Base address: 0x40010B00 Count: 80 */\r
+ 0x40010C56u, /* Base address: 0x40010C00 Count: 86 */\r
+ 0x40010D58u, /* Base address: 0x40010D00 Count: 88 */\r
+ 0x40010E4Cu, /* Base address: 0x40010E00 Count: 76 */\r
+ 0x40010F3Bu, /* Base address: 0x40010F00 Count: 59 */\r
+ 0x4001141Fu, /* Base address: 0x40011400 Count: 31 */\r
+ 0x40011554u, /* Base address: 0x40011500 Count: 84 */\r
+ 0x40011656u, /* Base address: 0x40011600 Count: 86 */\r
+ 0x40011744u, /* Base address: 0x40011700 Count: 68 */\r
+ 0x40011804u, /* Base address: 0x40011800 Count: 4 */\r
+ 0x40011905u, /* Base address: 0x40011900 Count: 5 */\r
+ 0x40011B02u, /* Base address: 0x40011B00 Count: 2 */\r
+ 0x40014019u, /* Base address: 0x40014000 Count: 25 */\r
+ 0x40014118u, /* Base address: 0x40014100 Count: 24 */\r
+ 0x4001420Du, /* Base address: 0x40014200 Count: 13 */\r
+ 0x4001430Du, /* Base address: 0x40014300 Count: 13 */\r
+ 0x40014411u, /* Base address: 0x40014400 Count: 17 */\r
+ 0x40014518u, /* Base address: 0x40014500 Count: 24 */\r
+ 0x4001460Eu, /* Base address: 0x40014600 Count: 14 */\r
+ 0x4001470Fu, /* Base address: 0x40014700 Count: 15 */\r
0x40014809u, /* Base address: 0x40014800 Count: 9 */\r
- 0x4001490Bu, /* Base address: 0x40014900 Count: 11 */\r
- 0x40014C0Cu, /* Base address: 0x40014C00 Count: 12 */\r
- 0x40014D0Cu, /* Base address: 0x40014D00 Count: 12 */\r
- 0x40015005u, /* Base address: 0x40015000 Count: 5 */\r
+ 0x4001490Du, /* Base address: 0x40014900 Count: 13 */\r
+ 0x40014C08u, /* Base address: 0x40014C00 Count: 8 */\r
+ 0x40014D0Bu, /* Base address: 0x40014D00 Count: 11 */\r
+ 0x40015002u, /* Base address: 0x40015000 Count: 2 */\r
0x40015104u, /* Base address: 0x40015100 Count: 4 */\r
};\r
\r
static const cy_cfg_addrvalue_t CYCODE cy_cfg_data_table[] = {\r
{0x7Eu, 0x02u},\r
{0x01u, 0x20u},\r
- {0x0Au, 0x27u},\r
- {0x00u, 0x48u},\r
- {0x01u, 0x4Cu},\r
+ {0x0Au, 0x36u},\r
+ {0x00u, 0x04u},\r
+ {0x01u, 0x0Cu},\r
{0x04u, 0x31u},\r
{0x10u, 0xC4u},\r
- {0x11u, 0x40u},\r
- {0x19u, 0x08u},\r
+ {0x11u, 0x44u},\r
+ {0x18u, 0x04u},\r
{0x1Cu, 0x30u},\r
- {0x20u, 0x10u},\r
- {0x21u, 0x10u},\r
{0x24u, 0x44u},\r
- {0x28u, 0x01u},\r
- {0x29u, 0x01u},\r
- {0x30u, 0x30u},\r
- {0x31u, 0x20u},\r
+ {0x28u, 0x02u},\r
+ {0x30u, 0x20u},\r
+ {0x31u, 0x30u},\r
{0x78u, 0x20u},\r
{0x79u, 0x20u},\r
{0x7Cu, 0x40u},\r
{0x20u, 0x01u},\r
- {0x87u, 0x0Fu},\r
- {0x00u, 0xE0u},\r
- {0x01u, 0x03u},\r
- {0x03u, 0x74u},\r
- {0x04u, 0x40u},\r
- {0x05u, 0x20u},\r
- {0x06u, 0x80u},\r
- {0x07u, 0x40u},\r
- {0x08u, 0x0Bu},\r
- {0x09u, 0x02u},\r
- {0x0Au, 0xF4u},\r
- {0x0Cu, 0x11u},\r
- {0x0Du, 0x64u},\r
- {0x0Eu, 0xECu},\r
- {0x16u, 0xFFu},\r
- {0x17u, 0x08u},\r
- {0x18u, 0xCAu},\r
- {0x1Au, 0x15u},\r
- {0x1Bu, 0x01u},\r
+ {0x85u, 0x0Fu},\r
+ {0x02u, 0xFFu},\r
+ {0x04u, 0x0Fu},\r
+ {0x06u, 0xF0u},\r
+ {0x0Au, 0xFFu},\r
+ {0x0Eu, 0xFFu},\r
+ {0x10u, 0x69u},\r
+ {0x12u, 0x96u},\r
+ {0x14u, 0xFFu},\r
+ {0x18u, 0x55u},\r
+ {0x19u, 0x04u},\r
+ {0x1Au, 0xAAu},\r
+ {0x1Cu, 0xFFu},\r
{0x1Du, 0x01u},\r
- {0x1Fu, 0x6Eu},\r
- {0x20u, 0x06u},\r
- {0x26u, 0x10u},\r
- {0x27u, 0x7Fu},\r
- {0x28u, 0x40u},\r
- {0x29u, 0x78u},\r
- {0x2Au, 0x80u},\r
- {0x2Bu, 0x03u},\r
- {0x2Cu, 0x01u},\r
- {0x2Du, 0x20u},\r
- {0x2Fu, 0x40u},\r
- {0x32u, 0xC0u},\r
- {0x34u, 0x3Fu},\r
- {0x35u, 0x60u},\r
- {0x37u, 0x1Fu},\r
+ {0x1Fu, 0x02u},\r
+ {0x23u, 0x01u},\r
+ {0x28u, 0x33u},\r
+ {0x2Au, 0xCCu},\r
+ {0x2Bu, 0x02u},\r
+ {0x31u, 0x04u},\r
+ {0x32u, 0xFFu},\r
+ {0x35u, 0x03u},\r
{0x3Au, 0x08u},\r
- {0x3Bu, 0x20u},\r
- {0x40u, 0x52u},\r
- {0x41u, 0x03u},\r
- {0x42u, 0x60u},\r
- {0x45u, 0xE2u},\r
+ {0x3Fu, 0x10u},\r
+ {0x40u, 0x53u},\r
+ {0x41u, 0x06u},\r
+ {0x42u, 0x40u},\r
+ {0x45u, 0xEFu},\r
{0x46u, 0xDCu},\r
- {0x47u, 0x0Fu},\r
- {0x48u, 0x1Fu},\r
+ {0x47u, 0x20u},\r
+ {0x48u, 0x2Fu},\r
{0x49u, 0xFFu},\r
{0x4Au, 0xFFu},\r
{0x4Bu, 0xFFu},\r
{0x59u, 0x04u},\r
{0x5Au, 0x04u},\r
{0x5Bu, 0x04u},\r
- {0x5Cu, 0x11u},\r
+ {0x5Cu, 0x91u},\r
{0x5Du, 0x01u},\r
{0x5Fu, 0x01u},\r
{0x60u, 0x08u},\r
{0x68u, 0x40u},\r
{0x69u, 0x40u},\r
{0x6Eu, 0x08u},\r
- {0x8Bu, 0x01u},\r
- {0xA6u, 0x01u},\r
- {0xABu, 0x02u},\r
- {0xB2u, 0x01u},\r
- {0xB5u, 0x01u},\r
- {0xB7u, 0x02u},\r
- {0xD8u, 0x04u},\r
+ {0x81u, 0x02u},\r
+ {0x83u, 0x01u},\r
+ {0x8Du, 0x02u},\r
+ {0x8Fu, 0x05u},\r
+ {0x91u, 0x02u},\r
+ {0x93u, 0x11u},\r
+ {0x95u, 0x02u},\r
+ {0x97u, 0x09u},\r
+ {0x99u, 0x01u},\r
+ {0x9Bu, 0x02u},\r
+ {0xB1u, 0x04u},\r
+ {0xB3u, 0x03u},\r
+ {0xB5u, 0x10u},\r
+ {0xB7u, 0x08u},\r
+ {0xBBu, 0x08u},\r
+ {0xD6u, 0x08u},\r
{0xD9u, 0x04u},\r
- {0xDCu, 0x11u},\r
+ {0xDBu, 0x04u},\r
+ {0xDCu, 0x10u},\r
+ {0xDDu, 0x90u},\r
{0xDFu, 0x01u},\r
- {0x01u, 0x8Au},\r
- {0x03u, 0x08u},\r
- {0x08u, 0x80u},\r
- {0x0Au, 0x04u},\r
- {0x0Bu, 0x22u},\r
- {0x10u, 0x80u},\r
- {0x11u, 0x80u},\r
- {0x12u, 0x14u},\r
- {0x17u, 0x08u},\r
- {0x19u, 0x28u},\r
- {0x1Au, 0x04u},\r
- {0x1Eu, 0x10u},\r
- {0x20u, 0x02u},\r
- {0x21u, 0x20u},\r
- {0x27u, 0x0Au},\r
- {0x29u, 0x20u},\r
- {0x2Bu, 0x22u},\r
- {0x2Eu, 0x10u},\r
- {0x30u, 0x20u},\r
- {0x31u, 0x84u},\r
- {0x38u, 0xA0u},\r
- {0x39u, 0x01u},\r
- {0x3Bu, 0x04u},\r
- {0x3Cu, 0x22u},\r
- {0x3Du, 0x01u},\r
- {0x42u, 0x0Cu},\r
- {0x43u, 0x08u},\r
- {0x44u, 0x20u},\r
- {0x45u, 0x08u},\r
- {0x48u, 0x05u},\r
- {0x49u, 0x84u},\r
- {0x4Bu, 0x0Au},\r
- {0x50u, 0x90u},\r
- {0x51u, 0x08u},\r
- {0x52u, 0x10u},\r
- {0x59u, 0x08u},\r
- {0x5Au, 0x22u},\r
- {0x5Bu, 0x80u},\r
+ {0x01u, 0xA8u},\r
+ {0x03u, 0x40u},\r
+ {0x09u, 0x08u},\r
+ {0x0Au, 0x02u},\r
+ {0x0Bu, 0x44u},\r
+ {0x12u, 0x04u},\r
+ {0x19u, 0x08u},\r
+ {0x1Au, 0x10u},\r
+ {0x21u, 0x02u},\r
+ {0x22u, 0x10u},\r
+ {0x25u, 0x41u},\r
+ {0x27u, 0x18u},\r
+ {0x2Au, 0x10u},\r
+ {0x2Bu, 0xC0u},\r
+ {0x32u, 0x80u},\r
+ {0x33u, 0x10u},\r
+ {0x34u, 0x02u},\r
+ {0x37u, 0x18u},\r
+ {0x3Du, 0x82u},\r
+ {0x41u, 0x09u},\r
+ {0x48u, 0x01u},\r
+ {0x49u, 0xA0u},\r
+ {0x4Au, 0x50u},\r
+ {0x51u, 0x50u},\r
+ {0x52u, 0x21u},\r
+ {0x59u, 0x10u},\r
+ {0x5Au, 0x84u},\r
+ {0x5Bu, 0x01u},\r
+ {0x5Cu, 0x40u},\r
+ {0x60u, 0x80u},\r
{0x61u, 0x20u},\r
- {0x62u, 0x01u},\r
- {0x63u, 0x21u},\r
- {0x68u, 0x48u},\r
- {0x69u, 0x84u},\r
- {0x71u, 0x10u},\r
- {0x72u, 0x81u},\r
- {0x73u, 0x10u},\r
- {0x81u, 0xB0u},\r
- {0x83u, 0x0Au},\r
- {0x84u, 0x80u},\r
- {0x87u, 0x40u},\r
- {0x88u, 0x01u},\r
- {0x8Au, 0x05u},\r
- {0x8Eu, 0x02u},\r
+ {0x62u, 0x08u},\r
+ {0x63u, 0x02u},\r
+ {0x64u, 0x02u},\r
+ {0x68u, 0x04u},\r
+ {0x69u, 0x45u},\r
+ {0x70u, 0x94u},\r
+ {0x72u, 0x80u},\r
+ {0x81u, 0x04u},\r
+ {0x82u, 0x80u},\r
+ {0x83u, 0x01u},\r
+ {0x85u, 0x04u},\r
+ {0x86u, 0x10u},\r
+ {0x88u, 0x04u},\r
+ {0x8Au, 0x10u},\r
+ {0x8Cu, 0x10u},\r
+ {0x8Du, 0x20u},\r
+ {0x8Eu, 0x90u},\r
{0xC0u, 0x0Fu},\r
- {0xC2u, 0x06u},\r
- {0xC4u, 0x2Fu},\r
- {0xCAu, 0x2Eu},\r
- {0xCCu, 0x0Eu},\r
- {0xCEu, 0x2Fu},\r
- {0xD0u, 0x06u},\r
+ {0xC2u, 0x0Fu},\r
+ {0xC4u, 0x02u},\r
+ {0xCAu, 0x05u},\r
+ {0xCCu, 0xECu},\r
+ {0xCEu, 0x90u},\r
+ {0xD0u, 0x03u},\r
{0xD2u, 0x0Cu},\r
- {0xD6u, 0x0Fu},\r
- {0xD8u, 0x0Fu},\r
- {0xE0u, 0x08u},\r
- {0xE4u, 0x05u},\r
- {0xE6u, 0x02u},\r
- {0x00u, 0x02u},\r
- {0x02u, 0x05u},\r
- {0x04u, 0x02u},\r
- {0x06u, 0x01u},\r
- {0x0Cu, 0x02u},\r
- {0x0Eu, 0x01u},\r
- {0x14u, 0x02u},\r
- {0x16u, 0x01u},\r
- {0x18u, 0x01u},\r
- {0x1Au, 0x02u},\r
- {0x1Cu, 0x02u},\r
- {0x1Eu, 0x09u},\r
- {0x20u, 0x02u},\r
- {0x22u, 0x11u},\r
- {0x24u, 0x02u},\r
- {0x25u, 0x01u},\r
- {0x26u, 0x01u},\r
- {0x30u, 0x08u},\r
- {0x32u, 0x04u},\r
- {0x34u, 0x03u},\r
- {0x35u, 0x01u},\r
- {0x36u, 0x10u},\r
+ {0xD6u, 0x1Fu},\r
+ {0xD8u, 0x1Fu},\r
+ {0xE2u, 0x82u},\r
+ {0xE4u, 0x02u},\r
+ {0xE6u, 0x05u},\r
+ {0x02u, 0xFFu},\r
+ {0x08u, 0x0Bu},\r
+ {0x0Au, 0xF4u},\r
+ {0x10u, 0xE0u},\r
+ {0x14u, 0xCAu},\r
+ {0x16u, 0x15u},\r
+ {0x18u, 0x40u},\r
+ {0x1Au, 0x80u},\r
+ {0x1Cu, 0x11u},\r
+ {0x1Eu, 0xECu},\r
+ {0x20u, 0x40u},\r
+ {0x22u, 0x80u},\r
+ {0x24u, 0x01u},\r
+ {0x2Au, 0x10u},\r
+ {0x2Cu, 0x06u},\r
+ {0x32u, 0x3Fu},\r
+ {0x34u, 0xC0u},\r
{0x3Au, 0x20u},\r
- {0x56u, 0x08u},\r
{0x58u, 0x04u},\r
- {0x59u, 0x04u},\r
{0x5Bu, 0x04u},\r
- {0x5Cu, 0x91u},\r
- {0x5Du, 0x90u},\r
+ {0x5Cu, 0x01u},\r
{0x5Fu, 0x01u},\r
- {0x80u, 0x02u},\r
- {0x81u, 0x8Bu},\r
- {0x82u, 0x21u},\r
- {0x83u, 0x74u},\r
- {0x84u, 0x02u},\r
- {0x86u, 0x01u},\r
- {0x87u, 0x01u},\r
- {0x89u, 0x02u},\r
- {0x8Cu, 0x02u},\r
- {0x8Du, 0x10u},\r
- {0x8Eu, 0x01u},\r
- {0x8Fu, 0x20u},\r
- {0x90u, 0x02u},\r
- {0x92u, 0x05u},\r
- {0x94u, 0x02u},\r
- {0x95u, 0x88u},\r
- {0x96u, 0x09u},\r
- {0x97u, 0x77u},\r
- {0x98u, 0x01u},\r
- {0x99u, 0x40u},\r
- {0x9Au, 0x12u},\r
- {0x9Bu, 0x80u},\r
- {0x9Cu, 0x02u},\r
- {0x9Du, 0x03u},\r
- {0x9Eu, 0x01u},\r
- {0x9Fu, 0x0Cu},\r
- {0xA1u, 0x34u},\r
- {0xA3u, 0x40u},\r
- {0xA4u, 0x02u},\r
- {0xA6u, 0x01u},\r
- {0xA7u, 0x77u},\r
- {0xA9u, 0x3Du},\r
- {0xABu, 0x42u},\r
- {0xACu, 0x10u},\r
- {0xADu, 0x10u},\r
- {0xAEu, 0x20u},\r
- {0xAFu, 0x20u},\r
- {0xB0u, 0x30u},\r
- {0xB1u, 0x30u},\r
- {0xB2u, 0x04u},\r
- {0xB4u, 0x03u},\r
- {0xB5u, 0xC0u},\r
- {0xB6u, 0x08u},\r
- {0xB7u, 0x0Fu},\r
- {0xBAu, 0x20u},\r
- {0xBBu, 0xA2u},\r
- {0xBEu, 0x01u},\r
+ {0x80u, 0x03u},\r
+ {0x81u, 0x08u},\r
+ {0x82u, 0x0Cu},\r
+ {0x83u, 0x10u},\r
+ {0x86u, 0xFFu},\r
+ {0x87u, 0x80u},\r
+ {0x88u, 0x05u},\r
+ {0x8Au, 0x0Au},\r
+ {0x8Bu, 0x04u},\r
+ {0x8Fu, 0x9Bu},\r
+ {0x90u, 0x06u},\r
+ {0x92u, 0x09u},\r
+ {0x93u, 0x60u},\r
+ {0x95u, 0x01u},\r
+ {0x97u, 0x02u},\r
+ {0x98u, 0x60u},\r
+ {0x99u, 0x9Bu},\r
+ {0x9Au, 0x90u},\r
+ {0x9Bu, 0x40u},\r
+ {0x9Cu, 0x0Fu},\r
+ {0x9Du, 0x08u},\r
+ {0x9Eu, 0xF0u},\r
+ {0x9Fu, 0x10u},\r
+ {0xA1u, 0x1Bu},\r
+ {0xA2u, 0xFFu},\r
+ {0xA4u, 0x30u},\r
+ {0xA5u, 0x01u},\r
+ {0xA6u, 0xC0u},\r
+ {0xA7u, 0x02u},\r
+ {0xA8u, 0xFFu},\r
+ {0xA9u, 0x80u},\r
+ {0xABu, 0x3Bu},\r
+ {0xACu, 0x50u},\r
+ {0xAEu, 0xA0u},\r
+ {0xAFu, 0x1Bu},\r
+ {0xB1u, 0xE0u},\r
+ {0xB3u, 0x03u},\r
+ {0xB4u, 0xFFu},\r
+ {0xB5u, 0x04u},\r
+ {0xB7u, 0x18u},\r
+ {0xBBu, 0x88u},\r
+ {0xBEu, 0x10u},\r
{0xD6u, 0x08u},\r
{0xD8u, 0x04u},\r
{0xD9u, 0x04u},\r
{0xDBu, 0x04u},\r
- {0xDCu, 0x11u},\r
+ {0xDCu, 0x10u},\r
{0xDDu, 0x90u},\r
{0xDFu, 0x01u},\r
- {0x00u, 0x81u},\r
- {0x01u, 0x08u},\r
- {0x05u, 0x05u},\r
- {0x07u, 0x02u},\r
- {0x09u, 0x08u},\r
- {0x0Au, 0x05u},\r
- {0x0Bu, 0x40u},\r
- {0x0Eu, 0x1Au},\r
- {0x10u, 0x02u},\r
- {0x11u, 0x08u},\r
+ {0x01u, 0x04u},\r
+ {0x03u, 0x84u},\r
+ {0x05u, 0x20u},\r
+ {0x07u, 0x40u},\r
+ {0x0Au, 0x48u},\r
+ {0x0Bu, 0x02u},\r
+ {0x0Du, 0x08u},\r
+ {0x0Eu, 0x05u},\r
+ {0x0Fu, 0x80u},\r
+ {0x11u, 0x02u},\r
+ {0x12u, 0x10u},\r
+ {0x13u, 0x90u},\r
+ {0x15u, 0xA4u},\r
{0x16u, 0x40u},\r
- {0x17u, 0x08u},\r
- {0x18u, 0x88u},\r
- {0x19u, 0x0Au},\r
- {0x1Au, 0x45u},\r
- {0x1Bu, 0x40u},\r
- {0x1Cu, 0x20u},\r
- {0x1Du, 0x05u},\r
- {0x1Eu, 0x0Au},\r
- {0x1Fu, 0x30u},\r
- {0x20u, 0x48u},\r
- {0x21u, 0x20u},\r
- {0x22u, 0x40u},\r
- {0x23u, 0x80u},\r
- {0x25u, 0x10u},\r
- {0x28u, 0x02u},\r
- {0x29u, 0x22u},\r
- {0x2Bu, 0x20u},\r
- {0x2Eu, 0x40u},\r
- {0x2Fu, 0x21u},\r
- {0x31u, 0x20u},\r
- {0x32u, 0x40u},\r
- {0x33u, 0x08u},\r
- {0x38u, 0x60u},\r
- {0x39u, 0x01u},\r
- {0x3Bu, 0x08u},\r
- {0x58u, 0x14u},\r
- {0x5Bu, 0x40u},\r
- {0x5Du, 0x40u},\r
+ {0x1Bu, 0x20u},\r
+ {0x1Du, 0x08u},\r
+ {0x1Eu, 0x04u},\r
+ {0x22u, 0x9Au},\r
+ {0x28u, 0x22u},\r
+ {0x29u, 0x20u},\r
+ {0x2Bu, 0x40u},\r
+ {0x2Cu, 0x20u},\r
+ {0x2Fu, 0x20u},\r
+ {0x30u, 0x10u},\r
+ {0x32u, 0x8Au},\r
+ {0x34u, 0x80u},\r
+ {0x36u, 0x80u},\r
+ {0x38u, 0x28u},\r
+ {0x3Au, 0x02u},\r
+ {0x3Bu, 0x80u},\r
+ {0x44u, 0x10u},\r
+ {0x45u, 0x08u},\r
+ {0x58u, 0x01u},\r
+ {0x59u, 0x84u},\r
+ {0x5Bu, 0x20u},\r
+ {0x5Cu, 0x04u},\r
+ {0x5Eu, 0xA2u},\r
{0x60u, 0x08u},\r
- {0x62u, 0x84u},\r
- {0x63u, 0x04u},\r
- {0x66u, 0x40u},\r
- {0x68u, 0x02u},\r
- {0x6Cu, 0x20u},\r
- {0x6Du, 0x10u},\r
- {0x6Fu, 0x02u},\r
- {0x80u, 0x04u},\r
- {0x81u, 0x40u},\r
- {0x82u, 0x01u},\r
- {0x88u, 0x01u},\r
- {0x8Au, 0x10u},\r
- {0x8Bu, 0x22u},\r
- {0x8Eu, 0x02u},\r
- {0x90u, 0x20u},\r
- {0x91u, 0x05u},\r
+ {0x62u, 0x04u},\r
+ {0x63u, 0x45u},\r
+ {0x66u, 0x80u},\r
+ {0x79u, 0x80u},\r
+ {0x7Bu, 0x02u},\r
+ {0x81u, 0x81u},\r
+ {0x82u, 0x02u},\r
+ {0x84u, 0x20u},\r
+ {0x88u, 0x40u},\r
+ {0x89u, 0x44u},\r
+ {0x8Bu, 0x10u},\r
+ {0x8Cu, 0x04u},\r
+ {0x8Eu, 0x21u},\r
+ {0x8Fu, 0x02u},\r
+ {0x90u, 0x08u},\r
+ {0x91u, 0xE1u},\r
{0x92u, 0x10u},\r
- {0x93u, 0x58u},\r
- {0x94u, 0x80u},\r
- {0x96u, 0x22u},\r
- {0x97u, 0x25u},\r
- {0x98u, 0xA4u},\r
- {0x99u, 0xA0u},\r
- {0x9Au, 0x9Au},\r
- {0x9Bu, 0x4Au},\r
- {0x9Du, 0x02u},\r
- {0x9Eu, 0x05u},\r
- {0x9Fu, 0x80u},\r
- {0xA0u, 0x88u},\r
- {0xA4u, 0x34u},\r
- {0xA5u, 0x50u},\r
- {0xA7u, 0x38u},\r
- {0xA9u, 0x10u},\r
- {0xACu, 0x40u},\r
- {0xB0u, 0x04u},\r
- {0xB1u, 0x08u},\r
- {0xB5u, 0x40u},\r
- {0xB7u, 0x41u},\r
- {0xC0u, 0xBDu},\r
- {0xC2u, 0xEFu},\r
- {0xC4u, 0x35u},\r
- {0xCAu, 0x4Fu},\r
- {0xCCu, 0x0Eu},\r
+ {0x93u, 0x02u},\r
+ {0x95u, 0x02u},\r
+ {0x96u, 0x86u},\r
+ {0x97u, 0x44u},\r
+ {0x98u, 0x01u},\r
+ {0x99u, 0x04u},\r
+ {0x9Au, 0x11u},\r
+ {0x9Bu, 0x30u},\r
+ {0x9Cu, 0x80u},\r
+ {0x9Du, 0x30u},\r
+ {0x9Eu, 0x04u},\r
+ {0x9Fu, 0x41u},\r
+ {0xA0u, 0x80u},\r
+ {0xA2u, 0x70u},\r
+ {0xA3u, 0x80u},\r
+ {0xA4u, 0x01u},\r
+ {0xA5u, 0x28u},\r
+ {0xA6u, 0x08u},\r
+ {0xA7u, 0x01u},\r
+ {0xA9u, 0x02u},\r
+ {0xABu, 0x40u},\r
+ {0xACu, 0x01u},\r
+ {0xAEu, 0x40u},\r
+ {0xAFu, 0x20u},\r
+ {0xB0u, 0x01u},\r
+ {0xB4u, 0x40u},\r
+ {0xB5u, 0x08u},\r
+ {0xC0u, 0x5Eu},\r
+ {0xC2u, 0xFBu},\r
+ {0xC4u, 0xFFu},\r
+ {0xCAu, 0x0Fu},\r
+ {0xCCu, 0x0Fu},\r
{0xCEu, 0x0Fu},\r
- {0xD6u, 0x1Eu},\r
- {0xD8u, 0x1Eu},\r
- {0xE2u, 0x04u},\r
- {0xE4u, 0x01u},\r
- {0xE6u, 0x80u},\r
- {0xE8u, 0x02u},\r
- {0xEAu, 0x40u},\r
- {0xEEu, 0x20u},\r
- {0x00u, 0xFFu},\r
- {0x01u, 0x1Bu},\r
- {0x05u, 0x9Bu},\r
- {0x06u, 0xFFu},\r
- {0x07u, 0x40u},\r
- {0x08u, 0xFFu},\r
- {0x09u, 0x08u},\r
- {0x0Bu, 0x10u},\r
- {0x0Cu, 0x0Fu},\r
- {0x0Eu, 0xF0u},\r
- {0x0Fu, 0x9Bu},\r
- {0x13u, 0x60u},\r
- {0x14u, 0x69u},\r
- {0x15u, 0x80u},\r
- {0x16u, 0x96u},\r
- {0x17u, 0x3Bu},\r
- {0x19u, 0x08u},\r
- {0x1Au, 0xFFu},\r
- {0x1Bu, 0x10u},\r
- {0x1Du, 0x01u},\r
- {0x1Fu, 0x02u},\r
- {0x20u, 0x33u},\r
- {0x22u, 0xCCu},\r
- {0x23u, 0x04u},\r
- {0x24u, 0x55u},\r
- {0x26u, 0xAAu},\r
- {0x27u, 0x1Bu},\r
- {0x29u, 0x01u},\r
- {0x2Bu, 0x02u},\r
- {0x2Eu, 0xFFu},\r
- {0x2Fu, 0x80u},\r
- {0x30u, 0xFFu},\r
- {0x31u, 0xE0u},\r
- {0x33u, 0x04u},\r
- {0x35u, 0x18u},\r
- {0x37u, 0x03u},\r
- {0x3Au, 0x02u},\r
- {0x3Bu, 0xA0u},\r
+ {0xD6u, 0xFFu},\r
+ {0xD8u, 0x1Fu},\r
+ {0xE2u, 0x24u},\r
+ {0xE6u, 0x0Du},\r
+ {0xE8u, 0x40u},\r
+ {0xEAu, 0x06u},\r
+ {0xECu, 0x08u},\r
+ {0x01u, 0x40u},\r
+ {0x02u, 0x24u},\r
+ {0x03u, 0x80u},\r
+ {0x05u, 0x04u},\r
+ {0x06u, 0x40u},\r
+ {0x07u, 0x08u},\r
+ {0x08u, 0x24u},\r
+ {0x09u, 0x04u},\r
+ {0x0Au, 0x09u},\r
+ {0x0Bu, 0x08u},\r
+ {0x0Du, 0x01u},\r
+ {0x0Eu, 0x20u},\r
+ {0x0Fu, 0x02u},\r
+ {0x11u, 0x3Fu},\r
+ {0x12u, 0x18u},\r
+ {0x13u, 0x40u},\r
+ {0x14u, 0x24u},\r
+ {0x15u, 0x3Fu},\r
+ {0x16u, 0x12u},\r
+ {0x17u, 0x40u},\r
+ {0x19u, 0x01u},\r
+ {0x1Au, 0x03u},\r
+ {0x1Bu, 0x02u},\r
+ {0x1Eu, 0x80u},\r
+ {0x1Fu, 0x7Fu},\r
+ {0x21u, 0x10u},\r
+ {0x22u, 0x04u},\r
+ {0x23u, 0x20u},\r
+ {0x25u, 0x80u},\r
+ {0x27u, 0x7Fu},\r
+ {0x29u, 0x10u},\r
+ {0x2Bu, 0x20u},\r
+ {0x2Cu, 0x40u},\r
+ {0x2Du, 0x80u},\r
+ {0x2Eu, 0x80u},\r
+ {0x2Fu, 0x7Fu},\r
+ {0x30u, 0x38u},\r
+ {0x31u, 0xC0u},\r
+ {0x33u, 0x0Cu},\r
+ {0x34u, 0x07u},\r
+ {0x35u, 0x03u},\r
+ {0x36u, 0xC0u},\r
+ {0x37u, 0x30u},\r
+ {0x3Bu, 0xAAu},\r
+ {0x3Eu, 0x40u},\r
{0x56u, 0x08u},\r
{0x58u, 0x04u},\r
{0x59u, 0x04u},\r
{0x5Cu, 0x11u},\r
{0x5Du, 0x90u},\r
{0x5Fu, 0x01u},\r
- {0x80u, 0xFFu},\r
- {0x84u, 0x55u},\r
- {0x85u, 0x06u},\r
- {0x86u, 0xAAu},\r
- {0x87u, 0x09u},\r
- {0x88u, 0xFFu},\r
- {0x89u, 0x03u},\r
- {0x8Bu, 0x0Cu},\r
- {0x8Eu, 0xFFu},\r
- {0x8Fu, 0x70u},\r
- {0x94u, 0x0Fu},\r
- {0x95u, 0x10u},\r
- {0x96u, 0xF0u},\r
- {0x97u, 0x2Fu},\r
- {0x9Au, 0xFFu},\r
- {0x9Du, 0x40u},\r
- {0x9Fu, 0x1Fu},\r
- {0xA5u, 0x0Fu},\r
- {0xA6u, 0xFFu},\r
- {0xA8u, 0x69u},\r
- {0xA9u, 0x20u},\r
- {0xAAu, 0x96u},\r
+ {0x82u, 0x7Fu},\r
+ {0x85u, 0x0Fu},\r
+ {0x88u, 0x20u},\r
+ {0x89u, 0x05u},\r
+ {0x8Au, 0x40u},\r
+ {0x8Bu, 0x0Au},\r
+ {0x8Eu, 0x08u},\r
+ {0x90u, 0x64u},\r
+ {0x94u, 0x78u},\r
+ {0x95u, 0x06u},\r
+ {0x96u, 0x03u},\r
+ {0x97u, 0x09u},\r
+ {0x98u, 0x02u},\r
+ {0x99u, 0x90u},\r
+ {0x9Bu, 0x2Fu},\r
+ {0x9Cu, 0x03u},\r
+ {0x9Eu, 0x74u},\r
+ {0x9Fu, 0x70u},\r
+ {0xA1u, 0xC0u},\r
+ {0xA3u, 0x1Fu},\r
+ {0xA5u, 0x03u},\r
+ {0xA6u, 0x01u},\r
+ {0xA7u, 0x0Cu},\r
+ {0xA8u, 0x01u},\r
+ {0xA9u, 0xA0u},\r
+ {0xAAu, 0x6Eu},\r
{0xABu, 0x4Fu},\r
- {0xACu, 0x33u},\r
- {0xADu, 0x05u},\r
- {0xAEu, 0xCCu},\r
- {0xAFu, 0x0Au},\r
- {0xB2u, 0xFFu},\r
- {0xB7u, 0x7Fu},\r
- {0xBAu, 0x08u},\r
+ {0xACu, 0x20u},\r
+ {0xAEu, 0x40u},\r
+ {0xAFu, 0x80u},\r
+ {0xB1u, 0x7Fu},\r
+ {0xB4u, 0x60u},\r
+ {0xB5u, 0x80u},\r
+ {0xB6u, 0x1Fu},\r
+ {0xBAu, 0x20u},\r
+ {0xBFu, 0x10u},\r
+ {0xD4u, 0x01u},\r
{0xD8u, 0x04u},\r
{0xD9u, 0x04u},\r
+ {0xDBu, 0x04u},\r
{0xDCu, 0x11u},\r
+ {0xDDu, 0x10u},\r
{0xDFu, 0x01u},\r
- {0x00u, 0x40u},\r
- {0x01u, 0x22u},\r
+ {0x00u, 0x02u},\r
+ {0x01u, 0x60u},\r
{0x03u, 0x20u},\r
{0x04u, 0x80u},\r
- {0x05u, 0xA6u},\r
- {0x06u, 0x08u},\r
- {0x08u, 0x08u},\r
- {0x09u, 0x10u},\r
- {0x0Eu, 0x18u},\r
- {0x12u, 0xA0u},\r
- {0x13u, 0x80u},\r
+ {0x05u, 0x10u},\r
+ {0x06u, 0x01u},\r
+ {0x07u, 0x40u},\r
+ {0x09u, 0x08u},\r
+ {0x0Au, 0x48u},\r
+ {0x0Bu, 0x01u},\r
+ {0x0Du, 0x18u},\r
+ {0x0Eu, 0x01u},\r
+ {0x0Fu, 0x80u},\r
+ {0x10u, 0x82u},\r
{0x14u, 0x02u},\r
- {0x16u, 0x04u},\r
- {0x17u, 0x04u},\r
- {0x18u, 0x40u},\r
- {0x1Bu, 0x02u},\r
- {0x1Eu, 0x10u},\r
- {0x20u, 0x20u},\r
- {0x22u, 0x52u},\r
- {0x23u, 0x41u},\r
- {0x25u, 0x40u},\r
- {0x27u, 0x02u},\r
- {0x2Au, 0x82u},\r
- {0x2Bu, 0x24u},\r
- {0x2Cu, 0x20u},\r
- {0x2Du, 0x20u},\r
- {0x2Fu, 0x02u},\r
- {0x32u, 0x52u},\r
- {0x33u, 0x08u},\r
- {0x35u, 0x80u},\r
- {0x37u, 0x84u},\r
- {0x38u, 0x80u},\r
- {0x3Au, 0x08u},\r
- {0x3Bu, 0x12u},\r
- {0x3Cu, 0x04u},\r
- {0x3Du, 0x80u},\r
- {0x3Eu, 0x10u},\r
- {0x43u, 0x0Cu},\r
- {0x58u, 0x10u},\r
- {0x59u, 0x08u},\r
- {0x5Bu, 0x41u},\r
- {0x60u, 0x01u},\r
- {0x61u, 0x46u},\r
- {0x62u, 0x20u},\r
- {0x63u, 0x18u},\r
- {0x7Du, 0x20u},\r
- {0x7Fu, 0x08u},\r
- {0x81u, 0x20u},\r
- {0x83u, 0x40u},\r
- {0x84u, 0x20u},\r
- {0x88u, 0x10u},\r
- {0x8Bu, 0x02u},\r
- {0x91u, 0x04u},\r
- {0x93u, 0x22u},\r
- {0x94u, 0x01u},\r
- {0x96u, 0x22u},\r
- {0x97u, 0x01u},\r
- {0x98u, 0xA9u},\r
- {0x99u, 0x82u},\r
- {0x9Au, 0x8Eu},\r
- {0x9Cu, 0x02u},\r
- {0xA0u, 0xA8u},\r
- {0xA2u, 0x84u},\r
- {0xA3u, 0x60u},\r
- {0xA4u, 0x40u},\r
- {0xA5u, 0x08u},\r
- {0xA6u, 0x02u},\r
- {0xA7u, 0x18u},\r
- {0xABu, 0x08u},\r
- {0xACu, 0x30u},\r
- {0xADu, 0x50u},\r
- {0xAFu, 0x10u},\r
- {0xB4u, 0x40u},\r
- {0xB5u, 0x04u},\r
- {0xB6u, 0x40u},\r
- {0xC0u, 0xFFu},\r
- {0xC2u, 0x66u},\r
- {0xC4u, 0xEDu},\r
- {0xCAu, 0x7Fu},\r
- {0xCCu, 0x5Fu},\r
- {0xCEu, 0x7Fu},\r
- {0xD6u, 0x0Fu},\r
- {0xD8u, 0x0Fu},\r
- {0xE0u, 0x02u},\r
- {0xE2u, 0x04u},\r
- {0xE6u, 0x11u},\r
- {0xE8u, 0x0Au},\r
- {0xEAu, 0x10u},\r
- {0xECu, 0x01u},\r
- {0xEEu, 0x02u},\r
- {0x00u, 0x1Fu},\r
- {0x01u, 0xE0u},\r
- {0x02u, 0x20u},\r
- {0x06u, 0x60u},\r
- {0x07u, 0x01u},\r
- {0x0Au, 0x9Fu},\r
- {0x0Fu, 0xECu},\r
- {0x10u, 0x90u},\r
- {0x11u, 0x21u},\r
- {0x12u, 0x40u},\r
- {0x13u, 0x02u},\r
- {0x14u, 0xC0u},\r
{0x15u, 0x04u},\r
{0x16u, 0x08u},\r
- {0x17u, 0x43u},\r
- {0x18u, 0xC0u},\r
- {0x19u, 0x88u},\r
- {0x1Au, 0x04u},\r
- {0x1Bu, 0x03u},\r
- {0x1Cu, 0xC0u},\r
+ {0x18u, 0x09u},\r
+ {0x1Au, 0x4Au},\r
+ {0x1Bu, 0x40u},\r
+ {0x1Cu, 0x02u},\r
+ {0x1Du, 0x50u},\r
{0x1Eu, 0x01u},\r
- {0x20u, 0xC0u},\r
- {0x22u, 0x02u},\r
+ {0x1Fu, 0x40u},\r
+ {0x21u, 0x21u},\r
+ {0x22u, 0x40u},\r
+ {0x23u, 0x30u},\r
{0x25u, 0x10u},\r
- {0x26u, 0xFFu},\r
- {0x28u, 0x7Fu},\r
- {0x2Au, 0x80u},\r
+ {0x27u, 0x80u},\r
+ {0x28u, 0x80u},\r
+ {0x29u, 0x40u},\r
+ {0x2Au, 0x18u},\r
+ {0x2Eu, 0x04u},\r
+ {0x2Fu, 0x4Au},\r
+ {0x31u, 0x28u},\r
+ {0x32u, 0x01u},\r
+ {0x33u, 0x48u},\r
+ {0x35u, 0x20u},\r
+ {0x37u, 0x88u},\r
+ {0x39u, 0x02u},\r
+ {0x3Au, 0x04u},\r
+ {0x3Bu, 0x50u},\r
+ {0x3Du, 0x04u},\r
+ {0x3Eu, 0x10u},\r
+ {0x58u, 0x40u},\r
+ {0x5Fu, 0x80u},\r
+ {0x62u, 0x40u},\r
+ {0x68u, 0x02u},\r
+ {0x83u, 0x14u},\r
+ {0x87u, 0x20u},\r
+ {0x88u, 0x01u},\r
+ {0x89u, 0x20u},\r
+ {0x8Au, 0x08u},\r
+ {0x8Cu, 0x24u},\r
+ {0x91u, 0x61u},\r
+ {0x92u, 0x30u},\r
+ {0x93u, 0x41u},\r
+ {0x94u, 0x20u},\r
+ {0x95u, 0x06u},\r
+ {0x96u, 0xC3u},\r
+ {0x97u, 0x80u},\r
+ {0x98u, 0x48u},\r
+ {0x9Au, 0x05u},\r
+ {0x9Bu, 0x50u},\r
+ {0x9Du, 0x30u},\r
+ {0x9Eu, 0x40u},\r
+ {0x9Fu, 0x05u},\r
+ {0xA0u, 0xA0u},\r
+ {0xA1u, 0x48u},\r
+ {0xA2u, 0x20u},\r
+ {0xA3u, 0x02u},\r
+ {0xA4u, 0x01u},\r
+ {0xA5u, 0x30u},\r
+ {0xA7u, 0x41u},\r
+ {0xA8u, 0x02u},\r
+ {0xAAu, 0x42u},\r
+ {0xABu, 0x40u},\r
+ {0xAEu, 0x04u},\r
+ {0xAFu, 0x80u},\r
+ {0xB5u, 0x10u},\r
+ {0xB6u, 0x80u},\r
+ {0xC0u, 0xDFu},\r
+ {0xC2u, 0xFFu},\r
+ {0xC4u, 0xE9u},\r
+ {0xCAu, 0xFFu},\r
+ {0xCCu, 0x7Fu},\r
+ {0xCEu, 0x6Fu},\r
+ {0xD6u, 0x18u},\r
+ {0xD8u, 0x08u},\r
+ {0xE0u, 0x04u},\r
+ {0xE2u, 0x01u},\r
+ {0xE4u, 0x08u},\r
+ {0xE8u, 0x05u},\r
+ {0xEAu, 0x12u},\r
+ {0xECu, 0x80u},\r
+ {0xEEu, 0x09u},\r
+ {0x00u, 0x55u},\r
+ {0x02u, 0xAAu},\r
+ {0x0Au, 0xFFu},\r
+ {0x0Eu, 0xFFu},\r
+ {0x0Fu, 0x12u},\r
+ {0x10u, 0xFFu},\r
+ {0x13u, 0x01u},\r
+ {0x14u, 0xFFu},\r
+ {0x17u, 0x0Cu},\r
+ {0x18u, 0x0Fu},\r
+ {0x19u, 0x24u},\r
+ {0x1Au, 0xF0u},\r
+ {0x1Bu, 0x03u},\r
+ {0x20u, 0x69u},\r
+ {0x22u, 0x96u},\r
+ {0x24u, 0x33u},\r
+ {0x25u, 0x28u},\r
+ {0x26u, 0xCCu},\r
+ {0x27u, 0x03u},\r
+ {0x29u, 0x21u},\r
{0x2Bu, 0x02u},\r
- {0x2Cu, 0x80u},\r
- {0x2Du, 0x10u},\r
- {0x33u, 0x10u},\r
+ {0x2Eu, 0xFFu},\r
+ {0x31u, 0x10u},\r
+ {0x33u, 0x20u},\r
{0x34u, 0xFFu},\r
- {0x35u, 0xE0u},\r
- {0x37u, 0x0Fu},\r
- {0x39u, 0x08u},\r
- {0x3Eu, 0x10u},\r
- {0x3Fu, 0x10u},\r
- {0x56u, 0x08u},\r
+ {0x35u, 0x0Fu},\r
+ {0x3Au, 0x20u},\r
+ {0x3Fu, 0x04u},\r
{0x58u, 0x04u},\r
{0x59u, 0x04u},\r
{0x5Bu, 0x04u},\r
- {0x5Du, 0x90u},\r
+ {0x5Cu, 0x01u},\r
{0x5Fu, 0x01u},\r
- {0x80u, 0x0Fu},\r
- {0x82u, 0x80u},\r
- {0x84u, 0x50u},\r
- {0x86u, 0x8Fu},\r
- {0x8Fu, 0x04u},\r
- {0x90u, 0x04u},\r
- {0x91u, 0x04u},\r
- {0x92u, 0x08u},\r
- {0x93u, 0x08u},\r
- {0x94u, 0x20u},\r
- {0x96u, 0x0Fu},\r
- {0x98u, 0x4Fu},\r
- {0x9Au, 0x80u},\r
- {0x9Bu, 0x08u},\r
- {0x9Cu, 0x01u},\r
- {0x9Eu, 0x02u},\r
- {0xA0u, 0x01u},\r
- {0xA2u, 0x02u},\r
- {0xA3u, 0x01u},\r
- {0xA6u, 0x10u},\r
- {0xA8u, 0x04u},\r
- {0xAAu, 0x08u},\r
+ {0x80u, 0x02u},\r
+ {0x82u, 0x09u},\r
+ {0x83u, 0x40u},\r
+ {0x84u, 0x01u},\r
+ {0x86u, 0x02u},\r
+ {0x8Bu, 0x80u},\r
+ {0x8Cu, 0x02u},\r
+ {0x8Eu, 0x01u},\r
+ {0x8Fu, 0x01u},\r
+ {0x91u, 0x03u},\r
+ {0x93u, 0x0Cu},\r
+ {0x94u, 0x02u},\r
+ {0x96u, 0x01u},\r
+ {0x97u, 0x30u},\r
+ {0x98u, 0x10u},\r
+ {0x99u, 0x02u},\r
+ {0x9Cu, 0x10u},\r
+ {0x9Fu, 0x07u},\r
+ {0xA0u, 0x02u},\r
+ {0xA1u, 0x04u},\r
+ {0xA2u, 0x05u},\r
+ {0xA4u, 0x10u},\r
+ {0xA5u, 0x4Du},\r
+ {0xA7u, 0x22u},\r
+ {0xA9u, 0x48u},\r
+ {0xABu, 0x17u},\r
{0xACu, 0x10u},\r
- {0xAEu, 0x8Fu},\r
- {0xAFu, 0x02u},\r
- {0xB1u, 0x01u},\r
- {0xB2u, 0xF0u},\r
- {0xB3u, 0x02u},\r
- {0xB4u, 0x0Cu},\r
- {0xB5u, 0x0Cu},\r
- {0xB6u, 0x03u},\r
- {0xB8u, 0x0Au},\r
- {0xBAu, 0xA0u},\r
- {0xBEu, 0x01u},\r
- {0xBFu, 0x10u},\r
+ {0xADu, 0x0Bu},\r
+ {0xAFu, 0x44u},\r
+ {0xB0u, 0x04u},\r
+ {0xB1u, 0x0Fu},\r
+ {0xB2u, 0x08u},\r
+ {0xB3u, 0x70u},\r
+ {0xB4u, 0x03u},\r
+ {0xB5u, 0x80u},\r
+ {0xB6u, 0x10u},\r
+ {0xB8u, 0x80u},\r
+ {0xBAu, 0x20u},\r
+ {0xBBu, 0x02u},\r
+ {0xBEu, 0x40u},\r
+ {0xD6u, 0x08u},\r
{0xD8u, 0x04u},\r
{0xD9u, 0x04u},\r
{0xDBu, 0x04u},\r
{0xDCu, 0x11u},\r
+ {0xDDu, 0x90u},\r
{0xDFu, 0x01u},\r
- {0x01u, 0x0Au},\r
- {0x04u, 0x02u},\r
- {0x06u, 0x04u},\r
- {0x07u, 0x20u},\r
- {0x08u, 0x10u},\r
- {0x09u, 0x02u},\r
- {0x0Au, 0x02u},\r
- {0x0Bu, 0x20u},\r
- {0x0Eu, 0x54u},\r
- {0x0Fu, 0x01u},\r
+ {0x01u, 0x82u},\r
+ {0x03u, 0x20u},\r
+ {0x04u, 0x01u},\r
+ {0x05u, 0x60u},\r
+ {0x08u, 0x20u},\r
+ {0x09u, 0x40u},\r
+ {0x0Au, 0x20u},\r
+ {0x0Cu, 0x04u},\r
+ {0x0Du, 0x08u},\r
+ {0x0Eu, 0x04u},\r
+ {0x0Fu, 0xA0u},\r
{0x10u, 0x20u},\r
- {0x11u, 0x20u},\r
- {0x12u, 0x82u},\r
- {0x15u, 0x01u},\r
- {0x17u, 0x58u},\r
+ {0x11u, 0x40u},\r
+ {0x13u, 0x01u},\r
+ {0x16u, 0x50u},\r
+ {0x17u, 0x40u},\r
{0x18u, 0x20u},\r
- {0x19u, 0x08u},\r
- {0x1Au, 0x82u},\r
- {0x1Bu, 0x1Cu},\r
- {0x1Fu, 0x20u},\r
- {0x20u, 0x80u},\r
- {0x21u, 0x08u},\r
- {0x23u, 0x04u},\r
- {0x25u, 0x40u},\r
- {0x27u, 0x24u},\r
- {0x28u, 0x10u},\r
- {0x29u, 0x40u},\r
- {0x2Au, 0x08u},\r
- {0x2Bu, 0x40u},\r
- {0x2Fu, 0x25u},\r
- {0x30u, 0x02u},\r
- {0x31u, 0x20u},\r
- {0x37u, 0x19u},\r
- {0x3Au, 0x20u},\r
- {0x3Bu, 0x60u},\r
- {0x3Cu, 0x08u},\r
- {0x3Du, 0xA0u},\r
- {0x3Eu, 0x02u},\r
- {0x3Fu, 0x20u},\r
- {0x49u, 0x80u},\r
- {0x4Au, 0x02u},\r
- {0x58u, 0xA5u},\r
- {0x5Cu, 0x40u},\r
- {0x62u, 0x40u},\r
- {0x64u, 0x02u},\r
- {0x68u, 0x02u},\r
- {0x69u, 0x40u},\r
- {0x81u, 0x40u},\r
- {0x82u, 0x40u},\r
- {0x8Au, 0x40u},\r
- {0x8Bu, 0x04u},\r
- {0x8Cu, 0x40u},\r
- {0x91u, 0x04u},\r
- {0x93u, 0x60u},\r
- {0x94u, 0x04u},\r
- {0x96u, 0x02u},\r
- {0x98u, 0xA5u},\r
- {0x99u, 0xC2u},\r
- {0x9Au, 0x08u},\r
+ {0x19u, 0x02u},\r
+ {0x1Au, 0x01u},\r
+ {0x1Bu, 0x20u},\r
+ {0x1Eu, 0x04u},\r
+ {0x20u, 0x08u},\r
+ {0x21u, 0x02u},\r
+ {0x22u, 0x04u},\r
+ {0x26u, 0x02u},\r
+ {0x27u, 0x28u},\r
+ {0x29u, 0x60u},\r
+ {0x2Bu, 0x50u},\r
+ {0x2Fu, 0x18u},\r
+ {0x31u, 0x02u},\r
+ {0x32u, 0x24u},\r
+ {0x33u, 0x40u},\r
+ {0x35u, 0x08u},\r
+ {0x36u, 0x02u},\r
+ {0x37u, 0x18u},\r
+ {0x38u, 0x80u},\r
+ {0x39u, 0x11u},\r
+ {0x3Cu, 0x80u},\r
+ {0x49u, 0x40u},\r
+ {0x4Bu, 0x80u},\r
+ {0x58u, 0x40u},\r
+ {0x59u, 0x10u},\r
+ {0x60u, 0x03u},\r
+ {0x62u, 0x10u},\r
+ {0x6Du, 0x04u},\r
+ {0x6Eu, 0x60u},\r
+ {0x80u, 0x10u},\r
+ {0x81u, 0xC2u},\r
+ {0x86u, 0x11u},\r
+ {0x8Au, 0x04u},\r
+ {0x8Du, 0x10u},\r
+ {0x90u, 0x80u},\r
+ {0x91u, 0x11u},\r
+ {0x92u, 0x22u},\r
+ {0x93u, 0x81u},\r
+ {0x94u, 0x20u},\r
+ {0x95u, 0x04u},\r
+ {0x96u, 0x04u},\r
+ {0x98u, 0x28u},\r
+ {0x9Au, 0x40u},\r
+ {0x9Bu, 0x40u},\r
{0x9Cu, 0x02u},\r
- {0xA0u, 0x28u},\r
- {0xA1u, 0x22u},\r
- {0xA2u, 0x80u},\r
- {0xA3u, 0x40u},\r
- {0xA4u, 0x40u},\r
- {0xA5u, 0x08u},\r
- {0xA7u, 0x18u},\r
- {0xA9u, 0x08u},\r
- {0xAFu, 0x01u},\r
- {0xB0u, 0x94u},\r
- {0xC0u, 0x7Cu},\r
- {0xC2u, 0xFFu},\r
- {0xC4u, 0xFFu},\r
- {0xCAu, 0x79u},\r
- {0xCCu, 0xE5u},\r
- {0xCEu, 0xD8u},\r
- {0xD6u, 0x1Fu},\r
- {0xD8u, 0x18u},\r
- {0xE2u, 0x04u},\r
- {0xE4u, 0x14u},\r
- {0xEAu, 0x03u},\r
- {0xEEu, 0x04u},\r
- {0x80u, 0x08u},\r
- {0x82u, 0x40u},\r
- {0x8Bu, 0x40u},\r
- {0x8Fu, 0x20u},\r
- {0x91u, 0x10u},\r
- {0x92u, 0x0Au},\r
- {0x93u, 0x90u},\r
- {0x95u, 0x48u},\r
- {0x96u, 0x20u},\r
- {0x97u, 0x02u},\r
- {0x98u, 0x20u},\r
- {0x9Bu, 0x10u},\r
- {0x9Cu, 0x08u},\r
- {0x9Du, 0x60u},\r
+ {0x9Du, 0x20u},\r
{0x9Eu, 0x10u},\r
- {0xA0u, 0x04u},\r
- {0xA1u, 0x40u},\r
- {0xA2u, 0x02u},\r
- {0xA3u, 0xA4u},\r
- {0xA7u, 0x12u},\r
- {0xACu, 0x04u},\r
- {0xAFu, 0x02u},\r
- {0xB7u, 0x10u},\r
+ {0xA0u, 0x20u},\r
+ {0xA1u, 0x48u},\r
+ {0xA2u, 0x20u},\r
+ {0xA3u, 0x40u},\r
+ {0xA7u, 0x21u},\r
+ {0xA8u, 0x80u},\r
+ {0xAAu, 0x40u},\r
+ {0xAFu, 0x29u},\r
+ {0xB1u, 0x18u},\r
+ {0xB4u, 0x01u},\r
+ {0xC0u, 0xDDu},\r
+ {0xC2u, 0x77u},\r
+ {0xC4u, 0xBDu},\r
+ {0xCAu, 0x6Fu},\r
+ {0xCCu, 0xEFu},\r
+ {0xCEu, 0x1Du},\r
+ {0xD6u, 0x0Cu},\r
+ {0xD8u, 0x0Cu},\r
+ {0xE0u, 0x08u},\r
+ {0xE6u, 0x05u},\r
+ {0xEAu, 0x09u},\r
+ {0x82u, 0x80u},\r
+ {0x89u, 0x08u},\r
+ {0x9Du, 0x08u},\r
+ {0xA2u, 0x80u},\r
+ {0xA7u, 0x08u},\r
+ {0xADu, 0x08u},\r
+ {0xAEu, 0x04u},\r
+ {0xAFu, 0x92u},\r
+ {0xB1u, 0x20u},\r
+ {0xB2u, 0x14u},\r
+ {0xB3u, 0x02u},\r
+ {0xB4u, 0x80u},\r
+ {0xB7u, 0x20u},\r
+ {0xE0u, 0x88u},\r
{0xE2u, 0x40u},\r
- {0xE4u, 0x30u},\r
- {0xE6u, 0x80u},\r
- {0xEAu, 0x23u},\r
- {0xEEu, 0x04u},\r
- {0x04u, 0x30u},\r
- {0x06u, 0xC0u},\r
- {0x07u, 0x01u},\r
- {0x0Au, 0xFFu},\r
- {0x0Bu, 0x02u},\r
- {0x0Eu, 0xFFu},\r
- {0x10u, 0x60u},\r
- {0x12u, 0x90u},\r
- {0x13u, 0x08u},\r
- {0x14u, 0x0Fu},\r
- {0x16u, 0xF0u},\r
- {0x18u, 0x06u},\r
- {0x1Au, 0x09u},\r
- {0x1Bu, 0x04u},\r
- {0x1Cu, 0x05u},\r
- {0x1Eu, 0x0Au},\r
- {0x20u, 0xFFu},\r
- {0x28u, 0x50u},\r
- {0x29u, 0x04u},\r
- {0x2Au, 0xA0u},\r
- {0x2Bu, 0x08u},\r
- {0x2Cu, 0x03u},\r
- {0x2Eu, 0x0Cu},\r
- {0x31u, 0x0Cu},\r
- {0x33u, 0x02u},\r
- {0x35u, 0x01u},\r
- {0x36u, 0xFFu},\r
- {0x3Eu, 0x40u},\r
- {0x3Fu, 0x01u},\r
+ {0xE6u, 0x01u},\r
+ {0xEAu, 0x81u},\r
+ {0xECu, 0x38u},\r
+ {0x02u, 0x04u},\r
+ {0x05u, 0x08u},\r
+ {0x06u, 0x08u},\r
+ {0x07u, 0x05u},\r
+ {0x0Cu, 0x2Au},\r
+ {0x0Du, 0x08u},\r
+ {0x0Eu, 0x54u},\r
+ {0x0Fu, 0x04u},\r
+ {0x12u, 0x01u},\r
+ {0x15u, 0x04u},\r
+ {0x16u, 0x02u},\r
+ {0x17u, 0x08u},\r
+ {0x19u, 0x08u},\r
+ {0x1Au, 0x40u},\r
+ {0x1Bu, 0x06u},\r
+ {0x1Du, 0x08u},\r
+ {0x1Eu, 0x20u},\r
+ {0x1Fu, 0x14u},\r
+ {0x22u, 0x10u},\r
+ {0x30u, 0x06u},\r
+ {0x31u, 0x02u},\r
+ {0x32u, 0x01u},\r
+ {0x33u, 0x0Cu},\r
+ {0x34u, 0x18u},\r
+ {0x35u, 0x10u},\r
+ {0x36u, 0x60u},\r
+ {0x37u, 0x01u},\r
+ {0x3Bu, 0x08u},\r
+ {0x3Eu, 0x51u},\r
+ {0x56u, 0x08u},\r
{0x58u, 0x04u},\r
{0x59u, 0x04u},\r
{0x5Bu, 0x04u},\r
- {0x5Cu, 0x10u},\r
+ {0x5Cu, 0x11u},\r
+ {0x5Du, 0x90u},\r
{0x5Fu, 0x01u},\r
- {0x84u, 0x50u},\r
- {0x85u, 0x30u},\r
- {0x86u, 0xA0u},\r
- {0x87u, 0xC0u},\r
- {0x88u, 0xFFu},\r
- {0x8Bu, 0xFFu},\r
- {0x8Eu, 0xFFu},\r
- {0x8Fu, 0xFFu},\r
- {0x90u, 0x03u},\r
- {0x91u, 0x90u},\r
- {0x92u, 0x0Cu},\r
- {0x93u, 0x60u},\r
- {0x94u, 0x06u},\r
- {0x95u, 0x0Fu},\r
- {0x96u, 0x09u},\r
- {0x97u, 0xF0u},\r
- {0x98u, 0x30u},\r
- {0x99u, 0x09u},\r
- {0x9Au, 0xC0u},\r
- {0x9Bu, 0x06u},\r
- {0x9Cu, 0x60u},\r
- {0x9Du, 0x05u},\r
- {0x9Eu, 0x90u},\r
- {0x9Fu, 0x0Au},\r
- {0xA0u, 0x05u},\r
- {0xA2u, 0x0Au},\r
- {0xA3u, 0xFFu},\r
- {0xA8u, 0x0Fu},\r
- {0xA9u, 0x50u},\r
- {0xAAu, 0xF0u},\r
- {0xABu, 0xA0u},\r
- {0xADu, 0x03u},\r
- {0xAEu, 0xFFu},\r
- {0xAFu, 0x0Cu},\r
- {0xB1u, 0xFFu},\r
- {0xB4u, 0xFFu},\r
- {0xBEu, 0x10u},\r
- {0xBFu, 0x01u},\r
- {0xD4u, 0x01u},\r
+ {0x84u, 0xFFu},\r
+ {0x89u, 0x04u},\r
+ {0x8Au, 0xFFu},\r
+ {0x8Bu, 0x03u},\r
+ {0x91u, 0x04u},\r
+ {0x93u, 0x0Au},\r
+ {0x94u, 0x0Fu},\r
+ {0x95u, 0x02u},\r
+ {0x96u, 0xF0u},\r
+ {0x97u, 0x04u},\r
+ {0x98u, 0xFFu},\r
+ {0x99u, 0x04u},\r
+ {0x9Bu, 0x02u},\r
+ {0x9Cu, 0x33u},\r
+ {0x9Eu, 0xCCu},\r
+ {0xA0u, 0x96u},\r
+ {0xA2u, 0x69u},\r
+ {0xA6u, 0xFFu},\r
+ {0xA9u, 0x04u},\r
+ {0xAAu, 0xFFu},\r
+ {0xABu, 0x02u},\r
+ {0xACu, 0x55u},\r
+ {0xAEu, 0xAAu},\r
+ {0xB0u, 0xFFu},\r
+ {0xB3u, 0x06u},\r
+ {0xB5u, 0x08u},\r
+ {0xB7u, 0x01u},\r
+ {0xBAu, 0x02u},\r
+ {0xBBu, 0x08u},\r
{0xD8u, 0x04u},\r
{0xD9u, 0x04u},\r
{0xDBu, 0x04u},\r
- {0xDDu, 0x10u},\r
+ {0xDCu, 0x11u},\r
{0xDFu, 0x01u},\r
- {0x00u, 0x90u},\r
- {0x01u, 0x84u},\r
- {0x04u, 0x10u},\r
- {0x05u, 0x80u},\r
- {0x06u, 0x20u},\r
- {0x08u, 0x98u},\r
+ {0x00u, 0x02u},\r
+ {0x01u, 0x48u},\r
+ {0x05u, 0x20u},\r
+ {0x07u, 0x20u},\r
+ {0x09u, 0x04u},\r
{0x0Au, 0x80u},\r
- {0x0Cu, 0x01u},\r
- {0x0Eu, 0x22u},\r
- {0x0Fu, 0x04u},\r
- {0x10u, 0x01u},\r
- {0x11u, 0x51u},\r
- {0x14u, 0x88u},\r
- {0x16u, 0x02u},\r
+ {0x0Bu, 0x05u},\r
+ {0x0Eu, 0x04u},\r
+ {0x0Fu, 0x12u},\r
+ {0x10u, 0x80u},\r
+ {0x14u, 0x02u},\r
+ {0x15u, 0x14u},\r
+ {0x16u, 0x40u},\r
+ {0x19u, 0x01u},\r
+ {0x1Au, 0x28u},\r
{0x1Bu, 0x80u},\r
- {0x1Fu, 0x20u},\r
- {0x20u, 0x04u},\r
- {0x21u, 0x10u},\r
- {0x22u, 0x05u},\r
- {0x26u, 0x02u},\r
- {0x28u, 0x08u},\r
- {0x2Du, 0x51u},\r
- {0x2Eu, 0x22u},\r
- {0x30u, 0x10u},\r
- {0x33u, 0x01u},\r
- {0x34u, 0x98u},\r
- {0x35u, 0x40u},\r
- {0x36u, 0x11u},\r
+ {0x1Fu, 0x02u},\r
+ {0x20u, 0x40u},\r
+ {0x21u, 0x88u},\r
+ {0x22u, 0x20u},\r
+ {0x24u, 0x10u},\r
+ {0x26u, 0x18u},\r
+ {0x27u, 0x01u},\r
+ {0x2Fu, 0x08u},\r
+ {0x31u, 0x88u},\r
+ {0x32u, 0x20u},\r
+ {0x36u, 0x18u},\r
{0x37u, 0x01u},\r
- {0x39u, 0x28u},\r
- {0x3Cu, 0x90u},\r
- {0x3Du, 0x04u},\r
- {0x3Fu, 0x04u},\r
- {0x5Fu, 0x40u},\r
- {0x60u, 0x04u},\r
- {0x63u, 0x08u},\r
- {0x69u, 0x16u},\r
- {0x6Au, 0x80u},\r
- {0x6Bu, 0x01u},\r
- {0x70u, 0xA2u},\r
- {0x73u, 0x10u},\r
- {0x80u, 0x02u},\r
- {0x84u, 0x40u},\r
- {0x8Au, 0x40u},\r
- {0x8Bu, 0x40u},\r
- {0x90u, 0x10u},\r
- {0x93u, 0x80u},\r
- {0x95u, 0x52u},\r
- {0x96u, 0x20u},\r
- {0x97u, 0x16u},\r
- {0x98u, 0x20u},\r
- {0x9Au, 0x02u},\r
- {0x9Bu, 0x10u},\r
- {0x9Cu, 0x8Cu},\r
- {0x9Du, 0x20u},\r
- {0x9Eu, 0x50u},\r
- {0x9Fu, 0x01u},\r
- {0xA0u, 0x04u},\r
- {0xA1u, 0x40u},\r
- {0xA2u, 0x10u},\r
- {0xA4u, 0xA2u},\r
- {0xAAu, 0x08u},\r
- {0xACu, 0x01u},\r
- {0xAEu, 0x22u},\r
- {0xAFu, 0x20u},\r
- {0xB4u, 0x04u},\r
- {0xB7u, 0x80u},\r
- {0xC0u, 0xE7u},\r
- {0xC2u, 0xFFu},\r
- {0xC4u, 0xDBu},\r
- {0xCAu, 0xB4u},\r
- {0xCCu, 0xF5u},\r
- {0xCEu, 0x76u},\r
- {0xD6u, 0x10u},\r
- {0xE0u, 0x20u},\r
- {0xE4u, 0x80u},\r
- {0xE6u, 0x11u},\r
- {0xECu, 0x10u},\r
- {0xEEu, 0x42u},\r
- {0x03u, 0x13u},\r
- {0x06u, 0xFFu},\r
- {0x08u, 0xFFu},\r
- {0x0Bu, 0x10u},\r
- {0x0Cu, 0x90u},\r
- {0x0Eu, 0x60u},\r
- {0x0Fu, 0x0Cu},\r
- {0x11u, 0x13u},\r
- {0x13u, 0x08u},\r
- {0x14u, 0x09u},\r
- {0x16u, 0x06u},\r
- {0x18u, 0x30u},\r
- {0x19u, 0x01u},\r
- {0x1Au, 0xC0u},\r
- {0x1Bu, 0x02u},\r
- {0x1Cu, 0x03u},\r
- {0x1Du, 0x03u},\r
- {0x1Eu, 0x0Cu},\r
- {0x20u, 0x05u},\r
- {0x22u, 0x0Au},\r
- {0x23u, 0x03u},\r
- {0x24u, 0x0Fu},\r
- {0x25u, 0x10u},\r
- {0x26u, 0xF0u},\r
- {0x27u, 0x07u},\r
- {0x28u, 0x50u},\r
- {0x2Au, 0xA0u},\r
- {0x2Bu, 0x20u},\r
- {0x2Cu, 0xFFu},\r
- {0x2Du, 0x01u},\r
- {0x2Fu, 0x02u},\r
- {0x33u, 0x20u},\r
- {0x34u, 0xFFu},\r
- {0x35u, 0x03u},\r
- {0x37u, 0x1Cu},\r
- {0x3Bu, 0x20u},\r
- {0x3Eu, 0x10u},\r
- {0x58u, 0x04u},\r
- {0x59u, 0x04u},\r
+ {0x38u, 0x44u},\r
+ {0x3Fu, 0x20u},\r
+ {0x58u, 0x94u},\r
{0x5Cu, 0x10u},\r
- {0x5Fu, 0x01u},\r
- {0x87u, 0x02u},\r
- {0x88u, 0x03u},\r
- {0x8Au, 0x0Cu},\r
- {0x8Bu, 0x10u},\r
- {0x8Cu, 0x06u},\r
- {0x8Eu, 0x09u},\r
- {0x8Fu, 0x01u},\r
+ {0x5Fu, 0x8Au},\r
+ {0x60u, 0x04u},\r
+ {0x62u, 0x40u},\r
+ {0x63u, 0x20u},\r
+ {0x65u, 0x40u},\r
+ {0x80u, 0x40u},\r
+ {0x83u, 0x89u},\r
+ {0x85u, 0x40u},\r
+ {0x88u, 0x04u},\r
+ {0x89u, 0x14u},\r
+ {0x8Du, 0x15u},\r
+ {0x90u, 0x80u},\r
+ {0x91u, 0x40u},\r
+ {0x92u, 0x80u},\r
{0x93u, 0x04u},\r
- {0x94u, 0x0Fu},\r
- {0x96u, 0xF0u},\r
- {0x97u, 0x20u},\r
- {0x9Bu, 0x08u},\r
- {0x9Cu, 0x05u},\r
- {0x9Eu, 0x0Au},\r
- {0x9Fu, 0x40u},\r
- {0xA4u, 0x60u},\r
- {0xA6u, 0x90u},\r
- {0xA8u, 0x50u},\r
- {0xA9u, 0x25u},\r
- {0xAAu, 0xA0u},\r
- {0xABu, 0x4Au},\r
- {0xACu, 0x30u},\r
- {0xAEu, 0xC0u},\r
- {0xB1u, 0x03u},\r
- {0xB2u, 0xFFu},\r
- {0xB3u, 0x60u},\r
- {0xB5u, 0x10u},\r
- {0xB7u, 0x0Cu},\r
- {0xBEu, 0x04u},\r
- {0xBFu, 0x45u},\r
- {0xD8u, 0x04u},\r
- {0xD9u, 0x04u},\r
- {0xDBu, 0x04u},\r
- {0xDCu, 0x10u},\r
- {0xDFu, 0x01u},\r
- {0x00u, 0x80u},\r
- {0x02u, 0x04u},\r
- {0x03u, 0x02u},\r
- {0x04u, 0x10u},\r
- {0x07u, 0x21u},\r
- {0x08u, 0x08u},\r
- {0x09u, 0x40u},\r
- {0x0Du, 0x40u},\r
- {0x0Eu, 0x20u},\r
- {0x0Fu, 0x04u},\r
- {0x10u, 0x22u},\r
- {0x13u, 0x10u},\r
- {0x14u, 0x80u},\r
- {0x15u, 0x10u},\r
- {0x16u, 0x02u},\r
- {0x17u, 0x08u},\r
- {0x18u, 0x10u},\r
- {0x1Cu, 0x08u},\r
- {0x20u, 0x24u},\r
- {0x23u, 0x42u},\r
- {0x25u, 0x60u},\r
- {0x26u, 0x20u},\r
- {0x27u, 0x10u},\r
- {0x28u, 0x08u},\r
- {0x2Du, 0x20u},\r
- {0x2Eu, 0x09u},\r
- {0x2Fu, 0x81u},\r
- {0x30u, 0xA0u},\r
- {0x31u, 0x08u},\r
- {0x33u, 0x02u},\r
- {0x34u, 0x01u},\r
- {0x36u, 0x20u},\r
- {0x37u, 0x80u},\r
- {0x39u, 0xC0u},\r
- {0x3Au, 0x10u},\r
- {0x3Bu, 0x04u},\r
- {0x3Du, 0x80u},\r
- {0x3Eu, 0x20u},\r
- {0x3Fu, 0x02u},\r
- {0x58u, 0x04u},\r
- {0x59u, 0x80u},\r
- {0x5Au, 0x21u},\r
- {0x5Cu, 0x08u},\r
- {0x5Fu, 0x08u},\r
- {0x60u, 0x02u},\r
- {0x80u, 0x02u},\r
- {0x81u, 0x20u},\r
- {0x87u, 0x40u},\r
- {0x88u, 0x10u},\r
- {0x8Bu, 0x82u},\r
- {0x8Eu, 0x44u},\r
- {0x93u, 0x80u},\r
- {0x94u, 0x04u},\r
- {0x95u, 0x02u},\r
- {0x96u, 0x80u},\r
- {0x98u, 0x21u},\r
- {0x99u, 0x80u},\r
- {0x9Cu, 0x08u},\r
- {0x9Eu, 0x40u},\r
- {0xA0u, 0x41u},\r
- {0xA1u, 0x08u},\r
- {0xA2u, 0x10u},\r
+ {0x96u, 0x20u},\r
+ {0x98u, 0x12u},\r
+ {0x99u, 0x30u},\r
+ {0x9Du, 0x0Cu},\r
+ {0xA0u, 0x81u},\r
+ {0xA1u, 0x04u},\r
+ {0xA2u, 0x80u},\r
{0xA3u, 0x01u},\r
- {0xA4u, 0x80u},\r
- {0xACu, 0x20u},\r
- {0xB4u, 0x20u},\r
- {0xB6u, 0x04u},\r
- {0xC0u, 0xE3u},\r
- {0xC2u, 0xE5u},\r
- {0xC4u, 0xF7u},\r
- {0xCAu, 0xF4u},\r
- {0xCCu, 0xBFu},\r
- {0xCEu, 0xBEu},\r
- {0xD6u, 0x0Fu},\r
- {0xD8u, 0x08u},\r
- {0xE0u, 0x80u},\r
- {0xE4u, 0x12u},\r
+ {0xA8u, 0x01u},\r
+ {0xA9u, 0x24u},\r
+ {0xAAu, 0x04u},\r
+ {0xABu, 0x41u},\r
+ {0xACu, 0x01u},\r
+ {0xADu, 0x10u},\r
+ {0xAFu, 0x80u},\r
+ {0xB0u, 0x10u},\r
+ {0xB2u, 0x02u},\r
+ {0xB3u, 0x10u},\r
+ {0xB4u, 0x40u},\r
+ {0xB6u, 0x20u},\r
+ {0xC0u, 0x6Du},\r
+ {0xC2u, 0xEFu},\r
+ {0xC4u, 0xF8u},\r
+ {0xCAu, 0x20u},\r
+ {0xCCu, 0xEEu},\r
+ {0xCEu, 0x2Au},\r
+ {0xD6u, 0xFEu},\r
+ {0xD8u, 0x1Eu},\r
+ {0xE0u, 0xB0u},\r
+ {0xE2u, 0x40u},\r
+ {0xE4u, 0x04u},\r
{0xEAu, 0x10u},\r
- {0xECu, 0x10u},\r
- {0xEEu, 0x80u},\r
- {0x00u, 0x02u},\r
- {0x01u, 0x08u},\r
- {0x02u, 0x11u},\r
- {0x03u, 0x04u},\r
- {0x04u, 0x02u},\r
- {0x05u, 0x02u},\r
- {0x06u, 0x01u},\r
- {0x07u, 0x01u},\r
- {0x10u, 0x02u},\r
- {0x12u, 0x01u},\r
- {0x14u, 0x02u},\r
- {0x15u, 0x01u},\r
- {0x16u, 0x01u},\r
- {0x17u, 0x02u},\r
- {0x18u, 0x02u},\r
- {0x1Au, 0x05u},\r
- {0x1Bu, 0x20u},\r
- {0x1Cu, 0x01u},\r
- {0x1Du, 0x04u},\r
- {0x1Eu, 0x02u},\r
- {0x1Fu, 0x08u},\r
- {0x20u, 0x02u},\r
- {0x22u, 0x01u},\r
- {0x23u, 0x10u},\r
- {0x29u, 0x03u},\r
- {0x2Bu, 0x0Cu},\r
- {0x2Cu, 0x02u},\r
- {0x2Eu, 0x09u},\r
- {0x30u, 0x10u},\r
- {0x31u, 0x10u},\r
- {0x32u, 0x08u},\r
- {0x33u, 0x20u},\r
- {0x34u, 0x04u},\r
- {0x36u, 0x03u},\r
- {0x37u, 0x0Fu},\r
- {0x3Au, 0x80u},\r
+ {0xECu, 0x84u},\r
+ {0x01u, 0xFFu},\r
+ {0x04u, 0x03u},\r
+ {0x05u, 0x03u},\r
+ {0x06u, 0x0Cu},\r
+ {0x07u, 0x0Cu},\r
+ {0x09u, 0x30u},\r
+ {0x0Au, 0xFFu},\r
+ {0x0Bu, 0xC0u},\r
+ {0x0Cu, 0x05u},\r
+ {0x0Du, 0x06u},\r
+ {0x0Eu, 0x0Au},\r
+ {0x0Fu, 0x09u},\r
+ {0x10u, 0x09u},\r
+ {0x12u, 0x06u},\r
+ {0x14u, 0x90u},\r
+ {0x16u, 0x60u},\r
+ {0x17u, 0xFFu},\r
+ {0x18u, 0x50u},\r
+ {0x1Au, 0xA0u},\r
+ {0x1Bu, 0xFFu},\r
+ {0x1Du, 0x0Fu},\r
+ {0x1Eu, 0xFFu},\r
+ {0x1Fu, 0xF0u},\r
+ {0x20u, 0x0Fu},\r
+ {0x21u, 0x60u},\r
+ {0x22u, 0xF0u},\r
+ {0x23u, 0x90u},\r
+ {0x25u, 0x50u},\r
+ {0x26u, 0xFFu},\r
+ {0x27u, 0xA0u},\r
+ {0x28u, 0x30u},\r
+ {0x2Au, 0xC0u},\r
+ {0x2Du, 0x05u},\r
+ {0x2Fu, 0x0Au},\r
+ {0x30u, 0xFFu},\r
+ {0x37u, 0xFFu},\r
+ {0x3Eu, 0x01u},\r
{0x3Fu, 0x40u},\r
{0x56u, 0x08u},\r
{0x58u, 0x04u},\r
{0x59u, 0x04u},\r
{0x5Bu, 0x04u},\r
- {0x5Cu, 0x11u},\r
{0x5Du, 0x90u},\r
{0x5Fu, 0x01u},\r
- {0x83u, 0x80u},\r
- {0x86u, 0x01u},\r
- {0x8Au, 0x80u},\r
- {0x8Bu, 0x04u},\r
- {0x8Cu, 0x98u},\r
- {0x8Eu, 0x22u},\r
- {0x91u, 0x24u},\r
- {0x92u, 0x06u},\r
- {0x93u, 0x09u},\r
- {0x96u, 0x60u},\r
- {0x97u, 0x58u},\r
- {0x9Au, 0x08u},\r
- {0x9Bu, 0x03u},\r
- {0x9Eu, 0x10u},\r
- {0xA0u, 0x10u},\r
- {0xA2u, 0x88u},\r
- {0xA3u, 0x24u},\r
- {0xA7u, 0x20u},\r
- {0xA9u, 0x40u},\r
- {0xABu, 0x80u},\r
- {0xACu, 0x98u},\r
- {0xADu, 0x24u},\r
- {0xAEu, 0x44u},\r
- {0xAFu, 0x12u},\r
- {0xB0u, 0x0Eu},\r
- {0xB1u, 0xC0u},\r
- {0xB2u, 0xE0u},\r
- {0xB3u, 0x07u},\r
- {0xB4u, 0x01u},\r
- {0xB5u, 0x38u},\r
- {0xB6u, 0x10u},\r
+ {0x81u, 0x08u},\r
+ {0x83u, 0x50u},\r
+ {0x88u, 0x20u},\r
+ {0x8Au, 0x10u},\r
+ {0x8Cu, 0x01u},\r
+ {0x8Eu, 0x02u},\r
+ {0x90u, 0x20u},\r
+ {0x91u, 0x26u},\r
+ {0x92u, 0x10u},\r
+ {0x93u, 0x58u},\r
+ {0x94u, 0x20u},\r
+ {0x95u, 0x02u},\r
+ {0x96u, 0x18u},\r
+ {0x97u, 0x24u},\r
+ {0x98u, 0x10u},\r
+ {0x9Au, 0x20u},\r
+ {0x9Du, 0x10u},\r
+ {0x9Eu, 0x01u},\r
+ {0x9Fu, 0x08u},\r
+ {0xA4u, 0x20u},\r
+ {0xA5u, 0x04u},\r
+ {0xA6u, 0x14u},\r
+ {0xA7u, 0x02u},\r
+ {0xA9u, 0x01u},\r
+ {0xAAu, 0x02u},\r
+ {0xB0u, 0x04u},\r
+ {0xB1u, 0x60u},\r
+ {0xB2u, 0x08u},\r
+ {0xB3u, 0x1Eu},\r
+ {0xB4u, 0x30u},\r
+ {0xB5u, 0x01u},\r
+ {0xB6u, 0x03u},\r
+ {0xBAu, 0x20u},\r
{0xBEu, 0x40u},\r
- {0xBFu, 0x01u},\r
+ {0xBFu, 0x05u},\r
+ {0xD6u, 0x08u},\r
{0xD8u, 0x04u},\r
{0xD9u, 0x04u},\r
- {0xDCu, 0x11u},\r
+ {0xDBu, 0x04u},\r
+ {0xDCu, 0x91u},\r
+ {0xDDu, 0x90u},\r
{0xDFu, 0x01u},\r
- {0x00u, 0x01u},\r
- {0x03u, 0x20u},\r
- {0x04u, 0x04u},\r
- {0x06u, 0x04u},\r
- {0x07u, 0x02u},\r
- {0x0Au, 0x6Au},\r
- {0x0Du, 0x02u},\r
+ {0x03u, 0x09u},\r
+ {0x04u, 0x84u},\r
+ {0x05u, 0x80u},\r
+ {0x06u, 0x08u},\r
+ {0x07u, 0x14u},\r
+ {0x0Au, 0xA8u},\r
+ {0x0Bu, 0x01u},\r
+ {0x0Cu, 0x20u},\r
+ {0x0Du, 0x90u},\r
{0x0Eu, 0x21u},\r
- {0x0Fu, 0x08u},\r
- {0x12u, 0x42u},\r
- {0x14u, 0x41u},\r
- {0x19u, 0x92u},\r
- {0x1Au, 0x62u},\r
- {0x1Bu, 0x20u},\r
+ {0x0Fu, 0x84u},\r
+ {0x10u, 0x08u},\r
+ {0x12u, 0x10u},\r
+ {0x14u, 0x20u},\r
+ {0x15u, 0x18u},\r
+ {0x17u, 0x21u},\r
+ {0x18u, 0x02u},\r
+ {0x19u, 0x20u},\r
+ {0x1Au, 0x88u},\r
+ {0x1Bu, 0x08u},\r
{0x1Cu, 0x80u},\r
- {0x1Du, 0x02u},\r
- {0x1Eu, 0x20u},\r
- {0x1Fu, 0x50u},\r
- {0x20u, 0x02u},\r
- {0x22u, 0x06u},\r
- {0x24u, 0x08u},\r
- {0x25u, 0x08u},\r
- {0x26u, 0x01u},\r
- {0x27u, 0x28u},\r
- {0x28u, 0x08u},\r
- {0x29u, 0x02u},\r
- {0x2Bu, 0x08u},\r
- {0x2Cu, 0x61u},\r
- {0x2Fu, 0x08u},\r
+ {0x21u, 0x04u},\r
+ {0x22u, 0x22u},\r
+ {0x26u, 0x80u},\r
+ {0x29u, 0x28u},\r
+ {0x2Cu, 0x20u},\r
+ {0x2Du, 0x80u},\r
+ {0x2Fu, 0x80u},\r
{0x30u, 0x80u},\r
- {0x31u, 0x08u},\r
- {0x32u, 0x10u},\r
- {0x37u, 0x2Au},\r
- {0x38u, 0x08u},\r
- {0x39u, 0x02u},\r
+ {0x31u, 0x04u},\r
+ {0x33u, 0x01u},\r
+ {0x34u, 0x20u},\r
+ {0x36u, 0x40u},\r
+ {0x37u, 0x04u},\r
{0x3Au, 0x02u},\r
- {0x3Eu, 0x02u},\r
- {0x3Fu, 0x10u},\r
- {0x5Au, 0x80u},\r
- {0x60u, 0x01u},\r
- {0x83u, 0x06u},\r
- {0x86u, 0x01u},\r
- {0x87u, 0x10u},\r
- {0x88u, 0x41u},\r
- {0x8Bu, 0x11u},\r
- {0x8Du, 0x10u},\r
- {0x8Eu, 0x01u},\r
- {0xC0u, 0xECu},\r
+ {0x3Cu, 0x04u},\r
+ {0x3Du, 0x10u},\r
+ {0x3Eu, 0x01u},\r
+ {0x3Fu, 0x80u},\r
+ {0x5Bu, 0x80u},\r
+ {0x5Cu, 0x40u},\r
+ {0x5Fu, 0x10u},\r
+ {0x63u, 0x02u},\r
+ {0x64u, 0x02u},\r
+ {0x66u, 0x10u},\r
+ {0x67u, 0x02u},\r
+ {0x6Du, 0x40u},\r
+ {0x6Eu, 0x80u},\r
+ {0x6Fu, 0x01u},\r
+ {0x81u, 0x80u},\r
+ {0x83u, 0x81u},\r
+ {0x87u, 0x01u},\r
+ {0x88u, 0x40u},\r
+ {0x89u, 0x04u},\r
+ {0x8Au, 0x08u},\r
+ {0x8Eu, 0x08u},\r
+ {0x8Fu, 0x10u},\r
+ {0x90u, 0x80u},\r
+ {0x91u, 0x20u},\r
+ {0x95u, 0x48u},\r
+ {0x99u, 0x10u},\r
+ {0x9Au, 0x02u},\r
+ {0x9Bu, 0x30u},\r
+ {0x9Eu, 0x04u},\r
+ {0xA0u, 0x89u},\r
+ {0xA1u, 0x80u},\r
+ {0xA2u, 0x10u},\r
+ {0xA7u, 0x50u},\r
+ {0xA8u, 0x01u},\r
+ {0xABu, 0x10u},\r
+ {0xACu, 0x08u},\r
+ {0xAFu, 0x20u},\r
+ {0xB7u, 0x01u},\r
+ {0xC0u, 0xE3u},\r
{0xC2u, 0xFFu},\r
- {0xC4u, 0x99u},\r
- {0xCAu, 0xF5u},\r
- {0xCCu, 0xEEu},\r
- {0xCEu, 0xA3u},\r
- {0xD6u, 0x08u},\r
- {0xD8u, 0x08u},\r
- {0xE0u, 0x80u},\r
- {0xE2u, 0x40u},\r
- {0xE4u, 0xA0u},\r
- {0x01u, 0x11u},\r
- {0x09u, 0x11u},\r
- {0x0Fu, 0x20u},\r
- {0x11u, 0x02u},\r
- {0x13u, 0x64u},\r
- {0x15u, 0x11u},\r
- {0x19u, 0x0Cu},\r
- {0x1Fu, 0x11u},\r
- {0x21u, 0x11u},\r
- {0x25u, 0x02u},\r
- {0x27u, 0xA8u},\r
- {0x29u, 0xC4u},\r
- {0x2Bu, 0x02u},\r
- {0x2Fu, 0x01u},\r
- {0x31u, 0xE0u},\r
- {0x33u, 0x01u},\r
- {0x35u, 0x0Eu},\r
- {0x37u, 0x10u},\r
- {0x39u, 0x20u},\r
- {0x3Fu, 0x44u},\r
- {0x40u, 0x36u},\r
- {0x41u, 0x04u},\r
- {0x42u, 0x10u},\r
- {0x44u, 0x05u},\r
- {0x45u, 0xCEu},\r
- {0x46u, 0xFDu},\r
- {0x47u, 0x0Bu},\r
- {0x48u, 0x1Fu},\r
- {0x49u, 0xFFu},\r
- {0x4Au, 0xFFu},\r
- {0x4Bu, 0xFFu},\r
- {0x4Cu, 0x22u},\r
- {0x4Eu, 0xF0u},\r
- {0x4Fu, 0x08u},\r
- {0x50u, 0x04u},\r
- {0x54u, 0x40u},\r
- {0x56u, 0x04u},\r
+ {0xC4u, 0x76u},\r
+ {0xCAu, 0xD6u},\r
+ {0xCCu, 0x7Bu},\r
+ {0xCEu, 0xF1u},\r
+ {0xD6u, 0x38u},\r
+ {0xD8u, 0x38u},\r
+ {0xE0u, 0x20u},\r
+ {0xE2u, 0x85u},\r
+ {0xE6u, 0xA0u},\r
+ {0xE8u, 0x01u},\r
+ {0xEAu, 0x02u},\r
+ {0xECu, 0x10u},\r
+ {0xEEu, 0x20u},\r
+ {0x00u, 0x24u},\r
+ {0x02u, 0x09u},\r
+ {0x05u, 0x50u},\r
+ {0x06u, 0x58u},\r
+ {0x07u, 0xA0u},\r
+ {0x09u, 0x60u},\r
+ {0x0Bu, 0x90u},\r
+ {0x0Du, 0x0Fu},\r
+ {0x0Fu, 0xF0u},\r
+ {0x11u, 0x30u},\r
+ {0x12u, 0x03u},\r
+ {0x13u, 0xC0u},\r
+ {0x15u, 0x06u},\r
+ {0x16u, 0x24u},\r
+ {0x17u, 0x09u},\r
+ {0x19u, 0x03u},\r
+ {0x1Bu, 0x0Cu},\r
+ {0x1Eu, 0x04u},\r
+ {0x20u, 0x24u},\r
+ {0x22u, 0x12u},\r
+ {0x25u, 0x05u},\r
+ {0x26u, 0x80u},\r
+ {0x27u, 0x0Au},\r
+ {0x2Au, 0x20u},\r
+ {0x2Cu, 0x40u},\r
+ {0x2Eu, 0x80u},\r
+ {0x30u, 0x07u},\r
+ {0x34u, 0x38u},\r
+ {0x36u, 0xC0u},\r
+ {0x37u, 0xFFu},\r
+ {0x3Eu, 0x40u},\r
+ {0x3Fu, 0x40u},\r
+ {0x58u, 0x04u},\r
{0x59u, 0x04u},\r
- {0x5Au, 0x04u},\r
{0x5Bu, 0x04u},\r
+ {0x5Cu, 0x01u},\r
{0x5Fu, 0x01u},\r
- {0x62u, 0xC0u},\r
- {0x64u, 0x40u},\r
- {0x65u, 0x01u},\r
- {0x66u, 0x10u},\r
- {0x67u, 0x11u},\r
- {0x68u, 0xC0u},\r
- {0x69u, 0x01u},\r
- {0x6Bu, 0x11u},\r
- {0x6Cu, 0x40u},\r
- {0x6Du, 0x01u},\r
- {0x6Eu, 0x40u},\r
- {0x6Fu, 0x01u},\r
- {0x80u, 0x07u},\r
- {0x81u, 0x6Cu},\r
- {0x82u, 0x18u},\r
- {0x84u, 0x04u},\r
- {0x85u, 0x64u},\r
- {0x87u, 0x08u},\r
- {0x88u, 0x10u},\r
- {0x8Au, 0x40u},\r
- {0x8Cu, 0x01u},\r
- {0x8Du, 0x2Cu},\r
- {0x8Fu, 0x40u},\r
- {0x90u, 0x01u},\r
- {0x91u, 0xA4u},\r
- {0x93u, 0x40u},\r
- {0x95u, 0x91u},\r
- {0x97u, 0x4Eu},\r
- {0x98u, 0x01u},\r
- {0x99u, 0xC0u},\r
- {0x9Bu, 0x2Fu},\r
- {0x9Cu, 0x01u},\r
- {0x9Du, 0x08u},\r
- {0x9Fu, 0x10u},\r
- {0xA0u, 0x01u},\r
- {0xA1u, 0x6Cu},\r
- {0xA4u, 0x08u},\r
- {0xA6u, 0x21u},\r
- {0xA8u, 0x22u},\r
- {0xA9u, 0x40u},\r
- {0xAAu, 0x08u},\r
- {0xABu, 0x2Cu},\r
- {0xADu, 0x71u},\r
- {0xAFu, 0x82u},\r
- {0xB0u, 0x3Fu},\r
- {0xB1u, 0xC0u},\r
- {0xB3u, 0x31u},\r
- {0xB4u, 0x40u},\r
- {0xB7u, 0x0Fu},\r
- {0xB8u, 0x02u},\r
- {0xBBu, 0x0Eu},\r
- {0xBEu, 0x01u},\r
+ {0x81u, 0x90u},\r
+ {0x83u, 0x48u},\r
+ {0x84u, 0x03u},\r
+ {0x86u, 0x0Cu},\r
+ {0x87u, 0x80u},\r
+ {0x88u, 0x50u},\r
+ {0x8Au, 0xA0u},\r
+ {0x8Bu, 0x0Du},\r
+ {0x8Cu, 0x90u},\r
+ {0x8Eu, 0x60u},\r
+ {0x8Fu, 0x02u},\r
+ {0x90u, 0x09u},\r
+ {0x91u, 0x90u},\r
+ {0x92u, 0x06u},\r
+ {0x93u, 0x24u},\r
+ {0x96u, 0xFFu},\r
+ {0x97u, 0x10u},\r
+ {0x9Bu, 0x60u},\r
+ {0x9Cu, 0x05u},\r
+ {0x9Eu, 0x0Au},\r
+ {0xA0u, 0xFFu},\r
+ {0xA4u, 0xFFu},\r
+ {0xA7u, 0x90u},\r
+ {0xA8u, 0x30u},\r
+ {0xAAu, 0xC0u},\r
+ {0xACu, 0x0Fu},\r
+ {0xADu, 0x01u},\r
+ {0xAEu, 0xF0u},\r
+ {0xAFu, 0x02u},\r
+ {0xB3u, 0xE0u},\r
+ {0xB4u, 0xFFu},\r
+ {0xB5u, 0x1Cu},\r
+ {0xB7u, 0x03u},\r
+ {0xBEu, 0x10u},\r
+ {0xBFu, 0x40u},\r
{0xD8u, 0x04u},\r
{0xD9u, 0x04u},\r
+ {0xDCu, 0x10u},\r
{0xDFu, 0x01u},\r
- {0x04u, 0x02u},\r
- {0x06u, 0x06u},\r
- {0x07u, 0x20u},\r
- {0x0Eu, 0x46u},\r
- {0x14u, 0x04u},\r
- {0x15u, 0x01u},\r
- {0x17u, 0x18u},\r
- {0x1Cu, 0x08u},\r
- {0x1Fu, 0x01u},\r
- {0x20u, 0x11u},\r
- {0x22u, 0x10u},\r
- {0x23u, 0x40u},\r
- {0x24u, 0x02u},\r
+ {0x00u, 0x04u},\r
+ {0x03u, 0x40u},\r
+ {0x05u, 0x40u},\r
+ {0x07u, 0x18u},\r
+ {0x08u, 0x08u},\r
+ {0x0Au, 0x42u},\r
+ {0x0Fu, 0xA2u},\r
+ {0x10u, 0x20u},\r
+ {0x11u, 0x40u},\r
+ {0x12u, 0x08u},\r
+ {0x13u, 0x01u},\r
+ {0x15u, 0x48u},\r
+ {0x17u, 0x22u},\r
+ {0x18u, 0x85u},\r
+ {0x1Au, 0x48u},\r
+ {0x1Bu, 0x01u},\r
+ {0x1Du, 0x10u},\r
+ {0x21u, 0x80u},\r
+ {0x23u, 0x02u},\r
+ {0x25u, 0x50u},\r
+ {0x26u, 0x20u},\r
+ {0x27u, 0x10u},\r
+ {0x2Au, 0x04u},\r
+ {0x2Du, 0x40u},\r
+ {0x2Fu, 0x20u},\r
+ {0x31u, 0x02u},\r
+ {0x32u, 0x24u},\r
+ {0x36u, 0x01u},\r
+ {0x37u, 0x14u},\r
+ {0x38u, 0x28u},\r
+ {0x39u, 0x40u},\r
+ {0x3Du, 0x20u},\r
+ {0x3Eu, 0x08u},\r
+ {0x3Fu, 0x41u},\r
+ {0x68u, 0x81u},\r
+ {0x69u, 0x20u},\r
+ {0x6Bu, 0x28u},\r
+ {0x70u, 0x3Cu},\r
+ {0x71u, 0x02u},\r
+ {0x72u, 0x02u},\r
+ {0x73u, 0x40u},\r
+ {0x81u, 0x40u},\r
+ {0x84u, 0x01u},\r
+ {0x85u, 0x40u},\r
+ {0x86u, 0x18u},\r
+ {0x87u, 0x20u},\r
+ {0x89u, 0x40u},\r
+ {0x8Au, 0x01u},\r
+ {0x8Eu, 0x09u},\r
+ {0x8Fu, 0x44u},\r
+ {0xC0u, 0xECu},\r
+ {0xC2u, 0xBDu},\r
+ {0xC4u, 0xFFu},\r
+ {0xCAu, 0x52u},\r
+ {0xCCu, 0xE7u},\r
+ {0xCEu, 0xFEu},\r
+ {0xE0u, 0x70u},\r
+ {0xE4u, 0x50u},\r
+ {0xE6u, 0x01u},\r
+ {0x84u, 0x08u},\r
+ {0x85u, 0x25u},\r
+ {0x86u, 0x13u},\r
+ {0x87u, 0x02u},\r
+ {0x89u, 0x38u},\r
+ {0x94u, 0x30u},\r
+ {0x95u, 0x09u},\r
+ {0x97u, 0x06u},\r
+ {0x98u, 0x16u},\r
+ {0x99u, 0x03u},\r
+ {0x9Au, 0x08u},\r
+ {0x9Bu, 0x14u},\r
+ {0x9Eu, 0x01u},\r
+ {0xA7u, 0x38u},\r
+ {0xA8u, 0x08u},\r
+ {0xA9u, 0x04u},\r
+ {0xAAu, 0x25u},\r
+ {0xABu, 0x03u},\r
+ {0xB2u, 0x38u},\r
+ {0xB5u, 0x07u},\r
+ {0xB6u, 0x07u},\r
+ {0xB7u, 0x38u},\r
+ {0xB8u, 0x08u},\r
+ {0xBBu, 0x20u},\r
+ {0xBFu, 0x40u},\r
+ {0xD6u, 0x02u},\r
+ {0xD7u, 0x24u},\r
+ {0xD8u, 0x04u},\r
+ {0xD9u, 0x04u},\r
+ {0xDBu, 0x04u},\r
+ {0xDFu, 0x01u},\r
+ {0x01u, 0x82u},\r
+ {0x03u, 0x18u},\r
+ {0x05u, 0x04u},\r
+ {0x09u, 0x01u},\r
+ {0x0Au, 0x08u},\r
+ {0x0Bu, 0x22u},\r
+ {0x0Eu, 0x25u},\r
+ {0x10u, 0x20u},\r
+ {0x11u, 0x40u},\r
+ {0x12u, 0x88u},\r
+ {0x17u, 0x10u},\r
+ {0x19u, 0x03u},\r
+ {0x1Au, 0x08u},\r
+ {0x1Cu, 0x20u},\r
+ {0x1Eu, 0x21u},\r
+ {0x22u, 0x08u},\r
{0x25u, 0x40u},\r
- {0x26u, 0x05u},\r
- {0x27u, 0x51u},\r
- {0x28u, 0x24u},\r
- {0x2Au, 0x42u},\r
- {0x2Du, 0x01u},\r
- {0x2Eu, 0x90u},\r
- {0x32u, 0x54u},\r
- {0x33u, 0x01u},\r
- {0x36u, 0x81u},\r
- {0x37u, 0x18u},\r
- {0x39u, 0x21u},\r
- {0x3Bu, 0x40u},\r
- {0x3Eu, 0x46u},\r
- {0x40u, 0x21u},\r
- {0x42u, 0x80u},\r
- {0x43u, 0x05u},\r
- {0x48u, 0x80u},\r
- {0x4Au, 0x86u},\r
+ {0x27u, 0x04u},\r
+ {0x29u, 0x41u},\r
+ {0x2Bu, 0x28u},\r
+ {0x2Du, 0x08u},\r
+ {0x2Eu, 0x20u},\r
+ {0x30u, 0x08u},\r
+ {0x32u, 0x80u},\r
+ {0x33u, 0x11u},\r
+ {0x35u, 0x04u},\r
+ {0x37u, 0x10u},\r
+ {0x38u, 0x80u},\r
+ {0x3Bu, 0x22u},\r
+ {0x3Cu, 0x20u},\r
+ {0x3Eu, 0x04u},\r
+ {0x40u, 0x06u},\r
+ {0x43u, 0x08u},\r
+ {0x46u, 0x20u},\r
+ {0x47u, 0x04u},\r
+ {0x48u, 0x41u},\r
+ {0x4Au, 0x84u},\r
{0x4Bu, 0x04u},\r
- {0x51u, 0x20u},\r
- {0x52u, 0x44u},\r
- {0x53u, 0x04u},\r
- {0x60u, 0x90u},\r
- {0x61u, 0x20u},\r
- {0x62u, 0x40u},\r
- {0x80u, 0x01u},\r
- {0x84u, 0x80u},\r
- {0x8Bu, 0x40u},\r
- {0x8Eu, 0x02u},\r
- {0x8Fu, 0x10u},\r
- {0x91u, 0x21u},\r
- {0x92u, 0xDCu},\r
- {0x94u, 0x03u},\r
- {0x96u, 0x20u},\r
- {0x97u, 0x0Eu},\r
- {0x9Au, 0x02u},\r
- {0x9Bu, 0x2Cu},\r
- {0x9Eu, 0x04u},\r
- {0x9Fu, 0x51u},\r
- {0xA4u, 0x84u},\r
- {0xA5u, 0x40u},\r
- {0xA6u, 0x01u},\r
- {0xA9u, 0x08u},\r
- {0xAAu, 0x02u},\r
- {0xACu, 0xC0u},\r
- {0xADu, 0x40u},\r
+ {0x50u, 0x84u},\r
+ {0x52u, 0x20u},\r
+ {0x66u, 0x20u},\r
+ {0x6Cu, 0x78u},\r
+ {0x6Du, 0x43u},\r
+ {0x6Fu, 0x21u},\r
+ {0x75u, 0xC0u},\r
+ {0x86u, 0x01u},\r
+ {0x88u, 0x40u},\r
+ {0x89u, 0x40u},\r
+ {0x8Cu, 0x02u},\r
+ {0x90u, 0x04u},\r
+ {0x92u, 0x04u},\r
+ {0x93u, 0x22u},\r
+ {0x94u, 0x28u},\r
+ {0x95u, 0x41u},\r
+ {0x97u, 0x04u},\r
+ {0x99u, 0x0Cu},\r
+ {0x9Bu, 0x10u},\r
+ {0x9Cu, 0x40u},\r
+ {0x9Du, 0x40u},\r
+ {0xA0u, 0x01u},\r
+ {0xA2u, 0x04u},\r
+ {0xA3u, 0x08u},\r
+ {0xA4u, 0xC8u},\r
+ {0xA6u, 0x20u},\r
+ {0xA7u, 0x20u},\r
+ {0xA9u, 0x02u},\r
+ {0xAEu, 0x80u},\r
+ {0xAFu, 0x20u},\r
{0xB0u, 0x80u},\r
+ {0xB1u, 0x10u},\r
+ {0xB2u, 0x80u},\r
{0xB3u, 0x10u},\r
- {0xB5u, 0x04u},\r
- {0xC0u, 0xF0u},\r
- {0xC2u, 0xD0u},\r
- {0xC4u, 0x70u},\r
- {0xCAu, 0xBFu},\r
- {0xCCu, 0xFFu},\r
- {0xCEu, 0xDDu},\r
- {0xD0u, 0x0Bu},\r
+ {0xC0u, 0x2Fu},\r
+ {0xC2u, 0xEFu},\r
+ {0xC4u, 0x4Fu},\r
+ {0xCAu, 0x6Fu},\r
+ {0xCCu, 0x6Fu},\r
+ {0xCEu, 0x6Du},\r
+ {0xD0u, 0x0Eu},\r
{0xD2u, 0x0Cu},\r
- {0xD8u, 0x0Fu},\r
- {0xE2u, 0x20u},\r
- {0xE4u, 0x14u},\r
- {0xEAu, 0x02u},\r
- {0xECu, 0x08u},\r
+ {0xD8u, 0x20u},\r
+ {0xE0u, 0x10u},\r
+ {0xE6u, 0x20u},\r
{0xEEu, 0x02u},\r
- {0x00u, 0xFFu},\r
+ {0x00u, 0xA4u},\r
{0x01u, 0xD6u},\r
- {0x04u, 0x0Fu},\r
- {0x05u, 0xD2u},\r
- {0x06u, 0xF0u},\r
- {0x07u, 0x04u},\r
+ {0x02u, 0x40u},\r
+ {0x04u, 0x71u},\r
+ {0x05u, 0x21u},\r
+ {0x06u, 0x82u},\r
+ {0x07u, 0x8Eu},\r
+ {0x08u, 0x64u},\r
{0x09u, 0x20u},\r
+ {0x0Au, 0x08u},\r
{0x0Bu, 0xD0u},\r
- {0x0Du, 0x17u},\r
- {0x0Eu, 0xFFu},\r
- {0x0Fu, 0x28u},\r
- {0x10u, 0x33u},\r
+ {0x0Cu, 0x6Cu},\r
{0x11u, 0x02u},\r
- {0x12u, 0xCCu},\r
- {0x14u, 0x96u},\r
- {0x15u, 0x29u},\r
- {0x16u, 0x69u},\r
- {0x17u, 0x46u},\r
- {0x19u, 0x21u},\r
- {0x1Au, 0xFFu},\r
- {0x1Bu, 0x8Eu},\r
- {0x20u, 0x55u},\r
+ {0x14u, 0x40u},\r
+ {0x15u, 0x17u},\r
+ {0x16u, 0x2Cu},\r
+ {0x17u, 0x28u},\r
+ {0x18u, 0xC0u},\r
+ {0x19u, 0x29u},\r
+ {0x1Au, 0x2Fu},\r
+ {0x1Bu, 0x46u},\r
+ {0x1Cu, 0x08u},\r
+ {0x1Du, 0xD6u},\r
+ {0x1Eu, 0x10u},\r
+ {0x20u, 0x6Cu},\r
{0x21u, 0x04u},\r
- {0x22u, 0xAAu},\r
- {0x25u, 0xD6u},\r
- {0x26u, 0xFFu},\r
- {0x28u, 0xFFu},\r
+ {0x25u, 0xD2u},\r
+ {0x27u, 0x04u},\r
+ {0x28u, 0x91u},\r
{0x29u, 0xD0u},\r
+ {0x2Au, 0x4Eu},\r
{0x2Bu, 0x06u},\r
+ {0x2Cu, 0x2Cu},\r
{0x2Du, 0xD6u},\r
- {0x31u, 0x01u},\r
- {0x33u, 0xF0u},\r
- {0x34u, 0xFFu},\r
- {0x35u, 0x0Fu},\r
+ {0x2Eu, 0x40u},\r
+ {0x30u, 0xC0u},\r
+ {0x32u, 0x0Fu},\r
+ {0x33u, 0x0Fu},\r
+ {0x34u, 0x31u},\r
+ {0x35u, 0xF0u},\r
{0x37u, 0x08u},\r
- {0x39u, 0x20u},\r
- {0x3Au, 0x20u},\r
- {0x3Bu, 0x08u},\r
- {0x3Fu, 0x41u},\r
+ {0x39u, 0x08u},\r
+ {0x3Au, 0x32u},\r
+ {0x3Bu, 0x20u},\r
+ {0x3Fu, 0x40u},\r
{0x54u, 0x09u},\r
{0x56u, 0x04u},\r
{0x58u, 0x04u},\r
{0x59u, 0x04u},\r
{0x5Bu, 0x04u},\r
- {0x5Cu, 0x01u},\r
{0x5Fu, 0x01u},\r
- {0x87u, 0x20u},\r
- {0x89u, 0x24u},\r
- {0x8Bu, 0x09u},\r
- {0x8Eu, 0x01u},\r
- {0x8Fu, 0x18u},\r
- {0x97u, 0x04u},\r
- {0x9Bu, 0x40u},\r
- {0x9Eu, 0x02u},\r
- {0x9Fu, 0x03u},\r
- {0xA5u, 0x24u},\r
- {0xA7u, 0x12u},\r
- {0xAFu, 0x24u},\r
- {0xB1u, 0x38u},\r
- {0xB2u, 0x02u},\r
- {0xB5u, 0x40u},\r
- {0xB6u, 0x01u},\r
- {0xB7u, 0x07u},\r
- {0xD6u, 0x02u},\r
- {0xD7u, 0x2Cu},\r
+ {0x80u, 0x02u},\r
+ {0x81u, 0x03u},\r
+ {0x82u, 0x30u},\r
+ {0x86u, 0x01u},\r
+ {0x87u, 0x01u},\r
+ {0x88u, 0x05u},\r
+ {0x89u, 0x03u},\r
+ {0x8Au, 0x38u},\r
+ {0x8Cu, 0x10u},\r
+ {0x8Eu, 0x20u},\r
+ {0x8Fu, 0x03u},\r
+ {0x90u, 0x01u},\r
+ {0x92u, 0x38u},\r
+ {0x94u, 0x10u},\r
+ {0x95u, 0x03u},\r
+ {0x96u, 0x20u},\r
+ {0x9Cu, 0x30u},\r
+ {0x9Eu, 0x08u},\r
+ {0xA8u, 0x34u},\r
+ {0xAAu, 0x08u},\r
+ {0xADu, 0x03u},\r
+ {0xB0u, 0x30u},\r
+ {0xB3u, 0x01u},\r
+ {0xB4u, 0x0Fu},\r
+ {0xB7u, 0x02u},\r
+ {0xB8u, 0x20u},\r
+ {0xBAu, 0x02u},\r
+ {0xBFu, 0x44u},\r
+ {0xD4u, 0x40u},\r
+ {0xD6u, 0x04u},\r
{0xD8u, 0x04u},\r
{0xD9u, 0x04u},\r
{0xDBu, 0x04u},\r
- {0xDCu, 0x11u},\r
+ {0xDCu, 0x01u},\r
{0xDFu, 0x01u},\r
- {0x00u, 0x80u},\r
- {0x04u, 0x04u},\r
- {0x05u, 0x82u},\r
+ {0x01u, 0x24u},\r
+ {0x03u, 0x42u},\r
+ {0x04u, 0x20u},\r
+ {0x05u, 0x45u},\r
+ {0x08u, 0x08u},\r
{0x0Au, 0x02u},\r
- {0x0Du, 0x02u},\r
- {0x0Eu, 0x20u},\r
- {0x0Fu, 0x08u},\r
- {0x16u, 0xA8u},\r
- {0x19u, 0x44u},\r
- {0x1Au, 0x02u},\r
+ {0x0Bu, 0x80u},\r
+ {0x0Cu, 0x88u},\r
+ {0x0Eu, 0x04u},\r
+ {0x10u, 0x04u},\r
+ {0x15u, 0x41u},\r
+ {0x17u, 0x10u},\r
+ {0x19u, 0x20u},\r
+ {0x1Bu, 0x03u},\r
{0x1Cu, 0x04u},\r
- {0x20u, 0x40u},\r
- {0x21u, 0x20u},\r
- {0x22u, 0x80u},\r
- {0x24u, 0x10u},\r
- {0x25u, 0x01u},\r
- {0x26u, 0x40u},\r
- {0x27u, 0x0Cu},\r
- {0x29u, 0x80u},\r
- {0x2Au, 0x08u},\r
- {0x2Cu, 0x80u},\r
- {0x2Du, 0x08u},\r
- {0x2Eu, 0x50u},\r
+ {0x1Du, 0x05u},\r
+ {0x1Eu, 0x04u},\r
+ {0x1Fu, 0x19u},\r
+ {0x20u, 0x02u},\r
+ {0x22u, 0x08u},\r
+ {0x23u, 0x01u},\r
+ {0x25u, 0x10u},\r
+ {0x26u, 0x44u},\r
+ {0x27u, 0x10u},\r
+ {0x29u, 0x40u},\r
+ {0x2Cu, 0x88u},\r
+ {0x2Du, 0x40u},\r
+ {0x2Fu, 0x20u},\r
{0x30u, 0x08u},\r
- {0x32u, 0xA0u},\r
- {0x36u, 0x01u},\r
- {0x37u, 0x18u},\r
- {0x38u, 0x60u},\r
- {0x39u, 0x04u},\r
- {0x3Cu, 0x10u},\r
- {0x3Du, 0x81u},\r
- {0x3Eu, 0x04u},\r
- {0x5Cu, 0x01u},\r
+ {0x35u, 0x45u},\r
+ {0x37u, 0x10u},\r
+ {0x38u, 0x28u},\r
+ {0x39u, 0x41u},\r
+ {0x3Cu, 0x04u},\r
+ {0x3Du, 0x21u},\r
+ {0x4Cu, 0x04u},\r
+ {0x4Du, 0x10u},\r
{0x5Eu, 0x80u},\r
- {0x5Fu, 0x14u},\r
- {0x60u, 0x80u},\r
- {0x64u, 0x02u},\r
- {0x67u, 0x40u},\r
- {0x69u, 0x21u},\r
- {0x6Au, 0xDCu},\r
- {0x72u, 0x02u},\r
- {0x73u, 0x01u},\r
- {0x7Cu, 0x02u},\r
- {0x7Du, 0x02u},\r
- {0x80u, 0x40u},\r
- {0x82u, 0x20u},\r
- {0x85u, 0x20u},\r
- {0x86u, 0x80u},\r
- {0x87u, 0x40u},\r
- {0x8Au, 0x90u},\r
- {0x8Fu, 0x08u},\r
- {0x90u, 0x20u},\r
+ {0x5Fu, 0x15u},\r
+ {0x61u, 0x02u},\r
+ {0x62u, 0xA8u},\r
+ {0x64u, 0x80u},\r
+ {0x66u, 0x80u},\r
{0x91u, 0x04u},\r
- {0x94u, 0x06u},\r
- {0x95u, 0x01u},\r
- {0x96u, 0x74u},\r
- {0x97u, 0x0Bu},\r
- {0x99u, 0x82u},\r
- {0x9Au, 0x28u},\r
- {0x9Bu, 0x20u},\r
- {0x9Eu, 0x04u},\r
- {0x9Fu, 0x59u},\r
- {0xA0u, 0x08u},\r
- {0xA1u, 0x02u},\r
- {0xA3u, 0x04u},\r
- {0xA4u, 0x04u},\r
- {0xABu, 0x04u},\r
- {0xB0u, 0x40u},\r
- {0xB6u, 0x12u},\r
- {0xC0u, 0xB1u},\r
- {0xC2u, 0x71u},\r
- {0xC4u, 0x70u},\r
- {0xCAu, 0xFAu},\r
- {0xCCu, 0xEEu},\r
- {0xCEu, 0xFEu},\r
+ {0x92u, 0x02u},\r
+ {0x93u, 0x80u},\r
+ {0x97u, 0x20u},\r
+ {0x98u, 0x0Cu},\r
+ {0x99u, 0x08u},\r
+ {0x9Bu, 0x60u},\r
+ {0x9Cu, 0xC0u},\r
+ {0x9Du, 0x20u},\r
+ {0x9Fu, 0x10u},\r
+ {0xA4u, 0x40u},\r
+ {0xA7u, 0x09u},\r
+ {0xAAu, 0x40u},\r
+ {0xB0u, 0x04u},\r
+ {0xB4u, 0x80u},\r
+ {0xC0u, 0xFFu},\r
+ {0xC2u, 0xEDu},\r
+ {0xC4u, 0xD2u},\r
+ {0xCAu, 0xF8u},\r
+ {0xCCu, 0xF2u},\r
+ {0xCEu, 0xEFu},\r
{0xD6u, 0xF0u},\r
- {0xD8u, 0x91u},\r
- {0xE0u, 0x08u},\r
- {0xE4u, 0x0Cu},\r
- {0xE6u, 0x01u},\r
- {0xEAu, 0x02u},\r
+ {0xD8u, 0x9Fu},\r
+ {0xEAu, 0x12u},\r
{0xEEu, 0x08u},\r
- {0x00u, 0x02u},\r
- {0x02u, 0x01u},\r
- {0x04u, 0x02u},\r
- {0x05u, 0x08u},\r
- {0x06u, 0x01u},\r
- {0x08u, 0x02u},\r
- {0x0Au, 0x11u},\r
- {0x0Cu, 0x01u},\r
- {0x0Du, 0x01u},\r
- {0x0Eu, 0x02u},\r
- {0x0Fu, 0x06u},\r
- {0x11u, 0x08u},\r
- {0x14u, 0x02u},\r
- {0x15u, 0x03u},\r
- {0x16u, 0x01u},\r
- {0x17u, 0x04u},\r
- {0x19u, 0x04u},\r
- {0x1Bu, 0x03u},\r
- {0x1Cu, 0x02u},\r
- {0x1Eu, 0x01u},\r
- {0x21u, 0x08u},\r
- {0x24u, 0x02u},\r
- {0x25u, 0x08u},\r
- {0x26u, 0x05u},\r
- {0x28u, 0x02u},\r
- {0x2Au, 0x09u},\r
- {0x2Du, 0x05u},\r
- {0x2Fu, 0x02u},\r
- {0x30u, 0x03u},\r
- {0x32u, 0x10u},\r
- {0x33u, 0x08u},\r
- {0x34u, 0x04u},\r
- {0x35u, 0x07u},\r
- {0x36u, 0x08u},\r
- {0x39u, 0x08u},\r
- {0x3Au, 0x02u},\r
- {0x3Bu, 0x20u},\r
- {0x3Fu, 0x04u},\r
- {0x56u, 0x08u},\r
- {0x58u, 0x04u},\r
- {0x59u, 0x04u},\r
- {0x5Bu, 0x04u},\r
- {0x5Cu, 0x01u},\r
- {0x5Du, 0x90u},\r
- {0x5Fu, 0x01u},\r
- {0x81u, 0x02u},\r
- {0x82u, 0x08u},\r
- {0x83u, 0x01u},\r
- {0x85u, 0x02u},\r
- {0x87u, 0x05u},\r
- {0x89u, 0x02u},\r
- {0x8Au, 0x10u},\r
- {0x8Bu, 0x11u},\r
- {0x8Cu, 0x01u},\r
- {0x8Du, 0x02u},\r
- {0x8Fu, 0x01u},\r
- {0x94u, 0x0Au},\r
- {0x95u, 0x02u},\r
- {0x96u, 0x14u},\r
- {0x97u, 0x09u},\r
- {0x99u, 0x01u},\r
- {0x9Bu, 0x02u},\r
- {0x9Du, 0x02u},\r
- {0x9Eu, 0x02u},\r
- {0x9Fu, 0x01u},\r
- {0xA9u, 0x02u},\r
- {0xAAu, 0x04u},\r
- {0xABu, 0x01u},\r
- {0xB0u, 0x01u},\r
- {0xB1u, 0x10u},\r
- {0xB2u, 0x18u},\r
- {0xB3u, 0x08u},\r
- {0xB4u, 0x06u},\r
- {0xB5u, 0x03u},\r
- {0xB7u, 0x04u},\r
- {0xBBu, 0x20u},\r
- {0xBEu, 0x14u},\r
- {0xD6u, 0x08u},\r
+ {0xB8u, 0x08u},\r
+ {0xBEu, 0x04u},\r
{0xD8u, 0x04u},\r
- {0xD9u, 0x04u},\r
- {0xDBu, 0x04u},\r
- {0xDCu, 0x19u},\r
- {0xDDu, 0x90u},\r
{0xDFu, 0x01u},\r
- {0x00u, 0x82u},\r
- {0x01u, 0x10u},\r
- {0x03u, 0x01u},\r
- {0x04u, 0x08u},\r
- {0x05u, 0x12u},\r
- {0x07u, 0x01u},\r
- {0x08u, 0x08u},\r
- {0x09u, 0x40u},\r
- {0x0Du, 0x08u},\r
- {0x0Eu, 0x02u},\r
- {0x13u, 0x10u},\r
- {0x16u, 0x20u},\r
- {0x17u, 0x10u},\r
- {0x19u, 0x04u},\r
- {0x1Au, 0x40u},\r
- {0x1Bu, 0x10u},\r
- {0x1Cu, 0x80u},\r
- {0x1Du, 0x18u},\r
- {0x1Eu, 0x02u},\r
- {0x1Fu, 0x02u},\r
- {0x20u, 0x10u},\r
- {0x21u, 0xA1u},\r
- {0x22u, 0x10u},\r
- {0x23u, 0x02u},\r
- {0x24u, 0x20u},\r
- {0x26u, 0x20u},\r
- {0x2Bu, 0x04u},\r
- {0x2Du, 0x80u},\r
- {0x2Fu, 0xA0u},\r
- {0x31u, 0xA0u},\r
- {0x32u, 0x04u},\r
- {0x36u, 0x2Au},\r
- {0x38u, 0x14u},\r
- {0x39u, 0x02u},\r
- {0x3Bu, 0x80u},\r
- {0x3Cu, 0x48u},\r
- {0x58u, 0x20u},\r
- {0x5Bu, 0x40u},\r
- {0x5Fu, 0x60u},\r
- {0x60u, 0x04u},\r
- {0x63u, 0x02u},\r
- {0x64u, 0x01u},\r
- {0x66u, 0x20u},\r
- {0x67u, 0x02u},\r
- {0x80u, 0x10u},\r
- {0x81u, 0x40u},\r
- {0x83u, 0x02u},\r
- {0x84u, 0x01u},\r
- {0x85u, 0x44u},\r
- {0x87u, 0x40u},\r
- {0x88u, 0x01u},\r
- {0x8Bu, 0x41u},\r
- {0x8Eu, 0x08u},\r
- {0x8Fu, 0x40u},\r
- {0x91u, 0x10u},\r
- {0x92u, 0x0Au},\r
- {0x93u, 0x10u},\r
- {0x95u, 0x48u},\r
- {0x96u, 0x60u},\r
- {0x97u, 0x02u},\r
- {0x98u, 0x28u},\r
- {0x9Bu, 0x30u},\r
- {0x9Du, 0x60u},\r
- {0xA0u, 0x04u},\r
- {0xA1u, 0x40u},\r
- {0xA2u, 0x02u},\r
- {0xA3u, 0xA4u},\r
- {0xA7u, 0x12u},\r
- {0xB2u, 0x10u},\r
- {0xC0u, 0xFBu},\r
- {0xC2u, 0xA5u},\r
- {0xC4u, 0x62u},\r
- {0xCAu, 0xD4u},\r
- {0xCCu, 0xEEu},\r
- {0xCEu, 0x5Fu},\r
- {0xD6u, 0x3Cu},\r
- {0xD8u, 0x3Cu},\r
- {0xE0u, 0x04u},\r
- {0xE2u, 0x80u},\r
- {0xE4u, 0x40u},\r
- {0xE6u, 0x20u},\r
+ {0x1Bu, 0x08u},\r
+ {0xB3u, 0x08u},\r
+ {0xE8u, 0x20u},\r
{0xEAu, 0x02u},\r
- {0xECu, 0x20u},\r
{0xEEu, 0x08u},\r
- {0x80u, 0x40u},\r
- {0x86u, 0x01u},\r
- {0x8Du, 0x80u},\r
- {0x92u, 0x02u},\r
- {0x94u, 0x40u},\r
- {0x9Du, 0x80u},\r
- {0xA9u, 0x04u},\r
- {0xADu, 0x0Au},\r
- {0xAEu, 0x20u},\r
- {0xB4u, 0x04u},\r
- {0xB5u, 0x20u},\r
- {0xE4u, 0x42u},\r
- {0xE8u, 0x10u},\r
- {0xECu, 0x01u},\r
- {0x04u, 0x80u},\r
- {0x0Eu, 0x08u},\r
- {0x13u, 0x42u},\r
+ {0xAFu, 0x08u},\r
+ {0xE2u, 0x80u},\r
+ {0x06u, 0x02u},\r
+ {0x0Du, 0x20u},\r
+ {0x12u, 0x08u},\r
+ {0x13u, 0x02u},\r
{0x16u, 0x80u},\r
- {0x17u, 0x40u},\r
+ {0x17u, 0x80u},\r
{0x30u, 0x10u},\r
{0x33u, 0x01u},\r
- {0x35u, 0x01u},\r
- {0x37u, 0x80u},\r
- {0x3Au, 0x82u},\r
- {0x3Cu, 0x80u},\r
- {0x3Du, 0x04u},\r
- {0x42u, 0x08u},\r
- {0x67u, 0x80u},\r
+ {0x36u, 0x20u},\r
+ {0x37u, 0x04u},\r
+ {0x39u, 0x04u},\r
+ {0x3Au, 0x80u},\r
+ {0x3Cu, 0x01u},\r
+ {0x3Du, 0x10u},\r
+ {0x40u, 0x02u},\r
+ {0x5Bu, 0x08u},\r
{0x6Bu, 0x03u},\r
+ {0x89u, 0x10u},\r
{0xC0u, 0x80u},\r
{0xC2u, 0x80u},\r
{0xC4u, 0xF0u},\r
{0xCCu, 0xF0u},\r
{0xCEu, 0xF0u},\r
{0xD0u, 0x10u},\r
- {0xD8u, 0x80u},\r
- {0x32u, 0x20u},\r
- {0x33u, 0x01u},\r
- {0x37u, 0x44u},\r
+ {0xD6u, 0x40u},\r
+ {0x33u, 0x11u},\r
+ {0x36u, 0x01u},\r
+ {0x37u, 0x80u},\r
{0x39u, 0x80u},\r
- {0x5Bu, 0x20u},\r
- {0x5Cu, 0x10u},\r
- {0x67u, 0x08u},\r
- {0x82u, 0x04u},\r
- {0x8Bu, 0x40u},\r
- {0x90u, 0x80u},\r
- {0x95u, 0x04u},\r
- {0x97u, 0x80u},\r
- {0x9Bu, 0x40u},\r
- {0x9Cu, 0x10u},\r
- {0x9Du, 0x01u},\r
- {0x9Eu, 0x08u},\r
- {0xA2u, 0x24u},\r
- {0xABu, 0x80u},\r
- {0xAEu, 0x20u},\r
- {0xAFu, 0x40u},\r
- {0xB0u, 0x40u},\r
+ {0x5Au, 0x10u},\r
+ {0x5Eu, 0x80u},\r
+ {0x63u, 0x02u},\r
+ {0x8Au, 0x40u},\r
+ {0x94u, 0x01u},\r
+ {0x9Bu, 0x90u},\r
+ {0x9Cu, 0x12u},\r
+ {0x9Fu, 0x08u},\r
+ {0xA1u, 0x20u},\r
+ {0xA6u, 0x20u},\r
+ {0xAAu, 0x08u},\r
+ {0xABu, 0x14u},\r
+ {0xADu, 0x04u},\r
{0xB6u, 0x02u},\r
{0xCCu, 0xF0u},\r
{0xCEu, 0x10u},\r
{0xD4u, 0x80u},\r
- {0xD6u, 0x20u},\r
- {0xD8u, 0x80u},\r
- {0xE4u, 0x20u},\r
+ {0xD6u, 0x60u},\r
{0xEAu, 0x80u},\r
+ {0xEEu, 0x40u},\r
{0x10u, 0x10u},\r
- {0x33u, 0x80u},\r
- {0x8Du, 0x40u},\r
- {0x90u, 0x80u},\r
- {0x95u, 0x84u},\r
- {0x9Cu, 0x10u},\r
- {0x9Du, 0x01u},\r
- {0x9Eu, 0x08u},\r
- {0x9Fu, 0x05u},\r
- {0xAFu, 0x24u},\r
- {0xB4u, 0x10u},\r
+ {0x31u, 0x40u},\r
+ {0x94u, 0x01u},\r
+ {0x95u, 0x80u},\r
+ {0x96u, 0x10u},\r
+ {0x9Cu, 0x12u},\r
+ {0x9Fu, 0x09u},\r
+ {0xA6u, 0x01u},\r
+ {0xA7u, 0x01u},\r
+ {0xB1u, 0x20u},\r
+ {0xB6u, 0x20u},\r
{0xC4u, 0x10u},\r
{0xCCu, 0x10u},\r
- {0xEAu, 0x40u},\r
- {0xEEu, 0x10u},\r
- {0x6Bu, 0x40u},\r
- {0x81u, 0x01u},\r
- {0x83u, 0x40u},\r
- {0x8Cu, 0x40u},\r
- {0x90u, 0x80u},\r
- {0x95u, 0x04u},\r
- {0x9Du, 0x01u},\r
- {0x9Eu, 0x08u},\r
- {0x9Fu, 0x01u},\r
- {0xA7u, 0x80u},\r
- {0xABu, 0x04u},\r
- {0xDCu, 0x20u},\r
- {0xE2u, 0x20u},\r
- {0xE6u, 0x80u},\r
+ {0x82u, 0x11u},\r
+ {0x87u, 0x01u},\r
+ {0x94u, 0x01u},\r
+ {0x96u, 0x10u},\r
+ {0x9Cu, 0x02u},\r
+ {0x9Du, 0x40u},\r
+ {0x9Fu, 0x09u},\r
+ {0xA6u, 0x01u},\r
+ {0xA7u, 0x01u},\r
+ {0xA9u, 0x40u},\r
+ {0xE2u, 0x80u},\r
+ {0xE6u, 0x90u},\r
{0xEAu, 0x80u},\r
- {0x03u, 0x08u},\r
- {0x04u, 0x40u},\r
+ {0x02u, 0x01u},\r
+ {0x07u, 0x08u},\r
{0x09u, 0x80u},\r
- {0x0Cu, 0x80u},\r
- {0x12u, 0x20u},\r
- {0x15u, 0x04u},\r
- {0x5Fu, 0x02u},\r
- {0x65u, 0x20u},\r
- {0x8Fu, 0x02u},\r
+ {0x0Cu, 0x40u},\r
+ {0x10u, 0x20u},\r
+ {0x16u, 0x80u},\r
+ {0x60u, 0x20u},\r
+ {0x66u, 0x02u},\r
+ {0x81u, 0x80u},\r
+ {0x8Bu, 0x20u},\r
+ {0x8Eu, 0x02u},\r
{0xC0u, 0x03u},\r
{0xC2u, 0x03u},\r
{0xC4u, 0x0Cu},\r
- {0xD6u, 0x01u},\r
- {0xD8u, 0x01u},\r
- {0xE0u, 0x08u},\r
- {0x03u, 0x40u},\r
- {0x04u, 0x08u},\r
- {0x0Bu, 0x20u},\r
+ {0xD8u, 0x03u},\r
+ {0xE0u, 0x02u},\r
+ {0xE4u, 0x04u},\r
+ {0x00u, 0x08u},\r
+ {0x05u, 0x04u},\r
+ {0x0Au, 0x20u},\r
{0x0Cu, 0x08u},\r
- {0x51u, 0x80u},\r
- {0x55u, 0x40u},\r
- {0x5Du, 0x01u},\r
- {0x64u, 0x10u},\r
- {0x85u, 0x20u},\r
- {0x88u, 0x10u},\r
- {0x89u, 0x01u},\r
- {0x8Fu, 0x40u},\r
- {0x91u, 0x04u},\r
- {0x9Du, 0x20u},\r
- {0xA2u, 0x20u},\r
- {0xA3u, 0x08u},\r
- {0xB0u, 0x80u},\r
- {0xB4u, 0x40u},\r
- {0xB5u, 0x80u},\r
+ {0x52u, 0x80u},\r
+ {0x5Fu, 0x20u},\r
+ {0x66u, 0x84u},\r
+ {0x80u, 0x08u},\r
+ {0x82u, 0x01u},\r
+ {0x88u, 0x40u},\r
+ {0x98u, 0x40u},\r
+ {0x9Au, 0x05u},\r
+ {0x9Bu, 0x28u},\r
+ {0x9Cu, 0x20u},\r
+ {0xAAu, 0x04u},\r
+ {0xAEu, 0x80u},\r
+ {0xB0u, 0x20u},\r
{0xC0u, 0x0Cu},\r
{0xC2u, 0x0Cu},\r
- {0xD4u, 0x06u},\r
- {0xD6u, 0x01u},\r
+ {0xD4u, 0x04u},\r
+ {0xD6u, 0x05u},\r
{0xD8u, 0x01u},\r
- {0xE0u, 0x04u},\r
- {0xE2u, 0x08u},\r
- {0xE4u, 0x01u},\r
- {0xEAu, 0x0Au},\r
- {0xEEu, 0x01u},\r
- {0x83u, 0x08u},\r
- {0x8Du, 0x10u},\r
- {0x90u, 0x08u},\r
- {0x91u, 0x04u},\r
- {0x93u, 0x20u},\r
- {0xA0u, 0x08u},\r
- {0xA3u, 0x08u},\r
- {0xA5u, 0xC0u},\r
- {0xAEu, 0x20u},\r
- {0xE6u, 0x08u},\r
- {0x09u, 0x18u},\r
- {0x0Du, 0x02u},\r
- {0x0Fu, 0x02u},\r
- {0x89u, 0x40u},\r
+ {0xE2u, 0x01u},\r
+ {0xEEu, 0x04u},\r
+ {0x83u, 0x20u},\r
+ {0x8Bu, 0x08u},\r
+ {0x8Du, 0x04u},\r
+ {0x99u, 0x04u},\r
+ {0x9Bu, 0x08u},\r
+ {0x9Cu, 0x20u},\r
+ {0xAAu, 0x80u},\r
+ {0xB0u, 0x04u},\r
+ {0xB2u, 0x80u},\r
+ {0xB6u, 0x10u},\r
+ {0xE4u, 0x02u},\r
+ {0xE6u, 0x01u},\r
+ {0xEAu, 0x06u},\r
+ {0xECu, 0x04u},\r
+ {0x09u, 0x08u},\r
+ {0x0Bu, 0x01u},\r
+ {0x0Fu, 0x22u},\r
+ {0x83u, 0x10u},\r
+ {0x86u, 0x20u},\r
{0x8Du, 0x10u},\r
- {0x90u, 0x08u},\r
- {0x93u, 0x20u},\r
- {0x95u, 0x40u},\r
- {0xA5u, 0x52u},\r
- {0xA9u, 0x42u},\r
- {0xACu, 0x08u},\r
- {0xB1u, 0x04u},\r
- {0xB5u, 0x80u},\r
+ {0x97u, 0x01u},\r
+ {0xA1u, 0x04u},\r
+ {0xA3u, 0x20u},\r
+ {0xABu, 0x01u},\r
+ {0xACu, 0x20u},\r
+ {0xB5u, 0x04u},\r
{0xC2u, 0x0Fu},\r
{0xE2u, 0x02u},\r
- {0xE4u, 0x04u},\r
- {0xE8u, 0x08u},\r
- {0xEAu, 0x04u},\r
- {0x86u, 0x08u},\r
- {0x95u, 0x04u},\r
- {0x9Eu, 0x08u},\r
- {0xA1u, 0x02u},\r
- {0xA9u, 0x02u},\r
- {0xAFu, 0x81u},\r
- {0xE6u, 0x40u},\r
- {0xEAu, 0xC0u},\r
+ {0xEAu, 0x08u},\r
+ {0x67u, 0x40u},\r
+ {0x94u, 0x01u},\r
+ {0xABu, 0x08u},\r
+ {0xADu, 0x40u},\r
+ {0xAFu, 0x01u},\r
+ {0xB4u, 0x02u},\r
+ {0xD8u, 0x80u},\r
+ {0xEAu, 0x60u},\r
{0xEEu, 0x10u},\r
- {0x06u, 0x80u},\r
- {0x51u, 0x02u},\r
- {0x53u, 0x10u},\r
- {0x85u, 0x04u},\r
- {0x8Bu, 0x10u},\r
- {0x8Eu, 0x80u},\r
- {0x95u, 0x04u},\r
- {0xA1u, 0x02u},\r
- {0xC0u, 0x20u},\r
- {0xD4u, 0xA0u},\r
- {0xE6u, 0x40u},\r
- {0x7Fu, 0x02u},\r
- {0x83u, 0x02u},\r
- {0x8Bu, 0x10u},\r
+ {0x04u, 0x08u},\r
+ {0x51u, 0x10u},\r
+ {0x56u, 0x40u},\r
+ {0x86u, 0x40u},\r
+ {0x89u, 0x10u},\r
{0x8Cu, 0x04u},\r
- {0x90u, 0x08u},\r
- {0x93u, 0x20u},\r
- {0x95u, 0x40u},\r
+ {0xA8u, 0x01u},\r
+ {0xAFu, 0x40u},\r
+ {0xC0u, 0x20u},\r
+ {0xD4u, 0x60u},\r
+ {0xE2u, 0x10u},\r
+ {0xEAu, 0x80u},\r
+ {0xEEu, 0x40u},\r
+ {0x76u, 0x20u},\r
+ {0x9Au, 0x20u},\r
{0x9Du, 0x10u},\r
+ {0xA1u, 0x04u},\r
+ {0xA3u, 0x20u},\r
{0xADu, 0x08u},\r
{0xAFu, 0x01u},\r
{0xDEu, 0x04u},\r
- {0xE2u, 0x0Cu},\r
- {0x01u, 0x40u},\r
+ {0x01u, 0x10u},\r
{0x05u, 0x10u},\r
- {0x53u, 0x10u},\r
- {0x5Du, 0x20u},\r
- {0x87u, 0x10u},\r
- {0x95u, 0x40u},\r
- {0x99u, 0x20u},\r
+ {0x53u, 0x20u},\r
+ {0x55u, 0x04u},\r
+ {0x89u, 0x10u},\r
{0x9Du, 0x10u},\r
- {0xA9u, 0x20u},\r
+ {0xA1u, 0x04u},\r
+ {0xA3u, 0x20u},\r
{0xC0u, 0x03u},\r
- {0xD4u, 0x04u},\r
- {0xD6u, 0x04u},\r
+ {0xD4u, 0x06u},\r
+ {0xE2u, 0x01u},\r
{0x10u, 0x03u},\r
- {0x11u, 0x01u},\r
{0x1Au, 0x03u},\r
- {0x1Cu, 0x03u},\r
- {0x1Du, 0x01u},\r
{0x00u, 0xFFu},\r
{0x01u, 0xBFu},\r
{0x02u, 0x2Au},\r
/* address, size */\r
{(void CYFAR *)(CYREG_TMR0_CFG0), 12u},\r
{(void CYFAR *)(CYDEV_UCFG_B0_P0_U0_BASE), 4096u},\r
- {(void CYFAR *)(CYDEV_UCFG_B1_P2_U0_BASE), 2048u},\r
+ {(void CYFAR *)(CYDEV_UCFG_B1_P2_U1_BASE), 1920u},\r
{(void CYFAR *)(CYDEV_UCFG_DSI0_BASE), 2560u},\r
{(void CYFAR *)(CYDEV_UCFG_DSI12_BASE), 512u},\r
{(void CYFAR *)(CYREG_BCTL1_MDCLK_EN), 16u},\r
};\r
\r
+ /* UDB_1_0_0_CONFIG Address: CYDEV_UCFG_B1_P2_U0_BASE Size (bytes): 128 */\r
+ static const uint8 CYCODE BS_UDB_1_0_0_CONFIG_VAL[] = {\r
+ 0x04u, 0x80u, 0x00u, 0x00u, 0x08u, 0x00u, 0x21u, 0x00u, 0x07u, 0x7Fu, 0x18u, 0x80u, 0x01u, 0xC0u, 0x00u, 0x02u, \r
+ 0x01u, 0x90u, 0x00u, 0x40u, 0x22u, 0xC0u, 0x08u, 0x08u, 0x40u, 0x00u, 0x00u, 0xFFu, 0x01u, 0x00u, 0x00u, 0x9Fu, \r
+ 0x10u, 0x00u, 0x00u, 0x60u, 0x01u, 0xC0u, 0x00u, 0x04u, 0x40u, 0x1Fu, 0x00u, 0x20u, 0x01u, 0xC0u, 0x00u, 0x01u, \r
+ 0x40u, 0x00u, 0x00u, 0xFFu, 0x3Fu, 0x00u, 0x00u, 0x00u, 0x22u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x10u, 0x04u, \r
+ 0x62u, 0x03u, 0x50u, 0x00u, 0x01u, 0xBEu, 0xFCu, 0x0Du, 0x1Fu, 0xFFu, 0xFFu, 0xFFu, 0x22u, 0x00u, 0xF0u, 0x08u, \r
+ 0x04u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x04u, 0x04u, 0x04u, 0x00u, 0x00u, 0x00u, 0x00u, 0x01u, \r
+ 0x00u, 0x00u, 0xC0u, 0x00u, 0x40u, 0x01u, 0x10u, 0x11u, 0xC0u, 0x01u, 0x00u, 0x11u, 0x40u, 0x01u, 0x40u, 0x01u, \r
+ 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u};\r
+\r
/* UCFG_BCTL0 Address: CYREG_BCTL0_MDCLK_EN Size (bytes): 16 */\r
static const uint8 CYCODE BS_UCFG_BCTL0_VAL[] = {\r
- 0x03u, 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x01u, 0x03u, 0x01u, 0x02u, 0x00u, 0x02u, 0x01u};\r
+ 0x03u, 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x01u, 0x03u, 0x01u, 0x02u, 0x01u, 0x02u, 0x01u};\r
\r
static const cfg_memcpy_t CYCODE cfg_memcpy_list [] = {\r
/* dest, src, size */\r
+ {(void CYFAR *)(CYDEV_UCFG_B1_P2_U0_BASE), BS_UDB_1_0_0_CONFIG_VAL, 128u},\r
{(void CYFAR *)(CYREG_BCTL0_MDCLK_EN), BS_UCFG_BCTL0_VAL, 16u},\r
};\r
\r
.set EXTLED__SLW, CYREG_PRT0_SLW\r
\r
/* SDCard */\r
-.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB07_08_ACTL\r
-.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB07_08_CTL\r
-.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB07_08_CTL\r
-.set SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB07_08_CTL\r
-.set SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB07_08_CTL\r
-.set SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B1_UDB07_08_MSK\r
-.set SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB07_08_MSK\r
-.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB07_08_MSK\r
-.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB07_08_MSK\r
-.set SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B1_UDB07_ACTL\r
-.set SDCard_BSPIM_BitCounter__CONTROL_REG, CYREG_B1_UDB07_CTL\r
-.set SDCard_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B1_UDB07_ST_CTL\r
-.set SDCard_BSPIM_BitCounter__COUNT_REG, CYREG_B1_UDB07_CTL\r
-.set SDCard_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B1_UDB07_ST_CTL\r
-.set SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB07_MSK_ACTL\r
-.set SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB07_MSK_ACTL\r
-.set SDCard_BSPIM_BitCounter__PERIOD_REG, CYREG_B1_UDB07_MSK\r
-.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB07_08_ACTL\r
-.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B1_UDB07_08_ST\r
-.set SDCard_BSPIM_BitCounter_ST__MASK_REG, CYREG_B1_UDB07_MSK\r
-.set SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B1_UDB07_MSK_ACTL\r
-.set SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B1_UDB07_MSK_ACTL\r
-.set SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B1_UDB07_ACTL\r
-.set SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B1_UDB07_ST_CTL\r
-.set SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B1_UDB07_ST_CTL\r
-.set SDCard_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B1_UDB07_ST\r
-.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB04_05_ACTL\r
-.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB04_05_ST\r
+.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB05_06_ACTL\r
+.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB05_06_CTL\r
+.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB05_06_CTL\r
+.set SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB05_06_CTL\r
+.set SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB05_06_CTL\r
+.set SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B1_UDB05_06_MSK\r
+.set SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB05_06_MSK\r
+.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB05_06_MSK\r
+.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB05_06_MSK\r
+.set SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B1_UDB05_ACTL\r
+.set SDCard_BSPIM_BitCounter__CONTROL_REG, CYREG_B1_UDB05_CTL\r
+.set SDCard_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B1_UDB05_ST_CTL\r
+.set SDCard_BSPIM_BitCounter__COUNT_REG, CYREG_B1_UDB05_CTL\r
+.set SDCard_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B1_UDB05_ST_CTL\r
+.set SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB05_MSK_ACTL\r
+.set SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB05_MSK_ACTL\r
+.set SDCard_BSPIM_BitCounter__PERIOD_REG, CYREG_B1_UDB05_MSK\r
+.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB05_06_ACTL\r
+.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B1_UDB05_06_ST\r
+.set SDCard_BSPIM_BitCounter_ST__MASK_REG, CYREG_B1_UDB05_MSK\r
+.set SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B1_UDB05_MSK_ACTL\r
+.set SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B1_UDB05_MSK_ACTL\r
+.set SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B1_UDB05_ACTL\r
+.set SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B1_UDB05_ST_CTL\r
+.set SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B1_UDB05_ST_CTL\r
+.set SDCard_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B1_UDB05_ST\r
+.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB07_08_ACTL\r
+.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB07_08_ST\r
.set SDCard_BSPIM_RxStsReg__4__MASK, 0x10\r
.set SDCard_BSPIM_RxStsReg__4__POS, 4\r
.set SDCard_BSPIM_RxStsReg__5__MASK, 0x20\r
.set SDCard_BSPIM_RxStsReg__6__MASK, 0x40\r
.set SDCard_BSPIM_RxStsReg__6__POS, 6\r
.set SDCard_BSPIM_RxStsReg__MASK, 0x70\r
-.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B1_UDB04_MSK\r
-.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB04_ACTL\r
-.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B1_UDB04_ST\r
+.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B1_UDB07_MSK\r
+.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB07_ACTL\r
+.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B1_UDB07_ST\r
.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG, CYREG_B1_UDB04_05_A0\r
.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG, CYREG_B1_UDB04_05_A1\r
.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG, CYREG_B1_UDB04_05_D0\r
.set SCSI_Out_Bits_Sync_ctrl_reg__0__POS, 0\r
.set SCSI_Out_Bits_Sync_ctrl_reg__1__MASK, 0x02\r
.set SCSI_Out_Bits_Sync_ctrl_reg__1__POS, 1\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB10_11_ACTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB10_11_CTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB10_11_CTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB10_11_CTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB10_11_CTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB10_11_MSK\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB10_11_MSK\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB10_11_MSK\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB10_11_MSK\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB14_15_ACTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB14_15_CTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB14_15_CTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB14_15_CTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB14_15_CTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB14_15_MSK\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB14_15_MSK\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB14_15_MSK\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB14_15_MSK\r
.set SCSI_Out_Bits_Sync_ctrl_reg__2__MASK, 0x04\r
.set SCSI_Out_Bits_Sync_ctrl_reg__2__POS, 2\r
.set SCSI_Out_Bits_Sync_ctrl_reg__3__MASK, 0x08\r
.set SCSI_Out_Bits_Sync_ctrl_reg__6__POS, 6\r
.set SCSI_Out_Bits_Sync_ctrl_reg__7__MASK, 0x80\r
.set SCSI_Out_Bits_Sync_ctrl_reg__7__POS, 7\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB10_ACTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB10_CTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB10_ST_CTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB10_CTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB10_ST_CTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB14_ACTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB14_CTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB14_ST_CTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB14_CTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB14_ST_CTL\r
.set SCSI_Out_Bits_Sync_ctrl_reg__MASK, 0xFF\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB10_MSK_ACTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB10_MSK_ACTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB10_MSK\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB14_MSK_ACTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB14_MSK_ACTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB14_MSK\r
.set SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK, 0x01\r
.set SCSI_Out_Ctl_Sync_ctrl_reg__0__POS, 0\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB07_08_ACTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB07_08_CTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB07_08_CTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB07_08_CTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB07_08_CTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB07_08_MSK\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB07_08_MSK\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB07_08_MSK\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB07_08_MSK\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB07_ACTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB07_CTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB07_ST_CTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB07_CTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB07_ST_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB12_13_ACTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB12_13_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB12_13_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB12_13_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB12_13_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB12_13_MSK\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB12_13_MSK\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB12_13_MSK\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB12_13_MSK\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB12_ACTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB12_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB12_ST_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB12_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB12_ST_CTL\r
.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK, 0x01\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB07_MSK_ACTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB07_MSK_ACTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB07_MSK\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB12_MSK\r
.set SCSI_Out_DBx__0__AG, CYREG_PRT5_AG\r
.set SCSI_Out_DBx__0__AMUX, CYREG_PRT5_AMUX\r
.set SCSI_Out_DBx__0__BIE, CYREG_PRT5_BIE\r
.set scsiTarget_StatusReg__0__POS, 0\r
.set scsiTarget_StatusReg__1__MASK, 0x02\r
.set scsiTarget_StatusReg__1__POS, 1\r
-.set scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB07_08_ACTL\r
-.set scsiTarget_StatusReg__16BIT_STATUS_REG, CYREG_B0_UDB07_08_ST\r
+.set scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB02_03_ACTL\r
+.set scsiTarget_StatusReg__16BIT_STATUS_REG, CYREG_B0_UDB02_03_ST\r
.set scsiTarget_StatusReg__2__MASK, 0x04\r
.set scsiTarget_StatusReg__2__POS, 2\r
.set scsiTarget_StatusReg__3__MASK, 0x08\r
.set scsiTarget_StatusReg__4__MASK, 0x10\r
.set scsiTarget_StatusReg__4__POS, 4\r
.set scsiTarget_StatusReg__MASK, 0x1F\r
-.set scsiTarget_StatusReg__MASK_REG, CYREG_B0_UDB07_MSK\r
-.set scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB07_MSK_ACTL\r
-.set scsiTarget_StatusReg__PER_ST_AUX_CTL_REG, CYREG_B0_UDB07_MSK_ACTL\r
-.set scsiTarget_StatusReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB07_ACTL\r
-.set scsiTarget_StatusReg__STATUS_CNT_REG, CYREG_B0_UDB07_ST_CTL\r
-.set scsiTarget_StatusReg__STATUS_CONTROL_REG, CYREG_B0_UDB07_ST_CTL\r
-.set scsiTarget_StatusReg__STATUS_REG, CYREG_B0_UDB07_ST\r
+.set scsiTarget_StatusReg__MASK_REG, CYREG_B0_UDB02_MSK\r
+.set scsiTarget_StatusReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB02_ACTL\r
+.set scsiTarget_StatusReg__STATUS_REG, CYREG_B0_UDB02_ST\r
\r
/* Debug_Timer */\r
.set Debug_Timer_Interrupt__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
.set SCSI_Filtered_sts_sts_reg__0__POS, 0\r
.set SCSI_Filtered_sts_sts_reg__1__MASK, 0x02\r
.set SCSI_Filtered_sts_sts_reg__1__POS, 1\r
-.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB13_14_ACTL\r
-.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB13_14_ST\r
+.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB11_12_ACTL\r
+.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB11_12_ST\r
.set SCSI_Filtered_sts_sts_reg__2__MASK, 0x04\r
.set SCSI_Filtered_sts_sts_reg__2__POS, 2\r
.set SCSI_Filtered_sts_sts_reg__3__MASK, 0x08\r
.set SCSI_Filtered_sts_sts_reg__4__MASK, 0x10\r
.set SCSI_Filtered_sts_sts_reg__4__POS, 4\r
.set SCSI_Filtered_sts_sts_reg__MASK, 0x1F\r
-.set SCSI_Filtered_sts_sts_reg__MASK_REG, CYREG_B0_UDB13_MSK\r
-.set SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB13_ACTL\r
-.set SCSI_Filtered_sts_sts_reg__STATUS_REG, CYREG_B0_UDB13_ST\r
+.set SCSI_Filtered_sts_sts_reg__MASK_REG, CYREG_B0_UDB11_MSK\r
+.set SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB11_ACTL\r
+.set SCSI_Filtered_sts_sts_reg__STATUS_REG, CYREG_B0_UDB11_ST\r
\r
/* SCSI_CTL_PHASE */\r
.set SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK, 0x01\r
.set SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS, 0\r
.set SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK, 0x02\r
.set SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS, 1\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB02_03_ACTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB02_03_CTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB02_03_CTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB02_03_CTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB02_03_CTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB02_03_MSK\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB02_03_MSK\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB02_03_MSK\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB02_03_MSK\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB06_07_ACTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB06_07_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB06_07_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB06_07_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB06_07_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB06_07_MSK\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB06_07_MSK\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB06_07_MSK\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB06_07_MSK\r
.set SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK, 0x04\r
.set SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS, 2\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB02_ACTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB02_CTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB02_ST_CTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB02_CTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB02_ST_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB06_ACTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB06_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB06_ST_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB06_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB06_ST_CTL\r
.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK, 0x07\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB02_MSK_ACTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB02_MSK_ACTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB02_MSK\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB06_MSK_ACTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB06_MSK_ACTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB06_MSK\r
\r
/* SCSI_Glitch_Ctl */\r
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK, 0x01\r
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS, 0\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB03_04_ACTL\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB03_04_CTL\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB03_04_CTL\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB03_04_CTL\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB03_04_CTL\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB03_04_MSK\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB03_04_MSK\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB03_04_MSK\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB03_04_MSK\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB03_ACTL\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB03_CTL\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB03_ST_CTL\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB03_CTL\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB03_ST_CTL\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB04_05_ACTL\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB04_05_CTL\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB04_05_CTL\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB04_05_CTL\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB04_05_CTL\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB04_05_MSK\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB04_05_MSK\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB04_05_MSK\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB04_05_MSK\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB04_ACTL\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB04_CTL\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB04_ST_CTL\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB04_CTL\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB04_ST_CTL\r
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK, 0x01\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB03_MSK\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB04_MSK\r
\r
/* SCSI_Parity_Error */\r
.set SCSI_Parity_Error_sts_sts_reg__0__MASK, 0x01\r
.set SCSI_Parity_Error_sts_sts_reg__0__POS, 0\r
-.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB11_12_ACTL\r
-.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB11_12_ST\r
+.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB05_06_ACTL\r
+.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB05_06_ST\r
.set SCSI_Parity_Error_sts_sts_reg__MASK, 0x01\r
-.set SCSI_Parity_Error_sts_sts_reg__MASK_REG, CYREG_B0_UDB11_MSK\r
-.set SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB11_ACTL\r
-.set SCSI_Parity_Error_sts_sts_reg__STATUS_REG, CYREG_B0_UDB11_ST\r
+.set SCSI_Parity_Error_sts_sts_reg__MASK_REG, CYREG_B0_UDB05_MSK\r
+.set SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB05_ACTL\r
+.set SCSI_Parity_Error_sts_sts_reg__STATUS_REG, CYREG_B0_UDB05_ST\r
\r
/* Miscellaneous */\r
.set BCLK__BUS_CLK__HZ, 50000000\r
EXTLED__SLW EQU CYREG_PRT0_SLW\r
\r
/* SDCard */\r
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL\r
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB07_08_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB07_08_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB07_08_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB07_08_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB07_08_MSK\r
-SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB07_08_MSK\r
-SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB07_08_MSK\r
-SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB07_08_MSK\r
-SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL\r
-SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB07_CTL\r
-SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB07_ST_CTL\r
-SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB07_CTL\r
-SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB07_ST_CTL\r
-SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL\r
-SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL\r
-SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB07_MSK\r
-SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL\r
-SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST\r
-SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB07_MSK\r
-SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL\r
-SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB07_ST_CTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB07_ST_CTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB07_ST\r
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL\r
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB04_05_ST\r
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB05_06_ACTL\r
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB05_06_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB05_06_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB05_06_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB05_06_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB05_06_MSK\r
+SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB05_06_MSK\r
+SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB05_06_MSK\r
+SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB05_06_MSK\r
+SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB05_ACTL\r
+SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB05_CTL\r
+SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB05_ST_CTL\r
+SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB05_CTL\r
+SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB05_ST_CTL\r
+SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL\r
+SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL\r
+SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB05_MSK\r
+SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB05_06_ACTL\r
+SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB05_06_ST\r
+SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB05_MSK\r
+SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL\r
+SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB05_ACTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB05_ST_CTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB05_ST_CTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB05_ST\r
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL\r
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST\r
SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10\r
SDCard_BSPIM_RxStsReg__4__POS EQU 4\r
SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20\r
SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40\r
SDCard_BSPIM_RxStsReg__6__POS EQU 6\r
SDCard_BSPIM_RxStsReg__MASK EQU 0x70\r
-SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB04_MSK\r
-SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL\r
-SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB04_ST\r
+SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB07_MSK\r
+SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL\r
+SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB07_ST\r
SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB04_05_A0\r
SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB04_05_A1\r
SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B1_UDB04_05_D0\r
SCSI_Out_Bits_Sync_ctrl_reg__0__POS EQU 0\r
SCSI_Out_Bits_Sync_ctrl_reg__1__MASK EQU 0x02\r
SCSI_Out_Bits_Sync_ctrl_reg__1__POS EQU 1\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB10_11_ACTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB10_11_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB10_11_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB10_11_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB10_11_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB10_11_MSK\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB10_11_MSK\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB10_11_MSK\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB10_11_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB14_15_ACTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB14_15_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB14_15_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB14_15_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB14_15_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB14_15_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB14_15_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB14_15_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB14_15_MSK\r
SCSI_Out_Bits_Sync_ctrl_reg__2__MASK EQU 0x04\r
SCSI_Out_Bits_Sync_ctrl_reg__2__POS EQU 2\r
SCSI_Out_Bits_Sync_ctrl_reg__3__MASK EQU 0x08\r
SCSI_Out_Bits_Sync_ctrl_reg__6__POS EQU 6\r
SCSI_Out_Bits_Sync_ctrl_reg__7__MASK EQU 0x80\r
SCSI_Out_Bits_Sync_ctrl_reg__7__POS EQU 7\r
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB10_ACTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB10_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB10_ST_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB10_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB10_ST_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB14_ACTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB14_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB14_ST_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB14_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB14_ST_CTL\r
SCSI_Out_Bits_Sync_ctrl_reg__MASK EQU 0xFF\r
-SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB10_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB14_MSK_ACTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB14_MSK_ACTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB14_MSK\r
SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01\r
SCSI_Out_Ctl_Sync_ctrl_reg__0__POS EQU 0\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB07_08_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB07_08_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB07_08_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB07_08_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB07_08_MSK\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB07_08_MSK\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB07_08_MSK\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB07_08_MSK\r
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB07_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB07_ST_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB07_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB07_ST_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB12_13_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB12_13_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB12_13_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB12_13_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB12_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB12_ST_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB12_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB12_ST_CTL\r
SCSI_Out_Ctl_Sync_ctrl_reg__MASK EQU 0x01\r
-SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB07_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB12_MSK\r
SCSI_Out_DBx__0__AG EQU CYREG_PRT5_AG\r
SCSI_Out_DBx__0__AMUX EQU CYREG_PRT5_AMUX\r
SCSI_Out_DBx__0__BIE EQU CYREG_PRT5_BIE\r
scsiTarget_StatusReg__0__POS EQU 0\r
scsiTarget_StatusReg__1__MASK EQU 0x02\r
scsiTarget_StatusReg__1__POS EQU 1\r
-scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL\r
-scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB07_08_ST\r
+scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL\r
+scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB02_03_ST\r
scsiTarget_StatusReg__2__MASK EQU 0x04\r
scsiTarget_StatusReg__2__POS EQU 2\r
scsiTarget_StatusReg__3__MASK EQU 0x08\r
scsiTarget_StatusReg__4__MASK EQU 0x10\r
scsiTarget_StatusReg__4__POS EQU 4\r
scsiTarget_StatusReg__MASK EQU 0x1F\r
-scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB07_MSK\r
-scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL\r
-scsiTarget_StatusReg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL\r
-scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL\r
-scsiTarget_StatusReg__STATUS_CNT_REG EQU CYREG_B0_UDB07_ST_CTL\r
-scsiTarget_StatusReg__STATUS_CONTROL_REG EQU CYREG_B0_UDB07_ST_CTL\r
-scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB07_ST\r
+scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB02_MSK\r
+scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL\r
+scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB02_ST\r
\r
/* Debug_Timer */\r
Debug_Timer_Interrupt__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
SCSI_Filtered_sts_sts_reg__0__POS EQU 0\r
SCSI_Filtered_sts_sts_reg__1__MASK EQU 0x02\r
SCSI_Filtered_sts_sts_reg__1__POS EQU 1\r
-SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB13_14_ACTL\r
-SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB13_14_ST\r
+SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL\r
+SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB11_12_ST\r
SCSI_Filtered_sts_sts_reg__2__MASK EQU 0x04\r
SCSI_Filtered_sts_sts_reg__2__POS EQU 2\r
SCSI_Filtered_sts_sts_reg__3__MASK EQU 0x08\r
SCSI_Filtered_sts_sts_reg__4__MASK EQU 0x10\r
SCSI_Filtered_sts_sts_reg__4__POS EQU 4\r
SCSI_Filtered_sts_sts_reg__MASK EQU 0x1F\r
-SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB13_MSK\r
-SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB13_ACTL\r
-SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB13_ST\r
+SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB11_MSK\r
+SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL\r
+SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB11_ST\r
\r
/* SCSI_CTL_PHASE */\r
SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01\r
SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS EQU 0\r
SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK EQU 0x02\r
SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS EQU 1\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB02_03_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB02_03_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB02_03_MSK\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB02_03_MSK\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB06_07_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB06_07_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB06_07_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB06_07_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB06_07_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB06_07_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB06_07_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB06_07_MSK\r
SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK EQU 0x04\r
SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS EQU 2\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB02_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB02_ST_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB02_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB02_ST_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB06_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB06_ST_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB06_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB06_ST_CTL\r
SCSI_CTL_PHASE_Sync_ctrl_reg__MASK EQU 0x07\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB02_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB06_MSK\r
\r
/* SCSI_Glitch_Ctl */\r
SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01\r
SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS EQU 0\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB03_04_CTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB03_04_CTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB03_04_MSK\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB03_04_MSK\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB03_CTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB03_ST_CTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB03_CTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB03_ST_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB04_05_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB04_05_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB04_05_MSK\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB04_05_MSK\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB04_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB04_ST_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB04_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB04_ST_CTL\r
SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK EQU 0x01\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB03_MSK\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB04_MSK\r
\r
/* SCSI_Parity_Error */\r
SCSI_Parity_Error_sts_sts_reg__0__MASK EQU 0x01\r
SCSI_Parity_Error_sts_sts_reg__0__POS EQU 0\r
-SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL\r
-SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB11_12_ST\r
+SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL\r
+SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB05_06_ST\r
SCSI_Parity_Error_sts_sts_reg__MASK EQU 0x01\r
-SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB11_MSK\r
-SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL\r
-SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB11_ST\r
+SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB05_MSK\r
+SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL\r
+SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB05_ST\r
\r
/* Miscellaneous */\r
BCLK__BUS_CLK__HZ EQU 50000000\r
EXTLED__SLW EQU CYREG_PRT0_SLW\r
\r
; SDCard\r
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL\r
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB07_08_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB07_08_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB07_08_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB07_08_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB07_08_MSK\r
-SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB07_08_MSK\r
-SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB07_08_MSK\r
-SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB07_08_MSK\r
-SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL\r
-SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB07_CTL\r
-SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB07_ST_CTL\r
-SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB07_CTL\r
-SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB07_ST_CTL\r
-SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL\r
-SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL\r
-SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB07_MSK\r
-SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL\r
-SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST\r
-SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB07_MSK\r
-SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL\r
-SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB07_ST_CTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB07_ST_CTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB07_ST\r
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL\r
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB04_05_ST\r
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB05_06_ACTL\r
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB05_06_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB05_06_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB05_06_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB05_06_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB05_06_MSK\r
+SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB05_06_MSK\r
+SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB05_06_MSK\r
+SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB05_06_MSK\r
+SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB05_ACTL\r
+SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB05_CTL\r
+SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB05_ST_CTL\r
+SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB05_CTL\r
+SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB05_ST_CTL\r
+SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL\r
+SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL\r
+SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB05_MSK\r
+SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB05_06_ACTL\r
+SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB05_06_ST\r
+SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB05_MSK\r
+SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL\r
+SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB05_ACTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB05_ST_CTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB05_ST_CTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB05_ST\r
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL\r
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST\r
SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10\r
SDCard_BSPIM_RxStsReg__4__POS EQU 4\r
SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20\r
SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40\r
SDCard_BSPIM_RxStsReg__6__POS EQU 6\r
SDCard_BSPIM_RxStsReg__MASK EQU 0x70\r
-SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB04_MSK\r
-SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL\r
-SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB04_ST\r
+SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB07_MSK\r
+SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL\r
+SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB07_ST\r
SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB04_05_A0\r
SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB04_05_A1\r
SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B1_UDB04_05_D0\r
SCSI_Out_Bits_Sync_ctrl_reg__0__POS EQU 0\r
SCSI_Out_Bits_Sync_ctrl_reg__1__MASK EQU 0x02\r
SCSI_Out_Bits_Sync_ctrl_reg__1__POS EQU 1\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB10_11_ACTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB10_11_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB10_11_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB10_11_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB10_11_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB10_11_MSK\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB10_11_MSK\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB10_11_MSK\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB10_11_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB14_15_ACTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB14_15_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB14_15_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB14_15_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB14_15_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB14_15_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB14_15_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB14_15_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB14_15_MSK\r
SCSI_Out_Bits_Sync_ctrl_reg__2__MASK EQU 0x04\r
SCSI_Out_Bits_Sync_ctrl_reg__2__POS EQU 2\r
SCSI_Out_Bits_Sync_ctrl_reg__3__MASK EQU 0x08\r
SCSI_Out_Bits_Sync_ctrl_reg__6__POS EQU 6\r
SCSI_Out_Bits_Sync_ctrl_reg__7__MASK EQU 0x80\r
SCSI_Out_Bits_Sync_ctrl_reg__7__POS EQU 7\r
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB10_ACTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB10_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB10_ST_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB10_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB10_ST_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB14_ACTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB14_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB14_ST_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB14_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB14_ST_CTL\r
SCSI_Out_Bits_Sync_ctrl_reg__MASK EQU 0xFF\r
-SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB10_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB14_MSK_ACTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB14_MSK_ACTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB14_MSK\r
SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01\r
SCSI_Out_Ctl_Sync_ctrl_reg__0__POS EQU 0\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB07_08_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB07_08_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB07_08_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB07_08_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB07_08_MSK\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB07_08_MSK\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB07_08_MSK\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB07_08_MSK\r
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB07_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB07_ST_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB07_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB07_ST_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB12_13_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB12_13_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB12_13_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB12_13_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB12_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB12_ST_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB12_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB12_ST_CTL\r
SCSI_Out_Ctl_Sync_ctrl_reg__MASK EQU 0x01\r
-SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB07_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB12_MSK\r
SCSI_Out_DBx__0__AG EQU CYREG_PRT5_AG\r
SCSI_Out_DBx__0__AMUX EQU CYREG_PRT5_AMUX\r
SCSI_Out_DBx__0__BIE EQU CYREG_PRT5_BIE\r
scsiTarget_StatusReg__0__POS EQU 0\r
scsiTarget_StatusReg__1__MASK EQU 0x02\r
scsiTarget_StatusReg__1__POS EQU 1\r
-scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL\r
-scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB07_08_ST\r
+scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL\r
+scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB02_03_ST\r
scsiTarget_StatusReg__2__MASK EQU 0x04\r
scsiTarget_StatusReg__2__POS EQU 2\r
scsiTarget_StatusReg__3__MASK EQU 0x08\r
scsiTarget_StatusReg__4__MASK EQU 0x10\r
scsiTarget_StatusReg__4__POS EQU 4\r
scsiTarget_StatusReg__MASK EQU 0x1F\r
-scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB07_MSK\r
-scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL\r
-scsiTarget_StatusReg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL\r
-scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL\r
-scsiTarget_StatusReg__STATUS_CNT_REG EQU CYREG_B0_UDB07_ST_CTL\r
-scsiTarget_StatusReg__STATUS_CONTROL_REG EQU CYREG_B0_UDB07_ST_CTL\r
-scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB07_ST\r
+scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB02_MSK\r
+scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL\r
+scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB02_ST\r
\r
; Debug_Timer\r
Debug_Timer_Interrupt__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
SCSI_Filtered_sts_sts_reg__0__POS EQU 0\r
SCSI_Filtered_sts_sts_reg__1__MASK EQU 0x02\r
SCSI_Filtered_sts_sts_reg__1__POS EQU 1\r
-SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB13_14_ACTL\r
-SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB13_14_ST\r
+SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL\r
+SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB11_12_ST\r
SCSI_Filtered_sts_sts_reg__2__MASK EQU 0x04\r
SCSI_Filtered_sts_sts_reg__2__POS EQU 2\r
SCSI_Filtered_sts_sts_reg__3__MASK EQU 0x08\r
SCSI_Filtered_sts_sts_reg__4__MASK EQU 0x10\r
SCSI_Filtered_sts_sts_reg__4__POS EQU 4\r
SCSI_Filtered_sts_sts_reg__MASK EQU 0x1F\r
-SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB13_MSK\r
-SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB13_ACTL\r
-SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB13_ST\r
+SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB11_MSK\r
+SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL\r
+SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB11_ST\r
\r
; SCSI_CTL_PHASE\r
SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01\r
SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS EQU 0\r
SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK EQU 0x02\r
SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS EQU 1\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB02_03_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB02_03_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB02_03_MSK\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB02_03_MSK\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB06_07_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB06_07_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB06_07_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB06_07_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB06_07_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB06_07_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB06_07_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB06_07_MSK\r
SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK EQU 0x04\r
SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS EQU 2\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB02_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB02_ST_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB02_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB02_ST_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB06_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB06_ST_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB06_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB06_ST_CTL\r
SCSI_CTL_PHASE_Sync_ctrl_reg__MASK EQU 0x07\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB02_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB06_MSK\r
\r
; SCSI_Glitch_Ctl\r
SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01\r
SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS EQU 0\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB03_04_CTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB03_04_CTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB03_04_MSK\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB03_04_MSK\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB03_CTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB03_ST_CTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB03_CTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB03_ST_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB04_05_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB04_05_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB04_05_MSK\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB04_05_MSK\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB04_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB04_ST_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB04_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB04_ST_CTL\r
SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK EQU 0x01\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB03_MSK\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB04_MSK\r
\r
; SCSI_Parity_Error\r
SCSI_Parity_Error_sts_sts_reg__0__MASK EQU 0x01\r
SCSI_Parity_Error_sts_sts_reg__0__POS EQU 0\r
-SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL\r
-SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB11_12_ST\r
+SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL\r
+SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB05_06_ST\r
SCSI_Parity_Error_sts_sts_reg__MASK EQU 0x01\r
-SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB11_MSK\r
-SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL\r
-SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB11_ST\r
+SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB05_MSK\r
+SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL\r
+SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB05_ST\r
\r
; Miscellaneous\r
BCLK__BUS_CLK__HZ EQU 50000000\r
<block name="SD_TX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
<block name="SD_RX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
<block name="SCSI_Filtered" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">\r
- <register name="SCSI_Filtered_STATUS_REG" address="0x4000646D" bitWidth="8" desc="" hidden="false" />\r
- <register name="SCSI_Filtered_MASK_REG" address="0x4000648D" bitWidth="8" desc="" hidden="false" />\r
- <register name="SCSI_Filtered_STATUS_AUX_CTL_REG" address="0x4000649D" bitWidth="8" desc="" hidden="false">\r
+ <register name="SCSI_Filtered_STATUS_REG" address="0x4000646B" bitWidth="8" desc="" hidden="false" />\r
+ <register name="SCSI_Filtered_MASK_REG" address="0x4000648B" bitWidth="8" desc="" hidden="false" />\r
+ <register name="SCSI_Filtered_STATUS_AUX_CTL_REG" address="0x4000649B" bitWidth="8" desc="" hidden="false">\r
<field name="FIFO0" from="5" to="5" access="RW" resetVal="" desc="FIFO0 clear" hidden="false">\r
<value name="ENABLED" value="1" desc="Enable counter" />\r
<value name="DISABLED" value="0" desc="Disable counter" />\r
</register>\r
</block>\r
<block name="SCSI_Parity_Error" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">\r
- <register name="SCSI_Parity_Error_STATUS_REG" address="0x4000646B" bitWidth="8" desc="" hidden="false" />\r
- <register name="SCSI_Parity_Error_MASK_REG" address="0x4000648B" bitWidth="8" desc="" hidden="false" />\r
- <register name="SCSI_Parity_Error_STATUS_AUX_CTL_REG" address="0x4000649B" bitWidth="8" desc="" hidden="false">\r
+ <register name="SCSI_Parity_Error_STATUS_REG" address="0x40006465" bitWidth="8" desc="" hidden="false" />\r
+ <register name="SCSI_Parity_Error_MASK_REG" address="0x40006485" bitWidth="8" desc="" hidden="false" />\r
+ <register name="SCSI_Parity_Error_STATUS_AUX_CTL_REG" address="0x40006495" bitWidth="8" desc="" hidden="false">\r
<field name="FIFO0" from="5" to="5" access="RW" resetVal="" desc="FIFO0 clear" hidden="false">\r
<value name="ENABLED" value="1" desc="Enable counter" />\r
<value name="DISABLED" value="0" desc="Disable counter" />\r
<block name="Em_EEPROM_Dynamic" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
<block name="cy_boot" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
<block name="SCSI_Glitch_Ctl" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">\r
- <register name="SCSI_Glitch_Ctl_CONTROL_REG" address="0x40006473" bitWidth="8" desc="" hidden="false" />\r
+ <register name="SCSI_Glitch_Ctl_CONTROL_REG" address="0x40006474" bitWidth="8" desc="" hidden="false" />\r
</block>\r
<block name="Clock_4" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
<block name="cydff_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
<block name="SCSI_In_DBx" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
<block name="OddParityGen_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
<block name="SCSI_CTL_PHASE" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">\r
- <register name="SCSI_CTL_PHASE_CONTROL_REG" address="0x40006472" bitWidth="8" desc="" hidden="false" />\r
+ <register name="SCSI_CTL_PHASE_CONTROL_REG" address="0x40006476" bitWidth="8" desc="" hidden="false" />\r
</block>\r
<block name="SD_CD" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
<block name="SCSI_Out_Mux" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
<register name="Debug_Timer_COUNTER" address="0x40004F06" bitWidth="16" desc="TMRx.CNT_CMP0 - Current Down Counter Value" hidden="false" />\r
</block>\r
<block name="SCSI_Out_Ctl" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">\r
- <register name="SCSI_Out_Ctl_CONTROL_REG" address="0x40006477" bitWidth="8" desc="" hidden="false" />\r
+ <register name="SCSI_Out_Ctl_CONTROL_REG" address="0x4000647C" bitWidth="8" desc="" hidden="false" />\r
</block>\r
<block name="SCSI_Out_Bits" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">\r
- <register name="SCSI_Out_Bits_CONTROL_REG" address="0x4000647A" bitWidth="8" desc="" hidden="false" />\r
+ <register name="SCSI_Out_Bits_CONTROL_REG" address="0x4000647E" bitWidth="8" desc="" hidden="false" />\r
</block>\r
<block name="SD_MISO" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
<block name="SCSI_RST_ISR" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
<register>\r
<name>SCSI_Filtered_STATUS_REG</name>\r
<description>No description available</description>\r
- <addressOffset>0x4000646D</addressOffset>\r
+ <addressOffset>0x4000646B</addressOffset>\r
<size>8</size>\r
<access>read-write</access>\r
<resetValue>0</resetValue>\r
<register>\r
<name>SCSI_Filtered_MASK_REG</name>\r
<description>No description available</description>\r
- <addressOffset>0x4000648D</addressOffset>\r
+ <addressOffset>0x4000648B</addressOffset>\r
<size>8</size>\r
<access>read-write</access>\r
<resetValue>0</resetValue>\r
<register>\r
<name>SCSI_Filtered_STATUS_AUX_CTL_REG</name>\r
<description>No description available</description>\r
- <addressOffset>0x4000649D</addressOffset>\r
+ <addressOffset>0x4000649B</addressOffset>\r
<size>8</size>\r
<access>read-write</access>\r
<resetValue>0</resetValue>\r
<register>\r
<name>SCSI_Parity_Error_STATUS_REG</name>\r
<description>No description available</description>\r
- <addressOffset>0x4000646B</addressOffset>\r
+ <addressOffset>0x40006465</addressOffset>\r
<size>8</size>\r
<access>read-write</access>\r
<resetValue>0</resetValue>\r
<register>\r
<name>SCSI_Parity_Error_MASK_REG</name>\r
<description>No description available</description>\r
- <addressOffset>0x4000648B</addressOffset>\r
+ <addressOffset>0x40006485</addressOffset>\r
<size>8</size>\r
<access>read-write</access>\r
<resetValue>0</resetValue>\r
<register>\r
<name>SCSI_Parity_Error_STATUS_AUX_CTL_REG</name>\r
<description>No description available</description>\r
- <addressOffset>0x4000649B</addressOffset>\r
+ <addressOffset>0x40006495</addressOffset>\r
<size>8</size>\r
<access>read-write</access>\r
<resetValue>0</resetValue>\r
<register>\r
<name>SCSI_Glitch_Ctl_CONTROL_REG</name>\r
<description>No description available</description>\r
- <addressOffset>0x40006473</addressOffset>\r
+ <addressOffset>0x40006474</addressOffset>\r
<size>8</size>\r
<access>read-write</access>\r
<resetValue>0</resetValue>\r
<register>\r
<name>SCSI_CTL_PHASE_CONTROL_REG</name>\r
<description>No description available</description>\r
- <addressOffset>0x40006472</addressOffset>\r
+ <addressOffset>0x40006476</addressOffset>\r
<size>8</size>\r
<access>read-write</access>\r
<resetValue>0</resetValue>\r
<register>\r
<name>SCSI_Out_Ctl_CONTROL_REG</name>\r
<description>No description available</description>\r
- <addressOffset>0x40006477</addressOffset>\r
+ <addressOffset>0x4000647C</addressOffset>\r
<size>8</size>\r
<access>read-write</access>\r
<resetValue>0</resetValue>\r
<register>\r
<name>SCSI_Out_Bits_CONTROL_REG</name>\r
<description>No description available</description>\r
- <addressOffset>0x4000647A</addressOffset>\r
+ <addressOffset>0x4000647E</addressOffset>\r
<size>8</size>\r
<access>read-write</access>\r
<resetValue>0</resetValue>\r
projects / SCSI2SD.git / commitdiff