-201507XX 4.4
+20150813 4.4
- Added configuration option to allow SCSI2 mode. This option is OFF by
default, and should only be enabled when using the SCSI2SD with a SCSI2 host
controller. Extra timing delays are added in the default SCSI1/SASI mode to
SCSI2SD now negotiates back to async transfers instead of simply
rejecting the message.
- Fixed INQUIRY response to commands lacking an allocation length.
+ - Firmware development updated to PSoC Creator 3.2 (from 3.1)
20150614 4.3
- Added configurable disk geometry.
Amiga 2000 (B2000 rev 6.4 ECS) with DKB RapidFire SCSI 1 card
Amiga 4000 equipped with CyberStorm PPC using 68pin adapter.
Atari TT030 System V
+ Atari TT running TOS 3.06 with HDDRIVER software version 9.06
Atari MEGA STE
needs J3 TERMPWR jumper
1GB limit (--blocks=2048000). The OS will fail to read the boot sector if the disk is >= 1GB.
+ Atari Falcon, TOS 4.02, HDDRIVER 9.06 driver
Sharp X68000
SASI models supported. See gamesx.com for information on building a custom cable.
needs J3 TERMPWR jumper
\r
#include <string.h>\r
\r
-static const uint16_t FIRMWARE_VERSION = 0x0430;\r
+static const uint16_t FIRMWARE_VERSION = 0x0440;\r
\r
// 1 flash row\r
static const uint8_t DEFAULT_CONFIG[256] =\r
\r
SCSI_SEL_ISR_StartEx(scsiSelectionISR);\r
\r
-/*\r
// Disable the glitch filter for ACK to improve performance.\r
- // TODO NEED SOME CONFIG\r
- SCSI_Glitch_Ctl_Write(1);\r
- CY_SET_REG8(scsiTarget_datapath__D0_REG, 0);\r
-*/\r
+ if (getConfigByIndex(0)->flags & CONFIG_DISABLE_GLITCH)\r
+ {\r
+ SCSI_Glitch_Ctl_Write(1);\r
+ CY_SET_REG8(scsiTarget_datapath__D0_REG, 0);\r
+ }\r
\r
}\r
\r
* Note:
*
********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
********************************************************************************
*
* Summary:
-* Set up the interrupt and enable it.
+* Set up the interrupt and enable it. This function disables the interrupt,
+* sets the default interrupt vector, sets the priority from the value in the
+* Design Wide Resources Interrupt Editor, then enables the interrupt to the
+* interrupt controller.
*
* Parameters:
* None
********************************************************************************
*
* Summary:
-* Set up the interrupt and enable it.
+* Sets up the interrupt and enables it. This function disables the interrupt,
+* sets the interrupt vector based on the address passed in, sets the priority
+* from the value in the Design Wide Resources Interrupt Editor, then enables
+* the interrupt to the interrupt controller.
+*
+* When defining ISR functions, the CY_ISR and CY_ISR_PROTO macros should be
+* used to provide consistent definition across compilers:
+*
+* Function definition example:
+* CY_ISR(MyISR)
+* {
+* }
+* Function prototype example:
+* CY_ISR_PROTO(MyISR);
*
* Parameters:
* address: Address of the ISR to set in the interrupt vector table.
* Disables and removes the interrupt.
*
* Parameters:
+* None
*
* Return:
* None
* Change the ISR vector for the Interrupt. Note calling Debug_Timer_Interrupt_Start
* will override any effect this method would have had. To set the vector
* before the component has been started use Debug_Timer_Interrupt_StartEx instead.
+*
+* When defining ISR functions, the CY_ISR and CY_ISR_PROTO macros should be
+* used to provide consistent definition across compilers:
+*
+* Function definition example:
+* CY_ISR(MyISR)
+* {
+* }
+*
+* Function prototype example:
+* CY_ISR_PROTO(MyISR);
*
* Parameters:
* address: Address of the ISR to set in the interrupt vector table.
********************************************************************************
*
* Summary:
-* Sets the Priority of the Interrupt. Note calling Debug_Timer_Interrupt_Start
-* or Debug_Timer_Interrupt_StartEx will override any effect this method
-* would have had. This method should only be called after
-* Debug_Timer_Interrupt_Start or Debug_Timer_Interrupt_StartEx has been called. To set
-* the initial priority for the component use the cydwr file in the tool.
+* Sets the Priority of the Interrupt.
+*
+* Note calling Debug_Timer_Interrupt_Start or Debug_Timer_Interrupt_StartEx will
+* override any effect this API would have had. This API should only be called
+* after Debug_Timer_Interrupt_Start or Debug_Timer_Interrupt_StartEx has been called.
+* To set the initial priority for the component, use the Design-Wide Resources
+* Interrupt Editor.
+*
+* Note This API has no effect on Non-maskable interrupt NMI).
*
* Parameters:
-* priority: Priority of the interrupt. 0 - 7, 0 being the highest.
+* priority: Priority of the interrupt, 0 being the highest priority
+* PSoC 3 and PSoC 5LP: Priority is from 0 to 7.
+* PSoC 4: Priority is from 0 to 3.
*
* Return:
* None
* None
*
* Return:
-* Priority of the interrupt. 0 - 7, 0 being the highest.
+* Priority of the interrupt, 0 being the highest priority
+* PSoC 3 and PSoC 5LP: Priority is from 0 to 7.
+* PSoC 4: Priority is from 0 to 3.
*
*******************************************************************************/
uint8 Debug_Timer_Interrupt_GetPriority(void)
********************************************************************************
*
* Summary:
-* Enables the interrupt.
+* Enables the interrupt to the interrupt controller. Do not call this function
+* unless ISR_Start() has been called or the functionality of the ISR_Start()
+* function, which sets the vector and the priority, has been called.
*
* Parameters:
* None
********************************************************************************
*
* Summary:
-* Disables the Interrupt.
+* Disables the Interrupt in the interrupt controller.
*
* Parameters:
* None
* Return:
* None
*
+* Side Effects:
+* If interrupts are enabled and the interrupt is set up properly, the ISR is
+* entered (depending on the priority of this interrupt and other pending
+* interrupts).
+*
*******************************************************************************/
void Debug_Timer_Interrupt_SetPending(void)
{
********************************************************************************
*
* Summary:
-* Clears a pending interrupt.
+* Clears a pending interrupt in the interrupt controller.
+*
+* Note Some interrupt sources are clear-on-read and require the block
+* interrupt/status register to be read/cleared with the appropriate block API
+* (GPIO, UART, and so on). Otherwise the ISR will continue to remain in
+* pending state even though the interrupt itself is cleared using this API.
*
* Parameters:
* None
*
*
********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
* Note:\r
*\r
********************************************************************************\r
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions, \r
* disclaimers, and limitations in the end user license agreement accompanying \r
* the software package with which this file was provided.\r
********************************************************************************\r
*\r
* Summary:\r
-* Set up the interrupt and enable it.\r
+* Set up the interrupt and enable it. This function disables the interrupt, \r
+* sets the default interrupt vector, sets the priority from the value in the\r
+* Design Wide Resources Interrupt Editor, then enables the interrupt to the \r
+* interrupt controller.\r
*\r
* Parameters: \r
* None\r
********************************************************************************\r
*\r
* Summary:\r
-* Set up the interrupt and enable it.\r
+* Sets up the interrupt and enables it. This function disables the interrupt,\r
+* sets the interrupt vector based on the address passed in, sets the priority \r
+* from the value in the Design Wide Resources Interrupt Editor, then enables \r
+* the interrupt to the interrupt controller.\r
+* \r
+* When defining ISR functions, the CY_ISR and CY_ISR_PROTO macros should be \r
+* used to provide consistent definition across compilers:\r
+* \r
+* Function definition example:\r
+* CY_ISR(MyISR)\r
+* {\r
+* }\r
+* Function prototype example:\r
+* CY_ISR_PROTO(MyISR);\r
*\r
* Parameters: \r
* address: Address of the ISR to set in the interrupt vector table.\r
* Disables and removes the interrupt.\r
*\r
* Parameters: \r
+* None\r
*\r
* Return:\r
* None\r
* Change the ISR vector for the Interrupt. Note calling SCSI_RST_ISR_Start\r
* will override any effect this method would have had. To set the vector \r
* before the component has been started use SCSI_RST_ISR_StartEx instead.\r
+* \r
+* When defining ISR functions, the CY_ISR and CY_ISR_PROTO macros should be \r
+* used to provide consistent definition across compilers:\r
+*\r
+* Function definition example:\r
+* CY_ISR(MyISR)\r
+* {\r
+* }\r
+*\r
+* Function prototype example:\r
+* CY_ISR_PROTO(MyISR);\r
*\r
* Parameters:\r
* address: Address of the ISR to set in the interrupt vector table.\r
********************************************************************************\r
*\r
* Summary:\r
-* Sets the Priority of the Interrupt. Note calling SCSI_RST_ISR_Start\r
-* or SCSI_RST_ISR_StartEx will override any effect this method \r
-* would have had. This method should only be called after \r
-* SCSI_RST_ISR_Start or SCSI_RST_ISR_StartEx has been called. To set \r
-* the initial priority for the component use the cydwr file in the tool.\r
+* Sets the Priority of the Interrupt. \r
+*\r
+* Note calling SCSI_RST_ISR_Start or SCSI_RST_ISR_StartEx will \r
+* override any effect this API would have had. This API should only be called\r
+* after SCSI_RST_ISR_Start or SCSI_RST_ISR_StartEx has been called. \r
+* To set the initial priority for the component, use the Design-Wide Resources\r
+* Interrupt Editor.\r
+*\r
+* Note This API has no effect on Non-maskable interrupt NMI).\r
*\r
* Parameters:\r
-* priority: Priority of the interrupt. 0 - 7, 0 being the highest.\r
+* priority: Priority of the interrupt, 0 being the highest priority\r
+* PSoC 3 and PSoC 5LP: Priority is from 0 to 7.\r
+* PSoC 4: Priority is from 0 to 3.\r
*\r
* Return:\r
* None\r
* None\r
*\r
* Return:\r
-* Priority of the interrupt. 0 - 7, 0 being the highest.\r
+* Priority of the interrupt, 0 being the highest priority\r
+* PSoC 3 and PSoC 5LP: Priority is from 0 to 7.\r
+* PSoC 4: Priority is from 0 to 3.\r
*\r
*******************************************************************************/\r
uint8 SCSI_RST_ISR_GetPriority(void)\r
********************************************************************************\r
*\r
* Summary:\r
-* Enables the interrupt.\r
+* Enables the interrupt to the interrupt controller. Do not call this function\r
+* unless ISR_Start() has been called or the functionality of the ISR_Start() \r
+* function, which sets the vector and the priority, has been called.\r
*\r
* Parameters:\r
* None\r
********************************************************************************\r
*\r
* Summary:\r
-* Disables the Interrupt.\r
+* Disables the Interrupt in the interrupt controller.\r
*\r
* Parameters:\r
* None\r
* Return:\r
* None\r
*\r
+* Side Effects:\r
+* If interrupts are enabled and the interrupt is set up properly, the ISR is\r
+* entered (depending on the priority of this interrupt and other pending \r
+* interrupts).\r
+*\r
*******************************************************************************/\r
void SCSI_RST_ISR_SetPending(void)\r
{\r
********************************************************************************\r
*\r
* Summary:\r
-* Clears a pending interrupt.\r
+* Clears a pending interrupt in the interrupt controller.\r
+*\r
+* Note Some interrupt sources are clear-on-read and require the block \r
+* interrupt/status register to be read/cleared with the appropriate block API \r
+* (GPIO, UART, and so on). Otherwise the ISR will continue to remain in \r
+* pending state even though the interrupt itself is cleared using this API.\r
*\r
* Parameters:\r
* None\r
*\r
*\r
********************************************************************************\r
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions, \r
* disclaimers, and limitations in the end user license agreement accompanying \r
* the software package with which this file was provided.\r
* Note:
*
********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
********************************************************************************
*
* Summary:
-* Set up the interrupt and enable it.
+* Set up the interrupt and enable it. This function disables the interrupt,
+* sets the default interrupt vector, sets the priority from the value in the
+* Design Wide Resources Interrupt Editor, then enables the interrupt to the
+* interrupt controller.
*
* Parameters:
* None
********************************************************************************
*
* Summary:
-* Set up the interrupt and enable it.
+* Sets up the interrupt and enables it. This function disables the interrupt,
+* sets the interrupt vector based on the address passed in, sets the priority
+* from the value in the Design Wide Resources Interrupt Editor, then enables
+* the interrupt to the interrupt controller.
+*
+* When defining ISR functions, the CY_ISR and CY_ISR_PROTO macros should be
+* used to provide consistent definition across compilers:
+*
+* Function definition example:
+* CY_ISR(MyISR)
+* {
+* }
+* Function prototype example:
+* CY_ISR_PROTO(MyISR);
*
* Parameters:
* address: Address of the ISR to set in the interrupt vector table.
* Disables and removes the interrupt.
*
* Parameters:
+* None
*
* Return:
* None
* Change the ISR vector for the Interrupt. Note calling SCSI_RX_DMA_COMPLETE_Start
* will override any effect this method would have had. To set the vector
* before the component has been started use SCSI_RX_DMA_COMPLETE_StartEx instead.
+*
+* When defining ISR functions, the CY_ISR and CY_ISR_PROTO macros should be
+* used to provide consistent definition across compilers:
+*
+* Function definition example:
+* CY_ISR(MyISR)
+* {
+* }
+*
+* Function prototype example:
+* CY_ISR_PROTO(MyISR);
*
* Parameters:
* address: Address of the ISR to set in the interrupt vector table.
********************************************************************************
*
* Summary:
-* Sets the Priority of the Interrupt. Note calling SCSI_RX_DMA_COMPLETE_Start
-* or SCSI_RX_DMA_COMPLETE_StartEx will override any effect this method
-* would have had. This method should only be called after
-* SCSI_RX_DMA_COMPLETE_Start or SCSI_RX_DMA_COMPLETE_StartEx has been called. To set
-* the initial priority for the component use the cydwr file in the tool.
+* Sets the Priority of the Interrupt.
+*
+* Note calling SCSI_RX_DMA_COMPLETE_Start or SCSI_RX_DMA_COMPLETE_StartEx will
+* override any effect this API would have had. This API should only be called
+* after SCSI_RX_DMA_COMPLETE_Start or SCSI_RX_DMA_COMPLETE_StartEx has been called.
+* To set the initial priority for the component, use the Design-Wide Resources
+* Interrupt Editor.
+*
+* Note This API has no effect on Non-maskable interrupt NMI).
*
* Parameters:
-* priority: Priority of the interrupt. 0 - 7, 0 being the highest.
+* priority: Priority of the interrupt, 0 being the highest priority
+* PSoC 3 and PSoC 5LP: Priority is from 0 to 7.
+* PSoC 4: Priority is from 0 to 3.
*
* Return:
* None
* None
*
* Return:
-* Priority of the interrupt. 0 - 7, 0 being the highest.
+* Priority of the interrupt, 0 being the highest priority
+* PSoC 3 and PSoC 5LP: Priority is from 0 to 7.
+* PSoC 4: Priority is from 0 to 3.
*
*******************************************************************************/
uint8 SCSI_RX_DMA_COMPLETE_GetPriority(void)
********************************************************************************
*
* Summary:
-* Enables the interrupt.
+* Enables the interrupt to the interrupt controller. Do not call this function
+* unless ISR_Start() has been called or the functionality of the ISR_Start()
+* function, which sets the vector and the priority, has been called.
*
* Parameters:
* None
********************************************************************************
*
* Summary:
-* Disables the Interrupt.
+* Disables the Interrupt in the interrupt controller.
*
* Parameters:
* None
* Return:
* None
*
+* Side Effects:
+* If interrupts are enabled and the interrupt is set up properly, the ISR is
+* entered (depending on the priority of this interrupt and other pending
+* interrupts).
+*
*******************************************************************************/
void SCSI_RX_DMA_COMPLETE_SetPending(void)
{
********************************************************************************
*
* Summary:
-* Clears a pending interrupt.
+* Clears a pending interrupt in the interrupt controller.
+*
+* Note Some interrupt sources are clear-on-read and require the block
+* interrupt/status register to be read/cleared with the appropriate block API
+* (GPIO, UART, and so on). Otherwise the ISR will continue to remain in
+* pending state even though the interrupt itself is cleared using this API.
*
* Parameters:
* None
*
*
********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
* Note:
*
********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
********************************************************************************
*
* Summary:
-* Set up the interrupt and enable it.
+* Set up the interrupt and enable it. This function disables the interrupt,
+* sets the default interrupt vector, sets the priority from the value in the
+* Design Wide Resources Interrupt Editor, then enables the interrupt to the
+* interrupt controller.
*
* Parameters:
* None
********************************************************************************
*
* Summary:
-* Set up the interrupt and enable it.
+* Sets up the interrupt and enables it. This function disables the interrupt,
+* sets the interrupt vector based on the address passed in, sets the priority
+* from the value in the Design Wide Resources Interrupt Editor, then enables
+* the interrupt to the interrupt controller.
+*
+* When defining ISR functions, the CY_ISR and CY_ISR_PROTO macros should be
+* used to provide consistent definition across compilers:
+*
+* Function definition example:
+* CY_ISR(MyISR)
+* {
+* }
+* Function prototype example:
+* CY_ISR_PROTO(MyISR);
*
* Parameters:
* address: Address of the ISR to set in the interrupt vector table.
* Disables and removes the interrupt.
*
* Parameters:
+* None
*
* Return:
* None
* Change the ISR vector for the Interrupt. Note calling SCSI_SEL_ISR_Start
* will override any effect this method would have had. To set the vector
* before the component has been started use SCSI_SEL_ISR_StartEx instead.
+*
+* When defining ISR functions, the CY_ISR and CY_ISR_PROTO macros should be
+* used to provide consistent definition across compilers:
+*
+* Function definition example:
+* CY_ISR(MyISR)
+* {
+* }
+*
+* Function prototype example:
+* CY_ISR_PROTO(MyISR);
*
* Parameters:
* address: Address of the ISR to set in the interrupt vector table.
********************************************************************************
*
* Summary:
-* Sets the Priority of the Interrupt. Note calling SCSI_SEL_ISR_Start
-* or SCSI_SEL_ISR_StartEx will override any effect this method
-* would have had. This method should only be called after
-* SCSI_SEL_ISR_Start or SCSI_SEL_ISR_StartEx has been called. To set
-* the initial priority for the component use the cydwr file in the tool.
+* Sets the Priority of the Interrupt.
+*
+* Note calling SCSI_SEL_ISR_Start or SCSI_SEL_ISR_StartEx will
+* override any effect this API would have had. This API should only be called
+* after SCSI_SEL_ISR_Start or SCSI_SEL_ISR_StartEx has been called.
+* To set the initial priority for the component, use the Design-Wide Resources
+* Interrupt Editor.
+*
+* Note This API has no effect on Non-maskable interrupt NMI).
*
* Parameters:
-* priority: Priority of the interrupt. 0 - 7, 0 being the highest.
+* priority: Priority of the interrupt, 0 being the highest priority
+* PSoC 3 and PSoC 5LP: Priority is from 0 to 7.
+* PSoC 4: Priority is from 0 to 3.
*
* Return:
* None
* None
*
* Return:
-* Priority of the interrupt. 0 - 7, 0 being the highest.
+* Priority of the interrupt, 0 being the highest priority
+* PSoC 3 and PSoC 5LP: Priority is from 0 to 7.
+* PSoC 4: Priority is from 0 to 3.
*
*******************************************************************************/
uint8 SCSI_SEL_ISR_GetPriority(void)
********************************************************************************
*
* Summary:
-* Enables the interrupt.
+* Enables the interrupt to the interrupt controller. Do not call this function
+* unless ISR_Start() has been called or the functionality of the ISR_Start()
+* function, which sets the vector and the priority, has been called.
*
* Parameters:
* None
********************************************************************************
*
* Summary:
-* Disables the Interrupt.
+* Disables the Interrupt in the interrupt controller.
*
* Parameters:
* None
* Return:
* None
*
+* Side Effects:
+* If interrupts are enabled and the interrupt is set up properly, the ISR is
+* entered (depending on the priority of this interrupt and other pending
+* interrupts).
+*
*******************************************************************************/
void SCSI_SEL_ISR_SetPending(void)
{
********************************************************************************
*
* Summary:
-* Clears a pending interrupt.
+* Clears a pending interrupt in the interrupt controller.
+*
+* Note Some interrupt sources are clear-on-read and require the block
+* interrupt/status register to be read/cleared with the appropriate block API
+* (GPIO, UART, and so on). Otherwise the ISR will continue to remain in
+* pending state even though the interrupt itself is cleared using this API.
*
* Parameters:
* None
*
*
********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
* Note:
*
********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
********************************************************************************
*
* Summary:
-* Set up the interrupt and enable it.
+* Set up the interrupt and enable it. This function disables the interrupt,
+* sets the default interrupt vector, sets the priority from the value in the
+* Design Wide Resources Interrupt Editor, then enables the interrupt to the
+* interrupt controller.
*
* Parameters:
* None
********************************************************************************
*
* Summary:
-* Set up the interrupt and enable it.
+* Sets up the interrupt and enables it. This function disables the interrupt,
+* sets the interrupt vector based on the address passed in, sets the priority
+* from the value in the Design Wide Resources Interrupt Editor, then enables
+* the interrupt to the interrupt controller.
+*
+* When defining ISR functions, the CY_ISR and CY_ISR_PROTO macros should be
+* used to provide consistent definition across compilers:
+*
+* Function definition example:
+* CY_ISR(MyISR)
+* {
+* }
+* Function prototype example:
+* CY_ISR_PROTO(MyISR);
*
* Parameters:
* address: Address of the ISR to set in the interrupt vector table.
* Disables and removes the interrupt.
*
* Parameters:
+* None
*
* Return:
* None
* Change the ISR vector for the Interrupt. Note calling SCSI_TX_DMA_COMPLETE_Start
* will override any effect this method would have had. To set the vector
* before the component has been started use SCSI_TX_DMA_COMPLETE_StartEx instead.
+*
+* When defining ISR functions, the CY_ISR and CY_ISR_PROTO macros should be
+* used to provide consistent definition across compilers:
+*
+* Function definition example:
+* CY_ISR(MyISR)
+* {
+* }
+*
+* Function prototype example:
+* CY_ISR_PROTO(MyISR);
*
* Parameters:
* address: Address of the ISR to set in the interrupt vector table.
********************************************************************************
*
* Summary:
-* Sets the Priority of the Interrupt. Note calling SCSI_TX_DMA_COMPLETE_Start
-* or SCSI_TX_DMA_COMPLETE_StartEx will override any effect this method
-* would have had. This method should only be called after
-* SCSI_TX_DMA_COMPLETE_Start or SCSI_TX_DMA_COMPLETE_StartEx has been called. To set
-* the initial priority for the component use the cydwr file in the tool.
+* Sets the Priority of the Interrupt.
+*
+* Note calling SCSI_TX_DMA_COMPLETE_Start or SCSI_TX_DMA_COMPLETE_StartEx will
+* override any effect this API would have had. This API should only be called
+* after SCSI_TX_DMA_COMPLETE_Start or SCSI_TX_DMA_COMPLETE_StartEx has been called.
+* To set the initial priority for the component, use the Design-Wide Resources
+* Interrupt Editor.
+*
+* Note This API has no effect on Non-maskable interrupt NMI).
*
* Parameters:
-* priority: Priority of the interrupt. 0 - 7, 0 being the highest.
+* priority: Priority of the interrupt, 0 being the highest priority
+* PSoC 3 and PSoC 5LP: Priority is from 0 to 7.
+* PSoC 4: Priority is from 0 to 3.
*
* Return:
* None
* None
*
* Return:
-* Priority of the interrupt. 0 - 7, 0 being the highest.
+* Priority of the interrupt, 0 being the highest priority
+* PSoC 3 and PSoC 5LP: Priority is from 0 to 7.
+* PSoC 4: Priority is from 0 to 3.
*
*******************************************************************************/
uint8 SCSI_TX_DMA_COMPLETE_GetPriority(void)
********************************************************************************
*
* Summary:
-* Enables the interrupt.
+* Enables the interrupt to the interrupt controller. Do not call this function
+* unless ISR_Start() has been called or the functionality of the ISR_Start()
+* function, which sets the vector and the priority, has been called.
*
* Parameters:
* None
********************************************************************************
*
* Summary:
-* Disables the Interrupt.
+* Disables the Interrupt in the interrupt controller.
*
* Parameters:
* None
* Return:
* None
*
+* Side Effects:
+* If interrupts are enabled and the interrupt is set up properly, the ISR is
+* entered (depending on the priority of this interrupt and other pending
+* interrupts).
+*
*******************************************************************************/
void SCSI_TX_DMA_COMPLETE_SetPending(void)
{
********************************************************************************
*
* Summary:
-* Clears a pending interrupt.
+* Clears a pending interrupt in the interrupt controller.
+*
+* Note Some interrupt sources are clear-on-read and require the block
+* interrupt/status register to be read/cleared with the appropriate block API
+* (GPIO, UART, and so on). Otherwise the ISR will continue to remain in
+* pending state even though the interrupt itself is cleared using this API.
*
* Parameters:
* None
*
*
********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
* Note:
*
********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
********************************************************************************
*
* Summary:
-* Set up the interrupt and enable it.
+* Set up the interrupt and enable it. This function disables the interrupt,
+* sets the default interrupt vector, sets the priority from the value in the
+* Design Wide Resources Interrupt Editor, then enables the interrupt to the
+* interrupt controller.
*
* Parameters:
* None
********************************************************************************
*
* Summary:
-* Set up the interrupt and enable it.
+* Sets up the interrupt and enables it. This function disables the interrupt,
+* sets the interrupt vector based on the address passed in, sets the priority
+* from the value in the Design Wide Resources Interrupt Editor, then enables
+* the interrupt to the interrupt controller.
+*
+* When defining ISR functions, the CY_ISR and CY_ISR_PROTO macros should be
+* used to provide consistent definition across compilers:
+*
+* Function definition example:
+* CY_ISR(MyISR)
+* {
+* }
+* Function prototype example:
+* CY_ISR_PROTO(MyISR);
*
* Parameters:
* address: Address of the ISR to set in the interrupt vector table.
* Disables and removes the interrupt.
*
* Parameters:
+* None
*
* Return:
* None
* Change the ISR vector for the Interrupt. Note calling SD_RX_DMA_COMPLETE_Start
* will override any effect this method would have had. To set the vector
* before the component has been started use SD_RX_DMA_COMPLETE_StartEx instead.
+*
+* When defining ISR functions, the CY_ISR and CY_ISR_PROTO macros should be
+* used to provide consistent definition across compilers:
+*
+* Function definition example:
+* CY_ISR(MyISR)
+* {
+* }
+*
+* Function prototype example:
+* CY_ISR_PROTO(MyISR);
*
* Parameters:
* address: Address of the ISR to set in the interrupt vector table.
********************************************************************************
*
* Summary:
-* Sets the Priority of the Interrupt. Note calling SD_RX_DMA_COMPLETE_Start
-* or SD_RX_DMA_COMPLETE_StartEx will override any effect this method
-* would have had. This method should only be called after
-* SD_RX_DMA_COMPLETE_Start or SD_RX_DMA_COMPLETE_StartEx has been called. To set
-* the initial priority for the component use the cydwr file in the tool.
+* Sets the Priority of the Interrupt.
+*
+* Note calling SD_RX_DMA_COMPLETE_Start or SD_RX_DMA_COMPLETE_StartEx will
+* override any effect this API would have had. This API should only be called
+* after SD_RX_DMA_COMPLETE_Start or SD_RX_DMA_COMPLETE_StartEx has been called.
+* To set the initial priority for the component, use the Design-Wide Resources
+* Interrupt Editor.
+*
+* Note This API has no effect on Non-maskable interrupt NMI).
*
* Parameters:
-* priority: Priority of the interrupt. 0 - 7, 0 being the highest.
+* priority: Priority of the interrupt, 0 being the highest priority
+* PSoC 3 and PSoC 5LP: Priority is from 0 to 7.
+* PSoC 4: Priority is from 0 to 3.
*
* Return:
* None
* None
*
* Return:
-* Priority of the interrupt. 0 - 7, 0 being the highest.
+* Priority of the interrupt, 0 being the highest priority
+* PSoC 3 and PSoC 5LP: Priority is from 0 to 7.
+* PSoC 4: Priority is from 0 to 3.
*
*******************************************************************************/
uint8 SD_RX_DMA_COMPLETE_GetPriority(void)
********************************************************************************
*
* Summary:
-* Enables the interrupt.
+* Enables the interrupt to the interrupt controller. Do not call this function
+* unless ISR_Start() has been called or the functionality of the ISR_Start()
+* function, which sets the vector and the priority, has been called.
*
* Parameters:
* None
********************************************************************************
*
* Summary:
-* Disables the Interrupt.
+* Disables the Interrupt in the interrupt controller.
*
* Parameters:
* None
* Return:
* None
*
+* Side Effects:
+* If interrupts are enabled and the interrupt is set up properly, the ISR is
+* entered (depending on the priority of this interrupt and other pending
+* interrupts).
+*
*******************************************************************************/
void SD_RX_DMA_COMPLETE_SetPending(void)
{
********************************************************************************
*
* Summary:
-* Clears a pending interrupt.
+* Clears a pending interrupt in the interrupt controller.
+*
+* Note Some interrupt sources are clear-on-read and require the block
+* interrupt/status register to be read/cleared with the appropriate block API
+* (GPIO, UART, and so on). Otherwise the ISR will continue to remain in
+* pending state even though the interrupt itself is cleared using this API.
*
* Parameters:
* None
*
*
********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
* Note:
*
********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
********************************************************************************
*
* Summary:
-* Set up the interrupt and enable it.
+* Set up the interrupt and enable it. This function disables the interrupt,
+* sets the default interrupt vector, sets the priority from the value in the
+* Design Wide Resources Interrupt Editor, then enables the interrupt to the
+* interrupt controller.
*
* Parameters:
* None
********************************************************************************
*
* Summary:
-* Set up the interrupt and enable it.
+* Sets up the interrupt and enables it. This function disables the interrupt,
+* sets the interrupt vector based on the address passed in, sets the priority
+* from the value in the Design Wide Resources Interrupt Editor, then enables
+* the interrupt to the interrupt controller.
+*
+* When defining ISR functions, the CY_ISR and CY_ISR_PROTO macros should be
+* used to provide consistent definition across compilers:
+*
+* Function definition example:
+* CY_ISR(MyISR)
+* {
+* }
+* Function prototype example:
+* CY_ISR_PROTO(MyISR);
*
* Parameters:
* address: Address of the ISR to set in the interrupt vector table.
* Disables and removes the interrupt.
*
* Parameters:
+* None
*
* Return:
* None
* Change the ISR vector for the Interrupt. Note calling SD_TX_DMA_COMPLETE_Start
* will override any effect this method would have had. To set the vector
* before the component has been started use SD_TX_DMA_COMPLETE_StartEx instead.
+*
+* When defining ISR functions, the CY_ISR and CY_ISR_PROTO macros should be
+* used to provide consistent definition across compilers:
+*
+* Function definition example:
+* CY_ISR(MyISR)
+* {
+* }
+*
+* Function prototype example:
+* CY_ISR_PROTO(MyISR);
*
* Parameters:
* address: Address of the ISR to set in the interrupt vector table.
********************************************************************************
*
* Summary:
-* Sets the Priority of the Interrupt. Note calling SD_TX_DMA_COMPLETE_Start
-* or SD_TX_DMA_COMPLETE_StartEx will override any effect this method
-* would have had. This method should only be called after
-* SD_TX_DMA_COMPLETE_Start or SD_TX_DMA_COMPLETE_StartEx has been called. To set
-* the initial priority for the component use the cydwr file in the tool.
+* Sets the Priority of the Interrupt.
+*
+* Note calling SD_TX_DMA_COMPLETE_Start or SD_TX_DMA_COMPLETE_StartEx will
+* override any effect this API would have had. This API should only be called
+* after SD_TX_DMA_COMPLETE_Start or SD_TX_DMA_COMPLETE_StartEx has been called.
+* To set the initial priority for the component, use the Design-Wide Resources
+* Interrupt Editor.
+*
+* Note This API has no effect on Non-maskable interrupt NMI).
*
* Parameters:
-* priority: Priority of the interrupt. 0 - 7, 0 being the highest.
+* priority: Priority of the interrupt, 0 being the highest priority
+* PSoC 3 and PSoC 5LP: Priority is from 0 to 7.
+* PSoC 4: Priority is from 0 to 3.
*
* Return:
* None
* None
*
* Return:
-* Priority of the interrupt. 0 - 7, 0 being the highest.
+* Priority of the interrupt, 0 being the highest priority
+* PSoC 3 and PSoC 5LP: Priority is from 0 to 7.
+* PSoC 4: Priority is from 0 to 3.
*
*******************************************************************************/
uint8 SD_TX_DMA_COMPLETE_GetPriority(void)
********************************************************************************
*
* Summary:
-* Enables the interrupt.
+* Enables the interrupt to the interrupt controller. Do not call this function
+* unless ISR_Start() has been called or the functionality of the ISR_Start()
+* function, which sets the vector and the priority, has been called.
*
* Parameters:
* None
********************************************************************************
*
* Summary:
-* Disables the Interrupt.
+* Disables the Interrupt in the interrupt controller.
*
* Parameters:
* None
* Return:
* None
*
+* Side Effects:
+* If interrupts are enabled and the interrupt is set up properly, the ISR is
+* entered (depending on the priority of this interrupt and other pending
+* interrupts).
+*
*******************************************************************************/
void SD_TX_DMA_COMPLETE_SetPending(void)
{
********************************************************************************
*
* Summary:
-* Clears a pending interrupt.
+* Clears a pending interrupt in the interrupt controller.
+*
+* Note Some interrupt sources are clear-on-read and require the block
+* interrupt/status register to be read/cleared with the appropriate block API
+* (GPIO, UART, and so on). Otherwise the ISR will continue to remain in
+* pending state even though the interrupt itself is cleared using this API.
*
* Parameters:
* None
*
*
********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
/*******************************************************************************\r
* FILENAME: cydevice.h\r
* OBSOLETE: Do not use this file. Use the _trm version instead.\r
-* PSoC Creator 3.1\r
+* PSoC Creator 3.2\r
*\r
* DESCRIPTION:\r
* This file provides all of the address values for the entire PSoC device.\r
* This file is automatically generated by PSoC Creator.\r
*\r
********************************************************************************\r
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright (c) 2007-2015 Cypress Semiconductor. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions, \r
* disclaimers, and limitations in the end user license agreement accompanying \r
* the software package with which this file was provided.\r
/*******************************************************************************\r
* FILENAME: cydevice_trm.h\r
* \r
-* PSoC Creator 3.1\r
+* PSoC Creator 3.2\r
*\r
* DESCRIPTION:\r
* This file provides all of the address values for the entire PSoC device.\r
* This file is automatically generated by PSoC Creator.\r
*\r
********************************************************************************\r
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright (c) 2007-2015 Cypress Semiconductor. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions, \r
* disclaimers, and limitations in the end user license agreement accompanying \r
* the software package with which this file was provided.\r
/*******************************************************************************\r
* FILENAME: cydevicegnu.inc\r
* OBSOLETE: Do not use this file. Use the _trm version instead.\r
-* PSoC Creator 3.1\r
+* PSoC Creator 3.2\r
*\r
* DESCRIPTION:\r
* This file provides all of the address values for the entire PSoC device.\r
* This file is automatically generated by PSoC Creator.\r
*\r
********************************************************************************\r
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright (c) 2007-2015 Cypress Semiconductor. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions, \r
* disclaimers, and limitations in the end user license agreement accompanying \r
* the software package with which this file was provided.\r
/*******************************************************************************\r
* FILENAME: cydevicegnu_trm.inc\r
* \r
-* PSoC Creator 3.1\r
+* PSoC Creator 3.2\r
*\r
* DESCRIPTION:\r
* This file provides all of the address values for the entire PSoC device.\r
* This file is automatically generated by PSoC Creator.\r
*\r
********************************************************************************\r
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright (c) 2007-2015 Cypress Semiconductor. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions, \r
* disclaimers, and limitations in the end user license agreement accompanying \r
* the software package with which this file was provided.\r
;\r
; FILENAME: cydeviceiar.inc\r
; OBSOLETE: Do not use this file. Use the _trm version instead.\r
-; PSoC Creator 3.1\r
+; PSoC Creator 3.2\r
;\r
; DESCRIPTION:\r
; This file provides all of the address values for the entire PSoC device.\r
;\r
;-------------------------------------------------------------------------------\r
-; Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.\r
+; Copyright (c) 2007-2015 Cypress Semiconductor. All rights reserved.\r
; You may use this file only in accordance with the license, terms, conditions, \r
; disclaimers, and limitations in the end user license agreement accompanying \r
; the software package with which this file was provided.\r
;\r
; FILENAME: cydeviceiar_trm.inc\r
; \r
-; PSoC Creator 3.1\r
+; PSoC Creator 3.2\r
;\r
; DESCRIPTION:\r
; This file provides all of the address values for the entire PSoC device.\r
;\r
;-------------------------------------------------------------------------------\r
-; Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.\r
+; Copyright (c) 2007-2015 Cypress Semiconductor. All rights reserved.\r
; You may use this file only in accordance with the license, terms, conditions, \r
; disclaimers, and limitations in the end user license agreement accompanying \r
; the software package with which this file was provided.\r
;\r
; FILENAME: cydevicerv.inc\r
; OBSOLETE: Do not use this file. Use the _trm version instead.\r
-; PSoC Creator 3.1\r
+; PSoC Creator 3.2\r
;\r
; DESCRIPTION:\r
; This file provides all of the address values for the entire PSoC device.\r
;\r
;-------------------------------------------------------------------------------\r
-; Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.\r
+; Copyright (c) 2007-2015 Cypress Semiconductor. All rights reserved.\r
; You may use this file only in accordance with the license, terms, conditions, \r
; disclaimers, and limitations in the end user license agreement accompanying \r
; the software package with which this file was provided.\r
;\r
; FILENAME: cydevicerv_trm.inc\r
; \r
-; PSoC Creator 3.1\r
+; PSoC Creator 3.2\r
;\r
; DESCRIPTION:\r
; This file provides all of the address values for the entire PSoC device.\r
;\r
;-------------------------------------------------------------------------------\r
-; Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.\r
+; Copyright (c) 2007-2015 Cypress Semiconductor. All rights reserved.\r
; You may use this file only in accordance with the license, terms, conditions, \r
; disclaimers, and limitations in the end user license agreement accompanying \r
; the software package with which this file was provided.\r
#ifndef INCLUDED_CYFITTER_H\r
#define INCLUDED_CYFITTER_H\r
-#include <cydevice.h>\r
-#include <cydevice_trm.h>\r
+#include "cydevice.h"\r
+#include "cydevice_trm.h"\r
\r
/* LED1 */\r
#define LED1__0__MASK 0x08u\r
#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B1_UDB05_ST_CTL\r
#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B1_UDB05_ST_CTL\r
#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B1_UDB05_ST\r
-#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB04_05_ACTL\r
-#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B1_UDB04_05_ST\r
+#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB06_07_ACTL\r
+#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B1_UDB06_07_ST\r
#define SDCard_BSPIM_RxStsReg__4__MASK 0x10u\r
#define SDCard_BSPIM_RxStsReg__4__POS 4\r
#define SDCard_BSPIM_RxStsReg__5__MASK 0x20u\r
#define SDCard_BSPIM_RxStsReg__6__MASK 0x40u\r
#define SDCard_BSPIM_RxStsReg__6__POS 6\r
#define SDCard_BSPIM_RxStsReg__MASK 0x70u\r
-#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B1_UDB04_MSK\r
-#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB04_ACTL\r
-#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B1_UDB04_ST\r
+#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B1_UDB06_MSK\r
+#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB06_ACTL\r
+#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B1_UDB06_ST\r
#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B1_UDB04_05_A0\r
#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B1_UDB04_05_A1\r
#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG CYREG_B1_UDB04_05_D0\r
#define SCSI_Out_Bits_Sync_ctrl_reg__0__POS 0\r
#define SCSI_Out_Bits_Sync_ctrl_reg__1__MASK 0x02u\r
#define SCSI_Out_Bits_Sync_ctrl_reg__1__POS 1\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB11_12_ACTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB11_12_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB11_12_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB11_12_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB11_12_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB11_12_MSK\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB11_12_MSK\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB11_12_MSK\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB11_12_MSK\r
#define SCSI_Out_Bits_Sync_ctrl_reg__2__MASK 0x04u\r
#define SCSI_Out_Bits_Sync_ctrl_reg__2__POS 2\r
#define SCSI_Out_Bits_Sync_ctrl_reg__3__MASK 0x08u\r
#define SCSI_Out_Bits_Sync_ctrl_reg__6__POS 6\r
#define SCSI_Out_Bits_Sync_ctrl_reg__7__MASK 0x80u\r
#define SCSI_Out_Bits_Sync_ctrl_reg__7__POS 7\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B1_UDB11_ACTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG CYREG_B1_UDB11_CTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B1_UDB11_ST_CTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG CYREG_B1_UDB11_CTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG CYREG_B1_UDB11_ST_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB11_ACTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB11_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB11_ST_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB11_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB11_ST_CTL\r
#define SCSI_Out_Bits_Sync_ctrl_reg__MASK 0xFFu\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB11_MSK_ACTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B1_UDB11_MSK_ACTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG CYREG_B1_UDB11_MSK\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB11_MSK\r
\r
/* SCSI_Out_Ctl */\r
#define SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK 0x01u\r
#define SCSI_Out_Ctl_Sync_ctrl_reg__0__POS 0\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB12_13_ACTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB12_13_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB12_13_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB12_13_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB12_13_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB12_13_MSK\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB12_13_MSK\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB12_13_MSK\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB12_13_MSK\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB12_ACTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB12_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB12_ST_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB12_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB12_ST_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB15_ACTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB15_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB15_ST_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB15_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB15_ST_CTL\r
#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK 0x01u\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB12_MSK\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB15_MSK_ACTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB15_MSK_ACTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB15_MSK\r
\r
/* SCSI_Out_DBx */\r
#define SCSI_Out_DBx__0__AG CYREG_PRT6_AG\r
#define scsiTarget_StatusReg__0__POS 0\r
#define scsiTarget_StatusReg__1__MASK 0x02u\r
#define scsiTarget_StatusReg__1__POS 1\r
+#define scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB02_03_ACTL\r
+#define scsiTarget_StatusReg__16BIT_STATUS_REG CYREG_B0_UDB02_03_ST\r
#define scsiTarget_StatusReg__2__MASK 0x04u\r
#define scsiTarget_StatusReg__2__POS 2\r
#define scsiTarget_StatusReg__3__MASK 0x08u\r
#define scsiTarget_StatusReg__4__MASK 0x10u\r
#define scsiTarget_StatusReg__4__POS 4\r
#define scsiTarget_StatusReg__MASK 0x1Fu\r
-#define scsiTarget_StatusReg__MASK_REG CYREG_B0_UDB15_MSK\r
-#define scsiTarget_StatusReg__STATUS_AUX_CTL_REG CYREG_B0_UDB15_ACTL\r
-#define scsiTarget_StatusReg__STATUS_REG CYREG_B0_UDB15_ST\r
+#define scsiTarget_StatusReg__MASK_REG CYREG_B0_UDB02_MSK\r
+#define scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG CYREG_B0_UDB02_MSK_ACTL\r
+#define scsiTarget_StatusReg__PER_ST_AUX_CTL_REG CYREG_B0_UDB02_MSK_ACTL\r
+#define scsiTarget_StatusReg__STATUS_AUX_CTL_REG CYREG_B0_UDB02_ACTL\r
+#define scsiTarget_StatusReg__STATUS_CNT_REG CYREG_B0_UDB02_ST_CTL\r
+#define scsiTarget_StatusReg__STATUS_CONTROL_REG CYREG_B0_UDB02_ST_CTL\r
+#define scsiTarget_StatusReg__STATUS_REG CYREG_B0_UDB02_ST\r
\r
/* Debug_Timer_Interrupt */\r
#define Debug_Timer_Interrupt__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
#define SCSI_Filtered_sts_sts_reg__0__POS 0\r
#define SCSI_Filtered_sts_sts_reg__1__MASK 0x02u\r
#define SCSI_Filtered_sts_sts_reg__1__POS 1\r
-#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB07_08_ACTL\r
-#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB07_08_ST\r
+#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB10_11_ACTL\r
+#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB10_11_ST\r
#define SCSI_Filtered_sts_sts_reg__2__MASK 0x04u\r
#define SCSI_Filtered_sts_sts_reg__2__POS 2\r
#define SCSI_Filtered_sts_sts_reg__3__MASK 0x08u\r
#define SCSI_Filtered_sts_sts_reg__4__MASK 0x10u\r
#define SCSI_Filtered_sts_sts_reg__4__POS 4\r
#define SCSI_Filtered_sts_sts_reg__MASK 0x1Fu\r
-#define SCSI_Filtered_sts_sts_reg__MASK_REG CYREG_B0_UDB07_MSK\r
-#define SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB07_ACTL\r
-#define SCSI_Filtered_sts_sts_reg__STATUS_REG CYREG_B0_UDB07_ST\r
+#define SCSI_Filtered_sts_sts_reg__MASK_REG CYREG_B0_UDB10_MSK\r
+#define SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB10_ACTL\r
+#define SCSI_Filtered_sts_sts_reg__STATUS_REG CYREG_B0_UDB10_ST\r
\r
/* SCSI_CTL_PHASE */\r
#define SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK 0x01u\r
#define SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS 0\r
#define SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK 0x02u\r
#define SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS 1\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB01_02_ACTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB01_02_CTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB01_02_CTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB01_02_CTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB01_02_CTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB01_02_MSK\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB01_02_MSK\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB01_02_MSK\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB01_02_MSK\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB02_03_ACTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB02_03_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB02_03_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB02_03_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB02_03_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB02_03_MSK\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB02_03_MSK\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB02_03_MSK\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB02_03_MSK\r
#define SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK 0x04u\r
#define SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS 2\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB01_ACTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB01_CTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB01_ST_CTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB01_CTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB01_ST_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB02_ACTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB02_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB02_ST_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB02_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB02_ST_CTL\r
#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK 0x07u\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB01_MSK_ACTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB01_MSK_ACTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB01_MSK\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB02_MSK_ACTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB02_MSK_ACTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB02_MSK\r
\r
/* SCSI_Glitch_Ctl */\r
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK 0x01u\r
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS 0\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB10_11_ACTL\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB10_11_CTL\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB10_11_CTL\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB10_11_CTL\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB10_11_CTL\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB10_11_MSK\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB10_11_MSK\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB10_11_MSK\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB10_11_MSK\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB10_ACTL\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB10_CTL\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB10_ST_CTL\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB10_CTL\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB10_ST_CTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB04_05_ACTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB04_05_CTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB04_05_CTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB04_05_CTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB04_05_CTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB04_05_MSK\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB04_05_MSK\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB04_05_MSK\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB04_05_MSK\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB04_ACTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB04_CTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB04_ST_CTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB04_CTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB04_ST_CTL\r
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK 0x01u\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB10_MSK_ACTL\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB10_MSK_ACTL\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB10_MSK\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB04_MSK\r
\r
/* SCSI_Parity_Error */\r
#define SCSI_Parity_Error_sts_sts_reg__0__MASK 0x01u\r
#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB11_12_ST\r
#define SCSI_Parity_Error_sts_sts_reg__MASK 0x01u\r
#define SCSI_Parity_Error_sts_sts_reg__MASK_REG CYREG_B0_UDB11_MSK\r
+#define SCSI_Parity_Error_sts_sts_reg__MASK_ST_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL\r
+#define SCSI_Parity_Error_sts_sts_reg__PER_ST_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL\r
#define SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB11_ACTL\r
+#define SCSI_Parity_Error_sts_sts_reg__STATUS_CNT_REG CYREG_B0_UDB11_ST_CTL\r
+#define SCSI_Parity_Error_sts_sts_reg__STATUS_CONTROL_REG CYREG_B0_UDB11_ST_CTL\r
#define SCSI_Parity_Error_sts_sts_reg__STATUS_REG CYREG_B0_UDB11_ST\r
\r
/* Miscellaneous */\r
#define BCLK__BUS_CLK__HZ 50000000U\r
#define BCLK__BUS_CLK__KHZ 50000U\r
#define BCLK__BUS_CLK__MHZ 50U\r
-#define CY_VERSION "PSoC Creator 3.1"\r
+#define CY_PROJECT_NAME "SCSI2SD"\r
+#define CY_VERSION "PSoC Creator 3.2"\r
+#define CYDEV_CHIP_DIE_GEN4 2u\r
#define CYDEV_CHIP_DIE_LEOPARD 1u\r
-#define CYDEV_CHIP_DIE_PANTHER 6u\r
-#define CYDEV_CHIP_DIE_PSOC4A 3u\r
-#define CYDEV_CHIP_DIE_PSOC5LP 5u\r
+#define CYDEV_CHIP_DIE_PANTHER 12u\r
+#define CYDEV_CHIP_DIE_PSOC4A 5u\r
+#define CYDEV_CHIP_DIE_PSOC5LP 11u\r
#define CYDEV_CHIP_DIE_UNKNOWN 0u\r
#define CYDEV_CHIP_FAMILY_PSOC3 1u\r
#define CYDEV_CHIP_FAMILY_PSOC4 2u\r
#define CYDEV_CHIP_FAMILY_USED CYDEV_CHIP_FAMILY_PSOC5\r
#define CYDEV_CHIP_JTAG_ID 0x2E133069u\r
#define CYDEV_CHIP_MEMBER_3A 1u\r
-#define CYDEV_CHIP_MEMBER_4A 3u\r
-#define CYDEV_CHIP_MEMBER_4D 2u\r
-#define CYDEV_CHIP_MEMBER_4F 4u\r
-#define CYDEV_CHIP_MEMBER_5A 6u\r
-#define CYDEV_CHIP_MEMBER_5B 5u\r
+#define CYDEV_CHIP_MEMBER_4A 5u\r
+#define CYDEV_CHIP_MEMBER_4C 9u\r
+#define CYDEV_CHIP_MEMBER_4D 3u\r
+#define CYDEV_CHIP_MEMBER_4E 4u\r
+#define CYDEV_CHIP_MEMBER_4F 6u\r
+#define CYDEV_CHIP_MEMBER_4G 2u\r
+#define CYDEV_CHIP_MEMBER_4L 8u\r
+#define CYDEV_CHIP_MEMBER_4M 7u\r
+#define CYDEV_CHIP_MEMBER_5A 11u\r
+#define CYDEV_CHIP_MEMBER_5B 10u\r
#define CYDEV_CHIP_MEMBER_UNKNOWN 0u\r
#define CYDEV_CHIP_MEMBER_USED CYDEV_CHIP_MEMBER_5B\r
#define CYDEV_CHIP_DIE_EXPECT CYDEV_CHIP_MEMBER_USED\r
#define CYDEV_CHIP_DIE_ACTUAL CYDEV_CHIP_DIE_EXPECT\r
+#define CYDEV_CHIP_REV_GEN4_ES 17u\r
+#define CYDEV_CHIP_REV_GEN4_ES2 33u\r
+#define CYDEV_CHIP_REV_GEN4_PRODUCTION 17u\r
#define CYDEV_CHIP_REV_LEOPARD_ES1 0u\r
#define CYDEV_CHIP_REV_LEOPARD_ES2 1u\r
#define CYDEV_CHIP_REV_LEOPARD_ES3 3u\r
#define CYDEV_CHIP_REVISION_3A_PRODUCTION 3u\r
#define CYDEV_CHIP_REVISION_4A_ES0 17u\r
#define CYDEV_CHIP_REVISION_4A_PRODUCTION 17u\r
+#define CYDEV_CHIP_REVISION_4C_PRODUCTION 0u\r
#define CYDEV_CHIP_REVISION_4D_PRODUCTION 0u\r
+#define CYDEV_CHIP_REVISION_4E_PRODUCTION 0u\r
#define CYDEV_CHIP_REVISION_4F_PRODUCTION 0u\r
+#define CYDEV_CHIP_REVISION_4F_PRODUCTION_256K 0u\r
+#define CYDEV_CHIP_REVISION_4G_ES 17u\r
+#define CYDEV_CHIP_REVISION_4G_ES2 33u\r
+#define CYDEV_CHIP_REVISION_4G_PRODUCTION 17u\r
+#define CYDEV_CHIP_REVISION_4L_PRODUCTION 0u\r
+#define CYDEV_CHIP_REVISION_4M_PRODUCTION 0u\r
#define CYDEV_CHIP_REVISION_5A_ES0 0u\r
#define CYDEV_CHIP_REVISION_5A_ES1 1u\r
#define CYDEV_CHIP_REVISION_5A_PRODUCTION 1u\r
#define CYDEV_CONFIGURATION_MODE_UNCOMPRESSED 1\r
#define CYDEV_DEBUG_ENABLE_MASK 0x20u\r
#define CYDEV_DEBUG_ENABLE_REGISTER CYREG_MLOGIC_DEBUG\r
-#define CYDEV_DEBUGGING_DPS_Disable 3\r
-#define CYDEV_DEBUGGING_DPS_JTAG_4 1\r
-#define CYDEV_DEBUGGING_DPS_JTAG_5 0\r
#define CYDEV_DEBUGGING_DPS_SWD 2\r
#define CYDEV_DEBUGGING_DPS_SWD_SWV 6\r
#define CYDEV_DEBUGGING_DPS CYDEV_DEBUGGING_DPS_SWD_SWV\r
#define CYDEV_INTR_RISING 0x0000007Eu\r
#define CYDEV_PROJ_TYPE 2\r
#define CYDEV_PROJ_TYPE_BOOTLOADER 1\r
+#define CYDEV_PROJ_TYPE_LAUNCHER 5\r
#define CYDEV_PROJ_TYPE_LOADABLE 2\r
+#define CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER 4\r
#define CYDEV_PROJ_TYPE_MULTIAPPBOOTLOADER 3\r
#define CYDEV_PROJ_TYPE_STANDARD 0\r
#define CYDEV_PROTECTION_ENABLE 0\r
/*******************************************************************************\r
* FILENAME: cyfitter_cfg.c\r
-* PSoC Creator 3.1\r
+* \r
+* PSoC Creator 3.2\r
*\r
-* Description:\r
-* This file is automatically generated by PSoC Creator with device \r
-* initialization code. Except for the user defined sections in\r
-* CyClockStartupError(), this file should not be modified.\r
+* DESCRIPTION:\r
+* This file contains device initialization code.\r
+* Except for the user defined sections in CyClockStartupError(), this file should not be modified.\r
+* This file is automatically generated by PSoC Creator.\r
*\r
********************************************************************************\r
-* Copyright 2013, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright (c) 2007-2015 Cypress Semiconductor. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions, \r
* disclaimers, and limitations in the end user license agreement accompanying \r
* the software package with which this file was provided.\r
********************************************************************************/\r
\r
#include <string.h>\r
-#include <cytypes.h>\r
-#include <cydevice_trm.h>\r
-#include <cyfitter.h>\r
-#include <CyLib.h>\r
-#include <cyfitter_cfg.h>\r
+#include "cytypes.h"\r
+#include "cydevice_trm.h"\r
+#include "cyfitter.h"\r
+#include "CyLib.h"\r
+#include "cyfitter_cfg.h"\r
\r
#define CY_NEED_CYCLOCKSTARTUPERROR 1\r
\r
0x4000520Cu, /* Base address: 0x40005200 Count: 12 */\r
0x40006401u, /* Base address: 0x40006400 Count: 1 */\r
0x40006501u, /* Base address: 0x40006500 Count: 1 */\r
- 0x40010039u, /* Base address: 0x40010000 Count: 57 */\r
- 0x40010135u, /* Base address: 0x40010100 Count: 53 */\r
- 0x40010243u, /* Base address: 0x40010200 Count: 67 */\r
- 0x40010354u, /* Base address: 0x40010300 Count: 84 */\r
- 0x4001043Fu, /* Base address: 0x40010400 Count: 63 */\r
- 0x40010551u, /* Base address: 0x40010500 Count: 81 */\r
+ 0x4001003Bu, /* Base address: 0x40010000 Count: 59 */\r
+ 0x40010142u, /* Base address: 0x40010100 Count: 66 */\r
+ 0x4001023Eu, /* Base address: 0x40010200 Count: 62 */\r
+ 0x4001035Au, /* Base address: 0x40010300 Count: 90 */\r
+ 0x40010447u, /* Base address: 0x40010400 Count: 71 */\r
+ 0x4001054Fu, /* Base address: 0x40010500 Count: 79 */\r
0x4001064Au, /* Base address: 0x40010600 Count: 74 */\r
- 0x4001074Du, /* Base address: 0x40010700 Count: 77 */\r
- 0x40010804u, /* Base address: 0x40010800 Count: 4 */\r
- 0x4001091Eu, /* Base address: 0x40010900 Count: 30 */\r
- 0x40010A54u, /* Base address: 0x40010A00 Count: 84 */\r
- 0x40010B53u, /* Base address: 0x40010B00 Count: 83 */\r
- 0x40010C4Eu, /* Base address: 0x40010C00 Count: 78 */\r
- 0x40010D52u, /* Base address: 0x40010D00 Count: 82 */\r
- 0x40010E42u, /* Base address: 0x40010E00 Count: 66 */\r
+ 0x40010749u, /* Base address: 0x40010700 Count: 73 */\r
+ 0x40010851u, /* Base address: 0x40010800 Count: 81 */\r
+ 0x40010941u, /* Base address: 0x40010900 Count: 65 */\r
+ 0x40010A43u, /* Base address: 0x40010A00 Count: 67 */\r
+ 0x40010B4Au, /* Base address: 0x40010B00 Count: 74 */\r
+ 0x40010C4Du, /* Base address: 0x40010C00 Count: 77 */\r
+ 0x40010D4Bu, /* Base address: 0x40010D00 Count: 75 */\r
+ 0x40010E44u, /* Base address: 0x40010E00 Count: 68 */\r
0x40010F3Cu, /* Base address: 0x40010F00 Count: 60 */\r
- 0x4001145Du, /* Base address: 0x40011400 Count: 93 */\r
- 0x40011552u, /* Base address: 0x40011500 Count: 82 */\r
- 0x40011653u, /* Base address: 0x40011600 Count: 83 */\r
- 0x40011744u, /* Base address: 0x40011700 Count: 68 */\r
- 0x40011912u, /* Base address: 0x40011900 Count: 18 */\r
- 0x40011A4Au, /* Base address: 0x40011A00 Count: 74 */\r
- 0x40011B47u, /* Base address: 0x40011B00 Count: 71 */\r
+ 0x4001142Du, /* Base address: 0x40011400 Count: 45 */\r
+ 0x4001154Du, /* Base address: 0x40011500 Count: 77 */\r
+ 0x40011649u, /* Base address: 0x40011600 Count: 73 */\r
+ 0x40011746u, /* Base address: 0x40011700 Count: 70 */\r
+ 0x40011804u, /* Base address: 0x40011800 Count: 4 */\r
+ 0x40011908u, /* Base address: 0x40011900 Count: 8 */\r
+ 0x40011B03u, /* Base address: 0x40011B00 Count: 3 */\r
0x4001401Bu, /* Base address: 0x40014000 Count: 27 */\r
- 0x4001411Du, /* Base address: 0x40014100 Count: 29 */\r
+ 0x4001411Au, /* Base address: 0x40014100 Count: 26 */\r
0x40014211u, /* Base address: 0x40014200 Count: 17 */\r
- 0x4001430Eu, /* Base address: 0x40014300 Count: 14 */\r
- 0x4001440Du, /* Base address: 0x40014400 Count: 13 */\r
- 0x40014517u, /* Base address: 0x40014500 Count: 23 */\r
- 0x4001460Fu, /* Base address: 0x40014600 Count: 15 */\r
- 0x4001470Bu, /* Base address: 0x40014700 Count: 11 */\r
- 0x4001480Eu, /* Base address: 0x40014800 Count: 14 */\r
+ 0x4001430Bu, /* Base address: 0x40014300 Count: 11 */\r
+ 0x4001440Fu, /* Base address: 0x40014400 Count: 15 */\r
+ 0x4001451Cu, /* Base address: 0x40014500 Count: 28 */\r
+ 0x4001460Cu, /* Base address: 0x40014600 Count: 12 */\r
+ 0x4001470Cu, /* Base address: 0x40014700 Count: 12 */\r
+ 0x4001480Cu, /* Base address: 0x40014800 Count: 12 */\r
0x4001490Bu, /* Base address: 0x40014900 Count: 11 */\r
- 0x40014C03u, /* Base address: 0x40014C00 Count: 3 */\r
+ 0x40014C01u, /* Base address: 0x40014C00 Count: 1 */\r
0x40014D04u, /* Base address: 0x40014D00 Count: 4 */\r
- 0x40015005u, /* Base address: 0x40015000 Count: 5 */\r
+ 0x40015002u, /* Base address: 0x40015000 Count: 2 */\r
0x40015104u, /* Base address: 0x40015100 Count: 4 */\r
};\r
\r
static const cy_cfg_addrvalue_t CYCODE cy_cfg_data_table[] = {\r
{0x7Eu, 0x02u},\r
{0x01u, 0x20u},\r
- {0x0Au, 0x1Bu},\r
- {0x00u, 0x14u},\r
- {0x01u, 0x11u},\r
- {0x18u, 0x08u},\r
- {0x19u, 0x04u},\r
+ {0x0Au, 0x36u},\r
+ {0x00u, 0x11u},\r
+ {0x01u, 0x02u},\r
+ {0x18u, 0x04u},\r
+ {0x19u, 0x0Cu},\r
{0x1Cu, 0x71u},\r
- {0x20u, 0x60u},\r
- {0x21u, 0xA0u},\r
+ {0x20u, 0xA8u},\r
+ {0x21u, 0x60u},\r
{0x2Cu, 0x0Eu},\r
- {0x30u, 0x06u},\r
- {0x31u, 0x03u},\r
+ {0x30u, 0x0Au},\r
+ {0x31u, 0x09u},\r
{0x34u, 0x80u},\r
{0x7Cu, 0x40u},\r
{0x20u, 0x02u},\r
{0x85u, 0x0Fu},\r
- {0x00u, 0x01u},\r
- {0x02u, 0x02u},\r
- {0x04u, 0x04u},\r
- {0x05u, 0x04u},\r
- {0x14u, 0x02u},\r
+ {0x04u, 0x50u},\r
+ {0x05u, 0x02u},\r
+ {0x06u, 0x28u},\r
+ {0x0Du, 0x01u},\r
+ {0x0Eu, 0x38u},\r
+ {0x10u, 0x02u},\r
+ {0x14u, 0x48u},\r
{0x15u, 0x08u},\r
- {0x16u, 0x01u},\r
- {0x18u, 0x02u},\r
- {0x1Au, 0x01u},\r
- {0x1Cu, 0x10u},\r
- {0x21u, 0x01u},\r
- {0x24u, 0x02u},\r
- {0x26u, 0x01u},\r
- {0x2Bu, 0x02u},\r
- {0x2Cu, 0x02u},\r
- {0x2Eu, 0x09u},\r
- {0x30u, 0x03u},\r
- {0x31u, 0x04u},\r
- {0x32u, 0x08u},\r
- {0x33u, 0x08u},\r
- {0x34u, 0x04u},\r
- {0x35u, 0x02u},\r
- {0x36u, 0x10u},\r
+ {0x16u, 0x10u},\r
+ {0x17u, 0x04u},\r
+ {0x18u, 0x04u},\r
+ {0x19u, 0x04u},\r
+ {0x1Bu, 0x08u},\r
+ {0x1Cu, 0x20u},\r
+ {0x1Du, 0x08u},\r
+ {0x1Eu, 0x40u},\r
+ {0x1Fu, 0x04u},\r
+ {0x21u, 0x08u},\r
+ {0x23u, 0x04u},\r
+ {0x26u, 0x40u},\r
+ {0x28u, 0x01u},\r
+ {0x29u, 0x10u},\r
+ {0x2Du, 0x08u},\r
+ {0x2Fu, 0x04u},\r
+ {0x30u, 0x04u},\r
+ {0x31u, 0x10u},\r
+ {0x32u, 0x01u},\r
+ {0x33u, 0x02u},\r
+ {0x34u, 0x02u},\r
+ {0x35u, 0x0Cu},\r
+ {0x36u, 0x78u},\r
{0x37u, 0x01u},\r
- {0x3Au, 0x02u},\r
- {0x3Eu, 0x50u},\r
+ {0x3Bu, 0x20u},\r
+ {0x3Eu, 0x15u},\r
{0x3Fu, 0x45u},\r
- {0x40u, 0x34u},\r
- {0x41u, 0x06u},\r
- {0x42u, 0x50u},\r
- {0x45u, 0xCDu},\r
- {0x46u, 0xE2u},\r
- {0x47u, 0x0Fu},\r
+ {0x40u, 0x62u},\r
+ {0x41u, 0x03u},\r
+ {0x42u, 0x40u},\r
+ {0x45u, 0xEFu},\r
+ {0x46u, 0x2Cu},\r
+ {0x47u, 0x0Du},\r
{0x48u, 0x1Fu},\r
{0x49u, 0xFFu},\r
{0x4Au, 0xFFu},\r
{0x59u, 0x04u},\r
{0x5Au, 0x04u},\r
{0x5Bu, 0x04u},\r
- {0x5Cu, 0x99u},\r
+ {0x5Cu, 0x91u},\r
{0x5Du, 0x01u},\r
{0x5Fu, 0x01u},\r
{0x62u, 0xC0u},\r
{0x68u, 0x40u},\r
{0x69u, 0x40u},\r
{0x6Eu, 0x08u},\r
- {0xADu, 0x01u},\r
- {0xB3u, 0x01u},\r
- {0xBFu, 0x04u},\r
- {0xD9u, 0x04u},\r
- {0xDBu, 0x04u},\r
- {0xDFu, 0x01u},\r
- {0x01u, 0x02u},\r
- {0x02u, 0x10u},\r
- {0x09u, 0x80u},\r
- {0x0Au, 0x18u},\r
- {0x11u, 0x40u},\r
- {0x12u, 0x20u},\r
- {0x19u, 0x12u},\r
- {0x1Au, 0x12u},\r
- {0x1Bu, 0x04u},\r
- {0x21u, 0x02u},\r
- {0x22u, 0xA8u},\r
- {0x27u, 0x10u},\r
- {0x2Bu, 0x44u},\r
- {0x2Fu, 0x01u},\r
- {0x31u, 0x08u},\r
- {0x3Au, 0x04u},\r
+ {0x01u, 0x80u},\r
+ {0x03u, 0x10u},\r
+ {0x08u, 0x22u},\r
+ {0x0Au, 0x10u},\r
+ {0x0Bu, 0x02u},\r
+ {0x10u, 0x10u},\r
+ {0x12u, 0x08u},\r
+ {0x15u, 0x04u},\r
+ {0x16u, 0x20u},\r
+ {0x18u, 0x04u},\r
+ {0x19u, 0x84u},\r
+ {0x1Bu, 0x02u},\r
+ {0x20u, 0x08u},\r
+ {0x21u, 0xA2u},\r
+ {0x22u, 0x04u},\r
+ {0x28u, 0x80u},\r
+ {0x29u, 0x40u},\r
+ {0x2Bu, 0x04u},\r
+ {0x30u, 0x08u},\r
+ {0x31u, 0x20u},\r
+ {0x33u, 0x40u},\r
+ {0x34u, 0x10u},\r
+ {0x37u, 0x20u},\r
+ {0x39u, 0x40u},\r
+ {0x3Bu, 0x04u},\r
{0x41u, 0x04u},\r
- {0x43u, 0x01u},\r
- {0x48u, 0xD4u},\r
- {0x49u, 0x04u},\r
- {0x4Au, 0x01u},\r
- {0x50u, 0x40u},\r
- {0x53u, 0xA4u},\r
- {0x5Au, 0x46u},\r
- {0x5Bu, 0x10u},\r
- {0x61u, 0x12u},\r
- {0x62u, 0x88u},\r
- {0x69u, 0x86u},\r
- {0x6Bu, 0x08u},\r
- {0x6Cu, 0x30u},\r
- {0x6Eu, 0x08u},\r
- {0x6Fu, 0x0Au},\r
- {0x72u, 0x02u},\r
- {0x73u, 0x64u},\r
- {0x82u, 0x04u},\r
- {0x83u, 0x08u},\r
- {0x85u, 0x02u},\r
- {0x87u, 0x02u},\r
- {0x89u, 0x01u},\r
+ {0x42u, 0x10u},\r
+ {0x43u, 0x11u},\r
+ {0x4Au, 0x50u},\r
+ {0x4Bu, 0x20u},\r
+ {0x50u, 0x20u},\r
+ {0x51u, 0x18u},\r
+ {0x53u, 0x68u},\r
+ {0x58u, 0x40u},\r
+ {0x59u, 0x14u},\r
+ {0x5Au, 0x01u},\r
+ {0x60u, 0x04u},\r
+ {0x61u, 0x82u},\r
+ {0x63u, 0x10u},\r
+ {0x68u, 0x42u},\r
+ {0x69u, 0x14u},\r
+ {0x70u, 0x50u},\r
+ {0x72u, 0x80u},\r
+ {0x73u, 0x20u},\r
+ {0x83u, 0x40u},\r
+ {0x84u, 0x40u},\r
+ {0x86u, 0x04u},\r
+ {0x87u, 0x1Au},\r
+ {0x88u, 0x40u},\r
+ {0x8Bu, 0x40u},\r
+ {0x8Cu, 0xC0u},\r
{0x8Du, 0x40u},\r
- {0x8Fu, 0x20u},\r
- {0xC0u, 0x0Cu},\r
- {0xC2u, 0x07u},\r
- {0xC4u, 0x05u},\r
- {0xCAu, 0x15u},\r
- {0xCCu, 0x02u},\r
- {0xCEu, 0x02u},\r
- {0xD0u, 0x03u},\r
- {0xD2u, 0x0Cu},\r
+ {0x8Eu, 0x02u},\r
+ {0xC0u, 0x05u},\r
+ {0xC2u, 0x0Fu},\r
+ {0xC4u, 0x06u},\r
+ {0xCAu, 0x0Du},\r
+ {0xCCu, 0x0Eu},\r
+ {0xCEu, 0x0Au},\r
+ {0xD0u, 0x07u},\r
+ {0xD2u, 0x04u},\r
{0xD6u, 0x0Fu},\r
{0xD8u, 0x0Fu},\r
- {0xE4u, 0x0Cu},\r
- {0xE6u, 0x02u},\r
- {0x04u, 0x09u},\r
- {0x05u, 0x0Cu},\r
- {0x06u, 0x02u},\r
- {0x07u, 0x30u},\r
- {0x09u, 0x13u},\r
- {0x0Bu, 0x44u},\r
- {0x0Cu, 0x0Au},\r
- {0x0Du, 0x08u},\r
- {0x0Eu, 0x05u},\r
- {0x13u, 0x7Fu},\r
- {0x14u, 0x04u},\r
- {0x16u, 0x08u},\r
- {0x17u, 0x02u},\r
- {0x1Au, 0x07u},\r
- {0x1Du, 0x6Cu},\r
- {0x1Fu, 0x13u},\r
- {0x23u, 0x20u},\r
- {0x25u, 0x03u},\r
- {0x26u, 0x08u},\r
- {0x29u, 0x71u},\r
- {0x34u, 0x0Fu},\r
+ {0xE2u, 0x06u},\r
+ {0xE4u, 0x02u},\r
+ {0xE6u, 0x81u},\r
+ {0x02u, 0x0Eu},\r
+ {0x04u, 0x0Bu},\r
+ {0x06u, 0x10u},\r
+ {0x07u, 0x7Fu},\r
+ {0x09u, 0x8Cu},\r
+ {0x0Bu, 0x30u},\r
+ {0x11u, 0x71u},\r
+ {0x13u, 0x80u},\r
+ {0x14u, 0x08u},\r
+ {0x15u, 0x03u},\r
+ {0x19u, 0xECu},\r
+ {0x1Au, 0x03u},\r
+ {0x1Bu, 0x13u},\r
+ {0x1Eu, 0x1Fu},\r
+ {0x20u, 0x14u},\r
+ {0x21u, 0x08u},\r
+ {0x22u, 0x0Bu},\r
+ {0x23u, 0x80u},\r
+ {0x24u, 0x01u},\r
+ {0x26u, 0x04u},\r
+ {0x27u, 0x20u},\r
+ {0x2Au, 0x04u},\r
+ {0x2Bu, 0x02u},\r
+ {0x2Du, 0x93u},\r
+ {0x2Fu, 0x44u},\r
+ {0x30u, 0x1Fu},\r
+ {0x31u, 0x80u},\r
+ {0x33u, 0x7Fu},\r
+ {0x34u, 0x1Fu},\r
{0x37u, 0x7Fu},\r
- {0x56u, 0x08u},\r
+ {0x3Fu, 0x01u},\r
{0x58u, 0x04u},\r
{0x59u, 0x04u},\r
{0x5Bu, 0x04u},\r
{0x5Cu, 0x11u},\r
- {0x5Du, 0x90u},\r
{0x5Fu, 0x01u},\r
- {0x83u, 0x08u},\r
- {0x84u, 0x09u},\r
- {0x85u, 0x44u},\r
- {0x86u, 0x02u},\r
- {0x87u, 0x88u},\r
- {0x8Au, 0x07u},\r
- {0x8Bu, 0x07u},\r
- {0x8Cu, 0x40u},\r
- {0x8Eu, 0x80u},\r
- {0x8Fu, 0x80u},\r
- {0x90u, 0x20u},\r
- {0x94u, 0x10u},\r
- {0x97u, 0x70u},\r
- {0x99u, 0x99u},\r
- {0x9Au, 0x40u},\r
- {0x9Bu, 0x22u},\r
- {0x9Du, 0xAAu},\r
- {0x9Fu, 0x55u},\r
- {0xA0u, 0x0Au},\r
- {0xA2u, 0x05u},\r
- {0xA6u, 0x08u},\r
- {0xA8u, 0x04u},\r
- {0xAAu, 0x08u},\r
- {0xAEu, 0x80u},\r
- {0xB0u, 0x20u},\r
- {0xB2u, 0x0Fu},\r
- {0xB3u, 0xF0u},\r
- {0xB4u, 0x10u},\r
- {0xB5u, 0x0Fu},\r
- {0xB6u, 0xC0u},\r
- {0xBEu, 0x51u},\r
+ {0x82u, 0x04u},\r
+ {0x83u, 0x70u},\r
+ {0x85u, 0x99u},\r
+ {0x87u, 0x22u},\r
+ {0x8Bu, 0x80u},\r
+ {0x97u, 0x07u},\r
+ {0x99u, 0xAAu},\r
+ {0x9Au, 0x02u},\r
+ {0x9Bu, 0x55u},\r
+ {0xA5u, 0x44u},\r
+ {0xA7u, 0x88u},\r
+ {0xABu, 0x08u},\r
+ {0xACu, 0x01u},\r
+ {0xB1u, 0xF0u},\r
+ {0xB2u, 0x04u},\r
+ {0xB3u, 0x0Fu},\r
+ {0xB4u, 0x01u},\r
+ {0xB6u, 0x02u},\r
+ {0xBEu, 0x10u},\r
{0xD6u, 0x08u},\r
{0xD8u, 0x04u},\r
{0xD9u, 0x04u},\r
{0xDBu, 0x04u},\r
- {0xDCu, 0x11u},\r
+ {0xDCu, 0x19u},\r
{0xDDu, 0x90u},\r
{0xDFu, 0x01u},\r
- {0x00u, 0x04u},\r
- {0x03u, 0x0Au},\r
- {0x04u, 0x04u},\r
- {0x07u, 0x01u},\r
- {0x08u, 0x0Au},\r
- {0x09u, 0x20u},\r
- {0x0Cu, 0x10u},\r
+ {0x03u, 0x40u},\r
+ {0x04u, 0x84u},\r
+ {0x05u, 0x41u},\r
+ {0x0Au, 0x04u},\r
+ {0x0Cu, 0x80u},\r
+ {0x0Du, 0x08u},\r
{0x0Eu, 0x08u},\r
- {0x0Fu, 0x10u},\r
- {0x12u, 0x82u},\r
- {0x13u, 0x14u},\r
- {0x17u, 0x08u},\r
- {0x19u, 0x40u},\r
- {0x1Au, 0x44u},\r
- {0x1Bu, 0x08u},\r
- {0x1Eu, 0x08u},\r
- {0x21u, 0x30u},\r
- {0x22u, 0x08u},\r
- {0x26u, 0x80u},\r
- {0x27u, 0x01u},\r
+ {0x13u, 0x40u},\r
+ {0x15u, 0x28u},\r
+ {0x17u, 0x02u},\r
+ {0x19u, 0x10u},\r
+ {0x1Au, 0x10u},\r
+ {0x1Bu, 0x80u},\r
+ {0x1Cu, 0x04u},\r
+ {0x1Fu, 0x31u},\r
+ {0x21u, 0x01u},\r
+ {0x22u, 0x05u},\r
+ {0x24u, 0x80u},\r
+ {0x27u, 0x12u},\r
+ {0x2Au, 0x20u},\r
+ {0x2Bu, 0x20u},\r
{0x2Cu, 0x20u},\r
- {0x2Eu, 0x20u},\r
- {0x2Fu, 0x80u},\r
- {0x32u, 0x98u},\r
- {0x35u, 0x06u},\r
- {0x36u, 0x80u},\r
- {0x39u, 0xA8u},\r
- {0x3Au, 0x02u},\r
- {0x3Cu, 0x88u},\r
- {0x3Fu, 0x10u},\r
- {0x5Au, 0x80u},\r
- {0x5Bu, 0x26u},\r
- {0x5Fu, 0x80u},\r
- {0x61u, 0x80u},\r
- {0x62u, 0x14u},\r
- {0x63u, 0xA0u},\r
- {0x64u, 0x01u},\r
- {0x67u, 0x02u},\r
- {0x83u, 0x30u},\r
- {0x85u, 0x40u},\r
- {0x87u, 0x03u},\r
- {0x88u, 0x10u},\r
- {0x8Au, 0x10u},\r
- {0x8Bu, 0x02u},\r
- {0x90u, 0xA0u},\r
- {0x91u, 0x84u},\r
- {0x93u, 0x44u},\r
+ {0x2Du, 0x02u},\r
+ {0x2Fu, 0x49u},\r
+ {0x32u, 0x04u},\r
+ {0x33u, 0x10u},\r
+ {0x35u, 0x01u},\r
+ {0x36u, 0x04u},\r
+ {0x37u, 0x10u},\r
+ {0x38u, 0x20u},\r
+ {0x39u, 0x0Au},\r
+ {0x3Cu, 0x28u},\r
+ {0x42u, 0x08u},\r
+ {0x43u, 0x10u},\r
+ {0x58u, 0x04u},\r
+ {0x59u, 0x80u},\r
+ {0x5Bu, 0x20u},\r
+ {0x5Cu, 0x08u},\r
+ {0x5Eu, 0xA2u},\r
+ {0x60u, 0x22u},\r
+ {0x62u, 0x20u},\r
+ {0x63u, 0x18u},\r
+ {0x65u, 0x40u},\r
+ {0x6Du, 0x04u},\r
+ {0x6Eu, 0x08u},\r
+ {0x6Fu, 0x06u},\r
+ {0x81u, 0x20u},\r
+ {0x82u, 0x10u},\r
+ {0x87u, 0xB0u},\r
+ {0x88u, 0x04u},\r
+ {0x8Au, 0x04u},\r
+ {0x8Eu, 0x04u},\r
+ {0x8Fu, 0x14u},\r
+ {0x90u, 0x20u},\r
+ {0x91u, 0x31u},\r
+ {0x93u, 0x80u},\r
{0x95u, 0x08u},\r
- {0x96u, 0x4Cu},\r
- {0x97u, 0x02u},\r
- {0x99u, 0x26u},\r
- {0x9Au, 0x02u},\r
- {0x9Bu, 0x08u},\r
- {0x9Eu, 0x14u},\r
- {0x9Fu, 0x01u},\r
- {0xA0u, 0x60u},\r
- {0xA2u, 0x20u},\r
- {0xA3u, 0x80u},\r
- {0xA4u, 0x04u},\r
- {0xA5u, 0x88u},\r
- {0xA6u, 0x01u},\r
- {0xA7u, 0x40u},\r
- {0xABu, 0xC0u},\r
- {0xACu, 0x10u},\r
- {0xADu, 0x20u},\r
- {0xAFu, 0x04u},\r
+ {0x97u, 0x26u},\r
+ {0x9Au, 0xA2u},\r
+ {0x9Cu, 0x22u},\r
+ {0x9Du, 0x10u},\r
+ {0x9Fu, 0x11u},\r
+ {0xA0u, 0xA6u},\r
+ {0xA1u, 0x28u},\r
+ {0xA2u, 0x51u},\r
+ {0xA3u, 0x08u},\r
+ {0xA6u, 0x08u},\r
+ {0xA7u, 0x04u},\r
+ {0xA9u, 0x80u},\r
+ {0xACu, 0x08u},\r
+ {0xADu, 0x40u},\r
+ {0xAEu, 0x01u},\r
{0xB0u, 0x80u},\r
- {0xB1u, 0x80u},\r
- {0xB7u, 0x20u},\r
- {0xC0u, 0xA7u},\r
- {0xC2u, 0x6Eu},\r
- {0xC4u, 0x2Fu},\r
- {0xCAu, 0xE0u},\r
- {0xCCu, 0xDEu},\r
- {0xCEu, 0x7Fu},\r
- {0xD6u, 0x1Fu},\r
- {0xD8u, 0x1Fu},\r
- {0xE0u, 0x02u},\r
- {0xE2u, 0x01u},\r
- {0xE4u, 0x01u},\r
- {0xE6u, 0x02u},\r
- {0xE8u, 0x0Cu},\r
- {0xECu, 0x0Cu},\r
- {0xEEu, 0x82u},\r
- {0x04u, 0x02u},\r
- {0x05u, 0x0Bu},\r
- {0x07u, 0x90u},\r
- {0x09u, 0x20u},\r
- {0x0Au, 0x04u},\r
- {0x0Bu, 0x03u},\r
- {0x0Cu, 0x02u},\r
- {0x0Fu, 0x04u},\r
- {0x12u, 0x20u},\r
+ {0xB1u, 0x21u},\r
+ {0xB6u, 0x01u},\r
+ {0xB7u, 0x28u},\r
+ {0xC0u, 0x38u},\r
+ {0xC2u, 0xE2u},\r
+ {0xC4u, 0x71u},\r
+ {0xCAu, 0xF6u},\r
+ {0xCCu, 0xE6u},\r
+ {0xCEu, 0x67u},\r
+ {0xD6u, 0xFEu},\r
+ {0xD8u, 0x1Eu},\r
+ {0xE2u, 0x42u},\r
+ {0xE4u, 0x0Au},\r
+ {0xE6u, 0x11u},\r
+ {0xE8u, 0x04u},\r
+ {0xEAu, 0x1Au},\r
+ {0xEEu, 0x08u},\r
+ {0x00u, 0x02u},\r
+ {0x01u, 0x08u},\r
+ {0x02u, 0x01u},\r
+ {0x05u, 0x01u},\r
+ {0x09u, 0x40u},\r
+ {0x0Bu, 0x84u},\r
+ {0x0Cu, 0x08u},\r
+ {0x0Du, 0x91u},\r
+ {0x0Eu, 0x10u},\r
+ {0x0Fu, 0x22u},\r
+ {0x10u, 0x02u},\r
+ {0x12u, 0x01u},\r
+ {0x14u, 0x02u},\r
{0x15u, 0x08u},\r
- {0x16u, 0x08u},\r
- {0x19u, 0x21u},\r
- {0x1Au, 0x10u},\r
- {0x1Bu, 0x44u},\r
- {0x1Cu, 0x02u},\r
- {0x1Du, 0x14u},\r
- {0x1Fu, 0xABu},\r
+ {0x16u, 0x01u},\r
+ {0x18u, 0x01u},\r
+ {0x19u, 0x02u},\r
+ {0x1Au, 0x0Au},\r
+ {0x1Bu, 0x05u},\r
+ {0x1Eu, 0x20u},\r
+ {0x1Fu, 0x70u},\r
{0x20u, 0x02u},\r
- {0x21u, 0x40u},\r
- {0x23u, 0xBFu},\r
- {0x26u, 0x01u},\r
- {0x28u, 0x14u},\r
- {0x2Au, 0x28u},\r
- {0x2Bu, 0x0Eu},\r
- {0x30u, 0x02u},\r
- {0x32u, 0x0Cu},\r
- {0x33u, 0x1Fu},\r
- {0x34u, 0x01u},\r
- {0x35u, 0xE0u},\r
- {0x36u, 0x30u},\r
- {0x38u, 0x02u},\r
- {0x3Bu, 0x20u},\r
- {0x3Eu, 0x45u},\r
+ {0x21u, 0x08u},\r
+ {0x22u, 0x15u},\r
+ {0x24u, 0x20u},\r
+ {0x25u, 0xA0u},\r
+ {0x26u, 0x40u},\r
+ {0x27u, 0x55u},\r
+ {0x29u, 0x08u},\r
+ {0x2Au, 0x40u},\r
+ {0x2Fu, 0x80u},\r
+ {0x30u, 0x18u},\r
+ {0x31u, 0x08u},\r
+ {0x32u, 0x60u},\r
+ {0x33u, 0x07u},\r
+ {0x34u, 0x03u},\r
+ {0x36u, 0x04u},\r
+ {0x37u, 0xF0u},\r
+ {0x39u, 0x02u},\r
+ {0x3Au, 0x20u},\r
+ {0x3Bu, 0x08u},\r
+ {0x3Eu, 0x05u},\r
+ {0x3Fu, 0x01u},\r
{0x56u, 0x08u},\r
{0x58u, 0x04u},\r
{0x59u, 0x04u},\r
{0x5Cu, 0x19u},\r
{0x5Du, 0x90u},\r
{0x5Fu, 0x01u},\r
- {0x80u, 0x01u},\r
- {0x85u, 0x01u},\r
- {0x87u, 0x02u},\r
- {0x88u, 0x02u},\r
- {0x89u, 0x04u},\r
- {0x8Bu, 0x03u},\r
- {0x95u, 0x08u},\r
- {0x97u, 0x03u},\r
- {0x9Bu, 0x01u},\r
- {0x9Cu, 0x0Eu},\r
- {0x9Fu, 0x0Cu},\r
- {0xA4u, 0x08u},\r
- {0xAAu, 0x04u},\r
- {0xABu, 0x02u},\r
- {0xAEu, 0x0Eu},\r
- {0xB0u, 0x01u},\r
- {0xB1u, 0x0Fu},\r
- {0xB4u, 0x0Eu},\r
- {0xBEu, 0x10u},\r
+ {0x84u, 0x40u},\r
+ {0x86u, 0x1Fu},\r
+ {0x88u, 0x03u},\r
+ {0x8Au, 0x0Cu},\r
+ {0x8Cu, 0x06u},\r
+ {0x8Eu, 0x09u},\r
+ {0x92u, 0x70u},\r
+ {0x98u, 0x0Fu},\r
+ {0xA0u, 0x05u},\r
+ {0xA2u, 0x0Au},\r
+ {0xA3u, 0x01u},\r
+ {0xA4u, 0x10u},\r
+ {0xA6u, 0x2Fu},\r
+ {0xA8u, 0x20u},\r
+ {0xAAu, 0x4Fu},\r
+ {0xB0u, 0x7Fu},\r
+ {0xB1u, 0x01u},\r
{0xD8u, 0x04u},\r
{0xD9u, 0x04u},\r
- {0xDCu, 0x09u},\r
+ {0xDCu, 0x91u},\r
{0xDFu, 0x01u},\r
- {0x00u, 0x40u},\r
- {0x02u, 0x10u},\r
- {0x03u, 0x08u},\r
- {0x05u, 0x02u},\r
- {0x06u, 0x08u},\r
- {0x08u, 0x10u},\r
- {0x09u, 0x02u},\r
- {0x0Au, 0x11u},\r
- {0x0Du, 0x40u},\r
- {0x10u, 0x80u},\r
- {0x12u, 0x24u},\r
- {0x17u, 0x98u},\r
- {0x19u, 0x08u},\r
- {0x1Au, 0x88u},\r
- {0x1Bu, 0x40u},\r
- {0x1Du, 0x10u},\r
- {0x1Eu, 0x40u},\r
- {0x20u, 0x0Cu},\r
- {0x21u, 0x14u},\r
- {0x22u, 0x10u},\r
- {0x23u, 0x10u},\r
- {0x27u, 0x80u},\r
- {0x29u, 0x02u},\r
- {0x2Au, 0x20u},\r
- {0x2Cu, 0x08u},\r
- {0x31u, 0x04u},\r
- {0x32u, 0x90u},\r
- {0x36u, 0x10u},\r
- {0x37u, 0x88u},\r
- {0x38u, 0xA0u},\r
- {0x39u, 0x18u},\r
- {0x3Cu, 0x20u},\r
- {0x3Eu, 0x0Cu},\r
- {0x44u, 0x02u},\r
- {0x45u, 0x40u},\r
- {0x58u, 0x80u},\r
- {0x5Bu, 0x24u},\r
- {0x60u, 0x0Au},\r
- {0x61u, 0x08u},\r
- {0x82u, 0x40u},\r
- {0x83u, 0x04u},\r
- {0x86u, 0x02u},\r
- {0x88u, 0x04u},\r
- {0x89u, 0x14u},\r
- {0x8Du, 0x08u},\r
- {0x8Fu, 0x40u},\r
- {0x90u, 0xA0u},\r
- {0x91u, 0x04u},\r
- {0x93u, 0x40u},\r
- {0x94u, 0x04u},\r
- {0x95u, 0x08u},\r
- {0x96u, 0x28u},\r
- {0x97u, 0x10u},\r
- {0x98u, 0x11u},\r
- {0x99u, 0x26u},\r
- {0x9Cu, 0x0Au},\r
- {0x9Eu, 0x20u},\r
- {0xA1u, 0x20u},\r
- {0xA2u, 0xA0u},\r
- {0xA3u, 0x08u},\r
- {0xA4u, 0x04u},\r
- {0xA5u, 0x08u},\r
- {0xA6u, 0x02u},\r
- {0xAAu, 0x01u},\r
- {0xABu, 0x04u},\r
- {0xAEu, 0x08u},\r
- {0xAFu, 0x80u},\r
- {0xB6u, 0x40u},\r
- {0xC0u, 0x57u},\r
- {0xC2u, 0x8Fu},\r
- {0xC4u, 0xEEu},\r
- {0xCAu, 0x25u},\r
- {0xCCu, 0x7Eu},\r
- {0xCEu, 0x6Eu},\r
- {0xD6u, 0x0Eu},\r
- {0xD8u, 0x0Eu},\r
- {0xE0u, 0x02u},\r
- {0xE2u, 0x41u},\r
- {0xE8u, 0x08u},\r
- {0xEAu, 0x07u},\r
- {0xEEu, 0x41u},\r
- {0x00u, 0x0Du},\r
- {0x04u, 0x0Du},\r
- {0x07u, 0xFFu},\r
- {0x08u, 0x0Du},\r
- {0x0Bu, 0xFFu},\r
- {0x0Du, 0x33u},\r
- {0x0Fu, 0xCCu},\r
- {0x10u, 0x02u},\r
- {0x11u, 0x55u},\r
- {0x12u, 0x0Du},\r
- {0x13u, 0xAAu},\r
- {0x15u, 0x69u},\r
- {0x16u, 0x80u},\r
- {0x17u, 0x96u},\r
- {0x18u, 0x01u},\r
- {0x19u, 0x0Fu},\r
- {0x1Au, 0x32u},\r
- {0x1Bu, 0xF0u},\r
- {0x1Du, 0xFFu},\r
- {0x1Eu, 0x10u},\r
- {0x20u, 0x0Du},\r
- {0x23u, 0xFFu},\r
- {0x24u, 0x62u},\r
- {0x26u, 0x08u},\r
- {0x28u, 0x02u},\r
- {0x29u, 0xFFu},\r
- {0x2Au, 0x54u},\r
- {0x2Cu, 0x0Du},\r
- {0x30u, 0x0Fu},\r
+ {0x01u, 0x40u},\r
+ {0x03u, 0x80u},\r
+ {0x04u, 0xA4u},\r
+ {0x09u, 0x01u},\r
+ {0x0Au, 0x16u},\r
+ {0x0Eu, 0x88u},\r
+ {0x10u, 0x14u},\r
+ {0x12u, 0x40u},\r
+ {0x15u, 0x08u},\r
+ {0x17u, 0x12u},\r
+ {0x19u, 0x01u},\r
+ {0x1Au, 0xA4u},\r
+ {0x1Bu, 0x90u},\r
+ {0x1Eu, 0x80u},\r
+ {0x1Fu, 0x02u},\r
+ {0x20u, 0x20u},\r
+ {0x21u, 0x04u},\r
+ {0x22u, 0x80u},\r
+ {0x23u, 0x80u},\r
+ {0x25u, 0x01u},\r
+ {0x27u, 0x40u},\r
+ {0x28u, 0x40u},\r
+ {0x2Au, 0x88u},\r
+ {0x2Bu, 0x08u},\r
+ {0x2Fu, 0x80u},\r
+ {0x30u, 0x08u},\r
+ {0x31u, 0x20u},\r
{0x32u, 0x80u},\r
- {0x35u, 0xFFu},\r
- {0x36u, 0x70u},\r
- {0x3Au, 0x02u},\r
- {0x3Bu, 0x20u},\r
- {0x58u, 0x04u},\r
- {0x59u, 0x04u},\r
- {0x5Cu, 0x10u},\r
- {0x5Fu, 0x01u},\r
- {0x80u, 0xFFu},\r
- {0x84u, 0x30u},\r
- {0x86u, 0xC0u},\r
- {0x87u, 0x80u},\r
- {0x88u, 0x0Fu},\r
+ {0x39u, 0x04u},\r
+ {0x3Bu, 0xA2u},\r
+ {0x59u, 0x64u},\r
+ {0x5Au, 0x01u},\r
+ {0x62u, 0x48u},\r
+ {0x63u, 0x44u},\r
+ {0x69u, 0x40u},\r
+ {0x81u, 0x04u},\r
+ {0x83u, 0x80u},\r
+ {0x84u, 0x14u},\r
+ {0x86u, 0x80u},\r
{0x89u, 0x44u},\r
- {0x8Au, 0xF0u},\r
- {0x8Bu, 0x88u},\r
- {0x8Cu, 0xFFu},\r
- {0x8Fu, 0x08u},\r
- {0x90u, 0x50u},\r
- {0x92u, 0xA0u},\r
- {0x93u, 0x07u},\r
- {0x94u, 0x09u},\r
- {0x96u, 0x06u},\r
- {0x97u, 0x70u},\r
- {0x98u, 0x05u},\r
- {0x99u, 0x99u},\r
- {0x9Au, 0x0Au},\r
- {0x9Bu, 0x22u},\r
- {0x9Du, 0xAAu},\r
- {0x9Fu, 0x55u},\r
- {0xA4u, 0x03u},\r
- {0xA6u, 0x0Cu},\r
- {0xAAu, 0xFFu},\r
- {0xACu, 0x90u},\r
- {0xAEu, 0x60u},\r
- {0xB0u, 0xFFu},\r
- {0xB1u, 0x0Fu},\r
- {0xB3u, 0xF0u},\r
- {0xBEu, 0x01u},\r
- {0xD8u, 0x04u},\r
- {0xD9u, 0x04u},\r
- {0xDBu, 0x04u},\r
- {0xDCu, 0x10u},\r
- {0xDFu, 0x01u},\r
- {0x00u, 0x04u},\r
- {0x01u, 0x80u},\r
- {0x02u, 0x44u},\r
- {0x03u, 0x08u},\r
- {0x04u, 0x28u},\r
- {0x07u, 0x40u},\r
- {0x08u, 0x14u},\r
- {0x09u, 0x02u},\r
- {0x0Cu, 0x08u},\r
- {0x0Eu, 0x46u},\r
- {0x10u, 0x20u},\r
- {0x11u, 0x10u},\r
- {0x12u, 0x01u},\r
- {0x15u, 0x41u},\r
- {0x17u, 0x18u},\r
- {0x18u, 0x40u},\r
- {0x1Eu, 0x62u},\r
- {0x21u, 0x08u},\r
- {0x22u, 0x01u},\r
- {0x26u, 0x20u},\r
- {0x2Du, 0x02u},\r
- {0x2Eu, 0x20u},\r
- {0x31u, 0x08u},\r
- {0x32u, 0x91u},\r
- {0x34u, 0x09u},\r
- {0x36u, 0xA0u},\r
- {0x39u, 0x04u},\r
- {0x3Bu, 0x50u},\r
- {0x3Cu, 0x08u},\r
- {0x3Du, 0x80u},\r
- {0x3Fu, 0x10u},\r
- {0x58u, 0x80u},\r
- {0x59u, 0x22u},\r
- {0x5Au, 0x08u},\r
- {0x63u, 0x02u},\r
- {0x80u, 0x80u},\r
- {0x85u, 0x10u},\r
- {0x88u, 0x20u},\r
- {0x89u, 0x08u},\r
- {0x8Au, 0x01u},\r
- {0x8Bu, 0x01u},\r
- {0x8Eu, 0x01u},\r
- {0x91u, 0x14u},\r
- {0x92u, 0x20u},\r
- {0x93u, 0x50u},\r
- {0x94u, 0x40u},\r
- {0x95u, 0x80u},\r
- {0x96u, 0x15u},\r
- {0x98u, 0x19u},\r
- {0x99u, 0x32u},\r
- {0x9Au, 0x20u},\r
- {0x9Eu, 0x14u},\r
- {0x9Fu, 0x18u},\r
- {0xA0u, 0x04u},\r
- {0xA1u, 0x40u},\r
- {0xA2u, 0x80u},\r
- {0xA4u, 0x98u},\r
- {0xA5u, 0x02u},\r
- {0xA6u, 0x12u},\r
- {0xAAu, 0x60u},\r
- {0xABu, 0x20u},\r
- {0xACu, 0x80u},\r
- {0xB1u, 0x08u},\r
- {0xB5u, 0x20u},\r
- {0xB7u, 0x08u},\r
- {0xC0u, 0x7Fu},\r
- {0xC2u, 0xFEu},\r
- {0xC4u, 0xF7u},\r
- {0xCAu, 0xA0u},\r
- {0xCCu, 0xFFu},\r
- {0xCEu, 0x7Eu},\r
- {0xD6u, 0x0Fu},\r
- {0xD8u, 0x08u},\r
- {0xE2u, 0x58u},\r
- {0xE6u, 0x01u},\r
- {0xEAu, 0x05u},\r
- {0xEEu, 0x02u},\r
- {0x39u, 0x80u},\r
- {0x3Fu, 0x40u},\r
- {0x59u, 0x04u},\r
- {0x5Fu, 0x01u},\r
- {0x24u, 0x02u},\r
- {0x7Au, 0x30u},\r
- {0x80u, 0x14u},\r
- {0x88u, 0x20u},\r
- {0x89u, 0x10u},\r
- {0x8Au, 0x08u},\r
- {0x8Cu, 0x01u},\r
- {0x90u, 0x10u},\r
- {0x91u, 0x02u},\r
- {0x94u, 0x08u},\r
- {0x95u, 0x01u},\r
- {0x97u, 0x01u},\r
- {0x98u, 0x28u},\r
- {0x9Au, 0x22u},\r
+ {0x8Bu, 0x40u},\r
+ {0x90u, 0x04u},\r
+ {0x91u, 0x15u},\r
+ {0x92u, 0x12u},\r
+ {0x93u, 0x30u},\r
+ {0x95u, 0x08u},\r
+ {0x96u, 0x20u},\r
+ {0x97u, 0x44u},\r
+ {0x98u, 0x42u},\r
+ {0x99u, 0x20u},\r
+ {0x9Au, 0x9Au},\r
{0x9Bu, 0x10u},\r
- {0x9Du, 0x0Bu},\r
- {0x9Eu, 0x18u},\r
- {0xA2u, 0x62u},\r
- {0xA4u, 0x80u},\r
- {0xABu, 0x02u},\r
+ {0x9Du, 0x01u},\r
+ {0x9Fu, 0x41u},\r
+ {0xA0u, 0x02u},\r
+ {0xA1u, 0x20u},\r
+ {0xA2u, 0x24u},\r
+ {0xA4u, 0x10u},\r
+ {0xA6u, 0x08u},\r
+ {0xA8u, 0x08u},\r
+ {0xA9u, 0x02u},\r
+ {0xACu, 0x40u},\r
+ {0xAEu, 0x10u},\r
+ {0xAFu, 0x02u},\r
+ {0xB1u, 0x80u},\r
{0xB2u, 0x04u},\r
- {0xB6u, 0x01u},\r
- {0xB7u, 0x10u},\r
- {0xE0u, 0x24u},\r
- {0xE2u, 0xC8u},\r
- {0xE4u, 0x20u},\r
- {0xE8u, 0x10u},\r
- {0xEAu, 0x01u},\r
- {0xECu, 0x60u},\r
- {0xEEu, 0x02u},\r
- {0x00u, 0x04u},\r
- {0x02u, 0x08u},\r
- {0x04u, 0x02u},\r
- {0x06u, 0x01u},\r
- {0x07u, 0x20u},\r
- {0x08u, 0x01u},\r
- {0x09u, 0x04u},\r
- {0x0Au, 0x02u},\r
- {0x0Bu, 0x08u},\r
- {0x0Cu, 0x02u},\r
- {0x0Du, 0x03u},\r
+ {0xC0u, 0xE9u},\r
+ {0xC2u, 0x5Fu},\r
+ {0xC4u, 0x7Eu},\r
+ {0xCAu, 0x8Fu},\r
+ {0xCCu, 0x0Eu},\r
+ {0xCEu, 0x0Fu},\r
+ {0xD6u, 0x0Fu},\r
+ {0xD8u, 0x0Fu},\r
+ {0xE2u, 0x18u},\r
+ {0xE4u, 0x08u},\r
+ {0xE6u, 0x23u},\r
+ {0xEAu, 0x03u},\r
+ {0xEEu, 0x08u},\r
+ {0x03u, 0x02u},\r
+ {0x05u, 0x01u},\r
+ {0x06u, 0x0Cu},\r
+ {0x09u, 0x10u},\r
+ {0x0Bu, 0x28u},\r
+ {0x0Du, 0x07u},\r
{0x0Eu, 0x01u},\r
- {0x0Fu, 0x0Cu},\r
- {0x11u, 0x02u},\r
- {0x12u, 0x20u},\r
- {0x13u, 0x01u},\r
- {0x14u, 0x02u},\r
- {0x16u, 0x01u},\r
- {0x1Au, 0x10u},\r
+ {0x11u, 0x08u},\r
+ {0x14u, 0x28u},\r
+ {0x16u, 0x13u},\r
+ {0x17u, 0x07u},\r
+ {0x18u, 0x60u},\r
+ {0x19u, 0x18u},\r
+ {0x1Bu, 0x20u},\r
+ {0x1Cu, 0x14u},\r
{0x1Du, 0x08u},\r
- {0x1Fu, 0x04u},\r
- {0x21u, 0x01u},\r
- {0x22u, 0x08u},\r
- {0x23u, 0x02u},\r
- {0x24u, 0x02u},\r
- {0x26u, 0x01u},\r
- {0x27u, 0x10u},\r
- {0x2Au, 0x04u},\r
- {0x2Cu, 0x10u},\r
- {0x2Eu, 0x20u},\r
- {0x30u, 0x30u},\r
- {0x31u, 0x20u},\r
- {0x32u, 0x03u},\r
- {0x33u, 0x10u},\r
- {0x34u, 0x0Cu},\r
- {0x35u, 0x0Fu},\r
- {0x3Au, 0x08u},\r
- {0x3Eu, 0x11u},\r
+ {0x1Eu, 0x43u},\r
+ {0x1Fu, 0x30u},\r
+ {0x22u, 0x82u},\r
+ {0x23u, 0x08u},\r
+ {0x25u, 0x10u},\r
+ {0x27u, 0x28u},\r
+ {0x28u, 0x11u},\r
+ {0x29u, 0x04u},\r
+ {0x2Au, 0x22u},\r
+ {0x32u, 0x0Fu},\r
+ {0x34u, 0x70u},\r
+ {0x35u, 0x07u},\r
+ {0x36u, 0x80u},\r
+ {0x37u, 0x38u},\r
+ {0x38u, 0x20u},\r
+ {0x3Bu, 0x80u},\r
{0x3Fu, 0x10u},\r
- {0x56u, 0x08u},\r
{0x58u, 0x04u},\r
{0x59u, 0x04u},\r
- {0x5Bu, 0x04u},\r
- {0x5Cu, 0x99u},\r
- {0x5Du, 0x90u},\r
+ {0x5Cu, 0x10u},\r
{0x5Fu, 0x01u},\r
- {0x81u, 0x60u},\r
- {0x83u, 0x90u},\r
- {0x84u, 0x03u},\r
- {0x85u, 0x03u},\r
- {0x86u, 0x0Cu},\r
- {0x87u, 0x0Cu},\r
- {0x88u, 0x06u},\r
- {0x89u, 0x06u},\r
- {0x8Au, 0x09u},\r
- {0x8Bu, 0x09u},\r
+ {0x80u, 0x33u},\r
+ {0x82u, 0xCCu},\r
+ {0x83u, 0xFFu},\r
+ {0x84u, 0xFFu},\r
+ {0x87u, 0xFFu},\r
+ {0x8Au, 0xFFu},\r
+ {0x8Bu, 0xFFu},\r
{0x8Cu, 0x0Fu},\r
- {0x92u, 0x70u},\r
- {0x95u, 0x05u},\r
- {0x97u, 0x0Au},\r
+ {0x8Du, 0x0Fu},\r
+ {0x8Eu, 0xF0u},\r
+ {0x8Fu, 0xF0u},\r
+ {0x90u, 0xFFu},\r
+ {0x96u, 0xFFu},\r
+ {0x9Du, 0xFFu},\r
+ {0xA1u, 0x55u},\r
+ {0xA2u, 0xFFu},\r
+ {0xA3u, 0xAAu},\r
+ {0xA4u, 0x96u},\r
+ {0xA5u, 0xFFu},\r
+ {0xA6u, 0x69u},\r
+ {0xA8u, 0x55u},\r
+ {0xA9u, 0x33u},\r
+ {0xAAu, 0xAAu},\r
+ {0xABu, 0xCCu},\r
+ {0xADu, 0x69u},\r
+ {0xAFu, 0x96u},\r
+ {0xB0u, 0xFFu},\r
+ {0xB7u, 0xFFu},\r
+ {0xBAu, 0x02u},\r
+ {0xBBu, 0x80u},\r
+ {0xD6u, 0x08u},\r
+ {0xD8u, 0x04u},\r
+ {0xD9u, 0x04u},\r
+ {0xDBu, 0x04u},\r
+ {0xDCu, 0x11u},\r
+ {0xDDu, 0x90u},\r
+ {0xDFu, 0x01u},\r
+ {0x00u, 0x20u},\r
+ {0x01u, 0x08u},\r
+ {0x02u, 0x40u},\r
+ {0x03u, 0x12u},\r
+ {0x05u, 0x44u},\r
+ {0x0Au, 0x80u},\r
+ {0x0Bu, 0x20u},\r
+ {0x0Cu, 0x08u},\r
+ {0x0Eu, 0x08u},\r
+ {0x0Fu, 0x22u},\r
+ {0x11u, 0x01u},\r
+ {0x12u, 0x20u},\r
+ {0x13u, 0x10u},\r
+ {0x16u, 0x88u},\r
+ {0x17u, 0x20u},\r
+ {0x18u, 0x80u},\r
+ {0x1Bu, 0x02u},\r
+ {0x1Du, 0x44u},\r
+ {0x1Eu, 0x08u},\r
+ {0x21u, 0x40u},\r
+ {0x23u, 0x02u},\r
+ {0x25u, 0x10u},\r
+ {0x26u, 0x80u},\r
+ {0x27u, 0x01u},\r
+ {0x28u, 0x02u},\r
+ {0x29u, 0x08u},\r
+ {0x2Au, 0x12u},\r
+ {0x2Cu, 0x08u},\r
+ {0x2Du, 0x01u},\r
+ {0x2Fu, 0x10u},\r
+ {0x32u, 0x40u},\r
+ {0x35u, 0x05u},\r
+ {0x36u, 0x80u},\r
+ {0x37u, 0x10u},\r
+ {0x39u, 0x89u},\r
+ {0x3Bu, 0x20u},\r
+ {0x3Cu, 0x60u},\r
+ {0x3Eu, 0x08u},\r
+ {0x3Fu, 0x02u},\r
+ {0x5Bu, 0x40u},\r
+ {0x62u, 0x40u},\r
+ {0x8Bu, 0x08u},\r
+ {0x8Fu, 0x01u},\r
+ {0x91u, 0x19u},\r
+ {0x92u, 0x80u},\r
+ {0x93u, 0x74u},\r
+ {0x94u, 0xA0u},\r
+ {0x97u, 0x02u},\r
+ {0x98u, 0x02u},\r
+ {0x99u, 0x01u},\r
+ {0x9Au, 0x12u},\r
+ {0x9Bu, 0x10u},\r
+ {0x9Fu, 0x03u},\r
+ {0xA0u, 0x12u},\r
+ {0xA2u, 0x28u},\r
+ {0xA7u, 0x08u},\r
+ {0xA8u, 0x08u},\r
+ {0xABu, 0x10u},\r
+ {0xAEu, 0x01u},\r
+ {0xB2u, 0x01u},\r
+ {0xB3u, 0x02u},\r
+ {0xB5u, 0x01u},\r
+ {0xC0u, 0xAFu},\r
+ {0xC2u, 0xECu},\r
+ {0xC4u, 0x5Eu},\r
+ {0xCAu, 0xEFu},\r
+ {0xCCu, 0xF8u},\r
+ {0xCEu, 0xFFu},\r
+ {0xD6u, 0x08u},\r
+ {0xD8u, 0x08u},\r
+ {0xE2u, 0x0Du},\r
+ {0xEAu, 0x0Du},\r
+ {0xECu, 0x01u},\r
+ {0x00u, 0x0Fu},\r
+ {0x01u, 0x03u},\r
+ {0x02u, 0xF0u},\r
+ {0x03u, 0x0Cu},\r
+ {0x04u, 0x30u},\r
+ {0x05u, 0xFFu},\r
+ {0x06u, 0xC0u},\r
+ {0x0Au, 0xFFu},\r
+ {0x0Cu, 0x03u},\r
+ {0x0Du, 0x05u},\r
+ {0x0Eu, 0x0Cu},\r
+ {0x0Fu, 0x0Au},\r
+ {0x10u, 0x05u},\r
+ {0x12u, 0x0Au},\r
+ {0x14u, 0x09u},\r
+ {0x15u, 0x50u},\r
+ {0x16u, 0x06u},\r
+ {0x17u, 0xA0u},\r
+ {0x19u, 0x30u},\r
+ {0x1Au, 0xFFu},\r
+ {0x1Bu, 0xC0u},\r
+ {0x1Du, 0x0Fu},\r
+ {0x1Eu, 0xFFu},\r
+ {0x1Fu, 0xF0u},\r
+ {0x20u, 0x90u},\r
+ {0x21u, 0x90u},\r
+ {0x22u, 0x60u},\r
+ {0x23u, 0x60u},\r
+ {0x24u, 0x50u},\r
+ {0x26u, 0xA0u},\r
+ {0x27u, 0xFFu},\r
+ {0x29u, 0x09u},\r
+ {0x2Bu, 0x06u},\r
+ {0x2Du, 0xFFu},\r
+ {0x36u, 0xFFu},\r
+ {0x37u, 0xFFu},\r
+ {0x3Eu, 0x40u},\r
+ {0x3Fu, 0x40u},\r
+ {0x58u, 0x04u},\r
+ {0x59u, 0x04u},\r
+ {0x5Fu, 0x01u},\r
+ {0x80u, 0x06u},\r
+ {0x82u, 0x18u},\r
+ {0x84u, 0x02u},\r
+ {0x85u, 0x02u},\r
+ {0x86u, 0x04u},\r
+ {0x8Cu, 0x40u},\r
+ {0x8Eu, 0x20u},\r
+ {0x90u, 0x40u},\r
+ {0x92u, 0x20u},\r
+ {0x93u, 0x01u},\r
+ {0x94u, 0x04u},\r
+ {0x96u, 0x02u},\r
{0x98u, 0x20u},\r
- {0x99u, 0x50u},\r
- {0x9Au, 0x4Fu},\r
- {0x9Bu, 0xA0u},\r
- {0x9Cu, 0x05u},\r
- {0x9Du, 0x0Fu},\r
- {0x9Eu, 0x0Au},\r
- {0x9Fu, 0xF0u},\r
- {0xA1u, 0x30u},\r
- {0xA3u, 0xC0u},\r
+ {0x9Au, 0x40u},\r
+ {0x9Cu, 0x40u},\r
+ {0x9Eu, 0x20u},\r
+ {0xA0u, 0x10u},\r
+ {0xA2u, 0x08u},\r
{0xA8u, 0x40u},\r
- {0xAAu, 0x1Fu},\r
- {0xACu, 0x10u},\r
- {0xAEu, 0x2Fu},\r
- {0xB0u, 0x7Fu},\r
+ {0xA9u, 0x08u},\r
+ {0xAAu, 0x21u},\r
+ {0xACu, 0x08u},\r
+ {0xAEu, 0x10u},\r
+ {0xAFu, 0x04u},\r
+ {0xB0u, 0x1Eu},\r
+ {0xB1u, 0x04u},\r
+ {0xB3u, 0x01u},\r
+ {0xB4u, 0x60u},\r
+ {0xB5u, 0x02u},\r
+ {0xB6u, 0x01u},\r
+ {0xB7u, 0x08u},\r
+ {0xBAu, 0x20u},\r
+ {0xBEu, 0x01u},\r
+ {0xD6u, 0x08u},\r
+ {0xD8u, 0x04u},\r
+ {0xD9u, 0x04u},\r
+ {0xDBu, 0x04u},\r
+ {0xDCu, 0x99u},\r
+ {0xDDu, 0x90u},\r
+ {0xDFu, 0x01u},\r
+ {0x01u, 0x80u},\r
+ {0x02u, 0x40u},\r
+ {0x03u, 0x20u},\r
+ {0x04u, 0x22u},\r
+ {0x06u, 0x4Au},\r
+ {0x07u, 0x90u},\r
+ {0x08u, 0x06u},\r
+ {0x0Au, 0x0Au},\r
+ {0x0Cu, 0x18u},\r
+ {0x0Du, 0x02u},\r
+ {0x0Eu, 0x01u},\r
+ {0x0Fu, 0x6Au},\r
+ {0x10u, 0x80u},\r
+ {0x12u, 0x09u},\r
+ {0x14u, 0x40u},\r
+ {0x17u, 0x05u},\r
+ {0x19u, 0xA0u},\r
+ {0x1Au, 0x08u},\r
+ {0x1Bu, 0x03u},\r
+ {0x1Fu, 0x80u},\r
+ {0x21u, 0x40u},\r
+ {0x22u, 0x09u},\r
+ {0x23u, 0x04u},\r
+ {0x26u, 0x40u},\r
+ {0x28u, 0x02u},\r
+ {0x29u, 0x20u},\r
+ {0x2Cu, 0x58u},\r
+ {0x2Fu, 0x02u},\r
+ {0x32u, 0x01u},\r
+ {0x37u, 0x94u},\r
+ {0x39u, 0x08u},\r
+ {0x3Eu, 0x0Au},\r
+ {0x3Fu, 0x40u},\r
+ {0x58u, 0x80u},\r
+ {0x60u, 0x02u},\r
+ {0x81u, 0x40u},\r
+ {0x8Au, 0x40u},\r
+ {0x8Fu, 0x80u},\r
+ {0x90u, 0x22u},\r
+ {0x91u, 0x08u},\r
+ {0x96u, 0x09u},\r
+ {0x98u, 0x04u},\r
+ {0x9Au, 0x03u},\r
+ {0x9Bu, 0x15u},\r
+ {0xA0u, 0x80u},\r
+ {0xA3u, 0x24u},\r
+ {0xA5u, 0x02u},\r
+ {0xA7u, 0x12u},\r
+ {0xA8u, 0x02u},\r
+ {0xA9u, 0x08u},\r
+ {0xB0u, 0x80u},\r
+ {0xB1u, 0x80u},\r
+ {0xB7u, 0x40u},\r
+ {0xC0u, 0xFDu},\r
+ {0xC2u, 0xFFu},\r
+ {0xC4u, 0x3Bu},\r
+ {0xCAu, 0xFCu},\r
+ {0xCCu, 0x71u},\r
+ {0xCEu, 0xD2u},\r
+ {0xD6u, 0x08u},\r
+ {0xD8u, 0x08u},\r
+ {0xE2u, 0x6Cu},\r
+ {0xE8u, 0x20u},\r
+ {0xEAu, 0x0Cu},\r
+ {0xECu, 0xC0u},\r
+ {0x00u, 0x01u},\r
+ {0x01u, 0x0Fu},\r
+ {0x02u, 0x02u},\r
+ {0x03u, 0xF0u},\r
+ {0x06u, 0x01u},\r
+ {0x09u, 0xFFu},\r
+ {0x0Du, 0x60u},\r
+ {0x0Eu, 0x02u},\r
+ {0x0Fu, 0x90u},\r
+ {0x11u, 0x05u},\r
+ {0x13u, 0x0Au},\r
+ {0x15u, 0x50u},\r
+ {0x17u, 0xA0u},\r
+ {0x19u, 0x30u},\r
+ {0x1Bu, 0xC0u},\r
+ {0x21u, 0x03u},\r
+ {0x23u, 0x0Cu},\r
+ {0x25u, 0x06u},\r
+ {0x27u, 0x09u},\r
+ {0x2Bu, 0xFFu},\r
+ {0x2Fu, 0xFFu},\r
+ {0x33u, 0xFFu},\r
+ {0x34u, 0x03u},\r
+ {0x3Eu, 0x10u},\r
+ {0x3Fu, 0x04u},\r
+ {0x58u, 0x04u},\r
+ {0x59u, 0x04u},\r
+ {0x5Bu, 0x04u},\r
+ {0x5Fu, 0x01u},\r
+ {0x80u, 0x10u},\r
+ {0x81u, 0x0Fu},\r
+ {0x82u, 0x20u},\r
+ {0x83u, 0xF0u},\r
+ {0x85u, 0x50u},\r
+ {0x87u, 0xA0u},\r
+ {0x88u, 0x0Au},\r
+ {0x8Au, 0x05u},\r
+ {0x91u, 0x05u},\r
+ {0x92u, 0x20u},\r
+ {0x93u, 0x0Au},\r
+ {0x96u, 0x10u},\r
+ {0x99u, 0x03u},\r
+ {0x9Au, 0x07u},\r
+ {0x9Bu, 0x0Cu},\r
+ {0x9Du, 0x06u},\r
+ {0x9Eu, 0x08u},\r
+ {0x9Fu, 0x09u},\r
+ {0xA0u, 0x09u},\r
+ {0xA2u, 0x02u},\r
+ {0xA4u, 0x04u},\r
+ {0xA5u, 0x60u},\r
+ {0xA6u, 0x08u},\r
+ {0xA7u, 0x90u},\r
+ {0xADu, 0x30u},\r
+ {0xAFu, 0xC0u},\r
+ {0xB2u, 0x30u},\r
{0xB3u, 0xFFu},\r
+ {0xB4u, 0x0Fu},\r
+ {0xBEu, 0x04u},\r
{0xBFu, 0x04u},\r
{0xD4u, 0x01u},\r
{0xD8u, 0x04u},\r
{0xDCu, 0x01u},\r
{0xDDu, 0x10u},\r
{0xDFu, 0x01u},\r
- {0x00u, 0x10u},\r
- {0x01u, 0x08u},\r
- {0x02u, 0x42u},\r
- {0x03u, 0x80u},\r
- {0x04u, 0x08u},\r
- {0x06u, 0x02u},\r
+ {0x00u, 0x81u},\r
+ {0x03u, 0x20u},\r
+ {0x04u, 0x02u},\r
{0x07u, 0x08u},\r
- {0x08u, 0x22u},\r
- {0x09u, 0x28u},\r
- {0x0Cu, 0x20u},\r
- {0x0Eu, 0x42u},\r
- {0x10u, 0x08u},\r
- {0x11u, 0x41u},\r
- {0x13u, 0x04u},\r
- {0x14u, 0x05u},\r
- {0x18u, 0x90u},\r
- {0x1Au, 0x08u},\r
- {0x1Bu, 0x02u},\r
- {0x1Eu, 0x40u},\r
+ {0x0Cu, 0x02u},\r
+ {0x0Du, 0x40u},\r
+ {0x0Eu, 0x28u},\r
+ {0x15u, 0x04u},\r
+ {0x16u, 0x40u},\r
+ {0x1Au, 0x04u},\r
+ {0x1Cu, 0x10u},\r
+ {0x1Eu, 0x08u},\r
+ {0x1Fu, 0x20u},\r
{0x21u, 0x08u},\r
- {0x22u, 0x22u},\r
- {0x27u, 0x10u},\r
- {0x29u, 0x18u},\r
- {0x2Au, 0x11u},\r
- {0x2Cu, 0x08u},\r
- {0x2Du, 0x02u},\r
- {0x2Eu, 0x20u},\r
- {0x30u, 0x80u},\r
- {0x32u, 0x01u},\r
- {0x35u, 0x10u},\r
- {0x36u, 0x40u},\r
- {0x37u, 0x04u},\r
- {0x39u, 0x20u},\r
- {0x3Au, 0x40u},\r
- {0x3Bu, 0x04u},\r
- {0x3Eu, 0x08u},\r
- {0x3Fu, 0x21u},\r
- {0x58u, 0x80u},\r
- {0x5Bu, 0x20u},\r
- {0x5Eu, 0x40u},\r
+ {0x24u, 0x20u},\r
+ {0x2Au, 0x02u},\r
+ {0x2Bu, 0x16u},\r
+ {0x2Cu, 0x22u},\r
+ {0x31u, 0x02u},\r
+ {0x33u, 0x14u},\r
+ {0x34u, 0x80u},\r
+ {0x36u, 0x11u},\r
+ {0x38u, 0x23u},\r
+ {0x39u, 0x42u},\r
+ {0x3Cu, 0x09u},\r
+ {0x58u, 0x01u},\r
+ {0x59u, 0x50u},\r
+ {0x5Au, 0x08u},\r
+ {0x5Du, 0x80u},\r
{0x60u, 0x02u},\r
- {0x62u, 0x80u},\r
- {0x63u, 0x04u},\r
- {0x69u, 0x40u},\r
- {0x7Au, 0x40u},\r
- {0x7Bu, 0x80u},\r
- {0x85u, 0x10u},\r
- {0x88u, 0x05u},\r
- {0x8Bu, 0x40u},\r
- {0x91u, 0x02u},\r
- {0x92u, 0x02u},\r
- {0x94u, 0x80u},\r
- {0x96u, 0x0Cu},\r
- {0x97u, 0x40u},\r
- {0x98u, 0x88u},\r
- {0x9Au, 0x22u},\r
- {0x9Bu, 0x2Cu},\r
- {0x9Cu, 0x06u},\r
- {0x9Du, 0x01u},\r
- {0x9Eu, 0x10u},\r
- {0xA0u, 0x20u},\r
- {0xA1u, 0x20u},\r
- {0xA2u, 0x41u},\r
- {0xA4u, 0x80u},\r
- {0xA6u, 0x80u},\r
- {0xA7u, 0x02u},\r
- {0xAAu, 0x40u},\r
+ {0x6Cu, 0x80u},\r
+ {0x6Du, 0x40u},\r
+ {0x6Fu, 0x15u},\r
+ {0x74u, 0x76u},\r
+ {0x76u, 0x01u},\r
+ {0x84u, 0x10u},\r
+ {0x85u, 0x01u},\r
+ {0x86u, 0x10u},\r
+ {0x89u, 0x01u},\r
+ {0x8Au, 0x40u},\r
+ {0x8Cu, 0x10u},\r
+ {0x90u, 0x02u},\r
+ {0x91u, 0x8Cu},\r
+ {0x94u, 0x20u},\r
+ {0x95u, 0x01u},\r
+ {0x96u, 0x05u},\r
+ {0x98u, 0x05u},\r
+ {0x99u, 0x50u},\r
+ {0x9Au, 0x02u},\r
+ {0x9Bu, 0x08u},\r
+ {0x9Eu, 0x40u},\r
+ {0x9Fu, 0x15u},\r
+ {0xA2u, 0x01u},\r
+ {0xA3u, 0x04u},\r
+ {0xA4u, 0x84u},\r
+ {0xA5u, 0x02u},\r
+ {0xA7u, 0x50u},\r
+ {0xA9u, 0x10u},\r
{0xACu, 0x80u},\r
- {0xAEu, 0x20u},\r
- {0xB6u, 0x40u},\r
- {0xC0u, 0xEFu},\r
- {0xC2u, 0xDEu},\r
- {0xC4u, 0xCFu},\r
- {0xCAu, 0x83u},\r
- {0xCCu, 0x79u},\r
- {0xCEu, 0xEEu},\r
- {0xD6u, 0x1Cu},\r
- {0xD8u, 0x0Cu},\r
- {0xE0u, 0x20u},\r
- {0xE2u, 0x01u},\r
- {0xE4u, 0xE0u},\r
- {0xEAu, 0x17u},\r
- {0xEEu, 0x42u},\r
- {0x00u, 0x08u},\r
- {0x01u, 0x33u},\r
- {0x02u, 0x16u},\r
- {0x03u, 0xCCu},\r
- {0x05u, 0xFFu},\r
- {0x06u, 0x40u},\r
- {0x09u, 0x0Fu},\r
- {0x0Au, 0x04u},\r
- {0x0Bu, 0xF0u},\r
- {0x0Eu, 0x07u},\r
- {0x0Fu, 0xFFu},\r
- {0x10u, 0x07u},\r
- {0x12u, 0x18u},\r
- {0x15u, 0x96u},\r
- {0x16u, 0x07u},\r
- {0x17u, 0x69u},\r
- {0x18u, 0x0Cu},\r
- {0x1Au, 0x13u},\r
- {0x1Bu, 0xFFu},\r
- {0x1Cu, 0x20u},\r
- {0x1Eu, 0x40u},\r
- {0x20u, 0x01u},\r
- {0x25u, 0x55u},\r
- {0x26u, 0x20u},\r
- {0x27u, 0xAAu},\r
- {0x28u, 0x0Fu},\r
- {0x2Au, 0x10u},\r
- {0x2Bu, 0xFFu},\r
- {0x2Cu, 0x01u},\r
- {0x2Du, 0xFFu},\r
- {0x2Eu, 0x02u},\r
- {0x30u, 0x1Fu},\r
- {0x34u, 0x60u},\r
- {0x35u, 0xFFu},\r
- {0x3Au, 0x02u},\r
+ {0xAEu, 0x80u},\r
+ {0xAFu, 0x04u},\r
+ {0xB1u, 0x08u},\r
+ {0xC0u, 0x5Du},\r
+ {0xC2u, 0xF0u},\r
+ {0xC4u, 0x30u},\r
+ {0xCAu, 0x5Fu},\r
+ {0xCCu, 0xB7u},\r
+ {0xCEu, 0xCDu},\r
+ {0xD6u, 0x1Fu},\r
+ {0xD8u, 0x08u},\r
+ {0xE2u, 0x90u},\r
+ {0xE4u, 0x80u},\r
+ {0xE6u, 0x21u},\r
+ {0xEEu, 0xA2u},\r
+ {0x00u, 0x0Fu},\r
+ {0x02u, 0xF0u},\r
+ {0x04u, 0x30u},\r
+ {0x05u, 0x0Fu},\r
+ {0x06u, 0xC0u},\r
+ {0x07u, 0x10u},\r
+ {0x09u, 0x07u},\r
+ {0x0Au, 0xFFu},\r
+ {0x0Bu, 0x18u},\r
+ {0x0Fu, 0x07u},\r
+ {0x10u, 0x05u},\r
+ {0x12u, 0x0Au},\r
+ {0x14u, 0x06u},\r
+ {0x15u, 0x0Cu},\r
+ {0x16u, 0x09u},\r
+ {0x17u, 0x13u},\r
+ {0x1Au, 0xFFu},\r
+ {0x1Bu, 0x04u},\r
+ {0x1Cu, 0xFFu},\r
+ {0x20u, 0x60u},\r
+ {0x21u, 0x08u},\r
+ {0x22u, 0x90u},\r
+ {0x23u, 0x16u},\r
+ {0x24u, 0x50u},\r
+ {0x25u, 0x01u},\r
+ {0x26u, 0xA0u},\r
+ {0x27u, 0x02u},\r
+ {0x29u, 0x01u},\r
+ {0x2Cu, 0x03u},\r
+ {0x2Eu, 0x0Cu},\r
+ {0x2Fu, 0x07u},\r
+ {0x32u, 0xFFu},\r
+ {0x35u, 0x1Fu},\r
{0x3Bu, 0x20u},\r
- {0x3Eu, 0x10u},\r
+ {0x3Eu, 0x04u},\r
+ {0x56u, 0x08u},\r
{0x58u, 0x04u},\r
{0x59u, 0x04u},\r
{0x5Bu, 0x04u},\r
- {0x5Cu, 0x11u},\r
+ {0x5Cu, 0x10u},\r
+ {0x5Du, 0x90u},\r
{0x5Fu, 0x01u},\r
- {0x82u, 0x10u},\r
- {0x85u, 0x02u},\r
- {0x87u, 0x01u},\r
- {0x8Cu, 0x10u},\r
- {0x90u, 0x10u},\r
- {0x92u, 0x60u},\r
+ {0x80u, 0x02u},\r
+ {0x81u, 0x02u},\r
+ {0x82u, 0x01u},\r
+ {0x83u, 0x04u},\r
+ {0x84u, 0x01u},\r
+ {0x86u, 0x02u},\r
+ {0x8Au, 0x08u},\r
+ {0x8Cu, 0x02u},\r
+ {0x8Eu, 0x01u},\r
+ {0x92u, 0x04u},\r
{0x93u, 0x04u},\r
- {0x98u, 0x3Au},\r
- {0x99u, 0x01u},\r
- {0x9Au, 0x45u},\r
- {0x9Bu, 0x02u},\r
- {0x9Du, 0x02u},\r
- {0x9Eu, 0x07u},\r
+ {0x94u, 0x02u},\r
+ {0x96u, 0x01u},\r
+ {0x97u, 0x08u},\r
+ {0x98u, 0x02u},\r
+ {0x9Au, 0x01u},\r
{0x9Fu, 0x01u},\r
- {0xA1u, 0x02u},\r
- {0xA3u, 0x01u},\r
- {0xA6u, 0x08u},\r
- {0xA8u, 0x24u},\r
- {0xAAu, 0x58u},\r
- {0xACu, 0x29u},\r
- {0xADu, 0x02u},\r
- {0xAEu, 0x52u},\r
- {0xAFu, 0x01u},\r
- {0xB0u, 0x70u},\r
- {0xB3u, 0x04u},\r
- {0xB5u, 0x03u},\r
- {0xB6u, 0x0Fu},\r
- {0xBAu, 0x02u},\r
- {0xBBu, 0x20u},\r
+ {0xA7u, 0x02u},\r
+ {0xACu, 0x04u},\r
+ {0xAEu, 0x08u},\r
+ {0xB1u, 0x08u},\r
+ {0xB2u, 0x0Cu},\r
+ {0xB3u, 0x01u},\r
+ {0xB4u, 0x03u},\r
+ {0xB5u, 0x06u},\r
+ {0xBAu, 0x20u},\r
+ {0xBEu, 0x04u},\r
+ {0xBFu, 0x10u},\r
{0xD6u, 0x08u},\r
{0xD8u, 0x04u},\r
{0xD9u, 0x04u},\r
{0xDBu, 0x04u},\r
- {0xDCu, 0x91u},\r
+ {0xDCu, 0x99u},\r
{0xDDu, 0x90u},\r
{0xDFu, 0x01u},\r
- {0x00u, 0x02u},\r
- {0x03u, 0x02u},\r
- {0x04u, 0x80u},\r
- {0x05u, 0x10u},\r
- {0x06u, 0x90u},\r
- {0x0Au, 0x82u},\r
- {0x0Bu, 0x06u},\r
- {0x0Eu, 0x61u},\r
- {0x0Fu, 0x04u},\r
- {0x10u, 0x04u},\r
- {0x11u, 0x04u},\r
- {0x13u, 0x40u},\r
- {0x14u, 0x14u},\r
- {0x15u, 0x01u},\r
+ {0x00u, 0x84u},\r
+ {0x02u, 0x80u},\r
+ {0x03u, 0x04u},\r
+ {0x04u, 0x22u},\r
+ {0x07u, 0x10u},\r
+ {0x09u, 0x0Au},\r
+ {0x0Au, 0x08u},\r
+ {0x0Du, 0x02u},\r
+ {0x0Eu, 0x01u},\r
+ {0x0Fu, 0x28u},\r
+ {0x12u, 0x01u},\r
+ {0x15u, 0x40u},\r
{0x16u, 0x02u},\r
- {0x17u, 0x04u},\r
- {0x1Au, 0x82u},\r
- {0x1Eu, 0x40u},\r
- {0x1Fu, 0x10u},\r
+ {0x17u, 0x05u},\r
+ {0x18u, 0x04u},\r
+ {0x19u, 0x10u},\r
+ {0x1Au, 0x10u},\r
+ {0x1Fu, 0x04u},\r
+ {0x20u, 0x80u},\r
{0x21u, 0x28u},\r
{0x25u, 0x10u},\r
- {0x27u, 0x08u},\r
- {0x29u, 0x82u},\r
- {0x2Cu, 0x04u},\r
- {0x2Eu, 0x04u},\r
- {0x2Fu, 0x02u},\r
- {0x31u, 0x21u},\r
- {0x32u, 0x80u},\r
- {0x35u, 0x04u},\r
- {0x36u, 0x10u},\r
- {0x38u, 0x08u},\r
- {0x3Du, 0x20u},\r
- {0x3Eu, 0x80u},\r
- {0x3Fu, 0x45u},\r
- {0x59u, 0x40u},\r
- {0x63u, 0x01u},\r
- {0x6Cu, 0x02u},\r
- {0x6Eu, 0x80u},\r
- {0x81u, 0x04u},\r
- {0x84u, 0x20u},\r
+ {0x2Bu, 0x10u},\r
+ {0x2Cu, 0x01u},\r
+ {0x2Du, 0xA9u},\r
+ {0x32u, 0x84u},\r
+ {0x33u, 0x01u},\r
+ {0x34u, 0x20u},\r
+ {0x37u, 0x08u},\r
+ {0x38u, 0x02u},\r
+ {0x3Au, 0x01u},\r
+ {0x3Du, 0x24u},\r
+ {0x3Fu, 0x80u},\r
+ {0x58u, 0x80u},\r
+ {0x5Eu, 0x40u},\r
+ {0x62u, 0x80u},\r
+ {0x66u, 0x80u},\r
+ {0x82u, 0x50u},\r
+ {0x85u, 0x24u},\r
{0x86u, 0x04u},\r
- {0x87u, 0x04u},\r
- {0x88u, 0x0Au},\r
- {0x89u, 0x41u},\r
- {0x8Au, 0x01u},\r
- {0x8Fu, 0x20u},\r
- {0x90u, 0x08u},\r
- {0x91u, 0x05u},\r
- {0x94u, 0x80u},\r
- {0x97u, 0x62u},\r
- {0x98u, 0x18u},\r
- {0x99u, 0x92u},\r
- {0x9Au, 0x02u},\r
- {0x9Cu, 0x06u},\r
- {0x9Du, 0x01u},\r
- {0xA0u, 0x01u},\r
- {0xA2u, 0x11u},\r
- {0xA4u, 0xAAu},\r
- {0xA5u, 0x08u},\r
- {0xA9u, 0x10u},\r
- {0xABu, 0x50u},\r
- {0xADu, 0x11u},\r
- {0xAEu, 0x01u},\r
- {0xB2u, 0x08u},\r
- {0xB3u, 0x08u},\r
- {0xB5u, 0x40u},\r
+ {0x8Au, 0x42u},\r
+ {0x8Du, 0x08u},\r
+ {0x8Eu, 0x20u},\r
+ {0x8Fu, 0x0Cu},\r
+ {0x90u, 0x02u},\r
+ {0x91u, 0x88u},\r
+ {0x95u, 0x44u},\r
+ {0x96u, 0x04u},\r
+ {0x98u, 0x24u},\r
+ {0x99u, 0xE0u},\r
+ {0x9Eu, 0xE0u},\r
+ {0x9Fu, 0x10u},\r
+ {0xA2u, 0x01u},\r
+ {0xA4u, 0x84u},\r
+ {0xA6u, 0x40u},\r
+ {0xA9u, 0x01u},\r
+ {0xADu, 0x40u},\r
+ {0xAFu, 0x03u},\r
+ {0xB1u, 0x84u},\r
+ {0xB3u, 0x20u},\r
+ {0xB4u, 0x30u},\r
{0xB6u, 0x40u},\r
- {0xC0u, 0xF9u},\r
- {0xC2u, 0xFBu},\r
- {0xC4u, 0xF7u},\r
- {0xCAu, 0x79u},\r
- {0xCCu, 0x6Du},\r
- {0xCEu, 0xF2u},\r
- {0xD6u, 0x08u},\r
- {0xD8u, 0x08u},\r
- {0xE0u, 0x20u},\r
- {0xE2u, 0x01u},\r
- {0xE4u, 0x28u},\r
- {0xE6u, 0x82u},\r
- {0xE8u, 0x60u},\r
+ {0xC0u, 0x7Fu},\r
+ {0xC2u, 0xFEu},\r
+ {0xC4u, 0xB1u},\r
+ {0xCAu, 0xF2u},\r
+ {0xCCu, 0x6Bu},\r
+ {0xCEu, 0x71u},\r
+ {0xD6u, 0x18u},\r
+ {0xD8u, 0x18u},\r
+ {0xE0u, 0xC9u},\r
+ {0xE2u, 0x06u},\r
+ {0xE4u, 0x40u},\r
+ {0xE6u, 0x81u},\r
+ {0xE8u, 0x40u},\r
{0xECu, 0x80u},\r
- {0xEEu, 0x01u},\r
- {0x02u, 0x02u},\r
- {0x03u, 0x04u},\r
- {0x09u, 0x02u},\r
- {0x0Bu, 0x01u},\r
- {0x0Du, 0x01u},\r
- {0x0Fu, 0x02u},\r
- {0x11u, 0x04u},\r
- {0x12u, 0x01u},\r
- {0x13u, 0x08u},\r
- {0x15u, 0x02u},\r
- {0x16u, 0x04u},\r
- {0x17u, 0x01u},\r
- {0x1Au, 0x08u},\r
+ {0x00u, 0x04u},\r
+ {0x01u, 0x04u},\r
+ {0x02u, 0x08u},\r
+ {0x03u, 0x08u},\r
+ {0x06u, 0x02u},\r
+ {0x08u, 0x08u},\r
+ {0x0Au, 0x04u},\r
+ {0x0Cu, 0x08u},\r
+ {0x0Eu, 0x04u},\r
+ {0x0Fu, 0x01u},\r
+ {0x10u, 0x01u},\r
+ {0x12u, 0x02u},\r
+ {0x17u, 0x02u},\r
+ {0x18u, 0x08u},\r
+ {0x1Au, 0x04u},\r
+ {0x1Bu, 0x10u},\r
{0x1Fu, 0x08u},\r
- {0x21u, 0x02u},\r
- {0x23u, 0x01u},\r
- {0x29u, 0x02u},\r
- {0x2Bu, 0x01u},\r
- {0x30u, 0x08u},\r
- {0x31u, 0x03u},\r
- {0x32u, 0x04u},\r
- {0x34u, 0x01u},\r
- {0x36u, 0x02u},\r
+ {0x24u, 0x08u},\r
+ {0x26u, 0x04u},\r
+ {0x2Bu, 0x04u},\r
+ {0x2Eu, 0x01u},\r
+ {0x31u, 0x02u},\r
+ {0x32u, 0x03u},\r
+ {0x33u, 0x10u},\r
+ {0x35u, 0x01u},\r
+ {0x36u, 0x0Cu},\r
{0x37u, 0x0Cu},\r
- {0x3Bu, 0x02u},\r
+ {0x3Au, 0x80u},\r
+ {0x3Eu, 0x04u},\r
{0x3Fu, 0x40u},\r
{0x56u, 0x08u},\r
{0x58u, 0x04u},\r
{0x5Cu, 0x99u},\r
{0x5Du, 0x90u},\r
{0x5Fu, 0x01u},\r
- {0x84u, 0x55u},\r
- {0x86u, 0xAAu},\r
- {0x88u, 0x33u},\r
- {0x8Au, 0xCCu},\r
- {0x8Bu, 0x08u},\r
- {0x8Cu, 0xFFu},\r
- {0x8Du, 0x19u},\r
- {0x8Fu, 0x02u},\r
- {0x92u, 0xFFu},\r
- {0x93u, 0x10u},\r
- {0x94u, 0x69u},\r
- {0x96u, 0x96u},\r
- {0x97u, 0x10u},\r
- {0x98u, 0xFFu},\r
- {0x9Bu, 0x07u},\r
- {0x9Cu, 0x0Fu},\r
- {0x9Eu, 0xF0u},\r
- {0xA5u, 0x1Au},\r
- {0xA6u, 0xFFu},\r
- {0xA7u, 0x05u},\r
- {0xA9u, 0x14u},\r
- {0xAAu, 0xFFu},\r
- {0xABu, 0x08u},\r
- {0xB1u, 0x10u},\r
- {0xB3u, 0x0Fu},\r
- {0xB6u, 0xFFu},\r
- {0xBAu, 0x80u},\r
- {0xBFu, 0x01u},\r
+ {0x80u, 0x10u},\r
+ {0x83u, 0x10u},\r
+ {0x84u, 0x0Au},\r
+ {0x86u, 0x05u},\r
+ {0x87u, 0x02u},\r
+ {0x8Bu, 0x04u},\r
+ {0x8Fu, 0x08u},\r
+ {0x93u, 0x01u},\r
+ {0x96u, 0x07u},\r
+ {0x9Au, 0x08u},\r
+ {0xA0u, 0x09u},\r
+ {0xA2u, 0x02u},\r
+ {0xA4u, 0x04u},\r
+ {0xA6u, 0x08u},\r
+ {0xADu, 0x01u},\r
+ {0xAFu, 0x02u},\r
+ {0xB0u, 0x10u},\r
+ {0xB1u, 0x04u},\r
+ {0xB2u, 0x0Fu},\r
+ {0xB3u, 0x10u},\r
+ {0xB5u, 0x03u},\r
+ {0xB7u, 0x08u},\r
+ {0xBEu, 0x01u},\r
+ {0xBFu, 0x10u},\r
+ {0xD6u, 0x08u},\r
{0xD8u, 0x04u},\r
{0xD9u, 0x04u},\r
{0xDBu, 0x04u},\r
- {0xDCu, 0x11u},\r
+ {0xDCu, 0x91u},\r
+ {0xDDu, 0x90u},\r
{0xDFu, 0x01u},\r
- {0x01u, 0x02u},\r
- {0x04u, 0x80u},\r
- {0x06u, 0x08u},\r
- {0x07u, 0x11u},\r
- {0x08u, 0x02u},\r
- {0x09u, 0x08u},\r
- {0x0Au, 0x04u},\r
- {0x0Cu, 0x28u},\r
- {0x0Eu, 0x02u},\r
- {0x0Fu, 0x40u},\r
- {0x14u, 0x24u},\r
- {0x18u, 0x08u},\r
- {0x19u, 0x82u},\r
- {0x1Au, 0x04u},\r
- {0x1Bu, 0x04u},\r
- {0x1Eu, 0x02u},\r
- {0x20u, 0x40u},\r
- {0x22u, 0x41u},\r
- {0x25u, 0x01u},\r
- {0x27u, 0x20u},\r
- {0x29u, 0x01u},\r
- {0x2Bu, 0x04u},\r
- {0x2Cu, 0x24u},\r
- {0x30u, 0x82u},\r
- {0x31u, 0x08u},\r
- {0x34u, 0x10u},\r
- {0x37u, 0x29u},\r
- {0x38u, 0x40u},\r
- {0x3Au, 0x10u},\r
- {0x3Bu, 0x02u},\r
- {0x3Eu, 0x10u},\r
- {0x3Fu, 0x40u},\r
- {0x45u, 0x01u},\r
- {0x46u, 0x40u},\r
- {0x59u, 0x20u},\r
- {0x5Bu, 0x40u},\r
- {0x5Du, 0x51u},\r
- {0x5Fu, 0x08u},\r
- {0x60u, 0x08u},\r
- {0x62u, 0x90u},\r
- {0x66u, 0x40u},\r
- {0x81u, 0x20u},\r
- {0x82u, 0x02u},\r
- {0x84u, 0x21u},\r
- {0x86u, 0x10u},\r
- {0x87u, 0x10u},\r
- {0x89u, 0x04u},\r
- {0x8Eu, 0x90u},\r
- {0xC0u, 0xE8u},\r
- {0xC2u, 0xFEu},\r
- {0xC4u, 0x60u},\r
- {0xCAu, 0x65u},\r
- {0xCCu, 0xEBu},\r
- {0xCEu, 0x3Du},\r
- {0xD6u, 0xFCu},\r
- {0xD8u, 0x1Cu},\r
- {0xE0u, 0x20u},\r
- {0xE2u, 0x40u},\r
- {0xE4u, 0x10u},\r
- {0xE6u, 0x01u},\r
- {0x02u, 0x02u},\r
- {0x08u, 0x01u},\r
- {0x09u, 0x01u},\r
- {0x0Au, 0x02u},\r
- {0x1Eu, 0x01u},\r
- {0x32u, 0x03u},\r
+ {0x00u, 0xA1u},\r
+ {0x03u, 0x10u},\r
+ {0x06u, 0xA0u},\r
+ {0x09u, 0x20u},\r
+ {0x0Au, 0x40u},\r
+ {0x0Cu, 0x04u},\r
+ {0x0Eu, 0x10u},\r
+ {0x0Fu, 0x04u},\r
+ {0x11u, 0x40u},\r
+ {0x12u, 0x20u},\r
+ {0x15u, 0x04u},\r
+ {0x16u, 0x40u},\r
+ {0x18u, 0x21u},\r
+ {0x19u, 0x40u},\r
+ {0x1Eu, 0x10u},\r
+ {0x1Fu, 0x0Au},\r
+ {0x20u, 0xA0u},\r
+ {0x21u, 0x08u},\r
+ {0x22u, 0x60u},\r
+ {0x23u, 0x40u},\r
+ {0x24u, 0x50u},\r
+ {0x25u, 0x41u},\r
+ {0x27u, 0x08u},\r
+ {0x2Bu, 0x08u},\r
+ {0x2Eu, 0x40u},\r
+ {0x30u, 0x80u},\r
+ {0x31u, 0x28u},\r
{0x35u, 0x01u},\r
- {0x3Eu, 0x04u},\r
- {0x40u, 0x36u},\r
- {0x41u, 0x02u},\r
- {0x42u, 0x10u},\r
- {0x44u, 0x05u},\r
- {0x45u, 0xDEu},\r
- {0x46u, 0xF0u},\r
- {0x47u, 0xCBu},\r
- {0x48u, 0x3Bu},\r
- {0x49u, 0xFFu},\r
- {0x4Au, 0xFFu},\r
- {0x4Bu, 0xFFu},\r
- {0x4Cu, 0x22u},\r
- {0x4Eu, 0xF0u},\r
- {0x4Fu, 0x08u},\r
- {0x50u, 0x04u},\r
- {0x54u, 0x40u},\r
- {0x56u, 0x04u},\r
- {0x58u, 0x04u},\r
- {0x59u, 0x04u},\r
- {0x5Au, 0x04u},\r
- {0x5Bu, 0x04u},\r
- {0x5Cu, 0x90u},\r
- {0x5Fu, 0x01u},\r
- {0x62u, 0xC0u},\r
- {0x64u, 0x40u},\r
- {0x65u, 0x01u},\r
- {0x66u, 0x10u},\r
- {0x67u, 0x11u},\r
- {0x68u, 0xC0u},\r
- {0x69u, 0x01u},\r
- {0x6Bu, 0x11u},\r
- {0x6Cu, 0x40u},\r
- {0x6Du, 0x01u},\r
+ {0x36u, 0x01u},\r
+ {0x38u, 0x02u},\r
+ {0x3Bu, 0x40u},\r
+ {0x3Cu, 0x58u},\r
+ {0x3Fu, 0x02u},\r
+ {0x58u, 0x40u},\r
+ {0x5Bu, 0x20u},\r
+ {0x5Eu, 0x80u},\r
+ {0x61u, 0x20u},\r
+ {0x63u, 0x02u},\r
+ {0x67u, 0x02u},\r
+ {0x6Cu, 0x01u},\r
{0x6Eu, 0x40u},\r
- {0x6Fu, 0x01u},\r
- {0x80u, 0x31u},\r
- {0x81u, 0xC1u},\r
- {0x84u, 0x01u},\r
- {0x85u, 0x07u},\r
- {0x86u, 0x30u},\r
- {0x87u, 0x18u},\r
- {0x88u, 0x43u},\r
- {0x89u, 0xC0u},\r
- {0x8Au, 0x3Cu},\r
- {0x8Cu, 0x31u},\r
- {0x8Du, 0x01u},\r
- {0x8Fu, 0xC0u},\r
- {0x90u, 0x30u},\r
- {0x92u, 0x01u},\r
- {0x93u, 0x40u},\r
- {0x94u, 0x06u},\r
- {0x95u, 0x22u},\r
- {0x96u, 0xB9u},\r
- {0x97u, 0x08u},\r
- {0x98u, 0x05u},\r
- {0x99u, 0x08u},\r
- {0x9Au, 0x4Au},\r
- {0x9Bu, 0x21u},\r
- {0x9Cu, 0xC0u},\r
- {0x9Du, 0xC1u},\r
- {0xA0u, 0x20u},\r
- {0xA1u, 0x04u},\r
- {0xA4u, 0x11u},\r
- {0xA5u, 0xC1u},\r
- {0xA6u, 0x20u},\r
- {0xA9u, 0x10u},\r
- {0xACu, 0x12u},\r
- {0xADu, 0x01u},\r
+ {0x81u, 0x01u},\r
+ {0x83u, 0x08u},\r
+ {0x85u, 0x20u},\r
+ {0x86u, 0x04u},\r
+ {0x88u, 0x40u},\r
+ {0x8Bu, 0x04u},\r
+ {0x8Cu, 0x10u},\r
+ {0x8Du, 0x40u},\r
+ {0x8Fu, 0x01u},\r
+ {0xC0u, 0x3Fu},\r
+ {0xC2u, 0x6Au},\r
+ {0xC4u, 0x35u},\r
+ {0xCAu, 0x14u},\r
+ {0xCCu, 0x8Eu},\r
+ {0xCEu, 0xF9u},\r
+ {0xD6u, 0x1Cu},\r
+ {0xD8u, 0x1Cu},\r
+ {0xE2u, 0x50u},\r
+ {0xE4u, 0x30u},\r
+ {0x81u, 0x01u},\r
+ {0x82u, 0xFFu},\r
+ {0x85u, 0x04u},\r
+ {0x86u, 0x60u},\r
+ {0x88u, 0x80u},\r
+ {0x89u, 0x22u},\r
+ {0x8Bu, 0x08u},\r
+ {0x8Cu, 0x90u},\r
+ {0x8Du, 0x10u},\r
+ {0x8Eu, 0x40u},\r
+ {0x91u, 0x01u},\r
+ {0x92u, 0x9Fu},\r
+ {0x94u, 0x7Fu},\r
+ {0x95u, 0x07u},\r
+ {0x96u, 0x80u},\r
+ {0x97u, 0x18u},\r
+ {0x98u, 0xC0u},\r
+ {0x99u, 0x01u},\r
+ {0x9Au, 0x04u},\r
+ {0x9Du, 0x40u},\r
+ {0xA0u, 0xC0u},\r
+ {0xA1u, 0x01u},\r
+ {0xA2u, 0x02u},\r
+ {0xA4u, 0xC0u},\r
+ {0xA5u, 0x01u},\r
+ {0xA6u, 0x08u},\r
+ {0xA8u, 0x1Fu},\r
+ {0xA9u, 0x40u},\r
+ {0xAAu, 0x20u},\r
+ {0xACu, 0xC0u},\r
+ {0xADu, 0x08u},\r
{0xAEu, 0x01u},\r
- {0xB0u, 0x03u},\r
- {0xB1u, 0x3Fu},\r
+ {0xAFu, 0x21u},\r
+ {0xB2u, 0xFFu},\r
{0xB3u, 0x40u},\r
- {0xB4u, 0x3Cu},\r
- {0xB6u, 0xC4u},\r
- {0xB7u, 0x80u},\r
- {0xB8u, 0x80u},\r
- {0xB9u, 0x02u},\r
- {0xBAu, 0x02u},\r
- {0xBFu, 0x45u},\r
+ {0xB7u, 0x3Fu},\r
+ {0xB9u, 0x88u},\r
+ {0xBEu, 0x04u},\r
+ {0xBFu, 0x40u},\r
{0xD6u, 0x02u},\r
{0xD7u, 0x24u},\r
{0xD8u, 0x04u},\r
{0xD9u, 0x04u},\r
{0xDBu, 0x04u},\r
{0xDFu, 0x01u},\r
- {0x00u, 0x02u},\r
- {0x03u, 0x08u},\r
- {0x04u, 0x08u},\r
- {0x05u, 0x10u},\r
- {0x06u, 0x02u},\r
- {0x07u, 0x40u},\r
- {0x0Au, 0x02u},\r
- {0x0Cu, 0x02u},\r
- {0x0Du, 0x40u},\r
- {0x0Eu, 0x26u},\r
- {0x14u, 0x01u},\r
- {0x15u, 0x06u},\r
- {0x19u, 0x08u},\r
- {0x1Eu, 0x06u},\r
- {0x1Fu, 0x11u},\r
- {0x21u, 0x10u},\r
- {0x24u, 0x90u},\r
- {0x25u, 0x80u},\r
- {0x27u, 0x02u},\r
- {0x2Cu, 0x09u},\r
- {0x2Du, 0x04u},\r
- {0x2Fu, 0x41u},\r
- {0x35u, 0x02u},\r
- {0x36u, 0x14u},\r
- {0x37u, 0x40u},\r
- {0x39u, 0x10u},\r
- {0x3Du, 0xA0u},\r
- {0x3Eu, 0x06u},\r
- {0x41u, 0x88u},\r
- {0x42u, 0x04u},\r
- {0x49u, 0x86u},\r
- {0x4Au, 0x84u},\r
- {0x50u, 0x08u},\r
- {0x51u, 0x01u},\r
+ {0x01u, 0x46u},\r
+ {0x02u, 0x08u},\r
+ {0x05u, 0x02u},\r
+ {0x07u, 0x19u},\r
+ {0x09u, 0x81u},\r
+ {0x0Au, 0x04u},\r
+ {0x0Cu, 0x20u},\r
+ {0x0Eu, 0x80u},\r
+ {0x0Fu, 0x20u},\r
+ {0x10u, 0x08u},\r
+ {0x12u, 0x21u},\r
+ {0x15u, 0x01u},\r
+ {0x16u, 0x02u},\r
+ {0x17u, 0x24u},\r
+ {0x19u, 0x82u},\r
+ {0x1Au, 0x44u},\r
+ {0x1Bu, 0x11u},\r
+ {0x1Eu, 0x10u},\r
+ {0x21u, 0x04u},\r
+ {0x22u, 0x2Bu},\r
+ {0x23u, 0x3Cu},\r
+ {0x25u, 0x04u},\r
+ {0x26u, 0x80u},\r
+ {0x27u, 0x10u},\r
+ {0x2Bu, 0x91u},\r
+ {0x2Cu, 0x20u},\r
+ {0x2Eu, 0x52u},\r
+ {0x30u, 0x28u},\r
+ {0x31u, 0x80u},\r
+ {0x36u, 0xA8u},\r
+ {0x37u, 0x01u},\r
+ {0x39u, 0x40u},\r
+ {0x3Au, 0x01u},\r
+ {0x3Bu, 0x14u},\r
+ {0x3Cu, 0x80u},\r
+ {0x3Du, 0x0Au},\r
+ {0x3Eu, 0x80u},\r
+ {0x3Fu, 0x20u},\r
+ {0x41u, 0x04u},\r
+ {0x42u, 0x44u},\r
+ {0x48u, 0x40u},\r
+ {0x49u, 0x08u},\r
+ {0x4Au, 0x46u},\r
+ {0x51u, 0x80u},\r
{0x52u, 0x10u},\r
- {0x60u, 0x10u},\r
- {0x61u, 0x01u},\r
- {0x62u, 0x90u},\r
- {0x67u, 0x04u},\r
- {0x6Cu, 0x16u},\r
- {0x6Du, 0xE4u},\r
- {0x6Fu, 0x40u},\r
- {0x76u, 0x02u},\r
- {0x84u, 0x01u},\r
- {0x85u, 0x80u},\r
- {0x89u, 0x10u},\r
- {0x8Au, 0x06u},\r
- {0x8Cu, 0x04u},\r
- {0x92u, 0x02u},\r
- {0x93u, 0x84u},\r
- {0x94u, 0xACu},\r
- {0x95u, 0xE6u},\r
- {0x96u, 0x0Cu},\r
- {0x97u, 0x22u},\r
- {0x99u, 0x10u},\r
- {0x9Du, 0x0Du},\r
- {0x9Eu, 0x02u},\r
- {0x9Fu, 0x42u},\r
- {0xA1u, 0x08u},\r
- {0xA2u, 0x14u},\r
- {0xA3u, 0x08u},\r
- {0xA4u, 0x08u},\r
- {0xA5u, 0x50u},\r
- {0xA6u, 0x02u},\r
- {0xA8u, 0x02u},\r
- {0xA9u, 0x82u},\r
- {0xADu, 0x29u},\r
- {0xB0u, 0x04u},\r
- {0xB2u, 0x90u},\r
- {0xB3u, 0x08u},\r
- {0xB4u, 0x40u},\r
- {0xC0u, 0xFAu},\r
- {0xC2u, 0xF1u},\r
- {0xC4u, 0xB0u},\r
- {0xCAu, 0xF0u},\r
- {0xCCu, 0xF0u},\r
- {0xCEu, 0xF4u},\r
- {0xD0u, 0x0Eu},\r
+ {0x53u, 0x01u},\r
+ {0x67u, 0x08u},\r
+ {0x6Cu, 0x28u},\r
+ {0x6Du, 0x47u},\r
+ {0x6Fu, 0x85u},\r
+ {0x76u, 0x03u},\r
+ {0x88u, 0x10u},\r
+ {0x89u, 0x80u},\r
+ {0x8Eu, 0x04u},\r
+ {0x93u, 0x08u},\r
+ {0x96u, 0x42u},\r
+ {0x97u, 0x02u},\r
+ {0x9Cu, 0x10u},\r
+ {0x9Du, 0x88u},\r
+ {0x9Eu, 0x92u},\r
+ {0x9Fu, 0x21u},\r
+ {0xA4u, 0x28u},\r
+ {0xA5u, 0x01u},\r
+ {0xA7u, 0x11u},\r
+ {0xAAu, 0x01u},\r
+ {0xADu, 0x01u},\r
+ {0xC0u, 0xFFu},\r
+ {0xC2u, 0x7Bu},\r
+ {0xC4u, 0xF7u},\r
+ {0xCAu, 0xFBu},\r
+ {0xCCu, 0xFEu},\r
+ {0xCEu, 0xFFu},\r
+ {0xD0u, 0x07u},\r
{0xD2u, 0x0Cu},\r
- {0xD8u, 0x2Fu},\r
- {0xE6u, 0x08u},\r
- {0xEAu, 0x05u},\r
- {0x00u, 0x34u},\r
- {0x01u, 0xC0u},\r
- {0x03u, 0x01u},\r
- {0x05u, 0x1Fu},\r
- {0x06u, 0x34u},\r
- {0x07u, 0x20u},\r
- {0x08u, 0x14u},\r
- {0x09u, 0xC0u},\r
- {0x0Au, 0x20u},\r
+ {0xD8u, 0x20u},\r
+ {0xE0u, 0x40u},\r
+ {0xECu, 0x02u},\r
+ {0x01u, 0x1Du},\r
+ {0x04u, 0x04u},\r
+ {0x06u, 0x03u},\r
+ {0x09u, 0x02u},\r
{0x0Bu, 0x08u},\r
- {0x0Cu, 0x80u},\r
- {0x0Du, 0x90u},\r
- {0x0Fu, 0x40u},\r
- {0x10u, 0x20u},\r
- {0x12u, 0x02u},\r
- {0x13u, 0x60u},\r
- {0x14u, 0x4Bu},\r
- {0x15u, 0x7Fu},\r
- {0x16u, 0x30u},\r
- {0x17u, 0x80u},\r
- {0x18u, 0x3Fu},\r
- {0x1Au, 0x40u},\r
- {0x1Bu, 0xFFu},\r
- {0x1Cu, 0x14u},\r
- {0x1Du, 0xC0u},\r
- {0x1Fu, 0x02u},\r
- {0x20u, 0x34u},\r
- {0x24u, 0x08u},\r
- {0x25u, 0xC0u},\r
- {0x26u, 0x75u},\r
- {0x27u, 0x04u},\r
- {0x28u, 0x80u},\r
- {0x2Bu, 0x9Fu},\r
- {0x2Cu, 0x34u},\r
- {0x2Du, 0x80u},\r
- {0x32u, 0x78u},\r
- {0x33u, 0xFFu},\r
- {0x34u, 0x07u},\r
- {0x36u, 0x80u},\r
- {0x38u, 0x88u},\r
- {0x3Au, 0x30u},\r
- {0x3Fu, 0x04u},\r
+ {0x0Du, 0x02u},\r
+ {0x0Fu, 0x04u},\r
+ {0x11u, 0x0Du},\r
+ {0x13u, 0x10u},\r
+ {0x14u, 0x6Du},\r
+ {0x16u, 0x02u},\r
+ {0x19u, 0x01u},\r
+ {0x1Au, 0x10u},\r
+ {0x1Bu, 0x02u},\r
+ {0x1Cu, 0x0Bu},\r
+ {0x1Du, 0x02u},\r
+ {0x1Eu, 0x54u},\r
+ {0x1Fu, 0x0Du},\r
+ {0x21u, 0x1Du},\r
+ {0x25u, 0x1Du},\r
+ {0x28u, 0x09u},\r
+ {0x29u, 0x1Du},\r
+ {0x2Au, 0x36u},\r
+ {0x2Fu, 0x10u},\r
+ {0x31u, 0x0Fu},\r
+ {0x32u, 0x07u},\r
+ {0x34u, 0x70u},\r
+ {0x35u, 0x10u},\r
+ {0x36u, 0x08u},\r
+ {0x3Au, 0x08u},\r
+ {0x3Bu, 0x02u},\r
+ {0x3Eu, 0x40u},\r
+ {0x3Fu, 0x10u},\r
+ {0x54u, 0x40u},\r
+ {0x56u, 0x04u},\r
{0x58u, 0x04u},\r
{0x59u, 0x04u},\r
+ {0x5Bu, 0x04u},\r
{0x5Fu, 0x01u},\r
{0x82u, 0xFFu},\r
- {0x84u, 0x30u},\r
- {0x86u, 0xC0u},\r
+ {0x83u, 0x70u},\r
+ {0x84u, 0xFFu},\r
+ {0x85u, 0x99u},\r
+ {0x87u, 0x22u},\r
{0x88u, 0x0Fu},\r
- {0x89u, 0x11u},\r
{0x8Au, 0xF0u},\r
- {0x8Bu, 0x0Eu},\r
- {0x8Cu, 0x60u},\r
- {0x8Eu, 0x90u},\r
- {0x90u, 0x50u},\r
- {0x92u, 0xA0u},\r
- {0x94u, 0x06u},\r
- {0x95u, 0x1Bu},\r
- {0x96u, 0x09u},\r
- {0x97u, 0x04u},\r
- {0x98u, 0x05u},\r
- {0x99u, 0x04u},\r
- {0x9Au, 0x0Au},\r
- {0x9Bu, 0x03u},\r
- {0xA4u, 0x03u},\r
- {0xA6u, 0x0Cu},\r
- {0xA9u, 0x15u},\r
- {0xAAu, 0xFFu},\r
- {0xABu, 0x0Au},\r
- {0xACu, 0xFFu},\r
- {0xB1u, 0x08u},\r
- {0xB5u, 0x07u},\r
- {0xB6u, 0xFFu},\r
- {0xB7u, 0x10u},\r
- {0xBBu, 0x20u},\r
- {0xBEu, 0x40u},\r
- {0xBFu, 0x41u},\r
+ {0x8Bu, 0x80u},\r
+ {0x90u, 0xFFu},\r
+ {0x93u, 0x08u},\r
+ {0x96u, 0xFFu},\r
+ {0x97u, 0x07u},\r
+ {0x98u, 0x33u},\r
+ {0x99u, 0xAAu},\r
+ {0x9Au, 0xCCu},\r
+ {0x9Bu, 0x55u},\r
+ {0x9Eu, 0xFFu},\r
+ {0xA8u, 0x69u},\r
+ {0xA9u, 0x44u},\r
+ {0xAAu, 0x96u},\r
+ {0xABu, 0x88u},\r
+ {0xACu, 0x55u},\r
+ {0xAEu, 0xAAu},\r
+ {0xB1u, 0xF0u},\r
+ {0xB2u, 0xFFu},\r
+ {0xB3u, 0x0Fu},\r
+ {0xBAu, 0x08u},\r
{0xD4u, 0x09u},\r
{0xD6u, 0x04u},\r
{0xD8u, 0x04u},\r
{0xD9u, 0x04u},\r
{0xDBu, 0x04u},\r
+ {0xDCu, 0x11u},\r
{0xDFu, 0x01u},\r
- {0x00u, 0x44u},\r
- {0x02u, 0xC1u},\r
- {0x03u, 0x08u},\r
- {0x04u, 0xA8u},\r
- {0x07u, 0x40u},\r
- {0x08u, 0x54u},\r
- {0x09u, 0x02u},\r
- {0x0Bu, 0x02u},\r
- {0x0Cu, 0x40u},\r
- {0x0Du, 0x01u},\r
- {0x0Eu, 0x24u},\r
- {0x10u, 0x22u},\r
- {0x11u, 0x10u},\r
- {0x15u, 0x41u},\r
- {0x17u, 0x28u},\r
- {0x1Au, 0x01u},\r
- {0x1Cu, 0x20u},\r
- {0x1Du, 0x18u},\r
- {0x1Eu, 0x2Au},\r
- {0x1Fu, 0x40u},\r
- {0x22u, 0x10u},\r
- {0x23u, 0x85u},\r
- {0x27u, 0x20u},\r
- {0x29u, 0x10u},\r
- {0x2Cu, 0x08u},\r
- {0x2Du, 0x04u},\r
+ {0x01u, 0x01u},\r
+ {0x03u, 0x18u},\r
+ {0x05u, 0x04u},\r
+ {0x08u, 0x04u},\r
+ {0x0Au, 0x81u},\r
+ {0x0Bu, 0x24u},\r
+ {0x0Eu, 0x08u},\r
+ {0x0Fu, 0x22u},\r
+ {0x12u, 0x08u},\r
+ {0x13u, 0x40u},\r
+ {0x17u, 0x20u},\r
+ {0x18u, 0x20u},\r
+ {0x1Bu, 0x08u},\r
+ {0x1Du, 0x84u},\r
+ {0x1Eu, 0x08u},\r
+ {0x1Fu, 0x04u},\r
+ {0x21u, 0x09u},\r
+ {0x25u, 0x20u},\r
+ {0x27u, 0x80u},\r
+ {0x28u, 0x04u},\r
+ {0x2Cu, 0x28u},\r
+ {0x2Eu, 0x02u},\r
{0x2Fu, 0x01u},\r
+ {0x30u, 0x02u},\r
{0x31u, 0x08u},\r
- {0x32u, 0x10u},\r
- {0x36u, 0x15u},\r
- {0x37u, 0x58u},\r
- {0x3Bu, 0x20u},\r
- {0x3Du, 0xA1u},\r
- {0x3Eu, 0x06u},\r
- {0x59u, 0x24u},\r
- {0x5Bu, 0x82u},\r
- {0x63u, 0x41u},\r
- {0x81u, 0x01u},\r
- {0x87u, 0x40u},\r
- {0x91u, 0x10u},\r
- {0x92u, 0x02u},\r
- {0x94u, 0x2Cu},\r
- {0x95u, 0xE1u},\r
- {0x96u, 0x0Du},\r
- {0x98u, 0x10u},\r
- {0x9Cu, 0x04u},\r
- {0x9Du, 0x80u},\r
- {0x9Eu, 0x51u},\r
- {0x9Fu, 0x58u},\r
- {0xA0u, 0x20u},\r
- {0xA4u, 0x18u},\r
- {0xA5u, 0x02u},\r
- {0xA6u, 0x02u},\r
- {0xA7u, 0x08u},\r
- {0xA8u, 0x80u},\r
- {0xA9u, 0x10u},\r
- {0xAAu, 0x30u},\r
- {0xC0u, 0xFFu},\r
- {0xC2u, 0xFEu},\r
- {0xC4u, 0xF7u},\r
- {0xCAu, 0x74u},\r
- {0xCCu, 0xF6u},\r
- {0xCEu, 0xF4u},\r
- {0xD6u, 0x0Fu},\r
- {0xD8u, 0x09u},\r
- {0xEAu, 0x07u},\r
- {0xECu, 0x01u},\r
- {0xEEu, 0x10u},\r
- {0x38u, 0x02u},\r
- {0x39u, 0x01u},\r
- {0x91u, 0x22u},\r
- {0x94u, 0x04u},\r
- {0x95u, 0x01u},\r
- {0x98u, 0x08u},\r
- {0x9Au, 0x22u},\r
+ {0x33u, 0x10u},\r
+ {0x37u, 0xA1u},\r
+ {0x39u, 0x1Au},\r
+ {0x3Du, 0x02u},\r
+ {0x3Eu, 0x40u},\r
+ {0x3Fu, 0x20u},\r
+ {0x45u, 0x20u},\r
+ {0x46u, 0x08u},\r
+ {0x58u, 0x10u},\r
+ {0x59u, 0x88u},\r
+ {0x5Au, 0x02u},\r
+ {0x60u, 0x80u},\r
+ {0x61u, 0x80u},\r
+ {0x66u, 0x19u},\r
+ {0x67u, 0x02u},\r
+ {0x82u, 0x04u},\r
+ {0x85u, 0x08u},\r
+ {0x8Cu, 0x80u},\r
+ {0x91u, 0x19u},\r
+ {0x92u, 0x81u},\r
+ {0x93u, 0x64u},\r
+ {0x94u, 0x20u},\r
{0x9Bu, 0x10u},\r
- {0x9Du, 0x0Bu},\r
- {0x9Eu, 0x14u},\r
- {0x9Fu, 0x08u},\r
- {0xA2u, 0x52u},\r
- {0xA4u, 0x80u},\r
- {0xA8u, 0x04u},\r
+ {0x9Eu, 0x80u},\r
+ {0x9Fu, 0x20u},\r
+ {0xA0u, 0x02u},\r
+ {0xA2u, 0x08u},\r
+ {0xA7u, 0x11u},\r
+ {0xA8u, 0x40u},\r
{0xAAu, 0x04u},\r
- {0xABu, 0x09u},\r
- {0xEAu, 0x02u},\r
- {0xEEu, 0x10u},\r
- {0x06u, 0x02u},\r
- {0x0Du, 0x02u},\r
- {0x0Eu, 0x08u},\r
- {0x0Fu, 0x01u},\r
- {0x10u, 0x01u},\r
- {0x12u, 0x02u},\r
- {0x15u, 0x02u},\r
- {0x16u, 0x04u},\r
- {0x17u, 0x09u},\r
- {0x19u, 0x02u},\r
- {0x1Au, 0x01u},\r
- {0x1Bu, 0x05u},\r
- {0x1Du, 0x01u},\r
- {0x1Fu, 0x02u},\r
- {0x2Du, 0x02u},\r
- {0x2Fu, 0x11u},\r
- {0x30u, 0x04u},\r
- {0x31u, 0x04u},\r
- {0x32u, 0x08u},\r
- {0x33u, 0x10u},\r
- {0x34u, 0x03u},\r
- {0x35u, 0x08u},\r
- {0x37u, 0x03u},\r
- {0x3Bu, 0x80u},\r
- {0x3Eu, 0x10u},\r
- {0x56u, 0x08u},\r
- {0x58u, 0x04u},\r
+ {0xABu, 0x40u},\r
+ {0xB1u, 0x04u},\r
+ {0xB2u, 0x01u},\r
+ {0xB5u, 0x10u},\r
+ {0xC0u, 0x2Eu},\r
+ {0xC2u, 0xEFu},\r
+ {0xC4u, 0x43u},\r
+ {0xCAu, 0xF4u},\r
+ {0xCCu, 0xB7u},\r
+ {0xCEu, 0xB7u},\r
+ {0xD6u, 0x0Fu},\r
+ {0xD8u, 0xF9u},\r
+ {0xE0u, 0x02u},\r
+ {0xE2u, 0x18u},\r
+ {0xEEu, 0x31u},\r
+ {0x39u, 0x20u},\r
+ {0x3Fu, 0x10u},\r
{0x59u, 0x04u},\r
- {0x5Bu, 0x04u},\r
- {0x5Cu, 0x99u},\r
- {0x5Du, 0x90u},\r
{0x5Fu, 0x01u},\r
- {0x80u, 0x90u},\r
- {0x82u, 0x60u},\r
- {0x83u, 0xFFu},\r
- {0x84u, 0x09u},\r
- {0x86u, 0x06u},\r
- {0x87u, 0xFFu},\r
- {0x88u, 0x30u},\r
- {0x89u, 0xFFu},\r
- {0x8Au, 0xC0u},\r
- {0x8Du, 0x60u},\r
- {0x8Eu, 0xFFu},\r
- {0x8Fu, 0x90u},\r
- {0x90u, 0x0Fu},\r
- {0x92u, 0xF0u},\r
- {0x95u, 0x50u},\r
- {0x96u, 0xFFu},\r
- {0x97u, 0xA0u},\r
- {0x98u, 0x03u},\r
- {0x99u, 0x03u},\r
- {0x9Au, 0x0Cu},\r
- {0x9Bu, 0x0Cu},\r
- {0x9Du, 0x0Fu},\r
- {0x9Fu, 0xF0u},\r
- {0xA0u, 0x05u},\r
- {0xA1u, 0x05u},\r
- {0xA2u, 0x0Au},\r
- {0xA3u, 0x0Au},\r
- {0xA4u, 0x50u},\r
- {0xA5u, 0x30u},\r
- {0xA6u, 0xA0u},\r
- {0xA7u, 0xC0u},\r
- {0xA9u, 0x06u},\r
- {0xAAu, 0xFFu},\r
- {0xABu, 0x09u},\r
- {0xB4u, 0xFFu},\r
- {0xB5u, 0xFFu},\r
- {0xBEu, 0x10u},\r
- {0xBFu, 0x10u},\r
- {0xD8u, 0x04u},\r
- {0xD9u, 0x04u},\r
- {0xDBu, 0x04u},\r
- {0xDFu, 0x01u},\r
- {0x02u, 0x02u},\r
- {0x03u, 0x20u},\r
- {0x04u, 0x22u},\r
- {0x06u, 0x22u},\r
- {0x08u, 0x18u},\r
- {0x0Au, 0x40u},\r
- {0x0Cu, 0x10u},\r
- {0x0Du, 0x10u},\r
- {0x0Eu, 0xE0u},\r
- {0x0Fu, 0x10u},\r
- {0x14u, 0x40u},\r
- {0x15u, 0x02u},\r
- {0x16u, 0x08u},\r
- {0x17u, 0x14u},\r
- {0x18u, 0x04u},\r
- {0x19u, 0x09u},\r
- {0x1Eu, 0x04u},\r
- {0x20u, 0x02u},\r
- {0x21u, 0xA8u},\r
- {0x23u, 0x40u},\r
{0x27u, 0x08u},\r
- {0x28u, 0x02u},\r
- {0x2Cu, 0x40u},\r
- {0x2Eu, 0x20u},\r
- {0x2Fu, 0x20u},\r
- {0x31u, 0xA8u},\r
- {0x34u, 0x10u},\r
- {0x36u, 0x40u},\r
- {0x37u, 0x04u},\r
- {0x3Bu, 0x40u},\r
- {0x3Du, 0x80u},\r
- {0x3Eu, 0x0Au},\r
- {0x3Fu, 0x10u},\r
- {0x59u, 0x80u},\r
- {0x60u, 0x02u},\r
- {0x6Cu, 0x91u},\r
- {0x6Du, 0x80u},\r
- {0x6Fu, 0x24u},\r
- {0x74u, 0x40u},\r
- {0x75u, 0x02u},\r
- {0x76u, 0x14u},\r
- {0x85u, 0x02u},\r
- {0x88u, 0x41u},\r
- {0x89u, 0x80u},\r
- {0x8Cu, 0x10u},\r
- {0x91u, 0x22u},\r
- {0x94u, 0x06u},\r
- {0x96u, 0x04u},\r
- {0x98u, 0x08u},\r
- {0x9Au, 0x22u},\r
- {0x9Bu, 0x10u},\r
- {0x9Du, 0x0Bu},\r
- {0x9Eu, 0x14u},\r
- {0x9Fu, 0x0Cu},\r
- {0xA2u, 0x52u},\r
- {0xA4u, 0x80u},\r
- {0xABu, 0x14u},\r
- {0xB2u, 0x74u},\r
- {0xB4u, 0x01u},\r
- {0xC0u, 0xF5u},\r
- {0xC2u, 0x7Eu},\r
- {0xC4u, 0x70u},\r
- {0xCAu, 0xE8u},\r
- {0xCCu, 0x7Eu},\r
- {0xCEu, 0xF8u},\r
- {0xD6u, 0x08u},\r
- {0xD8u, 0x08u},\r
- {0xE2u, 0x80u},\r
- {0xE6u, 0x60u},\r
- {0xEAu, 0xE0u},\r
- {0xEEu, 0xA0u},\r
+ {0x84u, 0x08u},\r
+ {0x87u, 0x08u},\r
+ {0x97u, 0x40u},\r
+ {0x9Cu, 0x80u},\r
+ {0xA4u, 0x08u},\r
+ {0xB3u, 0x04u},\r
+ {0xEEu, 0x21u},\r
+ {0x88u, 0x80u},\r
+ {0x9Cu, 0x80u},\r
+ {0xAFu, 0x40u},\r
{0x12u, 0x08u},\r
{0x16u, 0x80u},\r
{0x17u, 0x80u},\r
- {0x30u, 0x02u},\r
- {0x36u, 0x22u},\r
- {0x39u, 0x08u},\r
+ {0x31u, 0x08u},\r
+ {0x36u, 0x20u},\r
+ {0x37u, 0x04u},\r
+ {0x39u, 0x01u},\r
{0x3Au, 0x80u},\r
- {0x3Du, 0x08u},\r
- {0x3Fu, 0x10u},\r
- {0x42u, 0x08u},\r
- {0x53u, 0x08u},\r
- {0x5Au, 0x08u},\r
- {0x5Eu, 0x08u},\r
- {0x60u, 0x08u},\r
- {0x67u, 0x20u},\r
- {0x82u, 0x10u},\r
- {0x83u, 0x10u},\r
- {0x87u, 0x50u},\r
+ {0x3Cu, 0x04u},\r
+ {0x3Fu, 0x20u},\r
+ {0x43u, 0x40u},\r
+ {0x55u, 0x10u},\r
+ {0x59u, 0x04u},\r
+ {0x5Eu, 0x04u},\r
+ {0x61u, 0x10u},\r
+ {0x66u, 0x01u},\r
+ {0x82u, 0x01u},\r
+ {0x86u, 0x04u},\r
+ {0x89u, 0x01u},\r
{0xC4u, 0xE0u},\r
{0xCCu, 0xE0u},\r
{0xCEu, 0xF0u},\r
{0xD0u, 0x10u},\r
- {0xD4u, 0x20u},\r
+ {0xD4u, 0x40u},\r
{0xD6u, 0xC0u},\r
{0xD8u, 0xC0u},\r
- {0xE2u, 0x10u},\r
- {0xE6u, 0xE0u},\r
- {0x33u, 0x11u},\r
- {0x37u, 0x88u},\r
- {0x3Au, 0x40u},\r
- {0x50u, 0x80u},\r
- {0x57u, 0x10u},\r
- {0x5Au, 0x20u},\r
- {0x67u, 0x80u},\r
- {0x84u, 0x08u},\r
- {0x92u, 0x20u},\r
- {0x93u, 0x80u},\r
- {0x96u, 0x08u},\r
+ {0xE2u, 0x60u},\r
+ {0x32u, 0x08u},\r
+ {0x33u, 0x10u},\r
+ {0x35u, 0x01u},\r
+ {0x37u, 0x80u},\r
+ {0x3Bu, 0x10u},\r
+ {0x50u, 0x40u},\r
+ {0x57u, 0x80u},\r
+ {0x5Bu, 0x20u},\r
+ {0x5Eu, 0x01u},\r
+ {0x81u, 0x10u},\r
+ {0x8Cu, 0x40u},\r
+ {0x8Fu, 0x80u},\r
+ {0x94u, 0x04u},\r
{0x9Bu, 0x90u},\r
- {0x9Cu, 0x08u},\r
- {0x9Eu, 0x08u},\r
- {0xA3u, 0x10u},\r
- {0xA4u, 0x02u},\r
- {0xA5u, 0x04u},\r
- {0xA6u, 0x26u},\r
- {0xA7u, 0x08u},\r
+ {0x9Du, 0x14u},\r
+ {0x9Fu, 0x44u},\r
+ {0xA5u, 0x18u},\r
+ {0xA6u, 0x20u},\r
{0xAAu, 0x08u},\r
{0xABu, 0x10u},\r
- {0xAFu, 0x10u},\r
- {0xB1u, 0x04u},\r
+ {0xB7u, 0x10u},\r
{0xCCu, 0xF0u},\r
{0xCEu, 0x10u},\r
{0xD4u, 0xE0u},\r
- {0xD8u, 0x80u},\r
- {0xE6u, 0x10u},\r
- {0xEAu, 0x10u},\r
+ {0xD6u, 0x80u},\r
+ {0xE6u, 0x20u},\r
{0x12u, 0x20u},\r
{0x30u, 0x20u},\r
- {0x80u, 0x02u},\r
- {0x8Eu, 0x04u},\r
- {0x96u, 0x08u},\r
- {0x9Eu, 0x48u},\r
- {0x9Fu, 0x01u},\r
- {0xA4u, 0x02u},\r
- {0xA5u, 0x04u},\r
- {0xA6u, 0x26u},\r
- {0xA7u, 0x08u},\r
- {0xABu, 0x08u},\r
- {0xB4u, 0x80u},\r
+ {0x81u, 0x10u},\r
+ {0x88u, 0x20u},\r
+ {0x8Du, 0x04u},\r
+ {0x94u, 0x04u},\r
+ {0x97u, 0x10u},\r
+ {0x9Du, 0x05u},\r
+ {0x9Fu, 0x44u},\r
+ {0xA5u, 0x18u},\r
+ {0xA6u, 0x28u},\r
+ {0xABu, 0x20u},\r
+ {0xAEu, 0x01u},\r
{0xC4u, 0x10u},\r
{0xCCu, 0x10u},\r
- {0xE2u, 0x20u},\r
+ {0xE2u, 0x80u},\r
+ {0xEAu, 0x90u},\r
+ {0x81u, 0x01u},\r
+ {0x83u, 0x04u},\r
+ {0x87u, 0x10u},\r
+ {0x94u, 0x04u},\r
+ {0x97u, 0x10u},\r
+ {0x9Du, 0x01u},\r
+ {0x9Fu, 0x44u},\r
+ {0xA5u, 0x08u},\r
+ {0xAAu, 0x08u},\r
+ {0xE2u, 0xB0u},\r
{0xEAu, 0x20u},\r
- {0x60u, 0x20u},\r
- {0x86u, 0x42u},\r
- {0x8Cu, 0x20u},\r
- {0x8Du, 0x20u},\r
- {0x96u, 0x08u},\r
- {0x9Eu, 0x48u},\r
- {0x9Fu, 0x01u},\r
- {0xA4u, 0x20u},\r
- {0xA5u, 0x04u},\r
- {0xA6u, 0x02u},\r
- {0xABu, 0x08u},\r
- {0xD8u, 0x40u},\r
- {0xE2u, 0x50u},\r
- {0xEEu, 0x80u},\r
- {0x08u, 0x82u},\r
- {0x0Fu, 0x40u},\r
- {0x13u, 0x02u},\r
- {0x17u, 0x04u},\r
- {0x53u, 0x80u},\r
- {0x56u, 0x01u},\r
- {0x57u, 0x40u},\r
+ {0x08u, 0x20u},\r
+ {0x0Bu, 0x40u},\r
+ {0x0Eu, 0x20u},\r
+ {0x11u, 0x02u},\r
+ {0x16u, 0x10u},\r
+ {0x50u, 0x08u},\r
+ {0x54u, 0x80u},\r
{0x5Bu, 0x40u},\r
- {0x80u, 0x02u},\r
+ {0x5Du, 0x80u},\r
+ {0x88u, 0x20u},\r
{0xC2u, 0x0Eu},\r
{0xC4u, 0x0Cu},\r
{0xD4u, 0x07u},\r
{0xD6u, 0x04u},\r
- {0x02u, 0x02u},\r
- {0x03u, 0x20u},\r
- {0x04u, 0x80u},\r
- {0x07u, 0x80u},\r
- {0x09u, 0x10u},\r
- {0x0Bu, 0x20u},\r
- {0x0Cu, 0x20u},\r
- {0x0Fu, 0x20u},\r
- {0x80u, 0x40u},\r
- {0x87u, 0x90u},\r
- {0x8Bu, 0x20u},\r
- {0x8Fu, 0x04u},\r
+ {0xE2u, 0x01u},\r
+ {0x02u, 0x08u},\r
+ {0x03u, 0x40u},\r
+ {0x07u, 0x28u},\r
+ {0x08u, 0x02u},\r
+ {0x09u, 0x80u},\r
+ {0x0Cu, 0x02u},\r
+ {0x0Eu, 0x01u},\r
+ {0x80u, 0x0Au},\r
+ {0x81u, 0x01u},\r
+ {0x85u, 0x80u},\r
+ {0x87u, 0x20u},\r
+ {0x88u, 0x02u},\r
+ {0x8Au, 0x08u},\r
{0x93u, 0x40u},\r
- {0x9Bu, 0x06u},\r
- {0x9Eu, 0x01u},\r
- {0xA7u, 0xC0u},\r
- {0xA8u, 0x80u},\r
+ {0x9Du, 0x80u},\r
+ {0xA1u, 0x01u},\r
+ {0xA2u, 0x10u},\r
+ {0xA4u, 0x08u},\r
+ {0xB2u, 0x10u},\r
+ {0xB4u, 0x80u},\r
{0xB7u, 0x40u},\r
{0xC0u, 0x0Fu},\r
{0xC2u, 0x0Fu},\r
- {0xE2u, 0x01u},\r
- {0xE6u, 0x08u},\r
+ {0xE2u, 0x04u},\r
+ {0xE6u, 0x01u},\r
{0xE8u, 0x08u},\r
- {0x82u, 0x02u},\r
- {0x8Fu, 0x40u},\r
- {0x96u, 0x40u},\r
- {0x9Bu, 0x02u},\r
- {0x9Eu, 0x01u},\r
- {0xA1u, 0x10u},\r
- {0xA2u, 0x02u},\r
- {0xA7u, 0x40u},\r
- {0xAAu, 0x40u},\r
- {0xABu, 0x80u},\r
- {0xACu, 0x20u},\r
+ {0xECu, 0x02u},\r
+ {0xEEu, 0x04u},\r
+ {0x81u, 0x80u},\r
+ {0x89u, 0x10u},\r
+ {0x8Au, 0x10u},\r
+ {0x92u, 0x01u},\r
+ {0x9Bu, 0x40u},\r
+ {0xA1u, 0x80u},\r
+ {0xA2u, 0x10u},\r
{0xAFu, 0x40u},\r
- {0xB7u, 0x10u},\r
- {0xE4u, 0x02u},\r
- {0xEAu, 0x08u},\r
- {0x09u, 0x08u},\r
+ {0xB3u, 0x08u},\r
+ {0xE2u, 0x01u},\r
+ {0xE6u, 0x04u},\r
+ {0xEEu, 0x01u},\r
+ {0x09u, 0x04u},\r
{0x0Au, 0x01u},\r
- {0x0Eu, 0x40u},\r
- {0x0Fu, 0x01u},\r
- {0x82u, 0x01u},\r
+ {0x0Du, 0x10u},\r
+ {0x0Fu, 0x80u},\r
+ {0x83u, 0x40u},\r
{0x86u, 0x01u},\r
- {0x96u, 0x40u},\r
- {0x9Eu, 0x01u},\r
- {0xA9u, 0x10u},\r
- {0xAFu, 0x02u},\r
- {0xC2u, 0x0Fu},\r
- {0x81u, 0x04u},\r
- {0x86u, 0x08u},\r
- {0x96u, 0x08u},\r
- {0x99u, 0x20u},\r
- {0x9Eu, 0x08u},\r
- {0xA3u, 0x04u},\r
+ {0x95u, 0x20u},\r
+ {0x9Bu, 0x40u},\r
{0xA5u, 0x04u},\r
- {0xABu, 0x04u},\r
- {0xAFu, 0x01u},\r
- {0xB4u, 0x20u},\r
- {0xE2u, 0x20u},\r
- {0xE6u, 0x40u},\r
- {0xEAu, 0x40u},\r
- {0xEEu, 0x20u},\r
- {0x06u, 0x40u},\r
- {0x57u, 0x04u},\r
- {0x59u, 0x20u},\r
- {0x86u, 0x40u},\r
- {0x99u, 0x20u},\r
- {0xA3u, 0x04u},\r
- {0xAEu, 0x04u},\r
+ {0xA9u, 0x04u},\r
+ {0xAEu, 0x01u},\r
+ {0xC2u, 0x0Fu},\r
+ {0x67u, 0x80u},\r
+ {0x82u, 0x02u},\r
+ {0x87u, 0x40u},\r
+ {0x8Fu, 0x40u},\r
+ {0x94u, 0x04u},\r
+ {0x9Fu, 0x40u},\r
+ {0xA2u, 0x02u},\r
+ {0xB1u, 0x08u},\r
+ {0xB6u, 0x02u},\r
+ {0xD8u, 0x80u},\r
+ {0xE2u, 0x10u},\r
+ {0xE6u, 0x20u},\r
+ {0x04u, 0x02u},\r
+ {0x52u, 0x02u},\r
+ {0x56u, 0x02u},\r
+ {0x8Cu, 0x01u},\r
+ {0x9Au, 0x02u},\r
+ {0xA2u, 0x02u},\r
+ {0xA8u, 0x04u},\r
{0xC0u, 0x20u},\r
- {0xD4u, 0xC0u},\r
- {0xE0u, 0x10u},\r
- {0xEEu, 0x10u},\r
- {0xADu, 0x08u},\r
- {0xB7u, 0x01u},\r
- {0xEEu, 0x08u},\r
- {0x02u, 0x40u},\r
- {0x8Au, 0x40u},\r
+ {0xD4u, 0x80u},\r
+ {0xD6u, 0x20u},\r
+ {0xEAu, 0x20u},\r
+ {0xABu, 0x40u},\r
+ {0x01u, 0x04u},\r
+ {0x89u, 0x04u},\r
{0xC0u, 0x08u},\r
- {0xE6u, 0x01u},\r
- {0x10u, 0x01u},\r
- {0x11u, 0x01u},\r
- {0x1Au, 0x01u},\r
- {0x1Bu, 0x01u},\r
- {0x1Du, 0x01u},\r
+ {0xE2u, 0x04u},\r
+ {0x10u, 0x03u},\r
+ {0x1Au, 0x03u},\r
{0x00u, 0xFDu},\r
{0x01u, 0xBFu},\r
{0x02u, 0x2Au},\r
{(void CYFAR *)(CYREG_TMR0_CFG0), 12u},\r
{(void CYFAR *)(CYREG_PRT1_DR), 16u},\r
{(void CYFAR *)(CYDEV_UCFG_B0_P0_U0_BASE), 4096u},\r
- {(void CYFAR *)(CYDEV_UCFG_B1_P2_U0_BASE), 2048u},\r
+ {(void CYFAR *)(CYDEV_UCFG_B1_P2_U1_BASE), 1920u},\r
{(void CYFAR *)(CYDEV_UCFG_DSI0_BASE), 2560u},\r
{(void CYFAR *)(CYDEV_UCFG_DSI12_BASE), 512u},\r
{(void CYFAR *)(CYREG_BCTL1_MDCLK_EN), 16u},\r
};\r
\r
+ /* UDB_1_0_0_CONFIG Address: CYDEV_UCFG_B1_P2_U0_BASE Size (bytes): 128 */\r
+ static const uint8 CYCODE BS_UDB_1_0_0_CONFIG_VAL[] = {\r
+ 0x39u, 0x71u, 0x06u, 0x00u, 0x42u, 0x12u, 0x04u, 0x01u, 0x77u, 0x05u, 0x08u, 0x0Au, 0x46u, 0x30u, 0x00u, 0x41u, \r
+ 0x46u, 0x00u, 0x00u, 0x00u, 0x00u, 0x41u, 0x00u, 0x30u, 0x01u, 0x51u, 0x5Eu, 0x20u, 0x04u, 0x20u, 0x20u, 0x00u, \r
+ 0x00u, 0x71u, 0x00u, 0x00u, 0x42u, 0x03u, 0x00u, 0x3Cu, 0x00u, 0x00u, 0x46u, 0x00u, 0x46u, 0x06u, 0x00u, 0x39u, \r
+ 0x0Fu, 0x40u, 0x00u, 0x3Cu, 0x70u, 0x03u, 0x08u, 0x00u, 0x02u, 0x00u, 0x30u, 0x20u, 0x00u, 0x00u, 0x40u, 0x01u, \r
+ 0x42u, 0x03u, 0x50u, 0x00u, 0x06u, 0xBEu, 0xFCu, 0xD0u, 0x2Fu, 0xFFu, 0xFFu, 0xFFu, 0x22u, 0x00u, 0xF0u, 0x08u, \r
+ 0x04u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x04u, 0x04u, 0x04u, 0x00u, 0x00u, 0x00u, 0x00u, 0x01u, \r
+ 0x00u, 0x00u, 0xC0u, 0x00u, 0x40u, 0x01u, 0x10u, 0x11u, 0xC0u, 0x01u, 0x00u, 0x11u, 0x40u, 0x01u, 0x40u, 0x01u, \r
+ 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u};\r
+\r
/* UCFG_BCTL0 Address: CYREG_BCTL0_MDCLK_EN Size (bytes): 16 */\r
static const uint8 CYCODE BS_UCFG_BCTL0_VAL[] = {\r
0x03u, 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x01u, 0x03u, 0x01u, 0x02u, 0x01u, 0x02u, 0x01u};\r
\r
static const cfg_memcpy_t CYCODE cfg_memcpy_list [] = {\r
/* dest, src, size */\r
+ {(void CYFAR *)(CYDEV_UCFG_B1_P2_U0_BASE), BS_UDB_1_0_0_CONFIG_VAL, 128u},\r
{(void CYFAR *)(CYREG_BCTL0_MDCLK_EN), BS_UCFG_BCTL0_VAL, 16u},\r
};\r
\r
CY_SET_XTND_REG8((void CYFAR *)CYREG_PM_AVAIL_CR2, CY_GET_XTND_REG8((void CYFAR *)CYREG_PM_AVAIL_CR2) | 0x10u);\r
}\r
\r
+\r
/* Perform second pass device configuration. These items must be configured in specific order after the regular configuration is done. */\r
CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT0_DM0), (const void CYCODE *)(BS_IOPINS0_0_VAL), 8u);\r
CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT12_DR), (const void CYCODE *)(BS_IOPINS0_7_VAL), 10u);\r
CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT4_DM0), (const void CYCODE *)(BS_IOPINS0_4_VAL), 8u);\r
CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT5_DM0), (const void CYCODE *)(BS_IOPINS0_5_VAL), 8u);\r
CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT6_DM0), (const void CYCODE *)(BS_IOPINS0_6_VAL), 8u);\r
-\r
/* Switch Boost to the precision bandgap reference from its internal reference */\r
CY_SET_REG8((void CYXDATA *)CYREG_BOOST_CR2, (CY_GET_REG8((void CYXDATA *)CYREG_BOOST_CR2) | 0x08u));\r
\r
/*******************************************************************************\r
* FILENAME: cyfitter_cfg.h\r
-* PSoC Creator 3.1\r
+* \r
+* PSoC Creator 3.2\r
*\r
-* Description:\r
+* DESCRIPTION:\r
+* This file provides basic startup and mux configration settings\r
* This file is automatically generated by PSoC Creator.\r
*\r
********************************************************************************\r
-* Copyright 2012, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright (c) 2007-2015 Cypress Semiconductor. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions, \r
* disclaimers, and limitations in the end user license agreement accompanying \r
* the software package with which this file was provided.\r
#ifndef CYFITTER_CFG_H\r
#define CYFITTER_CFG_H\r
\r
-#include <cytypes.h>\r
+#include "cytypes.h"\r
\r
extern void cyfitter_cfg(void);\r
\r
.set SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B1_UDB05_ST_CTL\r
.set SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B1_UDB05_ST_CTL\r
.set SDCard_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B1_UDB05_ST\r
-.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB04_05_ACTL\r
-.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB04_05_ST\r
+.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB06_07_ACTL\r
+.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB06_07_ST\r
.set SDCard_BSPIM_RxStsReg__4__MASK, 0x10\r
.set SDCard_BSPIM_RxStsReg__4__POS, 4\r
.set SDCard_BSPIM_RxStsReg__5__MASK, 0x20\r
.set SDCard_BSPIM_RxStsReg__6__MASK, 0x40\r
.set SDCard_BSPIM_RxStsReg__6__POS, 6\r
.set SDCard_BSPIM_RxStsReg__MASK, 0x70\r
-.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B1_UDB04_MSK\r
-.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB04_ACTL\r
-.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B1_UDB04_ST\r
+.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B1_UDB06_MSK\r
+.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB06_ACTL\r
+.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B1_UDB06_ST\r
.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG, CYREG_B1_UDB04_05_A0\r
.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG, CYREG_B1_UDB04_05_A1\r
.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG, CYREG_B1_UDB04_05_D0\r
.set SCSI_Out_Bits_Sync_ctrl_reg__0__POS, 0\r
.set SCSI_Out_Bits_Sync_ctrl_reg__1__MASK, 0x02\r
.set SCSI_Out_Bits_Sync_ctrl_reg__1__POS, 1\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB11_12_ACTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB11_12_CTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB11_12_CTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB11_12_CTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB11_12_CTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB11_12_MSK\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB11_12_MSK\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB11_12_MSK\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB11_12_MSK\r
.set SCSI_Out_Bits_Sync_ctrl_reg__2__MASK, 0x04\r
.set SCSI_Out_Bits_Sync_ctrl_reg__2__POS, 2\r
.set SCSI_Out_Bits_Sync_ctrl_reg__3__MASK, 0x08\r
.set SCSI_Out_Bits_Sync_ctrl_reg__6__POS, 6\r
.set SCSI_Out_Bits_Sync_ctrl_reg__7__MASK, 0x80\r
.set SCSI_Out_Bits_Sync_ctrl_reg__7__POS, 7\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B1_UDB11_ACTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG, CYREG_B1_UDB11_CTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B1_UDB11_ST_CTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG, CYREG_B1_UDB11_CTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B1_UDB11_ST_CTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB11_ACTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB11_CTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB11_ST_CTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB11_CTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB11_ST_CTL\r
.set SCSI_Out_Bits_Sync_ctrl_reg__MASK, 0xFF\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB11_MSK_ACTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB11_MSK_ACTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG, CYREG_B1_UDB11_MSK\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB11_MSK\r
\r
/* SCSI_Out_Ctl */\r
.set SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK, 0x01\r
.set SCSI_Out_Ctl_Sync_ctrl_reg__0__POS, 0\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB12_13_ACTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB12_13_CTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB12_13_CTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB12_13_CTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB12_13_CTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB12_13_MSK\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB12_13_MSK\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB12_13_MSK\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB12_13_MSK\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB12_ACTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB12_CTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB12_ST_CTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB12_CTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB12_ST_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB15_ACTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB15_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB15_ST_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB15_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB15_ST_CTL\r
.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK, 0x01\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB12_MSK\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB15_MSK_ACTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB15_MSK_ACTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB15_MSK\r
\r
/* SCSI_Out_DBx */\r
.set SCSI_Out_DBx__0__AG, CYREG_PRT6_AG\r
.set scsiTarget_StatusReg__0__POS, 0\r
.set scsiTarget_StatusReg__1__MASK, 0x02\r
.set scsiTarget_StatusReg__1__POS, 1\r
+.set scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB02_03_ACTL\r
+.set scsiTarget_StatusReg__16BIT_STATUS_REG, CYREG_B0_UDB02_03_ST\r
.set scsiTarget_StatusReg__2__MASK, 0x04\r
.set scsiTarget_StatusReg__2__POS, 2\r
.set scsiTarget_StatusReg__3__MASK, 0x08\r
.set scsiTarget_StatusReg__4__MASK, 0x10\r
.set scsiTarget_StatusReg__4__POS, 4\r
.set scsiTarget_StatusReg__MASK, 0x1F\r
-.set scsiTarget_StatusReg__MASK_REG, CYREG_B0_UDB15_MSK\r
-.set scsiTarget_StatusReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB15_ACTL\r
-.set scsiTarget_StatusReg__STATUS_REG, CYREG_B0_UDB15_ST\r
+.set scsiTarget_StatusReg__MASK_REG, CYREG_B0_UDB02_MSK\r
+.set scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB02_MSK_ACTL\r
+.set scsiTarget_StatusReg__PER_ST_AUX_CTL_REG, CYREG_B0_UDB02_MSK_ACTL\r
+.set scsiTarget_StatusReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB02_ACTL\r
+.set scsiTarget_StatusReg__STATUS_CNT_REG, CYREG_B0_UDB02_ST_CTL\r
+.set scsiTarget_StatusReg__STATUS_CONTROL_REG, CYREG_B0_UDB02_ST_CTL\r
+.set scsiTarget_StatusReg__STATUS_REG, CYREG_B0_UDB02_ST\r
\r
/* Debug_Timer_Interrupt */\r
.set Debug_Timer_Interrupt__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
.set SCSI_Filtered_sts_sts_reg__0__POS, 0\r
.set SCSI_Filtered_sts_sts_reg__1__MASK, 0x02\r
.set SCSI_Filtered_sts_sts_reg__1__POS, 1\r
-.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB07_08_ACTL\r
-.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB07_08_ST\r
+.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB10_11_ACTL\r
+.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB10_11_ST\r
.set SCSI_Filtered_sts_sts_reg__2__MASK, 0x04\r
.set SCSI_Filtered_sts_sts_reg__2__POS, 2\r
.set SCSI_Filtered_sts_sts_reg__3__MASK, 0x08\r
.set SCSI_Filtered_sts_sts_reg__4__MASK, 0x10\r
.set SCSI_Filtered_sts_sts_reg__4__POS, 4\r
.set SCSI_Filtered_sts_sts_reg__MASK, 0x1F\r
-.set SCSI_Filtered_sts_sts_reg__MASK_REG, CYREG_B0_UDB07_MSK\r
-.set SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB07_ACTL\r
-.set SCSI_Filtered_sts_sts_reg__STATUS_REG, CYREG_B0_UDB07_ST\r
+.set SCSI_Filtered_sts_sts_reg__MASK_REG, CYREG_B0_UDB10_MSK\r
+.set SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB10_ACTL\r
+.set SCSI_Filtered_sts_sts_reg__STATUS_REG, CYREG_B0_UDB10_ST\r
\r
/* SCSI_CTL_PHASE */\r
.set SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK, 0x01\r
.set SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS, 0\r
.set SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK, 0x02\r
.set SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS, 1\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB01_02_ACTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB01_02_CTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB01_02_CTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB01_02_CTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB01_02_CTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB01_02_MSK\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB01_02_MSK\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB01_02_MSK\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB01_02_MSK\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB02_03_ACTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB02_03_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB02_03_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB02_03_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB02_03_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB02_03_MSK\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB02_03_MSK\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB02_03_MSK\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB02_03_MSK\r
.set SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK, 0x04\r
.set SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS, 2\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB01_ACTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB01_CTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB01_ST_CTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB01_CTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB01_ST_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB02_ACTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB02_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB02_ST_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB02_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB02_ST_CTL\r
.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK, 0x07\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB01_MSK_ACTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB01_MSK_ACTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB01_MSK\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB02_MSK_ACTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB02_MSK_ACTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB02_MSK\r
\r
/* SCSI_Glitch_Ctl */\r
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK, 0x01\r
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS, 0\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB10_11_ACTL\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB10_11_CTL\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB10_11_CTL\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB10_11_CTL\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB10_11_CTL\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB10_11_MSK\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB10_11_MSK\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB10_11_MSK\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB10_11_MSK\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB10_ACTL\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB10_CTL\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB10_ST_CTL\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB10_CTL\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB10_ST_CTL\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB04_05_ACTL\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB04_05_CTL\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB04_05_CTL\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB04_05_CTL\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB04_05_CTL\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB04_05_MSK\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB04_05_MSK\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB04_05_MSK\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB04_05_MSK\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB04_ACTL\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB04_CTL\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB04_ST_CTL\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB04_CTL\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB04_ST_CTL\r
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK, 0x01\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB10_MSK_ACTL\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB10_MSK_ACTL\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB10_MSK\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB04_MSK\r
\r
/* SCSI_Parity_Error */\r
.set SCSI_Parity_Error_sts_sts_reg__0__MASK, 0x01\r
.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB11_12_ST\r
.set SCSI_Parity_Error_sts_sts_reg__MASK, 0x01\r
.set SCSI_Parity_Error_sts_sts_reg__MASK_REG, CYREG_B0_UDB11_MSK\r
+.set SCSI_Parity_Error_sts_sts_reg__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL\r
+.set SCSI_Parity_Error_sts_sts_reg__PER_ST_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL\r
.set SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB11_ACTL\r
+.set SCSI_Parity_Error_sts_sts_reg__STATUS_CNT_REG, CYREG_B0_UDB11_ST_CTL\r
+.set SCSI_Parity_Error_sts_sts_reg__STATUS_CONTROL_REG, CYREG_B0_UDB11_ST_CTL\r
.set SCSI_Parity_Error_sts_sts_reg__STATUS_REG, CYREG_B0_UDB11_ST\r
\r
/* Miscellaneous */\r
.set BCLK__BUS_CLK__HZ, 50000000\r
.set BCLK__BUS_CLK__KHZ, 50000\r
.set BCLK__BUS_CLK__MHZ, 50\r
+.set CYDEV_CHIP_DIE_GEN4, 2\r
.set CYDEV_CHIP_DIE_LEOPARD, 1\r
-.set CYDEV_CHIP_DIE_PANTHER, 6\r
-.set CYDEV_CHIP_DIE_PSOC4A, 3\r
-.set CYDEV_CHIP_DIE_PSOC5LP, 5\r
+.set CYDEV_CHIP_DIE_PANTHER, 12\r
+.set CYDEV_CHIP_DIE_PSOC4A, 5\r
+.set CYDEV_CHIP_DIE_PSOC5LP, 11\r
.set CYDEV_CHIP_DIE_UNKNOWN, 0\r
.set CYDEV_CHIP_FAMILY_PSOC3, 1\r
.set CYDEV_CHIP_FAMILY_PSOC4, 2\r
.set CYDEV_CHIP_FAMILY_USED, CYDEV_CHIP_FAMILY_PSOC5\r
.set CYDEV_CHIP_JTAG_ID, 0x2E133069\r
.set CYDEV_CHIP_MEMBER_3A, 1\r
-.set CYDEV_CHIP_MEMBER_4A, 3\r
-.set CYDEV_CHIP_MEMBER_4D, 2\r
-.set CYDEV_CHIP_MEMBER_4F, 4\r
-.set CYDEV_CHIP_MEMBER_5A, 6\r
-.set CYDEV_CHIP_MEMBER_5B, 5\r
+.set CYDEV_CHIP_MEMBER_4A, 5\r
+.set CYDEV_CHIP_MEMBER_4C, 9\r
+.set CYDEV_CHIP_MEMBER_4D, 3\r
+.set CYDEV_CHIP_MEMBER_4E, 4\r
+.set CYDEV_CHIP_MEMBER_4F, 6\r
+.set CYDEV_CHIP_MEMBER_4G, 2\r
+.set CYDEV_CHIP_MEMBER_4L, 8\r
+.set CYDEV_CHIP_MEMBER_4M, 7\r
+.set CYDEV_CHIP_MEMBER_5A, 11\r
+.set CYDEV_CHIP_MEMBER_5B, 10\r
.set CYDEV_CHIP_MEMBER_UNKNOWN, 0\r
.set CYDEV_CHIP_MEMBER_USED, CYDEV_CHIP_MEMBER_5B\r
.set CYDEV_CHIP_DIE_EXPECT, CYDEV_CHIP_MEMBER_USED\r
.set CYDEV_CHIP_DIE_ACTUAL, CYDEV_CHIP_DIE_EXPECT\r
+.set CYDEV_CHIP_REV_GEN4_ES, 17\r
+.set CYDEV_CHIP_REV_GEN4_ES2, 33\r
+.set CYDEV_CHIP_REV_GEN4_PRODUCTION, 17\r
.set CYDEV_CHIP_REV_LEOPARD_ES1, 0\r
.set CYDEV_CHIP_REV_LEOPARD_ES2, 1\r
.set CYDEV_CHIP_REV_LEOPARD_ES3, 3\r
.set CYDEV_CHIP_REVISION_3A_PRODUCTION, 3\r
.set CYDEV_CHIP_REVISION_4A_ES0, 17\r
.set CYDEV_CHIP_REVISION_4A_PRODUCTION, 17\r
+.set CYDEV_CHIP_REVISION_4C_PRODUCTION, 0\r
.set CYDEV_CHIP_REVISION_4D_PRODUCTION, 0\r
+.set CYDEV_CHIP_REVISION_4E_PRODUCTION, 0\r
.set CYDEV_CHIP_REVISION_4F_PRODUCTION, 0\r
+.set CYDEV_CHIP_REVISION_4F_PRODUCTION_256K, 0\r
+.set CYDEV_CHIP_REVISION_4G_ES, 17\r
+.set CYDEV_CHIP_REVISION_4G_ES2, 33\r
+.set CYDEV_CHIP_REVISION_4G_PRODUCTION, 17\r
+.set CYDEV_CHIP_REVISION_4L_PRODUCTION, 0\r
+.set CYDEV_CHIP_REVISION_4M_PRODUCTION, 0\r
.set CYDEV_CHIP_REVISION_5A_ES0, 0\r
.set CYDEV_CHIP_REVISION_5A_ES1, 1\r
.set CYDEV_CHIP_REVISION_5A_PRODUCTION, 1\r
.set CYDEV_CONFIGURATION_MODE_UNCOMPRESSED, 1\r
.set CYDEV_DEBUG_ENABLE_MASK, 0x20\r
.set CYDEV_DEBUG_ENABLE_REGISTER, CYREG_MLOGIC_DEBUG\r
-.set CYDEV_DEBUGGING_DPS_Disable, 3\r
-.set CYDEV_DEBUGGING_DPS_JTAG_4, 1\r
-.set CYDEV_DEBUGGING_DPS_JTAG_5, 0\r
.set CYDEV_DEBUGGING_DPS_SWD, 2\r
.set CYDEV_DEBUGGING_DPS_SWD_SWV, 6\r
.set CYDEV_DEBUGGING_DPS, CYDEV_DEBUGGING_DPS_SWD_SWV\r
.set CYDEV_INTR_RISING, 0x0000007E\r
.set CYDEV_PROJ_TYPE, 2\r
.set CYDEV_PROJ_TYPE_BOOTLOADER, 1\r
+.set CYDEV_PROJ_TYPE_LAUNCHER, 5\r
.set CYDEV_PROJ_TYPE_LOADABLE, 2\r
+.set CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER, 4\r
.set CYDEV_PROJ_TYPE_MULTIAPPBOOTLOADER, 3\r
.set CYDEV_PROJ_TYPE_STANDARD, 0\r
.set CYDEV_PROTECTION_ENABLE, 0\r
SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB05_ST_CTL\r
SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB05_ST_CTL\r
SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB05_ST\r
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL\r
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB04_05_ST\r
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL\r
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB06_07_ST\r
SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10\r
SDCard_BSPIM_RxStsReg__4__POS EQU 4\r
SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20\r
SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40\r
SDCard_BSPIM_RxStsReg__6__POS EQU 6\r
SDCard_BSPIM_RxStsReg__MASK EQU 0x70\r
-SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB04_MSK\r
-SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL\r
-SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB04_ST\r
+SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB06_MSK\r
+SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL\r
+SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB06_ST\r
SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB04_05_A0\r
SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB04_05_A1\r
SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B1_UDB04_05_D0\r
SCSI_Out_Bits_Sync_ctrl_reg__0__POS EQU 0\r
SCSI_Out_Bits_Sync_ctrl_reg__1__MASK EQU 0x02\r
SCSI_Out_Bits_Sync_ctrl_reg__1__POS EQU 1\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB11_12_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB11_12_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB11_12_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB11_12_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK\r
SCSI_Out_Bits_Sync_ctrl_reg__2__MASK EQU 0x04\r
SCSI_Out_Bits_Sync_ctrl_reg__2__POS EQU 2\r
SCSI_Out_Bits_Sync_ctrl_reg__3__MASK EQU 0x08\r
SCSI_Out_Bits_Sync_ctrl_reg__6__POS EQU 6\r
SCSI_Out_Bits_Sync_ctrl_reg__7__MASK EQU 0x80\r
SCSI_Out_Bits_Sync_ctrl_reg__7__POS EQU 7\r
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB11_ACTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B1_UDB11_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B1_UDB11_ST_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B1_UDB11_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B1_UDB11_ST_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB11_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB11_ST_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB11_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB11_ST_CTL\r
SCSI_Out_Bits_Sync_ctrl_reg__MASK EQU 0xFF\r
-SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB11_MSK_ACTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB11_MSK_ACTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B1_UDB11_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB11_MSK\r
\r
/* SCSI_Out_Ctl */\r
SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01\r
SCSI_Out_Ctl_Sync_ctrl_reg__0__POS EQU 0\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB12_13_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB12_13_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB12_13_MSK\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB12_13_MSK\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK\r
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB12_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB12_ST_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB12_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB12_ST_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB15_ACTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB15_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB15_ST_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB15_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB15_ST_CTL\r
SCSI_Out_Ctl_Sync_ctrl_reg__MASK EQU 0x01\r
-SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB12_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB15_MSK_ACTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB15_MSK_ACTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB15_MSK\r
\r
/* SCSI_Out_DBx */\r
SCSI_Out_DBx__0__AG EQU CYREG_PRT6_AG\r
scsiTarget_StatusReg__0__POS EQU 0\r
scsiTarget_StatusReg__1__MASK EQU 0x02\r
scsiTarget_StatusReg__1__POS EQU 1\r
+scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL\r
+scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB02_03_ST\r
scsiTarget_StatusReg__2__MASK EQU 0x04\r
scsiTarget_StatusReg__2__POS EQU 2\r
scsiTarget_StatusReg__3__MASK EQU 0x08\r
scsiTarget_StatusReg__4__MASK EQU 0x10\r
scsiTarget_StatusReg__4__POS EQU 4\r
scsiTarget_StatusReg__MASK EQU 0x1F\r
-scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB15_MSK\r
-scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB15_ACTL\r
-scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB15_ST\r
+scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB02_MSK\r
+scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL\r
+scsiTarget_StatusReg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL\r
+scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL\r
+scsiTarget_StatusReg__STATUS_CNT_REG EQU CYREG_B0_UDB02_ST_CTL\r
+scsiTarget_StatusReg__STATUS_CONTROL_REG EQU CYREG_B0_UDB02_ST_CTL\r
+scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB02_ST\r
\r
/* Debug_Timer_Interrupt */\r
Debug_Timer_Interrupt__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
SCSI_Filtered_sts_sts_reg__0__POS EQU 0\r
SCSI_Filtered_sts_sts_reg__1__MASK EQU 0x02\r
SCSI_Filtered_sts_sts_reg__1__POS EQU 1\r
-SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL\r
-SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB07_08_ST\r
+SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB10_11_ACTL\r
+SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB10_11_ST\r
SCSI_Filtered_sts_sts_reg__2__MASK EQU 0x04\r
SCSI_Filtered_sts_sts_reg__2__POS EQU 2\r
SCSI_Filtered_sts_sts_reg__3__MASK EQU 0x08\r
SCSI_Filtered_sts_sts_reg__4__MASK EQU 0x10\r
SCSI_Filtered_sts_sts_reg__4__POS EQU 4\r
SCSI_Filtered_sts_sts_reg__MASK EQU 0x1F\r
-SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB07_MSK\r
-SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL\r
-SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB07_ST\r
+SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB10_MSK\r
+SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB10_ACTL\r
+SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB10_ST\r
\r
/* SCSI_CTL_PHASE */\r
SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01\r
SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS EQU 0\r
SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK EQU 0x02\r
SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS EQU 1\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB01_02_ACTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB01_02_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB01_02_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB01_02_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB01_02_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB01_02_MSK\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB01_02_MSK\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB01_02_MSK\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB01_02_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB02_03_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB02_03_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB02_03_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB02_03_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK\r
SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK EQU 0x04\r
SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS EQU 2\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB01_ACTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB01_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB01_ST_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB01_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB01_ST_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB02_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB02_ST_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB02_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB02_ST_CTL\r
SCSI_CTL_PHASE_Sync_ctrl_reg__MASK EQU 0x07\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB01_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB02_MSK\r
\r
/* SCSI_Glitch_Ctl */\r
SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01\r
SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS EQU 0\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB10_11_ACTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB10_11_CTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB10_11_CTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB10_11_CTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB10_11_CTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB10_11_MSK\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB10_11_MSK\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB10_11_MSK\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB10_11_MSK\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB10_ACTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB10_CTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB10_ST_CTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB10_CTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB10_ST_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB04_05_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB04_05_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB04_05_MSK\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB04_05_MSK\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB04_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB04_ST_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB04_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB04_ST_CTL\r
SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK EQU 0x01\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB10_MSK\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB04_MSK\r
\r
/* SCSI_Parity_Error */\r
SCSI_Parity_Error_sts_sts_reg__0__MASK EQU 0x01\r
SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB11_12_ST\r
SCSI_Parity_Error_sts_sts_reg__MASK EQU 0x01\r
SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB11_MSK\r
+SCSI_Parity_Error_sts_sts_reg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL\r
+SCSI_Parity_Error_sts_sts_reg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL\r
SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL\r
+SCSI_Parity_Error_sts_sts_reg__STATUS_CNT_REG EQU CYREG_B0_UDB11_ST_CTL\r
+SCSI_Parity_Error_sts_sts_reg__STATUS_CONTROL_REG EQU CYREG_B0_UDB11_ST_CTL\r
SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB11_ST\r
\r
/* Miscellaneous */\r
BCLK__BUS_CLK__HZ EQU 50000000\r
BCLK__BUS_CLK__KHZ EQU 50000\r
BCLK__BUS_CLK__MHZ EQU 50\r
+CYDEV_CHIP_DIE_GEN4 EQU 2\r
CYDEV_CHIP_DIE_LEOPARD EQU 1\r
-CYDEV_CHIP_DIE_PANTHER EQU 6\r
-CYDEV_CHIP_DIE_PSOC4A EQU 3\r
-CYDEV_CHIP_DIE_PSOC5LP EQU 5\r
+CYDEV_CHIP_DIE_PANTHER EQU 12\r
+CYDEV_CHIP_DIE_PSOC4A EQU 5\r
+CYDEV_CHIP_DIE_PSOC5LP EQU 11\r
CYDEV_CHIP_DIE_UNKNOWN EQU 0\r
CYDEV_CHIP_FAMILY_PSOC3 EQU 1\r
CYDEV_CHIP_FAMILY_PSOC4 EQU 2\r
CYDEV_CHIP_FAMILY_USED EQU CYDEV_CHIP_FAMILY_PSOC5\r
CYDEV_CHIP_JTAG_ID EQU 0x2E133069\r
CYDEV_CHIP_MEMBER_3A EQU 1\r
-CYDEV_CHIP_MEMBER_4A EQU 3\r
-CYDEV_CHIP_MEMBER_4D EQU 2\r
-CYDEV_CHIP_MEMBER_4F EQU 4\r
-CYDEV_CHIP_MEMBER_5A EQU 6\r
-CYDEV_CHIP_MEMBER_5B EQU 5\r
+CYDEV_CHIP_MEMBER_4A EQU 5\r
+CYDEV_CHIP_MEMBER_4C EQU 9\r
+CYDEV_CHIP_MEMBER_4D EQU 3\r
+CYDEV_CHIP_MEMBER_4E EQU 4\r
+CYDEV_CHIP_MEMBER_4F EQU 6\r
+CYDEV_CHIP_MEMBER_4G EQU 2\r
+CYDEV_CHIP_MEMBER_4L EQU 8\r
+CYDEV_CHIP_MEMBER_4M EQU 7\r
+CYDEV_CHIP_MEMBER_5A EQU 11\r
+CYDEV_CHIP_MEMBER_5B EQU 10\r
CYDEV_CHIP_MEMBER_UNKNOWN EQU 0\r
CYDEV_CHIP_MEMBER_USED EQU CYDEV_CHIP_MEMBER_5B\r
CYDEV_CHIP_DIE_EXPECT EQU CYDEV_CHIP_MEMBER_USED\r
CYDEV_CHIP_DIE_ACTUAL EQU CYDEV_CHIP_DIE_EXPECT\r
+CYDEV_CHIP_REV_GEN4_ES EQU 17\r
+CYDEV_CHIP_REV_GEN4_ES2 EQU 33\r
+CYDEV_CHIP_REV_GEN4_PRODUCTION EQU 17\r
CYDEV_CHIP_REV_LEOPARD_ES1 EQU 0\r
CYDEV_CHIP_REV_LEOPARD_ES2 EQU 1\r
CYDEV_CHIP_REV_LEOPARD_ES3 EQU 3\r
CYDEV_CHIP_REVISION_3A_PRODUCTION EQU 3\r
CYDEV_CHIP_REVISION_4A_ES0 EQU 17\r
CYDEV_CHIP_REVISION_4A_PRODUCTION EQU 17\r
+CYDEV_CHIP_REVISION_4C_PRODUCTION EQU 0\r
CYDEV_CHIP_REVISION_4D_PRODUCTION EQU 0\r
+CYDEV_CHIP_REVISION_4E_PRODUCTION EQU 0\r
CYDEV_CHIP_REVISION_4F_PRODUCTION EQU 0\r
+CYDEV_CHIP_REVISION_4F_PRODUCTION_256K EQU 0\r
+CYDEV_CHIP_REVISION_4G_ES EQU 17\r
+CYDEV_CHIP_REVISION_4G_ES2 EQU 33\r
+CYDEV_CHIP_REVISION_4G_PRODUCTION EQU 17\r
+CYDEV_CHIP_REVISION_4L_PRODUCTION EQU 0\r
+CYDEV_CHIP_REVISION_4M_PRODUCTION EQU 0\r
CYDEV_CHIP_REVISION_5A_ES0 EQU 0\r
CYDEV_CHIP_REVISION_5A_ES1 EQU 1\r
CYDEV_CHIP_REVISION_5A_PRODUCTION EQU 1\r
CYDEV_CONFIGURATION_MODE_UNCOMPRESSED EQU 1\r
CYDEV_DEBUG_ENABLE_MASK EQU 0x20\r
CYDEV_DEBUG_ENABLE_REGISTER EQU CYREG_MLOGIC_DEBUG\r
-CYDEV_DEBUGGING_DPS_Disable EQU 3\r
-CYDEV_DEBUGGING_DPS_JTAG_4 EQU 1\r
-CYDEV_DEBUGGING_DPS_JTAG_5 EQU 0\r
CYDEV_DEBUGGING_DPS_SWD EQU 2\r
CYDEV_DEBUGGING_DPS_SWD_SWV EQU 6\r
CYDEV_DEBUGGING_DPS EQU CYDEV_DEBUGGING_DPS_SWD_SWV\r
CYDEV_INTR_RISING EQU 0x0000007E\r
CYDEV_PROJ_TYPE EQU 2\r
CYDEV_PROJ_TYPE_BOOTLOADER EQU 1\r
+CYDEV_PROJ_TYPE_LAUNCHER EQU 5\r
CYDEV_PROJ_TYPE_LOADABLE EQU 2\r
+CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER EQU 4\r
CYDEV_PROJ_TYPE_MULTIAPPBOOTLOADER EQU 3\r
CYDEV_PROJ_TYPE_STANDARD EQU 0\r
CYDEV_PROTECTION_ENABLE EQU 0\r
SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB05_ST_CTL\r
SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB05_ST_CTL\r
SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB05_ST\r
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL\r
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB04_05_ST\r
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL\r
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB06_07_ST\r
SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10\r
SDCard_BSPIM_RxStsReg__4__POS EQU 4\r
SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20\r
SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40\r
SDCard_BSPIM_RxStsReg__6__POS EQU 6\r
SDCard_BSPIM_RxStsReg__MASK EQU 0x70\r
-SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB04_MSK\r
-SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL\r
-SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB04_ST\r
+SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB06_MSK\r
+SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL\r
+SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB06_ST\r
SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB04_05_A0\r
SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB04_05_A1\r
SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B1_UDB04_05_D0\r
SCSI_Out_Bits_Sync_ctrl_reg__0__POS EQU 0\r
SCSI_Out_Bits_Sync_ctrl_reg__1__MASK EQU 0x02\r
SCSI_Out_Bits_Sync_ctrl_reg__1__POS EQU 1\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB11_12_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB11_12_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB11_12_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB11_12_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK\r
SCSI_Out_Bits_Sync_ctrl_reg__2__MASK EQU 0x04\r
SCSI_Out_Bits_Sync_ctrl_reg__2__POS EQU 2\r
SCSI_Out_Bits_Sync_ctrl_reg__3__MASK EQU 0x08\r
SCSI_Out_Bits_Sync_ctrl_reg__6__POS EQU 6\r
SCSI_Out_Bits_Sync_ctrl_reg__7__MASK EQU 0x80\r
SCSI_Out_Bits_Sync_ctrl_reg__7__POS EQU 7\r
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB11_ACTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B1_UDB11_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B1_UDB11_ST_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B1_UDB11_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B1_UDB11_ST_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB11_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB11_ST_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB11_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB11_ST_CTL\r
SCSI_Out_Bits_Sync_ctrl_reg__MASK EQU 0xFF\r
-SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB11_MSK_ACTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB11_MSK_ACTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B1_UDB11_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB11_MSK\r
\r
; SCSI_Out_Ctl\r
SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01\r
SCSI_Out_Ctl_Sync_ctrl_reg__0__POS EQU 0\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB12_13_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB12_13_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB12_13_MSK\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB12_13_MSK\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK\r
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB12_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB12_ST_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB12_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB12_ST_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB15_ACTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB15_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB15_ST_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB15_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB15_ST_CTL\r
SCSI_Out_Ctl_Sync_ctrl_reg__MASK EQU 0x01\r
-SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB12_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB15_MSK_ACTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB15_MSK_ACTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB15_MSK\r
\r
; SCSI_Out_DBx\r
SCSI_Out_DBx__0__AG EQU CYREG_PRT6_AG\r
scsiTarget_StatusReg__0__POS EQU 0\r
scsiTarget_StatusReg__1__MASK EQU 0x02\r
scsiTarget_StatusReg__1__POS EQU 1\r
+scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL\r
+scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB02_03_ST\r
scsiTarget_StatusReg__2__MASK EQU 0x04\r
scsiTarget_StatusReg__2__POS EQU 2\r
scsiTarget_StatusReg__3__MASK EQU 0x08\r
scsiTarget_StatusReg__4__MASK EQU 0x10\r
scsiTarget_StatusReg__4__POS EQU 4\r
scsiTarget_StatusReg__MASK EQU 0x1F\r
-scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB15_MSK\r
-scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB15_ACTL\r
-scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB15_ST\r
+scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB02_MSK\r
+scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL\r
+scsiTarget_StatusReg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL\r
+scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL\r
+scsiTarget_StatusReg__STATUS_CNT_REG EQU CYREG_B0_UDB02_ST_CTL\r
+scsiTarget_StatusReg__STATUS_CONTROL_REG EQU CYREG_B0_UDB02_ST_CTL\r
+scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB02_ST\r
\r
; Debug_Timer_Interrupt\r
Debug_Timer_Interrupt__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
SCSI_Filtered_sts_sts_reg__0__POS EQU 0\r
SCSI_Filtered_sts_sts_reg__1__MASK EQU 0x02\r
SCSI_Filtered_sts_sts_reg__1__POS EQU 1\r
-SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL\r
-SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB07_08_ST\r
+SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB10_11_ACTL\r
+SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB10_11_ST\r
SCSI_Filtered_sts_sts_reg__2__MASK EQU 0x04\r
SCSI_Filtered_sts_sts_reg__2__POS EQU 2\r
SCSI_Filtered_sts_sts_reg__3__MASK EQU 0x08\r
SCSI_Filtered_sts_sts_reg__4__MASK EQU 0x10\r
SCSI_Filtered_sts_sts_reg__4__POS EQU 4\r
SCSI_Filtered_sts_sts_reg__MASK EQU 0x1F\r
-SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB07_MSK\r
-SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL\r
-SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB07_ST\r
+SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB10_MSK\r
+SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB10_ACTL\r
+SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB10_ST\r
\r
; SCSI_CTL_PHASE\r
SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01\r
SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS EQU 0\r
SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK EQU 0x02\r
SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS EQU 1\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB01_02_ACTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB01_02_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB01_02_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB01_02_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB01_02_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB01_02_MSK\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB01_02_MSK\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB01_02_MSK\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB01_02_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB02_03_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB02_03_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB02_03_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB02_03_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK\r
SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK EQU 0x04\r
SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS EQU 2\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB01_ACTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB01_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB01_ST_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB01_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB01_ST_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB02_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB02_ST_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB02_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB02_ST_CTL\r
SCSI_CTL_PHASE_Sync_ctrl_reg__MASK EQU 0x07\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB01_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB02_MSK\r
\r
; SCSI_Glitch_Ctl\r
SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01\r
SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS EQU 0\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB10_11_ACTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB10_11_CTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB10_11_CTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB10_11_CTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB10_11_CTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB10_11_MSK\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB10_11_MSK\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB10_11_MSK\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB10_11_MSK\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB10_ACTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB10_CTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB10_ST_CTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB10_CTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB10_ST_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB04_05_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB04_05_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB04_05_MSK\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB04_05_MSK\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB04_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB04_ST_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB04_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB04_ST_CTL\r
SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK EQU 0x01\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB10_MSK\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB04_MSK\r
\r
; SCSI_Parity_Error\r
SCSI_Parity_Error_sts_sts_reg__0__MASK EQU 0x01\r
SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB11_12_ST\r
SCSI_Parity_Error_sts_sts_reg__MASK EQU 0x01\r
SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB11_MSK\r
+SCSI_Parity_Error_sts_sts_reg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL\r
+SCSI_Parity_Error_sts_sts_reg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL\r
SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL\r
+SCSI_Parity_Error_sts_sts_reg__STATUS_CNT_REG EQU CYREG_B0_UDB11_ST_CTL\r
+SCSI_Parity_Error_sts_sts_reg__STATUS_CONTROL_REG EQU CYREG_B0_UDB11_ST_CTL\r
SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB11_ST\r
\r
; Miscellaneous\r
BCLK__BUS_CLK__HZ EQU 50000000\r
BCLK__BUS_CLK__KHZ EQU 50000\r
BCLK__BUS_CLK__MHZ EQU 50\r
+CYDEV_CHIP_DIE_GEN4 EQU 2\r
CYDEV_CHIP_DIE_LEOPARD EQU 1\r
-CYDEV_CHIP_DIE_PANTHER EQU 6\r
-CYDEV_CHIP_DIE_PSOC4A EQU 3\r
-CYDEV_CHIP_DIE_PSOC5LP EQU 5\r
+CYDEV_CHIP_DIE_PANTHER EQU 12\r
+CYDEV_CHIP_DIE_PSOC4A EQU 5\r
+CYDEV_CHIP_DIE_PSOC5LP EQU 11\r
CYDEV_CHIP_DIE_UNKNOWN EQU 0\r
CYDEV_CHIP_FAMILY_PSOC3 EQU 1\r
CYDEV_CHIP_FAMILY_PSOC4 EQU 2\r
CYDEV_CHIP_FAMILY_USED EQU CYDEV_CHIP_FAMILY_PSOC5\r
CYDEV_CHIP_JTAG_ID EQU 0x2E133069\r
CYDEV_CHIP_MEMBER_3A EQU 1\r
-CYDEV_CHIP_MEMBER_4A EQU 3\r
-CYDEV_CHIP_MEMBER_4D EQU 2\r
-CYDEV_CHIP_MEMBER_4F EQU 4\r
-CYDEV_CHIP_MEMBER_5A EQU 6\r
-CYDEV_CHIP_MEMBER_5B EQU 5\r
+CYDEV_CHIP_MEMBER_4A EQU 5\r
+CYDEV_CHIP_MEMBER_4C EQU 9\r
+CYDEV_CHIP_MEMBER_4D EQU 3\r
+CYDEV_CHIP_MEMBER_4E EQU 4\r
+CYDEV_CHIP_MEMBER_4F EQU 6\r
+CYDEV_CHIP_MEMBER_4G EQU 2\r
+CYDEV_CHIP_MEMBER_4L EQU 8\r
+CYDEV_CHIP_MEMBER_4M EQU 7\r
+CYDEV_CHIP_MEMBER_5A EQU 11\r
+CYDEV_CHIP_MEMBER_5B EQU 10\r
CYDEV_CHIP_MEMBER_UNKNOWN EQU 0\r
CYDEV_CHIP_MEMBER_USED EQU CYDEV_CHIP_MEMBER_5B\r
CYDEV_CHIP_DIE_EXPECT EQU CYDEV_CHIP_MEMBER_USED\r
CYDEV_CHIP_DIE_ACTUAL EQU CYDEV_CHIP_DIE_EXPECT\r
+CYDEV_CHIP_REV_GEN4_ES EQU 17\r
+CYDEV_CHIP_REV_GEN4_ES2 EQU 33\r
+CYDEV_CHIP_REV_GEN4_PRODUCTION EQU 17\r
CYDEV_CHIP_REV_LEOPARD_ES1 EQU 0\r
CYDEV_CHIP_REV_LEOPARD_ES2 EQU 1\r
CYDEV_CHIP_REV_LEOPARD_ES3 EQU 3\r
CYDEV_CHIP_REVISION_3A_PRODUCTION EQU 3\r
CYDEV_CHIP_REVISION_4A_ES0 EQU 17\r
CYDEV_CHIP_REVISION_4A_PRODUCTION EQU 17\r
+CYDEV_CHIP_REVISION_4C_PRODUCTION EQU 0\r
CYDEV_CHIP_REVISION_4D_PRODUCTION EQU 0\r
+CYDEV_CHIP_REVISION_4E_PRODUCTION EQU 0\r
CYDEV_CHIP_REVISION_4F_PRODUCTION EQU 0\r
+CYDEV_CHIP_REVISION_4F_PRODUCTION_256K EQU 0\r
+CYDEV_CHIP_REVISION_4G_ES EQU 17\r
+CYDEV_CHIP_REVISION_4G_ES2 EQU 33\r
+CYDEV_CHIP_REVISION_4G_PRODUCTION EQU 17\r
+CYDEV_CHIP_REVISION_4L_PRODUCTION EQU 0\r
+CYDEV_CHIP_REVISION_4M_PRODUCTION EQU 0\r
CYDEV_CHIP_REVISION_5A_ES0 EQU 0\r
CYDEV_CHIP_REVISION_5A_ES1 EQU 1\r
CYDEV_CHIP_REVISION_5A_PRODUCTION EQU 1\r
CYDEV_CONFIGURATION_MODE_UNCOMPRESSED EQU 1\r
CYDEV_DEBUG_ENABLE_MASK EQU 0x20\r
CYDEV_DEBUG_ENABLE_REGISTER EQU CYREG_MLOGIC_DEBUG\r
-CYDEV_DEBUGGING_DPS_Disable EQU 3\r
-CYDEV_DEBUGGING_DPS_JTAG_4 EQU 1\r
-CYDEV_DEBUGGING_DPS_JTAG_5 EQU 0\r
CYDEV_DEBUGGING_DPS_SWD EQU 2\r
CYDEV_DEBUGGING_DPS_SWD_SWV EQU 6\r
CYDEV_DEBUGGING_DPS EQU CYDEV_DEBUGGING_DPS_SWD_SWV\r
CYDEV_INTR_RISING EQU 0x0000007E\r
CYDEV_PROJ_TYPE EQU 2\r
CYDEV_PROJ_TYPE_BOOTLOADER EQU 1\r
+CYDEV_PROJ_TYPE_LAUNCHER EQU 5\r
CYDEV_PROJ_TYPE_LOADABLE EQU 2\r
+CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER EQU 4\r
CYDEV_PROJ_TYPE_MULTIAPPBOOTLOADER EQU 3\r
CYDEV_PROJ_TYPE_STANDARD EQU 0\r
CYDEV_PROTECTION_ENABLE EQU 0\r
/*******************************************************************************\r
* FILENAME: cymetadata.c\r
* \r
-* PSoC Creator 3.1\r
+* PSoC Creator 3.2\r
*\r
* DESCRIPTION:\r
* This file defines all extra memory spaces that need to be included.\r
* This file is automatically generated by PSoC Creator.\r
*\r
********************************************************************************\r
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright (c) 2007-2015 Cypress Semiconductor. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions, \r
* disclaimers, and limitations in the end user license agreement accompanying \r
* the software package with which this file was provided.\r
const uint8 cy_meta_loadable[] = {\r
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,\r
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,\r
- 0x00u, 0x00u, 0x00u, 0x00u, 0x5Cu, 0xD1u, 0x30u, 0x04u,\r
+ 0x00u, 0x00u, 0x00u, 0x00u, 0x5Cu, 0xD1u, 0x40u, 0x04u,\r
0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,\r
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,\r
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,\r
/*******************************************************************************\r
- * File Name: project.h\r
- * PSoC Creator 3.1\r
- *\r
- * Description:\r
- * This file is automatically generated by PSoC Creator and should not \r
- * be edited by hand.\r
- *\r
- *\r
- ********************************************************************************\r
- * Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.\r
- * You may use this file only in accordance with the license, terms, conditions, \r
- * disclaimers, and limitations in the end user license agreement accompanying \r
- * the software package with which this file was provided.\r
- ********************************************************************************/\r
+* FILENAME: project.h\r
+* \r
+* PSoC Creator 3.2\r
+*\r
+* DESCRIPTION:\r
+* It contains references to all generated header files and should not be modified.\r
+* This file is automatically generated by PSoC Creator.\r
+*\r
+********************************************************************************\r
+* Copyright (c) 2007-2015 Cypress Semiconductor. All rights reserved.\r
+* You may use this file only in accordance with the license, terms, conditions, \r
+* disclaimers, and limitations in the end user license agreement accompanying \r
+* the software package with which this file was provided.\r
+********************************************************************************/\r
\r
-#include <cyfitter_cfg.h>\r
-#include <cydevice.h>\r
-#include <cydevice_trm.h>\r
-#include <cyfitter.h>\r
-#include <cydisabledsheets.h>\r
-#include <SCSI_In_DBx_aliases.h>\r
-#include <SCSI_Out_DBx_aliases.h>\r
-#include <SD_Data_Clk.h>\r
-#include <SD_CD_aliases.h>\r
-#include <SD_CD.h>\r
-#include <SD_DAT2_aliases.h>\r
-#include <SD_DAT2.h>\r
-#include <SD_DAT1_aliases.h>\r
-#include <SD_DAT1.h>\r
-#include <SCSI_CTL_PHASE.h>\r
-#include <SCSI_In_aliases.h>\r
-#include <SCSI_Out_aliases.h>\r
-#include <CFG_EEPROM.h>\r
-#include <SD_CS_aliases.h>\r
-#include <SD_CS.h>\r
-#include <SD_SCK_aliases.h>\r
-#include <SD_SCK.h>\r
-#include <SD_MOSI_aliases.h>\r
-#include <SD_MOSI.h>\r
-#include <SCSI_CLK.h>\r
-#include <SCSI_Noise_aliases.h>\r
-#include <SCSI_RST_ISR.h>\r
-#include <LED1_aliases.h>\r
-#include <LED1.h>\r
-#include <SDCard.h>\r
-#include <SDCard_PVT.h>\r
-#include <SD_MISO_aliases.h>\r
-#include <SD_MISO.h>\r
-#include <USBFS.h>\r
-#include <USBFS_audio.h>\r
-#include <USBFS_cdc.h>\r
-#include <USBFS_hid.h>\r
-#include <USBFS_midi.h>\r
-#include <USBFS_pvt.h>\r
-#include <Bootloadable_1.h>\r
-#include <SCSI_Out_Bits.h>\r
-#include <SCSI_Out_Ctl.h>\r
-#include <Debug_Timer.h>\r
-#include <timer_clock.h>\r
-#include <Debug_Timer_Interrupt.h>\r
-#include <SCSI_TX_DMA_dma.h>\r
-#include <SCSI_TX_DMA_COMPLETE.h>\r
-#include <SD_RX_DMA_dma.h>\r
-#include <SD_TX_DMA_dma.h>\r
-#include <SD_RX_DMA_COMPLETE.h>\r
-#include <SD_TX_DMA_COMPLETE.h>\r
-#include <SCSI_RX_DMA_dma.h>\r
-#include <SCSI_RX_DMA_COMPLETE.h>\r
-#include <SCSI_Parity_Error.h>\r
-#include <SCSI_Filtered.h>\r
-#include <SCSI_SEL_ISR.h>\r
-#include <SCSI_Glitch_Ctl.h>\r
-#include <USBFS_Dm_aliases.h>\r
-#include <USBFS_Dm.h>\r
-#include <USBFS_Dp_aliases.h>\r
-#include <USBFS_Dp.h>\r
-#include <core_cm3_psoc5.h>\r
-#include <core_cm3.h>\r
-#include <CyDmac.h>\r
-#include <CyFlash.h>\r
-#include <CyLib.h>\r
-#include <cypins.h>\r
-#include <cyPm.h>\r
-#include <CySpc.h>\r
-#include <cytypes.h>\r
-#include <core_cmFunc.h>\r
-#include <core_cmInstr.h>\r
+#include "cyfitter_cfg.h"\r
+#include "cydevice.h"\r
+#include "cydevice_trm.h"\r
+#include "cyfitter.h"\r
+#include "cydisabledsheets.h"\r
+#include "SCSI_In_DBx_aliases.h"\r
+#include "SCSI_Out_DBx_aliases.h"\r
+#include "SD_Data_Clk.h"\r
+#include "SD_CD_aliases.h"\r
+#include "SD_CD.h"\r
+#include "SD_DAT2_aliases.h"\r
+#include "SD_DAT2.h"\r
+#include "SD_DAT1_aliases.h"\r
+#include "SD_DAT1.h"\r
+#include "SCSI_CTL_PHASE.h"\r
+#include "SCSI_In_aliases.h"\r
+#include "SCSI_Out_aliases.h"\r
+#include "CFG_EEPROM.h"\r
+#include "SD_CS_aliases.h"\r
+#include "SD_CS.h"\r
+#include "SD_SCK_aliases.h"\r
+#include "SD_SCK.h"\r
+#include "SD_MOSI_aliases.h"\r
+#include "SD_MOSI.h"\r
+#include "SCSI_CLK.h"\r
+#include "SCSI_Noise_aliases.h"\r
+#include "SCSI_RST_ISR.h"\r
+#include "LED1_aliases.h"\r
+#include "LED1.h"\r
+#include "SDCard.h"\r
+#include "SDCard_PVT.h"\r
+#include "SD_MISO_aliases.h"\r
+#include "SD_MISO.h"\r
+#include "USBFS.h"\r
+#include "USBFS_audio.h"\r
+#include "USBFS_cdc.h"\r
+#include "USBFS_hid.h"\r
+#include "USBFS_midi.h"\r
+#include "USBFS_pvt.h"\r
+#include "Bootloadable_1.h"\r
+#include "SCSI_Out_Bits.h"\r
+#include "SCSI_Out_Ctl.h"\r
+#include "Debug_Timer.h"\r
+#include "timer_clock.h"\r
+#include "Debug_Timer_Interrupt.h"\r
+#include "SCSI_TX_DMA_dma.h"\r
+#include "SCSI_TX_DMA_COMPLETE.h"\r
+#include "SD_RX_DMA_dma.h"\r
+#include "SD_TX_DMA_dma.h"\r
+#include "SD_RX_DMA_COMPLETE.h"\r
+#include "SD_TX_DMA_COMPLETE.h"\r
+#include "SCSI_RX_DMA_dma.h"\r
+#include "SCSI_RX_DMA_COMPLETE.h"\r
+#include "SCSI_Parity_Error.h"\r
+#include "SCSI_Filtered.h"\r
+#include "SCSI_SEL_ISR.h"\r
+#include "SCSI_Glitch_Ctl.h"\r
+#include "USBFS_Dm_aliases.h"\r
+#include "USBFS_Dm.h"\r
+#include "USBFS_Dp_aliases.h"\r
+#include "USBFS_Dp.h"\r
+#include "core_cm3_psoc5.h"\r
+#include "core_cm3.h"\r
+#include "CyDmac.h"\r
+#include "CyFlash.h"\r
+#include "CyLib.h"\r
+#include "cypins.h"\r
+#include "cyPm.h"\r
+#include "CySpc.h"\r
+#include "cytypes.h"\r
+#include "core_cmFunc.h"\r
+#include "core_cmInstr.h"\r
\r
/*[]*/\r
\r
<block name="SCSI_TX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="SCSI_TX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="Debug_Timer_Interrupt" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="Clock_4" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="cydff_2" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="SCSI_SEL_ISR" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="SCSI_Glitch_Ctl" BASE="0x0" SIZE="0x0" desc="" visible="true">\r
- <register name="SCSI_Glitch_Ctl_CONTROL_REG" address="0x4000647A" bitWidth="8" desc="" />\r
- </block>\r
- <block name="mux_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="not_2" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="Clock_3" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="Clock_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="GlitchFilter_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="SCSI_Filtered" BASE="0x0" SIZE="0x0" desc="" visible="true">\r
- <register name="SCSI_Filtered_STATUS_REG" address="0x40006467" bitWidth="8" desc="" />\r
- <register name="SCSI_Filtered_MASK_REG" address="0x40006487" bitWidth="8" desc="" />\r
- <register name="SCSI_Filtered_STATUS_AUX_CTL_REG" address="0x40006497" bitWidth="8" desc="">\r
+ <register name="SCSI_Filtered_STATUS_REG" address="0x4000646A" bitWidth="8" desc="" />\r
+ <register name="SCSI_Filtered_MASK_REG" address="0x4000648A" bitWidth="8" desc="" />\r
+ <register name="SCSI_Filtered_STATUS_AUX_CTL_REG" address="0x4000649A" bitWidth="8" desc="">\r
<field name="FIFO0" from="5" to="5" access="RW" resetVal="" desc="FIFO0 clear">\r
<value name="ENABLED" value="1" desc="Enable counter" />\r
<value name="DISABLED" value="0" desc="Disable counter" />\r
</field>\r
</register>\r
</block>\r
+ <block name="not_2" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="Clock_4" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="cydff_2" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="cy_boot" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="SCSI_Glitch_Ctl" BASE="0x0" SIZE="0x0" desc="" visible="true">\r
+ <register name="SCSI_Glitch_Ctl_CONTROL_REG" address="0x40006474" bitWidth="8" desc="" />\r
+ </block>\r
+ <block name="mux_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="SCSI_SEL_ISR" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="Clock_2" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="Clock_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="GlitchFilter_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="Clock_3" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="cydff_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="cy_constant_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="Clock_2" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="SCSI_Out_Ctl" BASE="0x0" SIZE="0x0" desc="" visible="true">\r
- <register name="SCSI_Out_Ctl_CONTROL_REG" address="0x4000647C" bitWidth="8" desc="" />\r
- </block>\r
<block name="SCSI_Out" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="SCSI_In" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="OddParityGen_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="SD_CS" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="CFG_EEPROM" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="SCSI_CTL_PHASE" BASE="0x0" SIZE="0x0" desc="" visible="true">\r
- <register name="SCSI_CTL_PHASE_CONTROL_REG" address="0x40006471" bitWidth="8" desc="" />\r
+ <register name="SCSI_CTL_PHASE_CONTROL_REG" address="0x40006472" bitWidth="8" desc="" />\r
</block>\r
<block name="SD_Data_Clk" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="SCSI_Out_DBx" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="SD_DAT1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="SD_DAT2" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="SD_CD" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="SD_MOSI" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="Bootloadable_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="USBFS" BASE="0x0" SIZE="0x0" desc="USBFS" visible="true">\r
<block name="ZeroTerminal_5" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="VirtualMux_6" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<register name="USBFS_USB_CLK_EN" address="0x4000609D" bitWidth="8" desc="USB Block Clock Enable Register" />\r
</block>\r
<block name="SD_MISO" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="SCSI_Out_Ctl" BASE="0x0" SIZE="0x0" desc="" visible="true">\r
+ <register name="SCSI_Out_Ctl_CONTROL_REG" address="0x4000647F" bitWidth="8" desc="" />\r
+ </block>\r
+ <block name="SCSI_Out_Bits" BASE="0x0" SIZE="0x0" desc="" visible="true">\r
+ <register name="SCSI_Out_Bits_CONTROL_REG" address="0x4000647B" bitWidth="8" desc="" />\r
+ </block>\r
+ <block name="SCSI_Out_Mux" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="SDCard" BASE="0x0" SIZE="0x0" desc="" visible="true">\r
<block name="VirtualMux_3" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="VirtualMux_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="BSPIM" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
</block>\r
- <block name="SCSI_Out_Bits" BASE="0x0" SIZE="0x0" desc="" visible="true">\r
- <register name="SCSI_Out_Bits_CONTROL_REG" address="0x4000657B" bitWidth="8" desc="" />\r
- </block>\r
- <block name="SCSI_Out_Mux" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="Bootloadable_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="LED1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="SCSI_Noise" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="not_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="SCSI_CLK" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="SD_MOSI" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="LED1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="scsiTarget" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="SCSI_RST_ISR" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="SCSI_Noise" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
</blockRegMap>
\ No newline at end of file
</register>\r
</registers>\r
</peripheral>\r
- <peripheral>\r
- <name>SCSI_Glitch_Ctl</name>\r
- <description>No description available</description>\r
- <baseAddress>0x4000647A</baseAddress>\r
- <addressBlock>\r
- <offset>0</offset>\r
- <size>0x0</size>\r
- <usage>registers</usage>\r
- </addressBlock>\r
- <registers>\r
- <register>\r
- <name>SCSI_Glitch_Ctl_CONTROL_REG</name>\r
- <description>No description available</description>\r
- <addressOffset>0x0</addressOffset>\r
- <size>8</size>\r
- <access>read-write</access>\r
- <resetValue>0</resetValue>\r
- <resetMask>0</resetMask>\r
- </register>\r
- </registers>\r
- </peripheral>\r
<peripheral>\r
<name>SCSI_Filtered</name>\r
<description>No description available</description>\r
- <baseAddress>0x40006467</baseAddress>\r
+ <baseAddress>0x4000646A</baseAddress>\r
<addressBlock>\r
<offset>0</offset>\r
<size>0x0</size>\r
</registers>\r
</peripheral>\r
<peripheral>\r
- <name>SCSI_Out_Ctl</name>\r
+ <name>SCSI_Glitch_Ctl</name>\r
<description>No description available</description>\r
- <baseAddress>0x4000647C</baseAddress>\r
+ <baseAddress>0x40006474</baseAddress>\r
<addressBlock>\r
<offset>0</offset>\r
<size>0x0</size>\r
</addressBlock>\r
<registers>\r
<register>\r
- <name>SCSI_Out_Ctl_CONTROL_REG</name>\r
+ <name>SCSI_Glitch_Ctl_CONTROL_REG</name>\r
<description>No description available</description>\r
<addressOffset>0x0</addressOffset>\r
<size>8</size>\r
<peripheral>\r
<name>SCSI_CTL_PHASE</name>\r
<description>No description available</description>\r
- <baseAddress>0x40006471</baseAddress>\r
+ <baseAddress>0x40006472</baseAddress>\r
<addressBlock>\r
<offset>0</offset>\r
<size>0x0</size>\r
</register>\r
</registers>\r
</peripheral>\r
+ <peripheral>\r
+ <name>SCSI_Out_Ctl</name>\r
+ <description>No description available</description>\r
+ <baseAddress>0x4000647F</baseAddress>\r
+ <addressBlock>\r
+ <offset>0</offset>\r
+ <size>0x0</size>\r
+ <usage>registers</usage>\r
+ </addressBlock>\r
+ <registers>\r
+ <register>\r
+ <name>SCSI_Out_Ctl_CONTROL_REG</name>\r
+ <description>No description available</description>\r
+ <addressOffset>0x0</addressOffset>\r
+ <size>8</size>\r
+ <access>read-write</access>\r
+ <resetValue>0</resetValue>\r
+ <resetMask>0</resetMask>\r
+ </register>\r
+ </registers>\r
+ </peripheral>\r
<peripheral>\r
<name>SCSI_Out_Bits</name>\r
<description>No description available</description>\r
- <baseAddress>0x4000657B</baseAddress>\r
+ <baseAddress>0x4000647B</baseAddress>\r
<addressBlock>\r
<offset>0</offset>\r
<size>0x0</size>\r
/*******************************************************************************
* File Name: CFG_EEPROM.c
-* Version 2.10
+* Version 3.0
*
-* Description:
-* Provides the source code to the API for the EEPROM component.
+* Description:
+* Provides the source code to the API for the EEPROM component.
*
********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
#include "CFG_EEPROM.h"
-#if (CY_PSOC3 || CY_PSOC5LP)
-
- /*******************************************************************************
- * Function Name: CFG_EEPROM_Enable
- ********************************************************************************
- *
- * Summary:
- * Enable the EEPROM.
- *
- * Parameters:
- * None
- *
- * Return:
- * None
- *
- *******************************************************************************/
- void CFG_EEPROM_Enable(void)
- {
- CyEEPROM_Start();
- }
+/*******************************************************************************
+* Function Name: CFG_EEPROM_Enable
+********************************************************************************
+*
+* Summary:
+* Enable the EEPROM block. Also reads the temperature and stores it for
+* future writes.
+*
+* Parameters:
+* None
+*
+* Return:
+* None
+*
+*******************************************************************************/
+void CFG_EEPROM_Enable(void)
+{
+ /* Read temperature value */
+ (void)CySetTemp();
+ /* Start EEPROM block */
+ CyEEPROM_Start();
+}
- /*******************************************************************************
- * Function Name: CFG_EEPROM_Start
- ********************************************************************************
- *
- * Summary:
- * Starts EEPROM.
- *
- * Parameters:
- * None
- *
- * Return:
- * None
- *
- *******************************************************************************/
- void CFG_EEPROM_Start(void)
- {
- /* Enable the EEPROM */
- CFG_EEPROM_Enable();
- }
+/*******************************************************************************
+* Function Name: CFG_EEPROM_Start
+********************************************************************************
+*
+* Summary:
+* Starts EEPROM.
+*
+* Parameters:
+* None
+*
+* Return:
+* None
+*
+*******************************************************************************/
+void CFG_EEPROM_Start(void)
+{
+ CFG_EEPROM_Enable();
+}
- /*******************************************************************************
- * Function Name: CFG_EEPROM_Stop
- ********************************************************************************
- *
- * Summary:
- * Stops and powers down EEPROM.
- *
- * Parameters:
- * None
- *
- * Return:
- * None
- *
- *******************************************************************************/
- void CFG_EEPROM_Stop (void)
- {
- /* Disable EEPROM */
- CyEEPROM_Stop();
- }
-#endif /* (CY_PSOC3 || CY_PSOC5LP) */
+/*******************************************************************************
+* Function Name: CFG_EEPROM_Stop
+********************************************************************************
+*
+* Summary:
+* Stops and powers down EEPROM.
+*
+* Parameters:
+* None
+*
+* Return:
+* None
+*
+*******************************************************************************/
+void CFG_EEPROM_Stop (void)
+{
+ /* Stop and power down EEPROM block */
+ CyEEPROM_Stop();
+}
/*******************************************************************************
-* Function Name: CFG_EEPROM_EraseSector
+* Function Name: CFG_EEPROM_WriteByte
********************************************************************************
*
* Summary:
-* Erases a sector of memory. This function blocks until the operation is
-* complete.
+* Writes a byte of data to the EEPROM. This function blocks until
+* the function is complete. For a reliable write procedure to occur you should
+* call CFG_EEPROM_UpdateTemperature() function if the temperature of the
+* silicon has been changed for more than 10C since the component was started.
*
* Parameters:
-* sectorNumber: Sector number to erase.
+* dataByte: The byte of data to write to the EEPROM
+* address: The address of data to be written. The maximum address is dependent
+* on the EEPROM size.
*
* Return:
* CYRET_SUCCESS, if the operation was successful.
-* CYRET_BAD_PARAM, if the parameter sectorNumber out of range.
-* CYRET_LOCKED, if the spc is being used.
+* CYRET_BAD_PARAM, if the parameter sectorNumber is out of range.
+* CYRET_LOCKED, if the SPC is being used.
* CYRET_UNKNOWN, if there was an SPC error.
*
*******************************************************************************/
-cystatus CFG_EEPROM_EraseSector(uint8 sectorNumber)
+cystatus CFG_EEPROM_WriteByte(uint8 dataByte, uint16 address)
{
cystatus status;
-
- /* Start the SPC */
+ uint16 rowNumber;
+ uint16 byteNumber;
+
CySpcStart();
- if(sectorNumber < (uint8) CY_EEPROM_NUMBER_ARRAYS)
+ if (address < CY_EEPROM_SIZE)
{
- /* See if we can get the SPC. */
- if(CySpcLock() == CYRET_SUCCESS)
+ rowNumber = address/(uint16)CY_EEPROM_SIZEOF_ROW;
+ byteNumber = address - (rowNumber * ((uint16)CY_EEPROM_SIZEOF_ROW));
+ if(CYRET_SUCCESS == CySpcLock())
{
- #if(CY_PSOC5A)
-
+ status = CySpcLoadMultiByte(CY_SPC_FIRST_EE_ARRAYID, byteNumber, &dataByte, \
+ CFG_EEPROM_SPC_BYTE_WRITE_SIZE);
+ if (CYRET_STARTED == status)
+ {
/* Plan for failure */
status = CYRET_UNKNOWN;
- /* Command to load a row of data */
- if(CySpcLoadRow(CY_SPC_FIRST_EE_ARRAYID, 0, CYDEV_EEPROM_ROW_SIZE) == CYRET_STARTED)
+ while(CY_SPC_BUSY)
{
- while(CY_SPC_BUSY)
- {
- /* Wait until SPC becomes idle */
- }
-
- /* SPC is idle now */
- if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS)
- {
- status = CYRET_SUCCESS;
- }
+ /* Wait until SPC becomes idle */
}
- /* Command to erase a sector */
- if(status == CYRET_SUCCESS)
+ if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS)
{
-
- #endif /* (CY_PSOC5A) */
-
- if(CySpcEraseSector(CY_SPC_FIRST_EE_ARRAYID, sectorNumber) == CYRET_STARTED)
+ status = CYRET_SUCCESS;
+ }
+ /* Command to erase and program the row. */
+ if(CYRET_SUCCESS == status)
+ {
+ if(CySpcWriteRow(CY_SPC_FIRST_EE_ARRAYID, (uint16)rowNumber, dieTemperature[0u],
+ dieTemperature[1u]) == CYRET_STARTED)
{
/* Plan for failure */
status = CYRET_UNKNOWN;
{
status = CYRET_UNKNOWN;
}
-
- #if(CY_PSOC5A)
-
}
else
{
status = CYRET_UNKNOWN;
}
+ }
+ else
+ {
+ if (CYRET_BAD_PARAM != status)
+ {
+ status = CYRET_UNKNOWN;
+ }
+ }
+ CySpcUnlock();
+ }
+ else
+ {
+ status = CYRET_LOCKED;
+ }
+ }
+ else
+ {
+ status = CYRET_BAD_PARAM;
+ }
+
+
+ return (status);
+}
+
+
+/*******************************************************************************
+* Function Name: CFG_EEPROM_ReadByte
+********************************************************************************
+*
+* Summary:
+* Reads and returns a byte of data from the on-chip EEPROM memory. Although
+* the data is present in the CPU memory space, this function provides an
+* intuitive user interface, addressing the EEPROM memory as a separate block with
+* the first EERPOM byte address equal to 0x0000.
+*
+* Parameters:
+* address: The address of data to be read. The maximum address is limited by the
+* size of the EEPROM array on a specific device.
+*
+* Return:
+* Data located at an address.
+*
+*******************************************************************************/
+uint8 CFG_EEPROM_ReadByte(uint16 address)
+{
+ uint8 retByte;
+ uint8 interruptState;
+
+ interruptState = CyEnterCriticalSection();
+
+ /* Request access to EEPROM for reading.
+ This is needed to reserve PHUB for read operation from EEPROM */
+ CyEEPROM_ReadReserve();
+
+ retByte = *((reg8 *) (CYDEV_EE_BASE + address));
+
+ /* Release EEPROM array */
+ CyEEPROM_ReadRelease();
+
+ CyExitCriticalSection(interruptState);
+
+ return (retByte);
+}
+
+
+/*******************************************************************************
+* Function Name: CFG_EEPROM_UpdateTemperature
+********************************************************************************
+*
+* Summary:
+* Updates and stores the temperature value. This function should be called
+* before EEPROM writes if the temperature may have been changed by more than
+* 10 degrees Celsius.
+*
+* Parameters:
+* None
+*
+* Return:
+* Status of operation, 0 if operation complete, non-zero value if error
+* was detected.
+*
+*******************************************************************************/
+uint8 CFG_EEPROM_UpdateTemperature(void)
+{
+ return ((uint8)CySetTemp());
+}
+
+
+/*******************************************************************************
+* Function Name: CFG_EEPROM_EraseSector
+********************************************************************************
+*
+* Summary:
+* Erase an EEPROM sector (64 rows). This function blocks until the erase
+* operation is complete. Using this API helps to erase the EEPROM sector at
+* a time. This is faster than using individual writes but affects a cycle
+* recourse of the whole EEPROM row.
+*
+* Parameters:
+* sectorNumber: The sector number to erase.
+*
+* Return:
+* CYRET_SUCCESS, if the operation was successful.
+* CYRET_BAD_PARAM, if the parameter sectorNumber is out of range.
+* CYRET_LOCKED, if the SPC is being used.
+* CYRET_UNKNOWN, if there was an SPC error.
+*
+*******************************************************************************/
+cystatus CFG_EEPROM_EraseSector(uint8 sectorNumber)
+{
+ cystatus status;
+
+ CySpcStart();
+
+ if(sectorNumber < (uint8) CFG_EEPROM_SECTORS_NUMBER)
+ {
+ /* See if we can get SPC. */
+ if(CySpcLock() == CYRET_SUCCESS)
+ {
+ if(CySpcEraseSector(CY_SPC_FIRST_EE_ARRAYID, sectorNumber) == CYRET_STARTED)
+ {
+ /* Plan for failure */
+ status = CYRET_UNKNOWN;
+
+ while(CY_SPC_BUSY)
+ {
+ /* Wait until SPC becomes idle */
+ }
- #endif /* (CY_PSOC5A) */
+ /* SPC is idle now */
+ if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS)
+ {
+ status = CYRET_SUCCESS;
+ }
+ }
+ else
+ {
+ status = CYRET_UNKNOWN;
+ }
- /* Unlock the SPC so someone else can use it. */
- CySpcUnlock();
+ /* Unlock SPC so that someone else can use it. */
+ CySpcUnlock();
}
else
{
********************************************************************************
*
* Summary:
-* Writes a row, CYDEV_EEPROM_ROW_SIZE of data to the EEPROM. This is
-* a blocking call. It will not return until the function succeeds or fails.
+* Writes a row (16 bytes) of data to the EEPROM. This function blocks until
+* the write operation is complete. Compared to functions that write one byte,
+* this function allows writing a whole row (16 bytes) at a time. For
+* a reliable write procedure to occur you should call the
+* CFG_EEPROM_UpdateTemperature() function if the temperature of the
+* silicon has changed for more than 10C since component was started.
*
* Parameters:
-* rowData: Address of the data to write to the EEPROM.
-* rowNumber: EEPROM row number to program.
+* rowData: The address of the data to write to the EEPROM.
+* rowNumber: The row number to write.
*
* Return:
* CYRET_SUCCESS, if the operation was successful.
-* CYRET_BAD_PARAM, if the parameter rowNumber out of range.
-* CYRET_LOCKED, if the spc is being used.
+* CYRET_BAD_PARAM, if the parameter rowNumber is out of range.
+* CYRET_LOCKED, if the SPC is being used.
* CYRET_UNKNOWN, if there was an SPC error.
*
*******************************************************************************/
cystatus CFG_EEPROM_Write(const uint8 * rowData, uint8 rowNumber)
{
cystatus status;
-
- /* Start the SPC */
+
CySpcStart();
if(rowNumber < (uint8) CY_EEPROM_NUMBER_ROWS)
{
- /* See if we can get the SPC. */
+ /* See if we can get SPC. */
if(CySpcLock() == CYRET_SUCCESS)
{
/* Plan for failure */
/* Command to erase and program the row. */
if(status == CYRET_SUCCESS)
{
- if(CySpcWriteRow(CY_SPC_FIRST_EE_ARRAYID, (uint16)rowNumber, dieTemperature[0],
- dieTemperature[1]) == CYRET_STARTED)
+ if(CySpcWriteRow(CY_SPC_FIRST_EE_ARRAYID, (uint16)rowNumber, dieTemperature[0u],
+ dieTemperature[1u]) == CYRET_STARTED)
{
/* Plan for failure */
status = CYRET_UNKNOWN;
}
}
- /* Unlock the SPC so someone else can use it. */
+ /* Unlock SPC so that someone else can use it. */
CySpcUnlock();
}
else
********************************************************************************
*
* Summary:
-* Starts the SPC write function. This function does not block, it returns
-* once the command has begun the SPC write function. This function must be used
-* in combination with CFG_EEPROM_QueryWrite(). Once this function has
-* been called the SPC will be locked until CFG_EEPROM_QueryWrite()
-* returns CYRET_SUCCESS.
+* Starts a write of a row (16 bytes) of data to the EEPROM.
+* This function does not block. The function returns once the SPC has begun
+* writing the data. This function must be used in combination with
+* CFG_EEPROM_Query(). CFG_EEPROM_Query() must be called
+* until it returns a status other than CYRET_STARTED. That indicates that the
+* write has completed. Until CFG_EEPROM_Query() detects that
+* the write is complete, the SPC is marked as locked to prevent another
+* SPC operation from being performed. For a reliable write procedure to occur
+* you should call CFG_EEPROM_UpdateTemperature() API if the temperature
+* of the silicon has changed for more than 10C since component was started.
*
* Parameters:
-* rowData: Address of buffer containing a row of data to write to the EEPROM.
-* rowNumber: EEPROM row number to program.
+* rowData: The address of the data to write to the EEPROM.
+* rowNumber: The row number to write.
*
* Return:
-* CYRET_STARTED, if the spc command to write was successfuly started.
-* CYRET_BAD_PARAM, if the parameter rowNumber out of range.
-* CYRET_LOCKED, if the spc is being used.
+* CYRET_STARTED, if the SPC command to write was successfully started.
+* CYRET_BAD_PARAM, if the parameter rowNumber is out of range.
+* CYRET_LOCKED, if the SPC is being used.
* CYRET_UNKNOWN, if there was an SPC error.
*
+* Side effects:
+* After calling this API, the device should not be powered down, reset or switched
+* to low power modes until EEPROM operation is complete.
+* Ignoring this recommendation may lead to data corruption or silicon
+* unexpected behavior.
+*
*******************************************************************************/
cystatus CFG_EEPROM_StartWrite(const uint8 * rowData, uint8 rowNumber) \
{
cystatus status;
+
+ CySpcStart();
if(rowNumber < (uint8) CY_EEPROM_NUMBER_ROWS)
{
- /* See if we can get the SPC. */
+ /* See if we can get SPC. */
if(CySpcLock() == CYRET_SUCCESS)
{
/* Plan for failure */
/* Command to erase and program the row. */
if(status == CYRET_SUCCESS)
{
- if(CySpcWriteRow(CY_SPC_FIRST_EE_ARRAYID, (uint16)rowNumber, dieTemperature[0],
- dieTemperature[1]) == CYRET_STARTED)
+ if(CySpcWriteRow(CY_SPC_FIRST_EE_ARRAYID, (uint16)rowNumber, dieTemperature[0u],
+ dieTemperature[1u]) == CYRET_STARTED)
{
status = CYRET_STARTED;
}
/*******************************************************************************
-* Function Name: CFG_EEPROM_QueryWrite
+* Function Name: CFG_EEPROM_StartErase
********************************************************************************
*
* Summary:
-* Checks the state of write to EEPROM. This function must be called until
-* the return value is not CYRET_STARTED.
+* Starts the EEPROM sector erase. This function does not block.
+* The function returns once the SPC has begun writing the data. This function
+* must be used in combination with CFG_EEPROM_Query().
+* CFG_EEPROM_Query() must be called until it returns a status
+* other than CYRET_STARTED. That indicates the erase has been completed.
+* Until CFG_EEPROM_Query() detects that the erase is
+* complete, the SPC is marked as locked to prevent another SPC operation
+* from being performed.
+*
+* Parameters:
+* sectorNumber: The sector number to erase.
+*
+* Return:
+* CYRET_STARTED, if the SPC command to erase was successfully started.
+* CYRET_BAD_PARAM, if the parameter sectorNumber is out of range.
+* CYRET_LOCKED, if the SPC is being used.
+* CYRET_UNKNOWN, if there was an SPC error.
+*
+* Side effects:
+* After calling this API, the device should not be powered down, reset or switched
+* to low power modes until EEPROM operation is complete.
+* Ignoring this recommendation may lead to data corruption or silicon
+* unexpected behavior.
+*
+*******************************************************************************/
+cystatus CFG_EEPROM_StartErase(uint8 sectorNumber)
+{
+ cystatus status;
+
+ CySpcStart();
+
+ if(sectorNumber < (uint8) CY_EEPROM_NUMBER_ARRAYS)
+ {
+ /* See if we can get SPC. */
+ if(CySpcLock() == CYRET_SUCCESS)
+ {
+ /* Plan for failure */
+ status = CYRET_UNKNOWN;
+
+ /* Command to load a row of data */
+ if(CySpcEraseSector(CY_SPC_FIRST_EE_ARRAYID, sectorNumber) == CYRET_STARTED)
+ {
+ status = CYRET_SUCCESS;
+ }
+ }
+ else
+ {
+ status = CYRET_LOCKED;
+ }
+ }
+ else
+ {
+ status = CYRET_BAD_PARAM;
+ }
+
+ return(status);
+}
+
+
+/*******************************************************************************
+* Function Name: CFG_EEPROM_Query
+********************************************************************************
+*
+* Summary:
+* Checks the status of an earlier call to CFG_EEPROM_StartWrite() or
+* CFG_EEPROM_StartErase().
+* This function must be called until it returns a value other than
+* CYRET_STARTED. Once that occurs, the write or erase has been completed and
+* the SPC is unlocked.
*
* Parameters:
* None
*
* Return:
-* CYRET_STARTED, if the spc command is still processing.
-* CYRET_SUCCESS, if the operation was successful.
+* CYRET_STARTED, if the SPC command is still processing.
+* CYRET_SUCCESS, if the operation was completed successfully.
* CYRET_UNKNOWN, if there was an SPC error.
*
*******************************************************************************/
-cystatus CFG_EEPROM_QueryWrite(void)
+cystatus CFG_EEPROM_Query(void)
{
cystatus status;
+
+ CySpcStart();
/* Check if SPC is idle */
if(CY_SPC_IDLE)
status = CYRET_UNKNOWN;
}
- /* Unlock the SPC so someone else can use it. */
+ /* Unlock SPC so that someone else can use it. */
CySpcUnlock();
}
else
/*******************************************************************************
-* Function Name: CFG_EEPROM_ByteWrite
+* Function Name: CFG_EEPROM_ByteWritePos
********************************************************************************
*
* Summary:
* Writes a byte of data to the EEPROM. This is a blocking call. It will not
-* return until the function succeeds or fails.
+* return until the write operation succeeds or fails.
*
* Parameters:
-* dataByte: Byte of data to write to the EEPROM.
-* rowNumber: EEPROM row number to program.
-* byteNumber: Byte number within the row to program.
+* dataByte: The byte of data to write to the EEPROM.
+* rowNumber: The EEPROM row number to program.
+* byteNumber: The byte number within the row to program.
*
* Return:
* CYRET_SUCCESS, if the operation was successful.
-* CYRET_BAD_PARAM, if the parameter rowNumber or byteNumber out of range.
-* CYRET_LOCKED, if the spc is being used.
+* CYRET_BAD_PARAM, if the parameter rowNumber or byteNumber is out of range.
+* CYRET_LOCKED, if the SPC is being used.
* CYRET_UNKNOWN, if there was an SPC error.
*
*******************************************************************************/
-cystatus CFG_EEPROM_ByteWrite(uint8 dataByte, uint8 rowNumber, uint8 byteNumber) \
+cystatus CFG_EEPROM_ByteWritePos(uint8 dataByte, uint8 rowNumber, uint8 byteNumber) \
{
cystatus status;
- /* Start the SPC */
+ /* Start SPC */
CySpcStart();
if((rowNumber < (uint8) CY_EEPROM_NUMBER_ROWS) && (byteNumber < (uint8) SIZEOF_EEPROM_ROW))
{
- /* See if we can get the SPC. */
+ /* See if we can get SPC. */
if(CySpcLock() == CYRET_SUCCESS)
{
/* Plan for failure */
status = CYRET_UNKNOWN;
- /* Command to load a byte of data */
+ /* Command to load byte of data */
if(CySpcLoadMultiByte(CY_SPC_FIRST_EE_ARRAYID, (uint16)byteNumber, &dataByte,\
CFG_EEPROM_SPC_BYTE_WRITE_SIZE) == CYRET_STARTED)
{
/* Command to erase and program the row. */
if(status == CYRET_SUCCESS)
{
- if(CySpcWriteRow(CY_SPC_FIRST_EE_ARRAYID, (uint16)rowNumber, dieTemperature[0],
- dieTemperature[1]) == CYRET_STARTED)
+ if(CySpcWriteRow(CY_SPC_FIRST_EE_ARRAYID, (uint16)rowNumber, dieTemperature[0u],
+ dieTemperature[1u]) == CYRET_STARTED)
{
/* Plan for failure */
status = CYRET_UNKNOWN;
}
}
- /* Unlock the SPC so someone else can use it. */
+ /* Unlock SPC so that someone else can use it. */
CySpcUnlock();
}
else
/*******************************************************************************
* File Name: CFG_EEPROM.h
-* Version 2.10
+* Version 3.0
*
-* Description:
-* Provides the function definitions for the EEPROM APIs.
+* Description:
+* Provides the function definitions for the EEPROM APIs.
*
********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
-* You may use this file only in accordance with the license, terms, conditions,
-* disclaimers, and limitations in the end user license agreement accompanying
+* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions,
+* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#include "CyFlash.h"
#if !defined(CY_PSOC5LP)
- #error Component EEPROM_v2_10 requires cy_boot v3.0 or later
+ #error Component EEPROM_v3_0 requires cy_boot v3.0 or later
#endif /* (CY_PSOC5LP) */
* Function Prototypes
***************************************/
-#if (CY_PSOC3 || CY_PSOC5LP)
- void CFG_EEPROM_Enable(void) ;
- void CFG_EEPROM_Start(void);
- void CFG_EEPROM_Stop(void) ;
-#endif /* (CY_PSOC3 || CY_PSOC5LP) */
-
+void CFG_EEPROM_Enable(void) ;
+void CFG_EEPROM_Start(void) ;
+void CFG_EEPROM_Stop (void) ;
+cystatus CFG_EEPROM_WriteByte(uint8 dataByte, uint16 address) \
+ ;
+uint8 CFG_EEPROM_ReadByte(uint16 address) ;
+uint8 CFG_EEPROM_UpdateTemperature(void) ;
cystatus CFG_EEPROM_EraseSector(uint8 sectorNumber) ;
cystatus CFG_EEPROM_Write(const uint8 * rowData, uint8 rowNumber) ;
cystatus CFG_EEPROM_StartWrite(const uint8 * rowData, uint8 rowNumber) \
- ;
-cystatus CFG_EEPROM_QueryWrite(void) ;
-cystatus CFG_EEPROM_ByteWrite(uint8 dataByte, uint8 rowNumber, uint8 byteNumber) \
- ;
+ ;
+cystatus CFG_EEPROM_StartErase(uint8 sectorNumber) ;
+cystatus CFG_EEPROM_Query(void) ;
+cystatus CFG_EEPROM_ByteWritePos(uint8 dataByte, uint8 rowNumber, uint8 byteNumber) \
+ ;
/****************************************
* API Constants
****************************************/
-#define CFG_EEPROM_EEPROM_SIZE CYDEV_EE_SIZE
+#define CFG_EEPROM_EEPROM_SIZE CYDEV_EE_SIZE
#define CFG_EEPROM_SPC_BYTE_WRITE_SIZE (0x01u)
+#define CFG_EEPROM_SECTORS_NUMBER (CYDEV_EE_SIZE / CYDEV_EEPROM_SECTOR_SIZE)
-/*******************************************************************************
-* Following code are OBSOLETE and must not be used starting from EEPROM 2.10
-*******************************************************************************/
-#define SPC_BYTE_WRITE_SIZE (CFG_EEPROM_SPC_BYTE_WRITE_SIZE)
+#define CFG_EEPROM_AHB_REQ_SHIFT (0x00u)
+#define CFG_EEPROM_AHB_REQ ((uint8)(0x01u << CFG_EEPROM_AHB_REQ_SHIFT))
+#define CFG_EEPROM_AHB_ACK_SHIFT (0x01u)
+#define CFG_EEPROM_AHB_ACK_MASK ((uint8)(0x01u << CFG_EEPROM_AHB_ACK_SHIFT))
+
+
+/***************************************
+* Registers
+***************************************/
+#define CFG_EEPROM_SPC_EE_SCR_REG (*(reg8 *) CYREG_SPC_EE_SCR)
+#define CFG_EEPROM_SPC_EE_SCR_PTR ( (reg8 *) CYREG_SPC_EE_SCR)
+
+
+
+/***************************************
+* The following code is DEPRECATED and
+* should not be used in new projects.
+***************************************/
+#define CFG_EEPROM_ByteWrite CFG_EEPROM_ByteWritePos
+#define CFG_EEPROM_QueryWrite CFG_EEPROM_Query
#endif /* CY_EEPROM_CFG_EEPROM_H */
* Note:
*
********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
********************************************************************************
*
* Summary:
-* Set up the interrupt and enable it.
+* Set up the interrupt and enable it. This function disables the interrupt,
+* sets the default interrupt vector, sets the priority from the value in the
+* Design Wide Resources Interrupt Editor, then enables the interrupt to the
+* interrupt controller.
*
* Parameters:
* None
********************************************************************************
*
* Summary:
-* Set up the interrupt and enable it.
+* Sets up the interrupt and enables it. This function disables the interrupt,
+* sets the interrupt vector based on the address passed in, sets the priority
+* from the value in the Design Wide Resources Interrupt Editor, then enables
+* the interrupt to the interrupt controller.
+*
+* When defining ISR functions, the CY_ISR and CY_ISR_PROTO macros should be
+* used to provide consistent definition across compilers:
+*
+* Function definition example:
+* CY_ISR(MyISR)
+* {
+* }
+* Function prototype example:
+* CY_ISR_PROTO(MyISR);
*
* Parameters:
* address: Address of the ISR to set in the interrupt vector table.
* Disables and removes the interrupt.
*
* Parameters:
+* None
*
* Return:
* None
* Change the ISR vector for the Interrupt. Note calling Debug_Timer_Interrupt_Start
* will override any effect this method would have had. To set the vector
* before the component has been started use Debug_Timer_Interrupt_StartEx instead.
+*
+* When defining ISR functions, the CY_ISR and CY_ISR_PROTO macros should be
+* used to provide consistent definition across compilers:
+*
+* Function definition example:
+* CY_ISR(MyISR)
+* {
+* }
+*
+* Function prototype example:
+* CY_ISR_PROTO(MyISR);
*
* Parameters:
* address: Address of the ISR to set in the interrupt vector table.
********************************************************************************
*
* Summary:
-* Sets the Priority of the Interrupt. Note calling Debug_Timer_Interrupt_Start
-* or Debug_Timer_Interrupt_StartEx will override any effect this method
-* would have had. This method should only be called after
-* Debug_Timer_Interrupt_Start or Debug_Timer_Interrupt_StartEx has been called. To set
-* the initial priority for the component use the cydwr file in the tool.
+* Sets the Priority of the Interrupt.
+*
+* Note calling Debug_Timer_Interrupt_Start or Debug_Timer_Interrupt_StartEx will
+* override any effect this API would have had. This API should only be called
+* after Debug_Timer_Interrupt_Start or Debug_Timer_Interrupt_StartEx has been called.
+* To set the initial priority for the component, use the Design-Wide Resources
+* Interrupt Editor.
+*
+* Note This API has no effect on Non-maskable interrupt NMI).
*
* Parameters:
-* priority: Priority of the interrupt. 0 - 7, 0 being the highest.
+* priority: Priority of the interrupt, 0 being the highest priority
+* PSoC 3 and PSoC 5LP: Priority is from 0 to 7.
+* PSoC 4: Priority is from 0 to 3.
*
* Return:
* None
* None
*
* Return:
-* Priority of the interrupt. 0 - 7, 0 being the highest.
+* Priority of the interrupt, 0 being the highest priority
+* PSoC 3 and PSoC 5LP: Priority is from 0 to 7.
+* PSoC 4: Priority is from 0 to 3.
*
*******************************************************************************/
uint8 Debug_Timer_Interrupt_GetPriority(void)
********************************************************************************
*
* Summary:
-* Enables the interrupt.
+* Enables the interrupt to the interrupt controller. Do not call this function
+* unless ISR_Start() has been called or the functionality of the ISR_Start()
+* function, which sets the vector and the priority, has been called.
*
* Parameters:
* None
********************************************************************************
*
* Summary:
-* Disables the Interrupt.
+* Disables the Interrupt in the interrupt controller.
*
* Parameters:
* None
* Return:
* None
*
+* Side Effects:
+* If interrupts are enabled and the interrupt is set up properly, the ISR is
+* entered (depending on the priority of this interrupt and other pending
+* interrupts).
+*
*******************************************************************************/
void Debug_Timer_Interrupt_SetPending(void)
{
********************************************************************************
*
* Summary:
-* Clears a pending interrupt.
+* Clears a pending interrupt in the interrupt controller.
+*
+* Note Some interrupt sources are clear-on-read and require the block
+* interrupt/status register to be read/cleared with the appropriate block API
+* (GPIO, UART, and so on). Otherwise the ISR will continue to remain in
+* pending state even though the interrupt itself is cleared using this API.
*
* Parameters:
* None
*
*
********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
/*******************************************************************************
* File Name: SCSI_CTL_PHASE.c
-* Version 1.70
+* Version 1.80
*
* Description:
* This file contains API to enable firmware control of a Control Register.
* Note:
*
********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
#include "SCSI_CTL_PHASE.h"
-#if !defined(SCSI_CTL_PHASE_Sync_ctrl_reg__REMOVED) /* Check for removal by optimization */
+/* Check for removal by optimization */
+#if !defined(SCSI_CTL_PHASE_Sync_ctrl_reg__REMOVED)
+
/*******************************************************************************
* Function Name: SCSI_CTL_PHASE_Write
********************************************************************************
/*******************************************************************************
* File Name: SCSI_CTL_PHASE.h
-* Version 1.70
+* Version 1.80
*
* Description:
* This file containts Control Register function prototypes and register defines
* Note:
*
********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
#include "cytypes.h"
+
+/***************************************
+* Data Struct Definitions
+***************************************/
+
+/* Sleep Mode API Support */
+typedef struct
+{
+ uint8 controlState;
+
+} SCSI_CTL_PHASE_BACKUP_STRUCT;
+
/***************************************
* Function Prototypes
void SCSI_CTL_PHASE_Write(uint8 control) ;
uint8 SCSI_CTL_PHASE_Read(void) ;
+void SCSI_CTL_PHASE_SaveConfig(void) ;
+void SCSI_CTL_PHASE_RestoreConfig(void) ;
+void SCSI_CTL_PHASE_Sleep(void) ;
+void SCSI_CTL_PHASE_Wakeup(void) ;
+
/***************************************
* Registers
--- /dev/null
+/*******************************************************************************
+* File Name: SCSI_CTL_PHASE_PM.c
+* Version 1.80
+*
+* Description:
+* This file contains the setup, control, and status commands to support
+* the component operation in the low power mode.
+*
+* Note:
+*
+********************************************************************************
+* Copyright 2015, Cypress Semiconductor Corporation. All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions,
+* disclaimers, and limitations in the end user license agreement accompanying
+* the software package with which this file was provided.
+*******************************************************************************/
+
+#include "SCSI_CTL_PHASE.h"
+
+/* Check for removal by optimization */
+#if !defined(SCSI_CTL_PHASE_Sync_ctrl_reg__REMOVED)
+
+static SCSI_CTL_PHASE_BACKUP_STRUCT SCSI_CTL_PHASE_backup = {0u};
+
+
+/*******************************************************************************
+* Function Name: SCSI_CTL_PHASE_SaveConfig
+********************************************************************************
+*
+* Summary:
+* Saves the control register value.
+*
+* Parameters:
+* None
+*
+* Return:
+* None
+*
+*******************************************************************************/
+void SCSI_CTL_PHASE_SaveConfig(void)
+{
+ SCSI_CTL_PHASE_backup.controlState = SCSI_CTL_PHASE_Control;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_CTL_PHASE_RestoreConfig
+********************************************************************************
+*
+* Summary:
+* Restores the control register value.
+*
+* Parameters:
+* None
+*
+* Return:
+* None
+*
+*
+*******************************************************************************/
+void SCSI_CTL_PHASE_RestoreConfig(void)
+{
+ SCSI_CTL_PHASE_Control = SCSI_CTL_PHASE_backup.controlState;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_CTL_PHASE_Sleep
+********************************************************************************
+*
+* Summary:
+* Prepares the component for entering the low power mode.
+*
+* Parameters:
+* None
+*
+* Return:
+* None
+*
+*******************************************************************************/
+void SCSI_CTL_PHASE_Sleep(void)
+{
+ SCSI_CTL_PHASE_SaveConfig();
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_CTL_PHASE_Wakeup
+********************************************************************************
+*
+* Summary:
+* Restores the component after waking up from the low power mode.
+*
+* Parameters:
+* None
+*
+* Return:
+* None
+*
+*******************************************************************************/
+void SCSI_CTL_PHASE_Wakeup(void)
+{
+ SCSI_CTL_PHASE_RestoreConfig();
+}
+
+#endif /* End check for removal by optimization */
+
+
+/* [] END OF FILE */
/*******************************************************************************
* File Name: SCSI_Filtered.c
-* Version 1.80
+* Version 1.90
*
* Description:
* This file contains API to enable firmware to read the value of a Status
* Note:
*
********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
void SCSI_Filtered_WriteMask(uint8 mask)
{
#if(SCSI_Filtered_INPUTS < 8u)
- mask &= (uint8)((((uint8)1u) << SCSI_Filtered_INPUTS) - 1u);
+ mask &= ((uint8)(1u << SCSI_Filtered_INPUTS) - 1u);
#endif /* End SCSI_Filtered_INPUTS < 8u */
SCSI_Filtered_Status_Mask = mask;
}
/*******************************************************************************
* File Name: SCSI_Filtered.h
-* Version 1.80
+* Version 1.90
*
* Description:
* This file containts Status Register function prototypes and register defines
* Note:
*
********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
#include "cytypes.h"
#include "CyLib.h"
+
+/***************************************
+* Data Struct Definitions
+***************************************/
+
+/* Sleep Mode API Support */
+typedef struct
+{
+ uint8 statusState;
+
+} SCSI_Filtered_BACKUP_STRUCT;
+
/***************************************
* Function Prototypes
/*******************************************************************************
* File Name: SCSI_Glitch_Ctl.c
-* Version 1.70
+* Version 1.80
*
* Description:
* This file contains API to enable firmware control of a Control Register.
* Note:
*
********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
#include "SCSI_Glitch_Ctl.h"
-#if !defined(SCSI_Glitch_Ctl_Sync_ctrl_reg__REMOVED) /* Check for removal by optimization */
+/* Check for removal by optimization */
+#if !defined(SCSI_Glitch_Ctl_Sync_ctrl_reg__REMOVED)
+
/*******************************************************************************
* Function Name: SCSI_Glitch_Ctl_Write
********************************************************************************
/*******************************************************************************
* File Name: SCSI_Glitch_Ctl.h
-* Version 1.70
+* Version 1.80
*
* Description:
* This file containts Control Register function prototypes and register defines
* Note:
*
********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
#include "cytypes.h"
+
+/***************************************
+* Data Struct Definitions
+***************************************/
+
+/* Sleep Mode API Support */
+typedef struct
+{
+ uint8 controlState;
+
+} SCSI_Glitch_Ctl_BACKUP_STRUCT;
+
/***************************************
* Function Prototypes
void SCSI_Glitch_Ctl_Write(uint8 control) ;
uint8 SCSI_Glitch_Ctl_Read(void) ;
+void SCSI_Glitch_Ctl_SaveConfig(void) ;
+void SCSI_Glitch_Ctl_RestoreConfig(void) ;
+void SCSI_Glitch_Ctl_Sleep(void) ;
+void SCSI_Glitch_Ctl_Wakeup(void) ;
+
/***************************************
* Registers
--- /dev/null
+/*******************************************************************************
+* File Name: SCSI_Glitch_Ctl_PM.c
+* Version 1.80
+*
+* Description:
+* This file contains the setup, control, and status commands to support
+* the component operation in the low power mode.
+*
+* Note:
+*
+********************************************************************************
+* Copyright 2015, Cypress Semiconductor Corporation. All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions,
+* disclaimers, and limitations in the end user license agreement accompanying
+* the software package with which this file was provided.
+*******************************************************************************/
+
+#include "SCSI_Glitch_Ctl.h"
+
+/* Check for removal by optimization */
+#if !defined(SCSI_Glitch_Ctl_Sync_ctrl_reg__REMOVED)
+
+static SCSI_Glitch_Ctl_BACKUP_STRUCT SCSI_Glitch_Ctl_backup = {0u};
+
+
+/*******************************************************************************
+* Function Name: SCSI_Glitch_Ctl_SaveConfig
+********************************************************************************
+*
+* Summary:
+* Saves the control register value.
+*
+* Parameters:
+* None
+*
+* Return:
+* None
+*
+*******************************************************************************/
+void SCSI_Glitch_Ctl_SaveConfig(void)
+{
+ SCSI_Glitch_Ctl_backup.controlState = SCSI_Glitch_Ctl_Control;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_Glitch_Ctl_RestoreConfig
+********************************************************************************
+*
+* Summary:
+* Restores the control register value.
+*
+* Parameters:
+* None
+*
+* Return:
+* None
+*
+*
+*******************************************************************************/
+void SCSI_Glitch_Ctl_RestoreConfig(void)
+{
+ SCSI_Glitch_Ctl_Control = SCSI_Glitch_Ctl_backup.controlState;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_Glitch_Ctl_Sleep
+********************************************************************************
+*
+* Summary:
+* Prepares the component for entering the low power mode.
+*
+* Parameters:
+* None
+*
+* Return:
+* None
+*
+*******************************************************************************/
+void SCSI_Glitch_Ctl_Sleep(void)
+{
+ SCSI_Glitch_Ctl_SaveConfig();
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_Glitch_Ctl_Wakeup
+********************************************************************************
+*
+* Summary:
+* Restores the component after waking up from the low power mode.
+*
+* Parameters:
+* None
+*
+* Return:
+* None
+*
+*******************************************************************************/
+void SCSI_Glitch_Ctl_Wakeup(void)
+{
+ SCSI_Glitch_Ctl_RestoreConfig();
+}
+
+#endif /* End check for removal by optimization */
+
+
+/* [] END OF FILE */
/*******************************************************************************
* File Name: SCSI_Out_Bits.c
-* Version 1.70
+* Version 1.80
*
* Description:
* This file contains API to enable firmware control of a Control Register.
* Note:
*
********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
#include "SCSI_Out_Bits.h"
-#if !defined(SCSI_Out_Bits_Sync_ctrl_reg__REMOVED) /* Check for removal by optimization */
+/* Check for removal by optimization */
+#if !defined(SCSI_Out_Bits_Sync_ctrl_reg__REMOVED)
+
/*******************************************************************************
* Function Name: SCSI_Out_Bits_Write
********************************************************************************
/*******************************************************************************
* File Name: SCSI_Out_Bits.h
-* Version 1.70
+* Version 1.80
*
* Description:
* This file containts Control Register function prototypes and register defines
* Note:
*
********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
#include "cytypes.h"
+
+/***************************************
+* Data Struct Definitions
+***************************************/
+
+/* Sleep Mode API Support */
+typedef struct
+{
+ uint8 controlState;
+
+} SCSI_Out_Bits_BACKUP_STRUCT;
+
/***************************************
* Function Prototypes
void SCSI_Out_Bits_Write(uint8 control) ;
uint8 SCSI_Out_Bits_Read(void) ;
+void SCSI_Out_Bits_SaveConfig(void) ;
+void SCSI_Out_Bits_RestoreConfig(void) ;
+void SCSI_Out_Bits_Sleep(void) ;
+void SCSI_Out_Bits_Wakeup(void) ;
+
/***************************************
* Registers
--- /dev/null
+/*******************************************************************************
+* File Name: SCSI_Out_Bits_PM.c
+* Version 1.80
+*
+* Description:
+* This file contains the setup, control, and status commands to support
+* the component operation in the low power mode.
+*
+* Note:
+*
+********************************************************************************
+* Copyright 2015, Cypress Semiconductor Corporation. All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions,
+* disclaimers, and limitations in the end user license agreement accompanying
+* the software package with which this file was provided.
+*******************************************************************************/
+
+#include "SCSI_Out_Bits.h"
+
+/* Check for removal by optimization */
+#if !defined(SCSI_Out_Bits_Sync_ctrl_reg__REMOVED)
+
+static SCSI_Out_Bits_BACKUP_STRUCT SCSI_Out_Bits_backup = {0u};
+
+
+/*******************************************************************************
+* Function Name: SCSI_Out_Bits_SaveConfig
+********************************************************************************
+*
+* Summary:
+* Saves the control register value.
+*
+* Parameters:
+* None
+*
+* Return:
+* None
+*
+*******************************************************************************/
+void SCSI_Out_Bits_SaveConfig(void)
+{
+ SCSI_Out_Bits_backup.controlState = SCSI_Out_Bits_Control;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_Out_Bits_RestoreConfig
+********************************************************************************
+*
+* Summary:
+* Restores the control register value.
+*
+* Parameters:
+* None
+*
+* Return:
+* None
+*
+*
+*******************************************************************************/
+void SCSI_Out_Bits_RestoreConfig(void)
+{
+ SCSI_Out_Bits_Control = SCSI_Out_Bits_backup.controlState;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_Out_Bits_Sleep
+********************************************************************************
+*
+* Summary:
+* Prepares the component for entering the low power mode.
+*
+* Parameters:
+* None
+*
+* Return:
+* None
+*
+*******************************************************************************/
+void SCSI_Out_Bits_Sleep(void)
+{
+ SCSI_Out_Bits_SaveConfig();
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_Out_Bits_Wakeup
+********************************************************************************
+*
+* Summary:
+* Restores the component after waking up from the low power mode.
+*
+* Parameters:
+* None
+*
+* Return:
+* None
+*
+*******************************************************************************/
+void SCSI_Out_Bits_Wakeup(void)
+{
+ SCSI_Out_Bits_RestoreConfig();
+}
+
+#endif /* End check for removal by optimization */
+
+
+/* [] END OF FILE */
/*******************************************************************************
* File Name: SCSI_Out_Ctl.c
-* Version 1.70
+* Version 1.80
*
* Description:
* This file contains API to enable firmware control of a Control Register.
* Note:
*
********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
#include "SCSI_Out_Ctl.h"
-#if !defined(SCSI_Out_Ctl_Sync_ctrl_reg__REMOVED) /* Check for removal by optimization */
+/* Check for removal by optimization */
+#if !defined(SCSI_Out_Ctl_Sync_ctrl_reg__REMOVED)
+
/*******************************************************************************
* Function Name: SCSI_Out_Ctl_Write
********************************************************************************
/*******************************************************************************
* File Name: SCSI_Out_Ctl.h
-* Version 1.70
+* Version 1.80
*
* Description:
* This file containts Control Register function prototypes and register defines
* Note:
*
********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
#include "cytypes.h"
+
+/***************************************
+* Data Struct Definitions
+***************************************/
+
+/* Sleep Mode API Support */
+typedef struct
+{
+ uint8 controlState;
+
+} SCSI_Out_Ctl_BACKUP_STRUCT;
+
/***************************************
* Function Prototypes
void SCSI_Out_Ctl_Write(uint8 control) ;
uint8 SCSI_Out_Ctl_Read(void) ;
+void SCSI_Out_Ctl_SaveConfig(void) ;
+void SCSI_Out_Ctl_RestoreConfig(void) ;
+void SCSI_Out_Ctl_Sleep(void) ;
+void SCSI_Out_Ctl_Wakeup(void) ;
+
/***************************************
* Registers
--- /dev/null
+/*******************************************************************************
+* File Name: SCSI_Out_Ctl_PM.c
+* Version 1.80
+*
+* Description:
+* This file contains the setup, control, and status commands to support
+* the component operation in the low power mode.
+*
+* Note:
+*
+********************************************************************************
+* Copyright 2015, Cypress Semiconductor Corporation. All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions,
+* disclaimers, and limitations in the end user license agreement accompanying
+* the software package with which this file was provided.
+*******************************************************************************/
+
+#include "SCSI_Out_Ctl.h"
+
+/* Check for removal by optimization */
+#if !defined(SCSI_Out_Ctl_Sync_ctrl_reg__REMOVED)
+
+static SCSI_Out_Ctl_BACKUP_STRUCT SCSI_Out_Ctl_backup = {0u};
+
+
+/*******************************************************************************
+* Function Name: SCSI_Out_Ctl_SaveConfig
+********************************************************************************
+*
+* Summary:
+* Saves the control register value.
+*
+* Parameters:
+* None
+*
+* Return:
+* None
+*
+*******************************************************************************/
+void SCSI_Out_Ctl_SaveConfig(void)
+{
+ SCSI_Out_Ctl_backup.controlState = SCSI_Out_Ctl_Control;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_Out_Ctl_RestoreConfig
+********************************************************************************
+*
+* Summary:
+* Restores the control register value.
+*
+* Parameters:
+* None
+*
+* Return:
+* None
+*
+*
+*******************************************************************************/
+void SCSI_Out_Ctl_RestoreConfig(void)
+{
+ SCSI_Out_Ctl_Control = SCSI_Out_Ctl_backup.controlState;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_Out_Ctl_Sleep
+********************************************************************************
+*
+* Summary:
+* Prepares the component for entering the low power mode.
+*
+* Parameters:
+* None
+*
+* Return:
+* None
+*
+*******************************************************************************/
+void SCSI_Out_Ctl_Sleep(void)
+{
+ SCSI_Out_Ctl_SaveConfig();
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_Out_Ctl_Wakeup
+********************************************************************************
+*
+* Summary:
+* Restores the component after waking up from the low power mode.
+*
+* Parameters:
+* None
+*
+* Return:
+* None
+*
+*******************************************************************************/
+void SCSI_Out_Ctl_Wakeup(void)
+{
+ SCSI_Out_Ctl_RestoreConfig();
+}
+
+#endif /* End check for removal by optimization */
+
+
+/* [] END OF FILE */
/*******************************************************************************
* File Name: SCSI_Parity_Error.c
-* Version 1.80
+* Version 1.90
*
* Description:
* This file contains API to enable firmware to read the value of a Status
* Note:
*
********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
void SCSI_Parity_Error_WriteMask(uint8 mask)
{
#if(SCSI_Parity_Error_INPUTS < 8u)
- mask &= (uint8)((((uint8)1u) << SCSI_Parity_Error_INPUTS) - 1u);
+ mask &= ((uint8)(1u << SCSI_Parity_Error_INPUTS) - 1u);
#endif /* End SCSI_Parity_Error_INPUTS < 8u */
SCSI_Parity_Error_Status_Mask = mask;
}
/*******************************************************************************
* File Name: SCSI_Parity_Error.h
-* Version 1.80
+* Version 1.90
*
* Description:
* This file containts Status Register function prototypes and register defines
* Note:
*
********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
#include "cytypes.h"
#include "CyLib.h"
+
+/***************************************
+* Data Struct Definitions
+***************************************/
+
+/* Sleep Mode API Support */
+typedef struct
+{
+ uint8 statusState;
+
+} SCSI_Parity_Error_BACKUP_STRUCT;
+
/***************************************
* Function Prototypes
* Note:
*
********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
********************************************************************************
*
* Summary:
-* Set up the interrupt and enable it.
+* Set up the interrupt and enable it. This function disables the interrupt,
+* sets the default interrupt vector, sets the priority from the value in the
+* Design Wide Resources Interrupt Editor, then enables the interrupt to the
+* interrupt controller.
*
* Parameters:
* None
********************************************************************************
*
* Summary:
-* Set up the interrupt and enable it.
+* Sets up the interrupt and enables it. This function disables the interrupt,
+* sets the interrupt vector based on the address passed in, sets the priority
+* from the value in the Design Wide Resources Interrupt Editor, then enables
+* the interrupt to the interrupt controller.
+*
+* When defining ISR functions, the CY_ISR and CY_ISR_PROTO macros should be
+* used to provide consistent definition across compilers:
+*
+* Function definition example:
+* CY_ISR(MyISR)
+* {
+* }
+* Function prototype example:
+* CY_ISR_PROTO(MyISR);
*
* Parameters:
* address: Address of the ISR to set in the interrupt vector table.
* Disables and removes the interrupt.
*
* Parameters:
+* None
*
* Return:
* None
* Change the ISR vector for the Interrupt. Note calling SCSI_RST_ISR_Start
* will override any effect this method would have had. To set the vector
* before the component has been started use SCSI_RST_ISR_StartEx instead.
+*
+* When defining ISR functions, the CY_ISR and CY_ISR_PROTO macros should be
+* used to provide consistent definition across compilers:
+*
+* Function definition example:
+* CY_ISR(MyISR)
+* {
+* }
+*
+* Function prototype example:
+* CY_ISR_PROTO(MyISR);
*
* Parameters:
* address: Address of the ISR to set in the interrupt vector table.
********************************************************************************
*
* Summary:
-* Sets the Priority of the Interrupt. Note calling SCSI_RST_ISR_Start
-* or SCSI_RST_ISR_StartEx will override any effect this method
-* would have had. This method should only be called after
-* SCSI_RST_ISR_Start or SCSI_RST_ISR_StartEx has been called. To set
-* the initial priority for the component use the cydwr file in the tool.
+* Sets the Priority of the Interrupt.
+*
+* Note calling SCSI_RST_ISR_Start or SCSI_RST_ISR_StartEx will
+* override any effect this API would have had. This API should only be called
+* after SCSI_RST_ISR_Start or SCSI_RST_ISR_StartEx has been called.
+* To set the initial priority for the component, use the Design-Wide Resources
+* Interrupt Editor.
+*
+* Note This API has no effect on Non-maskable interrupt NMI).
*
* Parameters:
-* priority: Priority of the interrupt. 0 - 7, 0 being the highest.
+* priority: Priority of the interrupt, 0 being the highest priority
+* PSoC 3 and PSoC 5LP: Priority is from 0 to 7.
+* PSoC 4: Priority is from 0 to 3.
*
* Return:
* None
* None
*
* Return:
-* Priority of the interrupt. 0 - 7, 0 being the highest.
+* Priority of the interrupt, 0 being the highest priority
+* PSoC 3 and PSoC 5LP: Priority is from 0 to 7.
+* PSoC 4: Priority is from 0 to 3.
*
*******************************************************************************/
uint8 SCSI_RST_ISR_GetPriority(void)
********************************************************************************
*
* Summary:
-* Enables the interrupt.
+* Enables the interrupt to the interrupt controller. Do not call this function
+* unless ISR_Start() has been called or the functionality of the ISR_Start()
+* function, which sets the vector and the priority, has been called.
*
* Parameters:
* None
********************************************************************************
*
* Summary:
-* Disables the Interrupt.
+* Disables the Interrupt in the interrupt controller.
*
* Parameters:
* None
* Return:
* None
*
+* Side Effects:
+* If interrupts are enabled and the interrupt is set up properly, the ISR is
+* entered (depending on the priority of this interrupt and other pending
+* interrupts).
+*
*******************************************************************************/
void SCSI_RST_ISR_SetPending(void)
{
********************************************************************************
*
* Summary:
-* Clears a pending interrupt.
+* Clears a pending interrupt in the interrupt controller.
+*
+* Note Some interrupt sources are clear-on-read and require the block
+* interrupt/status register to be read/cleared with the appropriate block API
+* (GPIO, UART, and so on). Otherwise the ISR will continue to remain in
+* pending state even though the interrupt itself is cleared using this API.
*
* Parameters:
* None
*
*
********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
* Note:
*
********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
********************************************************************************
*
* Summary:
-* Set up the interrupt and enable it.
+* Set up the interrupt and enable it. This function disables the interrupt,
+* sets the default interrupt vector, sets the priority from the value in the
+* Design Wide Resources Interrupt Editor, then enables the interrupt to the
+* interrupt controller.
*
* Parameters:
* None
********************************************************************************
*
* Summary:
-* Set up the interrupt and enable it.
+* Sets up the interrupt and enables it. This function disables the interrupt,
+* sets the interrupt vector based on the address passed in, sets the priority
+* from the value in the Design Wide Resources Interrupt Editor, then enables
+* the interrupt to the interrupt controller.
+*
+* When defining ISR functions, the CY_ISR and CY_ISR_PROTO macros should be
+* used to provide consistent definition across compilers:
+*
+* Function definition example:
+* CY_ISR(MyISR)
+* {
+* }
+* Function prototype example:
+* CY_ISR_PROTO(MyISR);
*
* Parameters:
* address: Address of the ISR to set in the interrupt vector table.
* Disables and removes the interrupt.
*
* Parameters:
+* None
*
* Return:
* None
* Change the ISR vector for the Interrupt. Note calling SCSI_RX_DMA_COMPLETE_Start
* will override any effect this method would have had. To set the vector
* before the component has been started use SCSI_RX_DMA_COMPLETE_StartEx instead.
+*
+* When defining ISR functions, the CY_ISR and CY_ISR_PROTO macros should be
+* used to provide consistent definition across compilers:
+*
+* Function definition example:
+* CY_ISR(MyISR)
+* {
+* }
+*
+* Function prototype example:
+* CY_ISR_PROTO(MyISR);
*
* Parameters:
* address: Address of the ISR to set in the interrupt vector table.
********************************************************************************
*
* Summary:
-* Sets the Priority of the Interrupt. Note calling SCSI_RX_DMA_COMPLETE_Start
-* or SCSI_RX_DMA_COMPLETE_StartEx will override any effect this method
-* would have had. This method should only be called after
-* SCSI_RX_DMA_COMPLETE_Start or SCSI_RX_DMA_COMPLETE_StartEx has been called. To set
-* the initial priority for the component use the cydwr file in the tool.
+* Sets the Priority of the Interrupt.
+*
+* Note calling SCSI_RX_DMA_COMPLETE_Start or SCSI_RX_DMA_COMPLETE_StartEx will
+* override any effect this API would have had. This API should only be called
+* after SCSI_RX_DMA_COMPLETE_Start or SCSI_RX_DMA_COMPLETE_StartEx has been called.
+* To set the initial priority for the component, use the Design-Wide Resources
+* Interrupt Editor.
+*
+* Note This API has no effect on Non-maskable interrupt NMI).
*
* Parameters:
-* priority: Priority of the interrupt. 0 - 7, 0 being the highest.
+* priority: Priority of the interrupt, 0 being the highest priority
+* PSoC 3 and PSoC 5LP: Priority is from 0 to 7.
+* PSoC 4: Priority is from 0 to 3.
*
* Return:
* None
* None
*
* Return:
-* Priority of the interrupt. 0 - 7, 0 being the highest.
+* Priority of the interrupt, 0 being the highest priority
+* PSoC 3 and PSoC 5LP: Priority is from 0 to 7.
+* PSoC 4: Priority is from 0 to 3.
*
*******************************************************************************/
uint8 SCSI_RX_DMA_COMPLETE_GetPriority(void)
********************************************************************************
*
* Summary:
-* Enables the interrupt.
+* Enables the interrupt to the interrupt controller. Do not call this function
+* unless ISR_Start() has been called or the functionality of the ISR_Start()
+* function, which sets the vector and the priority, has been called.
*
* Parameters:
* None
********************************************************************************
*
* Summary:
-* Disables the Interrupt.
+* Disables the Interrupt in the interrupt controller.
*
* Parameters:
* None
* Return:
* None
*
+* Side Effects:
+* If interrupts are enabled and the interrupt is set up properly, the ISR is
+* entered (depending on the priority of this interrupt and other pending
+* interrupts).
+*
*******************************************************************************/
void SCSI_RX_DMA_COMPLETE_SetPending(void)
{
********************************************************************************
*
* Summary:
-* Clears a pending interrupt.
+* Clears a pending interrupt in the interrupt controller.
+*
+* Note Some interrupt sources are clear-on-read and require the block
+* interrupt/status register to be read/cleared with the appropriate block API
+* (GPIO, UART, and so on). Otherwise the ISR will continue to remain in
+* pending state even though the interrupt itself is cleared using this API.
*
* Parameters:
* None
*
*
********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
* Note:
*
********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
********************************************************************************
*
* Summary:
-* Set up the interrupt and enable it.
+* Set up the interrupt and enable it. This function disables the interrupt,
+* sets the default interrupt vector, sets the priority from the value in the
+* Design Wide Resources Interrupt Editor, then enables the interrupt to the
+* interrupt controller.
*
* Parameters:
* None
********************************************************************************
*
* Summary:
-* Set up the interrupt and enable it.
+* Sets up the interrupt and enables it. This function disables the interrupt,
+* sets the interrupt vector based on the address passed in, sets the priority
+* from the value in the Design Wide Resources Interrupt Editor, then enables
+* the interrupt to the interrupt controller.
+*
+* When defining ISR functions, the CY_ISR and CY_ISR_PROTO macros should be
+* used to provide consistent definition across compilers:
+*
+* Function definition example:
+* CY_ISR(MyISR)
+* {
+* }
+* Function prototype example:
+* CY_ISR_PROTO(MyISR);
*
* Parameters:
* address: Address of the ISR to set in the interrupt vector table.
* Disables and removes the interrupt.
*
* Parameters:
+* None
*
* Return:
* None
* Change the ISR vector for the Interrupt. Note calling SCSI_SEL_ISR_Start
* will override any effect this method would have had. To set the vector
* before the component has been started use SCSI_SEL_ISR_StartEx instead.
+*
+* When defining ISR functions, the CY_ISR and CY_ISR_PROTO macros should be
+* used to provide consistent definition across compilers:
+*
+* Function definition example:
+* CY_ISR(MyISR)
+* {
+* }
+*
+* Function prototype example:
+* CY_ISR_PROTO(MyISR);
*
* Parameters:
* address: Address of the ISR to set in the interrupt vector table.
********************************************************************************
*
* Summary:
-* Sets the Priority of the Interrupt. Note calling SCSI_SEL_ISR_Start
-* or SCSI_SEL_ISR_StartEx will override any effect this method
-* would have had. This method should only be called after
-* SCSI_SEL_ISR_Start or SCSI_SEL_ISR_StartEx has been called. To set
-* the initial priority for the component use the cydwr file in the tool.
+* Sets the Priority of the Interrupt.
+*
+* Note calling SCSI_SEL_ISR_Start or SCSI_SEL_ISR_StartEx will
+* override any effect this API would have had. This API should only be called
+* after SCSI_SEL_ISR_Start or SCSI_SEL_ISR_StartEx has been called.
+* To set the initial priority for the component, use the Design-Wide Resources
+* Interrupt Editor.
+*
+* Note This API has no effect on Non-maskable interrupt NMI).
*
* Parameters:
-* priority: Priority of the interrupt. 0 - 7, 0 being the highest.
+* priority: Priority of the interrupt, 0 being the highest priority
+* PSoC 3 and PSoC 5LP: Priority is from 0 to 7.
+* PSoC 4: Priority is from 0 to 3.
*
* Return:
* None
* None
*
* Return:
-* Priority of the interrupt. 0 - 7, 0 being the highest.
+* Priority of the interrupt, 0 being the highest priority
+* PSoC 3 and PSoC 5LP: Priority is from 0 to 7.
+* PSoC 4: Priority is from 0 to 3.
*
*******************************************************************************/
uint8 SCSI_SEL_ISR_GetPriority(void)
********************************************************************************
*
* Summary:
-* Enables the interrupt.
+* Enables the interrupt to the interrupt controller. Do not call this function
+* unless ISR_Start() has been called or the functionality of the ISR_Start()
+* function, which sets the vector and the priority, has been called.
*
* Parameters:
* None
********************************************************************************
*
* Summary:
-* Disables the Interrupt.
+* Disables the Interrupt in the interrupt controller.
*
* Parameters:
* None
* Return:
* None
*
+* Side Effects:
+* If interrupts are enabled and the interrupt is set up properly, the ISR is
+* entered (depending on the priority of this interrupt and other pending
+* interrupts).
+*
*******************************************************************************/
void SCSI_SEL_ISR_SetPending(void)
{
********************************************************************************
*
* Summary:
-* Clears a pending interrupt.
+* Clears a pending interrupt in the interrupt controller.
+*
+* Note Some interrupt sources are clear-on-read and require the block
+* interrupt/status register to be read/cleared with the appropriate block API
+* (GPIO, UART, and so on). Otherwise the ISR will continue to remain in
+* pending state even though the interrupt itself is cleared using this API.
*
* Parameters:
* None
*
*
********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
* Note:
*
********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
********************************************************************************
*
* Summary:
-* Set up the interrupt and enable it.
+* Set up the interrupt and enable it. This function disables the interrupt,
+* sets the default interrupt vector, sets the priority from the value in the
+* Design Wide Resources Interrupt Editor, then enables the interrupt to the
+* interrupt controller.
*
* Parameters:
* None
********************************************************************************
*
* Summary:
-* Set up the interrupt and enable it.
+* Sets up the interrupt and enables it. This function disables the interrupt,
+* sets the interrupt vector based on the address passed in, sets the priority
+* from the value in the Design Wide Resources Interrupt Editor, then enables
+* the interrupt to the interrupt controller.
+*
+* When defining ISR functions, the CY_ISR and CY_ISR_PROTO macros should be
+* used to provide consistent definition across compilers:
+*
+* Function definition example:
+* CY_ISR(MyISR)
+* {
+* }
+* Function prototype example:
+* CY_ISR_PROTO(MyISR);
*
* Parameters:
* address: Address of the ISR to set in the interrupt vector table.
* Disables and removes the interrupt.
*
* Parameters:
+* None
*
* Return:
* None
* Change the ISR vector for the Interrupt. Note calling SCSI_TX_DMA_COMPLETE_Start
* will override any effect this method would have had. To set the vector
* before the component has been started use SCSI_TX_DMA_COMPLETE_StartEx instead.
+*
+* When defining ISR functions, the CY_ISR and CY_ISR_PROTO macros should be
+* used to provide consistent definition across compilers:
+*
+* Function definition example:
+* CY_ISR(MyISR)
+* {
+* }
+*
+* Function prototype example:
+* CY_ISR_PROTO(MyISR);
*
* Parameters:
* address: Address of the ISR to set in the interrupt vector table.
********************************************************************************
*
* Summary:
-* Sets the Priority of the Interrupt. Note calling SCSI_TX_DMA_COMPLETE_Start
-* or SCSI_TX_DMA_COMPLETE_StartEx will override any effect this method
-* would have had. This method should only be called after
-* SCSI_TX_DMA_COMPLETE_Start or SCSI_TX_DMA_COMPLETE_StartEx has been called. To set
-* the initial priority for the component use the cydwr file in the tool.
+* Sets the Priority of the Interrupt.
+*
+* Note calling SCSI_TX_DMA_COMPLETE_Start or SCSI_TX_DMA_COMPLETE_StartEx will
+* override any effect this API would have had. This API should only be called
+* after SCSI_TX_DMA_COMPLETE_Start or SCSI_TX_DMA_COMPLETE_StartEx has been called.
+* To set the initial priority for the component, use the Design-Wide Resources
+* Interrupt Editor.
+*
+* Note This API has no effect on Non-maskable interrupt NMI).
*
* Parameters:
-* priority: Priority of the interrupt. 0 - 7, 0 being the highest.
+* priority: Priority of the interrupt, 0 being the highest priority
+* PSoC 3 and PSoC 5LP: Priority is from 0 to 7.
+* PSoC 4: Priority is from 0 to 3.
*
* Return:
* None
* None
*
* Return:
-* Priority of the interrupt. 0 - 7, 0 being the highest.
+* Priority of the interrupt, 0 being the highest priority
+* PSoC 3 and PSoC 5LP: Priority is from 0 to 7.
+* PSoC 4: Priority is from 0 to 3.
*
*******************************************************************************/
uint8 SCSI_TX_DMA_COMPLETE_GetPriority(void)
********************************************************************************
*
* Summary:
-* Enables the interrupt.
+* Enables the interrupt to the interrupt controller. Do not call this function
+* unless ISR_Start() has been called or the functionality of the ISR_Start()
+* function, which sets the vector and the priority, has been called.
*
* Parameters:
* None
********************************************************************************
*
* Summary:
-* Disables the Interrupt.
+* Disables the Interrupt in the interrupt controller.
*
* Parameters:
* None
* Return:
* None
*
+* Side Effects:
+* If interrupts are enabled and the interrupt is set up properly, the ISR is
+* entered (depending on the priority of this interrupt and other pending
+* interrupts).
+*
*******************************************************************************/
void SCSI_TX_DMA_COMPLETE_SetPending(void)
{
********************************************************************************
*
* Summary:
-* Clears a pending interrupt.
+* Clears a pending interrupt in the interrupt controller.
+*
+* Note Some interrupt sources are clear-on-read and require the block
+* interrupt/status register to be read/cleared with the appropriate block API
+* (GPIO, UART, and so on). Otherwise the ISR will continue to remain in
+* pending state even though the interrupt itself is cleared using this API.
*
* Parameters:
* None
*
*
********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
/*******************************************************************************
* File Name: SDCard.c
-* Version 2.40
+* Version 2.50
*
* Description:
* This file provides all API functionality of the SPI Master component.
* None.
*
********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
#include "SDCard_PVT.h"
#if(SDCard_TX_SOFTWARE_BUF_ENABLED)
- volatile uint8 SDCard_txBuffer[SDCard_TX_BUFFER_SIZE] = {0u};
+ volatile uint8 SDCard_txBuffer[SDCard_TX_BUFFER_SIZE];
volatile uint8 SDCard_txBufferFull;
volatile uint8 SDCard_txBufferRead;
volatile uint8 SDCard_txBufferWrite;
#endif /* (SDCard_TX_SOFTWARE_BUF_ENABLED) */
#if(SDCard_RX_SOFTWARE_BUF_ENABLED)
- volatile uint8 SDCard_rxBuffer[SDCard_RX_BUFFER_SIZE] = {0u};
+ volatile uint8 SDCard_rxBuffer[SDCard_RX_BUFFER_SIZE];
volatile uint8 SDCard_rxBufferFull;
volatile uint8 SDCard_rxBufferRead;
volatile uint8 SDCard_rxBufferWrite;
if((SDCard_txBufferRead == SDCard_txBufferWrite) &&
(0u != (SDCard_swStatusTx & SDCard_STS_TX_FIFO_NOT_FULL)))
{
- /* Add directly to the TX FIFO */
+ /* Put data element into the TX FIFO */
CY_SET_REG8(SDCard_TXDATA_PTR, txData);
}
else
SDCard_EnableTxInt();
#else
-
+ /* Wait until TX FIFO has a place */
while(0u == (SDCard_TX_STATUS_REG & SDCard_STS_TX_FIFO_NOT_FULL))
{
- ; /* Wait for room in FIFO */
}
- /* Put byte in TX FIFO */
+ /* Put data element into the TX FIFO */
CY_SET_REG8(SDCard_TXDATA_PTR, txData);
#endif /* (SDCard_TX_SOFTWARE_BUF_ENABLED) */
/*******************************************************************************
* File Name: SDCard.h
-* Version 2.40
+* Version 2.50
*
* Description:
* Contains the function prototypes, constants and register definition
* None
*
********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
/* Check to see if required defines such as CY_PSOC5A are available */
/* They are defined starting with cy_boot v3.0 */
#if !defined (CY_PSOC5A)
- #error Component SPI_Master_v2_40 requires cy_boot v3.0 or later
+ #error Component SPI_Master_v2_50 requires cy_boot v3.0 or later
#endif /* (CY_PSOC5A) */
{
uint8 enableState;
uint8 cntrPeriod;
- #if(CY_UDB_V0)
- uint8 saveSrTxIntMask;
- uint8 saveSrRxIntMask;
- #endif /* (CY_UDB_V0) */
-
} SDCard_BACKUP_STRUCT;
CY_ISR_PROTO(SDCard_RX_ISR);
-/**********************************
+/***************************************
* Variable with external linkage
-**********************************/
+***************************************/
extern uint8 SDCard_initVar;
/***************************************
* Registers
***************************************/
-
#if(CY_PSOC3 || CY_PSOC5)
#define SDCard_TXDATA_REG (* (reg8 *) \
SDCard_BSPIM_sR8_Dp_u0__F0_REG)
SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG)
#define SDCard_RXDATA_REG (* (reg16 *) \
SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG)
- #define SDCard_RXDATA_PTR ( (reg16 *) \
+ #define SDCard_RXDATA_PTR ( (reg16 *) \
SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG)
#else
#define SDCard_TXDATA_REG (* (reg8 *) \
#define SDCard_RX_STATUS_PTR ( (reg8 *) SDCard_BSPIM_RxStsReg__STATUS_REG)
#define SDCard_CONTROL_REG (* (reg8 *) \
- SDCard_BSPIM_BidirMode_SyncCtl_CtrlReg__CONTROL_REG)
+ SDCard_BSPIM_BidirMode_CtrlReg__CONTROL_REG)
#define SDCard_CONTROL_PTR ( (reg8 *) \
- SDCard_BSPIM_BidirMode_SyncCtl_CtrlReg__CONTROL_REG)
+ SDCard_BSPIM_BidirMode_CtrlReg__CONTROL_REG)
#define SDCard_TX_STATUS_MASK_REG (* (reg8 *) SDCard_BSPIM_TxStsReg__MASK_REG)
#define SDCard_TX_STATUS_MASK_PTR ( (reg8 *) SDCard_BSPIM_TxStsReg__MASK_REG)
/***************************************
-* Obsolete definitions
+* The following code is DEPRECATED and
+* should not be used in new projects.
***************************************/
-/* Following definitions are for version compatibility.
-* They are obsolete in SPIM v2_30.
-* Please do not use it in new projects
-*/
-
#define SDCard_WriteByte SDCard_WriteTxData
#define SDCard_ReadByte SDCard_ReadRxData
void SDCard_SetInterruptMode(uint8 intSrc) ;
void SDCard_EnableInt(void) ;
void SDCard_DisableInt(void) ;
-/* Obsolete register names. Not to be used in new designs */
#define SDCard_TXDATA (SDCard_TXDATA_REG)
#define SDCard_RXDATA (SDCard_RXDATA_REG)
#define SDCard_AUX_CONTROLDP0 (SDCard_AUX_CONTROL_DP0_REG)
SDCard_INT_ON_RX_OVER | \
SDCard_INT_ON_BYTE_COMP)
-/* Following definitions are for version Compatibility.
-* They are obsolete in SPIM v2_40.
-* Please do not use it in new projects
-*/
-
#define SDCard_DataWidth (SDCard_DATA_WIDTH)
#define SDCard_InternalClockUsed (SDCard_INTERNAL_CLOCK)
#define SDCard_InternalTxInterruptEnabled (SDCard_INTERNAL_TX_INT_ENABLED)
/*******************************************************************************
* File Name: SDCard_INT.c
-* Version 2.40
+* Version 2.50
*
* Description:
* This file provides all Interrupt Service Routine (ISR) for the SPI Master
* None.
*
********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
SDCard_txBufferFull = 0u;
}
- /* Move data from the Buffer to the FIFO */
- CY_SET_REG8(SDCard_TXDATA_PTR,
- SDCard_txBuffer[SDCard_txBufferRead]);
+ /* Put data element into the TX FIFO */
+ CY_SET_REG8(SDCard_TXDATA_PTR,
+ SDCard_txBuffer[SDCard_txBufferRead]);
}
else
{
/*******************************************************************************
* File Name: SDCard_PM.c
-* Version 2.40
+* Version 2.50
*
* Description:
* This file contains the setup, control and status commands to support
* Note:
*
********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
{
SDCard_DISABLED,
SDCard_BITCTR_INIT,
- #if(CY_UDB_V0)
- SDCard_TX_INIT_INTERRUPTS_MASK,
- SDCard_RX_INIT_INTERRUPTS_MASK
- #endif /* CY_UDB_V0 */
};
********************************************************************************
*
* Summary:
-* Saves SPIM configuration.
+* Empty function. Included for consistency with other components.
*
* Parameters:
* None.
* Return:
* None.
*
-* Global Variables:
-* SDCard_backup - modified when non-retention registers are saved.
-*
-* Reentrant:
-* No.
-*
*******************************************************************************/
void SDCard_SaveConfig(void)
{
- /* Store Status Mask registers */
- #if(CY_UDB_V0)
- SDCard_backup.cntrPeriod = SDCard_COUNTER_PERIOD_REG;
- SDCard_backup.saveSrTxIntMask = SDCard_TX_STATUS_MASK_REG;
- SDCard_backup.saveSrRxIntMask = SDCard_RX_STATUS_MASK_REG;
- #endif /* (CY_UDB_V0) */
+
}
********************************************************************************
*
* Summary:
-* Restores SPIM configuration.
+* Empty function. Included for consistency with other components.
*
* Parameters:
* None.
* Return:
* None.
*
-* Global Variables:
-* SDCard_backup - used when non-retention registers are restored.
-*
-* Side Effects:
-* If this API is called without first calling SaveConfig then in the following
-* registers will be default values from Customizer:
-* SDCard_STATUS_MASK_REG and SDCard_COUNTER_PERIOD_REG.
-*
*******************************************************************************/
void SDCard_RestoreConfig(void)
{
- /* Restore the data, saved by SaveConfig() function */
- #if(CY_UDB_V0)
- SDCard_COUNTER_PERIOD_REG = SDCard_backup.cntrPeriod;
- SDCard_TX_STATUS_MASK_REG = ((uint8) SDCard_backup.saveSrTxIntMask);
- SDCard_RX_STATUS_MASK_REG = ((uint8) SDCard_backup.saveSrRxIntMask);
- #endif /* (CY_UDB_V0) */
+
}
SDCard_backup.enableState = ((uint8) SDCard_IS_ENABLED);
SDCard_Stop();
- SDCard_SaveConfig();
}
*******************************************************************************/
void SDCard_Wakeup(void)
{
- SDCard_RestoreConfig();
-
#if(SDCard_RX_SOFTWARE_BUF_ENABLED)
SDCard_rxBufferFull = 0u;
SDCard_rxBufferRead = 0u;
/*******************************************************************************
* File Name: .h
-* Version 2.40
+* Version 2.50
*
* Description:
* This private header file contains internal definitions for the SPIM
* Note:
*
********************************************************************************
-* Copyright 2012, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2012-2015, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
* Note:
*
********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
********************************************************************************
*
* Summary:
-* Set up the interrupt and enable it.
+* Set up the interrupt and enable it. This function disables the interrupt,
+* sets the default interrupt vector, sets the priority from the value in the
+* Design Wide Resources Interrupt Editor, then enables the interrupt to the
+* interrupt controller.
*
* Parameters:
* None
********************************************************************************
*
* Summary:
-* Set up the interrupt and enable it.
+* Sets up the interrupt and enables it. This function disables the interrupt,
+* sets the interrupt vector based on the address passed in, sets the priority
+* from the value in the Design Wide Resources Interrupt Editor, then enables
+* the interrupt to the interrupt controller.
+*
+* When defining ISR functions, the CY_ISR and CY_ISR_PROTO macros should be
+* used to provide consistent definition across compilers:
+*
+* Function definition example:
+* CY_ISR(MyISR)
+* {
+* }
+* Function prototype example:
+* CY_ISR_PROTO(MyISR);
*
* Parameters:
* address: Address of the ISR to set in the interrupt vector table.
* Disables and removes the interrupt.
*
* Parameters:
+* None
*
* Return:
* None
* Change the ISR vector for the Interrupt. Note calling SD_RX_DMA_COMPLETE_Start
* will override any effect this method would have had. To set the vector
* before the component has been started use SD_RX_DMA_COMPLETE_StartEx instead.
+*
+* When defining ISR functions, the CY_ISR and CY_ISR_PROTO macros should be
+* used to provide consistent definition across compilers:
+*
+* Function definition example:
+* CY_ISR(MyISR)
+* {
+* }
+*
+* Function prototype example:
+* CY_ISR_PROTO(MyISR);
*
* Parameters:
* address: Address of the ISR to set in the interrupt vector table.
********************************************************************************
*
* Summary:
-* Sets the Priority of the Interrupt. Note calling SD_RX_DMA_COMPLETE_Start
-* or SD_RX_DMA_COMPLETE_StartEx will override any effect this method
-* would have had. This method should only be called after
-* SD_RX_DMA_COMPLETE_Start or SD_RX_DMA_COMPLETE_StartEx has been called. To set
-* the initial priority for the component use the cydwr file in the tool.
+* Sets the Priority of the Interrupt.
+*
+* Note calling SD_RX_DMA_COMPLETE_Start or SD_RX_DMA_COMPLETE_StartEx will
+* override any effect this API would have had. This API should only be called
+* after SD_RX_DMA_COMPLETE_Start or SD_RX_DMA_COMPLETE_StartEx has been called.
+* To set the initial priority for the component, use the Design-Wide Resources
+* Interrupt Editor.
+*
+* Note This API has no effect on Non-maskable interrupt NMI).
*
* Parameters:
-* priority: Priority of the interrupt. 0 - 7, 0 being the highest.
+* priority: Priority of the interrupt, 0 being the highest priority
+* PSoC 3 and PSoC 5LP: Priority is from 0 to 7.
+* PSoC 4: Priority is from 0 to 3.
*
* Return:
* None
* None
*
* Return:
-* Priority of the interrupt. 0 - 7, 0 being the highest.
+* Priority of the interrupt, 0 being the highest priority
+* PSoC 3 and PSoC 5LP: Priority is from 0 to 7.
+* PSoC 4: Priority is from 0 to 3.
*
*******************************************************************************/
uint8 SD_RX_DMA_COMPLETE_GetPriority(void)
********************************************************************************
*
* Summary:
-* Enables the interrupt.
+* Enables the interrupt to the interrupt controller. Do not call this function
+* unless ISR_Start() has been called or the functionality of the ISR_Start()
+* function, which sets the vector and the priority, has been called.
*
* Parameters:
* None
********************************************************************************
*
* Summary:
-* Disables the Interrupt.
+* Disables the Interrupt in the interrupt controller.
*
* Parameters:
* None
* Return:
* None
*
+* Side Effects:
+* If interrupts are enabled and the interrupt is set up properly, the ISR is
+* entered (depending on the priority of this interrupt and other pending
+* interrupts).
+*
*******************************************************************************/
void SD_RX_DMA_COMPLETE_SetPending(void)
{
********************************************************************************
*
* Summary:
-* Clears a pending interrupt.
+* Clears a pending interrupt in the interrupt controller.
+*
+* Note Some interrupt sources are clear-on-read and require the block
+* interrupt/status register to be read/cleared with the appropriate block API
+* (GPIO, UART, and so on). Otherwise the ISR will continue to remain in
+* pending state even though the interrupt itself is cleared using this API.
*
* Parameters:
* None
*
*
********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
* Note:
*
********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
********************************************************************************
*
* Summary:
-* Set up the interrupt and enable it.
+* Set up the interrupt and enable it. This function disables the interrupt,
+* sets the default interrupt vector, sets the priority from the value in the
+* Design Wide Resources Interrupt Editor, then enables the interrupt to the
+* interrupt controller.
*
* Parameters:
* None
********************************************************************************
*
* Summary:
-* Set up the interrupt and enable it.
+* Sets up the interrupt and enables it. This function disables the interrupt,
+* sets the interrupt vector based on the address passed in, sets the priority
+* from the value in the Design Wide Resources Interrupt Editor, then enables
+* the interrupt to the interrupt controller.
+*
+* When defining ISR functions, the CY_ISR and CY_ISR_PROTO macros should be
+* used to provide consistent definition across compilers:
+*
+* Function definition example:
+* CY_ISR(MyISR)
+* {
+* }
+* Function prototype example:
+* CY_ISR_PROTO(MyISR);
*
* Parameters:
* address: Address of the ISR to set in the interrupt vector table.
* Disables and removes the interrupt.
*
* Parameters:
+* None
*
* Return:
* None
* Change the ISR vector for the Interrupt. Note calling SD_TX_DMA_COMPLETE_Start
* will override any effect this method would have had. To set the vector
* before the component has been started use SD_TX_DMA_COMPLETE_StartEx instead.
+*
+* When defining ISR functions, the CY_ISR and CY_ISR_PROTO macros should be
+* used to provide consistent definition across compilers:
+*
+* Function definition example:
+* CY_ISR(MyISR)
+* {
+* }
+*
+* Function prototype example:
+* CY_ISR_PROTO(MyISR);
*
* Parameters:
* address: Address of the ISR to set in the interrupt vector table.
********************************************************************************
*
* Summary:
-* Sets the Priority of the Interrupt. Note calling SD_TX_DMA_COMPLETE_Start
-* or SD_TX_DMA_COMPLETE_StartEx will override any effect this method
-* would have had. This method should only be called after
-* SD_TX_DMA_COMPLETE_Start or SD_TX_DMA_COMPLETE_StartEx has been called. To set
-* the initial priority for the component use the cydwr file in the tool.
+* Sets the Priority of the Interrupt.
+*
+* Note calling SD_TX_DMA_COMPLETE_Start or SD_TX_DMA_COMPLETE_StartEx will
+* override any effect this API would have had. This API should only be called
+* after SD_TX_DMA_COMPLETE_Start or SD_TX_DMA_COMPLETE_StartEx has been called.
+* To set the initial priority for the component, use the Design-Wide Resources
+* Interrupt Editor.
+*
+* Note This API has no effect on Non-maskable interrupt NMI).
*
* Parameters:
-* priority: Priority of the interrupt. 0 - 7, 0 being the highest.
+* priority: Priority of the interrupt, 0 being the highest priority
+* PSoC 3 and PSoC 5LP: Priority is from 0 to 7.
+* PSoC 4: Priority is from 0 to 3.
*
* Return:
* None
* None
*
* Return:
-* Priority of the interrupt. 0 - 7, 0 being the highest.
+* Priority of the interrupt, 0 being the highest priority
+* PSoC 3 and PSoC 5LP: Priority is from 0 to 7.
+* PSoC 4: Priority is from 0 to 3.
*
*******************************************************************************/
uint8 SD_TX_DMA_COMPLETE_GetPriority(void)
********************************************************************************
*
* Summary:
-* Enables the interrupt.
+* Enables the interrupt to the interrupt controller. Do not call this function
+* unless ISR_Start() has been called or the functionality of the ISR_Start()
+* function, which sets the vector and the priority, has been called.
*
* Parameters:
* None
********************************************************************************
*
* Summary:
-* Disables the Interrupt.
+* Disables the Interrupt in the interrupt controller.
*
* Parameters:
* None
* Return:
* None
*
+* Side Effects:
+* If interrupts are enabled and the interrupt is set up properly, the ISR is
+* entered (depending on the priority of this interrupt and other pending
+* interrupts).
+*
*******************************************************************************/
void SD_TX_DMA_COMPLETE_SetPending(void)
{
********************************************************************************
*
* Summary:
-* Clears a pending interrupt.
+* Clears a pending interrupt in the interrupt controller.
+*
+* Note Some interrupt sources are clear-on-read and require the block
+* interrupt/status register to be read/cleared with the appropriate block API
+* (GPIO, UART, and so on). Otherwise the ISR will continue to remain in
+* pending state even though the interrupt itself is cleared using this API.
*
* Parameters:
* None
*
*
********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
/*******************************************************************************
* FILENAME: cydevice.h
* OBSOLETE: Do not use this file. Use the _trm version instead.
-* PSoC Creator 3.1
+* PSoC Creator 3.2
*
* DESCRIPTION:
* This file provides all of the address values for the entire PSoC device.
* This file is automatically generated by PSoC Creator.
*
********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright (c) 2007-2015 Cypress Semiconductor. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
/*******************************************************************************
* FILENAME: cydevice_trm.h
*
-* PSoC Creator 3.1
+* PSoC Creator 3.2
*
* DESCRIPTION:
* This file provides all of the address values for the entire PSoC device.
* This file is automatically generated by PSoC Creator.
*
********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright (c) 2007-2015 Cypress Semiconductor. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
/*******************************************************************************
* FILENAME: cydevicegnu.inc
* OBSOLETE: Do not use this file. Use the _trm version instead.
-* PSoC Creator 3.1
+* PSoC Creator 3.2
*
* DESCRIPTION:
* This file provides all of the address values for the entire PSoC device.
* This file is automatically generated by PSoC Creator.
*
********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright (c) 2007-2015 Cypress Semiconductor. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
/*******************************************************************************
* FILENAME: cydevicegnu_trm.inc
*
-* PSoC Creator 3.1
+* PSoC Creator 3.2
*
* DESCRIPTION:
* This file provides all of the address values for the entire PSoC device.
* This file is automatically generated by PSoC Creator.
*
********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright (c) 2007-2015 Cypress Semiconductor. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
;
; FILENAME: cydeviceiar.inc
; OBSOLETE: Do not use this file. Use the _trm version instead.
-; PSoC Creator 3.1
+; PSoC Creator 3.2
;
; DESCRIPTION:
; This file provides all of the address values for the entire PSoC device.
;
;-------------------------------------------------------------------------------
-; Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.
+; Copyright (c) 2007-2015 Cypress Semiconductor. All rights reserved.
; You may use this file only in accordance with the license, terms, conditions,
; disclaimers, and limitations in the end user license agreement accompanying
; the software package with which this file was provided.
;
; FILENAME: cydeviceiar_trm.inc
;
-; PSoC Creator 3.1
+; PSoC Creator 3.2
;
; DESCRIPTION:
; This file provides all of the address values for the entire PSoC device.
;
;-------------------------------------------------------------------------------
-; Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.
+; Copyright (c) 2007-2015 Cypress Semiconductor. All rights reserved.
; You may use this file only in accordance with the license, terms, conditions,
; disclaimers, and limitations in the end user license agreement accompanying
; the software package with which this file was provided.
;
; FILENAME: cydevicerv.inc
; OBSOLETE: Do not use this file. Use the _trm version instead.
-; PSoC Creator 3.1
+; PSoC Creator 3.2
;
; DESCRIPTION:
; This file provides all of the address values for the entire PSoC device.
;
;-------------------------------------------------------------------------------
-; Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.
+; Copyright (c) 2007-2015 Cypress Semiconductor. All rights reserved.
; You may use this file only in accordance with the license, terms, conditions,
; disclaimers, and limitations in the end user license agreement accompanying
; the software package with which this file was provided.
;
; FILENAME: cydevicerv_trm.inc
;
-; PSoC Creator 3.1
+; PSoC Creator 3.2
;
; DESCRIPTION:
; This file provides all of the address values for the entire PSoC device.
;
;-------------------------------------------------------------------------------
-; Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.
+; Copyright (c) 2007-2015 Cypress Semiconductor. All rights reserved.
; You may use this file only in accordance with the license, terms, conditions,
; disclaimers, and limitations in the end user license agreement accompanying
; the software package with which this file was provided.
#ifndef INCLUDED_CYFITTER_H
#define INCLUDED_CYFITTER_H
-#include <cydevice.h>
-#include <cydevice_trm.h>
+#include "cydevice.h"
+#include "cydevice_trm.h"
/* LED1 */
#define LED1__0__MASK 0x02u
#define EXTLED__SLW CYREG_PRT0_SLW
/* SDCard_BSPIM */
-#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB06_07_ACTL
-#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB06_07_CTL
-#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB06_07_CTL
-#define SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB06_07_CTL
-#define SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B1_UDB06_07_CTL
-#define SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B1_UDB06_07_MSK
-#define SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B1_UDB06_07_MSK
-#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B1_UDB06_07_MSK
-#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB06_07_MSK
-#define SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B1_UDB06_ACTL
-#define SDCard_BSPIM_BitCounter__CONTROL_REG CYREG_B1_UDB06_CTL
-#define SDCard_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B1_UDB06_ST_CTL
-#define SDCard_BSPIM_BitCounter__COUNT_REG CYREG_B1_UDB06_CTL
-#define SDCard_BSPIM_BitCounter__COUNT_ST_REG CYREG_B1_UDB06_ST_CTL
-#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL
-#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL
-#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B1_UDB06_MSK
-#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB06_07_ACTL
-#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B1_UDB06_07_ST
-#define SDCard_BSPIM_BitCounter_ST__MASK_REG CYREG_B1_UDB06_MSK
-#define SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL
-#define SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL
-#define SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B1_UDB06_ACTL
-#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B1_UDB06_ST_CTL
-#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B1_UDB06_ST_CTL
-#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B1_UDB06_ST
-#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB04_05_ACTL
-#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B1_UDB04_05_ST
+#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB12_13_ACTL
+#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB12_13_CTL
+#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB12_13_CTL
+#define SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB12_13_CTL
+#define SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B0_UDB12_13_CTL
+#define SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B0_UDB12_13_MSK
+#define SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B0_UDB12_13_MSK
+#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B0_UDB12_13_MSK
+#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB12_13_MSK
+#define SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B0_UDB12_ACTL
+#define SDCard_BSPIM_BitCounter__CONTROL_REG CYREG_B0_UDB12_CTL
+#define SDCard_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B0_UDB12_ST_CTL
+#define SDCard_BSPIM_BitCounter__COUNT_REG CYREG_B0_UDB12_CTL
+#define SDCard_BSPIM_BitCounter__COUNT_ST_REG CYREG_B0_UDB12_ST_CTL
+#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL
+#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL
+#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B0_UDB12_MSK
+#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB12_13_ACTL
+#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B0_UDB12_13_ST
+#define SDCard_BSPIM_BitCounter_ST__MASK_REG CYREG_B0_UDB12_MSK
+#define SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL
+#define SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL
+#define SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B0_UDB12_ACTL
+#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B0_UDB12_ST_CTL
+#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B0_UDB12_ST_CTL
+#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B0_UDB12_ST
+#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB07_08_ACTL
+#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B1_UDB07_08_ST
#define SDCard_BSPIM_RxStsReg__4__MASK 0x10u
#define SDCard_BSPIM_RxStsReg__4__POS 4
#define SDCard_BSPIM_RxStsReg__5__MASK 0x20u
#define SDCard_BSPIM_RxStsReg__6__MASK 0x40u
#define SDCard_BSPIM_RxStsReg__6__POS 6
#define SDCard_BSPIM_RxStsReg__MASK 0x70u
-#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B1_UDB04_MSK
-#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB04_ACTL
-#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B1_UDB04_ST
+#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B1_UDB07_MSK
+#define SDCard_BSPIM_RxStsReg__MASK_ST_AUX_CTL_REG CYREG_B1_UDB07_MSK_ACTL
+#define SDCard_BSPIM_RxStsReg__PER_ST_AUX_CTL_REG CYREG_B1_UDB07_MSK_ACTL
+#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB07_ACTL
+#define SDCard_BSPIM_RxStsReg__STATUS_CNT_REG CYREG_B1_UDB07_ST_CTL
+#define SDCard_BSPIM_RxStsReg__STATUS_CONTROL_REG CYREG_B1_UDB07_ST_CTL
+#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B1_UDB07_ST
#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B1_UDB04_05_A0
#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B1_UDB04_05_A1
#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG CYREG_B1_UDB04_05_D0
#define SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG CYREG_B1_UDB04_F0_F1
#define SDCard_BSPIM_sR8_Dp_u0__F0_REG CYREG_B1_UDB04_F0
#define SDCard_BSPIM_sR8_Dp_u0__F1_REG CYREG_B1_UDB04_F1
+#define SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL
+#define SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL
#define SDCard_BSPIM_TxStsReg__0__MASK 0x01u
#define SDCard_BSPIM_TxStsReg__0__POS 0
#define SDCard_BSPIM_TxStsReg__1__MASK 0x02u
#define SDCard_BSPIM_TxStsReg__1__POS 1
-#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB07_08_ACTL
-#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B1_UDB07_08_ST
#define SDCard_BSPIM_TxStsReg__2__MASK 0x04u
#define SDCard_BSPIM_TxStsReg__2__POS 2
#define SDCard_BSPIM_TxStsReg__3__MASK 0x08u
#define SDCard_BSPIM_TxStsReg__4__MASK 0x10u
#define SDCard_BSPIM_TxStsReg__4__POS 4
#define SDCard_BSPIM_TxStsReg__MASK 0x1Fu
-#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B1_UDB07_MSK
-#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB07_ACTL
-#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B1_UDB07_ST
+#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B1_UDB11_MSK
+#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB11_ACTL
+#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B1_UDB11_ST
/* SD_SCK */
#define SD_SCK__0__MASK 0x04u
#define SCSI_Out_Bits_Sync_ctrl_reg__0__POS 0
#define SCSI_Out_Bits_Sync_ctrl_reg__1__MASK 0x02u
#define SCSI_Out_Bits_Sync_ctrl_reg__1__POS 1
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB11_12_ACTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB11_12_CTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB11_12_CTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB11_12_CTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB11_12_CTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB11_12_MSK
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB11_12_MSK
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB11_12_MSK
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB11_12_MSK
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB07_08_ACTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB07_08_CTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB07_08_CTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB07_08_CTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B1_UDB07_08_CTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B1_UDB07_08_MSK
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B1_UDB07_08_MSK
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B1_UDB07_08_MSK
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB07_08_MSK
#define SCSI_Out_Bits_Sync_ctrl_reg__2__MASK 0x04u
#define SCSI_Out_Bits_Sync_ctrl_reg__2__POS 2
#define SCSI_Out_Bits_Sync_ctrl_reg__3__MASK 0x08u
#define SCSI_Out_Bits_Sync_ctrl_reg__6__POS 6
#define SCSI_Out_Bits_Sync_ctrl_reg__7__MASK 0x80u
#define SCSI_Out_Bits_Sync_ctrl_reg__7__POS 7
-#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB11_ACTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB11_CTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB11_ST_CTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB11_CTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB11_ST_CTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B1_UDB07_ACTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG CYREG_B1_UDB07_CTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B1_UDB07_ST_CTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG CYREG_B1_UDB07_CTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG CYREG_B1_UDB07_ST_CTL
#define SCSI_Out_Bits_Sync_ctrl_reg__MASK 0xFFu
-#define SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB11_MSK
+#define SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB07_MSK_ACTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B1_UDB07_MSK_ACTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG CYREG_B1_UDB07_MSK
/* SCSI_Out_Ctl */
#define SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK 0x01u
#define SCSI_Out_Ctl_Sync_ctrl_reg__0__POS 0
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB08_09_ACTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB08_09_CTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB08_09_CTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB08_09_CTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB08_09_CTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB08_09_MSK
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB08_09_MSK
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB08_09_MSK
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB08_09_MSK
-#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB08_ACTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB08_CTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB08_ST_CTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB08_CTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB08_ST_CTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB04_05_ACTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB04_05_CTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB04_05_CTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB04_05_CTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B1_UDB04_05_CTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B1_UDB04_05_MSK
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B1_UDB04_05_MSK
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B1_UDB04_05_MSK
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB04_05_MSK
+#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B1_UDB04_ACTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B1_UDB04_CTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B1_UDB04_ST_CTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B1_UDB04_CTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B1_UDB04_ST_CTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK 0x01u
-#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB08_MSK
+#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B1_UDB04_MSK
/* SCSI_Out_DBx */
#define SCSI_Out_DBx__0__AG CYREG_PRT5_AG
#define SCSI_Filtered_sts_sts_reg__0__POS 0
#define SCSI_Filtered_sts_sts_reg__1__MASK 0x02u
#define SCSI_Filtered_sts_sts_reg__1__POS 1
-#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB08_09_ACTL
-#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB08_09_ST
+#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB11_12_ACTL
+#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB11_12_ST
#define SCSI_Filtered_sts_sts_reg__2__MASK 0x04u
#define SCSI_Filtered_sts_sts_reg__2__POS 2
#define SCSI_Filtered_sts_sts_reg__3__MASK 0x08u
#define SCSI_Filtered_sts_sts_reg__4__MASK 0x10u
#define SCSI_Filtered_sts_sts_reg__4__POS 4
#define SCSI_Filtered_sts_sts_reg__MASK 0x1Fu
-#define SCSI_Filtered_sts_sts_reg__MASK_REG CYREG_B0_UDB08_MSK
-#define SCSI_Filtered_sts_sts_reg__MASK_ST_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL
-#define SCSI_Filtered_sts_sts_reg__PER_ST_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL
-#define SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB08_ACTL
-#define SCSI_Filtered_sts_sts_reg__STATUS_CNT_REG CYREG_B0_UDB08_ST_CTL
-#define SCSI_Filtered_sts_sts_reg__STATUS_CONTROL_REG CYREG_B0_UDB08_ST_CTL
-#define SCSI_Filtered_sts_sts_reg__STATUS_REG CYREG_B0_UDB08_ST
+#define SCSI_Filtered_sts_sts_reg__MASK_REG CYREG_B0_UDB11_MSK
+#define SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB11_ACTL
+#define SCSI_Filtered_sts_sts_reg__STATUS_REG CYREG_B0_UDB11_ST
/* SCSI_CTL_PHASE */
#define SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK 0x01u
#define SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS 0
#define SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK 0x02u
#define SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS 1
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB02_03_ACTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB02_03_CTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB02_03_CTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB02_03_CTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB02_03_CTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB02_03_MSK
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB02_03_MSK
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB02_03_MSK
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB02_03_MSK
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB05_06_ACTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB05_06_CTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB05_06_CTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB05_06_CTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB05_06_CTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB05_06_MSK
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB05_06_MSK
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB05_06_MSK
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB05_06_MSK
#define SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK 0x04u
#define SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS 2
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB02_ACTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB02_CTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB02_ST_CTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB02_CTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB02_ST_CTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB05_ACTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB05_CTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB05_ST_CTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB05_CTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB05_ST_CTL
#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK 0x07u
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB02_MSK_ACTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB02_MSK_ACTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB02_MSK
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB05_MSK
/* SCSI_Glitch_Ctl */
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK 0x01u
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS 0
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB10_11_ACTL
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB10_11_CTL
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB10_11_CTL
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB10_11_CTL
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB10_11_CTL
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB10_11_MSK
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB10_11_MSK
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB10_11_MSK
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB10_11_MSK
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB10_ACTL
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB10_CTL
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB10_ST_CTL
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB10_CTL
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB10_ST_CTL
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB06_07_ACTL
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB06_07_CTL
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB06_07_CTL
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB06_07_CTL
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB06_07_CTL
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB06_07_MSK
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB06_07_MSK
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB06_07_MSK
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB06_07_MSK
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB06_ACTL
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB06_CTL
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB06_ST_CTL
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB06_CTL
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB06_ST_CTL
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK 0x01u
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB10_MSK_ACTL
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB10_MSK_ACTL
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB10_MSK
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB06_MSK
/* SCSI_Parity_Error */
#define SCSI_Parity_Error_sts_sts_reg__0__MASK 0x01u
#define SCSI_Parity_Error_sts_sts_reg__0__POS 0
-#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB09_10_ACTL
-#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB09_10_ST
+#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB10_11_ACTL
+#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB10_11_ST
#define SCSI_Parity_Error_sts_sts_reg__MASK 0x01u
-#define SCSI_Parity_Error_sts_sts_reg__MASK_REG CYREG_B0_UDB09_MSK
-#define SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB09_ACTL
-#define SCSI_Parity_Error_sts_sts_reg__STATUS_REG CYREG_B0_UDB09_ST
+#define SCSI_Parity_Error_sts_sts_reg__MASK_REG CYREG_B0_UDB10_MSK
+#define SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB10_ACTL
+#define SCSI_Parity_Error_sts_sts_reg__STATUS_REG CYREG_B0_UDB10_ST
/* Miscellaneous */
#define BCLK__BUS_CLK__HZ 50000000U
#define BCLK__BUS_CLK__KHZ 50000U
#define BCLK__BUS_CLK__MHZ 50U
-#define CY_VERSION "PSoC Creator 3.1"
+#define CY_PROJECT_NAME "SCSI2SD"
+#define CY_VERSION "PSoC Creator 3.2"
+#define CYDEV_CHIP_DIE_GEN4 2u
#define CYDEV_CHIP_DIE_LEOPARD 1u
-#define CYDEV_CHIP_DIE_PANTHER 6u
-#define CYDEV_CHIP_DIE_PSOC4A 3u
-#define CYDEV_CHIP_DIE_PSOC5LP 5u
+#define CYDEV_CHIP_DIE_PANTHER 12u
+#define CYDEV_CHIP_DIE_PSOC4A 5u
+#define CYDEV_CHIP_DIE_PSOC5LP 11u
#define CYDEV_CHIP_DIE_UNKNOWN 0u
#define CYDEV_CHIP_FAMILY_PSOC3 1u
#define CYDEV_CHIP_FAMILY_PSOC4 2u
#define CYDEV_CHIP_FAMILY_USED CYDEV_CHIP_FAMILY_PSOC5
#define CYDEV_CHIP_JTAG_ID 0x2E133069u
#define CYDEV_CHIP_MEMBER_3A 1u
-#define CYDEV_CHIP_MEMBER_4A 3u
-#define CYDEV_CHIP_MEMBER_4D 2u
-#define CYDEV_CHIP_MEMBER_4F 4u
-#define CYDEV_CHIP_MEMBER_5A 6u
-#define CYDEV_CHIP_MEMBER_5B 5u
+#define CYDEV_CHIP_MEMBER_4A 5u
+#define CYDEV_CHIP_MEMBER_4C 9u
+#define CYDEV_CHIP_MEMBER_4D 3u
+#define CYDEV_CHIP_MEMBER_4E 4u
+#define CYDEV_CHIP_MEMBER_4F 6u
+#define CYDEV_CHIP_MEMBER_4G 2u
+#define CYDEV_CHIP_MEMBER_4L 8u
+#define CYDEV_CHIP_MEMBER_4M 7u
+#define CYDEV_CHIP_MEMBER_5A 11u
+#define CYDEV_CHIP_MEMBER_5B 10u
#define CYDEV_CHIP_MEMBER_UNKNOWN 0u
#define CYDEV_CHIP_MEMBER_USED CYDEV_CHIP_MEMBER_5B
#define CYDEV_CHIP_DIE_EXPECT CYDEV_CHIP_MEMBER_USED
#define CYDEV_CHIP_DIE_ACTUAL CYDEV_CHIP_DIE_EXPECT
+#define CYDEV_CHIP_REV_GEN4_ES 17u
+#define CYDEV_CHIP_REV_GEN4_ES2 33u
+#define CYDEV_CHIP_REV_GEN4_PRODUCTION 17u
#define CYDEV_CHIP_REV_LEOPARD_ES1 0u
#define CYDEV_CHIP_REV_LEOPARD_ES2 1u
#define CYDEV_CHIP_REV_LEOPARD_ES3 3u
#define CYDEV_CHIP_REVISION_3A_PRODUCTION 3u
#define CYDEV_CHIP_REVISION_4A_ES0 17u
#define CYDEV_CHIP_REVISION_4A_PRODUCTION 17u
+#define CYDEV_CHIP_REVISION_4C_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_4D_PRODUCTION 0u
+#define CYDEV_CHIP_REVISION_4E_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_4F_PRODUCTION 0u
+#define CYDEV_CHIP_REVISION_4F_PRODUCTION_256K 0u
+#define CYDEV_CHIP_REVISION_4G_ES 17u
+#define CYDEV_CHIP_REVISION_4G_ES2 33u
+#define CYDEV_CHIP_REVISION_4G_PRODUCTION 17u
+#define CYDEV_CHIP_REVISION_4L_PRODUCTION 0u
+#define CYDEV_CHIP_REVISION_4M_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_5A_ES0 0u
#define CYDEV_CHIP_REVISION_5A_ES1 1u
#define CYDEV_CHIP_REVISION_5A_PRODUCTION 1u
#define CYDEV_CONFIGURATION_MODE_UNCOMPRESSED 1
#define CYDEV_DEBUG_ENABLE_MASK 0x20u
#define CYDEV_DEBUG_ENABLE_REGISTER CYREG_MLOGIC_DEBUG
-#define CYDEV_DEBUGGING_DPS_Disable 3
-#define CYDEV_DEBUGGING_DPS_JTAG_4 1
-#define CYDEV_DEBUGGING_DPS_JTAG_5 0
#define CYDEV_DEBUGGING_DPS_SWD 2
#define CYDEV_DEBUGGING_DPS_SWD_SWV 6
#define CYDEV_DEBUGGING_DPS CYDEV_DEBUGGING_DPS_SWD_SWV
#define CYDEV_INTR_RISING 0x0000007Eu
#define CYDEV_PROJ_TYPE 2
#define CYDEV_PROJ_TYPE_BOOTLOADER 1
+#define CYDEV_PROJ_TYPE_LAUNCHER 5
#define CYDEV_PROJ_TYPE_LOADABLE 2
+#define CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER 4
#define CYDEV_PROJ_TYPE_MULTIAPPBOOTLOADER 3
#define CYDEV_PROJ_TYPE_STANDARD 0
#define CYDEV_PROTECTION_ENABLE 0
/*******************************************************************************
* FILENAME: cyfitter_cfg.c
-* PSoC Creator 3.1
+*
+* PSoC Creator 3.2
*
-* Description:
-* This file is automatically generated by PSoC Creator with device
-* initialization code. Except for the user defined sections in
-* CyClockStartupError(), this file should not be modified.
+* DESCRIPTION:
+* This file contains device initialization code.
+* Except for the user defined sections in CyClockStartupError(), this file should not be modified.
+* This file is automatically generated by PSoC Creator.
*
********************************************************************************
-* Copyright 2013, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright (c) 2007-2015 Cypress Semiconductor. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
********************************************************************************/
#include <string.h>
-#include <cytypes.h>
-#include <cydevice_trm.h>
-#include <cyfitter.h>
-#include <CyLib.h>
-#include <cyfitter_cfg.h>
+#include "cytypes.h"
+#include "cydevice_trm.h"
+#include "cyfitter.h"
+#include "CyLib.h"
+#include "cyfitter_cfg.h"
#define CY_NEED_CYCLOCKSTARTUPERROR 1
}
#endif
-#define CY_CFG_BASE_ADDR_COUNT 41u
+#define CY_CFG_BASE_ADDR_COUNT 40u
CYPACKED typedef struct
{
uint8 offset;
0x40004501u, /* Base address: 0x40004500 Count: 1 */
0x40004F02u, /* Base address: 0x40004F00 Count: 2 */
0x40005210u, /* Base address: 0x40005200 Count: 16 */
- 0x40006401u, /* Base address: 0x40006400 Count: 1 */
- 0x40006501u, /* Base address: 0x40006500 Count: 1 */
- 0x40010048u, /* Base address: 0x40010000 Count: 72 */
- 0x40010145u, /* Base address: 0x40010100 Count: 69 */
- 0x40010244u, /* Base address: 0x40010200 Count: 68 */
- 0x40010362u, /* Base address: 0x40010300 Count: 98 */
+ 0x40006402u, /* Base address: 0x40006400 Count: 2 */
+ 0x4001003Du, /* Base address: 0x40010000 Count: 61 */
+ 0x4001013Du, /* Base address: 0x40010100 Count: 61 */
+ 0x40010240u, /* Base address: 0x40010200 Count: 64 */
+ 0x4001034Fu, /* Base address: 0x40010300 Count: 79 */
0x4001044Cu, /* Base address: 0x40010400 Count: 76 */
0x4001055Eu, /* Base address: 0x40010500 Count: 94 */
- 0x4001064Bu, /* Base address: 0x40010600 Count: 75 */
- 0x40010759u, /* Base address: 0x40010700 Count: 89 */
- 0x4001084Eu, /* Base address: 0x40010800 Count: 78 */
- 0x40010955u, /* Base address: 0x40010900 Count: 85 */
- 0x40010A47u, /* Base address: 0x40010A00 Count: 71 */
- 0x40010B58u, /* Base address: 0x40010B00 Count: 88 */
- 0x40010C4Fu, /* Base address: 0x40010C00 Count: 79 */
- 0x40010D49u, /* Base address: 0x40010D00 Count: 73 */
- 0x40010F08u, /* Base address: 0x40010F00 Count: 8 */
- 0x40011417u, /* Base address: 0x40011400 Count: 23 */
- 0x4001154Eu, /* Base address: 0x40011500 Count: 78 */
- 0x4001164Du, /* Base address: 0x40011600 Count: 77 */
- 0x4001175Bu, /* Base address: 0x40011700 Count: 91 */
- 0x40011918u, /* Base address: 0x40011900 Count: 24 */
- 0x40011A04u, /* Base address: 0x40011A00 Count: 4 */
- 0x40011B12u, /* Base address: 0x40011B00 Count: 18 */
- 0x40014015u, /* Base address: 0x40014000 Count: 21 */
- 0x4001411Du, /* Base address: 0x40014100 Count: 29 */
- 0x40014213u, /* Base address: 0x40014200 Count: 19 */
- 0x4001430Bu, /* Base address: 0x40014300 Count: 11 */
- 0x4001440Eu, /* Base address: 0x40014400 Count: 14 */
+ 0x40010656u, /* Base address: 0x40010600 Count: 86 */
+ 0x4001075Bu, /* Base address: 0x40010700 Count: 91 */
+ 0x40010923u, /* Base address: 0x40010900 Count: 35 */
+ 0x40010A51u, /* Base address: 0x40010A00 Count: 81 */
+ 0x40010B54u, /* Base address: 0x40010B00 Count: 84 */
+ 0x40010C4Eu, /* Base address: 0x40010C00 Count: 78 */
+ 0x40010D4Au, /* Base address: 0x40010D00 Count: 74 */
+ 0x40010E04u, /* Base address: 0x40010E00 Count: 4 */
+ 0x40010F07u, /* Base address: 0x40010F00 Count: 7 */
+ 0x40011422u, /* Base address: 0x40011400 Count: 34 */
+ 0x40011552u, /* Base address: 0x40011500 Count: 82 */
+ 0x40011646u, /* Base address: 0x40011600 Count: 70 */
+ 0x40011750u, /* Base address: 0x40011700 Count: 80 */
+ 0x40011916u, /* Base address: 0x40011900 Count: 22 */
+ 0x40011A50u, /* Base address: 0x40011A00 Count: 80 */
+ 0x40011B49u, /* Base address: 0x40011B00 Count: 73 */
+ 0x40014016u, /* Base address: 0x40014000 Count: 22 */
+ 0x4001411Cu, /* Base address: 0x40014100 Count: 28 */
+ 0x4001421Au, /* Base address: 0x40014200 Count: 26 */
+ 0x4001430Du, /* Base address: 0x40014300 Count: 13 */
+ 0x40014410u, /* Base address: 0x40014400 Count: 16 */
0x40014516u, /* Base address: 0x40014500 Count: 22 */
- 0x40014617u, /* Base address: 0x40014600 Count: 23 */
- 0x4001470Eu, /* Base address: 0x40014700 Count: 14 */
- 0x4001480Au, /* Base address: 0x40014800 Count: 10 */
- 0x4001490Bu, /* Base address: 0x40014900 Count: 11 */
- 0x40014C0Du, /* Base address: 0x40014C00 Count: 13 */
- 0x40014D0Eu, /* Base address: 0x40014D00 Count: 14 */
- 0x40015002u, /* Base address: 0x40015000 Count: 2 */
+ 0x40014614u, /* Base address: 0x40014600 Count: 20 */
+ 0x40014713u, /* Base address: 0x40014700 Count: 19 */
+ 0x40014808u, /* Base address: 0x40014800 Count: 8 */
+ 0x4001490Au, /* Base address: 0x40014900 Count: 10 */
+ 0x40014C09u, /* Base address: 0x40014C00 Count: 9 */
+ 0x40014D0Cu, /* Base address: 0x40014D00 Count: 12 */
+ 0x40015005u, /* Base address: 0x40015000 Count: 5 */
0x40015104u, /* Base address: 0x40015100 Count: 4 */
};
static const cy_cfg_addrvalue_t CYCODE cy_cfg_data_table[] = {
{0x7Eu, 0x02u},
{0x01u, 0x20u},
- {0x0Au, 0x36u},
- {0x00u, 0x44u},
- {0x01u, 0x01u},
+ {0x0Au, 0x4Bu},
+ {0x00u, 0x01u},
+ {0x01u, 0x48u},
{0x04u, 0x31u},
- {0x10u, 0x48u},
- {0x11u, 0x0Cu},
+ {0x10u, 0x84u},
+ {0x11u, 0x08u},
{0x18u, 0x04u},
{0x19u, 0x08u},
{0x1Cu, 0x30u},
- {0x21u, 0x10u},
+ {0x20u, 0x10u},
{0x24u, 0x44u},
{0x28u, 0x02u},
- {0x29u, 0x02u},
- {0x31u, 0x10u},
+ {0x29u, 0x01u},
+ {0x30u, 0x20u},
+ {0x31u, 0x30u},
{0x78u, 0x20u},
- {0x79u, 0x20u},
{0x7Cu, 0x40u},
{0x20u, 0x02u},
- {0x86u, 0x0Fu},
- {0x00u, 0x01u},
- {0x01u, 0x03u},
- {0x03u, 0x0Cu},
- {0x07u, 0xFFu},
- {0x09u, 0x05u},
- {0x0Bu, 0x0Au},
- {0x0Du, 0xFFu},
- {0x10u, 0x08u},
- {0x11u, 0x60u},
- {0x13u, 0x90u},
- {0x15u, 0x0Fu},
- {0x17u, 0xF0u},
- {0x18u, 0x02u},
- {0x1Du, 0x06u},
- {0x1Fu, 0x09u},
- {0x21u, 0x30u},
- {0x23u, 0xC0u},
- {0x24u, 0x04u},
- {0x25u, 0x50u},
- {0x27u, 0xA0u},
- {0x2Bu, 0xFFu},
- {0x30u, 0x02u},
- {0x32u, 0x04u},
+ {0x8Cu, 0x0Fu},
+ {0x08u, 0x28u},
+ {0x0Au, 0x14u},
+ {0x11u, 0x01u},
+ {0x12u, 0x1Cu},
+ {0x13u, 0x02u},
+ {0x14u, 0x10u},
+ {0x15u, 0x04u},
+ {0x16u, 0x20u},
+ {0x18u, 0x24u},
+ {0x1Au, 0x08u},
+ {0x1Bu, 0x02u},
+ {0x1Cu, 0x02u},
+ {0x22u, 0x20u},
+ {0x24u, 0x01u},
+ {0x2Bu, 0x01u},
+ {0x2Cu, 0x40u},
+ {0x2Du, 0x08u},
+ {0x30u, 0x3Cu},
+ {0x31u, 0x08u},
+ {0x32u, 0x40u},
+ {0x33u, 0x04u},
{0x34u, 0x01u},
- {0x36u, 0x08u},
- {0x37u, 0xFFu},
- {0x3Eu, 0x55u},
- {0x3Fu, 0x40u},
- {0x40u, 0x52u},
- {0x41u, 0x04u},
- {0x42u, 0x60u},
- {0x45u, 0xE2u},
- {0x46u, 0xCDu},
+ {0x35u, 0x03u},
+ {0x36u, 0x02u},
+ {0x3Eu, 0x54u},
+ {0x3Fu, 0x15u},
+ {0x40u, 0x63u},
+ {0x41u, 0x02u},
+ {0x42u, 0x50u},
+ {0x45u, 0x2Cu},
+ {0x46u, 0xEDu},
{0x47u, 0x0Fu},
{0x48u, 0x1Fu},
{0x49u, 0xFFu},
{0x59u, 0x04u},
{0x5Au, 0x04u},
{0x5Bu, 0x04u},
+ {0x5Cu, 0x01u},
{0x5Du, 0x01u},
{0x5Fu, 0x01u},
{0x62u, 0xC0u},
{0x68u, 0x40u},
{0x69u, 0x40u},
{0x6Eu, 0x08u},
- {0x81u, 0x03u},
- {0x83u, 0x0Cu},
- {0x85u, 0xFFu},
- {0x89u, 0x05u},
- {0x8Bu, 0x0Au},
- {0x8Du, 0x30u},
- {0x8Fu, 0xC0u},
- {0x91u, 0x50u},
- {0x93u, 0xA0u},
- {0x95u, 0x0Fu},
- {0x97u, 0xF0u},
- {0x9Du, 0x09u},
- {0x9Fu, 0x06u},
- {0xA1u, 0x90u},
- {0xA3u, 0x60u},
- {0xABu, 0xFFu},
- {0xADu, 0xFFu},
- {0xB5u, 0xFFu},
- {0xBFu, 0x10u},
+ {0x80u, 0x02u},
+ {0x99u, 0x01u},
+ {0xA8u, 0x01u},
+ {0xB0u, 0x02u},
+ {0xB1u, 0x01u},
+ {0xB6u, 0x01u},
+ {0xBEu, 0x41u},
+ {0xBFu, 0x01u},
+ {0xD8u, 0x04u},
{0xD9u, 0x04u},
{0xDFu, 0x01u},
- {0x00u, 0x80u},
- {0x01u, 0x40u},
- {0x02u, 0x40u},
- {0x08u, 0x20u},
- {0x09u, 0x02u},
+ {0x03u, 0x08u},
+ {0x06u, 0x80u},
+ {0x08u, 0x40u},
+ {0x09u, 0x20u},
+ {0x0Au, 0x40u},
+ {0x0Bu, 0x20u},
+ {0x10u, 0x80u},
{0x12u, 0x10u},
- {0x18u, 0x01u},
- {0x19u, 0x09u},
- {0x1Bu, 0x20u},
- {0x21u, 0x80u},
- {0x24u, 0x08u},
- {0x28u, 0x04u},
- {0x29u, 0x14u},
- {0x2Au, 0x01u},
- {0x2Bu, 0x40u},
- {0x2Cu, 0x04u},
- {0x2Du, 0x40u},
- {0x2Eu, 0x01u},
- {0x30u, 0x02u},
- {0x31u, 0x08u},
- {0x32u, 0x48u},
- {0x33u, 0x40u},
- {0x36u, 0x09u},
- {0x37u, 0x40u},
- {0x39u, 0x51u},
- {0x3Au, 0x08u},
- {0x3Du, 0x11u},
- {0x3Eu, 0x08u},
- {0x3Fu, 0x80u},
+ {0x13u, 0x40u},
+ {0x16u, 0x08u},
+ {0x18u, 0x04u},
+ {0x1Au, 0x50u},
+ {0x1Bu, 0x80u},
+ {0x1Du, 0x41u},
+ {0x22u, 0x04u},
+ {0x23u, 0x88u},
+ {0x25u, 0x02u},
+ {0x2Au, 0x40u},
+ {0x2Bu, 0x04u},
+ {0x31u, 0x10u},
+ {0x32u, 0x08u},
+ {0x33u, 0x01u},
+ {0x35u, 0x20u},
+ {0x38u, 0x02u},
+ {0x39u, 0x01u},
{0x41u, 0x20u},
- {0x42u, 0x40u},
- {0x48u, 0x10u},
- {0x49u, 0x80u},
- {0x4Bu, 0x22u},
- {0x4Cu, 0x08u},
- {0x4Du, 0x20u},
- {0x50u, 0x28u},
- {0x52u, 0x80u},
- {0x53u, 0x80u},
- {0x59u, 0x42u},
+ {0x43u, 0x08u},
+ {0x48u, 0x11u},
+ {0x49u, 0x02u},
+ {0x4Au, 0x50u},
+ {0x4Bu, 0x20u},
+ {0x50u, 0x40u},
+ {0x51u, 0x04u},
+ {0x52u, 0x20u},
+ {0x59u, 0x01u},
{0x5Au, 0x18u},
- {0x60u, 0x05u},
- {0x61u, 0x01u},
- {0x63u, 0x10u},
- {0x68u, 0x85u},
- {0x69u, 0x08u},
- {0x70u, 0x40u},
- {0x73u, 0x64u},
- {0x81u, 0x06u},
- {0x82u, 0x01u},
- {0x83u, 0x20u},
- {0x85u, 0x10u},
- {0x87u, 0x80u},
- {0x88u, 0x07u},
- {0x8Au, 0x01u},
- {0x8Eu, 0x40u},
- {0x8Fu, 0x80u},
- {0xC0u, 0x08u},
- {0xC2u, 0x0Au},
- {0xC4u, 0x04u},
- {0xCAu, 0xB7u},
- {0xCCu, 0xDBu},
- {0xCEu, 0xFFu},
- {0xD0u, 0x05u},
+ {0x5Bu, 0x80u},
+ {0x60u, 0x24u},
+ {0x61u, 0x42u},
+ {0x69u, 0x96u},
+ {0x70u, 0x81u},
+ {0x71u, 0x08u},
+ {0x72u, 0x04u},
+ {0x81u, 0x40u},
+ {0x85u, 0x04u},
+ {0x89u, 0x01u},
+ {0x8Cu, 0x40u},
+ {0x8Du, 0x40u},
+ {0x8Fu, 0x08u},
+ {0xC0u, 0x12u},
+ {0xC2u, 0x0Fu},
+ {0xC4u, 0x4Du},
+ {0xCAu, 0x0Cu},
+ {0xCCu, 0x27u},
+ {0xD0u, 0x06u},
{0xD2u, 0x0Cu},
{0xD6u, 0x0Fu},
{0xD8u, 0x0Fu},
- {0xE2u, 0x42u},
- {0xE6u, 0x09u},
- {0x04u, 0x0Fu},
- {0x06u, 0xF0u},
- {0x0Bu, 0x03u},
- {0x0Cu, 0x06u},
- {0x0Eu, 0x09u},
- {0x10u, 0x05u},
- {0x12u, 0x0Au},
- {0x15u, 0x06u},
- {0x1Bu, 0x01u},
- {0x20u, 0x60u},
- {0x22u, 0x90u},
- {0x24u, 0x30u},
- {0x26u, 0xC0u},
- {0x27u, 0x05u},
- {0x28u, 0x03u},
- {0x2Au, 0x0Cu},
- {0x2Cu, 0x50u},
- {0x2Eu, 0xA0u},
- {0x30u, 0xFFu},
- {0x33u, 0x07u},
- {0x3Eu, 0x01u},
+ {0xE0u, 0x01u},
+ {0xE4u, 0x02u},
+ {0xE6u, 0x10u},
+ {0x00u, 0x20u},
+ {0x02u, 0xC0u},
+ {0x04u, 0x4Bu},
+ {0x06u, 0xB0u},
+ {0x07u, 0x01u},
+ {0x0Cu, 0x08u},
+ {0x12u, 0x04u},
+ {0x13u, 0x02u},
+ {0x14u, 0x74u},
+ {0x16u, 0x8Bu},
+ {0x18u, 0x41u},
+ {0x1Au, 0xA4u},
+ {0x1Cu, 0x20u},
+ {0x1Eu, 0x0Eu},
+ {0x22u, 0x3Fu},
+ {0x2Au, 0x03u},
+ {0x2Fu, 0x04u},
+ {0x31u, 0x02u},
+ {0x34u, 0x1Fu},
+ {0x35u, 0x04u},
+ {0x36u, 0xE0u},
+ {0x37u, 0x01u},
+ {0x3Au, 0x80u},
+ {0x56u, 0x08u},
{0x58u, 0x04u},
{0x59u, 0x04u},
{0x5Bu, 0x04u},
+ {0x5Cu, 0x91u},
+ {0x5Du, 0x90u},
{0x5Fu, 0x01u},
- {0x83u, 0x04u},
- {0x86u, 0x38u},
- {0x8Au, 0x10u},
- {0x8Cu, 0x2Cu},
- {0x8Du, 0x20u},
- {0x8Eu, 0x40u},
- {0x8Fu, 0x10u},
- {0x90u, 0x04u},
- {0x91u, 0x18u},
- {0x92u, 0x10u},
- {0x93u, 0x20u},
- {0x95u, 0x02u},
- {0x96u, 0x7Cu},
- {0x97u, 0x04u},
- {0x98u, 0x50u},
- {0x9Au, 0x2Cu},
- {0x9Cu, 0x02u},
- {0x9Fu, 0x02u},
- {0xA0u, 0x20u},
- {0xA5u, 0x20u},
- {0xA6u, 0x0Cu},
- {0xA7u, 0x10u},
- {0xA8u, 0x01u},
- {0xA9u, 0x01u},
- {0xACu, 0x80u},
- {0xB0u, 0x80u},
- {0xB1u, 0x30u},
- {0xB2u, 0x01u},
- {0xB3u, 0x01u},
- {0xB4u, 0x02u},
- {0xB5u, 0x06u},
- {0xB6u, 0x7Cu},
- {0xB7u, 0x08u},
- {0xBBu, 0x02u},
- {0xBEu, 0x15u},
- {0xBFu, 0x14u},
+ {0x81u, 0x07u},
+ {0x82u, 0x10u},
+ {0x84u, 0x8Du},
+ {0x87u, 0x02u},
+ {0x88u, 0x8Du},
+ {0x8Cu, 0x02u},
+ {0x8Eu, 0x0Du},
+ {0x91u, 0x01u},
+ {0x92u, 0x80u},
+ {0x94u, 0x62u},
+ {0x95u, 0x04u},
+ {0x96u, 0x08u},
+ {0x98u, 0x02u},
+ {0x9Au, 0x54u},
+ {0x9Cu, 0x01u},
+ {0x9Eu, 0x32u},
+ {0x9Fu, 0x07u},
+ {0xA0u, 0x0Du},
+ {0xA2u, 0x80u},
+ {0xA4u, 0x8Du},
+ {0xA8u, 0x8Du},
+ {0xB0u, 0x0Fu},
+ {0xB4u, 0x80u},
+ {0xB5u, 0x07u},
+ {0xB6u, 0x70u},
+ {0xBAu, 0x02u},
+ {0xBEu, 0x10u},
+ {0xBFu, 0x10u},
{0xD6u, 0x08u},
{0xD8u, 0x04u},
{0xD9u, 0x04u},
{0xDBu, 0x04u},
- {0xDCu, 0x91u},
{0xDDu, 0x90u},
{0xDFu, 0x01u},
- {0x00u, 0x28u},
- {0x01u, 0x80u},
- {0x04u, 0x40u},
- {0x05u, 0x04u},
- {0x08u, 0x04u},
- {0x09u, 0x20u},
- {0x0Au, 0x40u},
- {0x0Bu, 0x01u},
- {0x0Fu, 0x80u},
- {0x11u, 0x08u},
- {0x12u, 0x86u},
- {0x14u, 0x01u},
- {0x15u, 0x20u},
- {0x16u, 0x80u},
- {0x17u, 0x08u},
- {0x18u, 0x04u},
- {0x19u, 0x80u},
- {0x1Au, 0x10u},
- {0x1Bu, 0x82u},
- {0x1Cu, 0x80u},
- {0x1Eu, 0x80u},
- {0x20u, 0x02u},
- {0x21u, 0x01u},
- {0x22u, 0x25u},
- {0x27u, 0x10u},
- {0x28u, 0x08u},
- {0x2Bu, 0x10u},
- {0x2Du, 0x08u},
- {0x31u, 0x0Cu},
+ {0x00u, 0x60u},
+ {0x01u, 0x08u},
+ {0x03u, 0x80u},
+ {0x04u, 0x85u},
+ {0x09u, 0x18u},
+ {0x0Au, 0x02u},
+ {0x0Bu, 0x88u},
+ {0x0Du, 0x20u},
+ {0x0Eu, 0x91u},
+ {0x10u, 0x80u},
+ {0x12u, 0x24u},
+ {0x15u, 0x02u},
+ {0x17u, 0x10u},
+ {0x18u, 0x40u},
+ {0x1Bu, 0x90u},
+ {0x1Cu, 0x07u},
+ {0x1Eu, 0x08u},
+ {0x1Fu, 0x10u},
+ {0x22u, 0x10u},
+ {0x25u, 0x40u},
+ {0x26u, 0x01u},
+ {0x27u, 0x08u},
+ {0x2Eu, 0x10u},
+ {0x2Fu, 0x09u},
+ {0x31u, 0x08u},
{0x32u, 0x41u},
- {0x36u, 0x08u},
- {0x37u, 0x10u},
- {0x39u, 0x40u},
- {0x3Au, 0x01u},
- {0x3Du, 0x20u},
- {0x41u, 0x10u},
- {0x43u, 0x20u},
- {0x5Au, 0x20u},
- {0x5Bu, 0x86u},
- {0x60u, 0x20u},
- {0x61u, 0x02u},
- {0x62u, 0x50u},
- {0x6Cu, 0x18u},
- {0x6Du, 0x08u},
- {0x6Eu, 0x08u},
- {0x6Fu, 0x01u},
- {0x7Du, 0x01u},
- {0x7Eu, 0x40u},
- {0x81u, 0x40u},
- {0x82u, 0x04u},
- {0x84u, 0x20u},
- {0x87u, 0x0Au},
- {0x88u, 0x01u},
- {0x8Bu, 0x12u},
- {0x8Du, 0x10u},
- {0x8Eu, 0x44u},
- {0x8Fu, 0x04u},
- {0x90u, 0x88u},
- {0x91u, 0x18u},
- {0x93u, 0x46u},
- {0x94u, 0x04u},
- {0x95u, 0x01u},
- {0x96u, 0x58u},
- {0x97u, 0x10u},
- {0x99u, 0x20u},
- {0x9Au, 0x28u},
- {0x9Bu, 0xA0u},
- {0x9Cu, 0x20u},
- {0x9Du, 0x90u},
- {0x9Eu, 0x51u},
+ {0x34u, 0x01u},
+ {0x38u, 0x02u},
+ {0x3Bu, 0x08u},
+ {0x3Fu, 0x04u},
+ {0x58u, 0x14u},
+ {0x59u, 0x81u},
+ {0x5Cu, 0x0Au},
+ {0x5Du, 0x40u},
+ {0x5Fu, 0x20u},
+ {0x62u, 0x58u},
+ {0x63u, 0xC0u},
+ {0x64u, 0x40u},
+ {0x65u, 0x20u},
+ {0x66u, 0x88u},
+ {0x82u, 0x14u},
+ {0x84u, 0x10u},
+ {0x86u, 0x20u},
+ {0x87u, 0x80u},
+ {0x8Bu, 0x08u},
+ {0x8Du, 0x01u},
+ {0x90u, 0x80u},
+ {0x91u, 0x59u},
+ {0x92u, 0x44u},
+ {0x97u, 0x60u},
+ {0x98u, 0x1Cu},
+ {0x99u, 0x02u},
+ {0x9Bu, 0x40u},
+ {0x9Cu, 0x40u},
+ {0x9Du, 0x30u},
+ {0x9Eu, 0xD8u},
{0x9Fu, 0x01u},
- {0xA0u, 0xB0u},
- {0xA1u, 0x80u},
- {0xA2u, 0x80u},
- {0xA4u, 0x40u},
- {0xA5u, 0x2Au},
- {0xA8u, 0x02u},
- {0xAAu, 0x08u},
- {0xACu, 0x10u},
- {0xADu, 0x48u},
- {0xAEu, 0x20u},
- {0xAFu, 0x11u},
- {0xB4u, 0x20u},
- {0xC0u, 0xA7u},
- {0xC2u, 0x1Fu},
- {0xC4u, 0xFFu},
- {0xCAu, 0x46u},
- {0xCCu, 0x6Bu},
- {0xCEu, 0x29u},
- {0xD6u, 0x0Fu},
- {0xD8u, 0x0Fu},
- {0xE0u, 0x01u},
- {0xE2u, 0x68u},
- {0xE4u, 0x09u},
- {0xE6u, 0x06u},
- {0xE8u, 0x09u},
- {0xEAu, 0x04u},
- {0xEEu, 0x13u},
- {0x00u, 0x44u},
- {0x02u, 0x88u},
- {0x09u, 0x03u},
- {0x0Du, 0x13u},
- {0x0Fu, 0x44u},
- {0x10u, 0x99u},
- {0x11u, 0x6Cu},
- {0x12u, 0x22u},
- {0x13u, 0x13u},
- {0x17u, 0x7Fu},
- {0x19u, 0x08u},
- {0x1Au, 0x70u},
- {0x1Eu, 0x07u},
- {0x1Fu, 0x02u},
- {0x21u, 0x71u},
- {0x24u, 0xAAu},
- {0x26u, 0x55u},
- {0x2Au, 0x08u},
- {0x2Bu, 0x20u},
- {0x2Du, 0x0Cu},
- {0x2Eu, 0x80u},
- {0x2Fu, 0x30u},
- {0x34u, 0xF0u},
- {0x35u, 0x7Fu},
- {0x36u, 0x0Fu},
+ {0xA2u, 0x50u},
+ {0xA4u, 0x01u},
+ {0xA5u, 0x20u},
+ {0xA6u, 0x08u},
+ {0xA7u, 0x0Cu},
+ {0xACu, 0x30u},
+ {0xAFu, 0x80u},
+ {0xB0u, 0x1Cu},
+ {0xB1u, 0x08u},
+ {0xB6u, 0x20u},
+ {0xB7u, 0x40u},
+ {0xC0u, 0xBFu},
+ {0xC2u, 0xFFu},
+ {0xC4u, 0x5Eu},
+ {0xCAu, 0x10u},
+ {0xCCu, 0x8Bu},
+ {0xCEu, 0x43u},
+ {0xD6u, 0xFFu},
+ {0xD8u, 0xFFu},
+ {0xE2u, 0x09u},
+ {0xEAu, 0x01u},
+ {0xEEu, 0x02u},
+ {0x04u, 0x44u},
+ {0x06u, 0x88u},
+ {0x07u, 0xFFu},
+ {0x0Bu, 0xFFu},
+ {0x0Fu, 0xFFu},
+ {0x11u, 0x0Fu},
+ {0x12u, 0x70u},
+ {0x13u, 0xF0u},
+ {0x15u, 0x69u},
+ {0x16u, 0x07u},
+ {0x17u, 0x96u},
+ {0x1Au, 0x08u},
+ {0x1Du, 0xFFu},
+ {0x21u, 0x55u},
+ {0x23u, 0xAAu},
+ {0x24u, 0x99u},
+ {0x26u, 0x22u},
+ {0x29u, 0xFFu},
+ {0x2Au, 0x80u},
+ {0x2Cu, 0xAAu},
+ {0x2Du, 0x33u},
+ {0x2Eu, 0x55u},
+ {0x2Fu, 0xCCu},
+ {0x30u, 0xF0u},
+ {0x31u, 0xFFu},
+ {0x32u, 0x0Fu},
+ {0x3Bu, 0x02u},
{0x56u, 0x08u},
{0x58u, 0x04u},
{0x59u, 0x04u},
{0x5Cu, 0x11u},
{0x5Du, 0x90u},
{0x5Fu, 0x01u},
- {0x81u, 0x6Cu},
- {0x85u, 0x64u},
- {0x87u, 0x08u},
- {0x88u, 0xFFu},
- {0x8Cu, 0x06u},
- {0x8Eu, 0x09u},
- {0x91u, 0x6Cu},
- {0x92u, 0xFFu},
- {0x94u, 0x0Fu},
- {0x95u, 0x71u},
- {0x96u, 0xF0u},
- {0x97u, 0x82u},
- {0x99u, 0xC0u},
- {0x9Au, 0xFFu},
- {0x9Bu, 0x2Fu},
- {0x9Cu, 0x50u},
- {0x9Du, 0xA4u},
- {0x9Eu, 0xA0u},
- {0x9Fu, 0x40u},
- {0xA0u, 0x03u},
- {0xA1u, 0x08u},
- {0xA2u, 0x0Cu},
- {0xA3u, 0x10u},
- {0xA4u, 0x60u},
- {0xA5u, 0x91u},
- {0xA6u, 0x90u},
- {0xA7u, 0x4Eu},
- {0xA8u, 0x05u},
- {0xA9u, 0x40u},
- {0xAAu, 0x0Au},
- {0xABu, 0x2Cu},
- {0xACu, 0x30u},
- {0xADu, 0x2Cu},
- {0xAEu, 0xC0u},
- {0xAFu, 0x40u},
- {0xB1u, 0xC0u},
- {0xB3u, 0x31u},
- {0xB4u, 0xFFu},
- {0xB5u, 0x0Fu},
- {0xBBu, 0x0Eu},
- {0xBEu, 0x10u},
+ {0x82u, 0x20u},
+ {0x83u, 0x07u},
+ {0x84u, 0x8Cu},
+ {0x85u, 0x28u},
+ {0x86u, 0x30u},
+ {0x87u, 0x56u},
+ {0x89u, 0x07u},
+ {0x8Bu, 0x18u},
+ {0x8Du, 0x40u},
+ {0x8Eu, 0x02u},
+ {0x8Fu, 0xA7u},
+ {0x90u, 0xECu},
+ {0x92u, 0x13u},
+ {0x93u, 0x04u},
+ {0x94u, 0x08u},
+ {0x95u, 0x0Fu},
+ {0x96u, 0x80u},
+ {0x97u, 0x90u},
+ {0x98u, 0x93u},
+ {0x9Au, 0x44u},
+ {0x9Cu, 0x71u},
+ {0x9Eu, 0x80u},
+ {0xA2u, 0x7Fu},
+ {0xA5u, 0x21u},
+ {0xA7u, 0x02u},
+ {0xA8u, 0x03u},
+ {0xA9u, 0x0Cu},
+ {0xABu, 0xB3u},
+ {0xADu, 0x01u},
+ {0xB2u, 0x7Fu},
+ {0xB3u, 0x1Fu},
+ {0xB5u, 0xE0u},
+ {0xB6u, 0x80u},
+ {0xBBu, 0x28u},
+ {0xBEu, 0x40u},
+ {0xD6u, 0x08u},
{0xD8u, 0x04u},
{0xD9u, 0x04u},
+ {0xDBu, 0x04u},
+ {0xDCu, 0x11u},
+ {0xDDu, 0x90u},
{0xDFu, 0x01u},
- {0x03u, 0x80u},
- {0x06u, 0x08u},
- {0x07u, 0x02u},
- {0x08u, 0x01u},
- {0x0Au, 0x4Au},
- {0x0Du, 0x18u},
- {0x0Eu, 0x82u},
+ {0x01u, 0x08u},
+ {0x04u, 0x84u},
+ {0x05u, 0x82u},
+ {0x06u, 0x02u},
+ {0x0Au, 0x54u},
+ {0x0Cu, 0x04u},
+ {0x0Eu, 0x29u},
+ {0x0Fu, 0x40u},
+ {0x11u, 0x10u},
{0x12u, 0x20u},
- {0x13u, 0x60u},
- {0x15u, 0x15u},
- {0x16u, 0x01u},
- {0x1Au, 0x0Au},
- {0x1Bu, 0x60u},
- {0x1Du, 0x10u},
- {0x21u, 0x20u},
- {0x22u, 0x20u},
- {0x25u, 0x10u},
- {0x26u, 0x08u},
- {0x27u, 0x58u},
- {0x28u, 0xC1u},
- {0x2Au, 0x20u},
- {0x2Cu, 0x02u},
- {0x2Du, 0x08u},
- {0x2Fu, 0x48u},
- {0x30u, 0x24u},
- {0x31u, 0x01u},
- {0x32u, 0x80u},
- {0x37u, 0x59u},
- {0x38u, 0x20u},
- {0x39u, 0xA0u},
- {0x3Du, 0x02u},
- {0x3Eu, 0x04u},
- {0x41u, 0x40u},
- {0x43u, 0x80u},
- {0x58u, 0x10u},
- {0x59u, 0x84u},
- {0x5Au, 0x01u},
- {0x60u, 0x08u},
- {0x62u, 0x06u},
- {0x63u, 0x01u},
- {0x65u, 0x40u},
- {0x67u, 0x02u},
- {0x81u, 0x25u},
- {0x83u, 0x20u},
- {0x84u, 0x10u},
- {0x86u, 0x02u},
+ {0x13u, 0x40u},
+ {0x15u, 0x02u},
+ {0x17u, 0x10u},
+ {0x1Au, 0x50u},
+ {0x1Bu, 0x04u},
+ {0x1Du, 0x40u},
+ {0x1Fu, 0x08u},
+ {0x20u, 0x80u},
+ {0x21u, 0x02u},
+ {0x24u, 0x14u},
+ {0x25u, 0x20u},
+ {0x26u, 0x20u},
+ {0x2Au, 0x40u},
+ {0x2Bu, 0x48u},
+ {0x2Du, 0x80u},
+ {0x2Fu, 0x28u},
+ {0x31u, 0x02u},
+ {0x32u, 0x08u},
+ {0x33u, 0x80u},
+ {0x35u, 0x0Au},
+ {0x36u, 0x04u},
+ {0x38u, 0x44u},
+ {0x3Bu, 0x20u},
+ {0x3Cu, 0x54u},
+ {0x3Eu, 0x01u},
+ {0x40u, 0x42u},
+ {0x41u, 0x01u},
+ {0x42u, 0x02u},
+ {0x58u, 0x80u},
+ {0x5Du, 0x40u},
+ {0x5Fu, 0x20u},
+ {0x63u, 0x02u},
+ {0x64u, 0x01u},
+ {0x67u, 0x04u},
+ {0x6Cu, 0x08u},
+ {0x6Du, 0x08u},
+ {0x6Fu, 0x32u},
+ {0x80u, 0x10u},
+ {0x81u, 0x20u},
+ {0x87u, 0x4Bu},
{0x89u, 0x01u},
- {0x8Fu, 0x41u},
- {0x90u, 0xA8u},
- {0x91u, 0x5Au},
- {0x92u, 0x01u},
- {0x93u, 0x46u},
- {0x94u, 0x40u},
- {0x95u, 0x01u},
- {0x96u, 0x60u},
- {0x97u, 0x01u},
- {0x99u, 0x20u},
- {0x9Au, 0x28u},
- {0x9Bu, 0x20u},
- {0x9Cu, 0x0Cu},
- {0x9Du, 0x08u},
- {0x9Eu, 0x85u},
- {0xA0u, 0xE0u},
- {0xA1u, 0x84u},
- {0xA2u, 0xC0u},
- {0xA3u, 0x80u},
- {0xA4u, 0x04u},
+ {0x8Cu, 0x88u},
+ {0x8Du, 0x44u},
+ {0x90u, 0x88u},
+ {0x91u, 0x19u},
+ {0x92u, 0x04u},
+ {0x93u, 0x20u},
+ {0x94u, 0x02u},
+ {0x95u, 0x02u},
+ {0x96u, 0x83u},
+ {0x97u, 0x86u},
+ {0x98u, 0x40u},
+ {0x99u, 0x22u},
+ {0x9Au, 0xF4u},
+ {0x9Bu, 0x48u},
+ {0x9Cu, 0x01u},
+ {0x9Du, 0x10u},
+ {0x9Fu, 0x11u},
+ {0xA1u, 0x40u},
+ {0xA2u, 0x1Du},
+ {0xA3u, 0x50u},
{0xA5u, 0x38u},
- {0xA6u, 0x0Au},
- {0xA7u, 0x70u},
- {0xAAu, 0x20u},
- {0xABu, 0x10u},
- {0xAEu, 0x50u},
- {0xB0u, 0x01u},
- {0xB1u, 0x02u},
- {0xB2u, 0x01u},
- {0xB4u, 0x08u},
+ {0xA7u, 0x0Cu},
+ {0xAAu, 0x60u},
+ {0xACu, 0x82u},
+ {0xB1u, 0x08u},
+ {0xB3u, 0x30u},
+ {0xB4u, 0x04u},
{0xB5u, 0x80u},
- {0xC0u, 0xC8u},
- {0xC2u, 0xFBu},
- {0xC4u, 0xF7u},
- {0xCAu, 0xFDu},
- {0xCCu, 0xFFu},
- {0xCEu, 0xCCu},
- {0xD6u, 0x0Fu},
- {0xD8u, 0x0Fu},
- {0xE0u, 0x06u},
- {0xE2u, 0x08u},
- {0xE4u, 0x04u},
- {0xE6u, 0x03u},
- {0xE8u, 0x0Au},
- {0xEAu, 0x80u},
- {0xECu, 0x01u},
- {0xEEu, 0x14u},
- {0x01u, 0x02u},
- {0x03u, 0x05u},
- {0x04u, 0x24u},
- {0x06u, 0x83u},
- {0x09u, 0x02u},
- {0x0Au, 0x12u},
- {0x0Bu, 0x01u},
- {0x14u, 0xC0u},
- {0x19u, 0x01u},
- {0x1Au, 0x0Cu},
- {0x1Bu, 0x02u},
- {0x1Eu, 0x01u},
- {0x24u, 0x21u},
- {0x26u, 0x42u},
- {0x28u, 0x48u},
- {0x2Au, 0x23u},
- {0x32u, 0xE0u},
- {0x33u, 0x03u},
- {0x34u, 0x0Fu},
- {0x35u, 0x04u},
- {0x36u, 0x10u},
- {0x38u, 0x08u},
- {0x3Bu, 0x08u},
+ {0xB6u, 0x08u},
+ {0xC0u, 0xB4u},
+ {0xC2u, 0xFEu},
+ {0xC4u, 0x57u},
+ {0xCAu, 0x7Du},
+ {0xCCu, 0xCBu},
+ {0xCEu, 0xFEu},
+ {0xD6u, 0x38u},
+ {0xD8u, 0x38u},
+ {0xE0u, 0x14u},
+ {0xE4u, 0x08u},
+ {0xE6u, 0xD0u},
+ {0xE8u, 0x04u},
+ {0xEAu, 0x08u},
+ {0xEEu, 0x03u},
+ {0x00u, 0x40u},
+ {0x01u, 0x05u},
+ {0x02u, 0x84u},
+ {0x03u, 0x02u},
+ {0x04u, 0x02u},
+ {0x05u, 0x02u},
+ {0x06u, 0x01u},
+ {0x07u, 0x01u},
+ {0x0Du, 0x02u},
+ {0x0Fu, 0x01u},
+ {0x10u, 0x80u},
+ {0x12u, 0x48u},
+ {0x14u, 0x10u},
+ {0x16u, 0x20u},
+ {0x17u, 0x08u},
+ {0x18u, 0x01u},
+ {0x1Au, 0x02u},
+ {0x1Cu, 0x80u},
+ {0x1Eu, 0x40u},
+ {0x20u, 0x20u},
+ {0x22u, 0x10u},
+ {0x24u, 0x20u},
+ {0x26u, 0x10u},
+ {0x28u, 0x02u},
+ {0x2Au, 0x01u},
+ {0x2Cu, 0x04u},
+ {0x2Eu, 0x08u},
+ {0x30u, 0xC0u},
+ {0x31u, 0x03u},
+ {0x32u, 0x30u},
+ {0x33u, 0x08u},
+ {0x34u, 0x03u},
+ {0x36u, 0x0Cu},
+ {0x37u, 0x04u},
+ {0x3Au, 0x2Au},
+ {0x3Bu, 0x02u},
+ {0x3Eu, 0x40u},
{0x56u, 0x08u},
{0x58u, 0x04u},
{0x59u, 0x04u},
{0x5Bu, 0x04u},
- {0x5Cu, 0x90u},
+ {0x5Cu, 0x99u},
{0x5Du, 0x90u},
{0x5Fu, 0x01u},
- {0x81u, 0x1Eu},
- {0x84u, 0x20u},
- {0x85u, 0x01u},
- {0x86u, 0x02u},
- {0x88u, 0x07u},
- {0x8Bu, 0xE0u},
- {0x8Du, 0x20u},
- {0x8Eu, 0x40u},
- {0x8Fu, 0x5Eu},
- {0x91u, 0x01u},
- {0x94u, 0x08u},
- {0x95u, 0x0Au},
- {0x96u, 0x10u},
- {0x97u, 0x14u},
- {0x99u, 0x40u},
- {0x9Au, 0x07u},
- {0x9Bu, 0x9Eu},
- {0x9Cu, 0x01u},
- {0x9Du, 0x01u},
- {0x9Eu, 0x20u},
- {0xA1u, 0x80u},
- {0xA2u, 0x08u},
- {0xA3u, 0x3Eu},
- {0xA5u, 0x06u},
- {0xA6u, 0x10u},
- {0xA7u, 0x18u},
- {0xA8u, 0x04u},
- {0xA9u, 0x01u},
- {0xAAu, 0x20u},
- {0xADu, 0x0Cu},
- {0xAFu, 0x12u},
- {0xB0u, 0x20u},
- {0xB2u, 0x07u},
- {0xB3u, 0xFEu},
- {0xB4u, 0x40u},
- {0xB6u, 0x18u},
- {0xB7u, 0x01u},
- {0xB9u, 0x80u},
- {0xBEu, 0x45u},
- {0xBFu, 0x40u},
- {0xD8u, 0x04u},
- {0xD9u, 0x04u},
+ {0x85u, 0xFFu},
+ {0x88u, 0x30u},
+ {0x89u, 0x50u},
+ {0x8Au, 0xC0u},
+ {0x8Bu, 0xA0u},
+ {0x8Cu, 0x0Fu},
+ {0x8Du, 0x90u},
+ {0x8Eu, 0xF0u},
+ {0x8Fu, 0x60u},
+ {0x90u, 0x05u},
+ {0x91u, 0x0Fu},
+ {0x92u, 0x0Au},
+ {0x93u, 0xF0u},
+ {0x94u, 0x06u},
+ {0x95u, 0x30u},
+ {0x96u, 0x09u},
+ {0x97u, 0xC0u},
+ {0x99u, 0xFFu},
+ {0x9Au, 0xFFu},
+ {0x9Cu, 0x03u},
+ {0x9Du, 0x05u},
+ {0x9Eu, 0x0Cu},
+ {0x9Fu, 0x0Au},
+ {0xA0u, 0xFFu},
+ {0xA1u, 0x03u},
+ {0xA3u, 0x0Cu},
+ {0xA6u, 0xFFu},
+ {0xA7u, 0xFFu},
+ {0xA8u, 0x50u},
+ {0xA9u, 0x09u},
+ {0xAAu, 0xA0u},
+ {0xABu, 0x06u},
+ {0xACu, 0x60u},
+ {0xAEu, 0x90u},
+ {0xB3u, 0xFFu},
+ {0xB6u, 0xFFu},
+ {0xBEu, 0x40u},
+ {0xBFu, 0x04u},
+ {0xD8u, 0x04u},
+ {0xD9u, 0x04u},
{0xDBu, 0x04u},
- {0xDCu, 0x19u},
{0xDFu, 0x01u},
{0x00u, 0x20u},
- {0x01u, 0x48u},
- {0x05u, 0x08u},
- {0x06u, 0x04u},
- {0x09u, 0x28u},
- {0x0Au, 0x41u},
- {0x0Bu, 0x50u},
- {0x0Du, 0x20u},
- {0x0Eu, 0x22u},
- {0x11u, 0x04u},
- {0x12u, 0x08u},
- {0x13u, 0x02u},
+ {0x02u, 0x08u},
+ {0x03u, 0x01u},
+ {0x05u, 0x09u},
+ {0x08u, 0x88u},
+ {0x09u, 0x80u},
+ {0x0Au, 0x40u},
+ {0x0Bu, 0x18u},
+ {0x0Cu, 0x01u},
+ {0x0Eu, 0x26u},
+ {0x10u, 0x10u},
+ {0x11u, 0x18u},
+ {0x12u, 0x82u},
+ {0x15u, 0x40u},
+ {0x16u, 0x40u},
{0x17u, 0x18u},
- {0x1Au, 0x90u},
- {0x1Bu, 0x50u},
- {0x1Cu, 0x20u},
- {0x1Du, 0x20u},
- {0x1Eu, 0x22u},
- {0x20u, 0x12u},
- {0x25u, 0x10u},
- {0x27u, 0x20u},
- {0x29u, 0x10u},
- {0x2Au, 0x08u},
- {0x2Bu, 0x81u},
- {0x31u, 0x84u},
- {0x32u, 0x22u},
- {0x37u, 0x20u},
- {0x38u, 0x18u},
- {0x3Au, 0x01u},
- {0x3Bu, 0x40u},
- {0x3Du, 0x20u},
- {0x3Fu, 0x01u},
- {0x59u, 0x62u},
- {0x5Bu, 0x04u},
- {0x5Du, 0x80u},
- {0x62u, 0x80u},
- {0x67u, 0x01u},
- {0x81u, 0x80u},
- {0x82u, 0x08u},
- {0x83u, 0x20u},
- {0x84u, 0x40u},
- {0x8Au, 0x02u},
- {0x8Bu, 0x01u},
+ {0x1Bu, 0x40u},
+ {0x1Cu, 0x10u},
+ {0x1Du, 0x01u},
+ {0x1Eu, 0x25u},
+ {0x1Fu, 0x80u},
+ {0x23u, 0x20u},
+ {0x24u, 0x40u},
+ {0x25u, 0x03u},
+ {0x27u, 0x12u},
+ {0x28u, 0x98u},
+ {0x2Cu, 0x08u},
+ {0x2Fu, 0x08u},
+ {0x30u, 0x80u},
+ {0x32u, 0x08u},
+ {0x33u, 0x21u},
+ {0x35u, 0x08u},
+ {0x39u, 0x90u},
+ {0x3Bu, 0x08u},
+ {0x3Du, 0x82u},
+ {0x3Fu, 0x04u},
+ {0x41u, 0x04u},
+ {0x42u, 0x10u},
+ {0x58u, 0x06u},
+ {0x5Au, 0x10u},
+ {0x5Bu, 0x40u},
+ {0x5Fu, 0x40u},
+ {0x61u, 0x40u},
+ {0x66u, 0x40u},
+ {0x67u, 0x02u},
+ {0x6Du, 0x40u},
+ {0x83u, 0x42u},
+ {0x85u, 0x08u},
+ {0x86u, 0x04u},
+ {0x89u, 0x10u},
+ {0x8Bu, 0x40u},
{0x8Cu, 0x10u},
- {0x8Eu, 0x50u},
- {0x90u, 0x88u},
- {0x91u, 0x4Cu},
- {0x93u, 0x04u},
- {0x94u, 0x40u},
- {0x95u, 0x01u},
- {0x96u, 0x64u},
- {0x97u, 0x80u},
- {0x98u, 0x44u},
- {0x99u, 0x72u},
- {0x9Bu, 0x5Au},
- {0x9Du, 0x08u},
- {0x9Eu, 0x80u},
+ {0x8Eu, 0x80u},
+ {0x8Fu, 0x20u},
+ {0x90u, 0x0Cu},
+ {0x91u, 0x0Du},
+ {0x92u, 0x40u},
+ {0x93u, 0x34u},
+ {0x94u, 0x42u},
+ {0x96u, 0x83u},
+ {0x97u, 0x8Au},
+ {0x98u, 0x47u},
+ {0x99u, 0x60u},
+ {0x9Au, 0xB4u},
+ {0x9Bu, 0x48u},
+ {0x9Du, 0x10u},
{0x9Fu, 0x01u},
- {0xA0u, 0xE0u},
- {0xA1u, 0x8Cu},
- {0xA2u, 0x28u},
- {0xA3u, 0x80u},
- {0xA4u, 0x02u},
- {0xA5u, 0x01u},
- {0xA7u, 0x18u},
- {0xA9u, 0x10u},
- {0xAAu, 0x01u},
- {0xABu, 0x02u},
- {0xACu, 0x84u},
- {0xADu, 0x80u},
- {0xB0u, 0x04u},
- {0xB1u, 0x0Eu},
- {0xB2u, 0x80u},
- {0xB4u, 0x08u},
- {0xB6u, 0x09u},
- {0xC0u, 0x67u},
- {0xC2u, 0xE7u},
- {0xC4u, 0x6Eu},
- {0xCAu, 0x0Fu},
- {0xCCu, 0x2Fu},
- {0xCEu, 0xAFu},
+ {0xA0u, 0xC0u},
+ {0xA1u, 0x44u},
+ {0xA2u, 0x01u},
+ {0xA3u, 0x1Cu},
+ {0xA5u, 0x18u},
+ {0xA7u, 0x80u},
+ {0xAFu, 0x24u},
+ {0xB1u, 0x04u},
+ {0xB3u, 0x10u},
+ {0xB4u, 0x80u},
+ {0xB6u, 0x40u},
+ {0xC0u, 0x33u},
+ {0xC2u, 0xFFu},
+ {0xC4u, 0xFFu},
+ {0xCAu, 0x07u},
+ {0xCCu, 0x4Fu},
+ {0xCEu, 0xDEu},
{0xD6u, 0x1Fu},
{0xD8u, 0x18u},
- {0xE0u, 0x03u},
- {0xE2u, 0x0Cu},
- {0xE6u, 0x13u},
- {0xE8u, 0x01u},
- {0xEAu, 0x0Cu},
- {0xEEu, 0x03u},
- {0x01u, 0x40u},
- {0x02u, 0xFFu},
- {0x03u, 0x80u},
- {0x04u, 0x50u},
- {0x05u, 0x0Au},
- {0x06u, 0xA0u},
- {0x07u, 0x05u},
- {0x08u, 0x09u},
- {0x0Au, 0x06u},
- {0x0Cu, 0x0Fu},
- {0x0Eu, 0xF0u},
- {0x10u, 0x90u},
- {0x11u, 0x30u},
- {0x12u, 0x60u},
- {0x13u, 0xC0u},
- {0x14u, 0x05u},
- {0x15u, 0x04u},
- {0x16u, 0x0Au},
- {0x17u, 0x08u},
- {0x1Au, 0xFFu},
- {0x1Bu, 0x07u},
- {0x1Du, 0x20u},
- {0x1Eu, 0xFFu},
- {0x1Fu, 0x10u},
- {0x21u, 0x80u},
- {0x23u, 0x40u},
- {0x24u, 0x03u},
- {0x26u, 0x0Cu},
- {0x27u, 0x08u},
- {0x28u, 0x30u},
- {0x29u, 0x10u},
- {0x2Au, 0xC0u},
- {0x2Bu, 0x20u},
- {0x2Du, 0x09u},
- {0x2Fu, 0x02u},
- {0x30u, 0xFFu},
- {0x31u, 0xF0u},
- {0x35u, 0x0Fu},
- {0x3Eu, 0x01u},
+ {0xE0u, 0x06u},
+ {0xE6u, 0x08u},
+ {0xEAu, 0x04u},
+ {0xECu, 0x08u},
+ {0xEEu, 0x02u},
+ {0x40u, 0x20u},
+ {0x41u, 0x08u},
+ {0x81u, 0x01u},
+ {0x82u, 0x02u},
+ {0x85u, 0x08u},
+ {0x87u, 0x41u},
+ {0x8Bu, 0x04u},
+ {0x8Cu, 0x80u},
+ {0x8Du, 0x08u},
+ {0x90u, 0x40u},
+ {0x93u, 0x40u},
+ {0x95u, 0x80u},
+ {0x97u, 0x29u},
+ {0x99u, 0x28u},
+ {0x9Bu, 0x56u},
+ {0x9Cu, 0xE0u},
+ {0x9Du, 0x81u},
+ {0x9Eu, 0x01u},
+ {0x9Fu, 0x20u},
+ {0xA0u, 0x06u},
+ {0xA2u, 0x10u},
+ {0xA3u, 0x01u},
+ {0xA4u, 0x80u},
+ {0xA5u, 0x40u},
+ {0xA6u, 0x80u},
+ {0xADu, 0x02u},
+ {0xB0u, 0x10u},
+ {0xB3u, 0x02u},
+ {0xB7u, 0x48u},
+ {0xE0u, 0x91u},
+ {0xE2u, 0x60u},
+ {0xE4u, 0x02u},
+ {0xEAu, 0x24u},
+ {0xECu, 0x40u},
+ {0xEEu, 0x82u},
+ {0x01u, 0x02u},
+ {0x03u, 0x05u},
+ {0x07u, 0x10u},
+ {0x0Cu, 0x04u},
+ {0x0Du, 0x08u},
+ {0x0Eu, 0x02u},
+ {0x0Fu, 0x10u},
+ {0x15u, 0x01u},
+ {0x17u, 0x02u},
+ {0x18u, 0x01u},
+ {0x19u, 0x02u},
+ {0x1Bu, 0x01u},
+ {0x1Cu, 0x06u},
+ {0x1Eu, 0x18u},
+ {0x20u, 0x08u},
+ {0x22u, 0x10u},
+ {0x23u, 0x08u},
+ {0x24u, 0x02u},
+ {0x26u, 0x04u},
+ {0x2Cu, 0x10u},
+ {0x2Eu, 0x08u},
+ {0x31u, 0x18u},
+ {0x32u, 0x1Eu},
+ {0x33u, 0x03u},
+ {0x35u, 0x04u},
+ {0x36u, 0x01u},
+ {0x3Bu, 0x08u},
+ {0x3Eu, 0x04u},
{0x3Fu, 0x01u},
+ {0x54u, 0x01u},
{0x58u, 0x04u},
{0x59u, 0x04u},
{0x5Bu, 0x04u},
- {0x5Cu, 0x10u},
+ {0x5Cu, 0x99u},
+ {0x5Du, 0x10u},
{0x5Fu, 0x01u},
- {0x80u, 0x0Fu},
- {0x82u, 0xF0u},
- {0x85u, 0x04u},
- {0x86u, 0xFFu},
- {0x8Fu, 0x08u},
- {0x91u, 0x09u},
- {0x93u, 0x12u},
- {0x94u, 0xFFu},
- {0x97u, 0x01u},
- {0x98u, 0x55u},
- {0x9Au, 0xAAu},
- {0x9Cu, 0xFFu},
- {0xA0u, 0x96u},
- {0xA2u, 0x69u},
- {0xA3u, 0x10u},
- {0xA4u, 0x33u},
- {0xA6u, 0xCCu},
- {0xA7u, 0x02u},
- {0xAAu, 0xFFu},
- {0xAEu, 0xFFu},
- {0xB1u, 0x18u},
- {0xB3u, 0x04u},
- {0xB5u, 0x03u},
- {0xB6u, 0xFFu},
- {0xBAu, 0x80u},
- {0xBFu, 0x11u},
- {0xD4u, 0x01u},
+ {0x80u, 0x01u},
+ {0x81u, 0x90u},
+ {0x83u, 0x60u},
+ {0x84u, 0x01u},
+ {0x87u, 0xFFu},
+ {0x88u, 0x01u},
+ {0x89u, 0x09u},
+ {0x8Bu, 0x06u},
+ {0x8Du, 0x0Fu},
+ {0x8Eu, 0x10u},
+ {0x8Fu, 0xF0u},
+ {0x90u, 0x14u},
+ {0x92u, 0x0Au},
+ {0x93u, 0xFFu},
+ {0x95u, 0x05u},
+ {0x96u, 0x0Eu},
+ {0x97u, 0x0Au},
+ {0x98u, 0x08u},
+ {0x99u, 0x03u},
+ {0x9Au, 0x10u},
+ {0x9Bu, 0x0Cu},
+ {0x9Eu, 0x40u},
+ {0xA0u, 0x20u},
+ {0xA1u, 0x30u},
+ {0xA2u, 0x40u},
+ {0xA3u, 0xC0u},
+ {0xA4u, 0x12u},
+ {0xA6u, 0x04u},
+ {0xA7u, 0xFFu},
+ {0xA9u, 0x50u},
+ {0xAAu, 0x20u},
+ {0xABu, 0xA0u},
+ {0xACu, 0x01u},
+ {0xB2u, 0x1Eu},
+ {0xB3u, 0xFFu},
+ {0xB4u, 0x60u},
+ {0xB6u, 0x01u},
+ {0xB8u, 0x80u},
+ {0xBEu, 0x50u},
+ {0xBFu, 0x04u},
{0xD8u, 0x04u},
{0xD9u, 0x04u},
{0xDBu, 0x04u},
- {0xDCu, 0x91u},
- {0xDDu, 0x10u},
+ {0xDCu, 0x01u},
{0xDFu, 0x01u},
- {0x00u, 0x04u},
- {0x02u, 0x20u},
- {0x03u, 0x80u},
+ {0x00u, 0x40u},
{0x04u, 0x18u},
- {0x05u, 0x05u},
+ {0x05u, 0x01u},
{0x07u, 0x01u},
- {0x09u, 0x04u},
- {0x0Au, 0x06u},
- {0x0Cu, 0x20u},
- {0x0Eu, 0x62u},
- {0x10u, 0x42u},
- {0x12u, 0x18u},
- {0x17u, 0x18u},
- {0x1Bu, 0x80u},
- {0x1Cu, 0x80u},
- {0x21u, 0x14u},
- {0x22u, 0x02u},
- {0x26u, 0x11u},
- {0x27u, 0x04u},
- {0x29u, 0x04u},
- {0x2Au, 0x02u},
- {0x2Cu, 0x9Au},
- {0x33u, 0x05u},
- {0x35u, 0x40u},
- {0x36u, 0x18u},
- {0x37u, 0x01u},
- {0x38u, 0x84u},
- {0x3Du, 0x08u},
- {0x3Eu, 0x02u},
- {0x58u, 0x80u},
- {0x5Cu, 0x02u},
- {0x5Du, 0x04u},
- {0x5Eu, 0x10u},
- {0x5Fu, 0x40u},
- {0x67u, 0x02u},
- {0x6Fu, 0x01u},
- {0x82u, 0x10u},
- {0x83u, 0x29u},
- {0x84u, 0x20u},
- {0x88u, 0x40u},
- {0x8Bu, 0x80u},
- {0x8Cu, 0x82u},
- {0x90u, 0x1Cu},
- {0x91u, 0x04u},
- {0x92u, 0xC6u},
- {0x93u, 0x40u},
- {0x95u, 0x09u},
- {0x96u, 0x01u},
- {0x97u, 0x08u},
- {0x98u, 0x50u},
- {0x9Au, 0x12u},
- {0x9Bu, 0x10u},
- {0x9Cu, 0x01u},
- {0x9Du, 0x08u},
- {0x9Eu, 0x08u},
- {0x9Fu, 0x01u},
- {0xA0u, 0x90u},
+ {0x09u, 0x40u},
+ {0x0Au, 0x08u},
+ {0x0Bu, 0x04u},
+ {0x0Cu, 0x10u},
+ {0x0Du, 0x01u},
+ {0x0Eu, 0x20u},
+ {0x0Fu, 0x01u},
+ {0x11u, 0x08u},
+ {0x12u, 0x81u},
+ {0x15u, 0x90u},
+ {0x16u, 0xA0u},
+ {0x19u, 0x08u},
+ {0x1Au, 0x02u},
+ {0x1Cu, 0x09u},
+ {0x1Du, 0x04u},
+ {0x1Eu, 0x20u},
+ {0x22u, 0x24u},
+ {0x23u, 0x40u},
+ {0x24u, 0x10u},
+ {0x2Bu, 0x40u},
+ {0x2Cu, 0x80u},
+ {0x2Du, 0x08u},
+ {0x2Fu, 0x04u},
+ {0x32u, 0x24u},
+ {0x35u, 0x22u},
+ {0x37u, 0x08u},
+ {0x3Au, 0x82u},
+ {0x3Bu, 0x08u},
+ {0x3Cu, 0x24u},
+ {0x3Du, 0x90u},
+ {0x3Eu, 0x80u},
+ {0x3Fu, 0x01u},
+ {0x58u, 0x40u},
+ {0x5Cu, 0xA2u},
+ {0x5Fu, 0x04u},
+ {0x65u, 0x80u},
+ {0x82u, 0x20u},
+ {0x86u, 0x02u},
+ {0x88u, 0x02u},
+ {0x8Cu, 0x05u},
+ {0x90u, 0x48u},
+ {0x91u, 0x02u},
+ {0x94u, 0x04u},
+ {0x96u, 0x02u},
+ {0x97u, 0x29u},
+ {0x98u, 0x10u},
+ {0x99u, 0x20u},
+ {0x9Bu, 0x57u},
+ {0x9Du, 0x0Eu},
+ {0x9Eu, 0x20u},
+ {0x9Fu, 0x28u},
+ {0xA0u, 0x12u},
{0xA1u, 0x04u},
- {0xA2u, 0x08u},
- {0xA3u, 0x28u},
- {0xA6u, 0x17u},
- {0xA8u, 0x10u},
- {0xABu, 0x14u},
- {0xAEu, 0x01u},
- {0xB0u, 0x20u},
- {0xB2u, 0x40u},
- {0xB3u, 0x09u},
- {0xB4u, 0x04u},
- {0xB7u, 0x44u},
- {0xC0u, 0xFCu},
- {0xC2u, 0xF7u},
- {0xC4u, 0x6Fu},
- {0xCAu, 0xF3u},
- {0xCCu, 0xF3u},
- {0xCEu, 0xCAu},
+ {0xA3u, 0x01u},
+ {0xA4u, 0x80u},
+ {0xA5u, 0x40u},
+ {0xA6u, 0x80u},
+ {0xA8u, 0x40u},
+ {0xA9u, 0x04u},
+ {0xABu, 0x02u},
+ {0xACu, 0x02u},
+ {0xAFu, 0x80u},
+ {0xB0u, 0x10u},
+ {0xB3u, 0x20u},
+ {0xC0u, 0xF1u},
+ {0xC2u, 0xF3u},
+ {0xC4u, 0xFDu},
+ {0xCAu, 0xE1u},
+ {0xCCu, 0xE6u},
+ {0xCEu, 0xFBu},
{0xD6u, 0xF8u},
{0xD8u, 0x10u},
- {0xE0u, 0x10u},
- {0xE2u, 0x8Cu},
+ {0xE0u, 0x20u},
+ {0xE2u, 0x40u},
{0xE4u, 0x40u},
- {0xE6u, 0x22u},
- {0xE8u, 0x40u},
- {0xEAu, 0x38u},
- {0xECu, 0x40u},
- {0xEEu, 0xA0u},
- {0x03u, 0x08u},
- {0x05u, 0x01u},
- {0x07u, 0x02u},
- {0x08u, 0x04u},
- {0x0Au, 0x09u},
- {0x0Du, 0x02u},
- {0x0Fu, 0x01u},
- {0x14u, 0x08u},
- {0x16u, 0x04u},
- {0x1Du, 0x02u},
- {0x1Fu, 0x05u},
- {0x20u, 0x08u},
- {0x22u, 0x06u},
- {0x2Cu, 0x01u},
- {0x2Eu, 0x02u},
- {0x31u, 0x04u},
- {0x33u, 0x08u},
- {0x34u, 0x0Cu},
- {0x35u, 0x03u},
- {0x36u, 0x03u},
- {0x3Au, 0x20u},
- {0x3Bu, 0x20u},
+ {0xE6u, 0x80u},
+ {0xE8u, 0x21u},
+ {0xEAu, 0x80u},
+ {0xECu, 0x08u},
+ {0xEEu, 0x62u},
+ {0x01u, 0x60u},
+ {0x03u, 0x90u},
+ {0x06u, 0x10u},
+ {0x07u, 0xFFu},
+ {0x08u, 0x0Au},
+ {0x09u, 0x03u},
+ {0x0Au, 0x05u},
+ {0x0Bu, 0x0Cu},
+ {0x0Du, 0x0Fu},
+ {0x0Fu, 0xF0u},
+ {0x10u, 0x10u},
+ {0x11u, 0xFFu},
+ {0x12u, 0x20u},
+ {0x15u, 0x05u},
+ {0x16u, 0x07u},
+ {0x17u, 0x0Au},
+ {0x18u, 0x04u},
+ {0x19u, 0x06u},
+ {0x1Au, 0x08u},
+ {0x1Bu, 0x09u},
+ {0x21u, 0x30u},
+ {0x22u, 0x08u},
+ {0x23u, 0xC0u},
+ {0x24u, 0x09u},
+ {0x26u, 0x02u},
+ {0x27u, 0xFFu},
+ {0x29u, 0x50u},
+ {0x2Au, 0x20u},
+ {0x2Bu, 0xA0u},
+ {0x32u, 0x0Fu},
+ {0x35u, 0xFFu},
+ {0x36u, 0x30u},
{0x3Eu, 0x40u},
- {0x56u, 0x08u},
+ {0x3Fu, 0x10u},
+ {0x56u, 0x02u},
+ {0x57u, 0x28u},
{0x58u, 0x04u},
{0x59u, 0x04u},
{0x5Bu, 0x04u},
- {0x5Cu, 0x99u},
- {0x5Du, 0x90u},
+ {0x5Cu, 0x01u},
{0x5Fu, 0x01u},
- {0x82u, 0x01u},
- {0x84u, 0x34u},
- {0x88u, 0x34u},
- {0x89u, 0x04u},
- {0x8Bu, 0x02u},
- {0x8Cu, 0x01u},
- {0x8Du, 0x02u},
- {0x8Eu, 0x02u},
- {0x8Fu, 0x04u},
- {0x90u, 0x08u},
- {0x91u, 0x08u},
- {0x92u, 0x20u},
- {0x93u, 0x10u},
- {0x94u, 0x08u},
- {0x96u, 0x34u},
- {0x98u, 0x08u},
- {0x9Au, 0x10u},
- {0x9Cu, 0x34u},
- {0xA0u, 0x34u},
- {0xA3u, 0x10u},
- {0xA4u, 0x04u},
- {0xA6u, 0x08u},
- {0xAAu, 0x02u},
- {0xABu, 0x08u},
- {0xACu, 0x34u},
- {0xADu, 0x04u},
- {0xAFu, 0x03u},
- {0xB2u, 0x3Cu},
- {0xB3u, 0x18u},
- {0xB5u, 0x01u},
- {0xB6u, 0x03u},
- {0xB7u, 0x06u},
- {0xBAu, 0x08u},
- {0xBBu, 0x80u},
- {0xBEu, 0x40u},
+ {0x81u, 0x28u},
+ {0x83u, 0x14u},
+ {0x86u, 0x08u},
+ {0x87u, 0x20u},
+ {0x89u, 0x24u},
+ {0x8Au, 0x07u},
+ {0x8Bu, 0x08u},
+ {0x8Cu, 0x0Au},
+ {0x8Eu, 0x05u},
+ {0x8Fu, 0x1Cu},
+ {0x94u, 0x09u},
+ {0x96u, 0x02u},
+ {0x98u, 0x04u},
+ {0x99u, 0x10u},
+ {0x9Au, 0x08u},
+ {0x9Bu, 0x20u},
+ {0x9Cu, 0x10u},
+ {0x9Eu, 0x20u},
+ {0x9Fu, 0x02u},
+ {0xA1u, 0x01u},
+ {0xA2u, 0x20u},
+ {0xA3u, 0x02u},
+ {0xA6u, 0x10u},
+ {0xABu, 0x01u},
+ {0xB0u, 0x30u},
+ {0xB1u, 0x3Cu},
+ {0xB2u, 0x0Fu},
+ {0xB3u, 0x03u},
+ {0xBEu, 0x01u},
{0xBFu, 0x04u},
+ {0xD6u, 0x08u},
{0xD8u, 0x04u},
{0xD9u, 0x04u},
{0xDBu, 0x04u},
- {0xDCu, 0x90u},
+ {0xDCu, 0x11u},
+ {0xDDu, 0x90u},
{0xDFu, 0x01u},
+ {0x00u, 0x18u},
{0x01u, 0x20u},
- {0x05u, 0x09u},
+ {0x02u, 0x01u},
+ {0x05u, 0x04u},
{0x06u, 0x08u},
- {0x07u, 0x01u},
- {0x09u, 0x08u},
- {0x0Eu, 0x19u},
+ {0x08u, 0x10u},
+ {0x09u, 0x40u},
+ {0x0Bu, 0x10u},
+ {0x0Cu, 0x10u},
+ {0x0Eu, 0x20u},
{0x0Fu, 0x80u},
- {0x10u, 0x02u},
- {0x13u, 0x01u},
- {0x14u, 0x01u},
- {0x15u, 0x01u},
- {0x17u, 0x24u},
- {0x19u, 0x60u},
- {0x1Au, 0x02u},
- {0x1Bu, 0x20u},
- {0x1Cu, 0x02u},
- {0x1Eu, 0x10u},
- {0x20u, 0x44u},
- {0x21u, 0x08u},
- {0x23u, 0x08u},
- {0x24u, 0x20u},
- {0x25u, 0x50u},
+ {0x11u, 0x08u},
+ {0x12u, 0x80u},
+ {0x16u, 0xA0u},
+ {0x17u, 0x20u},
+ {0x18u, 0x90u},
+ {0x1Cu, 0x20u},
+ {0x1Eu, 0x20u},
+ {0x1Fu, 0x80u},
+ {0x20u, 0x40u},
+ {0x22u, 0x08u},
+ {0x24u, 0x08u},
+ {0x29u, 0x20u},
+ {0x2Bu, 0x40u},
{0x2Cu, 0x80u},
- {0x2Fu, 0x05u},
- {0x32u, 0x80u},
- {0x34u, 0x02u},
- {0x37u, 0x01u},
- {0x38u, 0x44u},
- {0x3Bu, 0x01u},
- {0x3Du, 0xA0u},
- {0x3Fu, 0x40u},
- {0x58u, 0x20u},
- {0x5Bu, 0x40u},
- {0x62u, 0x10u},
- {0x63u, 0x01u},
- {0x68u, 0x02u},
- {0x6Cu, 0x84u},
- {0x6Eu, 0xC0u},
- {0x6Fu, 0x10u},
- {0x74u, 0x10u},
- {0x76u, 0x42u},
- {0x77u, 0x20u},
- {0x81u, 0x04u},
- {0x82u, 0x30u},
- {0x84u, 0x01u},
- {0x85u, 0x04u},
- {0x86u, 0x04u},
+ {0x2Du, 0x08u},
+ {0x2Fu, 0x04u},
+ {0x30u, 0x90u},
+ {0x35u, 0x02u},
+ {0x36u, 0x10u},
+ {0x37u, 0x08u},
+ {0x38u, 0x40u},
+ {0x39u, 0x06u},
+ {0x3Au, 0x21u},
+ {0x3Bu, 0x10u},
+ {0x3Cu, 0x14u},
+ {0x3Du, 0x80u},
+ {0x3Fu, 0x81u},
+ {0x58u, 0x80u},
+ {0x63u, 0x02u},
+ {0x67u, 0x20u},
+ {0x6Cu, 0x02u},
+ {0x6Du, 0x01u},
+ {0x6Fu, 0x74u},
+ {0x77u, 0x02u},
+ {0x83u, 0x04u},
+ {0x85u, 0x01u},
+ {0x89u, 0x01u},
+ {0x8Au, 0x08u},
+ {0x91u, 0x04u},
+ {0x96u, 0x02u},
+ {0x98u, 0x80u},
+ {0x9Au, 0x80u},
+ {0x9Bu, 0x01u},
+ {0xA0u, 0x04u},
+ {0xA6u, 0x08u},
+ {0xABu, 0x80u},
+ {0xAEu, 0x09u},
+ {0xB3u, 0x01u},
+ {0xB4u, 0x80u},
+ {0xC0u, 0x67u},
+ {0xC2u, 0x77u},
+ {0xC4u, 0x7Cu},
+ {0xCAu, 0xE5u},
+ {0xCCu, 0xECu},
+ {0xCEu, 0xFFu},
+ {0xD6u, 0x08u},
+ {0xD8u, 0x48u},
+ {0xE0u, 0x20u},
+ {0xE6u, 0x40u},
+ {0xE8u, 0x08u},
+ {0xEAu, 0xA0u},
+ {0xECu, 0x20u},
+ {0xEEu, 0x80u},
+ {0xB9u, 0x02u},
+ {0xBFu, 0x01u},
+ {0xD9u, 0x04u},
+ {0xDFu, 0x01u},
+ {0x27u, 0x80u},
+ {0x82u, 0x80u},
+ {0x84u, 0x04u},
{0x89u, 0x04u},
- {0x8Au, 0x02u},
- {0x8Cu, 0x20u},
- {0x8Du, 0x01u},
- {0x8Fu, 0x40u},
- {0x90u, 0x10u},
- {0x92u, 0x80u},
- {0x93u, 0x02u},
- {0x94u, 0x2Cu},
- {0x96u, 0x60u},
- {0x98u, 0x50u},
- {0x9Cu, 0x02u},
- {0x9Du, 0x40u},
- {0x9Eu, 0x60u},
- {0x9Fu, 0x28u},
- {0xA2u, 0x88u},
- {0xA3u, 0x08u},
- {0xA4u, 0x20u},
- {0xA5u, 0x04u},
- {0xA6u, 0x11u},
- {0xA7u, 0x04u},
- {0xA8u, 0x10u},
- {0xAFu, 0x41u},
- {0xB2u, 0x14u},
- {0xB3u, 0x40u},
- {0xB6u, 0x08u},
- {0xB7u, 0x12u},
- {0xC0u, 0xF2u},
- {0xC2u, 0xF4u},
- {0xC4u, 0xF9u},
- {0xCAu, 0xB0u},
- {0xCCu, 0x88u},
- {0xCEu, 0x3Bu},
- {0xD6u, 0x0Cu},
- {0xD8u, 0x0Cu},
{0xE0u, 0x20u},
- {0xE4u, 0x58u},
- {0xE6u, 0x03u},
- {0xE8u, 0x04u},
- {0xECu, 0x61u},
- {0xEEu, 0x84u},
- {0x01u, 0x01u},
- {0x03u, 0x02u},
- {0x04u, 0xFFu},
- {0x07u, 0x27u},
- {0x0Cu, 0xFFu},
- {0x0Du, 0x48u},
- {0x0Fu, 0xB6u},
- {0x11u, 0x07u},
- {0x13u, 0x18u},
- {0x14u, 0x0Fu},
- {0x15u, 0x01u},
- {0x16u, 0xF0u},
- {0x18u, 0x69u},
- {0x19u, 0x20u},
- {0x1Au, 0x96u},
- {0x1Bu, 0xC0u},
- {0x1Cu, 0x55u},
- {0x1Du, 0x20u},
- {0x1Eu, 0xAAu},
- {0x1Fu, 0x07u},
- {0x20u, 0x33u},
- {0x22u, 0xCCu},
- {0x23u, 0x04u},
- {0x26u, 0xFFu},
- {0x29u, 0x6Cu},
+ {0xE2u, 0x40u},
+ {0xE4u, 0x40u},
+ {0x80u, 0x30u},
+ {0x82u, 0xC0u},
+ {0x83u, 0x08u},
+ {0x84u, 0x03u},
+ {0x85u, 0x09u},
+ {0x86u, 0x0Cu},
+ {0x87u, 0x02u},
+ {0x88u, 0x60u},
+ {0x8Au, 0x90u},
+ {0x8Cu, 0x0Fu},
+ {0x8Eu, 0xF0u},
+ {0x91u, 0x10u},
+ {0x93u, 0x20u},
+ {0x94u, 0x50u},
+ {0x96u, 0xA0u},
+ {0x98u, 0x06u},
+ {0x9Au, 0x09u},
+ {0x9Bu, 0x17u},
+ {0x9Cu, 0x05u},
+ {0x9Eu, 0x0Au},
+ {0x9Fu, 0x20u},
+ {0xA5u, 0x04u},
+ {0xA7u, 0x08u},
+ {0xA9u, 0x0Au},
+ {0xABu, 0x05u},
+ {0xB2u, 0xFFu},
+ {0xB3u, 0x0Fu},
+ {0xB7u, 0x30u},
+ {0xBEu, 0x04u},
+ {0xBFu, 0x40u},
+ {0xD8u, 0x04u},
+ {0xD9u, 0x04u},
+ {0xDCu, 0x10u},
+ {0xDFu, 0x01u},
+ {0x01u, 0x08u},
+ {0x03u, 0x80u},
+ {0x05u, 0x10u},
+ {0x07u, 0x91u},
+ {0x09u, 0x08u},
+ {0x0Au, 0x82u},
+ {0x0Eu, 0x10u},
+ {0x0Fu, 0x0Au},
+ {0x11u, 0x20u},
+ {0x1Au, 0x80u},
+ {0x1Bu, 0x80u},
+ {0x1Fu, 0x04u},
+ {0x21u, 0xC8u},
+ {0x22u, 0x09u},
+ {0x23u, 0x40u},
+ {0x25u, 0x40u},
+ {0x27u, 0x10u},
+ {0x29u, 0x81u},
+ {0x2Au, 0x24u},
+ {0x2Cu, 0x08u},
+ {0x2Fu, 0x10u},
+ {0x31u, 0x88u},
+ {0x32u, 0x01u},
+ {0x37u, 0x91u},
+ {0x39u, 0x04u},
+ {0x3Au, 0x80u},
+ {0x3Bu, 0x01u},
+ {0x3Cu, 0x04u},
+ {0x3Du, 0x01u},
+ {0x40u, 0x08u},
+ {0x41u, 0x08u},
+ {0x42u, 0x80u},
+ {0x48u, 0x80u},
+ {0x49u, 0x28u},
+ {0x4Bu, 0x41u},
+ {0x51u, 0x20u},
+ {0x52u, 0x81u},
+ {0x53u, 0x40u},
+ {0x6Bu, 0x01u},
+ {0x80u, 0x40u},
+ {0x81u, 0x30u},
+ {0x82u, 0x81u},
+ {0x85u, 0x08u},
+ {0x88u, 0x88u},
+ {0x8Au, 0x01u},
+ {0x8Du, 0x40u},
+ {0x8Eu, 0x08u},
+ {0x90u, 0x04u},
+ {0x91u, 0x05u},
+ {0x92u, 0x10u},
+ {0x93u, 0x20u},
+ {0x94u, 0x80u},
+ {0x96u, 0x82u},
+ {0x97u, 0x88u},
+ {0x99u, 0x91u},
+ {0x9Au, 0x24u},
+ {0x9Bu, 0x80u},
+ {0x9Fu, 0x01u},
+ {0xA0u, 0x08u},
+ {0xA3u, 0x05u},
+ {0xA5u, 0x78u},
+ {0xA6u, 0x80u},
+ {0xAAu, 0x02u},
+ {0xACu, 0x10u},
+ {0xAFu, 0x81u},
+ {0xB3u, 0x01u},
+ {0xB4u, 0xC0u},
+ {0xB6u, 0x10u},
+ {0xC0u, 0xFCu},
+ {0xC2u, 0xEDu},
+ {0xC4u, 0x02u},
+ {0xCAu, 0x6Fu},
+ {0xCCu, 0xBBu},
+ {0xCEu, 0xCBu},
+ {0xD0u, 0x07u},
+ {0xD2u, 0x0Cu},
+ {0xE0u, 0x04u},
+ {0xE2u, 0x01u},
+ {0xE4u, 0x08u},
+ {0xE8u, 0x0Au},
+ {0xEAu, 0x40u},
+ {0xECu, 0x0Cu},
+ {0x00u, 0x33u},
+ {0x01u, 0x0Fu},
+ {0x02u, 0xCCu},
+ {0x03u, 0xF0u},
+ {0x04u, 0x55u},
+ {0x06u, 0xAAu},
+ {0x07u, 0xFFu},
+ {0x0Cu, 0x0Fu},
+ {0x0Eu, 0xF0u},
+ {0x12u, 0xFFu},
+ {0x13u, 0xFFu},
+ {0x14u, 0xFFu},
+ {0x15u, 0xFFu},
+ {0x1Au, 0xFFu},
+ {0x1Cu, 0xFFu},
+ {0x1Du, 0x55u},
+ {0x1Fu, 0xAAu},
+ {0x21u, 0xFFu},
+ {0x24u, 0x69u},
+ {0x26u, 0x96u},
+ {0x27u, 0xFFu},
+ {0x29u, 0x96u},
{0x2Au, 0xFFu},
- {0x2Bu, 0x93u},
- {0x2Du, 0x4Fu},
- {0x2Eu, 0xFFu},
- {0x2Fu, 0xB0u},
- {0x32u, 0xFFu},
- {0x35u, 0xE0u},
- {0x37u, 0x1Fu},
- {0x3Au, 0x08u},
- {0x3Bu, 0xA0u},
+ {0x2Bu, 0x69u},
+ {0x2Du, 0x33u},
+ {0x2Fu, 0xCCu},
+ {0x31u, 0xFFu},
+ {0x36u, 0xFFu},
+ {0x3Au, 0x80u},
+ {0x3Bu, 0x02u},
{0x56u, 0x08u},
{0x58u, 0x04u},
{0x59u, 0x04u},
{0x5Cu, 0x11u},
{0x5Du, 0x90u},
{0x5Fu, 0x01u},
- {0x81u, 0x0Fu},
- {0x83u, 0xF0u},
- {0x86u, 0x07u},
- {0x87u, 0xFFu},
- {0x88u, 0x04u},
- {0x89u, 0xFFu},
- {0x8Au, 0x08u},
- {0x8Du, 0x33u},
- {0x8Fu, 0xCCu},
- {0x90u, 0x10u},
- {0x92u, 0x20u},
- {0x96u, 0x10u},
- {0x97u, 0xFFu},
- {0x99u, 0x69u},
- {0x9Bu, 0x96u},
- {0x9Du, 0xFFu},
- {0xA2u, 0x20u},
- {0xA3u, 0xFFu},
- {0xA4u, 0x0Au},
- {0xA6u, 0x05u},
- {0xA9u, 0x55u},
- {0xAAu, 0x08u},
- {0xABu, 0xAAu},
- {0xACu, 0x09u},
- {0xAEu, 0x02u},
- {0xB2u, 0x0Fu},
- {0xB4u, 0x30u},
- {0xB7u, 0xFFu},
- {0xBBu, 0x80u},
- {0xBEu, 0x10u},
- {0xD6u, 0x08u},
+ {0x81u, 0x0Cu},
+ {0x82u, 0x70u},
+ {0x84u, 0x10u},
+ {0x86u, 0x2Fu},
+ {0x8Cu, 0x03u},
+ {0x8Du, 0x03u},
+ {0x8Eu, 0x0Cu},
+ {0x8Fu, 0x08u},
+ {0x91u, 0x03u},
+ {0x93u, 0x04u},
+ {0x94u, 0x0Fu},
+ {0x95u, 0x05u},
+ {0x97u, 0x02u},
+ {0x98u, 0x40u},
+ {0x9Au, 0x1Fu},
+ {0xA0u, 0x06u},
+ {0xA2u, 0x09u},
+ {0xA8u, 0x20u},
+ {0xAAu, 0x4Fu},
+ {0xACu, 0x05u},
+ {0xAEu, 0x0Au},
+ {0xB1u, 0x0Eu},
+ {0xB5u, 0x01u},
+ {0xB6u, 0x7Fu},
+ {0xB9u, 0x02u},
+ {0xBFu, 0x10u},
+ {0xD4u, 0x40u},
+ {0xD6u, 0x04u},
{0xD8u, 0x04u},
{0xD9u, 0x04u},
{0xDBu, 0x04u},
- {0xDCu, 0x11u},
- {0xDDu, 0x90u},
+ {0xDCu, 0x01u},
{0xDFu, 0x01u},
- {0x01u, 0x08u},
- {0x02u, 0x08u},
+ {0x00u, 0x84u},
+ {0x03u, 0x90u},
+ {0x04u, 0x08u},
{0x05u, 0x40u},
- {0x06u, 0x20u},
- {0x08u, 0x02u},
- {0x0Au, 0x20u},
- {0x0Du, 0x48u},
- {0x0Fu, 0x08u},
- {0x11u, 0x18u},
- {0x12u, 0x41u},
- {0x16u, 0x01u},
- {0x17u, 0x19u},
- {0x18u, 0x10u},
- {0x19u, 0x08u},
- {0x1Au, 0x08u},
- {0x1Du, 0x08u},
- {0x1Fu, 0x08u},
- {0x20u, 0x01u},
- {0x22u, 0x40u},
- {0x26u, 0x20u},
- {0x27u, 0x02u},
- {0x2Au, 0x11u},
- {0x2Du, 0x01u},
- {0x2Eu, 0x20u},
- {0x2Fu, 0x02u},
- {0x30u, 0x20u},
- {0x31u, 0x40u},
- {0x32u, 0x08u},
- {0x35u, 0x40u},
- {0x36u, 0x24u},
- {0x37u, 0x02u},
- {0x38u, 0x05u},
- {0x3Au, 0x20u},
- {0x3Bu, 0x80u},
+ {0x06u, 0x81u},
+ {0x09u, 0x04u},
+ {0x0Au, 0x04u},
+ {0x0Cu, 0x09u},
+ {0x0Du, 0x02u},
+ {0x0Eu, 0x05u},
+ {0x10u, 0x0Cu},
+ {0x11u, 0x02u},
+ {0x12u, 0x01u},
+ {0x16u, 0x10u},
+ {0x17u, 0x10u},
+ {0x1Bu, 0x80u},
+ {0x1Du, 0x40u},
+ {0x21u, 0x01u},
+ {0x22u, 0x10u},
+ {0x25u, 0x01u},
+ {0x2Du, 0x20u},
+ {0x2Eu, 0x05u},
+ {0x2Fu, 0x11u},
+ {0x31u, 0x08u},
+ {0x32u, 0x01u},
+ {0x34u, 0x45u},
+ {0x38u, 0x82u},
+ {0x39u, 0x02u},
{0x3Cu, 0x04u},
- {0x3Eu, 0x02u},
- {0x3Fu, 0x80u},
- {0x5Bu, 0x40u},
- {0x5Eu, 0x10u},
- {0x5Fu, 0x40u},
+ {0x3Du, 0x02u},
+ {0x5Cu, 0x80u},
+ {0x60u, 0x40u},
+ {0x61u, 0x20u},
{0x62u, 0x80u},
- {0x64u, 0x08u},
+ {0x63u, 0x20u},
{0x67u, 0x02u},
- {0x80u, 0x08u},
- {0x81u, 0x40u},
- {0x83u, 0x40u},
- {0x84u, 0x40u},
- {0x86u, 0x40u},
- {0x8Bu, 0x22u},
- {0x8Eu, 0x03u},
- {0x8Fu, 0x40u},
- {0x91u, 0x11u},
- {0x92u, 0x10u},
- {0x94u, 0x18u},
- {0x96u, 0x40u},
- {0x98u, 0x10u},
- {0xA2u, 0x04u},
- {0xA6u, 0x31u},
- {0xAAu, 0x51u},
- {0xADu, 0x01u},
- {0xAEu, 0x20u},
- {0xC0u, 0xA6u},
- {0xC2u, 0xECu},
- {0xC4u, 0xFFu},
- {0xCAu, 0xB5u},
- {0xCCu, 0xFEu},
- {0xCEu, 0xDFu},
- {0xD6u, 0x38u},
- {0xD8u, 0x38u},
- {0xE0u, 0x40u},
- {0xE2u, 0x20u},
- {0xE4u, 0x40u},
- {0xE6u, 0x32u},
- {0x80u, 0x04u},
- {0x86u, 0x10u},
- {0x88u, 0x10u},
- {0x89u, 0x10u},
- {0x8Cu, 0x10u},
- {0x8Eu, 0x04u},
- {0xE0u, 0xE0u},
- {0xE2u, 0x12u},
- {0x80u, 0x01u},
- {0x84u, 0x08u},
- {0x86u, 0x21u},
- {0x8Cu, 0x01u},
- {0x90u, 0x01u},
- {0x94u, 0x10u},
- {0x98u, 0x01u},
- {0x99u, 0x01u},
- {0x9Cu, 0x04u},
- {0xA0u, 0x01u},
- {0xA4u, 0x07u},
- {0xA5u, 0x01u},
- {0xA6u, 0x18u},
- {0xA8u, 0x22u},
- {0xAAu, 0x08u},
- {0xB1u, 0x01u},
- {0xB4u, 0x3Fu},
- {0xB8u, 0x20u},
- {0xB9u, 0x02u},
- {0xBEu, 0x10u},
- {0xD8u, 0x04u},
- {0xD9u, 0x04u},
- {0xDFu, 0x01u},
- {0x01u, 0x04u},
- {0x02u, 0x08u},
- {0x03u, 0x41u},
- {0x05u, 0x08u},
- {0x07u, 0x41u},
- {0x09u, 0x91u},
- {0x0Au, 0x10u},
- {0x0Cu, 0x0Au},
- {0x0Eu, 0x06u},
- {0x10u, 0x82u},
- {0x13u, 0x08u},
- {0x15u, 0x01u},
- {0x17u, 0x18u},
- {0x19u, 0x08u},
- {0x1Au, 0x11u},
- {0x1Bu, 0x10u},
- {0x1Fu, 0x20u},
- {0x20u, 0x04u},
- {0x21u, 0x18u},
- {0x26u, 0x03u},
- {0x29u, 0x02u},
- {0x2Fu, 0x20u},
- {0x31u, 0x08u},
- {0x32u, 0x20u},
- {0x33u, 0x80u},
- {0x37u, 0x20u},
- {0x38u, 0x80u},
- {0x39u, 0x28u},
- {0x42u, 0x91u},
- {0x43u, 0x10u},
- {0x48u, 0x80u},
- {0x49u, 0x04u},
- {0x4Au, 0x04u},
- {0x4Bu, 0x01u},
- {0x50u, 0x08u},
- {0x51u, 0x80u},
- {0x52u, 0x14u},
- {0x53u, 0x44u},
- {0x62u, 0x11u},
- {0x63u, 0x21u},
- {0x81u, 0x08u},
- {0x82u, 0x80u},
- {0x88u, 0x10u},
- {0x89u, 0x80u},
- {0x8Cu, 0x04u},
- {0x8Du, 0x08u},
- {0x90u, 0x80u},
- {0x91u, 0x0Du},
- {0x92u, 0x04u},
- {0x96u, 0x01u},
+ {0x68u, 0x90u},
+ {0x69u, 0x90u},
+ {0x71u, 0x10u},
+ {0x72u, 0x12u},
+ {0x73u, 0x80u},
+ {0x81u, 0x41u},
+ {0x82u, 0x02u},
+ {0x85u, 0x40u},
+ {0x8Cu, 0x80u},
+ {0x8Eu, 0x10u},
+ {0x90u, 0x0Cu},
+ {0x91u, 0x05u},
+ {0x92u, 0x01u},
+ {0x93u, 0x20u},
+ {0x94u, 0x02u},
+ {0x95u, 0x90u},
+ {0x96u, 0x82u},
{0x97u, 0x88u},
- {0x99u, 0x02u},
- {0x9Bu, 0x79u},
- {0x9Cu, 0x10u},
- {0x9Du, 0x0Cu},
- {0x9Eu, 0x05u},
- {0xA0u, 0x02u},
- {0xA1u, 0x11u},
- {0xA2u, 0x2Cu},
- {0xA3u, 0x80u},
+ {0x98u, 0x40u},
+ {0x99u, 0xA0u},
+ {0x9Au, 0xB4u},
+ {0x9Du, 0x10u},
+ {0x9Fu, 0x01u},
+ {0xA0u, 0x48u},
+ {0xA1u, 0x06u},
+ {0xA3u, 0x14u},
+ {0xA4u, 0x10u},
+ {0xA5u, 0x18u},
{0xA6u, 0x02u},
- {0xAAu, 0x11u},
- {0xACu, 0x42u},
- {0xB1u, 0x01u},
- {0xB2u, 0x04u},
- {0xB7u, 0x28u},
- {0xC0u, 0xBFu},
- {0xC2u, 0xFFu},
- {0xC4u, 0x7Du},
- {0xCAu, 0x41u},
- {0xCCu, 0x2Eu},
- {0xCEu, 0x0Eu},
- {0xD0u, 0x0Fu},
- {0xD2u, 0x04u},
- {0xD8u, 0x0Fu},
- {0xE4u, 0x04u},
- {0xE8u, 0x0Au},
- {0xEEu, 0x04u},
- {0x01u, 0xC0u},
- {0x03u, 0x02u},
- {0x04u, 0x07u},
- {0x05u, 0xC0u},
- {0x06u, 0x08u},
- {0x07u, 0x04u},
- {0x09u, 0xC0u},
- {0x0Bu, 0x08u},
- {0x0Du, 0xC0u},
+ {0xA9u, 0x81u},
+ {0xB5u, 0x80u},
+ {0xB7u, 0x20u},
+ {0xC0u, 0xBDu},
+ {0xC2u, 0xF6u},
+ {0xC4u, 0x6Bu},
+ {0xCAu, 0xF0u},
+ {0xCCu, 0xD3u},
+ {0xCEu, 0xC9u},
+ {0xD6u, 0x10u},
+ {0xD8u, 0x1Fu},
+ {0xE0u, 0x03u},
+ {0xE2u, 0x0Cu},
+ {0xE8u, 0x04u},
+ {0xEEu, 0x09u},
+ {0x80u, 0x02u},
+ {0x83u, 0x01u},
+ {0x87u, 0x40u},
+ {0x8Fu, 0x01u},
+ {0x90u, 0x40u},
+ {0x97u, 0x21u},
+ {0x9Bu, 0x56u},
+ {0x9Cu, 0x40u},
+ {0x9Eu, 0x01u},
+ {0x9Fu, 0x20u},
+ {0xA0u, 0x06u},
+ {0xA2u, 0x10u},
+ {0xA4u, 0x80u},
+ {0xA5u, 0x40u},
+ {0xA6u, 0x82u},
+ {0xA9u, 0xA0u},
+ {0xB5u, 0x40u},
+ {0xB7u, 0x10u},
+ {0xE0u, 0x42u},
+ {0xE2u, 0x10u},
+ {0xECu, 0x10u},
+ {0xEEu, 0x48u},
+ {0x00u, 0x01u},
+ {0x04u, 0x01u},
+ {0x08u, 0x07u},
+ {0x0Au, 0x18u},
+ {0x0Cu, 0x22u},
+ {0x0Eu, 0x08u},
{0x0Fu, 0x01u},
- {0x10u, 0x08u},
- {0x12u, 0x06u},
- {0x13u, 0x60u},
- {0x15u, 0x1Fu},
- {0x17u, 0x20u},
- {0x19u, 0x7Fu},
- {0x1Bu, 0x80u},
- {0x1Du, 0x80u},
- {0x24u, 0x03u},
- {0x26u, 0x0Cu},
- {0x27u, 0xFFu},
- {0x28u, 0x0Bu},
- {0x2Au, 0x04u},
- {0x2Bu, 0x9Fu},
- {0x2Du, 0x90u},
- {0x2Fu, 0x40u},
- {0x30u, 0x0Eu},
- {0x33u, 0xFFu},
- {0x34u, 0x0Eu},
- {0x36u, 0x01u},
- {0x3Au, 0x22u},
- {0x3Eu, 0x40u},
- {0x3Fu, 0x04u},
- {0x56u, 0x02u},
- {0x57u, 0x28u},
+ {0x11u, 0x04u},
+ {0x14u, 0x08u},
+ {0x16u, 0x21u},
+ {0x18u, 0x10u},
+ {0x19u, 0x01u},
+ {0x1Bu, 0x02u},
+ {0x1Cu, 0x04u},
+ {0x20u, 0x01u},
+ {0x23u, 0x02u},
+ {0x25u, 0x04u},
+ {0x28u, 0x01u},
+ {0x2Cu, 0x01u},
+ {0x31u, 0x03u},
+ {0x32u, 0x3Fu},
+ {0x37u, 0x04u},
+ {0x38u, 0x08u},
+ {0x39u, 0x80u},
+ {0x3Eu, 0x04u},
+ {0x3Fu, 0x01u},
{0x58u, 0x04u},
{0x59u, 0x04u},
- {0x5Bu, 0x04u},
{0x5Fu, 0x01u},
- {0x80u, 0x19u},
- {0x82u, 0x22u},
- {0x87u, 0x10u},
- {0x89u, 0x20u},
- {0x8Bu, 0x40u},
- {0x8Fu, 0x2Eu},
- {0x90u, 0x04u},
- {0x91u, 0x09u},
- {0x92u, 0x48u},
- {0x93u, 0x10u},
- {0x94u, 0x10u},
- {0x97u, 0x01u},
- {0x99u, 0x15u},
- {0x9Au, 0x07u},
- {0x9Bu, 0x0Au},
- {0x9Fu, 0x01u},
- {0xA1u, 0x13u},
- {0xA2u, 0x08u},
- {0xA3u, 0x04u},
- {0xA4u, 0x0Au},
- {0xA6u, 0x55u},
- {0xA8u, 0x20u},
- {0xAAu, 0x50u},
+ {0x80u, 0x86u},
+ {0x83u, 0x60u},
+ {0x84u, 0x39u},
+ {0x86u, 0x46u},
+ {0x88u, 0x17u},
+ {0x89u, 0x80u},
+ {0x8Au, 0x68u},
+ {0x8Cu, 0x51u},
+ {0x8Du, 0x7Fu},
+ {0x8Eu, 0x2Eu},
+ {0x8Fu, 0x80u},
+ {0x90u, 0x06u},
+ {0x91u, 0xC0u},
+ {0x92u, 0x80u},
+ {0x93u, 0x01u},
+ {0x94u, 0x02u},
+ {0x95u, 0xC0u},
+ {0x97u, 0x08u},
+ {0x98u, 0x40u},
+ {0x99u, 0xC0u},
+ {0x9Au, 0x30u},
+ {0x9Bu, 0x04u},
+ {0x9Cu, 0x04u},
+ {0x9Du, 0xC0u},
+ {0x9Fu, 0x02u},
+ {0xA0u, 0x86u},
+ {0xA3u, 0x9Fu},
+ {0xA4u, 0x80u},
+ {0xA5u, 0x1Fu},
+ {0xA6u, 0x06u},
+ {0xA7u, 0x20u},
+ {0xA8u, 0x82u},
+ {0xAAu, 0x04u},
+ {0xABu, 0xFFu},
+ {0xADu, 0x90u},
{0xAFu, 0x40u},
- {0xB0u, 0x70u},
- {0xB1u, 0x1Eu},
- {0xB4u, 0x0Fu},
- {0xB5u, 0x60u},
- {0xB7u, 0x01u},
- {0xBAu, 0x02u},
- {0xBFu, 0x50u},
+ {0xB0u, 0x08u},
+ {0xB2u, 0x0Fu},
+ {0xB4u, 0x70u},
+ {0xB6u, 0x80u},
+ {0xB7u, 0xFFu},
+ {0xB8u, 0x08u},
+ {0xBAu, 0x20u},
+ {0xBEu, 0x41u},
+ {0xBFu, 0x40u},
{0xD4u, 0x09u},
{0xD6u, 0x04u},
{0xD8u, 0x04u},
{0xD9u, 0x04u},
{0xDBu, 0x04u},
- {0xDCu, 0x11u},
{0xDFu, 0x01u},
- {0x01u, 0x02u},
- {0x05u, 0x08u},
- {0x08u, 0x03u},
- {0x09u, 0x04u},
- {0x0Au, 0x08u},
- {0x0Eu, 0x80u},
- {0x10u, 0x84u},
- {0x12u, 0x20u},
- {0x17u, 0x18u},
- {0x19u, 0x02u},
- {0x1Au, 0x48u},
- {0x1Du, 0x80u},
- {0x1Eu, 0x80u},
- {0x1Fu, 0x10u},
- {0x20u, 0x48u},
- {0x22u, 0x80u},
- {0x27u, 0x20u},
- {0x29u, 0x02u},
- {0x2Au, 0xC0u},
+ {0x01u, 0xA0u},
+ {0x03u, 0x50u},
+ {0x05u, 0x84u},
+ {0x06u, 0x08u},
+ {0x07u, 0x40u},
+ {0x0Au, 0x18u},
+ {0x0Bu, 0x01u},
+ {0x0Cu, 0x0Au},
+ {0x0Eu, 0x09u},
+ {0x10u, 0x0Au},
+ {0x13u, 0x02u},
+ {0x17u, 0x16u},
+ {0x19u, 0x08u},
+ {0x1Cu, 0x01u},
+ {0x1Du, 0x04u},
+ {0x1Eu, 0x58u},
+ {0x1Fu, 0x90u},
+ {0x22u, 0x02u},
+ {0x23u, 0x01u},
+ {0x27u, 0x01u},
+ {0x29u, 0x08u},
+ {0x2Au, 0x01u},
{0x2Cu, 0x02u},
- {0x2Du, 0x08u},
- {0x2Fu, 0x04u},
- {0x30u, 0x41u},
- {0x32u, 0x20u},
- {0x33u, 0x04u},
- {0x36u, 0x06u},
- {0x37u, 0x58u},
+ {0x2Du, 0x02u},
+ {0x2Eu, 0x18u},
+ {0x30u, 0x20u},
+ {0x33u, 0x01u},
+ {0x37u, 0x56u},
{0x38u, 0x40u},
- {0x3Bu, 0x14u},
- {0x3Cu, 0x80u},
- {0x3Du, 0x22u},
- {0x3Eu, 0x04u},
- {0x40u, 0x02u},
- {0x43u, 0x80u},
- {0x58u, 0x10u},
- {0x59u, 0x04u},
- {0x5Au, 0x81u},
- {0x61u, 0x80u},
- {0x63u, 0x40u},
- {0x67u, 0x20u},
- {0x6Cu, 0x02u},
- {0x6Du, 0x27u},
- {0x6Eu, 0x04u},
- {0x6Fu, 0x28u},
- {0x74u, 0x40u},
- {0x77u, 0x01u},
- {0x86u, 0x40u},
- {0x87u, 0x40u},
- {0x88u, 0x04u},
+ {0x3Du, 0x20u},
+ {0x3Fu, 0x81u},
+ {0x44u, 0x20u},
+ {0x47u, 0x08u},
+ {0x5Cu, 0x25u},
+ {0x5Eu, 0x40u},
+ {0x67u, 0x82u},
+ {0x80u, 0x04u},
+ {0x82u, 0x10u},
+ {0x85u, 0x02u},
+ {0x86u, 0x04u},
+ {0x89u, 0x20u},
+ {0x8Au, 0x09u},
+ {0x8Bu, 0x88u},
+ {0x8Cu, 0x08u},
+ {0x8Du, 0x90u},
{0x8Fu, 0x40u},
- {0x90u, 0x80u},
- {0x91u, 0x08u},
- {0x92u, 0x80u},
- {0x93u, 0x14u},
- {0x94u, 0x40u},
- {0x96u, 0x64u},
- {0x97u, 0x80u},
- {0x98u, 0x44u},
- {0x9Bu, 0x5Cu},
- {0x9Du, 0x08u},
- {0x9Eu, 0x84u},
- {0x9Fu, 0x01u},
- {0xA0u, 0x80u},
- {0xA1u, 0x04u},
- {0xA2u, 0x28u},
- {0xA3u, 0xC0u},
- {0xA4u, 0x02u},
- {0xA5u, 0x01u},
- {0xA6u, 0x80u},
- {0xA7u, 0x08u},
- {0xA8u, 0x20u},
- {0xA9u, 0x04u},
- {0xABu, 0x04u},
- {0xADu, 0x01u},
- {0xB0u, 0x01u},
- {0xB2u, 0x01u},
- {0xB3u, 0x08u},
- {0xB5u, 0x04u},
+ {0x90u, 0x40u},
+ {0x93u, 0x02u},
+ {0x97u, 0xA0u},
+ {0x9Au, 0x01u},
+ {0x9Bu, 0x56u},
+ {0xA0u, 0x22u},
+ {0xA6u, 0x02u},
+ {0xAAu, 0x80u},
+ {0xACu, 0xE0u},
+ {0xADu, 0x40u},
+ {0xB0u, 0x04u},
+ {0xB2u, 0x10u},
{0xB6u, 0x01u},
- {0xC0u, 0x28u},
- {0xC2u, 0x1Eu},
- {0xC4u, 0x6Eu},
- {0xCAu, 0x79u},
- {0xCCu, 0xFFu},
- {0xCEu, 0xFEu},
- {0xD6u, 0x0Fu},
- {0xD8u, 0x49u},
- {0xE2u, 0x08u},
- {0xE6u, 0x01u},
- {0xEAu, 0x08u},
- {0xEEu, 0x21u},
- {0x80u, 0x04u},
- {0x84u, 0x10u},
- {0x91u, 0x20u},
- {0x94u, 0x80u},
- {0x95u, 0x01u},
- {0x96u, 0x01u},
- {0x97u, 0x08u},
- {0x9Cu, 0x01u},
- {0x9Du, 0x48u},
- {0x9Eu, 0x08u},
- {0x9Fu, 0x08u},
- {0xA0u, 0x10u},
- {0xA6u, 0x04u},
- {0xA8u, 0x48u},
- {0xAAu, 0x40u},
- {0xAFu, 0x08u},
- {0xB0u, 0x02u},
- {0xB2u, 0x20u},
- {0xB5u, 0x01u},
+ {0xB7u, 0x20u},
+ {0xC0u, 0xFFu},
+ {0xC2u, 0xF7u},
+ {0xC4u, 0x7Bu},
+ {0xCAu, 0xF3u},
+ {0xCCu, 0xF5u},
+ {0xCEu, 0xB8u},
+ {0xD6u, 0xF0u},
+ {0xD8u, 0x90u},
{0xE0u, 0x20u},
- {0xE4u, 0x40u},
- {0xE8u, 0x80u},
- {0xECu, 0x40u},
- {0xEEu, 0x20u},
- {0x38u, 0x20u},
- {0x3Eu, 0x10u},
- {0x58u, 0x04u},
- {0x5Fu, 0x01u},
- {0x18u, 0x08u},
- {0x82u, 0x04u},
- {0x8Cu, 0x40u},
- {0x8Fu, 0x08u},
- {0x94u, 0x88u},
- {0x9Fu, 0x08u},
- {0xA6u, 0x04u},
- {0xACu, 0x01u},
- {0xADu, 0x01u},
- {0xB1u, 0x50u},
- {0xB2u, 0x01u},
- {0xB3u, 0x04u},
- {0xB5u, 0x08u},
- {0xB6u, 0x08u},
- {0xE4u, 0x50u},
- {0xE8u, 0xD0u},
- {0xECu, 0x80u},
- {0xEEu, 0x04u},
- {0x07u, 0x04u},
- {0x0Eu, 0x02u},
- {0x12u, 0x08u},
+ {0xE2u, 0x80u},
+ {0xE4u, 0xD0u},
+ {0xEAu, 0x80u},
+ {0xECu, 0x50u},
+ {0x04u, 0x10u},
+ {0x0Cu, 0x20u},
+ {0x13u, 0x20u},
{0x16u, 0x80u},
- {0x17u, 0x20u},
- {0x30u, 0x02u},
- {0x35u, 0x02u},
+ {0x17u, 0x80u},
+ {0x31u, 0x04u},
+ {0x34u, 0x02u},
{0x36u, 0x80u},
+ {0x39u, 0x01u},
{0x3Au, 0x80u},
- {0x3Bu, 0x01u},
- {0x3Cu, 0x44u},
- {0x42u, 0x08u},
- {0x62u, 0x02u},
- {0x8Cu, 0x40u},
+ {0x3Eu, 0x10u},
+ {0x3Fu, 0x08u},
+ {0x42u, 0x01u},
+ {0x65u, 0x80u},
+ {0x8Eu, 0x10u},
{0xC0u, 0x80u},
{0xC2u, 0x80u},
{0xC4u, 0xE0u},
{0xCCu, 0xE0u},
{0xCEu, 0xF0u},
{0xD0u, 0x10u},
- {0xD8u, 0x40u},
- {0x32u, 0x01u},
+ {0xD6u, 0x80u},
+ {0x30u, 0x04u},
{0x33u, 0x10u},
- {0x34u, 0x04u},
- {0x37u, 0x20u},
- {0x39u, 0x40u},
- {0x53u, 0x10u},
- {0x57u, 0x80u},
- {0x5Cu, 0x01u},
- {0x82u, 0x01u},
- {0x8Bu, 0x10u},
- {0x8Fu, 0x80u},
- {0x94u, 0x04u},
- {0x9Bu, 0x30u},
- {0x9Du, 0x02u},
- {0x9Eu, 0x08u},
- {0xA2u, 0x01u},
- {0xA4u, 0x02u},
+ {0x35u, 0x01u},
+ {0x37u, 0x80u},
+ {0x3Bu, 0x40u},
+ {0x51u, 0x20u},
+ {0x58u, 0x80u},
+ {0x62u, 0x02u},
+ {0x6Bu, 0x30u},
+ {0x83u, 0x01u},
+ {0x87u, 0x20u},
+ {0x90u, 0x10u},
+ {0x96u, 0x01u},
+ {0x9Bu, 0xA4u},
+ {0x9Du, 0x84u},
+ {0xA0u, 0x20u},
{0xA6u, 0x80u},
- {0xAAu, 0x08u},
- {0xABu, 0x14u},
- {0xAEu, 0x02u},
- {0xB7u, 0x01u},
+ {0xA7u, 0x04u},
+ {0xABu, 0x04u},
+ {0xACu, 0x02u},
+ {0xADu, 0x01u},
{0xCCu, 0xF0u},
{0xCEu, 0x10u},
- {0xD4u, 0x60u},
- {0xD6u, 0x80u},
- {0xE4u, 0x80u},
- {0xE8u, 0x80u},
- {0xEAu, 0x40u},
+ {0xD4u, 0xA0u},
+ {0xD8u, 0x40u},
+ {0xE6u, 0x30u},
+ {0xEAu, 0x90u},
+ {0xEEu, 0x40u},
{0x12u, 0x80u},
- {0x30u, 0x20u},
- {0x84u, 0x02u},
- {0x94u, 0x04u},
- {0x96u, 0x02u},
- {0x9Cu, 0x04u},
- {0x9Eu, 0x08u},
- {0xA3u, 0x40u},
- {0xA4u, 0x02u},
- {0xA6u, 0x80u},
- {0xA9u, 0x40u},
- {0xABu, 0x40u},
- {0xB1u, 0x02u},
- {0xB4u, 0x01u},
+ {0x33u, 0x80u},
+ {0x5Bu, 0x04u},
+ {0x80u, 0x80u},
+ {0x85u, 0x80u},
+ {0x88u, 0x04u},
+ {0x8Cu, 0x10u},
+ {0x8Du, 0x20u},
+ {0x8Eu, 0x02u},
+ {0x90u, 0x10u},
+ {0x93u, 0x02u},
+ {0x96u, 0x01u},
+ {0x97u, 0x40u},
+ {0x9Bu, 0x04u},
+ {0x9Cu, 0x84u},
+ {0x9Du, 0x85u},
+ {0xA0u, 0x20u},
+ {0xA3u, 0x20u},
+ {0xA5u, 0x20u},
+ {0xA6u, 0x82u},
+ {0xA7u, 0x04u},
{0xC4u, 0x10u},
{0xCCu, 0x10u},
+ {0xD6u, 0x40u},
{0xE2u, 0x10u},
+ {0xE6u, 0x80u},
+ {0x81u, 0x04u},
+ {0x93u, 0x02u},
+ {0x96u, 0x01u},
+ {0x9Du, 0x04u},
+ {0xA3u, 0x20u},
+ {0xA7u, 0x84u},
+ {0xA9u, 0x01u},
+ {0xACu, 0x20u},
+ {0xAFu, 0x40u},
+ {0xE6u, 0x80u},
+ {0xE8u, 0x40u},
{0xEAu, 0x20u},
- {0xEEu, 0x20u},
- {0x84u, 0x04u},
- {0x86u, 0x01u},
- {0x8Du, 0x02u},
- {0x94u, 0x04u},
- {0x96u, 0x02u},
- {0x9Cu, 0x04u},
- {0x9Eu, 0x08u},
- {0xA3u, 0x40u},
- {0xA4u, 0x20u},
- {0xE2u, 0x10u},
- {0xE6u, 0x40u},
- {0x01u, 0x20u},
- {0x06u, 0x01u},
- {0x0Bu, 0x04u},
- {0x0Du, 0x80u},
- {0x13u, 0x08u},
- {0x14u, 0x80u},
- {0x58u, 0x02u},
- {0x62u, 0x08u},
- {0x87u, 0x04u},
+ {0xEEu, 0x40u},
+ {0x01u, 0x40u},
+ {0x04u, 0x10u},
+ {0x08u, 0x20u},
+ {0x0Cu, 0x80u},
+ {0x10u, 0x10u},
+ {0x14u, 0x40u},
+ {0x62u, 0x04u},
+ {0x67u, 0x80u},
+ {0x8Cu, 0x20u},
+ {0x8Fu, 0x08u},
{0xC0u, 0x03u},
{0xC2u, 0x03u},
{0xC4u, 0x0Cu},
- {0xD6u, 0x02u},
- {0xD8u, 0x02u},
- {0x00u, 0x08u},
- {0x05u, 0x02u},
- {0x09u, 0x08u},
- {0x0Cu, 0x02u},
- {0x57u, 0x01u},
- {0x59u, 0x40u},
- {0x5Au, 0x04u},
- {0x5Fu, 0x02u},
- {0x84u, 0x80u},
- {0x8Du, 0x08u},
- {0x98u, 0x80u},
- {0x99u, 0x20u},
- {0x9Au, 0x01u},
+ {0xD8u, 0x03u},
+ {0xE2u, 0x02u},
+ {0xE4u, 0x02u},
+ {0x01u, 0x04u},
+ {0x04u, 0x08u},
+ {0x09u, 0x02u},
+ {0x0Fu, 0x40u},
+ {0x55u, 0x40u},
+ {0x58u, 0x40u},
+ {0x5Bu, 0x08u},
+ {0x5Cu, 0x01u},
+ {0x8Eu, 0x08u},
+ {0x91u, 0x40u},
{0x9Bu, 0x08u},
- {0x9Cu, 0x02u},
- {0xA1u, 0x80u},
- {0xA6u, 0x08u},
+ {0x9Eu, 0x04u},
+ {0xAFu, 0x40u},
+ {0xB0u, 0xD0u},
+ {0xB4u, 0x10u},
{0xC0u, 0x0Cu},
{0xC2u, 0x0Cu},
- {0xD4u, 0x01u},
- {0xD6u, 0x07u},
- {0xE6u, 0x08u},
- {0x80u, 0x10u},
- {0x85u, 0x80u},
- {0x87u, 0x01u},
- {0x8Au, 0x04u},
- {0x8Du, 0x20u},
- {0x96u, 0x04u},
- {0x97u, 0x02u},
- {0x99u, 0x22u},
- {0x9Au, 0x01u},
- {0x9Bu, 0x08u},
- {0x9Fu, 0x02u},
- {0xA1u, 0x80u},
- {0xA7u, 0x01u},
- {0xA8u, 0x02u},
- {0xAAu, 0x08u},
- {0xABu, 0x01u},
- {0xB0u, 0x06u},
- {0xB1u, 0x40u},
- {0xE2u, 0x08u},
- {0xE4u, 0x04u},
- {0xE8u, 0x01u},
- {0xEAu, 0x04u},
+ {0xD4u, 0x03u},
+ {0xD6u, 0x03u},
+ {0xE6u, 0x02u},
+ {0xEAu, 0x0Du},
{0xEEu, 0x01u},
- {0x0Bu, 0x22u},
- {0x0Cu, 0x02u},
- {0x0Eu, 0x04u},
- {0x82u, 0x01u},
- {0x84u, 0x02u},
- {0x87u, 0x10u},
- {0x94u, 0x10u},
- {0x97u, 0x02u},
- {0x9Au, 0x01u},
- {0x9Fu, 0x02u},
- {0xAFu, 0x08u},
+ {0x56u, 0x80u},
+ {0x8Bu, 0x40u},
+ {0x8Du, 0x40u},
+ {0x8Eu, 0x80u},
+ {0x90u, 0x08u},
+ {0x91u, 0x44u},
+ {0x94u, 0x20u},
+ {0x9Eu, 0x04u},
+ {0xA5u, 0x40u},
+ {0xA6u, 0x08u},
+ {0xA8u, 0x01u},
+ {0xACu, 0x40u},
+ {0xAFu, 0x40u},
{0xB1u, 0x02u},
+ {0xB4u, 0x10u},
+ {0xD4u, 0x02u},
+ {0xE2u, 0x02u},
+ {0xE4u, 0x08u},
+ {0xE6u, 0x01u},
+ {0xEEu, 0x06u},
+ {0x08u, 0x80u},
+ {0x0Bu, 0x80u},
+ {0x0Fu, 0x82u},
+ {0x82u, 0x04u},
+ {0x85u, 0x20u},
+ {0x89u, 0x04u},
+ {0x90u, 0x08u},
+ {0x91u, 0x04u},
+ {0x94u, 0x20u},
+ {0x97u, 0x80u},
+ {0x9Cu, 0x80u},
+ {0x9Eu, 0x04u},
+ {0xA5u, 0x40u},
+ {0xA6u, 0x08u},
+ {0xA7u, 0x40u},
+ {0xABu, 0x40u},
+ {0xACu, 0x80u},
{0xC2u, 0x0Fu},
- {0xEAu, 0x01u},
- {0x64u, 0x80u},
- {0x80u, 0x80u},
- {0x86u, 0x08u},
- {0x94u, 0x04u},
- {0x9Eu, 0x08u},
- {0xA1u, 0x02u},
- {0xA3u, 0x40u},
- {0xB0u, 0x20u},
- {0xD8u, 0x80u},
- {0xE6u, 0xC0u},
- {0x07u, 0x80u},
- {0x51u, 0x02u},
- {0x57u, 0x40u},
- {0x83u, 0x80u},
- {0xA1u, 0x02u},
- {0xA3u, 0x40u},
- {0xA8u, 0x04u},
+ {0xE2u, 0x04u},
+ {0x86u, 0x01u},
+ {0x93u, 0x02u},
+ {0x96u, 0x01u},
+ {0xA3u, 0x20u},
+ {0xA7u, 0x04u},
+ {0xAFu, 0x80u},
+ {0xE2u, 0x10u},
+ {0xEEu, 0x10u},
+ {0x05u, 0x04u},
+ {0x53u, 0x01u},
+ {0x57u, 0x20u},
+ {0x81u, 0x04u},
+ {0x93u, 0x02u},
+ {0xA3u, 0x20u},
+ {0xB7u, 0x04u},
{0xC0u, 0x20u},
{0xD4u, 0xC0u},
- {0xE0u, 0x80u},
- {0xEAu, 0x20u},
- {0x74u, 0x01u},
- {0x8Bu, 0x02u},
- {0x8Cu, 0x02u},
- {0x94u, 0x10u},
- {0x9Fu, 0x02u},
- {0xA0u, 0x01u},
- {0xB0u, 0x01u},
- {0xB2u, 0x04u},
- {0xDEu, 0x04u},
- {0xE0u, 0x04u},
- {0xE4u, 0x02u},
- {0xE8u, 0x01u},
- {0xEEu, 0x04u},
- {0x00u, 0x10u},
- {0x06u, 0x02u},
- {0x52u, 0x10u},
- {0x54u, 0x02u},
- {0x94u, 0x10u},
- {0x9Au, 0x10u},
- {0x9Eu, 0x02u},
- {0xA0u, 0x02u},
- {0xAAu, 0x02u},
- {0xB2u, 0x10u},
+ {0xE4u, 0x80u},
+ {0x85u, 0x40u},
+ {0x8Cu, 0x04u},
+ {0x90u, 0x08u},
+ {0x94u, 0x20u},
+ {0x99u, 0x20u},
+ {0xA5u, 0x40u},
+ {0xA6u, 0x08u},
+ {0xAFu, 0x01u},
+ {0xE2u, 0x08u},
+ {0x02u, 0x08u},
+ {0x04u, 0x20u},
+ {0x57u, 0x08u},
+ {0x59u, 0x20u},
+ {0x94u, 0x20u},
+ {0x99u, 0x20u},
+ {0xA3u, 0x08u},
+ {0xA6u, 0x08u},
+ {0xB3u, 0x08u},
{0xC0u, 0x03u},
- {0xD4u, 0x04u},
- {0xD6u, 0x04u},
- {0xECu, 0x04u},
+ {0xD4u, 0x03u},
+ {0xE8u, 0x04u},
{0x10u, 0x03u},
+ {0x11u, 0x01u},
{0x1Au, 0x03u},
+ {0x1Bu, 0x01u},
+ {0x1Cu, 0x01u},
{0x00u, 0xFDu},
{0x01u, 0xBFu},
{0x02u, 0x2Au},
/* UDB_1_0_0_CONFIG Address: CYDEV_UCFG_B1_P2_U0_BASE Size (bytes): 128 */
static const uint8 CYCODE BS_UDB_1_0_0_CONFIG_VAL[] = {
- 0x02u, 0x00u, 0x00u, 0x00u, 0x32u, 0x00u, 0x04u, 0x08u, 0x01u, 0x00u, 0x0Eu, 0x07u, 0x36u, 0x00u, 0x00u, 0x80u,
- 0x36u, 0x00u, 0x00u, 0x00u, 0x09u, 0x00u, 0x06u, 0x70u, 0x30u, 0xAAu, 0x06u, 0x55u, 0x04u, 0x44u, 0x00u, 0x88u,
- 0x00u, 0x99u, 0x10u, 0x22u, 0x07u, 0x00u, 0x08u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x06u, 0x00u, 0x30u, 0x00u,
- 0x00u, 0x00u, 0x0Fu, 0xF0u, 0x10u, 0x0Fu, 0x20u, 0x00u, 0x08u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x50u, 0x00u,
- 0x32u, 0x06u, 0x10u, 0x00u, 0x04u, 0xDEu, 0xFCu, 0x0Bu, 0x1Fu, 0xFFu, 0xFFu, 0xFFu, 0x22u, 0x00u, 0xF0u, 0x08u,
- 0x04u, 0x00u, 0x00u, 0x00u, 0x40u, 0x00u, 0x04u, 0x00u, 0x04u, 0x04u, 0x04u, 0x04u, 0x10u, 0x00u, 0x00u, 0x01u,
+ 0x00u, 0x08u, 0x02u, 0x10u, 0x00u, 0x6Cu, 0x05u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x91u, 0x00u, 0x4Eu,
+ 0x00u, 0x71u, 0x18u, 0x82u, 0x10u, 0xC0u, 0x06u, 0x2Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0xA4u, 0x04u, 0x40u,
+ 0x00u, 0x2Cu, 0x00u, 0x40u, 0x00u, 0x40u, 0x00u, 0x2Cu, 0x08u, 0x6Cu, 0x06u, 0x00u, 0x00u, 0x64u, 0x00u, 0x08u,
+ 0x1Eu, 0x0Fu, 0x00u, 0x31u, 0x00u, 0x00u, 0x01u, 0xC0u, 0x00u, 0x00u, 0x00u, 0x8Cu, 0x00u, 0x00u, 0x00u, 0x00u,
+ 0x43u, 0x05u, 0x20u, 0x00u, 0x06u, 0xCBu, 0xFDu, 0xE0u, 0x2Fu, 0xFFu, 0xFFu, 0xFFu, 0x22u, 0x00u, 0xF0u, 0x08u,
+ 0x04u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x04u, 0x04u, 0x04u, 0x04u, 0x00u, 0x00u, 0x00u, 0x01u,
0x00u, 0x00u, 0xC0u, 0x00u, 0x40u, 0x01u, 0x10u, 0x11u, 0xC0u, 0x01u, 0x00u, 0x11u, 0x40u, 0x01u, 0x40u, 0x01u,
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u};
/* UCFG_BCTL0 Address: CYREG_BCTL0_MDCLK_EN Size (bytes): 16 */
static const uint8 CYCODE BS_UCFG_BCTL0_VAL[] = {
- 0x03u, 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x03u, 0x01u, 0x03u, 0x01u, 0x03u, 0x01u, 0x02u, 0x01u};
+ 0x03u, 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x03u, 0x01u, 0x02u, 0x01u, 0x02u, 0x01u, 0x03u, 0x01u};
static const cfg_memcpy_t CYCODE cfg_memcpy_list [] = {
/* dest, src, size */
CY_SET_XTND_REG8((void CYFAR *)CYREG_PM_AVAIL_CR2, CY_GET_XTND_REG8((void CYFAR *)CYREG_PM_AVAIL_CR2) | 0x10u);
}
+
/* Perform second pass device configuration. These items must be configured in specific order after the regular configuration is done. */
CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT0_DR), (const void CYCODE *)(BS_IOPINS0_0_VAL), 10u);
CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT12_DM0), (const void CYCODE *)(BS_IOPINS0_7_VAL), 8u);
CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT4_DM0), (const void CYCODE *)(BS_IOPINS0_4_VAL), 8u);
CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT5_DM0), (const void CYCODE *)(BS_IOPINS0_5_VAL), 8u);
CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT6_DM0), (const void CYCODE *)(BS_IOPINS0_6_VAL), 8u);
-
/* Switch Boost to the precision bandgap reference from its internal reference */
CY_SET_REG8((void CYXDATA *)CYREG_BOOST_CR2, (CY_GET_REG8((void CYXDATA *)CYREG_BOOST_CR2) | 0x08u));
/*******************************************************************************
* FILENAME: cyfitter_cfg.h
-* PSoC Creator 3.1
+*
+* PSoC Creator 3.2
*
-* Description:
+* DESCRIPTION:
+* This file provides basic startup and mux configration settings
* This file is automatically generated by PSoC Creator.
*
********************************************************************************
-* Copyright 2012, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright (c) 2007-2015 Cypress Semiconductor. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
#ifndef CYFITTER_CFG_H
#define CYFITTER_CFG_H
-#include <cytypes.h>
+#include "cytypes.h"
extern void cyfitter_cfg(void);
.set EXTLED__SLW, CYREG_PRT0_SLW
/* SDCard_BSPIM */
-.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB06_07_ACTL
-.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB06_07_CTL
-.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB06_07_CTL
-.set SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB06_07_CTL
-.set SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB06_07_CTL
-.set SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B1_UDB06_07_MSK
-.set SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB06_07_MSK
-.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB06_07_MSK
-.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB06_07_MSK
-.set SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B1_UDB06_ACTL
-.set SDCard_BSPIM_BitCounter__CONTROL_REG, CYREG_B1_UDB06_CTL
-.set SDCard_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B1_UDB06_ST_CTL
-.set SDCard_BSPIM_BitCounter__COUNT_REG, CYREG_B1_UDB06_CTL
-.set SDCard_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B1_UDB06_ST_CTL
-.set SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB06_MSK_ACTL
-.set SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB06_MSK_ACTL
-.set SDCard_BSPIM_BitCounter__PERIOD_REG, CYREG_B1_UDB06_MSK
-.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB06_07_ACTL
-.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B1_UDB06_07_ST
-.set SDCard_BSPIM_BitCounter_ST__MASK_REG, CYREG_B1_UDB06_MSK
-.set SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B1_UDB06_MSK_ACTL
-.set SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B1_UDB06_MSK_ACTL
-.set SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B1_UDB06_ACTL
-.set SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B1_UDB06_ST_CTL
-.set SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B1_UDB06_ST_CTL
-.set SDCard_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B1_UDB06_ST
-.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB04_05_ACTL
-.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB04_05_ST
+.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB12_13_ACTL
+.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB12_13_CTL
+.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB12_13_CTL
+.set SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB12_13_CTL
+.set SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB12_13_CTL
+.set SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B0_UDB12_13_MSK
+.set SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB12_13_MSK
+.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB12_13_MSK
+.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB12_13_MSK
+.set SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B0_UDB12_ACTL
+.set SDCard_BSPIM_BitCounter__CONTROL_REG, CYREG_B0_UDB12_CTL
+.set SDCard_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B0_UDB12_ST_CTL
+.set SDCard_BSPIM_BitCounter__COUNT_REG, CYREG_B0_UDB12_CTL
+.set SDCard_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B0_UDB12_ST_CTL
+.set SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL
+.set SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL
+.set SDCard_BSPIM_BitCounter__PERIOD_REG, CYREG_B0_UDB12_MSK
+.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB12_13_ACTL
+.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B0_UDB12_13_ST
+.set SDCard_BSPIM_BitCounter_ST__MASK_REG, CYREG_B0_UDB12_MSK
+.set SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL
+.set SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL
+.set SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B0_UDB12_ACTL
+.set SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B0_UDB12_ST_CTL
+.set SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B0_UDB12_ST_CTL
+.set SDCard_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B0_UDB12_ST
+.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB07_08_ACTL
+.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB07_08_ST
.set SDCard_BSPIM_RxStsReg__4__MASK, 0x10
.set SDCard_BSPIM_RxStsReg__4__POS, 4
.set SDCard_BSPIM_RxStsReg__5__MASK, 0x20
.set SDCard_BSPIM_RxStsReg__6__MASK, 0x40
.set SDCard_BSPIM_RxStsReg__6__POS, 6
.set SDCard_BSPIM_RxStsReg__MASK, 0x70
-.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B1_UDB04_MSK
-.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB04_ACTL
-.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B1_UDB04_ST
+.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B1_UDB07_MSK
+.set SDCard_BSPIM_RxStsReg__MASK_ST_AUX_CTL_REG, CYREG_B1_UDB07_MSK_ACTL
+.set SDCard_BSPIM_RxStsReg__PER_ST_AUX_CTL_REG, CYREG_B1_UDB07_MSK_ACTL
+.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB07_ACTL
+.set SDCard_BSPIM_RxStsReg__STATUS_CNT_REG, CYREG_B1_UDB07_ST_CTL
+.set SDCard_BSPIM_RxStsReg__STATUS_CONTROL_REG, CYREG_B1_UDB07_ST_CTL
+.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B1_UDB07_ST
.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG, CYREG_B1_UDB04_05_A0
.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG, CYREG_B1_UDB04_05_A1
.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG, CYREG_B1_UDB04_05_D0
.set SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG, CYREG_B1_UDB04_F0_F1
.set SDCard_BSPIM_sR8_Dp_u0__F0_REG, CYREG_B1_UDB04_F0
.set SDCard_BSPIM_sR8_Dp_u0__F1_REG, CYREG_B1_UDB04_F1
+.set SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL
+.set SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL
.set SDCard_BSPIM_TxStsReg__0__MASK, 0x01
.set SDCard_BSPIM_TxStsReg__0__POS, 0
.set SDCard_BSPIM_TxStsReg__1__MASK, 0x02
.set SDCard_BSPIM_TxStsReg__1__POS, 1
-.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB07_08_ACTL
-.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB07_08_ST
.set SDCard_BSPIM_TxStsReg__2__MASK, 0x04
.set SDCard_BSPIM_TxStsReg__2__POS, 2
.set SDCard_BSPIM_TxStsReg__3__MASK, 0x08
.set SDCard_BSPIM_TxStsReg__4__MASK, 0x10
.set SDCard_BSPIM_TxStsReg__4__POS, 4
.set SDCard_BSPIM_TxStsReg__MASK, 0x1F
-.set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B1_UDB07_MSK
-.set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB07_ACTL
-.set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B1_UDB07_ST
+.set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B1_UDB11_MSK
+.set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB11_ACTL
+.set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B1_UDB11_ST
/* SD_SCK */
.set SD_SCK__0__MASK, 0x04
.set SCSI_Out_Bits_Sync_ctrl_reg__0__POS, 0
.set SCSI_Out_Bits_Sync_ctrl_reg__1__MASK, 0x02
.set SCSI_Out_Bits_Sync_ctrl_reg__1__POS, 1
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB11_12_ACTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB11_12_CTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB11_12_CTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB11_12_CTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB11_12_CTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB11_12_MSK
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB11_12_MSK
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB11_12_MSK
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB11_12_MSK
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB07_08_ACTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB07_08_CTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB07_08_CTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB07_08_CTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB07_08_CTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B1_UDB07_08_MSK
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB07_08_MSK
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB07_08_MSK
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB07_08_MSK
.set SCSI_Out_Bits_Sync_ctrl_reg__2__MASK, 0x04
.set SCSI_Out_Bits_Sync_ctrl_reg__2__POS, 2
.set SCSI_Out_Bits_Sync_ctrl_reg__3__MASK, 0x08
.set SCSI_Out_Bits_Sync_ctrl_reg__6__POS, 6
.set SCSI_Out_Bits_Sync_ctrl_reg__7__MASK, 0x80
.set SCSI_Out_Bits_Sync_ctrl_reg__7__POS, 7
-.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB11_ACTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB11_CTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB11_ST_CTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB11_CTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB11_ST_CTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B1_UDB07_ACTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG, CYREG_B1_UDB07_CTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B1_UDB07_ST_CTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG, CYREG_B1_UDB07_CTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B1_UDB07_ST_CTL
.set SCSI_Out_Bits_Sync_ctrl_reg__MASK, 0xFF
-.set SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB11_MSK
+.set SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB07_MSK_ACTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB07_MSK_ACTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG, CYREG_B1_UDB07_MSK
/* SCSI_Out_Ctl */
.set SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK, 0x01
.set SCSI_Out_Ctl_Sync_ctrl_reg__0__POS, 0
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB08_09_ACTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB08_09_CTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB08_09_CTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB08_09_CTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB08_09_CTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB08_09_MSK
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB08_09_MSK
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB08_09_MSK
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB08_09_MSK
-.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB08_ACTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB08_CTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB08_ST_CTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB08_CTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB08_ST_CTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB04_05_ACTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB04_05_CTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB04_05_CTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB04_05_CTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB04_05_CTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B1_UDB04_05_MSK
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB04_05_MSK
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB04_05_MSK
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB04_05_MSK
+.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B1_UDB04_ACTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B1_UDB04_CTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B1_UDB04_ST_CTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B1_UDB04_CTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B1_UDB04_ST_CTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK, 0x01
-.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB08_MSK_ACTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB08_MSK_ACTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB08_MSK
+.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B1_UDB04_MSK
/* SCSI_Out_DBx */
.set SCSI_Out_DBx__0__AG, CYREG_PRT5_AG
.set SCSI_Filtered_sts_sts_reg__0__POS, 0
.set SCSI_Filtered_sts_sts_reg__1__MASK, 0x02
.set SCSI_Filtered_sts_sts_reg__1__POS, 1
-.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB08_09_ACTL
-.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB08_09_ST
+.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB11_12_ACTL
+.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB11_12_ST
.set SCSI_Filtered_sts_sts_reg__2__MASK, 0x04
.set SCSI_Filtered_sts_sts_reg__2__POS, 2
.set SCSI_Filtered_sts_sts_reg__3__MASK, 0x08
.set SCSI_Filtered_sts_sts_reg__4__MASK, 0x10
.set SCSI_Filtered_sts_sts_reg__4__POS, 4
.set SCSI_Filtered_sts_sts_reg__MASK, 0x1F
-.set SCSI_Filtered_sts_sts_reg__MASK_REG, CYREG_B0_UDB08_MSK
-.set SCSI_Filtered_sts_sts_reg__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB08_MSK_ACTL
-.set SCSI_Filtered_sts_sts_reg__PER_ST_AUX_CTL_REG, CYREG_B0_UDB08_MSK_ACTL
-.set SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB08_ACTL
-.set SCSI_Filtered_sts_sts_reg__STATUS_CNT_REG, CYREG_B0_UDB08_ST_CTL
-.set SCSI_Filtered_sts_sts_reg__STATUS_CONTROL_REG, CYREG_B0_UDB08_ST_CTL
-.set SCSI_Filtered_sts_sts_reg__STATUS_REG, CYREG_B0_UDB08_ST
+.set SCSI_Filtered_sts_sts_reg__MASK_REG, CYREG_B0_UDB11_MSK
+.set SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB11_ACTL
+.set SCSI_Filtered_sts_sts_reg__STATUS_REG, CYREG_B0_UDB11_ST
/* SCSI_CTL_PHASE */
.set SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK, 0x01
.set SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS, 0
.set SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK, 0x02
.set SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS, 1
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB02_03_ACTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB02_03_CTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB02_03_CTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB02_03_CTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB02_03_CTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB02_03_MSK
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB02_03_MSK
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB02_03_MSK
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB02_03_MSK
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB05_06_ACTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB05_06_CTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB05_06_CTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB05_06_CTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB05_06_CTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB05_06_MSK
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB05_06_MSK
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB05_06_MSK
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB05_06_MSK
.set SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK, 0x04
.set SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS, 2
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB02_ACTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB02_CTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB02_ST_CTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB02_CTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB02_ST_CTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB05_ACTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB05_CTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB05_ST_CTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB05_CTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB05_ST_CTL
.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK, 0x07
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB02_MSK_ACTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB02_MSK_ACTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB02_MSK
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB05_MSK_ACTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB05_MSK_ACTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB05_MSK
/* SCSI_Glitch_Ctl */
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK, 0x01
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS, 0
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB10_11_ACTL
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB10_11_CTL
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB10_11_CTL
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB10_11_CTL
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB10_11_CTL
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB10_11_MSK
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB10_11_MSK
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB10_11_MSK
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB10_11_MSK
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB10_ACTL
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB10_CTL
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB10_ST_CTL
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB10_CTL
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB10_ST_CTL
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB06_07_ACTL
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB06_07_CTL
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB06_07_CTL
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB06_07_CTL
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB06_07_CTL
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB06_07_MSK
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB06_07_MSK
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB06_07_MSK
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB06_07_MSK
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB06_ACTL
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB06_CTL
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB06_ST_CTL
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB06_CTL
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB06_ST_CTL
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK, 0x01
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB10_MSK_ACTL
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB10_MSK_ACTL
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB10_MSK
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB06_MSK_ACTL
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB06_MSK_ACTL
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB06_MSK
/* SCSI_Parity_Error */
.set SCSI_Parity_Error_sts_sts_reg__0__MASK, 0x01
.set SCSI_Parity_Error_sts_sts_reg__0__POS, 0
-.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB09_10_ACTL
-.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB09_10_ST
+.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB10_11_ACTL
+.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB10_11_ST
.set SCSI_Parity_Error_sts_sts_reg__MASK, 0x01
-.set SCSI_Parity_Error_sts_sts_reg__MASK_REG, CYREG_B0_UDB09_MSK
-.set SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB09_ACTL
-.set SCSI_Parity_Error_sts_sts_reg__STATUS_REG, CYREG_B0_UDB09_ST
+.set SCSI_Parity_Error_sts_sts_reg__MASK_REG, CYREG_B0_UDB10_MSK
+.set SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB10_ACTL
+.set SCSI_Parity_Error_sts_sts_reg__STATUS_REG, CYREG_B0_UDB10_ST
/* Miscellaneous */
.set BCLK__BUS_CLK__HZ, 50000000
.set BCLK__BUS_CLK__KHZ, 50000
.set BCLK__BUS_CLK__MHZ, 50
+.set CYDEV_CHIP_DIE_GEN4, 2
.set CYDEV_CHIP_DIE_LEOPARD, 1
-.set CYDEV_CHIP_DIE_PANTHER, 6
-.set CYDEV_CHIP_DIE_PSOC4A, 3
-.set CYDEV_CHIP_DIE_PSOC5LP, 5
+.set CYDEV_CHIP_DIE_PANTHER, 12
+.set CYDEV_CHIP_DIE_PSOC4A, 5
+.set CYDEV_CHIP_DIE_PSOC5LP, 11
.set CYDEV_CHIP_DIE_UNKNOWN, 0
.set CYDEV_CHIP_FAMILY_PSOC3, 1
.set CYDEV_CHIP_FAMILY_PSOC4, 2
.set CYDEV_CHIP_FAMILY_USED, CYDEV_CHIP_FAMILY_PSOC5
.set CYDEV_CHIP_JTAG_ID, 0x2E133069
.set CYDEV_CHIP_MEMBER_3A, 1
-.set CYDEV_CHIP_MEMBER_4A, 3
-.set CYDEV_CHIP_MEMBER_4D, 2
-.set CYDEV_CHIP_MEMBER_4F, 4
-.set CYDEV_CHIP_MEMBER_5A, 6
-.set CYDEV_CHIP_MEMBER_5B, 5
+.set CYDEV_CHIP_MEMBER_4A, 5
+.set CYDEV_CHIP_MEMBER_4C, 9
+.set CYDEV_CHIP_MEMBER_4D, 3
+.set CYDEV_CHIP_MEMBER_4E, 4
+.set CYDEV_CHIP_MEMBER_4F, 6
+.set CYDEV_CHIP_MEMBER_4G, 2
+.set CYDEV_CHIP_MEMBER_4L, 8
+.set CYDEV_CHIP_MEMBER_4M, 7
+.set CYDEV_CHIP_MEMBER_5A, 11
+.set CYDEV_CHIP_MEMBER_5B, 10
.set CYDEV_CHIP_MEMBER_UNKNOWN, 0
.set CYDEV_CHIP_MEMBER_USED, CYDEV_CHIP_MEMBER_5B
.set CYDEV_CHIP_DIE_EXPECT, CYDEV_CHIP_MEMBER_USED
.set CYDEV_CHIP_DIE_ACTUAL, CYDEV_CHIP_DIE_EXPECT
+.set CYDEV_CHIP_REV_GEN4_ES, 17
+.set CYDEV_CHIP_REV_GEN4_ES2, 33
+.set CYDEV_CHIP_REV_GEN4_PRODUCTION, 17
.set CYDEV_CHIP_REV_LEOPARD_ES1, 0
.set CYDEV_CHIP_REV_LEOPARD_ES2, 1
.set CYDEV_CHIP_REV_LEOPARD_ES3, 3
.set CYDEV_CHIP_REVISION_3A_PRODUCTION, 3
.set CYDEV_CHIP_REVISION_4A_ES0, 17
.set CYDEV_CHIP_REVISION_4A_PRODUCTION, 17
+.set CYDEV_CHIP_REVISION_4C_PRODUCTION, 0
.set CYDEV_CHIP_REVISION_4D_PRODUCTION, 0
+.set CYDEV_CHIP_REVISION_4E_PRODUCTION, 0
.set CYDEV_CHIP_REVISION_4F_PRODUCTION, 0
+.set CYDEV_CHIP_REVISION_4F_PRODUCTION_256K, 0
+.set CYDEV_CHIP_REVISION_4G_ES, 17
+.set CYDEV_CHIP_REVISION_4G_ES2, 33
+.set CYDEV_CHIP_REVISION_4G_PRODUCTION, 17
+.set CYDEV_CHIP_REVISION_4L_PRODUCTION, 0
+.set CYDEV_CHIP_REVISION_4M_PRODUCTION, 0
.set CYDEV_CHIP_REVISION_5A_ES0, 0
.set CYDEV_CHIP_REVISION_5A_ES1, 1
.set CYDEV_CHIP_REVISION_5A_PRODUCTION, 1
.set CYDEV_CONFIGURATION_MODE_UNCOMPRESSED, 1
.set CYDEV_DEBUG_ENABLE_MASK, 0x20
.set CYDEV_DEBUG_ENABLE_REGISTER, CYREG_MLOGIC_DEBUG
-.set CYDEV_DEBUGGING_DPS_Disable, 3
-.set CYDEV_DEBUGGING_DPS_JTAG_4, 1
-.set CYDEV_DEBUGGING_DPS_JTAG_5, 0
.set CYDEV_DEBUGGING_DPS_SWD, 2
.set CYDEV_DEBUGGING_DPS_SWD_SWV, 6
.set CYDEV_DEBUGGING_DPS, CYDEV_DEBUGGING_DPS_SWD_SWV
.set CYDEV_INTR_RISING, 0x0000007E
.set CYDEV_PROJ_TYPE, 2
.set CYDEV_PROJ_TYPE_BOOTLOADER, 1
+.set CYDEV_PROJ_TYPE_LAUNCHER, 5
.set CYDEV_PROJ_TYPE_LOADABLE, 2
+.set CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER, 4
.set CYDEV_PROJ_TYPE_MULTIAPPBOOTLOADER, 3
.set CYDEV_PROJ_TYPE_STANDARD, 0
.set CYDEV_PROTECTION_ENABLE, 0
EXTLED__SLW EQU CYREG_PRT0_SLW
/* SDCard_BSPIM */
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB06_07_CTL
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB06_07_CTL
-SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB06_07_CTL
-SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB06_07_CTL
-SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB06_07_MSK
-SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB06_07_MSK
-SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB06_07_MSK
-SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB06_07_MSK
-SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL
-SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB06_CTL
-SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB06_ST_CTL
-SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB06_CTL
-SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB06_ST_CTL
-SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL
-SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL
-SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB06_MSK
-SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL
-SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB06_07_ST
-SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB06_MSK
-SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL
-SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL
-SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL
-SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB06_ST_CTL
-SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB06_ST_CTL
-SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB06_ST
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB04_05_ST
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB12_13_CTL
+SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL
+SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB12_13_CTL
+SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB12_13_MSK
+SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK
+SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB12_13_MSK
+SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK
+SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL
+SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B0_UDB12_CTL
+SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B0_UDB12_ST_CTL
+SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B0_UDB12_CTL
+SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B0_UDB12_ST_CTL
+SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL
+SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL
+SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B0_UDB12_MSK
+SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL
+SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B0_UDB12_13_ST
+SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B0_UDB12_MSK
+SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL
+SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL
+SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL
+SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B0_UDB12_ST_CTL
+SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B0_UDB12_ST_CTL
+SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B0_UDB12_ST
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST
SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10
SDCard_BSPIM_RxStsReg__4__POS EQU 4
SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20
SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40
SDCard_BSPIM_RxStsReg__6__POS EQU 6
SDCard_BSPIM_RxStsReg__MASK EQU 0x70
-SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB04_MSK
-SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL
-SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB04_ST
+SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB07_MSK
+SDCard_BSPIM_RxStsReg__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL
+SDCard_BSPIM_RxStsReg__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL
+SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL
+SDCard_BSPIM_RxStsReg__STATUS_CNT_REG EQU CYREG_B1_UDB07_ST_CTL
+SDCard_BSPIM_RxStsReg__STATUS_CONTROL_REG EQU CYREG_B1_UDB07_ST_CTL
+SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB07_ST
SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB04_05_A0
SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB04_05_A1
SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B1_UDB04_05_D0
SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B1_UDB04_F0_F1
SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B1_UDB04_F0
SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B1_UDB04_F1
+SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL
+SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL
SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01
SDCard_BSPIM_TxStsReg__0__POS EQU 0
SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02
SDCard_BSPIM_TxStsReg__1__POS EQU 1
-SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL
-SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST
SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04
SDCard_BSPIM_TxStsReg__2__POS EQU 2
SDCard_BSPIM_TxStsReg__3__MASK EQU 0x08
SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10
SDCard_BSPIM_TxStsReg__4__POS EQU 4
SDCard_BSPIM_TxStsReg__MASK EQU 0x1F
-SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB07_MSK
-SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL
-SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB07_ST
+SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB11_MSK
+SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB11_ACTL
+SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB11_ST
/* SD_SCK */
SD_SCK__0__MASK EQU 0x04
SCSI_Out_Bits_Sync_ctrl_reg__0__POS EQU 0
SCSI_Out_Bits_Sync_ctrl_reg__1__MASK EQU 0x02
SCSI_Out_Bits_Sync_ctrl_reg__1__POS EQU 1
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB11_12_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB11_12_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB11_12_MSK
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB11_12_MSK
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB07_08_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB07_08_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB07_08_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB07_08_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB07_08_MSK
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB07_08_MSK
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB07_08_MSK
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB07_08_MSK
SCSI_Out_Bits_Sync_ctrl_reg__2__MASK EQU 0x04
SCSI_Out_Bits_Sync_ctrl_reg__2__POS EQU 2
SCSI_Out_Bits_Sync_ctrl_reg__3__MASK EQU 0x08
SCSI_Out_Bits_Sync_ctrl_reg__6__POS EQU 6
SCSI_Out_Bits_Sync_ctrl_reg__7__MASK EQU 0x80
SCSI_Out_Bits_Sync_ctrl_reg__7__POS EQU 7
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB11_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB11_ST_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB11_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB11_ST_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B1_UDB07_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B1_UDB07_ST_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B1_UDB07_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B1_UDB07_ST_CTL
SCSI_Out_Bits_Sync_ctrl_reg__MASK EQU 0xFF
-SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
-SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
-SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB11_MSK
+SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL
+SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL
+SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B1_UDB07_MSK
/* SCSI_Out_Ctl */
SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01
SCSI_Out_Ctl_Sync_ctrl_reg__0__POS EQU 0
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB08_09_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB08_09_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB08_09_MSK
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB08_09_MSK
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB08_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB08_ST_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB08_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB08_ST_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB04_05_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB04_05_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB04_05_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB04_05_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB04_05_MSK
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB04_05_MSK
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB04_05_MSK
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB04_05_MSK
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B1_UDB04_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B1_UDB04_ST_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B1_UDB04_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B1_UDB04_ST_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__MASK EQU 0x01
-SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL
-SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL
-SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB08_MSK
+SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL
+SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL
+SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B1_UDB04_MSK
/* SCSI_Out_DBx */
SCSI_Out_DBx__0__AG EQU CYREG_PRT5_AG
SCSI_Filtered_sts_sts_reg__0__POS EQU 0
SCSI_Filtered_sts_sts_reg__1__MASK EQU 0x02
SCSI_Filtered_sts_sts_reg__1__POS EQU 1
-SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL
-SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB08_09_ST
+SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL
+SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB11_12_ST
SCSI_Filtered_sts_sts_reg__2__MASK EQU 0x04
SCSI_Filtered_sts_sts_reg__2__POS EQU 2
SCSI_Filtered_sts_sts_reg__3__MASK EQU 0x08
SCSI_Filtered_sts_sts_reg__4__MASK EQU 0x10
SCSI_Filtered_sts_sts_reg__4__POS EQU 4
SCSI_Filtered_sts_sts_reg__MASK EQU 0x1F
-SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB08_MSK
-SCSI_Filtered_sts_sts_reg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL
-SCSI_Filtered_sts_sts_reg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL
-SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL
-SCSI_Filtered_sts_sts_reg__STATUS_CNT_REG EQU CYREG_B0_UDB08_ST_CTL
-SCSI_Filtered_sts_sts_reg__STATUS_CONTROL_REG EQU CYREG_B0_UDB08_ST_CTL
-SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB08_ST
+SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB11_MSK
+SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL
+SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB11_ST
/* SCSI_CTL_PHASE */
SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01
SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS EQU 0
SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK EQU 0x02
SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS EQU 1
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB02_03_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB02_03_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB02_03_MSK
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB02_03_MSK
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB05_06_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB05_06_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB05_06_MSK
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB05_06_MSK
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK
SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK EQU 0x04
SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS EQU 2
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB02_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB02_ST_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB02_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB02_ST_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB05_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB05_ST_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB05_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB05_ST_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__MASK EQU 0x07
-SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB02_MSK
+SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB05_MSK
/* SCSI_Glitch_Ctl */
SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01
SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS EQU 0
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB10_11_ACTL
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB10_11_CTL
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB10_11_CTL
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB10_11_CTL
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB10_11_CTL
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB10_11_MSK
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB10_11_MSK
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB10_11_MSK
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB10_11_MSK
-SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB10_ACTL
-SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB10_CTL
-SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB10_ST_CTL
-SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB10_CTL
-SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB10_ST_CTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB06_07_CTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB06_07_CTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB06_07_CTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB06_07_CTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB06_07_MSK
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB06_07_MSK
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB06_07_MSK
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB06_07_MSK
+SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB06_CTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB06_ST_CTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB06_CTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB06_ST_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK EQU 0x01
-SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL
-SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL
-SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB10_MSK
+SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB06_MSK
/* SCSI_Parity_Error */
SCSI_Parity_Error_sts_sts_reg__0__MASK EQU 0x01
SCSI_Parity_Error_sts_sts_reg__0__POS EQU 0
-SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB09_10_ACTL
-SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB09_10_ST
+SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB10_11_ACTL
+SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB10_11_ST
SCSI_Parity_Error_sts_sts_reg__MASK EQU 0x01
-SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB09_MSK
-SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB09_ACTL
-SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB09_ST
+SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB10_MSK
+SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB10_ACTL
+SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB10_ST
/* Miscellaneous */
BCLK__BUS_CLK__HZ EQU 50000000
BCLK__BUS_CLK__KHZ EQU 50000
BCLK__BUS_CLK__MHZ EQU 50
+CYDEV_CHIP_DIE_GEN4 EQU 2
CYDEV_CHIP_DIE_LEOPARD EQU 1
-CYDEV_CHIP_DIE_PANTHER EQU 6
-CYDEV_CHIP_DIE_PSOC4A EQU 3
-CYDEV_CHIP_DIE_PSOC5LP EQU 5
+CYDEV_CHIP_DIE_PANTHER EQU 12
+CYDEV_CHIP_DIE_PSOC4A EQU 5
+CYDEV_CHIP_DIE_PSOC5LP EQU 11
CYDEV_CHIP_DIE_UNKNOWN EQU 0
CYDEV_CHIP_FAMILY_PSOC3 EQU 1
CYDEV_CHIP_FAMILY_PSOC4 EQU 2
CYDEV_CHIP_FAMILY_USED EQU CYDEV_CHIP_FAMILY_PSOC5
CYDEV_CHIP_JTAG_ID EQU 0x2E133069
CYDEV_CHIP_MEMBER_3A EQU 1
-CYDEV_CHIP_MEMBER_4A EQU 3
-CYDEV_CHIP_MEMBER_4D EQU 2
-CYDEV_CHIP_MEMBER_4F EQU 4
-CYDEV_CHIP_MEMBER_5A EQU 6
-CYDEV_CHIP_MEMBER_5B EQU 5
+CYDEV_CHIP_MEMBER_4A EQU 5
+CYDEV_CHIP_MEMBER_4C EQU 9
+CYDEV_CHIP_MEMBER_4D EQU 3
+CYDEV_CHIP_MEMBER_4E EQU 4
+CYDEV_CHIP_MEMBER_4F EQU 6
+CYDEV_CHIP_MEMBER_4G EQU 2
+CYDEV_CHIP_MEMBER_4L EQU 8
+CYDEV_CHIP_MEMBER_4M EQU 7
+CYDEV_CHIP_MEMBER_5A EQU 11
+CYDEV_CHIP_MEMBER_5B EQU 10
CYDEV_CHIP_MEMBER_UNKNOWN EQU 0
CYDEV_CHIP_MEMBER_USED EQU CYDEV_CHIP_MEMBER_5B
CYDEV_CHIP_DIE_EXPECT EQU CYDEV_CHIP_MEMBER_USED
CYDEV_CHIP_DIE_ACTUAL EQU CYDEV_CHIP_DIE_EXPECT
+CYDEV_CHIP_REV_GEN4_ES EQU 17
+CYDEV_CHIP_REV_GEN4_ES2 EQU 33
+CYDEV_CHIP_REV_GEN4_PRODUCTION EQU 17
CYDEV_CHIP_REV_LEOPARD_ES1 EQU 0
CYDEV_CHIP_REV_LEOPARD_ES2 EQU 1
CYDEV_CHIP_REV_LEOPARD_ES3 EQU 3
CYDEV_CHIP_REVISION_3A_PRODUCTION EQU 3
CYDEV_CHIP_REVISION_4A_ES0 EQU 17
CYDEV_CHIP_REVISION_4A_PRODUCTION EQU 17
+CYDEV_CHIP_REVISION_4C_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4D_PRODUCTION EQU 0
+CYDEV_CHIP_REVISION_4E_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4F_PRODUCTION EQU 0
+CYDEV_CHIP_REVISION_4F_PRODUCTION_256K EQU 0
+CYDEV_CHIP_REVISION_4G_ES EQU 17
+CYDEV_CHIP_REVISION_4G_ES2 EQU 33
+CYDEV_CHIP_REVISION_4G_PRODUCTION EQU 17
+CYDEV_CHIP_REVISION_4L_PRODUCTION EQU 0
+CYDEV_CHIP_REVISION_4M_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_5A_ES0 EQU 0
CYDEV_CHIP_REVISION_5A_ES1 EQU 1
CYDEV_CHIP_REVISION_5A_PRODUCTION EQU 1
CYDEV_CONFIGURATION_MODE_UNCOMPRESSED EQU 1
CYDEV_DEBUG_ENABLE_MASK EQU 0x20
CYDEV_DEBUG_ENABLE_REGISTER EQU CYREG_MLOGIC_DEBUG
-CYDEV_DEBUGGING_DPS_Disable EQU 3
-CYDEV_DEBUGGING_DPS_JTAG_4 EQU 1
-CYDEV_DEBUGGING_DPS_JTAG_5 EQU 0
CYDEV_DEBUGGING_DPS_SWD EQU 2
CYDEV_DEBUGGING_DPS_SWD_SWV EQU 6
CYDEV_DEBUGGING_DPS EQU CYDEV_DEBUGGING_DPS_SWD_SWV
CYDEV_INTR_RISING EQU 0x0000007E
CYDEV_PROJ_TYPE EQU 2
CYDEV_PROJ_TYPE_BOOTLOADER EQU 1
+CYDEV_PROJ_TYPE_LAUNCHER EQU 5
CYDEV_PROJ_TYPE_LOADABLE EQU 2
+CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER EQU 4
CYDEV_PROJ_TYPE_MULTIAPPBOOTLOADER EQU 3
CYDEV_PROJ_TYPE_STANDARD EQU 0
CYDEV_PROTECTION_ENABLE EQU 0
EXTLED__SLW EQU CYREG_PRT0_SLW
; SDCard_BSPIM
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB06_07_CTL
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB06_07_CTL
-SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB06_07_CTL
-SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB06_07_CTL
-SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB06_07_MSK
-SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB06_07_MSK
-SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB06_07_MSK
-SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB06_07_MSK
-SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL
-SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB06_CTL
-SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB06_ST_CTL
-SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB06_CTL
-SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB06_ST_CTL
-SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL
-SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL
-SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB06_MSK
-SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL
-SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB06_07_ST
-SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB06_MSK
-SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL
-SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL
-SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL
-SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB06_ST_CTL
-SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB06_ST_CTL
-SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB06_ST
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB04_05_ST
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB12_13_CTL
+SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL
+SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB12_13_CTL
+SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB12_13_MSK
+SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK
+SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB12_13_MSK
+SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK
+SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL
+SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B0_UDB12_CTL
+SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B0_UDB12_ST_CTL
+SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B0_UDB12_CTL
+SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B0_UDB12_ST_CTL
+SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL
+SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL
+SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B0_UDB12_MSK
+SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL
+SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B0_UDB12_13_ST
+SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B0_UDB12_MSK
+SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL
+SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL
+SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL
+SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B0_UDB12_ST_CTL
+SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B0_UDB12_ST_CTL
+SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B0_UDB12_ST
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST
SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10
SDCard_BSPIM_RxStsReg__4__POS EQU 4
SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20
SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40
SDCard_BSPIM_RxStsReg__6__POS EQU 6
SDCard_BSPIM_RxStsReg__MASK EQU 0x70
-SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB04_MSK
-SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL
-SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB04_ST
+SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB07_MSK
+SDCard_BSPIM_RxStsReg__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL
+SDCard_BSPIM_RxStsReg__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL
+SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL
+SDCard_BSPIM_RxStsReg__STATUS_CNT_REG EQU CYREG_B1_UDB07_ST_CTL
+SDCard_BSPIM_RxStsReg__STATUS_CONTROL_REG EQU CYREG_B1_UDB07_ST_CTL
+SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB07_ST
SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB04_05_A0
SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB04_05_A1
SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B1_UDB04_05_D0
SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B1_UDB04_F0_F1
SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B1_UDB04_F0
SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B1_UDB04_F1
+SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL
+SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL
SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01
SDCard_BSPIM_TxStsReg__0__POS EQU 0
SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02
SDCard_BSPIM_TxStsReg__1__POS EQU 1
-SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL
-SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST
SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04
SDCard_BSPIM_TxStsReg__2__POS EQU 2
SDCard_BSPIM_TxStsReg__3__MASK EQU 0x08
SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10
SDCard_BSPIM_TxStsReg__4__POS EQU 4
SDCard_BSPIM_TxStsReg__MASK EQU 0x1F
-SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB07_MSK
-SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL
-SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB07_ST
+SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB11_MSK
+SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB11_ACTL
+SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB11_ST
; SD_SCK
SD_SCK__0__MASK EQU 0x04
SCSI_Out_Bits_Sync_ctrl_reg__0__POS EQU 0
SCSI_Out_Bits_Sync_ctrl_reg__1__MASK EQU 0x02
SCSI_Out_Bits_Sync_ctrl_reg__1__POS EQU 1
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB11_12_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB11_12_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB11_12_MSK
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB11_12_MSK
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB07_08_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB07_08_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB07_08_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB07_08_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB07_08_MSK
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB07_08_MSK
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB07_08_MSK
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB07_08_MSK
SCSI_Out_Bits_Sync_ctrl_reg__2__MASK EQU 0x04
SCSI_Out_Bits_Sync_ctrl_reg__2__POS EQU 2
SCSI_Out_Bits_Sync_ctrl_reg__3__MASK EQU 0x08
SCSI_Out_Bits_Sync_ctrl_reg__6__POS EQU 6
SCSI_Out_Bits_Sync_ctrl_reg__7__MASK EQU 0x80
SCSI_Out_Bits_Sync_ctrl_reg__7__POS EQU 7
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB11_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB11_ST_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB11_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB11_ST_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B1_UDB07_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B1_UDB07_ST_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B1_UDB07_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B1_UDB07_ST_CTL
SCSI_Out_Bits_Sync_ctrl_reg__MASK EQU 0xFF
-SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
-SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
-SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB11_MSK
+SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL
+SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL
+SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B1_UDB07_MSK
; SCSI_Out_Ctl
SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01
SCSI_Out_Ctl_Sync_ctrl_reg__0__POS EQU 0
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB08_09_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB08_09_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB08_09_MSK
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB08_09_MSK
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB08_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB08_ST_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB08_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB08_ST_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB04_05_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB04_05_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB04_05_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB04_05_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB04_05_MSK
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB04_05_MSK
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB04_05_MSK
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB04_05_MSK
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B1_UDB04_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B1_UDB04_ST_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B1_UDB04_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B1_UDB04_ST_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__MASK EQU 0x01
-SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL
-SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL
-SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB08_MSK
+SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL
+SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL
+SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B1_UDB04_MSK
; SCSI_Out_DBx
SCSI_Out_DBx__0__AG EQU CYREG_PRT5_AG
SCSI_Filtered_sts_sts_reg__0__POS EQU 0
SCSI_Filtered_sts_sts_reg__1__MASK EQU 0x02
SCSI_Filtered_sts_sts_reg__1__POS EQU 1
-SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL
-SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB08_09_ST
+SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL
+SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB11_12_ST
SCSI_Filtered_sts_sts_reg__2__MASK EQU 0x04
SCSI_Filtered_sts_sts_reg__2__POS EQU 2
SCSI_Filtered_sts_sts_reg__3__MASK EQU 0x08
SCSI_Filtered_sts_sts_reg__4__MASK EQU 0x10
SCSI_Filtered_sts_sts_reg__4__POS EQU 4
SCSI_Filtered_sts_sts_reg__MASK EQU 0x1F
-SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB08_MSK
-SCSI_Filtered_sts_sts_reg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL
-SCSI_Filtered_sts_sts_reg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL
-SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL
-SCSI_Filtered_sts_sts_reg__STATUS_CNT_REG EQU CYREG_B0_UDB08_ST_CTL
-SCSI_Filtered_sts_sts_reg__STATUS_CONTROL_REG EQU CYREG_B0_UDB08_ST_CTL
-SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB08_ST
+SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB11_MSK
+SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL
+SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB11_ST
; SCSI_CTL_PHASE
SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01
SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS EQU 0
SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK EQU 0x02
SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS EQU 1
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB02_03_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB02_03_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB02_03_MSK
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB02_03_MSK
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB05_06_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB05_06_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB05_06_MSK
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB05_06_MSK
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK
SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK EQU 0x04
SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS EQU 2
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB02_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB02_ST_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB02_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB02_ST_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB05_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB05_ST_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB05_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB05_ST_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__MASK EQU 0x07
-SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB02_MSK
+SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB05_MSK
; SCSI_Glitch_Ctl
SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01
SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS EQU 0
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB10_11_ACTL
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB10_11_CTL
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB10_11_CTL
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB10_11_CTL
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB10_11_CTL
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB10_11_MSK
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB10_11_MSK
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB10_11_MSK
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB10_11_MSK
-SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB10_ACTL
-SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB10_CTL
-SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB10_ST_CTL
-SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB10_CTL
-SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB10_ST_CTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB06_07_CTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB06_07_CTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB06_07_CTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB06_07_CTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB06_07_MSK
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB06_07_MSK
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB06_07_MSK
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB06_07_MSK
+SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB06_CTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB06_ST_CTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB06_CTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB06_ST_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK EQU 0x01
-SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL
-SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL
-SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB10_MSK
+SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB06_MSK
; SCSI_Parity_Error
SCSI_Parity_Error_sts_sts_reg__0__MASK EQU 0x01
SCSI_Parity_Error_sts_sts_reg__0__POS EQU 0
-SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB09_10_ACTL
-SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB09_10_ST
+SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB10_11_ACTL
+SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB10_11_ST
SCSI_Parity_Error_sts_sts_reg__MASK EQU 0x01
-SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB09_MSK
-SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB09_ACTL
-SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB09_ST
+SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB10_MSK
+SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB10_ACTL
+SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB10_ST
; Miscellaneous
BCLK__BUS_CLK__HZ EQU 50000000
BCLK__BUS_CLK__KHZ EQU 50000
BCLK__BUS_CLK__MHZ EQU 50
+CYDEV_CHIP_DIE_GEN4 EQU 2
CYDEV_CHIP_DIE_LEOPARD EQU 1
-CYDEV_CHIP_DIE_PANTHER EQU 6
-CYDEV_CHIP_DIE_PSOC4A EQU 3
-CYDEV_CHIP_DIE_PSOC5LP EQU 5
+CYDEV_CHIP_DIE_PANTHER EQU 12
+CYDEV_CHIP_DIE_PSOC4A EQU 5
+CYDEV_CHIP_DIE_PSOC5LP EQU 11
CYDEV_CHIP_DIE_UNKNOWN EQU 0
CYDEV_CHIP_FAMILY_PSOC3 EQU 1
CYDEV_CHIP_FAMILY_PSOC4 EQU 2
CYDEV_CHIP_FAMILY_USED EQU CYDEV_CHIP_FAMILY_PSOC5
CYDEV_CHIP_JTAG_ID EQU 0x2E133069
CYDEV_CHIP_MEMBER_3A EQU 1
-CYDEV_CHIP_MEMBER_4A EQU 3
-CYDEV_CHIP_MEMBER_4D EQU 2
-CYDEV_CHIP_MEMBER_4F EQU 4
-CYDEV_CHIP_MEMBER_5A EQU 6
-CYDEV_CHIP_MEMBER_5B EQU 5
+CYDEV_CHIP_MEMBER_4A EQU 5
+CYDEV_CHIP_MEMBER_4C EQU 9
+CYDEV_CHIP_MEMBER_4D EQU 3
+CYDEV_CHIP_MEMBER_4E EQU 4
+CYDEV_CHIP_MEMBER_4F EQU 6
+CYDEV_CHIP_MEMBER_4G EQU 2
+CYDEV_CHIP_MEMBER_4L EQU 8
+CYDEV_CHIP_MEMBER_4M EQU 7
+CYDEV_CHIP_MEMBER_5A EQU 11
+CYDEV_CHIP_MEMBER_5B EQU 10
CYDEV_CHIP_MEMBER_UNKNOWN EQU 0
CYDEV_CHIP_MEMBER_USED EQU CYDEV_CHIP_MEMBER_5B
CYDEV_CHIP_DIE_EXPECT EQU CYDEV_CHIP_MEMBER_USED
CYDEV_CHIP_DIE_ACTUAL EQU CYDEV_CHIP_DIE_EXPECT
+CYDEV_CHIP_REV_GEN4_ES EQU 17
+CYDEV_CHIP_REV_GEN4_ES2 EQU 33
+CYDEV_CHIP_REV_GEN4_PRODUCTION EQU 17
CYDEV_CHIP_REV_LEOPARD_ES1 EQU 0
CYDEV_CHIP_REV_LEOPARD_ES2 EQU 1
CYDEV_CHIP_REV_LEOPARD_ES3 EQU 3
CYDEV_CHIP_REVISION_3A_PRODUCTION EQU 3
CYDEV_CHIP_REVISION_4A_ES0 EQU 17
CYDEV_CHIP_REVISION_4A_PRODUCTION EQU 17
+CYDEV_CHIP_REVISION_4C_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4D_PRODUCTION EQU 0
+CYDEV_CHIP_REVISION_4E_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4F_PRODUCTION EQU 0
+CYDEV_CHIP_REVISION_4F_PRODUCTION_256K EQU 0
+CYDEV_CHIP_REVISION_4G_ES EQU 17
+CYDEV_CHIP_REVISION_4G_ES2 EQU 33
+CYDEV_CHIP_REVISION_4G_PRODUCTION EQU 17
+CYDEV_CHIP_REVISION_4L_PRODUCTION EQU 0
+CYDEV_CHIP_REVISION_4M_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_5A_ES0 EQU 0
CYDEV_CHIP_REVISION_5A_ES1 EQU 1
CYDEV_CHIP_REVISION_5A_PRODUCTION EQU 1
CYDEV_CONFIGURATION_MODE_UNCOMPRESSED EQU 1
CYDEV_DEBUG_ENABLE_MASK EQU 0x20
CYDEV_DEBUG_ENABLE_REGISTER EQU CYREG_MLOGIC_DEBUG
-CYDEV_DEBUGGING_DPS_Disable EQU 3
-CYDEV_DEBUGGING_DPS_JTAG_4 EQU 1
-CYDEV_DEBUGGING_DPS_JTAG_5 EQU 0
CYDEV_DEBUGGING_DPS_SWD EQU 2
CYDEV_DEBUGGING_DPS_SWD_SWV EQU 6
CYDEV_DEBUGGING_DPS EQU CYDEV_DEBUGGING_DPS_SWD_SWV
CYDEV_INTR_RISING EQU 0x0000007E
CYDEV_PROJ_TYPE EQU 2
CYDEV_PROJ_TYPE_BOOTLOADER EQU 1
+CYDEV_PROJ_TYPE_LAUNCHER EQU 5
CYDEV_PROJ_TYPE_LOADABLE EQU 2
+CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER EQU 4
CYDEV_PROJ_TYPE_MULTIAPPBOOTLOADER EQU 3
CYDEV_PROJ_TYPE_STANDARD EQU 0
CYDEV_PROTECTION_ENABLE EQU 0
/*******************************************************************************
* FILENAME: cymetadata.c
*
-* PSoC Creator 3.1
+* PSoC Creator 3.2
*
* DESCRIPTION:
* This file defines all extra memory spaces that need to be included.
* This file is automatically generated by PSoC Creator.
*
********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright (c) 2007-2015 Cypress Semiconductor. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
const uint8 cy_meta_loadable[] = {
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
- 0x00u, 0x00u, 0x00u, 0x00u, 0x5Cu, 0xD1u, 0x30u, 0x04u,
+ 0x00u, 0x00u, 0x00u, 0x00u, 0x5Cu, 0xD1u, 0x40u, 0x04u,
0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
/*******************************************************************************
- * File Name: project.h
- * PSoC Creator 3.1
- *
- * Description:
- * This file is automatically generated by PSoC Creator and should not
- * be edited by hand.
- *
- *
- ********************************************************************************
- * Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.
- * You may use this file only in accordance with the license, terms, conditions,
- * disclaimers, and limitations in the end user license agreement accompanying
- * the software package with which this file was provided.
- ********************************************************************************/
+* FILENAME: project.h
+*
+* PSoC Creator 3.2
+*
+* DESCRIPTION:
+* It contains references to all generated header files and should not be modified.
+* This file is automatically generated by PSoC Creator.
+*
+********************************************************************************
+* Copyright (c) 2007-2015 Cypress Semiconductor. All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions,
+* disclaimers, and limitations in the end user license agreement accompanying
+* the software package with which this file was provided.
+********************************************************************************/
-#include <cyfitter_cfg.h>
-#include <cydevice.h>
-#include <cydevice_trm.h>
-#include <cyfitter.h>
-#include <cydisabledsheets.h>
-#include <SCSI_In_DBx_aliases.h>
-#include <SCSI_Out_DBx_aliases.h>
-#include <SD_Data_Clk.h>
-#include <SD_CD_aliases.h>
-#include <SD_CD.h>
-#include <SCSI_CTL_PHASE.h>
-#include <SCSI_In_aliases.h>
-#include <SCSI_Out_aliases.h>
-#include <CFG_EEPROM.h>
-#include <SD_CS_aliases.h>
-#include <SD_CS.h>
-#include <SD_SCK_aliases.h>
-#include <SD_SCK.h>
-#include <SD_MOSI_aliases.h>
-#include <SD_MOSI.h>
-#include <SCSI_CLK.h>
-#include <SCSI_Noise_aliases.h>
-#include <SCSI_RST_ISR.h>
-#include <LED1_aliases.h>
-#include <LED1.h>
-#include <SDCard.h>
-#include <SDCard_PVT.h>
-#include <SD_MISO_aliases.h>
-#include <SD_MISO.h>
-#include <USBFS.h>
-#include <USBFS_audio.h>
-#include <USBFS_cdc.h>
-#include <USBFS_hid.h>
-#include <USBFS_midi.h>
-#include <USBFS_pvt.h>
-#include <Bootloadable_1.h>
-#include <SCSI_Out_Bits.h>
-#include <SCSI_Out_Ctl.h>
-#include <Debug_Timer.h>
-#include <timer_clock.h>
-#include <Debug_Timer_Interrupt.h>
-#include <SCSI_TX_DMA_dma.h>
-#include <SCSI_TX_DMA_COMPLETE.h>
-#include <SD_RX_DMA_dma.h>
-#include <SD_TX_DMA_dma.h>
-#include <SD_RX_DMA_COMPLETE.h>
-#include <SD_TX_DMA_COMPLETE.h>
-#include <SCSI_RX_DMA_dma.h>
-#include <SCSI_RX_DMA_COMPLETE.h>
-#include <SCSI_Parity_Error.h>
-#include <SCSI_Filtered.h>
-#include <EXTLED_aliases.h>
-#include <EXTLED.h>
-#include <SCSI_SEL_ISR.h>
-#include <SCSI_Glitch_Ctl.h>
-#include <USBFS_Dm_aliases.h>
-#include <USBFS_Dm.h>
-#include <USBFS_Dp_aliases.h>
-#include <USBFS_Dp.h>
-#include <core_cm3_psoc5.h>
-#include <core_cm3.h>
-#include <CyDmac.h>
-#include <CyFlash.h>
-#include <CyLib.h>
-#include <cypins.h>
-#include <cyPm.h>
-#include <CySpc.h>
-#include <cytypes.h>
-#include <core_cmFunc.h>
-#include <core_cmInstr.h>
+#include "cyfitter_cfg.h"
+#include "cydevice.h"
+#include "cydevice_trm.h"
+#include "cyfitter.h"
+#include "cydisabledsheets.h"
+#include "SCSI_In_DBx_aliases.h"
+#include "SCSI_Out_DBx_aliases.h"
+#include "SD_Data_Clk.h"
+#include "SD_CD_aliases.h"
+#include "SD_CD.h"
+#include "SCSI_CTL_PHASE.h"
+#include "SCSI_In_aliases.h"
+#include "SCSI_Out_aliases.h"
+#include "CFG_EEPROM.h"
+#include "SD_CS_aliases.h"
+#include "SD_CS.h"
+#include "SD_SCK_aliases.h"
+#include "SD_SCK.h"
+#include "SD_MOSI_aliases.h"
+#include "SD_MOSI.h"
+#include "SCSI_CLK.h"
+#include "SCSI_Noise_aliases.h"
+#include "SCSI_RST_ISR.h"
+#include "LED1_aliases.h"
+#include "LED1.h"
+#include "SDCard.h"
+#include "SDCard_PVT.h"
+#include "SD_MISO_aliases.h"
+#include "SD_MISO.h"
+#include "USBFS.h"
+#include "USBFS_audio.h"
+#include "USBFS_cdc.h"
+#include "USBFS_hid.h"
+#include "USBFS_midi.h"
+#include "USBFS_pvt.h"
+#include "Bootloadable_1.h"
+#include "SCSI_Out_Bits.h"
+#include "SCSI_Out_Ctl.h"
+#include "Debug_Timer.h"
+#include "timer_clock.h"
+#include "Debug_Timer_Interrupt.h"
+#include "SCSI_TX_DMA_dma.h"
+#include "SCSI_TX_DMA_COMPLETE.h"
+#include "SD_RX_DMA_dma.h"
+#include "SD_TX_DMA_dma.h"
+#include "SD_RX_DMA_COMPLETE.h"
+#include "SD_TX_DMA_COMPLETE.h"
+#include "SCSI_RX_DMA_dma.h"
+#include "SCSI_RX_DMA_COMPLETE.h"
+#include "SCSI_Parity_Error.h"
+#include "SCSI_Filtered.h"
+#include "EXTLED_aliases.h"
+#include "EXTLED.h"
+#include "SCSI_SEL_ISR.h"
+#include "SCSI_Glitch_Ctl.h"
+#include "USBFS_Dm_aliases.h"
+#include "USBFS_Dm.h"
+#include "USBFS_Dp_aliases.h"
+#include "USBFS_Dp.h"
+#include "core_cm3_psoc5.h"
+#include "core_cm3.h"
+#include "CyDmac.h"
+#include "CyFlash.h"
+#include "CyLib.h"
+#include "cypins.h"
+#include "cyPm.h"
+#include "CySpc.h"
+#include "cytypes.h"
+#include "core_cmFunc.h"
+#include "core_cmInstr.h"
/*[]*/
<?xml version="1.0" encoding="utf-8"?>
<blockRegMap version="1" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://cypress.com/xsd/cyblockregmap cyblockregmap.xsd" xmlns="http://cypress.com/xsd/cyblockregmap">
+ <block name="SCSI_RX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="SCSI_RX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="SD_TX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" />
- <block name="SD_RX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+ <block name="GlitchFilter_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="SCSI_Filtered" BASE="0x0" SIZE="0x0" desc="" visible="true">
- <register name="SCSI_Filtered_STATUS_REG" address="0x40006468" bitWidth="8" desc="" />
- <register name="SCSI_Filtered_MASK_REG" address="0x40006488" bitWidth="8" desc="" />
- <register name="SCSI_Filtered_STATUS_AUX_CTL_REG" address="0x40006498" bitWidth="8" desc="">
+ <register name="SCSI_Filtered_STATUS_REG" address="0x4000646B" bitWidth="8" desc="" />
+ <register name="SCSI_Filtered_MASK_REG" address="0x4000648B" bitWidth="8" desc="" />
+ <register name="SCSI_Filtered_STATUS_AUX_CTL_REG" address="0x4000649B" bitWidth="8" desc="">
<field name="FIFO0" from="5" to="5" access="RW" resetVal="" desc="FIFO0 clear">
<value name="ENABLED" value="1" desc="Enable counter" />
<value name="DISABLED" value="0" desc="Disable counter" />
</register>
</block>
<block name="SCSI_Parity_Error" BASE="0x0" SIZE="0x0" desc="" visible="true">
- <register name="SCSI_Parity_Error_STATUS_REG" address="0x40006469" bitWidth="8" desc="" />
- <register name="SCSI_Parity_Error_MASK_REG" address="0x40006489" bitWidth="8" desc="" />
- <register name="SCSI_Parity_Error_STATUS_AUX_CTL_REG" address="0x40006499" bitWidth="8" desc="">
+ <register name="SCSI_Parity_Error_STATUS_REG" address="0x4000646A" bitWidth="8" desc="" />
+ <register name="SCSI_Parity_Error_MASK_REG" address="0x4000648A" bitWidth="8" desc="" />
+ <register name="SCSI_Parity_Error_STATUS_AUX_CTL_REG" address="0x4000649A" bitWidth="8" desc="">
<field name="FIFO0" from="5" to="5" access="RW" resetVal="" desc="FIFO0 clear">
<value name="ENABLED" value="1" desc="Enable counter" />
<value name="DISABLED" value="0" desc="Disable counter" />
</field>
</register>
</block>
- <block name="SCSI_RX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" />
- <block name="SD_TX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+ <block name="SD_RX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+ <block name="SCSI_TX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="Debug_Timer_Interrupt" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
- <block name="timer_clock" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+ <block name="SD_TX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="SD_RX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="SCSI_TX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" />
- <block name="SCSI_TX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+ <block name="SCSI_SEL_ISR" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="cydff_2" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="Clock_4" BASE="0x0" SIZE="0x0" desc="" visible="true" />
- <block name="not_2" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+ <block name="cy_boot" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="SCSI_Glitch_Ctl" BASE="0x0" SIZE="0x0" desc="" visible="true">
- <register name="SCSI_Glitch_Ctl_CONTROL_REG" address="0x4000647A" bitWidth="8" desc="" />
+ <register name="SCSI_Glitch_Ctl_CONTROL_REG" address="0x40006476" bitWidth="8" desc="" />
</block>
<block name="mux_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
- <block name="SCSI_SEL_ISR" BASE="0x0" SIZE="0x0" desc="" visible="true" />
- <block name="EXTLED" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+ <block name="not_2" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+ <block name="cy_constant_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="Clock_2" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="Clock_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
- <block name="GlitchFilter_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+ <block name="EXTLED" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="Clock_3" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="cydff_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
- <block name="cy_constant_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+ <block name="timer_clock" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="SD_CS" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="CFG_EEPROM" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="SCSI_Out" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="SCSI_In_DBx" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="OddParityGen_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="SCSI_CTL_PHASE" BASE="0x0" SIZE="0x0" desc="" visible="true">
- <register name="SCSI_CTL_PHASE_CONTROL_REG" address="0x40006472" bitWidth="8" desc="" />
+ <register name="SCSI_CTL_PHASE_CONTROL_REG" address="0x40006475" bitWidth="8" desc="" />
</block>
<block name="SD_CD" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="SCSI_Out_Mux" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<register name="Debug_Timer_COUNTER" address="0x40004F06" bitWidth="16" desc="TMRx.CNT_CMP0 - Current Down Counter Value" />
</block>
<block name="SCSI_Out_Ctl" BASE="0x0" SIZE="0x0" desc="" visible="true">
- <register name="SCSI_Out_Ctl_CONTROL_REG" address="0x40006478" bitWidth="8" desc="" />
+ <register name="SCSI_Out_Ctl_CONTROL_REG" address="0x40006574" bitWidth="8" desc="" />
</block>
<block name="SCSI_Out_Bits" BASE="0x0" SIZE="0x0" desc="" visible="true">
- <register name="SCSI_Out_Bits_CONTROL_REG" address="0x4000647B" bitWidth="8" desc="" />
+ <register name="SCSI_Out_Bits_CONTROL_REG" address="0x40006577" bitWidth="8" desc="" />
</block>
<block name="SD_MISO" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="SCSI_RST_ISR" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<PropertyDeltas />
</CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b>
</CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d>
+<CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFileGenerated" version="1">
+<CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFile" version="3" xml_contents_version="1">
+<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="SCSI_CTL_PHASE_PM.c" persistent=".\Generated_Source\PSoC5\SCSI_CTL_PHASE_PM.c">
+<Hidden v="False" />
+</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>
+<build_action v="ARM_C_FILE" />
+<PropertyDeltas />
+</CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b>
+</CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d>
</dependencies>
</CyGuid_0820c2e7-528d-4137-9a08-97257b946089>
</CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8>
<PropertyDeltas />
</CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b>
</CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d>
+<CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFileGenerated" version="1">
+<CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFile" version="3" xml_contents_version="1">
+<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="SCSI_Out_Bits_PM.c" persistent=".\Generated_Source\PSoC5\SCSI_Out_Bits_PM.c">
+<Hidden v="False" />
+</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>
+<build_action v="ARM_C_FILE" />
+<PropertyDeltas />
+</CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b>
+</CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d>
</dependencies>
</CyGuid_0820c2e7-528d-4137-9a08-97257b946089>
</CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8>
<PropertyDeltas />
</CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b>
</CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d>
+<CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFileGenerated" version="1">
+<CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFile" version="3" xml_contents_version="1">
+<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="SCSI_Out_Ctl_PM.c" persistent=".\Generated_Source\PSoC5\SCSI_Out_Ctl_PM.c">
+<Hidden v="False" />
+</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>
+<build_action v="ARM_C_FILE" />
+<PropertyDeltas />
+</CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b>
+</CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d>
</dependencies>
</CyGuid_0820c2e7-528d-4137-9a08-97257b946089>
</CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8>
<PropertyDeltas />
</CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b>
</CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d>
+<CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFileGenerated" version="1">
+<CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFile" version="3" xml_contents_version="1">
+<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="SCSI_Glitch_Ctl_PM.c" persistent=".\Generated_Source\PSoC5\SCSI_Glitch_Ctl_PM.c">
+<Hidden v="False" />
+</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>
+<build_action v="ARM_C_FILE" />
+<PropertyDeltas />
+</CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b>
+</CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d>
</dependencies>
</CyGuid_0820c2e7-528d-4137-9a08-97257b946089>
</CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8>
<GlobalPages />
<GlobalTools name="Code Generation">
<GlobalPages>
-<name_val_pair name="General@Application Type" v="Bootloadable" />
<name_val_pair name="General@Custom Code Gen Options" v="" />
<name_val_pair name="General@Skip Code Generation" v="False" />
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<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@General@Output Directory" v="${ProjectDir}\${ProcessorType}\${Platform}\${Config}" />
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<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@Linker@General@Custom Linker Script" v="" />
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<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM0@C/C++@Command Line@Command Line" v="" />
<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM0@Library Generation@Command Line@Command Line" v="" />
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<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM0@C/C++@Command Line@Command Line" v="" />
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<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM0@Linker@Optimization@Remove Unused Functions" v="True" />
<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM0@Linker@Command Line@Command Line" v="" />
<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM3@General@Output Directory" v="${ProjectDir}\${ProcessorType}\${Platform}\${Config}" />
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<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM3@C/C++@Command Line@Command Line" v="" />
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<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM3@Linker@General@Additional Libraries" v="" />
<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM3@Linker@General@Additional Link Files" v="" />
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<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM3@Linker@General@Custom Linker Script" v="" />
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<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM3@Linker@General@Use Default Libs" v="True" />
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<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM3@Linker@Optimization@Remove Unused Functions" v="True" />
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<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM3@General@Output Directory" v="${ProjectDir}\${ProcessorType}\${Platform}\${Config}" />
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<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM3@C/C++@Command Line@Command Line" v="" />
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<project_id v="6e1f5cbb-a0ca-4f55-a1fa-7b20c5be3a3e" /><custom_data><CyGuid_7a7929f8-5e3b-4f86-a093-2d4ee6513111 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtProjectCustomData" version="1"><CyGuid_fdba8dfd-b15b-4469-9bbb-9e40c3e70997 type_name="CyDesigner.Common.Base.CyCustomData" version="2"><userData /></CyGuid_fdba8dfd-b15b-4469-9bbb-9e40c3e70997><properties /></CyGuid_7a7929f8-5e3b-4f86-a093-2d4ee6513111></custom_data></CyGuid_49cfd574-032a-4a64-b7be-d4eeeaf25e43>
</CyGuid_60697ce6-dce2-4816-8680-4de0635742eb>
<top_block v="TopDesign" />
<ignored_deps />
</CyGuid_495451fe-d201-4d01-b22d-5d3f5609ac37>
<boot_component v="cy_boot_v4_20" />
-<BootloaderTag hexFile="" elfFile="" />
-<current_generation v="2" />
-</CyGuid_fec8f9e8-2365-4bdb-96d3-a4380222e01b>
+<current_generation v="2" /><BootloaderTag hexFile="" elfFile="" /></CyGuid_fec8f9e8-2365-4bdb-96d3-a4380222e01b>
</CyXmlSerializer>
\ No newline at end of file
<peripheral>
<name>SCSI_Filtered</name>
<description>No description available</description>
- <baseAddress>0x40006468</baseAddress>
+ <baseAddress>0x4000646B</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x0</size>
<peripheral>
<name>SCSI_Parity_Error</name>
<description>No description available</description>
- <baseAddress>0x40006469</baseAddress>
+ <baseAddress>0x4000646A</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x0</size>
<peripheral>
<name>SCSI_Glitch_Ctl</name>
<description>No description available</description>
- <baseAddress>0x4000647A</baseAddress>
+ <baseAddress>0x40006476</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x0</size>
<peripheral>
<name>SCSI_CTL_PHASE</name>
<description>No description available</description>
- <baseAddress>0x40006472</baseAddress>
+ <baseAddress>0x40006475</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x0</size>
<peripheral>
<name>SCSI_Out_Ctl</name>
<description>No description available</description>
- <baseAddress>0x40006478</baseAddress>
+ <baseAddress>0x40006574</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x0</size>
<peripheral>
<name>SCSI_Out_Bits</name>
<description>No description available</description>
- <baseAddress>0x4000647B</baseAddress>
+ <baseAddress>0x40006577</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x0</size>
{
CONFIG_ENABLE_UNIT_ATTENTION = 1,
CONFIG_ENABLE_PARITY = 2,
- CONFIG_ENABLE_SCSI2 = 4
+ CONFIG_ENABLE_SCSI2 = 4,
+ CONFIG_DISABLE_GLITCH = 8
} CONFIG_FLAGS;
typedef enum
(config.flags & CONFIG_ENABLE_PARITY ? "true" : "false") <<
"</parity>\n" <<
- " <!-- Only set to true when using with a fast SCSI2 host\n " <<
+ " <!-- ********************************************************\n" <<
+ " Only set to true when using with a fast SCSI2 host\n " <<
" controller. This can cause problems with older/slower\n" <<
- " hardware.-->\n" <<
+ " hardware.\n" <<
+ " ********************************************************* -->\n" <<
" <enableScsi2>" <<
(config.flags & CONFIG_ENABLE_SCSI2 ? "true" : "false") <<
"</enableScsi2>\n" <<
+ " <!-- ********************************************************\n" <<
+ " Setting to 'true' will result in increased performance at the\n" <<
+ " cost of lower noise immunity.\n" <<
+ " Only set to true when using short cables with only 1 or two\n" <<
+ " devices. This should remain off when using external SCSI1 DB25\n" <<
+ " cables.\n" <<
+ " ********************************************************* -->\n" <<
+ " <disableGlitchFilter>" <<
+ (config.flags & CONFIG_DISABLE_GLITCH ? "true" : "false") <<
+ "</disableGlitchFilter>\n" <<
+
"\n" <<
" <!-- ********************************************************\n" <<
" Space separated list. Available options:\n" <<
result.flags = result.flags & ~CONFIG_ENABLE_SCSI2;
}
}
+ else if (child->GetName() == "disableGlitchFilter")
+ {
+ std::string s(child->GetNodeContent().mb_str());
+ if (s == "true")
+ {
+ result.flags |= CONFIG_DISABLE_GLITCH;
+ }
+ else
+ {
+ result.flags = result.flags & ~CONFIG_DISABLE_GLITCH;
+ }
+ }
else if (child->GetName() == "quirks")
{
std::stringstream s(std::string(child->GetNodeContent().mb_str()));
myNumSectorValidator(new wxIntegerValidator<uint32_t>),
mySizeValidator(new wxFloatingPointValidator<float>(2))
{
- wxFlexGridSizer *fgs = new wxFlexGridSizer(14, 3, 9, 25);
+ wxFlexGridSizer *fgs = new wxFlexGridSizer(13, 3, 9, 25);
fgs->Add(new wxStaticText(this, wxID_ANY, wxT("")));
myEnableCtrl =
wxT("Enable Parity"));
myParityCtrl->SetToolTip(wxT("Enable to require valid SCSI parity bits when receiving data. Some hosts don't provide parity. SCSI2SD always outputs valid parity bits."));
fgs->Add(myParityCtrl);
- fgs->Add(new wxStaticText(this, wxID_ANY, wxT("")));
Bind(wxEVT_CHECKBOX, &TargetPanel::onInput<wxCommandEvent>, this, ID_parityCtrl);
- fgs->Add(new wxStaticText(this, wxID_ANY, wxT("")));
myUnitAttCtrl =
new wxCheckBox(
this,
wxT("Enable Unit Attention"));
myUnitAttCtrl->SetToolTip(wxT("Enable this to inform the host of changes after hot-swapping SD cards. Causes problems with Mac Plus."));
fgs->Add(myUnitAttCtrl);
- fgs->Add(new wxStaticText(this, wxID_ANY, wxT("")));
Bind(wxEVT_CHECKBOX, &TargetPanel::onInput<wxCommandEvent>, this, ID_unitAttCtrl);
fgs->Add(new wxStaticText(this, wxID_ANY, wxT("")));
wxT("Enable SCSI2 Mode"));
myScsi2Ctrl->SetToolTip(wxT("Enable high-performance mode. May cause problems with SASI/SCSI1 hosts."));
fgs->Add(myScsi2Ctrl);
- fgs->Add(new wxStaticText(this, wxID_ANY, wxT("")));
Bind(wxEVT_CHECKBOX, &TargetPanel::onInput<wxCommandEvent>, this, ID_scsi2Ctrl);
+ myGlitchCtrl =
+ new wxCheckBox(
+ this,
+ ID_glitchCtrl,
+ wxT("Disable glitch filter"));
+ myGlitchCtrl->SetToolTip(wxT("Improve performance at the cost of noise immunity. Only use with short cables."));
+ fgs->Add(myGlitchCtrl);
+ Bind(wxEVT_CHECKBOX, &TargetPanel::onInput<wxCommandEvent>, this, ID_glitchCtrl);
+
fgs->Add(new wxStaticText(this, wxID_ANY, wxT("SD card start sector")));
wxWrapSizer* startContainer = new wxWrapSizer();
myStartSDSectorCtrl =
myParityCtrl->Enable(enabled);
myUnitAttCtrl->Enable(enabled);
myScsi2Ctrl->Enable(enabled);
+ myGlitchCtrl->Enable(enabled);
myStartSDSectorCtrl->Enable(enabled && !myAutoStartSectorCtrl->IsChecked());
myAutoStartSectorCtrl->Enable(enabled);
mySectorSizeCtrl->Enable(enabled);
config.flags =
(myParityCtrl->IsChecked() ? CONFIG_ENABLE_PARITY : 0) |
(myUnitAttCtrl->IsChecked() ? CONFIG_ENABLE_UNIT_ATTENTION : 0) |
- (myScsi2Ctrl->IsChecked() ? CONFIG_ENABLE_SCSI2 : 0);
+ (myScsi2Ctrl->IsChecked() ? CONFIG_ENABLE_SCSI2 : 0) |
+ (myGlitchCtrl->IsChecked() ? CONFIG_DISABLE_GLITCH : 0);
auto startSDSector = CtrlGetValue<uint32_t>(myStartSDSectorCtrl);
config.sdSectorStart = startSDSector.first;
myParityCtrl->SetValue(config.flags & CONFIG_ENABLE_PARITY);
myUnitAttCtrl->SetValue(config.flags & CONFIG_ENABLE_UNIT_ATTENTION);
myScsi2Ctrl->SetValue(config.flags & CONFIG_ENABLE_SCSI2);
+ myGlitchCtrl->SetValue(config.flags & CONFIG_DISABLE_GLITCH);
{
std::stringstream ss; ss << config.sdSectorStart;
ID_parityCtrl,
ID_unitAttCtrl,
ID_scsi2Ctrl,
+ ID_glitchCtrl,
ID_startSDSectorCtrl,
ID_autoStartSectorCtrl,
ID_sectorSizeCtrl,
wxCheckBox* myParityCtrl;
wxCheckBox* myUnitAttCtrl;
wxCheckBox* myScsi2Ctrl;
+ wxCheckBox* myGlitchCtrl;
wxIntegerValidator<uint32_t>* myStartSDSectorValidator;
wxTextCtrl* myStartSDSectorCtrl;
projects / SCSI2SD-V6.git / commitdiff