+201404xx 3.5
+ - Fixed several performance issues. Transfer rates up to 2.5MB/s are now
+ possible.
+ - Implemented the READ BUFFER scsi command for performance testing purposes.
+
20140418 3.4
- Critical fix for writes when using non-standard block sizes.
- Fix to ensure SCSI phase bits are set atomically.
As currently implemented:
-Sequential read: 930kb/sec Sequential write: 900kb/sec
+Sequential read: 2.5MB/s Sequential write: 900kb/sec
Tested with a 16GB class 10 SD card, via the commands:
--- /dev/null
+/*******************************************************************************
+* File Name: SCSI_RX_DMA_COMPLETE.c
+* Version 1.70
+*
+* Description:
+* API for controlling the state of an interrupt.
+*
+*
+* Note:
+*
+********************************************************************************
+* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions,
+* disclaimers, and limitations in the end user license agreement accompanying
+* the software package with which this file was provided.
+*******************************************************************************/
+
+
+#include <cydevice_trm.h>
+#include <CyLib.h>
+#include <SCSI_RX_DMA_COMPLETE.h>
+
+#if !defined(SCSI_RX_DMA_COMPLETE__REMOVED) /* Check for removal by optimization */
+
+/*******************************************************************************
+* Place your includes, defines and code here
+********************************************************************************/
+/* `#START SCSI_RX_DMA_COMPLETE_intc` */
+
+/* `#END` */
+
+#ifndef CYINT_IRQ_BASE
+#define CYINT_IRQ_BASE 16
+#endif /* CYINT_IRQ_BASE */
+#ifndef CYINT_VECT_TABLE
+#define CYINT_VECT_TABLE ((cyisraddress **) CYREG_NVIC_VECT_OFFSET)
+#endif /* CYINT_VECT_TABLE */
+
+/* Declared in startup, used to set unused interrupts to. */
+CY_ISR_PROTO(IntDefaultHandler);
+
+
+/*******************************************************************************
+* Function Name: SCSI_RX_DMA_COMPLETE_Start
+********************************************************************************
+*
+* Summary:
+* Set up the interrupt and enable it.
+*
+* Parameters:
+* None
+*
+* Return:
+* None
+*
+*******************************************************************************/
+void SCSI_RX_DMA_COMPLETE_Start(void)
+{
+ /* For all we know the interrupt is active. */
+ SCSI_RX_DMA_COMPLETE_Disable();
+
+ /* Set the ISR to point to the SCSI_RX_DMA_COMPLETE Interrupt. */
+ SCSI_RX_DMA_COMPLETE_SetVector(&SCSI_RX_DMA_COMPLETE_Interrupt);
+
+ /* Set the priority. */
+ SCSI_RX_DMA_COMPLETE_SetPriority((uint8)SCSI_RX_DMA_COMPLETE_INTC_PRIOR_NUMBER);
+
+ /* Enable it. */
+ SCSI_RX_DMA_COMPLETE_Enable();
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_RX_DMA_COMPLETE_StartEx
+********************************************************************************
+*
+* Summary:
+* Set up the interrupt and enable it.
+*
+* Parameters:
+* address: Address of the ISR to set in the interrupt vector table.
+*
+* Return:
+* None
+*
+*******************************************************************************/
+void SCSI_RX_DMA_COMPLETE_StartEx(cyisraddress address)
+{
+ /* For all we know the interrupt is active. */
+ SCSI_RX_DMA_COMPLETE_Disable();
+
+ /* Set the ISR to point to the SCSI_RX_DMA_COMPLETE Interrupt. */
+ SCSI_RX_DMA_COMPLETE_SetVector(address);
+
+ /* Set the priority. */
+ SCSI_RX_DMA_COMPLETE_SetPriority((uint8)SCSI_RX_DMA_COMPLETE_INTC_PRIOR_NUMBER);
+
+ /* Enable it. */
+ SCSI_RX_DMA_COMPLETE_Enable();
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_RX_DMA_COMPLETE_Stop
+********************************************************************************
+*
+* Summary:
+* Disables and removes the interrupt.
+*
+* Parameters:
+*
+* Return:
+* None
+*
+*******************************************************************************/
+void SCSI_RX_DMA_COMPLETE_Stop(void)
+{
+ /* Disable this interrupt. */
+ SCSI_RX_DMA_COMPLETE_Disable();
+
+ /* Set the ISR to point to the passive one. */
+ SCSI_RX_DMA_COMPLETE_SetVector(&IntDefaultHandler);
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_RX_DMA_COMPLETE_Interrupt
+********************************************************************************
+*
+* Summary:
+* The default Interrupt Service Routine for SCSI_RX_DMA_COMPLETE.
+*
+* Add custom code between the coments to keep the next version of this file
+* from over writting your code.
+*
+* Parameters:
+*
+* Return:
+* None
+*
+*******************************************************************************/
+CY_ISR(SCSI_RX_DMA_COMPLETE_Interrupt)
+{
+ /* Place your Interrupt code here. */
+ /* `#START SCSI_RX_DMA_COMPLETE_Interrupt` */
+
+ /* `#END` */
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_RX_DMA_COMPLETE_SetVector
+********************************************************************************
+*
+* Summary:
+* Change the ISR vector for the Interrupt. Note calling SCSI_RX_DMA_COMPLETE_Start
+* will override any effect this method would have had. To set the vector
+* before the component has been started use SCSI_RX_DMA_COMPLETE_StartEx instead.
+*
+* Parameters:
+* address: Address of the ISR to set in the interrupt vector table.
+*
+* Return:
+* None
+*
+*******************************************************************************/
+void SCSI_RX_DMA_COMPLETE_SetVector(cyisraddress address)
+{
+ cyisraddress * ramVectorTable;
+
+ ramVectorTable = (cyisraddress *) *CYINT_VECT_TABLE;
+
+ ramVectorTable[CYINT_IRQ_BASE + (uint32)SCSI_RX_DMA_COMPLETE__INTC_NUMBER] = address;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_RX_DMA_COMPLETE_GetVector
+********************************************************************************
+*
+* Summary:
+* Gets the "address" of the current ISR vector for the Interrupt.
+*
+* Parameters:
+* None
+*
+* Return:
+* Address of the ISR in the interrupt vector table.
+*
+*******************************************************************************/
+cyisraddress SCSI_RX_DMA_COMPLETE_GetVector(void)
+{
+ cyisraddress * ramVectorTable;
+
+ ramVectorTable = (cyisraddress *) *CYINT_VECT_TABLE;
+
+ return ramVectorTable[CYINT_IRQ_BASE + (uint32)SCSI_RX_DMA_COMPLETE__INTC_NUMBER];
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_RX_DMA_COMPLETE_SetPriority
+********************************************************************************
+*
+* Summary:
+* Sets the Priority of the Interrupt. Note calling SCSI_RX_DMA_COMPLETE_Start
+* or SCSI_RX_DMA_COMPLETE_StartEx will override any effect this method
+* would have had. This method should only be called after
+* SCSI_RX_DMA_COMPLETE_Start or SCSI_RX_DMA_COMPLETE_StartEx has been called. To set
+* the initial priority for the component use the cydwr file in the tool.
+*
+* Parameters:
+* priority: Priority of the interrupt. 0 - 7, 0 being the highest.
+*
+* Return:
+* None
+*
+*******************************************************************************/
+void SCSI_RX_DMA_COMPLETE_SetPriority(uint8 priority)
+{
+ *SCSI_RX_DMA_COMPLETE_INTC_PRIOR = priority << 5;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_RX_DMA_COMPLETE_GetPriority
+********************************************************************************
+*
+* Summary:
+* Gets the Priority of the Interrupt.
+*
+* Parameters:
+* None
+*
+* Return:
+* Priority of the interrupt. 0 - 7, 0 being the highest.
+*
+*******************************************************************************/
+uint8 SCSI_RX_DMA_COMPLETE_GetPriority(void)
+{
+ uint8 priority;
+
+
+ priority = *SCSI_RX_DMA_COMPLETE_INTC_PRIOR >> 5;
+
+ return priority;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_RX_DMA_COMPLETE_Enable
+********************************************************************************
+*
+* Summary:
+* Enables the interrupt.
+*
+* Parameters:
+* None
+*
+* Return:
+* None
+*
+*******************************************************************************/
+void SCSI_RX_DMA_COMPLETE_Enable(void)
+{
+ /* Enable the general interrupt. */
+ *SCSI_RX_DMA_COMPLETE_INTC_SET_EN = SCSI_RX_DMA_COMPLETE__INTC_MASK;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_RX_DMA_COMPLETE_GetState
+********************************************************************************
+*
+* Summary:
+* Gets the state (enabled, disabled) of the Interrupt.
+*
+* Parameters:
+* None
+*
+* Return:
+* 1 if enabled, 0 if disabled.
+*
+*******************************************************************************/
+uint8 SCSI_RX_DMA_COMPLETE_GetState(void)
+{
+ /* Get the state of the general interrupt. */
+ return ((*SCSI_RX_DMA_COMPLETE_INTC_SET_EN & (uint32)SCSI_RX_DMA_COMPLETE__INTC_MASK) != 0u) ? 1u:0u;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_RX_DMA_COMPLETE_Disable
+********************************************************************************
+*
+* Summary:
+* Disables the Interrupt.
+*
+* Parameters:
+* None
+*
+* Return:
+* None
+*
+*******************************************************************************/
+void SCSI_RX_DMA_COMPLETE_Disable(void)
+{
+ /* Disable the general interrupt. */
+ *SCSI_RX_DMA_COMPLETE_INTC_CLR_EN = SCSI_RX_DMA_COMPLETE__INTC_MASK;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_RX_DMA_COMPLETE_SetPending
+********************************************************************************
+*
+* Summary:
+* Causes the Interrupt to enter the pending state, a software method of
+* generating the interrupt.
+*
+* Parameters:
+* None
+*
+* Return:
+* None
+*
+*******************************************************************************/
+void SCSI_RX_DMA_COMPLETE_SetPending(void)
+{
+ *SCSI_RX_DMA_COMPLETE_INTC_SET_PD = SCSI_RX_DMA_COMPLETE__INTC_MASK;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_RX_DMA_COMPLETE_ClearPending
+********************************************************************************
+*
+* Summary:
+* Clears a pending interrupt.
+*
+* Parameters:
+* None
+*
+* Return:
+* None
+*
+*******************************************************************************/
+void SCSI_RX_DMA_COMPLETE_ClearPending(void)
+{
+ *SCSI_RX_DMA_COMPLETE_INTC_CLR_PD = SCSI_RX_DMA_COMPLETE__INTC_MASK;
+}
+
+#endif /* End check for removal by optimization */
+
+
+/* [] END OF FILE */
--- /dev/null
+/*******************************************************************************
+* File Name: SCSI_RX_DMA_COMPLETE.h
+* Version 1.70
+*
+* Description:
+* Provides the function definitions for the Interrupt Controller.
+*
+*
+********************************************************************************
+* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions,
+* disclaimers, and limitations in the end user license agreement accompanying
+* the software package with which this file was provided.
+*******************************************************************************/
+#if !defined(CY_ISR_SCSI_RX_DMA_COMPLETE_H)
+#define CY_ISR_SCSI_RX_DMA_COMPLETE_H
+
+
+#include <cytypes.h>
+#include <cyfitter.h>
+
+/* Interrupt Controller API. */
+void SCSI_RX_DMA_COMPLETE_Start(void);
+void SCSI_RX_DMA_COMPLETE_StartEx(cyisraddress address);
+void SCSI_RX_DMA_COMPLETE_Stop(void);
+
+CY_ISR_PROTO(SCSI_RX_DMA_COMPLETE_Interrupt);
+
+void SCSI_RX_DMA_COMPLETE_SetVector(cyisraddress address);
+cyisraddress SCSI_RX_DMA_COMPLETE_GetVector(void);
+
+void SCSI_RX_DMA_COMPLETE_SetPriority(uint8 priority);
+uint8 SCSI_RX_DMA_COMPLETE_GetPriority(void);
+
+void SCSI_RX_DMA_COMPLETE_Enable(void);
+uint8 SCSI_RX_DMA_COMPLETE_GetState(void);
+void SCSI_RX_DMA_COMPLETE_Disable(void);
+
+void SCSI_RX_DMA_COMPLETE_SetPending(void);
+void SCSI_RX_DMA_COMPLETE_ClearPending(void);
+
+
+/* Interrupt Controller Constants */
+
+/* Address of the INTC.VECT[x] register that contains the Address of the SCSI_RX_DMA_COMPLETE ISR. */
+#define SCSI_RX_DMA_COMPLETE_INTC_VECTOR ((reg32 *) SCSI_RX_DMA_COMPLETE__INTC_VECT)
+
+/* Address of the SCSI_RX_DMA_COMPLETE ISR priority. */
+#define SCSI_RX_DMA_COMPLETE_INTC_PRIOR ((reg8 *) SCSI_RX_DMA_COMPLETE__INTC_PRIOR_REG)
+
+/* Priority of the SCSI_RX_DMA_COMPLETE interrupt. */
+#define SCSI_RX_DMA_COMPLETE_INTC_PRIOR_NUMBER SCSI_RX_DMA_COMPLETE__INTC_PRIOR_NUM
+
+/* Address of the INTC.SET_EN[x] byte to bit enable SCSI_RX_DMA_COMPLETE interrupt. */
+#define SCSI_RX_DMA_COMPLETE_INTC_SET_EN ((reg32 *) SCSI_RX_DMA_COMPLETE__INTC_SET_EN_REG)
+
+/* Address of the INTC.CLR_EN[x] register to bit clear the SCSI_RX_DMA_COMPLETE interrupt. */
+#define SCSI_RX_DMA_COMPLETE_INTC_CLR_EN ((reg32 *) SCSI_RX_DMA_COMPLETE__INTC_CLR_EN_REG)
+
+/* Address of the INTC.SET_PD[x] register to set the SCSI_RX_DMA_COMPLETE interrupt state to pending. */
+#define SCSI_RX_DMA_COMPLETE_INTC_SET_PD ((reg32 *) SCSI_RX_DMA_COMPLETE__INTC_SET_PD_REG)
+
+/* Address of the INTC.CLR_PD[x] register to clear the SCSI_RX_DMA_COMPLETE interrupt. */
+#define SCSI_RX_DMA_COMPLETE_INTC_CLR_PD ((reg32 *) SCSI_RX_DMA_COMPLETE__INTC_CLR_PD_REG)
+
+
+#endif /* CY_ISR_SCSI_RX_DMA_COMPLETE_H */
+
+
+/* [] END OF FILE */
--- /dev/null
+/***************************************************************************
+* File Name: SCSI_RX_DMA_dma.c
+* Version 1.70
+*
+* Description:
+* Provides an API for the DMAC component. The API includes functions
+* for the DMA controller, DMA channels and Transfer Descriptors.
+*
+*
+* Note:
+* This module requires the developer to finish or fill in the auto
+* generated funcions and setup the dma channel and TD's.
+*
+********************************************************************************
+* Copyright 2008-2010, Cypress Semiconductor Corporation. All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions,
+* disclaimers, and limitations in the end user license agreement accompanying
+* the software package with which this file was provided.
+********************************************************************************/
+#include <CYLIB.H>
+#include <CYDMAC.H>
+#include <SCSI_RX_DMA_dma.H>
+
+
+
+/****************************************************************************
+*
+* The following defines are available in Cyfitter.h
+*
+*
+*
+* SCSI_RX_DMA__DRQ_CTL_REG
+*
+*
+* SCSI_RX_DMA__DRQ_NUMBER
+*
+* Number of TD's used by this channel.
+* SCSI_RX_DMA__NUMBEROF_TDS
+*
+* Priority of this channel.
+* SCSI_RX_DMA__PRIORITY
+*
+* True if SCSI_RX_DMA_TERMIN_SEL is used.
+* SCSI_RX_DMA__TERMIN_EN
+*
+* TERMIN interrupt line to signal terminate.
+* SCSI_RX_DMA__TERMIN_SEL
+*
+*
+* True if SCSI_RX_DMA_TERMOUT0_SEL is used.
+* SCSI_RX_DMA__TERMOUT0_EN
+*
+*
+* TERMOUT0 interrupt line to signal completion.
+* SCSI_RX_DMA__TERMOUT0_SEL
+*
+*
+* True if SCSI_RX_DMA_TERMOUT1_SEL is used.
+* SCSI_RX_DMA__TERMOUT1_EN
+*
+*
+* TERMOUT1 interrupt line to signal completion.
+* SCSI_RX_DMA__TERMOUT1_SEL
+*
+****************************************************************************/
+
+
+/* Zero based index of SCSI_RX_DMA dma channel */
+uint8 SCSI_RX_DMA_DmaHandle = DMA_INVALID_CHANNEL;
+
+/*********************************************************************
+* Function Name: uint8 SCSI_RX_DMA_DmaInitalize
+**********************************************************************
+* Summary:
+* Allocates and initialises a channel of the DMAC to be used by the
+* caller.
+*
+* Parameters:
+* BurstCount.
+*
+*
+* ReqestPerBurst.
+*
+*
+* UpperSrcAddress.
+*
+*
+* UpperDestAddress.
+*
+*
+* Return:
+* The channel that can be used by the caller for DMA activity.
+* DMA_INVALID_CHANNEL (0xFF) if there are no channels left.
+*
+*
+*******************************************************************/
+uint8 SCSI_RX_DMA_DmaInitialize(uint8 BurstCount, uint8 ReqestPerBurst, uint16 UpperSrcAddress, uint16 UpperDestAddress)
+{
+
+ /* Allocate a DMA channel. */
+ SCSI_RX_DMA_DmaHandle = (uint8)SCSI_RX_DMA__DRQ_NUMBER;
+
+ /* Configure the channel. */
+ (void)CyDmaChSetConfiguration(SCSI_RX_DMA_DmaHandle,
+ BurstCount,
+ ReqestPerBurst,
+ (uint8)SCSI_RX_DMA__TERMOUT0_SEL,
+ (uint8)SCSI_RX_DMA__TERMOUT1_SEL,
+ (uint8)SCSI_RX_DMA__TERMIN_SEL);
+
+ /* Set the extended address for the transfers */
+ (void)CyDmaChSetExtendedAddress(SCSI_RX_DMA_DmaHandle, UpperSrcAddress, UpperDestAddress);
+
+ /* Set the priority for this channel */
+ (void)CyDmaChPriority(SCSI_RX_DMA_DmaHandle, (uint8)SCSI_RX_DMA__PRIORITY);
+
+ return SCSI_RX_DMA_DmaHandle;
+}
+
+/*********************************************************************
+* Function Name: void SCSI_RX_DMA_DmaRelease
+**********************************************************************
+* Summary:
+* Frees the channel associated with SCSI_RX_DMA.
+*
+*
+* Parameters:
+* void.
+*
+*
+*
+* Return:
+* void.
+*
+*******************************************************************/
+void SCSI_RX_DMA_DmaRelease(void)
+{
+ /* Disable the channel */
+ (void)CyDmaChDisable(SCSI_RX_DMA_DmaHandle);
+}
+
--- /dev/null
+/******************************************************************************
+* File Name: SCSI_RX_DMA_dma.h
+* Version 1.70
+*
+* Description:
+* Provides the function definitions for the DMA Controller.
+*
+*
+********************************************************************************
+* Copyright 2008-2010, Cypress Semiconductor Corporation. All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions,
+* disclaimers, and limitations in the end user license agreement accompanying
+* the software package with which this file was provided.
+********************************************************************************/
+#if !defined(CY_DMA_SCSI_RX_DMA_DMA_H__)
+#define CY_DMA_SCSI_RX_DMA_DMA_H__
+
+
+
+#include <CYDMAC.H>
+#include <CYFITTER.H>
+
+#define SCSI_RX_DMA__TD_TERMOUT_EN (((0 != SCSI_RX_DMA__TERMOUT0_EN) ? TD_TERMOUT0_EN : 0) | \
+ (SCSI_RX_DMA__TERMOUT1_EN ? TD_TERMOUT1_EN : 0))
+
+/* Zero based index of SCSI_RX_DMA dma channel */
+extern uint8 SCSI_RX_DMA_DmaHandle;
+
+
+uint8 SCSI_RX_DMA_DmaInitialize(uint8 BurstCount, uint8 ReqestPerBurst, uint16 UpperSrcAddress, uint16 UpperDestAddress) ;
+void SCSI_RX_DMA_DmaRelease(void) ;
+
+
+/* CY_DMA_SCSI_RX_DMA_DMA_H__ */
+#endif
--- /dev/null
+/*******************************************************************************
+* File Name: SCSI_TX_COMPLETE.c
+* Version 1.70
+*
+* Description:
+* API for controlling the state of an interrupt.
+*
+*
+* Note:
+*
+********************************************************************************
+* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions,
+* disclaimers, and limitations in the end user license agreement accompanying
+* the software package with which this file was provided.
+*******************************************************************************/
+
+
+#include <cydevice_trm.h>
+#include <CyLib.h>
+#include <SCSI_TX_COMPLETE.h>
+
+#if !defined(SCSI_TX_COMPLETE__REMOVED) /* Check for removal by optimization */
+
+/*******************************************************************************
+* Place your includes, defines and code here
+********************************************************************************/
+/* `#START SCSI_TX_COMPLETE_intc` */
+
+/* `#END` */
+
+#ifndef CYINT_IRQ_BASE
+#define CYINT_IRQ_BASE 16
+#endif /* CYINT_IRQ_BASE */
+#ifndef CYINT_VECT_TABLE
+#define CYINT_VECT_TABLE ((cyisraddress **) CYREG_NVIC_VECT_OFFSET)
+#endif /* CYINT_VECT_TABLE */
+
+/* Declared in startup, used to set unused interrupts to. */
+CY_ISR_PROTO(IntDefaultHandler);
+
+
+/*******************************************************************************
+* Function Name: SCSI_TX_COMPLETE_Start
+********************************************************************************
+*
+* Summary:
+* Set up the interrupt and enable it.
+*
+* Parameters:
+* None
+*
+* Return:
+* None
+*
+*******************************************************************************/
+void SCSI_TX_COMPLETE_Start(void)
+{
+ /* For all we know the interrupt is active. */
+ SCSI_TX_COMPLETE_Disable();
+
+ /* Set the ISR to point to the SCSI_TX_COMPLETE Interrupt. */
+ SCSI_TX_COMPLETE_SetVector(&SCSI_TX_COMPLETE_Interrupt);
+
+ /* Set the priority. */
+ SCSI_TX_COMPLETE_SetPriority((uint8)SCSI_TX_COMPLETE_INTC_PRIOR_NUMBER);
+
+ /* Enable it. */
+ SCSI_TX_COMPLETE_Enable();
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_TX_COMPLETE_StartEx
+********************************************************************************
+*
+* Summary:
+* Set up the interrupt and enable it.
+*
+* Parameters:
+* address: Address of the ISR to set in the interrupt vector table.
+*
+* Return:
+* None
+*
+*******************************************************************************/
+void SCSI_TX_COMPLETE_StartEx(cyisraddress address)
+{
+ /* For all we know the interrupt is active. */
+ SCSI_TX_COMPLETE_Disable();
+
+ /* Set the ISR to point to the SCSI_TX_COMPLETE Interrupt. */
+ SCSI_TX_COMPLETE_SetVector(address);
+
+ /* Set the priority. */
+ SCSI_TX_COMPLETE_SetPriority((uint8)SCSI_TX_COMPLETE_INTC_PRIOR_NUMBER);
+
+ /* Enable it. */
+ SCSI_TX_COMPLETE_Enable();
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_TX_COMPLETE_Stop
+********************************************************************************
+*
+* Summary:
+* Disables and removes the interrupt.
+*
+* Parameters:
+*
+* Return:
+* None
+*
+*******************************************************************************/
+void SCSI_TX_COMPLETE_Stop(void)
+{
+ /* Disable this interrupt. */
+ SCSI_TX_COMPLETE_Disable();
+
+ /* Set the ISR to point to the passive one. */
+ SCSI_TX_COMPLETE_SetVector(&IntDefaultHandler);
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_TX_COMPLETE_Interrupt
+********************************************************************************
+*
+* Summary:
+* The default Interrupt Service Routine for SCSI_TX_COMPLETE.
+*
+* Add custom code between the coments to keep the next version of this file
+* from over writting your code.
+*
+* Parameters:
+*
+* Return:
+* None
+*
+*******************************************************************************/
+CY_ISR(SCSI_TX_COMPLETE_Interrupt)
+{
+ /* Place your Interrupt code here. */
+ /* `#START SCSI_TX_COMPLETE_Interrupt` */
+
+ /* `#END` */
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_TX_COMPLETE_SetVector
+********************************************************************************
+*
+* Summary:
+* Change the ISR vector for the Interrupt. Note calling SCSI_TX_COMPLETE_Start
+* will override any effect this method would have had. To set the vector
+* before the component has been started use SCSI_TX_COMPLETE_StartEx instead.
+*
+* Parameters:
+* address: Address of the ISR to set in the interrupt vector table.
+*
+* Return:
+* None
+*
+*******************************************************************************/
+void SCSI_TX_COMPLETE_SetVector(cyisraddress address)
+{
+ cyisraddress * ramVectorTable;
+
+ ramVectorTable = (cyisraddress *) *CYINT_VECT_TABLE;
+
+ ramVectorTable[CYINT_IRQ_BASE + (uint32)SCSI_TX_COMPLETE__INTC_NUMBER] = address;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_TX_COMPLETE_GetVector
+********************************************************************************
+*
+* Summary:
+* Gets the "address" of the current ISR vector for the Interrupt.
+*
+* Parameters:
+* None
+*
+* Return:
+* Address of the ISR in the interrupt vector table.
+*
+*******************************************************************************/
+cyisraddress SCSI_TX_COMPLETE_GetVector(void)
+{
+ cyisraddress * ramVectorTable;
+
+ ramVectorTable = (cyisraddress *) *CYINT_VECT_TABLE;
+
+ return ramVectorTable[CYINT_IRQ_BASE + (uint32)SCSI_TX_COMPLETE__INTC_NUMBER];
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_TX_COMPLETE_SetPriority
+********************************************************************************
+*
+* Summary:
+* Sets the Priority of the Interrupt. Note calling SCSI_TX_COMPLETE_Start
+* or SCSI_TX_COMPLETE_StartEx will override any effect this method
+* would have had. This method should only be called after
+* SCSI_TX_COMPLETE_Start or SCSI_TX_COMPLETE_StartEx has been called. To set
+* the initial priority for the component use the cydwr file in the tool.
+*
+* Parameters:
+* priority: Priority of the interrupt. 0 - 7, 0 being the highest.
+*
+* Return:
+* None
+*
+*******************************************************************************/
+void SCSI_TX_COMPLETE_SetPriority(uint8 priority)
+{
+ *SCSI_TX_COMPLETE_INTC_PRIOR = priority << 5;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_TX_COMPLETE_GetPriority
+********************************************************************************
+*
+* Summary:
+* Gets the Priority of the Interrupt.
+*
+* Parameters:
+* None
+*
+* Return:
+* Priority of the interrupt. 0 - 7, 0 being the highest.
+*
+*******************************************************************************/
+uint8 SCSI_TX_COMPLETE_GetPriority(void)
+{
+ uint8 priority;
+
+
+ priority = *SCSI_TX_COMPLETE_INTC_PRIOR >> 5;
+
+ return priority;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_TX_COMPLETE_Enable
+********************************************************************************
+*
+* Summary:
+* Enables the interrupt.
+*
+* Parameters:
+* None
+*
+* Return:
+* None
+*
+*******************************************************************************/
+void SCSI_TX_COMPLETE_Enable(void)
+{
+ /* Enable the general interrupt. */
+ *SCSI_TX_COMPLETE_INTC_SET_EN = SCSI_TX_COMPLETE__INTC_MASK;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_TX_COMPLETE_GetState
+********************************************************************************
+*
+* Summary:
+* Gets the state (enabled, disabled) of the Interrupt.
+*
+* Parameters:
+* None
+*
+* Return:
+* 1 if enabled, 0 if disabled.
+*
+*******************************************************************************/
+uint8 SCSI_TX_COMPLETE_GetState(void)
+{
+ /* Get the state of the general interrupt. */
+ return ((*SCSI_TX_COMPLETE_INTC_SET_EN & (uint32)SCSI_TX_COMPLETE__INTC_MASK) != 0u) ? 1u:0u;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_TX_COMPLETE_Disable
+********************************************************************************
+*
+* Summary:
+* Disables the Interrupt.
+*
+* Parameters:
+* None
+*
+* Return:
+* None
+*
+*******************************************************************************/
+void SCSI_TX_COMPLETE_Disable(void)
+{
+ /* Disable the general interrupt. */
+ *SCSI_TX_COMPLETE_INTC_CLR_EN = SCSI_TX_COMPLETE__INTC_MASK;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_TX_COMPLETE_SetPending
+********************************************************************************
+*
+* Summary:
+* Causes the Interrupt to enter the pending state, a software method of
+* generating the interrupt.
+*
+* Parameters:
+* None
+*
+* Return:
+* None
+*
+*******************************************************************************/
+void SCSI_TX_COMPLETE_SetPending(void)
+{
+ *SCSI_TX_COMPLETE_INTC_SET_PD = SCSI_TX_COMPLETE__INTC_MASK;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_TX_COMPLETE_ClearPending
+********************************************************************************
+*
+* Summary:
+* Clears a pending interrupt.
+*
+* Parameters:
+* None
+*
+* Return:
+* None
+*
+*******************************************************************************/
+void SCSI_TX_COMPLETE_ClearPending(void)
+{
+ *SCSI_TX_COMPLETE_INTC_CLR_PD = SCSI_TX_COMPLETE__INTC_MASK;
+}
+
+#endif /* End check for removal by optimization */
+
+
+/* [] END OF FILE */
--- /dev/null
+/*******************************************************************************
+* File Name: SCSI_TX_COMPLETE.h
+* Version 1.70
+*
+* Description:
+* Provides the function definitions for the Interrupt Controller.
+*
+*
+********************************************************************************
+* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions,
+* disclaimers, and limitations in the end user license agreement accompanying
+* the software package with which this file was provided.
+*******************************************************************************/
+#if !defined(CY_ISR_SCSI_TX_COMPLETE_H)
+#define CY_ISR_SCSI_TX_COMPLETE_H
+
+
+#include <cytypes.h>
+#include <cyfitter.h>
+
+/* Interrupt Controller API. */
+void SCSI_TX_COMPLETE_Start(void);
+void SCSI_TX_COMPLETE_StartEx(cyisraddress address);
+void SCSI_TX_COMPLETE_Stop(void);
+
+CY_ISR_PROTO(SCSI_TX_COMPLETE_Interrupt);
+
+void SCSI_TX_COMPLETE_SetVector(cyisraddress address);
+cyisraddress SCSI_TX_COMPLETE_GetVector(void);
+
+void SCSI_TX_COMPLETE_SetPriority(uint8 priority);
+uint8 SCSI_TX_COMPLETE_GetPriority(void);
+
+void SCSI_TX_COMPLETE_Enable(void);
+uint8 SCSI_TX_COMPLETE_GetState(void);
+void SCSI_TX_COMPLETE_Disable(void);
+
+void SCSI_TX_COMPLETE_SetPending(void);
+void SCSI_TX_COMPLETE_ClearPending(void);
+
+
+/* Interrupt Controller Constants */
+
+/* Address of the INTC.VECT[x] register that contains the Address of the SCSI_TX_COMPLETE ISR. */
+#define SCSI_TX_COMPLETE_INTC_VECTOR ((reg32 *) SCSI_TX_COMPLETE__INTC_VECT)
+
+/* Address of the SCSI_TX_COMPLETE ISR priority. */
+#define SCSI_TX_COMPLETE_INTC_PRIOR ((reg8 *) SCSI_TX_COMPLETE__INTC_PRIOR_REG)
+
+/* Priority of the SCSI_TX_COMPLETE interrupt. */
+#define SCSI_TX_COMPLETE_INTC_PRIOR_NUMBER SCSI_TX_COMPLETE__INTC_PRIOR_NUM
+
+/* Address of the INTC.SET_EN[x] byte to bit enable SCSI_TX_COMPLETE interrupt. */
+#define SCSI_TX_COMPLETE_INTC_SET_EN ((reg32 *) SCSI_TX_COMPLETE__INTC_SET_EN_REG)
+
+/* Address of the INTC.CLR_EN[x] register to bit clear the SCSI_TX_COMPLETE interrupt. */
+#define SCSI_TX_COMPLETE_INTC_CLR_EN ((reg32 *) SCSI_TX_COMPLETE__INTC_CLR_EN_REG)
+
+/* Address of the INTC.SET_PD[x] register to set the SCSI_TX_COMPLETE interrupt state to pending. */
+#define SCSI_TX_COMPLETE_INTC_SET_PD ((reg32 *) SCSI_TX_COMPLETE__INTC_SET_PD_REG)
+
+/* Address of the INTC.CLR_PD[x] register to clear the SCSI_TX_COMPLETE interrupt. */
+#define SCSI_TX_COMPLETE_INTC_CLR_PD ((reg32 *) SCSI_TX_COMPLETE__INTC_CLR_PD_REG)
+
+
+#endif /* CY_ISR_SCSI_TX_COMPLETE_H */
+
+
+/* [] END OF FILE */
--- /dev/null
+/*******************************************************************************
+* File Name: SCSI_TX_DMA_COMPLETE.c
+* Version 1.70
+*
+* Description:
+* API for controlling the state of an interrupt.
+*
+*
+* Note:
+*
+********************************************************************************
+* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions,
+* disclaimers, and limitations in the end user license agreement accompanying
+* the software package with which this file was provided.
+*******************************************************************************/
+
+
+#include <cydevice_trm.h>
+#include <CyLib.h>
+#include <SCSI_TX_DMA_COMPLETE.h>
+
+#if !defined(SCSI_TX_DMA_COMPLETE__REMOVED) /* Check for removal by optimization */
+
+/*******************************************************************************
+* Place your includes, defines and code here
+********************************************************************************/
+/* `#START SCSI_TX_DMA_COMPLETE_intc` */
+
+/* `#END` */
+
+#ifndef CYINT_IRQ_BASE
+#define CYINT_IRQ_BASE 16
+#endif /* CYINT_IRQ_BASE */
+#ifndef CYINT_VECT_TABLE
+#define CYINT_VECT_TABLE ((cyisraddress **) CYREG_NVIC_VECT_OFFSET)
+#endif /* CYINT_VECT_TABLE */
+
+/* Declared in startup, used to set unused interrupts to. */
+CY_ISR_PROTO(IntDefaultHandler);
+
+
+/*******************************************************************************
+* Function Name: SCSI_TX_DMA_COMPLETE_Start
+********************************************************************************
+*
+* Summary:
+* Set up the interrupt and enable it.
+*
+* Parameters:
+* None
+*
+* Return:
+* None
+*
+*******************************************************************************/
+void SCSI_TX_DMA_COMPLETE_Start(void)
+{
+ /* For all we know the interrupt is active. */
+ SCSI_TX_DMA_COMPLETE_Disable();
+
+ /* Set the ISR to point to the SCSI_TX_DMA_COMPLETE Interrupt. */
+ SCSI_TX_DMA_COMPLETE_SetVector(&SCSI_TX_DMA_COMPLETE_Interrupt);
+
+ /* Set the priority. */
+ SCSI_TX_DMA_COMPLETE_SetPriority((uint8)SCSI_TX_DMA_COMPLETE_INTC_PRIOR_NUMBER);
+
+ /* Enable it. */
+ SCSI_TX_DMA_COMPLETE_Enable();
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_TX_DMA_COMPLETE_StartEx
+********************************************************************************
+*
+* Summary:
+* Set up the interrupt and enable it.
+*
+* Parameters:
+* address: Address of the ISR to set in the interrupt vector table.
+*
+* Return:
+* None
+*
+*******************************************************************************/
+void SCSI_TX_DMA_COMPLETE_StartEx(cyisraddress address)
+{
+ /* For all we know the interrupt is active. */
+ SCSI_TX_DMA_COMPLETE_Disable();
+
+ /* Set the ISR to point to the SCSI_TX_DMA_COMPLETE Interrupt. */
+ SCSI_TX_DMA_COMPLETE_SetVector(address);
+
+ /* Set the priority. */
+ SCSI_TX_DMA_COMPLETE_SetPriority((uint8)SCSI_TX_DMA_COMPLETE_INTC_PRIOR_NUMBER);
+
+ /* Enable it. */
+ SCSI_TX_DMA_COMPLETE_Enable();
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_TX_DMA_COMPLETE_Stop
+********************************************************************************
+*
+* Summary:
+* Disables and removes the interrupt.
+*
+* Parameters:
+*
+* Return:
+* None
+*
+*******************************************************************************/
+void SCSI_TX_DMA_COMPLETE_Stop(void)
+{
+ /* Disable this interrupt. */
+ SCSI_TX_DMA_COMPLETE_Disable();
+
+ /* Set the ISR to point to the passive one. */
+ SCSI_TX_DMA_COMPLETE_SetVector(&IntDefaultHandler);
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_TX_DMA_COMPLETE_Interrupt
+********************************************************************************
+*
+* Summary:
+* The default Interrupt Service Routine for SCSI_TX_DMA_COMPLETE.
+*
+* Add custom code between the coments to keep the next version of this file
+* from over writting your code.
+*
+* Parameters:
+*
+* Return:
+* None
+*
+*******************************************************************************/
+CY_ISR(SCSI_TX_DMA_COMPLETE_Interrupt)
+{
+ /* Place your Interrupt code here. */
+ /* `#START SCSI_TX_DMA_COMPLETE_Interrupt` */
+
+ /* `#END` */
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_TX_DMA_COMPLETE_SetVector
+********************************************************************************
+*
+* Summary:
+* Change the ISR vector for the Interrupt. Note calling SCSI_TX_DMA_COMPLETE_Start
+* will override any effect this method would have had. To set the vector
+* before the component has been started use SCSI_TX_DMA_COMPLETE_StartEx instead.
+*
+* Parameters:
+* address: Address of the ISR to set in the interrupt vector table.
+*
+* Return:
+* None
+*
+*******************************************************************************/
+void SCSI_TX_DMA_COMPLETE_SetVector(cyisraddress address)
+{
+ cyisraddress * ramVectorTable;
+
+ ramVectorTable = (cyisraddress *) *CYINT_VECT_TABLE;
+
+ ramVectorTable[CYINT_IRQ_BASE + (uint32)SCSI_TX_DMA_COMPLETE__INTC_NUMBER] = address;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_TX_DMA_COMPLETE_GetVector
+********************************************************************************
+*
+* Summary:
+* Gets the "address" of the current ISR vector for the Interrupt.
+*
+* Parameters:
+* None
+*
+* Return:
+* Address of the ISR in the interrupt vector table.
+*
+*******************************************************************************/
+cyisraddress SCSI_TX_DMA_COMPLETE_GetVector(void)
+{
+ cyisraddress * ramVectorTable;
+
+ ramVectorTable = (cyisraddress *) *CYINT_VECT_TABLE;
+
+ return ramVectorTable[CYINT_IRQ_BASE + (uint32)SCSI_TX_DMA_COMPLETE__INTC_NUMBER];
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_TX_DMA_COMPLETE_SetPriority
+********************************************************************************
+*
+* Summary:
+* Sets the Priority of the Interrupt. Note calling SCSI_TX_DMA_COMPLETE_Start
+* or SCSI_TX_DMA_COMPLETE_StartEx will override any effect this method
+* would have had. This method should only be called after
+* SCSI_TX_DMA_COMPLETE_Start or SCSI_TX_DMA_COMPLETE_StartEx has been called. To set
+* the initial priority for the component use the cydwr file in the tool.
+*
+* Parameters:
+* priority: Priority of the interrupt. 0 - 7, 0 being the highest.
+*
+* Return:
+* None
+*
+*******************************************************************************/
+void SCSI_TX_DMA_COMPLETE_SetPriority(uint8 priority)
+{
+ *SCSI_TX_DMA_COMPLETE_INTC_PRIOR = priority << 5;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_TX_DMA_COMPLETE_GetPriority
+********************************************************************************
+*
+* Summary:
+* Gets the Priority of the Interrupt.
+*
+* Parameters:
+* None
+*
+* Return:
+* Priority of the interrupt. 0 - 7, 0 being the highest.
+*
+*******************************************************************************/
+uint8 SCSI_TX_DMA_COMPLETE_GetPriority(void)
+{
+ uint8 priority;
+
+
+ priority = *SCSI_TX_DMA_COMPLETE_INTC_PRIOR >> 5;
+
+ return priority;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_TX_DMA_COMPLETE_Enable
+********************************************************************************
+*
+* Summary:
+* Enables the interrupt.
+*
+* Parameters:
+* None
+*
+* Return:
+* None
+*
+*******************************************************************************/
+void SCSI_TX_DMA_COMPLETE_Enable(void)
+{
+ /* Enable the general interrupt. */
+ *SCSI_TX_DMA_COMPLETE_INTC_SET_EN = SCSI_TX_DMA_COMPLETE__INTC_MASK;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_TX_DMA_COMPLETE_GetState
+********************************************************************************
+*
+* Summary:
+* Gets the state (enabled, disabled) of the Interrupt.
+*
+* Parameters:
+* None
+*
+* Return:
+* 1 if enabled, 0 if disabled.
+*
+*******************************************************************************/
+uint8 SCSI_TX_DMA_COMPLETE_GetState(void)
+{
+ /* Get the state of the general interrupt. */
+ return ((*SCSI_TX_DMA_COMPLETE_INTC_SET_EN & (uint32)SCSI_TX_DMA_COMPLETE__INTC_MASK) != 0u) ? 1u:0u;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_TX_DMA_COMPLETE_Disable
+********************************************************************************
+*
+* Summary:
+* Disables the Interrupt.
+*
+* Parameters:
+* None
+*
+* Return:
+* None
+*
+*******************************************************************************/
+void SCSI_TX_DMA_COMPLETE_Disable(void)
+{
+ /* Disable the general interrupt. */
+ *SCSI_TX_DMA_COMPLETE_INTC_CLR_EN = SCSI_TX_DMA_COMPLETE__INTC_MASK;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_TX_DMA_COMPLETE_SetPending
+********************************************************************************
+*
+* Summary:
+* Causes the Interrupt to enter the pending state, a software method of
+* generating the interrupt.
+*
+* Parameters:
+* None
+*
+* Return:
+* None
+*
+*******************************************************************************/
+void SCSI_TX_DMA_COMPLETE_SetPending(void)
+{
+ *SCSI_TX_DMA_COMPLETE_INTC_SET_PD = SCSI_TX_DMA_COMPLETE__INTC_MASK;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_TX_DMA_COMPLETE_ClearPending
+********************************************************************************
+*
+* Summary:
+* Clears a pending interrupt.
+*
+* Parameters:
+* None
+*
+* Return:
+* None
+*
+*******************************************************************************/
+void SCSI_TX_DMA_COMPLETE_ClearPending(void)
+{
+ *SCSI_TX_DMA_COMPLETE_INTC_CLR_PD = SCSI_TX_DMA_COMPLETE__INTC_MASK;
+}
+
+#endif /* End check for removal by optimization */
+
+
+/* [] END OF FILE */
--- /dev/null
+/*******************************************************************************
+* File Name: SCSI_TX_DMA_COMPLETE.h
+* Version 1.70
+*
+* Description:
+* Provides the function definitions for the Interrupt Controller.
+*
+*
+********************************************************************************
+* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions,
+* disclaimers, and limitations in the end user license agreement accompanying
+* the software package with which this file was provided.
+*******************************************************************************/
+#if !defined(CY_ISR_SCSI_TX_DMA_COMPLETE_H)
+#define CY_ISR_SCSI_TX_DMA_COMPLETE_H
+
+
+#include <cytypes.h>
+#include <cyfitter.h>
+
+/* Interrupt Controller API. */
+void SCSI_TX_DMA_COMPLETE_Start(void);
+void SCSI_TX_DMA_COMPLETE_StartEx(cyisraddress address);
+void SCSI_TX_DMA_COMPLETE_Stop(void);
+
+CY_ISR_PROTO(SCSI_TX_DMA_COMPLETE_Interrupt);
+
+void SCSI_TX_DMA_COMPLETE_SetVector(cyisraddress address);
+cyisraddress SCSI_TX_DMA_COMPLETE_GetVector(void);
+
+void SCSI_TX_DMA_COMPLETE_SetPriority(uint8 priority);
+uint8 SCSI_TX_DMA_COMPLETE_GetPriority(void);
+
+void SCSI_TX_DMA_COMPLETE_Enable(void);
+uint8 SCSI_TX_DMA_COMPLETE_GetState(void);
+void SCSI_TX_DMA_COMPLETE_Disable(void);
+
+void SCSI_TX_DMA_COMPLETE_SetPending(void);
+void SCSI_TX_DMA_COMPLETE_ClearPending(void);
+
+
+/* Interrupt Controller Constants */
+
+/* Address of the INTC.VECT[x] register that contains the Address of the SCSI_TX_DMA_COMPLETE ISR. */
+#define SCSI_TX_DMA_COMPLETE_INTC_VECTOR ((reg32 *) SCSI_TX_DMA_COMPLETE__INTC_VECT)
+
+/* Address of the SCSI_TX_DMA_COMPLETE ISR priority. */
+#define SCSI_TX_DMA_COMPLETE_INTC_PRIOR ((reg8 *) SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG)
+
+/* Priority of the SCSI_TX_DMA_COMPLETE interrupt. */
+#define SCSI_TX_DMA_COMPLETE_INTC_PRIOR_NUMBER SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM
+
+/* Address of the INTC.SET_EN[x] byte to bit enable SCSI_TX_DMA_COMPLETE interrupt. */
+#define SCSI_TX_DMA_COMPLETE_INTC_SET_EN ((reg32 *) SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG)
+
+/* Address of the INTC.CLR_EN[x] register to bit clear the SCSI_TX_DMA_COMPLETE interrupt. */
+#define SCSI_TX_DMA_COMPLETE_INTC_CLR_EN ((reg32 *) SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG)
+
+/* Address of the INTC.SET_PD[x] register to set the SCSI_TX_DMA_COMPLETE interrupt state to pending. */
+#define SCSI_TX_DMA_COMPLETE_INTC_SET_PD ((reg32 *) SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG)
+
+/* Address of the INTC.CLR_PD[x] register to clear the SCSI_TX_DMA_COMPLETE interrupt. */
+#define SCSI_TX_DMA_COMPLETE_INTC_CLR_PD ((reg32 *) SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG)
+
+
+#endif /* CY_ISR_SCSI_TX_DMA_COMPLETE_H */
+
+
+/* [] END OF FILE */
--- /dev/null
+/***************************************************************************
+* File Name: SCSI_TX_DMA_dma.c
+* Version 1.70
+*
+* Description:
+* Provides an API for the DMAC component. The API includes functions
+* for the DMA controller, DMA channels and Transfer Descriptors.
+*
+*
+* Note:
+* This module requires the developer to finish or fill in the auto
+* generated funcions and setup the dma channel and TD's.
+*
+********************************************************************************
+* Copyright 2008-2010, Cypress Semiconductor Corporation. All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions,
+* disclaimers, and limitations in the end user license agreement accompanying
+* the software package with which this file was provided.
+********************************************************************************/
+#include <CYLIB.H>
+#include <CYDMAC.H>
+#include <SCSI_TX_DMA_dma.H>
+
+
+
+/****************************************************************************
+*
+* The following defines are available in Cyfitter.h
+*
+*
+*
+* SCSI_TX_DMA__DRQ_CTL_REG
+*
+*
+* SCSI_TX_DMA__DRQ_NUMBER
+*
+* Number of TD's used by this channel.
+* SCSI_TX_DMA__NUMBEROF_TDS
+*
+* Priority of this channel.
+* SCSI_TX_DMA__PRIORITY
+*
+* True if SCSI_TX_DMA_TERMIN_SEL is used.
+* SCSI_TX_DMA__TERMIN_EN
+*
+* TERMIN interrupt line to signal terminate.
+* SCSI_TX_DMA__TERMIN_SEL
+*
+*
+* True if SCSI_TX_DMA_TERMOUT0_SEL is used.
+* SCSI_TX_DMA__TERMOUT0_EN
+*
+*
+* TERMOUT0 interrupt line to signal completion.
+* SCSI_TX_DMA__TERMOUT0_SEL
+*
+*
+* True if SCSI_TX_DMA_TERMOUT1_SEL is used.
+* SCSI_TX_DMA__TERMOUT1_EN
+*
+*
+* TERMOUT1 interrupt line to signal completion.
+* SCSI_TX_DMA__TERMOUT1_SEL
+*
+****************************************************************************/
+
+
+/* Zero based index of SCSI_TX_DMA dma channel */
+uint8 SCSI_TX_DMA_DmaHandle = DMA_INVALID_CHANNEL;
+
+/*********************************************************************
+* Function Name: uint8 SCSI_TX_DMA_DmaInitalize
+**********************************************************************
+* Summary:
+* Allocates and initialises a channel of the DMAC to be used by the
+* caller.
+*
+* Parameters:
+* BurstCount.
+*
+*
+* ReqestPerBurst.
+*
+*
+* UpperSrcAddress.
+*
+*
+* UpperDestAddress.
+*
+*
+* Return:
+* The channel that can be used by the caller for DMA activity.
+* DMA_INVALID_CHANNEL (0xFF) if there are no channels left.
+*
+*
+*******************************************************************/
+uint8 SCSI_TX_DMA_DmaInitialize(uint8 BurstCount, uint8 ReqestPerBurst, uint16 UpperSrcAddress, uint16 UpperDestAddress)
+{
+
+ /* Allocate a DMA channel. */
+ SCSI_TX_DMA_DmaHandle = (uint8)SCSI_TX_DMA__DRQ_NUMBER;
+
+ /* Configure the channel. */
+ (void)CyDmaChSetConfiguration(SCSI_TX_DMA_DmaHandle,
+ BurstCount,
+ ReqestPerBurst,
+ (uint8)SCSI_TX_DMA__TERMOUT0_SEL,
+ (uint8)SCSI_TX_DMA__TERMOUT1_SEL,
+ (uint8)SCSI_TX_DMA__TERMIN_SEL);
+
+ /* Set the extended address for the transfers */
+ (void)CyDmaChSetExtendedAddress(SCSI_TX_DMA_DmaHandle, UpperSrcAddress, UpperDestAddress);
+
+ /* Set the priority for this channel */
+ (void)CyDmaChPriority(SCSI_TX_DMA_DmaHandle, (uint8)SCSI_TX_DMA__PRIORITY);
+
+ return SCSI_TX_DMA_DmaHandle;
+}
+
+/*********************************************************************
+* Function Name: void SCSI_TX_DMA_DmaRelease
+**********************************************************************
+* Summary:
+* Frees the channel associated with SCSI_TX_DMA.
+*
+*
+* Parameters:
+* void.
+*
+*
+*
+* Return:
+* void.
+*
+*******************************************************************/
+void SCSI_TX_DMA_DmaRelease(void)
+{
+ /* Disable the channel */
+ (void)CyDmaChDisable(SCSI_TX_DMA_DmaHandle);
+}
+
--- /dev/null
+/******************************************************************************
+* File Name: SCSI_TX_DMA_dma.h
+* Version 1.70
+*
+* Description:
+* Provides the function definitions for the DMA Controller.
+*
+*
+********************************************************************************
+* Copyright 2008-2010, Cypress Semiconductor Corporation. All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions,
+* disclaimers, and limitations in the end user license agreement accompanying
+* the software package with which this file was provided.
+********************************************************************************/
+#if !defined(CY_DMA_SCSI_TX_DMA_DMA_H__)
+#define CY_DMA_SCSI_TX_DMA_DMA_H__
+
+
+
+#include <CYDMAC.H>
+#include <CYFITTER.H>
+
+#define SCSI_TX_DMA__TD_TERMOUT_EN (((0 != SCSI_TX_DMA__TERMOUT0_EN) ? TD_TERMOUT0_EN : 0) | \
+ (SCSI_TX_DMA__TERMOUT1_EN ? TD_TERMOUT1_EN : 0))
+
+/* Zero based index of SCSI_TX_DMA dma channel */
+extern uint8 SCSI_TX_DMA_DmaHandle;
+
+
+uint8 SCSI_TX_DMA_DmaInitialize(uint8 BurstCount, uint8 ReqestPerBurst, uint16 UpperSrcAddress, uint16 UpperDestAddress) ;
+void SCSI_TX_DMA_DmaRelease(void) ;
+
+
+/* CY_DMA_SCSI_TX_DMA_DMA_H__ */
+#endif
\r
#define SDCard_INT_ON_SPI_DONE ((uint8) (0u << SDCard_STS_SPI_DONE_SHIFT))\r
#define SDCard_INT_ON_TX_EMPTY ((uint8) (0u << SDCard_STS_TX_FIFO_EMPTY_SHIFT))\r
-#define SDCard_INT_ON_TX_NOT_FULL ((uint8) (0u << \\r
+#define SDCard_INT_ON_TX_NOT_FULL ((uint8) (1u << \\r
SDCard_STS_TX_FIFO_NOT_FULL_SHIFT))\r
#define SDCard_INT_ON_BYTE_COMP ((uint8) (0u << SDCard_STS_BYTE_COMPLETE_SHIFT))\r
#define SDCard_INT_ON_SPI_IDLE ((uint8) (0u << SDCard_STS_SPI_IDLE_SHIFT))\r
\r
#define SDCard_INT_ON_RX_FULL ((uint8) (0u << \\r
SDCard_STS_RX_FIFO_FULL_SHIFT))\r
-#define SDCard_INT_ON_RX_NOT_EMPTY ((uint8) (0u << \\r
+#define SDCard_INT_ON_RX_NOT_EMPTY ((uint8) (1u << \\r
SDCard_STS_RX_FIFO_NOT_EMPTY_SHIFT))\r
#define SDCard_INT_ON_RX_OVER ((uint8) (0u << \\r
SDCard_STS_RX_FIFO_OVERRUN_SHIFT))\r
+++ /dev/null
-/*******************************************************************************\r
-* File Name: SD_Clk_Ctl.c \r
-* Version 1.70\r
-*\r
-* Description:\r
-* This file contains API to enable firmware control of a Control Register.\r
-*\r
-* Note:\r
-*\r
-********************************************************************************\r
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.\r
-* You may use this file only in accordance with the license, terms, conditions, \r
-* disclaimers, and limitations in the end user license agreement accompanying \r
-* the software package with which this file was provided.\r
-*******************************************************************************/\r
-\r
-#include "SD_Clk_Ctl.h"\r
-\r
-#if !defined(SD_Clk_Ctl_Sync_ctrl_reg__REMOVED) /* Check for removal by optimization */\r
-\r
-/*******************************************************************************\r
-* Function Name: SD_Clk_Ctl_Write\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* Write a byte to the Control Register.\r
-*\r
-* Parameters:\r
-* control: The value to be assigned to the Control Register.\r
-*\r
-* Return:\r
-* None.\r
-*\r
-*******************************************************************************/\r
-void SD_Clk_Ctl_Write(uint8 control) \r
-{\r
- SD_Clk_Ctl_Control = control;\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: SD_Clk_Ctl_Read\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* Reads the current value assigned to the Control Register.\r
-*\r
-* Parameters:\r
-* None.\r
-*\r
-* Return:\r
-* Returns the current value in the Control Register.\r
-*\r
-*******************************************************************************/\r
-uint8 SD_Clk_Ctl_Read(void) \r
-{\r
- return SD_Clk_Ctl_Control;\r
-}\r
-\r
-#endif /* End check for removal by optimization */\r
-\r
-\r
-/* [] END OF FILE */\r
+++ /dev/null
-/*******************************************************************************\r
-* File Name: SD_Clk_Ctl.h \r
-* Version 1.70\r
-*\r
-* Description:\r
-* This file containts Control Register function prototypes and register defines\r
-*\r
-* Note:\r
-*\r
-********************************************************************************\r
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.\r
-* You may use this file only in accordance with the license, terms, conditions, \r
-* disclaimers, and limitations in the end user license agreement accompanying \r
-* the software package with which this file was provided.\r
-*******************************************************************************/\r
-\r
-#if !defined(CY_CONTROL_REG_SD_Clk_Ctl_H) /* CY_CONTROL_REG_SD_Clk_Ctl_H */\r
-#define CY_CONTROL_REG_SD_Clk_Ctl_H\r
-\r
-#include "cytypes.h"\r
-\r
-\r
-/***************************************\r
-* Function Prototypes \r
-***************************************/\r
-\r
-void SD_Clk_Ctl_Write(uint8 control) ;\r
-uint8 SD_Clk_Ctl_Read(void) ;\r
-\r
-\r
-/***************************************\r
-* Registers \r
-***************************************/\r
-\r
-/* Control Register */\r
-#define SD_Clk_Ctl_Control (* (reg8 *) SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG )\r
-#define SD_Clk_Ctl_Control_PTR ( (reg8 *) SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG )\r
-\r
-#endif /* End CY_CONTROL_REG_SD_Clk_Ctl_H */\r
-\r
-\r
-/* [] END OF FILE */\r
+++ /dev/null
-/*******************************************************************************\r
-* File Name: SD_Init_Clk.c\r
-* Version 2.10\r
-*\r
-* Description:\r
-* This file provides the source code to the API for the clock component.\r
-*\r
-* Note:\r
-*\r
-********************************************************************************\r
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.\r
-* You may use this file only in accordance with the license, terms, conditions, \r
-* disclaimers, and limitations in the end user license agreement accompanying \r
-* the software package with which this file was provided.\r
-*******************************************************************************/\r
-\r
-#include <cydevice_trm.h>\r
-#include "SD_Init_Clk.h"\r
-\r
-/* Clock Distribution registers. */\r
-#define CLK_DIST_LD (* (reg8 *) CYREG_CLKDIST_LD)\r
-#define CLK_DIST_BCFG2 (* (reg8 *) CYREG_CLKDIST_BCFG2)\r
-#define BCFG2_MASK (0x80u)\r
-#define CLK_DIST_DMASK (* (reg8 *) CYREG_CLKDIST_DMASK)\r
-#define CLK_DIST_AMASK (* (reg8 *) CYREG_CLKDIST_AMASK)\r
-\r
-#define HAS_CLKDIST_LD_DISABLE (CY_PSOC3 || CY_PSOC5LP)\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: SD_Init_Clk_Start\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* Starts the clock. Note that on startup, clocks may be already running if the\r
-* "Start on Reset" option is enabled in the DWR.\r
-*\r
-* Parameters:\r
-* None\r
-*\r
-* Returns:\r
-* None\r
-*\r
-*******************************************************************************/\r
-void SD_Init_Clk_Start(void) \r
-{\r
- /* Set the bit to enable the clock. */\r
- SD_Init_Clk_CLKEN |= SD_Init_Clk_CLKEN_MASK;\r
- SD_Init_Clk_CLKSTBY |= SD_Init_Clk_CLKSTBY_MASK;\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: SD_Init_Clk_Stop\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* Stops the clock and returns immediately. This API does not require the\r
-* source clock to be running but may return before the hardware is actually\r
-* disabled. If the settings of the clock are changed after calling this\r
-* function, the clock may glitch when it is started. To avoid the clock\r
-* glitch, use the StopBlock function.\r
-*\r
-* Parameters:\r
-* None\r
-*\r
-* Returns:\r
-* None\r
-*\r
-*******************************************************************************/\r
-void SD_Init_Clk_Stop(void) \r
-{\r
- /* Clear the bit to disable the clock. */\r
- SD_Init_Clk_CLKEN &= (uint8)(~SD_Init_Clk_CLKEN_MASK);\r
- SD_Init_Clk_CLKSTBY &= (uint8)(~SD_Init_Clk_CLKSTBY_MASK);\r
-}\r
-\r
-\r
-#if(CY_PSOC3 || CY_PSOC5LP)\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: SD_Init_Clk_StopBlock\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* Stops the clock and waits for the hardware to actually be disabled before\r
-* returning. This ensures that the clock is never truncated (high part of the\r
-* cycle will terminate before the clock is disabled and the API returns).\r
-* Note that the source clock must be running or this API will never return as\r
-* a stopped clock cannot be disabled.\r
-*\r
-* Parameters:\r
-* None\r
-*\r
-* Returns:\r
-* None\r
-*\r
-*******************************************************************************/\r
-void SD_Init_Clk_StopBlock(void) \r
-{\r
- if ((SD_Init_Clk_CLKEN & SD_Init_Clk_CLKEN_MASK) != 0u)\r
- {\r
-#if HAS_CLKDIST_LD_DISABLE\r
- uint16 oldDivider;\r
-\r
- CLK_DIST_LD = 0u;\r
-\r
- /* Clear all the mask bits except ours. */\r
-#if defined(SD_Init_Clk__CFG3)\r
- CLK_DIST_AMASK = SD_Init_Clk_CLKEN_MASK;\r
- CLK_DIST_DMASK = 0x00u;\r
-#else\r
- CLK_DIST_DMASK = SD_Init_Clk_CLKEN_MASK;\r
- CLK_DIST_AMASK = 0x00u;\r
-#endif /* SD_Init_Clk__CFG3 */\r
-\r
- /* Clear mask of bus clock. */\r
- CLK_DIST_BCFG2 &= (uint8)(~BCFG2_MASK);\r
-\r
- oldDivider = CY_GET_REG16(SD_Init_Clk_DIV_PTR);\r
- CY_SET_REG16(CYREG_CLKDIST_WRK0, oldDivider);\r
- CLK_DIST_LD = CYCLK_LD_DISABLE | CYCLK_LD_SYNC_EN | CYCLK_LD_LOAD;\r
-\r
- /* Wait for clock to be disabled */\r
- while ((CLK_DIST_LD & CYCLK_LD_LOAD) != 0u) { }\r
-#endif /* HAS_CLKDIST_LD_DISABLE */\r
-\r
- /* Clear the bit to disable the clock. */\r
- SD_Init_Clk_CLKEN &= (uint8)(~SD_Init_Clk_CLKEN_MASK);\r
- SD_Init_Clk_CLKSTBY &= (uint8)(~SD_Init_Clk_CLKSTBY_MASK);\r
-\r
-#if HAS_CLKDIST_LD_DISABLE\r
- /* Clear the disable bit */\r
- CLK_DIST_LD = 0x00u;\r
- CY_SET_REG16(SD_Init_Clk_DIV_PTR, oldDivider);\r
-#endif /* HAS_CLKDIST_LD_DISABLE */\r
- }\r
-}\r
-#endif /* (CY_PSOC3 || CY_PSOC5LP) */\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: SD_Init_Clk_StandbyPower\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* Sets whether the clock is active in standby mode.\r
-*\r
-* Parameters:\r
-* state: 0 to disable clock during standby, nonzero to enable.\r
-*\r
-* Returns:\r
-* None\r
-*\r
-*******************************************************************************/\r
-void SD_Init_Clk_StandbyPower(uint8 state) \r
-{\r
- if(state == 0u)\r
- {\r
- SD_Init_Clk_CLKSTBY &= (uint8)(~SD_Init_Clk_CLKSTBY_MASK);\r
- }\r
- else\r
- {\r
- SD_Init_Clk_CLKSTBY |= SD_Init_Clk_CLKSTBY_MASK;\r
- }\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: SD_Init_Clk_SetDividerRegister\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* Modifies the clock divider and, thus, the frequency. When the clock divider\r
-* register is set to zero or changed from zero, the clock will be temporarily\r
-* disabled in order to change the SSS mode bit. If the clock is enabled when\r
-* SetDividerRegister is called, then the source clock must be running.\r
-*\r
-* Parameters:\r
-* clkDivider: Divider register value (0-65,535). This value is NOT the\r
-* divider; the clock hardware divides by clkDivider plus one. For example,\r
-* to divide the clock by 2, this parameter should be set to 1.\r
-* restart: If nonzero, restarts the clock divider: the current clock cycle\r
-* will be truncated and the new divide value will take effect immediately. If\r
-* zero, the new divide value will take effect at the end of the current clock\r
-* cycle.\r
-*\r
-* Returns:\r
-* None\r
-*\r
-*******************************************************************************/\r
-void SD_Init_Clk_SetDividerRegister(uint16 clkDivider, uint8 restart)\r
- \r
-{\r
- uint8 enabled;\r
-\r
- uint8 currSrc = SD_Init_Clk_GetSourceRegister();\r
- uint16 oldDivider = SD_Init_Clk_GetDividerRegister();\r
-\r
- if (clkDivider != oldDivider)\r
- {\r
- enabled = SD_Init_Clk_CLKEN & SD_Init_Clk_CLKEN_MASK;\r
-\r
- if ((currSrc == (uint8)CYCLK_SRC_SEL_CLK_SYNC_D) && ((oldDivider == 0u) || (clkDivider == 0u)))\r
- {\r
- /* Moving to/from SSS requires correct ordering to prevent halting the clock */\r
- if (oldDivider == 0u)\r
- {\r
- /* Moving away from SSS, set the divider first so when SSS is cleared we */\r
- /* don't halt the clock. Using the shadow load isn't required as the */\r
- /* divider is ignored while SSS is set. */\r
- CY_SET_REG16(SD_Init_Clk_DIV_PTR, clkDivider);\r
- SD_Init_Clk_MOD_SRC &= (uint8)(~CYCLK_SSS);\r
- }\r
- else\r
- {\r
- /* Moving to SSS, set SSS which then ignores the divider and we can set */\r
- /* it without bothering with the shadow load. */\r
- SD_Init_Clk_MOD_SRC |= CYCLK_SSS;\r
- CY_SET_REG16(SD_Init_Clk_DIV_PTR, clkDivider);\r
- }\r
- }\r
- else\r
- {\r
- \r
- if (enabled != 0u)\r
- {\r
- CLK_DIST_LD = 0x00u;\r
-\r
- /* Clear all the mask bits except ours. */\r
-#if defined(SD_Init_Clk__CFG3)\r
- CLK_DIST_AMASK = SD_Init_Clk_CLKEN_MASK;\r
- CLK_DIST_DMASK = 0x00u;\r
-#else\r
- CLK_DIST_DMASK = SD_Init_Clk_CLKEN_MASK;\r
- CLK_DIST_AMASK = 0x00u;\r
-#endif /* SD_Init_Clk__CFG3 */\r
- /* Clear mask of bus clock. */\r
- CLK_DIST_BCFG2 &= (uint8)(~BCFG2_MASK);\r
-\r
- /* If clock is currently enabled, disable it if async or going from N-to-1*/\r
- if (((SD_Init_Clk_MOD_SRC & CYCLK_SYNC) == 0u) || (clkDivider == 0u))\r
- {\r
-#if HAS_CLKDIST_LD_DISABLE\r
- CY_SET_REG16(CYREG_CLKDIST_WRK0, oldDivider);\r
- CLK_DIST_LD = CYCLK_LD_DISABLE|CYCLK_LD_SYNC_EN|CYCLK_LD_LOAD;\r
-\r
- /* Wait for clock to be disabled */\r
- while ((CLK_DIST_LD & CYCLK_LD_LOAD) != 0u) { }\r
-#endif /* HAS_CLKDIST_LD_DISABLE */\r
-\r
- SD_Init_Clk_CLKEN &= (uint8)(~SD_Init_Clk_CLKEN_MASK);\r
-\r
-#if HAS_CLKDIST_LD_DISABLE\r
- /* Clear the disable bit */\r
- CLK_DIST_LD = 0x00u;\r
-#endif /* HAS_CLKDIST_LD_DISABLE */\r
- }\r
- }\r
-\r
- /* Load divide value. */\r
- if ((SD_Init_Clk_CLKEN & SD_Init_Clk_CLKEN_MASK) != 0u)\r
- {\r
- /* If the clock is still enabled, use the shadow registers */\r
- CY_SET_REG16(CYREG_CLKDIST_WRK0, clkDivider);\r
-\r
- CLK_DIST_LD = (CYCLK_LD_LOAD | ((restart != 0u) ? CYCLK_LD_SYNC_EN : 0x00u));\r
- while ((CLK_DIST_LD & CYCLK_LD_LOAD) != 0u) { }\r
- }\r
- else\r
- {\r
- /* If the clock is disabled, set the divider directly */\r
- CY_SET_REG16(SD_Init_Clk_DIV_PTR, clkDivider);\r
- SD_Init_Clk_CLKEN |= enabled;\r
- }\r
- }\r
- }\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: SD_Init_Clk_GetDividerRegister\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* Gets the clock divider register value.\r
-*\r
-* Parameters:\r
-* None\r
-*\r
-* Returns:\r
-* Divide value of the clock minus 1. For example, if the clock is set to\r
-* divide by 2, the return value will be 1.\r
-*\r
-*******************************************************************************/\r
-uint16 SD_Init_Clk_GetDividerRegister(void) \r
-{\r
- return CY_GET_REG16(SD_Init_Clk_DIV_PTR);\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: SD_Init_Clk_SetModeRegister\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* Sets flags that control the operating mode of the clock. This function only\r
-* changes flags from 0 to 1; flags that are already 1 will remain unchanged.\r
-* To clear flags, use the ClearModeRegister function. The clock must be\r
-* disabled before changing the mode.\r
-*\r
-* Parameters:\r
-* clkMode: Bit mask containing the bits to set. For PSoC 3 and PSoC 5,\r
-* clkMode should be a set of the following optional bits or'ed together.\r
-* - CYCLK_EARLY Enable early phase mode. Rising edge of output clock will\r
-* occur when the divider count reaches half of the divide\r
-* value.\r
-* - CYCLK_DUTY Enable 50% duty cycle output. When enabled, the output clock\r
-* is asserted for approximately half of its period. When\r
-* disabled, the output clock is asserted for one period of the\r
-* source clock.\r
-* - CYCLK_SYNC Enable output synchronization to master clock. This should\r
-* be enabled for all synchronous clocks.\r
-* See the Technical Reference Manual for details about setting the mode of\r
-* the clock. Specifically, see the CLKDIST.DCFG.CFG2 register.\r
-*\r
-* Returns:\r
-* None\r
-*\r
-*******************************************************************************/\r
-void SD_Init_Clk_SetModeRegister(uint8 modeBitMask) \r
-{\r
- SD_Init_Clk_MOD_SRC |= modeBitMask & (uint8)SD_Init_Clk_MODE_MASK;\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: SD_Init_Clk_ClearModeRegister\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* Clears flags that control the operating mode of the clock. This function\r
-* only changes flags from 1 to 0; flags that are already 0 will remain\r
-* unchanged. To set flags, use the SetModeRegister function. The clock must be\r
-* disabled before changing the mode.\r
-*\r
-* Parameters:\r
-* clkMode: Bit mask containing the bits to clear. For PSoC 3 and PSoC 5,\r
-* clkMode should be a set of the following optional bits or'ed together.\r
-* - CYCLK_EARLY Enable early phase mode. Rising edge of output clock will\r
-* occur when the divider count reaches half of the divide\r
-* value.\r
-* - CYCLK_DUTY Enable 50% duty cycle output. When enabled, the output clock\r
-* is asserted for approximately half of its period. When\r
-* disabled, the output clock is asserted for one period of the\r
-* source clock.\r
-* - CYCLK_SYNC Enable output synchronization to master clock. This should\r
-* be enabled for all synchronous clocks.\r
-* See the Technical Reference Manual for details about setting the mode of\r
-* the clock. Specifically, see the CLKDIST.DCFG.CFG2 register.\r
-*\r
-* Returns:\r
-* None\r
-*\r
-*******************************************************************************/\r
-void SD_Init_Clk_ClearModeRegister(uint8 modeBitMask) \r
-{\r
- SD_Init_Clk_MOD_SRC &= (uint8)(~modeBitMask) | (uint8)(~(uint8)(SD_Init_Clk_MODE_MASK));\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: SD_Init_Clk_GetModeRegister\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* Gets the clock mode register value.\r
-*\r
-* Parameters:\r
-* None\r
-*\r
-* Returns:\r
-* Bit mask representing the enabled mode bits. See the SetModeRegister and\r
-* ClearModeRegister descriptions for details about the mode bits.\r
-*\r
-*******************************************************************************/\r
-uint8 SD_Init_Clk_GetModeRegister(void) \r
-{\r
- return SD_Init_Clk_MOD_SRC & (uint8)(SD_Init_Clk_MODE_MASK);\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: SD_Init_Clk_SetSourceRegister\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* Sets the input source of the clock. The clock must be disabled before\r
-* changing the source. The old and new clock sources must be running.\r
-*\r
-* Parameters:\r
-* clkSource: For PSoC 3 and PSoC 5 devices, clkSource should be one of the\r
-* following input sources:\r
-* - CYCLK_SRC_SEL_SYNC_DIG\r
-* - CYCLK_SRC_SEL_IMO\r
-* - CYCLK_SRC_SEL_XTALM\r
-* - CYCLK_SRC_SEL_ILO\r
-* - CYCLK_SRC_SEL_PLL\r
-* - CYCLK_SRC_SEL_XTALK\r
-* - CYCLK_SRC_SEL_DSI_G\r
-* - CYCLK_SRC_SEL_DSI_D/CYCLK_SRC_SEL_DSI_A\r
-* See the Technical Reference Manual for details on clock sources.\r
-*\r
-* Returns:\r
-* None\r
-*\r
-*******************************************************************************/\r
-void SD_Init_Clk_SetSourceRegister(uint8 clkSource) \r
-{\r
- uint16 currDiv = SD_Init_Clk_GetDividerRegister();\r
- uint8 oldSrc = SD_Init_Clk_GetSourceRegister();\r
-\r
- if (((oldSrc != ((uint8)CYCLK_SRC_SEL_CLK_SYNC_D)) && \r
- (clkSource == ((uint8)CYCLK_SRC_SEL_CLK_SYNC_D))) && (currDiv == 0u))\r
- {\r
- /* Switching to Master and divider is 1, set SSS, which will output master, */\r
- /* then set the source so we are consistent. */\r
- SD_Init_Clk_MOD_SRC |= CYCLK_SSS;\r
- SD_Init_Clk_MOD_SRC =\r
- (SD_Init_Clk_MOD_SRC & (uint8)(~SD_Init_Clk_SRC_SEL_MSK)) | clkSource;\r
- }\r
- else if (((oldSrc == ((uint8)CYCLK_SRC_SEL_CLK_SYNC_D)) && \r
- (clkSource != ((uint8)CYCLK_SRC_SEL_CLK_SYNC_D))) && (currDiv == 0u))\r
- {\r
- /* Switching from Master to not and divider is 1, set source, so we don't */\r
- /* lock when we clear SSS. */\r
- SD_Init_Clk_MOD_SRC =\r
- (SD_Init_Clk_MOD_SRC & (uint8)(~SD_Init_Clk_SRC_SEL_MSK)) | clkSource;\r
- SD_Init_Clk_MOD_SRC &= (uint8)(~CYCLK_SSS);\r
- }\r
- else\r
- {\r
- SD_Init_Clk_MOD_SRC =\r
- (SD_Init_Clk_MOD_SRC & (uint8)(~SD_Init_Clk_SRC_SEL_MSK)) | clkSource;\r
- }\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: SD_Init_Clk_GetSourceRegister\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* Gets the input source of the clock.\r
-*\r
-* Parameters:\r
-* None\r
-*\r
-* Returns:\r
-* The input source of the clock. See SetSourceRegister for details.\r
-*\r
-*******************************************************************************/\r
-uint8 SD_Init_Clk_GetSourceRegister(void) \r
-{\r
- return SD_Init_Clk_MOD_SRC & SD_Init_Clk_SRC_SEL_MSK;\r
-}\r
-\r
-\r
-#if defined(SD_Init_Clk__CFG3)\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: SD_Init_Clk_SetPhaseRegister\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* Sets the phase delay of the analog clock. This function is only available\r
-* for analog clocks. The clock must be disabled before changing the phase\r
-* delay to avoid glitches.\r
-*\r
-* Parameters:\r
-* clkPhase: Amount to delay the phase of the clock, in 1.0ns increments.\r
-* clkPhase must be from 1 to 11 inclusive. Other values, including 0,\r
-* disable the clock. clkPhase = 1 produces a 0ns delay and clkPhase = 11 \r
-* produces a 10ns delay.\r
-*\r
-* Returns:\r
-* None\r
-*\r
-*******************************************************************************/\r
-void SD_Init_Clk_SetPhaseRegister(uint8 clkPhase) \r
-{\r
- SD_Init_Clk_PHASE = clkPhase & SD_Init_Clk_PHASE_MASK;\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: SD_Init_Clk_GetPhase\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* Gets the phase delay of the analog clock. This function is only available\r
-* for analog clocks.\r
-*\r
-* Parameters:\r
-* None\r
-*\r
-* Returns:\r
-* Phase of the analog clock. See SetPhaseRegister for details.\r
-*\r
-*******************************************************************************/\r
-uint8 SD_Init_Clk_GetPhaseRegister(void) \r
-{\r
- return SD_Init_Clk_PHASE & SD_Init_Clk_PHASE_MASK;\r
-}\r
-\r
-#endif /* SD_Init_Clk__CFG3 */\r
-\r
-\r
-/* [] END OF FILE */\r
+++ /dev/null
-/*******************************************************************************\r
-* File Name: SD_Init_Clk.h\r
-* Version 2.10\r
-*\r
-* Description:\r
-* Provides the function and constant definitions for the clock component.\r
-*\r
-* Note:\r
-*\r
-********************************************************************************\r
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.\r
-* You may use this file only in accordance with the license, terms, conditions, \r
-* disclaimers, and limitations in the end user license agreement accompanying \r
-* the software package with which this file was provided.\r
-*******************************************************************************/\r
-\r
-#if !defined(CY_CLOCK_SD_Init_Clk_H)\r
-#define CY_CLOCK_SD_Init_Clk_H\r
-\r
-#include <cytypes.h>\r
-#include <cyfitter.h>\r
-\r
-\r
-/***************************************\r
-* Conditional Compilation Parameters\r
-***************************************/\r
-\r
-/* Check to see if required defines such as CY_PSOC5LP are available */\r
-/* They are defined starting with cy_boot v3.0 */\r
-#if !defined (CY_PSOC5LP)\r
- #error Component cy_clock_v2_10 requires cy_boot v3.0 or later\r
-#endif /* (CY_PSOC5LP) */\r
-\r
-\r
-/***************************************\r
-* Function Prototypes\r
-***************************************/\r
-\r
-void SD_Init_Clk_Start(void) ;\r
-void SD_Init_Clk_Stop(void) ;\r
-\r
-#if(CY_PSOC3 || CY_PSOC5LP)\r
-void SD_Init_Clk_StopBlock(void) ;\r
-#endif /* (CY_PSOC3 || CY_PSOC5LP) */\r
-\r
-void SD_Init_Clk_StandbyPower(uint8 state) ;\r
-void SD_Init_Clk_SetDividerRegister(uint16 clkDivider, uint8 restart) \r
- ;\r
-uint16 SD_Init_Clk_GetDividerRegister(void) ;\r
-void SD_Init_Clk_SetModeRegister(uint8 modeBitMask) ;\r
-void SD_Init_Clk_ClearModeRegister(uint8 modeBitMask) ;\r
-uint8 SD_Init_Clk_GetModeRegister(void) ;\r
-void SD_Init_Clk_SetSourceRegister(uint8 clkSource) ;\r
-uint8 SD_Init_Clk_GetSourceRegister(void) ;\r
-#if defined(SD_Init_Clk__CFG3)\r
-void SD_Init_Clk_SetPhaseRegister(uint8 clkPhase) ;\r
-uint8 SD_Init_Clk_GetPhaseRegister(void) ;\r
-#endif /* defined(SD_Init_Clk__CFG3) */\r
-\r
-#define SD_Init_Clk_Enable() SD_Init_Clk_Start()\r
-#define SD_Init_Clk_Disable() SD_Init_Clk_Stop()\r
-#define SD_Init_Clk_SetDivider(clkDivider) SD_Init_Clk_SetDividerRegister(clkDivider, 1u)\r
-#define SD_Init_Clk_SetDividerValue(clkDivider) SD_Init_Clk_SetDividerRegister((clkDivider) - 1u, 1u)\r
-#define SD_Init_Clk_SetMode(clkMode) SD_Init_Clk_SetModeRegister(clkMode)\r
-#define SD_Init_Clk_SetSource(clkSource) SD_Init_Clk_SetSourceRegister(clkSource)\r
-#if defined(SD_Init_Clk__CFG3)\r
-#define SD_Init_Clk_SetPhase(clkPhase) SD_Init_Clk_SetPhaseRegister(clkPhase)\r
-#define SD_Init_Clk_SetPhaseValue(clkPhase) SD_Init_Clk_SetPhaseRegister((clkPhase) + 1u)\r
-#endif /* defined(SD_Init_Clk__CFG3) */\r
-\r
-\r
-/***************************************\r
-* Registers\r
-***************************************/\r
-\r
-/* Register to enable or disable the clock */\r
-#define SD_Init_Clk_CLKEN (* (reg8 *) SD_Init_Clk__PM_ACT_CFG)\r
-#define SD_Init_Clk_CLKEN_PTR ((reg8 *) SD_Init_Clk__PM_ACT_CFG)\r
-\r
-/* Register to enable or disable the clock */\r
-#define SD_Init_Clk_CLKSTBY (* (reg8 *) SD_Init_Clk__PM_STBY_CFG)\r
-#define SD_Init_Clk_CLKSTBY_PTR ((reg8 *) SD_Init_Clk__PM_STBY_CFG)\r
-\r
-/* Clock LSB divider configuration register. */\r
-#define SD_Init_Clk_DIV_LSB (* (reg8 *) SD_Init_Clk__CFG0)\r
-#define SD_Init_Clk_DIV_LSB_PTR ((reg8 *) SD_Init_Clk__CFG0)\r
-#define SD_Init_Clk_DIV_PTR ((reg16 *) SD_Init_Clk__CFG0)\r
-\r
-/* Clock MSB divider configuration register. */\r
-#define SD_Init_Clk_DIV_MSB (* (reg8 *) SD_Init_Clk__CFG1)\r
-#define SD_Init_Clk_DIV_MSB_PTR ((reg8 *) SD_Init_Clk__CFG1)\r
-\r
-/* Mode and source configuration register */\r
-#define SD_Init_Clk_MOD_SRC (* (reg8 *) SD_Init_Clk__CFG2)\r
-#define SD_Init_Clk_MOD_SRC_PTR ((reg8 *) SD_Init_Clk__CFG2)\r
-\r
-#if defined(SD_Init_Clk__CFG3)\r
-/* Analog clock phase configuration register */\r
-#define SD_Init_Clk_PHASE (* (reg8 *) SD_Init_Clk__CFG3)\r
-#define SD_Init_Clk_PHASE_PTR ((reg8 *) SD_Init_Clk__CFG3)\r
-#endif /* defined(SD_Init_Clk__CFG3) */\r
-\r
-\r
-/**************************************\r
-* Register Constants\r
-**************************************/\r
-\r
-/* Power manager register masks */\r
-#define SD_Init_Clk_CLKEN_MASK SD_Init_Clk__PM_ACT_MSK\r
-#define SD_Init_Clk_CLKSTBY_MASK SD_Init_Clk__PM_STBY_MSK\r
-\r
-/* CFG2 field masks */\r
-#define SD_Init_Clk_SRC_SEL_MSK SD_Init_Clk__CFG2_SRC_SEL_MASK\r
-#define SD_Init_Clk_MODE_MASK (~(SD_Init_Clk_SRC_SEL_MSK))\r
-\r
-#if defined(SD_Init_Clk__CFG3)\r
-/* CFG3 phase mask */\r
-#define SD_Init_Clk_PHASE_MASK SD_Init_Clk__CFG3_PHASE_DLY_MASK\r
-#endif /* defined(SD_Init_Clk__CFG3) */\r
-\r
-#endif /* CY_CLOCK_SD_Init_Clk_H */\r
-\r
-\r
-/* [] END OF FILE */\r
--- /dev/null
+/*******************************************************************************
+* File Name: SD_RX_DMA_COMPLETE.c
+* Version 1.70
+*
+* Description:
+* API for controlling the state of an interrupt.
+*
+*
+* Note:
+*
+********************************************************************************
+* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions,
+* disclaimers, and limitations in the end user license agreement accompanying
+* the software package with which this file was provided.
+*******************************************************************************/
+
+
+#include <cydevice_trm.h>
+#include <CyLib.h>
+#include <SD_RX_DMA_COMPLETE.h>
+
+#if !defined(SD_RX_DMA_COMPLETE__REMOVED) /* Check for removal by optimization */
+
+/*******************************************************************************
+* Place your includes, defines and code here
+********************************************************************************/
+/* `#START SD_RX_DMA_COMPLETE_intc` */
+
+/* `#END` */
+
+#ifndef CYINT_IRQ_BASE
+#define CYINT_IRQ_BASE 16
+#endif /* CYINT_IRQ_BASE */
+#ifndef CYINT_VECT_TABLE
+#define CYINT_VECT_TABLE ((cyisraddress **) CYREG_NVIC_VECT_OFFSET)
+#endif /* CYINT_VECT_TABLE */
+
+/* Declared in startup, used to set unused interrupts to. */
+CY_ISR_PROTO(IntDefaultHandler);
+
+
+/*******************************************************************************
+* Function Name: SD_RX_DMA_COMPLETE_Start
+********************************************************************************
+*
+* Summary:
+* Set up the interrupt and enable it.
+*
+* Parameters:
+* None
+*
+* Return:
+* None
+*
+*******************************************************************************/
+void SD_RX_DMA_COMPLETE_Start(void)
+{
+ /* For all we know the interrupt is active. */
+ SD_RX_DMA_COMPLETE_Disable();
+
+ /* Set the ISR to point to the SD_RX_DMA_COMPLETE Interrupt. */
+ SD_RX_DMA_COMPLETE_SetVector(&SD_RX_DMA_COMPLETE_Interrupt);
+
+ /* Set the priority. */
+ SD_RX_DMA_COMPLETE_SetPriority((uint8)SD_RX_DMA_COMPLETE_INTC_PRIOR_NUMBER);
+
+ /* Enable it. */
+ SD_RX_DMA_COMPLETE_Enable();
+}
+
+
+/*******************************************************************************
+* Function Name: SD_RX_DMA_COMPLETE_StartEx
+********************************************************************************
+*
+* Summary:
+* Set up the interrupt and enable it.
+*
+* Parameters:
+* address: Address of the ISR to set in the interrupt vector table.
+*
+* Return:
+* None
+*
+*******************************************************************************/
+void SD_RX_DMA_COMPLETE_StartEx(cyisraddress address)
+{
+ /* For all we know the interrupt is active. */
+ SD_RX_DMA_COMPLETE_Disable();
+
+ /* Set the ISR to point to the SD_RX_DMA_COMPLETE Interrupt. */
+ SD_RX_DMA_COMPLETE_SetVector(address);
+
+ /* Set the priority. */
+ SD_RX_DMA_COMPLETE_SetPriority((uint8)SD_RX_DMA_COMPLETE_INTC_PRIOR_NUMBER);
+
+ /* Enable it. */
+ SD_RX_DMA_COMPLETE_Enable();
+}
+
+
+/*******************************************************************************
+* Function Name: SD_RX_DMA_COMPLETE_Stop
+********************************************************************************
+*
+* Summary:
+* Disables and removes the interrupt.
+*
+* Parameters:
+*
+* Return:
+* None
+*
+*******************************************************************************/
+void SD_RX_DMA_COMPLETE_Stop(void)
+{
+ /* Disable this interrupt. */
+ SD_RX_DMA_COMPLETE_Disable();
+
+ /* Set the ISR to point to the passive one. */
+ SD_RX_DMA_COMPLETE_SetVector(&IntDefaultHandler);
+}
+
+
+/*******************************************************************************
+* Function Name: SD_RX_DMA_COMPLETE_Interrupt
+********************************************************************************
+*
+* Summary:
+* The default Interrupt Service Routine for SD_RX_DMA_COMPLETE.
+*
+* Add custom code between the coments to keep the next version of this file
+* from over writting your code.
+*
+* Parameters:
+*
+* Return:
+* None
+*
+*******************************************************************************/
+CY_ISR(SD_RX_DMA_COMPLETE_Interrupt)
+{
+ /* Place your Interrupt code here. */
+ /* `#START SD_RX_DMA_COMPLETE_Interrupt` */
+
+ /* `#END` */
+}
+
+
+/*******************************************************************************
+* Function Name: SD_RX_DMA_COMPLETE_SetVector
+********************************************************************************
+*
+* Summary:
+* Change the ISR vector for the Interrupt. Note calling SD_RX_DMA_COMPLETE_Start
+* will override any effect this method would have had. To set the vector
+* before the component has been started use SD_RX_DMA_COMPLETE_StartEx instead.
+*
+* Parameters:
+* address: Address of the ISR to set in the interrupt vector table.
+*
+* Return:
+* None
+*
+*******************************************************************************/
+void SD_RX_DMA_COMPLETE_SetVector(cyisraddress address)
+{
+ cyisraddress * ramVectorTable;
+
+ ramVectorTable = (cyisraddress *) *CYINT_VECT_TABLE;
+
+ ramVectorTable[CYINT_IRQ_BASE + (uint32)SD_RX_DMA_COMPLETE__INTC_NUMBER] = address;
+}
+
+
+/*******************************************************************************
+* Function Name: SD_RX_DMA_COMPLETE_GetVector
+********************************************************************************
+*
+* Summary:
+* Gets the "address" of the current ISR vector for the Interrupt.
+*
+* Parameters:
+* None
+*
+* Return:
+* Address of the ISR in the interrupt vector table.
+*
+*******************************************************************************/
+cyisraddress SD_RX_DMA_COMPLETE_GetVector(void)
+{
+ cyisraddress * ramVectorTable;
+
+ ramVectorTable = (cyisraddress *) *CYINT_VECT_TABLE;
+
+ return ramVectorTable[CYINT_IRQ_BASE + (uint32)SD_RX_DMA_COMPLETE__INTC_NUMBER];
+}
+
+
+/*******************************************************************************
+* Function Name: SD_RX_DMA_COMPLETE_SetPriority
+********************************************************************************
+*
+* Summary:
+* Sets the Priority of the Interrupt. Note calling SD_RX_DMA_COMPLETE_Start
+* or SD_RX_DMA_COMPLETE_StartEx will override any effect this method
+* would have had. This method should only be called after
+* SD_RX_DMA_COMPLETE_Start or SD_RX_DMA_COMPLETE_StartEx has been called. To set
+* the initial priority for the component use the cydwr file in the tool.
+*
+* Parameters:
+* priority: Priority of the interrupt. 0 - 7, 0 being the highest.
+*
+* Return:
+* None
+*
+*******************************************************************************/
+void SD_RX_DMA_COMPLETE_SetPriority(uint8 priority)
+{
+ *SD_RX_DMA_COMPLETE_INTC_PRIOR = priority << 5;
+}
+
+
+/*******************************************************************************
+* Function Name: SD_RX_DMA_COMPLETE_GetPriority
+********************************************************************************
+*
+* Summary:
+* Gets the Priority of the Interrupt.
+*
+* Parameters:
+* None
+*
+* Return:
+* Priority of the interrupt. 0 - 7, 0 being the highest.
+*
+*******************************************************************************/
+uint8 SD_RX_DMA_COMPLETE_GetPriority(void)
+{
+ uint8 priority;
+
+
+ priority = *SD_RX_DMA_COMPLETE_INTC_PRIOR >> 5;
+
+ return priority;
+}
+
+
+/*******************************************************************************
+* Function Name: SD_RX_DMA_COMPLETE_Enable
+********************************************************************************
+*
+* Summary:
+* Enables the interrupt.
+*
+* Parameters:
+* None
+*
+* Return:
+* None
+*
+*******************************************************************************/
+void SD_RX_DMA_COMPLETE_Enable(void)
+{
+ /* Enable the general interrupt. */
+ *SD_RX_DMA_COMPLETE_INTC_SET_EN = SD_RX_DMA_COMPLETE__INTC_MASK;
+}
+
+
+/*******************************************************************************
+* Function Name: SD_RX_DMA_COMPLETE_GetState
+********************************************************************************
+*
+* Summary:
+* Gets the state (enabled, disabled) of the Interrupt.
+*
+* Parameters:
+* None
+*
+* Return:
+* 1 if enabled, 0 if disabled.
+*
+*******************************************************************************/
+uint8 SD_RX_DMA_COMPLETE_GetState(void)
+{
+ /* Get the state of the general interrupt. */
+ return ((*SD_RX_DMA_COMPLETE_INTC_SET_EN & (uint32)SD_RX_DMA_COMPLETE__INTC_MASK) != 0u) ? 1u:0u;
+}
+
+
+/*******************************************************************************
+* Function Name: SD_RX_DMA_COMPLETE_Disable
+********************************************************************************
+*
+* Summary:
+* Disables the Interrupt.
+*
+* Parameters:
+* None
+*
+* Return:
+* None
+*
+*******************************************************************************/
+void SD_RX_DMA_COMPLETE_Disable(void)
+{
+ /* Disable the general interrupt. */
+ *SD_RX_DMA_COMPLETE_INTC_CLR_EN = SD_RX_DMA_COMPLETE__INTC_MASK;
+}
+
+
+/*******************************************************************************
+* Function Name: SD_RX_DMA_COMPLETE_SetPending
+********************************************************************************
+*
+* Summary:
+* Causes the Interrupt to enter the pending state, a software method of
+* generating the interrupt.
+*
+* Parameters:
+* None
+*
+* Return:
+* None
+*
+*******************************************************************************/
+void SD_RX_DMA_COMPLETE_SetPending(void)
+{
+ *SD_RX_DMA_COMPLETE_INTC_SET_PD = SD_RX_DMA_COMPLETE__INTC_MASK;
+}
+
+
+/*******************************************************************************
+* Function Name: SD_RX_DMA_COMPLETE_ClearPending
+********************************************************************************
+*
+* Summary:
+* Clears a pending interrupt.
+*
+* Parameters:
+* None
+*
+* Return:
+* None
+*
+*******************************************************************************/
+void SD_RX_DMA_COMPLETE_ClearPending(void)
+{
+ *SD_RX_DMA_COMPLETE_INTC_CLR_PD = SD_RX_DMA_COMPLETE__INTC_MASK;
+}
+
+#endif /* End check for removal by optimization */
+
+
+/* [] END OF FILE */
--- /dev/null
+/*******************************************************************************
+* File Name: SD_RX_DMA_COMPLETE.h
+* Version 1.70
+*
+* Description:
+* Provides the function definitions for the Interrupt Controller.
+*
+*
+********************************************************************************
+* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions,
+* disclaimers, and limitations in the end user license agreement accompanying
+* the software package with which this file was provided.
+*******************************************************************************/
+#if !defined(CY_ISR_SD_RX_DMA_COMPLETE_H)
+#define CY_ISR_SD_RX_DMA_COMPLETE_H
+
+
+#include <cytypes.h>
+#include <cyfitter.h>
+
+/* Interrupt Controller API. */
+void SD_RX_DMA_COMPLETE_Start(void);
+void SD_RX_DMA_COMPLETE_StartEx(cyisraddress address);
+void SD_RX_DMA_COMPLETE_Stop(void);
+
+CY_ISR_PROTO(SD_RX_DMA_COMPLETE_Interrupt);
+
+void SD_RX_DMA_COMPLETE_SetVector(cyisraddress address);
+cyisraddress SD_RX_DMA_COMPLETE_GetVector(void);
+
+void SD_RX_DMA_COMPLETE_SetPriority(uint8 priority);
+uint8 SD_RX_DMA_COMPLETE_GetPriority(void);
+
+void SD_RX_DMA_COMPLETE_Enable(void);
+uint8 SD_RX_DMA_COMPLETE_GetState(void);
+void SD_RX_DMA_COMPLETE_Disable(void);
+
+void SD_RX_DMA_COMPLETE_SetPending(void);
+void SD_RX_DMA_COMPLETE_ClearPending(void);
+
+
+/* Interrupt Controller Constants */
+
+/* Address of the INTC.VECT[x] register that contains the Address of the SD_RX_DMA_COMPLETE ISR. */
+#define SD_RX_DMA_COMPLETE_INTC_VECTOR ((reg32 *) SD_RX_DMA_COMPLETE__INTC_VECT)
+
+/* Address of the SD_RX_DMA_COMPLETE ISR priority. */
+#define SD_RX_DMA_COMPLETE_INTC_PRIOR ((reg8 *) SD_RX_DMA_COMPLETE__INTC_PRIOR_REG)
+
+/* Priority of the SD_RX_DMA_COMPLETE interrupt. */
+#define SD_RX_DMA_COMPLETE_INTC_PRIOR_NUMBER SD_RX_DMA_COMPLETE__INTC_PRIOR_NUM
+
+/* Address of the INTC.SET_EN[x] byte to bit enable SD_RX_DMA_COMPLETE interrupt. */
+#define SD_RX_DMA_COMPLETE_INTC_SET_EN ((reg32 *) SD_RX_DMA_COMPLETE__INTC_SET_EN_REG)
+
+/* Address of the INTC.CLR_EN[x] register to bit clear the SD_RX_DMA_COMPLETE interrupt. */
+#define SD_RX_DMA_COMPLETE_INTC_CLR_EN ((reg32 *) SD_RX_DMA_COMPLETE__INTC_CLR_EN_REG)
+
+/* Address of the INTC.SET_PD[x] register to set the SD_RX_DMA_COMPLETE interrupt state to pending. */
+#define SD_RX_DMA_COMPLETE_INTC_SET_PD ((reg32 *) SD_RX_DMA_COMPLETE__INTC_SET_PD_REG)
+
+/* Address of the INTC.CLR_PD[x] register to clear the SD_RX_DMA_COMPLETE interrupt. */
+#define SD_RX_DMA_COMPLETE_INTC_CLR_PD ((reg32 *) SD_RX_DMA_COMPLETE__INTC_CLR_PD_REG)
+
+
+#endif /* CY_ISR_SD_RX_DMA_COMPLETE_H */
+
+
+/* [] END OF FILE */
--- /dev/null
+/***************************************************************************
+* File Name: SD_RX_DMA_dma.c
+* Version 1.70
+*
+* Description:
+* Provides an API for the DMAC component. The API includes functions
+* for the DMA controller, DMA channels and Transfer Descriptors.
+*
+*
+* Note:
+* This module requires the developer to finish or fill in the auto
+* generated funcions and setup the dma channel and TD's.
+*
+********************************************************************************
+* Copyright 2008-2010, Cypress Semiconductor Corporation. All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions,
+* disclaimers, and limitations in the end user license agreement accompanying
+* the software package with which this file was provided.
+********************************************************************************/
+#include <CYLIB.H>
+#include <CYDMAC.H>
+#include <SD_RX_DMA_dma.H>
+
+
+
+/****************************************************************************
+*
+* The following defines are available in Cyfitter.h
+*
+*
+*
+* SD_RX_DMA__DRQ_CTL_REG
+*
+*
+* SD_RX_DMA__DRQ_NUMBER
+*
+* Number of TD's used by this channel.
+* SD_RX_DMA__NUMBEROF_TDS
+*
+* Priority of this channel.
+* SD_RX_DMA__PRIORITY
+*
+* True if SD_RX_DMA_TERMIN_SEL is used.
+* SD_RX_DMA__TERMIN_EN
+*
+* TERMIN interrupt line to signal terminate.
+* SD_RX_DMA__TERMIN_SEL
+*
+*
+* True if SD_RX_DMA_TERMOUT0_SEL is used.
+* SD_RX_DMA__TERMOUT0_EN
+*
+*
+* TERMOUT0 interrupt line to signal completion.
+* SD_RX_DMA__TERMOUT0_SEL
+*
+*
+* True if SD_RX_DMA_TERMOUT1_SEL is used.
+* SD_RX_DMA__TERMOUT1_EN
+*
+*
+* TERMOUT1 interrupt line to signal completion.
+* SD_RX_DMA__TERMOUT1_SEL
+*
+****************************************************************************/
+
+
+/* Zero based index of SD_RX_DMA dma channel */
+uint8 SD_RX_DMA_DmaHandle = DMA_INVALID_CHANNEL;
+
+/*********************************************************************
+* Function Name: uint8 SD_RX_DMA_DmaInitalize
+**********************************************************************
+* Summary:
+* Allocates and initialises a channel of the DMAC to be used by the
+* caller.
+*
+* Parameters:
+* BurstCount.
+*
+*
+* ReqestPerBurst.
+*
+*
+* UpperSrcAddress.
+*
+*
+* UpperDestAddress.
+*
+*
+* Return:
+* The channel that can be used by the caller for DMA activity.
+* DMA_INVALID_CHANNEL (0xFF) if there are no channels left.
+*
+*
+*******************************************************************/
+uint8 SD_RX_DMA_DmaInitialize(uint8 BurstCount, uint8 ReqestPerBurst, uint16 UpperSrcAddress, uint16 UpperDestAddress)
+{
+
+ /* Allocate a DMA channel. */
+ SD_RX_DMA_DmaHandle = (uint8)SD_RX_DMA__DRQ_NUMBER;
+
+ /* Configure the channel. */
+ (void)CyDmaChSetConfiguration(SD_RX_DMA_DmaHandle,
+ BurstCount,
+ ReqestPerBurst,
+ (uint8)SD_RX_DMA__TERMOUT0_SEL,
+ (uint8)SD_RX_DMA__TERMOUT1_SEL,
+ (uint8)SD_RX_DMA__TERMIN_SEL);
+
+ /* Set the extended address for the transfers */
+ (void)CyDmaChSetExtendedAddress(SD_RX_DMA_DmaHandle, UpperSrcAddress, UpperDestAddress);
+
+ /* Set the priority for this channel */
+ (void)CyDmaChPriority(SD_RX_DMA_DmaHandle, (uint8)SD_RX_DMA__PRIORITY);
+
+ return SD_RX_DMA_DmaHandle;
+}
+
+/*********************************************************************
+* Function Name: void SD_RX_DMA_DmaRelease
+**********************************************************************
+* Summary:
+* Frees the channel associated with SD_RX_DMA.
+*
+*
+* Parameters:
+* void.
+*
+*
+*
+* Return:
+* void.
+*
+*******************************************************************/
+void SD_RX_DMA_DmaRelease(void)
+{
+ /* Disable the channel */
+ (void)CyDmaChDisable(SD_RX_DMA_DmaHandle);
+}
+
--- /dev/null
+/******************************************************************************
+* File Name: SD_RX_DMA_dma.h
+* Version 1.70
+*
+* Description:
+* Provides the function definitions for the DMA Controller.
+*
+*
+********************************************************************************
+* Copyright 2008-2010, Cypress Semiconductor Corporation. All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions,
+* disclaimers, and limitations in the end user license agreement accompanying
+* the software package with which this file was provided.
+********************************************************************************/
+#if !defined(CY_DMA_SD_RX_DMA_DMA_H__)
+#define CY_DMA_SD_RX_DMA_DMA_H__
+
+
+
+#include <CYDMAC.H>
+#include <CYFITTER.H>
+
+#define SD_RX_DMA__TD_TERMOUT_EN (((0 != SD_RX_DMA__TERMOUT0_EN) ? TD_TERMOUT0_EN : 0) | \
+ (SD_RX_DMA__TERMOUT1_EN ? TD_TERMOUT1_EN : 0))
+
+/* Zero based index of SD_RX_DMA dma channel */
+extern uint8 SD_RX_DMA_DmaHandle;
+
+
+uint8 SD_RX_DMA_DmaInitialize(uint8 BurstCount, uint8 ReqestPerBurst, uint16 UpperSrcAddress, uint16 UpperDestAddress) ;
+void SD_RX_DMA_DmaRelease(void) ;
+
+
+/* CY_DMA_SD_RX_DMA_DMA_H__ */
+#endif
--- /dev/null
+/*******************************************************************************
+* File Name: SD_TX_DMA_COMPLETE.c
+* Version 1.70
+*
+* Description:
+* API for controlling the state of an interrupt.
+*
+*
+* Note:
+*
+********************************************************************************
+* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions,
+* disclaimers, and limitations in the end user license agreement accompanying
+* the software package with which this file was provided.
+*******************************************************************************/
+
+
+#include <cydevice_trm.h>
+#include <CyLib.h>
+#include <SD_TX_DMA_COMPLETE.h>
+
+#if !defined(SD_TX_DMA_COMPLETE__REMOVED) /* Check for removal by optimization */
+
+/*******************************************************************************
+* Place your includes, defines and code here
+********************************************************************************/
+/* `#START SD_TX_DMA_COMPLETE_intc` */
+
+/* `#END` */
+
+#ifndef CYINT_IRQ_BASE
+#define CYINT_IRQ_BASE 16
+#endif /* CYINT_IRQ_BASE */
+#ifndef CYINT_VECT_TABLE
+#define CYINT_VECT_TABLE ((cyisraddress **) CYREG_NVIC_VECT_OFFSET)
+#endif /* CYINT_VECT_TABLE */
+
+/* Declared in startup, used to set unused interrupts to. */
+CY_ISR_PROTO(IntDefaultHandler);
+
+
+/*******************************************************************************
+* Function Name: SD_TX_DMA_COMPLETE_Start
+********************************************************************************
+*
+* Summary:
+* Set up the interrupt and enable it.
+*
+* Parameters:
+* None
+*
+* Return:
+* None
+*
+*******************************************************************************/
+void SD_TX_DMA_COMPLETE_Start(void)
+{
+ /* For all we know the interrupt is active. */
+ SD_TX_DMA_COMPLETE_Disable();
+
+ /* Set the ISR to point to the SD_TX_DMA_COMPLETE Interrupt. */
+ SD_TX_DMA_COMPLETE_SetVector(&SD_TX_DMA_COMPLETE_Interrupt);
+
+ /* Set the priority. */
+ SD_TX_DMA_COMPLETE_SetPriority((uint8)SD_TX_DMA_COMPLETE_INTC_PRIOR_NUMBER);
+
+ /* Enable it. */
+ SD_TX_DMA_COMPLETE_Enable();
+}
+
+
+/*******************************************************************************
+* Function Name: SD_TX_DMA_COMPLETE_StartEx
+********************************************************************************
+*
+* Summary:
+* Set up the interrupt and enable it.
+*
+* Parameters:
+* address: Address of the ISR to set in the interrupt vector table.
+*
+* Return:
+* None
+*
+*******************************************************************************/
+void SD_TX_DMA_COMPLETE_StartEx(cyisraddress address)
+{
+ /* For all we know the interrupt is active. */
+ SD_TX_DMA_COMPLETE_Disable();
+
+ /* Set the ISR to point to the SD_TX_DMA_COMPLETE Interrupt. */
+ SD_TX_DMA_COMPLETE_SetVector(address);
+
+ /* Set the priority. */
+ SD_TX_DMA_COMPLETE_SetPriority((uint8)SD_TX_DMA_COMPLETE_INTC_PRIOR_NUMBER);
+
+ /* Enable it. */
+ SD_TX_DMA_COMPLETE_Enable();
+}
+
+
+/*******************************************************************************
+* Function Name: SD_TX_DMA_COMPLETE_Stop
+********************************************************************************
+*
+* Summary:
+* Disables and removes the interrupt.
+*
+* Parameters:
+*
+* Return:
+* None
+*
+*******************************************************************************/
+void SD_TX_DMA_COMPLETE_Stop(void)
+{
+ /* Disable this interrupt. */
+ SD_TX_DMA_COMPLETE_Disable();
+
+ /* Set the ISR to point to the passive one. */
+ SD_TX_DMA_COMPLETE_SetVector(&IntDefaultHandler);
+}
+
+
+/*******************************************************************************
+* Function Name: SD_TX_DMA_COMPLETE_Interrupt
+********************************************************************************
+*
+* Summary:
+* The default Interrupt Service Routine for SD_TX_DMA_COMPLETE.
+*
+* Add custom code between the coments to keep the next version of this file
+* from over writting your code.
+*
+* Parameters:
+*
+* Return:
+* None
+*
+*******************************************************************************/
+CY_ISR(SD_TX_DMA_COMPLETE_Interrupt)
+{
+ /* Place your Interrupt code here. */
+ /* `#START SD_TX_DMA_COMPLETE_Interrupt` */
+
+ /* `#END` */
+}
+
+
+/*******************************************************************************
+* Function Name: SD_TX_DMA_COMPLETE_SetVector
+********************************************************************************
+*
+* Summary:
+* Change the ISR vector for the Interrupt. Note calling SD_TX_DMA_COMPLETE_Start
+* will override any effect this method would have had. To set the vector
+* before the component has been started use SD_TX_DMA_COMPLETE_StartEx instead.
+*
+* Parameters:
+* address: Address of the ISR to set in the interrupt vector table.
+*
+* Return:
+* None
+*
+*******************************************************************************/
+void SD_TX_DMA_COMPLETE_SetVector(cyisraddress address)
+{
+ cyisraddress * ramVectorTable;
+
+ ramVectorTable = (cyisraddress *) *CYINT_VECT_TABLE;
+
+ ramVectorTable[CYINT_IRQ_BASE + (uint32)SD_TX_DMA_COMPLETE__INTC_NUMBER] = address;
+}
+
+
+/*******************************************************************************
+* Function Name: SD_TX_DMA_COMPLETE_GetVector
+********************************************************************************
+*
+* Summary:
+* Gets the "address" of the current ISR vector for the Interrupt.
+*
+* Parameters:
+* None
+*
+* Return:
+* Address of the ISR in the interrupt vector table.
+*
+*******************************************************************************/
+cyisraddress SD_TX_DMA_COMPLETE_GetVector(void)
+{
+ cyisraddress * ramVectorTable;
+
+ ramVectorTable = (cyisraddress *) *CYINT_VECT_TABLE;
+
+ return ramVectorTable[CYINT_IRQ_BASE + (uint32)SD_TX_DMA_COMPLETE__INTC_NUMBER];
+}
+
+
+/*******************************************************************************
+* Function Name: SD_TX_DMA_COMPLETE_SetPriority
+********************************************************************************
+*
+* Summary:
+* Sets the Priority of the Interrupt. Note calling SD_TX_DMA_COMPLETE_Start
+* or SD_TX_DMA_COMPLETE_StartEx will override any effect this method
+* would have had. This method should only be called after
+* SD_TX_DMA_COMPLETE_Start or SD_TX_DMA_COMPLETE_StartEx has been called. To set
+* the initial priority for the component use the cydwr file in the tool.
+*
+* Parameters:
+* priority: Priority of the interrupt. 0 - 7, 0 being the highest.
+*
+* Return:
+* None
+*
+*******************************************************************************/
+void SD_TX_DMA_COMPLETE_SetPriority(uint8 priority)
+{
+ *SD_TX_DMA_COMPLETE_INTC_PRIOR = priority << 5;
+}
+
+
+/*******************************************************************************
+* Function Name: SD_TX_DMA_COMPLETE_GetPriority
+********************************************************************************
+*
+* Summary:
+* Gets the Priority of the Interrupt.
+*
+* Parameters:
+* None
+*
+* Return:
+* Priority of the interrupt. 0 - 7, 0 being the highest.
+*
+*******************************************************************************/
+uint8 SD_TX_DMA_COMPLETE_GetPriority(void)
+{
+ uint8 priority;
+
+
+ priority = *SD_TX_DMA_COMPLETE_INTC_PRIOR >> 5;
+
+ return priority;
+}
+
+
+/*******************************************************************************
+* Function Name: SD_TX_DMA_COMPLETE_Enable
+********************************************************************************
+*
+* Summary:
+* Enables the interrupt.
+*
+* Parameters:
+* None
+*
+* Return:
+* None
+*
+*******************************************************************************/
+void SD_TX_DMA_COMPLETE_Enable(void)
+{
+ /* Enable the general interrupt. */
+ *SD_TX_DMA_COMPLETE_INTC_SET_EN = SD_TX_DMA_COMPLETE__INTC_MASK;
+}
+
+
+/*******************************************************************************
+* Function Name: SD_TX_DMA_COMPLETE_GetState
+********************************************************************************
+*
+* Summary:
+* Gets the state (enabled, disabled) of the Interrupt.
+*
+* Parameters:
+* None
+*
+* Return:
+* 1 if enabled, 0 if disabled.
+*
+*******************************************************************************/
+uint8 SD_TX_DMA_COMPLETE_GetState(void)
+{
+ /* Get the state of the general interrupt. */
+ return ((*SD_TX_DMA_COMPLETE_INTC_SET_EN & (uint32)SD_TX_DMA_COMPLETE__INTC_MASK) != 0u) ? 1u:0u;
+}
+
+
+/*******************************************************************************
+* Function Name: SD_TX_DMA_COMPLETE_Disable
+********************************************************************************
+*
+* Summary:
+* Disables the Interrupt.
+*
+* Parameters:
+* None
+*
+* Return:
+* None
+*
+*******************************************************************************/
+void SD_TX_DMA_COMPLETE_Disable(void)
+{
+ /* Disable the general interrupt. */
+ *SD_TX_DMA_COMPLETE_INTC_CLR_EN = SD_TX_DMA_COMPLETE__INTC_MASK;
+}
+
+
+/*******************************************************************************
+* Function Name: SD_TX_DMA_COMPLETE_SetPending
+********************************************************************************
+*
+* Summary:
+* Causes the Interrupt to enter the pending state, a software method of
+* generating the interrupt.
+*
+* Parameters:
+* None
+*
+* Return:
+* None
+*
+*******************************************************************************/
+void SD_TX_DMA_COMPLETE_SetPending(void)
+{
+ *SD_TX_DMA_COMPLETE_INTC_SET_PD = SD_TX_DMA_COMPLETE__INTC_MASK;
+}
+
+
+/*******************************************************************************
+* Function Name: SD_TX_DMA_COMPLETE_ClearPending
+********************************************************************************
+*
+* Summary:
+* Clears a pending interrupt.
+*
+* Parameters:
+* None
+*
+* Return:
+* None
+*
+*******************************************************************************/
+void SD_TX_DMA_COMPLETE_ClearPending(void)
+{
+ *SD_TX_DMA_COMPLETE_INTC_CLR_PD = SD_TX_DMA_COMPLETE__INTC_MASK;
+}
+
+#endif /* End check for removal by optimization */
+
+
+/* [] END OF FILE */
--- /dev/null
+/*******************************************************************************
+* File Name: SD_TX_DMA_COMPLETE.h
+* Version 1.70
+*
+* Description:
+* Provides the function definitions for the Interrupt Controller.
+*
+*
+********************************************************************************
+* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions,
+* disclaimers, and limitations in the end user license agreement accompanying
+* the software package with which this file was provided.
+*******************************************************************************/
+#if !defined(CY_ISR_SD_TX_DMA_COMPLETE_H)
+#define CY_ISR_SD_TX_DMA_COMPLETE_H
+
+
+#include <cytypes.h>
+#include <cyfitter.h>
+
+/* Interrupt Controller API. */
+void SD_TX_DMA_COMPLETE_Start(void);
+void SD_TX_DMA_COMPLETE_StartEx(cyisraddress address);
+void SD_TX_DMA_COMPLETE_Stop(void);
+
+CY_ISR_PROTO(SD_TX_DMA_COMPLETE_Interrupt);
+
+void SD_TX_DMA_COMPLETE_SetVector(cyisraddress address);
+cyisraddress SD_TX_DMA_COMPLETE_GetVector(void);
+
+void SD_TX_DMA_COMPLETE_SetPriority(uint8 priority);
+uint8 SD_TX_DMA_COMPLETE_GetPriority(void);
+
+void SD_TX_DMA_COMPLETE_Enable(void);
+uint8 SD_TX_DMA_COMPLETE_GetState(void);
+void SD_TX_DMA_COMPLETE_Disable(void);
+
+void SD_TX_DMA_COMPLETE_SetPending(void);
+void SD_TX_DMA_COMPLETE_ClearPending(void);
+
+
+/* Interrupt Controller Constants */
+
+/* Address of the INTC.VECT[x] register that contains the Address of the SD_TX_DMA_COMPLETE ISR. */
+#define SD_TX_DMA_COMPLETE_INTC_VECTOR ((reg32 *) SD_TX_DMA_COMPLETE__INTC_VECT)
+
+/* Address of the SD_TX_DMA_COMPLETE ISR priority. */
+#define SD_TX_DMA_COMPLETE_INTC_PRIOR ((reg8 *) SD_TX_DMA_COMPLETE__INTC_PRIOR_REG)
+
+/* Priority of the SD_TX_DMA_COMPLETE interrupt. */
+#define SD_TX_DMA_COMPLETE_INTC_PRIOR_NUMBER SD_TX_DMA_COMPLETE__INTC_PRIOR_NUM
+
+/* Address of the INTC.SET_EN[x] byte to bit enable SD_TX_DMA_COMPLETE interrupt. */
+#define SD_TX_DMA_COMPLETE_INTC_SET_EN ((reg32 *) SD_TX_DMA_COMPLETE__INTC_SET_EN_REG)
+
+/* Address of the INTC.CLR_EN[x] register to bit clear the SD_TX_DMA_COMPLETE interrupt. */
+#define SD_TX_DMA_COMPLETE_INTC_CLR_EN ((reg32 *) SD_TX_DMA_COMPLETE__INTC_CLR_EN_REG)
+
+/* Address of the INTC.SET_PD[x] register to set the SD_TX_DMA_COMPLETE interrupt state to pending. */
+#define SD_TX_DMA_COMPLETE_INTC_SET_PD ((reg32 *) SD_TX_DMA_COMPLETE__INTC_SET_PD_REG)
+
+/* Address of the INTC.CLR_PD[x] register to clear the SD_TX_DMA_COMPLETE interrupt. */
+#define SD_TX_DMA_COMPLETE_INTC_CLR_PD ((reg32 *) SD_TX_DMA_COMPLETE__INTC_CLR_PD_REG)
+
+
+#endif /* CY_ISR_SD_TX_DMA_COMPLETE_H */
+
+
+/* [] END OF FILE */
--- /dev/null
+/***************************************************************************
+* File Name: SD_TX_DMA_dma.c
+* Version 1.70
+*
+* Description:
+* Provides an API for the DMAC component. The API includes functions
+* for the DMA controller, DMA channels and Transfer Descriptors.
+*
+*
+* Note:
+* This module requires the developer to finish or fill in the auto
+* generated funcions and setup the dma channel and TD's.
+*
+********************************************************************************
+* Copyright 2008-2010, Cypress Semiconductor Corporation. All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions,
+* disclaimers, and limitations in the end user license agreement accompanying
+* the software package with which this file was provided.
+********************************************************************************/
+#include <CYLIB.H>
+#include <CYDMAC.H>
+#include <SD_TX_DMA_dma.H>
+
+
+
+/****************************************************************************
+*
+* The following defines are available in Cyfitter.h
+*
+*
+*
+* SD_TX_DMA__DRQ_CTL_REG
+*
+*
+* SD_TX_DMA__DRQ_NUMBER
+*
+* Number of TD's used by this channel.
+* SD_TX_DMA__NUMBEROF_TDS
+*
+* Priority of this channel.
+* SD_TX_DMA__PRIORITY
+*
+* True if SD_TX_DMA_TERMIN_SEL is used.
+* SD_TX_DMA__TERMIN_EN
+*
+* TERMIN interrupt line to signal terminate.
+* SD_TX_DMA__TERMIN_SEL
+*
+*
+* True if SD_TX_DMA_TERMOUT0_SEL is used.
+* SD_TX_DMA__TERMOUT0_EN
+*
+*
+* TERMOUT0 interrupt line to signal completion.
+* SD_TX_DMA__TERMOUT0_SEL
+*
+*
+* True if SD_TX_DMA_TERMOUT1_SEL is used.
+* SD_TX_DMA__TERMOUT1_EN
+*
+*
+* TERMOUT1 interrupt line to signal completion.
+* SD_TX_DMA__TERMOUT1_SEL
+*
+****************************************************************************/
+
+
+/* Zero based index of SD_TX_DMA dma channel */
+uint8 SD_TX_DMA_DmaHandle = DMA_INVALID_CHANNEL;
+
+/*********************************************************************
+* Function Name: uint8 SD_TX_DMA_DmaInitalize
+**********************************************************************
+* Summary:
+* Allocates and initialises a channel of the DMAC to be used by the
+* caller.
+*
+* Parameters:
+* BurstCount.
+*
+*
+* ReqestPerBurst.
+*
+*
+* UpperSrcAddress.
+*
+*
+* UpperDestAddress.
+*
+*
+* Return:
+* The channel that can be used by the caller for DMA activity.
+* DMA_INVALID_CHANNEL (0xFF) if there are no channels left.
+*
+*
+*******************************************************************/
+uint8 SD_TX_DMA_DmaInitialize(uint8 BurstCount, uint8 ReqestPerBurst, uint16 UpperSrcAddress, uint16 UpperDestAddress)
+{
+
+ /* Allocate a DMA channel. */
+ SD_TX_DMA_DmaHandle = (uint8)SD_TX_DMA__DRQ_NUMBER;
+
+ /* Configure the channel. */
+ (void)CyDmaChSetConfiguration(SD_TX_DMA_DmaHandle,
+ BurstCount,
+ ReqestPerBurst,
+ (uint8)SD_TX_DMA__TERMOUT0_SEL,
+ (uint8)SD_TX_DMA__TERMOUT1_SEL,
+ (uint8)SD_TX_DMA__TERMIN_SEL);
+
+ /* Set the extended address for the transfers */
+ (void)CyDmaChSetExtendedAddress(SD_TX_DMA_DmaHandle, UpperSrcAddress, UpperDestAddress);
+
+ /* Set the priority for this channel */
+ (void)CyDmaChPriority(SD_TX_DMA_DmaHandle, (uint8)SD_TX_DMA__PRIORITY);
+
+ return SD_TX_DMA_DmaHandle;
+}
+
+/*********************************************************************
+* Function Name: void SD_TX_DMA_DmaRelease
+**********************************************************************
+* Summary:
+* Frees the channel associated with SD_TX_DMA.
+*
+*
+* Parameters:
+* void.
+*
+*
+*
+* Return:
+* void.
+*
+*******************************************************************/
+void SD_TX_DMA_DmaRelease(void)
+{
+ /* Disable the channel */
+ (void)CyDmaChDisable(SD_TX_DMA_DmaHandle);
+}
+
--- /dev/null
+/******************************************************************************
+* File Name: SD_TX_DMA_dma.h
+* Version 1.70
+*
+* Description:
+* Provides the function definitions for the DMA Controller.
+*
+*
+********************************************************************************
+* Copyright 2008-2010, Cypress Semiconductor Corporation. All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions,
+* disclaimers, and limitations in the end user license agreement accompanying
+* the software package with which this file was provided.
+********************************************************************************/
+#if !defined(CY_DMA_SD_TX_DMA_DMA_H__)
+#define CY_DMA_SD_TX_DMA_DMA_H__
+
+
+
+#include <CYDMAC.H>
+#include <CYFITTER.H>
+
+#define SD_TX_DMA__TD_TERMOUT_EN (((0 != SD_TX_DMA__TERMOUT0_EN) ? TD_TERMOUT0_EN : 0) | \
+ (SD_TX_DMA__TERMOUT1_EN ? TD_TERMOUT1_EN : 0))
+
+/* Zero based index of SD_TX_DMA dma channel */
+extern uint8 SD_TX_DMA_DmaHandle;
+
+
+uint8 SD_TX_DMA_DmaInitialize(uint8 BurstCount, uint8 ReqestPerBurst, uint16 UpperSrcAddress, uint16 UpperDestAddress) ;
+void SD_TX_DMA_DmaRelease(void) ;
+
+
+/* CY_DMA_SD_TX_DMA_DMA_H__ */
+#endif
/* Debug_Timer_Interrupt */\r
#define Debug_Timer_Interrupt__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
#define Debug_Timer_Interrupt__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
-#define Debug_Timer_Interrupt__INTC_MASK 0x01u\r
-#define Debug_Timer_Interrupt__INTC_NUMBER 0u\r
+#define Debug_Timer_Interrupt__INTC_MASK 0x02u\r
+#define Debug_Timer_Interrupt__INTC_NUMBER 1u\r
#define Debug_Timer_Interrupt__INTC_PRIOR_NUM 7u\r
-#define Debug_Timer_Interrupt__INTC_PRIOR_REG CYREG_NVIC_PRI_0\r
+#define Debug_Timer_Interrupt__INTC_PRIOR_REG CYREG_NVIC_PRI_1\r
#define Debug_Timer_Interrupt__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
#define Debug_Timer_Interrupt__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
\r
+/* SCSI_RX_DMA_COMPLETE */\r
+#define SCSI_RX_DMA_COMPLETE__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
+#define SCSI_RX_DMA_COMPLETE__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
+#define SCSI_RX_DMA_COMPLETE__INTC_MASK 0x01u\r
+#define SCSI_RX_DMA_COMPLETE__INTC_NUMBER 0u\r
+#define SCSI_RX_DMA_COMPLETE__INTC_PRIOR_NUM 7u\r
+#define SCSI_RX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_0\r
+#define SCSI_RX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
+#define SCSI_RX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
+\r
+/* SCSI_TX_DMA_COMPLETE */\r
+#define SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
+#define SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
+#define SCSI_TX_DMA_COMPLETE__INTC_MASK 0x04u\r
+#define SCSI_TX_DMA_COMPLETE__INTC_NUMBER 2u\r
+#define SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM 7u\r
+#define SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_2\r
+#define SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
+#define SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
+\r
/* Debug_Timer_TimerHW */\r
#define Debug_Timer_TimerHW__CAP0 CYREG_TMR0_CAP0\r
#define Debug_Timer_TimerHW__CAP1 CYREG_TMR0_CAP1\r
#define Debug_Timer_TimerHW__RT1 CYREG_TMR0_RT1\r
#define Debug_Timer_TimerHW__SR0 CYREG_TMR0_SR0\r
\r
+/* SD_RX_DMA_COMPLETE */\r
+#define SD_RX_DMA_COMPLETE__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
+#define SD_RX_DMA_COMPLETE__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
+#define SD_RX_DMA_COMPLETE__INTC_MASK 0x08u\r
+#define SD_RX_DMA_COMPLETE__INTC_NUMBER 3u\r
+#define SD_RX_DMA_COMPLETE__INTC_PRIOR_NUM 7u\r
+#define SD_RX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_3\r
+#define SD_RX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
+#define SD_RX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
+\r
+/* SD_TX_DMA_COMPLETE */\r
+#define SD_TX_DMA_COMPLETE__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
+#define SD_TX_DMA_COMPLETE__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
+#define SD_TX_DMA_COMPLETE__INTC_MASK 0x10u\r
+#define SD_TX_DMA_COMPLETE__INTC_NUMBER 4u\r
+#define SD_TX_DMA_COMPLETE__INTC_PRIOR_NUM 7u\r
+#define SD_TX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_4\r
+#define SD_TX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
+#define SD_TX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
+\r
/* USBFS_bus_reset */\r
#define USBFS_bus_reset__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
#define USBFS_bus_reset__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
/* SCSI_CTL_PHASE */\r
#define SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK 0x01u\r
#define SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS 0\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB05_06_ACTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB05_06_CTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB05_06_CTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB05_06_CTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB05_06_CTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB05_06_MSK\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB05_06_MSK\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB05_06_MSK\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB05_06_MSK\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB02_03_ACTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB02_03_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB02_03_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB02_03_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB02_03_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB02_03_MSK\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB02_03_MSK\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB02_03_MSK\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB02_03_MSK\r
#define SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK 0x02u\r
#define SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS 1\r
#define SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK 0x04u\r
#define SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS 2\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB05_ACTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB05_CTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB05_ST_CTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB05_CTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB05_ST_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB02_ACTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB02_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB02_ST_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB02_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB02_ST_CTL\r
#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK 0x07u\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB05_MSK\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB02_MSK_ACTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB02_MSK\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB02_MSK_ACTL\r
\r
/* SCSI_Out_Bits */\r
#define SCSI_Out_Bits_Sync_ctrl_reg__0__MASK 0x01u\r
#define SCSI_Out_Bits_Sync_ctrl_reg__0__POS 0\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB00_01_ACTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB00_01_CTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB00_01_CTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB00_01_CTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB00_01_CTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB00_01_MSK\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB00_01_MSK\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB00_01_MSK\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB00_01_MSK\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB12_13_ACTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB12_13_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB12_13_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB12_13_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB12_13_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB12_13_MSK\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB12_13_MSK\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB12_13_MSK\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB12_13_MSK\r
#define SCSI_Out_Bits_Sync_ctrl_reg__1__MASK 0x02u\r
#define SCSI_Out_Bits_Sync_ctrl_reg__1__POS 1\r
#define SCSI_Out_Bits_Sync_ctrl_reg__2__MASK 0x04u\r
#define SCSI_Out_Bits_Sync_ctrl_reg__6__POS 6\r
#define SCSI_Out_Bits_Sync_ctrl_reg__7__MASK 0x80u\r
#define SCSI_Out_Bits_Sync_ctrl_reg__7__POS 7\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB00_ACTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB00_CTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB00_ST_CTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB00_CTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB00_ST_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB12_ACTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB12_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB12_ST_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB12_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB12_ST_CTL\r
#define SCSI_Out_Bits_Sync_ctrl_reg__MASK 0xFFu\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB00_MSK_ACTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB00_MSK\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB00_MSK_ACTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB12_MSK\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL\r
\r
/* USBFS_arb_int */\r
#define USBFS_arb_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
/* SCSI_Out_Ctl */\r
#define SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK 0x01u\r
#define SCSI_Out_Ctl_Sync_ctrl_reg__0__POS 0\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB03_04_ACTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB03_04_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB03_04_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB03_04_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB03_04_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB03_04_MSK\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB03_04_MSK\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB03_04_MSK\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB03_04_MSK\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB03_ACTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB03_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB03_ST_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB03_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB03_ST_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB07_08_ACTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB07_08_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB07_08_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB07_08_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B1_UDB07_08_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B1_UDB07_08_MSK\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B1_UDB07_08_MSK\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B1_UDB07_08_MSK\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB07_08_MSK\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B1_UDB07_ACTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B1_UDB07_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B1_UDB07_ST_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B1_UDB07_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B1_UDB07_ST_CTL\r
#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK 0x01u\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB03_MSK\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB07_MSK_ACTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B1_UDB07_MSK\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B1_UDB07_MSK_ACTL\r
\r
/* SCSI_Out_DBx */\r
#define SCSI_Out_DBx__0__AG CYREG_PRT6_AG\r
#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL\r
#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B1_UDB06_MSK\r
#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL\r
-#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB06_07_ACTL\r
-#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B0_UDB06_07_ST\r
+#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB07_08_ACTL\r
+#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B0_UDB07_08_ST\r
#define SDCard_BSPIM_RxStsReg__4__MASK 0x10u\r
#define SDCard_BSPIM_RxStsReg__4__POS 4\r
#define SDCard_BSPIM_RxStsReg__5__MASK 0x20u\r
#define SDCard_BSPIM_RxStsReg__6__MASK 0x40u\r
#define SDCard_BSPIM_RxStsReg__6__POS 6\r
#define SDCard_BSPIM_RxStsReg__MASK 0x70u\r
-#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B0_UDB06_MSK\r
-#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB06_ACTL\r
-#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B0_UDB06_ST\r
+#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B0_UDB07_MSK\r
+#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB07_ACTL\r
+#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B0_UDB07_ST\r
#define SDCard_BSPIM_TxStsReg__0__MASK 0x01u\r
#define SDCard_BSPIM_TxStsReg__0__POS 0\r
-#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB04_05_ACTL\r
-#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B0_UDB04_05_ST\r
+#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB07_08_ACTL\r
+#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B1_UDB07_08_ST\r
#define SDCard_BSPIM_TxStsReg__1__MASK 0x02u\r
#define SDCard_BSPIM_TxStsReg__1__POS 1\r
#define SDCard_BSPIM_TxStsReg__2__MASK 0x04u\r
#define SDCard_BSPIM_TxStsReg__4__MASK 0x10u\r
#define SDCard_BSPIM_TxStsReg__4__POS 4\r
#define SDCard_BSPIM_TxStsReg__MASK 0x1Fu\r
-#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B0_UDB04_MSK\r
-#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB04_ACTL\r
-#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B0_UDB04_ST\r
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B0_UDB06_07_A0\r
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B0_UDB06_07_A1\r
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG CYREG_B0_UDB06_07_D0\r
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG CYREG_B0_UDB06_07_D1\r
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG CYREG_B0_UDB06_07_ACTL\r
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG CYREG_B0_UDB06_07_F0\r
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG CYREG_B0_UDB06_07_F1\r
-#define SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG CYREG_B0_UDB06_A0_A1\r
-#define SDCard_BSPIM_sR8_Dp_u0__A0_REG CYREG_B0_UDB06_A0\r
-#define SDCard_BSPIM_sR8_Dp_u0__A1_REG CYREG_B0_UDB06_A1\r
-#define SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG CYREG_B0_UDB06_D0_D1\r
-#define SDCard_BSPIM_sR8_Dp_u0__D0_REG CYREG_B0_UDB06_D0\r
-#define SDCard_BSPIM_sR8_Dp_u0__D1_REG CYREG_B0_UDB06_D1\r
-#define SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG CYREG_B0_UDB06_ACTL\r
-#define SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG CYREG_B0_UDB06_F0_F1\r
-#define SDCard_BSPIM_sR8_Dp_u0__F0_REG CYREG_B0_UDB06_F0\r
-#define SDCard_BSPIM_sR8_Dp_u0__F1_REG CYREG_B0_UDB06_F1\r
+#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B1_UDB07_MSK\r
+#define SDCard_BSPIM_TxStsReg__MASK_ST_AUX_CTL_REG CYREG_B1_UDB07_MSK_ACTL\r
+#define SDCard_BSPIM_TxStsReg__PER_ST_AUX_CTL_REG CYREG_B1_UDB07_MSK_ACTL\r
+#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB07_ACTL\r
+#define SDCard_BSPIM_TxStsReg__STATUS_CNT_REG CYREG_B1_UDB07_ST_CTL\r
+#define SDCard_BSPIM_TxStsReg__STATUS_CONTROL_REG CYREG_B1_UDB07_ST_CTL\r
+#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B1_UDB07_ST\r
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B0_UDB04_05_A0\r
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B0_UDB04_05_A1\r
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG CYREG_B0_UDB04_05_D0\r
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG CYREG_B0_UDB04_05_D1\r
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG CYREG_B0_UDB04_05_ACTL\r
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG CYREG_B0_UDB04_05_F0\r
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG CYREG_B0_UDB04_05_F1\r
+#define SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG CYREG_B0_UDB04_A0_A1\r
+#define SDCard_BSPIM_sR8_Dp_u0__A0_REG CYREG_B0_UDB04_A0\r
+#define SDCard_BSPIM_sR8_Dp_u0__A1_REG CYREG_B0_UDB04_A1\r
+#define SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG CYREG_B0_UDB04_D0_D1\r
+#define SDCard_BSPIM_sR8_Dp_u0__D0_REG CYREG_B0_UDB04_D0\r
+#define SDCard_BSPIM_sR8_Dp_u0__D1_REG CYREG_B0_UDB04_D1\r
+#define SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG CYREG_B0_UDB04_ACTL\r
+#define SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG CYREG_B0_UDB04_F0_F1\r
+#define SDCard_BSPIM_sR8_Dp_u0__F0_REG CYREG_B0_UDB04_F0\r
+#define SDCard_BSPIM_sR8_Dp_u0__F1_REG CYREG_B0_UDB04_F1\r
\r
/* USBFS_dp_int */\r
#define USBFS_dp_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
#define SCSI_In_DBx__DB7__SHIFT 1\r
#define SCSI_In_DBx__DB7__SLW CYREG_PRT2_SLW\r
\r
+/* SCSI_RX_DMA */\r
+#define SCSI_RX_DMA__DRQ_CTL CYREG_IDMUX_DRQ_CTL0\r
+#define SCSI_RX_DMA__DRQ_NUMBER 0u\r
+#define SCSI_RX_DMA__NUMBEROF_TDS 0u\r
+#define SCSI_RX_DMA__PRIORITY 2u\r
+#define SCSI_RX_DMA__TERMIN_EN 0u\r
+#define SCSI_RX_DMA__TERMIN_SEL 0u\r
+#define SCSI_RX_DMA__TERMOUT0_EN 1u\r
+#define SCSI_RX_DMA__TERMOUT0_SEL 0u\r
+#define SCSI_RX_DMA__TERMOUT1_EN 0u\r
+#define SCSI_RX_DMA__TERMOUT1_SEL 0u\r
+\r
+/* SCSI_TX_DMA */\r
+#define SCSI_TX_DMA__DRQ_CTL CYREG_IDMUX_DRQ_CTL0\r
+#define SCSI_TX_DMA__DRQ_NUMBER 1u\r
+#define SCSI_TX_DMA__NUMBEROF_TDS 0u\r
+#define SCSI_TX_DMA__PRIORITY 2u\r
+#define SCSI_TX_DMA__TERMIN_EN 0u\r
+#define SCSI_TX_DMA__TERMIN_SEL 0u\r
+#define SCSI_TX_DMA__TERMOUT0_EN 1u\r
+#define SCSI_TX_DMA__TERMOUT0_SEL 1u\r
+#define SCSI_TX_DMA__TERMOUT1_EN 0u\r
+#define SCSI_TX_DMA__TERMOUT1_SEL 0u\r
+\r
/* SD_Data_Clk */\r
#define SD_Data_Clk__CFG0 CYREG_CLKDIST_DCFG0_CFG0\r
#define SD_Data_Clk__CFG1 CYREG_CLKDIST_DCFG0_CFG1\r
/* scsiTarget */\r
#define scsiTarget_StatusReg__0__MASK 0x01u\r
#define scsiTarget_StatusReg__0__POS 0\r
-#define scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB13_14_ACTL\r
-#define scsiTarget_StatusReg__16BIT_STATUS_REG CYREG_B0_UDB13_14_ST\r
+#define scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB04_05_ACTL\r
+#define scsiTarget_StatusReg__16BIT_STATUS_REG CYREG_B0_UDB04_05_ST\r
#define scsiTarget_StatusReg__1__MASK 0x02u\r
#define scsiTarget_StatusReg__1__POS 1\r
#define scsiTarget_StatusReg__2__MASK 0x04u\r
#define scsiTarget_StatusReg__2__POS 2\r
#define scsiTarget_StatusReg__3__MASK 0x08u\r
#define scsiTarget_StatusReg__3__POS 3\r
-#define scsiTarget_StatusReg__MASK 0x0Fu\r
-#define scsiTarget_StatusReg__MASK_REG CYREG_B0_UDB13_MSK\r
-#define scsiTarget_StatusReg__STATUS_AUX_CTL_REG CYREG_B0_UDB13_ACTL\r
-#define scsiTarget_StatusReg__STATUS_REG CYREG_B0_UDB13_ST\r
-#define scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB12_13_ACTL\r
-#define scsiTarget_datapath_PI__16BIT_STATUS_REG CYREG_B0_UDB12_13_ST\r
-#define scsiTarget_datapath_PI__MASK_REG CYREG_B0_UDB12_MSK\r
-#define scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL\r
-#define scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL\r
-#define scsiTarget_datapath_PI__STATUS_AUX_CTL_REG CYREG_B0_UDB12_ACTL\r
-#define scsiTarget_datapath_PI__STATUS_CNT_REG CYREG_B0_UDB12_ST_CTL\r
-#define scsiTarget_datapath_PI__STATUS_CONTROL_REG CYREG_B0_UDB12_ST_CTL\r
-#define scsiTarget_datapath_PI__STATUS_REG CYREG_B0_UDB12_ST\r
-#define scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB12_13_ACTL\r
-#define scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB12_13_CTL\r
-#define scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB12_13_CTL\r
-#define scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB12_13_CTL\r
-#define scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG CYREG_B0_UDB12_13_CTL\r
-#define scsiTarget_datapath_PO__16BIT_MASK_MASK_REG CYREG_B0_UDB12_13_MSK\r
-#define scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG CYREG_B0_UDB12_13_MSK\r
-#define scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG CYREG_B0_UDB12_13_MSK\r
-#define scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB12_13_MSK\r
-#define scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG CYREG_B0_UDB12_ACTL\r
-#define scsiTarget_datapath_PO__CONTROL_REG CYREG_B0_UDB12_CTL\r
-#define scsiTarget_datapath_PO__CONTROL_ST_REG CYREG_B0_UDB12_ST_CTL\r
-#define scsiTarget_datapath_PO__COUNT_REG CYREG_B0_UDB12_CTL\r
-#define scsiTarget_datapath_PO__COUNT_ST_REG CYREG_B0_UDB12_ST_CTL\r
-#define scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL\r
-#define scsiTarget_datapath_PO__PERIOD_REG CYREG_B0_UDB12_MSK\r
-#define scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL\r
-#define scsiTarget_datapath__16BIT_A0_REG CYREG_B0_UDB12_13_A0\r
-#define scsiTarget_datapath__16BIT_A1_REG CYREG_B0_UDB12_13_A1\r
-#define scsiTarget_datapath__16BIT_D0_REG CYREG_B0_UDB12_13_D0\r
-#define scsiTarget_datapath__16BIT_D1_REG CYREG_B0_UDB12_13_D1\r
-#define scsiTarget_datapath__16BIT_DP_AUX_CTL_REG CYREG_B0_UDB12_13_ACTL\r
-#define scsiTarget_datapath__16BIT_F0_REG CYREG_B0_UDB12_13_F0\r
-#define scsiTarget_datapath__16BIT_F1_REG CYREG_B0_UDB12_13_F1\r
-#define scsiTarget_datapath__A0_A1_REG CYREG_B0_UDB12_A0_A1\r
-#define scsiTarget_datapath__A0_REG CYREG_B0_UDB12_A0\r
-#define scsiTarget_datapath__A1_REG CYREG_B0_UDB12_A1\r
-#define scsiTarget_datapath__D0_D1_REG CYREG_B0_UDB12_D0_D1\r
-#define scsiTarget_datapath__D0_REG CYREG_B0_UDB12_D0\r
-#define scsiTarget_datapath__D1_REG CYREG_B0_UDB12_D1\r
-#define scsiTarget_datapath__DP_AUX_CTL_REG CYREG_B0_UDB12_ACTL\r
-#define scsiTarget_datapath__F0_F1_REG CYREG_B0_UDB12_F0_F1\r
-#define scsiTarget_datapath__F0_REG CYREG_B0_UDB12_F0\r
-#define scsiTarget_datapath__F1_REG CYREG_B0_UDB12_F1\r
-#define scsiTarget_datapath__MSK_DP_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL\r
-#define scsiTarget_datapath__PER_DP_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL\r
+#define scsiTarget_StatusReg__4__MASK 0x10u\r
+#define scsiTarget_StatusReg__4__POS 4\r
+#define scsiTarget_StatusReg__MASK 0x1Fu\r
+#define scsiTarget_StatusReg__MASK_REG CYREG_B0_UDB04_MSK\r
+#define scsiTarget_StatusReg__STATUS_AUX_CTL_REG CYREG_B0_UDB04_ACTL\r
+#define scsiTarget_StatusReg__STATUS_REG CYREG_B0_UDB04_ST\r
+#define scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB03_04_ACTL\r
+#define scsiTarget_datapath_PI__16BIT_STATUS_REG CYREG_B0_UDB03_04_ST\r
+#define scsiTarget_datapath_PI__MASK_REG CYREG_B0_UDB03_MSK\r
+#define scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL\r
+#define scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL\r
+#define scsiTarget_datapath_PI__STATUS_AUX_CTL_REG CYREG_B0_UDB03_ACTL\r
+#define scsiTarget_datapath_PI__STATUS_CNT_REG CYREG_B0_UDB03_ST_CTL\r
+#define scsiTarget_datapath_PI__STATUS_CONTROL_REG CYREG_B0_UDB03_ST_CTL\r
+#define scsiTarget_datapath_PI__STATUS_REG CYREG_B0_UDB03_ST\r
+#define scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB03_04_ACTL\r
+#define scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB03_04_CTL\r
+#define scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB03_04_CTL\r
+#define scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB03_04_CTL\r
+#define scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG CYREG_B0_UDB03_04_CTL\r
+#define scsiTarget_datapath_PO__16BIT_MASK_MASK_REG CYREG_B0_UDB03_04_MSK\r
+#define scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG CYREG_B0_UDB03_04_MSK\r
+#define scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG CYREG_B0_UDB03_04_MSK\r
+#define scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB03_04_MSK\r
+#define scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG CYREG_B0_UDB03_ACTL\r
+#define scsiTarget_datapath_PO__CONTROL_REG CYREG_B0_UDB03_CTL\r
+#define scsiTarget_datapath_PO__CONTROL_ST_REG CYREG_B0_UDB03_ST_CTL\r
+#define scsiTarget_datapath_PO__COUNT_REG CYREG_B0_UDB03_CTL\r
+#define scsiTarget_datapath_PO__COUNT_ST_REG CYREG_B0_UDB03_ST_CTL\r
+#define scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL\r
+#define scsiTarget_datapath_PO__PERIOD_REG CYREG_B0_UDB03_MSK\r
+#define scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL\r
+#define scsiTarget_datapath__16BIT_A0_REG CYREG_B0_UDB03_04_A0\r
+#define scsiTarget_datapath__16BIT_A1_REG CYREG_B0_UDB03_04_A1\r
+#define scsiTarget_datapath__16BIT_D0_REG CYREG_B0_UDB03_04_D0\r
+#define scsiTarget_datapath__16BIT_D1_REG CYREG_B0_UDB03_04_D1\r
+#define scsiTarget_datapath__16BIT_DP_AUX_CTL_REG CYREG_B0_UDB03_04_ACTL\r
+#define scsiTarget_datapath__16BIT_F0_REG CYREG_B0_UDB03_04_F0\r
+#define scsiTarget_datapath__16BIT_F1_REG CYREG_B0_UDB03_04_F1\r
+#define scsiTarget_datapath__A0_A1_REG CYREG_B0_UDB03_A0_A1\r
+#define scsiTarget_datapath__A0_REG CYREG_B0_UDB03_A0\r
+#define scsiTarget_datapath__A1_REG CYREG_B0_UDB03_A1\r
+#define scsiTarget_datapath__D0_D1_REG CYREG_B0_UDB03_D0_D1\r
+#define scsiTarget_datapath__D0_REG CYREG_B0_UDB03_D0\r
+#define scsiTarget_datapath__D1_REG CYREG_B0_UDB03_D1\r
+#define scsiTarget_datapath__DP_AUX_CTL_REG CYREG_B0_UDB03_ACTL\r
+#define scsiTarget_datapath__F0_F1_REG CYREG_B0_UDB03_F0_F1\r
+#define scsiTarget_datapath__F0_REG CYREG_B0_UDB03_F0\r
+#define scsiTarget_datapath__F1_REG CYREG_B0_UDB03_F1\r
+#define scsiTarget_datapath__MSK_DP_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL\r
+#define scsiTarget_datapath__PER_DP_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL\r
\r
/* SD_Clk_Ctl */\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__0__MASK 0x01u\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__0__POS 0\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB02_03_ACTL\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB02_03_CTL\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB02_03_CTL\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB02_03_CTL\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB02_03_CTL\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB02_03_MSK\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB02_03_MSK\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB02_03_MSK\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB02_03_MSK\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB02_ACTL\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB02_CTL\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB02_ST_CTL\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB02_CTL\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB02_ST_CTL\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__MASK 0x01u\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB02_MSK_ACTL\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB02_MSK\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB02_MSK_ACTL\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__REMOVED 1u\r
\r
/* USBFS_ep_0 */\r
#define USBFS_ep_0__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
/* USBFS_ep_1 */\r
#define USBFS_ep_1__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
#define USBFS_ep_1__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
-#define USBFS_ep_1__INTC_MASK 0x02u\r
-#define USBFS_ep_1__INTC_NUMBER 1u\r
+#define USBFS_ep_1__INTC_MASK 0x20u\r
+#define USBFS_ep_1__INTC_NUMBER 5u\r
#define USBFS_ep_1__INTC_PRIOR_NUM 7u\r
-#define USBFS_ep_1__INTC_PRIOR_REG CYREG_NVIC_PRI_1\r
+#define USBFS_ep_1__INTC_PRIOR_REG CYREG_NVIC_PRI_5\r
#define USBFS_ep_1__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
#define USBFS_ep_1__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
\r
/* USBFS_ep_2 */\r
#define USBFS_ep_2__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
#define USBFS_ep_2__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
-#define USBFS_ep_2__INTC_MASK 0x04u\r
-#define USBFS_ep_2__INTC_NUMBER 2u\r
+#define USBFS_ep_2__INTC_MASK 0x40u\r
+#define USBFS_ep_2__INTC_NUMBER 6u\r
#define USBFS_ep_2__INTC_PRIOR_NUM 7u\r
-#define USBFS_ep_2__INTC_PRIOR_REG CYREG_NVIC_PRI_2\r
+#define USBFS_ep_2__INTC_PRIOR_REG CYREG_NVIC_PRI_6\r
#define USBFS_ep_2__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
#define USBFS_ep_2__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
\r
/* USBFS_ep_3 */\r
#define USBFS_ep_3__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
#define USBFS_ep_3__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
-#define USBFS_ep_3__INTC_MASK 0x08u\r
-#define USBFS_ep_3__INTC_NUMBER 3u\r
+#define USBFS_ep_3__INTC_MASK 0x80u\r
+#define USBFS_ep_3__INTC_NUMBER 7u\r
#define USBFS_ep_3__INTC_PRIOR_NUM 7u\r
-#define USBFS_ep_3__INTC_PRIOR_REG CYREG_NVIC_PRI_3\r
+#define USBFS_ep_3__INTC_PRIOR_REG CYREG_NVIC_PRI_7\r
#define USBFS_ep_3__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
#define USBFS_ep_3__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
\r
/* USBFS_ep_4 */\r
#define USBFS_ep_4__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
#define USBFS_ep_4__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
-#define USBFS_ep_4__INTC_MASK 0x10u\r
-#define USBFS_ep_4__INTC_NUMBER 4u\r
+#define USBFS_ep_4__INTC_MASK 0x100u\r
+#define USBFS_ep_4__INTC_NUMBER 8u\r
#define USBFS_ep_4__INTC_PRIOR_NUM 7u\r
-#define USBFS_ep_4__INTC_PRIOR_REG CYREG_NVIC_PRI_4\r
+#define USBFS_ep_4__INTC_PRIOR_REG CYREG_NVIC_PRI_8\r
#define USBFS_ep_4__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
#define USBFS_ep_4__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
\r
+/* SD_RX_DMA */\r
+#define SD_RX_DMA__DRQ_CTL CYREG_IDMUX_DRQ_CTL0\r
+#define SD_RX_DMA__DRQ_NUMBER 2u\r
+#define SD_RX_DMA__NUMBEROF_TDS 0u\r
+#define SD_RX_DMA__PRIORITY 1u\r
+#define SD_RX_DMA__TERMIN_EN 0u\r
+#define SD_RX_DMA__TERMIN_SEL 0u\r
+#define SD_RX_DMA__TERMOUT0_EN 1u\r
+#define SD_RX_DMA__TERMOUT0_SEL 2u\r
+#define SD_RX_DMA__TERMOUT1_EN 0u\r
+#define SD_RX_DMA__TERMOUT1_SEL 0u\r
+\r
+/* SD_TX_DMA */\r
+#define SD_TX_DMA__DRQ_CTL CYREG_IDMUX_DRQ_CTL0\r
+#define SD_TX_DMA__DRQ_NUMBER 3u\r
+#define SD_TX_DMA__NUMBEROF_TDS 0u\r
+#define SD_TX_DMA__PRIORITY 2u\r
+#define SD_TX_DMA__TERMIN_EN 0u\r
+#define SD_TX_DMA__TERMIN_SEL 0u\r
+#define SD_TX_DMA__TERMOUT0_EN 1u\r
+#define SD_TX_DMA__TERMOUT0_SEL 3u\r
+#define SD_TX_DMA__TERMOUT1_EN 0u\r
+#define SD_TX_DMA__TERMOUT1_SEL 0u\r
+\r
/* USBFS_USB */\r
#define USBFS_USB__ARB_CFG CYREG_USB_ARB_CFG\r
#define USBFS_USB__ARB_EP1_CFG CYREG_USB_ARB_EP1_CFG\r
#define CYDEV_CHIP_FAMILY_PSOC5 3u\r
#define CYDEV_CHIP_DIE_PSOC5LP 4u\r
#define CYDEV_CHIP_DIE_EXPECT CYDEV_CHIP_DIE_PSOC5LP\r
-#define BCLK__BUS_CLK__HZ 60000000U\r
-#define BCLK__BUS_CLK__KHZ 60000U\r
-#define BCLK__BUS_CLK__MHZ 60U\r
+#define BCLK__BUS_CLK__HZ 50000000U\r
+#define BCLK__BUS_CLK__KHZ 50000U\r
+#define BCLK__BUS_CLK__MHZ 50U\r
#define CYDEV_CHIP_DIE_ACTUAL CYDEV_CHIP_DIE_EXPECT\r
#define CYDEV_CHIP_DIE_LEOPARD 1u\r
#define CYDEV_CHIP_DIE_PANTHER 3u\r
#define CYDEV_ECC_ENABLE 0\r
#define CYDEV_HEAP_SIZE 0x0400\r
#define CYDEV_INSTRUCT_CACHE_ENABLED 1\r
-#define CYDEV_INTR_RISING 0x00000001u\r
+#define CYDEV_INTR_RISING 0x0000001Eu\r
#define CYDEV_PROJ_TYPE 2\r
#define CYDEV_PROJ_TYPE_BOOTLOADER 1\r
#define CYDEV_PROJ_TYPE_LOADABLE 2\r
#define CYDEV_VIO2_MV 5000\r
#define CYDEV_VIO3 3.3\r
#define CYDEV_VIO3_MV 3300\r
-#define DMA_CHANNELS_USED__MASK0 0x00000000u\r
+#define DMA_CHANNELS_USED__MASK0 0x0000000Fu\r
#define CYDEV_BOOTLOADER_ENABLE 0\r
\r
#endif /* INCLUDED_CYFITTER_H */\r
}\r
#endif\r
\r
-#define CY_CFG_BASE_ADDR_COUNT 35u\r
+#define CY_CFG_BASE_ADDR_COUNT 37u\r
CYPACKED typedef struct\r
{\r
uint8 offset;\r
\r
\r
/* Configure Digital Clocks based on settings from Clock DWR */\r
- CY_SET_XTND_REG16((void CYFAR *)(CYREG_CLKDIST_DCFG0_CFG0), 0x0001u);\r
- CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_DCFG0_CFG0 + 0x2u), 0x10u);\r
- CY_SET_XTND_REG16((void CYFAR *)(CYREG_CLKDIST_DCFG1_CFG0), 0x0001u);\r
- CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_DCFG1_CFG0 + 0x2u), 0x18u);\r
+ CY_SET_XTND_REG16((void CYFAR *)(CYREG_CLKDIST_DCFG0_CFG0), 0x0000u);\r
+ CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_DCFG0_CFG0 + 0x2u), 0x58u);\r
+ CY_SET_XTND_REG16((void CYFAR *)(CYREG_CLKDIST_DCFG1_CFG0), 0x0000u);\r
+ CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_DCFG1_CFG0 + 0x2u), 0x58u);\r
CY_SET_XTND_REG16((void CYFAR *)(CYREG_CLKDIST_DCFG2_CFG0), 0x0017u);\r
CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_DCFG2_CFG0 + 0x2u), 0x19u);\r
CY_SET_XTND_REG16((void CYFAR *)(CYREG_CLKDIST_DCFG3_CFG0), 0x001Du);\r
CY_SET_XTND_REG8((void CYFAR *)(CYREG_IMO_TR1), (CY_GET_XTND_REG8((void CYFAR *)CYREG_FLSHID_CUST_TABLES_IMO_USB)));\r
\r
/* Configure PLL based on settings from Clock DWR */\r
- CY_SET_XTND_REG16((void CYFAR *)(CYREG_FASTCLK_PLL_P), 0x0919u);\r
+ CY_SET_XTND_REG16((void CYFAR *)(CYREG_FASTCLK_PLL_P), 0x0B19u);\r
CY_SET_XTND_REG16((void CYFAR *)(CYREG_FASTCLK_PLL_CFG0), 0x1251u);\r
/* Wait up to 250us for the PLL to lock */\r
pllLock = 0u;\r
CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_UCFG), 0x00u);\r
CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_LD), 0x02u);\r
\r
- CY_SET_XTND_REG8((void CYFAR *)(CYREG_PM_ACT_CFG2), ((CY_GET_XTND_REG8((void CYFAR *)CYREG_PM_ACT_CFG2) | 0x0Eu)));\r
+ CY_SET_XTND_REG8((void CYFAR *)(CYREG_PM_ACT_CFG2), ((CY_GET_XTND_REG8((void CYFAR *)CYREG_PM_ACT_CFG2) | 0x0Fu)));\r
}\r
\r
\r
static const uint8 CYCODE BS_IOPINS0_6_VAL[] = {\r
0xF0u, 0x0Fu, 0x0Fu, 0x00u, 0x0Fu, 0x00u, 0x00u, 0x01u};\r
\r
+ /* PHUB_CFGMEM1 Address: CYREG_PHUB_CFGMEM1_CFG0 Size (bytes): 4 */\r
+ static const uint8 CYCODE BS_PHUB_CFGMEM1_VAL[] = {\r
+ 0x00u, 0x01u, 0x00u, 0x00u};\r
+\r
+ /* PHUB_CFGMEM2 Address: CYREG_PHUB_CFGMEM2_CFG0 Size (bytes): 4 */\r
+ static const uint8 CYCODE BS_PHUB_CFGMEM2_VAL[] = {\r
+ 0x00u, 0x02u, 0x00u, 0x00u};\r
+\r
+ /* PHUB_CFGMEM3 Address: CYREG_PHUB_CFGMEM3_CFG0 Size (bytes): 4 */\r
+ static const uint8 CYCODE BS_PHUB_CFGMEM3_VAL[] = {\r
+ 0x00u, 0x03u, 0x00u, 0x00u};\r
+\r
#ifdef CYGlobalIntDisable\r
/* Disable interrupts by default. Let user enable if/when they want. */\r
CYGlobalIntDisable\r
CY_SET_XTND_REG8((void CYFAR *)(CYREG_CACHE_CC_CTL), (((CYDEV_INSTRUCT_CACHE_ENABLED) != 0) ? 0x01u : 0x00u));\r
/* Setup clocks based on selections from Clock DWR */\r
ClockSetup();\r
+ /* Set Flash Cycles based on newly configured 50.00MHz Bus Clock. */\r
+ CY_SET_XTND_REG8((void CYFAR *)(CYREG_CACHE_CC_CTL), (((CYDEV_INSTRUCT_CACHE_ENABLED) != 0) ? 0xC1u : 0xC0u));\r
/* Enable/Disable Debug functionality based on settings from System DWR */\r
CY_SET_XTND_REG8((void CYFAR *)CYREG_MLOGIC_DEBUG, (CY_GET_XTND_REG8((void CYFAR *)CYREG_MLOGIC_DEBUG) | 0x04u));\r
\r
static const uint32 CYCODE cy_cfg_addr_table[] = {\r
0x40004502u, /* Base address: 0x40004500 Count: 2 */\r
0x40004F02u, /* Base address: 0x40004F00 Count: 2 */\r
- 0x40005209u, /* Base address: 0x40005200 Count: 9 */\r
+ 0x4000520Au, /* Base address: 0x40005200 Count: 10 */\r
0x40006401u, /* Base address: 0x40006400 Count: 1 */\r
0x40006501u, /* Base address: 0x40006500 Count: 1 */\r
- 0x4001004Au, /* Base address: 0x40010000 Count: 74 */\r
- 0x40010134u, /* Base address: 0x40010100 Count: 52 */\r
- 0x40010252u, /* Base address: 0x40010200 Count: 82 */\r
- 0x40010355u, /* Base address: 0x40010300 Count: 85 */\r
- 0x40010449u, /* Base address: 0x40010400 Count: 73 */\r
- 0x40010555u, /* Base address: 0x40010500 Count: 85 */\r
- 0x4001060Eu, /* Base address: 0x40010600 Count: 14 */\r
- 0x40010747u, /* Base address: 0x40010700 Count: 71 */\r
- 0x40010903u, /* Base address: 0x40010900 Count: 3 */\r
- 0x40010B0Cu, /* Base address: 0x40010B00 Count: 12 */\r
- 0x40010C45u, /* Base address: 0x40010C00 Count: 69 */\r
- 0x40010D4Du, /* Base address: 0x40010D00 Count: 77 */\r
- 0x40010F04u, /* Base address: 0x40010F00 Count: 4 */\r
- 0x40011501u, /* Base address: 0x40011500 Count: 1 */\r
- 0x40011657u, /* Base address: 0x40011600 Count: 87 */\r
- 0x40011753u, /* Base address: 0x40011700 Count: 83 */\r
- 0x40011903u, /* Base address: 0x40011900 Count: 3 */\r
- 0x40011B02u, /* Base address: 0x40011B00 Count: 2 */\r
- 0x40014012u, /* Base address: 0x40014000 Count: 18 */\r
- 0x40014110u, /* Base address: 0x40014100 Count: 16 */\r
- 0x40014215u, /* Base address: 0x40014200 Count: 21 */\r
- 0x4001430Bu, /* Base address: 0x40014300 Count: 11 */\r
- 0x40014410u, /* Base address: 0x40014400 Count: 16 */\r
- 0x40014517u, /* Base address: 0x40014500 Count: 23 */\r
- 0x40014607u, /* Base address: 0x40014600 Count: 7 */\r
- 0x4001470Au, /* Base address: 0x40014700 Count: 10 */\r
- 0x4001480Cu, /* Base address: 0x40014800 Count: 12 */\r
- 0x4001490Bu, /* Base address: 0x40014900 Count: 11 */\r
- 0x4001500Bu, /* Base address: 0x40015000 Count: 11 */\r
- 0x40015102u, /* Base address: 0x40015100 Count: 2 */\r
+ 0x40010052u, /* Base address: 0x40010000 Count: 82 */\r
+ 0x40010139u, /* Base address: 0x40010100 Count: 57 */\r
+ 0x40010241u, /* Base address: 0x40010200 Count: 65 */\r
+ 0x4001035Cu, /* Base address: 0x40010300 Count: 92 */\r
+ 0x40010417u, /* Base address: 0x40010400 Count: 23 */\r
+ 0x40010560u, /* Base address: 0x40010500 Count: 96 */\r
+ 0x4001065Du, /* Base address: 0x40010600 Count: 93 */\r
+ 0x40010754u, /* Base address: 0x40010700 Count: 84 */\r
+ 0x40010804u, /* Base address: 0x40010800 Count: 4 */\r
+ 0x4001090Eu, /* Base address: 0x40010900 Count: 14 */\r
+ 0x40010B12u, /* Base address: 0x40010B00 Count: 18 */\r
+ 0x40010C47u, /* Base address: 0x40010C00 Count: 71 */\r
+ 0x40010D45u, /* Base address: 0x40010D00 Count: 69 */\r
+ 0x40010F05u, /* Base address: 0x40010F00 Count: 5 */\r
+ 0x40011505u, /* Base address: 0x40011500 Count: 5 */\r
+ 0x4001164Cu, /* Base address: 0x40011600 Count: 76 */\r
+ 0x4001174Bu, /* Base address: 0x40011700 Count: 75 */\r
+ 0x4001190Au, /* Base address: 0x40011900 Count: 10 */\r
+ 0x40011B03u, /* Base address: 0x40011B00 Count: 3 */\r
+ 0x40014019u, /* Base address: 0x40014000 Count: 25 */\r
+ 0x40014117u, /* Base address: 0x40014100 Count: 23 */\r
+ 0x4001420Fu, /* Base address: 0x40014200 Count: 15 */\r
+ 0x4001430Du, /* Base address: 0x40014300 Count: 13 */\r
+ 0x4001440Du, /* Base address: 0x40014400 Count: 13 */\r
+ 0x40014516u, /* Base address: 0x40014500 Count: 22 */\r
+ 0x40014608u, /* Base address: 0x40014600 Count: 8 */\r
+ 0x40014705u, /* Base address: 0x40014700 Count: 5 */\r
+ 0x40014807u, /* Base address: 0x40014800 Count: 7 */\r
+ 0x4001490Au, /* Base address: 0x40014900 Count: 10 */\r
+ 0x40014C01u, /* Base address: 0x40014C00 Count: 1 */\r
+ 0x40015005u, /* Base address: 0x40015000 Count: 5 */\r
+ 0x40015104u, /* Base address: 0x40015100 Count: 4 */\r
};\r
\r
static const cy_cfg_addrvalue_t CYCODE cy_cfg_data_table[] = {\r
{0x36u, 0x02u},\r
{0x7Eu, 0x02u},\r
{0x01u, 0x20u},\r
- {0x0Au, 0x36u},\r
- {0x00u, 0x13u},\r
- {0x01u, 0x05u},\r
- {0x19u, 0x04u},\r
+ {0x0Au, 0x1Bu},\r
+ {0x00u, 0x14u},\r
+ {0x01u, 0x01u},\r
+ {0x18u, 0x0Cu},\r
+ {0x19u, 0x08u},\r
{0x1Cu, 0x61u},\r
- {0x20u, 0xA8u},\r
- {0x21u, 0x60u},\r
- {0x30u, 0x09u},\r
- {0x31u, 0x0Au},\r
+ {0x20u, 0x60u},\r
+ {0x21u, 0xC0u},\r
+ {0x30u, 0x06u},\r
+ {0x31u, 0x0Cu},\r
{0x7Cu, 0x40u},\r
- {0x3Cu, 0x01u},\r
+ {0x23u, 0x02u},\r
{0x86u, 0x0Fu},\r
- {0x05u, 0x08u},\r
- {0x06u, 0x40u},\r
- {0x07u, 0x44u},\r
- {0x0Au, 0x10u},\r
- {0x0Cu, 0x55u},\r
- {0x0Du, 0x04u},\r
- {0x0Eu, 0xAAu},\r
- {0x0Fu, 0x09u},\r
- {0x11u, 0x4Du},\r
- {0x12u, 0x04u},\r
- {0x13u, 0xB2u},\r
- {0x16u, 0x20u},\r
- {0x1Au, 0x02u},\r
- {0x1Du, 0x20u},\r
- {0x1Fu, 0x90u},\r
- {0x22u, 0x01u},\r
- {0x2Au, 0x80u},\r
- {0x2Du, 0x10u},\r
- {0x2Eu, 0x08u},\r
- {0x2Fu, 0x22u},\r
- {0x30u, 0xC0u},\r
- {0x31u, 0xC0u},\r
- {0x32u, 0x0Cu},\r
- {0x33u, 0x03u},\r
- {0x34u, 0x30u},\r
- {0x35u, 0x3Cu},\r
- {0x36u, 0x03u},\r
- {0x3Eu, 0x55u},\r
- {0x3Fu, 0x15u},\r
+ {0x00u, 0x03u},\r
+ {0x01u, 0x09u},\r
+ {0x02u, 0x0Cu},\r
+ {0x03u, 0x24u},\r
+ {0x04u, 0x09u},\r
+ {0x06u, 0x06u},\r
+ {0x07u, 0x09u},\r
+ {0x08u, 0xFFu},\r
+ {0x09u, 0x40u},\r
+ {0x0Cu, 0x90u},\r
+ {0x0Eu, 0x60u},\r
+ {0x0Fu, 0x30u},\r
+ {0x10u, 0xFFu},\r
+ {0x11u, 0x09u},\r
+ {0x13u, 0x12u},\r
+ {0x14u, 0x05u},\r
+ {0x15u, 0x40u},\r
+ {0x16u, 0x0Au},\r
+ {0x1Bu, 0x01u},\r
+ {0x1Cu, 0x0Fu},\r
+ {0x1Eu, 0xF0u},\r
+ {0x1Fu, 0x06u},\r
+ {0x20u, 0x50u},\r
+ {0x22u, 0xA0u},\r
+ {0x23u, 0x08u},\r
+ {0x25u, 0x80u},\r
+ {0x26u, 0xFFu},\r
+ {0x29u, 0x40u},\r
+ {0x2Cu, 0x30u},\r
+ {0x2Du, 0x40u},\r
+ {0x2Eu, 0xC0u},\r
+ {0x31u, 0x38u},\r
+ {0x32u, 0xFFu},\r
+ {0x33u, 0x40u},\r
+ {0x35u, 0x80u},\r
+ {0x37u, 0x07u},\r
+ {0x39u, 0x08u},\r
+ {0x3Eu, 0x04u},\r
+ {0x3Fu, 0x14u},\r
{0x58u, 0x04u},\r
{0x59u, 0x04u},\r
- {0x5Bu, 0x04u},\r
+ {0x5Cu, 0x10u},\r
{0x5Fu, 0x01u},\r
- {0x80u, 0x03u},\r
- {0x81u, 0x06u},\r
- {0x82u, 0x0Cu},\r
- {0x83u, 0x09u},\r
- {0x84u, 0x05u},\r
- {0x86u, 0x0Au},\r
- {0x87u, 0xFFu},\r
- {0x89u, 0x30u},\r
- {0x8Au, 0xFFu},\r
- {0x8Bu, 0xC0u},\r
- {0x8Cu, 0x0Fu},\r
- {0x8Du, 0x60u},\r
- {0x8Eu, 0xF0u},\r
- {0x8Fu, 0x90u},\r
- {0x90u, 0x90u},\r
- {0x91u, 0x0Fu},\r
- {0x92u, 0x60u},\r
- {0x93u, 0xF0u},\r
- {0x94u, 0xFFu},\r
- {0x95u, 0x50u},\r
- {0x97u, 0xA0u},\r
- {0x98u, 0xFFu},\r
- {0x99u, 0xFFu},\r
- {0xA1u, 0x03u},\r
- {0xA3u, 0x0Cu},\r
- {0xA4u, 0x50u},\r
- {0xA6u, 0xA0u},\r
- {0xA7u, 0xFFu},\r
- {0xA8u, 0x30u},\r
- {0xA9u, 0x05u},\r
- {0xAAu, 0xC0u},\r
- {0xABu, 0x0Au},\r
- {0xACu, 0x09u},\r
- {0xAEu, 0x06u},\r
- {0xB2u, 0xFFu},\r
- {0xB5u, 0xFFu},\r
- {0xBEu, 0x04u},\r
- {0xBFu, 0x10u},\r
+ {0x81u, 0x10u},\r
+ {0x83u, 0x20u},\r
+ {0x85u, 0x43u},\r
+ {0x86u, 0xC1u},\r
+ {0x87u, 0x04u},\r
+ {0x89u, 0x45u},\r
+ {0x8Au, 0x04u},\r
+ {0x8Bu, 0x02u},\r
+ {0x8Du, 0x08u},\r
+ {0x8Eu, 0x02u},\r
+ {0x90u, 0x24u},\r
+ {0x91u, 0x41u},\r
+ {0x92u, 0x90u},\r
+ {0x93u, 0x06u},\r
+ {0x95u, 0x04u},\r
+ {0x96u, 0x24u},\r
+ {0x97u, 0x03u},\r
+ {0x9Au, 0x18u},\r
+ {0x9Fu, 0x10u},\r
+ {0xA0u, 0x01u},\r
+ {0xA2u, 0x02u},\r
+ {0xA6u, 0x20u},\r
+ {0xA8u, 0x24u},\r
+ {0xAAu, 0x48u},\r
+ {0xABu, 0x20u},\r
+ {0xB1u, 0x08u},\r
+ {0xB2u, 0xE0u},\r
+ {0xB3u, 0x07u},\r
+ {0xB4u, 0x1Cu},\r
+ {0xB5u, 0x30u},\r
+ {0xB6u, 0x03u},\r
+ {0xB7u, 0x40u},\r
+ {0xBBu, 0x08u},\r
+ {0xBEu, 0x40u},\r
+ {0xBFu, 0x51u},\r
{0xD8u, 0x04u},\r
{0xD9u, 0x04u},\r
+ {0xDCu, 0x01u},\r
{0xDFu, 0x01u},\r
- {0x00u, 0x08u},\r
- {0x01u, 0x10u},\r
- {0x03u, 0x01u},\r
- {0x05u, 0x02u},\r
- {0x06u, 0x28u},\r
- {0x07u, 0x03u},\r
- {0x08u, 0x01u},\r
- {0x0Au, 0x14u},\r
- {0x0Eu, 0x60u},\r
- {0x0Fu, 0x04u},\r
- {0x10u, 0x08u},\r
- {0x11u, 0x41u},\r
- {0x14u, 0x01u},\r
- {0x16u, 0x02u},\r
- {0x17u, 0x24u},\r
- {0x19u, 0x18u},\r
- {0x1Au, 0x80u},\r
- {0x1Bu, 0x80u},\r
- {0x1Du, 0x04u},\r
- {0x20u, 0x80u},\r
- {0x23u, 0x14u},\r
- {0x26u, 0x20u},\r
- {0x29u, 0x40u},\r
- {0x2Cu, 0x20u},\r
- {0x2Du, 0x13u},\r
- {0x2Eu, 0x20u},\r
- {0x33u, 0x41u},\r
- {0x34u, 0x10u},\r
- {0x36u, 0x10u},\r
- {0x37u, 0x06u},\r
- {0x39u, 0x88u},\r
- {0x3Cu, 0x20u},\r
- {0x3Eu, 0x42u},\r
- {0x3Fu, 0x04u},\r
- {0x41u, 0xC0u},\r
- {0x68u, 0x10u},\r
- {0x69u, 0x40u},\r
- {0x6Au, 0x54u},\r
- {0x6Bu, 0x64u},\r
- {0x70u, 0x18u},\r
- {0x71u, 0x41u},\r
- {0x80u, 0x08u},\r
- {0x8Bu, 0x80u},\r
- {0x8Eu, 0x40u},\r
- {0xC0u, 0xF7u},\r
- {0xC2u, 0x7Eu},\r
- {0xC4u, 0xEBu},\r
- {0xCAu, 0xE8u},\r
- {0xCCu, 0xE9u},\r
- {0xCEu, 0xFAu},\r
- {0xE2u, 0x10u},\r
- {0xE6u, 0x05u},\r
- {0x01u, 0x03u},\r
- {0x03u, 0x0Cu},\r
- {0x04u, 0x30u},\r
- {0x06u, 0xC0u},\r
- {0x07u, 0xFFu},\r
- {0x0Au, 0xFFu},\r
- {0x0Bu, 0xFFu},\r
- {0x0Cu, 0x06u},\r
- {0x0Du, 0x90u},\r
- {0x0Eu, 0x09u},\r
- {0x0Fu, 0x60u},\r
- {0x10u, 0x60u},\r
- {0x11u, 0x0Fu},\r
- {0x12u, 0x90u},\r
- {0x13u, 0xF0u},\r
- {0x15u, 0x50u},\r
- {0x16u, 0xFFu},\r
- {0x17u, 0xA0u},\r
- {0x18u, 0xFFu},\r
- {0x19u, 0x30u},\r
- {0x1Bu, 0xC0u},\r
- {0x1Cu, 0x03u},\r
- {0x1Eu, 0x0Cu},\r
- {0x20u, 0x0Fu},\r
- {0x21u, 0x09u},\r
- {0x22u, 0xF0u},\r
- {0x23u, 0x06u},\r
- {0x24u, 0x50u},\r
- {0x26u, 0xA0u},\r
- {0x27u, 0xFFu},\r
- {0x28u, 0x05u},\r
- {0x29u, 0x05u},\r
- {0x2Au, 0x0Au},\r
- {0x2Bu, 0x0Au},\r
- {0x34u, 0xFFu},\r
- {0x35u, 0xFFu},\r
- {0x3Eu, 0x10u},\r
+ {0x00u, 0x80u},\r
+ {0x02u, 0xA0u},\r
+ {0x03u, 0x08u},\r
+ {0x05u, 0x14u},\r
+ {0x07u, 0x01u},\r
+ {0x08u, 0x40u},\r
+ {0x09u, 0x05u},\r
+ {0x0Au, 0x01u},\r
+ {0x0Du, 0x25u},\r
+ {0x0Fu, 0x08u},\r
+ {0x11u, 0x84u},\r
+ {0x12u, 0x04u},\r
+ {0x13u, 0x22u},\r
+ {0x14u, 0x40u},\r
+ {0x15u, 0x20u},\r
+ {0x16u, 0x20u},\r
+ {0x18u, 0x10u},\r
+ {0x1Du, 0x24u},\r
+ {0x1Eu, 0x20u},\r
+ {0x1Fu, 0x80u},\r
+ {0x20u, 0x20u},\r
+ {0x22u, 0xD0u},\r
+ {0x23u, 0xC0u},\r
+ {0x24u, 0x40u},\r
+ {0x25u, 0x80u},\r
+ {0x26u, 0x04u},\r
+ {0x27u, 0x28u},\r
+ {0x28u, 0x08u},\r
+ {0x2Au, 0x02u},\r
+ {0x2Bu, 0x22u},\r
+ {0x2Cu, 0x04u},\r
+ {0x31u, 0x01u},\r
+ {0x32u, 0x44u},\r
+ {0x33u, 0x10u},\r
+ {0x36u, 0x06u},\r
+ {0x37u, 0x80u},\r
+ {0x38u, 0x10u},\r
+ {0x39u, 0x0Au},\r
+ {0x3Bu, 0x40u},\r
+ {0x3Eu, 0x05u},\r
+ {0x3Fu, 0x90u},\r
+ {0x46u, 0x40u},\r
+ {0x47u, 0x01u},\r
+ {0x86u, 0x20u},\r
+ {0x87u, 0x02u},\r
+ {0x88u, 0x08u},\r
+ {0x8Cu, 0x40u},\r
+ {0x8Du, 0x01u},\r
+ {0x8Fu, 0x08u},\r
+ {0xC0u, 0xEFu},\r
+ {0xC2u, 0x7Du},\r
+ {0xC4u, 0x7Du},\r
+ {0xCAu, 0x2Fu},\r
+ {0xCCu, 0xDFu},\r
+ {0xCEu, 0xFFu},\r
+ {0xE2u, 0x08u},\r
+ {0xE6u, 0x72u},\r
+ {0x21u, 0x01u},\r
+ {0x35u, 0x01u},\r
{0x3Fu, 0x10u},\r
- {0x56u, 0x08u},\r
- {0x58u, 0x04u},\r
{0x59u, 0x04u},\r
{0x5Bu, 0x04u},\r
- {0x5Du, 0x90u},\r
{0x5Fu, 0x01u},\r
- {0x84u, 0x0Du},\r
- {0x87u, 0x06u},\r
- {0x88u, 0x0Du},\r
- {0x8Bu, 0x08u},\r
- {0x8Cu, 0x0Du},\r
- {0x92u, 0x10u},\r
- {0x94u, 0x80u},\r
- {0x95u, 0x09u},\r
- {0x97u, 0x52u},\r
- {0x98u, 0x02u},\r
- {0x9Au, 0x54u},\r
- {0x9Cu, 0x02u},\r
- {0x9Eu, 0x0Du},\r
- {0x9Fu, 0x30u},\r
- {0xA0u, 0x0Du},\r
- {0xA1u, 0x09u},\r
- {0xA3u, 0x24u},\r
- {0xA4u, 0x01u},\r
- {0xA6u, 0x32u},\r
- {0xA7u, 0x01u},\r
- {0xA8u, 0x62u},\r
- {0xAAu, 0x08u},\r
- {0xABu, 0x49u},\r
- {0xACu, 0x0Du},\r
- {0xB0u, 0x70u},\r
- {0xB3u, 0x07u},\r
+ {0x80u, 0x80u},\r
+ {0x81u, 0x40u},\r
+ {0x84u, 0x02u},\r
+ {0x85u, 0x01u},\r
+ {0x8Au, 0x1Fu},\r
+ {0x8Bu, 0x20u},\r
+ {0x8Cu, 0x5Bu},\r
+ {0x8Du, 0x80u},\r
+ {0x8Eu, 0x24u},\r
+ {0x94u, 0x03u},\r
+ {0x95u, 0x08u},\r
+ {0x96u, 0x0Cu},\r
+ {0x97u, 0x12u},\r
+ {0x98u, 0x58u},\r
+ {0x99u, 0x0Bu},\r
+ {0x9Au, 0x24u},\r
+ {0x9Bu, 0x24u},\r
+ {0xA0u, 0x0Cu},\r
+ {0xA1u, 0x34u},\r
+ {0xA2u, 0x40u},\r
+ {0xA3u, 0x0Bu},\r
+ {0xA6u, 0x01u},\r
+ {0xA8u, 0x40u},\r
+ {0xAAu, 0x37u},\r
+ {0xABu, 0x3Fu},\r
+ {0xB0u, 0x1Fu},\r
+ {0xB1u, 0x80u},\r
+ {0xB2u, 0x20u},\r
+ {0xB3u, 0x38u},\r
{0xB4u, 0x80u},\r
- {0xB5u, 0x40u},\r
- {0xB6u, 0x0Fu},\r
- {0xB7u, 0x38u},\r
- {0xBAu, 0x80u},\r
- {0xBEu, 0x10u},\r
- {0xBFu, 0x10u},\r
- {0xD8u, 0x0Bu},\r
+ {0xB5u, 0x07u},\r
+ {0xB6u, 0x40u},\r
+ {0xB7u, 0x40u},\r
+ {0xBEu, 0x54u},\r
+ {0xBFu, 0x41u},\r
+ {0xC0u, 0x64u},\r
+ {0xC1u, 0x02u},\r
+ {0xC2u, 0x30u},\r
+ {0xC5u, 0xCDu},\r
+ {0xC6u, 0x2Eu},\r
+ {0xC7u, 0x0Fu},\r
+ {0xC8u, 0x1Fu},\r
+ {0xC9u, 0xFFu},\r
+ {0xCAu, 0xFFu},\r
+ {0xCBu, 0xFFu},\r
+ {0xCFu, 0x2Cu},\r
+ {0xD6u, 0x01u},\r
+ {0xD8u, 0x04u},\r
{0xD9u, 0x04u},\r
+ {0xDAu, 0x04u},\r
{0xDBu, 0x04u},\r
- {0xDCu, 0x19u},\r
+ {0xDCu, 0x11u},\r
+ {0xDDu, 0x01u},\r
{0xDFu, 0x01u},\r
- {0x03u, 0x19u},\r
- {0x06u, 0x0Au},\r
- {0x07u, 0x20u},\r
- {0x08u, 0x04u},\r
+ {0xE2u, 0xC0u},\r
+ {0xE6u, 0x80u},\r
+ {0xE8u, 0x40u},\r
+ {0xE9u, 0x40u},\r
+ {0xEEu, 0x08u},\r
+ {0x00u, 0x02u},\r
+ {0x01u, 0x08u},\r
+ {0x03u, 0x0Au},\r
{0x09u, 0x20u},\r
- {0x0Au, 0x81u},\r
- {0x0Eu, 0x50u},\r
- {0x0Fu, 0x05u},\r
+ {0x0Bu, 0x20u},\r
{0x10u, 0x80u},\r
- {0x11u, 0x40u},\r
- {0x13u, 0x18u},\r
- {0x14u, 0x40u},\r
- {0x15u, 0x10u},\r
- {0x17u, 0x06u},\r
- {0x19u, 0x20u},\r
- {0x1Au, 0x81u},\r
- {0x1Eu, 0x04u},\r
- {0x20u, 0x04u},\r
- {0x21u, 0x84u},\r
- {0x25u, 0x10u},\r
- {0x28u, 0x80u},\r
- {0x2Au, 0x10u},\r
- {0x2Bu, 0x10u},\r
- {0x2Cu, 0x20u},\r
- {0x2Du, 0x10u},\r
- {0x2Eu, 0x0Au},\r
- {0x31u, 0x80u},\r
- {0x32u, 0x04u},\r
- {0x37u, 0xE6u},\r
- {0x39u, 0x08u},\r
- {0x3Au, 0x20u},\r
- {0x3Du, 0x03u},\r
- {0x3Eu, 0x50u},\r
- {0x3Fu, 0x05u},\r
- {0x58u, 0x10u},\r
- {0x5Au, 0x10u},\r
- {0x5Fu, 0x80u},\r
- {0x61u, 0x01u},\r
- {0x62u, 0x02u},\r
- {0x64u, 0x02u},\r
- {0x6Bu, 0x02u},\r
- {0x6Cu, 0x02u},\r
- {0x78u, 0x02u},\r
- {0x82u, 0x02u},\r
- {0x83u, 0x10u},\r
- {0x84u, 0x80u},\r
- {0x86u, 0xA0u},\r
- {0x88u, 0x04u},\r
- {0x89u, 0x10u},\r
- {0x8Bu, 0x40u},\r
- {0x8Cu, 0x04u},\r
+ {0x11u, 0x04u},\r
+ {0x12u, 0x08u},\r
+ {0x18u, 0x04u},\r
+ {0x19u, 0x42u},\r
+ {0x1Au, 0x10u},\r
+ {0x1Bu, 0x02u},\r
+ {0x21u, 0x34u},\r
+ {0x22u, 0x09u},\r
+ {0x23u, 0x05u},\r
+ {0x27u, 0x04u},\r
+ {0x29u, 0x02u},\r
+ {0x2Bu, 0x08u},\r
+ {0x2Cu, 0x08u},\r
+ {0x2Du, 0x20u},\r
+ {0x2Fu, 0x80u},\r
+ {0x31u, 0x20u},\r
+ {0x32u, 0x08u},\r
+ {0x38u, 0x20u},\r
+ {0x39u, 0x85u},\r
+ {0x41u, 0x11u},\r
+ {0x42u, 0x10u},\r
+ {0x43u, 0x02u},\r
+ {0x48u, 0x90u},\r
+ {0x49u, 0x08u},\r
+ {0x4Au, 0x08u},\r
+ {0x50u, 0x58u},\r
+ {0x5Au, 0xA2u},\r
+ {0x5Bu, 0x04u},\r
+ {0x60u, 0x44u},\r
+ {0x61u, 0x08u},\r
+ {0x63u, 0x01u},\r
+ {0x69u, 0x10u},\r
+ {0x6Au, 0x40u},\r
+ {0x6Bu, 0x50u},\r
+ {0x6Du, 0x64u},\r
+ {0x71u, 0x10u},\r
+ {0x72u, 0x22u},\r
+ {0x73u, 0x40u},\r
+ {0x81u, 0x40u},\r
+ {0x82u, 0x40u},\r
+ {0x87u, 0x80u},\r
+ {0x89u, 0x05u},\r
+ {0x8Au, 0x80u},\r
+ {0x8Bu, 0x80u},\r
+ {0x8Cu, 0x08u},\r
{0x8Du, 0x40u},\r
- {0x90u, 0x20u},\r
+ {0x8Fu, 0x08u},\r
+ {0x90u, 0x40u},\r
+ {0x92u, 0x20u},\r
+ {0x93u, 0x20u},\r
+ {0x94u, 0x80u},\r
+ {0x95u, 0x2Eu},\r
+ {0x96u, 0x0Du},\r
+ {0x97u, 0x10u},\r
+ {0x9Au, 0x44u},\r
+ {0x9Bu, 0x80u},\r
+ {0x9Cu, 0x08u},\r
+ {0x9Du, 0x11u},\r
+ {0x9Eu, 0x22u},\r
+ {0x9Fu, 0x12u},\r
+ {0xA1u, 0x80u},\r
+ {0xA2u, 0x90u},\r
+ {0xA3u, 0x04u},\r
+ {0xA4u, 0x48u},\r
+ {0xA5u, 0x44u},\r
+ {0xA6u, 0x02u},\r
+ {0xA7u, 0x20u},\r
+ {0xABu, 0x40u},\r
+ {0xACu, 0x10u},\r
+ {0xAFu, 0x91u},\r
+ {0xB0u, 0x04u},\r
+ {0xB7u, 0x08u},\r
+ {0xC0u, 0x0Fu},\r
+ {0xC2u, 0x06u},\r
+ {0xC4u, 0x0Eu},\r
+ {0xCAu, 0x85u},\r
+ {0xCCu, 0x06u},\r
+ {0xCEu, 0x0Fu},\r
+ {0xD0u, 0x07u},\r
+ {0xD2u, 0x04u},\r
+ {0xD6u, 0x0Fu},\r
+ {0xD8u, 0x0Fu},\r
+ {0xE2u, 0x20u},\r
+ {0xE6u, 0x09u},\r
+ {0xEAu, 0x06u},\r
+ {0xEEu, 0x02u},\r
+ {0x85u, 0x02u},\r
+ {0x87u, 0x05u},\r
+ {0x8Fu, 0x02u},\r
+ {0x97u, 0x03u},\r
+ {0x9Au, 0x01u},\r
+ {0x9Fu, 0x0Cu},\r
+ {0xA1u, 0x02u},\r
+ {0xA2u, 0x04u},\r
+ {0xA3u, 0x08u},\r
+ {0xA4u, 0x05u},\r
+ {0xA6u, 0x0Au},\r
+ {0xAAu, 0x02u},\r
+ {0xAEu, 0x08u},\r
+ {0xB1u, 0x0Eu},\r
+ {0xB4u, 0x0Cu},\r
+ {0xB5u, 0x01u},\r
+ {0xB6u, 0x03u},\r
+ {0xBEu, 0x50u},\r
+ {0xBFu, 0x10u},\r
+ {0xD8u, 0x04u},\r
+ {0xD9u, 0x04u},\r
+ {0xDCu, 0x10u},\r
+ {0xDFu, 0x01u},\r
+ {0x01u, 0x41u},\r
+ {0x03u, 0x18u},\r
+ {0x04u, 0x80u},\r
+ {0x05u, 0x80u},\r
+ {0x08u, 0x48u},\r
+ {0x0Au, 0x86u},\r
+ {0x0Du, 0x80u},\r
+ {0x0Fu, 0x0Au},\r
+ {0x10u, 0x80u},\r
+ {0x12u, 0x02u},\r
+ {0x13u, 0x10u},\r
+ {0x14u, 0x01u},\r
+ {0x15u, 0x02u},\r
+ {0x17u, 0x28u},\r
+ {0x1Au, 0x82u},\r
+ {0x1Bu, 0x10u},\r
+ {0x1Fu, 0x90u},\r
+ {0x20u, 0x40u},\r
+ {0x22u, 0x10u},\r
+ {0x27u, 0x84u},\r
+ {0x29u, 0x02u},\r
+ {0x2Du, 0x02u},\r
+ {0x32u, 0x18u},\r
+ {0x33u, 0x40u},\r
+ {0x36u, 0x08u},\r
+ {0x37u, 0x80u},\r
+ {0x38u, 0x40u},\r
+ {0x39u, 0x10u},\r
+ {0x3Bu, 0x04u},\r
+ {0x3Fu, 0x44u},\r
+ {0x40u, 0x20u},\r
+ {0x42u, 0x04u},\r
+ {0x43u, 0x02u},\r
+ {0x49u, 0x04u},\r
+ {0x4Au, 0x02u},\r
+ {0x4Bu, 0x11u},\r
+ {0x50u, 0x08u},\r
+ {0x51u, 0x60u},\r
+ {0x53u, 0x01u},\r
+ {0x58u, 0x04u},\r
+ {0x59u, 0xA0u},\r
+ {0x5Au, 0x01u},\r
+ {0x61u, 0x40u},\r
+ {0x64u, 0x02u},\r
+ {0x67u, 0x02u},\r
+ {0x79u, 0x02u},\r
+ {0x7Au, 0x80u},\r
+ {0x7Du, 0x08u},\r
+ {0x7Eu, 0x10u},\r
+ {0x80u, 0x08u},\r
+ {0x83u, 0x05u},\r
+ {0x85u, 0x40u},\r
+ {0x88u, 0x20u},\r
+ {0x8Bu, 0x10u},\r
+ {0x8Fu, 0x80u},\r
+ {0x90u, 0x80u},\r
+ {0x91u, 0x14u},\r
{0x92u, 0x40u},\r
- {0x93u, 0x04u},\r
- {0x95u, 0x19u},\r
- {0x98u, 0x08u},\r
- {0x99u, 0x05u},\r
- {0x9Bu, 0x24u},\r
- {0x9Cu, 0x10u},\r
- {0x9Eu, 0x0Au},\r
- {0x9Fu, 0x02u},\r
- {0xA0u, 0x08u},\r
- {0xA2u, 0x20u},\r
- {0xA4u, 0x24u},\r
- {0xA5u, 0x80u},\r
- {0xACu, 0x40u},\r
- {0xADu, 0x08u},\r
- {0xB3u, 0x10u},\r
+ {0x93u, 0x44u},\r
+ {0x96u, 0x0Cu},\r
+ {0x97u, 0x10u},\r
+ {0x98u, 0x04u},\r
+ {0x99u, 0x62u},\r
+ {0x9Au, 0x44u},\r
+ {0x9Bu, 0x68u},\r
+ {0xA0u, 0x10u},\r
+ {0xA1u, 0x80u},\r
+ {0xA2u, 0x98u},\r
+ {0xA3u, 0x04u},\r
+ {0xA4u, 0x40u},\r
+ {0xA5u, 0x04u},\r
+ {0xA6u, 0x02u},\r
+ {0xA7u, 0x40u},\r
+ {0xA9u, 0x29u},\r
+ {0xABu, 0x20u},\r
+ {0xACu, 0x84u},\r
+ {0xADu, 0x40u},\r
+ {0xB0u, 0x01u},\r
+ {0xB2u, 0x01u},\r
+ {0xB3u, 0x28u},\r
{0xB5u, 0x10u},\r
- {0xC0u, 0xE7u},\r
- {0xC2u, 0xFFu},\r
- {0xC4u, 0x7Fu},\r
- {0xCAu, 0xE7u},\r
- {0xCCu, 0xEAu},\r
- {0xCEu, 0xF6u},\r
- {0xD6u, 0x10u},\r
- {0xD8u, 0x10u},\r
- {0xDEu, 0x01u},\r
- {0xE2u, 0x0Au},\r
- {0xE6u, 0x47u},\r
- {0xE8u, 0x02u},\r
- {0xEAu, 0x08u},\r
- {0xECu, 0x08u},\r
- {0xEEu, 0x80u},\r
- {0x01u, 0x44u},\r
- {0x05u, 0xE1u},\r
- {0x06u, 0x46u},\r
- {0x07u, 0x12u},\r
- {0x08u, 0x09u},\r
- {0x09u, 0x80u},\r
- {0x0Au, 0x12u},\r
- {0x0Bu, 0x5Fu},\r
- {0x0Du, 0x4Cu},\r
- {0x0Eu, 0x80u},\r
- {0x11u, 0x4Cu},\r
- {0x12u, 0x30u},\r
+ {0xB7u, 0x42u},\r
+ {0xC0u, 0x0Fu},\r
+ {0xC2u, 0x4Fu},\r
+ {0xC4u, 0xFBu},\r
+ {0xCAu, 0x81u},\r
+ {0xCCu, 0x5Eu},\r
+ {0xCEu, 0x5Eu},\r
+ {0xD0u, 0x07u},\r
+ {0xD2u, 0x0Cu},\r
+ {0xD6u, 0x0Fu},\r
+ {0xD8u, 0x08u},\r
+ {0xE0u, 0x80u},\r
+ {0xE2u, 0x40u},\r
+ {0xEAu, 0x03u},\r
+ {0xEEu, 0x54u},\r
+ {0x00u, 0x01u},\r
+ {0x03u, 0x9Fu},\r
+ {0x04u, 0x01u},\r
+ {0x07u, 0xFFu},\r
+ {0x08u, 0x04u},\r
+ {0x09u, 0x7Fu},\r
+ {0x0Bu, 0x80u},\r
+ {0x0Cu, 0x01u},\r
+ {0x0Du, 0x90u},\r
+ {0x0Fu, 0x40u},\r
+ {0x11u, 0x1Fu},\r
+ {0x12u, 0x40u},\r
+ {0x13u, 0x20u},\r
+ {0x14u, 0xA2u},\r
+ {0x15u, 0x80u},\r
{0x16u, 0x08u},\r
- {0x17u, 0x4Cu},\r
- {0x19u, 0xB1u},\r
- {0x1Au, 0x09u},\r
- {0x1Bu, 0x0Eu},\r
- {0x1Cu, 0x09u},\r
- {0x1Du, 0x4Cu},\r
- {0x1Eu, 0x24u},\r
- {0x20u, 0x40u},\r
- {0x21u, 0x08u},\r
- {0x22u, 0x80u},\r
- {0x23u, 0x20u},\r
- {0x25u, 0x44u},\r
- {0x26u, 0x01u},\r
- {0x27u, 0x08u},\r
- {0x30u, 0x38u},\r
- {0x31u, 0x10u},\r
- {0x33u, 0x61u},\r
- {0x34u, 0x07u},\r
- {0x35u, 0x0Fu},\r
- {0x36u, 0xC0u},\r
- {0x37u, 0x80u},\r
- {0x3Bu, 0x0Cu},\r
+ {0x18u, 0x08u},\r
+ {0x1Au, 0x61u},\r
+ {0x1Bu, 0x60u},\r
+ {0x1Cu, 0x01u},\r
+ {0x1Du, 0xC0u},\r
+ {0x1Fu, 0x02u},\r
+ {0x20u, 0x07u},\r
+ {0x21u, 0xC0u},\r
+ {0x22u, 0xD8u},\r
+ {0x23u, 0x01u},\r
+ {0x25u, 0xC0u},\r
+ {0x27u, 0x04u},\r
+ {0x28u, 0x01u},\r
+ {0x29u, 0xC0u},\r
+ {0x2Bu, 0x08u},\r
+ {0x2Cu, 0x10u},\r
+ {0x30u, 0xE0u},\r
+ {0x36u, 0x3Fu},\r
+ {0x37u, 0xFFu},\r
+ {0x38u, 0x80u},\r
{0x3Eu, 0x40u},\r
- {0x3Fu, 0x41u},\r
- {0x54u, 0x09u},\r
+ {0x3Fu, 0x40u},\r
{0x58u, 0x04u},\r
- {0x59u, 0x0Bu},\r
- {0x5Bu, 0x0Bu},\r
- {0x5Cu, 0x91u},\r
- {0x5Du, 0x90u},\r
+ {0x59u, 0x04u},\r
{0x5Fu, 0x01u},\r
- {0x82u, 0x38u},\r
- {0x85u, 0x04u},\r
- {0x88u, 0x01u},\r
- {0x89u, 0x04u},\r
- {0x8Au, 0x14u},\r
- {0x90u, 0x3Eu},\r
- {0x94u, 0x22u},\r
- {0x95u, 0x04u},\r
- {0x96u, 0x01u},\r
- {0x99u, 0x04u},\r
- {0x9Fu, 0x01u},\r
- {0xA4u, 0x09u},\r
- {0xA6u, 0x02u},\r
- {0xABu, 0x02u},\r
- {0xADu, 0x01u},\r
- {0xAFu, 0x02u},\r
- {0xB0u, 0x07u},\r
- {0xB1u, 0x03u},\r
- {0xB4u, 0x38u},\r
- {0xB7u, 0x04u},\r
- {0xB8u, 0x02u},\r
- {0xB9u, 0x80u},\r
- {0xBEu, 0x10u},\r
- {0xBFu, 0x41u},\r
- {0xD8u, 0x0Bu},\r
+ {0x80u, 0x56u},\r
+ {0x81u, 0x64u},\r
+ {0x84u, 0x52u},\r
+ {0x85u, 0x83u},\r
+ {0x86u, 0x04u},\r
+ {0x87u, 0x70u},\r
+ {0x88u, 0x50u},\r
+ {0x8Au, 0x06u},\r
+ {0x8Bu, 0xF5u},\r
+ {0x8Cu, 0x17u},\r
+ {0x8Du, 0x64u},\r
+ {0x8Eu, 0x28u},\r
+ {0x91u, 0x07u},\r
+ {0x93u, 0x90u},\r
+ {0x94u, 0x31u},\r
+ {0x95u, 0x40u},\r
+ {0x96u, 0x0Eu},\r
+ {0x97u, 0x02u},\r
+ {0x98u, 0x29u},\r
+ {0x99u, 0x24u},\r
+ {0x9Au, 0x16u},\r
+ {0x9Bu, 0x40u},\r
+ {0x9Du, 0x08u},\r
+ {0xA0u, 0x56u},\r
+ {0xA1u, 0x64u},\r
+ {0xA4u, 0x22u},\r
+ {0xA5u, 0x24u},\r
+ {0xA6u, 0x10u},\r
+ {0xA8u, 0x04u},\r
+ {0xABu, 0x64u},\r
+ {0xACu, 0x06u},\r
+ {0xADu, 0x08u},\r
+ {0xAEu, 0x50u},\r
+ {0xB0u, 0x40u},\r
+ {0xB1u, 0x71u},\r
+ {0xB2u, 0x30u},\r
+ {0xB3u, 0x07u},\r
+ {0xB4u, 0x0Fu},\r
+ {0xB5u, 0x08u},\r
+ {0xB7u, 0x80u},\r
+ {0xB8u, 0x20u},\r
+ {0xB9u, 0x20u},\r
+ {0xBAu, 0x08u},\r
+ {0xBBu, 0x0Cu},\r
+ {0xBEu, 0x01u},\r
+ {0xBFu, 0x40u},\r
+ {0xD4u, 0x40u},\r
+ {0xD6u, 0x04u},\r
+ {0xD8u, 0x04u},\r
{0xD9u, 0x04u},\r
{0xDBu, 0x04u},\r
- {0xDCu, 0x09u},\r
{0xDFu, 0x01u},\r
- {0x00u, 0x20u},\r
+ {0x01u, 0x01u},\r
{0x02u, 0x02u},\r
- {0x03u, 0x20u},\r
- {0x04u, 0x02u},\r
- {0x05u, 0x10u},\r
- {0x08u, 0x80u},\r
- {0x09u, 0x01u},\r
- {0x0Au, 0xA0u},\r
- {0x0Bu, 0x04u},\r
- {0x0Eu, 0x80u},\r
+ {0x03u, 0x18u},\r
+ {0x05u, 0x08u},\r
+ {0x07u, 0x49u},\r
+ {0x0Au, 0x04u},\r
+ {0x0Bu, 0x10u},\r
+ {0x0Cu, 0x80u},\r
+ {0x0Eu, 0x84u},\r
{0x0Fu, 0x10u},\r
- {0x10u, 0x40u},\r
- {0x11u, 0x08u},\r
- {0x17u, 0x08u},\r
- {0x19u, 0x20u},\r
- {0x1Au, 0x82u},\r
- {0x1Bu, 0x20u},\r
+ {0x10u, 0x98u},\r
+ {0x11u, 0x40u},\r
+ {0x15u, 0x82u},\r
+ {0x17u, 0x10u},\r
+ {0x18u, 0x08u},\r
+ {0x19u, 0x09u},\r
+ {0x1Au, 0x04u},\r
+ {0x1Bu, 0x02u},\r
+ {0x1Du, 0x40u},\r
{0x1Eu, 0x80u},\r
- {0x1Fu, 0x10u},\r
- {0x20u, 0x04u},\r
- {0x21u, 0x84u},\r
- {0x23u, 0x98u},\r
- {0x25u, 0x40u},\r
- {0x27u, 0x40u},\r
- {0x2Au, 0x0Bu},\r
- {0x2Cu, 0x02u},\r
- {0x2Fu, 0x04u},\r
- {0x30u, 0x80u},\r
- {0x31u, 0x10u},\r
- {0x33u, 0x09u},\r
- {0x35u, 0x04u},\r
- {0x36u, 0xA0u},\r
- {0x38u, 0x04u},\r
- {0x39u, 0x41u},\r
+ {0x21u, 0x01u},\r
+ {0x22u, 0x62u},\r
+ {0x23u, 0x18u},\r
+ {0x25u, 0x80u},\r
+ {0x28u, 0x10u},\r
+ {0x29u, 0x48u},\r
+ {0x2Bu, 0x88u},\r
+ {0x2Cu, 0xA0u},\r
+ {0x2Fu, 0x08u},\r
+ {0x30u, 0x28u},\r
+ {0x31u, 0x80u},\r
+ {0x32u, 0x02u},\r
+ {0x35u, 0x08u},\r
+ {0x36u, 0x22u},\r
+ {0x37u, 0x40u},\r
+ {0x38u, 0x08u},\r
+ {0x39u, 0x40u},\r
+ {0x3Au, 0x02u},\r
{0x3Bu, 0x10u},\r
- {0x3Du, 0x20u},\r
+ {0x3Du, 0x40u},\r
{0x3Eu, 0x04u},\r
- {0x58u, 0x20u},\r
- {0x59u, 0x09u},\r
- {0x5Bu, 0x80u},\r
- {0x61u, 0x80u},\r
- {0x65u, 0x08u},\r
- {0x66u, 0x14u},\r
- {0x67u, 0x04u},\r
- {0x6Cu, 0x20u},\r
- {0x6Fu, 0x06u},\r
- {0x78u, 0x02u},\r
- {0x7Cu, 0x02u},\r
- {0x82u, 0x80u},\r
- {0x85u, 0x40u},\r
- {0x86u, 0x01u},\r
- {0x87u, 0x02u},\r
- {0x90u, 0x20u},\r
- {0x91u, 0x80u},\r
- {0x92u, 0x24u},\r
- {0x93u, 0x40u},\r
- {0x95u, 0x40u},\r
- {0x96u, 0x18u},\r
- {0x97u, 0x10u},\r
- {0x98u, 0xCAu},\r
- {0x99u, 0x04u},\r
- {0x9Au, 0x80u},\r
- {0x9Eu, 0x10u},\r
- {0x9Fu, 0x59u},\r
- {0xA0u, 0x0Au},\r
- {0xA1u, 0x14u},\r
- {0xA2u, 0x22u},\r
- {0xA4u, 0xA4u},\r
- {0xA5u, 0x21u},\r
- {0xA7u, 0x08u},\r
- {0xA8u, 0x20u},\r
- {0xB1u, 0x20u},\r
- {0xB5u, 0x04u},\r
- {0xB6u, 0x50u},\r
- {0xC0u, 0x57u},\r
- {0xC2u, 0x3Fu},\r
- {0xC4u, 0x2Cu},\r
- {0xCAu, 0x33u},\r
- {0xCCu, 0x7Fu},\r
- {0xCEu, 0x6Fu},\r
- {0xD6u, 0x0Fu},\r
- {0xD8u, 0x08u},\r
- {0xDEu, 0x81u},\r
- {0xE2u, 0x01u},\r
- {0xEAu, 0x10u},\r
- {0x87u, 0x11u},\r
- {0x8Bu, 0x06u},\r
- {0x8Fu, 0x01u},\r
- {0x95u, 0x19u},\r
- {0x97u, 0x22u},\r
- {0x99u, 0x08u},\r
- {0xA1u, 0x21u},\r
- {0xA3u, 0x1Cu},\r
- {0xABu, 0x38u},\r
- {0xB3u, 0x38u},\r
- {0xB5u, 0x07u},\r
- {0xD9u, 0x04u},\r
- {0xDCu, 0x10u},\r
- {0xDFu, 0x01u},\r
- {0x04u, 0x04u},\r
- {0x05u, 0x10u},\r
- {0x07u, 0x42u},\r
- {0x0Eu, 0xA2u},\r
- {0x0Fu, 0x08u},\r
- {0x15u, 0x48u},\r
- {0x16u, 0x08u},\r
- {0x17u, 0x11u},\r
- {0x1Eu, 0xA0u},\r
- {0x20u, 0x28u},\r
- {0x21u, 0x10u},\r
- {0x22u, 0x04u},\r
- {0x27u, 0x02u},\r
- {0x28u, 0x88u},\r
- {0x2Fu, 0x1Au},\r
- {0x30u, 0x20u},\r
- {0x32u, 0x04u},\r
- {0x36u, 0x10u},\r
- {0x37u, 0x49u},\r
- {0x39u, 0x20u},\r
- {0x3Bu, 0x44u},\r
- {0x3Du, 0x41u},\r
- {0x3Eu, 0x01u},\r
- {0x3Fu, 0x18u},\r
- {0x45u, 0x22u},\r
- {0x46u, 0x20u},\r
- {0x47u, 0x08u},\r
- {0x4Du, 0x80u},\r
- {0x4Eu, 0x20u},\r
- {0x4Fu, 0x18u},\r
- {0x56u, 0x55u},\r
- {0x57u, 0x40u},\r
- {0x65u, 0x04u},\r
- {0x66u, 0x50u},\r
- {0x7Cu, 0x02u},\r
- {0x87u, 0x04u},\r
- {0x90u, 0x24u},\r
- {0x91u, 0x88u},\r
- {0x93u, 0x50u},\r
- {0x94u, 0x02u},\r
+ {0x3Fu, 0x11u},\r
+ {0x48u, 0x08u},\r
+ {0x49u, 0x20u},\r
+ {0x60u, 0x02u},\r
+ {0x61u, 0x20u},\r
+ {0x63u, 0xA0u},\r
+ {0x86u, 0x40u},\r
+ {0x88u, 0x01u},\r
+ {0x91u, 0x84u},\r
+ {0x92u, 0x60u},\r
+ {0x93u, 0x05u},\r
{0x95u, 0x41u},\r
- {0x96u, 0x18u},\r
- {0x97u, 0x0Cu},\r
- {0x98u, 0xCAu},\r
- {0x99u, 0x20u},\r
- {0x9Au, 0x80u},\r
- {0x9Bu, 0x08u},\r
- {0x9Du, 0x11u},\r
- {0x9Eu, 0x0Du},\r
- {0x9Fu, 0x11u},\r
- {0xA0u, 0x28u},\r
- {0xA2u, 0x02u},\r
- {0xA4u, 0x94u},\r
- {0xA5u, 0x20u},\r
- {0xA7u, 0x08u},\r
- {0xA8u, 0x20u},\r
- {0xAAu, 0x02u},\r
- {0xAFu, 0x10u},\r
- {0xB7u, 0x04u},\r
- {0xC0u, 0xF0u},\r
- {0xC2u, 0xF0u},\r
- {0xC4u, 0xF0u},\r
- {0xCAu, 0x75u},\r
- {0xCCu, 0xF6u},\r
- {0xCEu, 0xFEu},\r
- {0xD0u, 0xE0u},\r
- {0xD2u, 0x30u},\r
- {0xD8u, 0x70u},\r
- {0xDEu, 0x80u},\r
- {0xEAu, 0x08u},\r
- {0xEEu, 0x10u},\r
- {0x9Eu, 0x40u},\r
- {0x9Fu, 0x08u},\r
- {0xEAu, 0x08u},\r
- {0x9Eu, 0x40u},\r
- {0x9Fu, 0x08u},\r
- {0xABu, 0x01u},\r
- {0xAFu, 0x40u},\r
- {0xB0u, 0x04u},\r
- {0xB3u, 0x40u},\r
- {0xB5u, 0x01u},\r
- {0xB6u, 0x04u},\r
- {0xE2u, 0x01u},\r
- {0xE8u, 0x20u},\r
- {0xEAu, 0x49u},\r
- {0xEEu, 0x40u},\r
- {0x00u, 0x12u},\r
- {0x02u, 0x24u},\r
- {0x05u, 0x02u},\r
- {0x06u, 0x12u},\r
- {0x0Au, 0x0Cu},\r
- {0x0Eu, 0x02u},\r
- {0x11u, 0x06u},\r
- {0x13u, 0x08u},\r
- {0x16u, 0x60u},\r
- {0x17u, 0x0Du},\r
- {0x1Bu, 0x07u},\r
- {0x1Cu, 0x12u},\r
- {0x1Du, 0x07u},\r
- {0x1Eu, 0x48u},\r
- {0x1Fu, 0x08u},\r
- {0x20u, 0x01u},\r
- {0x21u, 0x02u},\r
- {0x25u, 0x01u},\r
- {0x26u, 0x10u},\r
- {0x27u, 0x02u},\r
- {0x29u, 0x10u},\r
- {0x30u, 0x01u},\r
- {0x32u, 0x70u},\r
- {0x33u, 0x08u},\r
- {0x34u, 0x0Eu},\r
- {0x35u, 0x10u},\r
- {0x37u, 0x07u},\r
- {0x3Eu, 0x01u},\r
- {0x3Fu, 0x14u},\r
- {0x40u, 0x31u},\r
- {0x41u, 0x04u},\r
- {0x42u, 0x60u},\r
- {0x45u, 0xEFu},\r
- {0x46u, 0x20u},\r
- {0x47u, 0xDCu},\r
- {0x48u, 0x3Bu},\r
- {0x49u, 0xFFu},\r
- {0x4Au, 0xFFu},\r
- {0x4Bu, 0xFFu},\r
- {0x4Fu, 0x2Cu},\r
- {0x56u, 0x01u},\r
+ {0x96u, 0x0Cu},\r
+ {0x97u, 0x10u},\r
+ {0x98u, 0x42u},\r
+ {0x99u, 0x06u},\r
+ {0x9Au, 0xC4u},\r
+ {0x9Bu, 0xA0u},\r
+ {0x9Cu, 0x01u},\r
+ {0x9Fu, 0x10u},\r
+ {0xA0u, 0x08u},\r
+ {0xA1u, 0x20u},\r
+ {0xA2u, 0x98u},\r
+ {0xA3u, 0x15u},\r
+ {0xA4u, 0x80u},\r
+ {0xA5u, 0x40u},\r
+ {0xA6u, 0x02u},\r
+ {0xA7u, 0x4Au},\r
+ {0xAAu, 0x10u},\r
+ {0xACu, 0x50u},\r
+ {0xAEu, 0x81u},\r
+ {0xB4u, 0x40u},\r
+ {0xC0u, 0xFFu},\r
+ {0xC2u, 0xF6u},\r
+ {0xC4u, 0xDFu},\r
+ {0xCAu, 0xEFu},\r
+ {0xCCu, 0xFFu},\r
+ {0xCEu, 0xFFu},\r
+ {0xD8u, 0x0Fu},\r
+ {0xE2u, 0x09u},\r
+ {0xE6u, 0x08u},\r
+ {0xEAu, 0x02u},\r
+ {0xECu, 0x04u},\r
+ {0x38u, 0x80u},\r
+ {0x3Eu, 0x40u},\r
+ {0x58u, 0x04u},\r
+ {0x5Fu, 0x01u},\r
+ {0x1Fu, 0x80u},\r
+ {0x8Au, 0x04u},\r
+ {0x92u, 0x0Cu},\r
+ {0x97u, 0x01u},\r
+ {0x9Bu, 0x80u},\r
+ {0x9Cu, 0x02u},\r
+ {0x9Du, 0x20u},\r
+ {0xA3u, 0x08u},\r
+ {0xAAu, 0x04u},\r
+ {0xADu, 0x40u},\r
+ {0xB5u, 0x08u},\r
+ {0xE2u, 0x09u},\r
+ {0xE6u, 0x28u},\r
+ {0xE8u, 0x40u},\r
+ {0x92u, 0x0Cu},\r
+ {0x97u, 0x01u},\r
+ {0x9Bu, 0x80u},\r
+ {0x9Cu, 0x02u},\r
+ {0x9Du, 0x28u},\r
+ {0xA1u, 0x40u},\r
+ {0xA3u, 0x08u},\r
+ {0xA6u, 0x04u},\r
+ {0xA8u, 0x40u},\r
+ {0xA9u, 0x04u},\r
+ {0xAEu, 0x04u},\r
+ {0xB0u, 0x20u},\r
+ {0xB1u, 0x01u},\r
+ {0xB6u, 0x08u},\r
+ {0xB7u, 0x08u},\r
+ {0xE0u, 0x20u},\r
+ {0xEAu, 0x94u},\r
+ {0xEEu, 0xA4u},\r
+ {0x01u, 0x0Fu},\r
+ {0x03u, 0xF0u},\r
+ {0x04u, 0x50u},\r
+ {0x05u, 0x30u},\r
+ {0x06u, 0xA0u},\r
+ {0x07u, 0xC0u},\r
+ {0x08u, 0x06u},\r
+ {0x09u, 0x50u},\r
+ {0x0Au, 0x09u},\r
+ {0x0Bu, 0xA0u},\r
+ {0x0Cu, 0x03u},\r
+ {0x0Du, 0x60u},\r
+ {0x0Eu, 0x0Cu},\r
+ {0x0Fu, 0x90u},\r
+ {0x11u, 0xFFu},\r
+ {0x12u, 0xFFu},\r
+ {0x14u, 0xFFu},\r
+ {0x15u, 0x05u},\r
+ {0x17u, 0x0Au},\r
+ {0x18u, 0x05u},\r
+ {0x19u, 0x06u},\r
+ {0x1Au, 0x0Au},\r
+ {0x1Bu, 0x09u},\r
+ {0x1Cu, 0x0Fu},\r
+ {0x1Eu, 0xF0u},\r
+ {0x1Fu, 0xFFu},\r
+ {0x21u, 0x03u},\r
+ {0x22u, 0xFFu},\r
+ {0x23u, 0x0Cu},\r
+ {0x24u, 0x30u},\r
+ {0x26u, 0xC0u},\r
+ {0x27u, 0xFFu},\r
+ {0x2Cu, 0x60u},\r
+ {0x2Eu, 0x90u},\r
+ {0x35u, 0xFFu},\r
+ {0x36u, 0xFFu},\r
+ {0x3Eu, 0x40u},\r
+ {0x3Fu, 0x10u},\r
{0x58u, 0x04u},\r
{0x59u, 0x04u},\r
- {0x5Au, 0x04u},\r
{0x5Bu, 0x04u},\r
- {0x5Cu, 0x11u},\r
- {0x5Du, 0x01u},\r
{0x5Fu, 0x01u},\r
- {0x62u, 0xC0u},\r
- {0x66u, 0x80u},\r
- {0x68u, 0x40u},\r
- {0x69u, 0x40u},\r
- {0x6Eu, 0x08u},\r
- {0x81u, 0x02u},\r
- {0x84u, 0x02u},\r
- {0x89u, 0x01u},\r
- {0x8Du, 0x04u},\r
- {0xACu, 0x01u},\r
- {0xB3u, 0x01u},\r
- {0xB4u, 0x02u},\r
- {0xB5u, 0x02u},\r
- {0xB6u, 0x01u},\r
- {0xB7u, 0x04u},\r
- {0xBEu, 0x50u},\r
- {0xBFu, 0x54u},\r
+ {0x84u, 0x10u},\r
+ {0x86u, 0x09u},\r
+ {0x87u, 0x10u},\r
+ {0x8Bu, 0x08u},\r
+ {0x8Du, 0x0Au},\r
+ {0x8Fu, 0x14u},\r
+ {0x90u, 0x08u},\r
+ {0x92u, 0x10u},\r
+ {0x93u, 0x04u},\r
+ {0x94u, 0x04u},\r
+ {0x95u, 0x01u},\r
+ {0x9Cu, 0x19u},\r
+ {0x9Eu, 0x62u},\r
+ {0xA0u, 0x40u},\r
+ {0xA2u, 0x22u},\r
+ {0xABu, 0x02u},\r
+ {0xACu, 0x20u},\r
+ {0xAEu, 0x40u},\r
+ {0xB0u, 0x04u},\r
+ {0xB1u, 0x06u},\r
+ {0xB2u, 0x03u},\r
+ {0xB3u, 0x18u},\r
+ {0xB4u, 0x78u},\r
+ {0xB5u, 0x01u},\r
+ {0xBEu, 0x15u},\r
+ {0xBFu, 0x15u},\r
{0xD8u, 0x04u},\r
{0xD9u, 0x04u},\r
- {0xDBu, 0x04u},\r
{0xDFu, 0x01u},\r
{0x01u, 0x08u},\r
- {0x05u, 0x10u},\r
- {0x06u, 0x60u},\r
- {0x07u, 0x01u},\r
- {0x08u, 0x08u},\r
- {0x09u, 0x08u},\r
- {0x0Du, 0x80u},\r
- {0x0Eu, 0x20u},\r
- {0x10u, 0x10u},\r
- {0x12u, 0x22u},\r
+ {0x04u, 0x08u},\r
+ {0x05u, 0x20u},\r
+ {0x06u, 0x02u},\r
+ {0x09u, 0x06u},\r
+ {0x0Bu, 0x01u},\r
+ {0x0Cu, 0x01u},\r
+ {0x0Du, 0x50u},\r
+ {0x0Eu, 0x08u},\r
+ {0x0Fu, 0x21u},\r
+ {0x11u, 0x02u},\r
+ {0x12u, 0x01u},\r
{0x14u, 0x80u},\r
- {0x17u, 0x04u},\r
- {0x19u, 0xA0u},\r
- {0x1Cu, 0x40u},\r
- {0x1Du, 0x10u},\r
- {0x1Eu, 0x20u},\r
- {0x20u, 0x01u},\r
- {0x21u, 0x08u},\r
- {0x23u, 0x04u},\r
- {0x25u, 0x80u},\r
- {0x26u, 0xA8u},\r
- {0x2Cu, 0x04u},\r
- {0x2Du, 0x02u},\r
+ {0x15u, 0x44u},\r
+ {0x18u, 0xA0u},\r
+ {0x1Au, 0x08u},\r
+ {0x1Bu, 0x30u},\r
+ {0x1Fu, 0x80u},\r
+ {0x22u, 0x2Au},\r
+ {0x27u, 0x08u},\r
+ {0x29u, 0x20u},\r
{0x2Eu, 0x02u},\r
- {0x2Fu, 0x10u},\r
- {0x34u, 0x20u},\r
- {0x36u, 0x80u},\r
- {0x37u, 0x0Au},\r
- {0x39u, 0x20u},\r
- {0x3Bu, 0x81u},\r
+ {0x2Fu, 0x20u},\r
+ {0x31u, 0x08u},\r
+ {0x33u, 0x02u},\r
+ {0x34u, 0x83u},\r
+ {0x35u, 0x20u},\r
+ {0x36u, 0x04u},\r
+ {0x38u, 0x08u},\r
+ {0x39u, 0xA0u},\r
+ {0x3Du, 0x91u},\r
{0x3Eu, 0x04u},\r
- {0x3Fu, 0x08u},\r
- {0x45u, 0x80u},\r
- {0x46u, 0x60u},\r
- {0x47u, 0x0Au},\r
- {0x4Eu, 0x58u},\r
- {0x55u, 0x10u},\r
- {0x56u, 0x02u},\r
- {0x57u, 0x04u},\r
- {0x59u, 0x02u},\r
- {0x5Au, 0xA4u},\r
- {0x5Cu, 0x49u},\r
- {0x5Du, 0x20u},\r
- {0x64u, 0x10u},\r
- {0x65u, 0x80u},\r
- {0x67u, 0x44u},\r
- {0x6Eu, 0x08u},\r
- {0x6Fu, 0x45u},\r
- {0x74u, 0xA4u},\r
- {0x75u, 0x01u},\r
- {0x81u, 0x10u},\r
- {0x82u, 0x02u},\r
- {0x83u, 0x40u},\r
- {0x84u, 0xA0u},\r
- {0x85u, 0x80u},\r
- {0x88u, 0x04u},\r
- {0x89u, 0x10u},\r
- {0x8Au, 0x10u},\r
- {0x8Du, 0x18u},\r
- {0x93u, 0x20u},\r
- {0x98u, 0xA0u},\r
- {0xB0u, 0x80u},\r
- {0xC0u, 0xF4u},\r
- {0xC2u, 0xA0u},\r
- {0xC4u, 0x31u},\r
- {0xCAu, 0xE0u},\r
- {0xCCu, 0xF0u},\r
- {0xCEu, 0x4Du},\r
- {0xD0u, 0xD0u},\r
- {0xD2u, 0x20u},\r
- {0xD6u, 0xFFu},\r
- {0xD8u, 0xF0u},\r
- {0xE2u, 0xA1u},\r
- {0xE6u, 0x90u},\r
- {0xE8u, 0x42u},\r
- {0xEAu, 0x08u},\r
- {0xECu, 0x08u},\r
- {0x80u, 0x20u},\r
- {0x87u, 0x10u},\r
- {0xE0u, 0x80u},\r
- {0xE6u, 0x07u},\r
- {0xB4u, 0x04u},\r
- {0x00u, 0xD6u},\r
- {0x04u, 0xD2u},\r
- {0x05u, 0x40u},\r
- {0x06u, 0x04u},\r
- {0x07u, 0x30u},\r
- {0x08u, 0x29u},\r
- {0x09u, 0x58u},\r
- {0x0Au, 0x16u},\r
- {0x0Bu, 0x23u},\r
- {0x0Cu, 0x04u},\r
- {0x0Fu, 0x0Cu},\r
- {0x12u, 0x80u},\r
- {0x14u, 0x31u},\r
- {0x16u, 0x0Eu},\r
- {0x17u, 0x01u},\r
- {0x1Bu, 0x82u},\r
- {0x1Cu, 0x22u},\r
- {0x1Eu, 0x10u},\r
- {0x20u, 0xD6u},\r
- {0x24u, 0x17u},\r
- {0x25u, 0x34u},\r
- {0x26u, 0x28u},\r
- {0x27u, 0x43u},\r
- {0x28u, 0xD0u},\r
- {0x29u, 0x11u},\r
- {0x2Au, 0x06u},\r
- {0x2Bu, 0x62u},\r
- {0x2Cu, 0x06u},\r
- {0x2Eu, 0xD0u},\r
- {0x30u, 0x40u},\r
- {0x32u, 0x80u},\r
- {0x33u, 0x80u},\r
- {0x34u, 0x0Fu},\r
- {0x35u, 0x70u},\r
- {0x36u, 0x30u},\r
- {0x37u, 0x0Fu},\r
- {0x38u, 0x20u},\r
- {0x39u, 0x02u},\r
- {0x3Au, 0x80u},\r
- {0x3Bu, 0x20u},\r
- {0x3Eu, 0x05u},\r
{0x3Fu, 0x01u},\r
+ {0x6Cu, 0x04u},\r
+ {0x6Du, 0xD6u},\r
+ {0x6Eu, 0x04u},\r
+ {0x6Fu, 0x0Au},\r
+ {0x74u, 0x20u},\r
+ {0x75u, 0x80u},\r
+ {0x76u, 0x11u},\r
+ {0x77u, 0x80u},\r
+ {0x82u, 0x20u},\r
+ {0x86u, 0x02u},\r
+ {0x88u, 0x80u},\r
+ {0x89u, 0x02u},\r
+ {0x8Au, 0x02u},\r
+ {0x8Cu, 0x10u},\r
+ {0x8Fu, 0x80u},\r
+ {0x9Cu, 0x02u},\r
+ {0x9Du, 0xA0u},\r
+ {0x9Eu, 0x10u},\r
+ {0x9Fu, 0x08u},\r
+ {0xA1u, 0x08u},\r
+ {0xA7u, 0x10u},\r
+ {0xAEu, 0x10u},\r
+ {0xB1u, 0x80u},\r
+ {0xB7u, 0x10u},\r
+ {0xC0u, 0xE4u},\r
+ {0xC2u, 0xFDu},\r
+ {0xC4u, 0xB9u},\r
+ {0xCAu, 0xC4u},\r
+ {0xCCu, 0xF3u},\r
+ {0xCEu, 0xFEu},\r
+ {0xE0u, 0xA2u},\r
+ {0xE2u, 0x50u},\r
+ {0xE4u, 0x20u},\r
+ {0xE6u, 0x98u},\r
+ {0xEAu, 0x14u},\r
+ {0xEEu, 0x82u},\r
+ {0x85u, 0x20u},\r
+ {0x87u, 0x08u},\r
+ {0x8Cu, 0x02u},\r
+ {0x8Du, 0x08u},\r
+ {0xE2u, 0x10u},\r
+ {0xAFu, 0x10u},\r
+ {0xB2u, 0x20u},\r
+ {0xB4u, 0x40u},\r
+ {0xEAu, 0x40u},\r
+ {0xECu, 0x02u},\r
+ {0x00u, 0x03u},\r
+ {0x02u, 0x0Cu},\r
+ {0x04u, 0x60u},\r
+ {0x05u, 0x01u},\r
+ {0x06u, 0x90u},\r
+ {0x07u, 0x02u},\r
+ {0x0Bu, 0x10u},\r
+ {0x0Cu, 0x0Fu},\r
+ {0x0Eu, 0xF0u},\r
+ {0x11u, 0x08u},\r
+ {0x13u, 0x10u},\r
+ {0x14u, 0x05u},\r
+ {0x16u, 0x0Au},\r
+ {0x17u, 0x01u},\r
+ {0x18u, 0x06u},\r
+ {0x1Au, 0x09u},\r
+ {0x1Bu, 0x06u},\r
+ {0x1Fu, 0x08u},\r
+ {0x20u, 0x50u},\r
+ {0x21u, 0x01u},\r
+ {0x22u, 0xA0u},\r
+ {0x23u, 0x04u},\r
+ {0x24u, 0x30u},\r
+ {0x26u, 0xC0u},\r
+ {0x2Fu, 0x01u},\r
+ {0x34u, 0xFFu},\r
+ {0x35u, 0x07u},\r
+ {0x37u, 0x18u},\r
+ {0x3Eu, 0x10u},\r
+ {0x3Fu, 0x40u},\r
{0x56u, 0x02u},\r
{0x57u, 0x28u},\r
- {0x58u, 0x0Bu},\r
- {0x59u, 0x0Bu},\r
- {0x5Bu, 0x0Bu},\r
- {0x5Cu, 0x99u},\r
- {0x5Du, 0x90u},\r
+ {0x58u, 0x04u},\r
+ {0x59u, 0x04u},\r
+ {0x5Bu, 0x04u},\r
+ {0x5Cu, 0x10u},\r
{0x5Fu, 0x01u},\r
- {0x84u, 0x05u},\r
- {0x86u, 0x0Au},\r
- {0x87u, 0x70u},\r
- {0x88u, 0x03u},\r
- {0x8Au, 0x0Cu},\r
- {0x8Bu, 0x80u},\r
- {0x8Cu, 0x30u},\r
- {0x8Eu, 0xC0u},\r
- {0x8Fu, 0x04u},\r
- {0x95u, 0x09u},\r
- {0x97u, 0x14u},\r
- {0x98u, 0x06u},\r
- {0x99u, 0x01u},\r
- {0x9Au, 0x09u},\r
+ {0x86u, 0xECu},\r
+ {0x87u, 0xFFu},\r
+ {0x8Bu, 0xFFu},\r
+ {0x8Du, 0x0Fu},\r
+ {0x8Eu, 0x01u},\r
+ {0x8Fu, 0xF0u},\r
+ {0x91u, 0x30u},\r
+ {0x93u, 0xC0u},\r
+ {0x98u, 0x04u},\r
+ {0x99u, 0x05u},\r
+ {0x9Au, 0x43u},\r
{0x9Bu, 0x0Au},\r
- {0x9Du, 0x40u},\r
- {0x9Fu, 0x80u},\r
- {0xA0u, 0x0Fu},\r
- {0xA1u, 0x0Eu},\r
- {0xA2u, 0xF0u},\r
- {0xA3u, 0x21u},\r
- {0xA4u, 0x60u},\r
- {0xA6u, 0x90u},\r
- {0xA8u, 0x50u},\r
- {0xAAu, 0xA0u},\r
- {0xABu, 0x07u},\r
- {0xAFu, 0x08u},\r
- {0xB1u, 0xC0u},\r
- {0xB2u, 0xFFu},\r
- {0xB3u, 0x38u},\r
- {0xB5u, 0x07u},\r
- {0xBEu, 0x04u},\r
- {0xBFu, 0x01u},\r
+ {0x9Du, 0x03u},\r
+ {0x9Eu, 0x12u},\r
+ {0x9Fu, 0x0Cu},\r
+ {0xA0u, 0xE0u},\r
+ {0xA1u, 0x50u},\r
+ {0xA3u, 0xA0u},\r
+ {0xA7u, 0xFFu},\r
+ {0xA8u, 0x88u},\r
+ {0xA9u, 0x09u},\r
+ {0xAAu, 0x03u},\r
+ {0xABu, 0x06u},\r
+ {0xACu, 0x21u},\r
+ {0xADu, 0x90u},\r
+ {0xAEu, 0x02u},\r
+ {0xAFu, 0x60u},\r
+ {0xB0u, 0xE0u},\r
+ {0xB3u, 0xFFu},\r
+ {0xB4u, 0x0Fu},\r
+ {0xB6u, 0x10u},\r
+ {0xBEu, 0x01u},\r
+ {0xBFu, 0x04u},\r
+ {0xD4u, 0x09u},\r
+ {0xD6u, 0x04u},\r
{0xD8u, 0x04u},\r
{0xD9u, 0x04u},\r
- {0xDCu, 0x10u},\r
+ {0xDBu, 0x04u},\r
{0xDFu, 0x01u},\r
- {0x00u, 0x08u},\r
- {0x01u, 0x20u},\r
- {0x02u, 0x02u},\r
- {0x05u, 0x10u},\r
- {0x06u, 0x01u},\r
- {0x07u, 0x50u},\r
- {0x0Bu, 0x08u},\r
- {0x0Eu, 0x02u},\r
- {0x0Fu, 0x90u},\r
- {0x10u, 0x48u},\r
- {0x12u, 0x10u},\r
- {0x15u, 0x50u},\r
- {0x17u, 0x09u},\r
- {0x1Au, 0x10u},\r
- {0x1Du, 0x37u},\r
- {0x1Eu, 0x03u},\r
+ {0x00u, 0x04u},\r
+ {0x01u, 0x80u},\r
+ {0x07u, 0xA2u},\r
+ {0x0Au, 0x04u},\r
+ {0x0Bu, 0x01u},\r
+ {0x0Eu, 0x20u},\r
+ {0x0Fu, 0x08u},\r
+ {0x10u, 0x40u},\r
+ {0x12u, 0x02u},\r
+ {0x13u, 0x10u},\r
+ {0x16u, 0x60u},\r
+ {0x18u, 0x44u},\r
+ {0x19u, 0x80u},\r
{0x1Fu, 0x10u},\r
- {0x20u, 0x04u},\r
- {0x21u, 0x05u},\r
- {0x22u, 0x10u},\r
- {0x23u, 0x04u},\r
- {0x24u, 0x02u},\r
- {0x25u, 0x51u},\r
- {0x26u, 0x08u},\r
- {0x28u, 0x88u},\r
+ {0x22u, 0x04u},\r
+ {0x25u, 0x40u},\r
+ {0x26u, 0x20u},\r
+ {0x28u, 0xA0u},\r
+ {0x29u, 0x10u},\r
{0x2Au, 0x80u},\r
- {0x2Eu, 0x20u},\r
- {0x2Fu, 0x10u},\r
- {0x30u, 0x40u},\r
- {0x32u, 0x14u},\r
+ {0x2Du, 0x02u},\r
+ {0x2Eu, 0x40u},\r
+ {0x30u, 0x01u},\r
+ {0x32u, 0x90u},\r
+ {0x35u, 0x10u},\r
{0x36u, 0x28u},\r
- {0x38u, 0x20u},\r
- {0x39u, 0x88u},\r
- {0x3Au, 0x10u},\r
- {0x3Bu, 0x08u},\r
- {0x3Du, 0x80u},\r
- {0x3Eu, 0x08u},\r
- {0x3Fu, 0x10u},\r
- {0x45u, 0x10u},\r
- {0x46u, 0x08u},\r
- {0x66u, 0x08u},\r
- {0x6Cu, 0x80u},\r
- {0x6Du, 0x50u},\r
- {0x6Fu, 0x58u},\r
- {0x77u, 0x01u},\r
- {0x7Cu, 0x02u},\r
- {0x83u, 0x12u},\r
- {0x8Du, 0x01u},\r
- {0x90u, 0x20u},\r
- {0x91u, 0x80u},\r
- {0x92u, 0x08u},\r
- {0x93u, 0x10u},\r
- {0x94u, 0x02u},\r
- {0x95u, 0x42u},\r
- {0x96u, 0x11u},\r
- {0x97u, 0x24u},\r
- {0x98u, 0xCAu},\r
- {0x99u, 0x20u},\r
- {0x9Au, 0xA1u},\r
- {0x9Bu, 0x08u},\r
- {0x9Du, 0x15u},\r
+ {0x37u, 0x82u},\r
+ {0x39u, 0x84u},\r
+ {0x3Bu, 0x20u},\r
+ {0x3Du, 0x20u},\r
+ {0x3Eu, 0x20u},\r
+ {0x3Fu, 0x04u},\r
+ {0x59u, 0x25u},\r
+ {0x5Au, 0x80u},\r
+ {0x63u, 0x82u},\r
+ {0x66u, 0x04u},\r
+ {0x69u, 0x80u},\r
+ {0x6Bu, 0x02u},\r
+ {0x6Cu, 0x20u},\r
+ {0x6Du, 0x41u},\r
+ {0x6Fu, 0xD9u},\r
+ {0x74u, 0x80u},\r
+ {0x76u, 0x02u},\r
+ {0x81u, 0x40u},\r
+ {0x8Fu, 0x40u},\r
+ {0x91u, 0x04u},\r
+ {0x92u, 0xE4u},\r
+ {0x93u, 0x15u},\r
+ {0x95u, 0x41u},\r
+ {0x96u, 0x08u},\r
+ {0x98u, 0xE1u},\r
+ {0x99u, 0x27u},\r
+ {0x9Au, 0xC4u},\r
+ {0x9Bu, 0xA0u},\r
+ {0x9Eu, 0x02u},\r
{0x9Fu, 0x51u},\r
- {0xA0u, 0x0Cu},\r
- {0xA2u, 0x22u},\r
- {0xA3u, 0x40u},\r
- {0xA4u, 0x80u},\r
- {0xA5u, 0x22u},\r
- {0xA6u, 0x01u},\r
- {0xA7u, 0x0Au},\r
- {0xB0u, 0x10u},\r
- {0xB1u, 0x01u},\r
- {0xB5u, 0x80u},\r
- {0xC0u, 0xF7u},\r
- {0xC2u, 0xB2u},\r
- {0xC4u, 0xFEu},\r
- {0xCAu, 0x6Du},\r
- {0xCCu, 0x6Eu},\r
- {0xCEu, 0x7Eu},\r
- {0xD8u, 0x40u},\r
- {0xDEu, 0x80u},\r
- {0xE2u, 0x10u},\r
- {0xEAu, 0x20u},\r
- {0xECu, 0x40u},\r
- {0x9Fu, 0x08u},\r
- {0xB2u, 0x40u},\r
- {0xECu, 0x80u},\r
- {0xB7u, 0x08u},\r
- {0xECu, 0x40u},\r
- {0x30u, 0x20u},\r
- {0x33u, 0x02u},\r
- {0x34u, 0x04u},\r
- {0x35u, 0x20u},\r
- {0x38u, 0x80u},\r
- {0x56u, 0x80u},\r
- {0x5Bu, 0x02u},\r
- {0x5Eu, 0x01u},\r
- {0x63u, 0x40u},\r
- {0x65u, 0x04u},\r
- {0x81u, 0x20u},\r
- {0x8Du, 0x04u},\r
- {0xCCu, 0xF0u},\r
- {0xCEu, 0x10u},\r
- {0xD4u, 0x40u},\r
+ {0xA1u, 0x10u},\r
+ {0xA2u, 0x9Au},\r
+ {0xA3u, 0x05u},\r
+ {0xA4u, 0xA0u},\r
+ {0xA5u, 0x40u},\r
+ {0xA7u, 0x88u},\r
+ {0xB0u, 0xA0u},\r
+ {0xB5u, 0x10u},\r
+ {0xC0u, 0xB5u},\r
+ {0xC2u, 0x63u},\r
+ {0xC4u, 0x3Bu},\r
+ {0xCAu, 0x9Fu},\r
+ {0xCCu, 0xFDu},\r
+ {0xCEu, 0x6Eu},\r
+ {0xD6u, 0x0Fu},\r
+ {0xD8u, 0x49u},\r
+ {0xE0u, 0x01u},\r
+ {0xE6u, 0x40u},\r
+ {0xEEu, 0x06u},\r
+ {0x83u, 0x01u},\r
+ {0x97u, 0x01u},\r
+ {0x9Cu, 0x02u},\r
+ {0x9Du, 0x20u},\r
+ {0xABu, 0x80u},\r
+ {0xB2u, 0x04u},\r
+ {0xB3u, 0x08u},\r
+ {0xB7u, 0x80u},\r
+ {0xEAu, 0xA0u},\r
+ {0xEEu, 0x12u},\r
+ {0xACu, 0x02u},\r
+ {0xB1u, 0x20u},\r
+ {0xE8u, 0x20u},\r
+ {0x12u, 0x08u},\r
+ {0x15u, 0x80u},\r
+ {0x17u, 0x01u},\r
+ {0x33u, 0x01u},\r
+ {0x36u, 0x88u},\r
+ {0x38u, 0x01u},\r
+ {0x39u, 0x80u},\r
+ {0x3Cu, 0x04u},\r
+ {0x3Du, 0x80u},\r
+ {0x43u, 0x10u},\r
+ {0x50u, 0x80u},\r
+ {0x5Au, 0x04u},\r
+ {0x5Du, 0x02u},\r
+ {0x61u, 0x20u},\r
+ {0x64u, 0x08u},\r
+ {0x89u, 0x40u},\r
+ {0x8Cu, 0x01u},\r
+ {0x8Du, 0x20u},\r
+ {0xC4u, 0xE0u},\r
+ {0xCCu, 0xE0u},\r
+ {0xCEu, 0xF0u},\r
+ {0xD0u, 0x10u},\r
+ {0xD4u, 0x20u},\r
{0xD6u, 0xC0u},\r
{0xD8u, 0xC0u},\r
- {0xE6u, 0x80u},\r
- {0x51u, 0x02u},\r
- {0x56u, 0x20u},\r
- {0x5Eu, 0x01u},\r
- {0x5Fu, 0x20u},\r
- {0x8Eu, 0x20u},\r
- {0x94u, 0x80u},\r
- {0x97u, 0x40u},\r
- {0x9Cu, 0x04u},\r
- {0x9Eu, 0x80u},\r
- {0x9Fu, 0x02u},\r
- {0xA4u, 0x20u},\r
- {0xAFu, 0x02u},\r
- {0xB2u, 0x01u},\r
- {0xD4u, 0xC0u},\r
- {0xD6u, 0xA0u},\r
+ {0x31u, 0x20u},\r
+ {0x32u, 0x04u},\r
+ {0x36u, 0x40u},\r
+ {0x37u, 0x04u},\r
+ {0x50u, 0x08u},\r
+ {0x51u, 0x01u},\r
+ {0x55u, 0x08u},\r
+ {0x5Du, 0x02u},\r
+ {0x81u, 0x02u},\r
+ {0x89u, 0x01u},\r
+ {0x94u, 0x04u},\r
+ {0x96u, 0x04u},\r
+ {0x9Cu, 0x08u},\r
+ {0x9Fu, 0x10u},\r
+ {0xA6u, 0x80u},\r
+ {0xACu, 0x80u},\r
+ {0xADu, 0x02u},\r
+ {0xCCu, 0xF0u},\r
+ {0xD4u, 0xE0u},\r
+ {0xD6u, 0x80u},\r
+ {0xE6u, 0x20u},\r
{0xEAu, 0x10u},\r
- {0x10u, 0x20u},\r
- {0x80u, 0x40u},\r
- {0x83u, 0x80u},\r
- {0x86u, 0x81u},\r
- {0x87u, 0x02u},\r
- {0x94u, 0x80u},\r
- {0x96u, 0x01u},\r
- {0x97u, 0x40u},\r
- {0x9Bu, 0x40u},\r
- {0x9Cu, 0x04u},\r
- {0x9Eu, 0x80u},\r
- {0x9Fu, 0x02u},\r
- {0xA4u, 0x20u},\r
- {0xA5u, 0x02u},\r
- {0xABu, 0x20u},\r
- {0xB7u, 0x40u},\r
+ {0xEEu, 0x10u},\r
+ {0x12u, 0x80u},\r
+ {0x80u, 0x08u},\r
+ {0x86u, 0x04u},\r
+ {0x89u, 0x02u},\r
+ {0x8Cu, 0x08u},\r
+ {0x96u, 0x0Cu},\r
+ {0x9Cu, 0x08u},\r
+ {0x9Fu, 0x14u},\r
+ {0xA4u, 0x08u},\r
+ {0xA5u, 0x20u},\r
+ {0xA6u, 0xC0u},\r
+ {0xB4u, 0x04u},\r
+ {0xB5u, 0x08u},\r
{0xC4u, 0x10u},\r
- {0xE2u, 0xD0u},\r
- {0xE4u, 0x20u},\r
- {0xE6u, 0x40u},\r
- {0xEAu, 0x80u},\r
- {0x86u, 0x80u},\r
- {0x97u, 0x40u},\r
- {0x9Bu, 0x40u},\r
- {0xA1u, 0x80u},\r
- {0xA7u, 0x80u},\r
- {0xACu, 0x04u},\r
- {0xADu, 0x80u},\r
- {0xB5u, 0x02u},\r
- {0xE4u, 0x10u},\r
- {0xEAu, 0x10u},\r
- {0xEEu, 0x40u},\r
- {0x0Bu, 0x02u},\r
- {0x0Fu, 0x40u},\r
- {0x10u, 0x10u},\r
- {0x52u, 0x80u},\r
- {0x54u, 0x40u},\r
- {0x58u, 0x20u},\r
- {0x5Eu, 0x20u},\r
- {0x80u, 0x02u},\r
- {0x83u, 0x01u},\r
- {0x87u, 0x40u},\r
- {0x88u, 0x20u},\r
+ {0xE2u, 0xC0u},\r
+ {0x63u, 0x08u},\r
+ {0x83u, 0x04u},\r
+ {0x85u, 0x20u},\r
+ {0x86u, 0x04u},\r
+ {0x87u, 0x08u},\r
+ {0x96u, 0x08u},\r
+ {0x9Du, 0x02u},\r
+ {0x9Fu, 0x14u},\r
+ {0xA5u, 0x20u},\r
+ {0xA6u, 0x40u},\r
+ {0xD8u, 0x40u},\r
+ {0xE2u, 0x90u},\r
+ {0xE6u, 0x50u},\r
+ {0x09u, 0x80u},\r
+ {0x0Eu, 0x80u},\r
+ {0x13u, 0x01u},\r
+ {0x50u, 0x80u},\r
+ {0x51u, 0x02u},\r
+ {0x54u, 0x04u},\r
+ {0x56u, 0x01u},\r
+ {0x8Fu, 0x01u},\r
{0xC2u, 0x06u},\r
{0xC4u, 0x08u},\r
{0xD4u, 0x07u},\r
{0xD6u, 0x04u},\r
- {0xE0u, 0x01u},\r
- {0x00u, 0x20u},\r
- {0x06u, 0x40u},\r
- {0x07u, 0x04u},\r
- {0x09u, 0x02u},\r
- {0x0Bu, 0x04u},\r
+ {0xE6u, 0x08u},\r
+ {0x02u, 0x08u},\r
+ {0x05u, 0x40u},\r
+ {0x06u, 0x20u},\r
+ {0x08u, 0x24u},\r
+ {0x0Du, 0x08u},\r
{0x0Eu, 0x08u},\r
- {0x0Fu, 0x10u},\r
- {0x81u, 0x02u},\r
- {0x8Au, 0x40u},\r
- {0x8Bu, 0x04u},\r
- {0x8Eu, 0x04u},\r
- {0x9Cu, 0x02u},\r
- {0xA4u, 0x02u},\r
- {0xACu, 0x42u},\r
- {0xAEu, 0x10u},\r
- {0xB0u, 0x10u},\r
- {0xB6u, 0x80u},\r
+ {0x84u, 0x20u},\r
+ {0x85u, 0x02u},\r
+ {0x88u, 0x04u},\r
+ {0x8Cu, 0x80u},\r
+ {0x8Du, 0x88u},\r
+ {0x9Eu, 0x21u},\r
+ {0xA1u, 0x80u},\r
+ {0xA4u, 0x84u},\r
+ {0xA5u, 0x02u},\r
+ {0xAAu, 0x20u},\r
+ {0xAEu, 0x40u},\r
{0xC0u, 0x07u},\r
{0xC2u, 0x0Fu},\r
- {0xE2u, 0x02u},\r
- {0xE6u, 0x05u},\r
- {0xE8u, 0x02u},\r
- {0xEAu, 0x04u},\r
- {0x81u, 0x40u},\r
- {0x9Cu, 0x02u},\r
- {0xA4u, 0x02u},\r
- {0xABu, 0x04u},\r
- {0xAFu, 0x10u},\r
- {0xB0u, 0x10u},\r
- {0xEEu, 0x01u},\r
- {0x08u, 0x02u},\r
- {0x0Au, 0x01u},\r
- {0x0Cu, 0x02u},\r
- {0x0Du, 0x40u},\r
- {0x95u, 0x80u},\r
- {0x96u, 0x01u},\r
- {0x9Cu, 0x02u},\r
- {0xA4u, 0x02u},\r
- {0xAEu, 0x01u},\r
+ {0xE2u, 0x08u},\r
+ {0xE4u, 0x02u},\r
+ {0xE6u, 0x09u},\r
+ {0x88u, 0x04u},\r
+ {0xA4u, 0x04u},\r
+ {0xAAu, 0x0Cu},\r
+ {0xB1u, 0x40u},\r
+ {0xB6u, 0x01u},\r
+ {0xE0u, 0x04u},\r
+ {0xEAu, 0x01u},\r
+ {0xECu, 0x02u},\r
+ {0x0Bu, 0x88u},\r
+ {0x0Fu, 0x41u},\r
+ {0x83u, 0x01u},\r
+ {0x87u, 0x44u},\r
{0xC2u, 0x0Fu},\r
- {0x26u, 0x80u},\r
- {0x65u, 0x04u},\r
- {0x8Du, 0x04u},\r
- {0x9Bu, 0x40u},\r
+ {0x8Fu, 0x10u},\r
+ {0x9Du, 0x02u},\r
{0x9Fu, 0x10u},\r
- {0xA1u, 0x80u},\r
- {0xA6u, 0x80u},\r
- {0xA7u, 0x80u},\r
- {0xB3u, 0x40u},\r
- {0xB7u, 0x10u},\r
- {0xC8u, 0x20u},\r
- {0xD8u, 0x80u},\r
- {0x07u, 0x10u},\r
- {0x1Bu, 0x80u},\r
- {0x51u, 0x80u},\r
- {0x5Bu, 0x40u},\r
- {0x9Bu, 0x40u},\r
- {0x9Fu, 0x10u},\r
- {0xA1u, 0x80u},\r
- {0xA7u, 0x80u},\r
+ {0xA3u, 0x08u},\r
+ {0xABu, 0x04u},\r
+ {0xAEu, 0x40u},\r
+ {0xEEu, 0x60u},\r
+ {0x05u, 0x02u},\r
+ {0x57u, 0x08u},\r
+ {0x5Du, 0x40u},\r
+ {0x91u, 0x40u},\r
+ {0x9Du, 0x02u},\r
+ {0xA3u, 0x08u},\r
+ {0xB5u, 0x40u},\r
{0xC0u, 0x20u},\r
- {0xC6u, 0x40u},\r
- {0xD4u, 0xA0u},\r
- {0x00u, 0x02u},\r
- {0x01u, 0x01u},\r
- {0x08u, 0x02u},\r
- {0x09u, 0x01u},\r
- {0x0Au, 0x02u},\r
- {0x0Bu, 0x01u},\r
- {0x0Eu, 0x02u},\r
- {0x10u, 0x02u},\r
- {0x11u, 0x01u},\r
- {0x1Au, 0x02u},\r
- {0x1Bu, 0x01u},\r
- {0x00u, 0xABu},\r
- {0x01u, 0x02u},\r
+ {0xD4u, 0x40u},\r
+ {0xD6u, 0x20u},\r
+ {0xAFu, 0x40u},\r
+ {0x00u, 0x03u},\r
+ {0x08u, 0x03u},\r
+ {0x0Au, 0x03u},\r
+ {0x10u, 0x03u},\r
+ {0x1Au, 0x03u},\r
+ {0x00u, 0xFDu},\r
+ {0x01u, 0xABu},\r
+ {0x02u, 0x02u},\r
+ {0x10u, 0x55u},\r
};\r
\r
\r
/* address, size */\r
{(void CYFAR *)(CYREG_TMR0_CFG0), 12u},\r
{(void CYFAR *)(CYREG_PRT1_DR), 16u},\r
- {(void CYFAR *)(CYDEV_UCFG_B0_P0_U0_BASE), 1536u},\r
- {(void CYFAR *)(CYDEV_UCFG_B0_P3_U1_BASE), 2432u},\r
+ {(void CYFAR *)(CYDEV_UCFG_B0_P0_U0_BASE), 1024u},\r
+ {(void CYFAR *)(CYDEV_UCFG_B0_P2_U1_BASE), 2944u},\r
{(void CYFAR *)(CYDEV_UCFG_B1_P2_U0_BASE), 2048u},\r
{(void CYFAR *)(CYDEV_UCFG_DSI0_BASE), 2560u},\r
{(void CYFAR *)(CYDEV_UCFG_DSI12_BASE), 512u},\r
{(void CYFAR *)(CYREG_BCTL0_MDCLK_EN), 32u},\r
};\r
\r
- /* UDB_1_2_1_CONFIG Address: CYDEV_UCFG_B0_P3_U0_BASE Size (bytes): 128 */\r
- static const uint8 CYCODE BS_UDB_1_2_1_CONFIG_VAL[] = {\r
- 0x01u, 0x80u, 0x00u, 0x00u, 0x07u, 0x00u, 0x18u, 0x9Fu, 0x08u, 0x7Fu, 0x21u, 0x80u, 0x40u, 0x90u, 0x00u, 0x40u, \r
- 0x40u, 0xC0u, 0x00u, 0x01u, 0x04u, 0x1Fu, 0x00u, 0x20u, 0x10u, 0x00u, 0x00u, 0x60u, 0x01u, 0xC0u, 0x00u, 0x02u, \r
- 0x01u, 0x00u, 0x00u, 0x00u, 0x22u, 0x00u, 0x08u, 0xFFu, 0x01u, 0xC0u, 0x00u, 0x08u, 0x01u, 0xC0u, 0x00u, 0x04u, \r
- 0x3Fu, 0x00u, 0x40u, 0x00u, 0x00u, 0x00u, 0x00u, 0xFFu, 0x0Au, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x01u, 0x40u, \r
- 0x26u, 0x03u, 0x40u, 0x00u, 0x05u, 0x0Bu, 0xFDu, 0xCEu, 0x3Du, 0xFFu, 0xFFu, 0xFFu, 0x22u, 0x00u, 0xF0u, 0x08u, \r
- 0x04u, 0x00u, 0x00u, 0x00u, 0x40u, 0x00u, 0x00u, 0x00u, 0x0Bu, 0x04u, 0x0Bu, 0x0Bu, 0x09u, 0x99u, 0x00u, 0x01u, \r
+ /* UDB_1_3_0_CONFIG Address: CYDEV_UCFG_B0_P2_U0_BASE Size (bytes): 128 */\r
+ static const uint8 CYCODE BS_UDB_1_3_0_CONFIG_VAL[] = {\r
+ 0x8Du, 0x00u, 0x00u, 0x00u, 0x8Du, 0x09u, 0x00u, 0x12u, 0x8Du, 0x00u, 0x00u, 0x01u, 0x0Du, 0x00u, 0x80u, 0x30u, \r
+ 0x02u, 0x00u, 0x0Du, 0x00u, 0x00u, 0x00u, 0x80u, 0x09u, 0x12u, 0x00u, 0x44u, 0x06u, 0x60u, 0x00u, 0x00u, 0x08u, \r
+ 0x8Du, 0x09u, 0x00u, 0x24u, 0x00u, 0x00u, 0x00u, 0x00u, 0x22u, 0x00u, 0x18u, 0x00u, 0x11u, 0x00u, 0x22u, 0x00u, \r
+ 0x0Fu, 0x38u, 0x00u, 0x00u, 0x80u, 0x07u, 0x70u, 0x00u, 0x80u, 0x00u, 0x02u, 0x00u, 0x00u, 0x00u, 0x10u, 0x00u, \r
+ 0x26u, 0x05u, 0x40u, 0x00u, 0x03u, 0xBEu, 0xFBu, 0xDCu, 0x3Fu, 0xFFu, 0xFFu, 0xFFu, 0x22u, 0x00u, 0xF0u, 0x08u, \r
+ 0x04u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x04u, 0x04u, 0x04u, 0x04u, 0x10u, 0x00u, 0x00u, 0x01u, \r
0x00u, 0x00u, 0xC0u, 0x00u, 0x40u, 0x01u, 0x10u, 0x11u, 0xC0u, 0x01u, 0x00u, 0x11u, 0x40u, 0x01u, 0x40u, 0x01u, \r
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u};\r
\r
static const cfg_memcpy_t CYCODE cfg_memcpy_list [] = {\r
/* dest, src, size */\r
- {(void CYFAR *)(CYDEV_UCFG_B0_P3_U0_BASE), BS_UDB_1_2_1_CONFIG_VAL, 128u},\r
+ {(void CYFAR *)(CYDEV_UCFG_B0_P2_U0_BASE), BS_UDB_1_3_0_CONFIG_VAL, 128u},\r
};\r
\r
uint8 CYDATA i;\r
\r
cfg_write_bytes32(cy_cfg_addr_table, cy_cfg_data_table);\r
\r
+ /* Perform normal device configuration. Order is not critical for these items. */\r
+ CYMEMZERO((void CYFAR *)(CYREG_PHUB_CFGMEM0_CFG0), 4u);\r
+ CYCONFIGCPYCODE((void CYFAR *)(CYREG_PHUB_CFGMEM1_CFG0), (const void CYCODE *)(BS_PHUB_CFGMEM1_VAL), 4u);\r
+ CYCONFIGCPYCODE((void CYFAR *)(CYREG_PHUB_CFGMEM2_CFG0), (const void CYCODE *)(BS_PHUB_CFGMEM2_VAL), 4u);\r
+ CYCONFIGCPYCODE((void CYFAR *)(CYREG_PHUB_CFGMEM3_CFG0), (const void CYCODE *)(BS_PHUB_CFGMEM3_VAL), 4u);\r
+\r
/* Enable digital routing */\r
CY_SET_XTND_REG8((void CYFAR *)CYREG_BCTL0_BANK_CTL, CY_GET_XTND_REG8((void CYFAR *)CYREG_BCTL0_BANK_CTL) | 0x02u);\r
CY_SET_XTND_REG8((void CYFAR *)CYREG_BCTL1_BANK_CTL, CY_GET_XTND_REG8((void CYFAR *)CYREG_BCTL1_BANK_CTL) | 0x02u);\r
/* Debug_Timer_Interrupt */\r
.set Debug_Timer_Interrupt__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
.set Debug_Timer_Interrupt__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
-.set Debug_Timer_Interrupt__INTC_MASK, 0x01\r
-.set Debug_Timer_Interrupt__INTC_NUMBER, 0\r
+.set Debug_Timer_Interrupt__INTC_MASK, 0x02\r
+.set Debug_Timer_Interrupt__INTC_NUMBER, 1\r
.set Debug_Timer_Interrupt__INTC_PRIOR_NUM, 7\r
-.set Debug_Timer_Interrupt__INTC_PRIOR_REG, CYREG_NVIC_PRI_0\r
+.set Debug_Timer_Interrupt__INTC_PRIOR_REG, CYREG_NVIC_PRI_1\r
.set Debug_Timer_Interrupt__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
.set Debug_Timer_Interrupt__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
\r
+/* SCSI_RX_DMA_COMPLETE */\r
+.set SCSI_RX_DMA_COMPLETE__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
+.set SCSI_RX_DMA_COMPLETE__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
+.set SCSI_RX_DMA_COMPLETE__INTC_MASK, 0x01\r
+.set SCSI_RX_DMA_COMPLETE__INTC_NUMBER, 0\r
+.set SCSI_RX_DMA_COMPLETE__INTC_PRIOR_NUM, 7\r
+.set SCSI_RX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_0\r
+.set SCSI_RX_DMA_COMPLETE__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
+.set SCSI_RX_DMA_COMPLETE__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
+\r
+/* SCSI_TX_DMA_COMPLETE */\r
+.set SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
+.set SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
+.set SCSI_TX_DMA_COMPLETE__INTC_MASK, 0x04\r
+.set SCSI_TX_DMA_COMPLETE__INTC_NUMBER, 2\r
+.set SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM, 7\r
+.set SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_2\r
+.set SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
+.set SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
+\r
/* Debug_Timer_TimerHW */\r
.set Debug_Timer_TimerHW__CAP0, CYREG_TMR0_CAP0\r
.set Debug_Timer_TimerHW__CAP1, CYREG_TMR0_CAP1\r
.set Debug_Timer_TimerHW__RT1, CYREG_TMR0_RT1\r
.set Debug_Timer_TimerHW__SR0, CYREG_TMR0_SR0\r
\r
+/* SD_RX_DMA_COMPLETE */\r
+.set SD_RX_DMA_COMPLETE__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
+.set SD_RX_DMA_COMPLETE__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
+.set SD_RX_DMA_COMPLETE__INTC_MASK, 0x08\r
+.set SD_RX_DMA_COMPLETE__INTC_NUMBER, 3\r
+.set SD_RX_DMA_COMPLETE__INTC_PRIOR_NUM, 7\r
+.set SD_RX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_3\r
+.set SD_RX_DMA_COMPLETE__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
+.set SD_RX_DMA_COMPLETE__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
+\r
+/* SD_TX_DMA_COMPLETE */\r
+.set SD_TX_DMA_COMPLETE__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
+.set SD_TX_DMA_COMPLETE__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
+.set SD_TX_DMA_COMPLETE__INTC_MASK, 0x10\r
+.set SD_TX_DMA_COMPLETE__INTC_NUMBER, 4\r
+.set SD_TX_DMA_COMPLETE__INTC_PRIOR_NUM, 7\r
+.set SD_TX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_4\r
+.set SD_TX_DMA_COMPLETE__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
+.set SD_TX_DMA_COMPLETE__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
+\r
/* USBFS_bus_reset */\r
.set USBFS_bus_reset__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
.set USBFS_bus_reset__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
/* SCSI_CTL_PHASE */\r
.set SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK, 0x01\r
.set SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS, 0\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB05_06_ACTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB05_06_CTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB05_06_CTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB05_06_CTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB05_06_CTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB05_06_MSK\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB05_06_MSK\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB05_06_MSK\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB05_06_MSK\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB02_03_ACTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB02_03_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB02_03_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB02_03_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB02_03_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB02_03_MSK\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB02_03_MSK\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB02_03_MSK\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB02_03_MSK\r
.set SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK, 0x02\r
.set SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS, 1\r
.set SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK, 0x04\r
.set SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS, 2\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB05_ACTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB05_CTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB05_ST_CTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB05_CTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB05_ST_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB02_ACTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB02_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB02_ST_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB02_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB02_ST_CTL\r
.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK, 0x07\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB05_MSK_ACTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB05_MSK\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB05_MSK_ACTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB02_MSK_ACTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB02_MSK\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB02_MSK_ACTL\r
\r
/* SCSI_Out_Bits */\r
.set SCSI_Out_Bits_Sync_ctrl_reg__0__MASK, 0x01\r
.set SCSI_Out_Bits_Sync_ctrl_reg__0__POS, 0\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB00_01_ACTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB00_01_CTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB00_01_CTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB00_01_CTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB00_01_CTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB00_01_MSK\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB00_01_MSK\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB00_01_MSK\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB00_01_MSK\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB12_13_ACTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB12_13_CTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB12_13_CTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB12_13_CTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB12_13_CTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB12_13_MSK\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB12_13_MSK\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB12_13_MSK\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB12_13_MSK\r
.set SCSI_Out_Bits_Sync_ctrl_reg__1__MASK, 0x02\r
.set SCSI_Out_Bits_Sync_ctrl_reg__1__POS, 1\r
.set SCSI_Out_Bits_Sync_ctrl_reg__2__MASK, 0x04\r
.set SCSI_Out_Bits_Sync_ctrl_reg__6__POS, 6\r
.set SCSI_Out_Bits_Sync_ctrl_reg__7__MASK, 0x80\r
.set SCSI_Out_Bits_Sync_ctrl_reg__7__POS, 7\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB00_ACTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB00_CTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB00_ST_CTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB00_CTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB00_ST_CTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB12_ACTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB12_CTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB12_ST_CTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB12_CTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB12_ST_CTL\r
.set SCSI_Out_Bits_Sync_ctrl_reg__MASK, 0xFF\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB00_MSK_ACTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB00_MSK\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB00_MSK_ACTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB12_MSK\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL\r
\r
/* USBFS_arb_int */\r
.set USBFS_arb_int__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
/* SCSI_Out_Ctl */\r
.set SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK, 0x01\r
.set SCSI_Out_Ctl_Sync_ctrl_reg__0__POS, 0\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB03_04_ACTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB03_04_CTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB03_04_CTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB03_04_CTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB03_04_CTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB03_04_MSK\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB03_04_MSK\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB03_04_MSK\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB03_04_MSK\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB03_ACTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB03_CTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB03_ST_CTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB03_CTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB03_ST_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB07_08_ACTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB07_08_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB07_08_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB07_08_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB07_08_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B1_UDB07_08_MSK\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB07_08_MSK\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB07_08_MSK\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB07_08_MSK\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B1_UDB07_ACTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B1_UDB07_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B1_UDB07_ST_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B1_UDB07_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B1_UDB07_ST_CTL\r
.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK, 0x01\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB03_MSK\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB07_MSK_ACTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B1_UDB07_MSK\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB07_MSK_ACTL\r
\r
/* SCSI_Out_DBx */\r
.set SCSI_Out_DBx__0__AG, CYREG_PRT6_AG\r
.set SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB06_MSK_ACTL\r
.set SDCard_BSPIM_BitCounter__PERIOD_REG, CYREG_B1_UDB06_MSK\r
.set SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB06_MSK_ACTL\r
-.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB06_07_ACTL\r
-.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB06_07_ST\r
+.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB07_08_ACTL\r
+.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB07_08_ST\r
.set SDCard_BSPIM_RxStsReg__4__MASK, 0x10\r
.set SDCard_BSPIM_RxStsReg__4__POS, 4\r
.set SDCard_BSPIM_RxStsReg__5__MASK, 0x20\r
.set SDCard_BSPIM_RxStsReg__6__MASK, 0x40\r
.set SDCard_BSPIM_RxStsReg__6__POS, 6\r
.set SDCard_BSPIM_RxStsReg__MASK, 0x70\r
-.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B0_UDB06_MSK\r
-.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB06_ACTL\r
-.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B0_UDB06_ST\r
+.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B0_UDB07_MSK\r
+.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB07_ACTL\r
+.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B0_UDB07_ST\r
.set SDCard_BSPIM_TxStsReg__0__MASK, 0x01\r
.set SDCard_BSPIM_TxStsReg__0__POS, 0\r
-.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB04_05_ACTL\r
-.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB04_05_ST\r
+.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB07_08_ACTL\r
+.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB07_08_ST\r
.set SDCard_BSPIM_TxStsReg__1__MASK, 0x02\r
.set SDCard_BSPIM_TxStsReg__1__POS, 1\r
.set SDCard_BSPIM_TxStsReg__2__MASK, 0x04\r
.set SDCard_BSPIM_TxStsReg__4__MASK, 0x10\r
.set SDCard_BSPIM_TxStsReg__4__POS, 4\r
.set SDCard_BSPIM_TxStsReg__MASK, 0x1F\r
-.set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B0_UDB04_MSK\r
-.set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB04_ACTL\r
-.set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B0_UDB04_ST\r
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG, CYREG_B0_UDB06_07_A0\r
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG, CYREG_B0_UDB06_07_A1\r
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG, CYREG_B0_UDB06_07_D0\r
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG, CYREG_B0_UDB06_07_D1\r
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG, CYREG_B0_UDB06_07_ACTL\r
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG, CYREG_B0_UDB06_07_F0\r
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG, CYREG_B0_UDB06_07_F1\r
-.set SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG, CYREG_B0_UDB06_A0_A1\r
-.set SDCard_BSPIM_sR8_Dp_u0__A0_REG, CYREG_B0_UDB06_A0\r
-.set SDCard_BSPIM_sR8_Dp_u0__A1_REG, CYREG_B0_UDB06_A1\r
-.set SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG, CYREG_B0_UDB06_D0_D1\r
-.set SDCard_BSPIM_sR8_Dp_u0__D0_REG, CYREG_B0_UDB06_D0\r
-.set SDCard_BSPIM_sR8_Dp_u0__D1_REG, CYREG_B0_UDB06_D1\r
-.set SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG, CYREG_B0_UDB06_ACTL\r
-.set SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG, CYREG_B0_UDB06_F0_F1\r
-.set SDCard_BSPIM_sR8_Dp_u0__F0_REG, CYREG_B0_UDB06_F0\r
-.set SDCard_BSPIM_sR8_Dp_u0__F1_REG, CYREG_B0_UDB06_F1\r
+.set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B1_UDB07_MSK\r
+.set SDCard_BSPIM_TxStsReg__MASK_ST_AUX_CTL_REG, CYREG_B1_UDB07_MSK_ACTL\r
+.set SDCard_BSPIM_TxStsReg__PER_ST_AUX_CTL_REG, CYREG_B1_UDB07_MSK_ACTL\r
+.set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB07_ACTL\r
+.set SDCard_BSPIM_TxStsReg__STATUS_CNT_REG, CYREG_B1_UDB07_ST_CTL\r
+.set SDCard_BSPIM_TxStsReg__STATUS_CONTROL_REG, CYREG_B1_UDB07_ST_CTL\r
+.set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B1_UDB07_ST\r
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG, CYREG_B0_UDB04_05_A0\r
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG, CYREG_B0_UDB04_05_A1\r
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG, CYREG_B0_UDB04_05_D0\r
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG, CYREG_B0_UDB04_05_D1\r
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG, CYREG_B0_UDB04_05_ACTL\r
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG, CYREG_B0_UDB04_05_F0\r
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG, CYREG_B0_UDB04_05_F1\r
+.set SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG, CYREG_B0_UDB04_A0_A1\r
+.set SDCard_BSPIM_sR8_Dp_u0__A0_REG, CYREG_B0_UDB04_A0\r
+.set SDCard_BSPIM_sR8_Dp_u0__A1_REG, CYREG_B0_UDB04_A1\r
+.set SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG, CYREG_B0_UDB04_D0_D1\r
+.set SDCard_BSPIM_sR8_Dp_u0__D0_REG, CYREG_B0_UDB04_D0\r
+.set SDCard_BSPIM_sR8_Dp_u0__D1_REG, CYREG_B0_UDB04_D1\r
+.set SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG, CYREG_B0_UDB04_ACTL\r
+.set SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG, CYREG_B0_UDB04_F0_F1\r
+.set SDCard_BSPIM_sR8_Dp_u0__F0_REG, CYREG_B0_UDB04_F0\r
+.set SDCard_BSPIM_sR8_Dp_u0__F1_REG, CYREG_B0_UDB04_F1\r
\r
/* USBFS_dp_int */\r
.set USBFS_dp_int__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
.set SCSI_In_DBx__DB7__SHIFT, 1\r
.set SCSI_In_DBx__DB7__SLW, CYREG_PRT2_SLW\r
\r
+/* SCSI_RX_DMA */\r
+.set SCSI_RX_DMA__DRQ_CTL, CYREG_IDMUX_DRQ_CTL0\r
+.set SCSI_RX_DMA__DRQ_NUMBER, 0\r
+.set SCSI_RX_DMA__NUMBEROF_TDS, 0\r
+.set SCSI_RX_DMA__PRIORITY, 2\r
+.set SCSI_RX_DMA__TERMIN_EN, 0\r
+.set SCSI_RX_DMA__TERMIN_SEL, 0\r
+.set SCSI_RX_DMA__TERMOUT0_EN, 1\r
+.set SCSI_RX_DMA__TERMOUT0_SEL, 0\r
+.set SCSI_RX_DMA__TERMOUT1_EN, 0\r
+.set SCSI_RX_DMA__TERMOUT1_SEL, 0\r
+\r
+/* SCSI_TX_DMA */\r
+.set SCSI_TX_DMA__DRQ_CTL, CYREG_IDMUX_DRQ_CTL0\r
+.set SCSI_TX_DMA__DRQ_NUMBER, 1\r
+.set SCSI_TX_DMA__NUMBEROF_TDS, 0\r
+.set SCSI_TX_DMA__PRIORITY, 2\r
+.set SCSI_TX_DMA__TERMIN_EN, 0\r
+.set SCSI_TX_DMA__TERMIN_SEL, 0\r
+.set SCSI_TX_DMA__TERMOUT0_EN, 1\r
+.set SCSI_TX_DMA__TERMOUT0_SEL, 1\r
+.set SCSI_TX_DMA__TERMOUT1_EN, 0\r
+.set SCSI_TX_DMA__TERMOUT1_SEL, 0\r
+\r
/* SD_Data_Clk */\r
.set SD_Data_Clk__CFG0, CYREG_CLKDIST_DCFG0_CFG0\r
.set SD_Data_Clk__CFG1, CYREG_CLKDIST_DCFG0_CFG1\r
/* scsiTarget */\r
.set scsiTarget_StatusReg__0__MASK, 0x01\r
.set scsiTarget_StatusReg__0__POS, 0\r
-.set scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB13_14_ACTL\r
-.set scsiTarget_StatusReg__16BIT_STATUS_REG, CYREG_B0_UDB13_14_ST\r
+.set scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB04_05_ACTL\r
+.set scsiTarget_StatusReg__16BIT_STATUS_REG, CYREG_B0_UDB04_05_ST\r
.set scsiTarget_StatusReg__1__MASK, 0x02\r
.set scsiTarget_StatusReg__1__POS, 1\r
.set scsiTarget_StatusReg__2__MASK, 0x04\r
.set scsiTarget_StatusReg__2__POS, 2\r
.set scsiTarget_StatusReg__3__MASK, 0x08\r
.set scsiTarget_StatusReg__3__POS, 3\r
-.set scsiTarget_StatusReg__MASK, 0x0F\r
-.set scsiTarget_StatusReg__MASK_REG, CYREG_B0_UDB13_MSK\r
-.set scsiTarget_StatusReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB13_ACTL\r
-.set scsiTarget_StatusReg__STATUS_REG, CYREG_B0_UDB13_ST\r
-.set scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB12_13_ACTL\r
-.set scsiTarget_datapath_PI__16BIT_STATUS_REG, CYREG_B0_UDB12_13_ST\r
-.set scsiTarget_datapath_PI__MASK_REG, CYREG_B0_UDB12_MSK\r
-.set scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL\r
-.set scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL\r
-.set scsiTarget_datapath_PI__STATUS_AUX_CTL_REG, CYREG_B0_UDB12_ACTL\r
-.set scsiTarget_datapath_PI__STATUS_CNT_REG, CYREG_B0_UDB12_ST_CTL\r
-.set scsiTarget_datapath_PI__STATUS_CONTROL_REG, CYREG_B0_UDB12_ST_CTL\r
-.set scsiTarget_datapath_PI__STATUS_REG, CYREG_B0_UDB12_ST\r
-.set scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB12_13_ACTL\r
-.set scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB12_13_CTL\r
-.set scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB12_13_CTL\r
-.set scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB12_13_CTL\r
-.set scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB12_13_CTL\r
-.set scsiTarget_datapath_PO__16BIT_MASK_MASK_REG, CYREG_B0_UDB12_13_MSK\r
-.set scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB12_13_MSK\r
-.set scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB12_13_MSK\r
-.set scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB12_13_MSK\r
-.set scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG, CYREG_B0_UDB12_ACTL\r
-.set scsiTarget_datapath_PO__CONTROL_REG, CYREG_B0_UDB12_CTL\r
-.set scsiTarget_datapath_PO__CONTROL_ST_REG, CYREG_B0_UDB12_ST_CTL\r
-.set scsiTarget_datapath_PO__COUNT_REG, CYREG_B0_UDB12_CTL\r
-.set scsiTarget_datapath_PO__COUNT_ST_REG, CYREG_B0_UDB12_ST_CTL\r
-.set scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL\r
-.set scsiTarget_datapath_PO__PERIOD_REG, CYREG_B0_UDB12_MSK\r
-.set scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL\r
-.set scsiTarget_datapath__16BIT_A0_REG, CYREG_B0_UDB12_13_A0\r
-.set scsiTarget_datapath__16BIT_A1_REG, CYREG_B0_UDB12_13_A1\r
-.set scsiTarget_datapath__16BIT_D0_REG, CYREG_B0_UDB12_13_D0\r
-.set scsiTarget_datapath__16BIT_D1_REG, CYREG_B0_UDB12_13_D1\r
-.set scsiTarget_datapath__16BIT_DP_AUX_CTL_REG, CYREG_B0_UDB12_13_ACTL\r
-.set scsiTarget_datapath__16BIT_F0_REG, CYREG_B0_UDB12_13_F0\r
-.set scsiTarget_datapath__16BIT_F1_REG, CYREG_B0_UDB12_13_F1\r
-.set scsiTarget_datapath__A0_A1_REG, CYREG_B0_UDB12_A0_A1\r
-.set scsiTarget_datapath__A0_REG, CYREG_B0_UDB12_A0\r
-.set scsiTarget_datapath__A1_REG, CYREG_B0_UDB12_A1\r
-.set scsiTarget_datapath__D0_D1_REG, CYREG_B0_UDB12_D0_D1\r
-.set scsiTarget_datapath__D0_REG, CYREG_B0_UDB12_D0\r
-.set scsiTarget_datapath__D1_REG, CYREG_B0_UDB12_D1\r
-.set scsiTarget_datapath__DP_AUX_CTL_REG, CYREG_B0_UDB12_ACTL\r
-.set scsiTarget_datapath__F0_F1_REG, CYREG_B0_UDB12_F0_F1\r
-.set scsiTarget_datapath__F0_REG, CYREG_B0_UDB12_F0\r
-.set scsiTarget_datapath__F1_REG, CYREG_B0_UDB12_F1\r
-.set scsiTarget_datapath__MSK_DP_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL\r
-.set scsiTarget_datapath__PER_DP_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL\r
+.set scsiTarget_StatusReg__4__MASK, 0x10\r
+.set scsiTarget_StatusReg__4__POS, 4\r
+.set scsiTarget_StatusReg__MASK, 0x1F\r
+.set scsiTarget_StatusReg__MASK_REG, CYREG_B0_UDB04_MSK\r
+.set scsiTarget_StatusReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB04_ACTL\r
+.set scsiTarget_StatusReg__STATUS_REG, CYREG_B0_UDB04_ST\r
+.set scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB03_04_ACTL\r
+.set scsiTarget_datapath_PI__16BIT_STATUS_REG, CYREG_B0_UDB03_04_ST\r
+.set scsiTarget_datapath_PI__MASK_REG, CYREG_B0_UDB03_MSK\r
+.set scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL\r
+.set scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL\r
+.set scsiTarget_datapath_PI__STATUS_AUX_CTL_REG, CYREG_B0_UDB03_ACTL\r
+.set scsiTarget_datapath_PI__STATUS_CNT_REG, CYREG_B0_UDB03_ST_CTL\r
+.set scsiTarget_datapath_PI__STATUS_CONTROL_REG, CYREG_B0_UDB03_ST_CTL\r
+.set scsiTarget_datapath_PI__STATUS_REG, CYREG_B0_UDB03_ST\r
+.set scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB03_04_ACTL\r
+.set scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB03_04_CTL\r
+.set scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB03_04_CTL\r
+.set scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB03_04_CTL\r
+.set scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB03_04_CTL\r
+.set scsiTarget_datapath_PO__16BIT_MASK_MASK_REG, CYREG_B0_UDB03_04_MSK\r
+.set scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB03_04_MSK\r
+.set scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB03_04_MSK\r
+.set scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB03_04_MSK\r
+.set scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG, CYREG_B0_UDB03_ACTL\r
+.set scsiTarget_datapath_PO__CONTROL_REG, CYREG_B0_UDB03_CTL\r
+.set scsiTarget_datapath_PO__CONTROL_ST_REG, CYREG_B0_UDB03_ST_CTL\r
+.set scsiTarget_datapath_PO__COUNT_REG, CYREG_B0_UDB03_CTL\r
+.set scsiTarget_datapath_PO__COUNT_ST_REG, CYREG_B0_UDB03_ST_CTL\r
+.set scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL\r
+.set scsiTarget_datapath_PO__PERIOD_REG, CYREG_B0_UDB03_MSK\r
+.set scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL\r
+.set scsiTarget_datapath__16BIT_A0_REG, CYREG_B0_UDB03_04_A0\r
+.set scsiTarget_datapath__16BIT_A1_REG, CYREG_B0_UDB03_04_A1\r
+.set scsiTarget_datapath__16BIT_D0_REG, CYREG_B0_UDB03_04_D0\r
+.set scsiTarget_datapath__16BIT_D1_REG, CYREG_B0_UDB03_04_D1\r
+.set scsiTarget_datapath__16BIT_DP_AUX_CTL_REG, CYREG_B0_UDB03_04_ACTL\r
+.set scsiTarget_datapath__16BIT_F0_REG, CYREG_B0_UDB03_04_F0\r
+.set scsiTarget_datapath__16BIT_F1_REG, CYREG_B0_UDB03_04_F1\r
+.set scsiTarget_datapath__A0_A1_REG, CYREG_B0_UDB03_A0_A1\r
+.set scsiTarget_datapath__A0_REG, CYREG_B0_UDB03_A0\r
+.set scsiTarget_datapath__A1_REG, CYREG_B0_UDB03_A1\r
+.set scsiTarget_datapath__D0_D1_REG, CYREG_B0_UDB03_D0_D1\r
+.set scsiTarget_datapath__D0_REG, CYREG_B0_UDB03_D0\r
+.set scsiTarget_datapath__D1_REG, CYREG_B0_UDB03_D1\r
+.set scsiTarget_datapath__DP_AUX_CTL_REG, CYREG_B0_UDB03_ACTL\r
+.set scsiTarget_datapath__F0_F1_REG, CYREG_B0_UDB03_F0_F1\r
+.set scsiTarget_datapath__F0_REG, CYREG_B0_UDB03_F0\r
+.set scsiTarget_datapath__F1_REG, CYREG_B0_UDB03_F1\r
+.set scsiTarget_datapath__MSK_DP_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL\r
+.set scsiTarget_datapath__PER_DP_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL\r
\r
/* SD_Clk_Ctl */\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__0__MASK, 0x01\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__0__POS, 0\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB02_03_ACTL\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB02_03_CTL\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB02_03_CTL\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB02_03_CTL\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB02_03_CTL\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB02_03_MSK\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB02_03_MSK\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB02_03_MSK\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB02_03_MSK\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB02_ACTL\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB02_CTL\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB02_ST_CTL\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB02_CTL\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB02_ST_CTL\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__MASK, 0x01\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB02_MSK_ACTL\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB02_MSK\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB02_MSK_ACTL\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__REMOVED, 1\r
\r
/* USBFS_ep_0 */\r
.set USBFS_ep_0__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
/* USBFS_ep_1 */\r
.set USBFS_ep_1__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
.set USBFS_ep_1__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
-.set USBFS_ep_1__INTC_MASK, 0x02\r
-.set USBFS_ep_1__INTC_NUMBER, 1\r
+.set USBFS_ep_1__INTC_MASK, 0x20\r
+.set USBFS_ep_1__INTC_NUMBER, 5\r
.set USBFS_ep_1__INTC_PRIOR_NUM, 7\r
-.set USBFS_ep_1__INTC_PRIOR_REG, CYREG_NVIC_PRI_1\r
+.set USBFS_ep_1__INTC_PRIOR_REG, CYREG_NVIC_PRI_5\r
.set USBFS_ep_1__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
.set USBFS_ep_1__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
\r
/* USBFS_ep_2 */\r
.set USBFS_ep_2__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
.set USBFS_ep_2__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
-.set USBFS_ep_2__INTC_MASK, 0x04\r
-.set USBFS_ep_2__INTC_NUMBER, 2\r
+.set USBFS_ep_2__INTC_MASK, 0x40\r
+.set USBFS_ep_2__INTC_NUMBER, 6\r
.set USBFS_ep_2__INTC_PRIOR_NUM, 7\r
-.set USBFS_ep_2__INTC_PRIOR_REG, CYREG_NVIC_PRI_2\r
+.set USBFS_ep_2__INTC_PRIOR_REG, CYREG_NVIC_PRI_6\r
.set USBFS_ep_2__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
.set USBFS_ep_2__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
\r
/* USBFS_ep_3 */\r
.set USBFS_ep_3__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
.set USBFS_ep_3__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
-.set USBFS_ep_3__INTC_MASK, 0x08\r
-.set USBFS_ep_3__INTC_NUMBER, 3\r
+.set USBFS_ep_3__INTC_MASK, 0x80\r
+.set USBFS_ep_3__INTC_NUMBER, 7\r
.set USBFS_ep_3__INTC_PRIOR_NUM, 7\r
-.set USBFS_ep_3__INTC_PRIOR_REG, CYREG_NVIC_PRI_3\r
+.set USBFS_ep_3__INTC_PRIOR_REG, CYREG_NVIC_PRI_7\r
.set USBFS_ep_3__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
.set USBFS_ep_3__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
\r
/* USBFS_ep_4 */\r
.set USBFS_ep_4__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
.set USBFS_ep_4__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
-.set USBFS_ep_4__INTC_MASK, 0x10\r
-.set USBFS_ep_4__INTC_NUMBER, 4\r
+.set USBFS_ep_4__INTC_MASK, 0x100\r
+.set USBFS_ep_4__INTC_NUMBER, 8\r
.set USBFS_ep_4__INTC_PRIOR_NUM, 7\r
-.set USBFS_ep_4__INTC_PRIOR_REG, CYREG_NVIC_PRI_4\r
+.set USBFS_ep_4__INTC_PRIOR_REG, CYREG_NVIC_PRI_8\r
.set USBFS_ep_4__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
.set USBFS_ep_4__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
\r
+/* SD_RX_DMA */\r
+.set SD_RX_DMA__DRQ_CTL, CYREG_IDMUX_DRQ_CTL0\r
+.set SD_RX_DMA__DRQ_NUMBER, 2\r
+.set SD_RX_DMA__NUMBEROF_TDS, 0\r
+.set SD_RX_DMA__PRIORITY, 1\r
+.set SD_RX_DMA__TERMIN_EN, 0\r
+.set SD_RX_DMA__TERMIN_SEL, 0\r
+.set SD_RX_DMA__TERMOUT0_EN, 1\r
+.set SD_RX_DMA__TERMOUT0_SEL, 2\r
+.set SD_RX_DMA__TERMOUT1_EN, 0\r
+.set SD_RX_DMA__TERMOUT1_SEL, 0\r
+\r
+/* SD_TX_DMA */\r
+.set SD_TX_DMA__DRQ_CTL, CYREG_IDMUX_DRQ_CTL0\r
+.set SD_TX_DMA__DRQ_NUMBER, 3\r
+.set SD_TX_DMA__NUMBEROF_TDS, 0\r
+.set SD_TX_DMA__PRIORITY, 2\r
+.set SD_TX_DMA__TERMIN_EN, 0\r
+.set SD_TX_DMA__TERMIN_SEL, 0\r
+.set SD_TX_DMA__TERMOUT0_EN, 1\r
+.set SD_TX_DMA__TERMOUT0_SEL, 3\r
+.set SD_TX_DMA__TERMOUT1_EN, 0\r
+.set SD_TX_DMA__TERMOUT1_SEL, 0\r
+\r
/* USBFS_USB */\r
.set USBFS_USB__ARB_CFG, CYREG_USB_ARB_CFG\r
.set USBFS_USB__ARB_EP1_CFG, CYREG_USB_ARB_EP1_CFG\r
.set CYDEV_CHIP_FAMILY_PSOC5, 3\r
.set CYDEV_CHIP_DIE_PSOC5LP, 4\r
.set CYDEV_CHIP_DIE_EXPECT, CYDEV_CHIP_DIE_PSOC5LP\r
-.set BCLK__BUS_CLK__HZ, 60000000\r
-.set BCLK__BUS_CLK__KHZ, 60000\r
-.set BCLK__BUS_CLK__MHZ, 60\r
+.set BCLK__BUS_CLK__HZ, 50000000\r
+.set BCLK__BUS_CLK__KHZ, 50000\r
+.set BCLK__BUS_CLK__MHZ, 50\r
.set CYDEV_CHIP_DIE_ACTUAL, CYDEV_CHIP_DIE_EXPECT\r
.set CYDEV_CHIP_DIE_LEOPARD, 1\r
.set CYDEV_CHIP_DIE_PANTHER, 3\r
.set CYDEV_ECC_ENABLE, 0\r
.set CYDEV_HEAP_SIZE, 0x0400\r
.set CYDEV_INSTRUCT_CACHE_ENABLED, 1\r
-.set CYDEV_INTR_RISING, 0x00000001\r
+.set CYDEV_INTR_RISING, 0x0000001E\r
.set CYDEV_PROJ_TYPE, 2\r
.set CYDEV_PROJ_TYPE_BOOTLOADER, 1\r
.set CYDEV_PROJ_TYPE_LOADABLE, 2\r
.set CYDEV_VIO2, 5\r
.set CYDEV_VIO2_MV, 5000\r
.set CYDEV_VIO3_MV, 3300\r
-.set DMA_CHANNELS_USED__MASK0, 0x00000000\r
+.set DMA_CHANNELS_USED__MASK0, 0x0000000F\r
.set CYDEV_BOOTLOADER_ENABLE, 0\r
.endif\r
/* Debug_Timer_Interrupt */\r
Debug_Timer_Interrupt__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
Debug_Timer_Interrupt__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
-Debug_Timer_Interrupt__INTC_MASK EQU 0x01\r
-Debug_Timer_Interrupt__INTC_NUMBER EQU 0\r
+Debug_Timer_Interrupt__INTC_MASK EQU 0x02\r
+Debug_Timer_Interrupt__INTC_NUMBER EQU 1\r
Debug_Timer_Interrupt__INTC_PRIOR_NUM EQU 7\r
-Debug_Timer_Interrupt__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_0\r
+Debug_Timer_Interrupt__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_1\r
Debug_Timer_Interrupt__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
Debug_Timer_Interrupt__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
\r
+/* SCSI_RX_DMA_COMPLETE */\r
+SCSI_RX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
+SCSI_RX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
+SCSI_RX_DMA_COMPLETE__INTC_MASK EQU 0x01\r
+SCSI_RX_DMA_COMPLETE__INTC_NUMBER EQU 0\r
+SCSI_RX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7\r
+SCSI_RX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_0\r
+SCSI_RX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
+SCSI_RX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
+\r
+/* SCSI_TX_DMA_COMPLETE */\r
+SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
+SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
+SCSI_TX_DMA_COMPLETE__INTC_MASK EQU 0x04\r
+SCSI_TX_DMA_COMPLETE__INTC_NUMBER EQU 2\r
+SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7\r
+SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_2\r
+SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
+SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
+\r
/* Debug_Timer_TimerHW */\r
Debug_Timer_TimerHW__CAP0 EQU CYREG_TMR0_CAP0\r
Debug_Timer_TimerHW__CAP1 EQU CYREG_TMR0_CAP1\r
Debug_Timer_TimerHW__RT1 EQU CYREG_TMR0_RT1\r
Debug_Timer_TimerHW__SR0 EQU CYREG_TMR0_SR0\r
\r
+/* SD_RX_DMA_COMPLETE */\r
+SD_RX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
+SD_RX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
+SD_RX_DMA_COMPLETE__INTC_MASK EQU 0x08\r
+SD_RX_DMA_COMPLETE__INTC_NUMBER EQU 3\r
+SD_RX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7\r
+SD_RX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_3\r
+SD_RX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
+SD_RX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
+\r
+/* SD_TX_DMA_COMPLETE */\r
+SD_TX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
+SD_TX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
+SD_TX_DMA_COMPLETE__INTC_MASK EQU 0x10\r
+SD_TX_DMA_COMPLETE__INTC_NUMBER EQU 4\r
+SD_TX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7\r
+SD_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_4\r
+SD_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
+SD_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
+\r
/* USBFS_bus_reset */\r
USBFS_bus_reset__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
USBFS_bus_reset__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
/* SCSI_CTL_PHASE */\r
SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01\r
SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS EQU 0\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB05_06_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB05_06_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB05_06_MSK\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB05_06_MSK\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB02_03_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB02_03_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB02_03_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB02_03_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK\r
SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK EQU 0x02\r
SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS EQU 1\r
SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK EQU 0x04\r
SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS EQU 2\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB05_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB05_ST_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB05_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB05_ST_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB02_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB02_ST_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB02_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB02_ST_CTL\r
SCSI_CTL_PHASE_Sync_ctrl_reg__MASK EQU 0x07\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB05_MSK\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB02_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL\r
\r
/* SCSI_Out_Bits */\r
SCSI_Out_Bits_Sync_ctrl_reg__0__MASK EQU 0x01\r
SCSI_Out_Bits_Sync_ctrl_reg__0__POS EQU 0\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB00_01_ACTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB00_01_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB00_01_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB00_01_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB00_01_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB00_01_MSK\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB00_01_MSK\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB00_01_MSK\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB00_01_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB12_13_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB12_13_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB12_13_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB12_13_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK\r
SCSI_Out_Bits_Sync_ctrl_reg__1__MASK EQU 0x02\r
SCSI_Out_Bits_Sync_ctrl_reg__1__POS EQU 1\r
SCSI_Out_Bits_Sync_ctrl_reg__2__MASK EQU 0x04\r
SCSI_Out_Bits_Sync_ctrl_reg__6__POS EQU 6\r
SCSI_Out_Bits_Sync_ctrl_reg__7__MASK EQU 0x80\r
SCSI_Out_Bits_Sync_ctrl_reg__7__POS EQU 7\r
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB00_ACTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB00_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB00_ST_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB00_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB00_ST_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB12_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB12_ST_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB12_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB12_ST_CTL\r
SCSI_Out_Bits_Sync_ctrl_reg__MASK EQU 0xFF\r
-SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB00_MSK_ACTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB00_MSK\r
-SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB00_MSK_ACTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB12_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL\r
\r
/* USBFS_arb_int */\r
USBFS_arb_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
/* SCSI_Out_Ctl */\r
SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01\r
SCSI_Out_Ctl_Sync_ctrl_reg__0__POS EQU 0\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB03_04_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB03_04_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB03_04_MSK\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB03_04_MSK\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK\r
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB03_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB03_ST_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB03_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB03_ST_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB07_08_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB07_08_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB07_08_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB07_08_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB07_08_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB07_08_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB07_08_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB07_08_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B1_UDB07_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B1_UDB07_ST_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B1_UDB07_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B1_UDB07_ST_CTL\r
SCSI_Out_Ctl_Sync_ctrl_reg__MASK EQU 0x01\r
-SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB03_MSK\r
-SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B1_UDB07_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL\r
\r
/* SCSI_Out_DBx */\r
SCSI_Out_DBx__0__AG EQU CYREG_PRT6_AG\r
SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL\r
SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB06_MSK\r
SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL\r
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL\r
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB06_07_ST\r
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL\r
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB07_08_ST\r
SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10\r
SDCard_BSPIM_RxStsReg__4__POS EQU 4\r
SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20\r
SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40\r
SDCard_BSPIM_RxStsReg__6__POS EQU 6\r
SDCard_BSPIM_RxStsReg__MASK EQU 0x70\r
-SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B0_UDB06_MSK\r
-SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL\r
-SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B0_UDB06_ST\r
+SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B0_UDB07_MSK\r
+SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL\r
+SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B0_UDB07_ST\r
SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01\r
SDCard_BSPIM_TxStsReg__0__POS EQU 0\r
-SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL\r
-SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB04_05_ST\r
+SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL\r
+SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST\r
SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02\r
SDCard_BSPIM_TxStsReg__1__POS EQU 1\r
SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04\r
SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10\r
SDCard_BSPIM_TxStsReg__4__POS EQU 4\r
SDCard_BSPIM_TxStsReg__MASK EQU 0x1F\r
-SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B0_UDB04_MSK\r
-SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL\r
-SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B0_UDB04_ST\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B0_UDB06_07_A0\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B0_UDB06_07_A1\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B0_UDB06_07_D0\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B0_UDB06_07_D1\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B0_UDB06_07_F0\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B0_UDB06_07_F1\r
-SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B0_UDB06_A0_A1\r
-SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B0_UDB06_A0\r
-SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B0_UDB06_A1\r
-SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B0_UDB06_D0_D1\r
-SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B0_UDB06_D0\r
-SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B0_UDB06_D1\r
-SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL\r
-SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B0_UDB06_F0_F1\r
-SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B0_UDB06_F0\r
-SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B0_UDB06_F1\r
+SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB07_MSK\r
+SDCard_BSPIM_TxStsReg__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL\r
+SDCard_BSPIM_TxStsReg__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL\r
+SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL\r
+SDCard_BSPIM_TxStsReg__STATUS_CNT_REG EQU CYREG_B1_UDB07_ST_CTL\r
+SDCard_BSPIM_TxStsReg__STATUS_CONTROL_REG EQU CYREG_B1_UDB07_ST_CTL\r
+SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB07_ST\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B0_UDB04_05_A0\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B0_UDB04_05_A1\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B0_UDB04_05_D0\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B0_UDB04_05_D1\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B0_UDB04_05_F0\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B0_UDB04_05_F1\r
+SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B0_UDB04_A0_A1\r
+SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B0_UDB04_A0\r
+SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B0_UDB04_A1\r
+SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B0_UDB04_D0_D1\r
+SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B0_UDB04_D0\r
+SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B0_UDB04_D1\r
+SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL\r
+SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B0_UDB04_F0_F1\r
+SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B0_UDB04_F0\r
+SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B0_UDB04_F1\r
\r
/* USBFS_dp_int */\r
USBFS_dp_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
SCSI_In_DBx__DB7__SHIFT EQU 1\r
SCSI_In_DBx__DB7__SLW EQU CYREG_PRT2_SLW\r
\r
+/* SCSI_RX_DMA */\r
+SCSI_RX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0\r
+SCSI_RX_DMA__DRQ_NUMBER EQU 0\r
+SCSI_RX_DMA__NUMBEROF_TDS EQU 0\r
+SCSI_RX_DMA__PRIORITY EQU 2\r
+SCSI_RX_DMA__TERMIN_EN EQU 0\r
+SCSI_RX_DMA__TERMIN_SEL EQU 0\r
+SCSI_RX_DMA__TERMOUT0_EN EQU 1\r
+SCSI_RX_DMA__TERMOUT0_SEL EQU 0\r
+SCSI_RX_DMA__TERMOUT1_EN EQU 0\r
+SCSI_RX_DMA__TERMOUT1_SEL EQU 0\r
+\r
+/* SCSI_TX_DMA */\r
+SCSI_TX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0\r
+SCSI_TX_DMA__DRQ_NUMBER EQU 1\r
+SCSI_TX_DMA__NUMBEROF_TDS EQU 0\r
+SCSI_TX_DMA__PRIORITY EQU 2\r
+SCSI_TX_DMA__TERMIN_EN EQU 0\r
+SCSI_TX_DMA__TERMIN_SEL EQU 0\r
+SCSI_TX_DMA__TERMOUT0_EN EQU 1\r
+SCSI_TX_DMA__TERMOUT0_SEL EQU 1\r
+SCSI_TX_DMA__TERMOUT1_EN EQU 0\r
+SCSI_TX_DMA__TERMOUT1_SEL EQU 0\r
+\r
/* SD_Data_Clk */\r
SD_Data_Clk__CFG0 EQU CYREG_CLKDIST_DCFG0_CFG0\r
SD_Data_Clk__CFG1 EQU CYREG_CLKDIST_DCFG0_CFG1\r
/* scsiTarget */\r
scsiTarget_StatusReg__0__MASK EQU 0x01\r
scsiTarget_StatusReg__0__POS EQU 0\r
-scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB13_14_ACTL\r
-scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB13_14_ST\r
+scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL\r
+scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB04_05_ST\r
scsiTarget_StatusReg__1__MASK EQU 0x02\r
scsiTarget_StatusReg__1__POS EQU 1\r
scsiTarget_StatusReg__2__MASK EQU 0x04\r
scsiTarget_StatusReg__2__POS EQU 2\r
scsiTarget_StatusReg__3__MASK EQU 0x08\r
scsiTarget_StatusReg__3__POS EQU 3\r
-scsiTarget_StatusReg__MASK EQU 0x0F\r
-scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB13_MSK\r
-scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB13_ACTL\r
-scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB13_ST\r
-scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL\r
-scsiTarget_datapath_PI__16BIT_STATUS_REG EQU CYREG_B0_UDB12_13_ST\r
-scsiTarget_datapath_PI__MASK_REG EQU CYREG_B0_UDB12_MSK\r
-scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL\r
-scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL\r
-scsiTarget_datapath_PI__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL\r
-scsiTarget_datapath_PI__STATUS_CNT_REG EQU CYREG_B0_UDB12_ST_CTL\r
-scsiTarget_datapath_PI__STATUS_CONTROL_REG EQU CYREG_B0_UDB12_ST_CTL\r
-scsiTarget_datapath_PI__STATUS_REG EQU CYREG_B0_UDB12_ST\r
-scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL\r
-scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL\r
-scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB12_13_CTL\r
-scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL\r
-scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB12_13_CTL\r
-scsiTarget_datapath_PO__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB12_13_MSK\r
-scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK\r
-scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB12_13_MSK\r
-scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK\r
-scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL\r
-scsiTarget_datapath_PO__CONTROL_REG EQU CYREG_B0_UDB12_CTL\r
-scsiTarget_datapath_PO__CONTROL_ST_REG EQU CYREG_B0_UDB12_ST_CTL\r
-scsiTarget_datapath_PO__COUNT_REG EQU CYREG_B0_UDB12_CTL\r
-scsiTarget_datapath_PO__COUNT_ST_REG EQU CYREG_B0_UDB12_ST_CTL\r
-scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL\r
-scsiTarget_datapath_PO__PERIOD_REG EQU CYREG_B0_UDB12_MSK\r
-scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL\r
-scsiTarget_datapath__16BIT_A0_REG EQU CYREG_B0_UDB12_13_A0\r
-scsiTarget_datapath__16BIT_A1_REG EQU CYREG_B0_UDB12_13_A1\r
-scsiTarget_datapath__16BIT_D0_REG EQU CYREG_B0_UDB12_13_D0\r
-scsiTarget_datapath__16BIT_D1_REG EQU CYREG_B0_UDB12_13_D1\r
-scsiTarget_datapath__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL\r
-scsiTarget_datapath__16BIT_F0_REG EQU CYREG_B0_UDB12_13_F0\r
-scsiTarget_datapath__16BIT_F1_REG EQU CYREG_B0_UDB12_13_F1\r
-scsiTarget_datapath__A0_A1_REG EQU CYREG_B0_UDB12_A0_A1\r
-scsiTarget_datapath__A0_REG EQU CYREG_B0_UDB12_A0\r
-scsiTarget_datapath__A1_REG EQU CYREG_B0_UDB12_A1\r
-scsiTarget_datapath__D0_D1_REG EQU CYREG_B0_UDB12_D0_D1\r
-scsiTarget_datapath__D0_REG EQU CYREG_B0_UDB12_D0\r
-scsiTarget_datapath__D1_REG EQU CYREG_B0_UDB12_D1\r
-scsiTarget_datapath__DP_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL\r
-scsiTarget_datapath__F0_F1_REG EQU CYREG_B0_UDB12_F0_F1\r
-scsiTarget_datapath__F0_REG EQU CYREG_B0_UDB12_F0\r
-scsiTarget_datapath__F1_REG EQU CYREG_B0_UDB12_F1\r
-scsiTarget_datapath__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL\r
-scsiTarget_datapath__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL\r
+scsiTarget_StatusReg__4__MASK EQU 0x10\r
+scsiTarget_StatusReg__4__POS EQU 4\r
+scsiTarget_StatusReg__MASK EQU 0x1F\r
+scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB04_MSK\r
+scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL\r
+scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB04_ST\r
+scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL\r
+scsiTarget_datapath_PI__16BIT_STATUS_REG EQU CYREG_B0_UDB03_04_ST\r
+scsiTarget_datapath_PI__MASK_REG EQU CYREG_B0_UDB03_MSK\r
+scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL\r
+scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL\r
+scsiTarget_datapath_PI__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL\r
+scsiTarget_datapath_PI__STATUS_CNT_REG EQU CYREG_B0_UDB03_ST_CTL\r
+scsiTarget_datapath_PI__STATUS_CONTROL_REG EQU CYREG_B0_UDB03_ST_CTL\r
+scsiTarget_datapath_PI__STATUS_REG EQU CYREG_B0_UDB03_ST\r
+scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL\r
+scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL\r
+scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB03_04_CTL\r
+scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL\r
+scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB03_04_CTL\r
+scsiTarget_datapath_PO__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB03_04_MSK\r
+scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK\r
+scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB03_04_MSK\r
+scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK\r
+scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL\r
+scsiTarget_datapath_PO__CONTROL_REG EQU CYREG_B0_UDB03_CTL\r
+scsiTarget_datapath_PO__CONTROL_ST_REG EQU CYREG_B0_UDB03_ST_CTL\r
+scsiTarget_datapath_PO__COUNT_REG EQU CYREG_B0_UDB03_CTL\r
+scsiTarget_datapath_PO__COUNT_ST_REG EQU CYREG_B0_UDB03_ST_CTL\r
+scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL\r
+scsiTarget_datapath_PO__PERIOD_REG EQU CYREG_B0_UDB03_MSK\r
+scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL\r
+scsiTarget_datapath__16BIT_A0_REG EQU CYREG_B0_UDB03_04_A0\r
+scsiTarget_datapath__16BIT_A1_REG EQU CYREG_B0_UDB03_04_A1\r
+scsiTarget_datapath__16BIT_D0_REG EQU CYREG_B0_UDB03_04_D0\r
+scsiTarget_datapath__16BIT_D1_REG EQU CYREG_B0_UDB03_04_D1\r
+scsiTarget_datapath__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL\r
+scsiTarget_datapath__16BIT_F0_REG EQU CYREG_B0_UDB03_04_F0\r
+scsiTarget_datapath__16BIT_F1_REG EQU CYREG_B0_UDB03_04_F1\r
+scsiTarget_datapath__A0_A1_REG EQU CYREG_B0_UDB03_A0_A1\r
+scsiTarget_datapath__A0_REG EQU CYREG_B0_UDB03_A0\r
+scsiTarget_datapath__A1_REG EQU CYREG_B0_UDB03_A1\r
+scsiTarget_datapath__D0_D1_REG EQU CYREG_B0_UDB03_D0_D1\r
+scsiTarget_datapath__D0_REG EQU CYREG_B0_UDB03_D0\r
+scsiTarget_datapath__D1_REG EQU CYREG_B0_UDB03_D1\r
+scsiTarget_datapath__DP_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL\r
+scsiTarget_datapath__F0_F1_REG EQU CYREG_B0_UDB03_F0_F1\r
+scsiTarget_datapath__F0_REG EQU CYREG_B0_UDB03_F0\r
+scsiTarget_datapath__F1_REG EQU CYREG_B0_UDB03_F1\r
+scsiTarget_datapath__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL\r
+scsiTarget_datapath__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL\r
\r
/* SD_Clk_Ctl */\r
-SD_Clk_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01\r
-SD_Clk_Ctl_Sync_ctrl_reg__0__POS EQU 0\r
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB02_03_CTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB02_03_CTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB02_03_MSK\r
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK\r
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB02_03_MSK\r
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK\r
-SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB02_CTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB02_ST_CTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB02_CTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB02_ST_CTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__MASK EQU 0x01\r
-SD_Clk_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB02_MSK\r
-SD_Clk_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__REMOVED EQU 1\r
\r
/* USBFS_ep_0 */\r
USBFS_ep_0__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
/* USBFS_ep_1 */\r
USBFS_ep_1__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
USBFS_ep_1__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
-USBFS_ep_1__INTC_MASK EQU 0x02\r
-USBFS_ep_1__INTC_NUMBER EQU 1\r
+USBFS_ep_1__INTC_MASK EQU 0x20\r
+USBFS_ep_1__INTC_NUMBER EQU 5\r
USBFS_ep_1__INTC_PRIOR_NUM EQU 7\r
-USBFS_ep_1__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_1\r
+USBFS_ep_1__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_5\r
USBFS_ep_1__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
USBFS_ep_1__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
\r
/* USBFS_ep_2 */\r
USBFS_ep_2__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
USBFS_ep_2__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
-USBFS_ep_2__INTC_MASK EQU 0x04\r
-USBFS_ep_2__INTC_NUMBER EQU 2\r
+USBFS_ep_2__INTC_MASK EQU 0x40\r
+USBFS_ep_2__INTC_NUMBER EQU 6\r
USBFS_ep_2__INTC_PRIOR_NUM EQU 7\r
-USBFS_ep_2__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_2\r
+USBFS_ep_2__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_6\r
USBFS_ep_2__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
USBFS_ep_2__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
\r
/* USBFS_ep_3 */\r
USBFS_ep_3__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
USBFS_ep_3__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
-USBFS_ep_3__INTC_MASK EQU 0x08\r
-USBFS_ep_3__INTC_NUMBER EQU 3\r
+USBFS_ep_3__INTC_MASK EQU 0x80\r
+USBFS_ep_3__INTC_NUMBER EQU 7\r
USBFS_ep_3__INTC_PRIOR_NUM EQU 7\r
-USBFS_ep_3__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_3\r
+USBFS_ep_3__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_7\r
USBFS_ep_3__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
USBFS_ep_3__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
\r
/* USBFS_ep_4 */\r
USBFS_ep_4__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
USBFS_ep_4__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
-USBFS_ep_4__INTC_MASK EQU 0x10\r
-USBFS_ep_4__INTC_NUMBER EQU 4\r
+USBFS_ep_4__INTC_MASK EQU 0x100\r
+USBFS_ep_4__INTC_NUMBER EQU 8\r
USBFS_ep_4__INTC_PRIOR_NUM EQU 7\r
-USBFS_ep_4__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_4\r
+USBFS_ep_4__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_8\r
USBFS_ep_4__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
USBFS_ep_4__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
\r
+/* SD_RX_DMA */\r
+SD_RX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0\r
+SD_RX_DMA__DRQ_NUMBER EQU 2\r
+SD_RX_DMA__NUMBEROF_TDS EQU 0\r
+SD_RX_DMA__PRIORITY EQU 1\r
+SD_RX_DMA__TERMIN_EN EQU 0\r
+SD_RX_DMA__TERMIN_SEL EQU 0\r
+SD_RX_DMA__TERMOUT0_EN EQU 1\r
+SD_RX_DMA__TERMOUT0_SEL EQU 2\r
+SD_RX_DMA__TERMOUT1_EN EQU 0\r
+SD_RX_DMA__TERMOUT1_SEL EQU 0\r
+\r
+/* SD_TX_DMA */\r
+SD_TX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0\r
+SD_TX_DMA__DRQ_NUMBER EQU 3\r
+SD_TX_DMA__NUMBEROF_TDS EQU 0\r
+SD_TX_DMA__PRIORITY EQU 2\r
+SD_TX_DMA__TERMIN_EN EQU 0\r
+SD_TX_DMA__TERMIN_SEL EQU 0\r
+SD_TX_DMA__TERMOUT0_EN EQU 1\r
+SD_TX_DMA__TERMOUT0_SEL EQU 3\r
+SD_TX_DMA__TERMOUT1_EN EQU 0\r
+SD_TX_DMA__TERMOUT1_SEL EQU 0\r
+\r
/* USBFS_USB */\r
USBFS_USB__ARB_CFG EQU CYREG_USB_ARB_CFG\r
USBFS_USB__ARB_EP1_CFG EQU CYREG_USB_ARB_EP1_CFG\r
CYDEV_CHIP_FAMILY_PSOC5 EQU 3\r
CYDEV_CHIP_DIE_PSOC5LP EQU 4\r
CYDEV_CHIP_DIE_EXPECT EQU CYDEV_CHIP_DIE_PSOC5LP\r
-BCLK__BUS_CLK__HZ EQU 60000000\r
-BCLK__BUS_CLK__KHZ EQU 60000\r
-BCLK__BUS_CLK__MHZ EQU 60\r
+BCLK__BUS_CLK__HZ EQU 50000000\r
+BCLK__BUS_CLK__KHZ EQU 50000\r
+BCLK__BUS_CLK__MHZ EQU 50\r
CYDEV_CHIP_DIE_ACTUAL EQU CYDEV_CHIP_DIE_EXPECT\r
CYDEV_CHIP_DIE_LEOPARD EQU 1\r
CYDEV_CHIP_DIE_PANTHER EQU 3\r
CYDEV_ECC_ENABLE EQU 0\r
CYDEV_HEAP_SIZE EQU 0x0400\r
CYDEV_INSTRUCT_CACHE_ENABLED EQU 1\r
-CYDEV_INTR_RISING EQU 0x00000001\r
+CYDEV_INTR_RISING EQU 0x0000001E\r
CYDEV_PROJ_TYPE EQU 2\r
CYDEV_PROJ_TYPE_BOOTLOADER EQU 1\r
CYDEV_PROJ_TYPE_LOADABLE EQU 2\r
CYDEV_VIO2 EQU 5\r
CYDEV_VIO2_MV EQU 5000\r
CYDEV_VIO3_MV EQU 3300\r
-DMA_CHANNELS_USED__MASK0 EQU 0x00000000\r
+DMA_CHANNELS_USED__MASK0 EQU 0x0000000F\r
CYDEV_BOOTLOADER_ENABLE EQU 0\r
\r
#endif /* INCLUDED_CYFITTERIAR_INC */\r
; Debug_Timer_Interrupt\r
Debug_Timer_Interrupt__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
Debug_Timer_Interrupt__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
-Debug_Timer_Interrupt__INTC_MASK EQU 0x01\r
-Debug_Timer_Interrupt__INTC_NUMBER EQU 0\r
+Debug_Timer_Interrupt__INTC_MASK EQU 0x02\r
+Debug_Timer_Interrupt__INTC_NUMBER EQU 1\r
Debug_Timer_Interrupt__INTC_PRIOR_NUM EQU 7\r
-Debug_Timer_Interrupt__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_0\r
+Debug_Timer_Interrupt__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_1\r
Debug_Timer_Interrupt__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
Debug_Timer_Interrupt__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
\r
+; SCSI_RX_DMA_COMPLETE\r
+SCSI_RX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
+SCSI_RX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
+SCSI_RX_DMA_COMPLETE__INTC_MASK EQU 0x01\r
+SCSI_RX_DMA_COMPLETE__INTC_NUMBER EQU 0\r
+SCSI_RX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7\r
+SCSI_RX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_0\r
+SCSI_RX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
+SCSI_RX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
+\r
+; SCSI_TX_DMA_COMPLETE\r
+SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
+SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
+SCSI_TX_DMA_COMPLETE__INTC_MASK EQU 0x04\r
+SCSI_TX_DMA_COMPLETE__INTC_NUMBER EQU 2\r
+SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7\r
+SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_2\r
+SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
+SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
+\r
; Debug_Timer_TimerHW\r
Debug_Timer_TimerHW__CAP0 EQU CYREG_TMR0_CAP0\r
Debug_Timer_TimerHW__CAP1 EQU CYREG_TMR0_CAP1\r
Debug_Timer_TimerHW__RT1 EQU CYREG_TMR0_RT1\r
Debug_Timer_TimerHW__SR0 EQU CYREG_TMR0_SR0\r
\r
+; SD_RX_DMA_COMPLETE\r
+SD_RX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
+SD_RX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
+SD_RX_DMA_COMPLETE__INTC_MASK EQU 0x08\r
+SD_RX_DMA_COMPLETE__INTC_NUMBER EQU 3\r
+SD_RX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7\r
+SD_RX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_3\r
+SD_RX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
+SD_RX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
+\r
+; SD_TX_DMA_COMPLETE\r
+SD_TX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
+SD_TX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
+SD_TX_DMA_COMPLETE__INTC_MASK EQU 0x10\r
+SD_TX_DMA_COMPLETE__INTC_NUMBER EQU 4\r
+SD_TX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7\r
+SD_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_4\r
+SD_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
+SD_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
+\r
; USBFS_bus_reset\r
USBFS_bus_reset__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
USBFS_bus_reset__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
; SCSI_CTL_PHASE\r
SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01\r
SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS EQU 0\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB05_06_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB05_06_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB05_06_MSK\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB05_06_MSK\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB02_03_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB02_03_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB02_03_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB02_03_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK\r
SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK EQU 0x02\r
SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS EQU 1\r
SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK EQU 0x04\r
SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS EQU 2\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB05_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB05_ST_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB05_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB05_ST_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB02_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB02_ST_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB02_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB02_ST_CTL\r
SCSI_CTL_PHASE_Sync_ctrl_reg__MASK EQU 0x07\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB05_MSK\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB02_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL\r
\r
; SCSI_Out_Bits\r
SCSI_Out_Bits_Sync_ctrl_reg__0__MASK EQU 0x01\r
SCSI_Out_Bits_Sync_ctrl_reg__0__POS EQU 0\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB00_01_ACTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB00_01_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB00_01_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB00_01_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB00_01_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB00_01_MSK\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB00_01_MSK\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB00_01_MSK\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB00_01_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB12_13_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB12_13_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB12_13_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB12_13_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK\r
SCSI_Out_Bits_Sync_ctrl_reg__1__MASK EQU 0x02\r
SCSI_Out_Bits_Sync_ctrl_reg__1__POS EQU 1\r
SCSI_Out_Bits_Sync_ctrl_reg__2__MASK EQU 0x04\r
SCSI_Out_Bits_Sync_ctrl_reg__6__POS EQU 6\r
SCSI_Out_Bits_Sync_ctrl_reg__7__MASK EQU 0x80\r
SCSI_Out_Bits_Sync_ctrl_reg__7__POS EQU 7\r
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB00_ACTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB00_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB00_ST_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB00_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB00_ST_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB12_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB12_ST_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB12_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB12_ST_CTL\r
SCSI_Out_Bits_Sync_ctrl_reg__MASK EQU 0xFF\r
-SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB00_MSK_ACTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB00_MSK\r
-SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB00_MSK_ACTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB12_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL\r
\r
; USBFS_arb_int\r
USBFS_arb_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
; SCSI_Out_Ctl\r
SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01\r
SCSI_Out_Ctl_Sync_ctrl_reg__0__POS EQU 0\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB03_04_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB03_04_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB03_04_MSK\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB03_04_MSK\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK\r
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB03_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB03_ST_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB03_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB03_ST_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB07_08_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB07_08_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB07_08_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB07_08_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB07_08_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB07_08_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB07_08_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB07_08_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B1_UDB07_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B1_UDB07_ST_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B1_UDB07_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B1_UDB07_ST_CTL\r
SCSI_Out_Ctl_Sync_ctrl_reg__MASK EQU 0x01\r
-SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB03_MSK\r
-SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B1_UDB07_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL\r
\r
; SCSI_Out_DBx\r
SCSI_Out_DBx__0__AG EQU CYREG_PRT6_AG\r
SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL\r
SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB06_MSK\r
SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL\r
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL\r
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB06_07_ST\r
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL\r
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB07_08_ST\r
SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10\r
SDCard_BSPIM_RxStsReg__4__POS EQU 4\r
SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20\r
SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40\r
SDCard_BSPIM_RxStsReg__6__POS EQU 6\r
SDCard_BSPIM_RxStsReg__MASK EQU 0x70\r
-SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B0_UDB06_MSK\r
-SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL\r
-SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B0_UDB06_ST\r
+SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B0_UDB07_MSK\r
+SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL\r
+SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B0_UDB07_ST\r
SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01\r
SDCard_BSPIM_TxStsReg__0__POS EQU 0\r
-SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL\r
-SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB04_05_ST\r
+SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL\r
+SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST\r
SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02\r
SDCard_BSPIM_TxStsReg__1__POS EQU 1\r
SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04\r
SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10\r
SDCard_BSPIM_TxStsReg__4__POS EQU 4\r
SDCard_BSPIM_TxStsReg__MASK EQU 0x1F\r
-SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B0_UDB04_MSK\r
-SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL\r
-SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B0_UDB04_ST\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B0_UDB06_07_A0\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B0_UDB06_07_A1\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B0_UDB06_07_D0\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B0_UDB06_07_D1\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B0_UDB06_07_F0\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B0_UDB06_07_F1\r
-SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B0_UDB06_A0_A1\r
-SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B0_UDB06_A0\r
-SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B0_UDB06_A1\r
-SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B0_UDB06_D0_D1\r
-SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B0_UDB06_D0\r
-SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B0_UDB06_D1\r
-SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL\r
-SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B0_UDB06_F0_F1\r
-SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B0_UDB06_F0\r
-SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B0_UDB06_F1\r
+SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB07_MSK\r
+SDCard_BSPIM_TxStsReg__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL\r
+SDCard_BSPIM_TxStsReg__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL\r
+SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL\r
+SDCard_BSPIM_TxStsReg__STATUS_CNT_REG EQU CYREG_B1_UDB07_ST_CTL\r
+SDCard_BSPIM_TxStsReg__STATUS_CONTROL_REG EQU CYREG_B1_UDB07_ST_CTL\r
+SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB07_ST\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B0_UDB04_05_A0\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B0_UDB04_05_A1\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B0_UDB04_05_D0\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B0_UDB04_05_D1\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B0_UDB04_05_F0\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B0_UDB04_05_F1\r
+SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B0_UDB04_A0_A1\r
+SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B0_UDB04_A0\r
+SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B0_UDB04_A1\r
+SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B0_UDB04_D0_D1\r
+SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B0_UDB04_D0\r
+SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B0_UDB04_D1\r
+SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL\r
+SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B0_UDB04_F0_F1\r
+SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B0_UDB04_F0\r
+SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B0_UDB04_F1\r
\r
; USBFS_dp_int\r
USBFS_dp_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
SCSI_In_DBx__DB7__SHIFT EQU 1\r
SCSI_In_DBx__DB7__SLW EQU CYREG_PRT2_SLW\r
\r
+; SCSI_RX_DMA\r
+SCSI_RX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0\r
+SCSI_RX_DMA__DRQ_NUMBER EQU 0\r
+SCSI_RX_DMA__NUMBEROF_TDS EQU 0\r
+SCSI_RX_DMA__PRIORITY EQU 2\r
+SCSI_RX_DMA__TERMIN_EN EQU 0\r
+SCSI_RX_DMA__TERMIN_SEL EQU 0\r
+SCSI_RX_DMA__TERMOUT0_EN EQU 1\r
+SCSI_RX_DMA__TERMOUT0_SEL EQU 0\r
+SCSI_RX_DMA__TERMOUT1_EN EQU 0\r
+SCSI_RX_DMA__TERMOUT1_SEL EQU 0\r
+\r
+; SCSI_TX_DMA\r
+SCSI_TX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0\r
+SCSI_TX_DMA__DRQ_NUMBER EQU 1\r
+SCSI_TX_DMA__NUMBEROF_TDS EQU 0\r
+SCSI_TX_DMA__PRIORITY EQU 2\r
+SCSI_TX_DMA__TERMIN_EN EQU 0\r
+SCSI_TX_DMA__TERMIN_SEL EQU 0\r
+SCSI_TX_DMA__TERMOUT0_EN EQU 1\r
+SCSI_TX_DMA__TERMOUT0_SEL EQU 1\r
+SCSI_TX_DMA__TERMOUT1_EN EQU 0\r
+SCSI_TX_DMA__TERMOUT1_SEL EQU 0\r
+\r
; SD_Data_Clk\r
SD_Data_Clk__CFG0 EQU CYREG_CLKDIST_DCFG0_CFG0\r
SD_Data_Clk__CFG1 EQU CYREG_CLKDIST_DCFG0_CFG1\r
; scsiTarget\r
scsiTarget_StatusReg__0__MASK EQU 0x01\r
scsiTarget_StatusReg__0__POS EQU 0\r
-scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB13_14_ACTL\r
-scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB13_14_ST\r
+scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL\r
+scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB04_05_ST\r
scsiTarget_StatusReg__1__MASK EQU 0x02\r
scsiTarget_StatusReg__1__POS EQU 1\r
scsiTarget_StatusReg__2__MASK EQU 0x04\r
scsiTarget_StatusReg__2__POS EQU 2\r
scsiTarget_StatusReg__3__MASK EQU 0x08\r
scsiTarget_StatusReg__3__POS EQU 3\r
-scsiTarget_StatusReg__MASK EQU 0x0F\r
-scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB13_MSK\r
-scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB13_ACTL\r
-scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB13_ST\r
-scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL\r
-scsiTarget_datapath_PI__16BIT_STATUS_REG EQU CYREG_B0_UDB12_13_ST\r
-scsiTarget_datapath_PI__MASK_REG EQU CYREG_B0_UDB12_MSK\r
-scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL\r
-scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL\r
-scsiTarget_datapath_PI__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL\r
-scsiTarget_datapath_PI__STATUS_CNT_REG EQU CYREG_B0_UDB12_ST_CTL\r
-scsiTarget_datapath_PI__STATUS_CONTROL_REG EQU CYREG_B0_UDB12_ST_CTL\r
-scsiTarget_datapath_PI__STATUS_REG EQU CYREG_B0_UDB12_ST\r
-scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL\r
-scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL\r
-scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB12_13_CTL\r
-scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL\r
-scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB12_13_CTL\r
-scsiTarget_datapath_PO__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB12_13_MSK\r
-scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK\r
-scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB12_13_MSK\r
-scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK\r
-scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL\r
-scsiTarget_datapath_PO__CONTROL_REG EQU CYREG_B0_UDB12_CTL\r
-scsiTarget_datapath_PO__CONTROL_ST_REG EQU CYREG_B0_UDB12_ST_CTL\r
-scsiTarget_datapath_PO__COUNT_REG EQU CYREG_B0_UDB12_CTL\r
-scsiTarget_datapath_PO__COUNT_ST_REG EQU CYREG_B0_UDB12_ST_CTL\r
-scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL\r
-scsiTarget_datapath_PO__PERIOD_REG EQU CYREG_B0_UDB12_MSK\r
-scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL\r
-scsiTarget_datapath__16BIT_A0_REG EQU CYREG_B0_UDB12_13_A0\r
-scsiTarget_datapath__16BIT_A1_REG EQU CYREG_B0_UDB12_13_A1\r
-scsiTarget_datapath__16BIT_D0_REG EQU CYREG_B0_UDB12_13_D0\r
-scsiTarget_datapath__16BIT_D1_REG EQU CYREG_B0_UDB12_13_D1\r
-scsiTarget_datapath__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL\r
-scsiTarget_datapath__16BIT_F0_REG EQU CYREG_B0_UDB12_13_F0\r
-scsiTarget_datapath__16BIT_F1_REG EQU CYREG_B0_UDB12_13_F1\r
-scsiTarget_datapath__A0_A1_REG EQU CYREG_B0_UDB12_A0_A1\r
-scsiTarget_datapath__A0_REG EQU CYREG_B0_UDB12_A0\r
-scsiTarget_datapath__A1_REG EQU CYREG_B0_UDB12_A1\r
-scsiTarget_datapath__D0_D1_REG EQU CYREG_B0_UDB12_D0_D1\r
-scsiTarget_datapath__D0_REG EQU CYREG_B0_UDB12_D0\r
-scsiTarget_datapath__D1_REG EQU CYREG_B0_UDB12_D1\r
-scsiTarget_datapath__DP_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL\r
-scsiTarget_datapath__F0_F1_REG EQU CYREG_B0_UDB12_F0_F1\r
-scsiTarget_datapath__F0_REG EQU CYREG_B0_UDB12_F0\r
-scsiTarget_datapath__F1_REG EQU CYREG_B0_UDB12_F1\r
-scsiTarget_datapath__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL\r
-scsiTarget_datapath__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL\r
+scsiTarget_StatusReg__4__MASK EQU 0x10\r
+scsiTarget_StatusReg__4__POS EQU 4\r
+scsiTarget_StatusReg__MASK EQU 0x1F\r
+scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB04_MSK\r
+scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL\r
+scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB04_ST\r
+scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL\r
+scsiTarget_datapath_PI__16BIT_STATUS_REG EQU CYREG_B0_UDB03_04_ST\r
+scsiTarget_datapath_PI__MASK_REG EQU CYREG_B0_UDB03_MSK\r
+scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL\r
+scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL\r
+scsiTarget_datapath_PI__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL\r
+scsiTarget_datapath_PI__STATUS_CNT_REG EQU CYREG_B0_UDB03_ST_CTL\r
+scsiTarget_datapath_PI__STATUS_CONTROL_REG EQU CYREG_B0_UDB03_ST_CTL\r
+scsiTarget_datapath_PI__STATUS_REG EQU CYREG_B0_UDB03_ST\r
+scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL\r
+scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL\r
+scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB03_04_CTL\r
+scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL\r
+scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB03_04_CTL\r
+scsiTarget_datapath_PO__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB03_04_MSK\r
+scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK\r
+scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB03_04_MSK\r
+scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK\r
+scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL\r
+scsiTarget_datapath_PO__CONTROL_REG EQU CYREG_B0_UDB03_CTL\r
+scsiTarget_datapath_PO__CONTROL_ST_REG EQU CYREG_B0_UDB03_ST_CTL\r
+scsiTarget_datapath_PO__COUNT_REG EQU CYREG_B0_UDB03_CTL\r
+scsiTarget_datapath_PO__COUNT_ST_REG EQU CYREG_B0_UDB03_ST_CTL\r
+scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL\r
+scsiTarget_datapath_PO__PERIOD_REG EQU CYREG_B0_UDB03_MSK\r
+scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL\r
+scsiTarget_datapath__16BIT_A0_REG EQU CYREG_B0_UDB03_04_A0\r
+scsiTarget_datapath__16BIT_A1_REG EQU CYREG_B0_UDB03_04_A1\r
+scsiTarget_datapath__16BIT_D0_REG EQU CYREG_B0_UDB03_04_D0\r
+scsiTarget_datapath__16BIT_D1_REG EQU CYREG_B0_UDB03_04_D1\r
+scsiTarget_datapath__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL\r
+scsiTarget_datapath__16BIT_F0_REG EQU CYREG_B0_UDB03_04_F0\r
+scsiTarget_datapath__16BIT_F1_REG EQU CYREG_B0_UDB03_04_F1\r
+scsiTarget_datapath__A0_A1_REG EQU CYREG_B0_UDB03_A0_A1\r
+scsiTarget_datapath__A0_REG EQU CYREG_B0_UDB03_A0\r
+scsiTarget_datapath__A1_REG EQU CYREG_B0_UDB03_A1\r
+scsiTarget_datapath__D0_D1_REG EQU CYREG_B0_UDB03_D0_D1\r
+scsiTarget_datapath__D0_REG EQU CYREG_B0_UDB03_D0\r
+scsiTarget_datapath__D1_REG EQU CYREG_B0_UDB03_D1\r
+scsiTarget_datapath__DP_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL\r
+scsiTarget_datapath__F0_F1_REG EQU CYREG_B0_UDB03_F0_F1\r
+scsiTarget_datapath__F0_REG EQU CYREG_B0_UDB03_F0\r
+scsiTarget_datapath__F1_REG EQU CYREG_B0_UDB03_F1\r
+scsiTarget_datapath__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL\r
+scsiTarget_datapath__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL\r
\r
; SD_Clk_Ctl\r
-SD_Clk_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01\r
-SD_Clk_Ctl_Sync_ctrl_reg__0__POS EQU 0\r
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB02_03_CTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB02_03_CTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB02_03_MSK\r
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK\r
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB02_03_MSK\r
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK\r
-SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB02_CTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB02_ST_CTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB02_CTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB02_ST_CTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__MASK EQU 0x01\r
-SD_Clk_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB02_MSK\r
-SD_Clk_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__REMOVED EQU 1\r
\r
; USBFS_ep_0\r
USBFS_ep_0__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
; USBFS_ep_1\r
USBFS_ep_1__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
USBFS_ep_1__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
-USBFS_ep_1__INTC_MASK EQU 0x02\r
-USBFS_ep_1__INTC_NUMBER EQU 1\r
+USBFS_ep_1__INTC_MASK EQU 0x20\r
+USBFS_ep_1__INTC_NUMBER EQU 5\r
USBFS_ep_1__INTC_PRIOR_NUM EQU 7\r
-USBFS_ep_1__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_1\r
+USBFS_ep_1__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_5\r
USBFS_ep_1__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
USBFS_ep_1__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
\r
; USBFS_ep_2\r
USBFS_ep_2__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
USBFS_ep_2__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
-USBFS_ep_2__INTC_MASK EQU 0x04\r
-USBFS_ep_2__INTC_NUMBER EQU 2\r
+USBFS_ep_2__INTC_MASK EQU 0x40\r
+USBFS_ep_2__INTC_NUMBER EQU 6\r
USBFS_ep_2__INTC_PRIOR_NUM EQU 7\r
-USBFS_ep_2__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_2\r
+USBFS_ep_2__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_6\r
USBFS_ep_2__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
USBFS_ep_2__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
\r
; USBFS_ep_3\r
USBFS_ep_3__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
USBFS_ep_3__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
-USBFS_ep_3__INTC_MASK EQU 0x08\r
-USBFS_ep_3__INTC_NUMBER EQU 3\r
+USBFS_ep_3__INTC_MASK EQU 0x80\r
+USBFS_ep_3__INTC_NUMBER EQU 7\r
USBFS_ep_3__INTC_PRIOR_NUM EQU 7\r
-USBFS_ep_3__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_3\r
+USBFS_ep_3__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_7\r
USBFS_ep_3__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
USBFS_ep_3__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
\r
; USBFS_ep_4\r
USBFS_ep_4__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
USBFS_ep_4__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
-USBFS_ep_4__INTC_MASK EQU 0x10\r
-USBFS_ep_4__INTC_NUMBER EQU 4\r
+USBFS_ep_4__INTC_MASK EQU 0x100\r
+USBFS_ep_4__INTC_NUMBER EQU 8\r
USBFS_ep_4__INTC_PRIOR_NUM EQU 7\r
-USBFS_ep_4__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_4\r
+USBFS_ep_4__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_8\r
USBFS_ep_4__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
USBFS_ep_4__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
\r
+; SD_RX_DMA\r
+SD_RX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0\r
+SD_RX_DMA__DRQ_NUMBER EQU 2\r
+SD_RX_DMA__NUMBEROF_TDS EQU 0\r
+SD_RX_DMA__PRIORITY EQU 1\r
+SD_RX_DMA__TERMIN_EN EQU 0\r
+SD_RX_DMA__TERMIN_SEL EQU 0\r
+SD_RX_DMA__TERMOUT0_EN EQU 1\r
+SD_RX_DMA__TERMOUT0_SEL EQU 2\r
+SD_RX_DMA__TERMOUT1_EN EQU 0\r
+SD_RX_DMA__TERMOUT1_SEL EQU 0\r
+\r
+; SD_TX_DMA\r
+SD_TX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0\r
+SD_TX_DMA__DRQ_NUMBER EQU 3\r
+SD_TX_DMA__NUMBEROF_TDS EQU 0\r
+SD_TX_DMA__PRIORITY EQU 2\r
+SD_TX_DMA__TERMIN_EN EQU 0\r
+SD_TX_DMA__TERMIN_SEL EQU 0\r
+SD_TX_DMA__TERMOUT0_EN EQU 1\r
+SD_TX_DMA__TERMOUT0_SEL EQU 3\r
+SD_TX_DMA__TERMOUT1_EN EQU 0\r
+SD_TX_DMA__TERMOUT1_SEL EQU 0\r
+\r
; USBFS_USB\r
USBFS_USB__ARB_CFG EQU CYREG_USB_ARB_CFG\r
USBFS_USB__ARB_EP1_CFG EQU CYREG_USB_ARB_EP1_CFG\r
CYDEV_CHIP_FAMILY_PSOC5 EQU 3\r
CYDEV_CHIP_DIE_PSOC5LP EQU 4\r
CYDEV_CHIP_DIE_EXPECT EQU CYDEV_CHIP_DIE_PSOC5LP\r
-BCLK__BUS_CLK__HZ EQU 60000000\r
-BCLK__BUS_CLK__KHZ EQU 60000\r
-BCLK__BUS_CLK__MHZ EQU 60\r
+BCLK__BUS_CLK__HZ EQU 50000000\r
+BCLK__BUS_CLK__KHZ EQU 50000\r
+BCLK__BUS_CLK__MHZ EQU 50\r
CYDEV_CHIP_DIE_ACTUAL EQU CYDEV_CHIP_DIE_EXPECT\r
CYDEV_CHIP_DIE_LEOPARD EQU 1\r
CYDEV_CHIP_DIE_PANTHER EQU 3\r
CYDEV_ECC_ENABLE EQU 0\r
CYDEV_HEAP_SIZE EQU 0x0400\r
CYDEV_INSTRUCT_CACHE_ENABLED EQU 1\r
-CYDEV_INTR_RISING EQU 0x00000001\r
+CYDEV_INTR_RISING EQU 0x0000001E\r
CYDEV_PROJ_TYPE EQU 2\r
CYDEV_PROJ_TYPE_BOOTLOADER EQU 1\r
CYDEV_PROJ_TYPE_LOADABLE EQU 2\r
CYDEV_VIO2 EQU 5\r
CYDEV_VIO2_MV EQU 5000\r
CYDEV_VIO3_MV EQU 3300\r
-DMA_CHANNELS_USED__MASK0 EQU 0x00000000\r
+DMA_CHANNELS_USED__MASK0 EQU 0x0000000F\r
CYDEV_BOOTLOADER_ENABLE EQU 0\r
ENDIF\r
END\r
#include <Debug_Timer.h>\r
#include <timer_clock.h>\r
#include <Debug_Timer_Interrupt.h>\r
+#include <SCSI_TX_DMA_dma.h>\r
+#include <SCSI_TX_DMA_COMPLETE.h>\r
+#include <SD_RX_DMA_dma.h>\r
+#include <SD_TX_DMA_dma.h>\r
+#include <SD_RX_DMA_COMPLETE.h>\r
+#include <SD_TX_DMA_COMPLETE.h>\r
+#include <SCSI_RX_DMA_dma.h>\r
+#include <SCSI_RX_DMA_COMPLETE.h>\r
#include <USBFS_Dm_aliases.h>\r
#include <USBFS_Dm.h>\r
#include <USBFS_Dp_aliases.h>\r
<?xml version="1.0" encoding="utf-8"?>\r
<blockRegMap version="1" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://cypress.com/xsd/cyblockregmap cyblockregmap.xsd" xmlns="http://cypress.com/xsd/cyblockregmap">\r
+ <block name="SCSI_Out_Mux" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="Bootloadable_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="SCSI_Out_Bits" BASE="0x0" SIZE="0x0" desc="" visible="true">\r
+ <register name="SCSI_Out_Bits_CONTROL_REG" address="0x4000647C" bitWidth="8" desc="" />\r
+ </block>\r
+ <block name="Debug_Timer" BASE="0x0" SIZE="0x0" desc="" visible="true">\r
+ <block name="VirtualMux_2" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="TimerHW" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="OneTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="VirtualMux_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="VirtualMux_3" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <register name="Debug_Timer_GLOBAL_ENABLE" address="0x400043A3" bitWidth="8" desc="PM.ACT.CFG">\r
+ <field name="en_timer" from="3" to="0" access="RW" resetVal="" desc="Enable timer/counters." />\r
+ </register>\r
+ <register name="Debug_Timer_CONTROL" address="0x40004F00" bitWidth="8" desc="TMRx.CFG0">\r
+ <field name="EN" from="0" to="0" access="RW" resetVal="" desc="Enables timer/comparator." />\r
+ <field name="MODE" from="1" to="1" access="RW" resetVal="" desc="Mode. (0 = Timer; 1 = Comparator)">\r
+ <value name="Timer" value="0" desc="Timer mode. CNT/CMP register holds timer count value." />\r
+ <value name="Comparator" value="1" desc="Comparator mode. CNT/CMP register holds comparator threshold value." />\r
+ </field>\r
+ <field name="ONESHOT" from="2" to="2" access="RW" resetVal="" desc="Timer stops upon reaching stop condition defined by TMR_CFG bits. Can be restarted by asserting TIMER RESET or disabling and re-enabling block." />\r
+ <field name="CMP_BUFF" from="3" to="3" access="RW" resetVal="" desc="Buffer compare register. Compare register updates only on timer terminal count." />\r
+ <field name="INV" from="4" to="4" access="RW" resetVal="" desc="Invert sense of TIMEREN signal" />\r
+ <field name="DB" from="5" to="5" access="RW" resetVal="" desc="Deadband mode--Deadband phases phi1 and phi2 are outputted on CMP and TC output pins respectively.">\r
+ <value name="Timer" value="0" desc="CMP and TC are output." />\r
+ <value name="Deadband" value="1" desc="PHI1 (instead of CMP) and PHI2 (instead of TC) are output." />\r
+ </field>\r
+ <field name="DEADBAND_PERIOD" from="7" to="6" access="RW" resetVal="" desc="Deadband Period" />\r
+ </register>\r
+ <register name="Debug_Timer_CONTROL2" address="0x40004F01" bitWidth="8" desc="TMRx.CFG1">\r
+ <field name="IRQ_SEL" from="0" to="0" access="RW" resetVal="" desc="Irq selection. (0 = raw interrupts; 1 = status register interrupts)" />\r
+ <field name="FTC" from="1" to="1" access="RW" resetVal="" desc="First Terminal Count (FTC). Setting this bit forces a single pulse on the TC pin when first enabled.">\r
+ <value name="Disable FTC" value="0" desc="Disable the single cycle pulse, which signifies the timer is starting." />\r
+ <value name="Enable FTC" value="1" desc="Enable the single cycle pulse, which signifies the timer is starting." />\r
+ </field>\r
+ <field name="DCOR" from="2" to="2" access="RW" resetVal="" desc="Disable Clear on Read (DCOR) of Status Register SR0." />\r
+ <field name="DBMODE" from="3" to="3" access="RW" resetVal="" desc="Deadband mode (asynchronous/synchronous). CMP output pin is also affected when not in deadband mode (CFG0.DEADBAND)." />\r
+ <field name="CLK_BUS_EN_SEL" from="6" to="4" access="RW" resetVal="" desc="Digital Global Clock selection." />\r
+ <field name="BUS_CLK_SEL" from="7" to="7" access="RW" resetVal="" desc="Bus Clock selection." />\r
+ </register>\r
+ <register name="Debug_Timer_CONTROL3_" address="0x40004F02" bitWidth="8" desc="TMRx.CFG2">\r
+ <field name="TMR_CFG" from="1" to="0" access="RW" resetVal="" desc="Timer configuration (MODE = 0): 000 = Continuous; 001 = Pulsewidth; 010 = Period; 011 = Stop on IRQ">\r
+ <value name="Continuous" value="0" desc="Timer runs while EN bit of CFG0 register is set to '1'." />\r
+ <value name="Pulsewidth" value="1" desc="Timer runs from positive to negative edge of TIMEREN." />\r
+ <value name="Period" value="10" desc="Timer runs from positive to positive edge of TIMEREN." />\r
+ <value name="Irq" value="11" desc="Timer runs until IRQ." />\r
+ </field>\r
+ <field name="COD" from="2" to="2" access="RW" resetVal="" desc="Clear On Disable (COD). Clears or gates outputs to zero." />\r
+ <field name="ROD" from="3" to="3" access="RW" resetVal="" desc="Reset On Disable (ROD). Resets internal state of output logic" />\r
+ <field name="CMP_CFG" from="6" to="4" access="RW" resetVal="" desc="Comparator configurations">\r
+ <value name="Equal" value="0" desc="Compare Equal " />\r
+ <value name="Less than" value="1" desc="Compare Less Than " />\r
+ <value name="Less than or equal" value="10" desc="Compare Less Than or Equal ." />\r
+ <value name="Greater" value="11" desc="Compare Greater Than ." />\r
+ <value name="Greater than or equal" value="100" desc="Compare Greater Than or Equal " />\r
+ </field>\r
+ <field name="HW_EN" from="7" to="7" access="RW" resetVal="" desc="When set Timer Enable controls counting." />\r
+ </register>\r
+ <register name="Debug_Timer_PERIOD" address="0x40004F04" bitWidth="16" desc="TMRx.PER0 - Assigned Period" />\r
+ <register name="Debug_Timer_COUNTER" address="0x40004F06" bitWidth="16" desc="TMRx.CNT_CMP0 - Current Down Counter Value" />\r
+ </block>\r
+ <block name="SCSI_Out_Ctl" BASE="0x0" SIZE="0x0" desc="" visible="true">\r
+ <register name="SCSI_Out_Ctl_CONTROL_REG" address="0x40006577" bitWidth="8" desc="" />\r
+ </block>\r
<block name="LED1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="scsiTarget" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="SD_MISO" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="SDCard" BASE="0x0" SIZE="0x0" desc="" visible="true">\r
<block name="VirtualMux_3" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="VirtualMux_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="BSPIM" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
</block>\r
- <block name="SCSI_RST" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="SCSI_CLK" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="SCSI_RST_ISR" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="SCSI_ATN" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="USBFS" BASE="0x0" SIZE="0x0" desc="USBFS" visible="true">\r
<block name="bus_reset" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="ep_0" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<register name="USBFS_EP_TYPE" address="0x4000608F" bitWidth="8" desc="Endpoint Type (IN/OUT) Indication" />\r
<register name="USBFS_USB_CLK_EN" address="0x4000609D" bitWidth="8" desc="USB Block Clock Enable Register" />\r
</block>\r
+ <block name="SD_MISO" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="timer_clock" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="Debug_Timer" BASE="0x0" SIZE="0x0" desc="" visible="true">\r
- <block name="VirtualMux_2" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="TimerHW" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="OneTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="VirtualMux_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="VirtualMux_3" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <register name="Debug_Timer_GLOBAL_ENABLE" address="0x400043A3" bitWidth="8" desc="PM.ACT.CFG">\r
- <field name="en_timer" from="3" to="0" access="RW" resetVal="" desc="Enable timer/counters." />\r
- </register>\r
- <register name="Debug_Timer_CONTROL" address="0x40004F00" bitWidth="8" desc="TMRx.CFG0">\r
- <field name="EN" from="0" to="0" access="RW" resetVal="" desc="Enables timer/comparator." />\r
- <field name="MODE" from="1" to="1" access="RW" resetVal="" desc="Mode. (0 = Timer; 1 = Comparator)">\r
- <value name="Timer" value="0" desc="Timer mode. CNT/CMP register holds timer count value." />\r
- <value name="Comparator" value="1" desc="Comparator mode. CNT/CMP register holds comparator threshold value." />\r
- </field>\r
- <field name="ONESHOT" from="2" to="2" access="RW" resetVal="" desc="Timer stops upon reaching stop condition defined by TMR_CFG bits. Can be restarted by asserting TIMER RESET or disabling and re-enabling block." />\r
- <field name="CMP_BUFF" from="3" to="3" access="RW" resetVal="" desc="Buffer compare register. Compare register updates only on timer terminal count." />\r
- <field name="INV" from="4" to="4" access="RW" resetVal="" desc="Invert sense of TIMEREN signal" />\r
- <field name="DB" from="5" to="5" access="RW" resetVal="" desc="Deadband mode--Deadband phases phi1 and phi2 are outputted on CMP and TC output pins respectively.">\r
- <value name="Timer" value="0" desc="CMP and TC are output." />\r
- <value name="Deadband" value="1" desc="PHI1 (instead of CMP) and PHI2 (instead of TC) are output." />\r
- </field>\r
- <field name="DEADBAND_PERIOD" from="7" to="6" access="RW" resetVal="" desc="Deadband Period" />\r
- </register>\r
- <register name="Debug_Timer_CONTROL2" address="0x40004F01" bitWidth="8" desc="TMRx.CFG1">\r
- <field name="IRQ_SEL" from="0" to="0" access="RW" resetVal="" desc="Irq selection. (0 = raw interrupts; 1 = status register interrupts)" />\r
- <field name="FTC" from="1" to="1" access="RW" resetVal="" desc="First Terminal Count (FTC). Setting this bit forces a single pulse on the TC pin when first enabled.">\r
- <value name="Disable FTC" value="0" desc="Disable the single cycle pulse, which signifies the timer is starting." />\r
- <value name="Enable FTC" value="1" desc="Enable the single cycle pulse, which signifies the timer is starting." />\r
- </field>\r
- <field name="DCOR" from="2" to="2" access="RW" resetVal="" desc="Disable Clear on Read (DCOR) of Status Register SR0." />\r
- <field name="DBMODE" from="3" to="3" access="RW" resetVal="" desc="Deadband mode (asynchronous/synchronous). CMP output pin is also affected when not in deadband mode (CFG0.DEADBAND)." />\r
- <field name="CLK_BUS_EN_SEL" from="6" to="4" access="RW" resetVal="" desc="Digital Global Clock selection." />\r
- <field name="BUS_CLK_SEL" from="7" to="7" access="RW" resetVal="" desc="Bus Clock selection." />\r
- </register>\r
- <register name="Debug_Timer_CONTROL3_" address="0x40004F02" bitWidth="8" desc="TMRx.CFG2">\r
- <field name="TMR_CFG" from="1" to="0" access="RW" resetVal="" desc="Timer configuration (MODE = 0): 000 = Continuous; 001 = Pulsewidth; 010 = Period; 011 = Stop on IRQ">\r
- <value name="Continuous" value="0" desc="Timer runs while EN bit of CFG0 register is set to '1'." />\r
- <value name="Pulsewidth" value="1" desc="Timer runs from positive to negative edge of TIMEREN." />\r
- <value name="Period" value="10" desc="Timer runs from positive to positive edge of TIMEREN." />\r
- <value name="Irq" value="11" desc="Timer runs until IRQ." />\r
- </field>\r
- <field name="COD" from="2" to="2" access="RW" resetVal="" desc="Clear On Disable (COD). Clears or gates outputs to zero." />\r
- <field name="ROD" from="3" to="3" access="RW" resetVal="" desc="Reset On Disable (ROD). Resets internal state of output logic" />\r
- <field name="CMP_CFG" from="6" to="4" access="RW" resetVal="" desc="Comparator configurations">\r
- <value name="Equal" value="0" desc="Compare Equal " />\r
- <value name="Less than" value="1" desc="Compare Less Than " />\r
- <value name="Less than or equal" value="10" desc="Compare Less Than or Equal ." />\r
- <value name="Greater" value="11" desc="Compare Greater Than ." />\r
- <value name="Greater than or equal" value="100" desc="Compare Greater Than or Equal " />\r
- </field>\r
- <field name="HW_EN" from="7" to="7" access="RW" resetVal="" desc="When set Timer Enable controls counting." />\r
- </register>\r
- <register name="Debug_Timer_PERIOD" address="0x40004F04" bitWidth="16" desc="TMRx.PER0 - Assigned Period" />\r
- <register name="Debug_Timer_COUNTER" address="0x40004F06" bitWidth="16" desc="TMRx.CNT_CMP0 - Current Down Counter Value" />\r
- </block>\r
+ <block name="SD_RX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="SD_TX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="SD_TX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="SCSI_RX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="SCSI_RX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="Debug_Timer_Interrupt" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="SCSI_Out_Mux" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="Bootloadable_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="SCSI_Out_Ctl" BASE="0x0" SIZE="0x0" desc="" visible="true">\r
- <register name="SCSI_Out_Ctl_CONTROL_REG" address="0x40006473" bitWidth="8" desc="" />\r
- </block>\r
- <block name="SCSI_Out_Bits" BASE="0x0" SIZE="0x0" desc="" visible="true">\r
- <register name="SCSI_Out_Bits_CONTROL_REG" address="0x40006470" bitWidth="8" desc="" />\r
- </block>\r
+ <block name="SCSI_TX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="SD_RX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="SCSI_TX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="SD_CD" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="SD_Init_Clk" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="SD_Data_Clk" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="SD_DAT2" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="SD_CD" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="SCSI_CTL_PHASE" BASE="0x0" SIZE="0x0" desc="" visible="true">\r
+ <register name="SCSI_CTL_PHASE_CONTROL_REG" address="0x40006472" bitWidth="8" desc="" />\r
+ </block>\r
+ <block name="SD_DAT1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="SCSI_Out_DBx" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="SCSI_In_DBx" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="SD_Clk_Ctl" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="SD_Data_Clk" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="SD_Clk_mux" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="SD_Clk_Ctl" BASE="0x0" SIZE="0x0" desc="" visible="true">\r
- <register name="SD_Clk_Ctl_CONTROL_REG" address="0x40006472" bitWidth="8" desc="" />\r
- </block>\r
- <block name="SD_DAT1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="SD_CS" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="CFG_EEPROM" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="SD_MOSI" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="SD_SCK" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="OddParityGen_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="SCSI_CTL_PHASE" BASE="0x0" SIZE="0x0" desc="" visible="true">\r
- <register name="SCSI_CTL_PHASE_CONTROL_REG" address="0x40006475" bitWidth="8" desc="" />\r
- </block>\r
+ <block name="SCSI_CLK" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="SD_MOSI" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="SCSI_RST" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="SCSI_RST_ISR" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="SCSI_ATN" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="SCSI_Out" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="SCSI_In" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="CFG_EEPROM" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
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+ <block name="SD_CS" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
</blockRegMap>
\ No newline at end of file
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<width>32</width>\r
<peripherals>\r
<peripheral>\r
- <name>USBFS</name>\r
- <description>USBFS</description>\r
- <baseAddress>0x40004394</baseAddress>\r
+ <name>SCSI_Out_Bits</name>\r
+ <description>No description available</description>\r
+ <baseAddress>0x4000647C</baseAddress>\r
<addressBlock>\r
<offset>0</offset>\r
- <size>0x1D0A</size>\r
+ <size>0x1</size>\r
<usage>registers</usage>\r
</addressBlock>\r
<registers>\r
<register>\r
- <name>USBFS_PM_USB_CR0</name>\r
- <description>USB Power Mode Control Register 0</description>\r
+ <name>SCSI_Out_Bits_CONTROL_REG</name>\r
+ <description>No description available</description>\r
+ <addressOffset>0x0</addressOffset>\r
+ <size>8</size>\r
+ <access>read-write</access>\r
+ <resetValue>0</resetValue>\r
+ <resetMask>0</resetMask>\r
+ </register>\r
+ </registers>\r
+ </peripheral>\r
+ <peripheral>\r
+ <name>Debug_Timer</name>\r
+ <description>No description available</description>\r
+ <baseAddress>0x400043A3</baseAddress>\r
+ <addressBlock>\r
+ <offset>0</offset>\r
+ <size>0xB64</size>\r
+ <usage>registers</usage>\r
+ </addressBlock>\r
+ <registers>\r
+ <register>\r
+ <name>Debug_Timer_GLOBAL_ENABLE</name>\r
+ <description>PM.ACT.CFG</description>\r
<addressOffset>0x0</addressOffset>\r
<size>8</size>\r
<access>read-write</access>\r
<resetMask>0</resetMask>\r
<fields>\r
<field>\r
- <name>fsusbio_ref_en</name>\r
- <description>No description available</description>\r
+ <name>en_timer</name>\r
+ <description>Enable timer/counters.</description>\r
+ <lsb>0</lsb>\r
+ <msb>3</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ </fields>\r
+ </register>\r
+ <register>\r
+ <name>Debug_Timer_CONTROL</name>\r
+ <description>TMRx.CFG0</description>\r
+ <addressOffset>0xB5D</addressOffset>\r
+ <size>8</size>\r
+ <access>read-write</access>\r
+ <resetValue>0</resetValue>\r
+ <resetMask>0</resetMask>\r
+ <fields>\r
+ <field>\r
+ <name>EN</name>\r
+ <description>Enables timer/comparator.</description>\r
<lsb>0</lsb>\r
<msb>0</msb>\r
<access>read-write</access>\r
</field>\r
<field>\r
- <name>fsusbio_pd_n</name>\r
- <description>No description available</description>\r
+ <name>MODE</name>\r
+ <description>Mode. (0 = Timer; 1 = Comparator)</description>\r
<lsb>1</lsb>\r
<msb>1</msb>\r
<access>read-write</access>\r
+ <enumeratedValues>\r
+ <enumeratedValue>\r
+ <name>Timer</name>\r
+ <description>Timer mode. CNT/CMP register holds timer count value.</description>\r
+ <value>0</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>Comparator</name>\r
+ <description>Comparator mode. CNT/CMP register holds comparator threshold value.</description>\r
+ <value>1</value>\r
+ </enumeratedValue>\r
+ </enumeratedValues>\r
</field>\r
<field>\r
- <name>fsusbio_pd_pullup_n</name>\r
- <description>No description available</description>\r
+ <name>ONESHOT</name>\r
+ <description>Timer stops upon reaching stop condition defined by TMR_CFG bits. Can be restarted by asserting TIMER RESET or disabling and re-enabling block.</description>\r
<lsb>2</lsb>\r
<msb>2</msb>\r
<access>read-write</access>\r
</field>\r
- </fields>\r
- </register>\r
- <register>\r
- <name>USBFS_PM_ACT_CFG</name>\r
- <description>Active Power Mode Configuration Register</description>\r
- <addressOffset>0x11</addressOffset>\r
- <size>8</size>\r
- <access>read-write</access>\r
- <resetValue>0</resetValue>\r
- <resetMask>0</resetMask>\r
- </register>\r
- <register>\r
- <name>USBFS_PM_STBY_CFG</name>\r
- <description>Standby Power Mode Configuration Register</description>\r
- <addressOffset>0x21</addressOffset>\r
- <size>8</size>\r
- <access>read-write</access>\r
- <resetValue>0</resetValue>\r
- <resetMask>0</resetMask>\r
- </register>\r
- <register>\r
- <name>USBFS_PRT_PS</name>\r
- <description>Port Pin State Register</description>\r
- <addressOffset>0xE5D</addressOffset>\r
- <size>8</size>\r
- <access>read-write</access>\r
- <resetValue>0</resetValue>\r
- <resetMask>0</resetMask>\r
- <fields>\r
<field>\r
- <name>PinState_DP</name>\r
- <description>No description available</description>\r
- <lsb>6</lsb>\r
- <msb>6</msb>\r
- <access>read-only</access>\r
+ <name>CMP_BUFF</name>\r
+ <description>Buffer compare register. Compare register updates only on timer terminal count.</description>\r
+ <lsb>3</lsb>\r
+ <msb>3</msb>\r
+ <access>read-write</access>\r
</field>\r
<field>\r
- <name>PinState_DM</name>\r
- <description>No description available</description>\r
- <lsb>7</lsb>\r
- <msb>7</msb>\r
- <access>read-only</access>\r
+ <name>INV</name>\r
+ <description>Invert sense of TIMEREN signal</description>\r
+ <lsb>4</lsb>\r
+ <msb>4</msb>\r
+ <access>read-write</access>\r
</field>\r
- </fields>\r
- </register>\r
- <register>\r
- <name>USBFS_PRT_DM0</name>\r
- <description>Port Drive Mode Register</description>\r
- <addressOffset>0xE5E</addressOffset>\r
- <size>8</size>\r
- <access>read-write</access>\r
- <resetValue>0</resetValue>\r
- <resetMask>0</resetMask>\r
- <fields>\r
<field>\r
- <name>DriveMode_DP</name>\r
- <description>No description available</description>\r
- <lsb>6</lsb>\r
- <msb>6</msb>\r
+ <name>DB</name>\r
+ <description>Deadband mode--Deadband phases phi1 and phi2 are outputted on CMP and TC output pins respectively.</description>\r
+ <lsb>5</lsb>\r
+ <msb>5</msb>\r
<access>read-write</access>\r
+ <enumeratedValues>\r
+ <enumeratedValue>\r
+ <name>Timer</name>\r
+ <description>CMP and TC are output.</description>\r
+ <value>0</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>Deadband</name>\r
+ <description>PHI1 (instead of CMP) and PHI2 (instead of TC) are output.</description>\r
+ <value>1</value>\r
+ </enumeratedValue>\r
+ </enumeratedValues>\r
</field>\r
<field>\r
- <name>DriveMode_DM</name>\r
- <description>No description available</description>\r
- <lsb>7</lsb>\r
+ <name>DEADBAND_PERIOD</name>\r
+ <description>Deadband Period</description>\r
+ <lsb>6</lsb>\r
<msb>7</msb>\r
<access>read-write</access>\r
</field>\r
</fields>\r
</register>\r
<register>\r
- <name>USBFS_PRT_DM1</name>\r
- <description>Port Drive Mode Register</description>\r
- <addressOffset>0xE5F</addressOffset>\r
+ <name>Debug_Timer_CONTROL2</name>\r
+ <description>TMRx.CFG1</description>\r
+ <addressOffset>0xB5E</addressOffset>\r
<size>8</size>\r
<access>read-write</access>\r
<resetValue>0</resetValue>\r
<resetMask>0</resetMask>\r
<fields>\r
<field>\r
- <name>PullUp_en_DP</name>\r
- <description>No description available</description>\r
- <lsb>6</lsb>\r
+ <name>IRQ_SEL</name>\r
+ <description>Irq selection. (0 = raw interrupts; 1 = status register interrupts)</description>\r
+ <lsb>0</lsb>\r
+ <msb>0</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>FTC</name>\r
+ <description>First Terminal Count (FTC). Setting this bit forces a single pulse on the TC pin when first enabled.</description>\r
+ <lsb>1</lsb>\r
+ <msb>1</msb>\r
+ <access>read-write</access>\r
+ <enumeratedValues>\r
+ <enumeratedValue>\r
+ <name>Disable_FTC</name>\r
+ <description>Disable the single cycle pulse, which signifies the timer is starting.</description>\r
+ <value>0</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>Enable_FTC</name>\r
+ <description>Enable the single cycle pulse, which signifies the timer is starting.</description>\r
+ <value>1</value>\r
+ </enumeratedValue>\r
+ </enumeratedValues>\r
+ </field>\r
+ <field>\r
+ <name>DCOR</name>\r
+ <description>Disable Clear on Read (DCOR) of Status Register SR0.</description>\r
+ <lsb>2</lsb>\r
+ <msb>2</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>DBMODE</name>\r
+ <description>Deadband mode (asynchronous/synchronous). CMP output pin is also affected when not in deadband mode (CFG0.DEADBAND).</description>\r
+ <lsb>3</lsb>\r
+ <msb>3</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>CLK_BUS_EN_SEL</name>\r
+ <description>Digital Global Clock selection.</description>\r
+ <lsb>4</lsb>\r
<msb>6</msb>\r
<access>read-write</access>\r
</field>\r
<field>\r
- <name>PullUp_en_DM</name>\r
- <description>No description available</description>\r
+ <name>BUS_CLK_SEL</name>\r
+ <description>Bus Clock selection.</description>\r
<lsb>7</lsb>\r
<msb>7</msb>\r
<access>read-write</access>\r
</fields>\r
</register>\r
<register>\r
- <name>USBFS_PRT_INP_DIS</name>\r
- <description>Input buffer disable override</description>\r
- <addressOffset>0xE64</addressOffset>\r
+ <name>Debug_Timer_CONTROL3_</name>\r
+ <description>TMRx.CFG2</description>\r
+ <addressOffset>0xB5F</addressOffset>\r
<size>8</size>\r
<access>read-write</access>\r
<resetValue>0</resetValue>\r
<resetMask>0</resetMask>\r
<fields>\r
<field>\r
- <name>seinput_dis_dp</name>\r
- <description>No description available</description>\r
- <lsb>6</lsb>\r
+ <name>TMR_CFG</name>\r
+ <description>Timer configuration (MODE = 0): 000 = Continuous; 001 = Pulsewidth; 010 = Period; 011 = Stop on IRQ</description>\r
+ <lsb>0</lsb>\r
+ <msb>1</msb>\r
+ <access>read-write</access>\r
+ <enumeratedValues>\r
+ <enumeratedValue>\r
+ <name>Continuous</name>\r
+ <description>Timer runs while EN bit of CFG0 register is set to '1'.</description>\r
+ <value>0</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>Pulsewidth</name>\r
+ <description>Timer runs from positive to negative edge of TIMEREN.</description>\r
+ <value>1</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>Period</name>\r
+ <description>Timer runs from positive to positive edge of TIMEREN.</description>\r
+ <value>2</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>Irq</name>\r
+ <description>Timer runs until IRQ.</description>\r
+ <value>3</value>\r
+ </enumeratedValue>\r
+ </enumeratedValues>\r
+ </field>\r
+ <field>\r
+ <name>COD</name>\r
+ <description>Clear On Disable (COD). Clears or gates outputs to zero.</description>\r
+ <lsb>2</lsb>\r
+ <msb>2</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>ROD</name>\r
+ <description>Reset On Disable (ROD). Resets internal state of output logic</description>\r
+ <lsb>3</lsb>\r
+ <msb>3</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>CMP_CFG</name>\r
+ <description>Comparator configurations</description>\r
+ <lsb>4</lsb>\r
<msb>6</msb>\r
<access>read-write</access>\r
+ <enumeratedValues>\r
+ <enumeratedValue>\r
+ <name>Equal</name>\r
+ <description>Compare Equal </description>\r
+ <value>0</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>Less_than</name>\r
+ <description>Compare Less Than </description>\r
+ <value>1</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>Less_than_or_equal</name>\r
+ <description>Compare Less Than or Equal .</description>\r
+ <value>2</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>Greater</name>\r
+ <description>Compare Greater Than .</description>\r
+ <value>3</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>Greater_than_or_equal</name>\r
+ <description>Compare Greater Than or Equal </description>\r
+ <value>4</value>\r
+ </enumeratedValue>\r
+ </enumeratedValues>\r
</field>\r
<field>\r
- <name>seinput_dis_dm</name>\r
- <description>No description available</description>\r
+ <name>HW_EN</name>\r
+ <description>When set Timer Enable controls counting.</description>\r
<lsb>7</lsb>\r
<msb>7</msb>\r
<access>read-write</access>\r
</fields>\r
</register>\r
<register>\r
- <name>USBFS_EP0_DR0</name>\r
- <description>bmRequestType</description>\r
- <addressOffset>0x1C6C</addressOffset>\r
- <size>8</size>\r
- <access>read-write</access>\r
- <resetValue>0</resetValue>\r
- <resetMask>0</resetMask>\r
- </register>\r
- <register>\r
- <name>USBFS_EP0_DR1</name>\r
- <description>bRequest</description>\r
- <addressOffset>0x1C6D</addressOffset>\r
- <size>8</size>\r
- <access>read-write</access>\r
- <resetValue>0</resetValue>\r
- <resetMask>0</resetMask>\r
- </register>\r
- <register>\r
- <name>USBFS_EP0_DR2</name>\r
- <description>wValueLo</description>\r
- <addressOffset>0x1C6E</addressOffset>\r
- <size>8</size>\r
+ <name>Debug_Timer_PERIOD</name>\r
+ <description>TMRx.PER0 - Assigned Period</description>\r
+ <addressOffset>0xB61</addressOffset>\r
+ <size>16</size>\r
<access>read-write</access>\r
<resetValue>0</resetValue>\r
<resetMask>0</resetMask>\r
</register>\r
<register>\r
- <name>USBFS_EP0_DR3</name>\r
- <description>wValueHi</description>\r
- <addressOffset>0x1C6F</addressOffset>\r
- <size>8</size>\r
+ <name>Debug_Timer_COUNTER</name>\r
+ <description>TMRx.CNT_CMP0 - Current Down Counter Value</description>\r
+ <addressOffset>0xB63</addressOffset>\r
+ <size>16</size>\r
<access>read-write</access>\r
<resetValue>0</resetValue>\r
<resetMask>0</resetMask>\r
</register>\r
+ </registers>\r
+ </peripheral>\r
+ <peripheral>\r
+ <name>SCSI_Out_Ctl</name>\r
+ <description>No description available</description>\r
+ <baseAddress>0x40006577</baseAddress>\r
+ <addressBlock>\r
+ <offset>0</offset>\r
+ <size>0x1</size>\r
+ <usage>registers</usage>\r
+ </addressBlock>\r
+ <registers>\r
<register>\r
- <name>USBFS_EP0_DR4</name>\r
- <description>wIndexLo</description>\r
- <addressOffset>0x1C70</addressOffset>\r
+ <name>SCSI_Out_Ctl_CONTROL_REG</name>\r
+ <description>No description available</description>\r
+ <addressOffset>0x0</addressOffset>\r
<size>8</size>\r
<access>read-write</access>\r
<resetValue>0</resetValue>\r
<resetMask>0</resetMask>\r
</register>\r
+ </registers>\r
+ </peripheral>\r
+ <peripheral>\r
+ <name>USBFS</name>\r
+ <description>USBFS</description>\r
+ <baseAddress>0x40004394</baseAddress>\r
+ <addressBlock>\r
+ <offset>0</offset>\r
+ <size>0x1D0A</size>\r
+ <usage>registers</usage>\r
+ </addressBlock>\r
+ <registers>\r
<register>\r
- <name>USBFS_EP0_DR5</name>\r
- <description>wIndexHi</description>\r
- <addressOffset>0x1C71</addressOffset>\r
+ <name>USBFS_PM_USB_CR0</name>\r
+ <description>USB Power Mode Control Register 0</description>\r
+ <addressOffset>0x0</addressOffset>\r
<size>8</size>\r
<access>read-write</access>\r
<resetValue>0</resetValue>\r
<resetMask>0</resetMask>\r
+ <fields>\r
+ <field>\r
+ <name>fsusbio_ref_en</name>\r
+ <description>No description available</description>\r
+ <lsb>0</lsb>\r
+ <msb>0</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>fsusbio_pd_n</name>\r
+ <description>No description available</description>\r
+ <lsb>1</lsb>\r
+ <msb>1</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>fsusbio_pd_pullup_n</name>\r
+ <description>No description available</description>\r
+ <lsb>2</lsb>\r
+ <msb>2</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ </fields>\r
</register>\r
<register>\r
- <name>USBFS_EP0_DR6</name>\r
- <description>lengthLo</description>\r
- <addressOffset>0x1C72</addressOffset>\r
+ <name>USBFS_PM_ACT_CFG</name>\r
+ <description>Active Power Mode Configuration Register</description>\r
+ <addressOffset>0x11</addressOffset>\r
<size>8</size>\r
<access>read-write</access>\r
<resetValue>0</resetValue>\r
<resetMask>0</resetMask>\r
</register>\r
<register>\r
- <name>USBFS_EP0_DR7</name>\r
- <description>lengthHi</description>\r
- <addressOffset>0x1C73</addressOffset>\r
+ <name>USBFS_PM_STBY_CFG</name>\r
+ <description>Standby Power Mode Configuration Register</description>\r
+ <addressOffset>0x21</addressOffset>\r
<size>8</size>\r
<access>read-write</access>\r
<resetValue>0</resetValue>\r
<resetMask>0</resetMask>\r
</register>\r
<register>\r
- <name>USBFS_CR0</name>\r
- <description>USB Control Register 0</description>\r
- <addressOffset>0x1C74</addressOffset>\r
+ <name>USBFS_PRT_PS</name>\r
+ <description>Port Pin State Register</description>\r
+ <addressOffset>0xE5D</addressOffset>\r
<size>8</size>\r
<access>read-write</access>\r
<resetValue>0</resetValue>\r
<resetMask>0</resetMask>\r
<fields>\r
<field>\r
- <name>device_address</name>\r
+ <name>PinState_DP</name>\r
<description>No description available</description>\r
<lsb>6</lsb>\r
- <msb>0</msb>\r
+ <msb>6</msb>\r
<access>read-only</access>\r
</field>\r
<field>\r
- <name>usb_enable</name>\r
+ <name>PinState_DM</name>\r
<description>No description available</description>\r
<lsb>7</lsb>\r
<msb>7</msb>\r
- <access>read-write</access>\r
+ <access>read-only</access>\r
</field>\r
</fields>\r
</register>\r
<register>\r
- <name>USBFS_CR1</name>\r
- <description>USB Control Register 1</description>\r
- <addressOffset>0x1C75</addressOffset>\r
+ <name>USBFS_PRT_DM0</name>\r
+ <description>Port Drive Mode Register</description>\r
+ <addressOffset>0xE5E</addressOffset>\r
<size>8</size>\r
<access>read-write</access>\r
<resetValue>0</resetValue>\r
<resetMask>0</resetMask>\r
<fields>\r
<field>\r
- <name>reg_enable</name>\r
- <description>No description available</description>\r
- <lsb>0</lsb>\r
- <msb>0</msb>\r
- <access>read-write</access>\r
- </field>\r
- <field>\r
- <name>enable_lock</name>\r
- <description>No description available</description>\r
- <lsb>1</lsb>\r
- <msb>1</msb>\r
- <access>read-write</access>\r
- </field>\r
- <field>\r
- <name>bus_activity</name>\r
+ <name>DriveMode_DP</name>\r
<description>No description available</description>\r
- <lsb>2</lsb>\r
- <msb>2</msb>\r
+ <lsb>6</lsb>\r
+ <msb>6</msb>\r
<access>read-write</access>\r
</field>\r
<field>\r
- <name>trim_offset_msb</name>\r
+ <name>DriveMode_DM</name>\r
<description>No description available</description>\r
- <lsb>3</lsb>\r
- <msb>3</msb>\r
+ <lsb>7</lsb>\r
+ <msb>7</msb>\r
<access>read-write</access>\r
</field>\r
</fields>\r
</register>\r
- <register>\r
- <name>USBFS_SIE_EP1_CR0</name>\r
- <description>The Endpoint1 Control Register</description>\r
- <addressOffset>0x1C7A</addressOffset>\r
- <size>8</size>\r
- <access>read-write</access>\r
- <resetValue>0</resetValue>\r
- <resetMask>0</resetMask>\r
- </register>\r
- <register>\r
- <name>USBFS_USBIO_CR0</name>\r
- <description>USBIO Control Register 0</description>\r
- <addressOffset>0x1C7C</addressOffset>\r
- <size>8</size>\r
- <access>read-write</access>\r
- <resetValue>0</resetValue>\r
- <resetMask>0</resetMask>\r
- <fields>\r
- <field>\r
- <name>rd</name>\r
- <description>No description available</description>\r
- <lsb>0</lsb>\r
- <msb>0</msb>\r
- <access>read-only</access>\r
- </field>\r
- <field>\r
- <name>td</name>\r
- <description>No description available</description>\r
- <lsb>5</lsb>\r
- <msb>5</msb>\r
- <access>read-write</access>\r
- </field>\r
+ <register>\r
+ <name>USBFS_PRT_DM1</name>\r
+ <description>Port Drive Mode Register</description>\r
+ <addressOffset>0xE5F</addressOffset>\r
+ <size>8</size>\r
+ <access>read-write</access>\r
+ <resetValue>0</resetValue>\r
+ <resetMask>0</resetMask>\r
+ <fields>\r
<field>\r
- <name>tse0</name>\r
+ <name>PullUp_en_DP</name>\r
<description>No description available</description>\r
<lsb>6</lsb>\r
<msb>6</msb>\r
<access>read-write</access>\r
</field>\r
<field>\r
- <name>ten</name>\r
+ <name>PullUp_en_DM</name>\r
<description>No description available</description>\r
<lsb>7</lsb>\r
<msb>7</msb>\r
</fields>\r
</register>\r
<register>\r
- <name>USBFS_USBIO_CR1</name>\r
- <description>USBIO Control Register 1</description>\r
- <addressOffset>0x1C7E</addressOffset>\r
+ <name>USBFS_PRT_INP_DIS</name>\r
+ <description>Input buffer disable override</description>\r
+ <addressOffset>0xE64</addressOffset>\r
<size>8</size>\r
<access>read-write</access>\r
<resetValue>0</resetValue>\r
<resetMask>0</resetMask>\r
<fields>\r
<field>\r
- <name>dmo</name>\r
- <description>No description available</description>\r
- <lsb>0</lsb>\r
- <msb>0</msb>\r
- <access>read-only</access>\r
- </field>\r
- <field>\r
- <name>dpo</name>\r
- <description>No description available</description>\r
- <lsb>1</lsb>\r
- <msb>1</msb>\r
- <access>read-only</access>\r
- </field>\r
- <field>\r
- <name>usbpuen</name>\r
+ <name>seinput_dis_dp</name>\r
<description>No description available</description>\r
- <lsb>2</lsb>\r
- <msb>2</msb>\r
+ <lsb>6</lsb>\r
+ <msb>6</msb>\r
<access>read-write</access>\r
</field>\r
<field>\r
- <name>iomode</name>\r
+ <name>seinput_dis_dm</name>\r
<description>No description available</description>\r
- <lsb>5</lsb>\r
- <msb>5</msb>\r
+ <lsb>7</lsb>\r
+ <msb>7</msb>\r
<access>read-write</access>\r
</field>\r
</fields>\r
</register>\r
<register>\r
- <name>USBFS_SIE_EP2_CR0</name>\r
- <description>The Endpoint2 Control Register</description>\r
- <addressOffset>0x1C8A</addressOffset>\r
- <size>8</size>\r
- <access>read-write</access>\r
- <resetValue>0</resetValue>\r
- <resetMask>0</resetMask>\r
- </register>\r
- <register>\r
- <name>USBFS_SIE_EP3_CR0</name>\r
- <description>The Endpoint3 Control Register</description>\r
- <addressOffset>0x1C9A</addressOffset>\r
- <size>8</size>\r
- <access>read-write</access>\r
- <resetValue>0</resetValue>\r
- <resetMask>0</resetMask>\r
- </register>\r
- <register>\r
- <name>USBFS_SIE_EP4_CR0</name>\r
- <description>The Endpoint4 Control Register</description>\r
- <addressOffset>0x1CAA</addressOffset>\r
- <size>8</size>\r
- <access>read-write</access>\r
- <resetValue>0</resetValue>\r
- <resetMask>0</resetMask>\r
- </register>\r
- <register>\r
- <name>USBFS_SIE_EP5_CR0</name>\r
- <description>The Endpoint5 Control Register</description>\r
- <addressOffset>0x1CBA</addressOffset>\r
+ <name>USBFS_EP0_DR0</name>\r
+ <description>bmRequestType</description>\r
+ <addressOffset>0x1C6C</addressOffset>\r
<size>8</size>\r
<access>read-write</access>\r
<resetValue>0</resetValue>\r
<resetMask>0</resetMask>\r
</register>\r
<register>\r
- <name>USBFS_SIE_EP6_CR0</name>\r
- <description>The Endpoint6 Control Register</description>\r
- <addressOffset>0x1CCA</addressOffset>\r
+ <name>USBFS_EP0_DR1</name>\r
+ <description>bRequest</description>\r
+ <addressOffset>0x1C6D</addressOffset>\r
<size>8</size>\r
<access>read-write</access>\r
<resetValue>0</resetValue>\r
<resetMask>0</resetMask>\r
</register>\r
<register>\r
- <name>USBFS_SIE_EP7_CR0</name>\r
- <description>The Endpoint7 Control Register</description>\r
- <addressOffset>0x1CDA</addressOffset>\r
+ <name>USBFS_EP0_DR2</name>\r
+ <description>wValueLo</description>\r
+ <addressOffset>0x1C6E</addressOffset>\r
<size>8</size>\r
<access>read-write</access>\r
<resetValue>0</resetValue>\r
<resetMask>0</resetMask>\r
</register>\r
<register>\r
- <name>USBFS_SIE_EP8_CR0</name>\r
- <description>The Endpoint8 Control Register</description>\r
- <addressOffset>0x1CEA</addressOffset>\r
+ <name>USBFS_EP0_DR3</name>\r
+ <description>wValueHi</description>\r
+ <addressOffset>0x1C6F</addressOffset>\r
<size>8</size>\r
<access>read-write</access>\r
<resetValue>0</resetValue>\r
<resetMask>0</resetMask>\r
</register>\r
<register>\r
- <name>USBFS_BUF_SIZE</name>\r
- <description>Dedicated Endpoint Buffer Size Register</description>\r
- <addressOffset>0x1CF8</addressOffset>\r
+ <name>USBFS_EP0_DR4</name>\r
+ <description>wIndexLo</description>\r
+ <addressOffset>0x1C70</addressOffset>\r
<size>8</size>\r
<access>read-write</access>\r
<resetValue>0</resetValue>\r
<resetMask>0</resetMask>\r
</register>\r
<register>\r
- <name>USBFS_EP_ACTIVE</name>\r
- <description>Endpoint Active Indication Register</description>\r
- <addressOffset>0x1CFA</addressOffset>\r
+ <name>USBFS_EP0_DR5</name>\r
+ <description>wIndexHi</description>\r
+ <addressOffset>0x1C71</addressOffset>\r
<size>8</size>\r
<access>read-write</access>\r
<resetValue>0</resetValue>\r
<resetMask>0</resetMask>\r
</register>\r
<register>\r
- <name>USBFS_EP_TYPE</name>\r
- <description>Endpoint Type (IN/OUT) Indication</description>\r
- <addressOffset>0x1CFB</addressOffset>\r
+ <name>USBFS_EP0_DR6</name>\r
+ <description>lengthLo</description>\r
+ <addressOffset>0x1C72</addressOffset>\r
<size>8</size>\r
<access>read-write</access>\r
<resetValue>0</resetValue>\r
<resetMask>0</resetMask>\r
</register>\r
<register>\r
- <name>USBFS_USB_CLK_EN</name>\r
- <description>USB Block Clock Enable Register</description>\r
- <addressOffset>0x1D09</addressOffset>\r
+ <name>USBFS_EP0_DR7</name>\r
+ <description>lengthHi</description>\r
+ <addressOffset>0x1C73</addressOffset>\r
<size>8</size>\r
<access>read-write</access>\r
<resetValue>0</resetValue>\r
<resetMask>0</resetMask>\r
</register>\r
- </registers>\r
- </peripheral>\r
- <peripheral>\r
- <name>Debug_Timer</name>\r
- <description>No description available</description>\r
- <baseAddress>0x400043A3</baseAddress>\r
- <addressBlock>\r
- <offset>0</offset>\r
- <size>0xB64</size>\r
- <usage>registers</usage>\r
- </addressBlock>\r
- <registers>\r
<register>\r
- <name>Debug_Timer_GLOBAL_ENABLE</name>\r
- <description>PM.ACT.CFG</description>\r
- <addressOffset>0x0</addressOffset>\r
+ <name>USBFS_CR0</name>\r
+ <description>USB Control Register 0</description>\r
+ <addressOffset>0x1C74</addressOffset>\r
<size>8</size>\r
<access>read-write</access>\r
<resetValue>0</resetValue>\r
<resetMask>0</resetMask>\r
<fields>\r
<field>\r
- <name>en_timer</name>\r
- <description>Enable timer/counters.</description>\r
- <lsb>0</lsb>\r
- <msb>3</msb>\r
+ <name>device_address</name>\r
+ <description>No description available</description>\r
+ <lsb>6</lsb>\r
+ <msb>0</msb>\r
+ <access>read-only</access>\r
+ </field>\r
+ <field>\r
+ <name>usb_enable</name>\r
+ <description>No description available</description>\r
+ <lsb>7</lsb>\r
+ <msb>7</msb>\r
<access>read-write</access>\r
</field>\r
</fields>\r
</register>\r
<register>\r
- <name>Debug_Timer_CONTROL</name>\r
- <description>TMRx.CFG0</description>\r
- <addressOffset>0xB5D</addressOffset>\r
+ <name>USBFS_CR1</name>\r
+ <description>USB Control Register 1</description>\r
+ <addressOffset>0x1C75</addressOffset>\r
<size>8</size>\r
<access>read-write</access>\r
<resetValue>0</resetValue>\r
<resetMask>0</resetMask>\r
<fields>\r
<field>\r
- <name>EN</name>\r
- <description>Enables timer/comparator.</description>\r
+ <name>reg_enable</name>\r
+ <description>No description available</description>\r
<lsb>0</lsb>\r
<msb>0</msb>\r
<access>read-write</access>\r
</field>\r
<field>\r
- <name>MODE</name>\r
- <description>Mode. (0 = Timer; 1 = Comparator)</description>\r
+ <name>enable_lock</name>\r
+ <description>No description available</description>\r
<lsb>1</lsb>\r
<msb>1</msb>\r
<access>read-write</access>\r
- <enumeratedValues>\r
- <enumeratedValue>\r
- <name>Timer</name>\r
- <description>Timer mode. CNT/CMP register holds timer count value.</description>\r
- <value>0</value>\r
- </enumeratedValue>\r
- <enumeratedValue>\r
- <name>Comparator</name>\r
- <description>Comparator mode. CNT/CMP register holds comparator threshold value.</description>\r
- <value>1</value>\r
- </enumeratedValue>\r
- </enumeratedValues>\r
</field>\r
<field>\r
- <name>ONESHOT</name>\r
- <description>Timer stops upon reaching stop condition defined by TMR_CFG bits. Can be restarted by asserting TIMER RESET or disabling and re-enabling block.</description>\r
+ <name>bus_activity</name>\r
+ <description>No description available</description>\r
<lsb>2</lsb>\r
<msb>2</msb>\r
<access>read-write</access>\r
</field>\r
<field>\r
- <name>CMP_BUFF</name>\r
- <description>Buffer compare register. Compare register updates only on timer terminal count.</description>\r
+ <name>trim_offset_msb</name>\r
+ <description>No description available</description>\r
<lsb>3</lsb>\r
<msb>3</msb>\r
<access>read-write</access>\r
</field>\r
- <field>\r
- <name>INV</name>\r
- <description>Invert sense of TIMEREN signal</description>\r
- <lsb>4</lsb>\r
- <msb>4</msb>\r
- <access>read-write</access>\r
- </field>\r
- <field>\r
- <name>DB</name>\r
- <description>Deadband mode--Deadband phases phi1 and phi2 are outputted on CMP and TC output pins respectively.</description>\r
- <lsb>5</lsb>\r
- <msb>5</msb>\r
- <access>read-write</access>\r
- <enumeratedValues>\r
- <enumeratedValue>\r
- <name>Timer</name>\r
- <description>CMP and TC are output.</description>\r
- <value>0</value>\r
- </enumeratedValue>\r
- <enumeratedValue>\r
- <name>Deadband</name>\r
- <description>PHI1 (instead of CMP) and PHI2 (instead of TC) are output.</description>\r
- <value>1</value>\r
- </enumeratedValue>\r
- </enumeratedValues>\r
- </field>\r
- <field>\r
- <name>DEADBAND_PERIOD</name>\r
- <description>Deadband Period</description>\r
- <lsb>6</lsb>\r
- <msb>7</msb>\r
- <access>read-write</access>\r
- </field>\r
</fields>\r
</register>\r
<register>\r
- <name>Debug_Timer_CONTROL2</name>\r
- <description>TMRx.CFG1</description>\r
- <addressOffset>0xB5E</addressOffset>\r
+ <name>USBFS_SIE_EP1_CR0</name>\r
+ <description>The Endpoint1 Control Register</description>\r
+ <addressOffset>0x1C7A</addressOffset>\r
<size>8</size>\r
- <access>read-write</access>\r
- <resetValue>0</resetValue>\r
- <resetMask>0</resetMask>\r
- <fields>\r
- <field>\r
- <name>IRQ_SEL</name>\r
- <description>Irq selection. (0 = raw interrupts; 1 = status register interrupts)</description>\r
- <lsb>0</lsb>\r
- <msb>0</msb>\r
- <access>read-write</access>\r
- </field>\r
- <field>\r
- <name>FTC</name>\r
- <description>First Terminal Count (FTC). Setting this bit forces a single pulse on the TC pin when first enabled.</description>\r
- <lsb>1</lsb>\r
- <msb>1</msb>\r
- <access>read-write</access>\r
- <enumeratedValues>\r
- <enumeratedValue>\r
- <name>Disable_FTC</name>\r
- <description>Disable the single cycle pulse, which signifies the timer is starting.</description>\r
- <value>0</value>\r
- </enumeratedValue>\r
- <enumeratedValue>\r
- <name>Enable_FTC</name>\r
- <description>Enable the single cycle pulse, which signifies the timer is starting.</description>\r
- <value>1</value>\r
- </enumeratedValue>\r
- </enumeratedValues>\r
- </field>\r
+ <access>read-write</access>\r
+ <resetValue>0</resetValue>\r
+ <resetMask>0</resetMask>\r
+ </register>\r
+ <register>\r
+ <name>USBFS_USBIO_CR0</name>\r
+ <description>USBIO Control Register 0</description>\r
+ <addressOffset>0x1C7C</addressOffset>\r
+ <size>8</size>\r
+ <access>read-write</access>\r
+ <resetValue>0</resetValue>\r
+ <resetMask>0</resetMask>\r
+ <fields>\r
<field>\r
- <name>DCOR</name>\r
- <description>Disable Clear on Read (DCOR) of Status Register SR0.</description>\r
- <lsb>2</lsb>\r
- <msb>2</msb>\r
- <access>read-write</access>\r
+ <name>rd</name>\r
+ <description>No description available</description>\r
+ <lsb>0</lsb>\r
+ <msb>0</msb>\r
+ <access>read-only</access>\r
</field>\r
<field>\r
- <name>DBMODE</name>\r
- <description>Deadband mode (asynchronous/synchronous). CMP output pin is also affected when not in deadband mode (CFG0.DEADBAND).</description>\r
- <lsb>3</lsb>\r
- <msb>3</msb>\r
+ <name>td</name>\r
+ <description>No description available</description>\r
+ <lsb>5</lsb>\r
+ <msb>5</msb>\r
<access>read-write</access>\r
</field>\r
<field>\r
- <name>CLK_BUS_EN_SEL</name>\r
- <description>Digital Global Clock selection.</description>\r
- <lsb>4</lsb>\r
+ <name>tse0</name>\r
+ <description>No description available</description>\r
+ <lsb>6</lsb>\r
<msb>6</msb>\r
<access>read-write</access>\r
</field>\r
<field>\r
- <name>BUS_CLK_SEL</name>\r
- <description>Bus Clock selection.</description>\r
+ <name>ten</name>\r
+ <description>No description available</description>\r
<lsb>7</lsb>\r
<msb>7</msb>\r
<access>read-write</access>\r
</fields>\r
</register>\r
<register>\r
- <name>Debug_Timer_CONTROL3_</name>\r
- <description>TMRx.CFG2</description>\r
- <addressOffset>0xB5F</addressOffset>\r
+ <name>USBFS_USBIO_CR1</name>\r
+ <description>USBIO Control Register 1</description>\r
+ <addressOffset>0x1C7E</addressOffset>\r
<size>8</size>\r
<access>read-write</access>\r
<resetValue>0</resetValue>\r
<resetMask>0</resetMask>\r
<fields>\r
<field>\r
- <name>TMR_CFG</name>\r
- <description>Timer configuration (MODE = 0): 000 = Continuous; 001 = Pulsewidth; 010 = Period; 011 = Stop on IRQ</description>\r
+ <name>dmo</name>\r
+ <description>No description available</description>\r
<lsb>0</lsb>\r
+ <msb>0</msb>\r
+ <access>read-only</access>\r
+ </field>\r
+ <field>\r
+ <name>dpo</name>\r
+ <description>No description available</description>\r
+ <lsb>1</lsb>\r
<msb>1</msb>\r
- <access>read-write</access>\r
- <enumeratedValues>\r
- <enumeratedValue>\r
- <name>Continuous</name>\r
- <description>Timer runs while EN bit of CFG0 register is set to '1'.</description>\r
- <value>0</value>\r
- </enumeratedValue>\r
- <enumeratedValue>\r
- <name>Pulsewidth</name>\r
- <description>Timer runs from positive to negative edge of TIMEREN.</description>\r
- <value>1</value>\r
- </enumeratedValue>\r
- <enumeratedValue>\r
- <name>Period</name>\r
- <description>Timer runs from positive to positive edge of TIMEREN.</description>\r
- <value>2</value>\r
- </enumeratedValue>\r
- <enumeratedValue>\r
- <name>Irq</name>\r
- <description>Timer runs until IRQ.</description>\r
- <value>3</value>\r
- </enumeratedValue>\r
- </enumeratedValues>\r
+ <access>read-only</access>\r
</field>\r
<field>\r
- <name>COD</name>\r
- <description>Clear On Disable (COD). Clears or gates outputs to zero.</description>\r
+ <name>usbpuen</name>\r
+ <description>No description available</description>\r
<lsb>2</lsb>\r
<msb>2</msb>\r
<access>read-write</access>\r
</field>\r
<field>\r
- <name>ROD</name>\r
- <description>Reset On Disable (ROD). Resets internal state of output logic</description>\r
- <lsb>3</lsb>\r
- <msb>3</msb>\r
- <access>read-write</access>\r
- </field>\r
- <field>\r
- <name>CMP_CFG</name>\r
- <description>Comparator configurations</description>\r
- <lsb>4</lsb>\r
- <msb>6</msb>\r
- <access>read-write</access>\r
- <enumeratedValues>\r
- <enumeratedValue>\r
- <name>Equal</name>\r
- <description>Compare Equal </description>\r
- <value>0</value>\r
- </enumeratedValue>\r
- <enumeratedValue>\r
- <name>Less_than</name>\r
- <description>Compare Less Than </description>\r
- <value>1</value>\r
- </enumeratedValue>\r
- <enumeratedValue>\r
- <name>Less_than_or_equal</name>\r
- <description>Compare Less Than or Equal .</description>\r
- <value>2</value>\r
- </enumeratedValue>\r
- <enumeratedValue>\r
- <name>Greater</name>\r
- <description>Compare Greater Than .</description>\r
- <value>3</value>\r
- </enumeratedValue>\r
- <enumeratedValue>\r
- <name>Greater_than_or_equal</name>\r
- <description>Compare Greater Than or Equal </description>\r
- <value>4</value>\r
- </enumeratedValue>\r
- </enumeratedValues>\r
- </field>\r
- <field>\r
- <name>HW_EN</name>\r
- <description>When set Timer Enable controls counting.</description>\r
- <lsb>7</lsb>\r
- <msb>7</msb>\r
+ <name>iomode</name>\r
+ <description>No description available</description>\r
+ <lsb>5</lsb>\r
+ <msb>5</msb>\r
<access>read-write</access>\r
</field>\r
</fields>\r
</register>\r
<register>\r
- <name>Debug_Timer_PERIOD</name>\r
- <description>TMRx.PER0 - Assigned Period</description>\r
- <addressOffset>0xB61</addressOffset>\r
- <size>16</size>\r
+ <name>USBFS_SIE_EP2_CR0</name>\r
+ <description>The Endpoint2 Control Register</description>\r
+ <addressOffset>0x1C8A</addressOffset>\r
+ <size>8</size>\r
<access>read-write</access>\r
<resetValue>0</resetValue>\r
<resetMask>0</resetMask>\r
</register>\r
<register>\r
- <name>Debug_Timer_COUNTER</name>\r
- <description>TMRx.CNT_CMP0 - Current Down Counter Value</description>\r
- <addressOffset>0xB63</addressOffset>\r
- <size>16</size>\r
+ <name>USBFS_SIE_EP3_CR0</name>\r
+ <description>The Endpoint3 Control Register</description>\r
+ <addressOffset>0x1C9A</addressOffset>\r
+ <size>8</size>\r
<access>read-write</access>\r
<resetValue>0</resetValue>\r
<resetMask>0</resetMask>\r
</register>\r
- </registers>\r
- </peripheral>\r
- <peripheral>\r
- <name>SCSI_Out_Ctl</name>\r
- <description>No description available</description>\r
- <baseAddress>0x40006473</baseAddress>\r
- <addressBlock>\r
- <offset>0</offset>\r
- <size>0x1</size>\r
- <usage>registers</usage>\r
- </addressBlock>\r
- <registers>\r
<register>\r
- <name>SCSI_Out_Ctl_CONTROL_REG</name>\r
- <description>No description available</description>\r
- <addressOffset>0x0</addressOffset>\r
+ <name>USBFS_SIE_EP4_CR0</name>\r
+ <description>The Endpoint4 Control Register</description>\r
+ <addressOffset>0x1CAA</addressOffset>\r
<size>8</size>\r
<access>read-write</access>\r
<resetValue>0</resetValue>\r
<resetMask>0</resetMask>\r
</register>\r
- </registers>\r
- </peripheral>\r
- <peripheral>\r
- <name>SCSI_Out_Bits</name>\r
- <description>No description available</description>\r
- <baseAddress>0x40006470</baseAddress>\r
- <addressBlock>\r
- <offset>0</offset>\r
- <size>0x1</size>\r
- <usage>registers</usage>\r
- </addressBlock>\r
- <registers>\r
<register>\r
- <name>SCSI_Out_Bits_CONTROL_REG</name>\r
- <description>No description available</description>\r
- <addressOffset>0x0</addressOffset>\r
+ <name>USBFS_SIE_EP5_CR0</name>\r
+ <description>The Endpoint5 Control Register</description>\r
+ <addressOffset>0x1CBA</addressOffset>\r
<size>8</size>\r
<access>read-write</access>\r
<resetValue>0</resetValue>\r
<resetMask>0</resetMask>\r
</register>\r
- </registers>\r
- </peripheral>\r
- <peripheral>\r
- <name>SD_Clk_Ctl</name>\r
- <description>No description available</description>\r
- <baseAddress>0x40006472</baseAddress>\r
- <addressBlock>\r
- <offset>0</offset>\r
- <size>0x1</size>\r
- <usage>registers</usage>\r
- </addressBlock>\r
- <registers>\r
<register>\r
- <name>SD_Clk_Ctl_CONTROL_REG</name>\r
- <description>No description available</description>\r
- <addressOffset>0x0</addressOffset>\r
+ <name>USBFS_SIE_EP6_CR0</name>\r
+ <description>The Endpoint6 Control Register</description>\r
+ <addressOffset>0x1CCA</addressOffset>\r
+ <size>8</size>\r
+ <access>read-write</access>\r
+ <resetValue>0</resetValue>\r
+ <resetMask>0</resetMask>\r
+ </register>\r
+ <register>\r
+ <name>USBFS_SIE_EP7_CR0</name>\r
+ <description>The Endpoint7 Control Register</description>\r
+ <addressOffset>0x1CDA</addressOffset>\r
+ <size>8</size>\r
+ <access>read-write</access>\r
+ <resetValue>0</resetValue>\r
+ <resetMask>0</resetMask>\r
+ </register>\r
+ <register>\r
+ <name>USBFS_SIE_EP8_CR0</name>\r
+ <description>The Endpoint8 Control Register</description>\r
+ <addressOffset>0x1CEA</addressOffset>\r
+ <size>8</size>\r
+ <access>read-write</access>\r
+ <resetValue>0</resetValue>\r
+ <resetMask>0</resetMask>\r
+ </register>\r
+ <register>\r
+ <name>USBFS_BUF_SIZE</name>\r
+ <description>Dedicated Endpoint Buffer Size Register</description>\r
+ <addressOffset>0x1CF8</addressOffset>\r
+ <size>8</size>\r
+ <access>read-write</access>\r
+ <resetValue>0</resetValue>\r
+ <resetMask>0</resetMask>\r
+ </register>\r
+ <register>\r
+ <name>USBFS_EP_ACTIVE</name>\r
+ <description>Endpoint Active Indication Register</description>\r
+ <addressOffset>0x1CFA</addressOffset>\r
+ <size>8</size>\r
+ <access>read-write</access>\r
+ <resetValue>0</resetValue>\r
+ <resetMask>0</resetMask>\r
+ </register>\r
+ <register>\r
+ <name>USBFS_EP_TYPE</name>\r
+ <description>Endpoint Type (IN/OUT) Indication</description>\r
+ <addressOffset>0x1CFB</addressOffset>\r
+ <size>8</size>\r
+ <access>read-write</access>\r
+ <resetValue>0</resetValue>\r
+ <resetMask>0</resetMask>\r
+ </register>\r
+ <register>\r
+ <name>USBFS_USB_CLK_EN</name>\r
+ <description>USB Block Clock Enable Register</description>\r
+ <addressOffset>0x1D09</addressOffset>\r
<size>8</size>\r
<access>read-write</access>\r
<resetValue>0</resetValue>\r
<peripheral>\r
<name>SCSI_CTL_PHASE</name>\r
<description>No description available</description>\r
- <baseAddress>0x40006475</baseAddress>\r
+ <baseAddress>0x40006472</baseAddress>\r
<addressBlock>\r
<offset>0</offset>\r
<size>0x1</size>\r
input [7:0] nDBx_in, // Active LOW, connected directly to SCSI bus.\r
input IO, // Active High, set by CPU via status register.\r
input nRST, // Active LOW, connected directly to SCSI bus.\r
- input clk\r
+ input clk,\r
+ output tx_intr,\r
+ output rx_intr\r
);\r
\r
\r
.clock_out(op_clk)\r
);\r
\r
-/////////////////////////////////////////////////////////////////////////////\r
-// FIFO Status Register\r
-/////////////////////////////////////////////////////////////////////////////\r
-// Status Register: scsiTarget_StatusReg__STATUS_REG\r
-// Bit 0: Tx FIFO not full\r
-// Bit 1: Rx FIFO not empty\r
-// Bit 2: Tx FIFO empty\r
-// Bit 3: Rx FIFO full\r
-//\r
-// TX FIFO Register: scsiTarget_scsiTarget_u0__F0_REG\r
-// RX FIFO Register: scsiTarget_scsiTarget_u0__F1_REG\r
-// Use with CY_GET_REG8 and CY_SET_REG8\r
-wire f0_bus_stat; // Tx FIFO not full\r
-wire f0_blk_stat; // Tx FIFO empty\r
-wire f1_bus_stat; // Rx FIFO not empty\r
-wire f1_blk_stat; // Rx FIFO full\r
-cy_psoc3_status #(.cy_force_order(1), .cy_md_select(8'h00)) StatusReg\r
-(\r
- /* input */ .clock(op_clk),\r
- /* input [04:00] */ .status({4'b0, f1_blk_stat, f0_blk_stat, f1_bus_stat, f0_bus_stat})\r
-);\r
-\r
/////////////////////////////////////////////////////////////////////////////\r
// CONSTANTS\r
/////////////////////////////////////////////////////////////////////////////\r
/////////////////////////////////////////////////////////////////////////////\r
// TX States:\r
// IDLE\r
-// Wait for an entry in the FIFO, and for the SCSI Initiator to be ready\r
+// Wait for the SCSI Initiator to be ready\r
// FIFOLOAD\r
// Load F0 into A0. Feed (old) A0 into the ALU SRCA.\r
// TX\r
// Load deskew clock count into A0 from D0\r
// DESKEW\r
// DBx output signals will be output in this state\r
-// Wait for the SCSI deskew time of 55ms. (DEC A0).\r
+// Wait for the SCSI deskew time of 55ns. (DEC A0).\r
// A1 must be fed into SRCA, so PO is now useless.\r
// READY\r
// REQ and DBx output signals will be output in this state\r
-// Wait for acknowledgement from the SCSI initiator.\r
+// Wait for acknowledgement from the SCSI initiator\r
+// Wait for space in output fifo\r
// RX\r
// Dummy state for flow control.\r
// REQ signal will be output in this state\r
//\r
// RX States:\r
// IDLE\r
-// Wait for a dummy "enabling" entry in the input FIFO, and wait for space\r
-// in output the FIFO, and for the SCSI Initiator to be ready\r
+// Wait for a dummy "enabling" entry in the input FIFO,\r
+// and for the SCSI Initiator to be ready\r
// FIFOLOAD\r
// Load F0 into A0.\r
// The input FIFO is used to control the number of bytes we attempt to\r
// READY\r
// REQ signal will be output in this state\r
// Wait for the initiator to send a byte on the SCSI bus.\r
+// Wait for space in output fifo\r
// RX\r
// REQ signal will be output in this state\r
// PI enabled for input into ALU "PASS" operation, storing into F1.\r
assign pi[7:0] = ~nDBx_in[7:0]; // Invert active low scsi bus\r
assign fifoStore = (state == STATE_RX) ? 1'b1 : 1'b0;\r
\r
+\r
+/////////////////////////////////////////////////////////////////////////////\r
+// FIFO Status Register\r
+/////////////////////////////////////////////////////////////////////////////\r
+// Status Register: scsiTarget_StatusReg__STATUS_REG\r
+// Bit 0: Tx FIFO not full\r
+// Bit 1: Rx FIFO not empty\r
+// Bit 2: Tx FIFO empty\r
+// Bit 3: Rx FIFO full\r
+// Bit 4: TX Complete. Fifos empty and idle.\r
+//\r
+// TX FIFO Register: scsiTarget_scsiTarget_u0__F0_REG\r
+// RX FIFO Register: scsiTarget_scsiTarget_u0__F1_REG\r
+// Use with CY_GET_REG8 and CY_SET_REG8\r
+wire f0_bus_stat; // Tx FIFO not full\r
+wire f0_blk_stat; // Tx FIFO empty\r
+wire f1_bus_stat; // Rx FIFO not empty\r
+wire f1_blk_stat; // Rx FIFO full\r
+wire txComplete = f0_blk_stat && (state == STATE_IDLE);\r
+cy_psoc3_status #(.cy_force_order(1), .cy_md_select(8'h00)) StatusReg\r
+(\r
+ /* input */ .clock(op_clk),\r
+ /* input [04:00] */ .status({3'b0, txComplete, f1_blk_stat, f0_blk_stat, f1_bus_stat, f0_bus_stat})\r
+);\r
+\r
+// DMA outputs\r
+assign tx_intr = f0_bus_stat;\r
+assign rx_intr = f1_bus_stat;\r
+\r
+/////////////////////////////////////////////////////////////////////////////\r
+// State machine\r
+/////////////////////////////////////////////////////////////////////////////\r
always @(posedge op_clk) begin\r
case (state)\r
STATE_IDLE:\r
// and output FIFO is not full.\r
// Note that output FIFO is unused in TX mode.\r
if (!nRST) state <= STATE_IDLE;\r
- else if (nACK & !f0_blk_stat && !f1_blk_stat)\r
+ else if (nACK & !f0_blk_stat)\r
state <= STATE_FIFOLOAD;\r
else\r
state <= STATE_IDLE;\r
\r
STATE_READY:\r
if (!nRST) state <= STATE_IDLE;\r
- else if (~nACK) state <= STATE_RX;\r
+ else if (~nACK && ((IO == IO_WRITE) || !f1_blk_stat)) state <= STATE_RX;\r
else state <= STATE_READY;\r
\r
- STATE_RX: state <= STATE_IDLE;\r
+ STATE_RX: // same code here as for the IDLE state, as we make\r
+ // a quick run back to the next byte if possible.\r
+ if (!nRST) state <= STATE_IDLE;\r
+ else if (nACK & !f0_blk_stat)\r
+ state <= STATE_FIFOLOAD;\r
+ else\r
+ state <= STATE_IDLE;\r
\r
default: state <= STATE_IDLE;\r
endcase\r
end\r
\r
-// D1 is used for the deskew count.\r
+// D0 is used for the deskew count.\r
// The data output is valid during the DESKEW_INIT phase as well,\r
// so we subtract 1.\r
-// D1 = [0.000000055 / (1 / clk)] - 1\r
-cy_psoc3_dp #(.d1_init(1), \r
+// D0 = [0.000000055 / (1 / clk)] - 1\r
+cy_psoc3_dp #(.d0_init(2), \r
.cy_dpconfig(\r
{\r
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,\r
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,\r
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,\r
- `CS_CMP_SEL_CFGA, /*CFGRAM0: IDLE*/\r
+ `CS_CMP_SEL_CFGA, /*CFGRAM0: IDLE*/\r
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,\r
`CS_SHFT_OP_PASS, `CS_A0_SRC___F0, `CS_A1_SRC_NONE,\r
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,\r
- `CS_CMP_SEL_CFGA, /*CFGRAM1: FIFO Load*/\r
+ `CS_CMP_SEL_CFGA, /*CFGRAM1: FIFO Load*/\r
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,\r
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,\r
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,\r
- `CS_CMP_SEL_CFGA, /*CFGRAM2: TX*/\r
+ `CS_CMP_SEL_CFGA, /*CFGRAM2: TX*/\r
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,\r
`CS_SHFT_OP_PASS, `CS_A0_SRC___D0, `CS_A1_SRC_NONE,\r
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,\r
- `CS_CMP_SEL_CFGA, /*CFGRAM3: DESKEW INIT*/\r
+ `CS_CMP_SEL_CFGA, /*CFGRAM3: DESKEW INIT*/\r
`CS_ALU_OP__DEC, `CS_SRCA_A0, `CS_SRCB_D0,\r
`CS_SHFT_OP_PASS, `CS_A0_SRC__ALU, `CS_A1_SRC_NONE,\r
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,\r
- `CS_CMP_SEL_CFGA, /*CFGRAM4: DESKEW*/\r
+ `CS_CMP_SEL_CFGA, /*CFGRAM4: DESKEW*/\r
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,\r
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,\r
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,\r
- `CS_CMP_SEL_CFGA, /*CFGRAM5: Not used*/\r
+ `CS_CMP_SEL_CFGA, /*CFGRAM5: Not used*/\r
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,\r
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,\r
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,\r
- `CS_CMP_SEL_CFGA, /*CFGRAM6: READY*/\r
+ `CS_CMP_SEL_CFGA, /*CFGRAM6: READY*/\r
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,\r
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,\r
`CS_FEEDBACK_ENBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,\r
- `CS_CMP_SEL_CFGA, /*CFGRAM7: RX*/\r
- 8'hFF, 8'h00, /*CFG9: */\r
- 8'hFF, 8'hFF, /*CFG11-10: */\r
+ `CS_CMP_SEL_CFGA, /*CFGRAM7: RX*/\r
+ 8'hFF, 8'h00, /*CFG9: */\r
+ 8'hFF, 8'hFF, /*CFG11-10: */\r
`SC_CMPB_A1_D1, `SC_CMPA_A1_D1, `SC_CI_B_ARITH,\r
`SC_CI_A_ARITH, `SC_C1_MASK_DSBL, `SC_C0_MASK_DSBL,\r
`SC_A_MASK_DSBL, `SC_DEF_SI_0, `SC_SI_B_DEFSI,\r
- `SC_SI_A_DEFSI, /*CFG13-12: */\r
+ `SC_SI_A_DEFSI, /*CFG13-12: */\r
`SC_A0_SRC_ACC, `SC_SHIFT_SL, `SC_PI_DYN_EN,\r
1'h0, `SC_FIFO1_ALU, `SC_FIFO0_BUS,\r
`SC_MSB_DSBL, `SC_MSB_BIT0, `SC_MSB_NOCHN,\r
`SC_FB_NOCHN, `SC_CMP1_NOCHN,\r
- `SC_CMP0_NOCHN, /*CFG15-14: */\r
+ `SC_CMP0_NOCHN, /*CFG15-14: */\r
10'h00, `SC_FIFO_CLK__DP,`SC_FIFO_CAP_AX,\r
`SC_FIFO_LEVEL,`SC_FIFO__SYNC,`SC_EXTCRC_DSBL,\r
- `SC_WRK16CAT_DSBL /*CFG17-16: */\r
+ `SC_WRK16CAT_DSBL /*CFG17-16: */\r
}\r
)) datapath(\r
/* input */ .reset(1'b0),\r
endmodule\r
//`#start footer` -- edit after this line, do not edit this line\r
//`#end` -- edit above this line, do not edit this line\r
+\r
<Tool Name="postbuild" Command="" Options="" />\r
</Toolchain>\r
</Toolchains>\r
- <Project Name="USB_Bootloader" Path="W:\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn" Version="4.0" Type="Bootloader">\r
+ <Project Name="USB_Bootloader" Path="Z:\projects\SCSI2SD\git-3.4_debug\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn" Version="4.0" Type="Bootloader">\r
<CMSIS_SVD_File>USB_Bootloader.svd</CMSIS_SVD_File>\r
<Datasheet />\r
<LinkerFiles>\r
<LinkerFile Toolchain="IAR EWARM">.\Generated_Source\PSoC5\Cm3Iar.icf</LinkerFile>\r
</LinkerFiles>\r
<Folders>\r
- <Folder BuildType="BUILD" Path="W:\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn">\r
- <Files Root="W:\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn">\r
+ <Folder BuildType="BUILD" Path="Z:\projects\SCSI2SD\git-3.4_debug\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn">\r
+ <Files Root="Z:\projects\SCSI2SD\git-3.4_debug\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn">\r
<File BuildType="BUILD" Toolchain="">.\main.c</File>\r
</Files>\r
</Folder>\r
- <Folder BuildType="STRICT" Path="W:\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn\Generated_Source\PSoC5">\r
- <Files Root="W:\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn">\r
+ <Folder BuildType="STRICT" Path="Z:\projects\SCSI2SD\git-3.4_debug\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn\Generated_Source\PSoC5">\r
+ <Files Root="Z:\projects\SCSI2SD\git-3.4_debug\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn">\r
<File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\cyfitter_cfg.h</File>\r
<File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\cyfitter_cfg.c</File>\r
<File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\cymetadata.c</File>\r
<File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\libelf.dll</File>\r
</Files>\r
</Folder>\r
- <Folder BuildType="STRICT" Path="W:\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn\Generated_Source\PSoC5\ARM_GCC">\r
- <Files Root="W:\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn">\r
+ <Folder BuildType="STRICT" Path="Z:\projects\SCSI2SD\git-3.4_debug\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn\Generated_Source\PSoC5\ARM_GCC">\r
+ <Files Root="Z:\projects\SCSI2SD\git-3.4_debug\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn">\r
<File BuildType="BUILD" Toolchain="ARM GCC">.\Generated_Source\PSoC5\ARM_GCC\CyComponentLibrary.a</File>\r
</Files>\r
</Folder>\r
- <Folder BuildType="STRICT" Path="W:\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn\Generated_Source\PSoC5\ARM_Keil_MDK">\r
- <Files Root="W:\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn">\r
+ <Folder BuildType="STRICT" Path="Z:\projects\SCSI2SD\git-3.4_debug\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn\Generated_Source\PSoC5\ARM_Keil_MDK">\r
+ <Files Root="Z:\projects\SCSI2SD\git-3.4_debug\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn">\r
<File BuildType="BUILD" Toolchain="ARM Keil MDK">.\Generated_Source\PSoC5\ARM_Keil_MDK\CyComponentLibrary.a</File>\r
</Files>\r
</Folder>\r
- <Folder BuildType="STRICT" Path="W:\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn\Generated_Source\PSoC5\IAR">\r
- <Files Root="W:\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn">\r
+ <Folder BuildType="STRICT" Path="Z:\projects\SCSI2SD\git-3.4_debug\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn\Generated_Source\PSoC5\IAR">\r
+ <Files Root="Z:\projects\SCSI2SD\git-3.4_debug\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn">\r
<File BuildType="BUILD" Toolchain="IAR">.\Generated_Source\PSoC5\IAR\CyComponentLibrary.a</File>\r
</Files>\r
</Folder>\r
<Folder BuildType="EXCLUDE" Path=".\codegentemp">\r
- <Files Root="W:\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn" />\r
+ <Files Root="Z:\projects\SCSI2SD\git-3.4_debug\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn" />\r
</Folder>\r
<Folder BuildType="EXCLUDE" Path=".\ARM_GCC_441">\r
- <Files Root="W:\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn" />\r
+ <Files Root="Z:\projects\SCSI2SD\git-3.4_debug\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn" />\r
</Folder>\r
<Folder BuildType="EXCLUDE" Path=".\ARM_GCC_473">\r
- <Files Root="W:\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn" />\r
+ <Files Root="Z:\projects\SCSI2SD\git-3.4_debug\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn" />\r
</Folder>\r
<Folder BuildType="EXCLUDE" Path=".\DP8051_Keil_951">\r
- <Files Root="W:\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn" />\r
+ <Files Root="Z:\projects\SCSI2SD\git-3.4_debug\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn" />\r
</Folder>\r
<Folder BuildType="EXCLUDE" Path=".\DP8051">\r
- <Files Root="W:\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn" />\r
+ <Files Root="Z:\projects\SCSI2SD\git-3.4_debug\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn" />\r
</Folder>\r
<Folder BuildType="EXCLUDE" Path=".\CortexM0">\r
- <Files Root="W:\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn" />\r
+ <Files Root="Z:\projects\SCSI2SD\git-3.4_debug\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn" />\r
</Folder>\r
<Folder BuildType="EXCLUDE" Path=".\CortexM3">\r
- <Files Root="W:\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn" />\r
+ <Files Root="Z:\projects\SCSI2SD\git-3.4_debug\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn" />\r
</Folder>\r
</Folders>\r
</Project>\r
<name_val_pair name="W:\SCSI2SD\USB_Bootloader.cydsn\CortexM3\ARM_GCC_473\Release\USB_Bootloader.hex" v=""-mthumb ""-march=armv7-m ""-mfix-cortex-m3-ldrd ""-T "".\Generated_Source\PSoC5\cm3gcc.ld ""-g ""-Wl,-Map,${OutputDir}\${ProjectShortName}.map ""-specs=nano.specs ""-Wl,--gc-sections "" />\r
<name_val_pair name=".\Generated_Source\PSoC5\SD_PULLUP.c" v=""-I. ""-I./Generated_Source/PSoC5 ""-Wno-main ""-mcpu=cortex-m3 ""-mthumb ""-Wall ""-g ""-D ""NDEBUG ""-Wa,-alh=${OutputDir}\${CompileFile}.lst ""-Os ""-ffunction-sections "" />\r
<name_val_pair name="W:\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn\CortexM3\ARM_GCC_473\Release\USB_Bootloader.hex" v=""-mthumb ""-march=armv7-m ""-mfix-cortex-m3-ldrd ""-T "".\Generated_Source\PSoC5\cm3gcc.ld ""-g ""-Wl,-Map,${OutputDir}\${ProjectShortName}.map ""-specs=nano.specs ""-Wl,--gc-sections "" />\r
+<name_val_pair name="Z:\projects\SCSI2SD\git-3.4_debug\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn\CortexM3\ARM_GCC_473\Release\USB_Bootloader.hex" v=""-mthumb ""-march=armv7-m ""-mfix-cortex-m3-ldrd ""-T "".\Generated_Source\PSoC5\cm3gcc.ld ""-g ""-Wl,-Map,${OutputDir}\${ProjectShortName}.map ""-specs=nano.specs ""-Wl,--gc-sections "" />\r
</name>\r
<name v="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3">\r
<name_val_pair name=".\main.c" v=""-I. ""-I./Generated_Source/PSoC5 ""-Wno-main ""-mcpu=cortex-m3 ""-mthumb ""-Wall ""-g ""-D ""DEBUG ""-Wa,-alh=${OutputDir}\${CompileFile}.lst ""-ffunction-sections "" />\r
<name_val_pair name="W:\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn\CortexM3\ARM_GCC_473\Debug\USB_Bootloader.hex" v=""-mthumb ""-march=armv7-m ""-mfix-cortex-m3-ldrd ""-T "".\Generated_Source\PSoC5\cm3gcc.ld ""-g ""-Wl,-Map,${OutputDir}\${ProjectShortName}.map ""-specs=nano.specs ""-Wl,--gc-sections "" />\r
</name>\r
</genericCmdLineData>\r
-<codeGenCmdLineTag v=""-.appdatapath" "C:\Users\Micha_000\AppData\Local\Cypress Semiconductor\PSoC Creator\3.0" "-.fdsnotice" "-.fdswarpdepfile=warp_dependencies.txt" "-.fdselabdepfile=elab_dependencies.txt" "-.fdsbldfile=generated_files.txt" "-p" "W:\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn\USB_Bootloader.cyprj" "-d" "CY8C5267AXI-LP051" "-s" "W:\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn\Generated_Source\PSoC5" "--" "-yv2" "-v3" "-ygs" "-q10" "-o2" "-.fftcfgtype=LE" " />\r
+<codeGenCmdLineTag v=""-.appdatapath" "C:\Users\Micha_000\AppData\Local\Cypress Semiconductor\PSoC Creator\3.0" "-.fdsnotice" "-.fdswarpdepfile=warp_dependencies.txt" "-.fdselabdepfile=elab_dependencies.txt" "-.fdsbldfile=generated_files.txt" "-p" "Z:\projects\SCSI2SD\git-3.4_debug\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn\USB_Bootloader.cyprj" "-d" "CY8C5267AXI-LP051" "-s" "Z:\projects\SCSI2SD\git-3.4_debug\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn\Generated_Source\PSoC5" "--" "-yv2" "-v3" "-ygs" "-q10" "-o2" "-.fftcfgtype=LE" " />\r
</CyGuid_b0374e30-ce3a-47f2-ad85-821643292c68>\r
</dataGuid>\r
<dataGuid v="597c5b74-0c46-4204-8b7f-96f3570671dc">\r
<v>C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\stdlogic\mod_genv.vif</v>\r
<v>C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\stdlogic\rtlpkg.vif</v>\r
</warp_dep>\r
-<deps_time v="130421205782926169" />\r
+<deps_time v="130450587785176249" />\r
<top_block v="TopDesign" />\r
<last_generation v="0" />\r
</CyGuid_925cc1e1-309e-4e08-b0a1-09a83c35b157>\r
</dataGuid>\r
<dataGuid v="769d31ea-68b1-4f0c-b90a-7c10a43ee563">\r
<CyGuid_769d31ea-68b1-4f0c-b90a-7c10a43ee563 type_name="CyDesigner.Common.ProjMgmt.Model.CyLinkCustomData" version="1">\r
-<deps_time v="130421206235126109" />\r
+<deps_time v="130450588791286055" />\r
</CyGuid_769d31ea-68b1-4f0c-b90a-7c10a43ee563>\r
</dataGuid>\r
<dataGuid v="bf610382-39c6-441f-80b8-b04622ea7845">\r
-Loading plugins phase: Elapsed time ==> 0s.481ms\r
-Initializing data phase: Elapsed time ==> 3s.796ms\r
+Loading plugins phase: Elapsed time ==> 1s.508ms\r
+Initializing data phase: Elapsed time ==> 9s.403ms\r
<CYPRESSTAG name="CyDsfit arguments...">\r
-cydsfit arguments: -.fdsnotice -.fdswarpdepfile=warp_dependencies.txt -.fdselabdepfile=elab_dependencies.txt -.fdsbldfile=generated_files.txt -p W:\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn\USB_Bootloader.cyprj -d CY8C5267AXI-LP051 -s W:\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn\Generated_Source\PSoC5 -- -yv2 -v3 -ygs -q10 -o2 -.fftcfgtype=LE</CYPRESSTAG>\r
+cydsfit arguments: -.fdsnotice -.fdswarpdepfile=warp_dependencies.txt -.fdselabdepfile=elab_dependencies.txt -.fdsbldfile=generated_files.txt -p Z:\projects\SCSI2SD\git-3.4_debug\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn\USB_Bootloader.cyprj -d CY8C5267AXI-LP051 -s Z:\projects\SCSI2SD\git-3.4_debug\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn\Generated_Source\PSoC5 -- -yv2 -v3 -ygs -q10 -o2 -.fftcfgtype=LE</CYPRESSTAG>\r
<CYPRESSTAG name="Design elaboration results...">\r
</CYPRESSTAG>\r
-Elaboration phase: Elapsed time ==> 7s.874ms\r
+Elaboration phase: Elapsed time ==> 9s.079ms\r
<CYPRESSTAG name="HDL generation results...">\r
</CYPRESSTAG>\r
-HDL generation phase: Elapsed time ==> 0s.173ms\r
+HDL generation phase: Elapsed time ==> 0s.906ms\r
<CYPRESSTAG name="Synthesis results...">\r
\r
| | | | | | |\r
======================================================================\r
Compiling: USB_Bootloader.v\r
Program : C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\bin/warp.exe\r
-Options : -yv2 -v3 -ygs -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=W:\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn\USB_Bootloader.cyprj -dcpsoc3 USB_Bootloader.v -verilog\r
+Options : -yv2 -v3 -ygs -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=Z:\projects\SCSI2SD\git-3.4_debug\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn\USB_Bootloader.cyprj -dcpsoc3 USB_Bootloader.v -verilog\r
======================================================================\r
\r
======================================================================\r
Compiling: USB_Bootloader.v\r
Program : C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\bin/warp.exe\r
-Options : -yv2 -v3 -ygs -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=W:\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn\USB_Bootloader.cyprj -dcpsoc3 USB_Bootloader.v -verilog\r
+Options : -yv2 -v3 -ygs -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=Z:\projects\SCSI2SD\git-3.4_debug\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn\USB_Bootloader.cyprj -dcpsoc3 USB_Bootloader.v -verilog\r
======================================================================\r
\r
======================================================================\r
Compiling: USB_Bootloader.v\r
Program : vlogfe\r
-Options : -yv2 -v3 -ygs -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=W:\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn\USB_Bootloader.cyprj -dcpsoc3 -verilog USB_Bootloader.v\r
+Options : -yv2 -v3 -ygs -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=Z:\projects\SCSI2SD\git-3.4_debug\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn\USB_Bootloader.cyprj -dcpsoc3 -verilog USB_Bootloader.v\r
======================================================================\r
\r
vlogfe V6.3 IR 41: Verilog parser\r
-Wed Apr 16 21:15:58 2014\r
+Tue May 20 21:24:38 2014\r
\r
\r
======================================================================\r
======================================================================\r
\r
vpp V6.3 IR 41: Verilog Pre-Processor\r
-Wed Apr 16 21:15:59 2014\r
+Tue May 20 21:24:39 2014\r
\r
\r
vpp: No errors.\r
======================================================================\r
Compiling: USB_Bootloader.v\r
Program : tovif\r
-Options : -yv2 -v3 -ygs -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=W:\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn\USB_Bootloader.cyprj -dcpsoc3 -verilog USB_Bootloader.v\r
+Options : -yv2 -v3 -ygs -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=Z:\projects\SCSI2SD\git-3.4_debug\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn\USB_Bootloader.cyprj -dcpsoc3 -verilog USB_Bootloader.v\r
======================================================================\r
\r
tovif V6.3 IR 41: High-level synthesis\r
-Wed Apr 16 21:15:59 2014\r
+Tue May 20 21:24:41 2014\r
\r
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\std.vhd'.\r
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\cypress.vhd'.\r
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\stdlogic\mod_cnst.vif'.\r
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\stdlogic\mod_mthv.vif'.\r
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\stdlogic\mod_genv.vif'.\r
-Linking 'W:\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn\codegentemp\USB_Bootloader.ctl'.\r
-Linking 'W:\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn\codegentemp\USB_Bootloader.v'.\r
+Linking 'Z:\projects\SCSI2SD\git-3.4_debug\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn\codegentemp\USB_Bootloader.ctl'.\r
+Linking 'Z:\projects\SCSI2SD\git-3.4_debug\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn\codegentemp\USB_Bootloader.v'.\r
\r
tovif: No errors.\r
\r
======================================================================\r
Compiling: USB_Bootloader.v\r
Program : topld\r
-Options : -yv2 -v3 -ygs -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=W:\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn\USB_Bootloader.cyprj -dcpsoc3 -verilog USB_Bootloader.v\r
+Options : -yv2 -v3 -ygs -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=Z:\projects\SCSI2SD\git-3.4_debug\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn\USB_Bootloader.cyprj -dcpsoc3 -verilog USB_Bootloader.v\r
======================================================================\r
\r
topld V6.3 IR 41: Synthesis and optimization\r
-Wed Apr 16 21:16:00 2014\r
+Tue May 20 21:24:44 2014\r
\r
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\std.vhd'.\r
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\cypress.vhd'.\r
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\stdlogic\mod_cnst.vif'.\r
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\stdlogic\mod_mthv.vif'.\r
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\stdlogic\mod_genv.vif'.\r
-Linking 'W:\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn\codegentemp\USB_Bootloader.ctl'.\r
-Linking 'W:\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn\codegentemp\USB_Bootloader.v'.\r
+Linking 'Z:\projects\SCSI2SD\git-3.4_debug\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn\codegentemp\USB_Bootloader.ctl'.\r
+Linking 'Z:\projects\SCSI2SD\git-3.4_debug\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn\codegentemp\USB_Bootloader.v'.\r
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\lcpsoc3\stdlogic\cpsoc3.vif'.\r
\r
----------------------------------------------------------\r
\r
CYPRESS_DIR : C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\r
Warp Program : C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\bin/warp.exe\r
-Warp Arguments : -yv2 -v3 -ygs -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=W:\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn\USB_Bootloader.cyprj -dcpsoc3 USB_Bootloader.v -verilog\r
+Warp Arguments : -yv2 -v3 -ygs -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=Z:\projects\SCSI2SD\git-3.4_debug\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn\USB_Bootloader.cyprj -dcpsoc3 USB_Bootloader.v -verilog\r
</CYPRESSTAG>\r
-Warp synthesis phase: Elapsed time ==> 2s.967ms\r
+Warp synthesis phase: Elapsed time ==> 9s.267ms\r
<CYPRESSTAG name="Fitter results...">\r
<CYPRESSTAG name="Fitter startup details...">\r
-cyp3fit: V3.0.0.1539, Family: PSoC3, Started at: Wednesday, 16 April 2014 21:16:01\r
-Options: -yv2 -v3 -ygs -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=W:\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn\USB_Bootloader.cyprj -d CY8C5267AXI-LP051 USB_Bootloader.v -verilog\r
+cyp3fit: V3.0.0.1539, Family: PSoC3, Started at: Tuesday, 20 May 2014 21:24:47\r
+Options: -yv2 -v3 -ygs -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=Z:\projects\SCSI2SD\git-3.4_debug\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn\USB_Bootloader.cyprj -d CY8C5267AXI-LP051 USB_Bootloader.v -verilog\r
</CYPRESSTAG>\r
<CYPRESSTAG name="Design parsing">\r
Design parsing phase: Elapsed time ==> 0s.046ms\r
LPF Fixed Blocks : 0 : 2 : 2 : 0.00%\r
SAR Fixed Blocks : 0 : 1 : 1 : 0.00%\r
</CYPRESSTAG>\r
-Technology Mapping: Elapsed time ==> 0s.015ms\r
-Tech mapping phase: Elapsed time ==> 0s.281ms\r
+Technology Mapping: Elapsed time ==> 0s.437ms\r
+Tech mapping phase: Elapsed time ==> 0s.672ms\r
</CYPRESSTAG>\r
<CYPRESSTAG name="Analog Placement">\r
Initial Analog Placement Results:\r
IO_7@[IOP=(15)][IoId=(7)] : \USBFS:Dm(0)\ (fixed)\r
IO_6@[IOP=(15)][IoId=(6)] : \USBFS:Dp(0)\ (fixed)\r
USB[0]@[FFB(USB,0)] : \USBFS:USB\\r
-Analog Placement phase: Elapsed time ==> 0s.109ms\r
+Analog Placement phase: Elapsed time ==> 0s.078ms\r
</CYPRESSTAG>\r
<CYPRESSTAG name="Analog Routing">\r
Analog Routing phase: Elapsed time ==> 0s.000ms\r
IsVddaHalfUsedForComp = False\r
IsVddaHalfUsedForSar0 = False\r
IsVddaHalfUsedForSar1 = False\r
-Analog Code Generation phase: Elapsed time ==> 1s.031ms\r
+Analog Code Generation phase: Elapsed time ==> 1s.828ms\r
</CYPRESSTAG>\r
<CYPRESSTAG name="Digital Placement">\r
<CYPRESSTAG name="Detailed placement messages">\r
I2659: No Constrained paths were found. The placer will run in non-timing driven mode.\r
-I2076: Total run-time: 1.6 sec.\r
+I2076: Total run-time: 3.9 sec.\r
\r
</CYPRESSTAG>\r
<CYPRESSTAG name="PLD Packing">\r
</CYPRESSTAG>\r
</CYPRESSTAG>\r
</CYPRESSTAG>\r
-Digital component placer commit/Report: Elapsed time ==> 0s.017ms\r
-Digital Placement phase: Elapsed time ==> 2s.641ms\r
+Digital component placer commit/Report: Elapsed time ==> 0s.375ms\r
+Digital Placement phase: Elapsed time ==> 8s.689ms\r
</CYPRESSTAG>\r
<CYPRESSTAG name="Digital Routing">\r
Routing successful.\r
-Digital Routing phase: Elapsed time ==> 3s.404ms\r
+Digital Routing phase: Elapsed time ==> 6s.563ms\r
</CYPRESSTAG>\r
<CYPRESSTAG name="Bitstream and API generation">\r
-Bitstream and API generation phase: Elapsed time ==> 0s.796ms\r
+Bitstream and API generation phase: Elapsed time ==> 26s.707ms\r
</CYPRESSTAG>\r
<CYPRESSTAG name="Bitstream verification">\r
-Bitstream verification phase: Elapsed time ==> 0s.171ms\r
+Bitstream verification phase: Elapsed time ==> 0s.140ms\r
</CYPRESSTAG>\r
<CYPRESSTAG name="Static timing analysis">\r
Timing report is in USB_Bootloader_timing.html.\r
-Static timing analysis phase: Elapsed time ==> 0s.812ms\r
+Static timing analysis phase: Elapsed time ==> 7s.016ms\r
</CYPRESSTAG>\r
<CYPRESSTAG name="Data reporting">\r
Data reporting phase: Elapsed time ==> 0s.000ms\r
</CYPRESSTAG>\r
<CYPRESSTAG name="Database update...">\r
-Design database save phase: Elapsed time ==> 0s.406ms\r
+Design database save phase: Elapsed time ==> 0s.577ms\r
</CYPRESSTAG>\r
-cydsfit: Elapsed time ==> 9s.781ms\r
+cydsfit: Elapsed time ==> 52s.696ms\r
</CYPRESSTAG>\r
-Fitter phase: Elapsed time ==> 9s.859ms\r
-API generation phase: Elapsed time ==> 4s.706ms\r
-Dependency generation phase: Elapsed time ==> 0s.028ms\r
-Cleanup phase: Elapsed time ==> 0s.063ms\r
+Fitter phase: Elapsed time ==> 52s.775ms\r
+API generation phase: Elapsed time ==> 25s.205ms\r
+Dependency generation phase: Elapsed time ==> 0s.796ms\r
+Cleanup phase: Elapsed time ==> 0s.750ms\r
<tr> <td class="prop"> Project :</td>\r
<td class="proptext"> USB_Bootloader</td></tr>\r
<tr> <td class="prop"> Build Time :</td>\r
-<td class="proptext"> 04/16/14 21:16:10</td></tr>\r
+<td class="proptext"> 05/20/14 21:25:38</td></tr>\r
<tr> <td class="prop"> Device :</td>\r
<td class="proptext"> CY8C5267AXI-LP051</td></tr>\r
<tr> <td class="prop"> Temperature :</td>\r
}\r
}\r
\r
+void scsiReadBuffer()\r
+{\r
+ // READ BUFFER\r
+ // Used for testing the speed of the SCSI interface.\r
+ uint8 mode = scsiDev.data[1] & 7;\r
+ \r
+ int allocLength =\r
+ (((uint32) scsiDev.cdb[6]) << 16) +\r
+ (((uint32) scsiDev.cdb[7]) << 8) +\r
+ scsiDev.cdb[8];\r
+\r
+ if (mode == 0)\r
+ {\r
+ uint32_t maxSize = MAX_SECTOR_SIZE - 4;\r
+ // 4 byte header\r
+ scsiDev.data[0] = 0;\r
+ scsiDev.data[1] = (maxSize >> 16) & 0xff;\r
+ scsiDev.data[2] = (maxSize >> 8) & 0xff;\r
+ scsiDev.data[3] = maxSize & 0xff;\r
+ \r
+ scsiDev.dataLen =\r
+ (allocLength > MAX_SECTOR_SIZE) ? MAX_SECTOR_SIZE : allocLength;\r
+ scsiDev.phase = DATA_IN;\r
+ }\r
+}\r
void scsiSendDiagnostic(void);
void scsiReceiveDiagnostic(void);
+void scsiReadBuffer(void);
#endif
int defectLength =\r
((((uint16_t)scsiDev.data[2])) << 8) +\r
scsiDev.data[3];\r
- \r
+\r
int patternLength =\r
((((uint16_t)scsiDev.data[4 + 2])) << 8) +\r
scsiDev.data[4 + 3];\r
transfer.multiBlock = 1;\r
\r
if (blocks > 1) scsiDev.needReconnect = 1;\r
- sdPrepareWrite();\r
+ sdWriteMultiSectorPrep();\r
}\r
}\r
\r
{\r
transfer.multiBlock = 1;\r
scsiDev.needReconnect = 1;\r
- sdPrepareRead();\r
+ sdReadMultiSectorPrep();\r
}\r
}\r
}\r
if (scsiDev.phase == DATA_IN &&\r
transfer.currentBlock != transfer.blocks)\r
{\r
- if (scsiDev.dataLen == 0)\r
+ int totalSDSectors = transfer.blocks * SDSectorsPerSCSISector();\r
+ uint32_t sdLBA = SCSISector2SD(transfer.lba);\r
+ int buffers = sizeof(scsiDev.data) / SD_SECTOR_SIZE;\r
+ int prep = 0;\r
+ int i = 0;\r
+ int scsiActive = 0;\r
+ int sdActive = 0;\r
+ while ((i < totalSDSectors) &&\r
+ (scsiDev.phase == DATA_IN) &&\r
+ !scsiDev.resetFlag)\r
{\r
- if (transfer.multiBlock)\r
+ if ((sdActive == 1) && sdReadSectorDMAPoll())\r
{\r
- sdReadSectorMulti();\r
+ sdActive = 0;\r
+ prep++;\r
}\r
- else\r
+ else if ((sdActive == 0) && (prep - i < buffers) && (prep < totalSDSectors))\r
{\r
- sdReadSectorSingle();\r
+ // Start an SD transfer if we have space.\r
+ if (transfer.multiBlock)\r
+ {\r
+ sdReadMultiSectorDMA(&scsiDev.data[SD_SECTOR_SIZE * (prep % buffers)]);\r
+ }\r
+ else\r
+ {\r
+ sdReadSingleSectorDMA(sdLBA + prep, &scsiDev.data[SD_SECTOR_SIZE * (prep % buffers)]);\r
+ }\r
+ sdActive = 1;\r
}\r
- }\r
- else if (scsiDev.dataPtr == scsiDev.dataLen)\r
- {\r
- scsiDev.dataLen = 0;\r
- scsiDev.dataPtr = 0;\r
- transfer.currentBlock++;\r
- if (transfer.currentBlock >= transfer.blocks)\r
+\r
+ if ((scsiActive == 1) && scsiWriteDMAPoll())\r
{\r
- scsiDev.phase = STATUS;\r
- scsiDiskReset();\r
+ scsiActive = 0;\r
+ ++i;\r
+ }\r
+ else if ((scsiActive == 0) && ((prep - i) > 0))\r
+ {\r
+ int dmaBytes = SD_SECTOR_SIZE;\r
+ if (i % SDSectorsPerSCSISector() == SDSectorsPerSCSISector() - 1)\r
+ {\r
+ dmaBytes = config->bytesPerSector % SD_SECTOR_SIZE;\r
+ if (dmaBytes == 0) dmaBytes = SD_SECTOR_SIZE;\r
+ }\r
+ scsiWriteDMA(&scsiDev.data[SD_SECTOR_SIZE * (i % buffers)], dmaBytes);\r
+ scsiActive = 1;\r
}\r
}\r
+ if (scsiDev.phase == DATA_IN)\r
+ {\r
+ scsiDev.phase = STATUS;\r
+ }\r
+ scsiDiskReset();\r
}\r
else if (scsiDev.phase == DATA_OUT &&\r
transfer.currentBlock != transfer.blocks)\r
{\r
- sdWriteSector();\r
- // TODO FIX scsiDiskPoll() scsiDev.dataPtr = 0;\r
- transfer.currentBlock++;\r
- if (transfer.currentBlock >= transfer.blocks)\r
+ int totalSDSectors = transfer.blocks * SDSectorsPerSCSISector();\r
+ int buffers = sizeof(scsiDev.data) / SD_SECTOR_SIZE;\r
+ int prep = 0;\r
+ int i = 0;\r
+ int scsiActive = 0;\r
+ int sdActive = 0;\r
+ while ((i < totalSDSectors) &&\r
+ (scsiDev.phase == DATA_OUT) &&\r
+ !scsiDev.resetFlag)\r
{\r
- scsiDev.dataLen = 0;\r
- scsiDev.dataPtr = 0;\r
- scsiDev.phase = STATUS;\r
+ if ((sdActive == 1) && sdWriteSectorDMAPoll())\r
+ {\r
+ sdActive = 0;\r
+ i++;\r
+ }\r
+ else if ((sdActive == 0) && ((prep - i) > 0))\r
+ {\r
+ // Start an SD transfer if we have space.\r
+ sdWriteMultiSectorDMA(&scsiDev.data[SD_SECTOR_SIZE * (i % buffers)]);\r
+ sdActive = 1;\r
+ }\r
\r
- scsiDiskReset();\r
+ if ((scsiActive == 1) && scsiReadDMAPoll())\r
+ {\r
+ scsiActive = 0;\r
+ ++prep;\r
+ }\r
+ else if ((scsiActive == 0) && ((prep - i) < buffers) && (prep < totalSDSectors))\r
+ {\r
+ int dmaBytes = SD_SECTOR_SIZE;\r
+ if (prep % SDSectorsPerSCSISector() == SDSectorsPerSCSISector() - 1)\r
+ {\r
+ dmaBytes = config->bytesPerSector % SD_SECTOR_SIZE;\r
+ if (dmaBytes == 0) dmaBytes = SD_SECTOR_SIZE;\r
+ }\r
+ scsiReadDMA(&scsiDev.data[SD_SECTOR_SIZE * (prep % buffers)], dmaBytes);\r
+ scsiActive = 1;\r
+ }\r
+ }\r
+ if (scsiDev.phase == DATA_OUT)\r
+ {\r
+ scsiDev.phase = STATUS;\r
}\r
+ scsiDiskReset();\r
}\r
}\r
\r
{\r
scsiSendDiagnostic();\r
}\r
+ else if (command == 0x3C)\r
+ {\r
+ scsiReadBuffer();\r
+ }\r
else if (\r
!scsiModeCommand() &&\r
!scsiDiskCommand())\r
\r
#define scsiTarget_AUX_CTL (* (reg8 *) scsiTarget_datapath__DP_AUX_CTL_REG)\r
\r
+// DMA controller can't handle any more bytes.\r
+#define MAX_DMA_BYTES 4095\r
+\r
+// Private DMA variables.\r
+static int dmaInProgress = 0;\r
+// used when transferring > MAX_DMA_BYTES.\r
+static uint8_t* dmaBuffer = NULL;\r
+static uint32_t dmaSentCount = 0;\r
+static uint32_t dmaTotalCount = 0;\r
+\r
+static uint8 scsiDmaRxChan = CY_DMA_INVALID_CHANNEL;\r
+static uint8 scsiDmaTxChan = CY_DMA_INVALID_CHANNEL;\r
+\r
+// DMA descriptors\r
+static uint8 scsiDmaRxTd[1] = { CY_DMA_INVALID_TD };\r
+static uint8 scsiDmaTxTd[1] = { CY_DMA_INVALID_TD };\r
+\r
+// Source of dummy bytes for DMA reads\r
+static uint8 dummyBuffer = 0xFF;\r
+\r
+volatile static uint8 rxDMAComplete;\r
+volatile static uint8 txDMAComplete;\r
+\r
+CY_ISR_PROTO(scsiRxCompleteISR);\r
+CY_ISR(scsiRxCompleteISR)\r
+{\r
+ rxDMAComplete = 1;\r
+}\r
+\r
+CY_ISR_PROTO(scsiTxCompleteISR);\r
+CY_ISR(scsiTxCompleteISR)\r
+{\r
+ txDMAComplete = 1;\r
+}\r
+\r
CY_ISR_PROTO(scsiResetISR);\r
CY_ISR(scsiResetISR)\r
{\r
SCSI_RST_ClearInterrupt();\r
}\r
\r
-uint8 scsiReadDBxPins()\r
+uint8_t\r
+scsiReadDBxPins()\r
{\r
return\r
(SCSI_ReadPin(SCSI_In_DBx_DB7) << 7) |\r
(SCSI_ReadPin(SCSI_In_DBx_DB3) << 3) |\r
(SCSI_ReadPin(SCSI_In_DBx_DB2) << 2) |\r
(SCSI_ReadPin(SCSI_In_DBx_DB1) << 1) |\r
- SCSI_ReadPin(SCSI_In_DBx_DB0); \r
+ SCSI_ReadPin(SCSI_In_DBx_DB0);\r
}\r
\r
-uint8 scsiReadByte(void)\r
+uint8_t\r
+scsiReadByte(void)\r
{\r
- while (!(CY_GET_REG8(scsiTarget_StatusReg__STATUS_REG) & 1) &&\r
- !scsiDev.resetFlag) {}\r
- CY_SET_REG8(scsiTarget_datapath__F0_REG, 0);\r
- while (!(CY_GET_REG8(scsiTarget_StatusReg__STATUS_REG) & 2) &&\r
- !scsiDev.resetFlag) {}\r
- \r
+ while (scsiPhyTxFifoFull() && !scsiDev.resetFlag) {}\r
+ scsiPhyTx(0);\r
+\r
+ while (scsiPhyRxFifoEmpty() && !scsiDev.resetFlag) {}\r
+ uint8_t val = scsiPhyRx();\r
+\r
while (SCSI_ReadPin(SCSI_In_ACK) && !scsiDev.resetFlag) {}\r
- \r
- return CY_GET_REG8(scsiTarget_datapath__F1_REG);\r
+\r
+ return val;\r
}\r
\r
-void scsiRead(uint8* data, uint32 count)\r
+static void\r
+scsiReadPIO(uint8* data, uint32 count)\r
{\r
int prep = 0;\r
int i = 0;\r
\r
while (i < count && !scsiDev.resetFlag)\r
{\r
- if (prep < count && (CY_GET_REG8(scsiTarget_StatusReg__STATUS_REG) & 1))\r
+ uint8_t status = scsiPhyStatus();\r
+\r
+ if (prep < count && (status & SCSI_PHY_TX_FIFO_NOT_FULL))\r
{\r
- CY_SET_REG8(scsiTarget_datapath__F0_REG, 0);\r
+ scsiPhyTx(0);\r
++prep;\r
}\r
- if ((CY_GET_REG8(scsiTarget_StatusReg__STATUS_REG) & 2))\r
+ if (status & SCSI_PHY_RX_FIFO_NOT_EMPTY)\r
{\r
- data[i] = CY_GET_REG8(scsiTarget_datapath__F1_REG);\r
+ data[i] = scsiPhyRx();\r
++i;\r
}\r
}\r
while (SCSI_ReadPin(SCSI_In_ACK) && !scsiDev.resetFlag) {}\r
-\r
}\r
\r
-void scsiWriteByte(uint8 value)\r
+static void\r
+doRxSingleDMA(uint8* data, uint32 count)\r
{\r
- while (!(CY_GET_REG8(scsiTarget_StatusReg__STATUS_REG) & 1) &&\r
- !scsiDev.resetFlag) {}\r
- CY_SET_REG8(scsiTarget_datapath__F0_REG, value);\r
+ // Prepare DMA transfer\r
+ dmaInProgress = 1;\r
\r
- // TODO maybe move this TX EMPTY check to scsiEnterPhase ?\r
- //while (!(CY_GET_REG8(scsiTarget_StatusReg__STATUS_REG) & 4)) {}\r
- while (!(CY_GET_REG8(scsiTarget_StatusReg__STATUS_REG) & 2) &&\r
- !scsiDev.resetFlag) {}\r
- value = CY_GET_REG8(scsiTarget_datapath__F1_REG);\r
+ CyDmaTdSetConfiguration(\r
+ scsiDmaTxTd[0],\r
+ count,\r
+ CY_DMA_DISABLE_TD, // Disable the DMA channel when TD completes count bytes\r
+ SCSI_TX_DMA__TD_TERMOUT_EN // Trigger interrupt when complete\r
+ );\r
+ CyDmaTdSetConfiguration(\r
+ scsiDmaRxTd[0],\r
+ count,\r
+ CY_DMA_DISABLE_TD, // Disable the DMA channel when TD completes count bytes\r
+ TD_INC_DST_ADR |\r
+ SCSI_RX_DMA__TD_TERMOUT_EN // Trigger interrupt when complete\r
+ );\r
\r
+ CyDmaTdSetAddress(\r
+ scsiDmaTxTd[0],\r
+ LO16((uint32)&dummyBuffer),\r
+ LO16((uint32)scsiTarget_datapath__F0_REG));\r
+ CyDmaTdSetAddress(\r
+ scsiDmaRxTd[0],\r
+ LO16((uint32)scsiTarget_datapath__F1_REG),\r
+ LO16((uint32)data)\r
+ );\r
+ \r
+ CyDmaChSetInitialTd(scsiDmaTxChan, scsiDmaTxTd[0]);\r
+ CyDmaChSetInitialTd(scsiDmaRxChan, scsiDmaRxTd[0]);\r
+ \r
+ // The DMA controller is a bit trigger-happy. It will retain\r
+ // a drq request that was triggered while the channel was\r
+ // disabled.\r
+ CyDmaClearPendingDrq(scsiDmaTxChan);\r
+ CyDmaClearPendingDrq(scsiDmaRxChan);\r
+\r
+ txDMAComplete = 0;\r
+ rxDMAComplete = 0;\r
+\r
+ CyDmaChEnable(scsiDmaRxChan, 1);\r
+ CyDmaChEnable(scsiDmaTxChan, 1);\r
+}\r
+\r
+void\r
+scsiReadDMA(uint8* data, uint32 count)\r
+{\r
+ dmaSentCount = 0;\r
+ dmaTotalCount = count;\r
+ dmaBuffer = data;\r
+\r
+ uint32_t singleCount = (count > MAX_DMA_BYTES) ? MAX_DMA_BYTES : count;\r
+ doRxSingleDMA(data, singleCount);\r
+ dmaSentCount += count;\r
+}\r
+\r
+int\r
+scsiReadDMAPoll()\r
+{\r
+ if (txDMAComplete && rxDMAComplete && (scsiPhyStatus() & SCSI_PHY_TX_COMPLETE))\r
+ {\r
+ if (dmaSentCount == dmaTotalCount)\r
+ {\r
+ dmaInProgress = 0;\r
+ while (SCSI_ReadPin(SCSI_In_ACK) && !scsiDev.resetFlag) {}\r
+ return 1;\r
+ }\r
+ else\r
+ {\r
+ // Transfer was too large for a single DMA transfer. Continue\r
+ // to send remaining bytes.\r
+ uint32_t count = dmaTotalCount - dmaSentCount;\r
+ if (count > MAX_DMA_BYTES) count = MAX_DMA_BYTES;\r
+ doRxSingleDMA(dmaBuffer + dmaSentCount, count);\r
+ dmaSentCount += count;\r
+ return 0;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ return 0;\r
+ }\r
+}\r
+\r
+void\r
+scsiRead(uint8_t* data, uint32_t count)\r
+{\r
+ if (count < 8)\r
+ {\r
+ scsiReadPIO(data, count);\r
+ }\r
+ else\r
+ {\r
+ scsiReadDMA(data, count);\r
+ while (!scsiReadDMAPoll() && !scsiDev.resetFlag) {};\r
+ }\r
+}\r
+\r
+void\r
+scsiWriteByte(uint8 value)\r
+{\r
+ while (scsiPhyTxFifoFull() && !scsiDev.resetFlag) {}\r
+ scsiPhyTx(value);\r
+\r
+ while (!(scsiPhyStatus() & SCSI_PHY_TX_COMPLETE) && !scsiDev.resetFlag) {}\r
+ scsiPhyRxFifoClear();\r
+\r
while (SCSI_ReadPin(SCSI_In_ACK) && !scsiDev.resetFlag) {}\r
}\r
\r
-void scsiWrite(uint8* data, uint32 count)\r
+static void\r
+scsiWritePIO(uint8_t* data, uint32_t count)\r
{\r
- int prep = 0;\r
int i = 0;\r
\r
while (i < count && !scsiDev.resetFlag)\r
{\r
- if (prep < count && (CY_GET_REG8(scsiTarget_StatusReg__STATUS_REG) & 1))\r
+ if (!scsiPhyTxFifoFull())\r
{\r
- CY_SET_REG8(scsiTarget_datapath__F0_REG, data[prep]);\r
- ++prep;\r
+ scsiPhyTx(data[i]);\r
+ ++i;\r
}\r
- if ((CY_GET_REG8(scsiTarget_StatusReg__STATUS_REG) & 2))\r
+ }\r
+\r
+ while (!(scsiPhyStatus() & SCSI_PHY_TX_COMPLETE) && !scsiDev.resetFlag) {}\r
+ scsiPhyRxFifoClear();\r
+}\r
+\r
+static void\r
+doTxSingleDMA(uint8* data, uint32 count)\r
+{\r
+ // Prepare DMA transfer\r
+ dmaInProgress = 1;\r
+\r
+ CyDmaTdSetConfiguration(\r
+ scsiDmaTxTd[0],\r
+ count,\r
+ CY_DMA_DISABLE_TD, // Disable the DMA channel when TD completes count bytes\r
+ TD_INC_SRC_ADR |\r
+ SCSI_TX_DMA__TD_TERMOUT_EN // Trigger interrupt when complete\r
+ );\r
+ CyDmaTdSetAddress(\r
+ scsiDmaTxTd[0],\r
+ LO16((uint32)data),\r
+ LO16((uint32)scsiTarget_datapath__F0_REG));\r
+ CyDmaChSetInitialTd(scsiDmaTxChan, scsiDmaTxTd[0]);\r
+\r
+ // The DMA controller is a bit trigger-happy. It will retain\r
+ // a drq request that was triggered while the channel was\r
+ // disabled.\r
+ CyDmaClearPendingDrq(scsiDmaTxChan);\r
+\r
+ txDMAComplete = 0;\r
+\r
+ CyDmaChEnable(scsiDmaTxChan, 1);\r
+}\r
+\r
+void\r
+scsiWriteDMA(uint8* data, uint32 count)\r
+{\r
+ dmaSentCount = 0;\r
+ dmaTotalCount = count;\r
+ dmaBuffer = data;\r
+\r
+ uint32_t singleCount = (count > MAX_DMA_BYTES) ? MAX_DMA_BYTES : count;\r
+ doTxSingleDMA(data, singleCount);\r
+ dmaSentCount += count;\r
+}\r
+\r
+int\r
+scsiWriteDMAPoll()\r
+{\r
+ if (txDMAComplete && (scsiPhyStatus() & SCSI_PHY_TX_COMPLETE))\r
+ {\r
+ if (dmaSentCount == dmaTotalCount)\r
{\r
- CY_GET_REG8(scsiTarget_datapath__F1_REG);\r
- ++i;\r
+ scsiPhyRxFifoClear();\r
+ dmaInProgress = 0;\r
+ while (SCSI_ReadPin(SCSI_In_ACK) && !scsiDev.resetFlag) {}\r
+ return 1;\r
+ }\r
+ else\r
+ {\r
+ // Transfer was too large for a single DMA transfer. Continue\r
+ // to send remaining bytes.\r
+ uint32_t count = dmaTotalCount - dmaSentCount;\r
+ if (count > MAX_DMA_BYTES) count = MAX_DMA_BYTES;\r
+ doTxSingleDMA(dmaBuffer + dmaSentCount, count);\r
+ dmaSentCount += count;\r
+ return 0;\r
}\r
}\r
- \r
- while (SCSI_ReadPin(SCSI_In_ACK) && !scsiDev.resetFlag) {}\r
+ else\r
+ {\r
+ return 0;\r
+ }\r
+}\r
+\r
+void\r
+scsiWrite(uint8_t* data, uint32_t count)\r
+{\r
+ if (count < 8)\r
+ {\r
+ scsiWritePIO(data, count);\r
+ }\r
+ else\r
+ {\r
+ scsiWriteDMA(data, count);\r
+ while (!scsiWriteDMAPoll() && !scsiDev.resetFlag) {};\r
+ }\r
}\r
\r
static void busSettleDelay(void)\r
\r
void scsiPhyReset()\r
{\r
+ if (dmaInProgress)\r
+ {\r
+ dmaInProgress = 0;\r
+ dmaBuffer = NULL;\r
+ dmaSentCount = 0;\r
+ dmaTotalCount = 0;\r
+ CyDmaChSetRequest(scsiDmaTxChan, CY_DMA_CPU_TERM_CHAIN);\r
+ CyDmaChSetRequest(scsiDmaRxChan, CY_DMA_CPU_TERM_CHAIN);\r
+ while (!(txDMAComplete && rxDMAComplete)) {}\r
+\r
+ CyDmaChDisable(scsiDmaTxChan);\r
+ CyDmaChDisable(scsiDmaRxChan);\r
+ }\r
+\r
// Set the Clear bits for both SCSI device FIFOs\r
scsiTarget_AUX_CTL = scsiTarget_AUX_CTL | 0x03;\r
\r
scsiTarget_AUX_CTL = scsiTarget_AUX_CTL & ~(0x03);\r
}\r
\r
+static void scsiPhyInitDMA()\r
+{\r
+ // One-time init only.\r
+ if (scsiDmaTxChan == CY_DMA_INVALID_CHANNEL)\r
+ {\r
+ scsiDmaRxChan =\r
+ SCSI_RX_DMA_DmaInitialize(\r
+ 1, // Bytes per burst\r
+ 1, // request per burst\r
+ HI16(CYDEV_PERIPH_BASE),\r
+ HI16(CYDEV_SRAM_BASE)\r
+ );\r
+ \r
+ scsiDmaTxChan =\r
+ SCSI_TX_DMA_DmaInitialize(\r
+ 1, // Bytes per burst\r
+ 1, // request per burst\r
+ HI16(CYDEV_SRAM_BASE),\r
+ HI16(CYDEV_PERIPH_BASE)\r
+ );\r
+\r
+ CyDmaChDisable(scsiDmaRxChan);\r
+ CyDmaChDisable(scsiDmaTxChan);\r
+\r
+ scsiDmaRxTd[0] = CyDmaTdAllocate();\r
+ scsiDmaTxTd[0] = CyDmaTdAllocate();\r
+ \r
+ SCSI_RX_DMA_COMPLETE_StartEx(scsiRxCompleteISR);\r
+ SCSI_TX_DMA_COMPLETE_StartEx(scsiTxCompleteISR);\r
+ }\r
+}\r
+\r
+\r
void scsiPhyInit()\r
{\r
+ scsiPhyInitDMA();\r
+\r
SCSI_RST_ISR_StartEx(scsiResetISR);\r
\r
// Interrupts may have already been directed to the (empty)\r
#ifndef SCSIPHY_H
#define SCSIPHY_H
+// Definitions to match the scsiTarget status register.
+typedef enum
+{
+ SCSI_PHY_TX_FIFO_NOT_FULL = 0x01,
+ SCSI_PHY_RX_FIFO_NOT_EMPTY = 0x02,
+
+ // The TX FIFO is empty and the state machine is in the idle state
+ SCSI_PHY_TX_COMPLETE = 0x10
+} SCSI_PHY_STATE;
+
+#define scsiPhyStatus() CY_GET_REG8(scsiTarget_StatusReg__STATUS_REG)
+#define scsiPhyTxFifoFull() ((scsiPhyStatus() & SCSI_PHY_TX_FIFO_NOT_FULL) == 0)
+#define scsiPhyRxFifoEmpty() ((scsiPhyStatus() & SCSI_PHY_RX_FIFO_NOT_EMPTY) == 0)
+
+// Clear 4 byte fifo
+#define scsiPhyRxFifoClear() scsiPhyRx(); scsiPhyRx(); scsiPhyRx(); scsiPhyRx();
+
+#define scsiPhyTx(val) CY_SET_REG8(scsiTarget_datapath__F0_REG, (val))
+#define scsiPhyRx() CY_GET_REG8(scsiTarget_datapath__F1_REG)
+
#define SCSI_SetPin(pin) \
CyPins_SetPin((pin));
(CyPins_ReadPin((pin)) == 0)
// Contains the odd-parity flag for a given 8-bit value.
-extern const uint8 Lookup_OddParity[256];
+extern const uint8_t Lookup_OddParity[256];
void scsiPhyReset(void);
void scsiPhyInit(void);
-uint8 scsiReadByte(void);
-void scsiRead(uint8* data, uint32 count);
-void scsiWriteByte(uint8 value);
-void scsiWrite(uint8* data, uint32 count);
-uint8 scsiReadDBxPins(void);
+uint8_t scsiReadByte(void);
+void scsiRead(uint8_t* data, uint32_t count);
+void scsiReadDMA(uint8_t* data, uint32_t count);
+int scsiReadDMAPoll();
+
+void scsiWriteByte(uint8_t value);
+void scsiWrite(uint8_t* data, uint32_t count);
+void scsiWriteDMA(uint8_t* data, uint32_t count);
+int scsiWriteDMAPoll();
+
+uint8_t scsiReadDBxPins(void);
void scsiEnterPhase(int phase);
// Global\r
SdDevice sdDev;\r
\r
+// Private DMA variables.\r
+static int dmaInProgress = 0;\r
+static uint8 sdDMARxChan = CY_DMA_INVALID_CHANNEL;\r
+static uint8 sdDMATxChan = CY_DMA_INVALID_CHANNEL;\r
+\r
+// DMA descriptors\r
+static uint8 sdDMARxTd[1] = { CY_DMA_INVALID_TD };\r
+static uint8 sdDMATxTd[1] = { CY_DMA_INVALID_TD };\r
+\r
+// Dummy location for DMA to send unchecked CRC bytes to\r
+static uint8 discardBuffer;\r
+\r
+// Source of dummy SPI bytes for DMA\r
+static uint8 dummyBuffer = 0xFF;\r
+\r
+volatile static uint8 rxDMAComplete;\r
+volatile static uint8 txDMAComplete;\r
+\r
+CY_ISR_PROTO(sdRxISR);\r
+CY_ISR(sdRxISR)\r
+{\r
+ rxDMAComplete = 1;\r
+}\r
+CY_ISR_PROTO(sdTxISR);\r
+CY_ISR(sdTxISR)\r
+{\r
+ txDMAComplete = 1;\r
+}\r
+\r
static uint8 sdCrc7(uint8* chr, uint8 cnt, uint8 crc)\r
{\r
uint8 a;\r
}\r
\r
\r
-void sdPrepareRead()\r
+void\r
+sdReadMultiSectorPrep()\r
{\r
uint8 v;\r
uint32 scsiLBA = (transfer.lba + transfer.currentBlock);\r
uint32 sdLBA = SCSISector2SD(scsiLBA);\r
- \r
+\r
if (!sdDev.ccs)\r
{\r
sdLBA = sdLBA * SD_SECTOR_SIZE;\r
}\r
}\r
\r
-static void doReadSector(uint32_t numBytes)\r
+static void\r
+dmaReadSector(uint8_t* outputBuffer)\r
{\r
- int prep, i, guard;\r
-\r
// Wait for a start-block token.\r
// Don't wait more than 100ms, which is the timeout recommended\r
// in the standard.\r
return;\r
}\r
\r
- scsiEnterPhase(DATA_IN);\r
+ CyDmaTdSetConfiguration(sdDMARxTd[0], SD_SECTOR_SIZE, CY_DMA_DISABLE_TD, TD_INC_DST_ADR | SD_RX_DMA__TD_TERMOUT_EN);\r
+ CyDmaTdSetAddress(sdDMARxTd[0], LO16((uint32)SDCard_RXDATA_PTR), LO16((uint32)outputBuffer));\r
+ CyDmaTdSetConfiguration(sdDMATxTd[0], SD_SECTOR_SIZE, CY_DMA_DISABLE_TD, SD_TX_DMA__TD_TERMOUT_EN);\r
+ CyDmaTdSetAddress(sdDMATxTd[0], LO16((uint32)&dummyBuffer), LO16((uint32)SDCard_TXDATA_PTR));\r
\r
- // Quickly seed the FIFO\r
- prep = 4;\r
- CY_SET_REG8(SDCard_TXDATA_PTR, 0xFF); // Put a byte in the FIFO\r
- CY_SET_REG8(SDCard_TXDATA_PTR, 0xFF); // Put a byte in the FIFO\r
- CY_SET_REG8(SDCard_TXDATA_PTR, 0xFF); // Put a byte in the FIFO\r
- CY_SET_REG8(SDCard_TXDATA_PTR, 0xFF); // Put a byte in the FIFO\r
- \r
- i = 0;\r
- guard = 0;\r
- \r
- // This loop is critically important for performance.\r
- // We stream data straight from the SDCard fifos into the SCSI component\r
- // FIFO's. If the loop isn't fast enough, the transmit FIFO's will empty,\r
- // and performance will suffer. Every clock cycle counts.\r
- while (i < numBytes && !scsiDev.resetFlag)\r
- {\r
- uint8_t sdRxStatus = CY_GET_REG8(SDCard_RX_STATUS_PTR);\r
- uint8_t scsiStatus = CY_GET_REG8(scsiTarget_StatusReg__STATUS_REG);\r
-\r
- // Read from the SPIM fifo if there is room to stream the byte to the\r
- // SCSI fifos\r
- if((sdRxStatus & SDCard_STS_RX_FIFO_NOT_EMPTY) &&\r
- (scsiStatus & 1) // SCSI TX FIFO NOT FULL\r
- )\r
- {\r
- uint8_t val = CY_GET_REG8(SDCard_RXDATA_PTR);\r
- CY_SET_REG8(scsiTarget_datapath__F0_REG, val);\r
- guard++;\r
+ dmaInProgress = 1;\r
+ // The DMA controller is a bit trigger-happy. It will retain\r
+ // a drq request that was triggered while the channel was\r
+ // disabled.\r
+ CyDmaClearPendingDrq(sdDMATxChan);\r
+ CyDmaClearPendingDrq(sdDMARxChan);\r
\r
- // How many bytes are in a 4-byte FIFO ? 5. 4 FIFO bytes PLUS one byte\r
- // being processed bit-by-bit. Artifically limit the number of bytes in the \r
- // "combined" SPIM TX and RX FIFOS to the individual FIFO size.\r
- // Unlike the SCSI component, SPIM doesn't check if there's room in\r
- // the output FIFO before starting to transmit.\r
+ txDMAComplete = 0;\r
+ rxDMAComplete = 0;\r
\r
- if (prep < numBytes)\r
- {\r
- CY_SET_REG8(SDCard_TXDATA_PTR, 0xFF); // Put a byte in the FIFO\r
- prep++;\r
- }\r
+ // Re-loading the initial TD's here is very important, or else\r
+ // we'll be re-using the last-used TD, which would be the last\r
+ // in the chain (ie. CRC TD)\r
+ CyDmaChSetInitialTd(sdDMARxChan, sdDMARxTd[0]);\r
+ CyDmaChSetInitialTd(sdDMATxChan, sdDMATxTd[0]);\r
\r
- }\r
- \r
- // Byte has been sent out the SCSI interface.\r
- if (scsiStatus & 2) // SCSI RX FIFO NOT EMPTY\r
- {\r
- CY_GET_REG8(scsiTarget_datapath__F1_REG);\r
- ++i;\r
- }\r
- }\r
+ // There is no flow control, so we must ensure we can read the bytes\r
+ // before we start transmitting\r
+ CyDmaChEnable(sdDMARxChan, 1);\r
+ CyDmaChEnable(sdDMATxChan, 1);\r
+}\r
\r
- // Read and discard remaining bytes. This applis for non-512 byte sectors,\r
- // or if a SCSI reset was triggered.\r
- while (guard < SD_SECTOR_SIZE)\r
+int\r
+sdReadSectorDMAPoll()\r
+{\r
+ if (rxDMAComplete && txDMAComplete)\r
{\r
- uint8_t sdRxStatus = CY_GET_REG8(SDCard_RX_STATUS_PTR);\r
- if(sdRxStatus & SDCard_STS_RX_FIFO_NOT_EMPTY)\r
- {\r
- CY_GET_REG8(SDCard_RXDATA_PTR);\r
- guard++;\r
- }\r
+ // DMA transfer is complete\r
+ dmaInProgress = 0;\r
\r
- if ((prep - guard < 4) && (prep < SD_SECTOR_SIZE))\r
- {\r
- CY_SET_REG8(SDCard_TXDATA_PTR, 0xFF); // Put a byte in the FIFO\r
- prep++;\r
- }\r
- }\r
+ sdSpiByte(0xFF); // CRC\r
+ sdSpiByte(0xFF); // CRC\r
\r
- sdSpiByte(0xFF); // CRC\r
- sdSpiByte(0xFF); // CRC\r
- scsiDev.dataLen = numBytes;\r
- scsiDev.dataPtr = numBytes;\r
- \r
- while (SCSI_ReadPin(SCSI_In_ACK) && !scsiDev.resetFlag) {}\r
+ return 1;\r
+ }\r
+ else\r
+ {\r
+ return 0;\r
+ }\r
}\r
\r
-static void doReadSectorSingle(uint32 sdBlock, int sdBytes)\r
+void sdReadSingleSectorDMA(uint32_t lba, uint8_t* outputBuffer)\r
{\r
uint8 v;\r
if (!sdDev.ccs)\r
{\r
- sdBlock = sdBlock * SD_SECTOR_SIZE;\r
- } \r
- v = sdCommandAndResponse(SD_READ_SINGLE_BLOCK, sdBlock);\r
+ lba = lba * SD_SECTOR_SIZE;\r
+ }\r
+ v = sdCommandAndResponse(SD_READ_SINGLE_BLOCK, lba);\r
if (v)\r
{\r
scsiDiskReset();\r
}\r
else\r
{\r
- doReadSector(sdBytes);\r
+ dmaReadSector(outputBuffer);\r
}\r
}\r
\r
-\r
-void sdReadSectorSingle()\r
+void\r
+sdReadMultiSectorDMA(uint8_t* outputBuffer)\r
{\r
- uint32 scsiLBA = (transfer.lba + transfer.currentBlock);\r
- uint32 sdLBA = SCSISector2SD(scsiLBA);\r
- \r
- int sdSectors = SDSectorsPerSCSISector();\r
- int i;\r
- for (i = 0; (i < sdSectors - 1) && (scsiDev.status != CHECK_CONDITION); ++i)\r
- {\r
- doReadSectorSingle(sdLBA + i, SD_SECTOR_SIZE);\r
- }\r
-\r
- if (scsiDev.status != CHECK_CONDITION)\r
- {\r
- int remaining = config->bytesPerSector % SD_SECTOR_SIZE;\r
- if (remaining == 0) remaining = SD_SECTOR_SIZE; // Full sector needed.\r
- doReadSectorSingle(sdLBA + i, remaining);\r
- }\r
+ // Pre: sdReadMultiSectorPrep called.\r
+ dmaReadSector(outputBuffer);\r
}\r
\r
-void sdReadSectorMulti()\r
-{\r
- // Pre: sdPrepareRead called.\r
- int sdSectors = SDSectorsPerSCSISector();\r
- int i;\r
- for (i = 0; (i < sdSectors - 1) && (scsiDev.status != CHECK_CONDITION); ++i)\r
- {\r
- doReadSector(SD_SECTOR_SIZE);\r
- }\r
\r
- if (scsiDev.status != CHECK_CONDITION)\r
+void sdCompleteRead()\r
+{\r
+ if (dmaInProgress)\r
{\r
- int remaining = config->bytesPerSector % SD_SECTOR_SIZE;\r
- if (remaining == 0) remaining = SD_SECTOR_SIZE; // Full sector needed.\r
- doReadSector(remaining);\r
+ // Not much choice but to wait until we've completed the transfer.\r
+ // Cancelling the transfer can't be done as we have no way to reset\r
+ // the SD card.\r
+ while (!sdReadSectorDMAPoll()) { /* spin */ }\r
}\r
-}\r
\r
-\r
-void sdCompleteRead()\r
-{\r
transfer.inProgress = 0;\r
\r
// We cannot send even a single "padding" byte, as we normally would when\r
} while (val != 0xFF);\r
}\r
\r
-static int doWriteSector(uint32_t numBytes)\r
+void\r
+sdWriteMultiSectorDMA(uint8_t* outputBuffer)\r
{\r
- int prep, i, guard;\r
- int result, maxWait;\r
- uint8 dataToken;\r
-\r
- scsiEnterPhase(DATA_OUT);\r
- \r
sdSpiByte(0xFC); // MULTIPLE byte start token\r
- \r
- prep = 0;\r
- i = 0;\r
- guard = 0;\r
-\r
- // This loop is critically important for performance.\r
- // We stream data straight from the SCSI fifos into the SPIM component\r
- // FIFO's. If the loop isn't fast enough, the transmit FIFO's will empty,\r
- // and performance will suffer. Every clock cycle counts. \r
- while (i < numBytes && !scsiDev.resetFlag)\r
- {\r
- uint8_t sdRxStatus = CY_GET_REG8(SDCard_RX_STATUS_PTR);\r
- uint8_t scsiStatus = CY_GET_REG8(scsiTarget_StatusReg__STATUS_REG);\r
-\r
- // Read from the SCSI fifo if there is room to stream the byte to the\r
- // SPIM fifos\r
- // See sdReadSector for comment on guard (FIFO size is really 5)\r
- if((guard - i < 4) &&\r
- (scsiDev.resetFlag || (scsiStatus & 2))\r
- ) // SCSI RX FIFO NOT EMPTY\r
- {\r
- uint8_t val = CY_GET_REG8(scsiTarget_datapath__F1_REG);\r
- CY_SET_REG8(SDCard_TXDATA_PTR, val);\r
- guard++;\r
- }\r
-\r
- // Byte has been sent out the SPIM interface.\r
- if (sdRxStatus & SDCard_STS_RX_FIFO_NOT_EMPTY)\r
- {\r
- CY_GET_REG8(SDCard_RXDATA_PTR);\r
- ++i;\r
- }\r
\r
- if (prep < numBytes &&\r
- (scsiDev.resetFlag || (scsiStatus & 1)) // SCSI TX FIFO NOT FULL\r
- )\r
- {\r
- // Trigger the SCSI component to read a byte\r
- CY_SET_REG8(scsiTarget_datapath__F0_REG, 0xFF);\r
- prep++;\r
- }\r
- }\r
+ CyDmaTdSetConfiguration(sdDMATxTd[0], SD_SECTOR_SIZE, CY_DMA_DISABLE_TD, TD_INC_SRC_ADR | SD_TX_DMA__TD_TERMOUT_EN);\r
+ CyDmaTdSetAddress(sdDMATxTd[0], LO16((uint32)outputBuffer), LO16((uint32)SDCard_TXDATA_PTR));\r
+ CyDmaTdSetConfiguration(sdDMARxTd[0], SD_SECTOR_SIZE, CY_DMA_DISABLE_TD, SD_RX_DMA__TD_TERMOUT_EN);\r
+ CyDmaTdSetAddress(sdDMARxTd[0], LO16((uint32)SDCard_RXDATA_PTR), LO16((uint32)&discardBuffer));\r
\r
- // Write remaining bytes as 0x00\r
- while (i < SD_SECTOR_SIZE)\r
+ dmaInProgress = 1;\r
+ // The DMA controller is a bit trigger-happy. It will retain\r
+ // a drq request that was triggered while the channel was\r
+ // disabled.\r
+ CyDmaClearPendingDrq(sdDMATxChan);\r
+ CyDmaClearPendingDrq(sdDMARxChan);\r
+\r
+ txDMAComplete = 0;\r
+ rxDMAComplete = 0;\r
+\r
+ // Re-loading the initial TD's here is very important, or else\r
+ // we'll be re-using the last-used TD, which would be the last\r
+ // in the chain (ie. CRC TD)\r
+ CyDmaChSetInitialTd(sdDMARxChan, sdDMARxTd[0]);\r
+ CyDmaChSetInitialTd(sdDMATxChan, sdDMATxTd[0]);\r
+\r
+ // There is no flow control, so we must ensure we can read the bytes\r
+ // before we start transmitting\r
+ CyDmaChEnable(sdDMARxChan, 1);\r
+ CyDmaChEnable(sdDMATxChan, 1);\r
+}\r
+\r
+int\r
+sdWriteSectorDMAPoll()\r
+{\r
+ if (rxDMAComplete && txDMAComplete)\r
{\r
- uint8_t sdRxStatus = CY_GET_REG8(SDCard_RX_STATUS_PTR);\r
+ // DMA transfer is complete\r
+ dmaInProgress = 0;\r
\r
- if((guard - i < 4) && (guard < SD_SECTOR_SIZE))\r
- {\r
- CY_SET_REG8(SDCard_TXDATA_PTR, 0x00);\r
- guard++;\r
- }\r
+ sdSpiByte(0x00); // CRC\r
+ sdSpiByte(0x00); // CRC\r
\r
- // Byte has been sent out the SPIM interface.\r
- if (sdRxStatus & SDCard_STS_RX_FIFO_NOT_EMPTY)\r
+ // Don't wait more than 1s.\r
+ // My 2g Kingston micro-sd card doesn't respond immediately.\r
+ // My 16Gb card does.\r
+ int maxWait = 1000000;\r
+ uint8_t dataToken = sdSpiByte(0xFF); // Response\r
+ while (dataToken == 0xFF && maxWait-- > 0)\r
{\r
- CY_GET_REG8(SDCard_RXDATA_PTR);\r
- ++i;\r
+ CyDelayUs(1);\r
+ dataToken = sdSpiByte(0xFF);\r
}\r
- }\r
- \r
- sdSpiByte(0x00); // CRC\r
- sdSpiByte(0x00); // CRC\r
-\r
- // Don't wait more than 1s.\r
- // My 2g Kingston micro-sd card doesn't respond immediately.\r
- // My 16Gb card does.\r
- maxWait = 1000000;\r
- dataToken = sdSpiByte(0xFF); // Response\r
- while (dataToken == 0xFF && maxWait-- > 0)\r
- {\r
- CyDelayUs(1);\r
- dataToken = sdSpiByte(0xFF);\r
- }\r
- if (((dataToken & 0x1F) >> 1) != 0x2) // Accepted.\r
- {\r
- uint8 r1b, busy;\r
+ if (((dataToken & 0x1F) >> 1) != 0x2) // Accepted.\r
+ {\r
+ uint8 r1b, busy;\r
\r
- sdWaitWriteBusy();\r
+ sdWaitWriteBusy();\r
\r
- r1b = sdCommandAndResponse(SD_STOP_TRANSMISSION, 0);\r
- (void) r1b;\r
- sdSpiByte(0xFF);\r
+ r1b = sdCommandAndResponse(SD_STOP_TRANSMISSION, 0);\r
+ (void) r1b;\r
+ sdSpiByte(0xFF);\r
\r
- // R1b has an optional trailing "busy" signal.\r
- do\r
- {\r
- busy = sdSpiByte(0xFF);\r
- } while (busy == 0);\r
+ // R1b has an optional trailing "busy" signal.\r
+ do\r
+ {\r
+ busy = sdSpiByte(0xFF);\r
+ } while (busy == 0);\r
\r
- // Wait for the card to come out of busy.\r
- sdWaitWriteBusy();\r
+ // Wait for the card to come out of busy.\r
+ sdWaitWriteBusy();\r
\r
- transfer.inProgress = 0;\r
- scsiDiskReset();\r
- sdClearStatus();\r
+ transfer.inProgress = 0;\r
+ scsiDiskReset();\r
+ sdClearStatus();\r
\r
- scsiDev.status = CHECK_CONDITION;\r
- scsiDev.sense.code = HARDWARE_ERROR;\r
- scsiDev.sense.asc = LOGICAL_UNIT_COMMUNICATION_FAILURE;\r
- scsiDev.phase = STATUS;\r
- result = 0;\r
+ scsiDev.status = CHECK_CONDITION;\r
+ scsiDev.sense.code = HARDWARE_ERROR;\r
+ scsiDev.sense.asc = LOGICAL_UNIT_COMMUNICATION_FAILURE;\r
+ scsiDev.phase = STATUS;\r
+ }\r
+ else\r
+ {\r
+ sdWaitWriteBusy();\r
+ } \r
+\r
+ return 1;\r
}\r
else\r
{\r
- sdWaitWriteBusy();\r
- result = 1;\r
+ return 0;\r
}\r
-\r
- while (SCSI_ReadPin(SCSI_In_ACK) && !scsiDev.resetFlag) {}\r
-\r
- return result;\r
}\r
\r
-int sdWriteSector()\r
+void sdCompleteWrite()\r
{\r
- int result = 1;\r
- // Pre: sdPrepareWrite called.\r
- int sdSectors = SDSectorsPerSCSISector();\r
- int i;\r
- for (i = 0; result && (i < sdSectors - 1) && (scsiDev.status != CHECK_CONDITION); ++i)\r
- {\r
- result = doWriteSector(SD_SECTOR_SIZE);\r
- }\r
-\r
- if (result && scsiDev.status != CHECK_CONDITION)\r
+ if (dmaInProgress)\r
{\r
- int remaining = config->bytesPerSector % SD_SECTOR_SIZE;\r
- if (remaining == 0) remaining = SD_SECTOR_SIZE; // Full sector needed.\r
- result = doWriteSector(remaining);\r
+ // Not much choice but to wait until we've completed the transfer.\r
+ // Cancelling the transfer can't be done as we have no way to reset\r
+ // the SD card.\r
+ while (!sdWriteSectorDMAPoll()) { /* spin */ }\r
}\r
- return result;\r
-}\r
-\r
-void sdCompleteWrite()\r
-{\r
+ \r
transfer.inProgress = 0;\r
\r
uint8 r1, r2;\r
return 0;\r
}\r
\r
+static void sdInitDMA()\r
+{\r
+ // One-time init only.\r
+ if (sdDMATxChan == CY_DMA_INVALID_CHANNEL)\r
+ {\r
+ sdDMATxChan =\r
+ SD_TX_DMA_DmaInitialize(\r
+ 1, // Bytes per burst\r
+ 1, // request per burst\r
+ HI16(CYDEV_SRAM_BASE),\r
+ HI16(CYDEV_PERIPH_BASE)\r
+ );\r
+\r
+ sdDMARxChan =\r
+ SD_RX_DMA_DmaInitialize(\r
+ 1, // Bytes per burst\r
+ 1, // request per burst\r
+ HI16(CYDEV_PERIPH_BASE),\r
+ HI16(CYDEV_SRAM_BASE)\r
+ );\r
+\r
+ CyDmaChDisable(sdDMATxChan);\r
+ CyDmaChDisable(sdDMARxChan);\r
+\r
+ sdDMARxTd[0] = CyDmaTdAllocate();\r
+ sdDMATxTd[0] = CyDmaTdAllocate();\r
+\r
+ SD_RX_DMA_COMPLETE_StartEx(sdRxISR);\r
+ SD_TX_DMA_COMPLETE_StartEx(sdTxISR);\r
+ }\r
+}\r
+\r
int sdInit()\r
{\r
int result = 0;\r
sdDev.ccs = 0;\r
sdDev.capacity = 0;\r
\r
+ sdInitDMA();\r
+\r
SD_CS_Write(1); // Set CS inactive (active low)\r
- SD_Init_Clk_Start(); // Turn on the slow 400KHz clock\r
- SD_Clk_Ctl_Write(0); // Select the 400KHz clock source.\r
+\r
+ // Set the SPI clock for 400kHz transfers\r
+ // 25MHz / 400kHz approx factor of 63.\r
+ uint16_t clkDiv25MHz = SD_Data_Clk_GetDividerRegister();\r
+ SD_Data_Clk_SetDivider(clkDiv25MHz * 63);\r
+ // Wait for the clock to settle.\r
+ CyDelayUs(1);\r
+\r
SDCard_Start(); // Enable SPI hardware\r
\r
// Power on sequence. 74 clock cycles of a "1" while CS unasserted.\r
v = sdCRCCommandAndResponse(SD_CRC_ON_OFF, 0); //crc off\r
if(v){goto bad;}\r
\r
- // now set the sd card up for full speed\r
+ // now set the sd card back to full speed.\r
// The SD Card spec says we can run SPI @ 25MHz\r
- // But the PSoC 5LP SPIM datasheet says the most we can do is 18MHz.\r
- // I've confirmed that no data is ever put into the RX FIFO when run at\r
- // 20MHz or 25MHz.\r
- // ... and then we get timing analysis failures if the BUS_CLK is over 62MHz.\r
- // So we run the MASTER_CLK and BUS_CLK at 60MHz, and run the SPI clock at 30MHz\r
- // (15MHz SPI transfer clock).\r
SDCard_Stop();\r
- \r
+\r
// We can't run at full-speed with the pullup resistors enabled.\r
SD_MISO_SetDriveMode(SD_MISO_DM_DIG_HIZ);\r
SD_MOSI_SetDriveMode(SD_MOSI_DM_STRONG);\r
SD_SCK_SetDriveMode(SD_SCK_DM_STRONG);\r
- \r
- SD_Data_Clk_Start(); // Turn on the fast clock\r
- SD_Clk_Ctl_Write(1); // Select the fast clock source.\r
- SD_Init_Clk_Stop(); // Stop the slow clock.\r
+\r
+ SD_Data_Clk_SetDivider(clkDiv25MHz);\r
CyDelayUs(1);\r
SDCard_Start();\r
\r
\r
}\r
\r
-void sdPrepareWrite()\r
+void sdWriteMultiSectorPrep()\r
{\r
uint8 v;\r
\r
extern SdDevice sdDev;
int sdInit(void);
-void sdPrepareWrite(void);
-int sdWriteSector(void);
+
+void sdWriteMultiSectorPrep(void);
+void sdWriteMultiSectorDMA(uint8_t* outputBuffer);
+int sdWriteSectorDMAPoll();
void sdCompleteWrite(void);
-void sdPrepareRead(void);
-void sdReadSectorMulti(void);
-void sdReadSectorSingle(void);
+void sdReadMultiSectorPrep(void);
+void sdReadMultiSectorDMA(uint8_t* outputBuffer);
+void sdReadSingleSectorDMA(uint32_t lba, uint8_t* outputBuffer);
+int sdReadSectorDMAPoll();
void sdCompleteRead(void);
#endif
projects / SCSI2SD.git / commitdiff