Renamed "pbook" firmware to "v4". Original "green" boards now under "v3".
Add external LED support for v4 firmware.
Added --reset to scsi2sd-config
bootloaderhost can now reset the board.
-201404xx 3.5
+20140713 3.5
- Fixed several performance issues. Transfer rates up to 2.5MB/s are now
possible.
- Implemented the READ BUFFER scsi command for performance testing purposes.
+ - Added support for the new "yellow" v4.2 revision boards.
+ - Improved firmware uploading. bootloaderhost can now reset the board back
+ to the bootloader.
+ - Display firmware version in scsi2sd-config
+ - Add "--reset" parameter to scsi2sd-config
20140418 3.4
- Critical fix for writes when using non-standard block sizes.
Compatibility
-Tested with Linux (current), Apple Macintosh System 7.5.3 on LC-III, and LC-475 hardware.
-
-Users have reported success on these systems:
+ Desktop systems
+ Mac LC-III and LC-475
Mac II running System 6.0.8
Mac SE/30
+ Apple IIgs using Apple II High Speed SCSI controller card (from v3.3)
+ Symbolics Lisp Machine XL1200, using 1280 byte sectors (from v3.4)
+ PDP-11/73 running RSX11M+ V4.6
+ Amiga 500+ with GVP A530
+ Atari TT030 System V
+
+Samplers
+
Roland JS-30 Sampler
Akai S1000, S3200, S3000XL, MPC 2000XL, DPS 12
+ SCSI cable reversed on S3200
+ There are compatibility problems with the Akai MPC3000. It works (slowly) with the alternate Vailixi OS with multi-sector transfers disabled.
EMU Emulator E4X with EOS 3.00b and E6400 (classic) with Eos 4.01
Ensoniq ASR-X, ASR-10 (from v3.4, 2GB size limit)
+ ASR-20 Requires TERMPWR jumper.
+ Kurzweil K2000R
+ See kurzweil.com for size limits which a dependant on the OS version. Older OS versions have a 1GB limit.
+ SCSI cable reversed
+ Casio FZ-20M
+ Requires TERMPWR jumper. The manual shows the pin25 of the DB25 connector is "not connected".
+ May require scsi2sd-config --apple flag
+
+Other
+
HP 16601A logic analyzer
- Apple IIgs using Apple II High Speed SCSI controller card (from v3.3)
- Symbolics List Machine XL1200, using 1280 byte sectors (from v3.4)
- Fluke 9100 series
- PDP-11/73 running RSX11M+ V4.6
- Amiga 500+ with GVP A530
+ Fluke 9100 series
+++ /dev/null
-../../SCSI2SD.cydsn/OddParityGen/
\ No newline at end of file
+++ /dev/null
-../../SCSI2SD.cydsn/scsiTarget/
\ No newline at end of file
\r
// CYDEV_EEPROM_ROW_SIZE == 16.\r
static const char magic[CYDEV_EEPROM_ROW_SIZE] = "codesrc_00000002";\r
+static const uint16_t FIRMWARE_VERSION = 0x0350;\r
\r
// Config shadow RAM (copy of EEPROM)\r
static Config shadow =\r
{\r
USB_EP_OUT = 1,\r
USB_EP_IN = 2,\r
+ USB_EP_COMMAND = 3,\r
USB_EP_DEBUG = 4\r
};\r
enum USB_STATE\r
if (reset)\r
{\r
USBFS_EnableOutEP(USB_EP_OUT);\r
+ USBFS_EnableOutEP(USB_EP_COMMAND);\r
usbInEpState = usbDebugEpState = USB_IDLE;\r
}\r
\r
}\r
}\r
\r
-#ifdef MM_DEBUG\r
void debugPoll()\r
{\r
if (!usbReady)\r
{\r
return;\r
}\r
- \r
+\r
+ if(USBFS_GetEPState(USB_EP_COMMAND) == USBFS_OUT_BUFFER_FULL)\r
+ {\r
+ // The host sent us some data!\r
+ int byteCount = USBFS_GetEPCount(USB_EP_COMMAND);\r
+ USBFS_ReadOutEP(USB_EP_COMMAND, (uint8 *)&debugBuffer, byteCount);\r
+\r
+ if (byteCount >= 1 &&\r
+ debugBuffer[0] == 0x01)\r
+ {\r
+ // Reboot command.\r
+ Bootloadable_1_Load();\r
+ }\r
+\r
+ // Allow the host to send us another command.\r
+ // (assuming we didn't reboot outselves)\r
+ USBFS_EnableOutEP(USB_EP_COMMAND);\r
+ }\r
+\r
switch (usbDebugEpState)\r
{\r
case USB_IDLE:\r
debugBuffer[24] = scsiDev.cmdCount;\r
debugBuffer[25] = scsiDev.watchdogTick;\r
\r
+ debugBuffer[58] = sdDev.capacity >> 24;\r
+ debugBuffer[59] = sdDev.capacity >> 16;\r
+ debugBuffer[60] = sdDev.capacity >> 8;\r
+ debugBuffer[61] = sdDev.capacity;\r
+\r
+ debugBuffer[62] = FIRMWARE_VERSION >> 8;\r
+ debugBuffer[63] = FIRMWARE_VERSION;\r
+\r
USBFS_LoadInEP(USB_EP_DEBUG, (uint8 *)&debugBuffer, sizeof(debugBuffer));\r
usbDebugEpState = USB_DATA_SENT;\r
break;\r
debugPoll();\r
CyExitCriticalSection(savedIntrStatus); \r
}\r
-#endif\r
\r
void debugInit()\r
{\r
-#ifdef MM_DEBUG\r
Debug_Timer_Interrupt_StartEx(debugTimerISR);\r
Debug_Timer_Start();\r
-#else\r
- Debug_Timer_Interrupt_Stop();\r
- Debug_Timer_Stop();\r
-#endif\r
- \r
}\r
\r
// Public method for storing MODE SELECT results.\r
// multi-block write is minimal.\r
transfer.multiBlock = 1;\r
\r
- if (blocks > 1) scsiDev.needReconnect = 1;\r
sdWriteMultiSectorPrep();\r
}\r
}\r
else\r
{\r
transfer.multiBlock = 1;\r
- scsiDev.needReconnect = 1;\r
sdReadMultiSectorPrep();\r
}\r
}\r
}\r
#endif\r
\r
- if (SD_CD_Read() == 1)\r
+ // The Card-detect switches of micro-sd sockets are not standard. Don't make\r
+ // use of SD_CD so we can use sockets from other manufacturers.\r
+ // Detect presence of the card by testing whether it responds to commands.\r
+ // if (SD_CD_Read() == 1)\r
{\r
int retry;\r
blockDev.state = blockDev.state | DISK_PRESENT;\r
--- /dev/null
+// Copyright (C) 2014 Michael McMaster <michael@codesrc.com>
+//
+// This file is part of SCSI2SD.
+//
+// SCSI2SD is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// SCSI2SD is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with SCSI2SD. If not, see <http://www.gnu.org/licenses/>.
+
+#include "led.h"
+
+// External LED support only exists on the 3.5" v4 board.
+// The powerbook v4 board ties the pin to ground.
+// The v3 boards do not have any such pin.
+#ifdef EXTLED_CTL
+#define HAVE_EXTLED 1
+#endif
+
+#ifdef HAVE_EXTLED
+static int enable_EXTLED = 0;
+#endif
+
+void ledInit()
+{
+#ifdef HAVE_EXTLED
+ EXTLED_SetDriveMode(EXTLED_DM_DIG_HIZ | EXTLED_DM_RES_UP);
+ int val = EXTLED_Read();
+ if (val)
+ {
+ // Pin is not tied to ground, so it's safe to use.
+ enable_EXTLED = 1;
+ EXTLED_SetDriveMode(LED1_DM_STRONG);
+ }
+ else
+ {
+ // Pin is tied to ground. Using it would damage hardware
+ // This is the case for the powerbook boards.
+ enable_EXTLED = 0;
+ EXTLED_SetDriveMode(EXTLED_DM_DIG_HIZ);
+
+ }
+#endif
+ ledOff();
+}
+
+void ledOn()
+{
+ LED1_Write(0);
+
+#ifdef HAVE_EXTLED
+ if (enable_EXTLED)
+ {
+ EXTLED_Write(1);
+ }
+#endif
+}
+
+void ledOff()
+{
+ LED1_Write(1);
+
+#ifdef HAVE_EXTLED
+ if (enable_EXTLED)
+ {
+ EXTLED_Write(0);
+ }
+#endif
+}
+
#include "device.h"
-#define ledOn() LED1_Write(0)
-#define ledOff() LED1_Write(1)
+void ledInit(void);
+void ledOn(void);
+void ledOff(void);
#endif
\r
int main()\r
{\r
- ledOff();\r
+ ledInit();\r
\r
// Enable global interrupts.\r
// Needed for RST and ATN interrupt handlers.\r
scsiInit();\r
scsiDiskInit();\r
\r
- if (!(blockDev.state & DISK_INITIALISED))\r
- {\r
- while (1) { ledOn();CyDelay(200); ledOff();CyDelay(200); }\r
-\r
- }\r
-\r
while (1)\r
{\r
-#ifdef MM_DEBUG\r
scsiDev.watchdogTick++;\r
-#endif\r
+\r
scsiPoll();\r
scsiDiskPoll();\r
configPoll();\r
scsiDev.status = status;\r
scsiDev.phase = STATUS;\r
\r
-\r
- #ifdef MM_DEBUG\r
scsiDev.lastStatus = scsiDev.status;\r
scsiDev.lastSense = scsiDev.sense.code;\r
- #endif\r
-}\r
-\r
-static void doReselectTest()\r
-{\r
- scsiDev.needReconnect = 0;\r
- scsiEnterPhase(MESSAGE_IN);\r
- scsiWriteByte(0x02); // save data pointer\r
-\r
- // TODO check if this message was rejected.\r
-\r
- scsiWriteByte(0x04); // disconnect msg.\r
- enter_BusFree();\r
- \r
- CyDelay(100);\r
-\r
- while (1)\r
- {\r
- int sel = SCSI_ReadPin(SCSI_In_SEL);\r
- int bsy = SCSI_ReadPin(SCSI_In_BSY);\r
- if (!sel && !bsy)\r
- {\r
- // TODO wait bus settle delay\r
- CyDelayUs(1); // TODO bus free delay 800ns\r
- \r
- // Arbitrate.\r
- ledOn();\r
- SCSI_Out_Bits_Write(scsiDev.scsiIdMask);\r
- SCSI_Out_Ctl_Write(1); // Write bits manually.\r
- SCSI_SetPin(SCSI_Out_BSY);\r
- \r
- CyDelayUs(3); // arbitrate delay. 2.4us.\r
- \r
- uint8_t dbx = scsiReadDBxPins();\r
- sel = SCSI_ReadPin(SCSI_In_SEL);\r
- if (sel || ((dbx ^ scsiDev.scsiIdMask) > scsiDev.scsiIdMask))\r
- {\r
- // Lost arbitration.\r
- SCSI_Out_Ctl_Write(0);\r
- SCSI_ClearPin(SCSI_Out_BSY);\r
- ledOff();\r
- }\r
- else\r
- {\r
- // Won arbitration \r
- SCSI_SetPin(SCSI_Out_SEL);\r
- CyDelayUs(1); // Bus clear + Bus settle.\r
-\r
- // Reselection phase\r
- scsiEnterPhase(__scsiphase_io); // TODO get rid of delay\r
- SCSI_Out_Bits_Write(scsiDev.scsiIdMask | (1 << scsiDev.initiatorId));\r
- CyDelayCycles(4); // 2 deskew delays\r
- SCSI_ClearPin(SCSI_Out_BSY);\r
- CyDelayUs(1); // Bus Settle Delay\r
-\r
- bsy = SCSI_ReadPin(SCSI_In_BSY);\r
- while (!bsy) { bsy = SCSI_ReadPin(SCSI_In_BSY); } // Wait for initiator.\r
- SCSI_SetPin(SCSI_Out_BSY);\r
-\r
- // Prepare for the initial IDENTIFY message.\r
- scsiEnterPhase(MESSAGE_IN);\r
-\r
- SCSI_Out_Ctl_Write(0);\r
- SCSI_ClearPin(SCSI_Out_SEL);\r
-\r
- // Send identify command\r
- scsiWriteByte(0x80);\r
- break;\r
- }\r
- }\r
-\r
- }\r
-\r
- // Continue with status.\r
- \r
}\r
\r
static void process_Status()\r
{\r
- if (scsiDev.status == GOOD && scsiDev.needReconnect && scsiDev.allowDisconnect)\r
- {\r
- // doReselectTest();\r
- }\r
scsiEnterPhase(STATUS);\r
\r
uint8 message;\r
}\r
scsiWriteByte(scsiDev.status);\r
\r
- #ifdef MM_DEBUG\r
scsiDev.lastStatus = scsiDev.status;\r
scsiDev.lastSense = scsiDev.sense.code;\r
- #endif\r
\r
// Command Complete occurs AFTER a valid status has been\r
// sent. then we go bus-free.\r
lun = scsiDev.cdb[1] >> 5;\r
control = scsiDev.cdb[scsiDev.cdbLen - 1];\r
\r
- #ifdef MM_DEBUG\r
scsiDev.cmdCount++;\r
- #endif\r
\r
if (scsiDev.resetFlag)\r
{\r
-#ifdef MM_DEBUG\r
// Don't log bogus commands\r
scsiDev.cmdCount--;\r
memset(scsiDev.cdb, 0xff, sizeof(scsiDev.cdb));\r
-#endif\r
return;\r
}\r
else if (scsiDev.parityError)\r
\r
static void scsiReset()\r
{\r
-#ifdef MM_DEBUG\r
scsiDev.rstCount++;\r
-#endif\r
ledOff();\r
\r
scsiPhyReset();\r
scsiDev.phase = BUS_FREE;\r
scsiDev.atnFlag = 0;\r
scsiDev.resetFlag = 0;\r
- scsiDev.needReconnect = 0;\r
\r
if (scsiDev.unitAttention != POWER_ON_RESET)\r
{\r
scsiDev.dataLen = 0;\r
scsiDev.status = GOOD;\r
scsiDev.phase = SELECTION;\r
- scsiDev.needReconnect = 0;\r
- scsiDev.allowDisconnect = 0;\r
\r
transfer.blocks = 0;\r
transfer.currentBlock = 0;\r
SCSI_SetPin(SCSI_Out_BSY);\r
ledOn();\r
\r
- #ifdef MM_DEBUG\r
scsiDev.selCount++;\r
- #endif\r
\r
// Wait until the end of the selection phase.\r
while (!scsiDev.resetFlag)\r
scsiDev.atnFlag = 0;\r
scsiDev.parityError = 0;\r
scsiDev.msgOut = scsiReadByte();\r
-#ifdef MM_DEBUG\r
scsiDev.msgCount++;\r
-#endif\r
\r
if (scsiDev.parityError)\r
{\r
//enter_Status(CHECK_CONDITION);\r
messageReject();\r
}\r
- scsiDev.allowDisconnect = scsiDev.msgOut & 0x40;\r
+ //scsiDev.allowDisconnect = scsiDev.msgOut & 0x40;\r
}\r
else if (scsiDev.msgOut >= 0x20 && scsiDev.msgOut <= 0x2F)\r
{\r
#ifndef SCSI_H
#define SCSI_H
-// Set this to true to log SCSI commands and status information via
-// USB HID packets. The can be captured and viewed in wireshark.
-// For windows users, capture using USBPcap http://desowin.org/usbpcap/
-//#define MM_DEBUG 1
-#undef MM_DEBUG
-
#include "geometry.h"
#include "sense.h"
void (*postDataOutHook)(void);
-#ifdef MM_DEBUG
uint8 cmdCount;
uint8 selCount;
uint8 rstCount;
uint8 watchdogTick;
uint8 lastStatus;
uint8 lastSense;
-#endif
-
-uint8 allowDisconnect;
-uint8 needReconnect;
} ScsiDevice;
extern ScsiDevice scsiDev;
/* bMaxPacketSize0 */ 0x08u,\r
/* idVendor */ 0xB4u, 0x04u,\r
/* idProduct */ 0x37u, 0x13u,\r
-/* bcdDevice */ 0x00u, 0x30u,\r
+/* bcdDevice */ 0x01u, 0x30u,\r
/* iManufacturer */ 0x02u,\r
/* iProduct */ 0x01u,\r
/* iSerialNumber */ 0x80u,\r
0xFFu, 0xF7u, 0xD4u, 0xFDu, 0x21u, 0x78u, 0x01u, 0xF0u,\r
0xC0u, 0x02u, 0x40u, 0x2Au, 0x00u, 0xD0u, 0x18u, 0xB1u,\r
0x00u, 0x20u, 0x20u, 0x70u, 0xFFu, 0xF7u, 0x0Cu, 0xFEu,\r
- 0x14u, 0x20u, 0xFFu, 0xF7u, 0x09u, 0xFEu, 0x80u, 0x20u,\r
+ 0x05u, 0x20u, 0xFFu, 0xF7u, 0x09u, 0xFEu, 0x80u, 0x20u,\r
0x20u, 0x70u, 0x00u, 0xF0u, 0xE7u, 0xF8u, 0x48u, 0xB0u,\r
0x10u, 0xBDu, 0x00u, 0xBFu, 0x0Cu, 0xC1u, 0xFFu, 0x1Fu,\r
0xFAu, 0x46u, 0x00u, 0x40u, 0x08u, 0xB5u, 0x0Au, 0x4Bu,\r
0x10u, 0xBDu, 0x82u, 0x18u, 0x03u, 0x46u, 0x93u, 0x42u,\r
0x02u, 0xD0u, 0x03u, 0xF8u, 0x01u, 0x1Bu, 0xFAu, 0xE7u,\r
0x70u, 0x47u, 0x00u, 0x00u, 0x80u, 0x22u, 0x00u, 0x00u,\r
- 0x40u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,\r
+ 0x4Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,\r
0x10u, 0x51u, 0x00u, 0x40u, 0x20u, 0x00u, 0x50u, 0x51u,\r
0x00u, 0x40u, 0x10u, 0x00u, 0xC0u, 0x51u, 0x00u, 0x40u,\r
0x10u, 0x00u, 0x00u, 0x00u, 0x01u, 0x40u, 0x00u, 0x10u,\r
const uint8 cy_meta_loadable[] = {\r
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,\r
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,\r
- 0x00u, 0x00u, 0x00u, 0x00u, 0x5Cu, 0xD1u, 0x01u, 0x00u,\r
+ 0x00u, 0x00u, 0x00u, 0x00u, 0x5Cu, 0xD1u, 0x50u, 0x03u,\r
0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,\r
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,\r
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,\r
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+<file name=".\CortexM3\ARM_GCC_473\Release\USBFS_pm.o">\r
+<dep name=".\Generated_Source\PSoC5\BL.h" />\r
+<dep name=".\Generated_Source\PSoC5\BL_PVT.h" />\r
+<dep name=".\Generated_Source\PSoC5\CyDmac.h" />\r
+<dep name=".\Generated_Source\PSoC5\CyFlash.h" />\r
+<dep name=".\Generated_Source\PSoC5\CyLib.h" />\r
+<dep name=".\Generated_Source\PSoC5\CySpc.h" />\r
+<dep name=".\Generated_Source\PSoC5\SCSI_Out_DBx_aliases.h" />\r
+<dep name=".\Generated_Source\PSoC5\SCSI_Out_aliases.h" />\r
+<dep name=".\Generated_Source\PSoC5\SD_PULLUP.h" />\r
+<dep name=".\Generated_Source\PSoC5\SD_PULLUP_aliases.h" />\r
+<dep name=".\Generated_Source\PSoC5\USBFS.h" />\r
+<dep name=".\Generated_Source\PSoC5\USBFS_Dm.h" />\r
+<dep name=".\Generated_Source\PSoC5\USBFS_Dm_aliases.h" />\r
+<dep name=".\Generated_Source\PSoC5\USBFS_Dp.h" />\r
+<dep name=".\Generated_Source\PSoC5\USBFS_Dp_aliases.h" />\r
+<dep name=".\Generated_Source\PSoC5\USBFS_audio.h" />\r
+<dep name=".\Generated_Source\PSoC5\USBFS_cdc.h" />\r
+<dep name=".\Generated_Source\PSoC5\USBFS_hid.h" />\r
+<dep name=".\Generated_Source\PSoC5\USBFS_midi.h" />\r
+<dep name=".\Generated_Source\PSoC5\USBFS_pvt.h" />\r
+<dep name=".\Generated_Source\PSoC5\core_cm3.h" />\r
+<dep name=".\Generated_Source\PSoC5\core_cm3_psoc5.h" />\r
+<dep name=".\Generated_Source\PSoC5\core_cmFunc.h" />\r
+<dep name=".\Generated_Source\PSoC5\core_cmInstr.h" />\r
+<dep name=".\Generated_Source\PSoC5\cyPm.h" />\r
+<dep name=".\Generated_Source\PSoC5\cydevice.h" />\r
+<dep name=".\Generated_Source\PSoC5\cydevice_trm.h" />\r
+<dep name=".\Generated_Source\PSoC5\cydisabledsheets.h" />\r
+<dep name=".\Generated_Source\PSoC5\cyfitter.h" />\r
+<dep name=".\Generated_Source\PSoC5\cyfitter_cfg.h" />\r
+<dep name=".\Generated_Source\PSoC5\cypins.h" />\r
+<dep name=".\Generated_Source\PSoC5\cytypes.h" />\r
+<dep name=".\Generated_Source\PSoC5\project.h" />\r
+<dep name=".\Generated_Source\PSoC5\USBFS_pm.c" />\r
+</file>\r
+<file name=".\Generated_Source\PSoC5\USBFS_pm.c" />\r
<file name=".\CortexM3\ARM_GCC_473\Release\Cm3Start.o">\r
<dep name=".\Generated_Source\PSoC5\CyDmac.h" />\r
<dep name=".\Generated_Source\PSoC5\CyFlash.h" />\r
<dep name=".\Generated_Source\PSoC5\USBFS_midi.c" />\r
</file>\r
<file name=".\Generated_Source\PSoC5\USBFS_midi.c" />\r
-<file name=".\CortexM3\ARM_GCC_473\Release\USBFS_pm.o">\r
-<dep name=".\Generated_Source\PSoC5\BL.h" />\r
-<dep name=".\Generated_Source\PSoC5\BL_PVT.h" />\r
-<dep name=".\Generated_Source\PSoC5\CyDmac.h" />\r
-<dep name=".\Generated_Source\PSoC5\CyFlash.h" />\r
-<dep name=".\Generated_Source\PSoC5\CyLib.h" />\r
-<dep name=".\Generated_Source\PSoC5\CySpc.h" />\r
-<dep name=".\Generated_Source\PSoC5\SCSI_Out_DBx_aliases.h" />\r
-<dep name=".\Generated_Source\PSoC5\SCSI_Out_aliases.h" />\r
-<dep name=".\Generated_Source\PSoC5\SD_PULLUP.h" />\r
-<dep name=".\Generated_Source\PSoC5\SD_PULLUP_aliases.h" />\r
-<dep name=".\Generated_Source\PSoC5\USBFS.h" />\r
-<dep name=".\Generated_Source\PSoC5\USBFS_Dm.h" />\r
-<dep name=".\Generated_Source\PSoC5\USBFS_Dm_aliases.h" />\r
-<dep name=".\Generated_Source\PSoC5\USBFS_Dp.h" />\r
-<dep name=".\Generated_Source\PSoC5\USBFS_Dp_aliases.h" />\r
-<dep name=".\Generated_Source\PSoC5\USBFS_audio.h" />\r
-<dep name=".\Generated_Source\PSoC5\USBFS_cdc.h" />\r
-<dep name=".\Generated_Source\PSoC5\USBFS_hid.h" />\r
-<dep name=".\Generated_Source\PSoC5\USBFS_midi.h" />\r
-<dep name=".\Generated_Source\PSoC5\USBFS_pvt.h" />\r
-<dep name=".\Generated_Source\PSoC5\core_cm3.h" />\r
-<dep name=".\Generated_Source\PSoC5\core_cm3_psoc5.h" />\r
-<dep name=".\Generated_Source\PSoC5\core_cmFunc.h" />\r
-<dep name=".\Generated_Source\PSoC5\core_cmInstr.h" />\r
-<dep name=".\Generated_Source\PSoC5\cyPm.h" />\r
-<dep name=".\Generated_Source\PSoC5\cydevice.h" />\r
-<dep name=".\Generated_Source\PSoC5\cydevice_trm.h" />\r
-<dep name=".\Generated_Source\PSoC5\cydisabledsheets.h" />\r
-<dep name=".\Generated_Source\PSoC5\cyfitter.h" />\r
-<dep name=".\Generated_Source\PSoC5\cyfitter_cfg.h" />\r
-<dep name=".\Generated_Source\PSoC5\cypins.h" />\r
-<dep name=".\Generated_Source\PSoC5\cytypes.h" />\r
-<dep name=".\Generated_Source\PSoC5\project.h" />\r
-<dep name=".\Generated_Source\PSoC5\USBFS_pm.c" />\r
-</file>\r
-<file name=".\Generated_Source\PSoC5\USBFS_pm.c" />\r
<file name=".\CortexM3\ARM_GCC_473\Release\USBFS_std.o">\r
<dep name=".\Generated_Source\PSoC5\CyDmac.h" />\r
<dep name=".\Generated_Source\PSoC5\CyFlash.h" />\r
<name_val_pair name=".\Generated_Source\PSoC5\SD_PULLUP.c" v=""-I. ""-I./Generated_Source/PSoC5 ""-Wno-main ""-mcpu=cortex-m3 ""-mthumb ""-Wall ""-g ""-D ""NDEBUG ""-Wa,-alh=${OutputDir}\${CompileFile}.lst ""-Os ""-ffunction-sections "" />\r
<name_val_pair name="W:\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn\CortexM3\ARM_GCC_473\Release\USB_Bootloader.hex" v=""-mthumb ""-march=armv7-m ""-mfix-cortex-m3-ldrd ""-T "".\Generated_Source\PSoC5\cm3gcc.ld ""-g ""-Wl,-Map,${OutputDir}\${ProjectShortName}.map ""-specs=nano.specs ""-Wl,--gc-sections "" />\r
<name_val_pair name="Z:\projects\SCSI2SD\git-3.4_debug\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn\CortexM3\ARM_GCC_473\Release\USB_Bootloader.hex" v=""-mthumb ""-march=armv7-m ""-mfix-cortex-m3-ldrd ""-T "".\Generated_Source\PSoC5\cm3gcc.ld ""-g ""-Wl,-Map,${OutputDir}\${ProjectShortName}.map ""-specs=nano.specs ""-Wl,--gc-sections "" />\r
+<name_val_pair name="Z:\projects\SCSI2SD\git-3.5\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn\CortexM3\ARM_GCC_473\Release\USB_Bootloader.hex" v=""-mthumb ""-march=armv7-m ""-mfix-cortex-m3-ldrd ""-T "".\Generated_Source\PSoC5\cm3gcc.ld ""-g ""-Wl,-Map,${OutputDir}\${ProjectShortName}.map ""-specs=nano.specs ""-Wl,--gc-sections "" />\r
+<name_val_pair name="Z:\projects\SCSI2SD\git-3.5\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn\CortexM3\ARM_GCC_473\Release\USB_Bootloader.hex" v=""-mthumb ""-march=armv7-m ""-mfix-cortex-m3-ldrd ""-T "".\Generated_Source\PSoC5\cm3gcc.ld ""-g ""-Wl,-Map,${OutputDir}\${ProjectShortName}.map ""-specs=nano.specs ""-Wl,--gc-sections "" />\r
</name>\r
<name v="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3">\r
<name_val_pair name=".\main.c" v=""-I. ""-I./Generated_Source/PSoC5 ""-Wno-main ""-mcpu=cortex-m3 ""-mthumb ""-Wall ""-g ""-D ""DEBUG ""-Wa,-alh=${OutputDir}\${CompileFile}.lst ""-ffunction-sections "" />\r
<name_val_pair name="W:\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn\CortexM3\ARM_GCC_473\Debug\USB_Bootloader.hex" v=""-mthumb ""-march=armv7-m ""-mfix-cortex-m3-ldrd ""-T "".\Generated_Source\PSoC5\cm3gcc.ld ""-g ""-Wl,-Map,${OutputDir}\${ProjectShortName}.map ""-specs=nano.specs ""-Wl,--gc-sections "" />\r
</name>\r
</genericCmdLineData>\r
-<codeGenCmdLineTag v=""-.appdatapath" "C:\Users\Micha_000\AppData\Local\Cypress Semiconductor\PSoC Creator\3.0" "-.fdsnotice" "-.fdswarpdepfile=warp_dependencies.txt" "-.fdselabdepfile=elab_dependencies.txt" "-.fdsbldfile=generated_files.txt" "-p" "Z:\projects\SCSI2SD\git-3.4_debug\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn\USB_Bootloader.cyprj" "-d" "CY8C5267AXI-LP051" "-s" "Z:\projects\SCSI2SD\git-3.4_debug\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn\Generated_Source\PSoC5" "--" "-yv2" "-v3" "-ygs" "-q10" "-o2" "-.fftcfgtype=LE" " />\r
+<codeGenCmdLineTag v=""-.appdatapath" "C:\Users\Micha_000\AppData\Local\Cypress Semiconductor\PSoC Creator\3.0" "-.fdsnotice" "-.fdswarpdepfile=warp_dependencies.txt" "-.fdselabdepfile=elab_dependencies.txt" "-.fdsbldfile=generated_files.txt" "-p" "Z:\projects\SCSI2SD\git-3.5\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn\USB_Bootloader.cyprj" "-d" "CY8C5267AXI-LP051" "-s" "Z:\projects\SCSI2SD\git-3.5\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn\Generated_Source\PSoC5" "--" "-yv2" "-v3" "-ygs" "-q10" "-o2" "-.fftcfgtype=LE" " />\r
</CyGuid_b0374e30-ce3a-47f2-ad85-821643292c68>\r
</dataGuid>\r
<dataGuid v="597c5b74-0c46-4204-8b7f-96f3570671dc">\r
<v>Cypress Component Catalog\System</v>\r
</ExpandedNodeIds>\r
<VisibleNodeIds>\r
+<v>Cypress Component Catalog\Digital\Functions\CRC [v2.40]</v>\r
+<v>Cypress Component Catalog\Digital\Functions\PrISM [v2.20]</v>\r
+<v>Cypress Component Catalog\Digital\Functions\PRS [v2.40]</v>\r
+<v>Cypress Component Catalog\Digital\Functions\PWM [v3.0]</v>\r
+<v>Cypress Component Catalog\Digital\Functions\Quadrature Decoder [v2.30]</v>\r
+<v>Cypress Component Catalog\Digital\Functions\Shift Register [v2.30]</v>\r
+<v>Cypress Component Catalog\Digital\Functions\Timer [v2.50]</v>\r
+<v>Cypress Component Catalog\Digital\Logic</v>\r
+<v>Cypress Component Catalog\Digital\Registers</v>\r
+<v>Cypress Component Catalog\Digital\Utility</v>\r
+<v>Cypress Component Catalog\Display</v>\r
+<v>Cypress Component Catalog\Filters</v>\r
+<v>Cypress Component Catalog\Ports and Pins</v>\r
+<v>Cypress Component Catalog\Ports and Pins\Analog Pin [v1.90]</v>\r
<v>Cypress Component Catalog\Ports and Pins\Digital Bidirectional Pin [v1.90]</v>\r
<v>Cypress Component Catalog\Ports and Pins\Digital Input Pin [v1.90]</v>\r
<v>Cypress Component Catalog\Ports and Pins\Digital Output Pin [v1.90]</v>\r
<v>Cypress Component Catalog\Power Supervision</v>\r
<v>Cypress Component Catalog\System</v>\r
<v>Cypress Component Catalog\System\Boost Converter [v5.0]</v>\r
-<v>Cypress Component Catalog\System\Bootloadable [v1.20]</v>\r
-<v>Cypress Component Catalog\System\Bootloader [v1.20]</v>\r
-<v>Cypress Component Catalog\System\Clock [v2.10]</v>\r
-<v>Cypress Component Catalog\System\Die Temperature [v2.0]</v>\r
-<v>Cypress Component Catalog\System\DMA [v1.70]</v>\r
-<v>Cypress Component Catalog\System\EEPROM [v2.10]</v>\r
-<v>Cypress Component Catalog\System\Emulated EEPROM [v1.10]</v>\r
-<v>Cypress Component Catalog\System\External Memory Interface</v>\r
-<v>Cypress Component Catalog\System\Global Signal Reference [v2.0]</v>\r
-<v>Cypress Component Catalog\System\ILO Trim [v1.0]</v>\r
-<v>Cypress Component Catalog\System\Interrupt [v1.70]</v>\r
-<v>Cypress Component Catalog\System\RTC [v2.0]</v>\r
-<v>Cypress Component Catalog\System\SleepTimer [v3.20]</v>\r
-<v>Cypress Component Catalog\Thermal Management</v>\r
</VisibleNodeIds>\r
</CyGuid_2a325b3b-c96a-4e9f-b7a0-2c44ecb5f237>\r
<CyGuid_2a325b3b-c96a-4e9f-b7a0-2c44ecb5f237 type_name="CyDesigner.Common.Base.Controls.CyTreeViewState" version="1" SelectedNodeId="">\r
<v>C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\stdlogic\mod_genv.vif</v>\r
<v>C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\stdlogic\rtlpkg.vif</v>\r
</warp_dep>\r
-<deps_time v="130450587785176249" />\r
+<deps_time v="130495593784227004" />\r
<top_block v="TopDesign" />\r
<last_generation v="0" />\r
</CyGuid_925cc1e1-309e-4e08-b0a1-09a83c35b157>\r
</dataGuid>\r
<dataGuid v="769d31ea-68b1-4f0c-b90a-7c10a43ee563">\r
<CyGuid_769d31ea-68b1-4f0c-b90a-7c10a43ee563 type_name="CyDesigner.Common.ProjMgmt.Model.CyLinkCustomData" version="1">\r
-<deps_time v="130450588791286055" />\r
+<deps_time v="130495594117493903" />\r
</CyGuid_769d31ea-68b1-4f0c-b90a-7c10a43ee563>\r
</dataGuid>\r
<dataGuid v="bf610382-39c6-441f-80b8-b04622ea7845">\r
-Loading plugins phase: Elapsed time ==> 1s.508ms\r
-Initializing data phase: Elapsed time ==> 9s.403ms\r
+Loading plugins phase: Elapsed time ==> 0s.663ms\r
+Initializing data phase: Elapsed time ==> 5s.693ms\r
<CYPRESSTAG name="CyDsfit arguments...">\r
-cydsfit arguments: -.fdsnotice -.fdswarpdepfile=warp_dependencies.txt -.fdselabdepfile=elab_dependencies.txt -.fdsbldfile=generated_files.txt -p Z:\projects\SCSI2SD\git-3.4_debug\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn\USB_Bootloader.cyprj -d CY8C5267AXI-LP051 -s Z:\projects\SCSI2SD\git-3.4_debug\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn\Generated_Source\PSoC5 -- -yv2 -v3 -ygs -q10 -o2 -.fftcfgtype=LE</CYPRESSTAG>\r
+cydsfit arguments: -.fdsnotice -.fdswarpdepfile=warp_dependencies.txt -.fdselabdepfile=elab_dependencies.txt -.fdsbldfile=generated_files.txt -p Z:\projects\SCSI2SD\git-3.5\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn\USB_Bootloader.cyprj -d CY8C5267AXI-LP051 -s Z:\projects\SCSI2SD\git-3.5\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn\Generated_Source\PSoC5 -- -yv2 -v3 -ygs -q10 -o2 -.fftcfgtype=LE</CYPRESSTAG>\r
<CYPRESSTAG name="Design elaboration results...">\r
</CYPRESSTAG>\r
-Elaboration phase: Elapsed time ==> 9s.079ms\r
+Elaboration phase: Elapsed time ==> 9s.252ms\r
<CYPRESSTAG name="HDL generation results...">\r
</CYPRESSTAG>\r
-HDL generation phase: Elapsed time ==> 0s.906ms\r
+HDL generation phase: Elapsed time ==> 0s.756ms\r
<CYPRESSTAG name="Synthesis results...">\r
\r
| | | | | | |\r
======================================================================\r
Compiling: USB_Bootloader.v\r
Program : C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\bin/warp.exe\r
-Options : -yv2 -v3 -ygs -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=Z:\projects\SCSI2SD\git-3.4_debug\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn\USB_Bootloader.cyprj -dcpsoc3 USB_Bootloader.v -verilog\r
+Options : -yv2 -v3 -ygs -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=Z:\projects\SCSI2SD\git-3.5\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn\USB_Bootloader.cyprj -dcpsoc3 USB_Bootloader.v -verilog\r
======================================================================\r
\r
======================================================================\r
Compiling: USB_Bootloader.v\r
Program : C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\bin/warp.exe\r
-Options : -yv2 -v3 -ygs -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=Z:\projects\SCSI2SD\git-3.4_debug\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn\USB_Bootloader.cyprj -dcpsoc3 USB_Bootloader.v -verilog\r
+Options : -yv2 -v3 -ygs -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=Z:\projects\SCSI2SD\git-3.5\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn\USB_Bootloader.cyprj -dcpsoc3 USB_Bootloader.v -verilog\r
======================================================================\r
\r
======================================================================\r
Compiling: USB_Bootloader.v\r
Program : vlogfe\r
-Options : -yv2 -v3 -ygs -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=Z:\projects\SCSI2SD\git-3.4_debug\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn\USB_Bootloader.cyprj -dcpsoc3 -verilog USB_Bootloader.v\r
+Options : -yv2 -v3 -ygs -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=Z:\projects\SCSI2SD\git-3.5\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn\USB_Bootloader.cyprj -dcpsoc3 -verilog USB_Bootloader.v\r
======================================================================\r
\r
vlogfe V6.3 IR 41: Verilog parser\r
-Tue May 20 21:24:38 2014\r
+Fri Jul 11 23:34:40 2014\r
\r
\r
======================================================================\r
======================================================================\r
\r
vpp V6.3 IR 41: Verilog Pre-Processor\r
-Tue May 20 21:24:39 2014\r
+Fri Jul 11 23:34:40 2014\r
\r
\r
vpp: No errors.\r
======================================================================\r
Compiling: USB_Bootloader.v\r
Program : tovif\r
-Options : -yv2 -v3 -ygs -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=Z:\projects\SCSI2SD\git-3.4_debug\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn\USB_Bootloader.cyprj -dcpsoc3 -verilog USB_Bootloader.v\r
+Options : -yv2 -v3 -ygs -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=Z:\projects\SCSI2SD\git-3.5\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn\USB_Bootloader.cyprj -dcpsoc3 -verilog USB_Bootloader.v\r
======================================================================\r
\r
tovif V6.3 IR 41: High-level synthesis\r
-Tue May 20 21:24:41 2014\r
+Fri Jul 11 23:34:41 2014\r
\r
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\std.vhd'.\r
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\cypress.vhd'.\r
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\stdlogic\mod_cnst.vif'.\r
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\stdlogic\mod_mthv.vif'.\r
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\stdlogic\mod_genv.vif'.\r
-Linking 'Z:\projects\SCSI2SD\git-3.4_debug\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn\codegentemp\USB_Bootloader.ctl'.\r
-Linking 'Z:\projects\SCSI2SD\git-3.4_debug\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn\codegentemp\USB_Bootloader.v'.\r
+Linking 'Z:\projects\SCSI2SD\git-3.5\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn\codegentemp\USB_Bootloader.ctl'.\r
+Linking 'Z:\projects\SCSI2SD\git-3.5\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn\codegentemp\USB_Bootloader.v'.\r
\r
tovif: No errors.\r
\r
======================================================================\r
Compiling: USB_Bootloader.v\r
Program : topld\r
-Options : -yv2 -v3 -ygs -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=Z:\projects\SCSI2SD\git-3.4_debug\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn\USB_Bootloader.cyprj -dcpsoc3 -verilog USB_Bootloader.v\r
+Options : -yv2 -v3 -ygs -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=Z:\projects\SCSI2SD\git-3.5\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn\USB_Bootloader.cyprj -dcpsoc3 -verilog USB_Bootloader.v\r
======================================================================\r
\r
topld V6.3 IR 41: Synthesis and optimization\r
-Tue May 20 21:24:44 2014\r
+Fri Jul 11 23:34:43 2014\r
\r
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\std.vhd'.\r
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\cypress.vhd'.\r
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\stdlogic\mod_cnst.vif'.\r
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\stdlogic\mod_mthv.vif'.\r
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\stdlogic\mod_genv.vif'.\r
-Linking 'Z:\projects\SCSI2SD\git-3.4_debug\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn\codegentemp\USB_Bootloader.ctl'.\r
-Linking 'Z:\projects\SCSI2SD\git-3.4_debug\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn\codegentemp\USB_Bootloader.v'.\r
+Linking 'Z:\projects\SCSI2SD\git-3.5\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn\codegentemp\USB_Bootloader.ctl'.\r
+Linking 'Z:\projects\SCSI2SD\git-3.5\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn\codegentemp\USB_Bootloader.v'.\r
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\lcpsoc3\stdlogic\cpsoc3.vif'.\r
\r
----------------------------------------------------------\r
\r
CYPRESS_DIR : C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\r
Warp Program : C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\bin/warp.exe\r
-Warp Arguments : -yv2 -v3 -ygs -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=Z:\projects\SCSI2SD\git-3.4_debug\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn\USB_Bootloader.cyprj -dcpsoc3 USB_Bootloader.v -verilog\r
+Warp Arguments : -yv2 -v3 -ygs -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=Z:\projects\SCSI2SD\git-3.5\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn\USB_Bootloader.cyprj -dcpsoc3 USB_Bootloader.v -verilog\r
</CYPRESSTAG>\r
-Warp synthesis phase: Elapsed time ==> 9s.267ms\r
+Warp synthesis phase: Elapsed time ==> 9s.922ms\r
<CYPRESSTAG name="Fitter results...">\r
<CYPRESSTAG name="Fitter startup details...">\r
-cyp3fit: V3.0.0.1539, Family: PSoC3, Started at: Tuesday, 20 May 2014 21:24:47\r
-Options: -yv2 -v3 -ygs -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=Z:\projects\SCSI2SD\git-3.4_debug\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn\USB_Bootloader.cyprj -d CY8C5267AXI-LP051 USB_Bootloader.v -verilog\r
+cyp3fit: V3.0.0.1539, Family: PSoC3, Started at: Friday, 11 July 2014 23:34:49\r
+Options: -yv2 -v3 -ygs -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=Z:\projects\SCSI2SD\git-3.5\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn\USB_Bootloader.cyprj -d CY8C5267AXI-LP051 USB_Bootloader.v -verilog\r
</CYPRESSTAG>\r
<CYPRESSTAG name="Design parsing">\r
-Design parsing phase: Elapsed time ==> 0s.046ms\r
+Design parsing phase: Elapsed time ==> 0s.152ms\r
</CYPRESSTAG>\r
<CYPRESSTAG name="Tech mapping">\r
<CYPRESSTAG name="Initial Mapping" icon="FILE_RPT_TECHM">\r
LPF Fixed Blocks : 0 : 2 : 2 : 0.00%\r
SAR Fixed Blocks : 0 : 1 : 1 : 0.00%\r
</CYPRESSTAG>\r
-Technology Mapping: Elapsed time ==> 0s.437ms\r
-Tech mapping phase: Elapsed time ==> 0s.672ms\r
+Technology Mapping: Elapsed time ==> 0s.414ms\r
+Tech mapping phase: Elapsed time ==> 0s.690ms\r
</CYPRESSTAG>\r
<CYPRESSTAG name="Analog Placement">\r
Initial Analog Placement Results:\r
IO_7@[IOP=(15)][IoId=(7)] : \USBFS:Dm(0)\ (fixed)\r
IO_6@[IOP=(15)][IoId=(6)] : \USBFS:Dp(0)\ (fixed)\r
USB[0]@[FFB(USB,0)] : \USBFS:USB\\r
-Analog Placement phase: Elapsed time ==> 0s.078ms\r
+Analog Placement phase: Elapsed time ==> 0s.169ms\r
</CYPRESSTAG>\r
<CYPRESSTAG name="Analog Routing">\r
-Analog Routing phase: Elapsed time ==> 0s.000ms\r
+Analog Routing phase: Elapsed time ==> 0s.001ms\r
</CYPRESSTAG>\r
<CYPRESSTAG name="Analog Code Generation">\r
============ Analog Final Answer Routes ============\r
IsVddaHalfUsedForComp = False\r
IsVddaHalfUsedForSar0 = False\r
IsVddaHalfUsedForSar1 = False\r
-Analog Code Generation phase: Elapsed time ==> 1s.828ms\r
+Analog Code Generation phase: Elapsed time ==> 1s.579ms\r
</CYPRESSTAG>\r
<CYPRESSTAG name="Digital Placement">\r
<CYPRESSTAG name="Detailed placement messages">\r
I2659: No Constrained paths were found. The placer will run in non-timing driven mode.\r
-I2076: Total run-time: 3.9 sec.\r
+I2076: Total run-time: 5.4 sec.\r
\r
</CYPRESSTAG>\r
<CYPRESSTAG name="PLD Packing">\r
<CYPRESSTAG name="PLD Packing Summary">\r
No PLDs were packed.\r
</CYPRESSTAG>\r
-PLD Packing: Elapsed time ==> 0s.000ms\r
+PLD Packing: Elapsed time ==> 0s.005ms\r
</CYPRESSTAG>\r
<CYPRESSTAG name="Partitioning">\r
<CYPRESSTAG name="Initial Partitioning Summary">\r
Initial Partitioning Summary not displayed at this verbose level.</CYPRESSTAG>\r
<CYPRESSTAG name="Final Partitioning Summary">\r
Final Partitioning Summary not displayed at this verbose level.</CYPRESSTAG>\r
-Partitioning: Elapsed time ==> 0s.077ms\r
+Partitioning: Elapsed time ==> 0s.088ms\r
</CYPRESSTAG>\r
<CYPRESSTAG name="Simulated Annealing">\r
-Annealing: Elapsed time ==> 0s.000ms\r
+Annealing: Elapsed time ==> 0s.003ms\r
<CYPRESSTAG name="Simulated Annealing Results">\r
The seed used for moves was 114161200.\r
Inital cost was 120, final cost is 120 (0.00% improvement).</CYPRESSTAG>\r
</CYPRESSTAG>\r
</CYPRESSTAG>\r
</CYPRESSTAG>\r
-Digital component placer commit/Report: Elapsed time ==> 0s.375ms\r
-Digital Placement phase: Elapsed time ==> 8s.689ms\r
+Digital component placer commit/Report: Elapsed time ==> 0s.381ms\r
+Digital Placement phase: Elapsed time ==> 9s.177ms\r
</CYPRESSTAG>\r
<CYPRESSTAG name="Digital Routing">\r
Routing successful.\r
-Digital Routing phase: Elapsed time ==> 6s.563ms\r
+Digital Routing phase: Elapsed time ==> 11s.165ms\r
</CYPRESSTAG>\r
<CYPRESSTAG name="Bitstream and API generation">\r
-Bitstream and API generation phase: Elapsed time ==> 26s.707ms\r
+Bitstream and API generation phase: Elapsed time ==> 25s.258ms\r
</CYPRESSTAG>\r
<CYPRESSTAG name="Bitstream verification">\r
-Bitstream verification phase: Elapsed time ==> 0s.140ms\r
+Bitstream verification phase: Elapsed time ==> 0s.188ms\r
</CYPRESSTAG>\r
<CYPRESSTAG name="Static timing analysis">\r
Timing report is in USB_Bootloader_timing.html.\r
-Static timing analysis phase: Elapsed time ==> 7s.016ms\r
+Static timing analysis phase: Elapsed time ==> 3s.834ms\r
</CYPRESSTAG>\r
<CYPRESSTAG name="Data reporting">\r
Data reporting phase: Elapsed time ==> 0s.000ms\r
</CYPRESSTAG>\r
<CYPRESSTAG name="Database update...">\r
-Design database save phase: Elapsed time ==> 0s.577ms\r
+Design database save phase: Elapsed time ==> 0s.664ms\r
</CYPRESSTAG>\r
-cydsfit: Elapsed time ==> 52s.696ms\r
+cydsfit: Elapsed time ==> 53s.302ms\r
</CYPRESSTAG>\r
-Fitter phase: Elapsed time ==> 52s.775ms\r
-API generation phase: Elapsed time ==> 25s.205ms\r
-Dependency generation phase: Elapsed time ==> 0s.796ms\r
-Cleanup phase: Elapsed time ==> 0s.750ms\r
+Fitter phase: Elapsed time ==> 53s.394ms\r
+API generation phase: Elapsed time ==> 23s.082ms\r
+Dependency generation phase: Elapsed time ==> 1s.067ms\r
+Cleanup phase: Elapsed time ==> 0s.811ms\r
<tr> <td class="prop"> Project :</td>\r
<td class="proptext"> USB_Bootloader</td></tr>\r
<tr> <td class="prop"> Build Time :</td>\r
-<td class="proptext"> 05/20/14 21:25:38</td></tr>\r
+<td class="proptext"> 07/11/14 23:35:41</td></tr>\r
<tr> <td class="prop"> Device :</td>\r
<td class="proptext"> CY8C5267AXI-LP051</td></tr>\r
<tr> <td class="prop"> Temperature :</td>\r
--- /dev/null
+/*******************************************************************************
+* File Name: EXTLED.c
+* Version 1.90
+*
+* Description:
+* This file contains API to enable firmware control of a Pins component.
+*
+* Note:
+*
+********************************************************************************
+* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions,
+* disclaimers, and limitations in the end user license agreement accompanying
+* the software package with which this file was provided.
+*******************************************************************************/
+
+#include "cytypes.h"
+#include "EXTLED.h"
+
+/* APIs are not generated for P15[7:6] on PSoC 5 */
+#if !(CY_PSOC5A &&\
+ EXTLED__PORT == 15 && ((EXTLED__MASK & 0xC0) != 0))
+
+
+/*******************************************************************************
+* Function Name: EXTLED_Write
+********************************************************************************
+*
+* Summary:
+* Assign a new value to the digital port's data output register.
+*
+* Parameters:
+* prtValue: The value to be assigned to the Digital Port.
+*
+* Return:
+* None
+*
+*******************************************************************************/
+void EXTLED_Write(uint8 value)
+{
+ uint8 staticBits = (EXTLED_DR & (uint8)(~EXTLED_MASK));
+ EXTLED_DR = staticBits | ((uint8)(value << EXTLED_SHIFT) & EXTLED_MASK);
+}
+
+
+/*******************************************************************************
+* Function Name: EXTLED_SetDriveMode
+********************************************************************************
+*
+* Summary:
+* Change the drive mode on the pins of the port.
+*
+* Parameters:
+* mode: Change the pins to this drive mode.
+*
+* Return:
+* None
+*
+*******************************************************************************/
+void EXTLED_SetDriveMode(uint8 mode)
+{
+ CyPins_SetPinDriveMode(EXTLED_0, mode);
+}
+
+
+/*******************************************************************************
+* Function Name: EXTLED_Read
+********************************************************************************
+*
+* Summary:
+* Read the current value on the pins of the Digital Port in right justified
+* form.
+*
+* Parameters:
+* None
+*
+* Return:
+* Returns the current value of the Digital Port as a right justified number
+*
+* Note:
+* Macro EXTLED_ReadPS calls this function.
+*
+*******************************************************************************/
+uint8 EXTLED_Read(void)
+{
+ return (EXTLED_PS & EXTLED_MASK) >> EXTLED_SHIFT;
+}
+
+
+/*******************************************************************************
+* Function Name: EXTLED_ReadDataReg
+********************************************************************************
+*
+* Summary:
+* Read the current value assigned to a Digital Port's data output register
+*
+* Parameters:
+* None
+*
+* Return:
+* Returns the current value assigned to the Digital Port's data output register
+*
+*******************************************************************************/
+uint8 EXTLED_ReadDataReg(void)
+{
+ return (EXTLED_DR & EXTLED_MASK) >> EXTLED_SHIFT;
+}
+
+
+/* If Interrupts Are Enabled for this Pins component */
+#if defined(EXTLED_INTSTAT)
+
+ /*******************************************************************************
+ * Function Name: EXTLED_ClearInterrupt
+ ********************************************************************************
+ * Summary:
+ * Clears any active interrupts attached to port and returns the value of the
+ * interrupt status register.
+ *
+ * Parameters:
+ * None
+ *
+ * Return:
+ * Returns the value of the interrupt status register
+ *
+ *******************************************************************************/
+ uint8 EXTLED_ClearInterrupt(void)
+ {
+ return (EXTLED_INTSTAT & EXTLED_MASK) >> EXTLED_SHIFT;
+ }
+
+#endif /* If Interrupts Are Enabled for this Pins component */
+
+#endif /* CY_PSOC5A... */
+
+
+/* [] END OF FILE */
--- /dev/null
+/*******************************************************************************
+* File Name: EXTLED.h
+* Version 1.90
+*
+* Description:
+* This file containts Control Register function prototypes and register defines
+*
+* Note:
+*
+********************************************************************************
+* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions,
+* disclaimers, and limitations in the end user license agreement accompanying
+* the software package with which this file was provided.
+*******************************************************************************/
+
+#if !defined(CY_PINS_EXTLED_H) /* Pins EXTLED_H */
+#define CY_PINS_EXTLED_H
+
+#include "cytypes.h"
+#include "cyfitter.h"
+#include "cypins.h"
+#include "EXTLED_aliases.h"
+
+/* Check to see if required defines such as CY_PSOC5A are available */
+/* They are defined starting with cy_boot v3.0 */
+#if !defined (CY_PSOC5A)
+ #error Component cy_pins_v1_90 requires cy_boot v3.0 or later
+#endif /* (CY_PSOC5A) */
+
+/* APIs are not generated for P15[7:6] */
+#if !(CY_PSOC5A &&\
+ EXTLED__PORT == 15 && ((EXTLED__MASK & 0xC0) != 0))
+
+
+/***************************************
+* Function Prototypes
+***************************************/
+
+void EXTLED_Write(uint8 value) ;
+void EXTLED_SetDriveMode(uint8 mode) ;
+uint8 EXTLED_ReadDataReg(void) ;
+uint8 EXTLED_Read(void) ;
+uint8 EXTLED_ClearInterrupt(void) ;
+
+
+/***************************************
+* API Constants
+***************************************/
+
+/* Drive Modes */
+#define EXTLED_DM_ALG_HIZ PIN_DM_ALG_HIZ
+#define EXTLED_DM_DIG_HIZ PIN_DM_DIG_HIZ
+#define EXTLED_DM_RES_UP PIN_DM_RES_UP
+#define EXTLED_DM_RES_DWN PIN_DM_RES_DWN
+#define EXTLED_DM_OD_LO PIN_DM_OD_LO
+#define EXTLED_DM_OD_HI PIN_DM_OD_HI
+#define EXTLED_DM_STRONG PIN_DM_STRONG
+#define EXTLED_DM_RES_UPDWN PIN_DM_RES_UPDWN
+
+/* Digital Port Constants */
+#define EXTLED_MASK EXTLED__MASK
+#define EXTLED_SHIFT EXTLED__SHIFT
+#define EXTLED_WIDTH 1u
+
+
+/***************************************
+* Registers
+***************************************/
+
+/* Main Port Registers */
+/* Pin State */
+#define EXTLED_PS (* (reg8 *) EXTLED__PS)
+/* Data Register */
+#define EXTLED_DR (* (reg8 *) EXTLED__DR)
+/* Port Number */
+#define EXTLED_PRT_NUM (* (reg8 *) EXTLED__PRT)
+/* Connect to Analog Globals */
+#define EXTLED_AG (* (reg8 *) EXTLED__AG)
+/* Analog MUX bux enable */
+#define EXTLED_AMUX (* (reg8 *) EXTLED__AMUX)
+/* Bidirectional Enable */
+#define EXTLED_BIE (* (reg8 *) EXTLED__BIE)
+/* Bit-mask for Aliased Register Access */
+#define EXTLED_BIT_MASK (* (reg8 *) EXTLED__BIT_MASK)
+/* Bypass Enable */
+#define EXTLED_BYP (* (reg8 *) EXTLED__BYP)
+/* Port wide control signals */
+#define EXTLED_CTL (* (reg8 *) EXTLED__CTL)
+/* Drive Modes */
+#define EXTLED_DM0 (* (reg8 *) EXTLED__DM0)
+#define EXTLED_DM1 (* (reg8 *) EXTLED__DM1)
+#define EXTLED_DM2 (* (reg8 *) EXTLED__DM2)
+/* Input Buffer Disable Override */
+#define EXTLED_INP_DIS (* (reg8 *) EXTLED__INP_DIS)
+/* LCD Common or Segment Drive */
+#define EXTLED_LCD_COM_SEG (* (reg8 *) EXTLED__LCD_COM_SEG)
+/* Enable Segment LCD */
+#define EXTLED_LCD_EN (* (reg8 *) EXTLED__LCD_EN)
+/* Slew Rate Control */
+#define EXTLED_SLW (* (reg8 *) EXTLED__SLW)
+
+/* DSI Port Registers */
+/* Global DSI Select Register */
+#define EXTLED_PRTDSI__CAPS_SEL (* (reg8 *) EXTLED__PRTDSI__CAPS_SEL)
+/* Double Sync Enable */
+#define EXTLED_PRTDSI__DBL_SYNC_IN (* (reg8 *) EXTLED__PRTDSI__DBL_SYNC_IN)
+/* Output Enable Select Drive Strength */
+#define EXTLED_PRTDSI__OE_SEL0 (* (reg8 *) EXTLED__PRTDSI__OE_SEL0)
+#define EXTLED_PRTDSI__OE_SEL1 (* (reg8 *) EXTLED__PRTDSI__OE_SEL1)
+/* Port Pin Output Select Registers */
+#define EXTLED_PRTDSI__OUT_SEL0 (* (reg8 *) EXTLED__PRTDSI__OUT_SEL0)
+#define EXTLED_PRTDSI__OUT_SEL1 (* (reg8 *) EXTLED__PRTDSI__OUT_SEL1)
+/* Sync Output Enable Registers */
+#define EXTLED_PRTDSI__SYNC_OUT (* (reg8 *) EXTLED__PRTDSI__SYNC_OUT)
+
+
+#if defined(EXTLED__INTSTAT) /* Interrupt Registers */
+
+ #define EXTLED_INTSTAT (* (reg8 *) EXTLED__INTSTAT)
+ #define EXTLED_SNAP (* (reg8 *) EXTLED__SNAP)
+
+#endif /* Interrupt Registers */
+
+#endif /* CY_PSOC5A... */
+
+#endif /* CY_PINS_EXTLED_H */
+
+
+/* [] END OF FILE */
--- /dev/null
+/*******************************************************************************
+* File Name: EXTLED.h
+* Version 1.90
+*
+* Description:
+* This file containts Control Register function prototypes and register defines
+*
+* Note:
+*
+********************************************************************************
+* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions,
+* disclaimers, and limitations in the end user license agreement accompanying
+* the software package with which this file was provided.
+*******************************************************************************/
+
+#if !defined(CY_PINS_EXTLED_ALIASES_H) /* Pins EXTLED_ALIASES_H */
+#define CY_PINS_EXTLED_ALIASES_H
+
+#include "cytypes.h"
+#include "cyfitter.h"
+
+
+
+/***************************************
+* Constants
+***************************************/
+#define EXTLED_0 EXTLED__0__PC
+
+#endif /* End Pins EXTLED_ALIASES_H */
+
+/* [] END OF FILE */
/* bMaxPacketSize0 */ 0x08u,
/* idVendor */ 0xB4u, 0x04u,
/* idProduct */ 0x37u, 0x13u,
-/* bcdDevice */ 0x00u, 0x30u,
+/* bcdDevice */ 0x02u, 0x30u,
/* iManufacturer */ 0x02u,
/* iProduct */ 0x01u,
/* iSerialNumber */ 0x80u,
0x00u, 0x40u, 0x00u, 0x20u, 0x11u, 0x00u, 0x00u, 0x00u,
0x59u, 0x01u, 0x00u, 0x00u, 0x59u, 0x01u, 0x00u, 0x00u,
0x08u, 0xB5u, 0x04u, 0x4Bu, 0x04u, 0x48u, 0x1Au, 0x68u,
- 0x02u, 0x60u, 0x00u, 0xF0u, 0x87u, 0xFCu, 0x00u, 0xF0u,
+ 0x02u, 0x60u, 0x00u, 0xF0u, 0x53u, 0xFCu, 0x00u, 0xF0u,
0x9Du, 0xF8u, 0x00u, 0xBFu, 0xFAu, 0x46u, 0x00u, 0x40u,
0xBCu, 0x76u, 0x00u, 0x40u, 0x10u, 0xB5u, 0x05u, 0x4Cu,
0x23u, 0x78u, 0x33u, 0xB9u, 0x04u, 0x48u, 0x10u, 0xB1u,
0x04u, 0x48u, 0xAFu, 0xF3u, 0x00u, 0x80u, 0x01u, 0x21u,
0x21u, 0x70u, 0x10u, 0xBDu, 0x28u, 0xC1u, 0xFFu, 0x1Fu,
- 0x00u, 0x00u, 0x00u, 0x00u, 0x24u, 0x20u, 0x00u, 0x00u,
+ 0x00u, 0x00u, 0x00u, 0x00u, 0xBCu, 0x1Fu, 0x00u, 0x00u,
0x08u, 0xB5u, 0x06u, 0x4Bu, 0x1Bu, 0xB1u, 0x06u, 0x48u,
0x06u, 0x49u, 0xAFu, 0xF3u, 0x00u, 0x80u, 0x06u, 0x48u,
0x01u, 0x68u, 0x11u, 0xB1u, 0x05u, 0x4Au, 0x02u, 0xB1u,
0x90u, 0x47u, 0x08u, 0xBDu, 0x00u, 0x00u, 0x00u, 0x00u,
- 0x24u, 0x20u, 0x00u, 0x00u, 0x2Cu, 0xC1u, 0xFFu, 0x1Fu,
+ 0xBCu, 0x1Fu, 0x00u, 0x00u, 0x2Cu, 0xC1u, 0xFFu, 0x1Fu,
0x08u, 0xC1u, 0xFFu, 0x1Fu, 0x00u, 0x00u, 0x00u, 0x00u,
0x08u, 0xB5u, 0x34u, 0x4Bu, 0x1Au, 0x78u, 0x02u, 0xF0u,
0xFEu, 0x00u, 0x18u, 0x70u, 0x93u, 0xF8u, 0x7Au, 0x10u,
0x16u, 0x1Cu, 0x01u, 0xF0u, 0xFEu, 0x02u, 0x03u, 0xF8u,
0x16u, 0x2Cu, 0x93u, 0xF8u, 0x55u, 0x00u, 0x00u, 0xF0u,
0xFEu, 0x01u, 0x83u, 0xF8u, 0x55u, 0x10u, 0x00u, 0xF0u,
- 0xADu, 0xFBu, 0xFEu, 0xE7u, 0x02u, 0x50u, 0x00u, 0x40u,
+ 0xEBu, 0xF9u, 0xFEu, 0xE7u, 0x02u, 0x50u, 0x00u, 0x40u,
0xFEu, 0xE7u, 0x00u, 0x00u, 0x08u, 0xB5u, 0x12u, 0x49u,
0x12u, 0x4Bu, 0x4Au, 0x1Cu, 0x1Au, 0xD0u, 0x53u, 0xF8u,
0x10u, 0x6Cu, 0x53u, 0xF8u, 0x0Cu, 0x0Cu, 0x53u, 0xF8u,
0x04u, 0x32u, 0xF7u, 0xE7u, 0x53u, 0xF8u, 0x04u, 0x0Cu,
0x00u, 0x22u, 0x82u, 0x42u, 0x03u, 0xD0u, 0x00u, 0x25u,
0xA5u, 0x50u, 0x04u, 0x32u, 0xF9u, 0xE7u, 0x01u, 0x39u,
- 0x10u, 0x33u, 0xE2u, 0xE7u, 0x01u, 0xF0u, 0x06u, 0xFFu,
+ 0x10u, 0x33u, 0xE2u, 0xE7u, 0x01u, 0xF0u, 0xD2u, 0xFEu,
0xFFu, 0xF7u, 0x6Eu, 0xFFu, 0xFEu, 0xE7u, 0x00u, 0xBFu,
- 0x00u, 0x00u, 0x00u, 0x00u, 0x80u, 0x22u, 0x00u, 0x00u,
+ 0x00u, 0x00u, 0x00u, 0x00u, 0x18u, 0x22u, 0x00u, 0x00u,
0x08u, 0xB5u, 0x10u, 0x4Au, 0x10u, 0x4Bu, 0x1Au, 0x60u,
0x98u, 0x68u, 0x40u, 0xF4u, 0x00u, 0x72u, 0x9Au, 0x60u,
0x00u, 0x23u, 0x03u, 0x2Bu, 0x96u, 0xBFu, 0x0Du, 0x4Au,
0x00u, 0x24u, 0x23u, 0xF8u, 0x02u, 0x1Cu, 0x5Fu, 0x4Eu,
0x4Fu, 0xF4u, 0xF0u, 0x70u, 0x37u, 0x78u, 0x07u, 0xF0u,
0x01u, 0x02u, 0x42u, 0xEAu, 0x44u, 0x04u, 0x00u, 0xF0u,
- 0x7Fu, 0xFBu, 0x01u, 0x3Du, 0x04u, 0xF0u, 0x03u, 0x04u,
+ 0x4Bu, 0xFBu, 0x01u, 0x3Du, 0x04u, 0xF0u, 0x03u, 0x04u,
0x17u, 0xD0u, 0x03u, 0x2Cu, 0xEFu, 0xD1u, 0x58u, 0x48u,
0x58u, 0x4Fu, 0x00u, 0x26u, 0x4Fu, 0xF4u, 0x80u, 0x73u,
0x57u, 0x4Du, 0x07u, 0x21u, 0x48u, 0x22u, 0x02u, 0x24u,
0x28u, 0x78u, 0x40u, 0xF0u, 0x04u, 0x03u, 0x2Bu, 0x70u,
0x00u, 0xE0u, 0xFEu, 0xE7u, 0x4Fu, 0x4Fu, 0x06u, 0x21u,
0x01u, 0xFBu, 0x06u, 0x72u, 0x00u, 0x21u, 0x10u, 0x68u,
- 0x01u, 0x36u, 0x92u, 0x88u, 0x01u, 0xF0u, 0xADu, 0xFEu,
+ 0x01u, 0x36u, 0x92u, 0x88u, 0x01u, 0xF0u, 0x79u, 0xFEu,
0x07u, 0x2Eu, 0xF3u, 0xD1u, 0x00u, 0x23u, 0x19u, 0x46u,
0x49u, 0x4Cu, 0x00u, 0x22u, 0x18u, 0x59u, 0x30u, 0x34u,
0xC6u, 0xB2u, 0x20u, 0xF0u, 0xFFu, 0x07u, 0x04u, 0xEBu,
0x0Fu, 0x01u, 0x00u, 0x49u, 0x22u, 0x42u, 0x00u, 0x40u,
0xA1u, 0x46u, 0x00u, 0x40u, 0x25u, 0x42u, 0x00u, 0x40u,
0x04u, 0x40u, 0x00u, 0x40u, 0x06u, 0x40u, 0x00u, 0x40u,
- 0xE8u, 0x46u, 0x00u, 0x40u, 0x28u, 0x20u, 0x00u, 0x00u,
- 0x54u, 0x20u, 0x00u, 0x00u, 0x03u, 0x50u, 0x01u, 0x40u,
+ 0xE8u, 0x46u, 0x00u, 0x40u, 0xC0u, 0x1Fu, 0x00u, 0x00u,
+ 0xECu, 0x1Fu, 0x00u, 0x00u, 0x03u, 0x50u, 0x01u, 0x40u,
0xC2u, 0x43u, 0x00u, 0x40u, 0xA0u, 0x43u, 0x00u, 0x40u,
- 0x00u, 0x51u, 0x00u, 0x40u, 0xB2u, 0x20u, 0x00u, 0x00u,
+ 0x00u, 0x51u, 0x00u, 0x40u, 0x4Au, 0x20u, 0x00u, 0x00u,
0xF0u, 0x51u, 0x00u, 0x40u, 0x62u, 0x51u, 0x00u, 0x40u,
0x22u, 0x43u, 0x00u, 0x40u, 0xCFu, 0x01u, 0x00u, 0x49u,
0x6Eu, 0x58u, 0x00u, 0x40u, 0x76u, 0x58u, 0x00u, 0x40u,
0x02u, 0x78u, 0xE4u, 0xB2u, 0x94u, 0x42u, 0x01u, 0xD0u,
0x06u, 0x20u, 0x70u, 0xBDu, 0x00u, 0x2Du, 0xFBu, 0xD0u,
0x00u, 0x20u, 0x70u, 0xBDu, 0xC0u, 0xFFu, 0x01u, 0x00u,
- 0x2Du, 0xE9u, 0xF0u, 0x4Fu, 0xADu, 0xF5u, 0x61u, 0x7Du,
- 0x80u, 0x46u, 0x00u, 0xF0u, 0xE5u, 0xFBu, 0x62u, 0xB6u,
- 0x00u, 0x26u, 0xB2u, 0x46u, 0x4Fu, 0xF0u, 0x0Au, 0x09u,
- 0x37u, 0x46u, 0xB8u, 0xF1u, 0x00u, 0x0Fu, 0x01u, 0xD1u,
- 0xFFu, 0x23u, 0x00u, 0xE0u, 0x43u, 0x46u, 0x4Au, 0xA8u,
- 0x4Fu, 0xF4u, 0x96u, 0x71u, 0x01u, 0xAAu, 0x00u, 0xF0u,
- 0x0Du, 0xFCu, 0xB8u, 0xF1u, 0x00u, 0x0Fu, 0x03u, 0xD0u,
- 0x09u, 0xF1u, 0xFFu, 0x39u, 0x5Fu, 0xFAu, 0x89u, 0xF9u,
- 0xB9u, 0xF1u, 0x00u, 0x0Fu, 0x02u, 0xD0u, 0x00u, 0x28u,
- 0xE7u, 0xD1u, 0x01u, 0xE0u, 0x00u, 0x28u, 0x71u, 0xD1u,
- 0xBDu, 0xF8u, 0x04u, 0x20u, 0x06u, 0x2Au, 0x40u, 0xF2u,
- 0x7Bu, 0x81u, 0x9Du, 0xF8u, 0x28u, 0x31u, 0x01u, 0x2Bu,
- 0x40u, 0xF0u, 0x76u, 0x81u, 0x9Du, 0xF8u, 0x2Au, 0x01u,
- 0x9Du, 0xF8u, 0x2Bu, 0x51u, 0x4Au, 0xA9u, 0x40u, 0xEAu,
- 0x05u, 0x25u, 0xECu, 0x1Du, 0x4Bu, 0x19u, 0x94u, 0x42u,
- 0x58u, 0x79u, 0x19u, 0x79u, 0x00u, 0xF2u, 0x66u, 0x81u,
- 0x9Au, 0x79u, 0x17u, 0x2Au, 0x40u, 0xF0u, 0x64u, 0x81u,
- 0x2Bu, 0x1Du, 0x9Bu, 0xB2u, 0x00u, 0x22u, 0x3Bu, 0xB1u,
- 0x0Du, 0xF2u, 0x27u, 0x14u, 0xE4u, 0x5Cu, 0x01u, 0x3Bu,
- 0x12u, 0x19u, 0x92u, 0xB2u, 0x9Bu, 0xB2u, 0xF6u, 0xE7u,
- 0x52u, 0x42u, 0x41u, 0xEAu, 0x00u, 0x20u, 0x91u, 0xB2u,
- 0x88u, 0x42u, 0x40u, 0xF0u, 0x53u, 0x81u, 0x4Au, 0xE0u,
- 0x00u, 0x2Eu, 0x00u, 0xF0u, 0x4Du, 0x81u, 0x01u, 0x2Du,
- 0x4Fu, 0xF0u, 0x00u, 0x04u, 0x40u, 0xF0u, 0x3Cu, 0x81u,
- 0xBBu, 0xF1u, 0x01u, 0x0Fu, 0x00u, 0xF2u, 0x38u, 0x81u,
- 0xFFu, 0x23u, 0x8Du, 0xF8u, 0x2Cu, 0x41u, 0x8Du, 0xF8u,
- 0x2Du, 0x41u, 0x25u, 0x46u, 0x8Du, 0xF8u, 0x2Eu, 0x31u,
- 0x8Du, 0xF8u, 0x2Fu, 0x61u, 0x04u, 0x24u, 0x01u, 0x20u,
- 0x00u, 0x22u, 0x21u, 0x1Du, 0xADu, 0xF8u, 0x06u, 0x40u,
- 0x8Du, 0xF8u, 0x28u, 0x01u, 0x8Du, 0xF8u, 0x29u, 0x51u,
- 0x8Du, 0xF8u, 0x2Au, 0x41u, 0x8Du, 0xF8u, 0x2Bu, 0x21u,
- 0x8Bu, 0xB2u, 0x0Du, 0xF2u, 0x27u, 0x10u, 0xC1u, 0x5Cu,
- 0x01u, 0x3Bu, 0x52u, 0x18u, 0x9Bu, 0xB2u, 0x92u, 0xB2u,
- 0x00u, 0x2Bu, 0xF6u, 0xD1u, 0x50u, 0x42u, 0x81u, 0xB2u,
- 0x08u, 0x0Au, 0x4Bu, 0xAAu, 0x0Du, 0xF2u, 0x2Du, 0x13u,
- 0x11u, 0x55u, 0x18u, 0x55u, 0x17u, 0x21u, 0x0Du, 0xF5u,
- 0x97u, 0x72u, 0xE3u, 0x1Du, 0x11u, 0x55u, 0x4Au, 0xA8u,
- 0x99u, 0xB2u, 0x0Du, 0xF1u, 0x06u, 0x02u, 0x96u, 0x23u,
- 0x00u, 0xF0u, 0x62u, 0xFBu, 0xB8u, 0xF1u, 0x00u, 0x0Fu,
- 0x3Fu, 0xF4u, 0x72u, 0xAFu, 0x00u, 0x2Eu, 0x00u, 0xF0u,
- 0x12u, 0x81u, 0x01u, 0x26u, 0x69u, 0xE7u, 0x9Du, 0xF8u,
- 0x29u, 0x21u, 0x9Du, 0xF8u, 0x2Cu, 0xB1u, 0xA2u, 0xF1u,
- 0x31u, 0x03u, 0x0Au, 0x2Bu, 0x00u, 0xF2u, 0xF7u, 0x80u,
- 0x01u, 0xA1u, 0x51u, 0xF8u, 0x23u, 0xF0u, 0x00u, 0xBFu,
- 0xB5u, 0x06u, 0x00u, 0x00u, 0xD9u, 0x05u, 0x00u, 0x00u,
- 0x6Fu, 0x08u, 0x00u, 0x00u, 0xD3u, 0x06u, 0x00u, 0x00u,
- 0x85u, 0x07u, 0x00u, 0x00u, 0x6Fu, 0x08u, 0x00u, 0x00u,
- 0x8Bu, 0x07u, 0x00u, 0x00u, 0xA9u, 0x07u, 0x00u, 0x00u,
- 0xD3u, 0x06u, 0x00u, 0x00u, 0xC3u, 0x07u, 0x00u, 0x00u,
- 0x4Fu, 0x08u, 0x00u, 0x00u, 0x00u, 0x2Eu, 0x00u, 0xF0u,
- 0xDFu, 0x80u, 0x00u, 0x2Du, 0x40u, 0xF0u, 0xDCu, 0x80u,
- 0xFFu, 0xF7u, 0xF0u, 0xFEu, 0xD0u, 0xF1u, 0x01u, 0x02u,
- 0x38u, 0xBFu, 0x00u, 0x22u, 0x8Du, 0xF8u, 0x2Cu, 0x21u,
- 0xBBu, 0xE0u, 0x34u, 0x2Au, 0x12u, 0xD1u, 0x00u, 0x2Eu,
- 0x00u, 0xF0u, 0xCEu, 0x80u, 0x03u, 0x2Du, 0x40u, 0xF0u,
- 0xCBu, 0x80u, 0xABu, 0xF1u, 0x40u, 0x07u, 0x3Fu, 0x2Fu,
- 0x8Cu, 0xBFu, 0x4Fu, 0xF4u, 0x90u, 0x77u, 0x10u, 0x27u,
- 0x95u, 0xA8u, 0x00u, 0x21u, 0x3Au, 0x46u, 0x01u, 0xF0u,
- 0x88u, 0xFCu, 0x05u, 0xE0u, 0x00u, 0x2Eu, 0x00u, 0xF0u,
- 0xBBu, 0x80u, 0x02u, 0x2Du, 0x40u, 0xF2u, 0xB8u, 0x80u,
- 0x03u, 0x3Du, 0x95u, 0xABu, 0x2Au, 0x46u, 0xD8u, 0x19u,
- 0x0Du, 0xF2u, 0x2Fu, 0x11u, 0x01u, 0xF0u, 0x70u, 0xFCu,
- 0xABu, 0xF1u, 0x40u, 0x00u, 0x7Au, 0x19u, 0x3Fu, 0x28u,
- 0x96u, 0xB2u, 0x03u, 0xD8u, 0x00u, 0xF0u, 0xD4u, 0xF9u,
- 0x10u, 0x24u, 0x01u, 0xE0u, 0x4Fu, 0xF4u, 0x90u, 0x74u,
- 0xA6u, 0x42u, 0x40u, 0xF0u, 0x97u, 0x80u, 0x9Du, 0xF8u,
- 0x2Eu, 0x11u, 0x9Du, 0xF8u, 0x2Du, 0x71u, 0xBBu, 0xF1u,
- 0x3Fu, 0x0Fu, 0x47u, 0xEAu, 0x01u, 0x25u, 0x11u, 0xD8u,
- 0xBAu, 0xF1u, 0x00u, 0x0Fu, 0x0Eu, 0xD1u, 0x51u, 0x46u,
- 0x4Fu, 0xF4u, 0x90u, 0x72u, 0x02u, 0xA8u, 0x01u, 0xF0u,
- 0x58u, 0xFCu, 0x01u, 0x20u, 0xFFu, 0x21u, 0x02u, 0xAAu,
- 0x4Fu, 0xF4u, 0x90u, 0x73u, 0x00u, 0xF0u, 0x64u, 0xF9u,
- 0x4Fu, 0xF0u, 0x01u, 0x0Au, 0x33u, 0x46u, 0x58u, 0x46u,
- 0x29u, 0x46u, 0x95u, 0xAAu, 0x00u, 0xF0u, 0x5Cu, 0xF9u,
- 0x01u, 0x26u, 0x00u, 0x28u, 0x75u, 0xD0u, 0x00u, 0x27u,
- 0x0Au, 0x25u, 0x75u, 0xE0u, 0x00u, 0x2Eu, 0x77u, 0xD0u,
- 0x7Au, 0xE0u, 0x00u, 0x2Eu, 0x74u, 0xD0u, 0x7Cu, 0x19u,
- 0xB4u, 0xF5u, 0x96u, 0x7Fu, 0x6Eu, 0xD8u, 0x95u, 0xA9u,
- 0xC8u, 0x19u, 0x2Au, 0x46u, 0x4Bu, 0xA9u, 0x01u, 0xF0u,
- 0x2Bu, 0xFCu, 0xA7u, 0xB2u, 0x00u, 0x25u, 0x63u, 0xE0u,
- 0x00u, 0x2Du, 0x65u, 0xD1u, 0x3Au, 0x48u, 0x02u, 0xAEu,
- 0x4Bu, 0xACu, 0x03u, 0xC8u, 0x86u, 0xE8u, 0x03u, 0x00u,
- 0x84u, 0xE8u, 0x03u, 0x00u, 0x01u, 0x26u, 0x08u, 0x24u,
- 0x21u, 0xE7u, 0x00u, 0x2Eu, 0x58u, 0xD0u, 0x03u, 0x2Du,
- 0x56u, 0xD1u, 0x9Du, 0xF8u, 0x2Eu, 0x01u, 0x9Du, 0xF8u,
- 0x2Du, 0x11u, 0xABu, 0xF1u, 0x40u, 0x02u, 0x3Fu, 0x2Au,
- 0x41u, 0xEAu, 0x00u, 0x25u, 0x0Au, 0xD8u, 0x2Du, 0x01u,
- 0x00u, 0x23u, 0x10u, 0x22u, 0x2Du, 0x48u, 0x11u, 0x18u,
- 0x4Cu, 0x5Du, 0x01u, 0x3Au, 0x23u, 0x44u, 0xDBu, 0xB2u,
- 0xF8u, 0xD1u, 0x26u, 0xE0u, 0x05u, 0xEBu, 0x0Bu, 0x23u,
- 0x1Cu, 0x02u, 0x4Fu, 0xF4u, 0x80u, 0x72u, 0x00u, 0x23u,
- 0x01u, 0x3Au, 0x10u, 0x5Du, 0x19u, 0x18u, 0xCBu, 0xB2u,
- 0x00u, 0x2Au, 0xF9u, 0xD1u, 0xBBu, 0xF1u, 0x3Fu, 0x0Fu,
- 0x17u, 0xD8u, 0x0Bu, 0xF5u, 0x10u, 0x34u, 0x05u, 0xEBu,
- 0x04u, 0x20u, 0x41u, 0x01u, 0x54u, 0x5Cu, 0x01u, 0x32u,
- 0x1Bu, 0x19u, 0x20u, 0x2Au, 0xDBu, 0xB2u, 0xF9u, 0xD1u,
- 0xBBu, 0xF1u, 0x01u, 0x0Fu, 0x09u, 0xD1u, 0xFFu, 0x2Du,
- 0x07u, 0xD1u, 0x1Bu, 0x4Du, 0x1Bu, 0x4Cu, 0x28u, 0x78u,
- 0x19u, 0x1Au, 0x23u, 0x78u, 0xCAu, 0x1Au, 0x02u, 0xF0u,
- 0xFFu, 0x03u, 0x5Du, 0x42u, 0x8Du, 0xF8u, 0x2Cu, 0x51u,
- 0x00u, 0x25u, 0x01u, 0x24u, 0xDBu, 0xE6u, 0xFFu, 0xF7u,
- 0x29u, 0xFEu, 0x10u, 0xB9u, 0x14u, 0x4Du, 0x80u, 0x24u,
- 0x2Cu, 0x70u, 0x00u, 0xF0u, 0x47u, 0xF9u, 0x0Bu, 0xE0u,
- 0x04u, 0x25u, 0xD0u, 0xE6u, 0x01u, 0x26u, 0x00u, 0x27u,
- 0x04u, 0xE0u, 0x07u, 0x46u, 0x9Au, 0xE7u, 0x05u, 0x25u,
- 0x00u, 0x24u, 0xC8u, 0xE6u, 0x03u, 0x25u, 0xFBu, 0xE7u,
- 0x04u, 0x25u, 0xF9u, 0xE7u, 0x08u, 0x25u, 0xF7u, 0xE7u,
- 0xB8u, 0xF1u, 0x00u, 0x0Fu, 0x01u, 0xD1u, 0x47u, 0x46u,
- 0x5Eu, 0xE6u, 0x00u, 0x27u, 0xEDu, 0xE6u, 0x0Du, 0xF5u,
- 0x61u, 0x7Du, 0xBDu, 0xE8u, 0xF0u, 0x8Fu, 0x00u, 0xBFu,
- 0xF0u, 0x20u, 0x00u, 0x00u, 0xFFu, 0x7Fu, 0x00u, 0x40u,
- 0xD0u, 0xFFu, 0x01u, 0x00u, 0xD1u, 0xFFu, 0x01u, 0x00u,
- 0xFAu, 0x46u, 0x00u, 0x40u, 0x10u, 0xB5u, 0xC8u, 0xB0u,
- 0x00u, 0xF0u, 0x94u, 0xF8u, 0x10u, 0xB1u, 0x00u, 0x20u,
- 0x00u, 0xF0u, 0x16u, 0xF9u, 0x68u, 0x46u, 0x00u, 0xF0u,
- 0xA1u, 0xF8u, 0x10u, 0xB1u, 0x00u, 0x20u, 0x00u, 0xF0u,
- 0x0Fu, 0xF9u, 0x16u, 0x48u, 0x03u, 0x68u, 0x19u, 0x68u,
+ 0x2Du, 0xE9u, 0xF0u, 0x43u, 0xADu, 0xF2u, 0xA4u, 0x4Du,
+ 0x00u, 0xF0u, 0x20u, 0xFAu, 0x10u, 0xB1u, 0x00u, 0x20u,
+ 0x00u, 0xF0u, 0xA2u, 0xFAu, 0x02u, 0xA8u, 0x00u, 0xF0u,
+ 0x2Du, 0xFAu, 0x10u, 0xB1u, 0x00u, 0x20u, 0x00u, 0xF0u,
+ 0x9Bu, 0xFAu, 0xB5u, 0x48u, 0x03u, 0x68u, 0x19u, 0x68u,
0x00u, 0x23u, 0x0Au, 0x46u, 0x22u, 0xB1u, 0x12u, 0xF8u,
0x01u, 0x4Du, 0xE3u, 0x18u, 0xDBu, 0xB2u, 0xF9u, 0xE7u,
- 0x42u, 0x68u, 0x10u, 0x78u, 0xC4u, 0x1Au, 0x04u, 0xF0u,
- 0xFFu, 0x03u, 0x83u, 0x42u, 0x00u, 0xD1u, 0x11u, 0xB9u,
- 0x00u, 0x20u, 0x00u, 0xF0u, 0xF9u, 0xF8u, 0x0Cu, 0x4Cu,
- 0xFFu, 0xF7u, 0xD4u, 0xFDu, 0x21u, 0x78u, 0x01u, 0xF0u,
- 0xC0u, 0x02u, 0x40u, 0x2Au, 0x00u, 0xD0u, 0x18u, 0xB1u,
- 0x00u, 0x20u, 0x20u, 0x70u, 0xFFu, 0xF7u, 0x0Cu, 0xFEu,
- 0x14u, 0x20u, 0xFFu, 0xF7u, 0x09u, 0xFEu, 0x80u, 0x20u,
- 0x20u, 0x70u, 0x00u, 0xF0u, 0xE7u, 0xF8u, 0x48u, 0xB0u,
- 0x10u, 0xBDu, 0x00u, 0xBFu, 0x0Cu, 0xC1u, 0xFFu, 0x1Fu,
+ 0x42u, 0x68u, 0x10u, 0x78u, 0xC3u, 0x1Au, 0x03u, 0xF0u,
+ 0xFFu, 0x02u, 0x82u, 0x42u, 0x00u, 0xD1u, 0x11u, 0xB9u,
+ 0x00u, 0x20u, 0x00u, 0xF0u, 0x85u, 0xFAu, 0xFFu, 0xF7u,
+ 0x95u, 0xFFu, 0xAAu, 0x49u, 0x0Bu, 0x78u, 0x03u, 0xF0u,
+ 0xC0u, 0x02u, 0x40u, 0x2Au, 0x0Bu, 0x46u, 0x01u, 0xD0u,
+ 0x00u, 0x28u, 0x3Eu, 0xD0u, 0x00u, 0x26u, 0x1Eu, 0x70u,
+ 0x00u, 0xF0u, 0x82u, 0xFBu, 0x62u, 0xB6u, 0xB1u, 0x46u,
+ 0x00u, 0x27u, 0x92u, 0xA8u, 0x4Fu, 0xF4u, 0x96u, 0x71u,
+ 0x01u, 0xAAu, 0xFFu, 0x23u, 0x00u, 0xF0u, 0xB2u, 0xFBu,
+ 0x00u, 0x28u, 0xF6u, 0xD1u, 0xBDu, 0xF8u, 0x04u, 0x20u,
+ 0x06u, 0x2Au, 0x40u, 0xF2u, 0x81u, 0x81u, 0x9Du, 0xF8u,
+ 0x48u, 0x42u, 0x01u, 0x2Cu, 0x40u, 0xF0u, 0x7Cu, 0x81u,
+ 0x9Du, 0xF8u, 0x4Au, 0x12u, 0x9Du, 0xF8u, 0x4Bu, 0x52u,
+ 0x92u, 0xABu, 0x41u, 0xEAu, 0x05u, 0x25u, 0x05u, 0xF1u,
+ 0x07u, 0x0Eu, 0x5Bu, 0x19u, 0x96u, 0x45u, 0x5Cu, 0x79u,
+ 0x19u, 0x79u, 0x00u, 0xF2u, 0x6Bu, 0x81u, 0x9Au, 0x79u,
+ 0x17u, 0x2Au, 0x40u, 0xF0u, 0x69u, 0x81u, 0x2Bu, 0x1Du,
+ 0x9Bu, 0xB2u, 0x33u, 0xB1u, 0x0Du, 0xF2u, 0x47u, 0x22u,
+ 0xD2u, 0x5Cu, 0x01u, 0x3Bu, 0x80u, 0x18u, 0x80u, 0xB2u,
+ 0xF6u, 0xE7u, 0x40u, 0x42u, 0x41u, 0xEAu, 0x04u, 0x24u,
+ 0x81u, 0xB2u, 0x8Cu, 0x42u, 0x40u, 0xF0u, 0x5Au, 0x81u,
+ 0x08u, 0xE0u, 0x80u, 0x20u, 0x08u, 0x70u, 0x00u, 0xF0u,
+ 0x39u, 0xFAu, 0x29u, 0xB0u, 0x0Du, 0xF5u, 0x80u, 0x6Du,
+ 0xBDu, 0xE8u, 0xF0u, 0x83u, 0x9Du, 0xF8u, 0x49u, 0x22u,
+ 0x9Du, 0xF8u, 0x4Cu, 0x82u, 0xA2u, 0xF1u, 0x31u, 0x03u,
+ 0x0Au, 0x2Bu, 0x00u, 0xF2u, 0x15u, 0x81u, 0xDFu, 0xE8u,
+ 0x13u, 0xF0u, 0x0Bu, 0x00u, 0x1Au, 0x00u, 0x13u, 0x01u,
+ 0x32u, 0x00u, 0x8Cu, 0x00u, 0x13u, 0x01u, 0x90u, 0x00u,
+ 0xA1u, 0x00u, 0x32u, 0x00u, 0xAFu, 0x00u, 0x03u, 0x01u,
+ 0x00u, 0x2Eu, 0x00u, 0xF0u, 0x35u, 0x81u, 0x00u, 0x2Du,
+ 0x40u, 0xF0u, 0x32u, 0x81u, 0xFFu, 0xF7u, 0x26u, 0xFFu,
+ 0xD0u, 0xF1u, 0x01u, 0x02u, 0x38u, 0xBFu, 0x00u, 0x22u,
+ 0x8Du, 0xF8u, 0x4Cu, 0x22u, 0xDAu, 0xE0u, 0x00u, 0x2Eu,
+ 0x00u, 0xF0u, 0x26u, 0x81u, 0x01u, 0x2Du, 0x4Fu, 0xF0u,
+ 0x00u, 0x04u, 0x40u, 0xF0u, 0xEAu, 0x80u, 0xB8u, 0xF1u,
+ 0x01u, 0x0Fu, 0x00u, 0xF2u, 0xE6u, 0x80u, 0xFFu, 0x23u,
+ 0x8Du, 0xF8u, 0x4Cu, 0x42u, 0x8Du, 0xF8u, 0x4Du, 0x42u,
+ 0x25u, 0x46u, 0x8Du, 0xF8u, 0x4Eu, 0x32u, 0x8Du, 0xF8u,
+ 0x4Fu, 0x62u, 0x04u, 0x24u, 0xE2u, 0xE0u, 0x34u, 0x2Au,
+ 0x12u, 0xD1u, 0x00u, 0x2Eu, 0x00u, 0xF0u, 0x0Cu, 0x81u,
+ 0x03u, 0x2Du, 0x40u, 0xF0u, 0x09u, 0x81u, 0xA8u, 0xF1u,
+ 0x40u, 0x07u, 0x3Fu, 0x2Fu, 0x8Cu, 0xBFu, 0x4Fu, 0xF4u,
+ 0x90u, 0x77u, 0x10u, 0x27u, 0xDDu, 0xA8u, 0x00u, 0x21u,
+ 0x3Au, 0x46u, 0x01u, 0xF0u, 0x72u, 0xFCu, 0x05u, 0xE0u,
+ 0x00u, 0x2Eu, 0x00u, 0xF0u, 0xF9u, 0x80u, 0x02u, 0x2Du,
+ 0x40u, 0xF2u, 0xF6u, 0x80u, 0x03u, 0x3Du, 0xDDu, 0xABu,
+ 0x2Au, 0x46u, 0xD8u, 0x19u, 0x0Du, 0xF2u, 0x4Fu, 0x21u,
+ 0x01u, 0xF0u, 0x5Au, 0xFCu, 0xA8u, 0xF1u, 0x40u, 0x00u,
+ 0x7Au, 0x19u, 0x3Fu, 0x28u, 0x96u, 0xB2u, 0x03u, 0xD8u,
+ 0x00u, 0xF0u, 0xBEu, 0xF9u, 0x10u, 0x24u, 0x01u, 0xE0u,
+ 0x4Fu, 0xF4u, 0x90u, 0x74u, 0xA6u, 0x42u, 0x40u, 0xF0u,
+ 0xAAu, 0x80u, 0x9Du, 0xF8u, 0x4Eu, 0x12u, 0x9Du, 0xF8u,
+ 0x4Du, 0x72u, 0xB8u, 0xF1u, 0x3Fu, 0x0Fu, 0x47u, 0xEAu,
+ 0x01u, 0x25u, 0x11u, 0xD8u, 0xB9u, 0xF1u, 0x00u, 0x0Fu,
+ 0x0Eu, 0xD1u, 0x49u, 0x46u, 0x4Fu, 0xF4u, 0x90u, 0x72u,
+ 0x4Au, 0xA8u, 0x01u, 0xF0u, 0x42u, 0xFCu, 0x01u, 0x20u,
+ 0xFFu, 0x21u, 0x4Au, 0xAAu, 0x4Fu, 0xF4u, 0x90u, 0x73u,
+ 0x00u, 0xF0u, 0x4Eu, 0xF9u, 0x4Fu, 0xF0u, 0x01u, 0x09u,
+ 0x33u, 0x46u, 0x40u, 0x46u, 0x29u, 0x46u, 0xDDu, 0xAAu,
+ 0x00u, 0xF0u, 0x46u, 0xF9u, 0x01u, 0x26u, 0x00u, 0x28u,
+ 0x00u, 0xF0u, 0x88u, 0x80u, 0x00u, 0x27u, 0x0Au, 0x25u,
+ 0x87u, 0xE0u, 0x00u, 0x2Eu, 0x00u, 0xF0u, 0xB4u, 0x80u,
+ 0x22u, 0xE7u, 0x00u, 0x2Eu, 0x00u, 0xF0u, 0xB0u, 0x80u,
+ 0x7Cu, 0x19u, 0xB4u, 0xF5u, 0x96u, 0x7Fu, 0x00u, 0xF2u,
+ 0xA9u, 0x80u, 0xDDu, 0xA9u, 0xC8u, 0x19u, 0x2Au, 0x46u,
+ 0x93u, 0xA9u, 0x01u, 0xF0u, 0x11u, 0xFCu, 0xA7u, 0xB2u,
+ 0x00u, 0x25u, 0x72u, 0xE0u, 0x00u, 0x2Du, 0x40u, 0xF0u,
+ 0x9Fu, 0x80u, 0x2Bu, 0x48u, 0x4Au, 0xAEu, 0x93u, 0xACu,
+ 0x03u, 0xC8u, 0x86u, 0xE8u, 0x03u, 0x00u, 0x84u, 0xE8u,
+ 0x03u, 0x00u, 0x01u, 0x26u, 0x08u, 0x24u, 0x65u, 0xE0u,
+ 0x00u, 0x2Eu, 0x00u, 0xF0u, 0x91u, 0x80u, 0x03u, 0x2Du,
+ 0x40u, 0xF0u, 0x8Eu, 0x80u, 0x9Du, 0xF8u, 0x4Eu, 0x42u,
+ 0x9Du, 0xF8u, 0x4Du, 0x12u, 0xA8u, 0xF1u, 0x40u, 0x02u,
+ 0x3Fu, 0x2Au, 0x41u, 0xEAu, 0x04u, 0x25u, 0x0Au, 0xD8u,
+ 0x2Du, 0x01u, 0x00u, 0x23u, 0x10u, 0x22u, 0x1Du, 0x48u,
+ 0x11u, 0x18u, 0x4Cu, 0x5Du, 0x01u, 0x3Au, 0x23u, 0x44u,
+ 0xDBu, 0xB2u, 0xF8u, 0xD1u, 0x26u, 0xE0u, 0x05u, 0xEBu,
+ 0x08u, 0x23u, 0x1Cu, 0x02u, 0x4Fu, 0xF4u, 0x80u, 0x72u,
+ 0x00u, 0x23u, 0x01u, 0x3Au, 0x10u, 0x5Du, 0x19u, 0x18u,
+ 0xCBu, 0xB2u, 0x00u, 0x2Au, 0xF9u, 0xD1u, 0xB8u, 0xF1u,
+ 0x3Fu, 0x0Fu, 0x17u, 0xD8u, 0x08u, 0xF5u, 0x10u, 0x34u,
+ 0x05u, 0xEBu, 0x04u, 0x20u, 0x41u, 0x01u, 0x54u, 0x5Cu,
+ 0x01u, 0x32u, 0x1Bu, 0x19u, 0x20u, 0x2Au, 0xDBu, 0xB2u,
+ 0xF9u, 0xD1u, 0xB8u, 0xF1u, 0x01u, 0x0Fu, 0x09u, 0xD1u,
+ 0xFFu, 0x2Du, 0x07u, 0xD1u, 0x0Au, 0x4Du, 0x0Bu, 0x4Cu,
+ 0x28u, 0x78u, 0x19u, 0x1Au, 0x23u, 0x78u, 0xCAu, 0x1Au,
+ 0x02u, 0xF0u, 0xFFu, 0x03u, 0x5Du, 0x42u, 0x8Du, 0xF8u,
+ 0x4Cu, 0x52u, 0x00u, 0x25u, 0x01u, 0x24u, 0x1Du, 0xE0u,
+ 0x0Cu, 0xC1u, 0xFFu, 0x1Fu, 0xFAu, 0x46u, 0x00u, 0x40u,
+ 0x88u, 0x20u, 0x00u, 0x00u, 0xFFu, 0x7Fu, 0x00u, 0x40u,
+ 0xD0u, 0xFFu, 0x01u, 0x00u, 0xD1u, 0xFFu, 0x01u, 0x00u,
+ 0xFFu, 0xF7u, 0x34u, 0xFEu, 0x10u, 0xB9u, 0x20u, 0x48u,
+ 0x80u, 0x25u, 0x05u, 0x70u, 0x00u, 0xF0u, 0x1Eu, 0xF9u,
+ 0x36u, 0xE0u, 0x04u, 0x25u, 0x06u, 0xE0u, 0x01u, 0x26u,
+ 0x00u, 0x27u, 0x2Fu, 0xE0u, 0x07u, 0x46u, 0x8Bu, 0xE7u,
+ 0x05u, 0x25u, 0x00u, 0x24u, 0x01u, 0x21u, 0x8Du, 0xF8u,
+ 0x49u, 0x52u, 0x00u, 0x22u, 0x25u, 0x1Du, 0xADu, 0xF8u,
+ 0x06u, 0x40u, 0x8Du, 0xF8u, 0x48u, 0x12u, 0x8Du, 0xF8u,
+ 0x4Au, 0x42u, 0x8Du, 0xF8u, 0x4Bu, 0x22u, 0xADu, 0xB2u,
+ 0x0Du, 0xF2u, 0x47u, 0x20u, 0x41u, 0x5Du, 0x6Bu, 0x1Eu,
+ 0x52u, 0x18u, 0x9Du, 0xB2u, 0x92u, 0xB2u, 0x00u, 0x2Du,
+ 0xF6u, 0xD1u, 0x50u, 0x42u, 0x81u, 0xB2u, 0x93u, 0xAAu,
+ 0x11u, 0x55u, 0x0Du, 0x0Au, 0x0Du, 0xF2u, 0x4Du, 0x23u,
+ 0x17u, 0x20u, 0x0Du, 0xF2u, 0x4Eu, 0x21u, 0x1Du, 0x55u,
+ 0x08u, 0x55u, 0x07u, 0x34u, 0x92u, 0xA8u, 0xA1u, 0xB2u,
+ 0x0Du, 0xF1u, 0x06u, 0x02u, 0x96u, 0x23u, 0x00u, 0xF0u,
+ 0x03u, 0xFAu, 0x72u, 0xE6u, 0x03u, 0x25u, 0xD0u, 0xE7u,
+ 0x04u, 0x25u, 0xCEu, 0xE7u, 0x08u, 0x25u, 0xCCu, 0xE7u,
0xFAu, 0x46u, 0x00u, 0x40u, 0x08u, 0xB5u, 0x0Au, 0x4Bu,
0x1Au, 0x78u, 0x02u, 0xF0u, 0xC0u, 0x00u, 0x80u, 0x28u,
0x0Cu, 0xD1u, 0x00u, 0x21u, 0x19u, 0x70u, 0x01u, 0x20u,
- 0xFFu, 0xF7u, 0x6Au, 0xFDu, 0x30u, 0xB1u, 0x01u, 0x20u,
- 0xFFu, 0xF7u, 0x66u, 0xFDu, 0xBDu, 0xE8u, 0x08u, 0x40u,
- 0xFFu, 0xF7u, 0x60u, 0xBDu, 0x08u, 0xBDu, 0x00u, 0xBFu,
+ 0xFFu, 0xF7u, 0x9Eu, 0xFDu, 0x30u, 0xB1u, 0x01u, 0x20u,
+ 0xFFu, 0xF7u, 0x9Au, 0xFDu, 0xBDu, 0xE8u, 0x08u, 0x40u,
+ 0xFFu, 0xF7u, 0x94u, 0xBDu, 0x08u, 0xBDu, 0x00u, 0xBFu,
0xFAu, 0x46u, 0x00u, 0x40u, 0x00u, 0x00u, 0x00u, 0x00u,
0x02u, 0x30u, 0x80u, 0x08u, 0x00u, 0xF0u, 0x05u, 0x80u,
0x00u, 0xBFu, 0x01u, 0x38u, 0x00u, 0x46u, 0x7Fu, 0xF4u,
0x23u, 0xBEu, 0x00u, 0xBFu, 0xA5u, 0x43u, 0x00u, 0x40u,
0x9Du, 0x60u, 0x00u, 0x40u, 0x94u, 0x43u, 0x00u, 0x40u,
0x12u, 0x60u, 0x00u, 0x40u, 0xF8u, 0x51u, 0x00u, 0x40u,
- 0x84u, 0x60u, 0x00u, 0x40u, 0x23u, 0x16u, 0x00u, 0x00u,
- 0x21u, 0x16u, 0x00u, 0x00u, 0x61u, 0x14u, 0x00u, 0x00u,
- 0xB9u, 0x15u, 0x00u, 0x00u, 0xEDu, 0x15u, 0x00u, 0x00u,
+ 0x84u, 0x60u, 0x00u, 0x40u, 0xBBu, 0x15u, 0x00u, 0x00u,
+ 0xB9u, 0x15u, 0x00u, 0x00u, 0xF9u, 0x13u, 0x00u, 0x00u,
+ 0x51u, 0x15u, 0x00u, 0x00u, 0x85u, 0x15u, 0x00u, 0x00u,
0x18u, 0x4Bu, 0x01u, 0x22u, 0x10u, 0xB5u, 0x1Au, 0x70u,
0x17u, 0x4Bu, 0x4Fu, 0xF4u, 0x00u, 0x04u, 0x1Cu, 0x60u,
0x4Fu, 0xF0u, 0x80u, 0x74u, 0x1Cu, 0x60u, 0x1Au, 0x60u,
0x04u, 0x4Bu, 0x05u, 0x49u, 0x1Au, 0x78u, 0x01u, 0xEBu,
0xC2u, 0x03u, 0x5Au, 0x68u, 0x02u, 0xEBu, 0xC0u, 0x00u,
0xC0u, 0x68u, 0x70u, 0x47u, 0x6Cu, 0xC1u, 0xFFu, 0x1Fu,
- 0xF8u, 0x20u, 0x00u, 0x00u, 0xF8u, 0xB5u, 0x3Du, 0x4Bu,
+ 0x90u, 0x20u, 0x00u, 0x00u, 0xF8u, 0xB5u, 0x3Du, 0x4Bu,
0x1Au, 0x78u, 0x00u, 0x2Au, 0x74u, 0xD0u, 0x18u, 0x78u,
0x41u, 0x1Eu, 0xC8u, 0xB2u, 0xFFu, 0xF7u, 0xE8u, 0xFFu,
0xC3u, 0x68u, 0x05u, 0x7Au, 0x08u, 0x33u, 0x00u, 0x20u,
0x08u, 0x70u, 0x32u, 0xE0u, 0x60u, 0xC1u, 0xFFu, 0x1Fu,
0x00u, 0x60u, 0x00u, 0x40u, 0x01u, 0x60u, 0x00u, 0x40u,
0x03u, 0x60u, 0x00u, 0x40u, 0x6Cu, 0xC1u, 0xFFu, 0x1Fu,
- 0xF8u, 0x20u, 0x00u, 0x00u, 0x02u, 0x60u, 0x00u, 0x40u,
- 0xBEu, 0x21u, 0x00u, 0x00u, 0x3Au, 0x22u, 0x00u, 0x00u,
- 0xB4u, 0x21u, 0x00u, 0x00u, 0x04u, 0x60u, 0x00u, 0x40u,
+ 0x90u, 0x20u, 0x00u, 0x00u, 0x02u, 0x60u, 0x00u, 0x40u,
+ 0x56u, 0x21u, 0x00u, 0x00u, 0xD2u, 0x21u, 0x00u, 0x00u,
+ 0x4Cu, 0x21u, 0x00u, 0x00u, 0x04u, 0x60u, 0x00u, 0x40u,
0x78u, 0xC1u, 0xFFu, 0x1Fu, 0x55u, 0xC1u, 0xFFu, 0x1Fu,
0x6Fu, 0xC1u, 0xFFu, 0x1Fu, 0x71u, 0xC1u, 0xFFu, 0x1Fu,
0x5Eu, 0xC1u, 0xFFu, 0x1Fu, 0x5Cu, 0xC1u, 0xFFu, 0x1Fu,
0x54u, 0x1Au, 0xA5u, 0x10u, 0x00u, 0x24u, 0xACu, 0x42u,
0x05u, 0xD0u, 0x05u, 0x4Bu, 0x53u, 0xF8u, 0x24u, 0x00u,
0x80u, 0x47u, 0x01u, 0x34u, 0xF7u, 0xE7u, 0x38u, 0xBDu,
- 0x58u, 0x22u, 0x00u, 0x00u, 0x58u, 0x22u, 0x00u, 0x00u,
- 0x58u, 0x22u, 0x00u, 0x00u, 0x60u, 0x22u, 0x00u, 0x00u,
+ 0xF0u, 0x21u, 0x00u, 0x00u, 0xF0u, 0x21u, 0x00u, 0x00u,
+ 0xF0u, 0x21u, 0x00u, 0x00u, 0xF8u, 0x21u, 0x00u, 0x00u,
0x10u, 0xB5u, 0x00u, 0x23u, 0x93u, 0x42u, 0x03u, 0xD0u,
0xCCu, 0x5Cu, 0xC4u, 0x54u, 0x01u, 0x33u, 0xF9u, 0xE7u,
0x10u, 0xBDu, 0x82u, 0x18u, 0x03u, 0x46u, 0x93u, 0x42u,
0x02u, 0xD0u, 0x03u, 0xF8u, 0x01u, 0x1Bu, 0xFAu, 0xE7u,
- 0x70u, 0x47u, 0x00u, 0x00u, 0xA0u, 0x22u, 0x00u, 0x00u,
- 0x32u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
+ 0x70u, 0x47u, 0x00u, 0x00u, 0x38u, 0x22u, 0x00u, 0x00u,
+ 0x8Eu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
0x10u, 0x51u, 0x00u, 0x40u, 0x10u, 0x00u, 0xC0u, 0x51u,
0x00u, 0x40u, 0x10u, 0x00u, 0x00u, 0x00u, 0x01u, 0x40u,
0x00u, 0x10u, 0x00u, 0x14u, 0x01u, 0x40u, 0x00u, 0x08u,
0x03u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x33u,
0x33u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
0x69u, 0x30u, 0x13u, 0x2Eu, 0x00u, 0x14u, 0x01u, 0x01u,
- 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x21u, 0x00u, 0x00u,
- 0x01u, 0x00u, 0x00u, 0x00u, 0x3Au, 0x22u, 0x00u, 0x00u,
- 0x01u, 0x00u, 0x00u, 0x00u, 0x10u, 0x21u, 0x00u, 0x00u,
- 0x01u, 0x00u, 0x00u, 0x00u, 0x11u, 0x22u, 0x00u, 0x00u,
- 0x02u, 0x00u, 0x00u, 0x00u, 0x32u, 0x21u, 0x00u, 0x00u,
- 0x01u, 0x00u, 0x00u, 0x00u, 0x44u, 0x21u, 0x00u, 0x00u,
- 0x00u, 0x00u, 0x00u, 0x00u, 0x30u, 0x21u, 0x00u, 0x00u,
+ 0x01u, 0x00u, 0x00u, 0x00u, 0x98u, 0x20u, 0x00u, 0x00u,
+ 0x01u, 0x00u, 0x00u, 0x00u, 0xD2u, 0x21u, 0x00u, 0x00u,
+ 0x01u, 0x00u, 0x00u, 0x00u, 0xA8u, 0x20u, 0x00u, 0x00u,
+ 0x01u, 0x00u, 0x00u, 0x00u, 0xA9u, 0x21u, 0x00u, 0x00u,
+ 0x02u, 0x00u, 0x00u, 0x00u, 0xCAu, 0x20u, 0x00u, 0x00u,
+ 0x01u, 0x00u, 0x00u, 0x00u, 0xDCu, 0x20u, 0x00u, 0x00u,
+ 0x00u, 0x00u, 0x00u, 0x00u, 0xC8u, 0x20u, 0x00u, 0x00u,
0x03u, 0x00u, 0x00u, 0x00u, 0x01u, 0x03u, 0x40u, 0x00u,
0x03u, 0x00u, 0x00u, 0x00u, 0x82u, 0x03u, 0x40u, 0x00u,
0x03u, 0x00u, 0x00u, 0x00u, 0x01u, 0x00u, 0x00u, 0x00u,
- 0x4Cu, 0x21u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
- 0x80u, 0x21u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
- 0x74u, 0x21u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
+ 0xE4u, 0x20u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
+ 0x18u, 0x21u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
+ 0x0Cu, 0x21u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
0x00u, 0x00u, 0x00u, 0x00u, 0x01u, 0x00u, 0x00u, 0x00u,
- 0x8Cu, 0x21u, 0x00u, 0x00u, 0x01u, 0x00u, 0x00u, 0x00u,
- 0x23u, 0x22u, 0x00u, 0x00u, 0x41u, 0x00u, 0x00u, 0x00u,
+ 0x24u, 0x21u, 0x00u, 0x00u, 0x01u, 0x00u, 0x00u, 0x00u,
+ 0xBBu, 0x21u, 0x00u, 0x00u, 0x41u, 0x00u, 0x00u, 0x00u,
0x33u, 0xC2u, 0xFFu, 0x1Fu, 0x74u, 0xC2u, 0xFFu, 0x1Fu,
0x41u, 0x00u, 0x00u, 0x00u, 0xF2u, 0xC1u, 0xFFu, 0x1Fu,
0xEEu, 0xC1u, 0xFFu, 0x1Fu, 0x24u, 0x00u, 0x05u, 0x01u,
0x51u, 0x00u, 0x00u, 0x00u, 0xB1u, 0x01u, 0x00u, 0x00u,
0xF8u, 0xB5u, 0x00u, 0xBFu, 0xF8u, 0xBCu, 0x08u, 0xBCu,
0x9Eu, 0x46u, 0x70u, 0x47u, 0x2Du, 0x00u, 0x00u, 0x00u,
- 0x80u, 0x22u, 0x00u, 0x00u, 0x08u, 0xC1u, 0xFFu, 0x1Fu,
+ 0x18u, 0x22u, 0x00u, 0x00u, 0x08u, 0xC1u, 0xFFu, 0x1Fu,
0x20u, 0x00u, 0x00u, 0x00u, 0x50u, 0x01u, 0x00u, 0x00u,
- 0x00u, 0x00u, 0x00u, 0x00u, 0x1Cu, 0x20u, 0x00u, 0x00u,
- 0x20u, 0x20u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x7Du,
+ 0x00u, 0x00u, 0x00u, 0x00u, 0xB4u, 0x1Fu, 0x00u, 0x00u,
+ 0xB8u, 0x1Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x7Du,
0x00u, 0xFAu, 0x00u, 0x00u, 0x40u, 0x00u, 0x00u, 0x00u,
0x00u, 0x90u, 0xD0u, 0x03u, 0x00u, 0x00u, 0x00u, 0x00u,
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
+ 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
+ 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
+ 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
+ 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
+ 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
+ 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
+ 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
+ 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
+ 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
+ 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
+ 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
+ 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
+ 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u};
#if defined(__GNUC__) || defined(__ARMCC_VERSION)
#endif
const uint8 cy_metadata[] = {
0x00u, 0x01u, 0x2Eu, 0x13u, 0x30u, 0x69u, 0x00u, 0x01u,
- 0x2Eu, 0x1Fu, 0x9Au, 0x6Bu};
+ 0x2Eu, 0x1Fu, 0x7Au, 0x6Bu};
#if defined(__GNUC__) || defined(__ARMCC_VERSION)
__attribute__ ((__section__(".cycustnvl"), used))
/* SCSI_CTL_PHASE */
#define SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK 0x01u
#define SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS 0
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB12_13_ACTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB12_13_CTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB12_13_CTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB12_13_CTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB12_13_CTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB12_13_MSK
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB12_13_MSK
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB12_13_MSK
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB12_13_MSK
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB11_12_ACTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB11_12_CTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB11_12_CTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB11_12_CTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB11_12_CTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB11_12_MSK
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB11_12_MSK
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB11_12_MSK
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB11_12_MSK
#define SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK 0x02u
#define SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS 1
#define SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK 0x04u
#define SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS 2
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB12_ACTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB12_CTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB12_ST_CTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB12_CTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB12_ST_CTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB11_ACTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB11_CTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB11_ST_CTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB11_CTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB11_ST_CTL
#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK 0x07u
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB12_MSK
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB11_MSK
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL
/* SCSI_Out_Bits */
#define SCSI_Out_Bits_Sync_ctrl_reg__0__MASK 0x01u
#define SCSI_Out_Bits_Sync_ctrl_reg__0__POS 0
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB10_11_ACTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB10_11_CTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB10_11_CTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB10_11_CTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB10_11_CTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB10_11_MSK
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB10_11_MSK
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB10_11_MSK
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB10_11_MSK
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB10_11_ACTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB10_11_CTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB10_11_CTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB10_11_CTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B1_UDB10_11_CTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B1_UDB10_11_MSK
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B1_UDB10_11_MSK
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B1_UDB10_11_MSK
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB10_11_MSK
#define SCSI_Out_Bits_Sync_ctrl_reg__1__MASK 0x02u
#define SCSI_Out_Bits_Sync_ctrl_reg__1__POS 1
#define SCSI_Out_Bits_Sync_ctrl_reg__2__MASK 0x04u
#define SCSI_Out_Bits_Sync_ctrl_reg__6__POS 6
#define SCSI_Out_Bits_Sync_ctrl_reg__7__MASK 0x80u
#define SCSI_Out_Bits_Sync_ctrl_reg__7__POS 7
-#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB10_ACTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB10_CTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB10_ST_CTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB10_CTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB10_ST_CTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B1_UDB10_ACTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG CYREG_B1_UDB10_CTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B1_UDB10_ST_CTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG CYREG_B1_UDB10_CTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG CYREG_B1_UDB10_ST_CTL
#define SCSI_Out_Bits_Sync_ctrl_reg__MASK 0xFFu
-#define SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB10_MSK_ACTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB10_MSK
-#define SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB10_MSK_ACTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB10_MSK_ACTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG CYREG_B1_UDB10_MSK
+#define SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B1_UDB10_MSK_ACTL
/* USBFS_arb_int */
#define USBFS_arb_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
/* SCSI_Out_Ctl */
#define SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK 0x01u
#define SCSI_Out_Ctl_Sync_ctrl_reg__0__POS 0
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB08_09_ACTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB08_09_CTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB08_09_CTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB08_09_CTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B1_UDB08_09_CTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B1_UDB08_09_MSK
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B1_UDB08_09_MSK
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B1_UDB08_09_MSK
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB08_09_MSK
-#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B1_UDB08_ACTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B1_UDB08_CTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B1_UDB08_ST_CTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B1_UDB08_CTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B1_UDB08_ST_CTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB09_10_ACTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB09_10_CTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB09_10_CTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB09_10_CTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B1_UDB09_10_CTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B1_UDB09_10_MSK
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B1_UDB09_10_MSK
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B1_UDB09_10_MSK
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB09_10_MSK
+#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B1_UDB09_ACTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B1_UDB09_CTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B1_UDB09_ST_CTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B1_UDB09_CTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B1_UDB09_ST_CTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK 0x01u
-#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB08_MSK_ACTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B1_UDB08_MSK
-#define SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B1_UDB08_MSK_ACTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB09_MSK_ACTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B1_UDB09_MSK
+#define SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B1_UDB09_MSK_ACTL
/* SCSI_Out_DBx */
#define SCSI_Out_DBx__0__AG CYREG_PRT5_AG
#define SCSI_RST_ISR__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
/* SDCard_BSPIM */
-#define SDCard_BSPIM_BitCounter_ST__MASK_REG CYREG_B1_UDB11_MSK
-#define SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B1_UDB11_MSK_ACTL
-#define SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B1_UDB11_MSK_ACTL
-#define SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B1_UDB11_ACTL
-#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B1_UDB11_ST_CTL
-#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B1_UDB11_ST_CTL
-#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B1_UDB11_ST
-#define SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B1_UDB11_ACTL
-#define SDCard_BSPIM_BitCounter__CONTROL_REG CYREG_B1_UDB11_CTL
-#define SDCard_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B1_UDB11_ST_CTL
-#define SDCard_BSPIM_BitCounter__COUNT_REG CYREG_B1_UDB11_CTL
-#define SDCard_BSPIM_BitCounter__COUNT_ST_REG CYREG_B1_UDB11_ST_CTL
-#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB11_MSK_ACTL
-#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B1_UDB11_MSK
-#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B1_UDB11_MSK_ACTL
-#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB10_11_ACTL
-#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B1_UDB10_11_ST
+#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB08_09_ACTL
+#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B0_UDB08_09_ST
+#define SDCard_BSPIM_BitCounter_ST__MASK_REG CYREG_B0_UDB08_MSK
+#define SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL
+#define SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL
+#define SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B0_UDB08_ACTL
+#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B0_UDB08_ST_CTL
+#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B0_UDB08_ST_CTL
+#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B0_UDB08_ST
+#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB08_09_ACTL
+#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB08_09_CTL
+#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB08_09_CTL
+#define SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB08_09_CTL
+#define SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B0_UDB08_09_CTL
+#define SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B0_UDB08_09_MSK
+#define SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B0_UDB08_09_MSK
+#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B0_UDB08_09_MSK
+#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB08_09_MSK
+#define SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B0_UDB08_ACTL
+#define SDCard_BSPIM_BitCounter__CONTROL_REG CYREG_B0_UDB08_CTL
+#define SDCard_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B0_UDB08_ST_CTL
+#define SDCard_BSPIM_BitCounter__COUNT_REG CYREG_B0_UDB08_CTL
+#define SDCard_BSPIM_BitCounter__COUNT_ST_REG CYREG_B0_UDB08_ST_CTL
+#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL
+#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B0_UDB08_MSK
+#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL
+#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB11_12_ACTL
+#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B0_UDB11_12_ST
#define SDCard_BSPIM_RxStsReg__4__MASK 0x10u
#define SDCard_BSPIM_RxStsReg__4__POS 4
#define SDCard_BSPIM_RxStsReg__5__MASK 0x20u
#define SDCard_BSPIM_RxStsReg__6__MASK 0x40u
#define SDCard_BSPIM_RxStsReg__6__POS 6
#define SDCard_BSPIM_RxStsReg__MASK 0x70u
-#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B1_UDB10_MSK
-#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB10_ACTL
-#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B1_UDB10_ST
+#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B0_UDB11_MSK
+#define SDCard_BSPIM_RxStsReg__MASK_ST_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL
+#define SDCard_BSPIM_RxStsReg__PER_ST_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL
+#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB11_ACTL
+#define SDCard_BSPIM_RxStsReg__STATUS_CNT_REG CYREG_B0_UDB11_ST_CTL
+#define SDCard_BSPIM_RxStsReg__STATUS_CONTROL_REG CYREG_B0_UDB11_ST_CTL
+#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B0_UDB11_ST
#define SDCard_BSPIM_TxStsReg__0__MASK 0x01u
#define SDCard_BSPIM_TxStsReg__0__POS 0
#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB08_09_ACTL
#define SDCard_BSPIM_TxStsReg__4__POS 4
#define SDCard_BSPIM_TxStsReg__MASK 0x1Fu
#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B1_UDB08_MSK
-#define SDCard_BSPIM_TxStsReg__MASK_ST_AUX_CTL_REG CYREG_B1_UDB08_MSK_ACTL
-#define SDCard_BSPIM_TxStsReg__PER_ST_AUX_CTL_REG CYREG_B1_UDB08_MSK_ACTL
#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB08_ACTL
-#define SDCard_BSPIM_TxStsReg__STATUS_CNT_REG CYREG_B1_UDB08_ST_CTL
-#define SDCard_BSPIM_TxStsReg__STATUS_CONTROL_REG CYREG_B1_UDB08_ST_CTL
#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B1_UDB08_ST
#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B0_UDB08_09_A0
#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B0_UDB08_09_A1
#define SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG CYREG_B0_UDB08_F0_F1
#define SDCard_BSPIM_sR8_Dp_u0__F0_REG CYREG_B0_UDB08_F0
#define SDCard_BSPIM_sR8_Dp_u0__F1_REG CYREG_B0_UDB08_F1
+#define SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL
+#define SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL
/* USBFS_dp_int */
#define USBFS_dp_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
#define SD_MOSI__SHIFT 3
#define SD_MOSI__SLW CYREG_PRT3_SLW
+/* EXTLED */
+#define EXTLED__0__MASK 0x01u
+#define EXTLED__0__PC CYREG_PRT0_PC0
+#define EXTLED__0__PORT 0u
+#define EXTLED__0__SHIFT 0
+#define EXTLED__AG CYREG_PRT0_AG
+#define EXTLED__AMUX CYREG_PRT0_AMUX
+#define EXTLED__BIE CYREG_PRT0_BIE
+#define EXTLED__BIT_MASK CYREG_PRT0_BIT_MASK
+#define EXTLED__BYP CYREG_PRT0_BYP
+#define EXTLED__CTL CYREG_PRT0_CTL
+#define EXTLED__DM0 CYREG_PRT0_DM0
+#define EXTLED__DM1 CYREG_PRT0_DM1
+#define EXTLED__DM2 CYREG_PRT0_DM2
+#define EXTLED__DR CYREG_PRT0_DR
+#define EXTLED__INP_DIS CYREG_PRT0_INP_DIS
+#define EXTLED__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG
+#define EXTLED__LCD_EN CYREG_PRT0_LCD_EN
+#define EXTLED__MASK 0x01u
+#define EXTLED__PORT 0u
+#define EXTLED__PRT CYREG_PRT0_PRT
+#define EXTLED__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL
+#define EXTLED__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN
+#define EXTLED__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0
+#define EXTLED__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1
+#define EXTLED__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0
+#define EXTLED__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1
+#define EXTLED__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT
+#define EXTLED__PS CYREG_PRT0_PS
+#define EXTLED__SHIFT 0
+#define EXTLED__SLW CYREG_PRT0_SLW
+
/* SD_SCK */
#define SD_SCK__0__MASK 0x04u
#define SD_SCK__0__PC CYREG_PRT3_PC2
}
#endif
-#define CY_CFG_BASE_ADDR_COUNT 38u
+#define CY_CFG_BASE_ADDR_COUNT 37u
CYPACKED typedef struct
{
uint8 offset;
{
/* IOPINS0_0 Address: CYREG_PRT0_DR Size (bytes): 10 */
static const uint8 CYCODE BS_IOPINS0_0_VAL[] = {
- 0x02u, 0x00u, 0x30u, 0xCCu, 0xCEu, 0x00u, 0x4Cu, 0x00u, 0x00u, 0x01u};
+ 0x02u, 0x00u, 0x31u, 0xCCu, 0xCEu, 0x00u, 0x4Cu, 0x00u, 0x00u, 0x01u};
/* IOPINS0_7 Address: CYREG_PRT12_DM0 Size (bytes): 8 */
static const uint8 CYCODE BS_IOPINS0_7_VAL[] = {
static const uint32 CYCODE cy_cfg_addr_table[] = {
0x40004502u, /* Base address: 0x40004500 Count: 2 */
0x40004F02u, /* Base address: 0x40004F00 Count: 2 */
- 0x4000520Bu, /* Base address: 0x40005200 Count: 11 */
- 0x40006401u, /* Base address: 0x40006400 Count: 1 */
- 0x40006501u, /* Base address: 0x40006500 Count: 1 */
- 0x40010101u, /* Base address: 0x40010100 Count: 1 */
- 0x40010302u, /* Base address: 0x40010300 Count: 2 */
+ 0x4000520Eu, /* Base address: 0x40005200 Count: 14 */
+ 0x40006402u, /* Base address: 0x40006400 Count: 2 */
+ 0x40010004u, /* Base address: 0x40010000 Count: 4 */
+ 0x40010103u, /* Base address: 0x40010100 Count: 3 */
+ 0x40010305u, /* Base address: 0x40010300 Count: 5 */
0x40010503u, /* Base address: 0x40010500 Count: 3 */
- 0x40010701u, /* Base address: 0x40010700 Count: 1 */
- 0x40010819u, /* Base address: 0x40010800 Count: 25 */
- 0x40010952u, /* Base address: 0x40010900 Count: 82 */
- 0x40010A49u, /* Base address: 0x40010A00 Count: 73 */
- 0x40010B4Cu, /* Base address: 0x40010B00 Count: 76 */
- 0x40010C51u, /* Base address: 0x40010C00 Count: 81 */
- 0x40010D53u, /* Base address: 0x40010D00 Count: 83 */
+ 0x40010702u, /* Base address: 0x40010700 Count: 2 */
+ 0x40010858u, /* Base address: 0x40010800 Count: 88 */
+ 0x4001094Du, /* Base address: 0x40010900 Count: 77 */
+ 0x40010A4Cu, /* Base address: 0x40010A00 Count: 76 */
+ 0x40010B49u, /* Base address: 0x40010B00 Count: 73 */
+ 0x40010C4Eu, /* Base address: 0x40010C00 Count: 78 */
+ 0x40010D4Cu, /* Base address: 0x40010D00 Count: 76 */
0x40010E3Au, /* Base address: 0x40010E00 Count: 58 */
0x40010F38u, /* Base address: 0x40010F00 Count: 56 */
0x40011503u, /* Base address: 0x40011500 Count: 3 */
- 0x40011604u, /* Base address: 0x40011600 Count: 4 */
- 0x40011705u, /* Base address: 0x40011700 Count: 5 */
- 0x40011852u, /* Base address: 0x40011800 Count: 82 */
- 0x4001194Cu, /* Base address: 0x40011900 Count: 76 */
- 0x40011A4Bu, /* Base address: 0x40011A00 Count: 75 */
- 0x40011B46u, /* Base address: 0x40011B00 Count: 70 */
- 0x40014013u, /* Base address: 0x40014000 Count: 19 */
+ 0x40011702u, /* Base address: 0x40011700 Count: 2 */
+ 0x40011853u, /* Base address: 0x40011800 Count: 83 */
+ 0x40011948u, /* Base address: 0x40011900 Count: 72 */
+ 0x40011A4Fu, /* Base address: 0x40011A00 Count: 79 */
+ 0x40011B4Au, /* Base address: 0x40011B00 Count: 74 */
+ 0x40014015u, /* Base address: 0x40014000 Count: 21 */
0x40014114u, /* Base address: 0x40014100 Count: 20 */
- 0x4001420Cu, /* Base address: 0x40014200 Count: 12 */
- 0x40014306u, /* Base address: 0x40014300 Count: 6 */
- 0x40014410u, /* Base address: 0x40014400 Count: 16 */
- 0x40014514u, /* Base address: 0x40014500 Count: 20 */
+ 0x40014213u, /* Base address: 0x40014200 Count: 19 */
+ 0x40014305u, /* Base address: 0x40014300 Count: 5 */
+ 0x4001440Du, /* Base address: 0x40014400 Count: 13 */
+ 0x40014515u, /* Base address: 0x40014500 Count: 21 */
0x40014610u, /* Base address: 0x40014600 Count: 16 */
- 0x4001470Du, /* Base address: 0x40014700 Count: 13 */
- 0x4001480Cu, /* Base address: 0x40014800 Count: 12 */
+ 0x40014717u, /* Base address: 0x40014700 Count: 23 */
+ 0x40014804u, /* Base address: 0x40014800 Count: 4 */
0x4001490Du, /* Base address: 0x40014900 Count: 13 */
- 0x40014C0Au, /* Base address: 0x40014C00 Count: 10 */
- 0x40014D0Fu, /* Base address: 0x40014D00 Count: 15 */
- 0x4001500Au, /* Base address: 0x40015000 Count: 10 */
+ 0x40014C09u, /* Base address: 0x40014C00 Count: 9 */
+ 0x40014D0Eu, /* Base address: 0x40014D00 Count: 14 */
+ 0x40015007u, /* Base address: 0x40015000 Count: 7 */
0x40015104u, /* Base address: 0x40015100 Count: 4 */
};
{0x27u, 0x02u},
{0x7Eu, 0x02u},
{0x01u, 0x10u},
- {0x0Au, 0x36u},
- {0x01u, 0x44u},
- {0x10u, 0x48u},
- {0x11u, 0x8Cu},
- {0x18u, 0x04u},
+ {0x0Au, 0x4Bu},
+ {0x00u, 0x40u},
+ {0x01u, 0x04u},
+ {0x04u, 0x01u},
+ {0x10u, 0x04u},
+ {0x11u, 0x88u},
+ {0x18u, 0x0Cu},
+ {0x19u, 0x08u},
{0x1Cu, 0x20u},
- {0x20u, 0x10u},
- {0x28u, 0x02u},
+ {0x21u, 0x10u},
+ {0x28u, 0x03u},
+ {0x29u, 0x01u},
{0x30u, 0x20u},
- {0x31u, 0x30u},
- {0x79u, 0x20u},
+ {0x78u, 0x20u},
{0x7Cu, 0x40u},
{0x2Eu, 0x02u},
- {0x8Bu, 0x0Fu},
- {0xE6u, 0x02u},
- {0xE6u, 0x06u},
- {0xEEu, 0x01u},
- {0xE8u, 0x40u},
- {0xEAu, 0x01u},
- {0xEEu, 0x02u},
+ {0x88u, 0x0Fu},
+ {0xB8u, 0x80u},
+ {0xBEu, 0x40u},
+ {0xD8u, 0x04u},
+ {0xDFu, 0x01u},
+ {0x1Eu, 0x02u},
+ {0xE0u, 0x40u},
+ {0xE2u, 0x81u},
+ {0x8Eu, 0x01u},
+ {0xA2u, 0x01u},
+ {0xE2u, 0x10u},
+ {0xE6u, 0x04u},
+ {0xEEu, 0x10u},
+ {0xE2u, 0x18u},
+ {0xE6u, 0x01u},
+ {0xEEu, 0x04u},
+ {0xEAu, 0x40u},
{0xEEu, 0x08u},
- {0x86u, 0x30u},
- {0x8Cu, 0x40u},
- {0x8Eu, 0x80u},
- {0x92u, 0x80u},
- {0x94u, 0x09u},
- {0x96u, 0x24u},
- {0x9Au, 0x09u},
- {0x9Du, 0x01u},
- {0x9Eu, 0x46u},
- {0xA0u, 0x09u},
- {0xA2u, 0x12u},
- {0xA6u, 0x08u},
- {0xADu, 0x02u},
+ {0x01u, 0x01u},
+ {0x04u, 0x04u},
+ {0x06u, 0x03u},
+ {0x08u, 0x85u},
+ {0x09u, 0x01u},
+ {0x0Au, 0x02u},
+ {0x10u, 0x83u},
+ {0x11u, 0x01u},
+ {0x12u, 0x04u},
+ {0x14u, 0x81u},
+ {0x16u, 0x06u},
+ {0x1Au, 0x08u},
+ {0x1Cu, 0x28u},
+ {0x1Du, 0x01u},
+ {0x1Eu, 0x50u},
+ {0x26u, 0x40u},
+ {0x2Au, 0x10u},
+ {0x2Eu, 0x20u},
+ {0x30u, 0x80u},
+ {0x31u, 0x01u},
+ {0x32u, 0x07u},
+ {0x34u, 0x18u},
+ {0x36u, 0x60u},
+ {0x39u, 0x02u},
+ {0x3Au, 0x08u},
+ {0x3Eu, 0x51u},
+ {0x3Fu, 0x01u},
+ {0x40u, 0x43u},
+ {0x41u, 0x02u},
+ {0x42u, 0x10u},
+ {0x44u, 0x05u},
+ {0x45u, 0x0Eu},
+ {0x46u, 0xBFu},
+ {0x47u, 0xDCu},
+ {0x48u, 0x3Du},
+ {0x49u, 0xFFu},
+ {0x4Au, 0xFFu},
+ {0x4Bu, 0xFFu},
+ {0x4Cu, 0x22u},
+ {0x4Eu, 0xF0u},
+ {0x4Fu, 0x08u},
+ {0x50u, 0x04u},
+ {0x56u, 0x02u},
+ {0x57u, 0x28u},
+ {0x58u, 0x04u},
+ {0x59u, 0x04u},
+ {0x5Au, 0x04u},
+ {0x5Bu, 0x04u},
+ {0x5Fu, 0x01u},
+ {0x62u, 0xC0u},
+ {0x64u, 0x40u},
+ {0x65u, 0x01u},
+ {0x66u, 0x10u},
+ {0x67u, 0x11u},
+ {0x68u, 0xC0u},
+ {0x69u, 0x01u},
+ {0x6Bu, 0x11u},
+ {0x6Cu, 0x40u},
+ {0x6Du, 0x01u},
+ {0x6Eu, 0x40u},
+ {0x6Fu, 0x01u},
+ {0x81u, 0x01u},
+ {0x82u, 0x06u},
+ {0x84u, 0x09u},
+ {0x85u, 0x04u},
+ {0x86u, 0x12u},
+ {0x8Au, 0x09u},
+ {0x8Eu, 0x08u},
+ {0x90u, 0x09u},
+ {0x92u, 0x24u},
+ {0x9Au, 0x70u},
+ {0x9Cu, 0x40u},
+ {0x9Eu, 0x80u},
+ {0xA1u, 0x02u},
+ {0xA2u, 0x80u},
{0xAEu, 0x01u},
- {0xB0u, 0xC0u},
+ {0xB0u, 0x07u},
{0xB3u, 0x02u},
{0xB4u, 0x38u},
{0xB5u, 0x01u},
- {0xB6u, 0x07u},
- {0xBEu, 0x01u},
- {0xBFu, 0x14u},
+ {0xB6u, 0xC0u},
+ {0xB7u, 0x04u},
+ {0xBEu, 0x40u},
+ {0xBFu, 0x54u},
{0xD8u, 0x04u},
{0xD9u, 0x04u},
{0xDCu, 0x09u},
{0xDFu, 0x01u},
- {0x01u, 0x40u},
- {0x03u, 0x20u},
- {0x04u, 0x02u},
+ {0x00u, 0x80u},
+ {0x01u, 0x2Au},
+ {0x04u, 0x20u},
{0x05u, 0x04u},
- {0x06u, 0x04u},
- {0x07u, 0x05u},
- {0x08u, 0x10u},
- {0x09u, 0x02u},
- {0x0Au, 0x01u},
- {0x0Bu, 0x20u},
- {0x0Cu, 0x02u},
- {0x0Eu, 0x10u},
- {0x0Fu, 0x08u},
- {0x11u, 0x02u},
- {0x13u, 0x44u},
- {0x15u, 0x05u},
- {0x16u, 0x02u},
- {0x17u, 0x20u},
- {0x18u, 0x80u},
- {0x1Au, 0x01u},
- {0x1Bu, 0xB0u},
- {0x1Fu, 0x40u},
+ {0x08u, 0x44u},
+ {0x09u, 0x08u},
+ {0x0Au, 0x48u},
+ {0x0Cu, 0x40u},
+ {0x0Du, 0x42u},
+ {0x0Eu, 0x20u},
+ {0x0Fu, 0x04u},
+ {0x11u, 0x01u},
+ {0x13u, 0x40u},
+ {0x14u, 0x01u},
+ {0x15u, 0x18u},
+ {0x16u, 0x01u},
+ {0x17u, 0x08u},
+ {0x19u, 0x02u},
+ {0x1Au, 0x0Au},
+ {0x1Du, 0x04u},
+ {0x1Eu, 0x08u},
+ {0x1Fu, 0x41u},
{0x20u, 0x04u},
- {0x22u, 0x08u},
- {0x24u, 0x0Au},
- {0x27u, 0x40u},
- {0x28u, 0x02u},
- {0x2Cu, 0x02u},
- {0x2Eu, 0x84u},
- {0x2Fu, 0x44u},
- {0x30u, 0x80u},
- {0x34u, 0x01u},
- {0x35u, 0x14u},
- {0x37u, 0x61u},
- {0x38u, 0x08u},
- {0x3Bu, 0x08u},
- {0x3Cu, 0x80u},
- {0x3Du, 0x21u},
- {0x3Fu, 0x08u},
- {0x40u, 0x08u},
- {0x42u, 0x08u},
- {0x45u, 0x18u},
- {0x46u, 0x40u},
- {0x4Du, 0x10u},
- {0x4Eu, 0x02u},
- {0x4Fu, 0x0Au},
- {0x55u, 0x20u},
- {0x56u, 0x28u},
- {0x57u, 0x02u},
- {0x79u, 0x10u},
- {0x7Au, 0x04u},
- {0x8Cu, 0x40u},
- {0x91u, 0xA0u},
- {0x92u, 0xE0u},
- {0x93u, 0x77u},
- {0x94u, 0x04u},
- {0x95u, 0x45u},
- {0x96u, 0x10u},
- {0x98u, 0x16u},
- {0x99u, 0x14u},
- {0x9Bu, 0x18u},
- {0x9Cu, 0x41u},
- {0x9Du, 0x62u},
- {0x9Eu, 0x86u},
- {0xA0u, 0x38u},
- {0xA1u, 0x0Fu},
- {0xA2u, 0x04u},
- {0xA4u, 0x03u},
- {0xA5u, 0x20u},
- {0xA6u, 0x08u},
- {0xA7u, 0x10u},
- {0xAFu, 0x01u},
- {0xB1u, 0x10u},
- {0xB3u, 0x01u},
- {0xC0u, 0xF5u},
- {0xC2u, 0x7Fu},
- {0xC4u, 0xFDu},
- {0xCAu, 0xF8u},
- {0xCCu, 0xF8u},
- {0xCEu, 0xF0u},
- {0xD0u, 0xE0u},
- {0xD2u, 0x30u},
- {0x02u, 0x30u},
- {0x06u, 0x06u},
- {0x0Du, 0x04u},
- {0x0Eu, 0x01u},
- {0x0Fu, 0x28u},
+ {0x22u, 0x40u},
+ {0x23u, 0x20u},
+ {0x25u, 0x01u},
+ {0x2Bu, 0x80u},
+ {0x36u, 0x82u},
+ {0x38u, 0x0Au},
+ {0x3Cu, 0x22u},
+ {0x44u, 0x02u},
+ {0x45u, 0x16u},
+ {0x4Du, 0x84u},
+ {0x56u, 0x18u},
+ {0x57u, 0x59u},
+ {0x65u, 0x04u},
+ {0x6Fu, 0x55u},
+ {0x76u, 0x02u},
+ {0x82u, 0x04u},
+ {0x86u, 0x01u},
+ {0x8Bu, 0xC0u},
+ {0x90u, 0x40u},
+ {0x92u, 0x40u},
+ {0x93u, 0x4Cu},
+ {0x94u, 0x24u},
+ {0x95u, 0x90u},
+ {0x96u, 0x80u},
+ {0x98u, 0x1Au},
+ {0x99u, 0x38u},
+ {0x9Au, 0x01u},
+ {0x9Cu, 0x64u},
+ {0x9Du, 0x41u},
+ {0x9Eu, 0x0Au},
+ {0x9Fu, 0x7Du},
+ {0xA0u, 0x41u},
+ {0xA1u, 0x42u},
+ {0xA2u, 0x81u},
+ {0xA3u, 0x22u},
+ {0xA5u, 0x35u},
+ {0xA6u, 0x10u},
+ {0xA7u, 0x41u},
+ {0xB0u, 0x08u},
+ {0xB5u, 0x41u},
+ {0xB6u, 0x20u},
+ {0xB7u, 0x40u},
+ {0xC0u, 0x6Fu},
+ {0xC2u, 0xFBu},
+ {0xC4u, 0xE9u},
+ {0xCAu, 0x01u},
+ {0xCCu, 0x90u},
+ {0xCEu, 0xA3u},
+ {0xD0u, 0xF0u},
+ {0xD2u, 0x10u},
+ {0xD8u, 0x40u},
+ {0xE4u, 0x06u},
+ {0xEAu, 0x40u},
+ {0xEEu, 0x08u},
+ {0x04u, 0x09u},
+ {0x05u, 0x04u},
+ {0x06u, 0x12u},
+ {0x0Au, 0x09u},
+ {0x0Eu, 0x30u},
{0x10u, 0x09u},
- {0x11u, 0x08u},
- {0x12u, 0x52u},
- {0x13u, 0x84u},
- {0x14u, 0x09u},
- {0x16u, 0x24u},
- {0x19u, 0x02u},
- {0x1Au, 0x49u},
- {0x1Bu, 0x41u},
+ {0x12u, 0x24u},
+ {0x15u, 0x02u},
+ {0x16u, 0x46u},
+ {0x1Au, 0x80u},
{0x1Eu, 0x08u},
+ {0x20u, 0x40u},
{0x21u, 0x01u},
- {0x23u, 0x12u},
- {0x2Du, 0x53u},
- {0x2Fu, 0xACu},
- {0x30u, 0x40u},
- {0x31u, 0x30u},
- {0x33u, 0xC0u},
- {0x34u, 0x07u},
- {0x36u, 0x38u},
- {0x37u, 0x0Fu},
- {0x3Eu, 0x01u},
- {0x3Fu, 0x45u},
+ {0x22u, 0x80u},
+ {0x26u, 0x01u},
+ {0x30u, 0x38u},
+ {0x31u, 0x02u},
+ {0x32u, 0x07u},
+ {0x33u, 0x04u},
+ {0x34u, 0xC0u},
+ {0x35u, 0x01u},
+ {0x3Eu, 0x10u},
+ {0x3Fu, 0x15u},
{0x58u, 0x04u},
{0x59u, 0x04u},
- {0x5Bu, 0x04u},
{0x5Cu, 0x09u},
{0x5Fu, 0x01u},
- {0x80u, 0x34u},
- {0x81u, 0x09u},
- {0x83u, 0x12u},
- {0x84u, 0x07u},
- {0x86u, 0x48u},
- {0x87u, 0x01u},
- {0x88u, 0x40u},
- {0x8Au, 0x3Du},
- {0x8Bu, 0x80u},
- {0x8Fu, 0x70u},
- {0x90u, 0x14u},
- {0x96u, 0x34u},
- {0x97u, 0x08u},
- {0x98u, 0x20u},
- {0x9Au, 0x02u},
- {0x9Bu, 0x06u},
- {0x9Cu, 0xC0u},
- {0xA0u, 0x34u},
- {0xA4u, 0x14u},
- {0xA6u, 0x20u},
- {0xA7u, 0x09u},
- {0xA8u, 0x03u},
- {0xA9u, 0x09u},
- {0xAAu, 0xB8u},
- {0xABu, 0x24u},
- {0xACu, 0x34u},
- {0xADu, 0x40u},
- {0xAFu, 0x80u},
- {0xB2u, 0x39u},
- {0xB3u, 0x07u},
- {0xB4u, 0x07u},
- {0xB5u, 0xC0u},
- {0xB6u, 0xC1u},
- {0xB7u, 0x38u},
- {0xB8u, 0x80u},
- {0xBAu, 0x30u},
- {0xBFu, 0x10u},
+ {0x80u, 0xD6u},
+ {0x81u, 0x0Du},
+ {0x84u, 0xD2u},
+ {0x85u, 0x22u},
+ {0x86u, 0x04u},
+ {0x87u, 0x18u},
+ {0x88u, 0x31u},
+ {0x89u, 0x11u},
+ {0x8Au, 0x0Eu},
+ {0x8Bu, 0x22u},
+ {0x8Du, 0x60u},
+ {0x90u, 0x29u},
+ {0x91u, 0x02u},
+ {0x92u, 0x16u},
+ {0x93u, 0x0Du},
+ {0x94u, 0x17u},
+ {0x95u, 0x0Du},
+ {0x96u, 0x28u},
+ {0x98u, 0x22u},
+ {0x99u, 0x0Du},
+ {0x9Au, 0x10u},
+ {0x9Du, 0x0Du},
+ {0x9Eu, 0x80u},
+ {0xA0u, 0x06u},
+ {0xA1u, 0x0Du},
+ {0xA2u, 0xD0u},
+ {0xA4u, 0xD0u},
+ {0xA6u, 0x06u},
+ {0xA8u, 0x04u},
+ {0xACu, 0xD6u},
+ {0xADu, 0x12u},
+ {0xAFu, 0x44u},
+ {0xB0u, 0x0Fu},
+ {0xB1u, 0x0Fu},
+ {0xB2u, 0x80u},
+ {0xB4u, 0x30u},
+ {0xB6u, 0x40u},
+ {0xB7u, 0x70u},
+ {0xB8u, 0x02u},
+ {0xB9u, 0x80u},
+ {0xBAu, 0x20u},
+ {0xBBu, 0x02u},
+ {0xBEu, 0x44u},
+ {0xD4u, 0x40u},
+ {0xD6u, 0x04u},
{0xD8u, 0x04u},
{0xD9u, 0x04u},
- {0xDCu, 0x90u},
+ {0xDBu, 0x04u},
{0xDFu, 0x01u},
- {0x00u, 0x80u},
- {0x03u, 0xA0u},
- {0x05u, 0x14u},
- {0x06u, 0x80u},
- {0x08u, 0x10u},
- {0x09u, 0x01u},
- {0x0Au, 0x01u},
- {0x0Bu, 0x20u},
- {0x0Cu, 0x01u},
- {0x0Du, 0x20u},
- {0x0Eu, 0x12u},
- {0x0Fu, 0x01u},
- {0x15u, 0x05u},
- {0x16u, 0x06u},
- {0x1Bu, 0xA1u},
- {0x1Du, 0x1Cu},
+ {0x01u, 0x28u},
+ {0x03u, 0x02u},
+ {0x04u, 0x20u},
+ {0x07u, 0x50u},
+ {0x08u, 0x08u},
+ {0x09u, 0x20u},
+ {0x0Au, 0x61u},
+ {0x0Du, 0x02u},
+ {0x0Eu, 0x28u},
+ {0x0Fu, 0x03u},
+ {0x10u, 0x60u},
+ {0x15u, 0x01u},
+ {0x16u, 0x0Au},
+ {0x17u, 0x05u},
+ {0x1Au, 0x28u},
+ {0x1Bu, 0x02u},
+ {0x1Cu, 0x40u},
+ {0x1Du, 0x16u},
{0x1Eu, 0x0Au},
- {0x21u, 0x41u},
- {0x22u, 0x84u},
- {0x24u, 0x08u},
+ {0x1Fu, 0x01u},
+ {0x21u, 0x08u},
+ {0x22u, 0x21u},
{0x25u, 0x40u},
- {0x27u, 0x30u},
- {0x2Bu, 0x82u},
- {0x2Cu, 0x10u},
- {0x2Du, 0x40u},
- {0x2Fu, 0x06u},
- {0x32u, 0x01u},
- {0x33u, 0x20u},
- {0x37u, 0x24u},
- {0x38u, 0x80u},
- {0x3Du, 0x92u},
- {0x3Eu, 0x44u},
- {0x68u, 0x10u},
- {0x69u, 0x10u},
- {0x6Au, 0x02u},
- {0x6Bu, 0x09u},
- {0x70u, 0x68u},
- {0x71u, 0x02u},
- {0x72u, 0x28u},
- {0x80u, 0x04u},
- {0x85u, 0x01u},
- {0x8Cu, 0x02u},
- {0x92u, 0xA5u},
- {0x93u, 0x7Eu},
+ {0x26u, 0x02u},
+ {0x29u, 0x02u},
+ {0x2Du, 0x01u},
+ {0x2Fu, 0x01u},
+ {0x30u, 0x08u},
+ {0x36u, 0x02u},
+ {0x37u, 0x54u},
+ {0x3Au, 0x04u},
+ {0x3Du, 0xA8u},
+ {0x3Eu, 0x02u},
+ {0x5Cu, 0x02u},
+ {0x5Eu, 0x02u},
+ {0x64u, 0x80u},
+ {0x65u, 0x04u},
+ {0x66u, 0x20u},
+ {0x67u, 0x01u},
+ {0x6Du, 0x40u},
+ {0x6Fu, 0x28u},
+ {0x80u, 0x80u},
+ {0x8Au, 0x04u},
+ {0x8Fu, 0x08u},
+ {0x92u, 0x41u},
+ {0x93u, 0x4Cu},
{0x94u, 0x04u},
- {0x95u, 0x55u},
- {0x96u, 0x18u},
- {0x98u, 0x14u},
- {0x9Bu, 0x04u},
- {0x9Cu, 0x40u},
- {0x9Du, 0x76u},
- {0x9Eu, 0x2Eu},
- {0x9Fu, 0x29u},
- {0xA0u, 0x40u},
- {0xA1u, 0x05u},
- {0xA4u, 0x13u},
- {0xA5u, 0x40u},
- {0xA6u, 0x88u},
- {0xA7u, 0x10u},
- {0xA9u, 0x08u},
- {0xABu, 0x80u},
- {0xAEu, 0x40u},
- {0xB0u, 0x01u},
- {0xB2u, 0x10u},
- {0xB4u, 0x02u},
- {0xB5u, 0x01u},
- {0xB7u, 0x20u},
- {0xC0u, 0x7Du},
+ {0x95u, 0x90u},
+ {0x96u, 0x82u},
+ {0x98u, 0x10u},
+ {0x99u, 0x2Au},
+ {0x9Au, 0x05u},
+ {0x9Cu, 0x24u},
+ {0x9Du, 0x41u},
+ {0x9Fu, 0x28u},
+ {0xA0u, 0x61u},
+ {0xA2u, 0x80u},
+ {0xA5u, 0x08u},
+ {0xA6u, 0x20u},
+ {0xA7u, 0x20u},
+ {0xAAu, 0x04u},
+ {0xB5u, 0x02u},
+ {0xB7u, 0x48u},
+ {0xC0u, 0x77u},
{0xC2u, 0xFFu},
- {0xC4u, 0xF0u},
- {0xCAu, 0x79u},
- {0xCCu, 0x65u},
- {0xCEu, 0xF8u},
- {0xE4u, 0x03u},
- {0xE8u, 0x40u},
+ {0xC4u, 0xFCu},
+ {0xCAu, 0x91u},
+ {0xCCu, 0xF2u},
+ {0xCEu, 0xF2u},
+ {0xD8u, 0xF0u},
+ {0xE2u, 0x18u},
{0xEAu, 0x01u},
- {0x03u, 0xFFu},
- {0x04u, 0x11u},
- {0x06u, 0x02u},
- {0x08u, 0x12u},
- {0x09u, 0x30u},
- {0x0Au, 0x08u},
- {0x0Bu, 0xC0u},
- {0x0Du, 0x05u},
- {0x0Fu, 0x0Au},
- {0x10u, 0x0Du},
- {0x11u, 0x90u},
- {0x13u, 0x60u},
- {0x14u, 0x0Du},
- {0x17u, 0xFFu},
- {0x18u, 0x02u},
- {0x19u, 0x03u},
- {0x1Au, 0x0Du},
- {0x1Bu, 0x0Cu},
- {0x1Fu, 0xFFu},
- {0x20u, 0x0Du},
- {0x21u, 0x09u},
- {0x23u, 0x06u},
- {0x24u, 0x0Du},
- {0x28u, 0x12u},
+ {0xEEu, 0x04u},
+ {0x00u, 0xFFu},
+ {0x04u, 0x50u},
+ {0x05u, 0x05u},
+ {0x06u, 0xA0u},
+ {0x07u, 0x0Au},
+ {0x08u, 0x30u},
+ {0x09u, 0x06u},
+ {0x0Au, 0xC0u},
+ {0x0Bu, 0x09u},
+ {0x0Cu, 0x90u},
+ {0x0Du, 0x03u},
+ {0x0Eu, 0x60u},
+ {0x0Fu, 0x0Cu},
+ {0x11u, 0xFFu},
+ {0x14u, 0xFFu},
+ {0x15u, 0x30u},
+ {0x17u, 0xC0u},
+ {0x18u, 0x05u},
+ {0x1Au, 0x0Au},
+ {0x1Bu, 0xFFu},
+ {0x1Du, 0x60u},
+ {0x1Fu, 0x90u},
+ {0x20u, 0x03u},
+ {0x21u, 0x0Fu},
+ {0x22u, 0x0Cu},
+ {0x23u, 0xF0u},
+ {0x24u, 0x09u},
+ {0x26u, 0x06u},
+ {0x27u, 0xFFu},
{0x29u, 0x50u},
- {0x2Au, 0x04u},
+ {0x2Au, 0xFFu},
{0x2Bu, 0xA0u},
- {0x2Cu, 0x0Du},
- {0x2Du, 0x0Fu},
- {0x2Fu, 0xF0u},
- {0x30u, 0x10u},
- {0x33u, 0xFFu},
- {0x34u, 0x0Fu},
- {0x3Au, 0x20u},
- {0x3Eu, 0x01u},
- {0x3Fu, 0x04u},
+ {0x2Cu, 0x0Fu},
+ {0x2Eu, 0xF0u},
+ {0x36u, 0xFFu},
+ {0x37u, 0xFFu},
+ {0x3Eu, 0x40u},
+ {0x3Fu, 0x40u},
{0x58u, 0x04u},
{0x59u, 0x04u},
- {0x5Bu, 0x04u},
{0x5Fu, 0x01u},
- {0x80u, 0xFFu},
- {0x84u, 0x03u},
- {0x85u, 0x5Bu},
- {0x86u, 0x0Cu},
- {0x87u, 0x24u},
- {0x88u, 0x30u},
- {0x8Au, 0xC0u},
- {0x8Bu, 0x01u},
- {0x8Cu, 0x90u},
- {0x8Eu, 0x60u},
- {0x90u, 0x05u},
- {0x91u, 0x58u},
- {0x92u, 0x0Au},
- {0x93u, 0x24u},
- {0x99u, 0x40u},
- {0x9Bu, 0x37u},
- {0x9Cu, 0x09u},
- {0x9Du, 0x0Cu},
- {0x9Eu, 0x06u},
- {0x9Fu, 0x40u},
- {0xA0u, 0xFFu},
- {0xA1u, 0x03u},
- {0xA3u, 0x0Cu},
- {0xA4u, 0x50u},
- {0xA6u, 0xA0u},
- {0xA7u, 0x1Fu},
- {0xA9u, 0x02u},
- {0xAAu, 0xFFu},
- {0xACu, 0x0Fu},
- {0xAEu, 0xF0u},
- {0xB2u, 0xFFu},
- {0xB3u, 0x1Fu},
- {0xB5u, 0x20u},
- {0xB7u, 0x40u},
+ {0x81u, 0x09u},
+ {0x83u, 0x24u},
+ {0x84u, 0x09u},
+ {0x86u, 0x12u},
+ {0x87u, 0x46u},
+ {0x8Bu, 0x08u},
+ {0x8Du, 0x40u},
+ {0x8Eu, 0x06u},
+ {0x8Fu, 0x80u},
+ {0x90u, 0x09u},
+ {0x92u, 0x24u},
+ {0x96u, 0x80u},
+ {0x9Au, 0x70u},
+ {0x9Bu, 0x30u},
+ {0xA2u, 0x09u},
+ {0xA3u, 0x01u},
+ {0xA5u, 0x09u},
+ {0xA6u, 0x01u},
+ {0xA7u, 0x12u},
+ {0xAAu, 0x08u},
+ {0xABu, 0x09u},
+ {0xACu, 0x40u},
+ {0xAEu, 0x80u},
+ {0xAFu, 0x80u},
+ {0xB0u, 0x07u},
+ {0xB1u, 0xC0u},
+ {0xB2u, 0xC0u},
+ {0xB3u, 0x07u},
+ {0xB4u, 0x38u},
+ {0xB5u, 0x38u},
{0xBEu, 0x04u},
- {0xBFu, 0x50u},
+ {0xBFu, 0x01u},
{0xD8u, 0x04u},
{0xD9u, 0x04u},
{0xDBu, 0x04u},
- {0xDCu, 0x90u},
+ {0xDCu, 0x99u},
{0xDFu, 0x01u},
- {0x00u, 0x22u},
- {0x02u, 0x20u},
- {0x03u, 0x01u},
- {0x05u, 0x14u},
- {0x08u, 0x40u},
- {0x09u, 0x08u},
- {0x0Au, 0x40u},
- {0x0Bu, 0x20u},
- {0x0Cu, 0x02u},
- {0x0Du, 0x20u},
- {0x0Eu, 0x10u},
- {0x10u, 0x04u},
- {0x11u, 0x40u},
- {0x12u, 0x80u},
- {0x13u, 0x08u},
- {0x15u, 0x05u},
- {0x16u, 0x06u},
- {0x1Au, 0x20u},
- {0x1Du, 0x20u},
- {0x1Fu, 0x01u},
- {0x20u, 0x18u},
- {0x21u, 0x0Cu},
- {0x23u, 0x01u},
- {0x25u, 0x04u},
- {0x29u, 0x01u},
- {0x2Au, 0x10u},
- {0x2Bu, 0x20u},
- {0x2Cu, 0x40u},
- {0x2Du, 0x50u},
- {0x30u, 0x10u},
- {0x31u, 0x80u},
- {0x32u, 0x02u},
- {0x33u, 0x90u},
- {0x34u, 0x04u},
- {0x36u, 0xA4u},
- {0x37u, 0x21u},
- {0x38u, 0x20u},
- {0x39u, 0x08u},
- {0x3Bu, 0x08u},
- {0x3Cu, 0x22u},
- {0x3Du, 0x80u},
- {0x3Eu, 0x40u},
- {0x58u, 0xA1u},
- {0x59u, 0x08u},
+ {0x00u, 0x40u},
+ {0x01u, 0x08u},
+ {0x02u, 0x01u},
+ {0x05u, 0x41u},
+ {0x06u, 0x20u},
+ {0x07u, 0x08u},
+ {0x08u, 0x14u},
+ {0x0Au, 0x44u},
+ {0x0Eu, 0x20u},
+ {0x0Fu, 0x04u},
+ {0x11u, 0x46u},
+ {0x13u, 0x10u},
+ {0x15u, 0x88u},
+ {0x16u, 0x88u},
+ {0x18u, 0x60u},
+ {0x1Au, 0x04u},
+ {0x1Cu, 0x02u},
+ {0x20u, 0x20u},
+ {0x21u, 0x24u},
+ {0x23u, 0x84u},
+ {0x26u, 0x80u},
+ {0x28u, 0x80u},
+ {0x29u, 0x68u},
+ {0x2Du, 0x10u},
+ {0x2Eu, 0x28u},
+ {0x2Fu, 0x60u},
+ {0x31u, 0x20u},
+ {0x34u, 0x20u},
+ {0x35u, 0x41u},
+ {0x36u, 0x10u},
+ {0x37u, 0x08u},
+ {0x39u, 0xCAu},
+ {0x3Bu, 0xA8u},
+ {0x3Cu, 0x60u},
+ {0x3Eu, 0x80u},
+ {0x3Fu, 0x04u},
+ {0x59u, 0x04u},
+ {0x5Au, 0x20u},
+ {0x5Bu, 0x41u},
{0x63u, 0x01u},
- {0x6Cu, 0x10u},
- {0x6Eu, 0x88u},
- {0x6Fu, 0x08u},
- {0x82u, 0x04u},
- {0x87u, 0x08u},
- {0x92u, 0x85u},
- {0x93u, 0x54u},
- {0x94u, 0x14u},
- {0x95u, 0x48u},
- {0x96u, 0x08u},
- {0x98u, 0xA0u},
- {0x9Au, 0x10u},
- {0x9Bu, 0x14u},
- {0x9Cu, 0x42u},
- {0x9Du, 0x62u},
- {0x9Eu, 0x28u},
- {0x9Fu, 0x01u},
- {0xA0u, 0x40u},
- {0xA1u, 0x81u},
- {0xA2u, 0x02u},
- {0xA4u, 0x04u},
- {0xA6u, 0x0Cu},
- {0xA7u, 0x30u},
- {0xA9u, 0x08u},
- {0xABu, 0x08u},
- {0xAEu, 0x04u},
- {0xB3u, 0x08u},
- {0xB6u, 0x01u},
- {0xC0u, 0x6Fu},
- {0xC2u, 0x79u},
+ {0x78u, 0x08u},
+ {0x7Au, 0x20u},
+ {0x83u, 0xA0u},
+ {0x8Cu, 0x10u},
+ {0x8Eu, 0x10u},
+ {0x8Fu, 0x80u},
+ {0x91u, 0x06u},
+ {0x92u, 0x41u},
+ {0x93u, 0x71u},
+ {0x94u, 0x04u},
+ {0x96u, 0x82u},
+ {0x98u, 0x80u},
+ {0x99u, 0x2Cu},
+ {0x9Bu, 0x01u},
+ {0x9Cu, 0x08u},
+ {0x9Fu, 0x20u},
+ {0xA0u, 0x60u},
+ {0xA1u, 0x01u},
+ {0xA3u, 0x88u},
+ {0xA5u, 0x08u},
+ {0xA7u, 0x20u},
+ {0xABu, 0x02u},
+ {0xAEu, 0x40u},
+ {0xB4u, 0x40u},
+ {0xB5u, 0x21u},
+ {0xC0u, 0xF5u},
+ {0xC2u, 0x6Eu},
{0xC4u, 0xFFu},
- {0xCAu, 0xB7u},
- {0xCCu, 0xFDu},
- {0xCEu, 0xB6u},
+ {0xCAu, 0xEFu},
+ {0xCCu, 0xF4u},
+ {0xCEu, 0x7Fu},
{0xD6u, 0x0Fu},
{0xD8u, 0x08u},
- {0xEAu, 0x01u},
- {0xECu, 0x08u},
- {0x07u, 0x10u},
- {0x0Bu, 0x02u},
- {0x0Du, 0x29u},
- {0x0Fu, 0x52u},
- {0x13u, 0x40u},
- {0x14u, 0x02u},
- {0x18u, 0x04u},
- {0x1Fu, 0x20u},
- {0x23u, 0x01u},
- {0x27u, 0x08u},
- {0x2Cu, 0x01u},
- {0x2Du, 0x04u},
- {0x30u, 0x04u},
- {0x31u, 0x04u},
- {0x32u, 0x01u},
- {0x33u, 0x18u},
- {0x35u, 0x60u},
- {0x36u, 0x02u},
- {0x37u, 0x03u},
- {0x3Eu, 0x45u},
- {0x3Fu, 0x55u},
- {0x40u, 0x23u},
- {0x41u, 0x05u},
- {0x42u, 0x60u},
- {0x45u, 0xE2u},
- {0x46u, 0xDCu},
- {0x47u, 0x0Fu},
+ {0xE0u, 0x01u},
+ {0xEAu, 0x0Cu},
+ {0xEEu, 0x10u},
+ {0x01u, 0x5Bu},
+ {0x03u, 0x24u},
+ {0x04u, 0x01u},
+ {0x08u, 0x08u},
+ {0x09u, 0x58u},
+ {0x0Au, 0x12u},
+ {0x0Bu, 0xA4u},
+ {0x0Cu, 0x40u},
+ {0x11u, 0x02u},
+ {0x14u, 0x0Bu},
+ {0x15u, 0x0Cu},
+ {0x16u, 0x24u},
+ {0x17u, 0x40u},
+ {0x1Bu, 0x01u},
+ {0x1Eu, 0x3Fu},
+ {0x20u, 0x80u},
+ {0x23u, 0x1Fu},
+ {0x26u, 0x20u},
+ {0x29u, 0x40u},
+ {0x2Bu, 0xB7u},
+ {0x2Cu, 0x34u},
+ {0x2Du, 0x03u},
+ {0x2Eu, 0x0Bu},
+ {0x2Fu, 0x0Cu},
+ {0x30u, 0x80u},
+ {0x31u, 0x1Fu},
+ {0x32u, 0x07u},
+ {0x33u, 0x80u},
+ {0x34u, 0x38u},
+ {0x35u, 0x20u},
+ {0x36u, 0x40u},
+ {0x37u, 0x40u},
+ {0x3Eu, 0x41u},
+ {0x3Fu, 0x54u},
+ {0x40u, 0x64u},
+ {0x41u, 0x03u},
+ {0x42u, 0x20u},
+ {0x45u, 0xDCu},
+ {0x46u, 0x2Fu},
+ {0x47u, 0x0Eu},
{0x48u, 0x1Fu},
{0x49u, 0xFFu},
{0x4Au, 0xFFu},
{0x59u, 0x04u},
{0x5Au, 0x04u},
{0x5Bu, 0x04u},
+ {0x5Cu, 0x99u},
{0x5Du, 0x09u},
{0x5Fu, 0x01u},
{0x62u, 0xC0u},
{0x68u, 0x40u},
{0x69u, 0x40u},
{0x6Eu, 0x08u},
- {0x89u, 0x26u},
- {0x8Bu, 0x19u},
- {0x91u, 0x19u},
- {0x93u, 0x24u},
- {0x95u, 0x08u},
- {0x99u, 0x01u},
- {0x9Bu, 0x12u},
- {0xA7u, 0x3Fu},
- {0xABu, 0x04u},
- {0xB1u, 0x38u},
- {0xB3u, 0x07u},
- {0xD9u, 0x04u},
- {0xDCu, 0x90u},
- {0xDFu, 0x01u},
- {0x08u, 0x10u},
- {0x09u, 0x08u},
- {0x12u, 0x01u},
- {0x18u, 0x01u},
- {0x19u, 0x05u},
- {0x20u, 0x20u},
- {0x21u, 0x02u},
- {0x22u, 0x80u},
- {0x23u, 0x08u},
- {0x25u, 0x01u},
- {0x26u, 0x03u},
- {0x27u, 0x10u},
- {0x28u, 0x02u},
- {0x29u, 0x02u},
- {0x2Bu, 0x10u},
- {0x2Fu, 0x24u},
- {0x30u, 0x40u},
- {0x33u, 0x01u},
- {0x36u, 0x06u},
- {0x37u, 0x10u},
- {0x39u, 0x40u},
- {0x3Au, 0x28u},
- {0x3Cu, 0x10u},
- {0x41u, 0x04u},
- {0x43u, 0x10u},
- {0x48u, 0x04u},
- {0x4Au, 0x41u},
- {0x4Bu, 0x08u},
- {0x51u, 0x80u},
- {0x52u, 0x10u},
- {0x53u, 0x08u},
- {0x59u, 0x65u},
- {0x60u, 0x05u},
- {0x61u, 0x02u},
- {0x62u, 0x08u},
+ {0x01u, 0x20u},
+ {0x03u, 0x22u},
+ {0x0Au, 0x10u},
+ {0x0Bu, 0x02u},
+ {0x11u, 0x01u},
+ {0x12u, 0x22u},
+ {0x18u, 0x60u},
+ {0x19u, 0x78u},
+ {0x1Au, 0x10u},
+ {0x21u, 0x11u},
+ {0x22u, 0x06u},
+ {0x23u, 0x01u},
+ {0x29u, 0x12u},
+ {0x2Au, 0x40u},
+ {0x31u, 0x05u},
+ {0x33u, 0x21u},
+ {0x38u, 0x20u},
+ {0x39u, 0x02u},
+ {0x41u, 0x11u},
+ {0x42u, 0x50u},
+ {0x49u, 0x15u},
+ {0x50u, 0x48u},
+ {0x52u, 0x20u},
+ {0x53u, 0x88u},
+ {0x58u, 0x08u},
+ {0x5Au, 0x82u},
+ {0x5Bu, 0x20u},
+ {0x5Cu, 0x80u},
+ {0x5Du, 0x40u},
+ {0x60u, 0x44u},
+ {0x61u, 0x48u},
{0x68u, 0x40u},
- {0x6Au, 0x84u},
- {0x6Bu, 0x04u},
+ {0x69u, 0x44u},
+ {0x6Au, 0x20u},
+ {0x70u, 0x20u},
{0x72u, 0x01u},
- {0x73u, 0x54u},
- {0x78u, 0x20u},
- {0x7Bu, 0x08u},
- {0x84u, 0x90u},
- {0x86u, 0x40u},
- {0x88u, 0x10u},
- {0x8Au, 0x80u},
- {0xC2u, 0x06u},
- {0xC4u, 0x01u},
- {0xCAu, 0x6Bu},
- {0xCCu, 0xE9u},
- {0xCEu, 0x2Eu},
- {0xD0u, 0x06u},
- {0xD2u, 0x0Cu},
+ {0x73u, 0x50u},
+ {0x7Eu, 0x10u},
+ {0x7Fu, 0x10u},
+ {0x80u, 0x08u},
+ {0x89u, 0x01u},
+ {0x8Au, 0x04u},
+ {0x8Du, 0x02u},
+ {0x8Fu, 0x01u},
+ {0xC0u, 0x07u},
+ {0xC2u, 0x05u},
+ {0xC4u, 0x0Du},
+ {0xCAu, 0x0Du},
+ {0xCCu, 0x07u},
+ {0xCEu, 0x05u},
+ {0xD0u, 0x07u},
+ {0xD2u, 0x04u},
{0xD6u, 0x0Fu},
{0xD8u, 0x0Fu},
- {0xE0u, 0x08u},
- {0xE2u, 0x20u},
- {0xE6u, 0x14u},
+ {0xE0u, 0x40u},
+ {0xE2u, 0x80u},
+ {0xE6u, 0x01u},
+ {0xECu, 0x40u},
{0xEEu, 0x02u},
- {0xB8u, 0x80u},
- {0xBEu, 0x40u},
- {0xD8u, 0x04u},
- {0xDFu, 0x01u},
- {0x1Au, 0x02u},
- {0x86u, 0x01u},
- {0xEAu, 0x03u},
- {0xECu, 0x80u},
+ {0xE2u, 0x20u},
{0xEEu, 0x08u},
- {0x03u, 0x80u},
- {0x04u, 0x01u},
- {0x05u, 0xD2u},
- {0x06u, 0x5Eu},
- {0x07u, 0x04u},
- {0x08u, 0x35u},
- {0x09u, 0xD0u},
- {0x0Au, 0x42u},
- {0x0Bu, 0x06u},
- {0x0Du, 0xD6u},
- {0x11u, 0x22u},
- {0x13u, 0x10u},
- {0x14u, 0x04u},
- {0x15u, 0x17u},
- {0x16u, 0x03u},
- {0x17u, 0x28u},
- {0x19u, 0x31u},
- {0x1Au, 0x08u},
- {0x1Bu, 0x0Eu},
- {0x21u, 0xD6u},
- {0x24u, 0x43u},
- {0x25u, 0x29u},
- {0x26u, 0x2Cu},
- {0x27u, 0x16u},
- {0x29u, 0x04u},
- {0x2Du, 0x06u},
- {0x2Fu, 0xD0u},
- {0x30u, 0x40u},
- {0x31u, 0x40u},
- {0x32u, 0x07u},
- {0x33u, 0x80u},
- {0x34u, 0x38u},
- {0x35u, 0x0Fu},
- {0x37u, 0x30u},
- {0x39u, 0x20u},
- {0x3Au, 0x08u},
- {0x3Bu, 0x80u},
+ {0x00u, 0xC0u},
+ {0x01u, 0x64u},
+ {0x02u, 0x02u},
+ {0x06u, 0x9Fu},
+ {0x07u, 0xF5u},
+ {0x08u, 0x80u},
+ {0x09u, 0x07u},
+ {0x0Bu, 0x90u},
+ {0x0Cu, 0xC0u},
+ {0x0Du, 0x83u},
+ {0x0Eu, 0x01u},
+ {0x0Fu, 0x70u},
+ {0x11u, 0x64u},
+ {0x12u, 0xFFu},
+ {0x14u, 0x1Fu},
+ {0x16u, 0x20u},
+ {0x17u, 0x64u},
+ {0x18u, 0x7Fu},
+ {0x19u, 0x24u},
+ {0x1Au, 0x80u},
+ {0x1Du, 0x64u},
+ {0x1Eu, 0x60u},
+ {0x20u, 0x90u},
+ {0x21u, 0x08u},
+ {0x22u, 0x40u},
+ {0x24u, 0xC0u},
+ {0x25u, 0x24u},
+ {0x26u, 0x08u},
+ {0x27u, 0x40u},
+ {0x28u, 0xC0u},
+ {0x29u, 0x40u},
+ {0x2Au, 0x04u},
+ {0x2Bu, 0x02u},
+ {0x2Du, 0x08u},
+ {0x30u, 0xFFu},
+ {0x31u, 0x80u},
+ {0x33u, 0x07u},
+ {0x35u, 0x71u},
+ {0x37u, 0x08u},
+ {0x39u, 0x80u},
+ {0x3Bu, 0x0Cu},
{0x3Eu, 0x01u},
- {0x3Fu, 0x05u},
+ {0x3Fu, 0x01u},
{0x54u, 0x09u},
{0x56u, 0x04u},
{0x58u, 0x04u},
{0x59u, 0x04u},
{0x5Bu, 0x04u},
{0x5Fu, 0x01u},
- {0x82u, 0x30u},
- {0x86u, 0x40u},
- {0x8Au, 0x80u},
- {0x8Cu, 0x40u},
- {0x8Du, 0x0Fu},
- {0x8Eu, 0x80u},
- {0x8Fu, 0xF0u},
- {0x91u, 0x30u},
- {0x92u, 0x01u},
- {0x93u, 0xC0u},
- {0x94u, 0x09u},
+ {0x86u, 0x01u},
+ {0x90u, 0x04u},
+ {0x92u, 0x43u},
+ {0x94u, 0x88u},
{0x95u, 0x50u},
- {0x96u, 0x24u},
+ {0x96u, 0x03u},
{0x97u, 0xA0u},
{0x99u, 0x60u},
- {0x9Au, 0x09u},
+ {0x9Au, 0xECu},
{0x9Bu, 0x90u},
- {0x9Du, 0x03u},
- {0x9Eu, 0x06u},
- {0x9Fu, 0x0Cu},
- {0xA0u, 0x09u},
- {0xA1u, 0x05u},
- {0xA2u, 0x12u},
- {0xA3u, 0x0Au},
- {0xA5u, 0x06u},
- {0xA7u, 0x09u},
- {0xAAu, 0x08u},
- {0xB0u, 0x38u},
- {0xB4u, 0xC0u},
- {0xB6u, 0x07u},
- {0xB7u, 0xFFu},
- {0xBEu, 0x10u},
- {0xBFu, 0x40u},
+ {0x9Cu, 0xE0u},
+ {0x9Du, 0x0Fu},
+ {0x9Fu, 0xF0u},
+ {0xA1u, 0x03u},
+ {0xA3u, 0x0Cu},
+ {0xA5u, 0x05u},
+ {0xA6u, 0x12u},
+ {0xA7u, 0x0Au},
+ {0xA8u, 0x21u},
+ {0xA9u, 0x06u},
+ {0xAAu, 0x02u},
+ {0xABu, 0x09u},
+ {0xADu, 0x30u},
+ {0xAFu, 0xC0u},
+ {0xB2u, 0x10u},
+ {0xB3u, 0xFFu},
+ {0xB4u, 0x0Fu},
+ {0xB6u, 0xE0u},
+ {0xBEu, 0x40u},
+ {0xBFu, 0x04u},
{0xD8u, 0x04u},
{0xD9u, 0x04u},
- {0xDCu, 0x09u},
+ {0xDBu, 0x04u},
{0xDFu, 0x01u},
- {0x00u, 0x20u},
- {0x01u, 0x42u},
- {0x03u, 0x10u},
- {0x05u, 0x14u},
- {0x08u, 0x50u},
- {0x0Au, 0x82u},
- {0x0Bu, 0x20u},
+ {0x01u, 0x08u},
+ {0x05u, 0x10u},
+ {0x06u, 0x12u},
+ {0x07u, 0x40u},
+ {0x09u, 0x46u},
+ {0x0Au, 0x04u},
+ {0x0Du, 0x82u},
{0x0Eu, 0x28u},
- {0x11u, 0x02u},
- {0x13u, 0x10u},
- {0x17u, 0x04u},
- {0x19u, 0x02u},
- {0x1Au, 0x0Au},
- {0x1Cu, 0x40u},
- {0x1Eu, 0x28u},
- {0x1Fu, 0x04u},
- {0x20u, 0x02u},
- {0x23u, 0x02u},
- {0x25u, 0x10u},
- {0x26u, 0x0Bu},
- {0x27u, 0x05u},
+ {0x11u, 0x20u},
+ {0x12u, 0x10u},
+ {0x16u, 0x08u},
+ {0x17u, 0x15u},
+ {0x19u, 0x08u},
+ {0x1Au, 0x06u},
+ {0x1Eu, 0x40u},
+ {0x22u, 0x08u},
+ {0x24u, 0x20u},
+ {0x25u, 0x94u},
+ {0x26u, 0x14u},
+ {0x27u, 0x88u},
+ {0x28u, 0x18u},
{0x29u, 0x02u},
- {0x2Bu, 0x10u},
- {0x2Cu, 0x02u},
- {0x2Du, 0x11u},
- {0x2Eu, 0x28u},
- {0x30u, 0x28u},
- {0x31u, 0x02u},
- {0x33u, 0x80u},
- {0x35u, 0x14u},
- {0x37u, 0x01u},
- {0x39u, 0x40u},
- {0x3Cu, 0x80u},
- {0x3Eu, 0x14u},
- {0x3Fu, 0x02u},
- {0x43u, 0x0Cu},
- {0x45u, 0x10u},
- {0x46u, 0x08u},
- {0x5Cu, 0x48u},
- {0x5Du, 0x10u},
+ {0x2Au, 0x80u},
+ {0x2Du, 0x20u},
+ {0x2Eu, 0x48u},
+ {0x2Fu, 0x88u},
+ {0x31u, 0x28u},
+ {0x32u, 0x40u},
+ {0x35u, 0x10u},
+ {0x37u, 0x45u},
+ {0x3Cu, 0x40u},
+ {0x3Du, 0x28u},
+ {0x3Eu, 0x02u},
+ {0x5Du, 0x24u},
{0x5Eu, 0x02u},
+ {0x5Fu, 0x80u},
{0x67u, 0x42u},
- {0x6Cu, 0x01u},
- {0x6Du, 0x40u},
- {0x91u, 0xA0u},
- {0x92u, 0xE0u},
- {0x93u, 0x33u},
- {0x95u, 0x45u},
- {0x96u, 0x14u},
- {0x98u, 0x1Cu},
- {0x99u, 0x14u},
- {0x9Au, 0x20u},
- {0x9Bu, 0x18u},
- {0x9Cu, 0x40u},
- {0x9Du, 0x62u},
- {0x9Eu, 0x02u},
- {0x9Fu, 0x05u},
- {0xA0u, 0x38u},
- {0xA1u, 0x07u},
- {0xA3u, 0x97u},
- {0xA4u, 0x43u},
- {0xA5u, 0x10u},
- {0xA6u, 0x02u},
- {0xB2u, 0x40u},
- {0xB4u, 0x80u},
- {0xC0u, 0x6Fu},
- {0xC2u, 0x6Fu},
- {0xC4u, 0x2Au},
- {0xCAu, 0xF3u},
- {0xCCu, 0xEFu},
- {0xCEu, 0xF8u},
+ {0x69u, 0x80u},
+ {0x6Au, 0x80u},
+ {0x78u, 0x20u},
+ {0x7Au, 0x08u},
+ {0x8Bu, 0x40u},
+ {0x8Cu, 0x04u},
+ {0x90u, 0x40u},
+ {0x91u, 0x04u},
+ {0x92u, 0x08u},
+ {0x93u, 0x0Eu},
+ {0x94u, 0x28u},
+ {0x95u, 0x99u},
+ {0x98u, 0x19u},
+ {0x99u, 0x12u},
+ {0x9Au, 0x12u},
+ {0x9Bu, 0x55u},
+ {0x9Cu, 0x20u},
+ {0x9Du, 0xC1u},
+ {0xA1u, 0x42u},
+ {0xA2u, 0x01u},
+ {0xA3u, 0x3Au},
+ {0xA4u, 0x10u},
+ {0xA5u, 0x3Cu},
+ {0xA6u, 0x12u},
+ {0xA8u, 0x01u},
+ {0xC0u, 0xF4u},
+ {0xC2u, 0xFFu},
+ {0xC4u, 0x76u},
+ {0xCAu, 0xFFu},
+ {0xCCu, 0xFEu},
+ {0xCEu, 0xF0u},
{0xD6u, 0xF0u},
{0xD8u, 0x90u},
- {0xEAu, 0x03u},
- {0xECu, 0x80u},
- {0xEEu, 0x08u},
- {0x00u, 0x01u},
- {0x04u, 0x04u},
+ {0xE2u, 0x20u},
+ {0xEEu, 0x0Cu},
+ {0x02u, 0x40u},
{0x05u, 0x30u},
{0x07u, 0xC0u},
- {0x09u, 0x60u},
- {0x0Bu, 0x90u},
- {0x0Du, 0xFFu},
- {0x11u, 0x05u},
- {0x13u, 0x0Au},
- {0x14u, 0x02u},
+ {0x09u, 0x50u},
+ {0x0Bu, 0xA0u},
+ {0x0Cu, 0x01u},
+ {0x0Eu, 0x12u},
+ {0x10u, 0x53u},
+ {0x12u, 0xACu},
+ {0x13u, 0xFFu},
+ {0x15u, 0xFFu},
{0x18u, 0x02u},
- {0x19u, 0x03u},
- {0x1Bu, 0x0Cu},
- {0x1Cu, 0x02u},
+ {0x1Au, 0x01u},
+ {0x1Bu, 0xFFu},
+ {0x1Cu, 0x08u},
{0x1Du, 0x0Fu},
+ {0x1Eu, 0x04u},
{0x1Fu, 0xF0u},
- {0x21u, 0x06u},
- {0x23u, 0x09u},
- {0x24u, 0x02u},
- {0x25u, 0x50u},
- {0x27u, 0xA0u},
- {0x2Bu, 0xFFu},
- {0x2Fu, 0xFFu},
- {0x32u, 0x02u},
- {0x34u, 0x01u},
- {0x35u, 0xFFu},
- {0x36u, 0x04u},
- {0x38u, 0x08u},
- {0x3Eu, 0x54u},
- {0x3Fu, 0x10u},
- {0x54u, 0x40u},
- {0x56u, 0x04u},
+ {0x20u, 0x04u},
+ {0x21u, 0x60u},
+ {0x22u, 0x28u},
+ {0x23u, 0x90u},
+ {0x25u, 0x05u},
+ {0x27u, 0x0Au},
+ {0x29u, 0x06u},
+ {0x2Bu, 0x09u},
+ {0x2Du, 0x03u},
+ {0x2Eu, 0x80u},
+ {0x2Fu, 0x0Cu},
+ {0x30u, 0x0Fu},
+ {0x32u, 0x30u},
+ {0x33u, 0xFFu},
+ {0x34u, 0xC0u},
+ {0x3Eu, 0x15u},
+ {0x3Fu, 0x04u},
{0x58u, 0x04u},
{0x59u, 0x04u},
{0x5Bu, 0x04u},
{0x5Fu, 0x01u},
- {0x80u, 0x0Fu},
- {0x81u, 0xE0u},
- {0x82u, 0xF0u},
- {0x84u, 0x03u},
- {0x86u, 0x0Cu},
- {0x87u, 0x12u},
- {0x8Bu, 0x01u},
- {0x8Cu, 0xFFu},
- {0x8Fu, 0xECu},
- {0x90u, 0x05u},
- {0x92u, 0x0Au},
- {0x94u, 0x30u},
- {0x95u, 0x21u},
- {0x96u, 0xC0u},
- {0x97u, 0x02u},
- {0x98u, 0x60u},
- {0x99u, 0x88u},
- {0x9Au, 0x90u},
- {0x9Bu, 0x03u},
- {0x9Eu, 0xFFu},
- {0xA0u, 0x06u},
- {0xA2u, 0x09u},
- {0xA4u, 0x50u},
- {0xA6u, 0xA0u},
- {0xA9u, 0x04u},
- {0xAAu, 0xFFu},
- {0xABu, 0x43u},
- {0xB3u, 0xE0u},
- {0xB5u, 0x10u},
- {0xB6u, 0xFFu},
- {0xB7u, 0x0Fu},
+ {0x80u, 0x01u},
+ {0x85u, 0x05u},
+ {0x86u, 0x40u},
+ {0x87u, 0x0Au},
+ {0x88u, 0x01u},
+ {0x89u, 0x50u},
+ {0x8Bu, 0xA0u},
+ {0x8Cu, 0x01u},
+ {0x8Du, 0x0Fu},
+ {0x8Fu, 0xF0u},
+ {0x90u, 0x08u},
+ {0x92u, 0x61u},
+ {0x93u, 0xFFu},
+ {0x94u, 0x10u},
+ {0x97u, 0xFFu},
+ {0x98u, 0xA2u},
+ {0x99u, 0x30u},
+ {0x9Au, 0x08u},
+ {0x9Bu, 0xC0u},
+ {0x9Cu, 0x04u},
+ {0xA0u, 0x01u},
+ {0xA1u, 0x90u},
+ {0xA3u, 0x60u},
+ {0xA4u, 0x07u},
+ {0xA6u, 0xD8u},
+ {0xA7u, 0xFFu},
+ {0xA8u, 0x01u},
+ {0xA9u, 0x09u},
+ {0xABu, 0x06u},
+ {0xADu, 0x03u},
+ {0xAFu, 0x0Cu},
+ {0xB1u, 0xFFu},
+ {0xB2u, 0xE0u},
+ {0xB6u, 0x3Fu},
+ {0xB8u, 0x80u},
{0xBEu, 0x40u},
- {0xBFu, 0x04u},
- {0xD6u, 0x02u},
- {0xD7u, 0x24u},
+ {0xBFu, 0x01u},
{0xD8u, 0x04u},
{0xD9u, 0x04u},
- {0xDBu, 0x04u},
{0xDFu, 0x01u},
- {0x03u, 0xA0u},
- {0x04u, 0x02u},
- {0x05u, 0x80u},
- {0x07u, 0x52u},
- {0x09u, 0xA0u},
- {0x0Au, 0x20u},
- {0x0Cu, 0x01u},
- {0x0Du, 0x54u},
- {0x0Eu, 0x40u},
- {0x11u, 0x08u},
- {0x14u, 0x54u},
- {0x17u, 0x08u},
- {0x19u, 0x68u},
- {0x1Du, 0x80u},
- {0x21u, 0x20u},
- {0x25u, 0x50u},
- {0x27u, 0x20u},
- {0x28u, 0x54u},
- {0x29u, 0x80u},
- {0x2Fu, 0x08u},
- {0x30u, 0x01u},
- {0x33u, 0x50u},
- {0x35u, 0x14u},
- {0x39u, 0xA8u},
- {0x3Du, 0xA0u},
- {0x3Fu, 0x09u},
- {0x60u, 0x84u},
- {0x62u, 0x08u},
- {0x63u, 0x02u},
- {0x67u, 0x08u},
- {0x6Cu, 0x02u},
- {0x6Du, 0x05u},
- {0x6Eu, 0x14u},
- {0x74u, 0x40u},
- {0x76u, 0x02u},
- {0x80u, 0x04u},
- {0x82u, 0x04u},
- {0x83u, 0x02u},
- {0x87u, 0x20u},
- {0x88u, 0x90u},
- {0x89u, 0x0Cu},
- {0x8Fu, 0xA0u},
- {0x90u, 0x02u},
- {0x91u, 0xA0u},
- {0x92u, 0x60u},
- {0x93u, 0x09u},
- {0x95u, 0x05u},
- {0x96u, 0x14u},
- {0x98u, 0x44u},
- {0x99u, 0x14u},
- {0x9Bu, 0x1Au},
- {0x9Du, 0x60u},
- {0x9Eu, 0x02u},
- {0xA0u, 0x10u},
- {0xA1u, 0x04u},
+ {0x01u, 0x02u},
+ {0x03u, 0x02u},
+ {0x05u, 0x14u},
+ {0x06u, 0x02u},
+ {0x07u, 0x40u},
+ {0x0Au, 0xCAu},
+ {0x0Du, 0x82u},
+ {0x0Eu, 0x08u},
+ {0x0Fu, 0x20u},
+ {0x13u, 0x42u},
+ {0x17u, 0x19u},
+ {0x18u, 0x04u},
+ {0x19u, 0x01u},
+ {0x1Au, 0x10u},
+ {0x1Du, 0x04u},
+ {0x1Fu, 0x80u},
+ {0x20u, 0x20u},
+ {0x26u, 0x02u},
+ {0x28u, 0x41u},
+ {0x29u, 0x20u},
+ {0x2Au, 0x08u},
+ {0x2Cu, 0x41u},
+ {0x2Du, 0x20u},
+ {0x2Fu, 0x64u},
+ {0x31u, 0x01u},
+ {0x32u, 0x48u},
+ {0x33u, 0x20u},
+ {0x35u, 0x01u},
+ {0x36u, 0x08u},
+ {0x37u, 0x20u},
+ {0x39u, 0x18u},
+ {0x3Du, 0x10u},
+ {0x3Eu, 0x48u},
+ {0x3Fu, 0x04u},
+ {0x48u, 0x01u},
+ {0x49u, 0x40u},
+ {0x4Bu, 0x80u},
+ {0x68u, 0x01u},
+ {0x69u, 0x19u},
+ {0x6Au, 0x02u},
+ {0x6Bu, 0x20u},
+ {0x71u, 0x28u},
+ {0x72u, 0x80u},
+ {0x73u, 0x42u},
+ {0x81u, 0x04u},
+ {0x82u, 0x10u},
+ {0x8Cu, 0x04u},
+ {0x92u, 0x88u},
+ {0x93u, 0x0Cu},
+ {0x94u, 0x0Cu},
+ {0x95u, 0x19u},
+ {0x98u, 0x01u},
+ {0x99u, 0x12u},
+ {0x9Au, 0x02u},
+ {0x9Bu, 0x59u},
+ {0x9Du, 0x41u},
+ {0x9Eu, 0x80u},
+ {0xA1u, 0x82u},
{0xA2u, 0x0Cu},
- {0xA3u, 0x0Fu},
- {0xA4u, 0x42u},
- {0xAEu, 0x04u},
- {0xAFu, 0x40u},
- {0xC0u, 0xBCu},
- {0xC2u, 0xF7u},
- {0xC4u, 0x74u},
- {0xCAu, 0x2Fu},
- {0xCCu, 0x6Du},
- {0xCEu, 0xFEu},
- {0xD8u, 0x2Fu},
- {0xE2u, 0x20u},
- {0xE6u, 0x18u},
- {0xECu, 0x08u},
+ {0xA3u, 0x32u},
+ {0xA4u, 0x10u},
+ {0xA5u, 0x28u},
+ {0xA6u, 0x02u},
+ {0xA7u, 0x80u},
+ {0xAEu, 0x01u},
+ {0xB5u, 0x80u},
+ {0xC0u, 0xF9u},
+ {0xC2u, 0xFBu},
+ {0xC4u, 0x79u},
+ {0xCAu, 0xFFu},
+ {0xCCu, 0xEFu},
+ {0xCEu, 0x76u},
+ {0xE0u, 0x01u},
+ {0xECu, 0x40u},
{0x0Eu, 0x08u},
{0x12u, 0x08u},
{0x15u, 0x80u},
{0x33u, 0x04u},
{0x36u, 0x88u},
{0x39u, 0x80u},
- {0x3Au, 0x08u},
- {0x3Cu, 0x18u},
- {0x40u, 0x02u},
- {0x5Fu, 0x02u},
- {0x86u, 0x08u},
+ {0x3Bu, 0x01u},
+ {0x3Eu, 0x88u},
+ {0x41u, 0x80u},
+ {0x60u, 0x20u},
+ {0x83u, 0x01u},
+ {0x8Bu, 0x20u},
+ {0x8Eu, 0x04u},
{0xC2u, 0x80u},
{0xC4u, 0xE0u},
{0xCCu, 0xE0u},
{0xCEu, 0xF0u},
{0xD0u, 0x10u},
- {0xD6u, 0x80u},
- {0xE6u, 0x40u},
- {0x33u, 0x81u},
- {0x37u, 0x20u},
- {0x3Au, 0x80u},
+ {0xD8u, 0x40u},
+ {0xE2u, 0x80u},
+ {0x32u, 0x04u},
+ {0x33u, 0x80u},
+ {0x35u, 0x80u},
+ {0x39u, 0x40u},
{0x53u, 0x20u},
{0x59u, 0x10u},
- {0x63u, 0x40u},
+ {0x5Cu, 0x02u},
{0x81u, 0x10u},
- {0x87u, 0x40u},
- {0x9Cu, 0x02u},
- {0x9Fu, 0x02u},
- {0xA2u, 0x04u},
- {0xA4u, 0x04u},
+ {0x8Fu, 0x02u},
+ {0x9Cu, 0x20u},
+ {0x9Eu, 0x08u},
+ {0xA3u, 0x20u},
+ {0xA5u, 0x80u},
{0xA6u, 0x80u},
- {0xA8u, 0x10u},
+ {0xB6u, 0x80u},
{0xCCu, 0x70u},
{0xCEu, 0x10u},
{0xD4u, 0xA0u},
- {0xD8u, 0x40u},
- {0xE6u, 0x60u},
- {0xEEu, 0x80u},
+ {0xD6u, 0x80u},
+ {0xE6u, 0x20u},
{0x12u, 0x80u},
- {0x9Cu, 0x02u},
- {0x9Fu, 0x21u},
- {0xA4u, 0x04u},
+ {0x5Bu, 0x02u},
+ {0x82u, 0x08u},
+ {0x85u, 0x80u},
+ {0x8Cu, 0x02u},
+ {0x96u, 0x08u},
+ {0x9Bu, 0x02u},
+ {0x9Cu, 0x22u},
+ {0x9Du, 0x80u},
+ {0x9Eu, 0x08u},
+ {0xA5u, 0x80u},
{0xA6u, 0x80u},
- {0xA7u, 0xA0u},
- {0xAAu, 0x80u},
- {0xAFu, 0x02u},
- {0xB6u, 0x04u},
+ {0xA7u, 0x80u},
+ {0xA9u, 0x40u},
{0xC4u, 0x10u},
- {0xEAu, 0x80u},
- {0xEEu, 0x40u},
- {0x9Cu, 0x02u},
- {0x9Fu, 0x21u},
- {0xA4u, 0x04u},
+ {0xD6u, 0x40u},
+ {0xE2u, 0x10u},
+ {0xE6u, 0x80u},
+ {0xEEu, 0x20u},
+ {0xA5u, 0x80u},
{0xA7u, 0x80u},
- {0xAFu, 0x20u},
+ {0xAEu, 0x04u},
+ {0xB4u, 0x20u},
{0xEEu, 0x10u},
- {0x02u, 0x01u},
- {0x08u, 0x80u},
- {0x0Cu, 0x80u},
- {0x11u, 0x08u},
- {0x16u, 0x80u},
- {0x60u, 0x20u},
- {0x65u, 0x08u},
- {0x85u, 0x01u},
- {0x88u, 0x80u},
- {0x8Au, 0x02u},
+ {0x00u, 0x20u},
+ {0x09u, 0x40u},
+ {0x0Fu, 0x08u},
+ {0x12u, 0x80u},
+ {0x17u, 0x08u},
+ {0x5Bu, 0x02u},
+ {0x66u, 0x40u},
+ {0x8Bu, 0x40u},
{0xC0u, 0x02u},
{0xC2u, 0x03u},
{0xC4u, 0x0Cu},
- {0xD8u, 0x03u},
- {0xE0u, 0x01u},
- {0xE2u, 0x04u},
- {0x09u, 0x01u},
- {0x0Fu, 0x20u},
- {0x56u, 0x02u},
- {0x5Au, 0x10u},
- {0x5Du, 0x01u},
- {0x63u, 0x40u},
- {0x91u, 0x01u},
- {0x9Au, 0x43u},
- {0x9Du, 0x08u},
- {0xA1u, 0x04u},
- {0xAAu, 0x80u},
- {0xACu, 0x20u},
- {0xB2u, 0x40u},
- {0xB4u, 0x80u},
+ {0xD6u, 0x03u},
+ {0xE6u, 0x01u},
+ {0x0Bu, 0x80u},
+ {0x0Du, 0x08u},
+ {0x53u, 0x02u},
+ {0x57u, 0x40u},
+ {0x61u, 0x40u},
+ {0x62u, 0x04u},
+ {0x81u, 0x10u},
+ {0x8Fu, 0x02u},
+ {0x97u, 0x80u},
+ {0x9Eu, 0x40u},
+ {0x9Fu, 0x02u},
+ {0xA1u, 0x40u},
+ {0xA2u, 0x80u},
+ {0xA3u, 0x04u},
+ {0xABu, 0x08u},
+ {0xACu, 0x10u},
{0xC2u, 0x0Cu},
- {0xD4u, 0x01u},
- {0xD6u, 0x05u},
+ {0xD4u, 0x03u},
+ {0xD6u, 0x02u},
{0xD8u, 0x02u},
- {0xECu, 0x01u},
- {0xEEu, 0x02u},
- {0x83u, 0x08u},
- {0x87u, 0x40u},
- {0x8Fu, 0x10u},
- {0x96u, 0x10u},
- {0x97u, 0x40u},
- {0x9Au, 0x40u},
- {0x9Du, 0x08u},
- {0xA1u, 0x04u},
- {0xA3u, 0x10u},
- {0xA4u, 0x20u},
- {0xA8u, 0x20u},
- {0xB5u, 0x01u},
- {0xB6u, 0x01u},
- {0xE2u, 0x08u},
- {0xEAu, 0x08u},
- {0xEEu, 0x02u},
+ {0xE4u, 0x02u},
+ {0x57u, 0x08u},
+ {0x87u, 0x10u},
+ {0x89u, 0x40u},
+ {0x9Du, 0x40u},
+ {0x9Eu, 0x44u},
+ {0x9Fu, 0x02u},
+ {0xA1u, 0x50u},
+ {0xA2u, 0x80u},
+ {0xA6u, 0x04u},
+ {0xA7u, 0x40u},
+ {0xA9u, 0x08u},
+ {0xAAu, 0x04u},
+ {0xB7u, 0x04u},
+ {0xD4u, 0x02u},
+ {0xE0u, 0x01u},
+ {0xEAu, 0x02u},
{0x08u, 0x08u},
- {0x0Bu, 0x04u},
- {0x0Cu, 0x20u},
- {0x0Du, 0x08u},
- {0x8Eu, 0x10u},
- {0x96u, 0x10u},
- {0x9Au, 0x40u},
- {0x9Du, 0x08u},
- {0xA1u, 0x04u},
- {0xA3u, 0x08u},
- {0xA4u, 0x20u},
+ {0x0Bu, 0x08u},
+ {0x0Eu, 0x08u},
+ {0x0Fu, 0x10u},
+ {0x82u, 0x02u},
+ {0x87u, 0x02u},
+ {0x89u, 0x10u},
+ {0x8Au, 0x40u},
+ {0x97u, 0x18u},
+ {0x9Eu, 0x44u},
+ {0x9Fu, 0x02u},
+ {0xA1u, 0x10u},
+ {0xA2u, 0x80u},
+ {0xA6u, 0x04u},
+ {0xA7u, 0x40u},
+ {0xAFu, 0x04u},
+ {0xB1u, 0x40u},
+ {0xB7u, 0x08u},
{0xC2u, 0x0Fu},
- {0xE4u, 0x08u},
- {0x67u, 0x20u},
- {0x87u, 0x10u},
- {0x9Cu, 0x02u},
- {0x9Eu, 0x40u},
- {0xA4u, 0x04u},
- {0xABu, 0x20u},
- {0xAFu, 0x81u},
- {0xB2u, 0x40u},
- {0xD8u, 0x80u},
- {0xE6u, 0x40u},
- {0xEAu, 0xC0u},
+ {0xE2u, 0x01u},
+ {0xE4u, 0x01u},
+ {0xE8u, 0x08u},
+ {0xEEu, 0x04u},
+ {0x89u, 0x80u},
+ {0xA5u, 0x80u},
+ {0xAFu, 0x80u},
{0xEEu, 0x10u},
- {0x06u, 0x40u},
- {0x50u, 0x40u},
- {0x57u, 0x20u},
- {0x83u, 0x20u},
- {0x88u, 0x04u},
- {0x8Cu, 0x40u},
- {0x9Eu, 0x40u},
- {0xA4u, 0x04u},
- {0xACu, 0x02u},
+ {0x06u, 0x20u},
+ {0x57u, 0x08u},
+ {0x5Fu, 0x40u},
+ {0x83u, 0x08u},
+ {0x93u, 0x40u},
+ {0x9Eu, 0x20u},
+ {0xAFu, 0x40u},
+ {0xB6u, 0x20u},
{0xC0u, 0x20u},
- {0xD4u, 0x60u},
- {0xE6u, 0x20u},
+ {0xD4u, 0x40u},
+ {0xD6u, 0x20u},
+ {0xE6u, 0x80u},
{0xEEu, 0x40u},
- {0x7Bu, 0x01u},
- {0x9Au, 0x40u},
- {0x9Du, 0x08u},
- {0xA3u, 0x08u},
- {0xA9u, 0x08u},
+ {0x8Fu, 0x40u},
+ {0x95u, 0x10u},
+ {0x9Au, 0x02u},
+ {0x9Eu, 0x04u},
+ {0xA1u, 0x10u},
+ {0xA7u, 0x40u},
+ {0xAAu, 0x80u},
{0xACu, 0x08u},
- {0xAFu, 0x04u},
- {0xB5u, 0x04u},
- {0xDCu, 0x01u},
- {0xEEu, 0x02u},
- {0x00u, 0x40u},
- {0x05u, 0x40u},
- {0x53u, 0x08u},
- {0x56u, 0x40u},
- {0x85u, 0x40u},
- {0x8Bu, 0x01u},
- {0x8Cu, 0x40u},
- {0x9Au, 0x40u},
- {0xA3u, 0x08u},
- {0xA7u, 0x01u},
- {0xADu, 0x08u},
+ {0xE4u, 0x02u},
+ {0x01u, 0x10u},
+ {0x04u, 0x10u},
+ {0x55u, 0x10u},
+ {0x56u, 0x02u},
+ {0x82u, 0x04u},
+ {0x8Cu, 0x10u},
+ {0x95u, 0x10u},
+ {0x9Au, 0x02u},
+ {0x9Eu, 0x04u},
+ {0xA1u, 0x10u},
{0xC0u, 0x03u},
- {0xD4u, 0x06u},
- {0xE0u, 0x01u},
- {0xE2u, 0x02u},
+ {0xD4u, 0x02u},
+ {0xD6u, 0x04u},
+ {0xE2u, 0x08u},
{0x00u, 0x01u},
{0x01u, 0x01u},
{0x0Cu, 0x01u},
{0x0Du, 0x01u},
- {0x0Eu, 0x01u},
{0x0Fu, 0x01u},
{0x10u, 0x01u},
- {0x11u, 0x01u},
{0x1Cu, 0x01u},
- {0x1Du, 0x01u},
{0x00u, 0xFDu},
{0x01u, 0xABu},
{0x02u, 0x08u},
uint16 size;
} CYPACKED_ATTR cfg_memset_t;
-
- CYPACKED typedef struct {
- void CYFAR *dest;
- const void CYCODE *src;
- uint16 size;
- } CYPACKED_ATTR cfg_memcpy_t;
-
static const cfg_memset_t CYCODE cfg_memset_list [] = {
/* address, size */
{(void CYFAR *)(CYREG_TMR0_CFG0), 12u},
{(void CYFAR *)(CYREG_PRT1_DR), 16u},
- {(void CYFAR *)(CYDEV_UCFG_B0_P0_U0_BASE), 2048u},
- {(void CYFAR *)(CYDEV_UCFG_B0_P4_U1_BASE), 1920u},
+ {(void CYFAR *)(CYDEV_UCFG_B0_P0_U0_BASE), 4096u},
{(void CYFAR *)(CYDEV_UCFG_B1_P2_U0_BASE), 2048u},
{(void CYFAR *)(CYDEV_UCFG_DSI0_BASE), 2560u},
{(void CYFAR *)(CYDEV_UCFG_DSI12_BASE), 512u},
{(void CYFAR *)(CYREG_BCTL0_MDCLK_EN), 32u},
};
- /* UDB_0_2_1_CONFIG Address: CYDEV_UCFG_B0_P4_U0_BASE Size (bytes): 128 */
- static const uint8 CYCODE BS_UDB_0_2_1_CONFIG_VAL[] = {
- 0x00u, 0x01u, 0x60u, 0x00u, 0x1Fu, 0x10u, 0x20u, 0x00u, 0x00u, 0x08u, 0xFFu, 0x21u, 0x80u, 0x01u, 0x00u, 0x00u,
- 0x90u, 0x01u, 0x40u, 0x00u, 0xC0u, 0x07u, 0x08u, 0x18u, 0x00u, 0x22u, 0x9Fu, 0x08u, 0x00u, 0x40u, 0x00u, 0x00u,
- 0xC0u, 0x40u, 0x02u, 0x00u, 0xC0u, 0x01u, 0x04u, 0x00u, 0x7Fu, 0x04u, 0x80u, 0x00u, 0xC0u, 0x01u, 0x01u, 0x00u,
- 0x00u, 0x3Fu, 0x00u, 0x00u, 0x00u, 0x40u, 0xFFu, 0x40u, 0x00u, 0xA2u, 0x00u, 0x00u, 0x00u, 0x00u, 0x40u, 0x01u,
- 0x26u, 0x03u, 0x50u, 0x00u, 0x04u, 0xDBu, 0xC0u, 0xFEu, 0x3Bu, 0xFFu, 0xFFu, 0xFFu, 0x22u, 0x00u, 0xF0u, 0x08u,
- 0x04u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x04u, 0x04u, 0x04u, 0x00u, 0x00u, 0x00u, 0x00u, 0x01u,
- 0x00u, 0x00u, 0xC0u, 0x00u, 0x40u, 0x01u, 0x10u, 0x11u, 0xC0u, 0x01u, 0x00u, 0x11u, 0x40u, 0x01u, 0x40u, 0x01u,
- 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u};
-
- static const cfg_memcpy_t CYCODE cfg_memcpy_list [] = {
- /* dest, src, size */
- {(void CYFAR *)(CYDEV_UCFG_B0_P4_U0_BASE), BS_UDB_0_2_1_CONFIG_VAL, 128u},
- };
-
uint8 CYDATA i;
/* Zero out critical memory blocks before beginning configuration */
CYMEMZERO(ms->address, (uint32)(ms->size));
}
- /* Copy device configuration data into registers */
- for (i = 0u; i < (sizeof(cfg_memcpy_list)/sizeof(cfg_memcpy_list[0])); i++)
- {
- const cfg_memcpy_t CYCODE * CYDATA mc = &cfg_memcpy_list[i];
- void * CYDATA destPtr = mc->dest;
- const void CYCODE * CYDATA srcPtr = mc->src;
- uint16 CYDATA numBytes = mc->size;
- CYCONFIGCPYCODE(destPtr, srcPtr, numBytes);
- }
-
cfg_write_bytes32(cy_cfg_addr_table, cy_cfg_data_table);
/* Perform normal device configuration. Order is not critical for these items. */
/* SCSI_CTL_PHASE */
.set SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK, 0x01
.set SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS, 0
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB12_13_ACTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB12_13_CTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB12_13_CTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB12_13_CTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB12_13_CTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB12_13_MSK
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB12_13_MSK
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB12_13_MSK
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB12_13_MSK
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB11_12_ACTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB11_12_CTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB11_12_CTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB11_12_CTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB11_12_CTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB11_12_MSK
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB11_12_MSK
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB11_12_MSK
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB11_12_MSK
.set SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK, 0x02
.set SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS, 1
.set SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK, 0x04
.set SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS, 2
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB12_ACTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB12_CTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB12_ST_CTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB12_CTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB12_ST_CTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB11_ACTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB11_CTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB11_ST_CTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB11_CTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB11_ST_CTL
.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK, 0x07
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB12_MSK
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB11_MSK
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL
/* SCSI_Out_Bits */
.set SCSI_Out_Bits_Sync_ctrl_reg__0__MASK, 0x01
.set SCSI_Out_Bits_Sync_ctrl_reg__0__POS, 0
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB10_11_ACTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB10_11_CTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB10_11_CTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB10_11_CTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB10_11_CTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB10_11_MSK
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB10_11_MSK
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB10_11_MSK
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB10_11_MSK
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB10_11_ACTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB10_11_CTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB10_11_CTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB10_11_CTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB10_11_CTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B1_UDB10_11_MSK
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB10_11_MSK
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB10_11_MSK
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB10_11_MSK
.set SCSI_Out_Bits_Sync_ctrl_reg__1__MASK, 0x02
.set SCSI_Out_Bits_Sync_ctrl_reg__1__POS, 1
.set SCSI_Out_Bits_Sync_ctrl_reg__2__MASK, 0x04
.set SCSI_Out_Bits_Sync_ctrl_reg__6__POS, 6
.set SCSI_Out_Bits_Sync_ctrl_reg__7__MASK, 0x80
.set SCSI_Out_Bits_Sync_ctrl_reg__7__POS, 7
-.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB10_ACTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB10_CTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB10_ST_CTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB10_CTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB10_ST_CTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B1_UDB10_ACTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG, CYREG_B1_UDB10_CTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B1_UDB10_ST_CTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG, CYREG_B1_UDB10_CTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B1_UDB10_ST_CTL
.set SCSI_Out_Bits_Sync_ctrl_reg__MASK, 0xFF
-.set SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB10_MSK_ACTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB10_MSK
-.set SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB10_MSK_ACTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB10_MSK_ACTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG, CYREG_B1_UDB10_MSK
+.set SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB10_MSK_ACTL
/* USBFS_arb_int */
.set USBFS_arb_int__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
/* SCSI_Out_Ctl */
.set SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK, 0x01
.set SCSI_Out_Ctl_Sync_ctrl_reg__0__POS, 0
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB08_09_ACTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB08_09_CTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB08_09_CTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB08_09_CTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB08_09_CTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B1_UDB08_09_MSK
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB08_09_MSK
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB08_09_MSK
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB08_09_MSK
-.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B1_UDB08_ACTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B1_UDB08_CTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B1_UDB08_ST_CTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B1_UDB08_CTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B1_UDB08_ST_CTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB09_10_ACTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB09_10_CTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB09_10_CTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB09_10_CTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB09_10_CTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B1_UDB09_10_MSK
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB09_10_MSK
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB09_10_MSK
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB09_10_MSK
+.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B1_UDB09_ACTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B1_UDB09_CTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B1_UDB09_ST_CTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B1_UDB09_CTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B1_UDB09_ST_CTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK, 0x01
-.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB08_MSK_ACTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B1_UDB08_MSK
-.set SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB08_MSK_ACTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB09_MSK_ACTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B1_UDB09_MSK
+.set SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB09_MSK_ACTL
/* SCSI_Out_DBx */
.set SCSI_Out_DBx__0__AG, CYREG_PRT5_AG
.set SCSI_RST_ISR__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
/* SDCard_BSPIM */
-.set SDCard_BSPIM_BitCounter_ST__MASK_REG, CYREG_B1_UDB11_MSK
-.set SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B1_UDB11_MSK_ACTL
-.set SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B1_UDB11_MSK_ACTL
-.set SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B1_UDB11_ACTL
-.set SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B1_UDB11_ST_CTL
-.set SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B1_UDB11_ST_CTL
-.set SDCard_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B1_UDB11_ST
-.set SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B1_UDB11_ACTL
-.set SDCard_BSPIM_BitCounter__CONTROL_REG, CYREG_B1_UDB11_CTL
-.set SDCard_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B1_UDB11_ST_CTL
-.set SDCard_BSPIM_BitCounter__COUNT_REG, CYREG_B1_UDB11_CTL
-.set SDCard_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B1_UDB11_ST_CTL
-.set SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB11_MSK_ACTL
-.set SDCard_BSPIM_BitCounter__PERIOD_REG, CYREG_B1_UDB11_MSK
-.set SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB11_MSK_ACTL
-.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB10_11_ACTL
-.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB10_11_ST
+.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB08_09_ACTL
+.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B0_UDB08_09_ST
+.set SDCard_BSPIM_BitCounter_ST__MASK_REG, CYREG_B0_UDB08_MSK
+.set SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB08_MSK_ACTL
+.set SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B0_UDB08_MSK_ACTL
+.set SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B0_UDB08_ACTL
+.set SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B0_UDB08_ST_CTL
+.set SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B0_UDB08_ST_CTL
+.set SDCard_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B0_UDB08_ST
+.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB08_09_ACTL
+.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB08_09_CTL
+.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB08_09_CTL
+.set SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB08_09_CTL
+.set SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB08_09_CTL
+.set SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B0_UDB08_09_MSK
+.set SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB08_09_MSK
+.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB08_09_MSK
+.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB08_09_MSK
+.set SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B0_UDB08_ACTL
+.set SDCard_BSPIM_BitCounter__CONTROL_REG, CYREG_B0_UDB08_CTL
+.set SDCard_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B0_UDB08_ST_CTL
+.set SDCard_BSPIM_BitCounter__COUNT_REG, CYREG_B0_UDB08_CTL
+.set SDCard_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B0_UDB08_ST_CTL
+.set SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB08_MSK_ACTL
+.set SDCard_BSPIM_BitCounter__PERIOD_REG, CYREG_B0_UDB08_MSK
+.set SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB08_MSK_ACTL
+.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB11_12_ACTL
+.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB11_12_ST
.set SDCard_BSPIM_RxStsReg__4__MASK, 0x10
.set SDCard_BSPIM_RxStsReg__4__POS, 4
.set SDCard_BSPIM_RxStsReg__5__MASK, 0x20
.set SDCard_BSPIM_RxStsReg__6__MASK, 0x40
.set SDCard_BSPIM_RxStsReg__6__POS, 6
.set SDCard_BSPIM_RxStsReg__MASK, 0x70
-.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B1_UDB10_MSK
-.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB10_ACTL
-.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B1_UDB10_ST
+.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B0_UDB11_MSK
+.set SDCard_BSPIM_RxStsReg__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL
+.set SDCard_BSPIM_RxStsReg__PER_ST_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL
+.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB11_ACTL
+.set SDCard_BSPIM_RxStsReg__STATUS_CNT_REG, CYREG_B0_UDB11_ST_CTL
+.set SDCard_BSPIM_RxStsReg__STATUS_CONTROL_REG, CYREG_B0_UDB11_ST_CTL
+.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B0_UDB11_ST
.set SDCard_BSPIM_TxStsReg__0__MASK, 0x01
.set SDCard_BSPIM_TxStsReg__0__POS, 0
.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB08_09_ACTL
.set SDCard_BSPIM_TxStsReg__4__POS, 4
.set SDCard_BSPIM_TxStsReg__MASK, 0x1F
.set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B1_UDB08_MSK
-.set SDCard_BSPIM_TxStsReg__MASK_ST_AUX_CTL_REG, CYREG_B1_UDB08_MSK_ACTL
-.set SDCard_BSPIM_TxStsReg__PER_ST_AUX_CTL_REG, CYREG_B1_UDB08_MSK_ACTL
.set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB08_ACTL
-.set SDCard_BSPIM_TxStsReg__STATUS_CNT_REG, CYREG_B1_UDB08_ST_CTL
-.set SDCard_BSPIM_TxStsReg__STATUS_CONTROL_REG, CYREG_B1_UDB08_ST_CTL
.set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B1_UDB08_ST
.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG, CYREG_B0_UDB08_09_A0
.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG, CYREG_B0_UDB08_09_A1
.set SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG, CYREG_B0_UDB08_F0_F1
.set SDCard_BSPIM_sR8_Dp_u0__F0_REG, CYREG_B0_UDB08_F0
.set SDCard_BSPIM_sR8_Dp_u0__F1_REG, CYREG_B0_UDB08_F1
+.set SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG, CYREG_B0_UDB08_MSK_ACTL
+.set SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG, CYREG_B0_UDB08_MSK_ACTL
/* USBFS_dp_int */
.set USBFS_dp_int__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
.set SD_MOSI__SHIFT, 3
.set SD_MOSI__SLW, CYREG_PRT3_SLW
+/* EXTLED */
+.set EXTLED__0__MASK, 0x01
+.set EXTLED__0__PC, CYREG_PRT0_PC0
+.set EXTLED__0__PORT, 0
+.set EXTLED__0__SHIFT, 0
+.set EXTLED__AG, CYREG_PRT0_AG
+.set EXTLED__AMUX, CYREG_PRT0_AMUX
+.set EXTLED__BIE, CYREG_PRT0_BIE
+.set EXTLED__BIT_MASK, CYREG_PRT0_BIT_MASK
+.set EXTLED__BYP, CYREG_PRT0_BYP
+.set EXTLED__CTL, CYREG_PRT0_CTL
+.set EXTLED__DM0, CYREG_PRT0_DM0
+.set EXTLED__DM1, CYREG_PRT0_DM1
+.set EXTLED__DM2, CYREG_PRT0_DM2
+.set EXTLED__DR, CYREG_PRT0_DR
+.set EXTLED__INP_DIS, CYREG_PRT0_INP_DIS
+.set EXTLED__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG
+.set EXTLED__LCD_EN, CYREG_PRT0_LCD_EN
+.set EXTLED__MASK, 0x01
+.set EXTLED__PORT, 0
+.set EXTLED__PRT, CYREG_PRT0_PRT
+.set EXTLED__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL
+.set EXTLED__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN
+.set EXTLED__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0
+.set EXTLED__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1
+.set EXTLED__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0
+.set EXTLED__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1
+.set EXTLED__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT
+.set EXTLED__PS, CYREG_PRT0_PS
+.set EXTLED__SHIFT, 0
+.set EXTLED__SLW, CYREG_PRT0_SLW
+
/* SD_SCK */
.set SD_SCK__0__MASK, 0x04
.set SD_SCK__0__PC, CYREG_PRT3_PC2
/* SCSI_CTL_PHASE */
SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01
SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS EQU 0
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB12_13_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB12_13_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB12_13_MSK
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB12_13_MSK
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB11_12_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB11_12_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB11_12_MSK
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB11_12_MSK
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK
SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK EQU 0x02
SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS EQU 1
SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK EQU 0x04
SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS EQU 2
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB12_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB12_ST_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB12_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB12_ST_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB11_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB11_ST_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB11_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB11_ST_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__MASK EQU 0x07
-SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB12_MSK
-SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB11_MSK
+SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
/* SCSI_Out_Bits */
SCSI_Out_Bits_Sync_ctrl_reg__0__MASK EQU 0x01
SCSI_Out_Bits_Sync_ctrl_reg__0__POS EQU 0
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB10_11_ACTL
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB10_11_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB10_11_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB10_11_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB10_11_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB10_11_MSK
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB10_11_MSK
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB10_11_MSK
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB10_11_MSK
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB10_11_ACTL
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB10_11_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB10_11_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB10_11_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB10_11_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB10_11_MSK
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB10_11_MSK
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB10_11_MSK
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB10_11_MSK
SCSI_Out_Bits_Sync_ctrl_reg__1__MASK EQU 0x02
SCSI_Out_Bits_Sync_ctrl_reg__1__POS EQU 1
SCSI_Out_Bits_Sync_ctrl_reg__2__MASK EQU 0x04
SCSI_Out_Bits_Sync_ctrl_reg__6__POS EQU 6
SCSI_Out_Bits_Sync_ctrl_reg__7__MASK EQU 0x80
SCSI_Out_Bits_Sync_ctrl_reg__7__POS EQU 7
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB10_ACTL
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB10_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB10_ST_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB10_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB10_ST_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB10_ACTL
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B1_UDB10_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B1_UDB10_ST_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B1_UDB10_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B1_UDB10_ST_CTL
SCSI_Out_Bits_Sync_ctrl_reg__MASK EQU 0xFF
-SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL
-SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB10_MSK
-SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL
+SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB10_MSK_ACTL
+SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B1_UDB10_MSK
+SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB10_MSK_ACTL
/* USBFS_arb_int */
USBFS_arb_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
/* SCSI_Out_Ctl */
SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01
SCSI_Out_Ctl_Sync_ctrl_reg__0__POS EQU 0
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB08_09_ACTL
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB08_09_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB08_09_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB08_09_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB08_09_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB08_09_MSK
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB08_09_MSK
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB08_09_MSK
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB08_09_MSK
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB08_ACTL
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B1_UDB08_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B1_UDB08_ST_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B1_UDB08_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B1_UDB08_ST_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB09_10_ACTL
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB09_10_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB09_10_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB09_10_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB09_10_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB09_10_MSK
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB09_10_MSK
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB09_10_MSK
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB09_10_MSK
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB09_ACTL
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B1_UDB09_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B1_UDB09_ST_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B1_UDB09_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B1_UDB09_ST_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__MASK EQU 0x01
-SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB08_MSK_ACTL
-SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B1_UDB08_MSK
-SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB08_MSK_ACTL
+SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB09_MSK_ACTL
+SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B1_UDB09_MSK
+SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB09_MSK_ACTL
/* SCSI_Out_DBx */
SCSI_Out_DBx__0__AG EQU CYREG_PRT5_AG
SCSI_RST_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
/* SDCard_BSPIM */
-SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB11_MSK
-SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB11_MSK_ACTL
-SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB11_MSK_ACTL
-SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB11_ACTL
-SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB11_ST_CTL
-SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB11_ST_CTL
-SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB11_ST
-SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB11_ACTL
-SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB11_CTL
-SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB11_ST_CTL
-SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB11_CTL
-SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB11_ST_CTL
-SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB11_MSK_ACTL
-SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB11_MSK
-SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB11_MSK_ACTL
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB10_11_ACTL
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB10_11_ST
+SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL
+SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B0_UDB08_09_ST
+SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B0_UDB08_MSK
+SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL
+SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL
+SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL
+SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B0_UDB08_ST_CTL
+SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B0_UDB08_ST_CTL
+SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B0_UDB08_ST
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB08_09_CTL
+SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL
+SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB08_09_CTL
+SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB08_09_MSK
+SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK
+SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB08_09_MSK
+SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK
+SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL
+SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B0_UDB08_CTL
+SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B0_UDB08_ST_CTL
+SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B0_UDB08_CTL
+SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B0_UDB08_ST_CTL
+SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL
+SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B0_UDB08_MSK
+SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB11_12_ST
SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10
SDCard_BSPIM_RxStsReg__4__POS EQU 4
SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20
SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40
SDCard_BSPIM_RxStsReg__6__POS EQU 6
SDCard_BSPIM_RxStsReg__MASK EQU 0x70
-SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB10_MSK
-SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB10_ACTL
-SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB10_ST
+SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B0_UDB11_MSK
+SDCard_BSPIM_RxStsReg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
+SDCard_BSPIM_RxStsReg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
+SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL
+SDCard_BSPIM_RxStsReg__STATUS_CNT_REG EQU CYREG_B0_UDB11_ST_CTL
+SDCard_BSPIM_RxStsReg__STATUS_CONTROL_REG EQU CYREG_B0_UDB11_ST_CTL
+SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B0_UDB11_ST
SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01
SDCard_BSPIM_TxStsReg__0__POS EQU 0
SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB08_09_ACTL
SDCard_BSPIM_TxStsReg__4__POS EQU 4
SDCard_BSPIM_TxStsReg__MASK EQU 0x1F
SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB08_MSK
-SDCard_BSPIM_TxStsReg__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB08_MSK_ACTL
-SDCard_BSPIM_TxStsReg__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB08_MSK_ACTL
SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB08_ACTL
-SDCard_BSPIM_TxStsReg__STATUS_CNT_REG EQU CYREG_B1_UDB08_ST_CTL
-SDCard_BSPIM_TxStsReg__STATUS_CONTROL_REG EQU CYREG_B1_UDB08_ST_CTL
SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB08_ST
SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B0_UDB08_09_A0
SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B0_UDB08_09_A1
SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B0_UDB08_F0_F1
SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B0_UDB08_F0
SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B0_UDB08_F1
+SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL
+SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL
/* USBFS_dp_int */
USBFS_dp_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
SD_MOSI__SHIFT EQU 3
SD_MOSI__SLW EQU CYREG_PRT3_SLW
+/* EXTLED */
+EXTLED__0__MASK EQU 0x01
+EXTLED__0__PC EQU CYREG_PRT0_PC0
+EXTLED__0__PORT EQU 0
+EXTLED__0__SHIFT EQU 0
+EXTLED__AG EQU CYREG_PRT0_AG
+EXTLED__AMUX EQU CYREG_PRT0_AMUX
+EXTLED__BIE EQU CYREG_PRT0_BIE
+EXTLED__BIT_MASK EQU CYREG_PRT0_BIT_MASK
+EXTLED__BYP EQU CYREG_PRT0_BYP
+EXTLED__CTL EQU CYREG_PRT0_CTL
+EXTLED__DM0 EQU CYREG_PRT0_DM0
+EXTLED__DM1 EQU CYREG_PRT0_DM1
+EXTLED__DM2 EQU CYREG_PRT0_DM2
+EXTLED__DR EQU CYREG_PRT0_DR
+EXTLED__INP_DIS EQU CYREG_PRT0_INP_DIS
+EXTLED__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
+EXTLED__LCD_EN EQU CYREG_PRT0_LCD_EN
+EXTLED__MASK EQU 0x01
+EXTLED__PORT EQU 0
+EXTLED__PRT EQU CYREG_PRT0_PRT
+EXTLED__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
+EXTLED__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
+EXTLED__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
+EXTLED__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
+EXTLED__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
+EXTLED__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
+EXTLED__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
+EXTLED__PS EQU CYREG_PRT0_PS
+EXTLED__SHIFT EQU 0
+EXTLED__SLW EQU CYREG_PRT0_SLW
+
/* SD_SCK */
SD_SCK__0__MASK EQU 0x04
SD_SCK__0__PC EQU CYREG_PRT3_PC2
; SCSI_CTL_PHASE
SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01
SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS EQU 0
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB12_13_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB12_13_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB12_13_MSK
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB12_13_MSK
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB11_12_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB11_12_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB11_12_MSK
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB11_12_MSK
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK
SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK EQU 0x02
SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS EQU 1
SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK EQU 0x04
SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS EQU 2
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB12_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB12_ST_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB12_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB12_ST_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB11_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB11_ST_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB11_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB11_ST_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__MASK EQU 0x07
-SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB12_MSK
-SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB11_MSK
+SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
; SCSI_Out_Bits
SCSI_Out_Bits_Sync_ctrl_reg__0__MASK EQU 0x01
SCSI_Out_Bits_Sync_ctrl_reg__0__POS EQU 0
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB10_11_ACTL
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB10_11_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB10_11_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB10_11_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB10_11_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB10_11_MSK
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB10_11_MSK
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB10_11_MSK
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB10_11_MSK
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB10_11_ACTL
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB10_11_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB10_11_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB10_11_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB10_11_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB10_11_MSK
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB10_11_MSK
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB10_11_MSK
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB10_11_MSK
SCSI_Out_Bits_Sync_ctrl_reg__1__MASK EQU 0x02
SCSI_Out_Bits_Sync_ctrl_reg__1__POS EQU 1
SCSI_Out_Bits_Sync_ctrl_reg__2__MASK EQU 0x04
SCSI_Out_Bits_Sync_ctrl_reg__6__POS EQU 6
SCSI_Out_Bits_Sync_ctrl_reg__7__MASK EQU 0x80
SCSI_Out_Bits_Sync_ctrl_reg__7__POS EQU 7
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB10_ACTL
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB10_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB10_ST_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB10_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB10_ST_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB10_ACTL
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B1_UDB10_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B1_UDB10_ST_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B1_UDB10_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B1_UDB10_ST_CTL
SCSI_Out_Bits_Sync_ctrl_reg__MASK EQU 0xFF
-SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL
-SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB10_MSK
-SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL
+SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB10_MSK_ACTL
+SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B1_UDB10_MSK
+SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB10_MSK_ACTL
; USBFS_arb_int
USBFS_arb_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
; SCSI_Out_Ctl
SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01
SCSI_Out_Ctl_Sync_ctrl_reg__0__POS EQU 0
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB08_09_ACTL
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB08_09_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB08_09_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB08_09_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB08_09_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB08_09_MSK
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB08_09_MSK
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB08_09_MSK
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB08_09_MSK
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB08_ACTL
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B1_UDB08_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B1_UDB08_ST_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B1_UDB08_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B1_UDB08_ST_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB09_10_ACTL
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB09_10_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB09_10_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB09_10_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB09_10_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB09_10_MSK
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB09_10_MSK
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB09_10_MSK
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB09_10_MSK
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB09_ACTL
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B1_UDB09_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B1_UDB09_ST_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B1_UDB09_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B1_UDB09_ST_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__MASK EQU 0x01
-SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB08_MSK_ACTL
-SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B1_UDB08_MSK
-SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB08_MSK_ACTL
+SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB09_MSK_ACTL
+SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B1_UDB09_MSK
+SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB09_MSK_ACTL
; SCSI_Out_DBx
SCSI_Out_DBx__0__AG EQU CYREG_PRT5_AG
SCSI_RST_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
; SDCard_BSPIM
-SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB11_MSK
-SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB11_MSK_ACTL
-SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB11_MSK_ACTL
-SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB11_ACTL
-SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB11_ST_CTL
-SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB11_ST_CTL
-SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB11_ST
-SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB11_ACTL
-SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB11_CTL
-SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB11_ST_CTL
-SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB11_CTL
-SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB11_ST_CTL
-SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB11_MSK_ACTL
-SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB11_MSK
-SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB11_MSK_ACTL
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB10_11_ACTL
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB10_11_ST
+SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL
+SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B0_UDB08_09_ST
+SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B0_UDB08_MSK
+SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL
+SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL
+SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL
+SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B0_UDB08_ST_CTL
+SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B0_UDB08_ST_CTL
+SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B0_UDB08_ST
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB08_09_CTL
+SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL
+SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB08_09_CTL
+SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB08_09_MSK
+SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK
+SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB08_09_MSK
+SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK
+SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL
+SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B0_UDB08_CTL
+SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B0_UDB08_ST_CTL
+SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B0_UDB08_CTL
+SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B0_UDB08_ST_CTL
+SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL
+SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B0_UDB08_MSK
+SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB11_12_ST
SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10
SDCard_BSPIM_RxStsReg__4__POS EQU 4
SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20
SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40
SDCard_BSPIM_RxStsReg__6__POS EQU 6
SDCard_BSPIM_RxStsReg__MASK EQU 0x70
-SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB10_MSK
-SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB10_ACTL
-SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB10_ST
+SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B0_UDB11_MSK
+SDCard_BSPIM_RxStsReg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
+SDCard_BSPIM_RxStsReg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
+SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL
+SDCard_BSPIM_RxStsReg__STATUS_CNT_REG EQU CYREG_B0_UDB11_ST_CTL
+SDCard_BSPIM_RxStsReg__STATUS_CONTROL_REG EQU CYREG_B0_UDB11_ST_CTL
+SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B0_UDB11_ST
SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01
SDCard_BSPIM_TxStsReg__0__POS EQU 0
SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB08_09_ACTL
SDCard_BSPIM_TxStsReg__4__POS EQU 4
SDCard_BSPIM_TxStsReg__MASK EQU 0x1F
SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB08_MSK
-SDCard_BSPIM_TxStsReg__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB08_MSK_ACTL
-SDCard_BSPIM_TxStsReg__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB08_MSK_ACTL
SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB08_ACTL
-SDCard_BSPIM_TxStsReg__STATUS_CNT_REG EQU CYREG_B1_UDB08_ST_CTL
-SDCard_BSPIM_TxStsReg__STATUS_CONTROL_REG EQU CYREG_B1_UDB08_ST_CTL
SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB08_ST
SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B0_UDB08_09_A0
SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B0_UDB08_09_A1
SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B0_UDB08_F0_F1
SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B0_UDB08_F0
SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B0_UDB08_F1
+SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL
+SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL
; USBFS_dp_int
USBFS_dp_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
SD_MOSI__SHIFT EQU 3
SD_MOSI__SLW EQU CYREG_PRT3_SLW
+; EXTLED
+EXTLED__0__MASK EQU 0x01
+EXTLED__0__PC EQU CYREG_PRT0_PC0
+EXTLED__0__PORT EQU 0
+EXTLED__0__SHIFT EQU 0
+EXTLED__AG EQU CYREG_PRT0_AG
+EXTLED__AMUX EQU CYREG_PRT0_AMUX
+EXTLED__BIE EQU CYREG_PRT0_BIE
+EXTLED__BIT_MASK EQU CYREG_PRT0_BIT_MASK
+EXTLED__BYP EQU CYREG_PRT0_BYP
+EXTLED__CTL EQU CYREG_PRT0_CTL
+EXTLED__DM0 EQU CYREG_PRT0_DM0
+EXTLED__DM1 EQU CYREG_PRT0_DM1
+EXTLED__DM2 EQU CYREG_PRT0_DM2
+EXTLED__DR EQU CYREG_PRT0_DR
+EXTLED__INP_DIS EQU CYREG_PRT0_INP_DIS
+EXTLED__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
+EXTLED__LCD_EN EQU CYREG_PRT0_LCD_EN
+EXTLED__MASK EQU 0x01
+EXTLED__PORT EQU 0
+EXTLED__PRT EQU CYREG_PRT0_PRT
+EXTLED__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
+EXTLED__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
+EXTLED__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
+EXTLED__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
+EXTLED__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
+EXTLED__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
+EXTLED__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
+EXTLED__PS EQU CYREG_PRT0_PS
+EXTLED__SHIFT EQU 0
+EXTLED__SLW EQU CYREG_PRT0_SLW
+
; SD_SCK
SD_SCK__0__MASK EQU 0x04
SD_SCK__0__PC EQU CYREG_PRT3_PC2
const uint8 cy_meta_loadable[] = {
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
- 0x00u, 0x00u, 0x00u, 0x00u, 0x5Cu, 0xD1u, 0x01u, 0x00u,
+ 0x00u, 0x00u, 0x00u, 0x00u, 0x5Cu, 0xD1u, 0x50u, 0x03u,
0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
#include <Debug_Timer.h>
#include <timer_clock.h>
#include <Debug_Timer_Interrupt.h>
+#include <EXTLED_aliases.h>
+#include <EXTLED.h>
#include <USBFS_Dm_aliases.h>
#include <USBFS_Dm.h>
#include <USBFS_Dp_aliases.h>
<Toolchain Name="ARM GCC" Selected="True">
<Tool Name="prebuild" Command="" Options="" />
<Tool Name="assembler" Command="arm-none-eabi-as.exe" Options="-I. -I./Generated_Source/PSoC5 -mcpu=cortex-m3 -mthumb -g -alh=${OutputDir}/${CompileFile}.lst " />
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<Tool Name="postbuild" Command="" Options="" />
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<Tool Name="prebuild" Command="" Options="" />
<Tool Name="assembler" Command="armasm.exe" Options="-i. -iGenerated_Source/PSoC5 --diag_style=gnu --thumb --cpu=Cortex-M3 -g --list=${OutputDir}/${CompileFile}.lst " />
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+ <Tool Name="compiler" Command="armcc.exe" Options="-I. -I./Generated_Source/PSoC5 --diag_suppress=951 --diag_style=gnu --cpu=Cortex-M3 -g -D NDEBUG --signed_chars --list -Ospace --split_sections " />
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- <CMSIS_SVD_File>pbook.svd</CMSIS_SVD_File>
+ <Project Name="SCSI2SD" Path="Z:\projects\SCSI2SD\git-3.5\SCSI2SD\software\SCSI2SD\v4\SCSI2SD.cydsn" Version="4.0" Type="Bootloadable">
+ <CMSIS_SVD_File>SCSI2SD.svd</CMSIS_SVD_File>
<Datasheet />
<LinkerFiles>
<LinkerFile Toolchain="ARM GCC">.\Generated_Source\PSoC5\cm3gcc.ld</LinkerFile>
<LinkerFile Toolchain="IAR EWARM">.\Generated_Source\PSoC5\Cm3Iar.icf</LinkerFile>
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- <Files Root="Z:\projects\SCSI2SD\git-3.4_debug\SCSI2SD\software\SCSI2SD\pbook\pbook.cydsn">
+ <Folder BuildType="BUILD" Path="Z:\projects\SCSI2SD\git-3.5\SCSI2SD\software\SCSI2SD\src">
+ <Files Root="Z:\projects\SCSI2SD\git-3.5\SCSI2SD\software\SCSI2SD\v4\SCSI2SD.cydsn">
<File BuildType="BUILD" Toolchain="">..\..\src\main.c</File>
<File BuildType="BUILD" Toolchain="">..\..\src\diagnostic.c</File>
<File BuildType="BUILD" Toolchain="">..\..\src\disk.c</File>
<File BuildType="BUILD" Toolchain="">..\..\src\bits.c</File>
<File BuildType="BUILD" Toolchain="">..\..\src\sd.c</File>
<File BuildType="BUILD" Toolchain="">..\..\src\config.c</File>
+ <File BuildType="BUILD" Toolchain="">..\..\src\led.c</File>
<File BuildType="BUILD" Toolchain="">..\..\src\diagnostic.h</File>
<File BuildType="BUILD" Toolchain="">..\..\src\disk.h</File>
<File BuildType="BUILD" Toolchain="">..\..\src\geometry.h</File>
<File BuildType="BUILD" Toolchain="">..\..\src\config.h</File>
</Files>
</Folder>
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- <Files Root="Z:\projects\SCSI2SD\git-3.4_debug\SCSI2SD\software\SCSI2SD\pbook\pbook.cydsn">
+ <Folder BuildType="BUILD" Path="Z:\projects\SCSI2SD\git-3.5\SCSI2SD\software\SCSI2SD\v4\SCSI2SD.cydsn">
+ <Files Root="Z:\projects\SCSI2SD\git-3.5\SCSI2SD\software\SCSI2SD\v4\SCSI2SD.cydsn">
<File BuildType="BUILD" Toolchain="">.\device.h</File>
</Files>
</Folder>
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- <Files Root="Z:\projects\SCSI2SD\git-3.4_debug\SCSI2SD\software\SCSI2SD\pbook\pbook.cydsn">
+ <Folder BuildType="STRICT" Path="Z:\projects\SCSI2SD\git-3.5\SCSI2SD\software\SCSI2SD\v4\SCSI2SD.cydsn\Generated_Source\PSoC5">
+ <Files Root="Z:\projects\SCSI2SD\git-3.5\SCSI2SD\software\SCSI2SD\v4\SCSI2SD.cydsn">
<File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\cyfitter_cfg.h</File>
<File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\cyfitter_cfg.c</File>
<File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\cybootloader.c</File>
<File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\timer_clock.h</File>
<File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\Debug_Timer_Interrupt.c</File>
<File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\Debug_Timer_Interrupt.h</File>
+ <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\EXTLED_aliases.h</File>
+ <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\EXTLED.c</File>
+ <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\EXTLED.h</File>
<File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\prebuild.bat</File>
<File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\postbuild.bat</File>
<File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\CyElfTool.exe</File>
<File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\libelf.dll</File>
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- <Files Root="Z:\projects\SCSI2SD\git-3.4_debug\SCSI2SD\software\SCSI2SD\pbook\pbook.cydsn">
+ <Folder BuildType="STRICT" Path="Z:\projects\SCSI2SD\git-3.5\SCSI2SD\software\SCSI2SD\v4\SCSI2SD.cydsn\Generated_Source\PSoC5\ARM_GCC">
+ <Files Root="Z:\projects\SCSI2SD\git-3.5\SCSI2SD\software\SCSI2SD\v4\SCSI2SD.cydsn">
<File BuildType="BUILD" Toolchain="ARM GCC">.\Generated_Source\PSoC5\ARM_GCC\CyComponentLibrary.a</File>
</Files>
</Folder>
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- <Files Root="Z:\projects\SCSI2SD\git-3.4_debug\SCSI2SD\software\SCSI2SD\pbook\pbook.cydsn">
+ <Folder BuildType="STRICT" Path="Z:\projects\SCSI2SD\git-3.5\SCSI2SD\software\SCSI2SD\v4\SCSI2SD.cydsn\Generated_Source\PSoC5\ARM_Keil_MDK">
+ <Files Root="Z:\projects\SCSI2SD\git-3.5\SCSI2SD\software\SCSI2SD\v4\SCSI2SD.cydsn">
<File BuildType="BUILD" Toolchain="ARM Keil MDK">.\Generated_Source\PSoC5\ARM_Keil_MDK\CyComponentLibrary.a</File>
</Files>
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- <Files Root="Z:\projects\SCSI2SD\git-3.4_debug\SCSI2SD\software\SCSI2SD\pbook\pbook.cydsn">
+ <Folder BuildType="STRICT" Path="Z:\projects\SCSI2SD\git-3.5\SCSI2SD\software\SCSI2SD\v4\SCSI2SD.cydsn\Generated_Source\PSoC5\IAR">
+ <Files Root="Z:\projects\SCSI2SD\git-3.5\SCSI2SD\software\SCSI2SD\v4\SCSI2SD.cydsn">
<File BuildType="BUILD" Toolchain="IAR">.\Generated_Source\PSoC5\IAR\CyComponentLibrary.a</File>
</Files>
</Folder>
<Folder BuildType="EXCLUDE" Path=".\codegentemp">
- <Files Root="Z:\projects\SCSI2SD\git-3.4_debug\SCSI2SD\software\SCSI2SD\pbook\pbook.cydsn" />
+ <Files Root="Z:\projects\SCSI2SD\git-3.5\SCSI2SD\software\SCSI2SD\v4\SCSI2SD.cydsn" />
</Folder>
<Folder BuildType="EXCLUDE" Path=".\ARM_GCC_441">
- <Files Root="Z:\projects\SCSI2SD\git-3.4_debug\SCSI2SD\software\SCSI2SD\pbook\pbook.cydsn" />
+ <Files Root="Z:\projects\SCSI2SD\git-3.5\SCSI2SD\software\SCSI2SD\v4\SCSI2SD.cydsn" />
</Folder>
<Folder BuildType="EXCLUDE" Path=".\ARM_GCC_473">
- <Files Root="Z:\projects\SCSI2SD\git-3.4_debug\SCSI2SD\software\SCSI2SD\pbook\pbook.cydsn" />
+ <Files Root="Z:\projects\SCSI2SD\git-3.5\SCSI2SD\software\SCSI2SD\v4\SCSI2SD.cydsn" />
</Folder>
<Folder BuildType="EXCLUDE" Path=".\DP8051_Keil_951">
- <Files Root="Z:\projects\SCSI2SD\git-3.4_debug\SCSI2SD\software\SCSI2SD\pbook\pbook.cydsn" />
+ <Files Root="Z:\projects\SCSI2SD\git-3.5\SCSI2SD\software\SCSI2SD\v4\SCSI2SD.cydsn" />
</Folder>
<Folder BuildType="EXCLUDE" Path=".\DP8051">
- <Files Root="Z:\projects\SCSI2SD\git-3.4_debug\SCSI2SD\software\SCSI2SD\pbook\pbook.cydsn" />
+ <Files Root="Z:\projects\SCSI2SD\git-3.5\SCSI2SD\software\SCSI2SD\v4\SCSI2SD.cydsn" />
</Folder>
<Folder BuildType="EXCLUDE" Path=".\CortexM0">
- <Files Root="Z:\projects\SCSI2SD\git-3.4_debug\SCSI2SD\software\SCSI2SD\pbook\pbook.cydsn" />
+ <Files Root="Z:\projects\SCSI2SD\git-3.5\SCSI2SD\software\SCSI2SD\v4\SCSI2SD.cydsn" />
</Folder>
<Folder BuildType="EXCLUDE" Path=".\CortexM3">
- <Files Root="Z:\projects\SCSI2SD\git-3.4_debug\SCSI2SD\software\SCSI2SD\pbook\pbook.cydsn" />
+ <Files Root="Z:\projects\SCSI2SD\git-3.5\SCSI2SD\software\SCSI2SD\v4\SCSI2SD.cydsn" />
</Folder>
</Folders>
</Project>
--- /dev/null
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\ No newline at end of file
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<block name="BSPIM" BASE="0x0" SIZE="0x0" desc="" visible="true" />
</block>
+ <block name="SCSI_TX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+ <block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="timer_clock" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+ <block name="EXTLED" BASE="0x0" SIZE="0x0" desc="" visible="true" />
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<block name="SCSI_Out_Ctl" BASE="0x0" SIZE="0x0" desc="" visible="true">
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<block name="SCSI_Out_Bits" BASE="0x0" SIZE="0x0" desc="" visible="true">
- <register name="SCSI_Out_Bits_CONTROL_REG" address="0x4000647A" bitWidth="8" desc="" />
+ <register name="SCSI_Out_Bits_CONTROL_REG" address="0x4000657A" bitWidth="8" desc="" />
</block>
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+ <register name="SCSI_CTL_PHASE_CONTROL_REG" address="0x4000647B" bitWidth="8" desc="" />
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<block name="SD_TX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" />
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<block name="Clock_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
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<block name="SCSI_Out" BASE="0x0" SIZE="0x0" desc="" visible="true" />
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+<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="EXTLED.h" persistent=".\Generated_Source\PSoC5\EXTLED.h">
+<Hidden v="False" />
+</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>
+<build_action v="NONE" />
+<PropertyDeltas />
+</CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b>
+</CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d>
+</dependencies>
+</CyGuid_0820c2e7-528d-4137-9a08-97257b946089>
+</CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8>
+<filters />
+</CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0>
</dependencies>
</CyGuid_0820c2e7-528d-4137-9a08-97257b946089>
</CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8>
<peripheral>
<name>SCSI_Out_Ctl</name>
<description>No description available</description>
- <baseAddress>0x40006578</baseAddress>
+ <baseAddress>0x40006579</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x1</size>
<peripheral>
<name>SCSI_Out_Bits</name>
<description>No description available</description>
- <baseAddress>0x4000647A</baseAddress>
+ <baseAddress>0x4000657A</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x1</size>
<peripheral>
<name>SCSI_CTL_PHASE</name>
<description>No description available</description>
- <baseAddress>0x4000647C</baseAddress>
+ <baseAddress>0x4000647B</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x1</size>
--- /dev/null
+../../v3/SCSI2SD.cydsn/scsiTarget/
\ No newline at end of file
<CyGuid_60697ce6-dce2-4816-8680-4de0635742eb type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtProjectExe" version="3">
<CyGuid_49cfd574-032a-4a64-b7be-d4eeeaf25e43 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtProject" version="7" xml_contents_version="1">
<CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtBaseContainer" version="1">
-<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="bootloader" persistent="">
+<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="USB_Bootloader" persistent="">
<Hidden v="False" />
</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>
<CyGuid_0820c2e7-528d-4137-9a08-97257b946089 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItemList" version="2">
</CyGuid_4429d4ed-fe84-42d0-9e9f-19aee0ff4e7e>
<CyGuid_409391e1-c2a7-4709-8a6b-4622593f7390 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtNameRestrictedFile" version="1">
<CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFile" version="3" xml_contents_version="1">
-<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="bootloader.cydwr" persistent=".\bootloader.cydwr">
+<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="USB_Bootloader.cydwr" persistent=".\USB_Bootloader.cydwr">
<Hidden v="False" />
</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>
<build_action v="NONE" />
<BootloaderTag hexFile="" elfFile="" />
<current_generation v="0" />
</CyGuid_fec8f9e8-2365-4bdb-96d3-a4380222e01b>
-</CyXmlSerializer>
\ No newline at end of file
+</CyXmlSerializer>
--- /dev/null
+// Copyright (C) 2014 Michael McMaster <michael@codesrc.com>
+//
+// This file is part of SCSI2SD.
+//
+// SCSI2SD is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// SCSI2SD is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with SCSI2SD. If not, see <http://www.gnu.org/licenses/>.
+
+#include "Firmware.hh"
+
+extern "C"
+{
+#include "cybtldr_parse.h"
+}
+
+#include <functional>
+#include <sstream>
+#include <stdexcept>
+
+#include <string.h>
+
+using namespace SCSI2SD;
+
+namespace
+{
+ struct FirmwareFile
+ {
+ ~FirmwareFile()
+ {
+ CyBtldr_CloseDataFile();
+ }
+ };
+}
+
+Firmware::Firmware(const std::string& path)
+{
+ if (CyBtldr_OpenDataFile(path.c_str()) != CYRET_SUCCESS)
+ {
+ std::stringstream msg;
+ msg << "Could not open file: " << path;
+ throw std::runtime_error(msg.str());
+ }
+
+ FirmwareFile closeOnReturn;
+
+ uint8_t buffer[MAX_BUFFER_SIZE];
+ unsigned int lineSize;
+ if (
+ CyBtldr_ReadLine(&lineSize, reinterpret_cast<char*>(buffer))
+ != CYRET_SUCCESS
+ )
+ {
+ std::stringstream msg;
+ msg << "Could not read file: " << path;
+ throw std::runtime_error(msg.str());
+ }
+
+ {
+ unsigned long silId;
+ unsigned char silRev[MAX_BUFFER_SIZE];
+ unsigned char chksum[MAX_BUFFER_SIZE];
+ if (
+ CyBtldr_ParseHeader(
+ lineSize,
+ buffer,
+ &silId,
+ silRev,
+ chksum)
+ != CYRET_SUCCESS)
+ {
+ std::stringstream msg;
+ msg << "Premature end of file: " << path;
+ throw std::runtime_error(msg.str());
+ }
+ mySiliconId = silId;
+ mySiliconRev =
+ std::string(
+ reinterpret_cast<char*>(silRev),
+ strnlen(reinterpret_cast<char*>(silRev), MAX_BUFFER_SIZE)
+ );
+ }
+
+ // Count the number of flash rows. This is used to show "percentage
+ // complete" when uploading the firmware.
+ myTotalFlashRows = 0;
+ while (
+ CyBtldr_ReadLine(&lineSize, reinterpret_cast<char*>(buffer))
+ == CYRET_SUCCESS
+ )
+ {
+ myTotalFlashRows++;
+ }
+}
+
+Firmware::~Firmware()
+{
+}
+
--- /dev/null
+// Copyright (C) 2014 Michael McMaster <michael@codesrc.com>
+//
+// This file is part of SCSI2SD.
+//
+// SCSI2SD is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// SCSI2SD is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with SCSI2SD. If not, see <http://www.gnu.org/licenses/>.
+
+#ifndef Firmware_HH
+#define Firmware_HH
+
+#include <cstdint>
+#include <string>
+
+namespace SCSI2SD
+{
+
+//
+// Warning: The Cypress API (used by the Firmware class) uses global data and
+// is NOT thread safe.
+//
+class Firmware
+{
+public:
+ Firmware(const std::string& path);
+ ~Firmware();
+
+ uint64_t siliconId() const { return mySiliconId; }
+ std::string siliconRev() const { return mySiliconRev; }
+
+ int totalFlashRows() const { return myTotalFlashRows; }
+
+private:
+ uint64_t mySiliconId;
+ std::string mySiliconRev;
+ int myTotalFlashRows;
+};
+
+} // namespace
+#endif
-all: build/bootloaderhost
+VPATH=cybootloaderutils
-CYAPI = \
- cybootloaderutils/cybtldr_api2.c \
- cybootloaderutils/cybtldr_api.c \
- cybootloaderutils/cybtldr_command.c \
- cybootloaderutils/cybtldr_parse.c \
-
-CFLAGS += -Wall -Wno-pointer-sign
+CPPFLAGS = -I cybootloaderutils -I hidapi/hidapi
+CFLAGS += -Wall -Wno-pointer-sign -O2
+CXXFLAGS += -Wall -std=c++11 -O2
UNAME_S := $(shell uname -s)
ifeq ($(UNAME_S),Linux)
- HID_C = hidapi/linux/hid.c
+ VPATH += hidapi/linux
LDFLAGS += -ludev
+ BUILD=build/linux
endif
ifeq ($(UNAME_S),Darwin)
# Should match OSX
- HID_C = hidapi/mac/hid.c
+ VPATH += hidapi/mac
LDFLAGS += -framework IOKit -framework CoreFoundation
- CFLAGS += -mmacosx-version-min=10.5 -arch x86_64 -arch i386 -arch ppc -isysroot /Xcode3.1.4/SDKs/MacOSX10.5.sdk
+ CPPFLAGS += -isysroot /Xcode3.1.4/SDKs/MacOSX10.5.sdk
+ CFLAGS += -mmacosx-version-min=10.5 -arch x86_64 -arch i386 -arch ppc
+ CXXFLAGS += -mmacosx-version-min=10.5 -arch x86_64 -arch i386 -arch ppc
CC=/Xcode3.1.4/usr/bin/gcc
+ CXX=/Xcode3.1.4/usr/bin/g++
+ BUILD=build/mac
endif
+all: $(BUILD)/bootloaderhost
+
+CYAPI = \
+ $(BUILD)/cybtldr_api2.o \
+ $(BUILD)/cybtldr_api.o \
+ $(BUILD)/cybtldr_command.o \
+ $(BUILD)/cybtldr_parse.o \
+
+
+HIDAPI = \
+ $(BUILD)/hid.o \
+
-build/bootloaderhost: main.c $(HID_C) $(CYAPI)
+OBJ = \
+ $(CYAPI) $(HIDAPI) \
+ $(BUILD)/main.o \
+ $(BUILD)/Firmware.o \
+ $(BUILD)/SCSI2SD_Bootloader.o \
+ $(BUILD)/SCSI2SD_HID.o \
+
+$(BUILD)/%.o: %.c
+ mkdir -p $(dir $@)
+ $(CC) $(CPPFLAGS) $(CFLAGS) $^ -c -o $@
+
+$(BUILD)/%.o: %.cc
mkdir -p $(dir $@)
- $(CC) $(CFLAGS) -I cybootloaderutils -I hidapi/hidapi $^ $(LDFLAGS) -o $@
+ $(CXX) $(CPPFLAGS) $(CXXFLAGS) $^ -c -o $@
+
+$(BUILD)/bootloaderhost: $(OBJ)
+ mkdir -p $(dir $@)
+ $(CXX) $(CXXFLAGS) $^ $(LDFLAGS) -o $@
clean:
- rm build/bootloaderhost
+ rm $(BUILD)/bootloaderhost $(OBJ)
+
--- /dev/null
+// Copyright (C) 2014 Michael McMaster <michael@codesrc.com>
+//
+// This file is part of SCSI2SD.
+//
+// SCSI2SD is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// SCSI2SD is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with SCSI2SD. If not, see <http://www.gnu.org/licenses/>.
+
+#include "SCSI2SD_Bootloader.hh"
+
+#include <cstdint>
+#include <iostream>
+#include <sstream>
+#include <stdexcept>
+
+
+extern "C"
+{
+#include "hidapi.h"
+#include "cybtldr_api.h"
+#include "cybtldr_api2.h"
+}
+#include <string.h>
+
+using namespace SCSI2SD;
+
+hid_device* SCSI2SDHID_handle = NULL;
+
+// cybtldr interface.
+extern "C" int
+SCSI2SDHID_OpenConnection(void)
+{
+ return 0;
+}
+
+extern "C" int
+SCSI2SDHID_CloseConnection(void)
+{
+ return 0;
+}
+
+extern "C" int
+SCSI2SDHID_ReadData(unsigned char* data, int count)
+{
+ uint8_t buf[65];
+ buf[0] = 0; // Report ID
+
+ int result = hid_read(SCSI2SDHID_handle, buf, count);
+
+ if (result < 0)
+ {
+ std::cerr << "USB HID Read Failure: " <<
+ hid_error(SCSI2SDHID_handle) << std::endl;
+ }
+
+ memcpy(data, buf, count);
+
+ return (result >= 0) ? 0 : -1;
+}
+
+extern "C" int
+SCSI2SDHID_WriteData(unsigned char* data, int count)
+{
+ uint8_t buf[65];
+ buf[0] = 0; // report ID
+ int i;
+ for (i = 0; i < count; ++i)
+ {
+ buf[i+1] = data[i];
+ }
+ int result = hid_write(SCSI2SDHID_handle, buf, count + 1);
+
+ if (result < 0)
+ {
+ std::cerr << "USB HID Write Failure: " <<
+ hid_error(SCSI2SDHID_handle) << std::endl;
+ }
+
+ return (result >= 0) ? 0 : -1;
+}
+
+Bootloader::Bootloader(hid_device_info* hidInfo) :
+ myHidInfo(hidInfo),
+ myBootloaderHandle(NULL)
+{
+ myBootloaderHandle = hid_open_path(hidInfo->path);
+ if (!myBootloaderHandle)
+ {
+ hid_free_enumeration(myHidInfo);
+ myHidInfo = NULL;
+
+ std::stringstream msg;
+ msg << "Error opening HID device " << hidInfo->path << std::endl;
+ throw std::runtime_error(msg.str());
+ }
+}
+
+Bootloader::~Bootloader()
+{
+ if (myBootloaderHandle)
+ {
+ hid_close(myBootloaderHandle);
+ }
+
+ hid_free_enumeration(myHidInfo);
+}
+
+Bootloader*
+Bootloader::Open()
+{
+ hid_device_info* dev = hid_enumerate(VENDOR_ID, PRODUCT_ID);
+ if (dev)
+ {
+ return new Bootloader(dev);
+ }
+ else
+ {
+ return NULL;
+ }
+}
+
+Bootloader::HWInfo
+Bootloader::getHWInfo() const
+{
+ HWInfo info = {"unknown", "unknown", "unknown"};
+
+ switch (myHidInfo->release_number)
+ {
+ case 0x3001:
+ info.desc = "3.5\" SCSI2SD (green)";
+ info.version = "V3.0";
+ info.firmwareName = "SCSI2SD-V3.cyacd";
+ break;
+ case 0x3002:
+ info.desc = "3.5\" SCSI2SD (yellow) or 2.5\" SCSI2SD for Apple Powerbook";
+ info.version = "V4.1/V4.2";
+ info.firmwareName = "SCSI2SD-V4.cyacd";
+ break;
+ }
+ return info;
+}
+
+bool
+Bootloader::isCorrectFirmware(const std::string& path) const
+{
+ HWInfo info = getHWInfo();
+ return path.rfind(info.firmwareName) != std::string::npos;
+}
+
+std::string
+Bootloader::getDevicePath() const
+{
+ return myHidInfo->path;
+}
+
+std::wstring
+Bootloader::getManufacturer() const
+{
+ return myHidInfo->manufacturer_string;
+}
+
+std::wstring
+Bootloader::getProductString() const
+{
+ return myHidInfo->product_string;
+}
+
+void
+Bootloader::load(const std::string& path, void (*progress)(uint8_t, uint16_t))
+{
+ CyBtldr_CommunicationsData cyComms =
+ {
+ &SCSI2SDHID_OpenConnection,
+ &SCSI2SDHID_CloseConnection,
+ &SCSI2SDHID_ReadData,
+ &SCSI2SDHID_WriteData,
+ HID_PACKET_SIZE
+ };
+
+ SCSI2SDHID_handle = myBootloaderHandle;
+
+ int result = CyBtldr_Program(
+ path.c_str(),
+ &cyComms,
+ progress);
+
+ if (result)
+ {
+ throw std::runtime_error("Firmware update failed");
+ }
+}
+
--- /dev/null
+// Copyright (C) 2014 Michael McMaster <michael@codesrc.com>
+//
+// This file is part of SCSI2SD.
+//
+// SCSI2SD is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// SCSI2SD is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with SCSI2SD. If not, see <http://www.gnu.org/licenses/>.
+
+#ifndef SCSI2SD_Bootloader_H
+#define SCSI2SD_Bootloader_H
+
+#include "hidapi.h"
+
+#include <cstdint>
+#include <string>
+
+namespace SCSI2SD
+{
+
+class Bootloader
+{
+public:
+ static const uint16_t VENDOR_ID = 0x04B4; // Cypress
+ static const uint16_t PRODUCT_ID = 0xB71D; // Default PSoC3/5LP Bootloader
+
+ static const size_t HID_PACKET_SIZE = 64;
+
+ static Bootloader* Open();
+
+ ~Bootloader();
+
+ struct HWInfo
+ {
+ std::string desc;
+ std::string version;
+ std::string firmwareName;
+ };
+ HWInfo getHWInfo() const;
+
+ // USB HID data
+ std::string getDevicePath() const;
+ std::wstring getManufacturer() const;
+ std::wstring getProductString() const;
+
+ bool isCorrectFirmware(const std::string& path) const;
+
+ // progress function accepts flash array ID and row Number
+ void load(const std::string& path, void (*progress)(uint8_t, uint16_t));
+private:
+ Bootloader(hid_device_info* hidInfo);
+
+ hid_device_info* myHidInfo;
+ hid_device* myBootloaderHandle;
+};
+
+} // namespace
+#endif
--- /dev/null
+// Copyright (C) 2014 Michael McMaster <michael@codesrc.com>
+//
+// This file is part of SCSI2SD.
+//
+// SCSI2SD is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// SCSI2SD is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with SCSI2SD. If not, see <http://www.gnu.org/licenses/>.
+#include "SCSI2SD_HID.hh"
+
+#include <cassert>
+#include <stdexcept>
+#include <sstream>
+
+#include <iostream>
+#include <string.h> // memcpy
+
+using namespace SCSI2SD;
+
+HID::HID(hid_device_info* hidInfo) :
+ myHidInfo(hidInfo),
+ myConfigHandle(NULL),
+ myDebugHandle(NULL),
+ myFirmwareVersion(0),
+ mySDCapacity(0)
+{
+ while (hidInfo)
+ {
+ if (hidInfo->interface_number == CONFIG_INTERFACE)
+ {
+ myConfigHandle = hid_open_path(hidInfo->path);
+ }
+ else if (hidInfo->interface_number == DEBUG_INTERFACE)
+ {
+ myDebugHandle = hid_open_path(hidInfo->path);
+ readDebugData();
+ }
+ hidInfo = hidInfo->next;
+ }
+}
+
+HID::~HID()
+{
+ if (myConfigHandle)
+ {
+ hid_close(myConfigHandle);
+ }
+ if (myDebugHandle)
+ {
+ hid_close(myDebugHandle);
+ }
+
+ hid_free_enumeration(myHidInfo);
+}
+
+HID*
+HID::Open()
+{
+ hid_device_info* dev = hid_enumerate(VENDOR_ID, PRODUCT_ID);
+ if (dev)
+ {
+ return new HID(dev);
+ }
+ else
+ {
+ return NULL;
+ }
+}
+
+void
+HID::enterBootloader()
+{
+ // Reboot commands added in firmware 3.5
+ if (!myDebugHandle)
+ {
+ throw std::runtime_error(
+ "Cannot enter SCSI2SD bootloader: debug interface not found");
+ }
+ else if (myFirmwareVersion == 0)
+ {
+ throw std::runtime_error(
+ "Cannot enter SCSI2SD bootloader: old firmware version running.\n"
+ "The SCSI2SD board cannot reset itself. Please disconnect and \n"
+ "reconnect the USB cable.\n");
+ }
+ else
+ {
+ uint8_t hidBuf[HID_PACKET_SIZE + 1] =
+ {
+ 0x00, // Report ID;
+ 0x01 // Reboot command
+ // 63 bytes unused.
+ };
+
+ int result = hid_write(myDebugHandle, hidBuf, sizeof(hidBuf));
+ if (result < 0)
+ {
+ const wchar_t* err = hid_error(myDebugHandle);
+ std::stringstream ss;
+ ss << "USB HID write failure: " << err;
+ throw std::runtime_error(ss.str());
+ }
+ }
+}
+
+void
+HID::readConfig(uint8_t* buffer, size_t len)
+{
+ assert(len >= 0);
+ buffer[0] = 0; // report id
+
+ int result = hid_read(myConfigHandle, buffer, len);
+
+ if (result < 0)
+ {
+ const wchar_t* err = hid_error(myConfigHandle);
+ std::stringstream ss;
+ ss << "USB HID read failure: " << err;
+ throw std::runtime_error(ss.str());
+ }
+}
+
+void
+HID::saveConfig(uint8_t* buffer, size_t len)
+{
+ assert(len >= 0 && len <= HID_PACKET_SIZE);
+
+ uint8_t hidBuf[HID_PACKET_SIZE + 1] =
+ {
+ 0x00, // Report ID;
+ };
+ memcpy(&hidBuf[1], buffer, len);
+
+ int result = hid_write(myConfigHandle, hidBuf, len + 1);
+
+ if (result < 0)
+ {
+ const wchar_t* err = hid_error(myConfigHandle);
+ std::stringstream ss;
+ ss << "USB HID write failure: " << err;
+ throw std::runtime_error(ss.str());
+ }
+
+
+}
+
+void
+HID::readDebugData()
+{
+ uint8_t buf[HID_PACKET_SIZE];
+ buf[0] = 0; // report id
+ int result = hid_read(myDebugHandle, buf, HID_PACKET_SIZE);
+
+ if (result < 0)
+ {
+ const wchar_t* err = hid_error(myDebugHandle);
+ std::stringstream ss;
+ ss << "USB HID read failure: " << err;
+ throw std::runtime_error(ss.str());
+ }
+ myFirmwareVersion = (((uint16_t)buf[62]) << 8) | buf[63];
+
+ mySDCapacity =
+ (((uint32_t)buf[58]) << 24) |
+ (((uint32_t)buf[59]) << 16) |
+ (((uint32_t)buf[60]) << 8) |
+ ((uint32_t)buf[61]);
+}
+
+std::string
+HID::getFirmwareVersionStr() const
+{
+ if (myFirmwareVersion == 0)
+ {
+ return "Unknown (3.0 - 3.4)";
+ }
+ else
+ {
+ std::stringstream ver;
+ ver << std::hex <<
+ (myFirmwareVersion >> 8) <<
+ '.' << (myFirmwareVersion & 0xFF);
+ return ver.str();
+ }
+}
+
+
--- /dev/null
+// Copyright (C) 2014 Michael McMaster <michael@codesrc.com>
+//
+// This file is part of SCSI2SD.
+//
+// SCSI2SD is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// SCSI2SD is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with SCSI2SD. If not, see <http://www.gnu.org/licenses/>.
+
+#ifndef SCSI2SD_HID_H
+#define SCSI2SD_HID_H
+
+#include "hidapi.h"
+
+#include <cstdint>
+#include <string>
+
+namespace SCSI2SD
+{
+
+class HID
+{
+public:
+ static const uint16_t VENDOR_ID = 0x04B4; // Cypress
+ static const uint16_t PRODUCT_ID = 0x1337; // SCSI2SD application firmware
+
+ static const int CONFIG_INTERFACE = 0;
+ static const int DEBUG_INTERFACE = 1;
+
+ static const size_t HID_PACKET_SIZE = 64;
+
+ static HID* Open();
+
+ ~HID();
+
+ uint16_t getFirmwareVersion() const { return myFirmwareVersion; }
+ std::string getFirmwareVersionStr() const;
+ uint32_t getSDCapacity() const { return mySDCapacity; }
+
+
+ void enterBootloader();
+
+ void readConfig(uint8_t* buffer, size_t len);
+ void saveConfig(uint8_t* buffer, size_t len);
+private:
+ HID(hid_device_info* hidInfo);
+ void readDebugData();
+
+ hid_device_info* myHidInfo;
+ hid_device* myConfigHandle;
+ hid_device* myDebugHandle;
+
+ // Read-only data from the debug interface.
+ uint16_t myFirmwareVersion;
+ uint32_t mySDCapacity;
+};
+
+} // namespace
+
+#endif
+++ /dev/null
-// Copyright (C) 2013 Michael McMaster <michael@codesrc.com>
-//
-// This file is part of SCSI2SD.
-//
-// SCSI2SD is free software: you can redistribute it and/or modify
-// it under the terms of the GNU General Public License as published by
-// the Free Software Foundation, either version 3 of the License, or
-// (at your option) any later version.
-//
-// SCSI2SD is distributed in the hope that it will be useful,
-// but WITHOUT ANY WARRANTY; without even the implied warranty of
-// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-// GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License
-// along with SCSI2SD. If not, see <http://www.gnu.org/licenses/>.
-
-#include <stdint.h>
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <unistd.h>
-
-
-#include "hidapi.h"
-#include "cybtldr_api.h"
-#include "cybtldr_api2.h"
-
-hid_device *handle = NULL;
-
-static int OpenConnection(void)
-{
- return 0;
-}
-
-static int CloseConnection(void)
-{
- return 0;
-}
-
-static int ReadData(unsigned char* data, int count)
-{
- unsigned char buf[65];
- buf[0] = 0; // Report ID
-
- int result = hid_read(handle, buf, count);
-
- if (result < 0)
- {
- fprintf(stderr, "USB HID Read Failure: %ls\n", hid_error(handle));
- }
-
- memcpy(data, buf, count);
-
- return (result >= 0) ? 0 : -1;
-}
-
-static int WriteData(unsigned char* data, int count)
-{
- unsigned char buf[65];
- buf[0] = 0; // report ID
- int i;
- for (i = 0; i < count; ++i)
- {
- buf[i+1] = data[i];
- }
- int result = hid_write(handle, buf, count + 1);
-
- if (result < 0)
- {
- fprintf(stderr, "USB HID Write Failure: %ls\n", hid_error(handle));
- }
-
- return (result >= 0) ? 0 : -1;
-}
-
-
-static void ProgressUpdate(unsigned char arrayId, unsigned short rowNum)
-{
- printf("Programmed flash array %d, row %d\n", arrayId, rowNum);
-}
-
-static void usage()
-{
- printf("Usage: bootloaderhost [-v UsbVendorId] [-p UsbProductId] [-f] /path/to/firmware.cyacd\n");
- printf("\t-f\tForce, even if the firmware doesn't match the target board.\n");
- printf("\n\n");
-}
-
-int main(int argc, char* argv[])
-{
- CyBtldr_CommunicationsData cyComms =
- {
- &OpenConnection,
- &CloseConnection,
- &ReadData,
- &WriteData,
- 64
- };
-
- printf("PSoC 3/5LP USB HID Bootloader Host\n");
- printf("Copyright (C) 2013 Michael McMaster <michael@codesrc.com>\n\n");
-
- uint16_t vendorId = 0x04B4; // Cypress
- uint16_t productId = 0xB71D; // Default PSoC3/5LP Bootloader
- int force = 0;
-
- opterr = 0;
- int c;
- while ((c = getopt(argc, argv, "v:p:f")) != -1)
- {
- switch (c)
- {
- case 'v':
- sscanf(optarg, "%hx", &vendorId);
- break;
- case 'p':
- sscanf(optarg, "%hx", &productId);
- break;
- case 'f':
- force = 1;
- break;
- case '?':
- usage();
- exit(1);
- }
- }
-
- const char* filename;
- if (optind < argc)
- {
- filename = argv[optind];
- }
- else
- {
- usage();
- exit(1);
- }
-
- printf(
- "USB device parameters\n\tVendor ID:\t0x%04X\n\tProduct ID:\t0x%04X\n",
- vendorId,
- productId);
-
- // Enumerate and print the HID devices on the system
- struct hid_device_info *dev = hid_enumerate(vendorId, productId);
-
- if (!dev)
- {
- printf("Waiting for device connection\n");
- printf("Connect USB cable to the bus-powered device now, or otherwise reset the device.\n");
- }
-
- while (!dev)
- {
- dev = hid_enumerate(vendorId, productId);
- usleep(10000); // 10ms
- }
-
- printf("Device Found\n type: %04hx %04hx\n path: %s\n serial_number: %ls",
- dev->vendor_id, dev->product_id, dev->path, dev->serial_number);
- printf("\n");
- printf(" Manufacturer: %ls\n", dev->manufacturer_string);
- printf(" Product: %ls\n", dev->product_string);
-
- int fileMismatch = 0;
- const char* expectedName = NULL;
- switch (dev->release_number)
- {
- case 0x3001:
- printf(" Release: 3.5\" SCSI2SD\n");
- expectedName = "SCSI2SD.cyacd";
- if (strncasecmp(filename, expectedName, 13))
- {
- fileMismatch = 1;
- }
- break;
- case 0x3002:
- printf(" Release: 2.5\" SCSI2SD for Apple Powerbook\n");
- expectedName = "pbook.cyacd";
- if (strncasecmp(filename, expectedName, 11))
- {
- fileMismatch = 1;
- }
- break;
- default:
- printf(" Release: Unknown hardware\n");
- expectedName = "unknown";
- fileMismatch = 1;
- }
- printf("\n");
-
- if (fileMismatch && !force)
- {
- fprintf(stderr, "ERROR: Unexpected firmware file. Expected: \"%s\"\n"
- "Using firmware design for a different board may destroy your "
- "hardware.\n"
- "If you still wish to proceed, try again with the \"-f\" flag.\n",
- expectedName);
- exit(1);
- }
- //hid_free_enumeration(devs);
-
- // Open the device using the VID, PID,
- // and optionally the Serial number.
- handle = hid_open(vendorId, productId, NULL);
- if (!handle)
- {
- fprintf(
- stderr,
- "Could not open device %s. Check permissions.\n", dev->path
- );
- exit(1);
- }
-
-
- printf("Starting firmware upload: %s\n", filename);
- int result = CyBtldr_Program(
- filename,
- &cyComms,
- &ProgressUpdate);
- if (result == 0)
- {
- printf("Firmware update complete\n");
- }
- else
- {
- printf("Firmware update failed\n");
- }
-
- return 0;
-}
-
--- /dev/null
+// Copyright (C) 2013 Michael McMaster <michael@codesrc.com>
+//
+// This file is part of SCSI2SD.
+//
+// SCSI2SD is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// SCSI2SD is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with SCSI2SD. If not, see <http://www.gnu.org/licenses/>.
+
+#include "SCSI2SD_HID.hh"
+#include "SCSI2SD_Bootloader.hh"
+#include "Firmware.hh"
+
+#include <cstdint>
+#include <iomanip>
+#include <iostream>
+#include <memory>
+#include <sstream>
+
+#include <stdio.h>
+#include <unistd.h>
+
+using namespace SCSI2SD;
+
+extern "C"
+void ProgressUpdate(unsigned char arrayId, unsigned short rowNum)
+{
+ //std::cerr <<
+ //"Programmed flash array " << static_cast<int>(arrayId) <<
+ // ", row " << rowNum << std::endl;
+ std::cout << "." << std::flush;
+}
+
+static void usage()
+{
+ std::cout << "Usage: bootloaderhost [-f] "
+ "/path/to/firmware.cyacd\n" <<
+ "\t-f\tForce, even if the firmware doesn't match the target board.\n\n" <<
+ std::endl;
+}
+
+
+int main(int argc, char* argv[])
+{
+ std::cout <<
+ "PSoC 3/5LP USB HID Bootloader Host\n" <<
+ "Copyright (C) 2013 Michael McMaster <michael@codesrc.com>\n" <<
+ std::endl;
+
+ int force = 0;
+
+ opterr = 0;
+ int c;
+ while ((c = getopt(argc, argv, "v:p:f")) != -1)
+ {
+ switch (c)
+ {
+ case 'f':
+ force = 1;
+ break;
+ case '?':
+ usage();
+ exit(1);
+ }
+ }
+
+ std::string filename;
+ if (optind < argc)
+ {
+ filename = argv[optind];
+ }
+ else
+ {
+ usage();
+ exit(1);
+ }
+
+ // Enumerate and print the HID devices on the system
+ std::shared_ptr<Bootloader> bootloader(Bootloader::Open());
+ std::shared_ptr<HID> hid(HID::Open());
+
+ if (hid)
+ {
+ try
+ {
+ hid->enterBootloader();
+ }
+ catch (std::exception& e)
+ {
+ std::cerr << e.what() << std::endl;
+ hid.reset();
+ }
+ }
+
+ if (!hid)
+ {
+ std::cout <<
+ "Waiting for device connection" << std::endl <<
+ "Connect USB cable to the bus-powered device now, or otherwise "
+ "reset the device." << std::endl;
+ }
+
+
+ while (!bootloader)
+ {
+ bootloader.reset(Bootloader::Open());
+
+ if (!bootloader && !hid)
+ {
+ hid.reset(HID::Open());
+ if (hid)
+ {
+ try
+ {
+ hid->enterBootloader();
+ }
+ catch (std::exception& e)
+ {
+ std::cerr << e.what();
+ }
+ }
+ }
+
+ if (!bootloader)
+ {
+ usleep(100000); // 100ms
+ }
+ }
+
+ std::stringstream foundMsg;
+ foundMsg <<
+ "Device Found\n" <<
+ " type:\t\t\t" << std::setw(4) << std::hex <<
+ Bootloader::VENDOR_ID << " " <<
+ Bootloader::PRODUCT_ID <<
+ "\n" <<
+ " path:\t\t\t" << bootloader->getDevicePath() << "\n";
+ std::cout << foundMsg.str() << std::endl;
+
+ Bootloader::HWInfo hwInfo(bootloader->getHWInfo());
+ std::cout <<
+ " Board:\t\t" << hwInfo.desc << "\n" <<
+ " Revision:\t\t" << hwInfo.version << std::endl;
+
+ if (hid)
+ {
+ std::cout <<
+ " Existing firmware:\t" <<
+ hid->getFirmwareVersionStr() << std::endl;
+ }
+
+
+ if (!bootloader->isCorrectFirmware(filename) && !force)
+ {
+ std::cerr <<
+ "ERROR: Unexpected firmware file. Expected: \""
+ << hwInfo.firmwareName << "\"\n\n" <<
+ "Using firmware design for a different board will destroy your " <<
+ "hardware.\n" <<
+ "If you still wish to proceed, try again with the \"-f\" flag.\n" <<
+ std::endl;
+ exit(1);
+ }
+
+ Firmware firmware(filename);
+
+ std::stringstream firmMsg;
+ firmMsg <<
+ " Firmware Silicon ID:\t" << std::hex << firmware.siliconId() <<
+ "\n" <<
+ std::cout << firmMsg.str() << std::endl;
+
+ std::cout << "Starting firmware upload: " << filename << std::endl;
+
+ try
+ {
+ bootloader->load(filename, &ProgressUpdate);
+ std::cout << "Firmware upload complete." << std::endl;
+ }
+ catch (std::exception& e)
+ {
+ std::cerr << "ERROR: Firmware update failed.\n" << e.what() << std::endl;
+ exit(1);
+ }
+
+ return 0;
+}
+
-all: build/scsi2sd-config
-CFLAGS += -Wall
+CPPFLAGS = -I ../bootloaderhost/hidapi/hidapi -I ../bootloaderhost
+CFLAGS += -Wall -Wno-pointer-sign -O2
+CXXFLAGS += -Wall -std=c++11 -O2
+VPATH += ../bootloaderhost
UNAME_S := $(shell uname -s)
ifeq ($(UNAME_S),Linux)
- HID_C = ../bootloaderhost/hidapi/linux/hid.c
+ VPATH += ../bootloaderhost/hidapi/linux
LDFLAGS += -ludev
+ BUILD=build/linux
endif
ifeq ($(UNAME_S),Darwin)
# Should match OSX
- HID_C = ../bootloaderhost/hidapi/mac/hid.c
+ VPATH += ../bootloaderhost/hidapi/mac
LDFLAGS += -framework IOKit -framework CoreFoundation
- CFLAGS += -mmacosx-version-min=10.5 -arch x86_64 -arch i386 -arch ppc -isysroot /Xcode3.1.4/SDKs/MacOSX10.5.sdk
- CC = /Xcode3.1.4/usr/bin/gcc
+ CPPFLAGS += -isysroot /Xcode3.1.4/SDKs/MacOSX10.5.sdk
+ CFLAGS += -mmacosx-version-min=10.5 -arch x86_64 -arch i386 -arch ppc
+ CXXFLAGS += -mmacosx-version-min=10.5 -arch x86_64 -arch i386 -arch ppc
+ CC=/Xcode3.1.4/usr/bin/gcc
+ CXX=/Xcode3.1.4/usr/bin/g++
+ BUILD=build/mac
endif
+all: $(BUILD)/scsi2sd-config
-build/scsi2sd-config: main.c $(HID_C) $(CYAPI)
+HIDAPI = \
+ $(BUILD)/hid.o \
+
+OBJ = \
+ $(HIDAPI) \
+ $(BUILD)/scsi2sd-config.o \
+ $(BUILD)/SCSI2SD_HID.o \
+
+$(BUILD)/%.o: %.c
+ mkdir -p $(dir $@)
+ $(CC) $(CPPFLAGS) $(CFLAGS) $^ -c -o $@
+
+$(BUILD)/%.o: %.cc
+ mkdir -p $(dir $@)
+ $(CXX) $(CPPFLAGS) $(CXXFLAGS) $^ -c -o $@
+
+$(BUILD)/scsi2sd-config: $(OBJ)
mkdir -p $(dir $@)
- $(CC) $(CFLAGS) -I ../bootloaderhost/hidapi/hidapi $^ $(LDFLAGS) -o $@
+ $(CXX) $(CXXFLAGS) $^ $(LDFLAGS) -o $@
clean:
- rm build/scsi2sd-config
+ rm $(BUILD)/scsi2sd-config $(OBJ)
// You should have received a copy of the GNU General Public License
// along with SCSI2SD. If not, see <http://www.gnu.org/licenses/>.
+#include "SCSI2SD_HID.hh"
+
+#include <iomanip>
+#include <iostream>
+#include <memory>
+#include <sstream>
+
#include <getopt.h>
#include <inttypes.h>
#include <stdint.h>
#define MIN(a,b) (a < b ? a : b)
+using namespace SCSI2SD;
+
enum
{
PARAM_ID,
PARAM_VENDOR,
PARAM_PRODID,
PARAM_REV,
- PARAM_BYTESPERSECTOR
+ PARAM_BYTESPERSECTOR,
+ PARAM_RESET
};
// Must be consistent with the structure defined in the SCSI2SD config.h header.
// We always transfer data in network byte order.
-typedef struct __attribute((packed))
+struct __attribute__((packed)) ConfigPacket
{
uint8_t scsiId;
char vendor[8];
// Pad to 64 bytes, which is what we can fit into a USB HID packet.
char reserved[26];
-} ConfigPacket;
+
+ void fromNet()
+ {
+ maxSectors = ntohl(maxSectors);
+ bytesPerSector = ntohs(bytesPerSector);
+ }
+ void toNet()
+ {
+ maxSectors = htonl(maxSectors);
+ bytesPerSector = htons(bytesPerSector);
+ }
+ void reset()
+ {
+ scsiId = 0;
+ strcpy(vendor, " codesrc");
+ strcpy(prodId, " SCSI2SD");
+ strcpy(revision, " 3.5");
+ enableParity = 1;
+ enableUnitAttention = 1;
+ reserved1 = 0;
+ maxSectors = 0;
+ bytesPerSector = 512;
+ }
+};
static void printConfig(ConfigPacket* packet)
{
}
}
-static int readConfig(hid_device* handle, ConfigPacket* packet)
-{
- // First byte is the report ID (0)
- unsigned char buf[1 + sizeof(ConfigPacket)];
- memset(buf, 0, sizeof(buf));
- memset(packet, 0, sizeof(ConfigPacket));
- int result = hid_read(handle, buf, sizeof(buf));
-
- if (result < 0)
- {
- fprintf(stderr, "USB HID Read Failure: %ls\n", hid_error(handle));
- }
-
- memcpy(packet, buf, result);
- packet->maxSectors = ntohl(packet->maxSectors);
- packet->bytesPerSector = ntohs(packet->bytesPerSector);
-
- return result;
-}
-
-static int writeConfig(hid_device* handle, ConfigPacket* packet)
-{
- unsigned char buf[1 + sizeof(ConfigPacket)];
- buf[0] = 0; // report ID
-
- packet->maxSectors = htonl(packet->maxSectors);
- packet->bytesPerSector = htons(packet->bytesPerSector);
- memcpy(buf + 1, packet, sizeof(ConfigPacket));
- packet->maxSectors = ntohl(packet->maxSectors);
- packet->bytesPerSector = ntohs(packet->bytesPerSector);
-
- int result = hid_write(handle, buf, sizeof(buf));
-
- if (result < 0)
- {
- fprintf(stderr, "USB HID Write Failure: %ls\n", hid_error(handle));
- }
-
- return result;
-}
-
static void usage()
{
printf("Usage: scsi2sd-config [options...]\n");
printf("--vendor={vendor}\tSets the reported device vendor. Up to 8 characters.\n\n");
printf("--prod-id={prod-id}\tSets the reported product ID. Up to 16 characters.\n\n");
printf("--rev={revision}\tSets the reported device revision. Up to 4 characters.\n\n");
+ printf("--reset\tRevert all settings to factory defaults.\n\n");
printf("\n");
printf("\nThe current configuration settings are displayed if no options are supplied");
printf("\n\n");
printf("SCSI2SD Configuration Utility.\n");
printf("Copyright (C) 2013 Michael McMaster <michael@codesrc.com>\n\n");
- uint16_t vendorId = 0x04B4; // Cypress
- uint16_t productId = 0x1337; // SCSI2SD
-
printf(
"USB device parameters\n\tVendor ID:\t0x%04X\n\tProduct ID:\t0x%04X\n",
- vendorId,
- productId);
+ HID::VENDOR_ID,
+ HID::PRODUCT_ID);
// Enumerate and print the HID devices on the system
- struct hid_device_info *dev = hid_enumerate(vendorId, productId);
- while (dev && dev->interface_number != 0)
- {
- dev = dev->next;
- }
+ std::shared_ptr<HID> scsi2sdHID(HID::Open());
- if (!dev)
+ if (!scsi2sdHID)
{
fprintf(stderr, "ERROR: SCSI2SD USB device not found.\n");
exit(1);
}
- printf("USB Device Found\n type: %04hx %04hx\n path: %s\n serial_number: %ls",
- dev->vendor_id, dev->product_id, dev->path, dev->serial_number);
- printf("\n");
- printf(" Manufacturer: %ls\n", dev->manufacturer_string);
- printf(" Product: %ls\n", dev->product_string);
- printf("\n");
+ std::stringstream foundMsg;
+ foundMsg <<
+ "Device Found\n" <<
+ " Firmware Version:\t" << scsi2sdHID->getFirmwareVersionStr();
- // Open the device using the VID, PID,
- // and optionally the Serial number.
- hid_device* handle = hid_open(vendorId, productId, NULL);
- if (!handle)
+ std::cout << foundMsg.str() << std::endl;
+
+ ConfigPacket packet;
+ try
{
- fprintf(
- stderr,
- "ERROR: Could not open device %s. Check permissions.\n", dev->path
+ scsi2sdHID->readConfig(
+ reinterpret_cast<uint8_t*>(&packet),
+ sizeof(packet)
);
- exit(1);
+ packet.fromNet();
}
-
- ConfigPacket packet;
- if (readConfig(handle, &packet) <= 0)
+ catch (std::exception& e)
{
- fprintf(stderr, "ERROR: Invalid data received from device.\n");
+ std::cerr << "ERROR: Invalid data received from device.\n" <<
+ e.what() << std::endl;
exit(1);
}
{
"sector", required_argument, NULL, PARAM_BYTESPERSECTOR
},
+ {
+ "reset", no_argument, NULL, PARAM_RESET
+ },
{
NULL, 0, NULL, 0
}
}
break;
}
+ case PARAM_RESET:
+ packet.reset();
+ break;
+
case '?':
usage();
}
if (doWrite)
{
- printf("Saving configuration...");
- if (writeConfig(handle, &packet) <= 0)
+ printf("\nSaving configuration...");
+ try
+ {
+ packet.toNet();
+ scsi2sdHID->saveConfig(
+ reinterpret_cast<uint8_t*>(&packet),
+ sizeof(packet));
+ }
+ catch (std::exception& e)
{
printf(" Fail.\n");
- fprintf(stderr, "ERROR: Failed to save config.\n");
+ std::cerr << "ERROR: Failed to save config.\n" << e.what() << std::endl;
exit(1);
}
printf(" Done.\n");
+ sleep(1); // Wait for the data to be saved to eeprom
+
// Clear outstanding stale data
- readConfig(handle, &packet);
+ scsi2sdHID->readConfig(
+ reinterpret_cast<uint8_t*>(&packet),
+ sizeof(packet));
// Proper update
- if (readConfig(handle, &packet) <= 0)
- {
- fprintf(stderr, "ERROR: Invalid data received from device.\n");
- exit(1);
- }
+ scsi2sdHID->readConfig(
+ reinterpret_cast<uint8_t*>(&packet),
+ sizeof(packet));
+ packet.fromNet();
}
printf("\nCurrent Device Settings:\n");
projects / SCSI2SD-V6.git / commitdiff