else\r
{\r
// Wait for our 1ms timer to save some power.\r
+ // There's an interrupt on the SEL signal to ensure we respond\r
+ // quickly to any SCSI commands.\r
__WFI();\r
}\r
}\r
if (scsiDev.compatMode < COMPAT_SCSI2)\r
{\r
// Required for some older SCSI1 devices using a 5380 chip.\r
- CyDelayUs(100);\r
+ CyDelay(1);\r
}\r
\r
int sel = SCSI_ReadFilt(SCSI_Filt_SEL);\r
scsiDev.resetFlag = 1;\r
}\r
\r
+CY_ISR_PROTO(scsiSelectionISR);\r
+CY_ISR(scsiSelectionISR)\r
+{\r
+ // The SEL signal ISR ensures we wake up from a _WFI() (wait-for-interrupt)\r
+ // call in the main loop without waiting for our 1ms timer to\r
+ // expire. This is done for performance reasons only.\r
+}\r
+\r
uint8_t\r
scsiReadDBxPins()\r
{\r
void\r
scsiRead(uint8_t* data, uint32_t count)\r
{\r
- if (count < 8)\r
+ if (count < 12)\r
{\r
scsiReadPIO(data, count);\r
}\r
void\r
scsiWrite(const uint8_t* data, uint32_t count)\r
{\r
- if (count < 8)\r
+ if (count < 12)\r
{\r
scsiWritePIO(data, count);\r
}\r
{\r
SCSI_CTL_PHASE_Write(phase > 0 ? phase : 0);\r
busSettleDelay();\r
+\r
+ if (scsiDev.compatMode < COMPAT_SCSI2)\r
+ {\r
+ CyDelayUs(100);\r
+ }\r
}\r
}\r
\r
scsiPhyInitDMA();\r
\r
SCSI_RST_ISR_StartEx(scsiResetISR);\r
+\r
+ SCSI_SEL_ISR_StartEx(scsiSelectionISR);\r
+\r
}\r
\r
// 1 = DBx error\r
/* USBFS_ep_1 */
#define USBFS_ep_1__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
#define USBFS_ep_1__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
-#define USBFS_ep_1__INTC_MASK 0x40u
-#define USBFS_ep_1__INTC_NUMBER 6u
+#define USBFS_ep_1__INTC_MASK 0x80u
+#define USBFS_ep_1__INTC_NUMBER 7u
#define USBFS_ep_1__INTC_PRIOR_NUM 7u
-#define USBFS_ep_1__INTC_PRIOR_REG CYREG_NVIC_PRI_6
+#define USBFS_ep_1__INTC_PRIOR_REG CYREG_NVIC_PRI_7
#define USBFS_ep_1__INTC_SET_EN_REG CYREG_NVIC_SETENA0
#define USBFS_ep_1__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
/* USBFS_ep_2 */
#define USBFS_ep_2__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
#define USBFS_ep_2__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
-#define USBFS_ep_2__INTC_MASK 0x80u
-#define USBFS_ep_2__INTC_NUMBER 7u
+#define USBFS_ep_2__INTC_MASK 0x100u
+#define USBFS_ep_2__INTC_NUMBER 8u
#define USBFS_ep_2__INTC_PRIOR_NUM 7u
-#define USBFS_ep_2__INTC_PRIOR_REG CYREG_NVIC_PRI_7
+#define USBFS_ep_2__INTC_PRIOR_REG CYREG_NVIC_PRI_8
#define USBFS_ep_2__INTC_SET_EN_REG CYREG_NVIC_SETENA0
#define USBFS_ep_2__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
/* USBFS_ep_3 */
#define USBFS_ep_3__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
#define USBFS_ep_3__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
-#define USBFS_ep_3__INTC_MASK 0x100u
-#define USBFS_ep_3__INTC_NUMBER 8u
+#define USBFS_ep_3__INTC_MASK 0x200u
+#define USBFS_ep_3__INTC_NUMBER 9u
#define USBFS_ep_3__INTC_PRIOR_NUM 7u
-#define USBFS_ep_3__INTC_PRIOR_REG CYREG_NVIC_PRI_8
+#define USBFS_ep_3__INTC_PRIOR_REG CYREG_NVIC_PRI_9
#define USBFS_ep_3__INTC_SET_EN_REG CYREG_NVIC_SETENA0
#define USBFS_ep_3__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
/* USBFS_ep_4 */
#define USBFS_ep_4__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
#define USBFS_ep_4__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
-#define USBFS_ep_4__INTC_MASK 0x200u
-#define USBFS_ep_4__INTC_NUMBER 9u
+#define USBFS_ep_4__INTC_MASK 0x400u
+#define USBFS_ep_4__INTC_NUMBER 10u
#define USBFS_ep_4__INTC_PRIOR_NUM 7u
-#define USBFS_ep_4__INTC_PRIOR_REG CYREG_NVIC_PRI_9
+#define USBFS_ep_4__INTC_PRIOR_REG CYREG_NVIC_PRI_10
#define USBFS_ep_4__INTC_SET_EN_REG CYREG_NVIC_SETENA0
#define USBFS_ep_4__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
#define EXTLED__SLW CYREG_PRT0_SLW
/* SDCard_BSPIM */
-#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB10_11_ACTL
-#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB10_11_CTL
-#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB10_11_CTL
-#define SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB10_11_CTL
-#define SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B1_UDB10_11_CTL
-#define SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B1_UDB10_11_MSK
-#define SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B1_UDB10_11_MSK
-#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B1_UDB10_11_MSK
-#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB10_11_MSK
-#define SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B1_UDB10_ACTL
-#define SDCard_BSPIM_BitCounter__CONTROL_REG CYREG_B1_UDB10_CTL
-#define SDCard_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B1_UDB10_ST_CTL
-#define SDCard_BSPIM_BitCounter__COUNT_REG CYREG_B1_UDB10_CTL
-#define SDCard_BSPIM_BitCounter__COUNT_ST_REG CYREG_B1_UDB10_ST_CTL
-#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB10_MSK_ACTL
-#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B1_UDB10_MSK_ACTL
-#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B1_UDB10_MSK
-#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB10_11_ACTL
-#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B1_UDB10_11_ST
-#define SDCard_BSPIM_BitCounter_ST__MASK_REG CYREG_B1_UDB10_MSK
-#define SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B1_UDB10_MSK_ACTL
-#define SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B1_UDB10_MSK_ACTL
-#define SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B1_UDB10_ACTL
-#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B1_UDB10_ST_CTL
-#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B1_UDB10_ST_CTL
-#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B1_UDB10_ST
+#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB09_10_ACTL
+#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB09_10_CTL
+#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB09_10_CTL
+#define SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB09_10_CTL
+#define SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B1_UDB09_10_CTL
+#define SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B1_UDB09_10_MSK
+#define SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B1_UDB09_10_MSK
+#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B1_UDB09_10_MSK
+#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB09_10_MSK
+#define SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B1_UDB09_ACTL
+#define SDCard_BSPIM_BitCounter__CONTROL_REG CYREG_B1_UDB09_CTL
+#define SDCard_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B1_UDB09_ST_CTL
+#define SDCard_BSPIM_BitCounter__COUNT_REG CYREG_B1_UDB09_CTL
+#define SDCard_BSPIM_BitCounter__COUNT_ST_REG CYREG_B1_UDB09_ST_CTL
+#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB09_MSK_ACTL
+#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B1_UDB09_MSK_ACTL
+#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B1_UDB09_MSK
+#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB09_10_ACTL
+#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B1_UDB09_10_ST
+#define SDCard_BSPIM_BitCounter_ST__MASK_REG CYREG_B1_UDB09_MSK
+#define SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B1_UDB09_MSK_ACTL
+#define SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B1_UDB09_MSK_ACTL
+#define SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B1_UDB09_ACTL
+#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B1_UDB09_ST_CTL
+#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B1_UDB09_ST_CTL
+#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B1_UDB09_ST
+#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB09_10_ACTL
+#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B0_UDB09_10_ST
#define SDCard_BSPIM_RxStsReg__4__MASK 0x10u
#define SDCard_BSPIM_RxStsReg__4__POS 4
#define SDCard_BSPIM_RxStsReg__5__MASK 0x20u
#define SDCard_BSPIM_RxStsReg__6__MASK 0x40u
#define SDCard_BSPIM_RxStsReg__6__POS 6
#define SDCard_BSPIM_RxStsReg__MASK 0x70u
-#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B1_UDB11_MSK
-#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB11_ACTL
-#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B1_UDB11_ST
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B1_UDB08_09_A0
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B1_UDB08_09_A1
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG CYREG_B1_UDB08_09_D0
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG CYREG_B1_UDB08_09_D1
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG CYREG_B1_UDB08_09_ACTL
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG CYREG_B1_UDB08_09_F0
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG CYREG_B1_UDB08_09_F1
-#define SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG CYREG_B1_UDB08_A0_A1
-#define SDCard_BSPIM_sR8_Dp_u0__A0_REG CYREG_B1_UDB08_A0
-#define SDCard_BSPIM_sR8_Dp_u0__A1_REG CYREG_B1_UDB08_A1
-#define SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG CYREG_B1_UDB08_D0_D1
-#define SDCard_BSPIM_sR8_Dp_u0__D0_REG CYREG_B1_UDB08_D0
-#define SDCard_BSPIM_sR8_Dp_u0__D1_REG CYREG_B1_UDB08_D1
-#define SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG CYREG_B1_UDB08_ACTL
-#define SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG CYREG_B1_UDB08_F0_F1
-#define SDCard_BSPIM_sR8_Dp_u0__F0_REG CYREG_B1_UDB08_F0
-#define SDCard_BSPIM_sR8_Dp_u0__F1_REG CYREG_B1_UDB08_F1
+#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B0_UDB09_MSK
+#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB09_ACTL
+#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B0_UDB09_ST
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B1_UDB09_10_A0
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B1_UDB09_10_A1
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG CYREG_B1_UDB09_10_D0
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG CYREG_B1_UDB09_10_D1
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG CYREG_B1_UDB09_10_ACTL
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG CYREG_B1_UDB09_10_F0
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG CYREG_B1_UDB09_10_F1
+#define SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG CYREG_B1_UDB09_A0_A1
+#define SDCard_BSPIM_sR8_Dp_u0__A0_REG CYREG_B1_UDB09_A0
+#define SDCard_BSPIM_sR8_Dp_u0__A1_REG CYREG_B1_UDB09_A1
+#define SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG CYREG_B1_UDB09_D0_D1
+#define SDCard_BSPIM_sR8_Dp_u0__D0_REG CYREG_B1_UDB09_D0
+#define SDCard_BSPIM_sR8_Dp_u0__D1_REG CYREG_B1_UDB09_D1
+#define SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG CYREG_B1_UDB09_ACTL
+#define SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG CYREG_B1_UDB09_F0_F1
+#define SDCard_BSPIM_sR8_Dp_u0__F0_REG CYREG_B1_UDB09_F0
+#define SDCard_BSPIM_sR8_Dp_u0__F1_REG CYREG_B1_UDB09_F1
+#define SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG CYREG_B1_UDB09_MSK_ACTL
+#define SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG CYREG_B1_UDB09_MSK_ACTL
#define SDCard_BSPIM_TxStsReg__0__MASK 0x01u
#define SDCard_BSPIM_TxStsReg__0__POS 0
#define SDCard_BSPIM_TxStsReg__1__MASK 0x02u
#define SDCard_BSPIM_TxStsReg__1__POS 1
-#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB08_09_ACTL
-#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B1_UDB08_09_ST
+#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB10_11_ACTL
+#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B1_UDB10_11_ST
#define SDCard_BSPIM_TxStsReg__2__MASK 0x04u
#define SDCard_BSPIM_TxStsReg__2__POS 2
#define SDCard_BSPIM_TxStsReg__3__MASK 0x08u
#define SDCard_BSPIM_TxStsReg__4__MASK 0x10u
#define SDCard_BSPIM_TxStsReg__4__POS 4
#define SDCard_BSPIM_TxStsReg__MASK 0x1Fu
-#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B1_UDB08_MSK
-#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB08_ACTL
-#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B1_UDB08_ST
+#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B1_UDB10_MSK
+#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB10_ACTL
+#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B1_UDB10_ST
/* SD_SCK */
#define SD_SCK__0__MASK 0x04u
#define SCSI_Out_Bits_Sync_ctrl_reg__0__POS 0
#define SCSI_Out_Bits_Sync_ctrl_reg__1__MASK 0x02u
#define SCSI_Out_Bits_Sync_ctrl_reg__1__POS 1
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB08_09_ACTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB08_09_CTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB08_09_CTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB08_09_CTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB08_09_CTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB08_09_MSK
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB08_09_MSK
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB08_09_MSK
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB08_09_MSK
#define SCSI_Out_Bits_Sync_ctrl_reg__2__MASK 0x04u
#define SCSI_Out_Bits_Sync_ctrl_reg__2__POS 2
#define SCSI_Out_Bits_Sync_ctrl_reg__3__MASK 0x08u
#define SCSI_Out_Bits_Sync_ctrl_reg__6__POS 6
#define SCSI_Out_Bits_Sync_ctrl_reg__7__MASK 0x80u
#define SCSI_Out_Bits_Sync_ctrl_reg__7__POS 7
-#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB15_ACTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB15_CTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB15_ST_CTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB15_CTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB15_ST_CTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB08_ACTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB08_CTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB08_ST_CTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB08_CTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB08_ST_CTL
#define SCSI_Out_Bits_Sync_ctrl_reg__MASK 0xFFu
-#define SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB15_MSK_ACTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB15_MSK_ACTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB15_MSK
+#define SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB08_MSK
/* SCSI_Out_Ctl */
#define SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK 0x01u
#define SCSI_Out_Ctl_Sync_ctrl_reg__0__POS 0
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB14_15_ACTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB14_15_CTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB14_15_CTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB14_15_CTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB14_15_CTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB14_15_MSK
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB14_15_MSK
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB14_15_MSK
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB14_15_MSK
-#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB14_ACTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB14_CTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB14_ST_CTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB14_CTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB14_ST_CTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB00_01_ACTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB00_01_CTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB00_01_CTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB00_01_CTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB00_01_CTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB00_01_MSK
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB00_01_MSK
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB00_01_MSK
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB00_01_MSK
+#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB00_ACTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB00_CTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB00_ST_CTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB00_CTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB00_ST_CTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK 0x01u
-#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB14_MSK_ACTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB14_MSK_ACTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB14_MSK
+#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB00_MSK_ACTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB00_MSK_ACTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB00_MSK
/* SCSI_Out_DBx */
#define SCSI_Out_DBx__0__AG CYREG_PRT5_AG
/* SD_RX_DMA_COMPLETE */
#define SD_RX_DMA_COMPLETE__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
#define SD_RX_DMA_COMPLETE__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
-#define SD_RX_DMA_COMPLETE__INTC_MASK 0x10u
-#define SD_RX_DMA_COMPLETE__INTC_NUMBER 4u
+#define SD_RX_DMA_COMPLETE__INTC_MASK 0x20u
+#define SD_RX_DMA_COMPLETE__INTC_NUMBER 5u
#define SD_RX_DMA_COMPLETE__INTC_PRIOR_NUM 7u
-#define SD_RX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_4
+#define SD_RX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_5
#define SD_RX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0
#define SD_RX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
/* SD_TX_DMA_COMPLETE */
#define SD_TX_DMA_COMPLETE__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
#define SD_TX_DMA_COMPLETE__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
-#define SD_TX_DMA_COMPLETE__INTC_MASK 0x20u
-#define SD_TX_DMA_COMPLETE__INTC_NUMBER 5u
+#define SD_TX_DMA_COMPLETE__INTC_MASK 0x40u
+#define SD_TX_DMA_COMPLETE__INTC_NUMBER 6u
#define SD_TX_DMA_COMPLETE__INTC_PRIOR_NUM 7u
-#define SD_TX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_5
+#define SD_TX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_6
#define SD_TX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0
#define SD_TX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
#define scsiTarget_StatusReg__0__POS 0
#define scsiTarget_StatusReg__1__MASK 0x02u
#define scsiTarget_StatusReg__1__POS 1
-#define scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB00_01_ACTL
-#define scsiTarget_StatusReg__16BIT_STATUS_REG CYREG_B0_UDB00_01_ST
#define scsiTarget_StatusReg__2__MASK 0x04u
#define scsiTarget_StatusReg__2__POS 2
#define scsiTarget_StatusReg__3__MASK 0x08u
#define scsiTarget_StatusReg__4__MASK 0x10u
#define scsiTarget_StatusReg__4__POS 4
#define scsiTarget_StatusReg__MASK 0x1Fu
-#define scsiTarget_StatusReg__MASK_REG CYREG_B0_UDB00_MSK
-#define scsiTarget_StatusReg__STATUS_AUX_CTL_REG CYREG_B0_UDB00_ACTL
-#define scsiTarget_StatusReg__STATUS_REG CYREG_B0_UDB00_ST
+#define scsiTarget_StatusReg__MASK_REG CYREG_B0_UDB15_MSK
+#define scsiTarget_StatusReg__STATUS_AUX_CTL_REG CYREG_B0_UDB15_ACTL
+#define scsiTarget_StatusReg__STATUS_REG CYREG_B0_UDB15_ST
/* Debug_Timer_Interrupt */
#define Debug_Timer_Interrupt__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
/* SCSI_TX_DMA_COMPLETE */
#define SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
#define SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
-#define SCSI_TX_DMA_COMPLETE__INTC_MASK 0x08u
-#define SCSI_TX_DMA_COMPLETE__INTC_NUMBER 3u
+#define SCSI_TX_DMA_COMPLETE__INTC_MASK 0x10u
+#define SCSI_TX_DMA_COMPLETE__INTC_NUMBER 4u
#define SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM 7u
-#define SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_3
+#define SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_4
#define SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0
#define SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
#define SCSI_RST_ISR__INTC_SET_EN_REG CYREG_NVIC_SETENA0
#define SCSI_RST_ISR__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
+/* SCSI_SEL_ISR */
+#define SCSI_SEL_ISR__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
+#define SCSI_SEL_ISR__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
+#define SCSI_SEL_ISR__INTC_MASK 0x08u
+#define SCSI_SEL_ISR__INTC_NUMBER 3u
+#define SCSI_SEL_ISR__INTC_PRIOR_NUM 7u
+#define SCSI_SEL_ISR__INTC_PRIOR_REG CYREG_NVIC_PRI_3
+#define SCSI_SEL_ISR__INTC_SET_EN_REG CYREG_NVIC_SETENA0
+#define SCSI_SEL_ISR__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
+
/* SCSI_Filtered */
#define SCSI_Filtered_sts_sts_reg__0__MASK 0x01u
#define SCSI_Filtered_sts_sts_reg__0__POS 0
#define SCSI_Filtered_sts_sts_reg__1__MASK 0x02u
#define SCSI_Filtered_sts_sts_reg__1__POS 1
-#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB04_05_ACTL
-#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB04_05_ST
+#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB01_02_ACTL
+#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB01_02_ST
#define SCSI_Filtered_sts_sts_reg__2__MASK 0x04u
#define SCSI_Filtered_sts_sts_reg__2__POS 2
#define SCSI_Filtered_sts_sts_reg__3__MASK 0x08u
#define SCSI_Filtered_sts_sts_reg__4__MASK 0x10u
#define SCSI_Filtered_sts_sts_reg__4__POS 4
#define SCSI_Filtered_sts_sts_reg__MASK 0x1Fu
-#define SCSI_Filtered_sts_sts_reg__MASK_REG CYREG_B0_UDB04_MSK
-#define SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB04_ACTL
-#define SCSI_Filtered_sts_sts_reg__STATUS_REG CYREG_B0_UDB04_ST
+#define SCSI_Filtered_sts_sts_reg__MASK_REG CYREG_B0_UDB01_MSK
+#define SCSI_Filtered_sts_sts_reg__MASK_ST_AUX_CTL_REG CYREG_B0_UDB01_MSK_ACTL
+#define SCSI_Filtered_sts_sts_reg__PER_ST_AUX_CTL_REG CYREG_B0_UDB01_MSK_ACTL
+#define SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB01_ACTL
+#define SCSI_Filtered_sts_sts_reg__STATUS_CNT_REG CYREG_B0_UDB01_ST_CTL
+#define SCSI_Filtered_sts_sts_reg__STATUS_CONTROL_REG CYREG_B0_UDB01_ST_CTL
+#define SCSI_Filtered_sts_sts_reg__STATUS_REG CYREG_B0_UDB01_ST
/* SCSI_CTL_PHASE */
#define SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK 0x01u
#define SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS 0
#define SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK 0x02u
#define SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS 1
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB12_13_ACTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB12_13_CTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB12_13_CTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB12_13_CTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB12_13_CTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB12_13_MSK
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB12_13_MSK
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB12_13_MSK
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB12_13_MSK
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB01_02_ACTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB01_02_CTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB01_02_CTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB01_02_CTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB01_02_CTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB01_02_MSK
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB01_02_MSK
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB01_02_MSK
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB01_02_MSK
#define SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK 0x04u
#define SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS 2
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB12_ACTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB12_CTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB12_ST_CTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB12_CTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB12_ST_CTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB01_ACTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB01_CTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB01_ST_CTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB01_CTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB01_ST_CTL
#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK 0x07u
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB12_MSK
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB01_MSK_ACTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB01_MSK_ACTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB01_MSK
/* SCSI_Parity_Error */
#define SCSI_Parity_Error_sts_sts_reg__0__MASK 0x01u
#define SCSI_Parity_Error_sts_sts_reg__0__POS 0
-#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB03_04_ACTL
-#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB03_04_ST
+#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB04_05_ACTL
+#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB04_05_ST
#define SCSI_Parity_Error_sts_sts_reg__MASK 0x01u
-#define SCSI_Parity_Error_sts_sts_reg__MASK_REG CYREG_B0_UDB03_MSK
-#define SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB03_ACTL
-#define SCSI_Parity_Error_sts_sts_reg__STATUS_REG CYREG_B0_UDB03_ST
+#define SCSI_Parity_Error_sts_sts_reg__MASK_REG CYREG_B0_UDB04_MSK
+#define SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB04_ACTL
+#define SCSI_Parity_Error_sts_sts_reg__STATUS_REG CYREG_B0_UDB04_ST
/* Miscellaneous */
#define BCLK__BUS_CLK__HZ 50000000U
#define CYDEV_ECC_ENABLE 0
#define CYDEV_HEAP_SIZE 0x0400
#define CYDEV_INSTRUCT_CACHE_ENABLED 1
-#define CYDEV_INTR_RISING 0x0000003Eu
+#define CYDEV_INTR_RISING 0x0000007Eu
#define CYDEV_PROJ_TYPE 2
#define CYDEV_PROJ_TYPE_BOOTLOADER 1
#define CYDEV_PROJ_TYPE_LOADABLE 2
static const uint32 CYCODE cy_cfg_addr_table[] = {
0x40004501u, /* Base address: 0x40004500 Count: 1 */
0x40004F02u, /* Base address: 0x40004F00 Count: 2 */
- 0x4000520Fu, /* Base address: 0x40005200 Count: 15 */
+ 0x40005210u, /* Base address: 0x40005200 Count: 16 */
0x40006401u, /* Base address: 0x40006400 Count: 1 */
0x40006501u, /* Base address: 0x40006500 Count: 1 */
- 0x40010050u, /* Base address: 0x40010000 Count: 80 */
- 0x4001013Eu, /* Base address: 0x40010100 Count: 62 */
- 0x4001024Eu, /* Base address: 0x40010200 Count: 78 */
- 0x40010358u, /* Base address: 0x40010300 Count: 88 */
- 0x40010450u, /* Base address: 0x40010400 Count: 80 */
- 0x4001054Eu, /* Base address: 0x40010500 Count: 78 */
- 0x4001070Fu, /* Base address: 0x40010700 Count: 15 */
- 0x4001084Bu, /* Base address: 0x40010800 Count: 75 */
- 0x40010942u, /* Base address: 0x40010900 Count: 66 */
- 0x40010A39u, /* Base address: 0x40010A00 Count: 57 */
- 0x40010B50u, /* Base address: 0x40010B00 Count: 80 */
- 0x40010C52u, /* Base address: 0x40010C00 Count: 82 */
- 0x40010D54u, /* Base address: 0x40010D00 Count: 84 */
- 0x40010E46u, /* Base address: 0x40010E00 Count: 70 */
- 0x40010F3Du, /* Base address: 0x40010F00 Count: 61 */
+ 0x40010041u, /* Base address: 0x40010000 Count: 65 */
+ 0x40010141u, /* Base address: 0x40010100 Count: 65 */
+ 0x40010259u, /* Base address: 0x40010200 Count: 89 */
+ 0x40010351u, /* Base address: 0x40010300 Count: 81 */
+ 0x4001044Eu, /* Base address: 0x40010400 Count: 78 */
+ 0x4001054Bu, /* Base address: 0x40010500 Count: 75 */
+ 0x40010716u, /* Base address: 0x40010700 Count: 22 */
+ 0x40010849u, /* Base address: 0x40010800 Count: 73 */
+ 0x40010950u, /* Base address: 0x40010900 Count: 80 */
+ 0x40010A3Cu, /* Base address: 0x40010A00 Count: 60 */
+ 0x40010B5Bu, /* Base address: 0x40010B00 Count: 91 */
+ 0x40010C4Bu, /* Base address: 0x40010C00 Count: 75 */
+ 0x40010D55u, /* Base address: 0x40010D00 Count: 85 */
+ 0x40010E53u, /* Base address: 0x40010E00 Count: 83 */
+ 0x40010F3Fu, /* Base address: 0x40010F00 Count: 63 */
0x40011505u, /* Base address: 0x40011500 Count: 5 */
- 0x40011703u, /* Base address: 0x40011700 Count: 3 */
- 0x40011857u, /* Base address: 0x40011800 Count: 87 */
- 0x40011941u, /* Base address: 0x40011900 Count: 65 */
- 0x40011A4Bu, /* Base address: 0x40011A00 Count: 75 */
- 0x40011B48u, /* Base address: 0x40011B00 Count: 72 */
- 0x40014014u, /* Base address: 0x40014000 Count: 20 */
- 0x4001411Bu, /* Base address: 0x40014100 Count: 27 */
- 0x40014217u, /* Base address: 0x40014200 Count: 23 */
- 0x4001430Au, /* Base address: 0x40014300 Count: 10 */
- 0x40014414u, /* Base address: 0x40014400 Count: 20 */
- 0x40014519u, /* Base address: 0x40014500 Count: 25 */
- 0x4001460Fu, /* Base address: 0x40014600 Count: 15 */
- 0x4001470Eu, /* Base address: 0x40014700 Count: 14 */
- 0x40014809u, /* Base address: 0x40014800 Count: 9 */
- 0x4001490Eu, /* Base address: 0x40014900 Count: 14 */
+ 0x40011711u, /* Base address: 0x40011700 Count: 17 */
+ 0x4001181Cu, /* Base address: 0x40011800 Count: 28 */
+ 0x40011950u, /* Base address: 0x40011900 Count: 80 */
+ 0x40011A50u, /* Base address: 0x40011A00 Count: 80 */
+ 0x40011B4Bu, /* Base address: 0x40011B00 Count: 75 */
+ 0x40014018u, /* Base address: 0x40014000 Count: 24 */
+ 0x40014117u, /* Base address: 0x40014100 Count: 23 */
+ 0x40014218u, /* Base address: 0x40014200 Count: 24 */
+ 0x4001430Bu, /* Base address: 0x40014300 Count: 11 */
+ 0x40014410u, /* Base address: 0x40014400 Count: 16 */
+ 0x4001451Au, /* Base address: 0x40014500 Count: 26 */
+ 0x4001460Eu, /* Base address: 0x40014600 Count: 14 */
+ 0x40014715u, /* Base address: 0x40014700 Count: 21 */
+ 0x40014805u, /* Base address: 0x40014800 Count: 5 */
+ 0x4001490Cu, /* Base address: 0x40014900 Count: 12 */
0x40014C07u, /* Base address: 0x40014C00 Count: 7 */
- 0x40014D0Au, /* Base address: 0x40014D00 Count: 10 */
+ 0x40014D0Cu, /* Base address: 0x40014D00 Count: 12 */
0x40015004u, /* Base address: 0x40015000 Count: 4 */
0x40015104u, /* Base address: 0x40015100 Count: 4 */
};
{0x7Eu, 0x02u},
{0x01u, 0x20u},
{0x0Au, 0x4Bu},
- {0x00u, 0x01u},
+ {0x00u, 0x04u},
{0x01u, 0x48u},
{0x04u, 0x31u},
- {0x10u, 0xC8u},
- {0x11u, 0x48u},
- {0x18u, 0x04u},
- {0x19u, 0x08u},
+ {0x10u, 0x88u},
+ {0x11u, 0x84u},
+ {0x18u, 0x08u},
+ {0x19u, 0x04u},
{0x1Cu, 0x30u},
{0x20u, 0x10u},
+ {0x21u, 0x10u},
{0x24u, 0x44u},
- {0x28u, 0x03u},
- {0x29u, 0x02u},
- {0x31u, 0x20u},
+ {0x29u, 0x01u},
+ {0x30u, 0x20u},
+ {0x31u, 0x30u},
{0x78u, 0x20u},
{0x7Cu, 0x40u},
{0x2Bu, 0x02u},
- {0x8Au, 0x0Fu},
- {0x01u, 0x50u},
- {0x03u, 0xA0u},
- {0x05u, 0x06u},
- {0x06u, 0x02u},
- {0x07u, 0x09u},
- {0x09u, 0x05u},
- {0x0Au, 0x04u},
- {0x0Bu, 0x0Au},
- {0x12u, 0x01u},
- {0x15u, 0x60u},
- {0x17u, 0x90u},
- {0x1Bu, 0xFFu},
- {0x1Cu, 0x04u},
- {0x1Du, 0x30u},
- {0x1Fu, 0xC0u},
- {0x20u, 0x01u},
- {0x21u, 0x03u},
- {0x22u, 0x02u},
- {0x23u, 0x0Cu},
- {0x24u, 0x04u},
- {0x27u, 0xFFu},
- {0x29u, 0xFFu},
- {0x2Au, 0x04u},
- {0x2Cu, 0x04u},
- {0x2Du, 0x0Fu},
- {0x2Fu, 0xF0u},
- {0x30u, 0x03u},
- {0x33u, 0xFFu},
- {0x36u, 0x04u},
- {0x39u, 0x20u},
- {0x3Eu, 0x41u},
+ {0x89u, 0x0Fu},
+ {0x01u, 0x02u},
+ {0x02u, 0x02u},
+ {0x03u, 0x11u},
+ {0x05u, 0x80u},
+ {0x07u, 0x40u},
+ {0x09u, 0x01u},
+ {0x0Bu, 0x02u},
+ {0x0Du, 0x40u},
+ {0x0Fu, 0x80u},
+ {0x11u, 0x13u},
+ {0x12u, 0x04u},
+ {0x13u, 0x2Cu},
+ {0x15u, 0x80u},
+ {0x17u, 0x40u},
+ {0x19u, 0x80u},
+ {0x1Au, 0x01u},
+ {0x1Bu, 0x40u},
+ {0x1Du, 0x80u},
+ {0x1Eu, 0x08u},
+ {0x1Fu, 0x40u},
+ {0x21u, 0x04u},
+ {0x23u, 0x08u},
+ {0x29u, 0x08u},
+ {0x2Bu, 0x24u},
+ {0x30u, 0x01u},
+ {0x31u, 0xC0u},
+ {0x32u, 0x04u},
+ {0x33u, 0x30u},
+ {0x34u, 0x08u},
+ {0x35u, 0x0Fu},
+ {0x36u, 0x02u},
+ {0x3Bu, 0x02u},
{0x3Fu, 0x14u},
+ {0x56u, 0x08u},
{0x58u, 0x04u},
{0x59u, 0x04u},
{0x5Bu, 0x04u},
+ {0x5Cu, 0x99u},
+ {0x5Du, 0x90u},
{0x5Fu, 0x01u},
- {0x81u, 0x0Fu},
- {0x83u, 0xF0u},
- {0x87u, 0xFFu},
- {0x88u, 0x09u},
- {0x89u, 0xFFu},
- {0x8Au, 0x06u},
- {0x8Cu, 0x03u},
- {0x8Du, 0x90u},
- {0x8Eu, 0x0Cu},
- {0x8Fu, 0x60u},
- {0x90u, 0x50u},
- {0x91u, 0x03u},
- {0x92u, 0xA0u},
- {0x93u, 0x0Cu},
- {0x94u, 0x90u},
- {0x96u, 0x60u},
- {0x98u, 0x05u},
- {0x99u, 0x05u},
- {0x9Au, 0x0Au},
- {0x9Bu, 0x0Au},
- {0x9Cu, 0x30u},
- {0x9Du, 0x50u},
- {0x9Eu, 0xC0u},
- {0x9Fu, 0xA0u},
- {0xA0u, 0x0Fu},
- {0xA1u, 0x30u},
- {0xA2u, 0xF0u},
- {0xA3u, 0xC0u},
- {0xA5u, 0xFFu},
- {0xA6u, 0xFFu},
- {0xA9u, 0x09u},
- {0xAAu, 0xFFu},
- {0xABu, 0x06u},
- {0xAEu, 0xFFu},
- {0xB1u, 0xFFu},
- {0xB4u, 0xFFu},
- {0xBEu, 0x10u},
- {0xBFu, 0x01u},
- {0xD6u, 0x08u},
+ {0x83u, 0x04u},
+ {0x86u, 0x70u},
+ {0x8Au, 0x08u},
+ {0x8Cu, 0x99u},
+ {0x8Eu, 0x22u},
+ {0x8Fu, 0x01u},
+ {0x93u, 0x08u},
+ {0x98u, 0xAAu},
+ {0x9Au, 0x55u},
+ {0x9Bu, 0x02u},
+ {0x9Eu, 0x07u},
+ {0xA2u, 0x80u},
+ {0xACu, 0x44u},
+ {0xAEu, 0x88u},
+ {0xB1u, 0x02u},
+ {0xB3u, 0x01u},
+ {0xB4u, 0xF0u},
+ {0xB5u, 0x08u},
+ {0xB6u, 0x0Fu},
+ {0xB7u, 0x04u},
{0xD8u, 0x04u},
{0xD9u, 0x04u},
{0xDBu, 0x04u},
- {0xDDu, 0x90u},
+ {0xDCu, 0x91u},
{0xDFu, 0x01u},
- {0x03u, 0x18u},
- {0x05u, 0x20u},
- {0x06u, 0x06u},
- {0x07u, 0x02u},
- {0x09u, 0x80u},
- {0x0Au, 0x80u},
- {0x0Cu, 0x90u},
- {0x0Du, 0x19u},
+ {0x03u, 0x40u},
+ {0x04u, 0x04u},
+ {0x05u, 0x10u},
+ {0x07u, 0x01u},
+ {0x0Au, 0x89u},
+ {0x0Cu, 0x80u},
{0x0Eu, 0x02u},
- {0x0Fu, 0x08u},
- {0x10u, 0x24u},
- {0x12u, 0x41u},
- {0x15u, 0x04u},
- {0x16u, 0x68u},
- {0x17u, 0x40u},
- {0x18u, 0x80u},
- {0x19u, 0x40u},
- {0x1Fu, 0x20u},
- {0x22u, 0x10u},
- {0x23u, 0x10u},
- {0x26u, 0x02u},
- {0x2Au, 0x6Au},
- {0x2Cu, 0x80u},
- {0x2Du, 0x24u},
- {0x30u, 0x80u},
- {0x31u, 0x08u},
- {0x32u, 0x20u},
- {0x34u, 0x90u},
- {0x37u, 0x02u},
- {0x39u, 0x22u},
- {0x3Au, 0x04u},
- {0x3Cu, 0x10u},
- {0x3Du, 0x81u},
- {0x3Eu, 0x08u},
- {0x58u, 0x04u},
- {0x59u, 0x04u},
- {0x5Au, 0x41u},
- {0x5Bu, 0x20u},
- {0x5Cu, 0x40u},
- {0x61u, 0x40u},
- {0x67u, 0x02u},
- {0x80u, 0x90u},
- {0x82u, 0x20u},
- {0x83u, 0x51u},
- {0x85u, 0x01u},
- {0x86u, 0x40u},
- {0x8Au, 0x01u},
- {0x8Bu, 0x04u},
- {0x8Cu, 0x42u},
- {0x8Eu, 0x70u},
- {0x8Fu, 0x02u},
- {0xC0u, 0xC6u},
- {0xC2u, 0xF9u},
- {0xC4u, 0xFFu},
- {0xCAu, 0xEFu},
- {0xCCu, 0xBEu},
- {0xCEu, 0xF7u},
- {0xD6u, 0x1Fu},
+ {0x0Fu, 0x04u},
+ {0x15u, 0x02u},
+ {0x16u, 0x01u},
+ {0x19u, 0x80u},
+ {0x1Au, 0xA8u},
+ {0x1Cu, 0x04u},
+ {0x1Eu, 0x02u},
+ {0x1Fu, 0x10u},
+ {0x20u, 0x08u},
+ {0x21u, 0x18u},
+ {0x22u, 0x02u},
+ {0x23u, 0x40u},
+ {0x24u, 0x80u},
+ {0x25u, 0x64u},
+ {0x26u, 0x20u},
+ {0x27u, 0x50u},
+ {0x28u, 0x04u},
+ {0x2Bu, 0x40u},
+ {0x2Du, 0x01u},
+ {0x2Eu, 0x02u},
+ {0x30u, 0x02u},
+ {0x32u, 0x54u},
+ {0x34u, 0x02u},
+ {0x36u, 0x20u},
+ {0x39u, 0x08u},
+ {0x3Au, 0x60u},
+ {0x3Bu, 0x41u},
+ {0x3Du, 0x80u},
+ {0x3Fu, 0x02u},
+ {0x58u, 0x80u},
+ {0x5Du, 0x01u},
+ {0x5Eu, 0x40u},
+ {0x5Fu, 0x28u},
+ {0x63u, 0x02u},
+ {0x66u, 0x40u},
+ {0x68u, 0x03u},
+ {0x6Du, 0x04u},
+ {0x6Fu, 0x2Au},
+ {0x81u, 0x28u},
+ {0x82u, 0x01u},
+ {0x87u, 0x0Au},
+ {0x88u, 0x01u},
+ {0x89u, 0x10u},
+ {0x8Au, 0x20u},
+ {0x8Bu, 0x10u},
+ {0x8Cu, 0xC0u},
+ {0x8Eu, 0x02u},
+ {0x8Fu, 0x40u},
+ {0xC0u, 0xE8u},
+ {0xC2u, 0xCBu},
+ {0xC4u, 0x90u},
+ {0xCAu, 0x05u},
+ {0xCCu, 0xAFu},
+ {0xCEu, 0x9Fu},
+ {0xD6u, 0xF8u},
{0xD8u, 0x18u},
- {0xE2u, 0x4Cu},
- {0xE4u, 0x04u},
- {0xE6u, 0x01u},
- {0x01u, 0x03u},
- {0x02u, 0x01u},
- {0x03u, 0x0Cu},
- {0x09u, 0xFFu},
- {0x0Au, 0x02u},
- {0x0Du, 0x60u},
- {0x0Fu, 0x90u},
- {0x11u, 0x30u},
- {0x12u, 0x04u},
- {0x13u, 0xC0u},
- {0x19u, 0x06u},
- {0x1Au, 0x10u},
- {0x1Bu, 0x09u},
- {0x1Du, 0x50u},
- {0x1Fu, 0xA0u},
- {0x20u, 0x02u},
- {0x21u, 0x0Fu},
+ {0xE0u, 0x05u},
+ {0xE4u, 0x01u},
+ {0x00u, 0x08u},
+ {0x01u, 0x04u},
+ {0x02u, 0x04u},
+ {0x03u, 0x02u},
+ {0x05u, 0x04u},
+ {0x06u, 0x01u},
+ {0x07u, 0x02u},
+ {0x09u, 0x08u},
+ {0x0Bu, 0x10u},
+ {0x0Du, 0x04u},
+ {0x0Fu, 0x02u},
+ {0x10u, 0x04u},
+ {0x11u, 0x10u},
+ {0x12u, 0x08u},
+ {0x13u, 0x08u},
+ {0x15u, 0x10u},
+ {0x17u, 0x08u},
+ {0x19u, 0x02u},
+ {0x1Au, 0x02u},
+ {0x1Bu, 0x04u},
+ {0x1Du, 0x10u},
+ {0x1Fu, 0x08u},
+ {0x20u, 0x08u},
{0x22u, 0x04u},
- {0x23u, 0xF0u},
- {0x27u, 0xFFu},
- {0x29u, 0x05u},
- {0x2Au, 0x08u},
- {0x2Bu, 0x0Au},
- {0x2Fu, 0xFFu},
- {0x30u, 0x10u},
- {0x32u, 0x06u},
- {0x33u, 0xFFu},
+ {0x24u, 0x08u},
+ {0x25u, 0x04u},
+ {0x26u, 0x04u},
+ {0x27u, 0x02u},
+ {0x28u, 0x08u},
+ {0x2Au, 0x04u},
+ {0x2Bu, 0x01u},
+ {0x2Du, 0x10u},
+ {0x2Fu, 0x08u},
+ {0x30u, 0x0Cu},
+ {0x33u, 0x06u},
{0x34u, 0x01u},
- {0x36u, 0x08u},
- {0x3Eu, 0x04u},
- {0x3Fu, 0x04u},
+ {0x35u, 0x18u},
+ {0x36u, 0x02u},
+ {0x37u, 0x01u},
+ {0x3Au, 0x02u},
+ {0x3Bu, 0x28u},
{0x56u, 0x08u},
{0x58u, 0x04u},
{0x59u, 0x04u},
{0x5Bu, 0x04u},
- {0x5Cu, 0x09u},
+ {0x5Cu, 0x99u},
{0x5Du, 0x90u},
{0x5Fu, 0x01u},
- {0x80u, 0x50u},
- {0x82u, 0xA0u},
- {0x86u, 0x08u},
- {0x89u, 0x0Fu},
- {0x8Au, 0x07u},
- {0x8Bu, 0xF0u},
- {0x8Cu, 0x0Au},
- {0x8Du, 0x69u},
- {0x8Eu, 0x05u},
- {0x8Fu, 0x96u},
+ {0x80u, 0x90u},
+ {0x82u, 0x60u},
+ {0x84u, 0xFFu},
+ {0x85u, 0xFFu},
+ {0x88u, 0x50u},
+ {0x8Au, 0xA0u},
+ {0x8Bu, 0xFFu},
+ {0x90u, 0xFFu},
{0x91u, 0xFFu},
- {0x92u, 0x40u},
- {0x95u, 0x33u},
- {0x97u, 0xCCu},
- {0x9Au, 0x80u},
- {0x9Bu, 0xFFu},
- {0x9Cu, 0x09u},
- {0x9Eu, 0x02u},
- {0x9Fu, 0xFFu},
- {0xA1u, 0xFFu},
- {0xA2u, 0x10u},
- {0xA4u, 0x04u},
- {0xA6u, 0x08u},
+ {0x94u, 0x03u},
+ {0x95u, 0x0Fu},
+ {0x96u, 0x0Cu},
+ {0x97u, 0xF0u},
+ {0x98u, 0x05u},
+ {0x9Au, 0x0Au},
+ {0x9Du, 0x33u},
+ {0x9Fu, 0xCCu},
+ {0xA0u, 0x09u},
+ {0xA2u, 0x06u},
+ {0xA3u, 0xFFu},
+ {0xA5u, 0x96u},
+ {0xA6u, 0xFFu},
+ {0xA7u, 0x69u},
+ {0xA8u, 0x30u},
{0xA9u, 0x55u},
- {0xAAu, 0x20u},
+ {0xAAu, 0xC0u},
{0xABu, 0xAAu},
+ {0xACu, 0x0Fu},
+ {0xAEu, 0xF0u},
{0xAFu, 0xFFu},
- {0xB0u, 0x30u},
- {0xB2u, 0x0Fu},
- {0xB4u, 0xC0u},
- {0xB5u, 0xFFu},
- {0xBBu, 0x20u},
- {0xBEu, 0x11u},
- {0xD4u, 0x01u},
+ {0xB2u, 0xFFu},
+ {0xB3u, 0xFFu},
+ {0xBBu, 0x08u},
+ {0xBEu, 0x04u},
+ {0xD6u, 0x08u},
{0xD8u, 0x04u},
{0xD9u, 0x04u},
{0xDBu, 0x04u},
- {0xDCu, 0x11u},
- {0xDDu, 0x10u},
+ {0xDCu, 0x10u},
+ {0xDDu, 0x90u},
{0xDFu, 0x01u},
- {0x01u, 0x09u},
- {0x02u, 0x01u},
- {0x03u, 0x08u},
- {0x04u, 0x20u},
- {0x06u, 0x80u},
- {0x09u, 0x82u},
- {0x0Bu, 0x08u},
- {0x0Du, 0x01u},
- {0x0Eu, 0x04u},
- {0x10u, 0x28u},
- {0x11u, 0x02u},
- {0x15u, 0x01u},
- {0x17u, 0x20u},
- {0x18u, 0xA0u},
- {0x1Bu, 0x1Cu},
- {0x1Cu, 0x22u},
- {0x1Du, 0x01u},
- {0x1Eu, 0x04u},
- {0x1Fu, 0x02u},
- {0x21u, 0x10u},
- {0x26u, 0x08u},
- {0x28u, 0x02u},
- {0x29u, 0x50u},
- {0x2Au, 0x01u},
- {0x2Cu, 0x02u},
- {0x2Du, 0x01u},
- {0x2Eu, 0x08u},
- {0x2Fu, 0x08u},
- {0x30u, 0x24u},
- {0x32u, 0x01u},
- {0x33u, 0x41u},
- {0x34u, 0x80u},
- {0x36u, 0x01u},
- {0x37u, 0x10u},
- {0x39u, 0xA0u},
- {0x3Cu, 0x10u},
- {0x3Du, 0x80u},
- {0x3Eu, 0x02u},
- {0x46u, 0x44u},
- {0x47u, 0x11u},
- {0x5Bu, 0x80u},
- {0x5Cu, 0x40u},
- {0x5Du, 0x10u},
- {0x66u, 0xA0u},
- {0x80u, 0x40u},
- {0x84u, 0x01u},
- {0x87u, 0x20u},
- {0x8Du, 0x54u},
- {0x90u, 0x10u},
- {0x91u, 0x03u},
- {0x92u, 0x02u},
- {0x93u, 0x18u},
- {0x98u, 0x80u},
+ {0x00u, 0x08u},
+ {0x02u, 0x40u},
+ {0x03u, 0x04u},
+ {0x05u, 0x01u},
+ {0x07u, 0x10u},
+ {0x09u, 0x20u},
+ {0x0Bu, 0xA0u},
+ {0x0Eu, 0x48u},
+ {0x10u, 0x82u},
+ {0x11u, 0x04u},
+ {0x12u, 0x04u},
+ {0x15u, 0x10u},
+ {0x16u, 0x20u},
+ {0x17u, 0x02u},
+ {0x18u, 0x10u},
+ {0x1Eu, 0x46u},
+ {0x22u, 0x08u},
+ {0x25u, 0x10u},
+ {0x27u, 0x2Au},
+ {0x28u, 0x08u},
+ {0x29u, 0x08u},
+ {0x2Au, 0x82u},
+ {0x2Du, 0x10u},
+ {0x2Eu, 0x04u},
+ {0x2Fu, 0x09u},
+ {0x32u, 0x8Au},
+ {0x35u, 0x40u},
+ {0x36u, 0x05u},
+ {0x37u, 0x20u},
+ {0x38u, 0x20u},
+ {0x3Bu, 0x04u},
+ {0x3Du, 0xA8u},
+ {0x3Fu, 0x02u},
+ {0x5Bu, 0x40u},
+ {0x5Du, 0x80u},
+ {0x62u, 0x80u},
+ {0x64u, 0x03u},
+ {0x80u, 0x10u},
+ {0x81u, 0x18u},
+ {0x82u, 0x01u},
+ {0x83u, 0x50u},
+ {0x88u, 0x01u},
+ {0x8Eu, 0x10u},
+ {0x90u, 0x04u},
+ {0x91u, 0x24u},
+ {0x93u, 0x20u},
+ {0x95u, 0x02u},
+ {0x96u, 0x40u},
+ {0x97u, 0x04u},
+ {0x98u, 0x10u},
{0x9Au, 0x02u},
- {0x9Du, 0x04u},
- {0x9Eu, 0x0Du},
- {0xA0u, 0x02u},
- {0xA1u, 0x41u},
- {0xA2u, 0x03u},
- {0xA3u, 0x20u},
- {0xA4u, 0x20u},
- {0xA5u, 0x80u},
- {0xA7u, 0x04u},
- {0xA9u, 0x01u},
- {0xACu, 0x80u},
- {0xADu, 0x01u},
- {0xAFu, 0x20u},
- {0xB1u, 0x48u},
- {0xB2u, 0x01u},
- {0xB3u, 0x08u},
- {0xB4u, 0x40u},
- {0xB6u, 0x40u},
- {0xC0u, 0x5Fu},
- {0xC2u, 0x5Bu},
- {0xC4u, 0x5Eu},
- {0xCAu, 0xFDu},
- {0xCCu, 0xBFu},
- {0xCEu, 0xBCu},
- {0xD6u, 0x38u},
- {0xD8u, 0x30u},
+ {0x9Bu, 0x10u},
+ {0x9Cu, 0x06u},
+ {0x9Du, 0x10u},
+ {0x9Eu, 0x01u},
+ {0x9Fu, 0x29u},
+ {0xA0u, 0x86u},
+ {0xA1u, 0x45u},
+ {0xA2u, 0x02u},
+ {0xA3u, 0x01u},
+ {0xA9u, 0x81u},
+ {0xABu, 0x01u},
+ {0xADu, 0x04u},
+ {0xAEu, 0x01u},
+ {0xB0u, 0x10u},
+ {0xB2u, 0x02u},
+ {0xB3u, 0x20u},
+ {0xC0u, 0x3Eu},
+ {0xC2u, 0x5Eu},
+ {0xC4u, 0x7Fu},
+ {0xCAu, 0x7Fu},
+ {0xCCu, 0xFBu},
+ {0xCEu, 0xF6u},
+ {0xD6u, 0x18u},
+ {0xD8u, 0x18u},
{0xE0u, 0x01u},
- {0xE2u, 0x02u},
- {0xE4u, 0x08u},
- {0xE6u, 0x02u},
- {0xE8u, 0x40u},
- {0xEAu, 0x08u},
- {0xECu, 0x40u},
- {0xEEu, 0x03u},
- {0x00u, 0x02u},
- {0x02u, 0x04u},
- {0x05u, 0x06u},
- {0x07u, 0x09u},
- {0x09u, 0x05u},
- {0x0Bu, 0x0Au},
- {0x13u, 0x70u},
- {0x18u, 0x04u},
- {0x19u, 0x40u},
- {0x1Au, 0x02u},
- {0x1Bu, 0x1Fu},
- {0x1Cu, 0x04u},
- {0x1Du, 0x10u},
- {0x1Eu, 0x0Au},
- {0x1Fu, 0x2Fu},
- {0x21u, 0x20u},
- {0x23u, 0x4Fu},
- {0x24u, 0x04u},
- {0x25u, 0x0Fu},
- {0x26u, 0x03u},
- {0x29u, 0x03u},
- {0x2Bu, 0x0Cu},
- {0x2Cu, 0x04u},
- {0x2Eu, 0x02u},
- {0x30u, 0x06u},
- {0x31u, 0x7Fu},
- {0x34u, 0x08u},
- {0x36u, 0x01u},
- {0x3Au, 0x02u},
+ {0xE2u, 0x24u},
+ {0xE6u, 0x05u},
+ {0xE8u, 0x04u},
+ {0xEAu, 0x09u},
+ {0xEEu, 0x01u},
+ {0x00u, 0x03u},
+ {0x02u, 0x0Cu},
+ {0x04u, 0x0Fu},
+ {0x05u, 0x03u},
+ {0x07u, 0x0Cu},
+ {0x08u, 0x80u},
+ {0x0Bu, 0xFFu},
+ {0x0Cu, 0x80u},
+ {0x0Du, 0xFFu},
+ {0x10u, 0x10u},
+ {0x11u, 0x0Fu},
+ {0x12u, 0x2Fu},
+ {0x13u, 0xF0u},
+ {0x14u, 0x20u},
+ {0x15u, 0x50u},
+ {0x16u, 0x4Fu},
+ {0x17u, 0xA0u},
+ {0x19u, 0x05u},
+ {0x1Au, 0x70u},
+ {0x1Bu, 0x0Au},
+ {0x1Cu, 0x80u},
+ {0x1Du, 0x06u},
+ {0x1Fu, 0x09u},
+ {0x20u, 0x05u},
+ {0x22u, 0x0Au},
+ {0x24u, 0x80u},
+ {0x25u, 0x30u},
+ {0x27u, 0xC0u},
+ {0x28u, 0x06u},
+ {0x2Au, 0x09u},
+ {0x2Bu, 0xFFu},
+ {0x2Cu, 0x40u},
+ {0x2Du, 0x60u},
+ {0x2Eu, 0x1Fu},
+ {0x2Fu, 0x90u},
+ {0x31u, 0xFFu},
+ {0x32u, 0x80u},
+ {0x34u, 0x7Fu},
+ {0x38u, 0x08u},
+ {0x3Eu, 0x04u},
+ {0x3Fu, 0x01u},
+ {0x54u, 0x01u},
{0x58u, 0x04u},
{0x59u, 0x04u},
{0x5Bu, 0x04u},
- {0x5Cu, 0x19u},
+ {0x5Cu, 0x01u},
+ {0x5Du, 0x10u},
{0x5Fu, 0x01u},
- {0x82u, 0x10u},
- {0x85u, 0x04u},
- {0x87u, 0x02u},
- {0x89u, 0x08u},
- {0x8Cu, 0x04u},
- {0x8Du, 0x04u},
- {0x8Eu, 0x02u},
- {0x8Fu, 0x02u},
- {0x91u, 0x08u},
- {0x94u, 0x02u},
- {0x95u, 0x08u},
- {0x96u, 0x04u},
- {0x98u, 0x04u},
- {0x99u, 0x02u},
- {0x9Au, 0x02u},
- {0x9Bu, 0x04u},
- {0x9Fu, 0x10u},
- {0xA0u, 0x04u},
- {0xA1u, 0x04u},
- {0xA2u, 0x0Au},
- {0xA3u, 0x02u},
- {0xA4u, 0x04u},
- {0xA5u, 0x08u},
- {0xA6u, 0x03u},
- {0xABu, 0x01u},
- {0xADu, 0x04u},
- {0xAFu, 0x02u},
- {0xB0u, 0x08u},
- {0xB1u, 0x08u},
- {0xB2u, 0x06u},
- {0xB3u, 0x06u},
+ {0x82u, 0x08u},
+ {0x85u, 0xFFu},
+ {0x89u, 0x55u},
+ {0x8Bu, 0xAAu},
+ {0x8Eu, 0x01u},
+ {0x8Fu, 0xFFu},
+ {0x91u, 0xFFu},
+ {0x95u, 0x33u},
+ {0x97u, 0xCCu},
+ {0x9Du, 0x0Fu},
+ {0x9Fu, 0xF0u},
+ {0xA3u, 0xFFu},
+ {0xA5u, 0x69u},
+ {0xA6u, 0x04u},
+ {0xA7u, 0x96u},
+ {0xAEu, 0x02u},
+ {0xAFu, 0xFFu},
+ {0xB0u, 0x04u},
+ {0xB1u, 0xFFu},
+ {0xB2u, 0x08u},
{0xB4u, 0x01u},
- {0xB5u, 0x10u},
- {0xB6u, 0x10u},
- {0xB7u, 0x01u},
- {0xB9u, 0x02u},
- {0xBAu, 0x08u},
- {0xBBu, 0x08u},
- {0xBFu, 0x01u},
+ {0xB6u, 0x02u},
+ {0xBBu, 0x02u},
{0xD6u, 0x08u},
{0xD8u, 0x04u},
{0xD9u, 0x04u},
{0xDBu, 0x04u},
- {0xDCu, 0x99u},
+ {0xDCu, 0x19u},
{0xDDu, 0x90u},
{0xDFu, 0x01u},
- {0x01u, 0x02u},
- {0x04u, 0x40u},
- {0x05u, 0x01u},
- {0x0Au, 0x09u},
- {0x0Eu, 0x28u},
- {0x10u, 0x01u},
- {0x12u, 0x20u},
+ {0x00u, 0x10u},
+ {0x01u, 0x84u},
+ {0x02u, 0x10u},
+ {0x03u, 0x40u},
+ {0x05u, 0x41u},
+ {0x09u, 0x0Au},
+ {0x0Au, 0x0Au},
+ {0x10u, 0x10u},
+ {0x11u, 0x02u},
+ {0x12u, 0x09u},
+ {0x14u, 0x02u},
{0x16u, 0x20u},
- {0x17u, 0x02u},
- {0x19u, 0x02u},
- {0x1Au, 0x09u},
- {0x1Cu, 0x40u},
- {0x1Eu, 0x28u},
- {0x1Fu, 0x40u},
- {0x21u, 0x02u},
- {0x23u, 0x80u},
- {0x26u, 0x21u},
- {0x27u, 0x22u},
- {0x2Au, 0x09u},
- {0x2Bu, 0x08u},
- {0x2Du, 0x10u},
- {0x2Fu, 0x62u},
- {0x30u, 0x20u},
- {0x31u, 0x82u},
- {0x35u, 0x80u},
- {0x36u, 0x0Au},
- {0x37u, 0x20u},
+ {0x1Au, 0x28u},
+ {0x1Du, 0x41u},
+ {0x1Eu, 0x08u},
+ {0x1Fu, 0x08u},
+ {0x22u, 0x01u},
+ {0x27u, 0x40u},
+ {0x2Au, 0x54u},
+ {0x2Du, 0x08u},
+ {0x2Eu, 0x82u},
+ {0x30u, 0x82u},
+ {0x31u, 0x20u},
+ {0x33u, 0x04u},
+ {0x36u, 0x02u},
+ {0x37u, 0x48u},
{0x38u, 0x04u},
- {0x39u, 0x20u},
- {0x3Eu, 0x84u},
- {0x3Fu, 0x10u},
- {0x58u, 0x0Au},
- {0x59u, 0x40u},
- {0x5Bu, 0x20u},
+ {0x39u, 0xA0u},
+ {0x3Bu, 0x80u},
+ {0x3Fu, 0xA4u},
+ {0x58u, 0x40u},
+ {0x5Eu, 0x10u},
{0x5Fu, 0x40u},
- {0x62u, 0x40u},
- {0x64u, 0x01u},
- {0x65u, 0x80u},
- {0x79u, 0x10u},
- {0x7Au, 0x04u},
- {0x82u, 0x01u},
- {0x87u, 0x40u},
- {0x89u, 0x08u},
- {0x90u, 0x04u},
- {0x91u, 0x20u},
- {0x92u, 0x04u},
- {0x93u, 0x10u},
- {0x98u, 0x02u},
- {0x99u, 0x01u},
- {0x9Au, 0xE8u},
- {0x9Du, 0x08u},
- {0x9Eu, 0x05u},
- {0x9Fu, 0xC0u},
- {0xA0u, 0x30u},
+ {0x64u, 0x02u},
+ {0x66u, 0x20u},
+ {0x67u, 0x02u},
+ {0x81u, 0x10u},
+ {0x83u, 0x04u},
+ {0x85u, 0x08u},
+ {0x87u, 0x04u},
+ {0x8Eu, 0x04u},
+ {0x90u, 0x14u},
+ {0x91u, 0x24u},
+ {0x92u, 0x10u},
+ {0x95u, 0x02u},
+ {0x97u, 0x86u},
+ {0x98u, 0x10u},
+ {0x9Au, 0x03u},
+ {0x9Cu, 0x0Cu},
+ {0x9Du, 0x51u},
+ {0x9Eu, 0xE4u},
+ {0x9Fu, 0x05u},
+ {0xA0u, 0x82u},
+ {0xA1u, 0x01u},
{0xA2u, 0x0Au},
- {0xA3u, 0x22u},
- {0xA5u, 0x80u},
- {0xA8u, 0x44u},
- {0xACu, 0x24u},
- {0xADu, 0x10u},
- {0xB0u, 0x08u},
- {0xB1u, 0x40u},
- {0xB2u, 0x08u},
- {0xB5u, 0x02u},
- {0xB7u, 0x10u},
- {0xC0u, 0x98u},
- {0xC2u, 0x63u},
- {0xC4u, 0x35u},
- {0xCAu, 0xF7u},
- {0xCCu, 0xFDu},
- {0xCEu, 0x76u},
- {0xD6u, 0x1Fu},
- {0xD8u, 0x18u},
- {0xE2u, 0x48u},
- {0xE4u, 0x01u},
- {0xE6u, 0x20u},
- {0xEAu, 0x2Fu},
- {0xEEu, 0x0Cu},
- {0x8Fu, 0x08u},
- {0x9Eu, 0x04u},
+ {0xA3u, 0x50u},
+ {0xA5u, 0x20u},
+ {0xA6u, 0x04u},
{0xA7u, 0x08u},
- {0xAAu, 0x01u},
- {0xACu, 0x10u},
- {0xADu, 0x40u},
- {0xAEu, 0x10u},
- {0xB4u, 0x08u},
- {0xB5u, 0x82u},
- {0xB7u, 0x40u},
- {0xE2u, 0x04u},
- {0xE6u, 0x04u},
- {0xE8u, 0x08u},
- {0xEAu, 0x84u},
- {0xEEu, 0x40u},
- {0x04u, 0x02u},
- {0x05u, 0xFFu},
- {0x06u, 0x0Du},
- {0x0Au, 0x10u},
- {0x0Bu, 0xFFu},
- {0x0Cu, 0x0Du},
- {0x10u, 0x0Du},
- {0x13u, 0xFFu},
- {0x14u, 0x0Du},
- {0x17u, 0xFFu},
- {0x18u, 0x0Du},
- {0x19u, 0xFFu},
- {0x1Du, 0x0Fu},
- {0x1Fu, 0xF0u},
- {0x20u, 0x0Du},
- {0x21u, 0x33u},
- {0x23u, 0xCCu},
- {0x24u, 0xE2u},
- {0x25u, 0x55u},
- {0x26u, 0x08u},
- {0x27u, 0xAAu},
- {0x28u, 0x82u},
- {0x29u, 0x69u},
- {0x2Au, 0x54u},
- {0x2Bu, 0x96u},
- {0x2Cu, 0x81u},
- {0x2Eu, 0x32u},
+ {0xABu, 0x40u},
+ {0xADu, 0x04u},
+ {0xB5u, 0x80u},
+ {0xC0u, 0x9Fu},
+ {0xC2u, 0x0Fu},
+ {0xC4u, 0xAFu},
+ {0xCAu, 0xDEu},
+ {0xCCu, 0xDFu},
+ {0xCEu, 0x7Eu},
+ {0xD6u, 0x38u},
+ {0xD8u, 0x30u},
+ {0xE2u, 0x03u},
+ {0xE6u, 0x0Du},
+ {0xEAu, 0x09u},
+ {0xECu, 0x40u},
+ {0xEEu, 0x01u},
+ {0x81u, 0x08u},
+ {0x88u, 0x04u},
+ {0x90u, 0x04u},
+ {0x91u, 0x20u},
+ {0x95u, 0x80u},
+ {0x9Cu, 0x0Cu},
+ {0x9Du, 0x88u},
+ {0xA0u, 0x82u},
+ {0xAAu, 0x10u},
+ {0xADu, 0x03u},
+ {0xAEu, 0x80u},
+ {0xAFu, 0x09u},
+ {0xB0u, 0x40u},
+ {0xB2u, 0x44u},
+ {0xB3u, 0x40u},
+ {0xB5u, 0x20u},
+ {0xE2u, 0x01u},
+ {0xE6u, 0x64u},
+ {0xE8u, 0x20u},
+ {0xEAu, 0x4Au},
+ {0xECu, 0x04u},
+ {0xEEu, 0x22u},
+ {0x06u, 0x02u},
+ {0x09u, 0x50u},
+ {0x0Bu, 0xA0u},
+ {0x0Cu, 0x08u},
+ {0x11u, 0x30u},
+ {0x13u, 0xC0u},
+ {0x15u, 0x60u},
+ {0x17u, 0x90u},
+ {0x19u, 0x06u},
+ {0x1Bu, 0x09u},
+ {0x24u, 0x04u},
+ {0x25u, 0x03u},
+ {0x27u, 0x0Cu},
+ {0x28u, 0x01u},
+ {0x29u, 0x0Fu},
+ {0x2Au, 0x02u},
+ {0x2Bu, 0xF0u},
+ {0x2Du, 0x05u},
+ {0x2Eu, 0x01u},
+ {0x2Fu, 0x0Au},
+ {0x30u, 0x03u},
{0x31u, 0xFFu},
- {0x32u, 0x0Fu},
- {0x34u, 0x70u},
- {0x36u, 0x80u},
- {0x3Au, 0x08u},
- {0x3Bu, 0x02u},
- {0x3Eu, 0x40u},
+ {0x34u, 0x08u},
+ {0x36u, 0x04u},
+ {0x3Eu, 0x11u},
+ {0x3Fu, 0x01u},
+ {0x56u, 0x08u},
{0x58u, 0x04u},
{0x59u, 0x04u},
- {0x5Cu, 0x10u},
+ {0x5Bu, 0x04u},
+ {0x5Cu, 0x09u},
+ {0x5Du, 0x90u},
{0x5Fu, 0x01u},
- {0x80u, 0x09u},
- {0x82u, 0x02u},
- {0x83u, 0x12u},
- {0x85u, 0x20u},
- {0x88u, 0x3Eu},
- {0x89u, 0x04u},
- {0x8Bu, 0x03u},
- {0x8Fu, 0x0Cu},
- {0x94u, 0x22u},
- {0x95u, 0x08u},
- {0x96u, 0x01u},
+ {0x83u, 0x01u},
+ {0x84u, 0x10u},
+ {0x86u, 0x0Cu},
+ {0x87u, 0x20u},
+ {0x88u, 0x08u},
+ {0x8Cu, 0x21u},
+ {0x8Du, 0x04u},
+ {0x8Eu, 0x1Eu},
+ {0x8Fu, 0xA3u},
+ {0x94u, 0x24u},
+ {0x95u, 0xC8u},
+ {0x96u, 0x10u},
{0x97u, 0x03u},
- {0x9Bu, 0x01u},
- {0x9Du, 0x01u},
- {0x9Fu, 0x02u},
- {0xA1u, 0x40u},
- {0xA2u, 0x38u},
- {0xA3u, 0x80u},
- {0xA4u, 0x01u},
- {0xA6u, 0x14u},
- {0xABu, 0x40u},
- {0xAFu, 0x80u},
- {0xB0u, 0x38u},
- {0xB1u, 0xC0u},
- {0xB3u, 0x20u},
- {0xB4u, 0x07u},
- {0xB5u, 0x10u},
- {0xB7u, 0x0Fu},
- {0xB8u, 0x20u},
- {0xBEu, 0x01u},
- {0xBFu, 0x05u},
- {0xD6u, 0x08u},
+ {0x98u, 0x11u},
+ {0x9Au, 0x22u},
+ {0x9Bu, 0x0Cu},
+ {0x9Cu, 0x1Cu},
+ {0x9Fu, 0x12u},
+ {0xA0u, 0x1Cu},
+ {0xA4u, 0x14u},
+ {0xA6u, 0x08u},
+ {0xA8u, 0x30u},
+ {0xAAu, 0x0Fu},
+ {0xACu, 0x0Cu},
+ {0xADu, 0x01u},
+ {0xAEu, 0x10u},
+ {0xAFu, 0x62u},
+ {0xB2u, 0x30u},
+ {0xB3u, 0xE0u},
+ {0xB4u, 0x0Fu},
+ {0xB5u, 0x0Fu},
+ {0xB6u, 0x0Fu},
+ {0xB7u, 0x10u},
+ {0xBAu, 0x08u},
+ {0xD4u, 0x40u},
+ {0xD6u, 0x04u},
{0xD8u, 0x04u},
{0xD9u, 0x04u},
{0xDBu, 0x04u},
- {0xDDu, 0x90u},
{0xDFu, 0x01u},
- {0x01u, 0x20u},
- {0x03u, 0x40u},
- {0x04u, 0x80u},
- {0x05u, 0x14u},
- {0x09u, 0x08u},
- {0x0Cu, 0x2Au},
- {0x11u, 0x08u},
- {0x12u, 0x80u},
- {0x15u, 0x29u},
- {0x17u, 0x40u},
- {0x19u, 0x20u},
- {0x1Au, 0x80u},
- {0x1Du, 0x54u},
- {0x21u, 0x60u},
- {0x22u, 0x81u},
- {0x23u, 0x20u},
- {0x25u, 0x01u},
- {0x27u, 0x80u},
- {0x29u, 0x01u},
- {0x2Au, 0x80u},
- {0x2Bu, 0x08u},
- {0x2Cu, 0x84u},
- {0x2Du, 0x04u},
- {0x31u, 0x28u},
- {0x33u, 0x40u},
- {0x36u, 0x08u},
- {0x37u, 0x91u},
- {0x39u, 0xA4u},
- {0x3Au, 0x01u},
- {0x3Bu, 0x04u},
- {0x3Cu, 0x08u},
- {0x3Du, 0x20u},
- {0x5Au, 0x60u},
- {0x5Bu, 0x08u},
- {0x60u, 0x22u},
- {0x63u, 0x04u},
+ {0x00u, 0x48u},
+ {0x02u, 0x04u},
+ {0x05u, 0x40u},
+ {0x06u, 0x20u},
+ {0x09u, 0x40u},
+ {0x0Au, 0x28u},
+ {0x10u, 0x10u},
+ {0x11u, 0x41u},
+ {0x12u, 0x08u},
+ {0x14u, 0x05u},
+ {0x17u, 0x04u},
+ {0x18u, 0x06u},
+ {0x19u, 0x80u},
+ {0x1Au, 0x28u},
+ {0x1Fu, 0x92u},
+ {0x20u, 0x01u},
+ {0x21u, 0x14u},
+ {0x22u, 0x20u},
+ {0x24u, 0x80u},
+ {0x26u, 0x01u},
+ {0x29u, 0x80u},
+ {0x2Cu, 0x05u},
+ {0x2Fu, 0x20u},
+ {0x32u, 0xA8u},
+ {0x35u, 0x02u},
+ {0x37u, 0x18u},
+ {0x38u, 0x41u},
+ {0x39u, 0x08u},
+ {0x3Eu, 0x20u},
+ {0x5Fu, 0x50u},
+ {0x60u, 0x10u},
+ {0x61u, 0x20u},
+ {0x62u, 0x41u},
+ {0x65u, 0x10u},
+ {0x67u, 0x02u},
+ {0x6Cu, 0x2Au},
+ {0x6Du, 0x20u},
+ {0x6Eu, 0x01u},
+ {0x74u, 0x80u},
+ {0x75u, 0x22u},
+ {0x76u, 0x20u},
+ {0x77u, 0x08u},
{0x81u, 0x10u},
- {0x8Du, 0x01u},
- {0x90u, 0x02u},
- {0x92u, 0x49u},
- {0x95u, 0x40u},
- {0x97u, 0x20u},
- {0x98u, 0x04u},
- {0x99u, 0x01u},
- {0x9Au, 0x8Au},
- {0x9Bu, 0x15u},
- {0x9Cu, 0x22u},
- {0x9Fu, 0x20u},
- {0xA0u, 0x84u},
- {0xA1u, 0x10u},
- {0xA2u, 0x08u},
- {0xA7u, 0x10u},
- {0xABu, 0x10u},
- {0xB4u, 0x14u},
- {0xC0u, 0xEAu},
- {0xC2u, 0x74u},
- {0xC4u, 0xFCu},
- {0xCAu, 0xEDu},
- {0xCCu, 0xFEu},
- {0xCEu, 0x6Fu},
- {0xD6u, 0x0Eu},
- {0xD8u, 0x0Eu},
- {0xE2u, 0x14u},
- {0xE8u, 0x08u},
- {0xEAu, 0x90u},
- {0xEEu, 0x40u},
- {0x25u, 0x01u},
- {0x2Du, 0x02u},
- {0x31u, 0x02u},
- {0x33u, 0x01u},
- {0x3Fu, 0x05u},
+ {0x87u, 0x40u},
+ {0x8Au, 0x05u},
+ {0x8Eu, 0x01u},
+ {0x94u, 0xC0u},
+ {0x95u, 0x41u},
+ {0x96u, 0x08u},
+ {0x97u, 0x22u},
+ {0x9Au, 0x90u},
+ {0x9Bu, 0x55u},
+ {0x9Cu, 0x14u},
+ {0x9Du, 0x32u},
+ {0xA2u, 0x14u},
+ {0xA3u, 0x19u},
+ {0xA4u, 0xAEu},
+ {0xA5u, 0x44u},
+ {0xA6u, 0x08u},
+ {0xA7u, 0xE2u},
+ {0xAAu, 0x20u},
+ {0xADu, 0x04u},
+ {0xAEu, 0x42u},
+ {0xB0u, 0x02u},
+ {0xB2u, 0x02u},
+ {0xB3u, 0x04u},
+ {0xB5u, 0x04u},
+ {0xC0u, 0xA7u},
+ {0xC2u, 0x07u},
+ {0xC4u, 0xEFu},
+ {0xCAu, 0x78u},
+ {0xCCu, 0xEEu},
+ {0xCEu, 0x2Bu},
+ {0xD6u, 0x30u},
+ {0xD8u, 0x3Fu},
+ {0xE2u, 0x01u},
+ {0xE6u, 0xE2u},
+ {0xEAu, 0x40u},
+ {0xECu, 0x05u},
+ {0xEEu, 0xE0u},
+ {0x13u, 0x02u},
+ {0x23u, 0x01u},
+ {0x25u, 0x04u},
+ {0x29u, 0x01u},
+ {0x2Bu, 0x02u},
+ {0x33u, 0x04u},
+ {0x35u, 0x03u},
+ {0x3Fu, 0x14u},
{0x59u, 0x04u},
{0x5Fu, 0x01u},
+ {0x80u, 0x04u},
+ {0x81u, 0x02u},
{0x85u, 0x08u},
{0x87u, 0x03u},
- {0x89u, 0x37u},
- {0x8Bu, 0x40u},
- {0x93u, 0x2Cu},
- {0x94u, 0x08u},
- {0x97u, 0x7Fu},
- {0x98u, 0x02u},
- {0x99u, 0x4Fu},
- {0x9Bu, 0x30u},
- {0x9Cu, 0x04u},
- {0xA1u, 0x02u},
- {0xA5u, 0x10u},
- {0xA7u, 0x01u},
- {0xA8u, 0x01u},
- {0xA9u, 0x03u},
+ {0x88u, 0x01u},
+ {0x8Bu, 0x7Fu},
+ {0x91u, 0x4Fu},
+ {0x93u, 0x30u},
+ {0x97u, 0x2Cu},
+ {0x98u, 0x08u},
+ {0x99u, 0x10u},
+ {0x9Bu, 0x01u},
+ {0x9Du, 0x37u},
+ {0x9Fu, 0x40u},
+ {0xA5u, 0x03u},
+ {0xA8u, 0x02u},
{0xADu, 0x80u},
{0xB0u, 0x04u},
- {0xB1u, 0x80u},
- {0xB2u, 0x01u},
- {0xB3u, 0x0Fu},
- {0xB4u, 0x08u},
- {0xB5u, 0x70u},
- {0xB6u, 0x02u},
+ {0xB1u, 0x70u},
+ {0xB2u, 0x02u},
+ {0xB3u, 0x80u},
+ {0xB4u, 0x01u},
+ {0xB6u, 0x08u},
+ {0xB7u, 0x0Fu},
{0xBEu, 0x55u},
- {0xBFu, 0x01u},
- {0xC0u, 0x42u},
- {0xC1u, 0x06u},
- {0xC2u, 0x50u},
- {0xC5u, 0xDEu},
+ {0xBFu, 0x04u},
+ {0xC0u, 0x24u},
+ {0xC1u, 0x05u},
+ {0xC2u, 0x60u},
+ {0xC5u, 0xE2u},
{0xC6u, 0xF0u},
- {0xC7u, 0x2Cu},
+ {0xC7u, 0xDCu},
{0xC8u, 0x3Bu},
{0xC9u, 0xFFu},
{0xCAu, 0xFFu},
{0xE8u, 0x40u},
{0xE9u, 0x40u},
{0xEEu, 0x08u},
- {0x0Cu, 0x84u},
- {0x0Fu, 0x0Au},
- {0x16u, 0x04u},
+ {0x05u, 0x10u},
+ {0x06u, 0x40u},
+ {0x0Au, 0x80u},
+ {0x0Bu, 0x40u},
+ {0x0Fu, 0x08u},
+ {0x11u, 0x08u},
+ {0x13u, 0x04u},
+ {0x14u, 0x08u},
+ {0x1Cu, 0x04u},
{0x1Du, 0x40u},
- {0x1Eu, 0x88u},
+ {0x1Eu, 0x80u},
{0x1Fu, 0x04u},
- {0x23u, 0x50u},
- {0x24u, 0x08u},
- {0x25u, 0x14u},
- {0x26u, 0x01u},
- {0x27u, 0x14u},
- {0x28u, 0x32u},
- {0x2Du, 0xA6u},
- {0x2Fu, 0x08u},
+ {0x20u, 0x10u},
+ {0x22u, 0x20u},
+ {0x25u, 0x08u},
+ {0x26u, 0x02u},
+ {0x27u, 0x41u},
+ {0x28u, 0x04u},
+ {0x29u, 0x04u},
+ {0x2Bu, 0x40u},
+ {0x2Eu, 0x48u},
+ {0x2Fu, 0x01u},
{0x30u, 0x02u},
- {0x31u, 0x01u},
- {0x36u, 0x08u},
- {0x37u, 0x11u},
- {0x3Cu, 0x08u},
- {0x3Du, 0x20u},
- {0x47u, 0x11u},
+ {0x36u, 0x14u},
+ {0x37u, 0x41u},
+ {0x3Du, 0x02u},
+ {0x3Eu, 0x04u},
+ {0x3Fu, 0x20u},
+ {0x45u, 0x28u},
+ {0x46u, 0x20u},
+ {0x47u, 0x01u},
{0x4Cu, 0x14u},
- {0x4Du, 0x03u},
- {0x4Eu, 0x02u},
- {0x55u, 0x01u},
- {0x56u, 0x10u},
- {0x57u, 0x08u},
- {0x5Eu, 0x8Au},
- {0x5Fu, 0x20u},
+ {0x4Du, 0x08u},
+ {0x4Eu, 0x42u},
+ {0x55u, 0x11u},
+ {0x56u, 0x0Cu},
+ {0x5Cu, 0x14u},
+ {0x5Eu, 0x82u},
{0x65u, 0x40u},
- {0x67u, 0x58u},
- {0x6Cu, 0x21u},
- {0x6Du, 0x10u},
+ {0x66u, 0x22u},
+ {0x67u, 0x20u},
+ {0x6Cu, 0x01u},
+ {0x6Du, 0x04u},
{0x6Eu, 0x01u},
- {0x74u, 0x08u},
- {0x76u, 0x4Au},
- {0x89u, 0x10u},
- {0x8Au, 0x10u},
- {0x91u, 0x04u},
- {0x92u, 0x48u},
- {0x94u, 0x08u},
+ {0x6Fu, 0x08u},
+ {0x74u, 0x10u},
+ {0x76u, 0x91u},
+ {0x80u, 0x09u},
+ {0x82u, 0x40u},
+ {0x87u, 0x81u},
+ {0x88u, 0x40u},
+ {0x8Cu, 0x20u},
+ {0x8Fu, 0x02u},
+ {0x90u, 0x08u},
+ {0x92u, 0x04u},
+ {0x94u, 0xE0u},
{0x95u, 0x41u},
- {0x97u, 0x20u},
- {0x98u, 0x04u},
- {0x99u, 0x80u},
- {0x9Au, 0x84u},
- {0x9Bu, 0x01u},
- {0x9Cu, 0x12u},
- {0x9Du, 0x20u},
- {0x9Eu, 0x40u},
- {0x9Fu, 0x10u},
- {0xA0u, 0x06u},
- {0xA2u, 0x0Au},
- {0xA3u, 0x05u},
- {0xA4u, 0x28u},
- {0xA5u, 0x15u},
- {0xA7u, 0x10u},
- {0xA8u, 0x10u},
- {0xAAu, 0x40u},
- {0xABu, 0x20u},
- {0xADu, 0x80u},
- {0xAFu, 0x01u},
- {0xB1u, 0x04u},
- {0xB2u, 0x14u},
- {0xB6u, 0x50u},
- {0xC2u, 0xE0u},
+ {0x96u, 0x49u},
+ {0x97u, 0x44u},
+ {0x98u, 0x08u},
+ {0x99u, 0x04u},
+ {0x9Au, 0x40u},
+ {0x9Bu, 0x14u},
+ {0x9Cu, 0x50u},
+ {0x9Du, 0x2Au},
+ {0x9Eu, 0x05u},
+ {0x9Fu, 0x41u},
+ {0xA1u, 0x20u},
+ {0xA2u, 0x15u},
+ {0xA3u, 0x15u},
+ {0xA4u, 0xBEu},
+ {0xA5u, 0x51u},
+ {0xA6u, 0x08u},
+ {0xA7u, 0x20u},
+ {0xA9u, 0x10u},
+ {0xABu, 0x40u},
+ {0xAFu, 0x60u},
+ {0xC0u, 0x50u},
+ {0xC2u, 0x40u},
{0xC4u, 0x40u},
- {0xCAu, 0xFAu},
- {0xCCu, 0xE0u},
- {0xCEu, 0x60u},
+ {0xCAu, 0x57u},
+ {0xCCu, 0xF1u},
+ {0xCEu, 0xE0u},
{0xD0u, 0xA0u},
{0xD2u, 0x30u},
{0xD6u, 0xF0u},
{0xD8u, 0xF0u},
- {0xE2u, 0xC8u},
- {0xE4u, 0x01u},
- {0xE6u, 0x20u},
- {0xE8u, 0x10u},
- {0xEAu, 0xA0u},
- {0xEEu, 0x3Du},
- {0x03u, 0x22u},
- {0x05u, 0x66u},
- {0x07u, 0x19u},
- {0x08u, 0x60u},
- {0x09u, 0x15u},
- {0x0Au, 0x90u},
- {0x0Bu, 0x2Au},
- {0x10u, 0x0Fu},
- {0x11u, 0x17u},
- {0x12u, 0xF0u},
- {0x13u, 0x48u},
- {0x14u, 0x03u},
- {0x16u, 0x0Cu},
- {0x17u, 0x73u},
- {0x19u, 0x03u},
- {0x1Bu, 0x0Cu},
- {0x1Cu, 0x05u},
- {0x1Eu, 0x0Au},
- {0x24u, 0x50u},
- {0x25u, 0x01u},
- {0x26u, 0xA0u},
- {0x28u, 0x30u},
- {0x2Au, 0xC0u},
- {0x2Cu, 0x06u},
- {0x2Eu, 0x09u},
- {0x30u, 0xFFu},
+ {0xE6u, 0x10u},
+ {0xE8u, 0x04u},
+ {0xEAu, 0x02u},
+ {0xEEu, 0x01u},
+ {0x05u, 0x10u},
+ {0x06u, 0x70u},
+ {0x0Au, 0x20u},
+ {0x0Bu, 0x08u},
+ {0x0Eu, 0x08u},
+ {0x11u, 0x3Au},
+ {0x13u, 0x45u},
+ {0x15u, 0x10u},
+ {0x16u, 0x07u},
+ {0x17u, 0x60u},
+ {0x18u, 0x94u},
+ {0x1Au, 0x48u},
+ {0x1Bu, 0x07u},
+ {0x1Du, 0x29u},
+ {0x1Fu, 0x52u},
+ {0x20u, 0xEAu},
+ {0x22u, 0x15u},
+ {0x25u, 0x24u},
+ {0x26u, 0x80u},
+ {0x27u, 0x58u},
+ {0x2Au, 0x80u},
+ {0x2Bu, 0x10u},
+ {0x2Cu, 0x99u},
+ {0x2Du, 0x80u},
+ {0x2Eu, 0x22u},
+ {0x30u, 0x80u},
+ {0x31u, 0x80u},
+ {0x32u, 0x0Fu},
{0x33u, 0x0Fu},
+ {0x34u, 0x70u},
{0x35u, 0x70u},
- {0x37u, 0x70u},
- {0x3Bu, 0x08u},
- {0x3Eu, 0x01u},
+ {0x38u, 0x80u},
+ {0x3Bu, 0x20u},
+ {0x3Eu, 0x41u},
+ {0x3Fu, 0x01u},
{0x56u, 0x08u},
{0x58u, 0x04u},
{0x59u, 0x04u},
{0x5Bu, 0x04u},
- {0x5Cu, 0x10u},
+ {0x5Cu, 0x11u},
{0x5Du, 0x90u},
{0x5Fu, 0x01u},
- {0x80u, 0x33u},
- {0x82u, 0xCCu},
- {0x83u, 0x40u},
- {0x84u, 0xFFu},
- {0x87u, 0x04u},
- {0x88u, 0x0Fu},
- {0x89u, 0x10u},
- {0x8Au, 0xF0u},
- {0x8Bu, 0x08u},
- {0x8Fu, 0x02u},
- {0x90u, 0x96u},
- {0x91u, 0x22u},
- {0x92u, 0x69u},
- {0x93u, 0x44u},
- {0x94u, 0xFFu},
- {0x95u, 0x08u},
- {0x97u, 0x10u},
- {0x99u, 0x10u},
- {0x9Au, 0xFFu},
- {0x9Bu, 0x08u},
- {0xA1u, 0x10u},
+ {0x84u, 0x0Du},
+ {0x8Cu, 0x32u},
+ {0x8Eu, 0x44u},
+ {0x90u, 0x40u},
+ {0x92u, 0x30u},
+ {0x94u, 0x02u},
+ {0x96u, 0x0Du},
+ {0x98u, 0x11u},
+ {0x9Au, 0x62u},
+ {0x9Bu, 0x01u},
+ {0x9Cu, 0x0Du},
+ {0x9Du, 0x05u},
+ {0x9Fu, 0x0Au},
+ {0xA0u, 0x0Du},
{0xA3u, 0x08u},
- {0xA4u, 0x55u},
- {0xA6u, 0xAAu},
- {0xA7u, 0x20u},
- {0xAAu, 0xFFu},
- {0xADu, 0x10u},
- {0xAEu, 0xFFu},
- {0xAFu, 0x09u},
- {0xB1u, 0x60u},
- {0xB2u, 0xFFu},
- {0xB3u, 0x18u},
- {0xB5u, 0x01u},
- {0xB7u, 0x06u},
- {0xBAu, 0x08u},
- {0xBBu, 0x08u},
- {0xBFu, 0x41u},
+ {0xA4u, 0x0Du},
+ {0xA7u, 0x04u},
+ {0xA8u, 0x52u},
+ {0xAAu, 0x28u},
+ {0xABu, 0x02u},
+ {0xACu, 0x0Du},
+ {0xB0u, 0x70u},
+ {0xB1u, 0x0Cu},
+ {0xB2u, 0x0Fu},
+ {0xB3u, 0x03u},
+ {0xBAu, 0x0Au},
+ {0xBFu, 0x05u},
{0xD6u, 0x08u},
{0xD8u, 0x04u},
{0xD9u, 0x04u},
{0xDBu, 0x04u},
- {0xDCu, 0x91u},
{0xDDu, 0x90u},
{0xDFu, 0x01u},
- {0x00u, 0x18u},
- {0x02u, 0x80u},
- {0x06u, 0x08u},
- {0x08u, 0x02u},
- {0x09u, 0x04u},
- {0x0Au, 0x08u},
- {0x0Cu, 0x02u},
- {0x0Eu, 0x12u},
+ {0x00u, 0x48u},
+ {0x04u, 0x24u},
+ {0x06u, 0x21u},
+ {0x09u, 0x40u},
+ {0x0Au, 0xA8u},
+ {0x0Eu, 0x18u},
{0x10u, 0x10u},
- {0x11u, 0xA0u},
- {0x14u, 0x08u},
- {0x15u, 0x40u},
- {0x16u, 0x10u},
- {0x18u, 0x30u},
- {0x1Du, 0x01u},
- {0x20u, 0x82u},
- {0x22u, 0x1Cu},
- {0x23u, 0x04u},
- {0x25u, 0x60u},
- {0x27u, 0x21u},
- {0x29u, 0x48u},
- {0x2Au, 0x02u},
- {0x2Bu, 0x10u},
- {0x2Du, 0x04u},
- {0x30u, 0x02u},
- {0x32u, 0x14u},
- {0x36u, 0x08u},
- {0x37u, 0x21u},
- {0x39u, 0x50u},
- {0x3Au, 0x09u},
- {0x3Du, 0x2Au},
- {0x59u, 0x10u},
- {0x5Au, 0x80u},
- {0x5Eu, 0x20u},
- {0x5Fu, 0x48u},
- {0x63u, 0x0Au},
- {0x64u, 0x04u},
- {0x65u, 0x80u},
- {0x66u, 0x04u},
- {0x6Du, 0x04u},
- {0x6Fu, 0x0Au},
- {0x81u, 0x10u},
- {0x85u, 0x10u},
- {0x87u, 0x0Cu},
- {0x88u, 0x41u},
- {0x8Du, 0x20u},
- {0x8Eu, 0x04u},
- {0x8Fu, 0x0Cu},
- {0x92u, 0x10u},
- {0x93u, 0x40u},
- {0x94u, 0x08u},
- {0x95u, 0x01u},
- {0x97u, 0x20u},
- {0x98u, 0x08u},
- {0x99u, 0x40u},
- {0x9Au, 0x9Bu},
- {0x9Du, 0x09u},
- {0x9Eu, 0x40u},
- {0x9Fu, 0x10u},
- {0xA0u, 0x06u},
- {0xA2u, 0x93u},
- {0xA4u, 0x28u},
- {0xA5u, 0x60u},
- {0xA6u, 0x08u},
- {0xA7u, 0x02u},
- {0xAAu, 0x01u},
- {0xAFu, 0x0Au},
+ {0x11u, 0x41u},
+ {0x12u, 0x08u},
+ {0x15u, 0x04u},
+ {0x16u, 0x04u},
+ {0x17u, 0x41u},
+ {0x1Au, 0xA0u},
+ {0x1Bu, 0x01u},
+ {0x1Du, 0x30u},
+ {0x1Eu, 0x18u},
+ {0x1Fu, 0x51u},
+ {0x21u, 0x04u},
+ {0x22u, 0x02u},
+ {0x24u, 0x08u},
+ {0x26u, 0x01u},
+ {0x27u, 0x18u},
+ {0x29u, 0x22u},
+ {0x2Bu, 0x20u},
+ {0x2Eu, 0xA0u},
+ {0x2Fu, 0x10u},
+ {0x32u, 0x80u},
+ {0x33u, 0x10u},
+ {0x37u, 0x59u},
+ {0x3Cu, 0x20u},
+ {0x3Du, 0x04u},
+ {0x3Eu, 0x04u},
+ {0x58u, 0x64u},
+ {0x5Du, 0x80u},
+ {0x5Fu, 0x20u},
+ {0x61u, 0x04u},
+ {0x62u, 0x40u},
+ {0x63u, 0x08u},
+ {0x64u, 0x08u},
+ {0x66u, 0x80u},
+ {0x80u, 0x08u},
+ {0x81u, 0x24u},
+ {0x83u, 0x04u},
+ {0x84u, 0x04u},
+ {0x86u, 0x02u},
+ {0x88u, 0x20u},
+ {0x89u, 0x06u},
+ {0x8Au, 0x40u},
+ {0x8Du, 0x80u},
+ {0x90u, 0x04u},
+ {0x92u, 0x04u},
+ {0x94u, 0x80u},
+ {0x96u, 0x51u},
+ {0x97u, 0x46u},
+ {0x9Du, 0x18u},
+ {0x9Eu, 0x84u},
+ {0x9Fu, 0x41u},
+ {0xA2u, 0xD0u},
+ {0xA3u, 0x50u},
+ {0xA4u, 0xAAu},
+ {0xA5u, 0x13u},
+ {0xA6u, 0x04u},
+ {0xA7u, 0x04u},
+ {0xA9u, 0x08u},
+ {0xAAu, 0x20u},
+ {0xABu, 0x10u},
+ {0xAEu, 0x40u},
+ {0xAFu, 0x80u},
{0xB0u, 0x04u},
- {0xB2u, 0x80u},
- {0xB3u, 0x01u},
- {0xB5u, 0x80u},
- {0xC0u, 0x4Eu},
- {0xC2u, 0xBEu},
- {0xC4u, 0xE7u},
- {0xCAu, 0x4Bu},
- {0xCCu, 0xE7u},
- {0xCEu, 0xEFu},
- {0xD6u, 0x7Cu},
- {0xD8u, 0x7Cu},
- {0xE0u, 0x01u},
- {0xE2u, 0x50u},
- {0xE6u, 0x14u},
- {0xEAu, 0x20u},
- {0xEEu, 0x20u},
- {0x02u, 0x01u},
- {0x04u, 0x10u},
- {0x05u, 0x02u},
- {0x06u, 0x20u},
- {0x07u, 0x09u},
- {0x09u, 0x02u},
- {0x0Bu, 0x01u},
- {0x0Cu, 0x40u},
- {0x0Eu, 0x80u},
- {0x14u, 0x20u},
- {0x16u, 0x12u},
- {0x19u, 0x01u},
- {0x1Bu, 0x02u},
- {0x1Du, 0x02u},
- {0x1Fu, 0x01u},
- {0x20u, 0x80u},
- {0x22u, 0x44u},
- {0x25u, 0x02u},
- {0x27u, 0x05u},
- {0x2Au, 0x08u},
- {0x2Cu, 0x32u},
- {0x2Eu, 0xC4u},
- {0x30u, 0x06u},
- {0x32u, 0x08u},
- {0x33u, 0x08u},
- {0x34u, 0xF0u},
- {0x35u, 0x03u},
- {0x36u, 0x01u},
- {0x37u, 0x04u},
- {0x3Bu, 0x20u},
- {0x3Eu, 0x11u},
+ {0xB2u, 0x16u},
+ {0xC0u, 0xE5u},
+ {0xC2u, 0x6Fu},
+ {0xC4u, 0xFFu},
+ {0xCAu, 0x77u},
+ {0xCCu, 0xFCu},
+ {0xCEu, 0x60u},
+ {0xD6u, 0x3Eu},
+ {0xD8u, 0x3Eu},
+ {0xE0u, 0x02u},
+ {0xE2u, 0x28u},
+ {0xE4u, 0x20u},
+ {0xE6u, 0x10u},
+ {0xE8u, 0x80u},
+ {0xEAu, 0x22u},
+ {0xECu, 0x20u},
+ {0x00u, 0x20u},
+ {0x02u, 0x10u},
+ {0x03u, 0xFFu},
+ {0x04u, 0x20u},
+ {0x05u, 0x05u},
+ {0x06u, 0x10u},
+ {0x07u, 0x0Au},
+ {0x0Au, 0x04u},
+ {0x0Bu, 0xFFu},
+ {0x0Fu, 0xFFu},
+ {0x10u, 0x20u},
+ {0x11u, 0x90u},
+ {0x12u, 0x10u},
+ {0x13u, 0x60u},
+ {0x15u, 0x50u},
+ {0x16u, 0x01u},
+ {0x17u, 0xA0u},
+ {0x18u, 0x10u},
+ {0x19u, 0x30u},
+ {0x1Au, 0x20u},
+ {0x1Bu, 0xC0u},
+ {0x1Cu, 0x05u},
+ {0x1Eu, 0x0Au},
+ {0x21u, 0x0Fu},
+ {0x22u, 0x02u},
+ {0x23u, 0xF0u},
+ {0x25u, 0x09u},
+ {0x26u, 0x08u},
+ {0x27u, 0x06u},
+ {0x29u, 0x03u},
+ {0x2Bu, 0x0Cu},
+ {0x2Cu, 0x20u},
+ {0x2Eu, 0x10u},
+ {0x32u, 0x0Cu},
+ {0x34u, 0x30u},
+ {0x35u, 0xFFu},
+ {0x36u, 0x03u},
+ {0x3Au, 0x20u},
+ {0x3Eu, 0x44u},
+ {0x3Fu, 0x10u},
{0x56u, 0x08u},
{0x58u, 0x04u},
{0x59u, 0x04u},
{0x5Bu, 0x04u},
- {0x5Cu, 0x99u},
+ {0x5Cu, 0x09u},
{0x5Du, 0x90u},
{0x5Fu, 0x01u},
- {0x82u, 0x80u},
- {0x83u, 0x38u},
- {0x84u, 0x99u},
- {0x85u, 0x01u},
- {0x86u, 0x22u},
- {0x89u, 0x4Au},
- {0x8Au, 0x70u},
- {0x8Bu, 0x15u},
- {0x8Du, 0x22u},
- {0x8Fu, 0x45u},
- {0x91u, 0x01u},
- {0x93u, 0x06u},
- {0x96u, 0x08u},
- {0x97u, 0x01u},
- {0x98u, 0x44u},
- {0x99u, 0x53u},
+ {0x80u, 0x59u},
+ {0x82u, 0xA2u},
+ {0x85u, 0x55u},
+ {0x86u, 0x20u},
+ {0x87u, 0xAAu},
+ {0x8Au, 0x30u},
+ {0x8Bu, 0xFFu},
+ {0x8Du, 0x69u},
+ {0x8Fu, 0x96u},
+ {0x90u, 0x30u},
+ {0x91u, 0xFFu},
+ {0x92u, 0xC0u},
+ {0x95u, 0x0Fu},
+ {0x96u, 0x07u},
+ {0x97u, 0xF0u},
+ {0x98u, 0x74u},
{0x9Au, 0x88u},
- {0x9Bu, 0x2Cu},
- {0x9Eu, 0x07u},
- {0xA7u, 0x40u},
- {0xA8u, 0xAAu},
- {0xAAu, 0x55u},
- {0xB1u, 0x07u},
- {0xB2u, 0xF0u},
- {0xB6u, 0x0Fu},
- {0xB7u, 0x78u},
- {0xBBu, 0x02u},
+ {0x9Bu, 0xFFu},
+ {0x9Eu, 0x08u},
+ {0x9Fu, 0xFFu},
+ {0xA0u, 0x6Au},
+ {0xA2u, 0x95u},
+ {0xA5u, 0xFFu},
+ {0xACu, 0x10u},
+ {0xADu, 0x33u},
+ {0xAFu, 0xCCu},
+ {0xB0u, 0xF0u},
+ {0xB2u, 0x0Fu},
+ {0xB5u, 0xFFu},
+ {0xBAu, 0x02u},
+ {0xBBu, 0x20u},
{0xD8u, 0x04u},
{0xD9u, 0x04u},
{0xDBu, 0x04u},
{0xDCu, 0x11u},
{0xDFu, 0x01u},
- {0x01u, 0x08u},
- {0x02u, 0x01u},
- {0x03u, 0x80u},
- {0x04u, 0x18u},
- {0x06u, 0x60u},
- {0x0Bu, 0x20u},
- {0x0Cu, 0x08u},
- {0x0Du, 0x20u},
- {0x0Eu, 0x02u},
- {0x10u, 0x82u},
- {0x13u, 0x10u},
- {0x17u, 0x10u},
- {0x18u, 0x80u},
- {0x19u, 0x64u},
- {0x1Cu, 0x10u},
- {0x1Eu, 0x12u},
+ {0x00u, 0x01u},
+ {0x03u, 0x18u},
+ {0x05u, 0x28u},
+ {0x07u, 0x40u},
+ {0x08u, 0x40u},
+ {0x09u, 0x02u},
+ {0x0Au, 0x18u},
+ {0x0Bu, 0x10u},
+ {0x0Du, 0x08u},
+ {0x0Eu, 0x89u},
+ {0x10u, 0xA0u},
+ {0x12u, 0x01u},
+ {0x14u, 0x08u},
+ {0x16u, 0x06u},
+ {0x17u, 0x01u},
+ {0x18u, 0x04u},
+ {0x19u, 0x20u},
+ {0x1Au, 0x28u},
+ {0x1Bu, 0x70u},
+ {0x1Du, 0x08u},
+ {0x1Eu, 0x80u},
{0x20u, 0x08u},
- {0x22u, 0x50u},
- {0x23u, 0x10u},
- {0x24u, 0x01u},
- {0x25u, 0x80u},
- {0x26u, 0x02u},
- {0x29u, 0x04u},
- {0x2Cu, 0x20u},
- {0x32u, 0x50u},
- {0x36u, 0x0Au},
- {0x37u, 0x10u},
- {0x3Bu, 0x14u},
- {0x3Cu, 0x09u},
- {0x3Du, 0x80u},
- {0x3Eu, 0x20u},
- {0x59u, 0x90u},
- {0x62u, 0x80u},
- {0x63u, 0x04u},
- {0x68u, 0x02u},
- {0x6Cu, 0x90u},
- {0x6Fu, 0x09u},
- {0x75u, 0x02u},
- {0x76u, 0x19u},
- {0x80u, 0x50u},
- {0x81u, 0x20u},
- {0x82u, 0x02u},
- {0x83u, 0x80u},
- {0x84u, 0x02u},
- {0x86u, 0x10u},
- {0x88u, 0x08u},
- {0x89u, 0x03u},
- {0x8Bu, 0x40u},
- {0x8Du, 0x91u},
- {0xC0u, 0x7Du},
- {0xC2u, 0xE4u},
- {0xC4u, 0x4Bu},
- {0xCAu, 0x42u},
- {0xCCu, 0xECu},
- {0xCEu, 0xF6u},
- {0xD6u, 0x0Cu},
- {0xD8u, 0x0Cu},
- {0xE0u, 0x01u},
- {0xE2u, 0x90u},
- {0xE4u, 0x10u},
- {0xE6u, 0xC8u},
- {0xAAu, 0x04u},
- {0xE0u, 0x08u},
+ {0x26u, 0x20u},
+ {0x27u, 0x08u},
+ {0x28u, 0x40u},
+ {0x2Au, 0x08u},
+ {0x2Bu, 0x08u},
+ {0x2Eu, 0x84u},
+ {0x30u, 0x2Au},
+ {0x35u, 0x10u},
+ {0x37u, 0x49u},
+ {0x38u, 0x80u},
+ {0x3Au, 0x12u},
+ {0x3Bu, 0x04u},
+ {0x3Du, 0x03u},
+ {0x3Eu, 0x40u},
+ {0x3Fu, 0x28u},
+ {0x45u, 0x10u},
+ {0x47u, 0x20u},
+ {0x5Bu, 0x80u},
+ {0x5Cu, 0x08u},
+ {0x5Du, 0x01u},
+ {0x5Fu, 0x60u},
+ {0x62u, 0x40u},
+ {0x67u, 0x02u},
+ {0x82u, 0x19u},
+ {0x88u, 0x40u},
+ {0x8Au, 0x90u},
+ {0x8Bu, 0x18u},
+ {0x8Cu, 0x81u},
+ {0x8Fu, 0x20u},
+ {0xC0u, 0x7Eu},
+ {0xC2u, 0xFFu},
+ {0xC4u, 0x9Du},
+ {0xCAu, 0x57u},
+ {0xCCu, 0xF7u},
+ {0xCEu, 0x7Fu},
+ {0xD6u, 0xF8u},
+ {0xD8u, 0x18u},
+ {0xE0u, 0xA1u},
+ {0xE2u, 0x50u},
+ {0xE4u, 0x34u},
+ {0xE6u, 0xC0u},
+ {0xA9u, 0x80u},
+ {0xE4u, 0x80u},
{0xE6u, 0x02u},
- {0xEAu, 0x01u},
- {0xEEu, 0x02u},
- {0x9Eu, 0x04u},
+ {0xEAu, 0x04u},
+ {0xEEu, 0x20u},
+ {0x80u, 0x04u},
+ {0x84u, 0x08u},
+ {0x88u, 0x02u},
+ {0x89u, 0x10u},
+ {0x90u, 0x04u},
+ {0x91u, 0x20u},
+ {0x9Cu, 0x08u},
+ {0x9Du, 0x80u},
+ {0xA0u, 0x02u},
+ {0xA8u, 0x80u},
+ {0xA9u, 0x40u},
+ {0xE0u, 0x04u},
{0xE2u, 0x08u},
- {0xEEu, 0x01u},
- {0x02u, 0x08u},
- {0x03u, 0x08u},
- {0x07u, 0x80u},
- {0x0Bu, 0x07u},
- {0x0Cu, 0x44u},
- {0x0Eu, 0x88u},
- {0x0Fu, 0x70u},
- {0x11u, 0x44u},
- {0x13u, 0x88u},
- {0x15u, 0x99u},
- {0x16u, 0x07u},
- {0x17u, 0x22u},
- {0x19u, 0xAAu},
- {0x1Au, 0x70u},
- {0x1Bu, 0x55u},
- {0x1Eu, 0x80u},
- {0x24u, 0x99u},
- {0x26u, 0x22u},
- {0x28u, 0xAAu},
- {0x2Au, 0x55u},
- {0x32u, 0x0Fu},
- {0x34u, 0xF0u},
- {0x35u, 0x0Fu},
- {0x37u, 0xF0u},
- {0x40u, 0x36u},
- {0x41u, 0x01u},
- {0x42u, 0x50u},
- {0x44u, 0x04u},
- {0x45u, 0x0Eu},
- {0x46u, 0xFCu},
- {0x47u, 0xBDu},
- {0x48u, 0x3Du},
- {0x49u, 0xFFu},
- {0x4Au, 0xFFu},
- {0x4Bu, 0xFFu},
- {0x4Cu, 0x22u},
- {0x4Eu, 0xF0u},
- {0x4Fu, 0x08u},
- {0x50u, 0x04u},
- {0x54u, 0x09u},
- {0x56u, 0x04u},
+ {0xE6u, 0x08u},
+ {0xE8u, 0x04u},
+ {0xEAu, 0x01u},
+ {0xEEu, 0x08u},
+ {0x05u, 0x05u},
+ {0x07u, 0x0Au},
+ {0x09u, 0x50u},
+ {0x0Bu, 0xA0u},
+ {0x0Du, 0x06u},
+ {0x0Fu, 0x09u},
+ {0x13u, 0xFFu},
+ {0x14u, 0x01u},
+ {0x15u, 0x03u},
+ {0x17u, 0x0Cu},
+ {0x1Bu, 0xFFu},
+ {0x1Du, 0xFFu},
+ {0x25u, 0x30u},
+ {0x27u, 0xC0u},
+ {0x29u, 0x0Fu},
+ {0x2Bu, 0xF0u},
+ {0x2Du, 0x60u},
+ {0x2Fu, 0x90u},
+ {0x33u, 0xFFu},
+ {0x34u, 0x01u},
+ {0x3Fu, 0x04u},
+ {0x56u, 0x08u},
{0x58u, 0x04u},
- {0x59u, 0x04u},
- {0x5Au, 0x04u},
- {0x5Bu, 0x04u},
- {0x5Cu, 0x11u},
- {0x5Fu, 0x01u},
- {0x62u, 0xC0u},
- {0x64u, 0x40u},
- {0x65u, 0x01u},
- {0x66u, 0x10u},
- {0x67u, 0x11u},
- {0x68u, 0xC0u},
- {0x69u, 0x01u},
- {0x6Bu, 0x11u},
- {0x6Cu, 0x40u},
- {0x6Du, 0x01u},
- {0x6Eu, 0x40u},
- {0x6Fu, 0x01u},
- {0x81u, 0x0Cu},
- {0x85u, 0xB8u},
- {0x87u, 0x45u},
- {0x89u, 0x73u},
- {0x8Bu, 0x88u},
- {0x8Du, 0x0Cu},
- {0x91u, 0x04u},
- {0x93u, 0x08u},
- {0x95u, 0x08u},
- {0x97u, 0x04u},
- {0x98u, 0x01u},
- {0x99u, 0x14u},
- {0x9Bu, 0x08u},
- {0x9Du, 0x80u},
- {0x9Fu, 0x60u},
- {0xA3u, 0x02u},
- {0xA9u, 0x0Cu},
- {0xADu, 0x2Fu},
- {0xAFu, 0xD0u},
- {0xB3u, 0x07u},
- {0xB5u, 0x18u},
- {0xB6u, 0x01u},
- {0xB7u, 0xE0u},
- {0xBBu, 0xACu},
- {0xD8u, 0x04u},
- {0xD9u, 0x04u},
- {0xDCu, 0x09u},
- {0xDFu, 0x01u},
- {0x04u, 0x02u},
- {0x07u, 0x01u},
- {0x0Au, 0x08u},
- {0x0Eu, 0x19u},
- {0x17u, 0x14u},
+ {0x59u, 0x04u},
+ {0x5Bu, 0x04u},
+ {0x5Cu, 0x09u},
+ {0x5Du, 0x90u},
+ {0x5Fu, 0x01u},
+ {0x00u, 0x64u},
+ {0x01u, 0x02u},
+ {0x09u, 0x40u},
+ {0x0Au, 0x21u},
+ {0x0Bu, 0x84u},
+ {0x0Fu, 0x20u},
+ {0x10u, 0x18u},
+ {0x11u, 0x45u},
+ {0x18u, 0x10u},
+ {0x19u, 0x20u},
{0x1Au, 0x02u},
- {0x1Eu, 0x18u},
- {0x1Fu, 0x18u},
- {0x20u, 0x04u},
- {0x21u, 0x0Cu},
- {0x22u, 0x90u},
- {0x23u, 0x10u},
- {0x25u, 0x50u},
- {0x28u, 0x01u},
- {0x29u, 0x10u},
- {0x2Bu, 0x40u},
- {0x30u, 0x0Au},
- {0x32u, 0x90u},
- {0x37u, 0x15u},
- {0x38u, 0x80u},
- {0x39u, 0x29u},
- {0x3Du, 0xE0u},
- {0x3Eu, 0x0Au},
- {0x3Fu, 0x20u},
- {0x44u, 0x01u},
- {0x45u, 0x04u},
- {0x46u, 0x40u},
- {0x47u, 0x40u},
- {0x4Du, 0x84u},
- {0x4Fu, 0x10u},
- {0x56u, 0x25u},
- {0x57u, 0xC0u},
- {0x5Du, 0x04u},
- {0x5Eu, 0x62u},
+ {0x1Bu, 0x80u},
+ {0x1Eu, 0x04u},
+ {0x21u, 0x80u},
+ {0x22u, 0x20u},
+ {0x23u, 0x20u},
+ {0x27u, 0x10u},
+ {0x2Cu, 0x26u},
+ {0x32u, 0x28u},
+ {0x36u, 0x11u},
+ {0x37u, 0x88u},
+ {0x38u, 0x44u},
+ {0x39u, 0x20u},
+ {0x3Du, 0x28u},
+ {0x3Fu, 0x80u},
+ {0x40u, 0x04u},
+ {0x42u, 0x20u},
+ {0x43u, 0x80u},
+ {0x48u, 0x40u},
+ {0x49u, 0x06u},
+ {0x4Au, 0x8Au},
+ {0x51u, 0x20u},
+ {0x52u, 0x44u},
+ {0x53u, 0x40u},
+ {0x5Fu, 0x40u},
+ {0x63u, 0x02u},
{0x65u, 0x40u},
- {0x67u, 0x80u},
- {0x87u, 0x40u},
- {0x90u, 0x02u},
- {0x92u, 0x09u},
- {0x94u, 0x80u},
- {0x95u, 0x69u},
- {0x97u, 0x20u},
- {0x99u, 0x40u},
- {0x9Au, 0x0Au},
- {0x9Bu, 0x15u},
- {0x9Eu, 0x01u},
- {0x9Fu, 0x40u},
- {0xA4u, 0x2Au},
- {0xA5u, 0x0Cu},
- {0xA7u, 0x18u},
- {0xAAu, 0x50u},
- {0xABu, 0x08u},
- {0xB2u, 0x01u},
- {0xC0u, 0x90u},
- {0xC2u, 0xE2u},
- {0xC4u, 0x60u},
- {0xCAu, 0x0Du},
- {0xCCu, 0xEFu},
- {0xCEu, 0xFFu},
- {0xD0u, 0xD0u},
- {0xD2u, 0x30u},
- {0xD6u, 0xF0u},
- {0xD8u, 0x90u},
- {0xEAu, 0x04u},
- {0xEEu, 0x04u},
- {0x00u, 0x01u},
- {0x01u, 0xC0u},
- {0x03u, 0x02u},
- {0x05u, 0x80u},
- {0x0Bu, 0xFFu},
- {0x0Du, 0xC0u},
- {0x0Fu, 0x01u},
- {0x11u, 0x90u},
- {0x13u, 0x40u},
- {0x15u, 0xC0u},
- {0x17u, 0x08u},
- {0x18u, 0x01u},
- {0x19u, 0xC0u},
- {0x1Bu, 0x04u},
- {0x1Du, 0x1Fu},
- {0x1Fu, 0x20u},
- {0x23u, 0x9Fu},
- {0x25u, 0x7Fu},
- {0x27u, 0x80u},
- {0x2Fu, 0x60u},
- {0x30u, 0x01u},
- {0x37u, 0xFFu},
- {0x38u, 0x02u},
+ {0x68u, 0x0Cu},
+ {0x69u, 0x55u},
+ {0x72u, 0x01u},
+ {0x83u, 0x08u},
+ {0x85u, 0x44u},
+ {0x88u, 0x04u},
+ {0x8Bu, 0x82u},
+ {0x90u, 0x06u},
+ {0x91u, 0x28u},
+ {0x92u, 0x20u},
+ {0x94u, 0x50u},
+ {0x95u, 0x41u},
+ {0x96u, 0x04u},
+ {0x9Au, 0x90u},
+ {0x9Bu, 0x41u},
+ {0x9Cu, 0x14u},
+ {0x9Du, 0x40u},
+ {0x9Eu, 0x44u},
+ {0xA0u, 0x22u},
+ {0xA1u, 0x10u},
+ {0xA2u, 0x15u},
+ {0xA3u, 0x59u},
+ {0xA4u, 0x04u},
+ {0xA5u, 0x6Cu},
+ {0xA6u, 0x88u},
+ {0xA7u, 0x20u},
+ {0xA8u, 0x40u},
+ {0xABu, 0x40u},
+ {0xB0u, 0x01u},
+ {0xB1u, 0x08u},
+ {0xB3u, 0x10u},
+ {0xC0u, 0x0Fu},
+ {0xC2u, 0x2Fu},
+ {0xC4u, 0x0Fu},
+ {0xCAu, 0x70u},
+ {0xCCu, 0xF6u},
+ {0xCEu, 0x7Eu},
+ {0xD0u, 0x0Eu},
+ {0xD2u, 0x0Cu},
+ {0xD6u, 0x10u},
+ {0xD8u, 0x18u},
+ {0xE4u, 0xA0u},
+ {0xEEu, 0x08u},
+ {0x00u, 0xC0u},
+ {0x01u, 0x77u},
+ {0x02u, 0x02u},
+ {0x03u, 0x80u},
+ {0x04u, 0x1Fu},
+ {0x05u, 0x24u},
+ {0x06u, 0x20u},
+ {0x07u, 0x40u},
+ {0x08u, 0x7Fu},
+ {0x0Au, 0x80u},
+ {0x0Bu, 0x64u},
+ {0x0Du, 0x64u},
+ {0x0Eu, 0x9Fu},
+ {0x11u, 0x93u},
+ {0x12u, 0xFFu},
+ {0x13u, 0x60u},
+ {0x14u, 0x80u},
+ {0x15u, 0x10u},
+ {0x17u, 0xE5u},
+ {0x19u, 0x24u},
+ {0x1Au, 0x60u},
+ {0x1Cu, 0xC0u},
+ {0x1Du, 0x64u},
+ {0x1Eu, 0x01u},
+ {0x21u, 0x08u},
+ {0x24u, 0xC0u},
+ {0x25u, 0x40u},
+ {0x26u, 0x04u},
+ {0x27u, 0x02u},
+ {0x28u, 0xC0u},
+ {0x29u, 0x08u},
+ {0x2Au, 0x08u},
+ {0x2Cu, 0x90u},
+ {0x2Du, 0x64u},
+ {0x2Eu, 0x40u},
+ {0x30u, 0xFFu},
+ {0x31u, 0xF0u},
+ {0x33u, 0x07u},
+ {0x35u, 0x08u},
+ {0x37u, 0x80u},
+ {0x39u, 0x22u},
+ {0x3Bu, 0x0Cu},
+ {0x3Eu, 0x01u},
{0x3Fu, 0x40u},
- {0x56u, 0x02u},
- {0x57u, 0x20u},
+ {0x54u, 0x09u},
+ {0x56u, 0x04u},
{0x58u, 0x04u},
{0x59u, 0x04u},
{0x5Bu, 0x04u},
{0x5Fu, 0x01u},
- {0x80u, 0x07u},
- {0x81u, 0x6Cu},
- {0x82u, 0x18u},
- {0x84u, 0x01u},
- {0x85u, 0x24u},
- {0x89u, 0x91u},
- {0x8Au, 0x80u},
- {0x8Bu, 0x6Eu},
- {0x8Cu, 0xC1u},
- {0x8Du, 0x48u},
- {0x90u, 0x01u},
- {0x92u, 0xC0u},
- {0x94u, 0xC0u},
- {0x98u, 0x08u},
- {0x99u, 0x24u},
- {0x9Au, 0x21u},
- {0x9Bu, 0x48u},
- {0x9Cu, 0x04u},
- {0x9Du, 0x71u},
- {0x9Fu, 0x82u},
- {0xA0u, 0xC1u},
- {0xA1u, 0x6Cu},
- {0xA4u, 0x22u},
- {0xA5u, 0x10u},
+ {0x82u, 0x80u},
+ {0x8Au, 0x70u},
+ {0x8Bu, 0x20u},
+ {0x8Cu, 0xAAu},
+ {0x8Eu, 0x55u},
+ {0x91u, 0x0Au},
+ {0x93u, 0x05u},
+ {0x95u, 0x04u},
+ {0x96u, 0x07u},
+ {0x97u, 0x08u},
+ {0x98u, 0x44u},
+ {0x9Au, 0x88u},
+ {0x9Bu, 0x17u},
+ {0x9Du, 0x09u},
+ {0x9Fu, 0x02u},
{0xA6u, 0x08u},
- {0xA7u, 0xEFu},
- {0xA8u, 0xC1u},
- {0xABu, 0x6Cu},
- {0xACu, 0x10u},
- {0xADu, 0x6Cu},
- {0xB0u, 0x08u},
- {0xB1u, 0x0Fu},
- {0xB2u, 0x80u},
- {0xB3u, 0xF0u},
- {0xB4u, 0x3Fu},
- {0xB6u, 0x40u},
- {0xB8u, 0x20u},
- {0xB9u, 0x08u},
- {0xBEu, 0x55u},
- {0xD4u, 0x40u},
- {0xD6u, 0x04u},
+ {0xABu, 0x08u},
+ {0xACu, 0x99u},
+ {0xADu, 0x10u},
+ {0xAEu, 0x22u},
+ {0xAFu, 0x20u},
+ {0xB2u, 0x0Fu},
+ {0xB3u, 0x0Fu},
+ {0xB4u, 0xF0u},
+ {0xB5u, 0x30u},
+ {0xBFu, 0x10u},
{0xD8u, 0x04u},
{0xD9u, 0x04u},
- {0xDBu, 0x04u},
+ {0xDCu, 0x11u},
{0xDFu, 0x01u},
- {0x00u, 0x02u},
- {0x04u, 0x04u},
- {0x06u, 0x06u},
- {0x07u, 0x40u},
- {0x0Au, 0x04u},
- {0x0Cu, 0x0Au},
- {0x0Eu, 0x08u},
- {0x0Fu, 0x02u},
- {0x14u, 0x10u},
- {0x15u, 0x09u},
- {0x16u, 0x01u},
- {0x17u, 0x20u},
- {0x1Bu, 0x01u},
- {0x1Du, 0x44u},
- {0x1Eu, 0x46u},
- {0x20u, 0x02u},
- {0x24u, 0x10u},
+ {0x00u, 0xA4u},
+ {0x01u, 0x01u},
+ {0x02u, 0x40u},
+ {0x05u, 0x10u},
+ {0x06u, 0x80u},
+ {0x07u, 0x01u},
+ {0x08u, 0x40u},
+ {0x09u, 0x02u},
+ {0x0Au, 0x21u},
+ {0x0Bu, 0x04u},
+ {0x0Eu, 0x28u},
+ {0x10u, 0x08u},
+ {0x11u, 0x44u},
+ {0x16u, 0x10u},
+ {0x17u, 0x40u},
+ {0x19u, 0x02u},
+ {0x1Du, 0x18u},
+ {0x1Eu, 0x20u},
+ {0x1Fu, 0x20u},
+ {0x20u, 0x60u},
+ {0x21u, 0x02u},
+ {0x22u, 0x4Au},
+ {0x23u, 0x04u},
{0x25u, 0x04u},
- {0x26u, 0x04u},
- {0x27u, 0x40u},
+ {0x27u, 0x18u},
{0x28u, 0x10u},
- {0x2Au, 0x01u},
- {0x2Bu, 0x01u},
- {0x2Cu, 0x1Au},
- {0x2Eu, 0x02u},
- {0x30u, 0x2Au},
- {0x31u, 0x10u},
- {0x33u, 0x40u},
- {0x37u, 0x60u},
- {0x38u, 0x94u},
- {0x39u, 0x21u},
- {0x3Cu, 0x14u},
- {0x3Du, 0x01u},
- {0x3Fu, 0x80u},
- {0x59u, 0xC0u},
- {0x62u, 0x80u},
- {0x65u, 0x04u},
- {0x66u, 0xA0u},
- {0x67u, 0x40u},
- {0x68u, 0x2Au},
- {0x69u, 0x01u},
- {0x6Bu, 0x20u},
- {0x70u, 0x40u},
- {0x72u, 0x02u},
- {0x86u, 0x40u},
+ {0x29u, 0x22u},
+ {0x2Au, 0x44u},
+ {0x2Fu, 0x0Au},
+ {0x30u, 0x40u},
+ {0x31u, 0x02u},
+ {0x32u, 0x18u},
+ {0x36u, 0x04u},
+ {0x37u, 0x51u},
+ {0x38u, 0x02u},
+ {0x39u, 0x54u},
+ {0x3Du, 0x20u},
+ {0x58u, 0x10u},
+ {0x59u, 0x04u},
+ {0x5Au, 0x82u},
+ {0x61u, 0x80u},
+ {0x63u, 0x40u},
{0x87u, 0x40u},
- {0x8Eu, 0x84u},
- {0x90u, 0x04u},
- {0x91u, 0x08u},
- {0x94u, 0x80u},
- {0x95u, 0x21u},
- {0x96u, 0x40u},
- {0x9Au, 0x25u},
- {0x9Du, 0x90u},
- {0x9Eu, 0x40u},
- {0x9Fu, 0x40u},
- {0xA2u, 0x80u},
- {0xA3u, 0x40u},
- {0xA4u, 0x2Au},
- {0xA5u, 0x04u},
- {0xA6u, 0x01u},
- {0xAAu, 0x10u},
- {0xAEu, 0x01u},
- {0xB2u, 0x10u},
- {0xB3u, 0x80u},
- {0xC0u, 0xF8u},
- {0xC2u, 0xF2u},
- {0xC4u, 0xF0u},
- {0xCAu, 0xFBu},
- {0xCCu, 0x3Fu},
- {0xCEu, 0xFFu},
- {0xD8u, 0xF8u},
- {0x06u, 0x08u},
- {0x0Fu, 0x08u},
- {0x13u, 0x40u},
- {0x17u, 0x48u},
- {0x33u, 0x08u},
+ {0x8Au, 0x20u},
+ {0x8Fu, 0x08u},
+ {0x90u, 0x06u},
+ {0x91u, 0x55u},
+ {0x92u, 0x23u},
+ {0x94u, 0x40u},
+ {0x97u, 0x04u},
+ {0x99u, 0x24u},
+ {0x9Au, 0x94u},
+ {0x9Bu, 0x41u},
+ {0x9Eu, 0x20u},
+ {0xA0u, 0x48u},
+ {0xA1u, 0x90u},
+ {0xA2u, 0x04u},
+ {0xA3u, 0x0Au},
+ {0xA4u, 0x10u},
+ {0xA5u, 0x0Cu},
+ {0xA6u, 0x0Au},
+ {0xA7u, 0x20u},
+ {0xABu, 0x10u},
+ {0xAFu, 0x40u},
+ {0xB3u, 0x20u},
+ {0xC0u, 0xDFu},
+ {0xC2u, 0x6Fu},
+ {0xC4u, 0xA7u},
+ {0xCAu, 0x3Fu},
+ {0xCCu, 0xFFu},
+ {0xCEu, 0x2Fu},
+ {0xD6u, 0x0Fu},
+ {0xD8u, 0x09u},
+ {0xE4u, 0x80u},
+ {0xEEu, 0x22u},
+ {0x05u, 0x20u},
+ {0x0Du, 0x20u},
+ {0x12u, 0x08u},
+ {0x16u, 0x80u},
+ {0x17u, 0x80u},
+ {0x31u, 0x02u},
+ {0x35u, 0x08u},
{0x36u, 0x80u},
- {0x37u, 0x08u},
- {0x3Au, 0x01u},
- {0x3Bu, 0x40u},
- {0x3Du, 0x84u},
- {0x42u, 0x01u},
- {0x5Du, 0x01u},
- {0x8Cu, 0x08u},
+ {0x38u, 0x08u},
+ {0x3Au, 0x80u},
+ {0x3Du, 0x28u},
+ {0x40u, 0x02u},
+ {0x67u, 0x80u},
+ {0x84u, 0x80u},
+ {0x87u, 0x40u},
{0xC0u, 0x80u},
{0xC2u, 0x80u},
{0xC4u, 0xE0u},
{0xCCu, 0xE0u},
{0xCEu, 0xF0u},
{0xD0u, 0x10u},
- {0xD6u, 0x80u},
- {0x32u, 0x08u},
- {0x33u, 0x40u},
- {0x35u, 0x88u},
- {0x38u, 0x40u},
- {0x52u, 0x20u},
- {0x5Bu, 0x20u},
- {0x63u, 0x40u},
- {0x87u, 0x40u},
- {0x95u, 0x04u},
- {0x96u, 0x01u},
- {0x98u, 0x08u},
- {0x9Au, 0x08u},
- {0x9Bu, 0x40u},
- {0x9Eu, 0x01u},
- {0xA5u, 0x40u},
+ {0xD8u, 0x80u},
+ {0xE2u, 0x10u},
+ {0xE6u, 0x40u},
+ {0x30u, 0x08u},
+ {0x33u, 0x10u},
+ {0x37u, 0x84u},
+ {0x39u, 0x40u},
+ {0x51u, 0x01u},
+ {0x56u, 0x08u},
+ {0x60u, 0x80u},
+ {0x89u, 0x01u},
+ {0x94u, 0x08u},
+ {0x98u, 0x80u},
+ {0x99u, 0x20u},
+ {0x9Bu, 0x90u},
+ {0x9Cu, 0x02u},
+ {0x9Du, 0x08u},
+ {0xA1u, 0x20u},
+ {0xA5u, 0x16u},
{0xA6u, 0x80u},
- {0xA7u, 0x08u},
- {0xADu, 0x41u},
- {0xB6u, 0x01u},
- {0xB7u, 0x04u},
+ {0xAAu, 0x08u},
+ {0xABu, 0x10u},
{0xCCu, 0xF0u},
{0xCEu, 0x10u},
- {0xD4u, 0xA0u},
+ {0xD4u, 0xC0u},
{0xD8u, 0x40u},
- {0xE6u, 0x40u},
- {0xE8u, 0x40u},
- {0xEAu, 0x10u},
{0x12u, 0x80u},
- {0x58u, 0x08u},
- {0x85u, 0x80u},
- {0x86u, 0x08u},
- {0x89u, 0x40u},
- {0x8Cu, 0x40u},
- {0x94u, 0x40u},
- {0x95u, 0x04u},
- {0x96u, 0x01u},
- {0x98u, 0x08u},
- {0x9Au, 0x08u},
- {0x9Du, 0x88u},
- {0x9Eu, 0x01u},
- {0xA5u, 0x40u},
- {0xA6u, 0x88u},
- {0xA7u, 0x08u},
- {0xABu, 0x20u},
- {0xB2u, 0x20u},
+ {0x33u, 0x80u},
+ {0x5Au, 0x01u},
+ {0x80u, 0x04u},
+ {0x85u, 0x08u},
+ {0x92u, 0x01u},
+ {0x94u, 0x08u},
+ {0x95u, 0x40u},
+ {0x99u, 0x20u},
+ {0x9Cu, 0x02u},
+ {0x9Du, 0x08u},
+ {0x9Fu, 0x04u},
+ {0xA4u, 0x08u},
+ {0xA5u, 0x06u},
+ {0xA6u, 0x80u},
+ {0xA9u, 0x10u},
+ {0xAEu, 0x09u},
+ {0xB5u, 0x20u},
{0xC4u, 0x10u},
+ {0xCCu, 0x10u},
{0xD6u, 0x40u},
- {0xE2u, 0x10u},
- {0xE4u, 0x40u},
- {0xEAu, 0x80u},
- {0x82u, 0x08u},
- {0x83u, 0x20u},
- {0x95u, 0x04u},
- {0x96u, 0x01u},
- {0xA6u, 0x08u},
- {0xA7u, 0x08u},
- {0xB1u, 0x08u},
- {0xB6u, 0x01u},
- {0xE2u, 0x20u},
- {0xE6u, 0x20u},
- {0x01u, 0x40u},
- {0x05u, 0x10u},
- {0x08u, 0x80u},
- {0x0Fu, 0x02u},
- {0x10u, 0x80u},
- {0x14u, 0x20u},
- {0x5Bu, 0x04u},
- {0x62u, 0x04u},
+ {0xE6u, 0x90u},
+ {0xEAu, 0x90u},
+ {0xEEu, 0x40u},
{0x83u, 0x04u},
- {0x87u, 0x01u},
- {0x88u, 0x80u},
- {0x8Du, 0x40u},
- {0x8Eu, 0x04u},
+ {0x89u, 0x02u},
+ {0x8Du, 0x04u},
+ {0x9Cu, 0x02u},
+ {0x9Fu, 0x04u},
+ {0xA5u, 0x06u},
+ {0xA7u, 0x80u},
+ {0xB0u, 0x08u},
+ {0xB1u, 0x20u},
+ {0xB5u, 0x40u},
+ {0xE2u, 0x80u},
+ {0x00u, 0x80u},
+ {0x05u, 0x20u},
+ {0x09u, 0x20u},
+ {0x0Eu, 0x01u},
+ {0x13u, 0x02u},
+ {0x14u, 0x40u},
+ {0x62u, 0x02u},
+ {0x65u, 0x02u},
+ {0x81u, 0x02u},
+ {0x82u, 0x02u},
+ {0x8Du, 0x20u},
{0xC0u, 0x03u},
{0xC2u, 0x03u},
{0xC4u, 0x0Cu},
- {0xD6u, 0x02u},
- {0xD8u, 0x02u},
- {0xE2u, 0x06u},
- {0xE4u, 0x08u},
- {0x01u, 0x02u},
- {0x05u, 0x01u},
- {0x09u, 0x04u},
- {0x0Eu, 0x40u},
- {0x50u, 0x04u},
- {0x5Fu, 0x20u},
- {0x64u, 0x09u},
- {0x80u, 0x20u},
- {0x83u, 0x20u},
- {0x88u, 0x09u},
- {0x8Cu, 0x80u},
- {0x98u, 0x20u},
- {0x99u, 0x10u},
- {0x9Du, 0x01u},
- {0xA0u, 0x80u},
- {0xB5u, 0x01u},
+ {0xD8u, 0x03u},
+ {0xE2u, 0x08u},
+ {0x00u, 0x01u},
+ {0x07u, 0x40u},
+ {0x08u, 0x01u},
+ {0x0Eu, 0x80u},
+ {0x51u, 0x02u},
+ {0x56u, 0x20u},
+ {0x58u, 0x04u},
+ {0x65u, 0x01u},
+ {0x84u, 0x10u},
+ {0x85u, 0x02u},
+ {0x88u, 0x44u},
+ {0x8Cu, 0x01u},
+ {0x8Du, 0x20u},
+ {0x92u, 0x01u},
+ {0x98u, 0x40u},
+ {0x9Bu, 0x02u},
+ {0xA1u, 0x20u},
+ {0xACu, 0x40u},
{0xC0u, 0x0Cu},
{0xC2u, 0x0Cu},
- {0xD4u, 0x04u},
- {0xD6u, 0x05u},
+ {0xD4u, 0x03u},
+ {0xD6u, 0x02u},
{0xD8u, 0x01u},
- {0xE0u, 0x01u},
- {0xE4u, 0x04u},
- {0xE6u, 0x02u},
- {0xEEu, 0x02u},
- {0x57u, 0x08u},
- {0x83u, 0x08u},
- {0x87u, 0x10u},
- {0x8Fu, 0x04u},
- {0x92u, 0x40u},
- {0x94u, 0x10u},
- {0xA8u, 0x10u},
- {0xA9u, 0x10u},
- {0xADu, 0x02u},
- {0xB4u, 0x04u},
- {0xB5u, 0x04u},
+ {0xE2u, 0x01u},
+ {0xE4u, 0x01u},
+ {0xE6u, 0x0Au},
+ {0x57u, 0x80u},
+ {0x89u, 0x40u},
+ {0x8Eu, 0x20u},
+ {0x92u, 0x01u},
+ {0x9Bu, 0x02u},
+ {0x9Eu, 0x20u},
+ {0xA2u, 0x40u},
+ {0xA4u, 0x10u},
+ {0xA9u, 0x01u},
+ {0xABu, 0x40u},
+ {0xACu, 0x01u},
{0xD4u, 0x02u},
- {0xE2u, 0x02u},
- {0xE8u, 0x08u},
- {0xEEu, 0x02u},
- {0x0Au, 0x08u},
- {0x0Bu, 0x10u},
- {0x0Fu, 0x88u},
- {0x83u, 0x40u},
- {0x92u, 0x40u},
- {0x94u, 0x10u},
- {0x96u, 0x08u},
- {0x97u, 0x10u},
- {0xA0u, 0x10u},
- {0xA7u, 0x04u},
- {0xACu, 0x10u},
- {0xB2u, 0x04u},
+ {0xE2u, 0x01u},
+ {0xE4u, 0x02u},
+ {0x08u, 0x01u},
+ {0x0Bu, 0x02u},
+ {0x0Cu, 0x08u},
+ {0x0Fu, 0x02u},
+ {0x80u, 0x08u},
+ {0x87u, 0x02u},
+ {0x90u, 0x08u},
+ {0x92u, 0x01u},
+ {0x97u, 0x02u},
+ {0x9Bu, 0x02u},
+ {0x9Cu, 0x01u},
+ {0x9Du, 0x40u},
+ {0xA2u, 0x40u},
+ {0xA4u, 0x10u},
+ {0xA8u, 0x04u},
+ {0xABu, 0x80u},
+ {0xB0u, 0x01u},
+ {0xB7u, 0x01u},
{0xC2u, 0x0Fu},
- {0xEAu, 0x01u},
- {0x86u, 0x01u},
- {0x92u, 0x80u},
- {0x95u, 0x04u},
- {0x96u, 0x01u},
- {0xA3u, 0x20u},
- {0xA7u, 0x08u},
- {0xAAu, 0x40u},
+ {0xEAu, 0x02u},
+ {0xEEu, 0x04u},
+ {0x84u, 0x02u},
+ {0x9Cu, 0x02u},
+ {0xAFu, 0x80u},
{0xE2u, 0x10u},
- {0xEEu, 0x80u},
- {0x06u, 0x40u},
- {0x57u, 0x20u},
- {0x5Au, 0x80u},
- {0x85u, 0x04u},
- {0x86u, 0x40u},
- {0x92u, 0x80u},
- {0x95u, 0x04u},
- {0xA3u, 0x20u},
- {0xAFu, 0x08u},
+ {0xEEu, 0x10u},
+ {0x06u, 0x20u},
+ {0x50u, 0x02u},
+ {0x56u, 0x80u},
+ {0x84u, 0x02u},
+ {0x8Au, 0x20u},
+ {0x9Au, 0x80u},
+ {0x9Cu, 0x02u},
+ {0xA0u, 0x02u},
+ {0xB2u, 0x80u},
{0xC0u, 0x20u},
{0xD4u, 0xC0u},
- {0xE0u, 0x10u},
{0xE6u, 0x40u},
- {0xEEu, 0x40u},
- {0x94u, 0x50u},
- {0x99u, 0x20u},
- {0xA0u, 0x10u},
- {0xA8u, 0x40u},
- {0xAAu, 0x40u},
- {0xB1u, 0x20u},
- {0xE8u, 0x04u},
- {0x00u, 0x40u},
- {0x04u, 0x10u},
- {0x54u, 0x10u},
- {0x5Du, 0x20u},
- {0x94u, 0x50u},
- {0x99u, 0x20u},
- {0xA0u, 0x10u},
+ {0x90u, 0x08u},
+ {0x9Du, 0x40u},
+ {0xA2u, 0x40u},
+ {0xA4u, 0x10u},
+ {0xAFu, 0x01u},
+ {0xB2u, 0x01u},
+ {0xEEu, 0x01u},
+ {0x00u, 0x20u},
+ {0x05u, 0x40u},
+ {0x50u, 0x04u},
+ {0x5Au, 0x40u},
+ {0x8Eu, 0x40u},
+ {0x90u, 0x08u},
+ {0x9Du, 0x40u},
+ {0xA4u, 0x10u},
+ {0xAEu, 0x40u},
{0xC0u, 0x03u},
- {0xD4u, 0x02u},
- {0xD6u, 0x04u},
+ {0xD4u, 0x05u},
+ {0xE4u, 0x02u},
{0x10u, 0x03u},
{0x11u, 0x01u},
{0x1Cu, 0x03u},
{0x1Du, 0x01u},
{0x00u, 0xFDu},
- {0x01u, 0xAFu},
- {0x02u, 0x0Au},
+ {0x01u, 0xBFu},
+ {0x02u, 0x2Au},
{0x10u, 0x55u},
};
{(void CYFAR *)(CYREG_TMR0_CFG0), 12u},
{(void CYFAR *)(CYREG_PRT1_DR), 16u},
{(void CYFAR *)(CYDEV_UCFG_B0_P0_U0_BASE), 4096u},
- {(void CYFAR *)(CYDEV_UCFG_B1_P2_U0_BASE), 2048u},
+ {(void CYFAR *)(CYDEV_UCFG_B1_P2_U0_BASE), 1152u},
+ {(void CYFAR *)(CYDEV_UCFG_B1_P4_ROUTE_BASE), 768u},
{(void CYFAR *)(CYDEV_UCFG_DSI0_BASE), 2560u},
{(void CYFAR *)(CYDEV_UCFG_DSI12_BASE), 512u},
{(void CYFAR *)(CYREG_BCTL1_MDCLK_EN), 16u},
};
+ /* UDB_0_1_0_CONFIG Address: CYDEV_UCFG_B1_P4_U1_BASE Size (bytes): 128 */
+ static const uint8 CYCODE BS_UDB_0_1_0_CONFIG_VAL[] = {
+ 0x10u, 0x00u, 0x00u, 0x00u, 0x07u, 0x13u, 0x18u, 0x20u, 0x22u, 0x00u, 0x08u, 0x0Eu, 0x08u, 0x11u, 0x21u, 0x44u,
+ 0x00u, 0x00u, 0x80u, 0x00u, 0x01u, 0x29u, 0x00u, 0x10u, 0x04u, 0x6Eu, 0x00u, 0x00u, 0xC1u, 0x00u, 0x00u, 0x00u,
+ 0xC1u, 0x00u, 0x00u, 0x00u, 0xC1u, 0x00u, 0x00u, 0x00u, 0xC0u, 0x00u, 0x00u, 0x00u, 0x01u, 0x00u, 0xC0u, 0x00u,
+ 0x00u, 0x00u, 0x80u, 0x0Eu, 0x3Fu, 0x70u, 0x40u, 0x01u, 0x20u, 0x20u, 0x00u, 0x00u, 0x00u, 0x00u, 0x54u, 0x44u,
+ 0x56u, 0x02u, 0x10u, 0x00u, 0x03u, 0xBEu, 0xFDu, 0x0Cu, 0x1Fu, 0xFFu, 0xFFu, 0xFFu, 0x22u, 0x00u, 0xF0u, 0x08u,
+ 0x04u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x20u, 0x04u, 0x04u, 0x04u, 0x04u, 0x00u, 0x00u, 0x00u, 0x01u,
+ 0x00u, 0x00u, 0xC0u, 0x00u, 0x40u, 0x01u, 0x10u, 0x11u, 0xC0u, 0x01u, 0x00u, 0x11u, 0x40u, 0x01u, 0x40u, 0x01u,
+ 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u};
+
/* UCFG_BCTL0 Address: CYREG_BCTL0_MDCLK_EN Size (bytes): 16 */
static const uint8 CYCODE BS_UCFG_BCTL0_VAL[] = {
- 0x03u, 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x01u, 0x02u, 0x01u, 0x03u, 0x01u, 0x02u, 0x01u};
+ 0x03u, 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x01u, 0x02u, 0x01u, 0x03u, 0x01u, 0x03u, 0x01u};
static const cfg_memcpy_t CYCODE cfg_memcpy_list [] = {
/* dest, src, size */
+ {(void CYFAR *)(CYDEV_UCFG_B1_P4_U1_BASE), BS_UDB_0_1_0_CONFIG_VAL, 128u},
{(void CYFAR *)(CYREG_BCTL0_MDCLK_EN), BS_UCFG_BCTL0_VAL, 16u},
};
/* USBFS_ep_1 */
.set USBFS_ep_1__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
.set USBFS_ep_1__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
-.set USBFS_ep_1__INTC_MASK, 0x40
-.set USBFS_ep_1__INTC_NUMBER, 6
+.set USBFS_ep_1__INTC_MASK, 0x80
+.set USBFS_ep_1__INTC_NUMBER, 7
.set USBFS_ep_1__INTC_PRIOR_NUM, 7
-.set USBFS_ep_1__INTC_PRIOR_REG, CYREG_NVIC_PRI_6
+.set USBFS_ep_1__INTC_PRIOR_REG, CYREG_NVIC_PRI_7
.set USBFS_ep_1__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
.set USBFS_ep_1__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
/* USBFS_ep_2 */
.set USBFS_ep_2__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
.set USBFS_ep_2__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
-.set USBFS_ep_2__INTC_MASK, 0x80
-.set USBFS_ep_2__INTC_NUMBER, 7
+.set USBFS_ep_2__INTC_MASK, 0x100
+.set USBFS_ep_2__INTC_NUMBER, 8
.set USBFS_ep_2__INTC_PRIOR_NUM, 7
-.set USBFS_ep_2__INTC_PRIOR_REG, CYREG_NVIC_PRI_7
+.set USBFS_ep_2__INTC_PRIOR_REG, CYREG_NVIC_PRI_8
.set USBFS_ep_2__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
.set USBFS_ep_2__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
/* USBFS_ep_3 */
.set USBFS_ep_3__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
.set USBFS_ep_3__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
-.set USBFS_ep_3__INTC_MASK, 0x100
-.set USBFS_ep_3__INTC_NUMBER, 8
+.set USBFS_ep_3__INTC_MASK, 0x200
+.set USBFS_ep_3__INTC_NUMBER, 9
.set USBFS_ep_3__INTC_PRIOR_NUM, 7
-.set USBFS_ep_3__INTC_PRIOR_REG, CYREG_NVIC_PRI_8
+.set USBFS_ep_3__INTC_PRIOR_REG, CYREG_NVIC_PRI_9
.set USBFS_ep_3__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
.set USBFS_ep_3__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
/* USBFS_ep_4 */
.set USBFS_ep_4__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
.set USBFS_ep_4__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
-.set USBFS_ep_4__INTC_MASK, 0x200
-.set USBFS_ep_4__INTC_NUMBER, 9
+.set USBFS_ep_4__INTC_MASK, 0x400
+.set USBFS_ep_4__INTC_NUMBER, 10
.set USBFS_ep_4__INTC_PRIOR_NUM, 7
-.set USBFS_ep_4__INTC_PRIOR_REG, CYREG_NVIC_PRI_9
+.set USBFS_ep_4__INTC_PRIOR_REG, CYREG_NVIC_PRI_10
.set USBFS_ep_4__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
.set USBFS_ep_4__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
.set EXTLED__SLW, CYREG_PRT0_SLW
/* SDCard_BSPIM */
-.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB10_11_ACTL
-.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB10_11_CTL
-.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB10_11_CTL
-.set SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB10_11_CTL
-.set SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB10_11_CTL
-.set SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B1_UDB10_11_MSK
-.set SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB10_11_MSK
-.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB10_11_MSK
-.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB10_11_MSK
-.set SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B1_UDB10_ACTL
-.set SDCard_BSPIM_BitCounter__CONTROL_REG, CYREG_B1_UDB10_CTL
-.set SDCard_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B1_UDB10_ST_CTL
-.set SDCard_BSPIM_BitCounter__COUNT_REG, CYREG_B1_UDB10_CTL
-.set SDCard_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B1_UDB10_ST_CTL
-.set SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB10_MSK_ACTL
-.set SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB10_MSK_ACTL
-.set SDCard_BSPIM_BitCounter__PERIOD_REG, CYREG_B1_UDB10_MSK
-.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB10_11_ACTL
-.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B1_UDB10_11_ST
-.set SDCard_BSPIM_BitCounter_ST__MASK_REG, CYREG_B1_UDB10_MSK
-.set SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B1_UDB10_MSK_ACTL
-.set SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B1_UDB10_MSK_ACTL
-.set SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B1_UDB10_ACTL
-.set SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B1_UDB10_ST_CTL
-.set SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B1_UDB10_ST_CTL
-.set SDCard_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B1_UDB10_ST
+.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB09_10_ACTL
+.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB09_10_CTL
+.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB09_10_CTL
+.set SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB09_10_CTL
+.set SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB09_10_CTL
+.set SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B1_UDB09_10_MSK
+.set SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB09_10_MSK
+.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB09_10_MSK
+.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB09_10_MSK
+.set SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B1_UDB09_ACTL
+.set SDCard_BSPIM_BitCounter__CONTROL_REG, CYREG_B1_UDB09_CTL
+.set SDCard_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B1_UDB09_ST_CTL
+.set SDCard_BSPIM_BitCounter__COUNT_REG, CYREG_B1_UDB09_CTL
+.set SDCard_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B1_UDB09_ST_CTL
+.set SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB09_MSK_ACTL
+.set SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB09_MSK_ACTL
+.set SDCard_BSPIM_BitCounter__PERIOD_REG, CYREG_B1_UDB09_MSK
+.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB09_10_ACTL
+.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B1_UDB09_10_ST
+.set SDCard_BSPIM_BitCounter_ST__MASK_REG, CYREG_B1_UDB09_MSK
+.set SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B1_UDB09_MSK_ACTL
+.set SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B1_UDB09_MSK_ACTL
+.set SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B1_UDB09_ACTL
+.set SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B1_UDB09_ST_CTL
+.set SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B1_UDB09_ST_CTL
+.set SDCard_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B1_UDB09_ST
+.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB09_10_ACTL
+.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB09_10_ST
.set SDCard_BSPIM_RxStsReg__4__MASK, 0x10
.set SDCard_BSPIM_RxStsReg__4__POS, 4
.set SDCard_BSPIM_RxStsReg__5__MASK, 0x20
.set SDCard_BSPIM_RxStsReg__6__MASK, 0x40
.set SDCard_BSPIM_RxStsReg__6__POS, 6
.set SDCard_BSPIM_RxStsReg__MASK, 0x70
-.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B1_UDB11_MSK
-.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB11_ACTL
-.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B1_UDB11_ST
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG, CYREG_B1_UDB08_09_A0
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG, CYREG_B1_UDB08_09_A1
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG, CYREG_B1_UDB08_09_D0
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG, CYREG_B1_UDB08_09_D1
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG, CYREG_B1_UDB08_09_ACTL
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG, CYREG_B1_UDB08_09_F0
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG, CYREG_B1_UDB08_09_F1
-.set SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG, CYREG_B1_UDB08_A0_A1
-.set SDCard_BSPIM_sR8_Dp_u0__A0_REG, CYREG_B1_UDB08_A0
-.set SDCard_BSPIM_sR8_Dp_u0__A1_REG, CYREG_B1_UDB08_A1
-.set SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG, CYREG_B1_UDB08_D0_D1
-.set SDCard_BSPIM_sR8_Dp_u0__D0_REG, CYREG_B1_UDB08_D0
-.set SDCard_BSPIM_sR8_Dp_u0__D1_REG, CYREG_B1_UDB08_D1
-.set SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG, CYREG_B1_UDB08_ACTL
-.set SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG, CYREG_B1_UDB08_F0_F1
-.set SDCard_BSPIM_sR8_Dp_u0__F0_REG, CYREG_B1_UDB08_F0
-.set SDCard_BSPIM_sR8_Dp_u0__F1_REG, CYREG_B1_UDB08_F1
+.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B0_UDB09_MSK
+.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB09_ACTL
+.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B0_UDB09_ST
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG, CYREG_B1_UDB09_10_A0
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG, CYREG_B1_UDB09_10_A1
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG, CYREG_B1_UDB09_10_D0
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG, CYREG_B1_UDB09_10_D1
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG, CYREG_B1_UDB09_10_ACTL
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG, CYREG_B1_UDB09_10_F0
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG, CYREG_B1_UDB09_10_F1
+.set SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG, CYREG_B1_UDB09_A0_A1
+.set SDCard_BSPIM_sR8_Dp_u0__A0_REG, CYREG_B1_UDB09_A0
+.set SDCard_BSPIM_sR8_Dp_u0__A1_REG, CYREG_B1_UDB09_A1
+.set SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG, CYREG_B1_UDB09_D0_D1
+.set SDCard_BSPIM_sR8_Dp_u0__D0_REG, CYREG_B1_UDB09_D0
+.set SDCard_BSPIM_sR8_Dp_u0__D1_REG, CYREG_B1_UDB09_D1
+.set SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG, CYREG_B1_UDB09_ACTL
+.set SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG, CYREG_B1_UDB09_F0_F1
+.set SDCard_BSPIM_sR8_Dp_u0__F0_REG, CYREG_B1_UDB09_F0
+.set SDCard_BSPIM_sR8_Dp_u0__F1_REG, CYREG_B1_UDB09_F1
+.set SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG, CYREG_B1_UDB09_MSK_ACTL
+.set SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG, CYREG_B1_UDB09_MSK_ACTL
.set SDCard_BSPIM_TxStsReg__0__MASK, 0x01
.set SDCard_BSPIM_TxStsReg__0__POS, 0
.set SDCard_BSPIM_TxStsReg__1__MASK, 0x02
.set SDCard_BSPIM_TxStsReg__1__POS, 1
-.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB08_09_ACTL
-.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB08_09_ST
+.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB10_11_ACTL
+.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB10_11_ST
.set SDCard_BSPIM_TxStsReg__2__MASK, 0x04
.set SDCard_BSPIM_TxStsReg__2__POS, 2
.set SDCard_BSPIM_TxStsReg__3__MASK, 0x08
.set SDCard_BSPIM_TxStsReg__4__MASK, 0x10
.set SDCard_BSPIM_TxStsReg__4__POS, 4
.set SDCard_BSPIM_TxStsReg__MASK, 0x1F
-.set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B1_UDB08_MSK
-.set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB08_ACTL
-.set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B1_UDB08_ST
+.set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B1_UDB10_MSK
+.set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB10_ACTL
+.set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B1_UDB10_ST
/* SD_SCK */
.set SD_SCK__0__MASK, 0x04
.set SCSI_Out_Bits_Sync_ctrl_reg__0__POS, 0
.set SCSI_Out_Bits_Sync_ctrl_reg__1__MASK, 0x02
.set SCSI_Out_Bits_Sync_ctrl_reg__1__POS, 1
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB08_09_ACTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB08_09_CTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB08_09_CTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB08_09_CTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB08_09_CTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB08_09_MSK
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB08_09_MSK
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB08_09_MSK
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB08_09_MSK
.set SCSI_Out_Bits_Sync_ctrl_reg__2__MASK, 0x04
.set SCSI_Out_Bits_Sync_ctrl_reg__2__POS, 2
.set SCSI_Out_Bits_Sync_ctrl_reg__3__MASK, 0x08
.set SCSI_Out_Bits_Sync_ctrl_reg__6__POS, 6
.set SCSI_Out_Bits_Sync_ctrl_reg__7__MASK, 0x80
.set SCSI_Out_Bits_Sync_ctrl_reg__7__POS, 7
-.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB15_ACTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB15_CTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB15_ST_CTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB15_CTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB15_ST_CTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB08_ACTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB08_CTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB08_ST_CTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB08_CTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB08_ST_CTL
.set SCSI_Out_Bits_Sync_ctrl_reg__MASK, 0xFF
-.set SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB15_MSK_ACTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB15_MSK_ACTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB15_MSK
+.set SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB08_MSK_ACTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB08_MSK_ACTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB08_MSK
/* SCSI_Out_Ctl */
.set SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK, 0x01
.set SCSI_Out_Ctl_Sync_ctrl_reg__0__POS, 0
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB14_15_ACTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB14_15_CTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB14_15_CTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB14_15_CTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB14_15_CTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB14_15_MSK
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB14_15_MSK
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB14_15_MSK
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB14_15_MSK
-.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB14_ACTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB14_CTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB14_ST_CTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB14_CTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB14_ST_CTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB00_01_ACTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB00_01_CTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB00_01_CTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB00_01_CTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB00_01_CTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB00_01_MSK
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB00_01_MSK
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB00_01_MSK
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB00_01_MSK
+.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB00_ACTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB00_CTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB00_ST_CTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB00_CTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB00_ST_CTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK, 0x01
-.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB14_MSK_ACTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB14_MSK_ACTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB14_MSK
+.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB00_MSK_ACTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB00_MSK_ACTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB00_MSK
/* SCSI_Out_DBx */
.set SCSI_Out_DBx__0__AG, CYREG_PRT5_AG
/* SD_RX_DMA_COMPLETE */
.set SD_RX_DMA_COMPLETE__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
.set SD_RX_DMA_COMPLETE__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
-.set SD_RX_DMA_COMPLETE__INTC_MASK, 0x10
-.set SD_RX_DMA_COMPLETE__INTC_NUMBER, 4
+.set SD_RX_DMA_COMPLETE__INTC_MASK, 0x20
+.set SD_RX_DMA_COMPLETE__INTC_NUMBER, 5
.set SD_RX_DMA_COMPLETE__INTC_PRIOR_NUM, 7
-.set SD_RX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_4
+.set SD_RX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_5
.set SD_RX_DMA_COMPLETE__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
.set SD_RX_DMA_COMPLETE__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
/* SD_TX_DMA_COMPLETE */
.set SD_TX_DMA_COMPLETE__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
.set SD_TX_DMA_COMPLETE__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
-.set SD_TX_DMA_COMPLETE__INTC_MASK, 0x20
-.set SD_TX_DMA_COMPLETE__INTC_NUMBER, 5
+.set SD_TX_DMA_COMPLETE__INTC_MASK, 0x40
+.set SD_TX_DMA_COMPLETE__INTC_NUMBER, 6
.set SD_TX_DMA_COMPLETE__INTC_PRIOR_NUM, 7
-.set SD_TX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_5
+.set SD_TX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_6
.set SD_TX_DMA_COMPLETE__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
.set SD_TX_DMA_COMPLETE__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
.set scsiTarget_StatusReg__0__POS, 0
.set scsiTarget_StatusReg__1__MASK, 0x02
.set scsiTarget_StatusReg__1__POS, 1
-.set scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB00_01_ACTL
-.set scsiTarget_StatusReg__16BIT_STATUS_REG, CYREG_B0_UDB00_01_ST
.set scsiTarget_StatusReg__2__MASK, 0x04
.set scsiTarget_StatusReg__2__POS, 2
.set scsiTarget_StatusReg__3__MASK, 0x08
.set scsiTarget_StatusReg__4__MASK, 0x10
.set scsiTarget_StatusReg__4__POS, 4
.set scsiTarget_StatusReg__MASK, 0x1F
-.set scsiTarget_StatusReg__MASK_REG, CYREG_B0_UDB00_MSK
-.set scsiTarget_StatusReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB00_ACTL
-.set scsiTarget_StatusReg__STATUS_REG, CYREG_B0_UDB00_ST
+.set scsiTarget_StatusReg__MASK_REG, CYREG_B0_UDB15_MSK
+.set scsiTarget_StatusReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB15_ACTL
+.set scsiTarget_StatusReg__STATUS_REG, CYREG_B0_UDB15_ST
/* Debug_Timer_Interrupt */
.set Debug_Timer_Interrupt__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
/* SCSI_TX_DMA_COMPLETE */
.set SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
.set SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
-.set SCSI_TX_DMA_COMPLETE__INTC_MASK, 0x08
-.set SCSI_TX_DMA_COMPLETE__INTC_NUMBER, 3
+.set SCSI_TX_DMA_COMPLETE__INTC_MASK, 0x10
+.set SCSI_TX_DMA_COMPLETE__INTC_NUMBER, 4
.set SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM, 7
-.set SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_3
+.set SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_4
.set SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
.set SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
.set SCSI_RST_ISR__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
.set SCSI_RST_ISR__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
+/* SCSI_SEL_ISR */
+.set SCSI_SEL_ISR__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
+.set SCSI_SEL_ISR__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
+.set SCSI_SEL_ISR__INTC_MASK, 0x08
+.set SCSI_SEL_ISR__INTC_NUMBER, 3
+.set SCSI_SEL_ISR__INTC_PRIOR_NUM, 7
+.set SCSI_SEL_ISR__INTC_PRIOR_REG, CYREG_NVIC_PRI_3
+.set SCSI_SEL_ISR__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
+.set SCSI_SEL_ISR__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
+
/* SCSI_Filtered */
.set SCSI_Filtered_sts_sts_reg__0__MASK, 0x01
.set SCSI_Filtered_sts_sts_reg__0__POS, 0
.set SCSI_Filtered_sts_sts_reg__1__MASK, 0x02
.set SCSI_Filtered_sts_sts_reg__1__POS, 1
-.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB04_05_ACTL
-.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB04_05_ST
+.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB01_02_ACTL
+.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB01_02_ST
.set SCSI_Filtered_sts_sts_reg__2__MASK, 0x04
.set SCSI_Filtered_sts_sts_reg__2__POS, 2
.set SCSI_Filtered_sts_sts_reg__3__MASK, 0x08
.set SCSI_Filtered_sts_sts_reg__4__MASK, 0x10
.set SCSI_Filtered_sts_sts_reg__4__POS, 4
.set SCSI_Filtered_sts_sts_reg__MASK, 0x1F
-.set SCSI_Filtered_sts_sts_reg__MASK_REG, CYREG_B0_UDB04_MSK
-.set SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB04_ACTL
-.set SCSI_Filtered_sts_sts_reg__STATUS_REG, CYREG_B0_UDB04_ST
+.set SCSI_Filtered_sts_sts_reg__MASK_REG, CYREG_B0_UDB01_MSK
+.set SCSI_Filtered_sts_sts_reg__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB01_MSK_ACTL
+.set SCSI_Filtered_sts_sts_reg__PER_ST_AUX_CTL_REG, CYREG_B0_UDB01_MSK_ACTL
+.set SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB01_ACTL
+.set SCSI_Filtered_sts_sts_reg__STATUS_CNT_REG, CYREG_B0_UDB01_ST_CTL
+.set SCSI_Filtered_sts_sts_reg__STATUS_CONTROL_REG, CYREG_B0_UDB01_ST_CTL
+.set SCSI_Filtered_sts_sts_reg__STATUS_REG, CYREG_B0_UDB01_ST
/* SCSI_CTL_PHASE */
.set SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK, 0x01
.set SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS, 0
.set SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK, 0x02
.set SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS, 1
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB12_13_ACTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB12_13_CTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB12_13_CTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB12_13_CTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB12_13_CTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB12_13_MSK
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB12_13_MSK
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB12_13_MSK
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB12_13_MSK
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB01_02_ACTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB01_02_CTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB01_02_CTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB01_02_CTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB01_02_CTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB01_02_MSK
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB01_02_MSK
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB01_02_MSK
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB01_02_MSK
.set SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK, 0x04
.set SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS, 2
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB12_ACTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB12_CTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB12_ST_CTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB12_CTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB12_ST_CTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB01_ACTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB01_CTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB01_ST_CTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB01_CTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB01_ST_CTL
.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK, 0x07
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB12_MSK
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB01_MSK_ACTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB01_MSK_ACTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB01_MSK
/* SCSI_Parity_Error */
.set SCSI_Parity_Error_sts_sts_reg__0__MASK, 0x01
.set SCSI_Parity_Error_sts_sts_reg__0__POS, 0
-.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB03_04_ACTL
-.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB03_04_ST
+.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB04_05_ACTL
+.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB04_05_ST
.set SCSI_Parity_Error_sts_sts_reg__MASK, 0x01
-.set SCSI_Parity_Error_sts_sts_reg__MASK_REG, CYREG_B0_UDB03_MSK
-.set SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB03_ACTL
-.set SCSI_Parity_Error_sts_sts_reg__STATUS_REG, CYREG_B0_UDB03_ST
+.set SCSI_Parity_Error_sts_sts_reg__MASK_REG, CYREG_B0_UDB04_MSK
+.set SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB04_ACTL
+.set SCSI_Parity_Error_sts_sts_reg__STATUS_REG, CYREG_B0_UDB04_ST
/* Miscellaneous */
.set BCLK__BUS_CLK__HZ, 50000000
.set CYDEV_ECC_ENABLE, 0
.set CYDEV_HEAP_SIZE, 0x0400
.set CYDEV_INSTRUCT_CACHE_ENABLED, 1
-.set CYDEV_INTR_RISING, 0x0000003E
+.set CYDEV_INTR_RISING, 0x0000007E
.set CYDEV_PROJ_TYPE, 2
.set CYDEV_PROJ_TYPE_BOOTLOADER, 1
.set CYDEV_PROJ_TYPE_LOADABLE, 2
/* USBFS_ep_1 */
USBFS_ep_1__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
USBFS_ep_1__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-USBFS_ep_1__INTC_MASK EQU 0x40
-USBFS_ep_1__INTC_NUMBER EQU 6
+USBFS_ep_1__INTC_MASK EQU 0x80
+USBFS_ep_1__INTC_NUMBER EQU 7
USBFS_ep_1__INTC_PRIOR_NUM EQU 7
-USBFS_ep_1__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_6
+USBFS_ep_1__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_7
USBFS_ep_1__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
USBFS_ep_1__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
/* USBFS_ep_2 */
USBFS_ep_2__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
USBFS_ep_2__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-USBFS_ep_2__INTC_MASK EQU 0x80
-USBFS_ep_2__INTC_NUMBER EQU 7
+USBFS_ep_2__INTC_MASK EQU 0x100
+USBFS_ep_2__INTC_NUMBER EQU 8
USBFS_ep_2__INTC_PRIOR_NUM EQU 7
-USBFS_ep_2__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_7
+USBFS_ep_2__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_8
USBFS_ep_2__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
USBFS_ep_2__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
/* USBFS_ep_3 */
USBFS_ep_3__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
USBFS_ep_3__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-USBFS_ep_3__INTC_MASK EQU 0x100
-USBFS_ep_3__INTC_NUMBER EQU 8
+USBFS_ep_3__INTC_MASK EQU 0x200
+USBFS_ep_3__INTC_NUMBER EQU 9
USBFS_ep_3__INTC_PRIOR_NUM EQU 7
-USBFS_ep_3__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_8
+USBFS_ep_3__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_9
USBFS_ep_3__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
USBFS_ep_3__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
/* USBFS_ep_4 */
USBFS_ep_4__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
USBFS_ep_4__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-USBFS_ep_4__INTC_MASK EQU 0x200
-USBFS_ep_4__INTC_NUMBER EQU 9
+USBFS_ep_4__INTC_MASK EQU 0x400
+USBFS_ep_4__INTC_NUMBER EQU 10
USBFS_ep_4__INTC_PRIOR_NUM EQU 7
-USBFS_ep_4__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_9
+USBFS_ep_4__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_10
USBFS_ep_4__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
USBFS_ep_4__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
EXTLED__SLW EQU CYREG_PRT0_SLW
/* SDCard_BSPIM */
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB10_11_ACTL
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB10_11_CTL
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB10_11_CTL
-SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB10_11_CTL
-SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB10_11_CTL
-SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB10_11_MSK
-SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB10_11_MSK
-SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB10_11_MSK
-SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB10_11_MSK
-SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB10_ACTL
-SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB10_CTL
-SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB10_ST_CTL
-SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB10_CTL
-SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB10_ST_CTL
-SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB10_MSK_ACTL
-SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB10_MSK_ACTL
-SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB10_MSK
-SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB10_11_ACTL
-SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB10_11_ST
-SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB10_MSK
-SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB10_MSK_ACTL
-SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB10_MSK_ACTL
-SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB10_ACTL
-SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB10_ST_CTL
-SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB10_ST_CTL
-SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB10_ST
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB09_10_ACTL
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB09_10_CTL
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB09_10_CTL
+SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB09_10_CTL
+SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB09_10_CTL
+SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB09_10_MSK
+SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB09_10_MSK
+SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB09_10_MSK
+SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB09_10_MSK
+SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB09_ACTL
+SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB09_CTL
+SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB09_ST_CTL
+SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB09_CTL
+SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB09_ST_CTL
+SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB09_MSK_ACTL
+SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB09_MSK_ACTL
+SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB09_MSK
+SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB09_10_ACTL
+SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB09_10_ST
+SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB09_MSK
+SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB09_MSK_ACTL
+SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB09_MSK_ACTL
+SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB09_ACTL
+SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB09_ST_CTL
+SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB09_ST_CTL
+SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB09_ST
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB09_10_ACTL
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB09_10_ST
SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10
SDCard_BSPIM_RxStsReg__4__POS EQU 4
SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20
SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40
SDCard_BSPIM_RxStsReg__6__POS EQU 6
SDCard_BSPIM_RxStsReg__MASK EQU 0x70
-SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB11_MSK
-SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB11_ACTL
-SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB11_ST
-SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB08_09_A0
-SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB08_09_A1
-SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B1_UDB08_09_D0
-SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B1_UDB08_09_D1
-SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B1_UDB08_09_ACTL
-SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B1_UDB08_09_F0
-SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B1_UDB08_09_F1
-SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B1_UDB08_A0_A1
-SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B1_UDB08_A0
-SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B1_UDB08_A1
-SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B1_UDB08_D0_D1
-SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B1_UDB08_D0
-SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B1_UDB08_D1
-SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B1_UDB08_ACTL
-SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B1_UDB08_F0_F1
-SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B1_UDB08_F0
-SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B1_UDB08_F1
+SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B0_UDB09_MSK
+SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB09_ACTL
+SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B0_UDB09_ST
+SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB09_10_A0
+SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB09_10_A1
+SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B1_UDB09_10_D0
+SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B1_UDB09_10_D1
+SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B1_UDB09_10_ACTL
+SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B1_UDB09_10_F0
+SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B1_UDB09_10_F1
+SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B1_UDB09_A0_A1
+SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B1_UDB09_A0
+SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B1_UDB09_A1
+SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B1_UDB09_D0_D1
+SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B1_UDB09_D0
+SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B1_UDB09_D1
+SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B1_UDB09_ACTL
+SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B1_UDB09_F0_F1
+SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B1_UDB09_F0
+SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B1_UDB09_F1
+SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG EQU CYREG_B1_UDB09_MSK_ACTL
+SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG EQU CYREG_B1_UDB09_MSK_ACTL
SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01
SDCard_BSPIM_TxStsReg__0__POS EQU 0
SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02
SDCard_BSPIM_TxStsReg__1__POS EQU 1
-SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB08_09_ACTL
-SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB08_09_ST
+SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB10_11_ACTL
+SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB10_11_ST
SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04
SDCard_BSPIM_TxStsReg__2__POS EQU 2
SDCard_BSPIM_TxStsReg__3__MASK EQU 0x08
SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10
SDCard_BSPIM_TxStsReg__4__POS EQU 4
SDCard_BSPIM_TxStsReg__MASK EQU 0x1F
-SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB08_MSK
-SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB08_ACTL
-SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB08_ST
+SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB10_MSK
+SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB10_ACTL
+SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB10_ST
/* SD_SCK */
SD_SCK__0__MASK EQU 0x04
SCSI_Out_Bits_Sync_ctrl_reg__0__POS EQU 0
SCSI_Out_Bits_Sync_ctrl_reg__1__MASK EQU 0x02
SCSI_Out_Bits_Sync_ctrl_reg__1__POS EQU 1
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB08_09_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB08_09_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB08_09_MSK
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB08_09_MSK
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK
SCSI_Out_Bits_Sync_ctrl_reg__2__MASK EQU 0x04
SCSI_Out_Bits_Sync_ctrl_reg__2__POS EQU 2
SCSI_Out_Bits_Sync_ctrl_reg__3__MASK EQU 0x08
SCSI_Out_Bits_Sync_ctrl_reg__6__POS EQU 6
SCSI_Out_Bits_Sync_ctrl_reg__7__MASK EQU 0x80
SCSI_Out_Bits_Sync_ctrl_reg__7__POS EQU 7
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB15_ACTL
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB15_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB15_ST_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB15_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB15_ST_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB08_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB08_ST_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB08_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB08_ST_CTL
SCSI_Out_Bits_Sync_ctrl_reg__MASK EQU 0xFF
-SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB15_MSK_ACTL
-SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB15_MSK_ACTL
-SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB15_MSK
+SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL
+SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL
+SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB08_MSK
/* SCSI_Out_Ctl */
SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01
SCSI_Out_Ctl_Sync_ctrl_reg__0__POS EQU 0
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB14_15_ACTL
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB14_15_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB14_15_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB14_15_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB14_15_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB14_15_MSK
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB14_15_MSK
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB14_15_MSK
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB14_15_MSK
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB14_ACTL
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB14_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB14_ST_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB14_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB14_ST_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB00_01_ACTL
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB00_01_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB00_01_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB00_01_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB00_01_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB00_01_MSK
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB00_01_MSK
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB00_01_MSK
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB00_01_MSK
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB00_ACTL
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB00_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB00_ST_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB00_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB00_ST_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__MASK EQU 0x01
-SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB14_MSK_ACTL
-SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB14_MSK_ACTL
-SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB14_MSK
+SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB00_MSK_ACTL
+SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB00_MSK_ACTL
+SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB00_MSK
/* SCSI_Out_DBx */
SCSI_Out_DBx__0__AG EQU CYREG_PRT5_AG
/* SD_RX_DMA_COMPLETE */
SD_RX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
SD_RX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-SD_RX_DMA_COMPLETE__INTC_MASK EQU 0x10
-SD_RX_DMA_COMPLETE__INTC_NUMBER EQU 4
+SD_RX_DMA_COMPLETE__INTC_MASK EQU 0x20
+SD_RX_DMA_COMPLETE__INTC_NUMBER EQU 5
SD_RX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7
-SD_RX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_4
+SD_RX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_5
SD_RX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
SD_RX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
/* SD_TX_DMA_COMPLETE */
SD_TX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
SD_TX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-SD_TX_DMA_COMPLETE__INTC_MASK EQU 0x20
-SD_TX_DMA_COMPLETE__INTC_NUMBER EQU 5
+SD_TX_DMA_COMPLETE__INTC_MASK EQU 0x40
+SD_TX_DMA_COMPLETE__INTC_NUMBER EQU 6
SD_TX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7
-SD_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_5
+SD_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_6
SD_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
SD_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
scsiTarget_StatusReg__0__POS EQU 0
scsiTarget_StatusReg__1__MASK EQU 0x02
scsiTarget_StatusReg__1__POS EQU 1
-scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB00_01_ACTL
-scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB00_01_ST
scsiTarget_StatusReg__2__MASK EQU 0x04
scsiTarget_StatusReg__2__POS EQU 2
scsiTarget_StatusReg__3__MASK EQU 0x08
scsiTarget_StatusReg__4__MASK EQU 0x10
scsiTarget_StatusReg__4__POS EQU 4
scsiTarget_StatusReg__MASK EQU 0x1F
-scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB00_MSK
-scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB00_ACTL
-scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB00_ST
+scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB15_MSK
+scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB15_ACTL
+scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB15_ST
/* Debug_Timer_Interrupt */
Debug_Timer_Interrupt__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
/* SCSI_TX_DMA_COMPLETE */
SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-SCSI_TX_DMA_COMPLETE__INTC_MASK EQU 0x08
-SCSI_TX_DMA_COMPLETE__INTC_NUMBER EQU 3
+SCSI_TX_DMA_COMPLETE__INTC_MASK EQU 0x10
+SCSI_TX_DMA_COMPLETE__INTC_NUMBER EQU 4
SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7
-SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_3
+SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_4
SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
SCSI_RST_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
SCSI_RST_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
+/* SCSI_SEL_ISR */
+SCSI_SEL_ISR__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
+SCSI_SEL_ISR__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
+SCSI_SEL_ISR__INTC_MASK EQU 0x08
+SCSI_SEL_ISR__INTC_NUMBER EQU 3
+SCSI_SEL_ISR__INTC_PRIOR_NUM EQU 7
+SCSI_SEL_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_3
+SCSI_SEL_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
+SCSI_SEL_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
+
/* SCSI_Filtered */
SCSI_Filtered_sts_sts_reg__0__MASK EQU 0x01
SCSI_Filtered_sts_sts_reg__0__POS EQU 0
SCSI_Filtered_sts_sts_reg__1__MASK EQU 0x02
SCSI_Filtered_sts_sts_reg__1__POS EQU 1
-SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL
-SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB04_05_ST
+SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB01_02_ACTL
+SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB01_02_ST
SCSI_Filtered_sts_sts_reg__2__MASK EQU 0x04
SCSI_Filtered_sts_sts_reg__2__POS EQU 2
SCSI_Filtered_sts_sts_reg__3__MASK EQU 0x08
SCSI_Filtered_sts_sts_reg__4__MASK EQU 0x10
SCSI_Filtered_sts_sts_reg__4__POS EQU 4
SCSI_Filtered_sts_sts_reg__MASK EQU 0x1F
-SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB04_MSK
-SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL
-SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB04_ST
+SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB01_MSK
+SCSI_Filtered_sts_sts_reg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL
+SCSI_Filtered_sts_sts_reg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL
+SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB01_ACTL
+SCSI_Filtered_sts_sts_reg__STATUS_CNT_REG EQU CYREG_B0_UDB01_ST_CTL
+SCSI_Filtered_sts_sts_reg__STATUS_CONTROL_REG EQU CYREG_B0_UDB01_ST_CTL
+SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB01_ST
/* SCSI_CTL_PHASE */
SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01
SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS EQU 0
SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK EQU 0x02
SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS EQU 1
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB12_13_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB12_13_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB12_13_MSK
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB12_13_MSK
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB01_02_ACTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB01_02_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB01_02_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB01_02_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB01_02_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB01_02_MSK
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB01_02_MSK
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB01_02_MSK
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB01_02_MSK
SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK EQU 0x04
SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS EQU 2
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB12_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB12_ST_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB12_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB12_ST_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB01_ACTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB01_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB01_ST_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB01_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB01_ST_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__MASK EQU 0x07
-SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB12_MSK
+SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB01_MSK
/* SCSI_Parity_Error */
SCSI_Parity_Error_sts_sts_reg__0__MASK EQU 0x01
SCSI_Parity_Error_sts_sts_reg__0__POS EQU 0
-SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL
-SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB03_04_ST
+SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL
+SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB04_05_ST
SCSI_Parity_Error_sts_sts_reg__MASK EQU 0x01
-SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB03_MSK
-SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL
-SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB03_ST
+SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB04_MSK
+SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL
+SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB04_ST
/* Miscellaneous */
BCLK__BUS_CLK__HZ EQU 50000000
CYDEV_ECC_ENABLE EQU 0
CYDEV_HEAP_SIZE EQU 0x0400
CYDEV_INSTRUCT_CACHE_ENABLED EQU 1
-CYDEV_INTR_RISING EQU 0x0000003E
+CYDEV_INTR_RISING EQU 0x0000007E
CYDEV_PROJ_TYPE EQU 2
CYDEV_PROJ_TYPE_BOOTLOADER EQU 1
CYDEV_PROJ_TYPE_LOADABLE EQU 2
; USBFS_ep_1
USBFS_ep_1__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
USBFS_ep_1__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-USBFS_ep_1__INTC_MASK EQU 0x40
-USBFS_ep_1__INTC_NUMBER EQU 6
+USBFS_ep_1__INTC_MASK EQU 0x80
+USBFS_ep_1__INTC_NUMBER EQU 7
USBFS_ep_1__INTC_PRIOR_NUM EQU 7
-USBFS_ep_1__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_6
+USBFS_ep_1__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_7
USBFS_ep_1__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
USBFS_ep_1__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
; USBFS_ep_2
USBFS_ep_2__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
USBFS_ep_2__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-USBFS_ep_2__INTC_MASK EQU 0x80
-USBFS_ep_2__INTC_NUMBER EQU 7
+USBFS_ep_2__INTC_MASK EQU 0x100
+USBFS_ep_2__INTC_NUMBER EQU 8
USBFS_ep_2__INTC_PRIOR_NUM EQU 7
-USBFS_ep_2__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_7
+USBFS_ep_2__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_8
USBFS_ep_2__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
USBFS_ep_2__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
; USBFS_ep_3
USBFS_ep_3__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
USBFS_ep_3__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-USBFS_ep_3__INTC_MASK EQU 0x100
-USBFS_ep_3__INTC_NUMBER EQU 8
+USBFS_ep_3__INTC_MASK EQU 0x200
+USBFS_ep_3__INTC_NUMBER EQU 9
USBFS_ep_3__INTC_PRIOR_NUM EQU 7
-USBFS_ep_3__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_8
+USBFS_ep_3__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_9
USBFS_ep_3__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
USBFS_ep_3__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
; USBFS_ep_4
USBFS_ep_4__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
USBFS_ep_4__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-USBFS_ep_4__INTC_MASK EQU 0x200
-USBFS_ep_4__INTC_NUMBER EQU 9
+USBFS_ep_4__INTC_MASK EQU 0x400
+USBFS_ep_4__INTC_NUMBER EQU 10
USBFS_ep_4__INTC_PRIOR_NUM EQU 7
-USBFS_ep_4__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_9
+USBFS_ep_4__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_10
USBFS_ep_4__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
USBFS_ep_4__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
EXTLED__SLW EQU CYREG_PRT0_SLW
; SDCard_BSPIM
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB10_11_ACTL
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB10_11_CTL
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB10_11_CTL
-SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB10_11_CTL
-SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB10_11_CTL
-SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB10_11_MSK
-SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB10_11_MSK
-SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB10_11_MSK
-SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB10_11_MSK
-SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB10_ACTL
-SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB10_CTL
-SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB10_ST_CTL
-SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB10_CTL
-SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB10_ST_CTL
-SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB10_MSK_ACTL
-SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB10_MSK_ACTL
-SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB10_MSK
-SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB10_11_ACTL
-SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB10_11_ST
-SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB10_MSK
-SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB10_MSK_ACTL
-SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB10_MSK_ACTL
-SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB10_ACTL
-SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB10_ST_CTL
-SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB10_ST_CTL
-SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB10_ST
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB09_10_ACTL
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB09_10_CTL
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB09_10_CTL
+SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB09_10_CTL
+SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB09_10_CTL
+SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB09_10_MSK
+SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB09_10_MSK
+SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB09_10_MSK
+SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB09_10_MSK
+SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB09_ACTL
+SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB09_CTL
+SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB09_ST_CTL
+SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB09_CTL
+SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB09_ST_CTL
+SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB09_MSK_ACTL
+SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB09_MSK_ACTL
+SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB09_MSK
+SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB09_10_ACTL
+SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB09_10_ST
+SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB09_MSK
+SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB09_MSK_ACTL
+SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB09_MSK_ACTL
+SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB09_ACTL
+SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB09_ST_CTL
+SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB09_ST_CTL
+SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB09_ST
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB09_10_ACTL
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB09_10_ST
SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10
SDCard_BSPIM_RxStsReg__4__POS EQU 4
SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20
SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40
SDCard_BSPIM_RxStsReg__6__POS EQU 6
SDCard_BSPIM_RxStsReg__MASK EQU 0x70
-SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB11_MSK
-SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB11_ACTL
-SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB11_ST
-SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB08_09_A0
-SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB08_09_A1
-SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B1_UDB08_09_D0
-SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B1_UDB08_09_D1
-SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B1_UDB08_09_ACTL
-SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B1_UDB08_09_F0
-SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B1_UDB08_09_F1
-SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B1_UDB08_A0_A1
-SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B1_UDB08_A0
-SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B1_UDB08_A1
-SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B1_UDB08_D0_D1
-SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B1_UDB08_D0
-SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B1_UDB08_D1
-SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B1_UDB08_ACTL
-SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B1_UDB08_F0_F1
-SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B1_UDB08_F0
-SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B1_UDB08_F1
+SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B0_UDB09_MSK
+SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB09_ACTL
+SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B0_UDB09_ST
+SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB09_10_A0
+SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB09_10_A1
+SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B1_UDB09_10_D0
+SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B1_UDB09_10_D1
+SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B1_UDB09_10_ACTL
+SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B1_UDB09_10_F0
+SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B1_UDB09_10_F1
+SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B1_UDB09_A0_A1
+SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B1_UDB09_A0
+SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B1_UDB09_A1
+SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B1_UDB09_D0_D1
+SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B1_UDB09_D0
+SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B1_UDB09_D1
+SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B1_UDB09_ACTL
+SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B1_UDB09_F0_F1
+SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B1_UDB09_F0
+SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B1_UDB09_F1
+SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG EQU CYREG_B1_UDB09_MSK_ACTL
+SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG EQU CYREG_B1_UDB09_MSK_ACTL
SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01
SDCard_BSPIM_TxStsReg__0__POS EQU 0
SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02
SDCard_BSPIM_TxStsReg__1__POS EQU 1
-SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB08_09_ACTL
-SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB08_09_ST
+SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB10_11_ACTL
+SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB10_11_ST
SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04
SDCard_BSPIM_TxStsReg__2__POS EQU 2
SDCard_BSPIM_TxStsReg__3__MASK EQU 0x08
SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10
SDCard_BSPIM_TxStsReg__4__POS EQU 4
SDCard_BSPIM_TxStsReg__MASK EQU 0x1F
-SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB08_MSK
-SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB08_ACTL
-SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB08_ST
+SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB10_MSK
+SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB10_ACTL
+SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB10_ST
; SD_SCK
SD_SCK__0__MASK EQU 0x04
SCSI_Out_Bits_Sync_ctrl_reg__0__POS EQU 0
SCSI_Out_Bits_Sync_ctrl_reg__1__MASK EQU 0x02
SCSI_Out_Bits_Sync_ctrl_reg__1__POS EQU 1
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB08_09_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB08_09_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB08_09_MSK
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB08_09_MSK
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK
SCSI_Out_Bits_Sync_ctrl_reg__2__MASK EQU 0x04
SCSI_Out_Bits_Sync_ctrl_reg__2__POS EQU 2
SCSI_Out_Bits_Sync_ctrl_reg__3__MASK EQU 0x08
SCSI_Out_Bits_Sync_ctrl_reg__6__POS EQU 6
SCSI_Out_Bits_Sync_ctrl_reg__7__MASK EQU 0x80
SCSI_Out_Bits_Sync_ctrl_reg__7__POS EQU 7
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB15_ACTL
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB15_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB15_ST_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB15_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB15_ST_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB08_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB08_ST_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB08_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB08_ST_CTL
SCSI_Out_Bits_Sync_ctrl_reg__MASK EQU 0xFF
-SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB15_MSK_ACTL
-SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB15_MSK_ACTL
-SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB15_MSK
+SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL
+SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL
+SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB08_MSK
; SCSI_Out_Ctl
SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01
SCSI_Out_Ctl_Sync_ctrl_reg__0__POS EQU 0
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB14_15_ACTL
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB14_15_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB14_15_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB14_15_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB14_15_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB14_15_MSK
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB14_15_MSK
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB14_15_MSK
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB14_15_MSK
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB14_ACTL
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB14_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB14_ST_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB14_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB14_ST_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB00_01_ACTL
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB00_01_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB00_01_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB00_01_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB00_01_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB00_01_MSK
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB00_01_MSK
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB00_01_MSK
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB00_01_MSK
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB00_ACTL
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB00_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB00_ST_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB00_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB00_ST_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__MASK EQU 0x01
-SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB14_MSK_ACTL
-SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB14_MSK_ACTL
-SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB14_MSK
+SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB00_MSK_ACTL
+SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB00_MSK_ACTL
+SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB00_MSK
; SCSI_Out_DBx
SCSI_Out_DBx__0__AG EQU CYREG_PRT5_AG
; SD_RX_DMA_COMPLETE
SD_RX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
SD_RX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-SD_RX_DMA_COMPLETE__INTC_MASK EQU 0x10
-SD_RX_DMA_COMPLETE__INTC_NUMBER EQU 4
+SD_RX_DMA_COMPLETE__INTC_MASK EQU 0x20
+SD_RX_DMA_COMPLETE__INTC_NUMBER EQU 5
SD_RX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7
-SD_RX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_4
+SD_RX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_5
SD_RX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
SD_RX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
; SD_TX_DMA_COMPLETE
SD_TX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
SD_TX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-SD_TX_DMA_COMPLETE__INTC_MASK EQU 0x20
-SD_TX_DMA_COMPLETE__INTC_NUMBER EQU 5
+SD_TX_DMA_COMPLETE__INTC_MASK EQU 0x40
+SD_TX_DMA_COMPLETE__INTC_NUMBER EQU 6
SD_TX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7
-SD_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_5
+SD_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_6
SD_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
SD_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
scsiTarget_StatusReg__0__POS EQU 0
scsiTarget_StatusReg__1__MASK EQU 0x02
scsiTarget_StatusReg__1__POS EQU 1
-scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB00_01_ACTL
-scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB00_01_ST
scsiTarget_StatusReg__2__MASK EQU 0x04
scsiTarget_StatusReg__2__POS EQU 2
scsiTarget_StatusReg__3__MASK EQU 0x08
scsiTarget_StatusReg__4__MASK EQU 0x10
scsiTarget_StatusReg__4__POS EQU 4
scsiTarget_StatusReg__MASK EQU 0x1F
-scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB00_MSK
-scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB00_ACTL
-scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB00_ST
+scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB15_MSK
+scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB15_ACTL
+scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB15_ST
; Debug_Timer_Interrupt
Debug_Timer_Interrupt__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
; SCSI_TX_DMA_COMPLETE
SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-SCSI_TX_DMA_COMPLETE__INTC_MASK EQU 0x08
-SCSI_TX_DMA_COMPLETE__INTC_NUMBER EQU 3
+SCSI_TX_DMA_COMPLETE__INTC_MASK EQU 0x10
+SCSI_TX_DMA_COMPLETE__INTC_NUMBER EQU 4
SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7
-SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_3
+SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_4
SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
SCSI_RST_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
SCSI_RST_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
+; SCSI_SEL_ISR
+SCSI_SEL_ISR__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
+SCSI_SEL_ISR__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
+SCSI_SEL_ISR__INTC_MASK EQU 0x08
+SCSI_SEL_ISR__INTC_NUMBER EQU 3
+SCSI_SEL_ISR__INTC_PRIOR_NUM EQU 7
+SCSI_SEL_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_3
+SCSI_SEL_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
+SCSI_SEL_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
+
; SCSI_Filtered
SCSI_Filtered_sts_sts_reg__0__MASK EQU 0x01
SCSI_Filtered_sts_sts_reg__0__POS EQU 0
SCSI_Filtered_sts_sts_reg__1__MASK EQU 0x02
SCSI_Filtered_sts_sts_reg__1__POS EQU 1
-SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL
-SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB04_05_ST
+SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB01_02_ACTL
+SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB01_02_ST
SCSI_Filtered_sts_sts_reg__2__MASK EQU 0x04
SCSI_Filtered_sts_sts_reg__2__POS EQU 2
SCSI_Filtered_sts_sts_reg__3__MASK EQU 0x08
SCSI_Filtered_sts_sts_reg__4__MASK EQU 0x10
SCSI_Filtered_sts_sts_reg__4__POS EQU 4
SCSI_Filtered_sts_sts_reg__MASK EQU 0x1F
-SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB04_MSK
-SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL
-SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB04_ST
+SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB01_MSK
+SCSI_Filtered_sts_sts_reg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL
+SCSI_Filtered_sts_sts_reg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL
+SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB01_ACTL
+SCSI_Filtered_sts_sts_reg__STATUS_CNT_REG EQU CYREG_B0_UDB01_ST_CTL
+SCSI_Filtered_sts_sts_reg__STATUS_CONTROL_REG EQU CYREG_B0_UDB01_ST_CTL
+SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB01_ST
; SCSI_CTL_PHASE
SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01
SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS EQU 0
SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK EQU 0x02
SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS EQU 1
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB12_13_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB12_13_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB12_13_MSK
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB12_13_MSK
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB01_02_ACTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB01_02_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB01_02_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB01_02_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB01_02_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB01_02_MSK
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB01_02_MSK
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB01_02_MSK
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB01_02_MSK
SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK EQU 0x04
SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS EQU 2
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB12_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB12_ST_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB12_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB12_ST_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB01_ACTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB01_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB01_ST_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB01_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB01_ST_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__MASK EQU 0x07
-SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB12_MSK
+SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB01_MSK
; SCSI_Parity_Error
SCSI_Parity_Error_sts_sts_reg__0__MASK EQU 0x01
SCSI_Parity_Error_sts_sts_reg__0__POS EQU 0
-SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL
-SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB03_04_ST
+SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL
+SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB04_05_ST
SCSI_Parity_Error_sts_sts_reg__MASK EQU 0x01
-SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB03_MSK
-SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL
-SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB03_ST
+SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB04_MSK
+SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL
+SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB04_ST
; Miscellaneous
BCLK__BUS_CLK__HZ EQU 50000000
CYDEV_ECC_ENABLE EQU 0
CYDEV_HEAP_SIZE EQU 0x0400
CYDEV_INSTRUCT_CACHE_ENABLED EQU 1
-CYDEV_INTR_RISING EQU 0x0000003E
+CYDEV_INTR_RISING EQU 0x0000007E
CYDEV_PROJ_TYPE EQU 2
CYDEV_PROJ_TYPE_BOOTLOADER EQU 1
CYDEV_PROJ_TYPE_LOADABLE EQU 2
#include <SCSI_Filtered.h>
#include <EXTLED_aliases.h>
#include <EXTLED.h>
+#include <SCSI_SEL_ISR.h>
#include <USBFS_Dm_aliases.h>
#include <USBFS_Dm.h>
#include <USBFS_Dp_aliases.h>
<?xml version="1.0" encoding="utf-8"?>
<blockRegMap version="1" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://cypress.com/xsd/cyblockregmap cyblockregmap.xsd" xmlns="http://cypress.com/xsd/cyblockregmap">
- <block name="SCSI_TX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" />
- <block name="SCSI_TX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" />
- <block name="SD_RX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="SD_RX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="SD_TX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" />
- <block name="Debug_Timer_Interrupt" BASE="0x0" SIZE="0x0" desc="" visible="true" />
- <block name="SCSI_Out_Ctl" BASE="0x0" SIZE="0x0" desc="" visible="true">
- <register name="SCSI_Out_Ctl_CONTROL_REG" address="0x4000647E" bitWidth="8" desc="" />
- </block>
- <block name="SCSI_Out_Bits" BASE="0x0" SIZE="0x0" desc="" visible="true">
- <register name="SCSI_Out_Bits_CONTROL_REG" address="0x4000647F" bitWidth="8" desc="" />
- </block>
+ <block name="SD_RX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+ <block name="SCSI_RX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+ <block name="SCSI_RX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+ <block name="SD_TX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+ <block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+ <block name="timer_clock" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="Debug_Timer" BASE="0x0" SIZE="0x0" desc="" visible="true">
<block name="VirtualMux_2" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<register name="Debug_Timer_PERIOD" address="0x40004F04" bitWidth="16" desc="TMRx.PER0 - Assigned Period" />
<register name="Debug_Timer_COUNTER" address="0x40004F06" bitWidth="16" desc="TMRx.CNT_CMP0 - Current Down Counter Value" />
</block>
- <block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
- <block name="timer_clock" BASE="0x0" SIZE="0x0" desc="" visible="true" />
- <block name="SD_TX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" />
- <block name="cy_constant_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
- <block name="Clock_2" BASE="0x0" SIZE="0x0" desc="" visible="true" />
- <block name="cydff_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
- <block name="EXTLED" BASE="0x0" SIZE="0x0" desc="" visible="true" />
- <block name="Clock_3" BASE="0x0" SIZE="0x0" desc="" visible="true" />
- <block name="Clock_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
- <block name="SCSI_RX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" />
- <block name="SCSI_RX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+ <block name="SCSI_TX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+ <block name="SCSI_TX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+ <block name="Debug_Timer_Interrupt" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="SCSI_Parity_Error" BASE="0x0" SIZE="0x0" desc="" visible="true">
- <register name="SCSI_Parity_Error_STATUS_REG" address="0x40006463" bitWidth="8" desc="" />
- <register name="SCSI_Parity_Error_MASK_REG" address="0x40006483" bitWidth="8" desc="" />
- <register name="SCSI_Parity_Error_STATUS_AUX_CTL_REG" address="0x40006493" bitWidth="8" desc="">
+ <register name="SCSI_Parity_Error_STATUS_REG" address="0x40006464" bitWidth="8" desc="" />
+ <register name="SCSI_Parity_Error_MASK_REG" address="0x40006484" bitWidth="8" desc="" />
+ <register name="SCSI_Parity_Error_STATUS_AUX_CTL_REG" address="0x40006494" bitWidth="8" desc="">
<field name="FIFO0" from="5" to="5" access="RW" resetVal="" desc="FIFO0 clear">
<value name="ENABLED" value="1" desc="Enable counter" />
<value name="DISABLED" value="0" desc="Disable counter" />
</field>
</register>
</block>
+ <block name="not_2" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+ <block name="EXTLED" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+ <block name="Clock_3" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+ <block name="SCSI_SEL_ISR" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+ <block name="cydff_2" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+ <block name="Clock_4" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+ <block name="Clock_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="GlitchFilter_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="SCSI_Filtered" BASE="0x0" SIZE="0x0" desc="" visible="true">
- <register name="SCSI_Filtered_STATUS_REG" address="0x40006464" bitWidth="8" desc="" />
- <register name="SCSI_Filtered_MASK_REG" address="0x40006484" bitWidth="8" desc="" />
- <register name="SCSI_Filtered_STATUS_AUX_CTL_REG" address="0x40006494" bitWidth="8" desc="">
+ <register name="SCSI_Filtered_STATUS_REG" address="0x40006461" bitWidth="8" desc="" />
+ <register name="SCSI_Filtered_MASK_REG" address="0x40006481" bitWidth="8" desc="" />
+ <register name="SCSI_Filtered_STATUS_AUX_CTL_REG" address="0x40006491" bitWidth="8" desc="">
<field name="FIFO0" from="5" to="5" access="RW" resetVal="" desc="FIFO0 clear">
<value name="ENABLED" value="1" desc="Enable counter" />
<value name="DISABLED" value="0" desc="Disable counter" />
</field>
</register>
</block>
+ <block name="cydff_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+ <block name="cy_constant_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+ <block name="Clock_2" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+ <block name="CFG_EEPROM" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="SCSI_Out" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="SCSI_In" BASE="0x0" SIZE="0x0" desc="" visible="true" />
- <block name="CFG_EEPROM" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+ <block name="SD_MOSI" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="SD_SCK" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="SD_CS" BASE="0x0" SIZE="0x0" desc="" visible="true" />
- <block name="OddParityGen_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+ <block name="SD_Data_Clk" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="SCSI_Out_DBx" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="SCSI_In_DBx" BASE="0x0" SIZE="0x0" desc="" visible="true" />
- <block name="SD_Data_Clk" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+ <block name="OddParityGen_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="SCSI_CTL_PHASE" BASE="0x0" SIZE="0x0" desc="" visible="true">
- <register name="SCSI_CTL_PHASE_CONTROL_REG" address="0x4000647C" bitWidth="8" desc="" />
+ <register name="SCSI_CTL_PHASE_CONTROL_REG" address="0x40006471" bitWidth="8" desc="" />
</block>
<block name="SD_CD" BASE="0x0" SIZE="0x0" desc="" visible="true" />
- <block name="SD_MOSI" BASE="0x0" SIZE="0x0" desc="" visible="true" />
- <block name="SD_MISO" BASE="0x0" SIZE="0x0" desc="" visible="true" />
- <block name="SDCard" BASE="0x0" SIZE="0x0" desc="" visible="true">
- <block name="VirtualMux_3" BASE="0x0" SIZE="0x0" desc="" visible="true" />
- <block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
- <block name="VirtualMux_2" BASE="0x0" SIZE="0x0" desc="" visible="true" />
- <block name="VirtualMux_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
- <block name="BSPIM" BASE="0x0" SIZE="0x0" desc="" visible="true" />
- </block>
+ <block name="SCSI_CLK" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+ <block name="Bootloadable_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="USBFS" BASE="0x0" SIZE="0x0" desc="USBFS" visible="true">
<block name="ZeroTerminal_5" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="VirtualMux_6" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<register name="USBFS_EP_TYPE" address="0x4000608F" bitWidth="8" desc="Endpoint Type (IN/OUT) Indication" />
<register name="USBFS_USB_CLK_EN" address="0x4000609D" bitWidth="8" desc="USB Block Clock Enable Register" />
</block>
+ <block name="SD_MISO" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+ <block name="SCSI_Out_Ctl" BASE="0x0" SIZE="0x0" desc="" visible="true">
+ <register name="SCSI_Out_Ctl_CONTROL_REG" address="0x40006470" bitWidth="8" desc="" />
+ </block>
+ <block name="SCSI_Out_Bits" BASE="0x0" SIZE="0x0" desc="" visible="true">
+ <register name="SCSI_Out_Bits_CONTROL_REG" address="0x40006478" bitWidth="8" desc="" />
+ </block>
<block name="SCSI_Out_Mux" BASE="0x0" SIZE="0x0" desc="" visible="true" />
- <block name="Bootloadable_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
- <block name="LED1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
- <block name="not_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
- <block name="SCSI_CLK" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+ <block name="SCSI_RST_ISR" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="SCSI_Noise" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+ <block name="not_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+ <block name="SDCard" BASE="0x0" SIZE="0x0" desc="" visible="true">
+ <block name="VirtualMux_3" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+ <block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+ <block name="VirtualMux_2" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+ <block name="VirtualMux_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+ <block name="BSPIM" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+ </block>
+ <block name="LED1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="scsiTarget" BASE="0x0" SIZE="0x0" desc="" visible="true" />
- <block name="SCSI_RST_ISR" BASE="0x0" SIZE="0x0" desc="" visible="true" />
</blockRegMap>
\ No newline at end of file
</CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8>
<filters />
</CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0>
+<CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFolder" version="2">
+<CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtBaseContainer" version="1">
+<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="SCSI_SEL_ISR" persistent="">
+<Hidden v="False" />
+</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>
+<CyGuid_0820c2e7-528d-4137-9a08-97257b946089 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItemList" version="2">
+<dependencies>
+<CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFileGenerated" version="1">
+<CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFile" version="3" xml_contents_version="1">
+<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="SCSI_SEL_ISR.c" persistent=".\Generated_Source\PSoC5\SCSI_SEL_ISR.c">
+<Hidden v="False" />
+</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>
+<build_action v="ARM_C_FILE" />
+<PropertyDeltas />
+</CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b>
+</CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d>
+<CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFileGenerated" version="1">
+<CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFile" version="3" xml_contents_version="1">
+<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="SCSI_SEL_ISR.h" persistent=".\Generated_Source\PSoC5\SCSI_SEL_ISR.h">
+<Hidden v="False" />
+</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>
+<build_action v="NONE" />
+<PropertyDeltas />
+</CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b>
+</CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d>
+</dependencies>
+</CyGuid_0820c2e7-528d-4137-9a08-97257b946089>
+</CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8>
+<filters />
+</CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0>
</dependencies>
</CyGuid_0820c2e7-528d-4137-9a08-97257b946089>
</CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8>
<addressUnitBits>8</addressUnitBits>
<width>32</width>
<peripherals>
- <peripheral>
- <name>SCSI_Out_Ctl</name>
- <description>No description available</description>
- <baseAddress>0x4000647E</baseAddress>
- <addressBlock>
- <offset>0</offset>
- <size>0x0</size>
- <usage>registers</usage>
- </addressBlock>
- <registers>
- <register>
- <name>SCSI_Out_Ctl_CONTROL_REG</name>
- <description>No description available</description>
- <addressOffset>0x0</addressOffset>
- <size>8</size>
- <access>read-write</access>
- <resetValue>0</resetValue>
- <resetMask>0</resetMask>
- </register>
- </registers>
- </peripheral>
- <peripheral>
- <name>SCSI_Out_Bits</name>
- <description>No description available</description>
- <baseAddress>0x4000647F</baseAddress>
- <addressBlock>
- <offset>0</offset>
- <size>0x0</size>
- <usage>registers</usage>
- </addressBlock>
- <registers>
- <register>
- <name>SCSI_Out_Bits_CONTROL_REG</name>
- <description>No description available</description>
- <addressOffset>0x0</addressOffset>
- <size>8</size>
- <access>read-write</access>
- <resetValue>0</resetValue>
- <resetMask>0</resetMask>
- </register>
- </registers>
- </peripheral>
<peripheral>
<name>Debug_Timer</name>
<description>No description available</description>
<peripheral>
<name>SCSI_Parity_Error</name>
<description>No description available</description>
- <baseAddress>0x40006463</baseAddress>
+ <baseAddress>0x40006464</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x0</size>
<peripheral>
<name>SCSI_Filtered</name>
<description>No description available</description>
- <baseAddress>0x40006464</baseAddress>
+ <baseAddress>0x40006461</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x0</size>
<peripheral>
<name>SCSI_CTL_PHASE</name>
<description>No description available</description>
- <baseAddress>0x4000647C</baseAddress>
+ <baseAddress>0x40006471</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x0</size>
</register>
</registers>
</peripheral>
+ <peripheral>
+ <name>SCSI_Out_Ctl</name>
+ <description>No description available</description>
+ <baseAddress>0x40006470</baseAddress>
+ <addressBlock>
+ <offset>0</offset>
+ <size>0x0</size>
+ <usage>registers</usage>
+ </addressBlock>
+ <registers>
+ <register>
+ <name>SCSI_Out_Ctl_CONTROL_REG</name>
+ <description>No description available</description>
+ <addressOffset>0x0</addressOffset>
+ <size>8</size>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0</resetMask>
+ </register>
+ </registers>
+ </peripheral>
+ <peripheral>
+ <name>SCSI_Out_Bits</name>
+ <description>No description available</description>
+ <baseAddress>0x40006478</baseAddress>
+ <addressBlock>
+ <offset>0</offset>
+ <size>0x0</size>
+ <usage>registers</usage>
+ </addressBlock>
+ <registers>
+ <register>
+ <name>SCSI_Out_Bits_CONTROL_REG</name>
+ <description>No description available</description>
+ <addressOffset>0x0</addressOffset>
+ <size>8</size>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0</resetMask>
+ </register>
+ </registers>
+ </peripheral>
</peripherals>
</device>
\ No newline at end of file
#include "ConfigUtil.hh"
#include <limits>
+#include <sstream>
+#include <stdexcept>
#include <string.h>
+#include <wx/xml/xml.h>
+
using namespace SCSI2SD;
return std::vector<uint8_t>(begin, begin + sizeof(config));
}
-/*
-wxXmlNode*
+std::string
ConfigUtil::toXML(const TargetConfig& config)
{
- wxXmlNode* target = new wxXmlNode(wxXML_ELEMENT_NODE, "SCSITarget");
+ std::stringstream s;
+
+ s <<
+ "<SCSITarget id=\"" <<
+ static_cast<int>(config.scsiId & CONFIG_TARGET_ID_BITS) << "\">\n" <<
+
+ " <enabled>" <<
+ (config.scsiId & CONFIG_TARGET_ENABLED ? "true" : "false") <<
+ "</enabled>\n" <<
+
+ " <unitAttention>" <<
+ (config.flags & CONFIG_ENABLE_UNIT_ATTENTION ? "true" : "false") <<
+ "</unitAttention>\n" <<
+
+ " <parity>" <<
+ (config.flags & CONFIG_ENABLE_PARITY ? "true" : "false") <<
+ "</parity>\n" <<
+
+ "\n" <<
+ " <!-- ********************************************************\n" <<
+ " Space separated list. Available options:\n" <<
+ " apple\t\tReturns Apple-specific mode pages\n" <<
+ " ********************************************************* -->\n" <<
+ " <quirks>" <<
+ (config.quirks & CONFIG_QUIRKS_APPLE ? "apple" : "") <<
+ "</quirks>\n" <<
+
+ "\n\n" <<
+ " <!-- ********************************************************\n" <<
+ " 0x0 Fixed hard drive.\n" <<
+ " 0x1 Removable drive.\n" <<
+ " 0x2 Optical drive (ie. CD drive).\n" <<
+ " 0x3 1.44MB Floppy Drive.\n" <<
+ " ********************************************************* -->\n" <<
+ " <deviceType>0x" <<
+ std::hex << static_cast<int>(config.deviceType) <<
+ "</deviceType>\n" <<
+
+ "\n\n" <<
+ " <!-- ********************************************************\n" <<
+ " Device type modifier is usually 0x00. Only change this if your\n" <<
+ " OS requires some special value.\n" <<
+ "\n" <<
+ " 0x4C Data General Micropolis disk\n" <<
+ " ********************************************************* -->\n" <<
+ " <deviceTypeModifier>0x" <<
+ std::hex << static_cast<int>(config.deviceTypeModifier) <<
+ "</deviceTypeModifier>\n" <<
+
+ "\n\n" <<
+ " <!-- ********************************************************\n" <<
+ " SD card offset, as a sector number (always 512 bytes).\n" <<
+ " ********************************************************* -->\n" <<
+ " <sdSectorStart>" << std::dec << config.sdSectorStart << "</sdSectorStart>\n" <<
+ "\n\n" <<
+ " <!-- ********************************************************\n" <<
+ " Drive geometry settings.\n" <<
+ " ********************************************************* -->\n" <<
+ "\n"
+ " <scsiSectors>" << std::dec << config.scsiSectors << "</scsiSectors>\n" <<
+ " <bytesPerSector>" << std::dec << config.bytesPerSector << "</bytesPerSector>\n" <<
+ " <sectorsPerTrack>" << std::dec << config.sectorsPerTrack<< "</sectorsPerTrack>\n" <<
+ " <headsPerCylinder>" << std::dec << config.headsPerCylinder << "</headsPerCylinder>\n" <<
+ "\n\n" <<
+ " <!-- ********************************************************\n" <<
+ " Drive identification information. The SCSI2SD doesn't\n" <<
+ " care what these are set to. Use these strings to trick a OS\n" <<
+ " thinking a specific hard drive model is attached.\n" <<
+ " ********************************************************* -->\n" <<
+ "\n"
+ " <!-- 8 character vendor string -->\n" <<
+ " <!-- For Apple HD SC Setup/Drive Setup, use ' SEAGATE' -->\n" <<
+ " <vendor>" << std::string(config.vendor, 8) << "</vendor>\n" <<
+ "\n" <<
+ " <!-- 16 character produce identifier -->\n" <<
+ " <!-- For Apple HD SC Setup/Drive Setup, use ' ST225N' -->\n" <<
+ " <prodId>" << std::string(config.prodId, 16) << "</prodId>\n" <<
+ "\n" <<
+ " <!-- 4 character product revision number -->\n" <<
+ " <!-- For Apple HD SC Setup/Drive Setup, use '1.0 ' -->\n" <<
+ " <revision>" << std::string(config.revision, 4) << "</revision>\n" <<
+ "\n" <<
+ " <!-- 16 character serial number -->\n" <<
+ " <serial>" << std::string(config.serial, 16) << "</serial>\n" <<
+ "</SCSITarget>\n";
+
+ return s.str();
+}
+
+static uint64_t parseInt(wxXmlNode* node, uint64_t limit)
+{
+ std::string str(node->GetNodeContent().mb_str());
+ if (str.empty())
+ {
+ throw std::runtime_error("Empty " + node->GetName());
+ }
+ std::stringstream s;
+ if (str.find("0x") == 0)
{
- std::stringstream s; s << scsiId & CONFIG_TARGET_ID_BITS;
- target.AddAttribute("id", s.str());
+ s << std::hex << str.substr(2);
}
+ else
{
- std::stringstream s; s << config.deviceType;
- new wxXmlNode(
- new wxXmlNode(target, wxXML_ELEMENT_NODE, "deviceType"),
- wxXML_TEXT_NODE, "", s.str());
+ s << str;
}
+ uint64_t result;
+ s >> result;
+ if (!s)
{
- std::stringstream s; s << "0x" << std::hex << config.deviceTypeModifier;
- new wxXmlNode(
- new wxXmlNode(target, wxXML_ELEMENT_NODE, "deviceTypeModifier"),
- wxXML_TEXT_NODE, "", s.str());
+ throw std::runtime_error("Invalid value for " + node->GetName());
}
- wxXmlNode* flags(new wxXmlNode(target, wxXML_ELEMENT_NODE, "flags"));
-
- new wxXmlNode(
- new wxXmlNode(flags, wxXML_ELEMENT_NODE, "enabled"),
- wxXML_TEXT_NODE,
- "",
- config.scsiId & CONFIG_TARGET_ENABLED ? "true" : "false");
-
- "<unitAttention>" <<
- (config.flags & CONFIG_ENABLE_UNIT_ATTENTION ? "true" : "false") <<
- "</unitAttention>\n" <<
- "<parity>" <<
- (config.flags & CONFIG_ENABLE_PARITY ? "true" : "false") <<
- "</parity>\n" <<
+ if (result > limit)
+ {
+ std::stringstream msg;
+ msg << "Invalid value for " << node->GetName() <<
+ " (max=" << limit << ")";
+ throw std::runtime_error(msg.str());
+ }
+ return result;
+}
- "<sdSectorStart>" << config.sdSectorStart << "</sdSectorStart>\n" <<
- "<scsiSectors>" << config.scsiSectors << "</scsiSectors>\n" <<
- "<bytesPerSector>" << config.bytesPerSector << "</bytesPerSector>\n" <<
- "<sectorsPerTrack>" << config.sectorsPerTrack<< "</sectorsPerTrack>\n" <<
- "<headsPerCylinder>" << config.headsPerCylinder << "</headsPerCylinder>\n" <<
+static TargetConfig
+parseTarget(wxXmlNode* node)
+{
+ int id;
+ {
+ std::stringstream s;
+ s << node->GetAttribute("id", "7");
+ s >> id;
+ if (!s) throw std::runtime_error("Could not parse SCSITarget id attr");
+ }
+ TargetConfig result = ConfigUtil::Default(id & 0x7);
- "<vendor>" << std::string(config.vendor, 8) << "</vendor>" <<
- "<prodId>" << std::string(config.prodId, 16) << "</prodId>" <<
- "<revision>" << std::string(config.revision, 4) << "</revision>" <<
- "<serial>" << std::string(config.serial, 16) << "</serial>" <<
+ wxXmlNode *child = node->GetChildren();
+ while (child)
+ {
+ if (child->GetName() == "enabled")
+ {
+ std::string s(child->GetNodeContent().mb_str());
+ if (s == "true")
+ {
+ result.scsiId |= CONFIG_TARGET_ENABLED;
+ }
+ else
+ {
+ result.scsiId = result.scsiId & ~CONFIG_TARGET_ENABLED;
+ }
+ }
+ if (child->GetName() == "unitAttention")
+ {
+ std::string s(child->GetNodeContent().mb_str());
+ if (s == "true")
+ {
+ result.flags |= CONFIG_ENABLE_UNIT_ATTENTION;
+ }
+ else
+ {
+ result.flags = result.flags & ~CONFIG_ENABLE_UNIT_ATTENTION;
+ }
+ }
+ if (child->GetName() == "parity")
+ {
+ std::string s(child->GetNodeContent().mb_str());
+ if (s == "true")
+ {
+ result.flags |= CONFIG_ENABLE_PARITY;
+ }
+ else
+ {
+ result.flags = result.flags & ~CONFIG_ENABLE_PARITY;
+ }
+ }
+ else if (child->GetName() == "quirks")
+ {
+ std::stringstream s(std::string(child->GetNodeContent().mb_str()));
+ std::string quirk;
+ while (s >> quirk)
+ {
+ if (quirk == "apple")
+ {
+ result.quirks |= CONFIG_QUIRKS_APPLE;
+ }
+ }
+ }
+ else if (child->GetName() == "deviceType")
+ {
+ result.deviceType = parseInt(child, 0xFF);
+ }
+ else if (child->GetName() == "deviceTypeModifier")
+ {
+ result.deviceTypeModifier = parseInt(child, 0xFF);
+ }
+ else if (child->GetName() == "sdSectorStart")
+ {
+ result.sdSectorStart = parseInt(child, 0xFFFFFFFF);
+ }
+ else if (child->GetName() == "scsiSectors")
+ {
+ result.scsiSectors = parseInt(child, 0xFFFFFFFF);
+ }
+ else if (child->GetName() == "bytesPerSector")
+ {
+ result.bytesPerSector = parseInt(child, 8192);
+ }
+ else if (child->GetName() == "sectorsPerTrack")
+ {
+ result.sectorsPerTrack = parseInt(child, 255);
+ }
+ else if (child->GetName() == "headsPerCylinder")
+ {
+ result.headsPerCylinder = parseInt(child, 255);
+ }
+ else if (child->GetName() == "vendor")
+ {
+ std::string s(child->GetNodeContent().mb_str());
+ s = s.substr(0, sizeof(result.vendor));
+ memset(result.vendor, ' ', sizeof(result.vendor));
+ memcpy(result.vendor, s.c_str(), s.size());
+ }
+ else if (child->GetName() == "prodId")
+ {
+ std::string s(child->GetNodeContent().mb_str());
+ s = s.substr(0, sizeof(result.prodId));
+ memset(result.prodId, ' ', sizeof(result.prodId));
+ memcpy(result.prodId, s.c_str(), s.size());
+ }
+ else if (child->GetName() == "revision")
+ {
+ std::string s(child->GetNodeContent().mb_str());
+ s = s.substr(0, sizeof(result.revision));
+ memset(result.revision, ' ', sizeof(result.revision));
+ memcpy(result.revision, s.c_str(), s.size());
+ }
+ else if (child->GetName() == "serial")
+ {
+ std::string s(child->GetNodeContent().mb_str());
+ s = s.substr(0, sizeof(result.serial));
+ memset(result.serial, ' ', sizeof(result.serial));
+ memcpy(result.serial, s.c_str(), s.size());
+ }
- "</SCSITarget>";
+ child = child->GetNext();
+ }
+ return result;
}
-void
-ConfigUtil::deserialise(const std::string& in)
+std::vector<TargetConfig>
+ConfigUtil::fromXML(const std::string& filename)
{
+ wxXmlDocument doc;
+ if (!doc.Load(filename))
+ {
+ throw std::runtime_error("Could not load XML file");
+ }
+
+ // start processing the XML file
+ if (doc.GetRoot()->GetName() != "SCSI2SD")
+ {
+ throw std::runtime_error("Invalid root node, expected <SCSI2SD>");
+ }
+ std::vector<TargetConfig> result;
+ wxXmlNode *child = doc.GetRoot()->GetChildren();
+ while (child)
+ {
+ if (child->GetName() == "SCSITarget")
+ {
+ result.push_back(parseTarget(child));
+ }
+ child = child->GetNext();
+ }
+ return result;
}
-*/
+
#include "scsi2sd.h"
#include <cstddef>
+#include <string>
#include <vector>
namespace SCSI2SD
static TargetConfig fromBytes(const uint8_t* data);
static std::vector<uint8_t> toBytes(const TargetConfig& config);
+
+ static std::string toXML(const TargetConfig& config);
+ static std::vector<TargetConfig> fromXML(const std::string& filename);
};
}
CPPFLAGS = -I cybootloaderutils -I hidapi/hidapi -I ../include -Ilibzipper-1.0.4 -I$(BUILD)/zlib
CFLAGS += -Wall -Wno-pointer-sign -O2 -g
CXXFLAGS += -Wall -O2 -g -std=c++0x
-LDFLAGS += -L$(BUILD)/libzipper/.libs -lzipper -L$(BUILD)/zlib -lz
+LDFLAGS += -L$(BUILD)/libzipper/.libs -lzipper -L$(BUILD)/zlib -lz -lexpat
LIBZIPPER_CONFIG = --disable-shared LDFLAGS="-L../zlib" CPPFLAGS="-I../zlib"
void CtrlGetFixedString(wxTextEntry* ctrl, char* dest, size_t len)
{
memset(dest, ' ', len);
- strncpy(dest, ctrl->GetValue().ToAscii(), len);
+ std::string str(ctrl->GetValue().ToAscii());
+ // Don't use strncpy - we need to avoid NULL's
+ memcpy(dest, str.c_str(), std::min(len, str.size()));
}
bool CtrlIsAscii(wxTextEntry* ctrl)
#include <wx/notebook.h>
#include <wx/progdlg.h>
#include <wx/utils.h>
+#include <wx/wfstream.h>
#include <wx/windowptr.h>
#include <wx/thread.h>
+#include <wx/txtstrm.h>
#include <zipper.hh>
myLastPollTime(0)
{
wxMenu *menuFile = new wxMenu();
+ menuFile->Append(
+ ID_SaveFile,
+ "&Save to file...",
+ "Save settings to local file.");
+ menuFile->Append(
+ ID_OpenFile,
+ "&Open file...",
+ "Load settings from local file.");
+ menuFile->AppendSeparator();
menuFile->Append(
ID_ConfigDefaults,
"Load &Defaults",
ID_BtnSave,
ID_LogWindow,
ID_SCSILog,
- ID_SelfTest
+ ID_SelfTest,
+ ID_SaveFile,
+ ID_OpenFile
};
void OnID_ConfigDefaults(wxCommandEvent& event)
}
}
+ void OnID_SaveFile(wxCommandEvent& event)
+ {
+ TimerLock lock(myTimer);
+
+
+
+ wxFileDialog dlg(
+ this,
+ "Save config settings",
+ "",
+ "",
+ "XML files (*.xml)|*.xml",
+ wxFD_SAVE | wxFD_OVERWRITE_PROMPT);
+ if (dlg.ShowModal() == wxID_CANCEL) return;
+
+ wxFileOutputStream file(dlg.GetPath());
+ if (!file.IsOk())
+ {
+ wxLogError("Cannot save settings to file '%s'.", dlg.GetPath());
+ return;
+ }
+
+ wxTextOutputStream s(file);
+
+ s << "<SCSI2SD>\n";
+
+ for (size_t i = 0; i < myTargets.size(); ++i)
+ {
+ s << ConfigUtil::toXML(myTargets[i]->getConfig());
+ }
+
+ s << "</SCSI2SD>\n";
+ }
+
+ void OnID_OpenFile(wxCommandEvent& event)
+ {
+ TimerLock lock(myTimer);
+
+ wxFileDialog dlg(
+ this,
+ "Load config settings",
+ "",
+ "",
+ "XML files (*.xml)|*.xml",
+ wxFD_OPEN | wxFD_FILE_MUST_EXIST);
+ if (dlg.ShowModal() == wxID_CANCEL) return;
+
+ try
+ {
+ std::vector<TargetConfig> configs(
+ ConfigUtil::fromXML(dlg.GetPath()));
+
+ size_t i;
+ for (i = 0; i < configs.size() && i < myTargets.size(); ++i)
+ {
+ myTargets[i]->setConfig(configs[i]);
+ }
+
+ for (; i < myTargets.size(); ++i)
+ {
+ myTargets[i]->setConfig(ConfigUtil::Default(i));
+ }
+ }
+ catch (std::exception& e)
+ {
+ wxLogError(
+ "Cannot load settings from file '%s'.\n%s",
+ dlg.GetPath(),
+ e.what());
+
+ wxMessageBox(
+ e.what(),
+ "Load error",
+ wxOK | wxICON_ERROR);
+ }
+ }
+
void OnID_Firmware(wxCommandEvent& event)
{
TimerLock lock(myTimer);
EVT_MENU(AppFrame::ID_ConfigDefaults, AppFrame::OnID_ConfigDefaults)
EVT_MENU(AppFrame::ID_Firmware, AppFrame::OnID_Firmware)
EVT_MENU(AppFrame::ID_LogWindow, AppFrame::OnID_LogWindow)
+ EVT_MENU(AppFrame::ID_SaveFile, AppFrame::OnID_SaveFile)
+ EVT_MENU(AppFrame::ID_OpenFile, AppFrame::OnID_OpenFile)
EVT_MENU(wxID_EXIT, AppFrame::OnExitEvt)
EVT_MENU(wxID_ABOUT, AppFrame::OnAbout)
projects / SCSI2SD.git / commitdiff